PIC24FJ128GA010 FAMILY
64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers
High-Performance CPU:
Analog Features:
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator with 4x PLL Option and
Multiple Divide Options
• 17-Bit x 17-Bit Single-Cycle Hardware
Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16 x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture:
- 76 base instructions
- Flexible addressing modes
• Two Address Generation Units for Separate Read
and Write Addressing of Data Memory
• 10-Bit, Up to 16-Channel Analog-to-Digital Converter
- 500 ksps conversion rate
- Conversion available during Sleep and Idle
• Dual Analog Comparators with Programmable
Input/Output Configuration
Peripheral Features:
• Two 3-Wire/4-Wire SPI modules, Supporting
4 Frame modes with 8-Level FIFO Buffer
• Two I2C™ modules Support Multi-Master/Slave
mode and 7-Bit/10-Bit Addressing
• Two UART modules:
- Supports RS-232, RS-485 and LIN/J2602
- On-chip hardware encoder/decoder for IrDA®
- Auto-wake-up on Start bit
- Auto-Baud Detect
- 4-level FIFO buffer
• Parallel Master Slave Port (PMP/PSP):
- Supports 8-bit or 16-bit data
- Supports 16 address lines
• Hardware Real-Time Clock/Calendar (RTCC):
- Provides clock, calendar and alarm functions
• Programmable Cyclic Redundancy Check (CRC)
- User-programmable polynomial
- 8/16-level FIFO buffer
• Five 16-Bit Timers/Counters with Programmable
Prescaler
• Five 16-Bit Capture Inputs
• Five 16-Bit Compare/PWM Outputs
• High-Current Sink/Source (18 mA/18 mA) on All
I/O Pins
• Configurable, Open-Drain Output on Digital I/O Pins
• Up to 5 External Interrupt Sources
• 5.5V Tolerant Input (digital pins only)
Special Microcontroller Features:
UART
SPI
I2C™
10-Bit
A/D (ch)
Comparators
PMP/PSP
JTAG
5
2
2
2
16
2
Y
Y
2
2
2
16
2
Y
Y
5
2
2
2
16
2
Y
Y
5
5
2
2
2
16
2
Y
Y
5
5
2
2
2
16
2
Y
Y
5
5
5
2
2
2
16
2
Y
Y
8K
5
5
5
2
2
2
16
2
Y
Y
8K
5
5
5
2
2
2
16
2
Y
Y
8K
5
5
5
2
2
2
16
2
Y
Y
Pins
Program
Memory
(Bytes)
SRAM
(Bytes)
Timers
16-Bit
Capture
Input
Compare/
PWM Output
• Operating Voltage Range of 2.0V to 3.6V
• Flash Program Memory:
- 1000 erase/write cycles
- 20-year data retention minimum
• Self-Reprogrammable under Software Control
• Selectable Power Management modes:
- Sleep, Idle and Alternate Clock modes
• Fail-Safe Clock Monitor Operation:
- Detects clock failure and switches to on-chip,
low-power RC oscillator
• On-Chip 2.5V Regulator
• JTAG Boundary Scan and Programming Support
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Flexible Watchdog Timer (WDT) with On-Chip,
Low-Power RC Oscillator for Reliable Operation
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Emulation (ICE) via 2 Pins
PIC24FJ64GA006
64
64K
8K
5
5
PIC24FJ96GA006
64
96K
8K
5
5
5
PIC24FJ128GA006
64
128K
8K
5
5
PIC24FJ64GA008
80
64K
8K
5
PIC24FJ96GA008
80
96K
8K
5
PIC24FJ128GA008
80
128K
8K
PIC24FJ64GA010
100
64K
PIC24FJ96GA010
100
96K
PIC24FJ128GA010
100
128K
Device
2005-2012 Microchip Technology Inc.
DS39747F-page 1
PIC24FJ128GA010 FAMILY
Pin Diagrams
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
RF1
RF0
ENVREG
VCAP/VDDCORE
CN16/RD7
CN15/RD6
PMRD/CN14/RD5
PMWR/OC5/IC5/CN13/RD4
PMBE/OC4/RD3
OC3/RD2
OC2/RD1
64-Pin TQFP/QFN(1)
PMD5/RE5
PMD6/RE6
PMD7/RE7
PMA5/SCK2/CN8/RG6
PMA4/SDI2/CN9/RG7
PMA3/SDO2/CN10/RG8
MCLR
PMA2/SS2/CN11/RG9
VSS
VDD
C1IN+/AN5/CN7/RB5
C1IN-/AN4/CN6/RB4
C2IN+/AN3/CN5/RB3
C2IN-/AN2/SS1/CN4/RB2
PGC1/EMUC1/VREF-/AN1/CN3/RB1
2
3
4
5
6
7
8
9
10
11
12
PIC24FJXXGA006
PIC24FJXXXGA006
13
14
15
16
48
SOSCO/T1CK/CN0/RC14
47
46
45
44
43
42
41
40
SOSCI/CN1/RC13
OC1/RD0
IC4/PMCS1/INT4/RD11
IC3/PMCS2/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/RTCC/INT1/RD8
Vss
OSC2/CLKO/RC15
39
38
37
OSC1/CLKI/RC12
36
35
34
33
SDA1/RG3
U1RTS/BCLK1/SCK1/INT0/RF6
VDD
SCL1/RG2
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGC2/EMUC2/AN6/OCFA/RB6
PGD2/EMUD2/AN7/RB7
AVDD
AVSS
U2CTS/C1OUT/AN8/RB8
PMA7/C2OUT/AN9/RB9
TMS/PMA13/CVREF/AN10/RB10
TDO/PMA12/AN11/RB11
VSS
VDD
TCK/PMA11/AN12/RB12
TDI/PMA10/AN13/RB13
PMA1/U2RTS/BCLK2/AN14/RB14
PMA0/AN15/OCFB/CN12/RB15
PMA9/U2RX/SDA2/CN17/RF4
PMA8/U2TX/SCL2/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PGD1/EMUD1/PMA6/VREF+/AN0/CN2/RB0
1
Legend:
Shaded pins indicate pins that are tolerant to up to +5.5 VDC.
Note 1:
Bottom pad of QFN package must be connected to VSS.
DS39747F-page 2
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
Pin Diagrams (Continued)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
RG0
RG1
RF1
RF0
ENVREG
VCAP/VDDCORE
CN16/RD7
CN15/RD6
PMRD/CN14/RD5
PMWR/OC5/CN13/RD4
CN19/RD13
IC5/RD12
PMBE/OC4/RD3
OC3/RD2
OC2/RD1
80-Pin TQFP
PMD5/RE5
PMD6/RE6
PMD7/RE7
T2CK/RC1
T4CK/RC3
PMA5/SCK2/CN8/RG6
PMA4/SDI2/CN9/RG7
PMA3/SDO2/CN10/RG8
MCLR
PMA2/SS2/CN11/RG9
VSS
VDD
TMS/INT1/RE8
TDO/INT2/RE9
2
3
4
5
6
7
8
9
10
11
12
PIC24FJXXGA008
PIC24FJXXXGA008
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/RD0
IC4/PMCS1/RD11
IC3/PMCS2/RD10
IC2/RD9
IC1/RTCC/RD8
SDA2/INT4/RA15
SCL2/INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGC2/EMUC2/AN6/OCFA/RB6
PGD2/EMUD2/AN7/RB7
PMA7/VREF-/RA9
PMA6/VREF+/RA10
AVDD
AVSS
U2CTS/C1OUT/AN8/RB8
C2OUT/AN9/RB9
PMA13/CVREF/AN10/RB10
PMA12/AN11/RB11
VSS
VDD
TCK/PMA11/AN12/RB12
TDI/PMA10/AN13/RB13
PMA1/U2RTS/BCLK2/AN14/RB14
PMA0/AN15/OCFB/CN12/RB15
U1CTS/CN20/RD14
U1RTS/BCLK1/CN21/RD15
PMA9/U2RX/CN17/RF4
PMA8/U2TX/CN18/RF5
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
C1IN+/AN5/CN7/RB5
C1IN-/AN4/CN6/RB4
C2IN+/AN3/CN5/RB3
C2IN-/AN2/SS1/CN4/RB2
PGC1/EMUC1/AN1/CN3/RB1
PGD1/EMUD1/AN0/CN2/RB0
1
Legend: Shaded pins indicate pins that are tolerant to up to +5.5 VDC.
2005-2012 Microchip Technology Inc.
DS39747F-page 3
PIC24FJ128GA010 FAMILY
Pin Diagrams (Continued))
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PMD4/RE4
PMD3/RE3
PMD2/RE2
RG13
RG12
RG14
PMD1/RE1
PMD0/RE0
RA7
RA6
RG0
RG1
RF1
RF0
ENVREG
VCAP/VDDCORE
CN16/RD7
CN15/RD6
PMRD/CN14/RD5
PMWR/OC5/CN13/RD4
CN19/RD13
IC5/RD12
PMBE/OC4/RD3
OC3/RD2
OC2/RD1
100-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIC24FJXXGA010
PIC24FJXXXGA010
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/RD0
IC4/PMCS1/RD11
IC3/PMCS2/RD10
IC2/RD9
IC1/RTCC/RD8
INT4/RA15
INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGC2/EMUC2/AN6/OCFA/RB6
PGD2/EMUD2/AN7/RB7
PMA7/VREF-/RA9
PMA6/VREF+/RA10
AVDD
AVSS
C1OUT/AN8/RB8
C2OUT/AN9/RB9
PMA13/CVREF/AN10/RB10
PMA12/AN11/RB11
VSS
VDD
TCK/RA1
U2RTS/BCLK2/RF13
U2CTS/RF12
PMA11/AN12/RB12
PMA10/AN13/RB13
PMA1/AN14/RB14
PMA0/AN15/OCFB/CN12/RB15
VSS
VDD
U1CTS/CN20/RD14
U1RTS/BCLK1/CN21/RD15
PMA9/U2RX/CN17/RF4
PMA8/U2TX/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RG15
VDD
PMD5/RE5
PMD6/RE6
PMD7/RE7
T2CK/RC1
T3CK/RC2
T4CK/RC3
T5CK/RC4
PMA5/SCK2/CN8/RG6
PMA4/SDI2/CN9/RG7
PMA3/SDO2/CN10/RG8
MCLR
PMA2/SS2/CN11/RG9
VSS
VDD
TMS/RA0
INT1/RE8
INT2/RE9
C1IN+/AN5/CN7/RB5
C1IN-/AN4/CN6/RB4
C2IN+/AN3/CN5/RB3
C2IN-/AN2/SS1/CN4/RB2
PGC1/EMUC1/AN1/CN3/RB1
PGD1/EMUD1/AN0/CN2/RB0
Legend: Shaded pins indicate pins that are tolerant to up to +5.5 VDC.
DS39747F-page 4
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 19
3.0 CPU............................................................................................................................................................................................ 25
4.0 Memory Organization ................................................................................................................................................................. 31
5.0 Flash Program Memory.............................................................................................................................................................. 51
6.0 Resets ........................................................................................................................................................................................ 57
7.0 Interrupt Controller ..................................................................................................................................................................... 63
8.0 Oscillator Configuration .............................................................................................................................................................. 97
9.0 Power-Saving Features............................................................................................................................................................ 105
10.0 I/O Ports ................................................................................................................................................................................... 107
11.0 Timer1 ...................................................................................................................................................................................... 111
12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 113
13.0 Input Capture............................................................................................................................................................................ 119
14.0 Output Compare....................................................................................................................................................................... 121
15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 127
16.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 137
17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 145
18.0 Parallel Master Port (PMP)....................................................................................................................................................... 153
19.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 163
20.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 175
21.0 10-bit High-Speed A/D Converter............................................................................................................................................. 179
22.0 Comparator Module.................................................................................................................................................................. 189
23.0 Comparator Voltage Reference................................................................................................................................................ 193
24.0 Special Features ...................................................................................................................................................................... 195
25.0 Instruction Set Summary .......................................................................................................................................................... 205
26.0 Development Support............................................................................................................................................................... 213
27.0 Electrical Characteristics .......................................................................................................................................................... 217
28.0 Packaging Information.............................................................................................................................................................. 231
Appendix A: Revision History............................................................................................................................................................. 245
Index ................................................................................................................................................................................................. 247
The Microchip Web Site ..................................................................................................................................................................... 251
Customer Change Notification Service .............................................................................................................................................. 251
Customer Support .............................................................................................................................................................................. 251
Reader Response .............................................................................................................................................................................. 252
Product Identification System ............................................................................................................................................................ 253
2005-2012 Microchip Technology Inc.
DS39747F-page 5
PIC24FJ128GA010 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS39747F-page 6
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
•
•
•
•
•
•
•
•
•
PIC24FJ64GA006
PIC24FJ64GA008
PIC24FJ64GA010
PIC24FJ96GA006
PIC24FJ96GA008
PIC24FJ96GA010
PIC24FJ128GA006
PIC24FJ128GA008
PIC24FJ128GA010
1.1.2
POWER-SAVING TECHNOLOGY
All of the devices in the PIC24FJ128GA010 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:
This family introduces a new line of Microchip devices:
a 16-bit microcontroller family with a broad peripheral
feature set and enhanced computational performance.
The PIC24FJ128GA010 family offers a new migration
option for those high-performance applications which
may be outgrowing their 8-bit platforms, but don’t
require the numerical processing power of a digital
signal processor.
• On-the-Fly Clock Switching: The device clock
can be changed under software control to the
Timer1 source or the internal low-power RC
oscillator during operation, allowing the user to
incorporate power-saving ideas into their software
designs.
• Doze Mode Operation: When timing-sensitive
applications, such as serial communications,
require the uninterrupted operation of peripherals,
the CPU clock speed can be selectively reduced,
allowing incremental power savings without
missing a beat.
• Instruction-Based Power-Saving Modes: The
microcontroller can suspend all operations, or
selectively shut down its core while leaving its
peripherals active, with a single instruction in
software.
1.1
1.1.3
1.1.1
Core Features
16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® digital signal controllers. The PIC24F CPU core
offers a wide range of enhancements, such as:
• 16-bit data and 24-bit address paths, with the
ability to move information between data and
memory spaces
• Linear addressing of up to 8 Mbytes (program
space) and 64 Kbytes (data)
• A 16-element working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32 by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages such as ‘C’
• Operational performance up to 16 MIPS
OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC24FJ128GA010 family offer
five different oscillator options, allowing users a range
of choices in developing application hardware. These
include:
• Two Crystal modes using crystals or ceramic
resonators.
• Two External Clock modes offering the option of a
divide-by-2 clock output.
• A Fast Internal Oscillator (FRC) with a nominal
8 MHz output, which can also be divided under
software control to provide clock speeds as low as
31 kHz.
• A Phase Lock Loop (PLL) frequency multiplier,
available to the external oscillator modes and the
FRC oscillator, which allows clock speeds of up to
32 MHz.
• A separate internal RC oscillator (LPRC) with a
fixed, 31 kHz output, which provides a low-power
option for timing-insensitive applications.
The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor. This
option constantly monitors the main clock source
against a reference signal provided by the internal
oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
2005-2012 Microchip Technology Inc.
DS39747F-page 7
PIC24FJ128GA010 FAMILY
1.1.4
EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between devices with
the same pin count, or even jumping from 64-pin to
80-pin to 100-pin devices.
The PIC24F family is pin-compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex, yet still selecting
a Microchip device.
1.2
Other Special Features
• Communications: The PIC24FJ128GA010
family incorporates a range of serial communication peripherals to handle a range of application
requirements. All devices are equipped with two
independent UARTs with built-in IrDA
encoder/decoders. There are also two independent SPI modules, and two independent I2C
modules that support both Master and Slave
modes of operation.
• Parallel Master/Enhanced Parallel Slave Port:
One of the general purpose I/O ports can be
reconfigured for enhanced parallel data communications. In this mode, the port can be configured
for both master and slave operations, and
supports 8-bit and 16-bit data transfers with up to
16 external address lines in Master modes.
• Real-Time Clock/Calendar: This module
implements a full-featured clock and calendar with
alarm functions in hardware, freeing up timer
resources and program memory space for use of
the core application.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, as
well as faster sampling speeds.
DS39747F-page 8
1.3
Details on Individual Family
Members
Devices in the PIC24FJ128GA010 family are available
in 64-pin, 80-pin and 100-pin packages. The general
block diagram for all devices is shown in Figure 1-1.
The devices are differentiated from each other in two
ways:
1.
2.
Flash program memory (64 Kbytes for
PIC24FJ64GA devices, 96 Kbytes for
PIC24FJ96GA devices and 128 Kbytes for
PIC24FJ128GA devices).
Available I/O pins and ports (53 pins on 6 ports for
64-pin devices, 69 pins on 7 ports for 80-pin
devices and 84 pins on 7 ports for 100-pin
devices). Note also that, since interrupt-on-change
inputs are available on every I/O pin for this family
of devices, the number of CN inputs also differs
between package sizes.
All other features for devices in this family are identical.
These are summarized in Table 1-1.
A list of the pin features available on the
PIC24FJ128GA010 family devices, sorted by function,
is shown in Table 1-2. Note that this table shows the pin
location of individual peripheral features and not how
they are multiplexed on the same pin. This information
is provided in the pinout diagrams in the beginning of
the data sheet. Multiplexed features are sorted by the
priority given to a feature, with the highest priority
peripheral being listed first.
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
Operating Frequency
PIC24FJ128GA010
PIC24FJ96GA010
PIC24FJ64GA010
PIC24FJ128GA008
DC – 32 MHz
Program Memory (Bytes)
Program Memory (Instructions)
PIC24FJ96GA008
PIC24FJ64GA008
PIC24FJ128GA006
Features
PIC24FJ96GA006
DEVICE FEATURES FOR THE PIC24FJ128GA010 FAMILY
PIC24FJ64GA006
TABLE 1-1:
64K
96K
128K
64K
96K
128K
64K
96K
128K
22,016
32,768
44,032
22,016
32,768
44,032
22,016
32,768
44,032
Data Memory (Bytes)
8192
Interrupt Sources
(Soft Vectors/NMI Traps)
43
(39/4)
I/O Ports
Total I/O Pins
Ports B, C, D, E, F, G
Ports A, B, C, D, E, F, G
Ports A, B, C, D, E, F, G
53
69
84
Timers:
Total Number (16-bit)
5
32-Bit (from paired 16-bit timers)
2
Input Capture Channels
5
Output Compare/PWM
Channels
5
Input Change Notification
Interrupt
19
22
Serial Communications:
UART
2
SPI (3-wire/4-wire)
2
I2C™
2
Parallel Communications
(PMP/PSP)
Yes
JTAG Boundary Scan
Yes
10-Bit Analog-to-Digital Module
(input channels)
16
Analog Comparators
2
Resets (and Delays)
POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, Configuration Word
Mismatch, REPEAT Instruction, Hardware Traps (PWRT, OST, PLL Lock)
Instruction Set
Packages
2005-2012 Microchip Technology Inc.
76 Base Instructions, Multiple Addressing Mode Variations
64-Pin TQFP/QFN
80-Pin TQFP
100-Pin TQFP
DS39747F-page 9
PIC24FJ128GA010 FAMILY
FIGURE 1-1:
PIC24FJ128GA010 FAMILY GENERAL BLOCK DIAGRAM
Data Bus
Interrupt
Controller
PORTA(1)
RA0:RA7,
RA9:RA10,
RA14:15
16
16
8
16
Data Latch
PSV & Table
Data Access
Control Block
Data RAM
PCH
PCL
Program Counter
Repeat
Stack
Control
Control
Logic
Logic
23
PORTB(1)
Address
Latch
RB0:RB15
16
23
16
Read AGU
Write AGU
Address Latch
16
PORTC
RC1:RC4,
RC12:RC15
Program Memory
Data Latch
EA MUX
24
Inst Latch
Literal Data
Address Bus
16
PORTD(1)
16
RD0:RD15
Inst Register
Instruction
Decode &
Control
RE0:RE9
Control Signals
OSC2/CLKO
OSC1/CLKI
Timing
Generation
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
ENVREG
Voltage
Regulator
VDDCORE/VCAP
Timer1
PORTE(1)
Divide
Support
16 x 16
W Reg Array
17x17
Multiplier
Power-up
Timer
PORTF(1)
RF0:RF8,
RF12:RF13
Oscillator
Start-up Timer
16-Bit ALU
Power-on
Reset
16
Watchdog
Timer
PORTG(1)
Brown-out
Reset(2)
RG0:RG9,
RG12:RG15
VDD, VSS
Timer2/3
MCLR
Timer4/5
RTCC
10-Bit
A/D
Comparators
PMP/PSP
IC1-5
Note
PWM/
OC1-5
CN1-22(1)
SPI1/2
I2C1/2
UART1/2
1:
Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions.
2:
BOR functionality is provided when the on-board voltage regulator is enabled.
DS39747F-page 10
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 1-2:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS
Pin Number
Function
I/O
100-Pin
Input
Buffer
64-Pin
80-Pin
AN0
16
20
25
I
ANA
AN1
15
19
24
I
ANA
AN2
14
18
23
I
ANA
AN3
13
17
22
I
ANA
AN4
12
16
21
I
ANA
AN5
11
15
20
I
ANA
AN6
17
21
26
I
ANA
AN7
18
22
27
I
ANA
AN8
21
27
32
I
ANA
AN9
22
28
33
I
ANA
Description
A/D Analog Inputs.
AN10
23
29
34
I
ANA
AN11
24
30
35
I
ANA
AN12
27
33
41
I
ANA
AN13
28
34
42
I
ANA
AN14
29
35
43
I
ANA
AN15
30
36
44
I
ANA
AVDD
19
25
30
P
—
Positive Supply for Analog Modules.
AVSS
20
26
31
P
—
Ground Reference for Analog Modules.
BCLK1
35
38
48
O
—
UART1 IrDA® Baud Clock.
BCLK2
29
35
39
O
—
UART2 IrDA® Baud Clock.
C1IN-
12
16
21
I
ANA
Comparator 1 Negative Input.
C1IN+
11
15
20
I
ANA
Comparator 1 Positive Input.
C1OUT
21
27
32
O
—
C2IN-
14
18
23
I
ANA
Comparator 2 Negative Input.
Comparator 1 Output.
C2IN+
13
17
22
I
ANA
Comparator 2 Positive Input.
C2OUT
22
28
33
O
—
Comparator 2 Output.
CLKI
39
49
63
I
ANA
CLKO
40
50
64
O
—
System Clock Output.
CN0
48
60
74
I
ST
Interrupt-on-Change Inputs.
CN1
47
59
73
I
ST
CN2
16
20
25
I
ST
CN3
15
19
24
I
ST
CN4
14
18
23
I
ST
CN5
13
17
22
I
ST
CN6
12
16
21
I
ST
CN7
11
15
20
I
ST
CN8
4
6
10
I
ST
CN9
5
7
11
I
ST
ST
CN10
6
8
12
I
CN11
8
10
14
I
ST
CN12
30
36
44
I
ST
CN13
52
66
81
I
ST
CN14
53
67
82
I
ST
CN15
54
68
83
I
ST
CN16
55
69
84
I
ST
CN17
31
39
49
I
ST
Legend:
Main Clock Input Connection.
TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer
2005-2012 Microchip Technology Inc.
DS39747F-page 11
PIC24FJ128GA010 FAMILY
TABLE 1-2:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
I/O
Input
Buffer
50
I
ST
80
I
ST
47
I
ST
Function
64-Pin
80-Pin
100-Pin
CN18
32
40
CN19
—
65
CN20
—
37
Description
Interrupt-on-Change Inputs.
CN21
—
38
48
I
ST
CVREF
23
29
34
O
ANA
Comparator Voltage Reference Output.
EMUC1
15
19
24
I/O
ST
In-Circuit Emulator Clock Input/Output.
EMUD1
16
20
25
I/O
ST
In-Circuit Emulator Data Input/Output.
EMUC2
17
21
26
I/O
ST
In-Circuit Emulator Clock Input/Output.
EMUD2
18
22
27
I/O
ST
In-Circuit Emulator Data Input/Output.
ENVREG
57
71
86
I
ST
Enable for On-Chip Voltage Regulator.
IC1
42
54
68
I
ST
Input Capture Inputs.
IC2
43
55
69
I
ST
IC3
44
56
70
I
ST
IC4
45
57
71
I
ST
IC5
52
64
79
I
ST
INT0
35
45
55
I
ST
INT1
42
13
18
I
ST
INT2
43
14
19
I
ST
INT3
44
52
66
I
ST
INT4
45
53
67
I
ST
MCLR
7
9
13
I
ST
Master Clear (Device Reset) Input. This line is brought
low to cause a Reset.
OC1
46
58
72
O
—
Output Compare/PWM Outputs.
OC2
49
61
76
O
—
OC3
50
62
77
O
—
OC4
51
63
78
O
—
OC5
52
66
81
O
—
External Interrupt Inputs.
OCFA
17
21
26
I
ST
OCFB
30
36
44
I
ST
OSC1
39
49
63
I
ANA
Main Oscillator Input Connection.
OSC2
40
50
64
O
ANA
Main Oscillator Output Connection.
PGC1
15
19
24
I/O
ST
PGD1
16
20
25
I/O
ST
In-Circuit Debugger and ICSP Programming Data.
PGC2
17
21
26
I/O
ST
In-Circuit Debugger and ICSP™ Programming Clock.
PGD2
18
22
27
I/O
ST
In-Circuit Debugger and ICSP Programming Data.
Legend:
Output Compare Fault A Input.
Output Compare Fault B Input.
In-Circuit Debugger and ICSP™ Programming Clock.
TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer
DS39747F-page 12
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 1-2:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
I/O
Input
Buffer
44
I/O
ST/TTL
Parallel Master Port Address Bit 0 Input (Buffered Slave
modes) and Output (Master modes).
35
43
I/O
ST/TTL
Parallel Master Port Address Bit 1 Input (Buffered Slave
modes) and Output (Master modes).
8
10
14
O
—
6
8
12
O
—
PMA4
5
7
11
O
—
PMA5
4
6
10
O
—
PMA6
16
24
29
O
—
PMA7
22
23
28
O
—
PMA8
32
40
50
O
—
PMA9
31
39
49
O
—
PMA10
28
34
42
O
—
PMA11
27
33
41
O
—
PMA12
24
30
35
O
—
PMA13
23
29
34
O
—
Function
64-Pin
80-Pin
100-Pin
PMA0
30
36
PMA1
29
PMA2
PMA3
Description
Parallel Master Port Address (Demultiplexed Master
modes).
PMBE
51
63
78
O
—
PMCS1
45
57
71
I/O
ST/TTL
PMCS2
44
56
70
O
—
Parallel Master Port Chip Select 2 Strobe/Address bit 15.
PMD0
60
76
93
I/O
ST/TTL
PMD1
61
77
94
I/O
ST/TTL
Parallel Master Port Data (Demultiplexed Master mode)
or Address/Data (Multiplexed Master modes).
PMD2
62
78
98
I/O
ST/TTL
PMD3
63
79
99
I/O
ST/TTL
PMD4
64
80
100
I/O
ST/TTL
PMD5
1
1
3
I/O
ST/TTL
PMD6
2
2
4
I/O
ST/TTL
PMD7
3
3
5
I/O
ST/TTL
PMRD
53
67
82
I/O
ST/TTL
Parallel Master Port Read Strobe.
52
66
81
I/O
ST/TTL
Parallel Master Port Write Strobe.
PMWR
Legend:
Parallel Master Port Byte Enable Strobe.
Parallel Master Port Chip Select 1 Strobe/Address bit 14.
TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer
2005-2012 Microchip Technology Inc.
DS39747F-page 13
PIC24FJ128GA010 FAMILY
TABLE 1-2:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
I/O
Input
Buffer
17
I/O
ST
38
I/O
ST
—
58
I/O
ST
—
59
I/O
ST
—
—
60
I/O
ST
RA5
—
—
61
I/O
ST
RA6
—
—
91
I/O
ST
RA7
—
—
92
I/O
ST
RA9
—
23
28
I/O
ST
RA10
—
24
29
I/O
ST
RA14
—
52
66
I/O
ST
RA15
—
53
67
I/O
ST
RB0
16
20
25
I/O
ST
RB1
15
19
24
I/O
ST
RB2
14
18
23
I/O
ST
RB3
13
17
22
I/O
ST
RB4
12
16
21
I/O
ST
RB5
11
15
20
I/O
ST
RB6
17
21
26
I/O
ST
RB7
18
22
27
I/O
ST
RB8
21
27
32
I/O
ST
RB9
22
28
33
I/O
ST
Function
64-Pin
80-Pin
100-Pin
RA0
—
—
RA1
—
—
RA2
—
RA3
—
RA4
RB10
23
29
34
I/O
ST
RB11
24
30
35
I/O
ST
RB12
27
33
41
I/O
ST
RB13
28
34
42
I/O
ST
RB14
29
35
43
I/O
ST
RB15
30
36
44
I/O
ST
RC1
—
4
6
I/O
ST
RC2
—
—
7
I/O
ST
RC3
—
5
8
I/O
ST
RC4
—
—
9
I/O
ST
RC12
39
49
63
I/O
ST
RC13
47
59
73
I/O
ST
RC14
48
60
74
I/O
ST
RC15
40
50
64
I/O
ST
Legend:
Description
PORTA Digital I/O.
PORTB Digital I/O.
PORTC Digital I/O.
TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer
DS39747F-page 14
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 1-2:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
I/O
Input
Buffer
72
I/O
ST
76
I/O
ST
62
77
I/O
ST
63
78
I/O
ST
52
66
81
I/O
ST
RD5
53
67
82
I/O
ST
RD6
54
68
83
I/O
ST
RD7
55
69
84
I/O
ST
RD8
42
54
68
I/O
ST
RD9
43
55
69
I/O
ST
ST
Function
64-Pin
80-Pin
100-Pin
RD0
46
58
RD1
49
61
RD2
50
RD3
51
RD4
RD10
44
56
70
I/O
RD11
45
57
71
I/O
ST
RD12
—
64
79
I/O
ST
RD13
—
65
80
I/O
ST
RD14
—
37
47
I/O
ST
RD15
—
38
48
I/O
ST
RE0
60
76
93
I/O
ST
RE1
61
77
94
I/O
ST
RE2
62
78
98
I/O
ST
RE3
63
79
99
I/O
ST
RE4
64
80
100
I/O
ST
RE5
1
1
3
I/O
ST
RE6
2
2
4
I/O
ST
RE7
3
3
5
I/O
ST
RE8
—
13
18
I/O
ST
RE9
—
14
19
I/O
ST
RF0
58
72
87
I/O
ST
RF1
59
73
88
I/O
ST
RF2
34
42
52
I/O
ST
RF3
33
41
51
I/O
ST
RF4
31
39
49
I/O
ST
RF5
32
40
50
I/O
ST
RF6
35
45
55
I/O
ST
RF7
—
44
54
I/O
ST
RF8
—
43
53
I/O
ST
RF12
—
—
40
I/O
ST
RF13
—
—
39
I/O
ST
Legend:
Description
PORTD Digital I/O.
PORTE Digital I/O.
PORTF Digital I/O.
TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer
2005-2012 Microchip Technology Inc.
DS39747F-page 15
PIC24FJ128GA010 FAMILY
TABLE 1-2:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Function
I/O
64-Pin
80-Pin
100-Pin
Input
Buffer
RG0
—
75
90
I/O
ST
RG1
—
74
89
I/O
ST
RG2
37
47
57
I/O
ST
RG3
36
46
56
I/O
ST
RG6
4
6
10
I/O
ST
RG7
5
7
11
I/O
ST
Description
PORTG Digital I/O.
RG8
6
8
12
I/O
ST
RG9
8
10
14
I/O
ST
RG12
—
—
96
I/O
ST
RG13
—
—
97
I/O
ST
RG14
—
—
95
I/O
ST
RG15
—
—
1
I/O
ST
RTCC
42
54
68
O
—
Real-Time Clock Alarm Output.
SCK1
35
45
55
O
—
SPI1 Serial Clock Output.
SCK2
4
6
10
I/O
ST
SPI2 Serial Clock Output.
SCL1
37
47
57
I/O
I2C
I2C1 Synchronous Serial Clock Input/Output.
SCL2
32
52
58
I/O
I2C
I2C2 Synchronous Serial Clock Input/Output.
SDA1
36
46
56
I/O
I2C
I2C1 Data Input/Output.
2
SDA2
31
53
59
I/O
I C
I2C2 Data Input/Output.
SDI1
34
44
54
I
ST
SPI1 Serial Data Input.
SDI2
5
7
11
I
ST
SPI2 Serial Data Input.
SDO1
33
43
53
O
—
SPI1 Serial Data Output.
SPI2 Serial Data Output.
SDO2
6
8
12
O
—
SOSCI
47
59
73
I
ANA
Secondary Oscillator/Timer1 Clock Input.
SOSCO
48
60
74
O
ANA
Secondary Oscillator/Timer1 Clock Output.
SS1
14
18
23
I/O
ST
SS2
8
10
14
I/O
ST
Slave Select Input/Frame Select Output (SPI2).
T1CK
48
60
74
I
ST
Timer1 Clock.
T2CK
—
4
6
I
ST
Timer2 External Clock Input.
T3CK
—
—
7
I
ST
Timer3 External Clock Input.
T4CK
—
5
8
I
ST
Timer4 External Clock Input.
T5CK
—
—
9
I
ST
Timer5 External Clock Input.
TCK
27
33
38
I
ST
JTAG Test Clock/Programming Clock Input.
TDI
28
34
60
I
ST
JTAG Test Data/Programming Data Input.
TDO
24
14
61
O
—
JTAG Test Data Output.
TMS
23
13
17
I
ST
JTAG Test Mode Select Input.
Legend:
Slave Select Input/Frame Select Output (SPI1).
TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer
DS39747F-page 16
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 1-2:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
I/O
Input
Buffer
47
I
ST
Function
U1CTS
64-Pin
80-Pin
100-Pin
43
37
Description
UART1 Clear-to-Send Input.
U1RTS
35
38
48
O
—
UART1 Request-to-Send Output.
U1RX
34
42
52
I
ST
UART1 Receive.
U1TX
33
41
51
O
DIG
UART1 Transmit Output.
U2CTS
21
27
40
I
ST
UART2 Clear-to-Send Input.
U2RTS
29
35
39
O
—
UART2 Request-to-Send Output.
U2RX
31
39
49
I
ST
UART 2 Receive Input.
U2TX
32
40
50
O
—
UART2 Transmit Output.
VDD
10, 26, 38
12, 32, 48
2, 16, 37,
46, 62
P
—
Positive Supply for Peripheral Digital Logic and I/O Pins.
VDDCAP
56
70
85
P
—
External Filter Capacitor Connection (regulator is
enabled).
VDDCORE
56
70
85
P
—
Positive Supply for Microcontroller Core Logic (regulator
is disabled).
VREF-
15
23
28
I
ANA
VREF+
16
24
29
I
ANA
VSS
9, 25, 41
11, 31, 51
15, 36, 45,
65, 75
P
—
Legend:
A/D and Comparator Reference Voltage (Low) Input.
A/D and Comparator Reference Voltage (High) Input.
Ground Reference for Logic and I/O Pins.
TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer
2005-2012 Microchip Technology Inc.
DS39747F-page 17
PIC24FJ128GA010 FAMILY
NOTES:
DS39747F-page 18
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
MICROCONTROLLERS
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTIONS
C2(2)
• All VDD and VSS pins
(see Section 2.2 “Power Supply Pins”)
• All AVDD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
• ENVREG/DISVREG and VCAP/VDDCORE pins
(PIC24F J devices only)
(see Section 2.4 “Voltage Regulator Pins
(ENVREG/DISVREG and VCAP/VDDCORE)”)
These pins must also be connected if they are being
used in the end application:
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Additionally, the following pins may be required:
• VREF+/VREF- pins used when external voltage
reference for analog modules is implemented
Note:
VSS
VDD
R2
(1) (1)
(EN/DIS)VREG
MCLR
VCAP/VDDCORE
C1
C7
PIC24FJXXXX
VSS
VDD
VDD
VSS
C3(2)
C6(2)
C5(2)
VSS
The following pins must always be connected:
R1
VDD
Getting started with the PIC24FJ128GA010 family
family of 16-bit microcontrollers requires attention to a
minimal set of device pin connections before
proceeding with development.
VDD
AVSS
Basic Connection Requirements
AVDD
2.1
C4(2)
Key (all values are recommendations):
C1 through C6: 0.1 F, 20V ceramic
C7: 10 F, 6.3V or greater, tantalum or ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
Note 1:
2:
See Section 2.4 “Voltage Regulator Pins
(ENVREG/DISVREG and VCAP/VDDCORE)”
for explanation of ENVREG/DISVREG pin
connections.
The example shown is for a PIC24F device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
The minimum mandatory connections are shown in
Figure 2-1.
2005-2012 Microchip Technology Inc.
DS39747F-page 19
PIC24FJ128GA010 FAMILY
2.2
2.2.1
Power Supply Pins
DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
2.2.2
TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including microcontrollers to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.
DS39747F-page 20
2.3
Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions: device Reset, and device programming
and debugging. If programming and debugging are
not required in the end application, a direct
connection to VDD may be all that is required. The
addition of other components, to help increase the
application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and
debugging operations by using a jumper (Figure 2-2).
The jumper is replaced for normal run-time
operations.
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R1
R2
JP
MCLR
PIC24FXXXX
C1
Note 1:
R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2:
R2 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
2.4
Designers may use Figure 2-3 to evaluate ESR
equivalence of candidate devices.
Voltage Regulator Pins
(ENVREG/DISVREG and
VCAP/VDDCORE)
Note:
This section applies only to PIC24F J
devices with an on-chip voltage regulator.
The on-chip voltage regulator enable/disable pin
(ENVREG or DISVREG, depending on the device
family) must always be connected directly to either a
supply voltage or to ground. The particular connection
is determined by whether or not the regulator is to be
used:
The placement of this capacitor should be close to
VCAP/VDDCORE. It is recommended that the trace
length not exceed 0.25 inch (6 mm). Refer to
Section 27.0 “Electrical Characteristics” for
additional information.
When the regulator is disabled, the VCAP/VDDCORE pin
must be tied to a voltage supply at the VDDCORE level.
Refer to Section 27.0 “Electrical Characteristics” for
information on VDD and VDDCORE.
FIGURE 2-3:
• For ENVREG, tie to VDD to enable the regulator,
or to ground to disable the regulator
• For DISVREG, tie to ground to enable the
regulator or to VDD to disable the regulator
FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
10
Refer to Section 24.2 “On-Chip Voltage Regulator”
for details on connecting and using the on-chip
regulator.
ESR ()
1
When the regulator is enabled, a low-ESR (< 5Ω)
capacitor is required on the VCAP/VDDCORE pin to
stabilize the voltage regulator output voltage. The
VCAP/VDDCORE pin must not be connected to VDD and
must use a capacitor of 10 µF connected to ground. The
type can be ceramic or tantalum. Suitable examples of
capacitors are shown in Table 2-1. Capacitors with
equivalent specification can be used.
0.1
0.01
0.001
0.01
Note:
0.1
1
10
100
Frequency (MHz)
1000 10,000
Typical data measurement at 25°C, 0V DC bias.
.
TABLE 2-1:
SUITABLE CAPACITOR EQUIVALENTS
Make
Part #
Nominal
Capacitance
Base Tolerance
Rated Voltage
Temp. Range
TDK
C3216X7R1C106K
10 µF
±10%
16V
-55 to 125ºC
TDK
C3216X5R1C106K
10 µF
±10%
16V
-55 to 85ºC
Panasonic
ECJ-3YX1C106K
10 µF
±10%
16V
-55 to 125ºC
Panasonic
ECJ-4YB1C106K
10 µF
±10%
16V
-55 to 85ºC
Murata
GRM32DR71C106KA01L
10 µF
±10%
16V
-55 to 125ºC
Murata
GRM31CR61C106KC31L
10 µF
±10%
16V
-55 to 85ºC
2005-2012 Microchip Technology Inc.
DS39747F-page 21
PIC24FJ128GA010 FAMILY
CONSIDERATIONS FOR CERAMIC
CAPACITORS
In recent years, large value, low-voltage, surface-mount
ceramic capacitors have become very cost effective in
sizes up to a few tens of microfarad. The low-ESR, small
physical size and other properties make ceramic
capacitors very attractive in many types of applications.
Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller. However,
some care is needed in selecting the capacitor to
ensure that it maintains sufficient capacitance over the
intended operating range of the application.
Typical low-cost, 10 F ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial tolerance specifications for these types of capacitors are
often specified as ±10% to ±20% (X5R and X7R), or
-20%/+80% (Y5V). However, the effective capacitance
that these capacitors provide in an application circuit will
also vary based on additional factors, such as the
applied DC bias voltage and the temperature. The total
in-circuit tolerance is, therefore, much wider than the
initial tolerance specification.
The X5R and X7R capacitors typically exhibit satisfactory temperature stability (ex: ±15% over a wide
temperature range, but consult the manufacturer's data
sheets for exact specifications). However, Y5V capacitors typically have extreme temperature tolerance
specifications of +22%/-82%. Due to the extreme temperature tolerance, a 10 F nominal rated Y5V type
capacitor may not deliver enough total capacitance to
meet minimum internal voltage regulator stability and
transient response requirements. Therefore, Y5V
capacitors are not recommended for use with the
internal regulator if the application must operate over a
wide temperature range.
In addition to temperature tolerance, the effective
capacitance of large value ceramic capacitors can vary
substantially, based on the amount of DC voltage
applied to the capacitor. This effect can be very significant, but is often overlooked or is not always
documented.
Typical DC bias voltage vs. capacitance graph for X7R
type capacitors is shown in Figure 2-4.
FIGURE 2-4:
Capacitance Change (%)
2.4.1
DC BIAS VOLTAGE vs.
CAPACITANCE
CHARACTERISTICS
10
0
-10
16V Capacitor
-20
-30
-40
10V Capacitor
-50
-60
-70
6.3V Capacitor
-80
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DC Bias Voltage (VDC)
When selecting a ceramic capacitor to be used with the
internal voltage regulator, it is suggested to select a
high-voltage rating, so that the operating voltage is a
small percentage of the maximum rated capacitor voltage. For example, choose a ceramic capacitor rated at
16V for the 2.5V or 1.8V core voltage. Suggested
capacitors are shown in Table 2-1.
2.5
ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming (ICSP) and debugging purposes.
It is recommended to keep the trace length between
the ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGECx/PGEDx pins),
programmed into the device, matches the physical
connections for the ICSP to the Microchip
debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 26.0 “Development Support”.
DS39747F-page 22
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
2.6
External Oscillator Pins
FIGURE 2-5:
Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency
secondary
oscillator
(refer to
Section 8.0 “Oscillator Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.
Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
Single-Sided and In-line Layouts:
Copper Pour
(tied to ground)
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate web site
(www.microchip.com):
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design”
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work”
Primary Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
OSCI
C1
`
OSCO
GND
C2
`
SOSCO
SOSC I
Secondary
Oscillator
Crystal
Layout suggestions are shown in Figure 2-5. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
In planning the application’s routing and I/O assignments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times
and other similar noise).
SUGGESTED
PLACEMENT OF THE
OSCILLATOR CIRCUIT
`
Sec Oscillator: C1
Sec Oscillator: C2
Fine-Pitch (Dual-Sided) Layouts:
Top Layer Copper Pour
(tied to ground)
Bottom Layer
Copper Pour
(tied to ground)
OSCO
C2
Oscillator
Crystal
GND
C1
OSCI
DEVICE PINS
2005-2012 Microchip Technology Inc.
DS39747F-page 23
PIC24FJ128GA010 FAMILY
2.7
Configuration of Analog and
Digital Pins During ICSP
Operations
If an ICSP compliant emulator is selected as a debugger, it automatically initializes all of the A/D input pins
(ANx) as “digital” pins. Depending on the particular
device, this is done by setting all bits in the ADnPCFG
register(s), or clearing all bit in the ANSx registers.
All PIC24F devices will have either one or more
ADnPCFG registers or several ANSx registers (one for
each port); no device will have both. Refer to
Section 21.0 “10-bit High-Speed A/D Converter” for
more specific information.
The bits in these registers that correspond to the A/D
pins that initialized the emulator must not be changed
by the user application firmware; otherwise,
communication errors will result between the debugger
and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must modify the appropriate bits during
initialization of the A/D module, as follows:
• For devices with an ADnPCFG register, clear the
bits corresponding to the pin(s) to be configured
as analog. Do not change any other bits, particularly those corresponding to the PGECx/PGEDx
pair, at any time.
• For devices with ANSx registers, set the bits
corresponding to the pin(s) to be configured as
analog. Do not change any other bits, particularly
those corresponding to the PGECx/PGEDx pair,
at any time.
When a Microchip debugger/emulator is used as a
programmer, the user application firmware must
correctly configure the ADnPCFG or ANSx registers.
Automatic initialization of this register is only done
during debugger operation. Failure to correctly
configure the register(s) will result in all A/D pins being
recognized as analog input pins, resulting in the port
value being read as a logic '0', which may affect user
application functionality.
2.8
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
DS39747F-page 24
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
3.0
Note:
CPU
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 2. “CPU”
(DS39703) in the “PIC24F Family Reference
Manual” for more information.
The PIC24F CPU has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set, and a
24-bit instruction word with a variable length opcode
field. The Program Counter (PC) is 23 bits wide and
addresses up to 4M instructions of user program
memory space. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and
provides predictable execution. All instructions execute
in a single cycle, with the exception of instructions that
change the program flow, the double-word move
(MOV.D) instruction and the table instructions.
Overhead-free program loop constructs are supported
using the REPEAT instructions, which are interruptible
at any point.
PIC24F devices have sixteen 16-bit working registers
in the programmer’s model. Each of the working
registers can act as a data, address or address offset
register. The 16th working register (W15) operates as
a Software Stack Pointer for interrupts and calls.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K word boundary defined by the 8-bit Program
Space Visibility Page (PSVPAG) register. The program
to data space mapping feature lets any instruction
access program space as if it were data space.
The Instruction Set Architecture (ISA) has been significantly enhanced beyond that of the PIC18, but
maintains an acceptable level of backward compatibility.
All PIC18 instructions and addressing modes are
supported either directly or through simple macros.
Many of the ISA enhancements have been driven by
compiler efficiency needs.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working register (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, three parameter instructions can be supported,
allowing trinary operations (that is, A + B = C) to be
executed in a single cycle.
A high-speed, 17-bit by 17-bit multiplier has been
included to significantly enhance the core arithmetic
capability and throughput. The multiplier supports
signed, unsigned and Mixed mode 16-bit by 16-bit or
8-bit by 8-bit integer multiplication. All multiply
instructions execute in a single cycle.
The 16-bit ALU has been enhanced with integer divide
assist hardware that supports an iterative, non-restoring
divide algorithm. It operates in conjunction with the
REPEAT instruction looping mechanism, and a selection
of iterative divide instructions, to support 32-bit (or
16-bit) divided by 16-bit integer signed and unsigned
division. All divide operations require 19 cycles to
complete but are interruptible at any cycle boundary.
The PIC24F has a vectored exception scheme with up
to 8 sources of non-maskable traps and up to
118 interrupt sources. Each interrupt source can be
assigned to one of seven priority levels.
A block diagram of the CPU is shown in Figure 3-1.
3.1
Programmer’s Model
The programmer’s model for the PIC24F is shown in
Figure 3-2. All registers in the programmer’s model are
memory mapped and can be manipulated directly by
instructions. A description of each register is provided
in Table 3-1. All registers associated with the
programmer’s model are memory mapped.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct and three groups of addressing
modes. All modes support Register Direct and various
Register Indirect modes. Each group offers up to
7 addressing modes. Instructions are associated with
predefined addressing modes depending upon their
functional requirements.
2005-2012 Microchip Technology Inc.
DS39747F-page 25
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FIGURE 3-1:
PIC24F CPU CORE BLOCK DIAGRAM
PSV & Table
Data Access
Control Block
Data Bus
Interrupt
Controller
16
8
16
16
Data Latch
23
23
PCL
PCH
Program Counter
Loop
Stack
Control
Control
Logic
Logic
16
Data RAM
Address
Latch
23
16
RAGU
WAGU
Address Latch
Program Memory
EA MUX
Address Bus
Data Latch
ROM Latch
24
Control Signals
to Various Blocks
Instruction Reg
Hardware
Multiplier
Divide
Support
16
Literal Data
Instruction
Decode &
Control
16
16 x 16
W Register Array
16
16-Bit ALU
16
To Peripheral Modules
DS39747F-page 26
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PIC24FJ128GA010 FAMILY
TABLE 3-1:
CPU CORE REGISTERS
Register(s) Name
Description
W0 through W15
Working Register Array
PC
23-Bit Program Counter
SR
ALU STATUS Register
SPLIM
Stack Pointer Limit Value Register
TBLPAG
Table Memory Page Address Register
PSVPAG
Program Space Visibility Page Address Register
RCOUNT
Repeat Loop Counter Register
CORCON
CPU Control Register
FIGURE 3-2:
PROGRAMMER’S MODEL
15
Divider Working Registers
0
W0 (WREG)
W1
W2
Multiplier Registers
W3
W4
W5
W6
W7
Working/Address
Registers
W8
W9
W10
W11
W12
W13
W14
Frame Pointer
W15
Stack Pointer
0
SPLIM
0
Stack Pointer Limit
0
0
Program Counter
22
PC
7
0
TBLPAG
7
Data Table Page Address
0
PSVPAG
15
0
RCOUNT
15
Program Space Visibility
Page Address
SRH
Repeat Loop Counter
SRL
0
— — — — — — — DC IPL RA N OV Z C
2 1 0
15
STATUS Register (SR)
0
— — — — — — — — — — — — IPL3 PSV — —
Core Control Register (CORCON)
Registers or bits are shadowed for PUSH.S and POP.S instructions.
2005-2012 Microchip Technology Inc.
DS39747F-page 27
PIC24FJ128GA010 FAMILY
3.2
CPU Control Registers
REGISTER 3-1:
SR: CPU STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
DC
bit 15
bit 8
R/W-0(1)
IPL2
R/W-0(1)
(2)
IPL1
(2)
R/W-0(1)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
IPL0(2)
RA
N
OV
Z
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented: Read as ‘0’
bit 8
DC: ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th or 8th low-order bit of the result has occurred
bit 7-5
IPL: CPU Interrupt Priority Level Status bits(2)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4
RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3
N: ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2
OV: ALU Overflow bit
1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation
0 = No overflow has occurred
bit 1
Z: ALU Zero bit
1 = An operation, which effects the Z bit, has set it at some time in the past
0 = The most recent operation, which effects the Z bit, has cleared it (i.e., a non-zero result)
bit 0
C: ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
The IPL Status bits are read-only when NSTDIS (INTCON1) = 1.
The IPL bits are concatenated with the IPL3 bit (CORCON) to form the CPU Interrupt Priority Level.
The value in parentheses indicates the IPL when IPL3 = 1.
DS39747F-page 28
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
U-0
—
—
U-0
—
R/C-0
(1)
IPL3
R/W-0
U-0
U-0
PSV
—
—
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-4
Unimplemented: Read as ‘0’
bit 3
IPL3: CPU Interrupt Priority Level Status bit(1)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
bit 2
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space is visible in data space
0 = Program space is not visible in data space
bit 1-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
User interrupts are disabled when IPL3 = 1.
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DS39747F-page 29
PIC24FJ128GA010 FAMILY
3.3
Arithmetic Logic Unit (ALU)
The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless
otherwise mentioned, arithmetic operations are 2’s
complement in nature. Depending on the operation, the
ALU may affect the values of the Carry (C), Zero (Z),
Negative (N), Overflow (OV) and Digit Carry (DC)
Status bits in the SR register. The C and DC Status bits
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array, or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
The PIC24F CPU incorporates hardware support for
both multiplication and division. This includes a dedicated hardware multiplier and support hardware for
16-bit divisor division.
3.3.1
MULTIPLIER
The ALU contains a high-speed, 17-bit x 17-bit
multiplier. It supports unsigned, signed or mixed sign
operation in several multiplication modes:
1.
2.
3.
4.
5.
6.
7.
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
TABLE 3-2:
Instruction
3.3.2
DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operation with the
following data sizes:
1.
2.
3.
4.
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both the
16-bit divisor (Wn) and any W register (aligned) pair
(W(m+1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
3.3.3
MULTI-BIT SHIFT SUPPORT
The PIC24F ALU supports both single bit and
single-cycle, multi-bit arithmetic and logic shifts.
Multi-bit shifts are implemented using a shifter block,
capable of performing up to a 15-bit arithmetic right
shift, or up to a 15-bit left shift, in a single cycle. All
multi-bit shift instructions only support Register Direct
Addressing for both the operand source and result
destination.
A full summary of instructions that use the shift
operation is provided below in Table 3-2.
INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION
Description
ASR
Arithmetic shift right source register by one or more bits.
SL
Shift left source register by one or more bits.
LSR
Logical shift right source register by one or more bits.
DS39747F-page 30
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
4.0
MEMORY ORGANIZATION
As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory
spaces and busses. This architecture also allows the
direct access of program memory from the data space
during code execution.
4.1
Program Address Space
The
program
address
memory
space
of
PIC24FJ128GA010 family devices is 4M instructions.
The space is addressable by a 24-bit value derived from
FIGURE 4-1:
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24FJ128GA010 family of
devices are shown in Figure 4-1.
PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GA010 FAMILY DEVICES
PIC24FJ64GA
PIC24FJ96GA
PIC24FJ128GA
GOTO Instruction
Reset Address
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Interrupt Vector Table
Reserved
GOTO Instruction
Reset Address
Interrupt Vector Table
Alternate Vector Table
Alternate Vector Table
User Flash
Program Memory
(22K instructions)
User Memory Space
either the 23-bit Program Counter (PC) during program
execution, or from table operation or data space
remapping, as described in Section 4.3 “Interfacing
Program and Data Memory Spaces”.
Flash Config Words
User Flash
Program Memory
(32K instructions)
Reserved
Alternate Vector Table
User Flash
Program Memory
(44K instructions)
0000FEh
000100h
000104h
0001FEh
000200h
00ABFEh
00AC00h
00FFFEh
010000h
Flash Config Words
Flash Config Words
Unimplemented
(Read ‘0’s)
000000h
000002h
000004h
0157FEh
015800h
Unimplemented
(Read ‘0’s)
Unimplemented
(Read ‘0’s)
Configuration Memory Space
7FFFFEh
800000h
Note:
Reserved
Reserved
Reserved
Device Configuration
Registers
Device Configuration
Registers
Device Configuration
Registers
Reserved
Reserved
DEVID (2)
DEVID (2)
F7FFFEh
F80000h
F8000Eh
F80010h
Reserved
DEVID (2)
FEFFFEh
FF0000h
FFFFFEh
Memory areas are not shown to scale.
2005-2012 Microchip Technology Inc.
DS39747F-page 31
PIC24FJ128GA010 FAMILY
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.3
In PIC24FJ128GA010 family devices, the top two words
of on-chip program memory are reserved for configuration information. On device Reset, the configuration
information is copied into the appropriate Configuration
registers. The addresses of the Flash Configuration
Word for devices in the PIC24FJ128GA010 family are
shown in Table 4-1. Their location in the memory map is
shown with the other memory vectors in Figure 4-1.
The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 4-2).
The Configuration Words in program memory are a
compact format. The actual Configuration bits are
mapped in several different registers in the configuration
memory space. Their order in the Flash Configuration
Words do not reflect a corresponding arrangement in the
configuration space. Additional details on the device
Configuration Words are provided in Section 24.1
“Configuration Bits”.
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
4.1.2
HARD MEMORY VECTORS
TABLE 4-1:
All PIC24F devices reserve the addresses between
00000h and 000200h for hard coded program execution vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the
PC on device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h, with
the actual address for the start of code at 000002h.
PIC24F devices also have two Interrupt Vector Tables
(IVT), located from 000004h to 0000FFh, and 000100h
to 0001FFh. These vector tables allow each of the
many device interrupt sources to be handled by separate ISRs. A more detailed discussion of the Interrupt
Vector Tables is provided in Section 7.1 “Interrupt
Vector Table”.
FIGURE 4-2:
msw
Address
Device
Program
Memory
(Words)
Configuration
Word
Addresses
PIC24FJ64GA
22,016
00ABFCh:
00ABFEh
PIC24FJ96GA
32,768
00FFFCh:
00FFFEh
PIC24FJ128GA
44,032
0157FCh:
0157FEh
least significant word
most significant word
16
8
PC Address
(lsw Address)
0
000000h
000002h
000004h
000006h
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte’
(read as ‘0’)
DS39747F-page 32
FLASH CONFIGURATION
WORDS FOR
PIC24FJ128GA010 FAMILY
DEVICES
PROGRAM MEMORY ORGANIZATION
23
000001h
000003h
000005h
000007h
FLASH CONFIGURATION WORDS
Instruction Width
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
4.2
Note:
Data Address Space
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 3. “Data Memory” (DS39717) in the “PIC24F Family
Reference Manual” for more information.
The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The
data space is accessed using two Address Generation
Units (AGUs), one each for read and write operations.
The data space memory map is shown in Figure 4-3.
All Effective Addresses (EAs) in the data memory
space are 16 bits wide and point to bytes within the
data space. This gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
FIGURE 4-3:
memory space (that is, when EA = 0) is used for
implemented memory addresses, while the upper half
(EA = 1) is reserved for the Program Space Visibility area (see Section 4.3.3 “Reading Data from
Program Memory Using Program Space Visibility”).
PIC24FJ128GA010 family devices implement a total of
8 Kbytes of data memory. Should an EA point to a
location outside of this area, an all zero word or byte will
be returned.
4.2.1
DATA SPACE WIDTH
The data memory space is organized in
byte-addressable, 16-bit wide blocks. Data is aligned in
data memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant Bytes
(LSBs) of each word have even addresses, while the
Most Significant Bytes (MSBs) have odd addresses.
DATA SPACE MEMORY MAP FOR PIC24FJ128GA010 FAMILY DEVICES
MSB
Address
0001h
07FFh
0801h
Implemented
Data RAM
MSB
LSB
SFR Space
LSB
Address
0000h
07FEh
0800h
Near
Data Space
Data RAM
1FFFh
2001h
27FFh
2801h
SFR
Space
1FFEh
2000h
27FEh
2800h
Unimplemented
Read as ‘0’
7FFFh
8001h
7FFFh
8000h
Program Space
Visibility Area
FFFFh
Note:
FFFEh
Data memory areas are not shown to scale.
2005-2012 Microchip Technology Inc.
DS39747F-page 33
PIC24FJ128GA010 FAMILY
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
A Sign-Extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
Zero-Extend (ZE) instruction on the appropriate
address.
To maintain backward compatibility with PIC® devices
and improve data space memory usage efficiency, the
PIC24F instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
Effective Address calculations are internally scaled to
step through word-aligned memory. For example, the
core recognizes that Post-Modified Register Indirect
Addressing mode [Ws++] will result in a value of
Ws + 1 for byte operations and Ws + 2 for word
operations.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions operate only on words.
4.2.3
The 8-Kbyte area, between 0000h and 1FFFh, is
referred to as the Near Data Space (NDS). Locations in
this space are directly addressable via a 13-bit absolute address field within all memory direct instructions.
The remainder of the data space is indirectly addressable. Additionally, the whole data space is addressable
using MOV instructions, which support Memory Direct
Addressing with a 16-bit address field.
Data byte reads will read the complete word which contains the byte, using the LSb of any EA to determine
which byte to select. The selected byte is placed onto
the LSB of the data path. That is, data memory and registers are organized as two parallel, byte-wide entities
with shared (word) address decode, but separate write
lines. Data byte writes only write to the corresponding
side of the array or register which matches the byte
address.
4.2.4
SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0000h
to 07FFh, are primarily occupied with Special Function
Registers (SFRs). These are used by the PIC24F core
and peripheral modules for controlling the operation of
the device.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed; if it occurred on
a write, the instruction will be executed but the write will
not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine
state prior to execution of the address Fault.
SFRs are distributed among the modules that they control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A diagram of the SFR space,
showing where SFRs are actually implemented, is
shown in Table 4-2. Each implemented area indicates
a 32-byte region where at least one address is implemented as an SFR. A complete listing of implemented
SFRs, including their addresses, is shown in Tables 4-3
through 4-30.
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.
TABLE 4-2:
NEAR DATA SPACE
IMPLEMENTED REGIONS OF SFR DATA SPACE
SFR Space Address
xx00
xx20
xx60
Core
000h
Timers
100h
200h
xx40
I
2C™
ICN
Capture
UART
A/D
300h
xx80
—
SPI
xxA0
xxC0
xxE0
Interrupts
Compare
—
—
—
—
—
—
I/O
—
—
—
—
—
—
400h
—
—
—
—
—
—
—
—
500h
—
—
—
—
—
—
—
—
600h
PMP
RTC/Comp
CRC
—
—
—
700h
—
—
System
NVM/PMD
—
—
I/O
—
—
Legend: — = No implemented SFRs in this block
DS39747F-page 34
2005-2012 Microchip Technology Inc.
2005-2012 Microchip Technology Inc.
TABLE 4-3:
CPU CORE REGISTERS MAP
WREG0
0000
Working Register 0
0000
WREG1
0002
Working Register 1
0000
WREG2
0004
Working Register 2
0000
WREG3
0006
Working Register 3
0000
WREG4
0008
Working Register 4
0000
WREG5
000A
Working Register 5
0000
WREG6
000C
Working Register 6
0000
WREG7
000E
Working Register 7
0000
WREG8
0010
Working Register 8
0000
WREG9
0012
Working Register 9
0000
WREG10
0014
Working Register 10
0000
WREG11
0016
Working Register 11
0000
WREG12
0018
Working Register 12
0000
WREG13
001A
Working Register 13
0000
WREG14
001C
Working Register 14
0000
WREG15
001E
Working Register 15
0800
SPLIM
0020
Stack Pointer Limit
xxxx
PCL
002E
Program Counter Low Word
PCH
0030
—
—
—
—
—
—
—
—
TBLPAG
0032
—
—
—
—
—
—
—
PSVPAG
0034
—
—
—
—
—
—
—
RCOUNT
0036
SR
0042
—
—
—
—
—
—
—
DC
IPL2
IPL1
IPL0
RA
N
OV
Z
C
0000
CORCON
0044
—
—
—
—
—
—
—
—
—
—
—
—
IPL3
PSV
—
—
0000
0052
—
—
Legend:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000
Program Counter High Byte
0000
—
Table Page Address Pointer
0000
—
Program Memory Visibility Page Address Pointer
0000
Repeat Loop Counter
xxxx
Disable Interrupts Counter
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
xxxx
DS39747F-page 35
PIC24FJ128GA010 FAMILY
Addr
DISICNT
Bit 15
All
Resets
File Name
INTERRUPT CONTROLLER REGISTER MAP
File
Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
INTCON1
0080
NSTDIS
—
—
—
—
—
—
—
—
—
—
INTCON2
0082
ALTIVT
DISI
—
—
—
—
—
—
—
—
—
IFS0
0084
—
—
AD1IF
U1TXIF
U1RXIF
SPI1IF
SPF1IF
T3IF
T2IF
OC2IF
IC2IF
IFS1
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
—
—
—
—
Bit 4
Bit 3
MATHERR ADDRERR
Bit 2
Bit 1
Bit 0
All
Resets
STKERR
OSCFAIL
—
0000
INT3EP
INT2EP
INT1EP
INT0EP
0000
—
T1IF
OC1IF
IC1IF
INT0IF
0000
INT1IF
CNIF
CMIF
MI2C1IF
SI2C1IF
0000
INT4EP
IFS2
0088
—
—
PMPIF
—
—
—
OC5IF
—
IC5IF
IC4IF
IC3IF
—
—
—
SPI2IF
SPF2IF
0000
IFS3
008A
—
RTCIF
—
—
—
—
—
—
—
INT4IF
INT3IF
—
—
MI2C2IF
SI2C2IF
—
0000
IFS4
008C
—
—
—
—
—
—
—
—
—
—
—
—
CRCIF
U2ERIF
U1ERIF
—
0000
IEC0
0094
—
—
AD1IE
U1TXIE
U1RXIE
SPI1IE
SPF1IE
T3IE
T2IE
OC2IE
IC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
—
—
—
—
INT1IE
CNIE
CMIE
MI2C1IE
SI2C1IE
0000
2005-2012 Microchip Technology Inc.
IEC2
0098
—
—
PMPIE
—
—
—
OC5IE
—
IC5IE
IC4IE
IC3IE
—
—
—
SPI2IE
SPF2IE
0000
IEC3
009A
—
RTCIE
—
—
—
—
—
—
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
0000
IEC4
009C
—
—
—
—
—
—
—
—
—
—
—
—
CRCIE
U2ERIE
U1ERIE
—
0000
IPC0
00A4
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
4444
IPC1
00A6
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
—
—
—
4440
IPC2
00A8
—
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPF1IP2
SPF1IP1
SPF1IP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
00AA
—
—
—
—
—
—
—
—
—
AD1IP2
AD1IP1
AD1IP0
—
U1TXIP2
U1TXIP1
U1TXIP0
0044
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
CMIP2
CMIP1
CMIP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2
SI2C1IP1
SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
0004
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
—
—
—
4440
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2 U2RXIP1 U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
4444
IPC8
00B4
—
—
—
—
—
—
—
—
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPF2IP2
SPF2IP1
SPF2IP0
0044
IPC9
00B6
—
IC5IP2
IC5IP1
IC5IP0
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
—
—
—
4440
IPC10
00B8
—
—
—
—
—
—
—
—
—
OC5IP2
OC5IP1
OC5IP0
—
—
—
—
0040
IPC11
00BA
—
—
—
—
—
—
—
—
—
PMPIP2
PMPIP1
PMPIP0
—
—
—
—
0040
IPC12
00BC
—
—
—
—
—
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
00BE
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
0440
IPC15
00C2
—
—
—
—
—
RTCIP2
RTCIP1
RTCIP0
—
—
—
—
—
—
—
—
0400
IPC16
00C4
—
CRCIP2
CRCIP1
CRCIP0
—
—
U1ERIP2
U1ERIP1
U1ERIP0
—
—
—
—
INTTREG
00E0
CPUIRQ
—
VHOLD
—
ILR3
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
U1RXIP2 U1RXIP1 U1RXIP0
MI2C2IP2 MI2C2IP1 MI2C2IP0
U2ERIP2 U2ERIP1 U2ERIP0
ILR2
ILR1
ILR0
—
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
4440
0000
PIC24FJ128GA010 FAMILY
DS39747F-page 36
TABLE 4-4:
2005-2012 Microchip Technology Inc.
TABLE 4-5:
File
Name
Addr
ICN REGISTER MAP
Bit 5
CN1IE
CN0IE
0000
CN16IE
0000
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
CNEN1 0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CNEN2 0062
—
—
—
—
—
—
—
—
—
—
CN21IE(1)
CN20IE(1)
CN19IE(1)
CN18IE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN0PUE
0000
CN21PUE(1) CN20PUE(1) CN19PUE(1) CN18PUE CN17PUE CN16PUE
0000
Legend:
Note 1:
—
—
—
—
—
—
—
—
—
Bit 1
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal
Implemented in 80-pin and 100-pin devices only.
TABLE 4-6:
File Name
—
Bit 2
CN17IE
Bit 13
CNPU2 006A
Bit 3
All
Resets
Bit 14
CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE
Bit 4
Bit 0
Bit 15
Addr
TIMER REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TMR1
0100
Timer1 Register
PR1
0102
Period Register 1
T1CON
0104
TMR2
0106
Timer2 Register
xxxx
TMR3HLD
0108
Timer3 Holding Register (For 32-bit timer operations only)
xxxx
TMR3
010A
Timer3 Register
xxxx
PR2
010C
Period Register 2
FFFF
PR3
010E
Period Register 3
T2CON
0110
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS
—
0000
T3CON
0112
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
—
—
TCS
—
0000
TMR4
0114
Timer4 Register
xxxx
TMR5HLD
0116
Timer5 Holding Register (For 32-bit operations only)
xxxx
TMR5
0118
Timer5 Register
xxxx
PR4
011A
Period Register 4
FFFF
PR5
011C
Period Register 5
T4CON
011E
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS
—
0000
0120
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
—
—
TCS
—
0000
Legend:
—
TSIDL
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
FFFF
TGATE
TCKPS1
TCKPS0
—
TSYNC
TCS
—
0000
FFFF
FFFF
DS39747F-page 37
PIC24FJ128GA010 FAMILY
T5CON
TON
xxxx
File Name
Addr
IC1BUF
0140
IC1CON
0142
IC2BUF
0144
IC2CON
0146
IC3BUF
0148
IC3CON
014A
IC4BUF
014C
IC4CON
014E
IC5BUF
0150
IC5CON
0152
INPUT CAPTURE REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
—
ICSIDL
—
—
—
—
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
Input 1 Capture Register
—
ICTMR
xxxx
Input 2 Capture Register
—
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICI1
ICTMR
ICOV
ICBNE
ICM2
ICM1
ICM0
—
ICSIDL
—
—
—
—
—
ICI1
ICTMR
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
—
ICSIDL
—
—
—
—
—
ICTMR
0000
xxxx
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
Input 5 Capture Register
—
0000
xxxx
0000
xxxx
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
Bit 1
Bit 0
All
Resets
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Legend:
TABLE 4-8:
File Name
Addr
OUTPUT COMPARE REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
OC1RS
0180
Output Compare 1 Secondary Register
OC1R
0182
Output Compare 1 Register
OC1CON
0184
OC2RS
0186
2005-2012 Microchip Technology Inc.
OC2R
0188
OC2CON
018A
OC3RS
018C
OC3R
018E
OC3CON
0190
OC4RS
0192
OC4R
0194
OC4CON
0196
OC5RS
0198
OC5R
019A
OC5CON
019C
Legend:
ICI0
Input 4 Capture Register
—
0000
xxxx
Input 3 Capture Register
—
All
Resets
—
—
OCSIDL
—
—
—
—
—
—
—
Bit 5
Bit 4
Bit 3
Bit 2
xxxx
xxxx
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
Output Compare 2 Secondary Register
Output Compare 2 Register
—
—
OCSIDL
—
—
—
—
—
—
—
xxxx
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
Output Compare 3 Secondary Register
—
OCSIDL
—
—
—
—
—
—
—
xxxx
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
Output Compare 4 Secondary Register
—
OCSIDL
—
—
—
—
—
—
—
xxxx
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
Output Compare 5 Secondary Register
—
OCSIDL
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
0000
xxxx
Output Compare 5 Register
—
0000
xxxx
Output Compare 4 Register
—
0000
xxxx
Output Compare 3 Register
—
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
0000
PIC24FJ128GA010 FAMILY
DS39747F-page 38
TABLE 4-7:
2005-2012 Microchip Technology Inc.
TABLE 4-9:
I2C1 REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
I2C1RCV
0200
—
—
—
—
—
—
—
—
Receive Register
I2C1TRN
0202
—
—
—
—
—
—
—
—
Transmit Register
I2C1BRG
0204
—
—
—
—
—
—
—
Bit 2
Bit 1
Bit 0
All
Resets
0000
00FF
Baud Rate Generator
0000
I2C1CON
0206
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
I2C1STAT
0208
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
I2C1ADD
020A
—
—
—
—
—
—
Address Register
0000
I2C1MSK
020C
—
—
—
—
—
—
Address Mask
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-10:
File Name
I2C2 REGISTER MAP
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C2RCV
0210
—
—
—
—
—
—
—
—
Receive Register
I2C2TRN
0212
—
—
—
—
—
—
—
—
Transmit Register
I2C2BRG
0214
—
—
—
—
—
—
—
I2C2CON
0216
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
I2C2STAT
0218
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2CPOV
I2C2ADD
021A
—
—
—
—
—
—
Address Register
0000
021C
—
—
—
—
—
—
Address Mask
0000
I2C2MSK
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
00FF
Baud Rate Generator
0000
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
D/A
P
S
R/W
RBF
TBF
1000
0000
DS39747F-page 39
PIC24FJ128GA010 FAMILY
All
Resets
File Name
Addr
UART1 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
WAKE
LPBACK
Bit 0
All
Resets
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ABAUD
RXINV
BRGH
PDSEL1
PDSEL0
STSEL
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
U1MODE
0220
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
U1STA
0222
UTXISEL1
TXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
U1TXREG
0224
—
—
—
—
—
—
—
Transmit Register
xxxx
U1RXREG
0226
—
—
—
—
—
—
—
Receive Register
0000
U1BRG
0228
Legend:
Baud Rate Generator Prescaler
UART2 REGISTER MAP
File Name
Addr
U2MODE
0230
UARTEN
U2STA
0232
UTXISEL1
U2TXREG
0234
—
U2RXREG
0236
—
U2BRG
0238
Bit 15
Bit 14
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
WAKE
LPBACK
Bit 0
All
Resets
PDSEL0
STSEL
0000
OERR
URXDA
0110
Bit 13
Bit 12
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
TXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
—
—
—
—
—
—
Transmit Register
xxxx
—
—
—
—
—
—
Receive Register
0000
URXISEL1 URXISEL0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ABAUD
RXINV
BRGH
PDSEL1
ADDEN
RIDLE
PERR
FERR
Baud Rate Generator Prescaler
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-13:
File Name
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-12:
Legend:
URXISEL1 URXISEL0
SPI1 REGISTER MAP
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
2005-2012 Microchip Technology Inc.
SPI1STAT
0240
SPIEN
—
SPISIDL
—
—
SRMPT
SPIROV
SRXMPT
SISEL2
SISEL1
SISEL0
SPITBF
SPIRBF
0000
SPI1CON1
0242
—
—
—
DISSCK
DISSDO
MODE16
SMP
CKE
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
0000
SPI1CON2
0244
FRMEN
SPIFSD
SPIFPOL
—
—
—
—
—
—
—
—
—
—
—
SPIFE
SPIBEN
0000
SPI1BUF
0248
Legend:
SPI1 Transmit and Receive Buffer
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-14:
File Name
SPIBEC2 SPIBEC1 SPIBEC0
Bit 7
SPI2 REGISTER MAP
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
SPI2STAT
0260
SPIEN
—
SPISIDL
—
—
SRMPT
SPIROV
SRXMPT
SISEL2
SISEL1
SISEL0
SPITBF
SPIRBF
0000
SPI2CON1
0262
—
—
—
DISSCK
DISSDO
MODE16
SMP
CKE
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
0000
SPI2CON2
0264
FRMEN
SPIFSD
SPIFPOL
—
—
—
—
—
—
—
—
—
—
—
SPIFE
SPIBEN
0000
SPI2BUF
0268
Legend:
SPIBEC2 SPIBEC1 SPIBEC0
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SPI2 Transmit and Receive Buffer
0000
PIC24FJ128GA010 FAMILY
DS39747F-page 40
TABLE 4-11:
2005-2012 Microchip Technology Inc.
TABLE 4-15:
File Name
Addr
A/D REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ADC1BUF0
0300
A/D Data Buffer 0
xxxx
ADC1BUF1
0302
A/D Data Buffer 1
xxxx
xxxx
ADC1BUF2
0304
A/D Data Buffer 2
ADC1BUF3
0306
A/D Data Buffer 3
xxxx
ADC1BUF4
0308
A/D Data Buffer 4
xxxx
ADC1BUF5
030A
A/D Data Buffer 5
xxxx
ADC1BUF6
030C
A/D Data Buffer 6
xxxx
ADC1BUF7
030E
A/D Data Buffer 7
xxxx
ADC1BUF8
0310
A/D Data Buffer 8
xxxx
0312
A/D Data Buffer 9
xxxx
0314
A/D Data Buffer 10
xxxx
ADC1BUFB
0316
A/D Data Buffer 11
xxxx
ADC1BUFC
0318
A/D Data Buffer 12
xxxx
ADC1BUFD
031A
A/D Data Buffer 13
xxxx
ADC1BUFE
031C
A/D Data Buffer 14
xxxx
ADC1BUFF
031E
A/D Data Buffer 15
AD1CON1
0320
ADON
—
ADSIDL
AD1CON2
0322
VCFG2
VCFG1
VCFG0
AD1CON3
0324
ADRC
—
—
—
FORM1
FORM0
SSRC2
xxxx
—
—
SSRC1
SSRC0
—
—
ASAM
SAMP
DONE
r
—
CSCNA
—
—
BUFS
—
SMPI3
SMPI2
SMPI1
SMPI0
BUFM
ALTS
0000
SAMC4
SAMC3
SAMC2
SAMC1
SAMC0
ADCS7
ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
ADCS0
0000
0000
AD1CHS
0328
CH0NB
—
—
—
CH0SB3
CH0SB2
CH0SB1
CH0SB0
CH0NA
—
—
—
CH0SA3
CH0SA2
CH0SA1
CH0SA0
0000
AD1PCFG
032C
PCFG15
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000
AD1CSSL
0330
CSSL15
CSSL14
CSSL13
CSSL12
CSSL11
CSSL10
CSSL9
CSSL8
CSSL7
CSSL6
CSSL5
CSSL4
CSSL3
CSSL2
CSSL1
CSSL0
0000
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’; r = reserved, maintain as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-16:
PORTA REGISTER MAP
DS39747F-page 41
File Name
Addr
TRISA
02C0
PORTA
02C2
RA15(1)
RA14(1)
LATA
02C4
LATA15(1)
ODCA
06C0
ODA15(1)
Legend:
Note 1:
2:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
—
—
—
—
—
—
RA10(1)
RA9(1)
—
RA7
RA6
RA5(2)
RA4(2)
RA3(2)
RA2(2)
RA1(2)
RA0(2)
xxxx
LATA14(1)
—
—
—
LATA10(1)
LATA9(1)
—
LATA7
LATA6
LATA5(2)
LATA4(2)
LATA3(2)
LATA2(2)
LATA1(2)
LATA0(2)
xxxx
ODA14(1)
—
—
—
ODA10(1)
ODA9(1)
—
ODA7
ODA6
ODA5(2)
ODA4(2)
ODA3(2)
ODA2(2)
ODA1(2)
ODA0(2)
0000
TRISA15(1) TRISA14(1)
Bit 10
Bit 9
TRISA10(1) TRISA9(1)
Bit 8
—
Bit 7
Bit 6
Bit 5
TRISA7(2) TRISA6(2) TRISA5(2)
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.
Implemented in 80-pin and 100-pin devices only.
Implemented in 100-pin devices only.
Bit 4
TRISA4(2) TRISA3(2) TRISA2(2) TRISA1(2) TRISA0(2)
C6FF
PIC24FJ128GA010 FAMILY
ADC1BUF9
ADC1BUFA
File Name
PORTB REGISTER MAP
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
TRISB13(1) TRISB12(1) TRISB11(1) TRISB10(1)
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISB
02C6
TRISB15
TRISB14
TRISB9
TRISB8
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
FFFF
PORTB
02C8
RB15
RB14
RB13(1)
RB12(1)
RB11(1)
RB10(1)
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx
LATB
02CA
LATB15
LATB14
LATB13(1)
LATB12(1)
LATB11(1)
LATB10(1)
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx
ODCB
06C6
ODB15
ODB14
ODB13(1)
ODB12(1)
ODB11(1)
ODB10(1)
ODB9
ODB8
ODB7
ODB6
ODB5
ODB4
ODB3
ODB2
ODB1
ODB0
0000
Legend:
Note 1:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices
Unimplemented when JTAG is enabled.
TABLE 4-18:
PORTC REGISTER MAP
File Name
Addr
TRISC
02CC
PORTC
02CE
RC15
RC14
RC13
LATC
02D0
LATC15
LATC14
ODCC
06CC
ODC15
ODC14
Legend:
Note 1:
2:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 2
—
F01E
—
xxxx
LATC1(1)
—
xxxx
ODC1(1)
—
0000
All
Resets
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 1
—
—
—
—
—
—
—
RC12
—
—
—
—
—
—
—
RC4(2)
RC3(1)
RC2(2)
RC1(1)
LATC13
LATC12
—
—
—
—
—
—
—
LATC4(2)
LATC3(1)
LATC2(2)
ODC13
ODC12
—
—
—
—
—
—
—
ODC4(2)
ODC3(1)
ODC2(2)
TRISC4(2) TRISC3(1) TRISC2(2) TRISC1(1)
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.
Implemented in 80-pin and 100-pin devices only.
Implemented in 100-pin devices only
TABLE 4-19:
PORTD REGISTER MAP
2005-2012 Microchip Technology Inc.
File Name
Addr
TRISD
02D2
PORTD
02D4
RD15(1)
RD14(1)
RD13(1)
RD12(1)
LATD
02D6
LATD15(1)
LATD14(1)
LATD13(1)
ODCD
06D2
ODD15(1)
ODD14(1)
ODD13(1)
Legend:
Note 1:
Bit 3
All
Resets
Bit 10
TRISC15 TRISC14 TRISC13 TRISC12
Bit 4
Bit 0
Bit 11
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISD11
TRISD10
TRISD9
TRISD8
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
FFFF
RD11
RD10
RD9
RD8
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx
LATD12(1)
LATD11
LATD10
LATD9
LATD8
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx
ODD12(1)
ODD11
ODD10
ODD9
ODD8
ODD7
ODD6
ODD5
ODD4
ODD3
ODD2
ODD1
ODD0
0000
TRISD15(1) TRISD14(1) TRISD13(1) TRISD12(1)
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.
Implemented in 80-pin and 100-pin devices only.
PIC24FJ128GA010 FAMILY
DS39747F-page 42
TABLE 4-17:
2005-2012 Microchip Technology Inc.
TABLE 4-20:
PORTE REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
TRISE
02D8
—
—
—
—
—
—
PORTE
02DA
—
—
—
—
—
—
RE9(1)
RE8(1)
LATE
02DC
—
—
—
—
—
—
LATE9(1)
—
(1)
ODCE
Legend:
Note 1:
06D8
—
—
—
—
—
Bit 9
Bit 8
All
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
03FF
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
xxxx
LATE8(1)
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
xxxx
ODE8(1)
ODE7
ODE6
ODE5
ODE4
ODE3
ODE2
ODE1
ODE0
0000
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISE9(1) TRISE8(1)
ODE9
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.
Implemented in 80-pin and 100-pin devices only.
TABLE 4-21:
PORTF REGISTER MAP
File Name
Addr
Bit 15
Bit 14
TRISF
02DE
—
—
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
TRISF13(1) TRISF12(1)
Bit 8
Bit 7
TRISF8(2) TRISF7(2)
—
—
—
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0
31FF
RF12(1)
—
—
—
RF8(2)
RF7(2)
RF6
RF5
RF4
RF3
RF2
RF1
RF0
xxxx
02E0
—
—
LATF
02E2
—
—
LATF13(1)
LATF12(1)
—
—
—
LATF8(2)
LATF7(2)
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
xxxx
ODCF
06DE
—
—
ODF13(1)
ODF12(1)
—
—
—
ODF8(2)
ODF7(2)
ODF6
ODF5
ODF4
ODF3
ODF2
ODF1
ODF0
0000
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 0
All
Resets
Legend:
Note 1:
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.
Implemented in 100-pin devices only.
Implemented in 80-pin and 100-pin devices only.
TABLE 4-22:
PORTG REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
TRISG14(1) TRISG13(1) TRISG12(1)
Bit 8
Bit 7
Bit 1
TRISG1(2) TRISG0(2)
TRISG
02E4
TRISG15
—
—
TRISG9
TRISG6
—
—
TRISG3
TRISG2
PORTG
02E6
RG15
RG14(1)
RG13(1)
RG12(1)
—
—
RG9
RG8
RG7
RG6
—
—
RG3
RG2
RG1(2)
RG0(2)
xxxx
LATG
02E8
LATG15
LATG14(1)
LATG13(1)
LATG12(1)
—
—
LATG9
LATG8
LATG7
LATG6
—
—
LATG3
LATG2
LATG1(2)
LATG0(2)
xxxx
ODCG
06E4
ODG15
ODG14(1)
ODG13(1)
ODG12(1)
—
—
ODG9
ODG8
ODG7
ODG6
—
—
ODG3
ODG2
ODG1(2)
ODG0(2)
0000
Legend:
Note 1:
2:
DS39747F-page 43
PADCFG1
Legend:
F3CF
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.
Implemented in 100-pin devices only.
Implemented in 80-pin and 100-pin devices only.
TABLE 4-23:
File Name
TRISG8 TRISG7
PAD CONFIGURATION MAP
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
02FC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RTSECSEL
PMPTTL
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.
PIC24FJ128GA010 FAMILY
PORTF
RF13(1)
File Name
PARALLEL MASTER/SLAVE PORT REGISTER MAP
Addr
Bit 15
PMCON
0600
PMPEN
—
PSIDL
PMMODE
0602
BUSY
IRQM1
IRQM0
CS2
CS1
PMADDR(1)
PMDOUT1(1)
0604
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN
INCM1
INCM0
MODE16
MODE1
MODE0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
CSF1
CSF0
ALP
CS2P
CS1P
BEP
WRSP
RDSP
WAITB1
WAITB0
WAITM3
WAITM2
WAITM1
WAITM0
WAITE1
WAITE0
Parallel Port Destination Address (Master modes)
0000
0000
Parallel Port Data Out Register 1 (Buffers 0 and 1)
0000
PMDOUT2
0606
Parallel Port Data Out Register 2 (Buffers 2 and 3)
0000
PMDIN1
0608
Parallel Port Data In Register 1 (Buffers 0 and 1)
0000
PMDIN2
060A
Parallel Port Data In Register 2 (Buffers 2 and 3)
PMAEN
060C
PTEN15
PTEN14
PTEN13
PTEN12
PTEN11
PTEN10
PTEN9
PTEN8
PTEN7
PTEN6
PTEN5
PTEN4
PTEN3
PTEN2
PTEN1
PTEN0
0000
PMSTAT
060E
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
008F
Legend:
Note 1:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PMADDR and PMDOUT1 share the same physical register. The register functions as PMDOUT1 only in Slave modes and as PMADDR only in Master modes.
TABLE 4-25:
File Name
Addr
ALRMVAL
0620
ALCFGRPT
0622
RTCVAL
0624
RCFGCAL(1)
0626
Legend:
Note 1:
REAL-TIME CLOCK AND CALENDAR REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
ALRMEN
CHIME
AMASK3
AMASK2
AMASK1
Bit 9
Bit 8
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ARPT5
ARPT4
ARPT3
ARPT2
ARPT1
ARPT0
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
Alarm Value Register Window Based on ALRMPTR
AMASK0 ALRMPTR1 ALRMPTR0
ARPT7
ARPT6
RTCEN
—
RTCWREN RTCSYNC HALFSEC
RTCOE
RTCPTR1
RTCPTR0
CAL7
All
Resets
xxxx
RTCC Value Register Window Based on RTCPTR
CAL6
0000
xxxx
0000
DUAL COMPARATOR REGISTER MAP
2005-2012 Microchip Technology Inc.
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
CMCON
0630
CMIDL
—
C2EVT
C1EVT
C2EN
C1EN
C2OUTEN
C1OUTEN
CVRCON
0632
—
—
—
—
—
—
—
—
Legend:
Bit 7
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCFGCAL register Reset value is dependent on the type of Reset.
TABLE 4-26:
File Name
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 7
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
C2INV
C1INV
C2NEG
C2POS
C1NEG
C1POS
0000
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
0000
Bit 6
Bit 5
C2OUT
C1OUT
CVREN
CVROE
PIC24FJ128GA010 FAMILY
DS39747F-page 44
TABLE 4-24:
2005-2012 Microchip Technology Inc.
TABLE 4-27:
File Name
CRC REGISTER MAP
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
CRCGO
PLEN3
PLEN2
PLEN1
PLEN0
0000
Bit 15
Bit 14
Bit 13
CRCCON
0640
—
—
CSIDL
CRCXOR
0642
CRC XOR Polynomial Register
CRCDAT
0644
CRC Data Input Register
0000
CRCWDAT
0646
CRC Result Register
0000
Legend:
Bit 12
Bit 5
Addr
VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-28:
SYSTEM REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RCON
0740
TRAPR
IOPUWR
—
—
—
—
CM
VREGS
EXTR
SWR
SWDTEN
WDTO
SLEEP
IDLE
BOR
POR
xxxx(1)
OSCCON
0742
—
COSC2
COSC1
COSC0
—
NOSC2
NOSC1
NOSC0
CLKLOCK
—
LOCK
—
CF
—
SOSCEN
OSWEN
xxxx(2)
CLKDIV
0744
ROI
DOZE2
DOZE1
DOZE0
DOZEN
RCDIV2
RCDIV1
RCDIV0
—
—
—
—
—
—
—
—
OSCTUN
0748
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values are dependent on the type of Reset.
OSCCON register Reset values are dependent on the FOSC Configuration bits and by type of Reset.
TABLE 4-29:
NVM REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
NVMCON
0760
WR
WREN
NVMKEY
0766
—
—
Legend:
Note 1:
Bit 12
Bit 11
Bit 10
Bit 9
WRERR
—
—
—
Bit 8
Bit 7
Bit 6
Bit 5
—
—
—
—
—
—
—
ERASE
—
—
—
Bit 4
—
Bit 3
Bit 2
Bit 1
Bit 0
NVMOP3 NVMOP2 NVMOP1 NVMOP0
NVMKEY
All
Resets
0000(1)
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-30:
PMD REGISTER MAP
DS39747F-page 45
File Name
Addr
Bit 15
Bit 14
Bit 13
PMD1
0770
T5MD
T4MD
T3MD
T2MD
T1MD
—
PMD2
0772
—
—
—
IC5MD
IC4MD
IC3MD
PMD3
0774
—
—
—
—
—
Legend:
0100
0000
Bit 12
Bit 11
Bit 10
Bit 9
Bit 0
All
Resets
—
—
ADC1MD
0000
OC3MD
OC2MD
OC1MD
0000
I2C2MD
—
0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
—
—
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
IC2MD
IC1MD
—
—
—
OC5MD
OC4MD
PMPMD
CRCPMD
—
—
—
—
—
CMPMD RTCCMD
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 1
Bit 8
Bit 2
PIC24FJ128GA010 FAMILY
Legend:
Note 1:
2:
TUN
PIC24FJ128GA010 FAMILY
4.2.5
SOFTWARE STACK
4.3
In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software
Stack Pointer. The pointer always points to the first
available free word and grows from lower to higher
addresses. It predecrements for stack pops and postincrements for stack pushes, as shown in Figure 4-4.
Note that for a PC push during any CALL instruction,
the MSB of the PC is zero-extended before the push,
ensuring that the MSB is always clear.
Note:
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM is forced to ‘0’
because all stack operations must be word-aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the
Stack Pointer (W15) and the SPLIM register are equal
and a push operation is performed, a stack error trap
will not occur. The stack error trap will occur on a
subsequent push operation. Thus, for example, if it is
desirable to cause a stack error trap when the stack
grows beyond address, 2000h, in RAM, initialize the
SPLIM with the value, 1FFEh.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0800h. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-4:
Stack Grows Towards
Higher Address
0000h
CALL STACK FRAME
15
0
PC
000000000 PC
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
DS39747F-page 46
Interfacing Program and Data
Memory Spaces
The PIC24F architecture uses a 24-bit wide program
space and 16-bit wide data space. The architecture is
also a modified Harvard scheme, meaning that data
can also be present in the program space. To use this
data successfully, it must be accessed in a way that
preserves the alignment of information in both spaces.
Aside from normal execution, the PIC24F architecture
provides two methods by which program space can be
accessed during operation:
• Using table instructions to access individual bytes
or words anywhere in the program space
• Remapping a portion of the program space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This makes the
method ideal for accessing data tables that need to be
updated from time to time. It also allows access to all
bytes of the program word. The remapping method
allows an application to access a large block of data on
a read-only basis, which is ideal for look ups from a
large table of static data. It can only access the least
significant word of the program word.
4.3.1
ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the Most Significant bit of TBLPAG is used
to determine if the operation occurs in the user memory
(TBLPAG = 0) or the configuration memory
(TBLPAG = 1).
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the Most
Significant bit of the EA is ‘1’, PSVPAG is concatenated
with the lower 15 bits of the EA to form a 23-bit program
space address. Unlike table operations, this limits
remapping operations strictly to the user memory area.
Table 4-31 and Figure 4-5 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P refers to a program
space word, whereas D refers to a data space
word.
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 4-31:
PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
Instruction Access
(Code Execution)
User
TBLRD/TBLWT
(Byte/Word Read/Write)
User
TBLPAG
Data EA
0xxx xxxx
xxxx xxxx xxxx xxxx
Configuration
TBLPAG
Data EA
1xxx xxxx
xxxx xxxx xxxx xxxx
0
0xx xxxx xxxx xxxx xxxx xxx0
Program Space Visibility
(Block Remap/Read)
Note 1:
PC
0
User
0
PSVPAG
Data EA(1)
0
xxxx xxxx
xxx xxxx xxxx xxxx
Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG.
FIGURE 4-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
0
0
23 Bits
EA
Table Operations(2)
1/0
1/0
TBLPAG
8 Bits
16 Bits
24 Bits
Select
Program Space
(Remapping)
Visibility(1)
0
EA
1
0
PSVPAG
8 Bits
15 Bits
23 Bits
User/Configuration
Space Select
Byte Select
Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of
data in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted in the
configuration memory space.
2005-2012 Microchip Technology Inc.
DS39747F-page 47
PIC24FJ128GA010 FAMILY
4.3.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space, without going
through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits
of a program space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit,
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDH and TBLWTH access the space
which contains the upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
1.
TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space
location (P) to a data address (D).
In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when byte select is ‘1’; the lower byte
is selected when it is ‘0’.
FIGURE 4-6:
2.
TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
(P) to a data address. Note that
D, the “phantom byte”, will always be ‘0’.
In Byte mode, it maps the upper or lower byte of
the program word to D of the data
address, as above. Note that the data will
always be ‘0’ when the upper “phantom” byte is
selected (byte select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user and configuration spaces. When TBLPAG = 0, the Table Page
is located in the user memory space. When
TBLPAG = 1, the page is located in configuration
space.
Note:
Only table read operations will execute in
the configuration memory space, and only
then, in implemented areas such as the
Device ID. Table write operations are not
allowed.
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
Data EA
23
15
0
000000h
23
16
8
0
00000000
020000h
030000h
00000000
00000000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn = 0)
TBLRDL.B (Wn = 1)
TBLRDL.B (Wn = 0)
TBLRDL.W
800000h
DS39747F-page 48
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
4.3.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This provides transparent access of stored constant
data from the data space without the need to use
special instructions (i.e., TBLRDL/H).
Program space access through the data space occurs
if the Most Significant bit of the data space EA is ‘1’ and
Program Space Visibility is enabled by setting the PSV
bit in the Core Control register (CORCON). The
location of the program memory space to be mapped
into the data space is determined by the Program
Space Visibility Page register (PSVPAG). This 8-bit
register defines any one of 256 possible pages of
16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory
address, with the 15 bits of the EA functioning as the
lower bits. Note that by incrementing the PC by 2 for
each program memory word, the lower 15 bits of data
space addresses directly map to the lower 15 bits in the
corresponding program space addresses.
Data reads to this area add an additional cycle to the
instruction being executed, since two program memory
fetches are required.
Although each data space address, 8000h and higher,
maps directly into a corresponding program memory
address (see Figure 4-7), only the lower 16 bits of the
FIGURE 4-7:
24-bit program word are used to contain the data. The
upper 8 bits of any program space locations used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
PSV access is temporarily disabled during
table reads/writes.
Note:
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions will
require one instruction cycle in addition to the specified
execution time. All other instructions will require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV which are executed inside
a REPEAT loop, there will be some instances that
require two instruction cycles in addition to the
specified execution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction accessing data, using PSV, to execute in a
single cycle.
PROGRAM SPACE VISIBILITY OPERATION
When CORCON = 1 and EA = 1:
Program Space
PSVPAG
02
23
15
Data Space
0
000000h
0000h
Data EA
010000h
018000h
The data in the page
designated by PSVPAG is mapped into
the upper half of the
data memory
space....
8000h
PSV Area
FFFFh
800000h
2005-2012 Microchip Technology Inc.
...while the lower 15
bits of the EA specify
an exact address
within the PSV area.
This corresponds
exactly to the same
lower 15 bits of the
actual program space
address.
DS39747F-page 49
PIC24FJ128GA010 FAMILY
NOTES:
DS39747F-page 50
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
5.0
controller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
FLASH PROGRAM MEMORY
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 4. “Program
Memory” (DS39715) in the “PIC24F
Family Reference Manual” for more
information.
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
may write program memory data in blocks of 64 instructions (192 bytes) at a time, and erase program memory
in blocks of 512 instructions (1536 bytes) at a time.
5.1
The PIC24FJ128GA010 family of devices contains
internal Flash program memory for storing and executing application code. The memory is readable, writable
and erasable during normal operation over the
specified VDD range.
Regardless of the method used, all programming of
Flash memory is done with the table read and table
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using the TBLPAG bits and the Effective
Address (EA) from a W register specified in the table
instruction, as shown in Figure 5-1.
Flash memory can be programmed in four ways:
1.
2.
3.
4.
In-Circuit Serial Programming™ (ICSP™)
Run-Time Self-Programming (RTSP)
JTAG
Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
The TBLRDL and the TBLWTL instructions are used to
read or write to bits of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
ICSP allows a PIC24FJ128GA010 family device to be
serially programmed while in the end application circuit.
This is simply done with two lines for Programming
Clock and Programming Data (which are named PGCx
and PGDx, respectively), and three other lines for
power (VDD), ground (VSS) and Master Clear (MCLR).
This allows customers to manufacture boards with
unprogrammed devices and then program the micro-
FIGURE 5-1:
Table Instructions and Flash
Programming
The TBLRDH and TBLWTH instructions are used to read
or write to bits of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
ADDRESSING FOR TABLE REGISTERS
24 Bits
Using
Program
Counter
Program Counter
0
0
Working Reg EA
Using
Table
Instruction
User/Configuration
Space Select
2005-2012 Microchip Technology Inc.
1/0
TBLPAG Reg
8 Bits
16 Bits
24-Bit EA
Byte
Select
DS39747F-page 51
PIC24FJ128GA010 FAMILY
5.2
RTSP Operation
The PIC24F Flash program memory array is organized
into rows of 64 instructions or 192 bytes. RTSP allows
the user to erase blocks of eight rows (512 instructions)
at a time and to program one row at a time. It is also
possible to program single words.
The 8-row erase blocks and single row write blocks are
edge-aligned, from the beginning of program memory,
on boundaries of 1536 bytes and 192 bytes,
respectively.
When data is written to program memory using TBLWT
instructions, the data is not written directly to memory.
Instead, data written using table writes is stored in
holding latches until the programming sequence is
executed.
Any number of TBLWT instructions can be executed
and a write will be successfully performed. However,
64 TBLWT instructions are required to write the full row
of memory.
To ensure that no data is corrupted during a write, any
unused addresses should be programmed with
FFFFFFh. This is because the holding latches reset to
an unknown state, so if the addresses are left in the
Reset state, they may overwrite the locations on rows
which were not rewritten.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register.
Data can be loaded in any order and the holding registers can be written to multiple times before performing
a write operation. Subsequent writes, however, will
wipe out any previous writes.
Note:
Writing to a location multiple times without
erasing is not recommended.
All of the table write operations are single-word writes
(2 instruction cycles), because only the buffers are
written. A programming cycle is required for
programming each row.
5.3
5.4
Enhanced In-Circuit Serial
Programming
Enhanced In-Circuit Serial Programming uses an onboard bootloader, known as the program executive, to
manage the programming process. Using an SPI data
frame format, the program executive can erase,
program and verify program memory. See the device
programming specification for more information on
Enhanced ICSP
5.5
Control Registers
There are two SFRs used to read and write the
program Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 55h and AAh to the
NVMKEY register. Refer to Section 5.6 “Programming
Operations” for further details.
5.6
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. During a programming or an erase operation,
the processor stalls (Waits) until the operation is
finished. Setting the WR bit (NVMCON) starts the
operation and the WR bit is automatically cleared when
the operation is finished.
Configuration Word values are stored in the last two
locations of program memory. Performing a page erase
operation on the last page of program memory clears
these values and enables code protection. As a result,
avoid performing page erase operations on the last
page of program memory.
JTAG Operation
The PIC24F family supports JTAG programming and
boundary scan. Boundary scan can improve the manufacturing process by verifying pin to PCB connectivity.
Programming can be performed with industry standard
JTAG programmers supporting Serial Vector Format
(SVF).
DS39747F-page 52
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
REGISTER 5-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0(1)
R/W-0(1)
R/W-0(1)
U-0
U-0
U-0
U-0
U-0
WR
WREN
WRERR
—
—
—
—
—
bit 15
bit 8
R/W-0(1)
U-0
—
U-0
ERASE
—
U-0
R/W-0(1)
R/W-0(1)
R/W-0(1)
R/W-0(1)
—
NVMOP3(2)
NVMOP2(2)
NVMOP1(2)
NVMOP0(2)
bit 7
bit 0
Legend:
SO = Settable Only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete.
0 = Program or erase operation is complete and inactive
bit 14
WREN: Write Enable bit
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
bit 13
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically
on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12-7
Unimplemented: Read as ‘0’
bit 6
ERASE: Erase/Program Enable bit
1 = Performs the erase operation specified by NVMOP on the next WR command
0 = Performs the program operation specified by NVMOP on the next WR command
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
NVMOP: NVM Operation Select bits(2)
1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(3)
0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1)
0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)
0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)
Note 1:
2:
3:
These bits can only be reset on a POR.
All other combinations of NVMOP are unimplemented.
Available in ICSP™ mode only. Refer to the device programming specifications.
2005-2012 Microchip Technology Inc.
DS39747F-page 53
PIC24FJ128GA010 FAMILY
5.6.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
4.
5.
The user can program one row of program Flash memory
at a time. To do this, it is necessary to erase the 8-row
erase block containing the desired row. The general
process is:
1.
2.
3.
Read eight rows of program memory
(512 instructions) and store in data RAM.
Update the program data in RAM with the
desired new data.
Erase the block (see Example 5-1):
a) Set the NVMOP bits (NVMCON) to
‘0010’ to configure for block erase. Set the
ERASE (NVMCON) and WREN
(NVMCON) bits.
b) Write the starting address of the block to be
erased into the TBLPAG and W registers.
c) Write 55h to NVMKEY.
d) Write AAh to NVMKEY.
e) Set the WR bit (NVMCON). The erase
cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
EXAMPLE 5-1:
DS39747F-page 54
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 5-3.
ERASING A PROGRAM MEMORY BLOCK
; Set up NVMCON for block erase operation
MOV
#0x4042, W0
MOV
W0, NVMCON
; Init pointer to row to be ERASED
MOV
#tblpage(PROG_ADDR), W0
MOV
W0, TBLPAG
MOV
#tbloffset(PROG_ADDR), W0
TBLWTL W0, [W0]
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
6.
Write the first 64 instructions from data RAM into
the program memory buffers (see Example 5-2).
Write the program block to Flash memory:
a) Set the NVMOP bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
b) Write 55h to NVMKEY.
c) Write AAh to NVMKEY.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash
memory is done, the WR bit is cleared
automatically.
Repeat Steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash
memory.
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
;
; Initialize NVMCON
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PM Page Boundary SFR
Initialize in-page EA[15:0] pointer
Set base address of erase block
Block all interrupts with priority 7 and 16-deep otherwise. The data for which the CRC is to be calculated
must first be written into the FIFO. The smallest data
element that can be written into the FIFO is one byte.
For example, if PLEN = 5, then the size of the data is
PLEN + 1 = 6. The data must be written as follows:
data[5:0] = crc_input[5:0]
data[7:6] = ‘bxx
Once data is written into the CRCWDAT MSb (as
defined by PLEN), the value of the VWORD bits
(CRCCON) increment by one. The serial shifter
starts shifting data into the CRC engine when
CRCGO = 1 and VWORD > 0. When the MSb is
shifted out, VWORD decrements by one. The serial
shifter continues shifting until the VWORD reaches 0.
Therefore, for a given value of PLEN, it will take
(PLEN + 1)/2 x VWORD number of clock cycles
to complete the CRC calculations.
When VWORD reaches 8 (or 16), the CRCFUL bit will
be set. When VWORD reaches 0, the CRCMPT bit will
be set.
DS39747F-page 176
To continually feed data into the CRC engine, the recommended mode of operation is to initially “prime” the
FIFO with a sufficient number of words, so no interrupt
is generated before the next word can be written. Once
that is done, start the CRC by setting the CRCGO bit to
‘1’. From that point onward, the VWORD bits should be
polled. If they read less than 8 or 16, another word can
be written into the FIFO.
To empty words already written into a FIFO, the
CRCGO bit must be set to ‘1’ and the CRC shifter
allowed to run until the CRCMPT bit is set.
Also, to get the correct CRC reading, it will be
necessary to wait for the CRCMPT bit to go high before
reading the CRCWDAT register.
If a word is written when the CRCFUL bit is set, the
VWORD Pointer will roll over to 0. The hardware will
then behave as if the FIFO is empty. However, the condition to generate an interrupt will not be met; therefore,
no interrupt will be generated (see Section 20.3.2
“Interrupt Operation”).
At least one instruction cycle must pass after a write to
CRCWDAT before a read of the VWORD bits is done.
20.3.2
INTERRUPT OPERATION
When VWORD make a transition from a value of
‘1’ to ‘0’, an interrupt will be generated.
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
REGISTER 20-1:
CRCCON: CRC CONTROL REGISTER
U-0
U-0
R/W-0
R-0
R-0
R-0
R-0
R-0
—
—
CSIDL
VWORD4
VWORD3
VWORD2
VWORD1
VWORD0
bit 15
bit 8
R-0
R-1
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CRCFUL
CRCMPT
—
CRCGO
PLEN3
PLEN2
PLEN1
PLEN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13
CSIDL: CRC Stop in Idle Mode bit
1 = Discontinues module operation when the device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-8
VWORD: Pointer Value bits
Indicates the number of valid words in the FIFO. It has a maximum value of 8 when PLEN > 7
or 16 when PLEN 7.
bit 7
CRCFUL: FIFO Full bit
1 = FIFO is full
0 = FIFO is not full
bit 6
CRCMPT: FIFO Empty bit
1 = FIFO is empty
0 = FIFO is not empty
bit 5
Unimplemented: Read as ‘0’
bit 4
CRCGO: Start CRC bit
1 = Starts CRC serial shifter
0 = CRC serial shifter is turned off
bit 3-0
PLEN: Polynomial Length bits
Denotes the length of the polynomial to be generated minus 1.
20.4
20.4.1
Operation in Power Save Modes
SLEEP MODE
If Sleep mode is entered while the module is operating,
the module will be suspended in its current state until
clock execution resumes.
2005-2012 Microchip Technology Inc.
20.4.2
IDLE MODE
To continue full module operation in Idle mode, the
CSIDL bit must be cleared prior to entry into the mode.
If CSIDL = 1, the module will behave the same way as
it does in Sleep mode. Pending interrupt events will be
passed on, even though the module clocks are not
available.
DS39747F-page 177
PIC24FJ128GA010 FAMILY
NOTES:
DS39747F-page 178
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
21.0
Note:
10-BIT HIGH-SPEED A/D
CONVERTER
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 17. “10-Bit A/D
Converter” (DS39705) in the “PIC24F
Family Reference Manual” for more
information.
A block diagram of the A/D Converter is shown in
Figure 21-1.
To perform an A/D conversion:
1.
The 10-bit A/D Converter has the following key
features:
•
•
•
•
•
•
•
•
•
•
Successive Approximation (SAR) conversion
Conversion speeds of up to 500 ksps
Up to 16 analog input pins
External voltage reference input pins
Automatic Channel Scan mode
Selectable conversion trigger source
16-word conversion result buffer
Selectable Buffer Fill modes
Four result alignment options
Operation during CPU Sleep and Idle modes
Depending on the particular device pinout, the 10-bit
A/D Converter can have up to 16 analog input pins,
designated AN0 through AN15. In addition, there are
two analog input pins for external voltage reference
connections. These voltage reference inputs may be
shared with other analog input pins. The actual number
of analog input pins and external voltage reference
input configuration will depend on the device. Refer to
the specific device data sheet for further details.
2005-2012 Microchip Technology Inc.
2.
Configure the A/D module:
a) Select the port pins as analog inputs
(AD1PCFG).
b) Select a voltage reference source to match
the expected range on the analog inputs
(AD1CON2).
c) Select the analog conversion clock to match
the desired data rate with the processor clock
(AD1CON3).
d) Select the appropriate sample/conversion sequence (AD1CON1 and
AD1CON3).
e) Select how conversion results are
presented in the buffer (AD1CON1).
f) Select the interrupt rate (AD1CON2).
g) Turn on the A/D module (AD1CON1).
Configure the A/D interrupt (if required):
a) Clear the AD1IF bit.
b) Select the A/D interrupt priority.
Note:
A/D results should be read with the ADON
bit = 1. If the A/D is disabled before
reading the buffer, it is possible to lose
data.
DS39747F-page 179
PIC24FJ128GA010 FAMILY
Figure 21-1:
10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM
Internal Data Bus
AVSS
VREF+
VR Select
AVDD
16
VR+
VR-
Comparator
VREF-
VINH
VINL
AN0
AN1
VRS/H
VINH
10-Bit SAR
AN4
MUX A
AN2
AN3
AN5
VINL
ADC1BUF0:
ADC1BUFF
AN7
AN8
AD1CON1
AD1CON2
AD1CON3
AD1CHS
AN12
MUX B
AN9
AN11
Conversion Logic
Data Formatting
AN6
AN10
VR+
DAC
VINH
AD1PCFG
AD1CSSL
VINL
AN13
AN14
AN15
DS39747F-page 180
Sample Control
Control Logic
Conversion Control
Input MUX Control
Pin Config. Control
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
REGISTER 21-1:
AD1CON1: A/D CONTROL REGISTER 1
R/W-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
ADON(1)
—
ADSIDL
—
—
—
FORM1
FORM0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0, HCS
R/C-0, HCS
SSRC2
SSRC1
SSRC0
—
—
ASAM
SAMP
DONE
bit 7
bit 0
Legend:
C = Clearable bit
HCS = Hardware Clearable/Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ADON: A/D Operating Mode bit(1)
1 = A/D Converter module is operating
0 = A/D Converter is off
bit 14
Unimplemented: Read as ‘0’
bit 13
ADSIDL: Stop in Idle Mode bit
1 = Discontinues module operation when the device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-10
Unimplemented: Read as ‘0’
bit 9-8
FORM: Data Output Format bits
11 = Signed fractional (sddd dddd dd00 0000)
10 = Fractional (dddd dddd dd00 0000)
01 = Signed integer (ssss sssd dddd dddd)
00 = Integer (0000 00dd dddd dddd)
bit 7-5
SSRC: Conversion Trigger Source Select bits
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = Reserved
10x = Reserved
011 = Reserved
010 = Timer3 compare ends sampling and starts conversion
001 = Active transition on the INT0 pin ends sampling and starts conversion
000 = Clearing the SAMP bit ends sampling and starts conversion
bit 4-3
Unimplemented: Read as ‘0’
bit 2
ASAM: A/D Sample Auto-Start bit
1 = Sampling begins immediately after the last conversion completes; SAMP bit is auto-set
0 = Sampling begins when the SAMP bit is set
bit 1
SAMP: A/D Sample Enable bit
1 = A/D Sample-and-Hold amplifier is sampling input
0 = A/D Sample-and-Hold amplifier is holding
bit 0
DONE: A/D Conversion Status bit
1 = A/D conversion is done
0 = A/D conversion is NOT done
Note 1:
The values of the ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out
the conversion values from the buffer before disabling the module.
2005-2012 Microchip Technology Inc.
DS39747F-page 181
PIC24FJ128GA010 FAMILY
REGISTER 21-2:
AD1CON2: A/D CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
U-0
U-0
VCFG2
VCFG1
VCFG0
r
—
CSCNA
—
—
bit 15
bit 8
R-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUFS
—
SMPI3
SMPI2
SMPI1
SMPI0
BUFM
ALTS
bit 7
bit 0
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
x = Bit is unknown
VCFG: Voltage Reference Configuration bits:
VCFG
VR+
VR-
000
AVDD
AVSS
001
External VREF+ pin
AVSS
010
AVDD
External VREF- pin
011
External VREF+ pin
External VREF- pin
1xx
AVDD
AVSS
bit 12
Reserved
bit 11
Unimplemented: Read as ‘0’
bit 10
CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexor Setting bit
1 = Scan inputs
0 = Do not scan inputs
bit 9-8
Unimplemented: Read as ‘0’
bit 7
BUFS: Buffer Fill Status bit (valid only when BUFM = 1)
1 = A/D is currently filling Buffer 08-0F, user should access data in 00-07
0 = A/D is currently filling Buffer 00-07, user should access data in 08-0F
bit 6
Unimplemented: Read as ‘0’
bit 5-2
SMPI: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
.....
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
bit 1
BUFM: Buffer Mode Select bit
1 = Buffer configured as two 8-word buffers (ADC1BUFx and ADC1BUFx)
0 = Buffer configured as one 16-word buffer (ADC1BUFx)
bit 0
ALTS: Alternate Input Sample Mode Select bit
1 = Uses MUX A input multiplexor settings for the first sample, then alternates between the MUX B and
MUX A input multiplexor settings for all subsequent samples
0 = Always uses MUX A input multiplexor settings
DS39747F-page 182
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
REGISTER 21-3:
AD1CON3: A/D CONTROL REGISTER 3
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADRC
—
—
SAMC4
SAMC3
SAMC2
SAMC1
SAMC0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCS7
ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
ADRC: A/D Conversion Clock Source bit
1 = A/D internal RC clock
0 = Clock is derived from the system clock
bit 14-13
Unimplemented: Read as ‘0’
bit 12-8
SAMC: Auto-Sample Time bits
11111 = 31 TAD
x = Bit is unknown
·····
00001 = 1 TAD
00000 = 0 TAD (not recommended)
bit 7-0
ADCS A/D Conversion Clock Select bits
11111111
····· = Reserved
01000000
00111111 = 64 * TCY
·····
00000001 = 2 * TCY
00000000 = TCY
2005-2012 Microchip Technology Inc.
DS39747F-page 183
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REGISTER 21-4:
AD1CHS: A/D INPUT SELECT REGISTER
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0NB
—
—
—
CH0SB3
CH0SB2
CH0SB1
CH0SB0
bit 15
bit 8
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0NA
—
—
—
CH0SA3
CH0SA2
CH0SA1
CH0SA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CH0NB: Channel 0 Negative Input Select for MUX B Multiplexor Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VR-
bit 14-12
Unimplemented: Read as ‘0’
bit 11-8
CH0SB: Channel 0 Positive Input Select for MUX B Multiplexor Setting bits
1111 = Channel 0 positive input is AN15
1110 = Channel 0 positive input is AN14
·····
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
bit 7
CH0NA: Channel 0 Negative Input Select for MUX A Multiplexor Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VR-
bit 6-4
Unimplemented: Read as ‘0’
bit 3-0
CH0SA: Channel 0 Positive Input Select for MUX A Multiplexor Setting bits
1111 = Channel 0 positive input is AN15
1110 = Channel 0 positive input is AN14
·····
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
DS39747F-page 184
2005-2012 Microchip Technology Inc.
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REGISTER 21-5:
AD1PCFG: A/D PORT CONFIGURATION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG15
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
PCFG: Analog Input Pin Configuration Control bits
1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read is enabled
0 = Pin configured in Analog mode; I/O port read is disabled, A/D samples pin voltage
REGISTER 21-6:
AD1CSSL: A/D INPUT SCAN SELECT REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSSL15
CSSL14
CSSL13
CSSL12
CSSL11
CSSL10
CSSL9
CSSL8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSSL7
CSSL6
CSSL5
CSSL4
CSSL3
CSSL2
CSSL1
CSSL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
CSSL: A/D Input Pin Scan Selection bits
1 = Corresponding analog channel is selected for input scan
0 = Analog channel is omitted from input scan
2005-2012 Microchip Technology Inc.
DS39747F-page 185
PIC24FJ128GA010 FAMILY
A/D CONVERSION CLOCK PERIOD(1)
EQUATION 21-1:
TAD = TCY (ADCS + 1)
TAD
–1
ADCS =
TCY
Note 1:
Based on TCY = TOSC * 2; Doze mode and PLL are disabled.
FIGURE 21-2:
10-BIT A/D CONVERTER ANALOG INPUT MODEL
VDD
Rs
VA
RIC 250
VT = 0.6V
ANx
CPIN
6-11 pF
(Typical)
VT = 0.6V
Sampling
Switch
RSS 5 k(Typical)
RSS
ILEAKAGE
500 nA
CHOLD
= DAC Capacitance
= 4.4 pF (Typical)
VSS
Legend: CPIN
= Input Capacitance
= Threshold Voltage
VT
ILEAKAGE = Leakage Current at the pin due to
various junctions
= Interconnect Resistance
RIC
= Sampling Switch Resistance
RSS
= Sample/Hold Capacitance (from DAC)
CHOLD
Note: CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs 5 k.
DS39747F-page 186
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
FIGURE 21-3:
A/D TRANSFER FUNCTION
Output Code
(Binary (Decimal))
11 1111 1111 (1023)
11 1111 1110 (1022)
10 0000 0011 (515)
10 0000 0010 (514)
10 0000 0001 (513)
10 0000 0000 (512)
01 1111 1111 (511)
01 1111 1110 (510)
01 1111 1101 (509)
00 0000 0001 (1)
2005-2012 Microchip Technology Inc.
(VINH – VINL)
VR+
1024
1023*(VR+ – VR-)
VR- +
1024
VR- +
512*(VR+ – VR-)
1024
VR- +
Voltage Level
VR+ – VR-
0
VR-
00 0000 0000 (0)
DS39747F-page 187
PIC24FJ128GA010 FAMILY
NOTES:
DS39747F-page 188
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
22.0
COMPARATOR MODULE
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 19. “Comparator
Module” (DS39710) in the “PIC24F Family
Reference Manual” for more information.
FIGURE 22-1:
The analog comparator module contains two
comparators that can be configured in a variety of
ways. The inputs can be selected from the analog
inputs, multiplexed with I/O pins, as well as the on-chip
voltage reference. Block diagrams of the various
comparator configurations are shown in Figure 22-1.
COMPARATOR I/O OPERATING MODES
C1NEG
C1IN+
C1IN-
C1EN
CMCON
C1INV
VINC1OUT
C1POS
C1IN+
CVREF
C1
VIN+
C2NEG
C2IN+
C2IN-
C1OUTEN
C2EN
CMCON
C2INV
VINC2OUT
C2POS
C2IN+
CVREF
2005-2012 Microchip Technology Inc.
C2
VIN+
C2OUTEN
DS39747F-page 189
PIC24FJ128GA010 FAMILY
REGISTER 22-1:
CMCON: COMPARATOR CONTROL REGISTER
R/W-0
U-0
R/C-0
R/C-0
R/W-0
R/W-0
R/W-0
R/W-0
CMIDL
—
C2EVT
C1EVT
C2EN
C1EN
C2OUTEN
C1OUTEN
bit 15
bit 8
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
C2OUT
C1OUT
C2INV
C1INV
C2NEG
C2POS
C1NEG
C1POS
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CMIDL: Stop in Idle Mode bit
1 = When the device enters Idle mode, the module does not generate interrupts; module is still enabled
0 = Continues normal module operation in Idle mode
bit 14
Unimplemented: Read as ‘0’
bit 13
C2EVT: Comparator 2 Event bit
1 = Comparator output changed states
0 = Comparator output did not change states
bit 12
C1EVT: Comparator 1 Event bit
1 = Comparator output changed states
0 = Comparator output did not change states
bit 11
C2EN: Comparator 2 Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
bit 10
C1EN: Comparator 1 Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
bit 9
C2OUTEN: Comparator 2 Output Enable bit
1 = Comparator output is driven on the output pad
0 = Comparator output is not driven on the output pad
bit 8
C1OUTEN: Comparator 1 Output Enable bit
1 = Comparator output is driven on the output pad
0 = Comparator output is not driven on the output pad
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1:
0 = C2 VIN+ > C2 VIN1 = C2 VIN+ < C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1:
0 = C1 VIN+ > C1 VIN1 = C1 VIN+ < C1 VIN-
DS39747F-page 190
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
REGISTER 22-1:
CMCON: COMPARATOR CONTROL REGISTER (CONTINUED)
bit 5
C2INV: Comparator 2 Output Inversion bit
1 = C2 output is inverted
0 = C2 output is not inverted
bit 4
C1INV: Comparator 1 Output Inversion bit
1 = C1 output is inverted
0 = C1 output is not inverted
bit 3
C2NEG: Comparator 2 Negative Input Configure bit
1 = C2IN+ is connected to VIN0 = C2IN- is connected to VINSee Figure 22-1 for the Comparator modes.
bit 2
C2POS: Comparator 2 Positive Input Configure bit
1 = C2IN+ is connected to VIN+
0 = CVREF is connected to VIN+
See Figure 22-1 for the Comparator modes.
bit 1
C1NEG: Comparator 1 Negative Input Configure bit
1 = C1IN+ is connected to VIN0 = C1IN- is connected to VINSee Figure 22-1 for the Comparator modes.
bit 0
C1POS: Comparator 1 Positive Input Configure bit
1 = C1IN is connected to VIN+
0 = CVREF is connected to VIN+
See Figure 22-1 for the Comparator modes.
2005-2012 Microchip Technology Inc.
DS39747F-page 191
PIC24FJ128GA010 FAMILY
NOTES:
DS39747F-page 192
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
23.0
Note:
23.1
voltage, each with 16 distinct levels. The range to be
used is selected by the CVRR bit (CVRCON). The
primary difference between the ranges is the size of the
steps selected by the CVREF Selection bits
(CVR), with one range offering finer resolution.
COMPARATOR VOLTAGE
REFERENCE
This data sheet summarizes features of
PIC24F group of devices and is not
intended to be a comprehensive reference
source. Refer to Section 20. “Comparator
Voltage Reference Module” (DS39709)
in the “PIC24F Family Reference Manual”
for more information.
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF-. The voltage source is selected by the CVRSS
bit (CVRCON).
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output.
Configuring the Comparator
Voltage Reference
The voltage reference module is controlled through the
CVRCON register (Register 23-1). The comparator
voltage reference provides two ranges of output
FIGURE 23-1:
CVRR: Comparator VREF Range Selection bit 1 = 0
to 0.625 CVRSRC, with CVRSRC/24 step size.
0 = 0.25 CVRSRC to 0.72 CVRSRC, with CVRSRC/32
step size
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+
AVDD
CVRSS = 1
8R
CVRSS = 0
CVR
R
CVREN
R
R
16-to-1 MUX
R
16 Steps
R
CVREF
R
R
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
AVSS
2005-2012 Microchip Technology Inc.
DS39747F-page 193
PIC24FJ128GA010 FAMILY
REGISTER 23-1:
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7
CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit is powered on
0 = CVREF circuit is powered down
bit 6
CVROE: Comparator VREF Output Enable bit
1 = CVREF voltage level is output on the CVREF pin
0 = CVREF voltage level is disconnected from the CVREF pin
bit 5
CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.625 CVRSRC, with CVRSRC/24 step size
0 = 0.25 CVRSRC to 0.72 CVRSRC, with CVRSRC/32 step size
bit 4
CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source: CVRSRC = VREF+ – VREF0 = Comparator reference source: CVRSRC = AVDD – AVSS
bit 3-0
CVR: Comparator VREF Value Selection 0 CVR 15 bits
When CVRR = 1:
CVREF = (CVR/ 24) (CVRSRC)
When CVRR = 0:
CVREF = 1/4 (CVRSRC) + (CVR/32) (CVRSRC)
DS39747F-page 194
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
24.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference source. Refer to Section 32.
“High-Level
Device
Integration”
(DS39719) in the “PIC24F Family
Reference Manual” for more information.
PIC24FJ128GA010 devices include several features
intended to maximize application flexibility and reliability, and minimize cost through elimination of external
components. These are:
•
•
•
•
•
•
Flexible Configuration
Watchdog Timer (WDT)
Code Protection
JTAG Boundary Scan Interface
In-Circuit Serial Programming™ (ICSP™)
In-Circuit Emulation
24.1
24.1.1
CONSIDERATIONS FOR
CONFIGURING PIC24FJ128GA010
FAMILY DEVICES
In PIC24FJ128GA010 family devices, the configuration
bytes are implemented as volatile memory. This means
that configuration data must be programmed each time
the device is powered up. Configuration data is stored
in the two words at the top of the on-chip program
memory space, known as the Flash Configuration
Words. Their specific locations are shown in
Table 24-1. These are packed representations of the
actual device Configuration bits, whose actual
locations are distributed among five locations in configuration space. The configuration data is automatically
loaded from the Flash Configuration Words to the
proper Configuration registers during device Resets.
Note:
Configuration data is reloaded on all types
of device Resets.
TABLE 24-1:
Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped, starting
at program memory location, F80000h. A complete list
is shown in Table 24-1. A detailed explanation of the
various bit functions is provided in Register 24-1
through Register 24-4.
Note that address, F80000h, is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (800000h-FFFFFFh), which can only be
accessed using table reads and table writes.
FLASH CONFIGURATION
WORD LOCATIONS
Device
Configuration Word
Addresses
1
2
PIC24FJ64GA
00ABFEh
00ABFCh
PIC24FJ96GA
00FFFEh
00FFFCh
PIC24FJ128GA
0157FEh
0157FCh
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
The Configuration bits are reloaded from the Flash
Configuration Word on any device Reset.
The upper byte of both Flash Configuration Words in
program memory should always be ‘1111 1111’. This
makes them appear to be NOP instructions in the
remote event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
2005-2012 Microchip Technology Inc.
DS39747F-page 195
PIC24FJ128GA010 FAMILY
REGISTER 24-1:
FLASH CONFIGURATION WORD 1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
r-x
r
bit 16
R/PO-1
(1)
JTAGEN
R/PO-1
R/PO-1
R/PO-1
r-1
U-1
R/PO-1
GCP
GWRP
DEBUG
r
—
ICS
bit 15
bit 8
R/PO-1
R/PO-1
U-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
FWDTEN
WINDIS
—
FWPSA
WDTPS3
WDTPS2
WDTPS1
WDTPS0
bit 7
bit 0
Legend:
x = Bit is unknown
r = Reserved
R = Readable bit
PO = Program Once bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-16
Unimplemented: Read as ‘1’
bit 15
Reserved: Program as ‘0’. Read value is unknown.
bit 14
JTAGEN: JTAG Port Enable bit(1)
1 = JTAG port is enabled
0 = JTAG port is disabled
bit 13
GCP: General Segment Program Memory Code Protection bit
1 = Code protection is disabled
0 = Code protection is enabled for the entire program memory space
bit 12
GWRP: General Segment Code Flash Write Protection bit
1 = Writes to program memory are allowed
0 = Writes to program memory are disabled
bit 11
DEBUG: Background Debugger Enable bit
1 = Device resets into Operational mode
0 = Device resets into Debug mode
bit 10
Reserved: Program as ‘1’
bit 9
Unimplemented: Read as ‘1’
bit 8
ICS: Emulator Pin Placement Select bit
1 = Emulator/debugger uses EMUC2/EMUD2
0 = Emulator/debugger uses EMUC1/EMUD1
bit 7
FWDTEN: Watchdog Timer Enable bit
1 = Watchdog Timer is enabled
0 = Watchdog Timer is disabled
bit 6
WINDIS: Windowed Watchdog Timer Disable bit
1 = Standard Watchdog Timer is enabled
0 = Windowed Watchdog Timer is enabled; FWDTEN must be ‘1’
bit 5
Unimplemented: Read as ‘1’
bit 4
FWPSA: WDT Prescaler Ratio Select bit
1 = Prescaler ratio of 1:128
0 = Prescaler ratio of 1:32
Note 1:
JTAGEN bit can not be modified using JTAG programming. It can only change using In-Circuit Serial
Programming™ (ICSP™).
DS39747F-page 196
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
REGISTER 24-1:
bit 3-0
Note 1:
FLASH CONFIGURATION WORD 1 (CONTINUED)
WDTPS: Watchdog Timer Postscaler Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
JTAGEN bit can not be modified using JTAG programming. It can only change using In-Circuit Serial
Programming™ (ICSP™).
2005-2012 Microchip Technology Inc.
DS39747F-page 197
PIC24FJ128GA010 FAMILY
REGISTER 24-2:
FLASH CONFIGURATION WORD 2
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
R/PO-1
U-1
U-1
U-1
U-1
R/PO-1
R/PO-1
R/PO-1
IESO
—
—
—
—
FNOSC2
FNOSC1
FNOSC0
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
U-1
U-1
U-1
R/PO-1
R/PO-1
FCKSM1
FCKSM0
OSCIOFCN
—
—
—
POSCMD1
POSCMD0
bit 7
bit 0
Legend:
x = Bit is unknown
R = Readable bit
PO = Program Once bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-16
Unimplemented: Read as ‘1’
bit 15
IESO: Internal External Switchover bit
1 = IESO mode (Two-Speed Start-up) is enabled
0 = IESO mode (Two-Speed Start-up) is disabled
bit 14-11
Unimplemented: Read as ‘1’
bit 10-8
FNOSC: Initial Oscillator Select bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 7-6
FCKSM: Clock Switching and Fail-Safe Clock Monitor Configuration bits
1x = Clock switching and Fail-Safe Clock Monitor are disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 5
OSCIOFCN: OSC2 Pin Configuration bit
If POSCMD = 11 or 00:
1 = OSC2/CLKO/RC15 functions as CLKO (FOSC/2)
0 = OSC2/CLKO/RC15 functions as port I/O (RC15)
If POSCMD = 10 or 01:
OSCIOFCN has no effect on OSC2/CLKO/RC15.
bit 4-2
Unimplemented: Read as ‘1’
bit 1-0
POSCMD: Primary Oscillator Configuration bits
11 = Primary oscillator is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = EC Oscillator mode is selected
DS39747F-page 198
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
REGISTER 24-3:
DEVID: DEVICE ID REGISTER
U
U
U
U
U
U
U
U
—
—
—
—
—
—
—
—
bit 23
bit 16
U
U
R
R
R
R
R
R
—
—
FAMID7
FAMID6
FAMID5
FAMID4
FAMID3
FAMID2
bit 15
bit 8
R
R
R
R
R
R
R
R
FAMID1
FAMID0
DEV5
DEV4
DEV3
DEV2
DEV1
DEV0
bit 7
bit 0
Legend:
x = Bit is unknown
R = Readable bit
PO = Program Once bit
U = Unimplemented bit, read as ‘1’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-14
Unimplemented: Read as ‘0’
bit 13-6
FAMID: Device Family Identifier bits
00010000 = PIC24FJ128GA010 family
bit 5-0
DEV: Individual Device Identifier bits
000101 = PIC24FJ64GA006
000110 = PIC24FJ96GA006
000111 = PIC24FJ128GA006
001000 = PIC24FJ64GA008
001001 = PIC24FJ96GA008
001010 = PIC24FJ128GA008
001011 = PIC24FJ64GA010
001100 = PIC24FJ96GA010
001101 = PIC24FJ128GA010
2005-2012 Microchip Technology Inc.
x = Bit is unknown
DS39747F-page 199
PIC24FJ128GA010 FAMILY
REGISTER 24-4:
DEVREV: DEVICE REVISION REGISTER
U
U
U
U
U
U
U
U
—
—
—
—
—
—
—
—
bit 23
bit 16
R-0
R-0
R-1
R-1
U
U
U
R
r
r
r
r
—
—
—
MAJRV2
bit 15
bit 8
R
R
U
U
U
R
R
R
MAJRV1
MAJRV0
—
—
—
DOT2
DOT1
DOT0
bit 7
bit 0
Legend:
x = Bit is unknown
R = Readable bit
PO = Program Once bit
U = Unimplemented bit, read as ‘1’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-16
Unimplemented: Read as ‘0’
bit 15-12
Reserved: Read as ‘0011’
bit 11-9
Unimplemented: Read as ‘0’
bit 8-6
MAJRV: Major Revision Identifier bits
bit 5-3
Unimplemented: Read as ‘0’
bit 2-0
DOT: Minor Revision Identifier bits
DS39747F-page 200
r = Reserved
x = Bit is unknown
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
24.2
On-Chip Voltage Regulator
All of the PIC24FJ128GA010 family devices power
their core digital logic at a nominal 2.5V. This may
create an issue for designs that are required to operate
at a higher typical voltage, such as 3.3V. To simplify
system design, all devices in the PIC24FJ128GA010
family incorporate an on-chip regulator that allows the
device to run its core logic from VDD.
The regulator is controlled by the ENVREG pin. Tying
VDD to the pin enables the regulator, which in turn,
provides power to the core from the other VDD pins.
When the regulator is enabled, a low-ESR capacitor
(such as tantalum) must be connected to the
VDDCORE/VCAP pin (Figure 24-1). This helps to maintain the stability of the regulator. The recommended
value for the filter capacitor, CEFC, is provided in
Section 27.1 “DC Characteristics”.
If ENVREG is tied to VSS, the regulator is disabled. In
this case, separate power for the core logic, at a nominal 2.5V, must be supplied to the device on the
VDDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the VDDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 24-1 for possible
configurations.
24.2.1
FIGURE 24-1:
Regulator Enabled (ENVREG tied to VDD):
3.3V
PIC24FJ128GA010
VDD
ENVREG
VDDCORE/VCAP
CEFC
(10 F typ)
Regulator Disabled (ENVREG tied to ground):
2.5V(1)
3.3V(1)
PIC24FJ128GA010
VDD
ENVREG
VDDCORE/VCAP
VSS
Regulator Disabled (VDD tied to VDDCORE):
2.5V(1)
PIC24FJ128GA010
VDD
If the regulator is disabled, a separate Power-up Timer
(PWRT) is automatically enabled. The PWRT adds a
fixed delay of 64 ms nominal delay at device start-up.
ENVREG
VDDCORE/VCAP
ON-CHIP REGULATOR AND BOR
When
the
on-chip
regulator
is
enabled,
PIC24FJ128GA010 devices also have a simple
brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the
regulator Reset circuitry will generate a Brown-out
Reset. This event is captured by the BOR flag bit
(RCON). The brown-out voltage specifications can
be found in the “PIC24F Family Reference Manual” in
Section 7. “Reset” (DS39712).
24.2.3
VSS
ON-CHIP REGULATOR AND POR
When the voltage regulator is enabled, it takes approximately 20 s for it to generate output. During this time,
designated as TSTARTUP, code execution is disabled.
TSTARTUP is applied every time the device resumes
operation after any power-down, including Sleep mode.
24.2.2
CONNECTIONS FOR THE
ON-CHIP REGULATOR
VSS
Note 1:
These are typical operating voltages. Refer
to Section 27.1 “DC Characteristics” for
the full operating ranges of VDD and
VDDCORE.
POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, VDDCORE must
never exceed VDD by 0.3 volts.
2005-2012 Microchip Technology Inc.
DS39747F-page 201
PIC24FJ128GA010 FAMILY
24.3
Watchdog Timer (WDT)
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 9. “Watchdog
Timer (WDT)” (DS39697) in the “PIC24F
Family Reference Manual” for more
information.
For PIC24FJ128GA010 family devices, the WDT is
driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 32 kHz input, the prescaler yields a nominal
WDT time-out period (TWDT) of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPS Configuration bits (Flash Configuration Word 1),
which allow the selection of a total of 16 settings, from
1:1 to 1:32,768. Using the prescaler and postscaler,
time-out periods, ranging from 1 ms to 131 seconds,
can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed (i.e.,
Sleep or Idle mode is entered)
FIGURE 24-2:
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDT instruction during normal execution
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake-up and code execution will continue from where the PWRSAV instruction was executed.
The corresponding SLEEP or IDLE bits (RCON)
will need to be cleared in software after the device
wakes up.
The WDT Flag bit, WDTO (RCON), is not automatically cleared following a WDT time-out. To detect
subsequent WDT events, the flag must be cleared in
software.
Note:
24.3.1
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
CONTROL REGISTER
The WDT is enabled or disabled by the FWDTEN
Configuration bit. When the FWDTEN Configuration bit
is set, the WDT is always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON). The SWDTEN control bit is cleared on any device Reset. The software
WDT option allows the user to enable the WDT for critical code segments and disables the WDT during
non-critical segments for maximum power savings.
WATCHDOG TIMER (WDT) BLOCK DIAGRAM
SWDTEN
FWDTEN
LPRC Control
FWPSA
WDTPS
Prescaler
(5-bit/7-bit)
LPRC Input
32 kHz
Wake from Sleep
WDT
Counter
1 ms/4 ms
Postscaler
1:1 to 1:32.768
WDT Overflow
Reset
All Device Resets
Transition to
New Clock Source
Exit Sleep or
Idle Mode
CLRWDT Instr.
PWRSAV Instr.
Sleep or Idle Mode
DS39747F-page 202
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
24.4
Note:
JTAG Interface
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 33. “Programming and Diagnostics” (DS39716) in the
“PIC24F Family Reference Manual” for
more information.
PIC24FJ128GA010 family devices implement a JTAG
interface, which supports boundary scan device testing
as well as In-Circuit Serial Programming™ (ICSP™).
Refer to the Microchip web site (www.microchip.com)
for JTAG support files and additional information.
24.5
Note:
Program Verification and
Code Protection
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 33. “Programming and Diagnostics” (DS39716) in the
“PIC24F Family Reference Manual” for
more information.
For all devices in the PIC24FJ128GA010 family, the
on-chip program memory space is treated as a single
block. Code protection for this block is controlled by
one Configuration bit, GCP (Flash Configuration
Word 1. This bit inhibits external reads and writes
to the program memory space. It has no direct effect in
normal execution mode.
Write protection is controlled by the GWRP bit (Flash
Configuration Word 1. When GWRP is programmed to ‘0’, internal write and erase operations to
the program memory are blocked.
24.5.1
24.6
Note:
In-Circuit Serial Programming
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 33. “Programming and Diagnostics” (DS39716) in the
“PIC24F Family Reference Manual” for
more information.
PIC24FJ128GA010 family microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock (PGCx) and
data (PGDx), and three other lines for power, ground
and the programming voltage. This allows customers to
manufacture boards with unprogrammed devices and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or a custom firmware to be programmed.
24.7
In-Circuit Debugger
When MPLAB® ICD 2 is selected as a debugger, the
In-Circuit Debugging functionality is enabled. This
function allows simple debugging functions when used
with MPLAB IDE. Debugging functionality is controlled
through the EMUCx (Emulation/Debug Clock) and
EMUDx (Emulation/Debug Data) pins.
To use the In-Circuit Debugger function of the device, the
design must implement ICSP connections to MCLR,
VDD, VSS, PGCx, PGDx and the EMUDx/EMUCx pin
pair. In addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and two
I/O pins.
CONFIGURATION REGISTER
PROTECTION
The Configuration registers are protected against
inadvertent or unwanted changes, or reads in two
ways. The primary protection method is the same as
that of the shadow registers, which contain a complimentary value that is constantly compared with the
actual value. To safeguard against unpredictable
events, Configuration bit changes resulting from individual cell level disruptions (such as ESD events) will
cause a parity error and trigger a device Configuration
Word Mismatch Reset.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory. As
a consequence, when the GCP bit is set, the source
data for the device configuration is also protected.
2005-2012 Microchip Technology Inc.
DS39747F-page 203
PIC24FJ128GA010 FAMILY
NOTES:
DS39747F-page 204
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
25.0
INSTRUCTION SET SUMMARY
The PIC24F instruction set adds many enhancements
to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU
instruction sets. Most instructions are a single program
memory word. Only three instructions require two
program memory locations.
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction. The instruction set is
highly orthogonal and is grouped into four basic
categories:
•
•
•
•
Word or byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
Table 25-1 shows the general symbols used in
describing the instructions. The PIC24F instruction set
summary in Table 25-2 lists all the instructions, along
with the status flags affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand which is typically a
register ‘Wb’ without any address modifier
• The second source operand which is typically a
register ‘Ws’ with or without an address modifier
• The destination of the result which is typically a
register ‘Wd’ with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value, ‘f’
• The destination, which could either be the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register, ‘Wb’)
2005-2012 Microchip Technology Inc.
The literal instructions that involve data movement may
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by the value of ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand which is a register, ‘Wb’,
without any address modifier
• The second source operand which is a literal
value
• The destination of the result (only if not the same
as the first source operand) which is typically a
register, ‘Wd’, with or without an address modifier
The control instructions may use some of the following
operands:
• A program memory address
• The mode of the table read and table write
instructions
All instructions are a single word, except for certain
double-word instructions, which were made doubleword instructions so that all of the required information
is available in these 48 bits. In the second word, the
8 MSbs are ‘0’s. If this second word is executed as an
instruction (by itself), it will execute as a NOP.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Program Counter (PC) is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles, with the additional instruction
cycle(s) executed as a NOP. Notable exceptions are the
BRA (unconditional/computed branch), indirect CALL/
GOTO, all table reads and writes, and RETURN/RETFIE
instructions, which are single-word instructions but take
two or three cycles.
Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if
the skip is performed, depending on whether the
instruction being skipped is a single-word or two-word
instruction. Moreover, double-word moves require two
cycles. The double-word instructions execute in two
instruction cycles.
DS39747F-page 205
PIC24FJ128GA010 FAMILY
TABLE 25-1:
SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
Means literal defined by “text”
(text)
Means “content of text”
[text]
Means “the location addressed by text”
{ }
Optional field or operation
Register bit field
.b
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
bit4
4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr
Absolute address, label or expression (resolved by the linker)
f
File register address {0000h...1FFFh}
lit1
1-bit unsigned literal {0,1}
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14
14-bit unsigned literal {0...16384}
lit16
16-bit unsigned literal {0...65535}
lit23
23-bit unsigned literal {0...8388608}; LSB must be ‘0’
None
Field does not require an entry, may be blank
PC
Program Counter
Slit10
10-bit signed literal {-512...511}
Slit16
16-bit signed literal {-32768...32767}
Slit6
6-bit signed literal {-16...16}
Wb
Base W register {W0..W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor working register pair (Direct Addressing)
Wn
One of 16 working registers {W0..W15}
Wnd
One of 16 destination working registers {W0..W15}
Wns
One of 16 source working registers {W0..W15}
WREG
W0 (working register used in file register instructions)
Ws
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
DS39747F-page 206
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 25-2:
INSTRUCTION SET OVERVIEW
Assembly
Mnemonic
ADD
ADDC
AND
ASR
BCLR
BRA
BSET
BSW
BTG
BTSC
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
ADD
f
f = f + WREG
1
1
C, DC, N, OV, Z
ADD
f,WREG
WREG = f + WREG
1
1
C, DC, N, OV, Z
ADD
#lit10,Wn
Wd = lit10 + Wd
1
1
C, DC, N, OV, Z
ADD
Wb,Ws,Wd
Wd = Wb + Ws
1
1
C, DC, N, OV, Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
1
1
C, DC, N, OV, Z
ADDC
f
f = f + WREG + (C)
1
1
C, DC, N, OV, Z
ADDC
f,WREG
WREG = f + WREG + (C)
1
1
C, DC, N, OV, Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
1
1
C, DC, N, OV, Z
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
1
1
C, DC, N, OV, Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
1
1
C, DC, N, OV, Z
AND
f
f = f .AND. WREG
1
1
N, Z
AND
f,WREG
WREG = f .AND. WREG
1
1
N, Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
1
1
N, Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
1
1
N, Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
1
1
N, Z
ASR
f
f = Arithmetic Right Shift f
1
1
C, N, OV, Z
ASR
f,WREG
WREG = Arithmetic Right Shift f
1
1
C, N, OV, Z
ASR
Ws,Wd
Wd = Arithmetic Right Shift Ws
1
1
C, N, OV, Z
ASR
Wb,Wns,Wnd
Wnd = Arithmetic Right Shift Wb by Wns
1
1
N, Z
ASR
Wb,#lit5,Wnd
Wnd = Arithmetic Right Shift Wb by lit5
1
1
N, Z
BCLR
f,#bit4
Bit Clear f
1
1
None
BCLR
Ws,#bit4
Bit Clear Ws
1
1
None
BRA
C,Expr
Branch if Carry
1
1 (2)
None
BRA
GE,Expr
Branch if Greater than or Equal
1
1 (2)
None
BRA
GEU,Expr
Branch if Unsigned Greater than or Equal
1
1 (2)
None
BRA
GT,Expr
Branch if Greater than
1
1 (2)
None
BRA
GTU,Expr
Branch if Unsigned Greater than
1
1 (2)
None
BRA
LE,Expr
Branch if Less than or Equal
1
1 (2)
None
BRA
LEU,Expr
Branch if Unsigned Less than or Equal
1
1 (2)
None
BRA
LT,Expr
Branch if Less than
1
1 (2)
None
BRA
LTU,Expr
Branch if Unsigned Less than
1
1 (2)
None
BRA
N,Expr
Branch if Negative
1
1 (2)
None
BRA
NC,Expr
Branch if Not Carry
1
1 (2)
None
BRA
NN,Expr
Branch if Not Negative
1
1 (2)
None
BRA
NOV,Expr
Branch if Not Overflow
1
1 (2)
None
BRA
NZ,Expr
Branch if Not Zero
1
1 (2)
None
BRA
OV,Expr
Branch if Overflow
1
1 (2)
None
BRA
Expr
Branch Unconditionally
1
2
None
BRA
Z,Expr
Branch if Zero
1
1 (2)
None
BRA
Wn
Computed Branch
1
2
None
BSET
f,#bit4
Bit Set f
1
1
None
BSET
Ws,#bit4
Bit Set Ws
1
1
None
BSW.C
Ws,Wb
Write C bit to Ws
1
1
None
BSW.Z
Ws,Wb
Write Z bit to Ws
1
1
None
BTG
f,#bit4
Bit Toggle f
1
1
None
BTG
Ws,#bit4
Bit Toggle Ws
1
1
None
BTSC
f,#bit4
Bit Test f, Skip if Clear
1
1
None
(2 or 3)
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
None
(2 or 3)
2005-2012 Microchip Technology Inc.
DS39747F-page 207
PIC24FJ128GA010 FAMILY
TABLE 25-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
BTSS
BTST
BTSTS
Assembly Syntax
# of
Words
Description
# of
Cycles
Status Flags
Affected
BTSS
f,#bit4
Bit Test f, Skip if Set
1
1
None
(2 or 3)
BTSS
Ws,#bit4
Bit Test Ws, Skip if Set
1
1
None
(2 or 3)
BTST
f,#bit4
Bit Test f
1
1
Z
BTST.C
Ws,#bit4
Bit Test Ws to C
1
1
C
BTST.Z
Ws,#bit4
Bit Test Ws to Z
1
1
Z
BTST.C
Ws,Wb
Bit Test Ws to C
1
1
C
Z
BTST.Z
Ws,Wb
Bit Test Ws to Z
1
1
BTSTS
f,#bit4
Bit Test then Set f
1
1
Z
BTSTS.C
Ws,#bit4
Bit Test Ws to C, then Set
1
1
C
BTSTS.Z
Ws,#bit4
Bit Test Ws to Z, then Set
1
1
Z
CALL
CALL
lit23
Call Subroutine
2
2
None
CALL
Wn
Call Indirect Subroutine
1
2
None
CLR
CLR
f
f = 0x0000
1
1
None
CLR
WREG
WREG = 0x0000
1
1
None
CLR
Ws
Ws = 0x0000
1
1
None
Clear Watchdog Timer
1
1
WDTO, Sleep
CLRWDT
CLRWDT
COM
COM
f
f=f
1
1
N, Z
COM
f,WREG
WREG = f
1
1
N, Z
COM
Ws,Wd
Wd = Ws
1
1
N, Z
CP
f
Compare f with WREG
1
1
C, DC, N, OV, Z
CP
Wb,#lit5
Compare Wb with lit5
1
1
C, DC, N, OV, Z
CP
Wb,Ws
Compare Wb with Ws (Wb – Ws)
1
1
C, DC, N, OV, Z
CP0
CP0
f
Compare f with 0x0000
1
1
C, DC, N, OV, Z
CP0
Ws
Compare Ws with 0x0000
1
1
C, DC, N, OV, Z
CPB
CPB
f
Compare f with WREG, with Borrow
1
1
C, DC, N, OV, Z
CPB
Wb,#lit5
Compare Wb with lit5, with Borrow
1
1
C, DC, N, OV, Z
CPB
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
1
1
C, DC, N, OV, Z
CPSEQ
CPSEQ
Wb,Wn
Compare Wb with Wn, Skip if =
1
1
None
(2 or 3)
CPSGT
CPSGT
Wb,Wn
Compare Wb with Wn, Skip if >
1
1
None
(2 or 3)
CPSLT
CPSLT
Wb,Wn
Compare Wb with Wn, Skip if <
1
1
None
(2 or 3)
CPSNE
CPSNE
Wb,Wn
Compare Wb with Wn, Skip if
1
1
None
(2 or 3)
DAW
DAW.B
Wn
Wn = Decimal Adjust Wn
1
1
DEC
DEC
f
f = f –1
1
1
C, DC, N, OV, Z
DEC
f,WREG
WREG = f –1
1
1
C, DC, N, OV, Z
CP
C
DEC
Ws,Wd
Wd = Ws – 1
1
1
C, DC, N, OV, Z
DEC2
f
f=f–2
1
1
C, DC, N, OV, Z
DEC2
f,WREG
WREG = f – 2
1
1
C, DC, N, OV, Z
DEC2
Ws,Wd
Wd = Ws – 2
1
1
C, DC, N, OV, Z
DISI
DISI
#lit14
Disable Interrupts for k Instruction Cycles
1
1
None
DIV
DIV.SW
Wm,Wn
Signed 16/16-Bit Integer Divide
1
18
N, Z, C, OV
DIV.SD
Wm,Wn
Signed 32/16-Bit Integer Divide
1
18
N, Z, C, OV
DIV.UW
Wm,Wn
Unsigned 16/16-Bit Integer Divide
1
18
N, Z, C, OV
DIV.UD
Wm,Wn
Unsigned 32/16-Bit Integer Divide
1
18
N, Z, C, OV
EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
1
1
None
FF1L
FF1L
Ws,Wnd
Find First One from Left (MSb) Side
1
1
C
FF1R
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
1
1
C
DEC2
DS39747F-page 208
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 25-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
GOTO
INC
INC2
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
GOTO
Expr
Go to Address
2
2
None
GOTO
Wn
Go to Indirect
1
2
None
INC
f
f=f+1
1
1
C, DC, N, OV, Z
INC
f,WREG
WREG = f + 1
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
INC
Ws,Wd
Wd = Ws + 1
1
1
INC2
f
f=f+2
1
1
C, DC, N, OV, Z
INC2
f,WREG
WREG = f + 2
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
INC2
Ws,Wd
Wd = Ws + 2
1
1
IOR
f
f = f .IOR. WREG
1
1
N, Z
IOR
f,WREG
WREG = f .IOR. WREG
1
1
N, Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
1
1
N, Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
1
1
N, Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
1
1
N, Z
LNK
LNK
#lit14
Link Frame Pointer
1
1
None
LSR
LSR
f
f = Logical Right Shift f
1
1
C, N, OV, Z
LSR
f,WREG
WREG = Logical Right Shift f
1
1
C, N, OV, Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
1
1
C, N, OV, Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
1
1
N, Z
LSR
Wb,#lit5,Wnd
Wnd = Logical Right Shift Wb by lit5
1
1
N, Z
MOV
f,Wn
Move f to Wn
1
1
None
MOV
[Wns+Slit10],Wnd
Move [Wns+Slit10] to Wnd
1
1
None
MOV
f
Move f to f
1
1
N, Z
MOV
f,WREG
Move f to WREG
1
1
N, Z
MOV
#lit16,Wn
Move 16-Bit Literal to Wn
1
1
None
MOV.b
#lit8,Wn
Move 8-Bit Literal to Wn
1
1
None
MOV
Wn,f
Move Wn to f
1
1
None
MOV
Wns,[Wns+Slit10]
Move Wns to [Wns+Slit10]
1
1
MOV
Wso,Wdo
Move Ws to Wd
1
1
None
MOV
WREG,f
Move WREG to f
1
1
N, Z
MOV.D
Wns,Wd
Move Double from W(ns):W(ns+1) to Wd
1
2
None
MOV.D
Ws,Wnd
Move Double from Ws to W(nd+1):W(nd)
1
2
None
MUL.SS
Wb,Ws,Wnd
{Wnd+1, Wnd} = Signed(Wb) * Signed(Ws)
1
1
None
MUL.SU
Wb,Ws,Wnd
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws)
1
1
None
MUL.US
Wb,Ws,Wnd
{Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws)
1
1
None
MUL.UU
Wb,Ws,Wnd
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Wnd
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5)
1
1
None
MUL
f
W3:W2 = f * WREG
1
1
None
NEG
f
f=f+1
1
1
C, DC, N, OV, Z
NEG
f,WREG
WREG = f + 1
1
1
C, DC, N, OV, Z
NEG
Ws,Wd
Wd = Ws + 1
1
1
C, DC, N, OV, Z
NOP
No Operation
1
1
None
NOPR
No Operation
1
1
None
IOR
MOV
MUL
NEG
NOP
POP
POP
f
Pop f from Top-of-Stack (TOS)
1
1
None
POP
Wdo
Pop from Top-of-Stack (TOS) to Wdo
1
1
None
POP.D
Wnd
Pop from Top-of-Stack (TOS) to W(nd):W(nd+1)
1
2
None
Pop Shadow Registers
1
1
All
POP.S
PUSH
PUSH
f
Push f to Top-of-Stack (TOS)
1
1
None
PUSH
Wso
Push Wso to Top-of-Stack (TOS)
1
1
None
PUSH.D
Wns
Push W(ns):W(ns+1) to Top-of-Stack (TOS)
1
2
None
Push Shadow Registers
1
1
None
PUSH.S
2005-2012 Microchip Technology Inc.
DS39747F-page 209
PIC24FJ128GA010 FAMILY
TABLE 25-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
PWRSAV
PWRSAV
#lit1
Go into Sleep or Idle mode
1
1
WDTO, Sleep
RCALL
RCALL
Expr
Relative Call
1
2
None
RCALL
Wn
Computed Call
1
2
None
REPEAT
REPEAT
#lit14
Repeat Next Instruction lit14 + 1 times
1
1
None
REPEAT
Wn
Repeat Next Instruction (Wn) + 1 times
1
1
None
RESET
RESET
Software Device Reset
1
1
None
RETFIE
RETFIE
Return from Interrupt
1
3 (2)
None
RETLW
RETLW
Return with Literal in Wn
1
3 (2)
None
RETURN
RETURN
Return from Subroutine
1
3 (2)
None
RLC
RLC
f
f = Rotate Left through Carry f
1
1
C, N, Z
RLC
f,WREG
WREG = Rotate Left through Carry f
1
1
C, N, Z
C, N, Z
RLNC
RRC
RRNC
#lit10,Wn
RLC
Ws,Wd
Wd = Rotate Left through Carry Ws
1
1
RLNC
f
f = Rotate Left (No Carry) f
1
1
N, Z
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
1
1
N, Z
N, Z
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
1
1
RRC
f
f = Rotate Right through Carry f
1
1
C, N, Z
RRC
f,WREG
WREG = Rotate Right through Carry f
1
1
C, N, Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
1
1
C, N, Z
RRNC
f
f = Rotate Right (No Carry) f
1
1
N, Z
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
1
1
N, Z
RRNC
Ws,Wd
Wd = Rotate Right (No Carry) Ws
1
1
N, Z
SE
SE
Ws,Wnd
Wnd = Sign-Extended Ws
1
1
C, N, Z
SETM
SETM
f
f = FFFFh
1
1
None
SETM
WREG
WREG = FFFFh
1
1
None
SETM
Ws
Ws = FFFFh
1
1
None
SL
f
f = Left Shift f
1
1
C, N, OV, Z
SL
f,WREG
WREG = Left Shift f
1
1
C, N, OV, Z
SL
Ws,Wd
Wd = Left Shift Ws
1
1
C, N, OV, Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
1
1
N, Z
SL
Wb,#lit5,Wnd
Wnd = Left Shift Wb by lit5
1
1
N, Z
SUB
f
f = f – WREG
1
1
C, DC, N, OV, Z
SUB
f,WREG
WREG = f – WREG
1
1
C, DC, N, OV, Z
SUB
#lit10,Wn
Wn = Wn – lit10
1
1
C, DC, N, OV, Z
SUB
Wb,Ws,Wd
Wd = Wb – Ws
1
1
C, DC, N, OV, Z
SUB
Wb,#lit5,Wd
Wd = Wb – lit5
1
1
C, DC, N, OV, Z
SUBB
f
f = f – WREG – (C)
1
1
C, DC, N, OV, Z
SL
SUB
SUBB
SUBR
SUBBR
SWAP
TBLRDH
SUBB
f,WREG
WREG = f – WREG – (C)
1
1
C, DC, N, OV, Z
SUBB
#lit10,Wn
Wn = Wn – lit10 – (C)
1
1
C, DC, N, OV, Z
SUBB
Wb,Ws,Wd
Wd = Wb – Ws – (C)
1
1
C, DC, N, OV, Z
SUBB
Wb,#lit5,Wd
Wd = Wb – lit5 – (C)
1
1
C, DC, N, OV, Z
SUBR
f
f = WREG – f
1
1
C, DC, N, OV, Z
SUBR
f,WREG
WREG = WREG – f
1
1
C, DC, N, OV, Z
SUBR
Wb,Ws,Wd
Wd = Ws – Wb
1
1
C, DC, N, OV, Z
SUBR
Wb,#lit5,Wd
Wd = lit5 – Wb
1
1
C, DC, N, OV, Z
SUBBR
f
f = WREG – f – (C)
1
1
C, DC, N, OV, Z
SUBBR
f,WREG
WREG = WREG – f – (C)
1
1
C, DC, N, OV, Z
SUBBR
Wb,Ws,Wd
Wd = Ws – Wb – (C)
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
SUBBR
Wb,#lit5,Wd
Wd = lit5 – Wb – (C)
1
1
SWAP.b
Wn
Wn = Nibble Swap Wn
1
1
None
SWAP
Wn
Wn = Byte Swap Wn
1
1
None
TBLRDH
Ws,Wd
Read Prog to Wd
1
2
None
DS39747F-page 210
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 25-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
TBLRDL
TBLRDL
Ws,Wd
Read Prog to Wd
1
2
None
TBLWTH
TBLWTH
Ws,Wd
Write Ws to Prog
1
2
None
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog
1
2
None
ULNK
ULNK
Unlink Frame Pointer
1
1
None
XOR
XOR
f
f = f .XOR. WREG
1
1
N, Z
XOR
f,WREG
WREG = f .XOR. WREG
1
1
N, Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
1
1
N, Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
1
1
N, Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
1
1
N, Z
ZE
Ws,Wnd
Wnd = Zero-Extend Ws
1
1
C, Z, N
ZE
2005-2012 Microchip Technology Inc.
DS39747F-page 211
PIC24FJ128GA010 FAMILY
NOTES:
DS39747F-page 212
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
26.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C® for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
26.1
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
2005-2012 Microchip Technology Inc.
DS39747F-page 213
PIC24FJ128GA010 FAMILY
26.2
MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
26.3
HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple
platforms.
26.4
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
26.5
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
26.6
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS39747F-page 214
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
26.7
MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
26.8
MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
2005-2012 Microchip Technology Inc.
26.9
MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
26.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial
Programming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
DS39747F-page 215
PIC24FJ128GA010 FAMILY
26.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
26.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a breakpoint, the file registers can be examined and modified.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
26.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
DS39747F-page 216
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta A/D, flow rate sensing,
plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
27.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC24FJ128GA010 electrical characteristics. Additional information will be
provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC24FJ128GA010 are listed below. Exposure to these maximum rating conditions
for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions
above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................. .-40°C to +85°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)
Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +6.0V
Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +2.8V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin (Note 1)................................................................................................................250 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 1)....................................................................................................200 mA
Note 1:
Maximum allowable current is a function of device maximum power dissipation (see Table 27-2).
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those, or any other conditions above those
indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
FIGURE 27-1:
FREQUENCY/VOLTAGE GRAPH
3.00V
Voltage VDDCORE(1)
2.75V
2.75V
2.50V
2.25V
2.00V
32 MHz
16 MHz
Frequency
Note 1: When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCORE VDD 3.6V.
2005-2012 Microchip Technology Inc.
DS39747F-page 217
PIC24FJ128GA010 FAMILY
27.1
DC Characteristics
TABLE 27-1:
OPERATING MIPS vs. VOLTAGE
Max MIPS
VDD Range
(in Volts)
Temp Range
(in °C)
PIC24FJ128GA010 Family
2.0-3.6V
-40°C to +85°C
16
TABLE 27-2:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
PIC24FJ128GA010 Family:
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
I/O Pin Power Dissipation:
PI/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
TABLE 27-3:
THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Notes
JA
50
—
°C/W
(Note 1)
Package Thermal Resistance, 12x12x1 mm TQFP
JA
69.4
—
°C/W
(Note 1)
Package Thermal Resistance, 10x10x1 mm TQFP
JA
76.6
—
°C/W
(Note 1)
Package Thermal Resistance, 14x14x1 mm TQFP
Note 1:
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
TABLE 27-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
DC CHARACTERISTICS
Param
No.
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
Min
Typ(1)
Max
Units
VDD
VBOR
—
3.6
V
VDD
VDDCORE
—
3.6
V
Regulator is disabled
2.0
—
2.75
V
Regulator is disabled
Sym
Characteristic
Conditions
Operating Voltage
DC10
Supply Voltage
VDDCORE
DC12
VDR
RAM Data Retention
Voltage(2)
1.5
—
—
V
DC16
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
—
—
VSS
V
DC17
SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05
—
—
V/ms
DC18
VBOR
Brown-out Reset
Voltage(3)
1.9
2.2
2.5
V
Note 1:
2:
3:
Regulator is enabled
0-3.3V in 0.1s
0-2.5V in 60 ms
Regulator must be enabled
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
This is the limit to which VDD can be lowered without losing RAM data.
Device will operate normally until Brown-out reset occurs even though VDD may be below VDDMIN.
DS39747F-page 218
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 27-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Operating Current (IDD)(2)
DC20
1.6
4.0
mA
-40°C
DC20a
1.6
4.0
mA
+25°C
DC20b
1.6
4.0
mA
+85°C
DC20d
1.6
4.0
mA
-40°C
DC20e
1.6
4.0
mA
+25°C
DC20f
1.6
4.0
mA
+85°C
DC23
6.0
12
mA
-40°C
DC23a
6.0
12
mA
+25°C
DC23b
6.0
12
mA
+85°C
DC23d
6.0
12
mA
-40°C
DC23e
6.0
12
mA
+25°C
DC23f
6.0
12
mA
+85°C
DC24
20
32
mA
-40°C
DC24a
20
32
mA
+25°C
DC24b
20
32
mA
+85°C
DC24d
20
32
mA
-40°C
DC24e
20
32
mA
+25°C
DC24f
20
32
mA
+85°C
DC31
70
150
A
-40°C
DC31a
100
200
A
+25°C
DC31b
200
400
A
+85°C
DC31d
70
150
A
-40°C
DC31e
100
200
A
+25°C
DC31f
200
400
A
+85°C
Note 1:
2:
3:
4:
2.5V(3)
1 MIPS
3.6V(4)
2.5V(3)
4 MIPS
3.6V(4)
2.5V(3)
16 MIPS
3.6V(4)
2.5V(3)
LPRC (31 kHz)
3.6V(4)
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail-to-rail. All I/O pins are configured as inputs and pulled to VDD.
MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are
operational. No peripheral modules are operating and PMD bits are set.
On-chip voltage regulator is disabled (ENVREG tied to VSS).
On-chip voltage regulator is enabled (ENVREG tied to VDD).
2005-2012 Microchip Technology Inc.
DS39747F-page 219
PIC24FJ128GA010 FAMILY
TABLE 27-6:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Idle Current (IIDLE): Core Off, Clock On Base Current(2)
DC40
0.7
2
mA
-40°C
DC40a
0.7
2
mA
+25°C
DC40b
0.7
2
mA
+85°C
DC40d
0.7
2
mA
-40°C
DC40e
0.7
2
mA
+25°C
DC40f
0.7
2
mA
+85°C
DC43
2.1
4
mA
-40°C
DC43a
2.1
4
mA
+25°C
DC43b
2.1
4
mA
+85°C
DC43d
2.1
4
mA
-40°C
DC43e
2.1
4
mA
+25°C
DC43f
2.1
4
mA
+85°C
DC47
6.8
8
mA
-40°C
DC47a
6.8
8
mA
+25°C
DC47b
6.8
8
mA
+85°C
DC47c
6.8
8
mA
-40°C
DC47d
6.8
8
mA
+25°C
DC47e
6.8
8
mA
+85°C
DC51
70
150
A
-40°C
DC51a
100
200
A
+25°C
DC51b
150
400
A
+85°C
DC51d
70
150
A
-40°C
DC51e
100
200
A
+25°C
DC51f
150
400
A
+85°C
Note 1:
2:
3:
4:
2.5V(3)
1 MIPS
3.6V(4)
2.5V(3)
4 MIPS
3.6V(4)
2.5V(3)
16 MIPS
3.6V(4)
2.5V(3)
LPRC (31 kHz)
3.6V(4)
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Base IIDLE current is measured with core off, clock on, PMD bits set and all modules turned off.
On-chip voltage regulator is disabled (ENVREG tied to VSS).
On-chip voltage regulator is enabled (ENVREG tied to VDD).
DS39747F-page 220
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 27-7:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Power-Down Current (IPD)(2)
DC60
3
25
A
-40°C
DC60a
3
45
A
+25°C
DC60b
100
600
A
+85°C
DC60f
20
40
A
-40°C
DC60g
27
60
A
+25°C
DC60h
120
600
A
+85°C
2.0V(3)
Base Power-Down Current(5)
3.6V(4)
Module Differential Current
DC61
10
25
A
-40°C
DC61a
10
25
A
+25°C
DC61b
10
25
A
+85°C
DC61f
10
25
A
-40°C
DC61g
10
25
A
+25°C
DC61h
10
25
A
+85°C
DC62
8
15
A
-40°C
DC62a
8
15
A
+25°C
DC62b
8
15
A
+85°C
DC62f
8
15
A
-40°C
DC62g
8
15
A
+25°C
8
15
A
+85°C
DC62h
Note 1:
2:
3:
4:
5:
2.0V(3)
Watchdog Timer Current: IWDT(5)
3.6V(4)
2.0V(3)
RTCC + Timer1 w/32 kHz Crystal:
IRTCC(5)
3.6V(4)
Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled high. WDT, etc., are all switched off. Unused PMD bits are set. VREGS bit is clear.
On-chip voltage regulator is disabled (ENVREG tied to VSS).
On-chip voltage regulator is enabled (ENVREG tied to VDD).
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
2005-2012 Microchip Technology Inc.
DS39747F-page 221
PIC24FJ128GA010 FAMILY
TABLE 27-8:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param
No.
Sym
VIL
DI10
Characteristic
Min
Typ(1)
Max
Units
VSS
—
0.2 VDD
V
Input Low Voltage(4)
I/O Pins with ST Buffer
DI11
I/O Pins with TTL Buffer
VSS
—
0.15 VDD
V
DI15
MCLR
VSS
—
0.2 VDD
V
DI16
OSC1 (XT mode)
VSS
—
0.2 VDD
V
DI17
OSC1 (HS mode)
VSS
—
0.2 VDD
V
2
DI18
I/O Pins with I C™ Buffer
VSS
—
0.3 VDD
V
DI19
I/O Pins with SMBus Buffer
VSS
—
0.8
V
I/O Pins with ST Buffer:
with Analog Functions
Digital Only
0.8 VDD
0.8 VDD
—
—
VDD
5.5
V
V
I/O Pins with TTL Buffer:
with Analog Functions,
Digital Only
0.25 VDD + 0.8
0.25 VDD + 0.8
—
—
VDD
5.5
V
V
VIH
DI20
DI21
Conditions
Input High
SMBus enabled
Voltage(4)
DI25
MCLR
0.8 VDD
—
VDD
V
DI26
OSC1 (XT mode)
0.7 VDD
—
VDD
V
DI27
OSC1 (HS mode)
0.7 VDD
—
VDD
V
DI28
I/O Pins with I2C Buffer:
with Analog Functions
Digital Only
0.7 VDD
0.7 VDD
—
—
VDD
5.5
V
V
VDD
5.5
V
V
2.5V VPIN VDD
400
A
VDD = 3.3V, VPIN = VSS
DI29
I/O Pins with SMBus Buffer:
with Analog Functions
Digital Only
2.1
2.1
DI30
ICNPU CNxx Pull-up Current
50
250
DI31
IPU
—
—
30
A
VDD = 2.0V
—
—
100
A
VDD = 3.3V
I/O Ports:
with Analog Functions
Digital Only
—
—
50
50
1000
1000
nA
nA
Pin at high-impedance
VSS VPIN VDD
VSS VPIN 5.5V
DI51
Analog Input Pins
—
50
1000
nA
DI55
MCLR
—
50
1000
nA
VSS VPIN VDD
DI56
OSC1
—
50
1000
nA
VSS VPIN VDD,
XT and HS modes
IIL
DI50
Note 1:
2:
3:
4:
Maximum Load Current
for Digital High Detection
w/Internal Pull-up
Input Leakage Current(2,3)
VSS VPIN VDD,
Pin at high-impedance
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
Refer to Table 1-2 for I/O pins buffer types.
DS39747F-page 222
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 27-9:
DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Param
No.
Sym
VOL
Characteristic
I/O Ports
DO16
OSC2/CLKO
DO20
DO26
Note 1:
Min
Typ(1)
Max
Units
—
—
0.4
V
IOL = 8.5 mA, VDD = 3.6V
—
—
0.4
V
IOL = 6.0 mA, VDD = 2.0V
—
—
0.4
V
IOL = 8.5 mA, VDD = 3.6V
—
—
0.4
V
IOL = 6.0 mA, VDD = 2.0V
Conditions
Output Low Voltage
DO10
VOH
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
Output High Voltage
I/O Ports
OSC2/CLKO
3.0
—
—
V
IOH = -3.0 mA, VDD = 3.6V
2.4
—
—
V
IOH = -6.0 mA, VDD = 3.6V
1.65
—
—
V
IOH = -1.0 mA, VDD = 2.0V
1.4
—
—
V
IOH = -3.0 mA, VDD = 2.0V
2.4
—
—
V
IOH = -6.0 mA, VDD = 3.6V
1.4
—
—
V
IOH = -3.0 mA, VDD = 2.0V
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2005-2012 Microchip Technology Inc.
DS39747F-page 223
PIC24FJ128GA010 FAMILY
TABLE 27-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param. Symbol
IICL
Characteristic
Min.
Typ(1)
Max.
Units
Conditions
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP,
RB11, SOSCI, SOSCO, D+,
D-, VUSB and VBUS
All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP,
RB11, SOSCI, SOSCO, D+,
D-, VUSB and VBUS, and all
5V tolerant pins(4)
Input Low Injection Current
DI60a
0
IICH
—
(2,5)
-5
Input High Injection Current
DI60b
IICT
DI60c
4:
5:
6:
—
+5(3,4,5)
mA
-20(6)
—
+20(6)
mA
Total Input Injection Current
(sum of all I/O and control
pins)
Note 1:
2:
3:
0
Absolute instantaneous sum
of all ± input injection currents from all I/O pins
( | IICL + | IICH | ) IICT
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
Characterized but not tested.
Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
DS39747F-page 224
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 27-11: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
Program Flash Memory
D130
EP
Cell Endurance
100
1K
—
E/W
D131
VPR
VDD for Read
VMIN
—
3.6
V
2.25
—
3.6
V
—
3
—
ms
D132B VPEW VDD for Self-Timed
Erase/Write
D133A TIW
Self-Timed Write Cycle Time
D134
TRETD Characteristic Retention
20
—
—
Year
D135
IDDP
—
10
—
mA
Note 1:
Supply Current During
Programming
-40C to +85C
VMIN = Minimum operating
voltage
Provided no other specifications
are violated
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
TABLE 27-12: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
VRGOUT Regulator Output Voltage
Min
Typ
Max Units
Comments
—
2.5
—
V
CEFC
External Filter Capacitor Value
4.7
10
—
F
Series resistance < 3 Ohm recommended;
< 5 Ohm required.
TVREG
Voltage Regulator Start-up Time
—
500
—
s
ENVREG = VDD
TPWRT Power-up Timer Period
—
64
—
ms
ENVREG = VSS
TBG
—
—
1
ms
Band Gap Reference Start-up Time
2005-2012 Microchip Technology Inc.
DS39747F-page 225
PIC24FJ128GA010 FAMILY
TABLE 27-13: COMPARATOR SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
D300
VIOFF
Input Offset Voltage*
—
10
30
mV
D301
VICM
Input Common Mode Voltage*
0
—
VDD
V
D302
CMRR
Common Mode Rejection
Ratio*
55
—
—
dB
300
TRESP
Response Time*(1)
—
150
400
ns
301
TMC2OV
Comparator Mode Change to
Output Valid*
—
—
10
s
*
Note 1:
Comments
Parameters are characterized but not tested.
Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
TABLE 27-14: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
VDD/24
—
VDD/32
LSb
VRD310 CVRES
Resolution
VRD311 CVRAA
Absolute Accuracy
—
—
AVDD – 1.5
LSb
VRD312 CVRUR
Unit Resistor Value (R)
—
2k
—
Time(1)
—
—
10
s
VR310
Note 1:
TSET
Settling
Comments
Settling time measured while CVRR = 1 and CVR bits transition from ‘0000’ to ‘1111’.
DS39747F-page 226
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
27.2
AC Characteristics and Timing Parameters
The information contained in this section defines the PIC24FJ128GA010 AC characteristics and timing parameters.
TABLE 27-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Operating voltage VDD range as described in Section 27.1 “DC Characteristics”.
AC CHARACTERISTICS
FIGURE 27-2:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 27-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
DO50
COSC2
OSC2/CLKO Pin
—
—
15
pF
In XT and HS modes when
external clock is used to drive
OSC1
DO56
CIO
All I/O Pins and OSC2
—
—
50
pF
EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C™ mode
Note 1:
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2005-2012 Microchip Technology Inc.
DS39747F-page 227
PIC24FJ128GA010 FAMILY
FIGURE 27-3:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OS30
OS30
Q1
Q3
Q2
OSC1
OS20
OS31
OS31
OS25
CLKO
OS40
OS41
TABLE 27-17: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Sym
No.
OS10
Characteristic
FOSC External CLKI Frequency
(external clocks allowed
only in EC mode)
Oscillator Frequency
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min
Typ(1)
Max
Units
DC
3
—
—
32
8
MHz
MHz
EC mode
ECPLL mode
3.5
3.5
10
31
—
—
—
—
10
8
32
33
MHz
MHz
MHz
kHz
XT mode
XTPLL mode
HS mode
SOSC
—
—
—
—
Conditions
OS20
TOSC TOSC = 1/FOSC
OS25
TCY
62.5
—
DC
ns
OS30
TosL, External Clock in (OSC1)
TosH High or Low Time
0.45 x TOSC
—
—
ns
EC mode
OS31
TosR, External Clock in (OSC1)
TosF Rise or Fall Time
—
—
20
ns
EC mode
OS40
TckR
CLKO Rise Time(3)
—
6
10
ns
OS41
TckF
CLKO Fall Time(3)
—
6
10
ns
Note 1:
2:
3:
Instruction Cycle Time(2)
See Parameter OS10
for FOSC value
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an
external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “Max.” cycle time
limit is “DC” (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. CLKO is low for the
Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
DS39747F-page 228
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 27-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Sym
Min
Typ(2)
Max
Units
OS50
FPLLI
PLL Input Frequency
Range
3
—
8
MHz
OS51
FSYS
PLL Output Frequency
Range
12
—
32
MHz
OS52
TLOCK PLL Start-up Time
(Lock Time)
—
—
2
ms
OS53
DCLK
-2
1
+2
%
Note 1:
2:
CLKO Stability (Jitter)
Conditions
ECPLL, HSPLL, XTPLL
modes
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 27-19: INTERNAL RC OSCILLATOR SPECIFICATIONS
AC CHARACTERISTICS
Industrial
Param
No.
Characteristic(1)
Sym
TFRC
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
FRC Start-up Time
TLPRC LPRC Start-up Time
Note 1:
Min
Typ
Max
Units
—
15
—
µs
—
500
—
µs
Conditions
These parameters are characterized but not tested in manufacturing.
TABLE 27-20: INTERNAL RC OSCILLATOR ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min
Typ
Max
Units
Conditions
-2
—
+2
%
+25°C
VDD = 3.0 - 3.6V
-5
—
+5
%
-40°C TA +85°C
VDD = 3.0 - 3.6V
-15
—
+15
%
-40°C TA +85°C
VDD = 3.0 - 3.6V
Internal FRC Accuracy @ 8 MHz(1)
F20
F21
FRC
LPRC @ 31
Note 1:
kHz(1)
Change of LPRC frequency as VDD changes.
2005-2012 Microchip Technology Inc.
DS39747F-page 229
PIC24FJ128GA010 FAMILY
FIGURE 27-4:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 27-2 for load conditions.
TABLE 27-21: CLKO AND I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
—
10
25
ns
DO31
TIOR
DO32
TIOF
Port Output Fall Time
—
10
25
ns
DI35
TINP
INTx Pin High or Low
Time (output)
20
—
—
ns
DI40
TRBP
CNx High or Low Time
(input)
2
—
—
TCY
Note 1:
Port Output Rise Time
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
Conditions
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
DS39747F-page 230
2005-2012 Microchip Technology Inc.
PIC24FJ128GA010 FAMILY
TABLE 27-22: A/D MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param
No.
Symbol
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of
VDD – 0.3
or 2.0
—
Lesser of
VDD + 0.3
or 3.6
V
AD02
AVSS
Module VSS Supply
VSS – 0.3
—
VSS + 0.3
V
Reference Inputs
AD05
VREFH
Reference Voltage High
AVSS + 1.7
—
AVDD
V
AD06
VREFL
Reference Voltage Low
AVSS
—
AVDD – 1.7
V
AD07
VREF
Absolute Reference
Voltage
AVSS – 0.3
—
AVDD + 0.3
V
AD08
IVREF
Reference Voltage Input
Current
—
—
1.25
mA
AD09
ZVREF
Reference Input
Impedance
—
10K
—
VREFL
VREFH
V
AVSS – 0.3
AVDD + 0.3
V
±0.610
A
AVDD/2
V
Analog Input
AD10
VINH-VINL Full-Scale Input
AD11
VIN
AD12
Span(2)
Absolute Input Voltage
—
Leakage Current
—
AD14
VINL
Absolute VINL Input Voltage
AVSS – 0.3
AD17
RIN
Recommended
Impedance of Analog Voltage
—
±0.001
—
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V,
Source Impedance = 2.5 k
2.5K
A/D Accuracy
AD20a Nr
Resolution
AD21a INL
Integral Nonlinearity(2)
—
+1
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