PIC24HJ12GP201/202
Data Sheet
High-Performance,
16-bit Microcontrollers
© 2007-2011 Microchip Technology Inc.
DS70282E
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-373-9
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70282E-page 2
© 2007-2011 Microchip Technology Inc.
PIC24HJ12GP201/202
High-Performance, 16-bit Microcontrollers
Operating Range:
Digital I/O:
• Up to 40 MIPS operation (@ 3.0-3.6V):
- Industrial temperature range (-40°C to +85°C)
- Extended temperature range (-40°C to +125°C)
•
•
•
•
•
High-Performance CPU:
•
•
•
•
•
•
•
•
•
•
•
•
•
Modified Harvard architecture
C compiler optimized instruction set
16-bit-wide data path
24-bit-wide instructions
Linear program memory addressing up to 4M
instruction words
Linear data memory addressing up to 64 Kbytes
71 base instructions, mostly one word/one cycle
Sixteen 16-bit general purpose registers
Flexible and powerful addressing modes
Software stack
16 x 16 multiply operations
32/16 and 16/16 divide operations
Up to ±16-bit shifts for up to 40-bit data
Interrupt Controller:
•
•
•
•
•
5-cycle latency
Up to 21 available interrupt sources
Up to three external interrupts
Seven programmable priority levels
Four processor exceptions
On-Chip Flash and SRAM:
• Flash program memory (12 Kbytes)
• Data SRAM (1024 bytes)
• Boot and General Security for Program Flash
© 2007-2011 Microchip Technology Inc.
Peripheral Pin Select Functionality
Up to 21 programmable digital I/O pins
Wake-up/Interrupt-on-Change for up to 21 pins
Output pins can drive from 3.0V to 3.6V
Up to 5V output with open drain configurations on
5V tolerant pins
• 4 mA sink on all I/O pins
System Management:
• Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated Phase-Locked Loop (PLL)
- Extremely low-jitter PLL
• Power-up Timer
• Oscillator Start-up Timer/Stabilizer
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor (FSCM)
• Reset by multiple sources
Power Management:
• On-chip 2.5V voltage regulator
• Switch between clock sources in real time
• Idle, Sleep, and Doze modes with fast wake-up
Timers/Capture/Compare:
• Timer/Counters, up to three 16-bit timers:
- Can pair up to make one 32-bit timer
- One timer runs as Real-Time Clock with
external 32.768 kHz oscillator
- Programmable prescaler
• Input Capture (up to four channels):
- Capture on up, down, or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
• Output Compare (up to two channels):
- Single or Dual 16-bit Compare mode
- 16-bit Glitchless PWM Mode
DS70282E-page 3
PIC24HJ12GP201/202
Communication Modules:
Analog-to-Digital Converters (ADCs):
• 4-wire SPI:
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
• I2C™:
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
• UART:
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
- IrDA® encoding and decoding in hardware
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
• 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
- Two and four simultaneous samples (10-bit ADC)
- Up to 10 input channels with auto-scanning
- Conversion start can be manual or
synchronized with one of four trigger sources
- Conversion possible in Sleep mode
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
DS70282E-page 4
CMOS Flash Technology:
•
•
•
•
•
Low-power, high-speed Flash technology
Fully static design
3.3V (±10%) operating voltage
Industrial and extended temperature
Low power consumption
Packaging:
• 18-pin PDIP/SOIC
• 28-pin SPDIP/SOIC/QFN/SSOP
Note:
See Table 1 for the exact peripheral
features per device.
© 2007-2011 Microchip Technology Inc.
PIC24HJ12GP201/202
PIC24HJ12GP201/202 Product Families
The device names, pin counts, memory sizes and
peripheral availability of each family are listed below,
followed by their pinout diagrams.
PIC24HJ12GP201/202 CONTROLLER FAMILIES
RAM (Kbyte)
Remappable Pins
16-bit Timer
Input Capture
Output Compare
Std. PWM
UART
External Interrupts(2)
SPI
10-Bit/12-Bit ADC
I2C™
I/O Pins (Max)
PIC24HJ12GP201
18
12
1
8
3(1)
4
2
1
3
1
1 ADC, 6 ch
1
13
PIC24HJ12GP202
28
12
1
16
3(1)
4
2
1
3
1
1 ADC, 10 ch
1
21 SPDIP
SOIC
SSOP
QFN
Note 1:
2:
Packages
Device
Program Flash Memory
(Kbyte)
Remappable Peripherals
Pins
TABLE 1:
PDIP
SOIC
Only two out of three timers are remappable.
Only two out of three interrupts are remappable.
© 2007-2011 Microchip Technology Inc.
DS70282E-page 5
PIC24HJ12GP201/202
Pin Diagrams
18-Pin PDIP, SOIC
= Pins are up to 5V tolerant
1
18
VDD
2
17
VSS
PGEC2/AN1/VREF-/CN3/RA1
3
16
AN6/RP15(1)/CN11/RB15
PGED1/AN2/RP0(1)/CN4/RB0
4
15
AN7/RP14(1)/CN12/RB14
14
VCAP
(1)
PGEC1/AN3/RP1 /CN5/RB1
5
OSC1/CLKI/CN30/RA2
6
OSC2/CLKO/CN29/RA3
7
PGED3/SOSCI/RP4(1)/CN1/RB4
8
PGEC3/SOSCO/T1CK/CN0/RA4
9
PIC24HJ12GP201
MCLR
PGED2/AN0/VREF+/CN2/RA0
13
VSS
12
SDA1/RP9(1)/CN21/RB9
11
SCL1/RP8(1)/CN22/RB8
10
INT0/RP7(1)/CN23/RB7
= Pins are up to 5V tolerant
28-Pin SPDIP, SOIC, SSOP
AVDD
1
28
PGED2/AN0/VREF+/CN2/RA0
2
27
AVSS
PGEC2/AN1/VREF-/CN3/RA1
3
26
AN6/RP15(1)/CN11/RB15
PGED1/AN2/RP0(1)/CN4/RB0
4
25
AN7/RP14(1)/CN12/RB14
PGEC1/AN3/RP1(1)/CN5/RB1
5
24
AN8/RP13(1)/CN13/RB13
AN4/RP2(1)/CN6/RB2
6
23
AN9/RP12(1)/CN14/RB12
(1)
AN5/RP3 /CN7/RB3
7
22
TMS/RP11(1)/CN15/RB11
Vss
8
21
TDI/RP10(1)/CN16/RB10
OSC1/CLKI/CN30/RA2
9
OSC2/CLKO/CN29/RA3
10
PGED3/SOSC/RP4(1)/CN1/RB4
PIC24HJ12GP202
MCLR
20
VCAP
19
Vss
11
18
TDO/SDA1/RP9(1)/CN21/RB9
PGEC3/SOSCO/T1CK/CN0/RA4
12
17
TCK/SCL1/RP8(1)/CN22/RB8
VDD
13
16
INT0/RP7(1)/CN23/RB7
ASDA1/RP5(1)/CN27/RB5
14
15
ASCL1/RP6(1)/CN24/RB6
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
DS70282E-page 6
© 2007-2011 Microchip Technology Inc.
PIC24HJ12GP201/202
Pin Diagrams (Continued)
28-Pin QFN(2)
MCLR
AVDD
AVSS
AN6/RP15(1)/CN11/RB15
AN7/RP14(1)/CN12/RB14
28
PGED2/AN0/VREF+/CN2/RA0
PGEC2//AN1/VREF-/CN3/RA1
= Pins are up to 5V tolerant
27
26
25
24
23
22
PGED1/AN2/RP0(1)/CN4/RB0
1
21
AN8/RP13(1)/CN13/RB13
PGEC1/AN3/RP1(1)/CN5/RB1
2
20
AN9/RP12(1)/CN14/RB12
AN4/RP2(1)/CN6/RB2
3
19
TMS/RP11(1)/CN15/RB11
AN5/RP3(1)/CN7/RB3
4
18
TDI/RP10(1)/CN16/RB10
VSS
5
17
VCAP
OSC1/CLKI/CN30/RA2
6
16
VSS
OSC2/CLKO/CN29/RA3
7
15
TDO/SDA1/RP9(1)/CN21/RB9
11
12
13
14
(1)
ASCL1/RP6 /CN24/RB6
INT0/RP7(1)/CN23/RB7
TCK/SCL1/RP8(1)/CN22/RB8
VDD
10
(1)
9
PGEC3/SOSCO/T1CK/CN0/RA4
PGED3/SOSCI/RP4(1)/CN1/RB4
8
ASDA1/RP5 /CN27/RB5
PIC24HJ12GP202
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to
be connected to VSS externally.
© 2007-2011 Microchip Technology Inc.
DS70282E-page 7
PIC24HJ12GP201/202
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 13
3.0 CPU............................................................................................................................................................................................ 19
4.0 Memory Organization ................................................................................................................................................................. 25
5.0 Flash Program Memory .............................................................................................................................................................. 45
6.0 Resets ....................................................................................................................................................................................... 51
7.0 Interrupt Controller ..................................................................................................................................................................... 59
8.0 Oscillator Configuration .............................................................................................................................................................. 87
9.0 Power-Saving Features.............................................................................................................................................................. 97
10.0 I/O Ports ................................................................................................................................................................................... 101
11.0 Timer1 ...................................................................................................................................................................................... 119
12.0 Timer2/3 Feature...................................................................................................................................................................... 121
13.0 Input Capture............................................................................................................................................................................ 127
14.0 Output Compare....................................................................................................................................................................... 129
15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 133
16.0 Inter-Integrated Circuit™ (I2C™) .............................................................................................................................................. 139
17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 147
18.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 153
19.0 Special Features ...................................................................................................................................................................... 167
20.0 Instruction Set Summary .......................................................................................................................................................... 175
21.0 Development Support............................................................................................................................................................... 183
22.0 Electrical Characteristics .......................................................................................................................................................... 187
23.0 Packaging Information.............................................................................................................................................................. 231
Appendix A: Revision History............................................................................................................................................................. 245
Index ................................................................................................................................................................................................. 255
The Microchip Web Site ..................................................................................................................................................................... 259
Customer Change Notification Service .............................................................................................................................................. 259
Customer Support .............................................................................................................................................................................. 259
Reader Response .............................................................................................................................................................................. 260
Product Identification System............................................................................................................................................................. 261
TO OUR VALUED CUSTOMERS
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enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS70282E-page 8
© 2007-2011 Microchip Technology Inc.
PIC24HJ12GP201/202
1.0
DEVICE OVERVIEW
Note 1: This data sheet summarizes the features
of the PIC24HJ12GP201/202 devices. It
is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“dsPIC33F/PIC24H Family Reference
Manual”. Please see the Microchip web
site (www.microchip.com) for the latest
dsPIC33F/PIC24H Family Reference
Manual sections.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
This document contains device specific information
for the PIC24HJ12GP201/202 devices. PIC24H
devices contain extensive functionality with a highperformance,
16-bit
microcontroller
(MCU)
architecture.
Figure 1-1 shows a general block diagram of the core
and peripheral modules in the PIC24HJ12GP201/202
family of devices. Table 1-1 lists the functions of the
various pins shown in the pinout diagrams.
© 2007-2011 Microchip Technology Inc.
DS70282E-page 9
PIC24HJ12GP201/202
FIGURE 1-1:
PIC24HJ12GP201/202 BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Data Bus
Interrupt
Controller
16
8
16
PORTA
16
Data Latch
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
23
23
X RAM
PORTB
Address
Latch
16
16
Remappable
Pins
Address Generator Units
Address Latch
Program Memory
EA MUX
Data Latch
ROM Latch
24
Instruction
Decode and
Control
Instruction Reg
Control Signals
to Various Blocks
OSC2/CLKO
OSC1/CLKI
Timing
Generation
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
Voltage
Regulator
VCAP
Timers
1-3
IC1,2,7,8
Note:
Literal Data
16
16
16
17 x 17 Multiplier
Power-up
Timer
Divide Support
16 x 16
W Register Array
16
Oscillator
Start-up Timer
Power-on
Reset
16-bit ALU
Watchdog
Timer
16
Brown-out
Reset
VDD, VSS
MCLR
ADC1
OC/
PWM1,2
UART1
CNx
SPI1
I2C1
Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specific pins
and features present on each device.
DS70282E-page 10
© 2007-2011 Microchip Technology Inc.
PIC24HJ12GP201/202
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin
Type
Buffer
Type
PPS
AN0-AN9
I
Analog
No
Analog input channels.
CLKI
CLKO
I
O
ST/CMOS
—
No
No
External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
OSC1
I
ST/CMOS
No
OSC2
I/O
—
No
Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
SOSCI
SOSCO
I
O
ST/CMOS
—
No
No
32.768 kHz low-power oscillator crystal input; CMOS otherwise.
32.768 kHz low-power oscillator crystal output.
CN0-CN7
CN11-CN15
CN21-CN24
CN27
CN29-CN30
I
ST
No
No
No
No
No
Change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
IC1-IC2
IC7-IC8
I
ST
Yes
Yes
Capture inputs 1/2.
Capture inputs 7/8.
OCFA
OC1-OC2
I
O
ST
—
Yes
Yes
Compare Fault A input (for Compare Channels 1 and 2).
Compare outputs 1 through 2.
INT0
INT1
INT2
I
I
I
ST
ST
ST
No
Yes
Yes
External interrupt 0.
External interrupt 1.
External interrupt 2.
RA0-RA4
I/O
ST
No
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
No
PORTB is a bidirectional I/O port.
T1CK
T2CK
T3CK
I
I
I
ST
ST
ST
No
Yes
Yes
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
U1CTS
U1RTS
U1RX
U1TX
I
O
I
O
ST
—
ST
—
Yes
Yes
Yes
Yes
UART1 clear to send.
UART1 ready to send.
UART1 receive.
UART1 transmit.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I/O
ST
ST
—
ST
Yes
Yes
Yes
Yes
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
SCL1
SDA1
ASCL1
ASDA1
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No
No
No
No
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
TMS
TCK
TDI
TDO
I
I
I
O
ST
ST
ST
—
No
No
No
No
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
Pin Name
Description
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
© 2007-2011 Microchip Technology Inc.
Analog = Analog input
O = Output
P = Power
I = Input
DS70282E-page 11
PIC24HJ12GP201/202
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
PPS
VCAP
P
—
No
CPU logic filter capacitor connection.
VSS
P
—
No
Ground reference for logic and I/O pins.
Pin Name
Description
VREF+
I
Analog
No
Analog voltage reference (high) input.
VREF-
I
Analog
No
Analog voltage reference (low) input.
AVDD
P
P
No
Positive supply for analog modules. This pin must be connected at all
times.
MCLR
I/P
ST
No
Master Clear (Reset) input. This pin is an active-low Reset to the device.
AVSS
P
P
No
Ground reference for analog modules.
VDD
P
—
No
Positive supply for peripheral logic and I/O pins.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
DS70282E-page 12
Analog = Analog input
O = Output
P = Power
I = Input
© 2007-2011 Microchip Technology Inc.
PIC24HJ12GP201/202
1.1
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33F/PIC24H Family
Reference Manual”. These documents should be
considered as the general reference for the operation
of a particular module or device feature.
Note 1: To access the documents listed below,
browse to the documentation section of
the PIC24HJ12GP202 product page on
the
Microchip
web
site
(www.microchip.com) or select a family
reference manual section from the
following list.
In addition to parameters, features, and
other documentation, the resulting page
provides links to the related family
reference manual sections.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Section 1. “Introduction” (DS70197)
Section 2. “CPU” (DS70204)
Section 3. “Data Memory (DS70202)
Section 4. “Program Memory” (DS70202)
Section 5. “Flash Programming” (DS70191)
Section 6. “Interrupts” (DS70184)
Section 7. “Oscillator” (DS70186)
Section 8. “Reset” (DS70192)
Section 9. “Watchdog Timer and Power-saving Modes” (DS70196)
Section 10. “I/O Ports” (DS70193)
Section 11. “Timers” (DS70205)
Section 12. “Input Capture” (DS70198)
Section 13. “Output Compare” (DS70209)
Section 16. “Analog-to-Digital Converter (ADC) with DMA” (DS70183)
Section 17. “UART” (DS70188)
Section 18. “Serial Peripheral Interface (SPI)” (DS70206)
Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195)
Section 23. “CodeGuard Security” (DS70199)
Section 25. “Device Configuration” (DS70194)
© 2007-2011 Microchip Technology Inc.
DS70282E-page 13
PIC24HJ12GP201/202
NOTES:
DS70282E-page 14
© 2007-2011 Microchip Technology Inc.
PIC24HJ12GP201/202
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
MICROCONTROLLERS
Note 1: This data sheet summarizes the features
of the PIC24HJ12GP201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1
Basic Connection Requirements
Getting started with the PIC24HJ12GP201/202 family
of 16-bit microcontrollers requires attention to a
minimal set of device pin connections before
proceeding with development. The following is a list of
pin names, which must always be connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins (even if ADC module is not
used)
(see Section 2.2 “Decoupling Capacitors”)
• VCAP
(see Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
2.2
Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD, and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have a resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the microcontroller. If space is constricted, the capacitor can be placed on another
layer on the PCB using a via; however, ensure
that the trace length from the pin to the capacitor
is within one-quarter inch (6 mm) in length.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the microcontroller pins. This ensures
that the decoupling capacitors are first in the
power chain. Equally important is to keep the
trace length between the capacitor and the power
pins to a minimum thereby reducing PCB track
inductance.
Additionally, the following pins may be required:
• VREF+/VREF- pins used when external voltage
reference for ADC module is implemented
Note:
The AVDD and AVSS pins must be
connected independent of the ADC
voltage reference source.
© 2007-2011 Microchip Technology Inc.
DS70282E-page 15
PIC24HJ12GP201/202
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
R
R1
MCLR
C
PIC24H
VSS
10 Ω
2.2.1
VDD
0.1 µF
Ceramic
VSS
VDD
AVSS
VDD
AVDD
0.1 µF
Ceramic
VSS
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
• Device Reset
• Device programming and debugging
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
VSS
VCAP
VDD
10 µF
Tantalum
VDD
2.4
0.1 µF
Ceramic
0.1 µF
Ceramic
TANK CAPACITORS
For example, as shown in Figure 2-2, it is
recommended that capacitor C is isolated from the
MCLR pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including microcontrollers to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance
that connects the power supply source to the microcontroller, and the maximum current drawn by the microcontroller in the application. In other words, select the
tank capacitor so that it meets the acceptable voltage
sag at the device. Typical values range from 4.7 µF to
47 µF.
2.3
CPU Logic Filter Capacitor
Connection (VCAP)
A low-ESR (4)1@
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DS70282E-page 244
© 2007-2011 Microchip Technology Inc.
PIC24HJ12GP201/202
APPENDIX A:
REVISION HISTORY
Revision A (February 2007)
This is the initial released version of this document.
Revision B (May 2007)
This revision includes the following corrections and
updates:
• Minor typographical and formatting corrections
throughout the data sheet text.
• New content:
- Addition of bullet item (16-word conversion
result buffer) (see Section 17.1 “Key
Features”)
• Figure update:
- Oscillator System Diagram (see Figure 7-1)
- WDT Block Diagram (see Figure 18-2)
• Equation update:
- Serial Clock Rate (see Equation 15-1)
• Register updates:
- Clock Divisor Register (see Register 7-2)
- PLL Feedback Divisor Register (see
Register 7-3)
- Peripheral Pin Select Input Registers (see
Register 9-1 through Register 9-9)
- ADC1 Input Channel 1, 2, 3 Select Register
(see Register 17-4)
- ADC1 Input Channel 0 Select Register (see
Register 17-5)
• Table updates:
- CNEN2 (see Table 3-2 and Table 3-3)
- Reset Flag Bit Operation (see Table 5-1)
- Configuration Bit Values for Clock Operation
(see Table 7-1)
• Operation value update:
- IOLOCK set/clear operation (see
Section 9.4.3.1 “Control Register Lock”)
• The following tables in Section 21.0 “Electrical
Characteristics” have been updated with
preliminary values:
- Updated Max MIPS for -40°C to +125°C
Temp Range (see Table 21-1)
- Added new parameters for +40°C and
updated Typical and Max values for most
parameters (see Table 21-5)
- Added new parameters for +40°C and
updated Typical and Max values for most
parameters (see Table 21-6)
© 2007-2011 Microchip Technology Inc.
- Added new parameters for +40°C and
updated Typical and Max values for most
parameters (see Table 21-7)
- Added new parameters for +40°C and
updated Typical and Max values for most
parameters (see Table 21-8)
- Updated parameter DI51, added parameter
DI51a (see Table 21-9)
- Added Note 1 (see Table 21-11)
- Updated parameter OS30 (see Table 21-16)
- Updated parameter OS52 (see Table 21-17)
- Updated parameter F20, added Note 2 (see
Table 21-18)
- Updated parameter TA15 (see Table 21-22)
- Updated parameter TB15 (see Table 21-23)
- Updated parameter TC15 (see Table 21-24)
- Updated parameters AD05, AD06, AD07,
AD08, AD10, and AD11; added parameters
AD05a and AD06a; added Note 2; modified
ADC Accuracy headings to include
measurement information (see Table 21-34)
- Separated the ADC Module Specification
table in to three tables (see Table 21-34,
Table 21-35, and Table 21-36)
- Updated parameter AD50 (see Table 21-37)
- Updated parameters AD50 and AD57 (see
Table 21-38)
DS70282E-page 245
PIC24HJ12GP201/202
Revision C (May 2008)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
The major changes are referenced by their respective
section in the following table.
TABLE 23-1:
MAJOR SECTION UPDATES
Section Name
“High-Performance, 16-Bit
Digital Signal Controllers”
Update Description
Added SSOP to list of available 28-pin packages (see “Packaging:” and Table 1).
Added External Interrupts column to Remappable Peripherals in the Controller
Families table and Note 2 (see Table 1).
Added Note 1 to all pin diagrams, which references RPn pin usage by remappable
peripherals (see “Pin Diagrams”).
Section 1.0 “Device
Overview”
Changed Capture Input pin names from IC0-IC1 to IC1-IC2 and updated description
for AVDD (see Table 1-1).
Section 3.0 “Memory
Organization”
Updated Reset values for the following SFRs: IPC0, IPC2-IPC7, IPC16, and
INTTREG (see Table 3-4).
The following changes were made to the ADC1 Register Maps:
• Updated the bit range for AD1CON3 from ADCS to ADCS)
(see Table 3-14 and Table 3-15).
• Added Bit 6 (PCFG7) and Bit 7 (PCFG6) names to AD1PCFGL (Table 3-14).
• Added Bit 6 (CSS7) and Bit 7 (CSS6) names to AD1CSSL (see Table 3-14).
• Changed Bit 5 and Bit 4 in AD1CSSL to unimplemented (see Table 3-14).
Updated the Reset value for CLKDIV in the System Control Register Map
(see Table 3-19).
Section 4.0 “Flash Program
Memory”
Updated Section 4.3 “Programming Operations” with programming time formula.
Section 5.0 “Resets”
Entire section was replaced to maintain consistency with other PIC24H data sheets.
Section 7.0 “Oscillator
Configuration”
Removed the first sentence of the third clock source item (External Clock) in
Section 7.1.1.2 “Primary”
Updated the default bit values for DOZE and FRCDIV in the Clock Divisor Register
(see Register 7-2).
Added the center frequency in the OSCTUN register for the FRC Tuning bits
(TUN) value 011111 and updated the center frequency for bits value 011110
(see Register 7-4)
Section 8.0 “Power-Saving
Features”
Added the following two registers:
• PMD1: Peripheral Module Disable Control Register 1
• PMD2: Peripheral Module Disable Control Register 2
Section 9.0 “I/O Ports”
Added paragraph and Table 9-1 to Section 9.1.1 “Open-Drain Configuration”,
which provides details on I/O pins and their functionality.
Removed the following sections, which are now available in the related section of
the “PIC24H Family Reference Manual”:
• 9.4.2 “Available Peripherals”
• 9.4.3.3 “Mapping”
• 9.4.5 “Considerations for Peripheral Pin Selection”
Section 13.0 “Output
Compare”
DS70282E-page 246
Replaced sections 13.1, 13.2, and 13.3 and related figures and tables with entirely
new content.
© 2007-2011 Microchip Technology Inc.
PIC24HJ12GP201/202
TABLE 23-1:
MAJOR SECTION UPDATES
Section Name
Section 14.0 “Serial
Peripheral Interface (SPI)”
Update Description
Removed the following sections, which are now available in the related section of
the “PIC24H Family Reference Manual”:
• 14.1 “Interrupts”
• 14.2 “Receive Operations”
• 14.3 “Transmit Operations”
• 14.4 “SPI Setup” (retained Figure 14-1: SPI Module Block Diagram)
Section 15.0 “Inter-Integrated Removed the following sections, which are now available in the related section of
the “PIC24H Family Reference Manual”:
Circuit™ (I2C)”
• 15.3 “I2C Interrupts”
• 15.4 “Baud Rate Generator” (retained Figure 15-1: I2C Block Diagram)
• 15.5 “I2C Module Addresses
• 15.6 “Slave Address Masking”
• 15.7 “IPMI Support”
• 15.8 “General Call Address Support”
• 15.9 “Automatic Clock Stretch”
• 15.10 “Software Controlled Clock Stretching (STREN = 1)”
• 15.11 “Slope Control”
• 15.12 “Clock Arbitration”
• 15.13 “Multi-Master Communication, Bus Collision, and Bus Arbitration
• 15.14 “Peripheral Pin Select Limitations
Section 16.0 “Universal
Asynchronous Receiver
Transmitter (UART)”
Removed the following sections, which are now available in the related section of
the “PIC24H Family Reference Manual”:
• 16.1 “UART Baud Rate Generator”
• 16.2 “Transmitting in 8-bit Data Mode
• 16.3 “Transmitting in 9-bit Data Mode
• 16.4 “Break and Sync Transmit Sequence”
• 16.5 “Receiving in 8-bit or 9-bit Data Mode”
• 16.6 “Flow Control Using UxCTS and UxRTS Pins”
• 16.7 “Infrared Support”
Removed IrDA references and Note 1, and updated the bit and bit value
descriptions for UTXINV (UxSTA) in the UARTx Status and Control Register
(see Register 16-2).
© 2007-2011 Microchip Technology Inc.
DS70282E-page 247
PIC24HJ12GP201/202
TABLE 23-1:
MAJOR SECTION UPDATES
Section Name
Section 17.0 “10-bit/12-bit
Analog-to-Digital Converter
(ADC)”
Update Description
Updated ADC Conversion Clock Select bits in the AD1CON3 register from
ADCS to ADCS. Any references to these bits have also been updated
throughout this data sheet (Register 17-3).
Replaced Figure 17-1 (ADC1 Module Block Diagram for PIC24HJ12GP201) and
added Figure 17-2 (ADC1 Block Diagram for PIC24HJ12GP202).
Removed Equation 17-1: ADC Conversion Clock Period and Figure 17-2: ADC
Transfer Function (10-Bit Example).
Added Note 2 to Figure 17-2: ADC Conversion Clock Period Block Diagram.
Updated ADC1 Input Channel 1, 2, 3 Select Register (see Register 17-4) as follows:
• Changed bit 10-9 (CH123NB - PIC24HJ12GP201 devices only) description for
bit value of 10 (if AD12B = 0).
• Updated bit 8 (CH123SB) to reflect device-specific information.
• Updated bit 0 (CH123SA) to reflect device-specific information.
• Changed bit 2-1 (CH123NA - PIC24HJ12GP201 devices only) description for
bit value of 10 (if AD12B = 0).
Updated ADC1 Input Channel 0 Select Register (see Register 17-5) as follows:
• Changed bit value descriptions for bits 12-8
• Changed bit value descriptions for bits 4-0 (PIC24HJ12GP201 devices)
Modified Notes 1 and 2 in the ADC1 Input Scan Select Register Low
(see Register 17-6)
Modified Notes 1 and 2 in the ADC1 Port Configuration Register Low
(see Register 17-7)
Section 18.0 “Special
Features”
Added FICD register information for address 0xF8000E in the Device Configuration
Register Map (see Table 18-1).
Added FICD register content (BKBUG, COE, JTAGEN, and ICS to the
PIC24HJ12GP201/202 Configuration Bits Description (see Table 18-2).
Added a note regarding the placement of low-ESR capacitors, after the second
paragraph of Section 18.2 “On-Chip Voltage Regulator” and to Figure 18-1.
Removed the words “if enabled” from the second sentence in the fifth paragraph of
Section 18.3 “BOR: Brown-out Reset”
DS70282E-page 248
© 2007-2011 Microchip Technology Inc.
PIC24HJ12GP201/202
TABLE 23-1:
MAJOR SECTION UPDATES
Section Name
Section 21.0 “Electrical
Characteristics”
Update Description
Updated Max MIPS value for -40ºC to +125ºC temperature range in Operating
MIPS vs. Voltage (see Table 21-1).
Added 28-pin SSOP package information to Thermal Packaging Characteristics
and updated Typical values for all devices (see Table 21-3).
Removed Typ value for parameter DC12 (see Table 21-4).
Updated Note 2 in Table 21-7: DC Characteristics: Power-Down Current (IPD).
Updated MIPS conditions for parameters DC24c, DC44c, DC72a, DC72f, and
DC72g (see Table 21-5, Table 21-6, and Table 21-8).
Added Note 4 (reference to new table containing digital-only and analog pin
information to I/O Pin Input Specifications (see Table 21-9).
Updated Program Memory parameters (D136a, D136b, D137a, D137b, D138a, and
D138b) and added Note 2 (see Table 21-12).
Updated Max value for Internal RC Accuracy parameter F21 for -40°C ≤TA ≤+125°C
condition and added Note 2 (see Table 21-19).
Removed all values for Reset, Watchdog Timer, Oscillator Start-up Timer, and
Power-up Timer parameter SY20 and updated conditions, which now refers to
Section 18.4 “Watchdog Timer (WDT)” and LPRC parameter F21
(see Table 21-21).
Updated Min value for Input Capture Timing Requirements parameter IC15
(see Table 21-25).
The following changes were made to the ADC Module Specifications (Table 21-34):
• Updated Min value for ADC Module Specification parameter AD07.
• Updated Typ value for parameter AD08
• Added references to Note 1 for parameters AD12 and AD13
• Removed Note 2.
The following changes were made to the ADC Module Specifications (12-bit Mode)
(Table 21-35):
• Updated Min and Max values for both AD21a parameters (measurements with
internal and external VREF+/VREF-).
• Updated Min, Typ, and Max values for parameter AD24a.
• Updated Max value for parameter AD32a.
• Removed Note 1.
• Removed VREFL from Conditions for parameters AD21a, AD22a, AD23a, and
AD24a (measurements with internal VREF+/VREF-).
The following changes were made to the ADC Module Specifications (10-bit Mode)
(Table 21-36):
• Updated Min and Max values for parameter AD21b (measurements with
external VREF+/VREF-).
• Removed ± symbol from Min, Typ, and Max values for parameters AD23b and
AD24b (measurements with internal VREF+/VREF-).
• Updated Typ and Max values for parameter AD32b.
• Removed Note 1.
• Removed VREFL from Conditions for parameters AD21a, AD22a, AD23a, and
AD24a (measurements with internal VREF+/VREF-).
Updated Min and Typ values for parameters AD60, AD61, AD62, and AD63 and
removed Note 3 (see Table 21-37 and Table 21-38).
© 2007-2011 Microchip Technology Inc.
DS70282E-page 249
PIC24HJ12GP201/202
TABLE 23-1:
MAJOR SECTION UPDATES
Section Name
Update Description
Section 22.0 “Packaging
Information”
Added 28-lead SSOP package marking information.
“Product Identification
System”
Added Plastic Shrink Small Outline (SSOP) package information.
DS70282E-page 250
© 2007-2011 Microchip Technology Inc.
PIC24HJ12GP201/202
Revision D (June 2009)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
Global changes include:
• Changed all instances of OSCI to OSC1 and
OSCO to OSC2
• Changed all instances of PGCx/EMUCx and
PGDx/EMUDx (where x = 1, 2, or 3) to PGECx
and PGEDx
Changed all instances of VDDCORE and VDDCORE/VCAP
to VCAP/VDDCORE
All other major changes are referenced by their
respective section in the following table.
TABLE 23-2:
MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, 16-Bit
Microcontrollers”
Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams,
which references pin connections to VSS.
Section 2.0 “Guidelines for Getting
Started with 16-bit Microcontrollers”
Added new section to the data sheet that provides guidelines on getting
started with 16-bit Digital Signal Controllers.
Section 8.0 “Oscillator Configuration”
Updated the Oscillator System Diagram (see Figure 8-1).
Added Note 1 to the Oscillator Tuning (OSCTUN) register (see
Register 8-4).
Section 10.0 “I/O Ports”
Removed Table 10-1 and added reference to pin diagrams for I/O pin
availability and functionality.
Section 15.0 “Serial Peripheral Interface
(SPI)”
Added Note 2 to the SPIx Control Register 1 (see Register 15-2).
Section 17.0 “Universal Asynchronous
Receiver Transmitter (UART)”
Updated the UTXINV bit settings in the UxSTA register and added Note
1 (see Register 17-2).
Section 22.0 “Electrical Characteristics” Updated the Min value for parameter DC12 (RAM Retention Voltage)
and added Note 4 to the DC Temperature and Voltage Specifications
(see Table 22-4).
Updated the Min value for parameter DI35 (see Table 22-20).
Updated AD08 and added reference to Note 2 for parameters AD05a,
AD06a, and AD08a (see Table 22-34).
© 2007-2011 Microchip Technology Inc.
DS70282E-page 251
PIC24HJ12GP201/202
Revision E (July 2011)
This revision includes formatting changes and minor
typographical throughout the data sheet text.
Global changes include:
• Removed Preliminary marking from the footer
• Updated all family reference manual information
in the note boxes located at the beginning of most
chapters
• Changed all instances of VCAP/VDDCORE to VCAP
All other major changes are referenced by their
respective section in the following table.
TABLE 23-3:
MAJOR SECTION UPDATES
Section Name
Section 2.0 “Guidelines for Getting
Started with 16-bit Microcontrollers”
Update Description
Changed the title of section 2.3 to Section 2.3 “CPU Logic Filter
Capacitor Connection (VCAP)”.
Updated the second paragraph in Section 2.9 “Unused I/Os”.
Section 4.0 “Memory Organization”
Revised the data memory implementation value in the third paragraph
of Section 4.2 “Data Address Space”.
Updated the All Resets values for TMR1, TMR2, and TMR3 in the
Timer Register Map (see Table 4-5).
Section 8.0 “Oscillator Configuration”
Added Note 3 to the Oscillator Control Register (see Register 8-1).
Added Note 2 to the Clock Divisor Register (see Register 8-2).
Added Note 1 to the PLL Feedback Divisor Register (see Register 8-3).
Added Note 2 to the FRC Oscillator Tuning Register (see Register 8-4).
Section 10.0 “I/O Ports”
Revised the second paragraph in Section 10.1.1 “Open-Drain
Configuration”.
Section 14.0 “Output Compare”
Updated the Output Compare Module Block Diagram (see Figure 14-1).
Section 17.0 “Universal Asynchronous
Receiver Transmitter (UART)”
Revised the UART module Baud Rate features, replacing both items
with “Baud rates ranging from 10 Mbps to 38 bps at 40 MIPS”.
Section 19.0 “Special Features”
Revised all paragraphs in Section 19.1 “Configuration Bits”.
Updated the Device Configuration Register Map (see Table 19-1).
Added the RTSP Effect column in the Configuration Bits Description
(see Table 19-2).
DS70282E-page 252
© 2007-2011 Microchip Technology Inc.
PIC24HJ12GP201/202
TABLE 23-3:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
Section 22.0 “Electrical Characteristics” Updated the following Absolute Maximum Ratings:
• Storage temperature
• Voltage on any pin that is not 5V tolerant with respect to VSS
• Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V
• Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V
• Added Note 4
Revised parameters DI18, DI19, DI50, and DI51, added parameters
DI21, DI25, DI26, DI27, DI28, DI29, DI60a, DI60b, and DI60c, and
added Notes 5, 6, 7, 8, and 9 to the I/O Pin Input Specifications (see
Table 22-9).
Removed Note 2 from the AC Characteristics: Internal RC Accuracy
(see Table 22-18).
Updated the maximum value for parameter OC15 and the minimum
value for parameter OC20 in the Simple OC/PWM Mode Timing
Requirements (see Table 22-27).
Updated all SPI specifications (see Table 22-28 through Table 22-35
and Figure 22-9 through Figure 22-16).
Updated the minimum values for parameters AD05 and AD07, and the
maximum value for parameter AD06 in the ADC Module Specifications
(see Table 22-38).
Added Note 4 regarding injection currents to the ADC Module
Specifications (12-bit mode) (see Table 22-39).
Added Note 4 regarding injection currents to the ADC Module
Specifications (10-bit mode) (see Table 22-40).
© 2007-2011 Microchip Technology Inc.
DS70282E-page 253
PIC24HJ12GP201/202
NOTES:
DS70282E-page 254
© 2007-2011 Microchip Technology Inc.
PIC24HJ12GP201/202
INDEX
A
AC Characteristics ............................................................ 198
Internal RC Accuracy ................................................ 200
Load Conditions ........................................................ 198
ADC
Initialization ............................................................... 153
Key Features............................................................. 153
ADC Module
ADC1 Register Map for PIC24HJ12GP201 ................ 35
ADC1 Register Map for PIC24HJ12GP202 ................ 36
Alternate Interrupt Vector Table (AIVT) .............................. 59
Analog-to-Digital Converter (ADC).................................... 153
Arithmetic Logic Unit (ALU)................................................. 24
Assembler
MPASM Assembler................................................... 184
B
Block Diagrams
16-bit Timer1 Module ................................................ 119
Connections for On-Chip Voltage Regulator............. 170
Input Capture ............................................................ 127
Output Compare ....................................................... 129
PIC24HJ12GP201/202 ............................................... 10
PIC24HJ12GP201/202 CPU Core .............................. 20
PIC24HJ12GP201/202 Oscillator System Diagram.... 87
PIC24HJ12GP201/202 PLL ........................................ 89
PLL.............................................................................. 89
Reset System.............................................................. 51
Shared Port Structure ............................................... 101
SPI ............................................................................ 133
Timer2 (16-bit) .......................................................... 123
Timer2/3 (32-bit) ....................................................... 122
UART ........................................................................ 147
Watchdog Timer (WDT) ............................................ 171
C
C Compilers
MPLAB C18 .............................................................. 184
Clock Switching................................................................... 95
Enabling ...................................................................... 95
Sequence.................................................................... 95
Code Examples
Erasing a Program Memory Page............................... 49
Initiating a Programming Sequence............................ 50
Loading Write Buffers ................................................. 50
Port Write/Read ........................................................ 102
PWRSAV Instruction Syntax....................................... 97
Code Protection ........................................................ 167, 172
Configuration Bits.............................................................. 167
Description (Table).................................................... 168
Configuration Register Map .............................................. 167
Configuring Analog Port Pins ............................................ 102
CPU
Control Register .......................................................... 22
CPU Clocking System......................................................... 88
Options........................................................................ 88
Selection ..................................................................... 88
Customer Change Notification Service ............................. 259
Customer Notification Service........................................... 259
Customer Support ............................................................. 259
D
Data Address Space ........................................................... 27
Alignment .................................................................... 27
© 2007-2011 Microchip Technology Inc.
Memory Map for PIC24HJ12GP201/202 Devices with 1
KB RAM.............................................................. 28
Near Data Space ........................................................ 27
Software Stack ........................................................... 39
Width .......................................................................... 27
DC Characteristics............................................................ 188
I/O Pin Input Specifications ...................................... 193
I/O Pin Output Specifications.................................... 196
Idle Current (IDOZE) .................................................. 192
Idle Current (IIDLE) .................................................... 191
Operating Current (IDD) ............................................ 190
Power-Down Current (IPD)........................................ 192
Program Memory...................................................... 197
Temperature and Voltage Specifications.................. 189
Development Support ....................................................... 183
Doze Mode ......................................................................... 98
E
Electrical Characteristics .................................................. 187
AC............................................................................. 198
Equations
Device Operating Frequency...................................... 88
Errata .................................................................................... 8
F
Fail-Safe Clock Monitor ...................................................... 95
Flash Program Memory ...................................................... 45
Control Registers........................................................ 46
Operations .................................................................. 46
Programming Algorithm.............................................. 49
RTSP Operation ......................................................... 46
Table Instructions ....................................................... 45
Flexible Configuration ....................................................... 167
I
I/O Ports ........................................................................... 101
Parallel I/O (PIO) ...................................................... 101
Write/Read Timing.................................................... 102
I2 C
Addresses................................................................. 141
Operating Modes ...................................................... 139
Registers .................................................................. 139
I2C Module
I2C1 Register Map...................................................... 33
In-Circuit Debugger........................................................... 173
In-Circuit Emulation .......................................................... 167
In-Circuit Serial Programming (ICSP)....................... 167, 173
Input Capture .................................................................... 127
Registers .................................................................. 128
Input Change Notification ................................................. 102
Instruction Addressing Modes ............................................ 39
File Register Instructions ............................................ 39
Fundamental Modes Supported ................................. 40
MCU Instructions ........................................................ 39
Move and Accumulator Instructions ........................... 40
Other Instructions ....................................................... 40
Instruction Set
Overview................................................................... 177
Summary .................................................................. 175
Instruction-Based Power-Saving Modes............................. 97
Idle.............................................................................. 98
Sleep .......................................................................... 97
Interfacing Program and Data Memory Spaces.................. 41
Internal RC Oscillator
DS70282E-page 255
PIC24HJ12GP201/202
Use with WDT ........................................................... 171
Internet Address................................................................ 259
Interrupt Control and Status Registers................................ 63
IECx ............................................................................ 63
IFSx............................................................................. 63
INTCON1 .................................................................... 63
INTCON2 .................................................................... 63
IPCx ............................................................................ 63
Interrupt Setup Procedures ................................................. 85
Initialization ................................................................. 85
Interrupt Disable.......................................................... 85
Interrupt Service Routine ............................................ 85
Trap Service Routine .................................................. 85
Interrupt Vector Table (IVT) ................................................ 59
Interrupts Coincident with Power Save Instructions............ 98
J
JTAG Boundary Scan Interface ........................................ 167
JTAG Interface .................................................................. 172
M
Memory Organization.......................................................... 25
Microchip Internet Web Site .............................................. 259
MPLAB ASM30 Assembler, Linker, Librarian ................... 184
MPLAB Integrated Development Environment Software .. 183
MPLAB PM3 Device Programmer..................................... 186
MPLAB REAL ICE In-Circuit Emulator System................. 185
MPLINK Object Linker/MPLIB Object Librarian ................ 184
Multi-Bit Data Shifter ........................................................... 24
N
NVM Module
Register Map............................................................... 38
O
Open-Drain Configuration ................................................. 102
Oscillator Configuration....................................................... 87
Output Compare................................................................ 129
Registers ................................................................... 131
P
Packaging ......................................................................... 231
Details ....................................................................... 233
Marking ............................................................. 231, 232
Peripheral Module Disable (PMD)....................................... 98
Peripheral Pin Select Module
Input Register Map...................................................... 34
Output Register Map for PIC24HJ12GP202 ............... 34
Pinout I/O Descriptions (table) ............................................ 11
PMD Module
Register Map............................................................... 38
PORTA
Register Map............................................................... 37
PORTB
Register Map for PIC24HJ12GP201 ........................... 37
Register Map for PIC24HJ12GP202 ........................... 37
Power-on Reset (POR) ....................................................... 56
Power-Saving Features....................................................... 97
Clock Frequency and Switching.................................. 97
Program Address Space ..................................................... 25
Construction ................................................................ 41
Data Access from Program Memory Using Program
Space Visibility.................................................... 44
Data Access from Program Memory Using Table Instructions .................................................................... 43
Data Access from, Address Generation...................... 42
DS70282E-page 256
Memory Map for PIC24HJ12GP201/202 .................... 25
Table Read Instructions
TBLRDH ............................................................. 43
TBLRDL.............................................................. 43
Visibility Operation ...................................................... 44
Program Memory
Interrupt Vector ........................................................... 26
Organization ............................................................... 26
Reset Vector ............................................................... 26
R
Reader Response............................................................. 260
Registers
AD1CHS0 (ADC1 Input Channel 0 Select ................ 164
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 161
AD1CON1 (ADC1 Control 1) .................................... 157
AD1CON2 (ADC1 Control 2) .................................... 159
AD1CON3 (ADC1 Control 3) .................................... 160
AD1CSSL (ADC1 Input Scan Select Low)................ 166
AD1PCFGL (ADC1 Port Configuration Low) ............ 166
CLKDIV (Clock Divisor) .............................................. 92
CORCON (Core Control) ...................................... 23, 65
I2CxCON (I2Cx Control) ........................................... 141
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 145
I2CxSTAT (I2Cx Status) ........................................... 143
ICxCON (Input Capture x Control)............................ 128
IEC0 (Interrupt Enable Control 0) ............................... 72
IEC1 (Interrupt Enable Control 0) ............................... 74
IEC4 (Interrupt Enable Control 0) ............................... 75
IFS0 (Interrupt Flag Status 0) ..................................... 68
IFS1 (Interrupt Flag Status 1) ..................................... 70
IFS4 (Interrupt Flag Status 4) ..................................... 71
INTCON1 (Interrupt Control 1).................................... 66
INTCON2 (Interrupt Control 2).................................... 67
INTTREG Interrupt Control and Status Register ........ 84
IPC0 (Interrupt Priority Control 0) ............................... 76
IPC1 (Interrupt Priority Control 1) ............................... 77
IPC16 (Interrupt Priority Control 16) ........................... 83
IPC2 (Interrupt Priority Control 2) ............................... 78
IPC3 (Interrupt Priority Control 3) ............................... 79
IPC4 (Interrupt Priority Control 4) ............................... 80
IPC5 (Interrupt Priority Control 5) ............................... 81
IPC7 (Interrupt Priority Control 7) ............................... 82
NVMCON (Flash Memory Control) ............................. 47
NVMKEY (Nonvolatile Memory Key) .......................... 48
OCxCON (Output Compare x Control) ..................... 131
OSCCON (Oscillator Control) ..................................... 90
OSCTUN (FRC Oscillator Tuning).............................. 94
PLLFBD (PLL Feedback Divisor)................................ 93
PMD1 (Peripheral Module Disable Control Register 1) ..
99
PMD2 (Peripheral Module Disable Control Register 2) ..
100
RCON (Reset Control)................................................ 52
SPIxCON1 (SPIx Control 1)...................................... 135
SPIxCON2 (SPIx Control 2)...................................... 137
SPIxSTAT (SPIx Status and Control) ....................... 134
SR (CPU Status)................................................... 22, 64
T1CON (Timer1 Control) .......................................... 120
T2CON Control ......................................................... 124
T3CON Control ......................................................... 125
UxMODE (UARTx Mode).......................................... 148
UxSTA (UARTx Status and Control)......................... 150
Reset
Illegal Opcode....................................................... 51, 57
Trap Conflict ............................................................... 57
© 2007-2011 Microchip Technology Inc.
PIC24HJ12GP201/202
Uninitialized W Register.................................. 51, 57, 58
Reset Sequence ................................................................. 59
Resets ................................................................................. 51
Universal Asynchronous Receiver Transmitter (UART) ... 147
Using the RCON Status Bits............................................... 58
S
Voltage Regulator (On-Chip) ............................................ 170
Serial Peripheral Interface (SPI) ....................................... 133
Software Reset Instruction (SWR) ...................................... 57
Software Simulator (MPLAB SIM)..................................... 185
Software Stack Pointer, Frame Pointer
CALL Stack Frame...................................................... 39
Special Features of the CPU ............................................ 167
Special MCU Features ........................................................ 19
SPI Module
SPI1 Register Map...................................................... 33
Symbols Used in Opcode Descriptions............................. 176
System Control
Register Map............................................................... 38
V
W
Watchdog Time-out Reset (WDTR).................................... 57
Watchdog Timer (WDT)............................................ 167, 171
Programming Considerations ................................... 171
WWW Address ................................................................. 259
WWW, On-Line Support ....................................................... 8
T
Temperature and Voltage Specifications
AC ............................................................................. 198
Timer1 ............................................................................... 119
Timer2/3 ............................................................................ 121
Timing Characteristics
CLKO and I/O ........................................................... 201
Timing Diagrams
10-bit A/D Conversion............................................... 228
10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM
= 0, SSRC = 000) ............................................. 228
12-bit A/D Conversion (ASAM = 0, SSRC = 000) ..... 227
Brown-out Situations................................................... 56
External Clock........................................................... 199
I2Cx Bus Data (Master Mode) .................................. 220
I2Cx Bus Data (Slave Mode) .................................... 222
I2Cx Bus Start/Stop Bits (Master Mode) ................... 220
I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 222
Input Capture (CAPx)................................................ 206
OC/PWM................................................................... 207
Output Compare (OCx)............................................. 206
Reset, Watchdog Timer, Oscillator Start-up Timer and
Power-up Timer ................................................ 202
Timer1, 2 and 3 External Clock................................. 204
Timing Requirements
CLKO and I/O ........................................................... 201
DCI AC-Link Mode .................................................... 224
DCI Multi-Channel, I2S Modes.................................. 224
External Clock........................................................... 199
Input Capture ............................................................ 206
Timing Specifications
10-bit A/D Conversion Requirements ....................... 229
12-bit A/D Conversion Requirements ....................... 227
I2Cx Bus Data Requirements (Master Mode) ........... 221
I2Cx Bus Data Requirements (Slave Mode) ............. 223
Output Compare Requirements ................................ 206
PLL Clock.................................................................. 200
Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ...
203
Simple OC/PWM Mode Requirements ..................... 207
Timer1 External Clock Requirements ....................... 204
Timer2 External Clock Requirements ....................... 205
Timer3 External Clock Requirements ....................... 205
U
UART Module
UART1 Register Map.................................................. 33
© 2007-2011 Microchip Technology Inc.
DS70282E-page 257
PIC24HJ12GP201/202
NOTES:
DS70282E-page 258
© 2007-2011 Microchip Technology Inc.
PIC24HJ12GP201/202
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
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© 2007-2011 Microchip Technology Inc.
DS70282E-page 259
PIC24HJ12GP201/202
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
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Device: PIC24HJ12GP201/202
Literature Number: DS70282E
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
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DS70282E-page 260
© 2007-2011 Microchip Technology Inc.
PIC24HJ12GP201/202
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PIC 24 HJ 12 GP2 02 T E / SP - XXX
Examples:
a)
Microchip Trademark
Architecture
PIC24HJ12GP202-E/SP:
General purpose PIC24H, 12 KB program
memory, 28-pin, Extended temp.,
SPDIP package.
Flash Memory Family
Program Memory Size (KB)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture:
24
=
16-bit Microcontroller
Flash Memory Family:
HJ
=
Flash program memory, 3.3V
Product Group:
GP2
=
General purpose family
Pin Count:
01
02
=
=
18-pin
28-pin
Temperature Range:
I
E
=
=
-40° C to +85° C (Industrial)
-40° C to +125° C (Extended)
Package:
P
SP
SO
ML
SS
=
=
=
=
=
Plastic Dual In-Line - 300 mil body (PDIP)
Skinny Plastic Dual In-Line - 300 mil body (SPDIP)
Plastic Small Outline - Wide, 7.50 mil body (SOIC)
Plastic Quad, No Lead Package - 6x6 mm body (QFN)
Plastic Shrink Small Outline - 5.3 mm body (SSOP)
© 2007-2011 Microchip Technology Inc.
DS70282E-page 261
Worldwide Sales and Service
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DS70282E-page 262
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05/02/11
© 2007-2011 Microchip Technology Inc.
