PIC24HJXXXGPX06A/X08A/X10A
16-bit Microcontrollers (up to 256 KB Flash and
16 KB SRAM) with Advanced Analog
Operating Conditions
Communication Interfaces
• 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
• Two UART modules (10 Mbps)
- With support for LIN 2.0 protocols and IrDA®
• Two 4-wire SPI modules (15 Mbps)
• Up to two I2C™ modules (up to 1 Mbaud) with
SMBus support
• Up to two Enhanced CAN (ECAN) modules
(1 Mbaud) with 2.0B support
• Data Converter Interface (DCI) module with I2S
codec support
Core: 16-bit PIC24H CPU
• Code-efficient (C and Assembly) architecture
• Single-cycle mixed-sign MUL plus hardware divide
Clock Management
•
•
•
•
•
±2% internal oscillator
Programmable PLLs and oscillator clock sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast wake-up and start-up
Input/Output
• Sink/Source up to 10 mA (pin specific) for standard VOH/VOL, up to 16 mA (pin specific) for nonstandard VOH1
• 5V-tolerant pins
• Selectable open drain, pull-ups, and pull-downs
• Up to 5 mA overvoltage clamp current
• External interrupts on all I/O pins
Power Management
• Low-power management modes (Sleep, Idle,
Doze)
• Integrated Power-on Reset and Brown-out Reset
• 1.35 mA/MHz dynamic current (typical)
• 55 μA IPD current (typical)
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1 -40ºC to +125ºC)
• AEC-Q100 REVG (Grade 0 -40ºC to +150ºC)
• Class B Safety Library, IEC 60730
Advanced Analog Features
• Two ADC modules:
- Configurable as 10-bit, 1.1 Msps with four
S&H or 12-bit, 500 ksps with one S&H
- 18 analog inputs on 64-pin devices and up to
32 analog inputs on 100-pin devices
• Flexible and independent ADC trigger sources
Debugger Development Support
•
•
•
•
In-circuit and in-application programming
Two program and two complex data breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Trace and run-time watch
Timers/Output Compare/Input Capture
• Up to nine 16-bit timers/counters. Can pair up to
make four 32-bit timers.
• Eight Output Compare modules configurable as
timers/counters
• Eight Input Capture modules
Packages
Type
QFN
Pin Count
64
Contact Lead/Pitch
0.50
I/O Pins
53
Dimensions
9x9x0.9
Note: All dimensions are in millimeters (mm) unless specified.
2009-2012 Microchip Technology Inc.
TQFP
TQFP
TQFP
64
0.50
53
10x10x1
100
0.50
85
12x12x1
100
0.40
85
14x14x1
DS70592D-page 1
PIC24HJXXXGPX06A/X08A/X10A
PIC24H PRODUCT FAMILIES
The PIC24H Family of devices is ideal for a wide variety of 16-bit MCU embedded applications. The device
names, pin counts, memory sizes and peripheral availability of each device are listed below, followed by their
pinout diagrams.
Pins
Program
Flash
Memory (KB)
RAM(1) (KB)
DMA Channels
Timer 16-bit
Input Capture
Output Compare
Std. PWM
Codec
Interface
ADC
UART
SPI
I2C™
CAN
I/O Pins (Max)(2)
Packages
PIC24H Family Controllers
PIC24HJ64GP206A
64
64
8
8
9
8
8
0
1 ADC,
18 ch
2
2
1
0
53
PT, MR
PIC24HJ64GP210A
100
64
8
8
9
8
8
0
1 ADC,
32 ch
2
2
2
0
85
PF, PT
PIC24HJ64GP506A
64
64
8
8
9
8
8
0
1 ADC,
18 ch
2
2
2
1
53
PT, MR
PIC24HJ64GP510A
100
64
8
8
9
8
8
0
1 ADC,
32 ch
2
2
2
1
85
PF, PT
PIC24HJ128GP206A
64
128
8
8
9
8
8
0
1 ADC,
18 ch
2
2
2
0
53
PT, MR
PIC24HJ128GP210A 100
128
8
8
9
8
8
0
1 ADC,
32 ch
2
2
2
0
85
PF, PT
PIC24HJ128GP506A
64
128
8
8
9
8
8
0
1 ADC,
18 ch
2
2
2
1
53
PT, MR
PIC24HJ128GP510A 100
128
8
8
9
8
8
0
1 ADC,
32 ch
2
2
2
1
85
PF, PT
PIC24HJ128GP306A
64
128
16
8
9
8
8
0
1 ADC,
18 ch
2
2
2
0
53
PT, MR
PIC24HJ128GP310A 100
128
16
8
9
8
8
0
1 ADC,
32 ch
2
2
2
0
85
PF, PT
PIC24HJ256GP206A
64
256
16
8
9
8
8
0
1 ADC,
18 ch
2
2
2
0
53
PT, MR
PIC24HJ256GP210A 100
256
16
8
9
8
8
0
1 ADC,
32 ch
2
2
2
0
85
PF, PT
PIC24HJ256GP610A 100
256
16
8
9
8
8
0
2 ADC,
32 ch
2
2
2
2
85
PF, PT
Device
Note 1:
2:
RAM size is inclusive of 2 Kbytes DMA RAM.
Maximum I/O pin count includes pins shared by the peripheral functions.
DS70592D-page 2
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams
64-Pin QFN(1)
RG13
RG12
RG14
RG0
RG1
RF1
RF0
VDD
VCAP(3)
OC8/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC24HJ64GP206A(2)
PIC24HJ128GP206A
PIC24HJ256GP206A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/SDA2/CN17/RF4
U2TX/SCL2/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note
1:
The metal plane at the bottom of the device is not connected to any pins and should be connected to VSS externally.
2:
The PIC24HJ64GP206A device does not have the SCL2 and SDA2 pins.
3:
Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
2009-2012 Microchip Technology Inc.
DS70592D-page 3
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
64-Pin QFN(1)
RG13
RG12
RG14
RG0
RG1
RF1
RF0
VDD
VCAP(2)
OC8/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC24HJ128GP306A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/SDA2/CN17/RF4
U2TX/SCL2/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note
1:
The metal plane at the bottom of the device is not connected to any pins and should be connected to VSS externally.
2:
Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
DS70592D-page 4
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
64-Pin QFN(1)
RG13
RG12
RG14
RG0
RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP(2)
OC8/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC24HJ64GP506A
PIC24HJ128GP506A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/SDA2/CN17/RF4
U2TX/SCL2/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note
1:
The metal plane at the bottom of the device is not connected to any pins and should be connected to VSS externally.
2:
Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
2009-2012 Microchip Technology Inc.
DS70592D-page 5
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
64-Pin TQFP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RG13
RG12
RG14
RG0
RG1
RF1
RF0
VDD
VCAP(2)
OC8/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC24HJ64GP206A
PIC24HJ128GP206A
PIC24HJ256GP206A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/SDA2(1)/CN17/RF4
U2TX/SCL2(1)/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
Note
DS70592D-page 6
1:
This pin is not present on the PIC24HJ64GP206A device.
2:
Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
64-Pin TQFP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RG13
RG12
RG14
RG0
RG1
RF1
RF0
VDD
VCAP(1)
OC8/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC24HJ128GP306A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/SDA2/CN17/RF4
U2TX/SCL2/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
Note
1:
Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
2009-2012 Microchip Technology Inc.
DS70592D-page 7
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
64-Pin TQFP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RG13
RG12
RG14
RG0
RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP(1)
OC8/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC24HJ64GP506A
PIC24HJ128GP506A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/SDA2/CN17/RF4
U2TX/SCL2/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
Note
DS70592D-page 8
1:
Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AN28/RE4
AN27/RE3
AN26/RE2
RG13
RG12
RG14
AN25/RE1
AN24/RE0
AN23/CN23/RA7
AN22/CN22/RA6
RG0
RG1
RF1
RF0
VDD
VCAP(1)
OC8/CN16/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
100-Pin TQFP
RG15
VDD
AN29/RE5
AN30/RE6
AN31/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/CN3/RB1
75
VSS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
74
PGEC2/SOSCO/T1CK/CN0/RC14
73
PGED2/SOSCI/CN1/RC13
OC1/RD0
IC4/RD11
23
24
25
72
71
70
69
68
67
66
PIC24HJ64GP210A
PIC24HJ128GP210A
PIC24HJ128GP310A
PIC24HJ256GP210A
65
64
63
62
IC3/RD10
IC2/RD9
IC1/RD8
INT4/RA15
INT3/RA14
VSS
61
60
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
TDO/RA5
TDI/RA4
59
58
SDA2/RA3
SCL2/RA2
57
56
55
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
54
53
52
51
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC1/AN6/OCFA/RB6
26
PGED1PGED1/AN7/RB727
VREF-/RA9
28
VREF+/RA10
29
30
AVDD
31
AVSS
32
AN8/RB8
33
AN9/RB9
34
AN10/RB10
35
AN11/RB11
36
VSS
VDD
37
38
TCK/RA1
U2RTS/RF13
39
40
U2CTS/RF12
41
AN12/RB12
42
AN13/RB13
43
AN14/RB14
44
AN15/OCFB/CN12/RB15
45
VSS
46
VDD
47
IC7/U1CTS/CN20/RD14
48
IC8/U1RTS/CN21/RD15
49
U2RX/CN17/RF4
50
U2TX/CN18/RF5
PGED3/AN0/CN2/RB0
1
Note
1:
Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
2009-2012 Microchip Technology Inc.
DS70592D-page 9
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
100-Pin TQFP
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AN28/RE4
AN27/RE3
AN26/RE2
RG13
RG12
RG14
AN25/RE1
AN24/RE0
AN23/CN23/RA7
AN22/CN22/RA6
RG0
RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP(1)
OC8/CN16/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
RG15
VDD
AN29/RE5
AN30/RE6
AN31/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/CN3/RB1
75
74
VSS
PGEC2/SOSCO/T1CK/CN0/RC14
73
PGED2/SOSCI/CN1/RC13
OC1/RD0
5
6
7
8
9
71
70
69
68
67
66
72
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIC24HJ64GP510A
PIC24HJ128GP510A
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
IC4/RD11
IC3/RD10
IC2/RD9
IC1/RD8
INT4/RA15
INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
VREF-/RA9
VREF+/RA10
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
VSS
VDD
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PGED3/AN0/CN2/RB0
1
2
3
4
Note
1:
DS70592D-page 10
Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AN28/RE4
AN27/RE3
AN26/RE2
RG13
RG12
RG14
AN25/RE1
AN24/RE0
AN23/CN23/RA7
AN22/CN22/RA6
C2RX/RG0
C2TX/RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP(1)
OC8/CN16/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
100-Pin TQFP
RG15
VDD
AN29/RE5
AN30/RE6
AN31/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
75
VSS
2
3
4
5
6
7
8
9
10
11
12
74
73
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/CN1/RC13
72
OC1/RD0
71
70
69
IC4/RD11
IC3/RD10
IC2/RD9
68
67
66
IC1/RD8
INT4/RA15
13
14
15
16
17
18
19
20
21
22
23
24
25
PIC24HJ256GP610A
65
64
63
62
61
60
59
58
INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
57
56
55
54
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
53
52
51
SDO1/RF8
U1RX/RF2
SDI1/RF7
U1TX/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
VREF-/RA9
VREF+/RA10
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
VSS
VDD
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
1
Note
1:
Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
2009-2012 Microchip Technology Inc.
DS70592D-page 11
PIC24HJXXXGPX06A/X08A/X10A
Table of Contents
PIC24H Product Families....................................................................................................................................................................... 2
1.0 Device Overview ........................................................................................................................................................................ 15
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers ........................................................................................................ 19
3.0 CPU ............................................................................................................................................................................................ 23
4.0 Memory Organization ................................................................................................................................................................. 29
5.0 Flash Program Memory .............................................................................................................................................................. 59
6.0 Reset ......................................................................................................................................................................................... 65
7.0 Interrupt Controller ..................................................................................................................................................................... 69
8.0 Direct Memory Access (DMA) .................................................................................................................................................. 113
9.0 Oscillator Configuration ............................................................................................................................................................ 123
10.0 Power-Saving Features ............................................................................................................................................................ 133
11.0 I/O Ports ................................................................................................................................................................................... 141
12.0 Timer1 ...................................................................................................................................................................................... 145
13.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................ 147
14.0 Input Capture............................................................................................................................................................................ 153
15.0 Output Compare ....................................................................................................................................................................... 155
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 159
17.0 Inter-Integrated Circuit™ (I2C™) .............................................................................................................................................. 165
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 173
19.0 Enhanced CAN (ECAN™) Module ........................................................................................................................................... 179
20.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 207
21.0 Special Features ...................................................................................................................................................................... 221
22.0 Instruction Set Summary .......................................................................................................................................................... 229
23.0 Development Support............................................................................................................................................................... 237
24.0 Electrical Characteristics .......................................................................................................................................................... 241
25.0 High Temperature Electrical Characteristics ............................................................................................................................ 287
26.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 297
27.0 Packaging Information.............................................................................................................................................................. 301
Appendix A: Migrating from PIC24HJXXXGPX06/X08/X10 Devices to PIC24HJXXXGPX06A/X08A/X10A Devices ....................... 311
Appendix B: Revision History............................................................................................................................................................. 312
Index ................................................................................................................................................................................................. 317
The Microchip Web Site ..................................................................................................................................................................... 321
Customer Change Notification Service .............................................................................................................................................. 321
Customer Support .............................................................................................................................................................................. 321
Reader Response .............................................................................................................................................................................. 322
Product Identification System............................................................................................................................................................. 323
DS70592D-page 12
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via Email at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of
silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
2009-2012 Microchip Technology Inc.
DS70592D-page 13
PIC24HJXXXGPX06A/X08A/X10A
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33F/PIC24H Family
Reference Manual”. These documents should be
considered as the general reference for the operation
of a particular module or device feature.
Note:
To access the documents listed below,
browse to the documentation section of
the PIC24HJ256GP610A product page
on
the
Microchip
web
site
(www.microchip.com) or by selecting a
family reference manual section from
the following list.
In addition to parameters, features, and
other documentation, the resulting page
provides links to the related family
reference manual sections.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Section 1. “Introduction” (DS70197)
Section 2. “CPU” (DS70204)
Section 3. “Data Memory” (DS70202)
Section 4. “Program Memory” (DS70203)
Section 5. “Flash Programming” (DS70191)
Section 6. “Interrupts” (DS70184)
Section 7. “Oscillator” (DS70186)
Section 8. “Reset” (DS70192)
Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196)
Section 10. “I/O Ports” (DS70193)
Section 11. “Timers” (DS70205)
Section 12. “Input Capture” (DS70198)
Section 13. “Output Compare” (DS70209)
Section 16. “Analog-to-Digital Converter (ADC)” (DS70183)
Section 17. “UART” (DS70188)
Section 18. “Serial Peripheral Interface (SPI)” (DS70206)
Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195)
Section 20. “Data Converter Interface (DCI)” (DS70288)
Section 21. “Enhanced Controller Area Network (ECAN™)” (DS70185)
Section 22. “Direct Memory Access (DMA)” (DS70182)
Section 23. “CodeGuard™ Security” (DS70199)
Section 24. “Programming and Diagnostics” (DS70207)
Section 25. “Device Configuration” (DS70194)
DS70592D-page 14
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
1.0
Note:
DEVICE OVERVIEW
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the latest
family reference sections of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
This document contains device specific information for
the following devices:
•
•
•
•
•
•
•
•
•
•
•
•
•
PIC24HJ64GP206A
PIC24HJ64GP210A
PIC24HJ64GP506A
PIC24HJ64GP510A
PIC24HJ128GP206A
PIC24HJ128GP210A
PIC24HJ128GP506A
PIC24HJ128GP510A
PIC24HJ128GP306A
PIC24HJ128GP310A
PIC24HJ256GP206A
PIC24HJ256GP210A
PIC24HJ256GP610A
The PIC24HJXXXGPX06A/X08A/X10A device family
includes devices with different pin counts (64 and 100
pins), different program memory sizes (64 Kbytes, 128
Kbytes and 256 Kbytes) and different RAM sizes (8
Kbytes and 16 Kbytes).
2009-2012 Microchip Technology Inc.
This makes these families suitable for a wide variety of
high-performance digital signal control applications.
The devices are pin compatible with the dsPIC33F family of devices, and also share a very high degree of
compatibility with the dsPIC30F family devices. This
allows easy migration between device families as may
be necessitated by the specific functionality, computational resource and system cost requirements of the
application.
The PIC24HJXXXGPX06A/X08A/X10A device family
employs a powerful 16-bit architecture, ideal for
applications that rely on high-speed, repetitive
computations, as well as control.
The 17 x 17 multiplier, hardware support for division
operations, multi-bit data shifter, a large array of 16-bit
working registers and a wide variety of data addressing
modes,
together
provide
the
PIC24HJXXXGPX06A/X08A/X10A Central Processing
Unit (CPU) with extensive mathematical processing
capability. Flexible and deterministic interrupt handling,
coupled with a powerful array of peripherals, renders
the PIC24HJXXXGPX06A/X08A/X10A devices suitable for control applications. Further, Direct Memory
Access (DMA) enables overhead-free transfer of data
between several peripherals and a dedicated DMA
RAM. Reliable, field programmable Flash program
memory ensures scalability of applications that use
PIC24HJXXXGPX06A/X08A/X10A devices.
Figure 1-1 shows a general block diagram of the
various core and peripheral modules in the
PIC24HJXXXGPX06A/X08A/X10A family of devices,
while Table 1-1 lists the functions of the various pins
shown in the pinout diagrams.
DS70592D-page 15
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 1-1:
PIC24HJXXXGPX06A/X08A/X10A GENERAL BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Data Bus
Interrupt
Controller
16
8
16
PORTA
16
DMA
RAM
Data Latch
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
23
X RAM
PORTB
Address
Latch
DMA
23
Controller
16
PORTC
Address Generator Units
Address Latch
16
Program Memory
EA MUX
Data Latch
24
Instruction Reg
Control Signals
to Various Blocks
Timing
Generation
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
Voltage
Regulator
VCAP
Timers
1-9
IC1-8
Note:
Literal Data
16
Instruction
Decode and
Control
OSC2/CLKO
OSC1/CLKI
PORTD
ROM Latch
16
PORTE
16
17 x 17 Multiplier
Power-up
Timer
Divide Support
16 x 16
W Register Array
16
Oscillator
Start-up Timer
Power-on
Reset
16-bit ALU
Watchdog
Timer
16
Brown-out
Reset
VDD, VSS
ADC1,2
OC/
PWM1-8
PORTF
PORTG
MCLR
ECAN1,2
UART1,2
CN1-23
SPI1,2
I2C1,2
Not all pins or features are implemented on all device pinout configurations. See Pin Diagrams for the specific pins and
features present on each device.
DS70592D-page 16
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin
Type
Buffer
Type
AN0-AN31
I
Analog
AVDD
P
P
Positive supply for analog modules. This pin must be connected at all times.
AVSS
P
P
Ground reference for analog modules.
CLKI
CLKO
I
O
CN0-CN23
I
ST
Input change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
C1RX
C1TX
C2RX
C2TX
I
O
I
O
ST
—
ST
—
ECAN1 bus receive pin.
ECAN1 bus transmit pin.
ECAN2 bus receive pin.
ECAN2 bus transmit pin.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
IC1-IC8
I
ST
Capture inputs 1 through 8.
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.
Pin Name
Description
Analog input channels.
ST/CMOS External clock source input. Always associated with OSC1 pin function.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
MCLR
I/P
ST
Master Clear (Reset) input. This pin is an active-low Reset to the device.
OCFA
OCFB
OC1-OC8
I
I
O
ST
ST
—
Compare Fault A input (for Compare Channels 1, 2, 3 and 4).
Compare Fault B input (for Compare Channels 5, 6, 7 and 8).
Compare outputs 1 through 8.
OSC1
I
OSC2
I/O
RA0-RA7
RA9-RA10
RA12-RA15
I/O
I/O
I/O
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
ST
ST
ST
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
PORTB is a bidirectional I/O port.
RC1-RC4
RC12-RC15
I/O
I/O
ST
ST
PORTC is a bidirectional I/O port.
RD0-RD15
I/O
ST
PORTD is a bidirectional I/O port.
RE0-RE7
I/O
ST
PORTE is a bidirectional I/O port.
RF0-RF8
RF12-RF13
I/O
ST
PORTF is a bidirectional I/O port.
RG0-RG3
RG6-RG9
RG12-RG15
I/O
I/O
I/O
ST
ST
ST
PORTG is a bidirectional I/O port.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
2009-2012 Microchip Technology Inc.
Analog = Analog input
O = Output
P = Power
I = Input
DS70592D-page 17
PIC24HJXXXGPX06A/X08A/X10A
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2
I/O
I
O
I/O
I/O
I
O
I/O
ST
ST
—
ST
ST
ST
—
ST
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
Synchronous serial clock input/output for SPI2.
SPI2 data in.
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.
SCL1
SDA1
SCL2
SDA2
I/O
I/O
I/O
I/O
ST
ST
ST
ST
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Synchronous serial clock input/output for I2C2.
Synchronous serial data input/output for I2C2.
SOSCI
SOSCO
I
O
TMS
TCK
TDI
TDO
I
I
I
O
ST
ST
ST
—
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
T1CK
T2CK
T3CK
T4CK
T5CK
T6CK
T7CK
T8CK
T9CK
I
I
I
I
I
I
I
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
Timer6 external clock input.
Timer7 external clock input.
Timer8 external clock input.
Timer9 external clock input.
U1CTS
U1RTS
U1RX
U1TX
U2CTS
U2RTS
U2RX
U2TX
I
O
I
O
I
O
I
O
ST
—
ST
—
ST
—
ST
—
UART1 clear to send.
UART1 ready to send.
UART1 receive.
UART1 transmit.
UART2 clear to send.
UART2 ready to send.
UART2 receive.
UART2 transmit.
VDD
P
—
Positive supply for peripheral logic and I/O pins.
VCAP
P
—
CPU logic filter capacitor connection.
VSS
P
—
Ground reference for logic and I/O pins.
VREF+
I
Analog
Analog voltage reference (high) input.
VREF-
I
Analog
Analog voltage reference (low) input.
Pin Name
Description
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
—
32.768 kHz low-power oscillator crystal output.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
DS70592D-page 18
Analog = Analog input
O = Output
P = Power
I = Input
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
MICROCONTROLLERS
Note 1: This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”. Please see
the
Microchip
web
site
(www.microchip.com) for the latest
dsPIC33F/PIC24H Family Reference
Manual sections.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1
Basic Connection Requirements
Getting
started
with
the
PIC24HJXXXGPX06A/X08A/X10A family of 16-bit
Microcontrollers (MCUs) requires attention to a minimal
set of device pin connections before proceeding with
development. The following is a list of pin names, which
must always be connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2 “Decoupling Capacitors”)
• VCAP
(see Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
2.2
Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
Additionally, the following pins may be required:
• VREF+/VREF- pins used when external voltage
reference for ADC module is implemented
Note:
The AVDD and AVSS pins must be
connected independent of the ADC
voltage reference source.
2009-2012 Microchip Technology Inc.
DS70592D-page 19
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
10 µF
Tantalum
R
R1
VSS
VDD
2.4
VCAP
VDD
• Device Reset
• Device programming and debugging
C
PIC24H
VSS
VDD
VSS
VDD
AVSS
VDD
AVDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
L1(1)
Note
1:
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
Where:
F CNV
f = ------------2
1
f = ---------------------- 2 LC
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
MCLR
0.1 µF
Ceramic
The placement of this capacitor should be close to the
VCAP. It is recommended that the trace length not
exceed one-quarter inch (6 mm). Refer to Section 21.2
“On-Chip Voltage Regulator” for details.
(i.e., ADC conversion rate/2)
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
2
1
L = ----------------------
2f C
R(1)
R1(2)
2.2.1
TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including MCUs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that connects the power supply source to the device, and the
maximum current drawn by the device in the application. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
2.3
CPU Logic Filter Capacitor
Connection (VCAP)
JP
MCLR
PIC24H
C
Note 1:
R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
2:
R1 470 will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
A low-ESR (< 5 Ohms) capacitor is required on the
VCAP pin, which is used to stabilize the voltage
regulator output voltage. The VCAP pin must not be
connected to VDD, and must have a capacitor between
4.7 µF and 10 µF, 16V connected to ground. The type
can be ceramic or tantalum. Refer to Section 24.0
“Electrical
Characteristics”
for
additional
information.
DS70592D-page 20
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
2.5
ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing
requirements
information
in
the
“dsPIC33F/PIC24H Flash Programming Specification”
(DS70152) for information on capacitive loading limits
and pin input voltage high (VIH) and input low (VIL)
requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 3 or MPLAB REAL ICE™.
For more information on ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web
site.
• “Using MPLAB® ICD 3 In-Circuit Debugger”
(poster) DS51765
• “MPLAB® ICD 3 Design Advisory” DS51764
• “MPLAB® REAL ICE™ In-Circuit Emulator User’s
Guide” DS51616
• “Using MPLAB® REAL ICE™” (poster) DS51749
2009-2012 Microchip Technology Inc.
2.6
External Oscillator Pins
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 9.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Main Oscillator
13
Guard Ring
14
15
Guard Trace
Secondary
Oscillator
16
17
18
19
20
DS70592D-page 21
PIC24HJXXXGPX06A/X08A/X10A
2.7
Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 8 MHz for start-up with PLL enabled to comply with
device PLL start-up conditions. This means that if the
external oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration word.
2.8
Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins
(ANx) as “digital” pins, by setting all bits in the
AD1PCFGL register.
The bits in this register that correspond to the A/D pins
that are initialized by MPLAB ICD 3 or REAL ICE, must
not be cleared by the user application firmware;
otherwise, communication errors will result between
the debugger and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 3 or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the AD1PCFGL register. Automatic
initialization of this register is only done during
debugger operation. Failure to correctly configure the
register(s) will result in all A/D pins being recognized as
analog input pins, resulting in the port value being read
as a logic ‘0’, which may affect user application
functionality.
2.9
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternatively, connect a 1k to 10k resistor between VSS
and the unused pins.
DS70592D-page 22
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
3.0
CPU
Note 1: This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 2. “CPU” (DS70204) of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The PIC24HJXXXGPX06A/X08A/X10A CPU module
has a 16-bit (data) modified Harvard architecture with an
enhanced instruction set and addressing modes. The
CPU has a 24-bit instruction word with a variable length
opcode field. The Program Counter (PC) is 23 bits wide
and addresses up to 4M x 24 bits of user program
memory space. The actual amount of program memory
implemented varies by device. A single-cycle instruction
prefetch mechanism is used to help maintain throughput
and provides predictable execution. All instructions
execute in a single cycle, with the exception of
instructions that change the program flow, the double
word move (MOV.D) instruction and the table instructions.
Overhead-free, single-cycle program loop constructs are
supported using the REPEAT instruction, which is
interruptible at any point.
3.1
Data Addressing Overview
The data space can be linearly addressed as 32K words
or 64 Kbytes using an Address Generation Unit (AGU).
The upper 32 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space
Visibility Page (PSVPAG) register. The program to data
space mapping feature lets any instruction access program space as if it were data space.
The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers, but may
be used as general purpose RAM.
3.2
Special MCU Features
The PIC24HJXXXGPX06A/X08A/X10A features a
17-bit by 17-bit, single-cycle multiplier. The multiplier
can perform signed, unsigned and mixed-sign
multiplication. Using a 17-bit by 17-bit multiplier for
16-bit by 16-bit multiplication makes mixed-sign
multiplication possible.
The PIC24HJXXXGPX06A/X08A/X10A supports 16/16
and 32/16 integer divide operations. All divide
instructions are iterative operations. They must be
executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
A multi-bit data shifter is used to perform up to a 16-bit,
left or right shift in a single cycle.
The PIC24HJXXXGPX06A/X08A/X10A devices have
sixteen, 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a data,
address or address offset register. The 16th working
register (W15) operates as a software Stack Pointer (SP)
for interrupts and calls.
The PIC24HJXXXGPX06A/X08A/X10A instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
the PIC24HJXXXGPX06A/X08A/X10A is capable of
executing a data (or program data) memory read, a
working register (data) read, a data memory write and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in Figure 3-1,
and
the
programmer’s
model
for
the
PIC24HJXXXGPX06A/X08A/X10A is shown in
Figure 3-2.
2009-2012 Microchip Technology Inc.
DS70592D-page 23
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 3-1:
PIC24HJXXXGPX06A/X08A/X10A CPU CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
X Data Bus
Interrupt
Controller
8
16
16
16
Data Latch
23
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
DMA
X RAM
RAM
16
Address
Latch
23
16
DMA
Controller
Address Generator Units
Address Latch
Program Memory
EA MUX
Data Latch
ROM Latch
24
Control Signals
to Various Blocks
Instruction Reg
Literal Data
Instruction
Decode and
Control
16
16
16
17 x 17
Multiplier
Divide Support
16 x 16
W Register Array
16
16-bit ALU
16
To Peripheral Modules
DS70592D-page 24
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 3-2:
PIC24HJXXXGPX06A/X08A/X10A PROGRAMMER’S MODEL
D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
W5
W6
W7
Working Registers
W8
W9
W10
W11
W12
W13
W14/Frame Pointer
W15/Stack Pointer
Stack Pointer Limit Register
SPLIM
PC22
PC0
Program Counter
0
0
7
Data Table Page Address
TBLPAG
7
0
PSVPAG
Program Space Visibility Page Address
15
0
RCOUNT
REPEAT Loop Counter
15
0
Core Configuration Register
CORCON
—
—
—
—
—
—
SRH
2009-2012 Microchip Technology Inc.
— DC
IPL2 IPL1 IPL0 RA
N
OV
Z
C
STATUS Register
SRL
DS70592D-page 25
PIC24HJXXXGPX06A/X08A/X10A
3.3
CPU Control Registers
REGISTER 3-1:
SR: CPU STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
DC
bit 15
bit 8
R/W-0(1)
R/W-0(2)
R/W-0(2)
(2)
IPL
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RA
N
OV
Z
C
bit 7
bit 0
Legend:
C = Clear only bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
S = Set only bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented: Read as ‘0’
bit 8
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized
data) of the result occurred
bit 7-5
IPL: CPU Interrupt Priority Level Status bits(2)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4
RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3
N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1
Z: MCU ALU Zero bit
1 = An operation which affects the Z bit has set it at some time in the past
0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result)
bit 0
C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit (MSb) of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when
IPL = 1.
The IPL Status bits are read only when NSTDIS = 1 (INTCON1).
DS70592D-page 26
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER
U-0
—
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 8
U-0
—
U-0
—
R/C-0
IPL3(1)
R/W-0
PSV
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
0’ = Bit is cleared
bit 15-4
bit 3
bit 2
bit 1-0
Note 1:
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
Unimplemented: Read as ‘0’
IPL3: CPU Interrupt Priority Level Status bit 3(1)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
Unimplemented: Read as ‘0’
The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level.
2009-2012 Microchip Technology Inc.
DS70592D-page 27
PIC24HJXXXGPX06A/X08A/X10A
3.4
Arithmetic Logic Unit (ALU)
The PIC24HJXXXGPX06A/X08A/X10A ALU is 16 bits
wide and is capable of addition, subtraction, bit shifts
and logic operations. Unless otherwise mentioned,
arithmetic operations are 2’s complement in nature.
Depending on the operation, the ALU may affect the
values of the Carry (C), Zero (Z), Negative (N),
Overflow (OV) and Digit Carry (DC) Status bits in the
SR register. The C and DC Status bits operate as
Borrow and Digit Borrow bits, respectively, for
subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from
the ALU can be written to the W register array or a data
memory location.
Refer to the “16-bit MCU and DSC Programmer’s
Reference Manual” (DS70157) for information on the
SR bits affected by each instruction.
The
PIC24HJXXXGPX06A/X08A/X10A
CPU
incorporates hardware support for both multiplication
and division. This includes a dedicated hardware
multiplier and support hardware for 16-bit divisor
division.
3.4.1
MULTIPLIER
3.4.2
DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
•
•
•
•
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. Sixteen-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn) and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
3.4.3
MULTI-BIT DATA SHIFTER
The multi-bit data shifter is capable of performing up to
16-bit arithmetic or logic right shifts, or up to 16-bit left
shifts in a single cycle. The source can be either a
working register or a memory location.
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
Using the high-speed 17-bit x 17-bit multiplier, the ALU
supports unsigned, signed or mixed-sign operation in
several multiplication modes:
•
•
•
•
•
•
•
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
DS70592D-page 28
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
4.0
MEMORY ORGANIZATION
4.1
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 3.
“Data Memory” (DS70202) of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
Note:
The PIC24HJXXXGPX06A/X08A/X10A architecture
features separate program and data memory spaces
and buses. This architecture also allows the direct
access of program memory from the data space during
code execution.
FIGURE 4-1:
The program address memory space of the
PIC24HJXXXGPX06A/X08A/X10A devices is 4M
instructions. The space is addressable by a 24-bit value
derived from either the 23-bit Program Counter (PC)
during program execution, or from table operation or
data space remapping as described in Section 4.4
“Interfacing Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (0x000000 to
0x7FFFFF). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24HJXXXGPX06A/X08A/
X10A family of devices are shown in Figure 4-1.
PROGRAM MEMORY MAP FOR PIC24HJXXXGPX06A/X08A/X10A FAMILY DEVICES
PIC24HJ64XXXXXA
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Memory Space
Program Address Space
User Program
Flash Memory
(22K instructions)
PIC24HJ128XXXXXA
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
PIC24HJ256XXXXXA
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(44K instructions)
User Program
Flash Memory
(88K instructions)
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x00ABFE
0x00AC00
0x0157FE
0x015800
Unimplemented
(Read ‘0’s)
Unimplemented
0x02ABFE
0x02AC00
(Read ‘0’s)
Unimplemented
(Read ‘0’s)
Configuration Memory Space
0x7FFFFE
0x800000
Reserved
Reserved
Reserved
Device Configuration
Registers
Device Configuration
Registers
Device Configuration
Registers
Reserved
Reserved
Reserved
DEVID (2)
DEVID (2)
DEVID (2)
2009-2012 Microchip Technology Inc.
0xF7FFFE
0xF80000
0xF80017
0xF80010
0xFEFFFE
0xFF0000
0xFFFFFE
DS70592D-page 29
PIC24HJXXXGPX06A/X08A/X10A
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.2
All PIC24HJXXXGPX06A/X08A/X10A devices reserve
the addresses between 0x00000 and 0x000200 for
hard-coded program execution vectors. A hardware
Reset vector is provided to redirect code execution
from the default value of the PC on device Reset to the
actual start of code. A GOTO instruction is programmed
by the user at 0x000000, with the actual address for the
start of code at 0x000002.
The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-2).
PIC24HJXXXGPX06A/X08A/X10A devices also have
two interrupt vector tables, located from 0x000004 to
0x0000FF and 0x000100 to 0x0001FF. These vector
tables allow each of the many device interrupt sources
to be handled by separate Interrupt Service Routines
(ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector
Table”.
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
FIGURE 4-2:
msw
Address
PROGRAM MEMORY ORGANIZATION
16
8
PC Address
(lsw Address)
0
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
DS70592D-page 30
least significant word
most significant word
23
0x000001
0x000003
0x000005
0x000007
INTERRUPT AND TRAP VECTORS
Instruction Width
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
4.2
Data Address Space
The PIC24HJXXXGPX06A/X08A/X10A CPU has a
separate 16-bit wide data memory space. The data
space is accessed using separate Address Generation
Units (AGUs) for read and write operations. Data memory maps of devices with different RAM sizes are
shown in Figure 4-3 and Figure 4-4.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA = 0) is used for
implemented memory addresses, while the upper half
(EA = 1) is reserved for the Program Space
Visibility area (see Section 4.4.3 “Reading Data from
Program Memory Using Program Space Visibility”).
PIC24HJXXXGPX06A/X08A/X10A devices implement
up to 16 Kbytes of data memory. Should an EA point to
a location outside of this area, an all-zero word or byte
will be returned.
4.2.1
DATA SPACE WIDTH
The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes of each word have even addresses, while the
Most Significant Bytes have odd addresses.
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCU
devices and improve data space memory usage
efficiency, the PIC24HJXXXGPX06A/X08A/X10A
instruction set supports both word and byte operations.
As a consequence of byte accessibility, all effective
address calculations are internally scaled to step
through word-aligned memory. For example, the core
recognizes that Post-Modified Register Indirect
Addressing mode [Ws++] will result in a value of Ws +
1 for byte operations and Ws + 2 for word operations.
Data byte reads will read the complete word that
contains the byte, using the Least Significant bit (LSb)
of any EA to determine which byte to select. The
selected byte is placed onto the Least Significant Byte
(LSB) of the data path. That is, data memory and registers are organized as two parallel byte-wide entities
with shared (word) address decode but separate write
lines. Data byte writes only write to the corresponding
side of the array or register which matches the byte
address.
2009-2012 Microchip Technology Inc.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed; if it occurred on a
write, the instruction will be executed but the write does
not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine
state prior to execution of the address Fault.
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte
(MSB) is not modified.
A sign-extend instruction (SE) is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the Most Significant Byte of any W register by
executing a zero-extend (ZE) instruction on the
appropriate address.
4.2.3
SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
PIC24HJXXXGPX06A/X08A/X10A core and peripheral
modules for controlling the operation of the device.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A complete listing of implemented
SFRs, including their addresses, is shown in Table 4-1
through Table 4-33.
Note:
4.2.4
The actual set of peripheral features and
interrupts varies by the device. Please
refer to the corresponding device tables
and pinout diagrams for device-specific
information.
NEAR DATA SPACE
The 8-Kbyte area between 0x0000 and 0x1FFF is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an Address Pointer.
DS70592D-page 31
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 4-3:
DATA MEMORY MAP FOR PIC24HJXXXGPX06A/X08A/X10A DEVICES WITH 8 KB
RAM
MSB
Address
MSB
2 Kbyte
SFR Space
LSB
Address
16 bits
LSB
0x0000
0x0001
SFR Space
0x07FE
0x0800
0x07FF
0x0801
8 Kbyte
Near
Data
Space
X Data RAM (X)
8 Kbyte
SRAM Space
0x1FFF
0x2001
0x27FF
0x2801
0x1FFE
0x2000
DMA RAM
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
DS70592D-page 32
0x27FE
0x2800
0xFFFE
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 4-4:
DATA MEMORY MAP FOR PIC24HJXXXGPX06A/X08A/X10A DEVICES WITH 16 KB RAM
MSB
Address
LSB
Address
16 bits
MSB
2 Kbyte
SFR Space
LSB
0x0000
0x0001
SFR Space
0x07FE
0x0800
0x07FF
0x0801
0x1FFF
8 Kbyte
Near
Data
Space
0x1FFE
X Data RAM (X)
16 Kbyte
SRAM Space
0x3FFF
0x4001
0x47FF
0x4801
0x3FFE
0x4000
DMA RAM
0x47FE
0x4800
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
4.2.5
DMA RAM
Every
PIC24HJXXXGPX06A/X08A/X10A
device
contains 2 Kbytes of dual ported DMA RAM located at
the end of data space. Memory locations in the DMA
RAM space are accessible simultaneously by the CPU
and the DMA controller module. DMA RAM is utilized by
the DMA controller to store data to be transferred to
various peripherals using DMA, as well as data
0xFFFE
transferred from various peripherals using DMA. The
DMA RAM can be accessed by the DMA controller
without having to steal cycles from the CPU.
When the CPU and the DMA controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.
Note:
2009-2012 Microchip Technology Inc.
DMA RAM can be used for general
purpose data storage if the DMA function
is not required in an application.
DS70592D-page 33
CPU CORE REGISTERS MAP
All
Resets
2009-2012 Microchip Technology Inc.
SFR Name
SFR
Addr
WREG0
0000
Working Register 0
xxxx
WREG1
0002
Working Register 1
xxxx
WREG2
0004
Working Register 2
xxxx
WREG3
0006
Working Register 3
xxxx
WREG4
0008
Working Register 4
xxxx
WREG5
000A
Working Register 5
xxxx
WREG6
000C
Working Register 6
xxxx
WREG7
000E
Working Register 7
xxxx
WREG8
0010
Working Register 8
xxxx
WREG9
0012
Working Register 9
xxxx
WREG10
0014
Working Register 10
xxxx
WREG11
0016
Working Register 11
xxxx
WREG12
0018
Working Register 12
xxxx
WREG13
001A
Working Register 13
xxxx
WREG14
001C
Working Register 14
xxxx
WREG15
001E
Working Register 15
0800
SPLIM
0020
Stack Pointer Limit Register
xxxx
PCL
002E
Program Counter Low Word Register
PCH
0030
—
—
—
—
—
—
—
—
Program Counter High Byte Register
0000
TBLPAG
0032
—
—
—
—
—
—
—
—
Table Page Address Pointer Register
0000
PSVPAG
0034
—
—
—
—
—
—
—
—
Program Memory Visibility Page Address Pointer Register
0000
RCOUNT
0036
SR
0042
—
—
—
—
—
—
—
DC
CORCON
0044
—
—
—
—
—
—
—
—
DISICNT
0052
—
—
BSRAM
0750
—
—
—
—
—
—
—
—
—
SSRAM
0752
—
—
—
—
—
—
—
—
—
Legend:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000
Repeat Loop Counter Register
xxxx
IPL
—
—
RA
N
OV
Z
C
0000
—
IPL3
PSV
—
—
0000
—
—
—
IW_BSR
IR_BSR
RL_BSR
0000
—
—
—
IW_SSR
IR_SSR
RL_SSR
0000
—
Disable Interrupts Counter Register
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
xxxx
PIC24HJXXXGPX06A/X08A/X10A
DS70592D-page 34
TABLE 4-1:
CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJXXXGPX10A DEVICES
SFR
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
CNEN1
0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CNEN2
0062
—
—
—
—
—
—
—
—
CN23IE
CN22IE
CN21IE
CN20IE
CN19IE
CN18IE
CNPU1
0068
CN8PUE
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CNPU2
006A
Legend:
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE
—
—
—
—
—
—
—
—
Bit 0
All
Resets
CN1IE
CN0IE
0000
CN17IE
CN16IE
0000
CN0PUE
0000
CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-3:
CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJXXXGPX08A DEVICES
SFR
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
CNEN1
0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CNEN2
0062
—
—
—
—
—
—
—
—
—
—
CN21IE
CN20IE
CN19IE
CN18IE
CNPU1
0068
CN8PUE
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CNPU2
006A
—
—
—
Legend:
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE
—
—
—
—
—
—
—
Bit 0
All
Resets
CN1IE
CN0IE
0000
CN17IE
CN16IE
0000
CN0PUE
0000
CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
0000
Bit 5
Bit 3
Bit 2
Bit 1
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-4:
CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJXXXGPX06A DEVICES
SFR
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
CNEN1
0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CNEN2
0062
—
—
—
—
—
—
—
—
—
—
CNPU1
0068
CN8PUE
CN7PUE
CN6PUE
CN5PUE
CNPU2
006A
—
—
—
Legend:
Bit 4
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE
—
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 5
Bit 0
All
Resets
CN1IE
CN0IE
0000
CN17IE
CN16IE
0000
CN0PUE
0000
CN18PUE CN17PUE CN16PUE
0000
Bit 4
Bit 3
CN5IE
CN4IE
CN3IE
CN2IE
CN21IE
CN20IE
—
CN18IE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN21PUE CN20PUE
—
Bit 2
Bit 1
DS70592D-page 35
PIC24HJXXXGPX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-2:
SFR
Name
INTERRUPT CONTROLLER REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
INTCON1
0080
NSTDIS
—
—
—
—
—
—
—
—
OSCFAIL
—
0000
INTCON2
0082
ALTIVT
DISI
—
—
—
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
IFS0
0084
—
DMA1IF
AD1IF
U1TXIF
U1RXIF
T3IF
T2IF
OC2IF
IC2IF
DMA0IF
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
DMA2IF
IC8IF
IC7IF
AD2IF
INT1IF
CNIF
—
MI2C1IF
SI2C1IF
0000
IFS2
0088
T6IF
DMA4IF
—
OC8IF
OC7IF
OC6IF
OC5IF
IC6IF
IC5IF
IC4IF
IC3IF
DMA3IF
C1IF
C1RXIF
SPI2IF
SPI2EIF
0000
IFS3
008A
—
—
DMA5IF
—
—
—
—
C2IF
C2RXIF
INT4IF
INT3IF
T9IF
T8IF
MI2C2IF
SI2C2IF
T7IF
0000
IFS4
008C
—
—
—
—
—
—
—
—
C2TXIF
C1TXIF
DMA7IF
DMA6IF
—
U2EIF
U1EIF
—
0000
IEC0
0094
—
DMA1IE
AD1IE
U1TXIE
U1RXIE
T3IE
T2IE
OC2IE
IC2IE
DMA0IE
T1IE
OC1IE
IC1IE
INT0IE
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
DMA2IE
IC8IE
IC7IE
AD2IE
INT1IE
CNIE
—
IEC2
0098
T6IE
DMA4IE
—
OC8IE
OC7IE
OC6IE
OC5IE
IC6IE
IC5IE
IC4IE
IC3IE
DMA3IE
C1IE
C1RXIE
SPI2IE
SPI2EIE
IEC3
009A
—
—
DMA5IE
—
—
—
—
C2IE
C2RXIE
INT4IE
INT3IE
T9IE
T8IE
MI2C2IE
SI2C2IE
T7IE
0000
IEC4
009C
—
—
—
—
—
—
—
—
C2TXIE
C1TXIE
DMA7IE
DMA6IE
—
U2EIE
U1EIE
—
0000
SPI1IF SPI1EIF
SPI1IE SPI1EIE
DIV0ERR DMACERR MATHERR ADDRERR STKERR
MI2C1IE SI2C1IE
0000
0000
0000
2009-2012 Microchip Technology Inc.
IPC0
00A4
—
T1IP
—
OC1IP
—
IC1IP
—
INT0IP
4444
IPC1
00A6
—
T2IP
—
OC2IP
—
IC2IP
—
DMA0IP
4444
IPC2
00A8
—
U1RXIP
—
SPI1IP
—
SPI1EIP
—
T3IP
4444
IPC3
00AA
—
—
DMA1IP
—
AD1IP
—
U1TXIP
0444
IPC4
00AC
—
CNIP
—
—
MI2C1IP
—
SI2C1IP
4044
IPC5
00AE
—
IC8IP
—
IC7IP
—
AD2IP
—
INT1IP
4444
IPC6
00B0
—
T4IP
—
OC4IP
—
OC3IP
—
DMA2IP
4444
IPC7
00B2
—
U2TXIP
—
U2RXIP
—
INT2IP
—
T5IP
4444
IPC8
00B4
—
C1IP
—
C1RXIP
—
SPI2IP
—
SPI2EIP
4444
IPC9
00B6
—
IC5IP
—
IC4IP
—
IC3IP
—
DMA3IP
4444
IPC10
00B8
—
OC7IP
—
OC6IP
—
OC5IP
—
IC6IP
4444
IPC11
00BA
—
T6IP
—
DMA4IP
—
—
OC8IP
4404
IPC12
00BC
—
T8IP
—
MI2C2IP
—
SI2C2IP
—
T7IP
4444
IPC13
00BE
—
C2RXIP
—
INT4IP
—
INT3IP
—
T9IP
4444
IPC14
00C0
—
—
—
—
—
—
—
—
—
—
C2IP
IPC15
00C2
—
—
—
—
—
—
—
—
—
DMA5IP
—
—
—
—
IPC16
00C4
—
—
—
—
—
U2EIP
—
U1EIP
—
—
—
—
IPC17
00C6
—
—
C1TXIP
—
DMA7IP
—
INTTREG
00E0
—
Legend:
—
—
—
C2TXIP
—
—
—
—
—
ILR
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
—
—
VECNUM
DMA6IP
0004
0040
0440
4444
0000
PIC24HJXXXGPX06A/X08A/X10A
DS70592D-page 36
TABLE 4-5:
SFR
Name
SFR
Addr
TIMER REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
TMR1
0100
Timer1 Register
PR1
0102
Period Register 1
T1CON
0104
TMR2
0106
TON
—
TSIDL
—
—
—
TMR3HLD 0108
—
—
—
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
FFFF
TGATE
TCKPS
—
TSYNC
TCS
—
0000
Timer2 Register
0000
Timer3 Holding Register (for 32-bit timer operations only)
xxxx
TMR3
010A
Timer3 Register
0000
PR2
010C
Period Register 2
FFFF
PR3
010E
Period Register 3
T2CON
0110
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
T3CON
0112
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
—
—
TCS
—
0000
TMR4
0114
Timer4 Register
0000
TMR5HLD
0116
Timer5 Holding Register (for 32-bit operations only)
xxxx
TMR5
0118
Timer5 Register
0000
PR4
011A
Period Register 4
FFFF
PR5
011C
Period Register 5
T4CON
011E
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
T5CON
0120
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
—
—
TCS
—
0000
TMR6
0122
TMR7HLD 0124
FFFF
FFFF
Timer6 Register
0000
Timer7 Holding Register (for 32-bit operations only)
xxxx
TMR7
0126
Timer7 Register
0000
PR6
0128
Period Register 6
FFFF
PR7
012A
Period Register 7
T6CON
012C
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
T7CON
012E
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
—
—
TCS
—
0000
TMR8
0130
TMR9HLD 0132
FFFF
Timer8 Register
0000
DS70592D-page 37
Timer9 Holding Register (for 32-bit operations only)
xxxx
TMR9
0134
Timer9 Register
0000
PR8
0136
Period Register 8
FFFF
PR9
0138
Period Register 9
T8CON
013A
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
T9CON
013C
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
—
—
TCS
—
0000
Legend:
FFFF
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
PIC24HJXXXGPX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-6:
SFR Name
SFR
Addr
IC1BUF
0140
IC1CON
0142
IC2BUF
0144
IC2CON
0146
IC3BUF
0148
IC3CON
014A
IC4BUF
014C
IC4CON
014E
IC5BUF
0150
IC5CON
0152
IC6BUF
0154
IC6CON
0156
IC7BUF
0158
IC7CON
015A
IC8BUF
015C
IC8CON
015E
Legend:
INPUT CAPTURE REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
—
ICSIDL
—
—
—
—
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
Input 1 Capture Register
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
0000
xxxx
Input 8 Capture Register
—
0000
xxxx
Input 7 Capture Register
—
0000
xxxx
Input 6 Capture Register
—
0000
xxxx
Input 5 Capture Register
—
0000
xxxx
Input 4 Capture Register
—
0000
xxxx
Input 3 Capture Register
—
All
Resets
xxxx
Input 2 Capture Register
—
Bit 0
0000
xxxx
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
0000
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
DS70592D-page 38
TABLE 4-7:
SFR Name
OUTPUT COMPARE REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
OC1RS
0180
Output Compare 1 Secondary Register
OC1R
0182
Output Compare 1 Register
OC1CON
0184
OC2RS
0186
Output Compare 2 Secondary Register
OC2R
0188
Output Compare 2 Register
OC2CON
018A
OC3RS
018C
Output Compare 3 Secondary Register
OC3R
018E
Output Compare 3 Register
OC3CON
0190
OC4RS
0192
Output Compare 4 Secondary Register
OC4R
0194
Output Compare 4 Register
OC4CON
0196
OC5RS
0198
Output Compare 5 Secondary Register
OC5R
019A
Output Compare 5 Register
OC5CON
019C
OC6RS
019E
Output Compare 6 Secondary Register
OC6R
01A0
Output Compare 6 Register
OC6CON
01A2
OC7RS
01A4
Output Compare 7 Secondary Register
OC7R
01A6
Output Compare 7 Register
OC7CON
01A8
OC8RS
01AA
Output Compare 8 Secondary Register
OC8R
01AC
Output Compare 8 Register
OC8CON
01AE
Legend:
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
OCFLT
OCTSEL
OCM
0000
DS70592D-page 39
PIC24HJXXXGPX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-8:
I2C1 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
I2C1RCV
0200
—
—
—
—
—
—
—
—
Receive Register
0000
I2C1TRN
0202
—
—
—
—
—
—
—
—
Transmit Register
00FF
I2C1BRG
0204
—
—
—
—
—
—
—
I2C1CON
0206
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
I2C1STAT
0208
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
0000
I2C1ADD
020A
—
—
—
—
—
—
Address Register
0000
I2C1MSK
020C
—
—
—
—
—
—
Address Mask Register
0000
SFR Name
Legend:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Baud Rate Generator Register
All
Resets
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-10:
I2C2 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
I2C2RCV
0210
—
—
—
—
—
—
—
—
Receive Register
0000
I2C2TRN
0212
—
—
—
—
—
—
—
—
Transmit Register
00FF
I2C2BRG
0214
—
—
—
—
—
—
—
I2C2CON
0216
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
I2C2STAT
0218
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
0000
I2C2ADD
021A
—
—
—
—
—
—
Address Register
0000
I2C2MSK
021C
—
—
—
—
—
—
Address Mask Register
0000
SFR Name
Legend:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Baud Rate Generator Register
All
Resets
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-11:
UART1 REGISTER MAP
2009-2012 Microchip Technology Inc.
SFR Name
SFR
Addr
U1MODE
0220
UARTEN
U1STA
0222
UTXISEL1
U1TXREG
0224
—
—
U1RXREG
0226
—
—
U1BRG
0228
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Bit 15
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
UEN1
UEN0
WAKE
LPBACK
UTXBF
TRMT
Bit 4
Bit 3
ABAUD
URXINV
BRGH
ADDEN
RIDLE
PERR
Bit 1
STSEL
0000
0110
—
USIDL
IREN
RTSMD
—
—
UTXBRK
UTXEN
—
—
—
—
—
UART Transmit Register
xxxx
—
—
—
—
—
UART Receive Register
0000
Baud Rate Generator Prescaler
Bit 2
URXDA
Bit 12
URXISEL
Bit 5
All
Resets
Bit 13
UTXINV UTXISEL0
Bit 11
Bit 0
Bit 14
PDSEL
FERR
OERR
0000
PIC24HJXXXGPX06A/X08A/X10A
DS70592D-page 40
TABLE 4-9:
SFR
Name
SFR
Addr
UART2 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
WAKE
LPBACK
Bit 5
Bit 4
Bit 3
ABAUD
URXINV
BRGH
ADDEN
RIDLE
PERR
Bit 2
Bit 1
All
Resets
STSEL
0000
URXDA
0110
U2MODE
0230
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
U2STA
0232
UTXISEL1
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
U2TXREG
0234
—
—
—
—
—
—
—
UART Transmit Register
xxxx
U2RXREG
0236
—
—
—
—
—
—
—
UART Receive Register
0000
U2BRG
0238
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-13:
SFR
Name
URXISEL
OERR
0000
SPI1 REGISTER MAP
Bit 15
Bit 14
Bit 13
SPI1STAT
0240
SPIEN
—
SPISIDL
—
—
—
—
SPI1CON1
0242
—
—
—
DISSCK
DISSDO
MODE16
SMP
SPI1CON2
0244
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
SPI1BUF
0248
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
—
—
CKE
SSEN
SPIROV
—
—
CKP
MSTEN
—
—
—
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
SPITBF
SPIRBF
0000
SPRE
—
—
PPRE
—
FRMDLY
—
SPI1 Transmit and Receive Buffer Register
0000
0000
0000
SPI2 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
SPI2STAT
0260
SPIEN
—
SPISIDL
—
—
—
—
SPI2CON1
0262
—
—
—
DISSCK
DISSDO
MODE16
SMP
SPI2CON2
0264
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
SPI2BUF
0268
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
SFR Name
FERR
Baud Rate Generator Prescaler
SFR
Addr
TABLE 4-14:
PDSEL
Bit 0
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
—
—
CKE
SSEN
SPIROV
—
—
CKP
MSTEN
—
—
—
SPI2 Transmit and Receive Buffer Register
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
SPITBF
SPIRBF
0000
SPRE
—
—
PPRE
—
FRMDLY
—
0000
0000
0000
DS70592D-page 41
PIC24HJXXXGPX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-12:
File Name
ADC1 REGISTER MAP
Addr
ADC1BUF0
0300
AD1CON1
0320
AD1CON2
0322
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
ADON
—
ADSIDL
ADDMABM
—
AD12B
FORM
—
—
CSCNA
CHPS
—
—
Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
—
SIMSAM
ASAM
SAMP
DONE
0000
BUFM
ALTS
0000
CH123SA
0000
ADC Data Buffer 0
VCFG
AD1CON3
0324
ADRC
—
—
AD1CHS123
0326
—
—
—
—
xxxx
SSRC
BUFS
—
CH123SB
—
—
SMPI
SAMC
ADCS
CH123NB
All
Resets
Bit 4
—
—
—
0000
CH123NA
AD1CHS0
0328
CH0NB
CH0NA
—
—
AD1PCFGH(1)
032A
PCFG31 PCFG30
PCFG29
PCFG28
PCFG27 PCFG26 PCFG25
PCFG24
PCFG23
PCFG22
PCFG21
PCFG20
PCFG19 PCFG18 PCFG17
AD1PCFGL
032C
PCFG15 PCFG14
PCFG13
PCFG12
PCFG11 PCFG10
PCFG9
PCFG8
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
AD1CSSH(1)
032E
CSS31
CSS30
CSS29
CSS28
CSS27
CSS26
CSS25
CSS24
CSS23
CSS22
CSS21
CSS20
CSS19
AD1CSSL
0330
CSS15
CSS14
CSS13
CSS12
CSS11
CSS10
CSS9
CSS8
CSS7
CSS6
CSS5
CSS4
CSS3
AD1CON4
0332
—
—
—
—
—
—
—
—
—
—
—
—
—
Reserved
0334033E
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
SIMSAM
ASAM
SAMP
DONE
0000
BUFM
ALTS
0000
Legend:
Note 1:
—
CH0SB
0000
PCFG16
0000
PCFG1
PCFG0
0000
CSS18
CSS17
CSS16
0000
CSS2
CSS1
CSS0
DMABL
0000
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Not all ANx inputs are available on all devices. See the device pin diagrams for available ANx inputs.
TABLE 4-16:
File Name
Addr
ADC2BUF0
0340
AD2CON1
0360
AD2CON2
0362
ADC2 REGISTER MAP
2009-2012 Microchip Technology Inc.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
ADON
—
ADSIDL
ADDMABM
—
AD12B
FORM
Bit 9
Bit 8
—
—
CSCNA
CHPS
—
Bit 7
Bit 6
ADC Data Buffer 0
VCFG
AD2CON3
0364
ADRC
—
—
AD2CHS123
0366
—
—
—
—
AD2CHS0
0368
CH0NB
—
—
—
Reserved
036A
—
—
—
—
AD2PCFGL
036C
PCFG13
PCFG12
Reserved
036E
—
—
—
—
—
—
AD2CSSL
0370
CSS15
CSS14
CSS13
CSS12
CSS11
AD2CON4
0372
—
—
—
—
Reserved
0374037E
—
—
—
—
Legend:
CH0SA
PCFG15 PCFG14
xxxx
SSRC
BUFS
—
SMPI
—
—
—
—
CH0NA
—
—
—
SAMC
ADCS
CH123NB
CH123SB
CH0SB
—
—
—
0000
CH123NA
CH123SA
0000
CH0SA
0000
—
—
—
—
—
—
—
—
—
—
0000
PCFG9
PCFG8
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000
—
—
—
—
—
—
—
—
—
—
0000
CSS10
CSS9
CSS8
CSS7
CSS6
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PCFG11 PCFG10
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
DMABL
—
—
0000
0000
—
0000
PIC24HJXXXGPX06A/X08A/X10A
DS70592D-page 42
TABLE 4-15:
File Name Addr
DMA REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DMA0CON 0380
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
—
DMA0REQ 0382
FORCE
—
—
—
—
—
—
—
—
Bit 5
Bit 4
AMODE
Bit 3
Bit 2
—
—
Bit 1
Bit 0
MODE
IRQSEL
All
Resets
0000
0000
DMA0STA
0384
STA
0000
DMA0STB
0386
STB
0000
DMA0PAD
0388
PAD
DMA0CNT
038A
—
—
—
—
—
—
DMA1CON 038C
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA1REQ 038E
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA1STA
0390
STA
0000
DMA1STB
0392
STB
0000
DMA1PAD
0394
PAD
DMA1CNT
0396
—
—
—
—
—
—
DMA2CON 0398
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA2REQ 039A
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA2STA
039C
STA
0000
DMA2STB
039E
STB
0000
DMA2PAD
03A0
PAD
DMA2CNT
03A2
—
—
—
—
—
—
DMA3CON 03A4
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA3REQ 03A6
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA3STA
03A8
STA
0000
DMA3STB
03AA
STB
0000
DMA3PAD 03AC
PAD
DMA3CNT 03AE
—
—
—
—
—
—
DMA4CON 03B0
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA4REQ 03B2
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA4STA
03B4
STA
0000
DMA4STB
03B6
STB
0000
DMA4PAD
03B8
PAD
DS70592D-page 43
DMA4CNT 03BA
—
—
—
—
—
—
DMA5CON 03BC
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA5REQ 03BE
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
IRQSEL
—
MODE
0000
0000
DMA5STA
03C0
STA
0000
DMA5STB
03C2
STB
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
PIC24HJXXXGPX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-17:
File Name Addr
DMA REGISTER MAP (CONTINUED)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
DMA5CNT 03C6
—
—
—
—
—
—
DMA6CON 03C8
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
—
—
—
—
—
—
—
—
DMA5PAD
Bit 9
Bit 8
03C4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PAD
DMA6REQ 03CA FORCE
All
Resets
0000
CNT
—
0000
AMODE
—
—
MODE
IRQSEL
0000
0000
DMA6STA
03CC
STA
0000
DMA6STB
03CE
STB
0000
DMA6PAD
03D0
PAD
DMA6CNT 03D2
—
—
—
—
—
—
DMA7CON 03D4
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA7REQ 03D6
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
0000
AMODE
—
—
MODE
IRQSEL
0000
0000
DMA7STA
03D8
STA
0000
DMA7STB
03DA
STB
0000
DMA7PAD 03DC
PAD
DMA7CNT 03DE
—
—
—
—
—
CNT
DMACS0
03E0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0
DMACS1
03E2
DSADR
03E4
Legend:
—
—
—
XWCOL7
LSTCH
XWCOL6 XWCOL5
PPST7
PPST6
0000
XWCOL4
XWCOL3
XWCOL2
PPST4
PPST3
PPST2
PPST5
XWCOL1 XWCOL0
PPST1
PPST0
DSADR
0000
0000
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-18:
File Name
—
0000
—
ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 OR 1 FOR PIC24HJXXXGP506A/510A/610A DEVICES ONLY
2009-2012 Microchip Technology Inc.
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
C1CTRL1
0400
—
—
CSIDL
ABAT
—
C1CTRL2
0402
—
—
—
—
—
—
—
—
—
—
C1VEC
0404
C1FCTRL
0406
C1FIFO
0408
—
—
DMABS
Bit 10
Bit 9
Bit 8
Bit 7
—
—
—
—
—
REQOP
—
Bit 5
OPMODE
FILHIT
—
Bit 6
—
—
—
—
—
—
—
Bit 4
Bit 3
—
CANCAP
Bit 1
Bit 0
—
—
WIN
DNCNT
—
FBP
Bit 2
All
Resets
0480
0000
ICODE
0000
FSA
0000
FNRB
0000
C1INTF
040A
—
—
TXBO
TXBP
RXBP
TXWAR
RXWAR
EWARN
IVRIF
WAKIF
ERRIF
—
FIFOIF
RBOVIF
RBIF
TBIF
0000
C1INTE
040C
—
—
—
—
—
—
—
—
IVRIE
WAKIE
ERRIE
—
FIFOIE
RBOVIE
RBIE
TBIE
0000
C1EC
040E
C1CFG1
0410
—
—
—
—
—
C1CFG2
0412
—
WAKFIL
—
—
—
C1FEN1
0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10
TERRCNT
RERRCNT
—
—
—
SEG2PH
FLTEN9
FLTEN8
SJW
SEG2PHTS
SAM
FLTEN7
FLTEN6
0000
BRP
SEG1PH
FLTEN5
FLTEN4
0000
PRSEG
FLTEN3
FLTEN2
FLTEN1
FLTEN0
0000
FFFF
C1FMSKSEL1 0418
F7MSK
F6MSK
F5MSK
F4MSK
F3MSK
F2MSK
F1MSK
F0MSK
0000
C1FMSKSEL2 041A
F15MSK
F14MSK
F13MSK
F12MSK
F11MSK
F10MSK
F9MSK
F8MSK
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
PIC24HJXXXGPX06A/X08A/X10A
DS70592D-page 44
TABLE 4-17:
File Name
ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 FOR PIC24HJXXXGP506A/510A/610A DEVICES ONLY
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
0400041E
Bit 8
Bit 7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RXFUL5
RXFUL4
RXFUL3
RXFUL2
RXFUL1
Bit 6
See definition when WIN = x
C1RXFUL1
0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9
RXFUL0
0000
C1RXFUL2
0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16
0000
C1RXOVF1
0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9
RXOVF0
0000
C1RXOVF2
042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16
0000
C1TR01CO
N
0430
TXEN1
TX
ABT1
TX
LARB1
TX
ERR1
TX
REQ1
RTREN1
TX1PRI
TXEN0
TX
ABAT0
TX
LARB0
TX
ERR0
TX
REQ0
RTREN0
TX0PRI
0000
C1TR23CO
N
0432
TXEN3
TX
ABT3
TX
LARB3
TX
ERR3
TX
REQ3
RTREN3
TX3PRI
TXEN2
TX
ABAT2
TX
LARB2
TX
ERR2
TX
REQ2
RTREN2
TX2PRI
0000
C1TR45CO
N
0434
TXEN5
TX
ABT5
TX
LARB5
TX
ERR5
TX
REQ5
RTREN5
TX5PRI
TXEN4
TX
ABAT4
TX
LARB4
TX
ERR4
TX
REQ4
RTREN4
TX4PRI
0000
C1TR67CO
N
0436
TXEN7
TX
ABT7
TX
LARB7
TX
ERR7
TX
REQ7
RTREN7
TX7PRI
TXEN6
TX
ABAT6
TX
LARB6
TX
ERR6
TX
REQ6
RTREN6
TX6PRI
xxxx
C1RXD
0440
Recieved Data Word
xxxx
C1TXD
0442
Transmit Data Word
xxxx
Legend:
RXOVF8
RXFUL7
RXOVF7
RXFUL6
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-20:
File Name
RXFUL8
ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 FOR PIC24HJXXXGP506A/510A/610A DEVICES ONLY
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
0400041E
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
See definition when WIN = x
DS70592D-page 45
C1BUFPNT1
0420
F3BP
F2BP
F1BP
F0BP
0000
C1BUFPNT2
0422
F7BP
F6BP
F5BP
F4BP
0000
C1BUFPNT3
0424
F11BP
F10BP
F9BP
F8BP
0000
C1BUFPNT4
0426
F15BP
F14BP
F13BP
F12BP
0000
C1RXM0SID
0430
SID
—
EID
xxxx
C1RXM0EID
0432
EID
C1RXM1SID
0434
SID
—
EID
C1RXM1EID
0436
EID
C1RXM2SID
0438
SID
—
EID
C1RXM2EID
043A
EID
C1RXF0SID
0440
SID
—
EID
C1RXF0EID
0442
EID
C1RXF1SID
0444
SID
—
EID
Legend:
SID
—
MIDE
EID
SID
—
MIDE
xxxx
EID
SID
—
MIDE
xxxx
EID
SID
—
EXIDE
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
—
EXIDE
xxxx
xxxx
EID
SID
xxxx
xxxx
xxxx
xxxx
PIC24HJXXXGPX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-19:
File Name
ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 FOR PIC24HJXXXGP506A/510A/610A DEVICES ONLY (CONTINUED)
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
2009-2012 Microchip Technology Inc.
C1RXF1EID
0446
EID
C1RXF2SID
0448
SID
C1RXF2EID
044A
EID
C1RXF3SID
044C
SID
C1RXF3EID
044E
EID
C1RXF4SID
0450
SID
C1RXF4EID
0452
EID
C1RXF5SID
0454
SID
C1RXF5EID
0456
EID
C1RXF6SID
0458
SID
C1RXF6EID
045A
EID
C1RXF7SID
045C
SID
C1RXF7EID
045E
EID
C1RXF8SID
0460
SID
C1RXF8EID
0462
EID
C1RXF9SID
0464
SID
C1RXF9EID
0466
EID
C1RXF10SID
0468
SID
C1RXF10EID
046A
EID
C1RXF11SID
046C
SID
C1RXF11EID
046E
EID
C1RXF12SID
0470
SID
C1RXF12EID
0472
EID
C1RXF13SID
0474
SID
C1RXF13EID
0476
EID
C1RXF14SID
0478
SID
C1RXF14EID
047A
EID
C1RXF15SID
047C
SID
C1RXF15EID
047E
EID
Legend:
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EID
SID
—
EXIDE
xxxx
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
EID
SID
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
—
EXIDE
EID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
All
Resets
xxxx
xxxx
xxxx
xxxx
PIC24HJXXXGPX06A/X08A/X10A
DS70592D-page 46
TABLE 4-20:
File Name
ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0 OR 1 FOR PIC24HJ256GP610A DEVICES ONLY
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
C2CTRL1
0500
—
—
CSIDL
ABAT
—
C2CTRL2
0502
—
—
—
—
—
C2VEC
0504
—
—
—
C2FCTRL
0506
C2FIFO
0508
—
—
C2INTF
050A
—
—
TXBO
C2INTE
050C
—
—
—
C2EC
050E
Bit 10
Bit 9
Bit 8
Bit 7
—
—
REQOP
—
—
—
—
—
—
TXWAR
—
—
—
Bit 3
—
CANCAP
—
RXWAR EWARN
—
—
Bit 2
Bit 1
Bit 0
All
Resets
—
—
WIN
0480
DNCNT
0000
ICODE
—
—
—
—
IVRIF
WAKIF
ERRIF
IVRIE
WAKIE
ERRIE
FBP
RXBP
—
Bit 4
—
—
TXBP
Bit 5
OPMODE
FILHIT
DMABS
Bit 6
—
0000
FSA
0000
FNRB
TERRCNT
0000
—
FIFOIF
RBOVIF
RBIF
TBIF
—
FIFOIE
RBOVIE
RBIE
TBIE
RERRCNT
0000
0000
0000
C2CFG1
0510
—
—
—
—
—
C2CFG2
0512
—
WAKFIL
—
—
—
SEG2PH
SEG2PHTS
C2FEN1
0514
FLTEN15
FLTEN14
FLTEN13
FLTEN12
FLTEN11
FLTEN10 FLTEN9 FLTEN8
FLTEN7
C2FMSKSEL1
0518
F7MSK
F6MSK
F5MSK
F4MSK
F3MSK
F2MSK
F1MSK
F0MSK
0000
C2FMSKSEL2
051A
F15MSK
F14MSK
F13MSK
F12MSK
F11MSK
F10MSK
F9MSK
F8MSK
0000
Legend:
—
—
SJW
BRP
SAM
SEG1PH
0000
PRSEG
FLTEN6 FLTEN5 FLTEN4 FLTEN3
FLTEN2 FLTEN1
0000
FLTEN0
FFFF
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-22:
File Name
—
Addr
ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0 FOR PIC24HJ256GP610A DEVICES ONLY
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
0500051E
Bit 9
Bit 8
Bit 7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RXFUL5
RXFUL4
RXFUL3
RXFUL2
RXFUL1
Bit 6
See definition when WIN = x
C2RXFUL1
0520 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10
RXFUL0
0000
C2RXFUL2
0522 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16
RXFUL9
RXFUL8
RXFUL7
RXFUL6
0000
C2RXOVF1
0528 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF09 RXOVF08 RXOVF7
RXOVF0
0000
C2RXOVF2
052A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16
0000
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
DS70592D-page 47
C2TR01CON 0530
TXEN1
TX
ABAT1
TX
LARB1
TX
ERR1
TX
REQ1
RTREN1
TX1PRI
TXEN0
TX
ABAT0
TX
LARB0
TX
ERR0
TX
REQ0
RTREN0
TX0PRI
0000
C2TR23CON 0532
TXEN3
TX
ABAT3
TX
LARB3
TX
ERR3
TX
REQ3
RTREN3
TX3PRI
TXEN2
TX
ABAT2
TX
LARB2
TX
ERR2
TX
REQ2
RTREN2
TX2PRI
0000
C2TR45CON 0534
TXEN5
TX
ABAT5
TX
LARB5
TX
ERR5
TX
REQ5
RTREN5
TX5PRI
TXEN4
TX
ABAT4
TX
LARB4
TX
ERR4
TX
REQ4
RTREN4
TX4PRI
0000
C2TR67CON 0536
TXEN7
TX
ABAT7
TX
LARB7
TX
ERR7
TX
REQ7
RTREN7
TX7PRI
TXEN6
TX
ABAT6
TX
LARB6
TX
ERR6
TX
REQ6
RTREN6
TX6PRI
xxxx
C2RXD
0540
Recieved Data Word
xxxx
C2TXD
0542
Transmit Data Word
xxxx
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
PIC24HJXXXGPX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-21:
File Name
ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR PIC24HJ256GP610A DEVICES ONLY
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
0500051E
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
See definition when WIN = x
2009-2012 Microchip Technology Inc.
C2BUFPNT1
0520
F3BP
F2BP
F1BP
F0BP
0000
C2BUFPNT2
0522
F7BP
F6BP
F5BP
F4BP
0000
C2BUFPNT3
0524
F12BP
F10BP
F9BP
F8BP
0000
C2BUFPNT4
0526
F15BP
F14BP
F13BP
F12BP
0000
C2RXM0SID
0530
SID
—
EID
xxxx
C2RXM0EID
0532
EID
C2RXM1SID
0534
SID
—
EID
C2RXM1EID
0536
EID
C2RXM2SID
0538
SID
—
EID
C2RXM2EID
053A
EID
C2RXF0SID
0540
SID
—
EID
C2RXF0EID
0542
EID
C2RXF1SID
0544
SID
—
EID
C2RXF1EID
0546
EID
C2RXF2SID
0548
SID
—
EID
C2RXF2EID
054A
EID
C2RXF3SID
054C
SID
—
EID
C2RXF3EID
054E
EID
C2RXF4SID
0550
SID
—
EID
C2RXF4EID
0552
EID
C2RXF5SID
0554
SID
—
EID
C2RXF5EID
0556
EID
C2RXF6SID
0558
SID
—
EID
C2RXF6EID
055A
EID
C2RXF7SID
055C
SID
—
EID
C2RXF7EID
055E
EID
C2RXF8SID
0560
SID
—
EID
C2RXF8EID
0562
EID
C2RXF9SID
0564
SID
—
EID
C2RXF9EID
0566
EID
C2RXF10SID
0568
SID
—
EID
C2RXF10EID
056A
EID
C2RXF11SID
056C
SID
—
EID
Legend:
SID
—
MIDE
EID
SID
—
MIDE
xxxx
EID
SID
—
MIDE
xxxx
EID
SID
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
—
EXIDE
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
xxxx
xxxx
PIC24HJXXXGPX06A/X08A/X10A
DS70592D-page 48
TABLE 4-23:
ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR PIC24HJ256GP610A DEVICES ONLY (CONTINUED)
File Name
Addr
C2RXF11EID
056E
EID
C2RXF12SID
0570
SID
C2RXF12EID
0572
EID
C2RXF13SID
0574
SID
C2RXF13EID
0576
EID
C2RXF14SID
0578
SID
C2RXF14EID
057A
EID
C2RXF15SID
057C
SID
C2RXF15EID
057E
EID
Legend:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EID
SID
—
EXIDE
xxxx
—
EID
—
EID
—
EID
—
EID
EID
SID
—
EXIDE
—
EXIDE
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
—
EXIDE
EID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
All
Resets
xxxx
xxxx
xxxx
xxxx
DS70592D-page 49
PIC24HJXXXGPX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-23:
File Name
PORTA REGISTER MAP(1)
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISA9
—
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
F6FF
RA9
—
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx
LATA10
LATA9
—
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
xxxx
—
—
—
—
—
ODCA5
ODCA4
ODCA3
ODCA2
ODCA1
ODCA0
0000
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
TRISA
02C0
TRISA15
TRISA14
TRISA13
TRISA12
—
TRISA10
PORTA
02C2
RA15
RA14
RA13
RA12
—
RA10
LATA
02C4
LATA15
LATA14
LATA13
LATA12
—
ODCA
06C0
ODCA15
ODCA14
—
—
—
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
TABLE 4-25:
PORTB REGISTER MAP(1)
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISB
02C6
TRISB15
TRISB14
TRISB13
TRISB12
TRISB11
TRISB10
TRISB9
TRISB8
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
FFFF
PORTB
02C8
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx
LATB
02CA
LATB15
LATB14
LATB13
LATB12
LATB11
LATB10
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
File Name
TABLE 4-26:
PORTC REGISTER MAP(1)
Bit 14
Bit 13
Bit 12
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
—
—
—
—
TRISC4
TRISC3
TRISC2
TRISC1
—
F01E
—
—
—
—
—
—
—
RC4
RC3
RC2
RC1
—
xxxx
—
—
—
—
—
—
—
LATC4
LATC3
LATC2
LATC1
—
xxxx
2009-2012 Microchip Technology Inc.
Addr
TRISC
02CC
PORTC
02CE
RC15
RC14
RC13
RC12
LATC
02D0
LATC15
LATC14
LATC13
LATC12
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
TABLE 4-27:
Bit 15
Bit 11
File Name
TRISC15 TRISC14 TRISC13 TRISC12
PORTD REGISTER MAP(1)
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISD
02D2
TRISD15
TRISD14
TRISD13
TRISD12
TRISD11
TRISD10
TRISD9
TRISD8
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
FFFF
PORTD
02D4
RD15
RD14
RD13
RD12
RD11
RD10
RD9
RD8
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx
LATD
02D6
LATD15
LATD14
LATD13
LATD12
LATD11
LATD10
LATD9
LATD8
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx
ODCD
06D2
ODCD15
ODCD14
ODCD13
ODCD12
ODCD11
ODCD10
ODCD9
ODCD8
ODCD7
ODCD6
ODCD5
ODCD4
ODCD3
ODCD2
ODCD1
ODCD0
0000
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
PIC24HJXXXGPX06A/X08A/X10A
DS70592D-page 50
TABLE 4-24:
PORTE REGISTER MAP(1)
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISE
02D8
—
—
—
—
—
—
—
—
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
00FF
PORTE
02DA
—
—
—
—
—
—
—
—
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
xxxx
LATE
02DC
—
—
—
—
—
—
—
—
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
xxxx
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
File Name
TABLE 4-29:
PORTF REGISTER MAP(1)
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
TRISF
02DE
—
—
TRISF13
TRISF12
—
—
—
TRISF8
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0
31FF
PORTF
02E0
—
—
RF13
RF12
—
—
—
RF8
RF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
xxxx
LATF
02E2
—
—
LATF13
LATF12
—
—
—
LATF8
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
xxxx
ODCF(2)
06DE
—
—
ODCF13
ODCF12
—
—
—
ODCF8
ODCF7
ODCF6
ODCF5
ODCF4
ODCF3
ODCF2
ODCF1
ODCF0
0000
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
TABLE 4-30:
PORTG REGISTER MAP(1)
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISG
02E4
TRISG15
TRISG14
TRISG13
TRISG12
—
—
TRISG9
TRISG8
TRISG7
TRISG6
—
—
TRISG3
TRISG2
TRISG1
TRISG0
F3CF
PORTG
02E6
RG15
RG14
RG13
RG12
—
—
RG9
RG8
RG7
RG6
—
—
RG3
RG2
RG1
RG0
xxxx
LATG
02E8
LATG15
LATG14
LATG13
LATG12
—
—
LATG9
LATG8
LATG7
LATG6
—
—
LATG3
LATG2
LATG1
LATG0
xxxx
ODCG(2)
06E4
ODCG15
ODCG14
ODCG13
ODCG12
—
—
ODCG9
ODCG8
ODCG7
ODCG6
—
—
ODCG3
ODCG2
ODCG1
ODCG0
0000
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
File Name
DS70592D-page 51
PIC24HJXXXGPX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-28:
SYSTEM CONTROL REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RCON
0740
TRAPR
IOPUWR
—
—
—
—
—
VREGS
EXTR
SWR
SWDTEN
WDTO
SLEEP
IDLE
BOR
POR
xxxx(1)
OSCCON
0742
—
CLKLOCK
—
LOCK
—
CF
—
LPOSCEN
OSWEN
0300(2)
COSC
—
CLKDIV
0744
ROI
PLLFBD
0746
—
—
—
—
—
—
—
OSCTUN
0748
—
—
—
—
—
—
—
Legend:
Note 1:
2:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
TABLE 4-32:
File Name
DOZE
NOSC
DOZEN
FRCDIV
Bit 15
Bit 14
Bit 13
NVMCON
0760
WR
WREN
WRERR
—
—
—
NVMKEY
0766
—
—
—
—
—
—
PLLPRE
3040
PLLDIV
—
—
0030
—
TUN
0000
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
—
—
—
ERASE
—
—
—
Bit 4
Bit 3
—
Bit 2
Bit 1
Bit 0
All
Resets
0000(1)
NVMOP
NVMKEY
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-33:
File Name
—
NVM REGISTER MAP
Addr
Legend:
Note 1:
PLLPOST
Addr
PMD REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PMD1
0770
T5MD
T4MD
T3MD
T2MD
T1MD
—
—
—
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
C2MD
C1MD
AD1MD
0000
PMD2
0772
IC8MD
IC7MD
IC6MD
IC5MD
IC4MD
IC3MD
IC2MD
IC1MD
OC8MD
OC7MD
OC6MD
OC5MD
OC4MD
OC3MD
OC2MD
OC1MD
0000
PMD3
0774
T9MD
T8MD
T7MD
T6MD
—
—
—
—
—
—
—
—
—
—
I2C2MD
AD2MD
0000
2009-2012 Microchip Technology Inc.
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
PIC24HJXXXGPX06A/X08A/X10A
DS70592D-page 52
TABLE 4-31:
PIC24HJXXXGPX06A/X08A/X10A
4.2.6
4.2.7
SOFTWARE STACK
In addition to its use as a working register, the W15
register in the PIC24HJXXXGPX06A/X08A/X10A
devices is also used as a software Stack Pointer. The
Stack Pointer always points to the first available free
word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for
stack pushes, as shown in Figure 4-5. For a PC push
during any CALL instruction, the MSB of the PC is zeroextended before the push, ensuring that the MSB is
always clear.
Note:
A PC push during exception processing
concatenates the SRL register to the MSB
of the PC prior to the push.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM is forced to ‘0’
because all stack operations must be word-aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error
trap will not occur. The stack error trap will occur on a
subsequent push operation. Thus, for example, if it is
desirable to cause a stack error trap when the stack
grows beyond address 0x2000 in RAM, initialize the
SPLIM with the value 0x1FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-5:
Stack Grows Towards
Higher Address
0x0000
CALL STACK FRAME
15
0
PC
000000000 PC
The PIC24H product family supports Data RAM protection features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessible only from the Boot Segment Flash code, when enabled. SSRAM (Secure
RAM segment for RAM) is accessible only from the
Secure Segment Flash code, when enabled. See
Table 4-1 for an overview of the BSRAM and SSRAM
SFRs.
4.3
Instruction Addressing Modes
The addressing modes in Table 4-34 form the basis of
the addressing modes optimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
4.3.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (Near Data Space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
4.3.2
MCU INSTRUCTIONS
The 3-operand MCU instructions are of the form:
Operand 3 = Operand 1 Operand 2
where:
Operand 1 is always a working register (i.e., the
addressing mode can only be Register Direct) which is
referred to as Wb.
Operand 2 can be a W register, fetched from data
memory, or a 5-bit literal. The result location can be
either a W register or a data memory location. The following addressing modes are supported by MCU
instructions:
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
5-bit or 10-bit Literal
Note:
2009-2012 Microchip Technology Inc.
DATA RAM PROTECTION FEATURE
Not all instructions support all the
addressing
modes
given
above.
Individual instructions may support
different subsets of these addressing
modes.
DS70592D-page 53
PIC24HJXXXGPX06A/X08A/X10A
TABLE 4-34:
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
Description
File Register Direct
The address of the file register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the EA.
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
4.3.3
The sum of Wn and a literal forms the EA.
MOVE INSTRUCTIONS
Move instructions provide a greater degree of addressing flexibility than other instructions. In addition to the
Addressing modes supported by most MCU instructions, move instructions also support Register Indirect
with Register Offset Addressing mode, also referred to
as Register Indexed mode.
Note:
For the MOV instructions, the Addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (Register Offset)
field is shared between both source and
destination (but typically only used by
one).
In summary, the following Addressing modes are
supported by move instructions:
•
•
•
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
Note:
4.3.4
Not all instructions support all the
Addressing
modes
given
above.
Individual instructions may support
different subsets of these Addressing
modes.
OTHER INSTRUCTIONS
Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, the source of an operand or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
DS70592D-page 54
4.4
Interfacing Program and Data
Memory Spaces
The PIC24HJXXXGPX06A/X08A/X10A architecture
uses a 24-bit wide program space and a 16-bit wide
data space. The architecture is also a modified Harvard
scheme, meaning that data can also be present in the
program space. To use this data successfully, it must
be accessed in a way that preserves the alignment of
information in both spaces.
Aside
from
normal
execution,
the
PIC24HJXXXGPX06A/X08A/X10A architecture provides two methods by which program space can be
accessed during operation:
• Using table instructions to access individual bytes
or words anywhere in the program space
• Remapping a portion of the program space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated from time to time. It also allows
access to all bytes of the program word. The remapping method allows an application to access a large
block of data on a read-only basis, which is ideal for
look ups from a large table of static data. It can only
access the least significant word of the program word.
4.4.1
ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the Most Significant bit of TBLPAG is used
to determine if the operation occurs in the user memory
(TBLPAG = 0) or the configuration memory
(TBLPAG = 1).
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the Most
Significant bit of the EA is ‘1’, PSVPAG is concatenated
with the lower 15 bits of the EA to form a 23-bit program
space address. Unlike table operations, this limits
remapping operations strictly to the user memory area.
TABLE 4-35:
Table 4-35 and Figure 4-6 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P refers to a program
space word, whereas D refers to a data space
word.
PROGRAM SPACE ADDRESS CONSTRUCTION
Access
Space
Access Type
Program Space Address
Instruction Access
(Code Execution)
User
TBLRD/TBLWT
(Byte/Word Read/Write)
User
TBLPAG
Configuration
TBLPAG
Data EA
1xxx xxxx
xxxx xxxx xxxx xxxx
Program Space Visibility
(Block Remap/Read)
Note 1:
PC
0
0xxx
xxxx
0xxx xxxx
User
xxxx
0
xxxx
xxxx xxx0
Data EA
xxxx xxxx xxxx xxxx
0
PSVPAG
0
xxxx xxxx
Data EA(1)
xxx xxxx xxxx xxxx
Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG.
2009-2012 Microchip Technology Inc.
DS70592D-page 55
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 4-6:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
0
0
23 bits
EA
Table Operations(2)
1/0
1/0
TBLPAG
8 bits
16 bits
24 bits
Select
Program Space Visibility(1)
(Remapping)
0
EA
1
0
PSVPAG
8 bits
15 bits
23 bits
User/Configuration
Space Select
Byte Select
Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word
alignment of data in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted
in the configuration memory space.
DS70592D-page 56
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
4.4.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
2.
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going
through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper
8 bits of a program space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit,
word wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word and TBLRDH and TBLWTH access the space
which contains the upper data byte.
Two table instructions are provided to move byte or
word sized (16-bit) data to and from program space.
Both function as either byte or word operations.
1.
TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space
location (P) to a data address (D).
TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
(P) to a data address. Note that
D, the ‘phantom byte’, will always be ‘0’.
In Byte mode, it maps the upper or lower byte of
the program word to D of the data
address, as above. Note that the data will
always be ‘0’ when the upper ‘phantom’ byte is
selected (Byte Select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user and configuration spaces. When TBLPAG = 0, the table page
is located in the user memory space. When
TBLPAG = 1, the page is located in configuration
space.
In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when Byte Select is ‘1’; the lower byte
is selected when it is ‘0’.
FIGURE 4-7:
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
23
15
0
0x000000
23
16
8
0
00000000
0x020000
0x030000
00000000
00000000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn = 0)
TBLRDL.B (Wn = 1)
TBLRDL.B (Wn = 0)
TBLRDL.W
0x800000
2009-2012 Microchip Technology Inc.
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
DS70592D-page 57
PIC24HJXXXGPX06A/X08A/X10A
4.4.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This option provides transparent access of stored constant data from the data space without the need to use
special instructions (i.e., TBLRDL/H).
Program space access through the data space occurs
if the Most Significant bit of the data space EA is ‘1’ and
program space visibility is enabled by setting the PSV
bit in the Core Control register (CORCON). The
location of the program memory space to be mapped
into the data space is determined by the Program
Space Visibility Page register (PSVPAG). This 8-bit
register defines any one of 256 possible pages of
16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory
address, with the 15 bits of the EA functioning as the
lower bits. Note that by incrementing the PC by 2 for
each program memory word, the lower 15 bits of data
space addresses directly map to the lower 15 bits in the
corresponding program space addresses.
Data reads to this area add an additional cycle to the
instruction being executed, since two program memory
fetches are required.
Although each data space address, 0x8000 and higher,
maps directly into a corresponding program memory
address (see Figure 4-8), only the lower 16 bits of the
FIGURE 4-8:
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
Note:
PSV access is temporarily disabled during
table reads/writes.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions
require one instruction cycle in addition to the specified
execution time. All other instructions require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV, which are executed inside
a REPEAT loop, there will be some instances that
require two instruction cycles in addition to the
specified execution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction accessing data, using PSV, to execute in a
single cycle.
PROGRAM SPACE VISIBILITY OPERATION
When CORCON = 1 and EA = 1:
Program Space
PSVPAG
02
23
15
Data Space
0
0x000000
0x0000
Data EA
0x010000
0x018000
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space...
0x8000
PSV Area
0x800000
DS70592D-page 58
...while the lower 15 bits
of the EA specify an
exact address within
0xFFFF the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
5.0
lines for power (VDD), ground (VSS) and Master Clear
(MCLR). This allows customers to manufacture boards
with unprogrammed devices and then program the digital signal controller just before shipping the product.
This also allows the most recent firmware or a custom
firmware to be programmed.
FLASH PROGRAM MEMORY
Note 1: This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section
5. “Flash Programming” (DS70191) of
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
can write program memory data either in blocks or
‘rows’ of 64 instructions (192 bytes) at a time, or single
instructions and erase program memory in blocks or
‘pages’ of 512 instructions (1536 bytes) at a time.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
5.1
The PIC24HJXXXGPX06A/X08A/X10A devices contain internal Flash program memory for storing and
executing application code. The memory is readable,
writable and erasable during normal operation over the
entire VDD range.
Flash memory can be programmed in two ways:
1.
2.
In-Circuit Serial Programming™ (ICSP™)
programming capability
Run-Time Self-Programming (RTSP)
ICSP
programming
capability
allows
a
PIC24HJXXXGPX06A/X08A/X10A device to be serially programmed while in the end application circuit.
This is simply done with two lines for programming
clock and programming data (one of the alternate programming pin pairs: PGECx/PGEDx, and three other
FIGURE 5-1:
Table Instructions and Flash
Programming
Regardless of the method used, all programming of
Flash memory is done with the table read and table
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 5-1.
The TBLRDL and the TBLWTL instructions are used to
read or write to bits of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to read
or write to bits of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
ADDRESSING FOR TABLE REGISTERS
24 bits
Using
Program Counter
Program Counter
0
0
Working Reg EA
Using
Table Instruction
1/0
TBLPAG Reg
8 bits
User/Configuration
Space Select
2009-2012 Microchip Technology Inc.
16 bits
24-bit EA
Byte
Select
DS70592D-page 59
PIC24HJXXXGPX06A/X08A/X10A
5.2
RTSP Operation
The PIC24HJXXXGPX06A/X08A/X10A Flash program
memory array is organized into rows of 64 instructions
or 192 bytes. RTSP allows the user to erase a page of
memory, which consists of eight rows (512 instructions)
at a time, and to program one row or one word at a
time. Table 24-12 displays typical erase and programming times. The 8-row erase pages and single row
write rows are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192
bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers in sequential order. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of
64 TBLWTL and TBLWTH instructions are required to
load the instructions.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
written. A programming cycle is required for
programming each row.
5.3
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
programming operation is finished.
The programming time depends on the FRC accuracy
(see Table 24-19) and the value of the FRC Oscillator
Tuning register (see Register 9-4). Use the following
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time and Word
Write Cycle Time parameters (see Table 24-12).
EQUATION 5-1:
For example, if the device is operating at +125°C, the
FRC accuracy will be ±5%. If the TUN bits (see
Register 9-4) are set to ‘b111111, the minimum row
write time is equal to Equation 5-2.
EQUATION 5-2:
MINIMUM ROW WRITE
TIME
11064 Cycles
T RW = ---------------------------------------------------------------------------------------------- = 1.435ms
7.37 MHz 1 + 0.05 1 – 0.00375
The maximum row write time is equal to Equation 5-3.
EQUATION 5-3:
MAXIMUM ROW WRITE
TIME
11064 Cycles
T RW = ---------------------------------------------------------------------------------------------- = 1.586ms
7.37 MHz 1 – 0.05 1 – 0.00375
Setting the WR bit (NVMCON) starts the
operation, and the WR bit is automatically cleared
when the operation is finished.
5.4
Control Registers
The two SFRs that are used to read and write the
program Flash memory are:
• NVMCON
• NVMKEY
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 0x55 and 0xAA to the
NVMKEY register. Refer to Section 5.3 “Programming
Operations” for further details.
PROGRAMMING TIME
T
-------------------------------------------------------------------------------------------------------------------------7.37 MHz FRC Accuracy % FRC Tuning %
DS70592D-page 60
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 5-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0(1)
R/W-0(1)
R/W-0(1)
U-0
U-0
U-0
U-0
U-0
WR
WREN
WRERR
—
—
—
—
—
bit 15
bit 8
R/W-0(1)
U-0
—
U-0
ERASE
—
R/W-0(1)
U-0
R/W-0(1)
R/W-0(1)
R/W-0(1)
NVMOP(2)
—
bit 7
bit 0
Legend:
SO = Settable only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete
0 = Program or erase operation is complete and inactive
bit 14
WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
bit 13
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12-7
Unimplemented: Read as ‘0’
bit 6
ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP on the next WR command
0 = Perform the program operation specified by NVMOP on the next WR command
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
NVMOP: NVM Operation Select bits(2)
1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)
1110 = Reserved
1101 = Erase General Segment and FGS Configuration Register
(ERASE = 1) or no operation (ERASE = 0)
1100 = Erase Secure Segment and FSS Configuration Register
(ERASE = 1) or no operation (ERASE = 0)
1011 = Reserved
•
•
•
0100 = Reserved
0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1)
0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)
0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)
0000 = Program or erase a single Configuration register byte
Note 1:
2:
These bits can only be reset on a POR.
All other combinations of NVMOP are unimplemented.
2009-2012 Microchip Technology Inc.
DS70592D-page 61
PIC24HJXXXGPX06A/X08A/X10A
5.4.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
4.
5.
The user can program one row of program Flash
memory at a time. To do this, it is necessary to erase
the 8-row erase page that contains the desired row.
The general process is:
1.
2.
3.
Read eight rows of program memory
(512 instructions) and store in data RAM.
Update the program data in RAM with the
desired new data.
Erase the page (see Example 5-1):
a) Set the NVMOP bits (NVMCON) to
‘0010’ to configure for block erase. Set the
ERASE (NVMCON) and WREN
(NVMCON) bits.
b) Write the starting address of the page to be
erased into the TBLPAG and W registers.
c) Perform a dummy table write operation
(TBLWTL) to any address within the page
that needs to be erased.
d) Write 0x55 to NVMKEY.
e) Write 0xAA to NVMKEY.
f) Set the WR bit (NVMCON). The erase
cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
EXAMPLE 5-1:
Note:
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 5-3.
ERASING A PROGRAM MEMORY PAGE
; Set up NVMCON for block erase operation
MOV
#0x4042, W0
MOV
W0, NVMCON
; Init pointer to row to be ERASED
MOV
#tblpage(PROG_ADDR), W0
MOV
W0, TBLPAG
MOV
#tbloffset(PROG_ADDR), W0
TBLWTL W0, [W0]
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
6.
Write the first 64 instructions from data RAM into
the program memory buffers (see Example 5-2).
Write the program block to Flash memory:
a) Set the NVMOP bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
b) Write 0x55 to NVMKEY.
c) Write 0xAA to NVMKEY.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash memory is done, the WR bit is cleared
automatically.
Repeat steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash memory.
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
;
; Initialize NVMCON
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PM Page Boundary SFR
Initialize in-page EA pointer
Set base address of erase block
Block all interrupts with priority | 0 | can affect the ADC results by approximately 4-6 counts.
TABLE 25-16: ADC MODULE SPECIFICATIONS (10-BIT MODE)(3)
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC
CHARACTERISTICS Operating temperature -40°C TA +150°C for High Temperature
Param
No.
AD23b
AD24b
AD23b
AD24b
HAD33b
Note 1:
2:
3:
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
ADC Accuracy (12-bit Mode) – Measurements with external VREF+/VREF-(1)
GERR
Gain Error
—
3
6
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
EOFF
Offset Error
—
2
5
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
ADC Accuracy (12-bit Mode) – Measurements with internal VREF+/VREF-(1)
GERR
Gain Error
—
7
15
LSb VINL = AVSS = 0V, AVDD = 3.6V
Offset Error
—
3
7
LSb VINL = AVSS = 0V, AVDD = 3.6V
EOFF
Dynamic Performance (10-bit Mode)(2)
FNYQ
Input Signal Bandwidth
—
—
400
kHz
—
These parameters are characterized, but are tested at 20 ksps only.
These parameters are characterized by similarity, but are not tested in manufacturing.
Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
DS70592D-page 294
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 25-17: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC
CHARACTERISTICS Operating temperature -40°C TA +150°C for High Temperature
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
—
—
ns
—
—
400
Ksps
—
Clock Parameters
HAD50
TAD
ADC Clock Period(1)
HAD56
FCNV
Throughput Rate(1)
147
Conversion Rate
Note 1:
—
These parameters are characterized but not tested in manufacturing.
TABLE 25-18: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC
CHARACTERISTICS Operating temperature -40°C TA +150°C for High Temperature
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
—
ns
—
800
Ksps
—
Clock Parameters
HAD50
TAD
ADC Clock Period(1)
HAD56
FCNV
Throughput Rate(1)
Note 1:
These parameters are characterized but not tested in manufacturing.
104
—
Conversion Rate
2009-2012 Microchip Technology Inc.
—
—
DS70592D-page 295
PIC24HJXXXGPX06A/X08A/X10A
NOTES:
DS70592D-page 296
2009-2012 Microchip Technology Inc.
DC AND AC DEVICE CHARACTERISTICS GRAPHS
Note:
The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes
only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating
range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FIGURE 26-1:
VOH – 2x DRIVER PINS
-0.040
-0.016
-0.035
3.6V
IOH (A)
-0.012
-0.010
3V
-0.008
-0.006
3.3V
-0.025
3V
-0.020
-0.015
-0.004
-0.010
-0.002
-0.005
0.000
0.00
3.6V
-0.030
3.3V
IOH (A)
-0.014
VOH – 8x DRIVER PINS
FIGURE 26-3:
0.50
1.00
1.50
2.00
2.50
3.00
3.50
0.000
0.00
4.00
1.00
2.00
VOH (V)
FIGURE 26-2:
VOH – 4x DRIVER PINS
FIGURE 26-4:
3.6V
-0.070
IOH (A)
IOH (A)
3V
-0.015
-0.010
DS70592D-page 297
3.00
4.00
VOH – 16x DRIVER PINS
3.6V
-0.060
3.3V
-0.020
3.3V
-0.050
3V
-0.040
-0.030
-0.020
-0.005
0.000
0.00
4.00
-0.080
-0.030
-0.025
3.00
VOH (V)
-0.010
0.50
1.00
1.50
2.00
VOH (V)
2.50
3.00
3.50
4.00
0.000
0.00
1.00
2.00
VOH (V)
PIC24HJXXXGPX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
26.0
VOL – 2x DRIVER PINS
FIGURE 26-7:
0.060
0.020
0.018
3.6V
0.016
3.6V
0.050
3.3V
3.3V
0.014
0.040
3V
0.012
IOL (A)
IOL (A)
VOL – 8x DRIVER PINS
0.010
0.008
3V
0.030
0.020
0.006
0.004
0.010
0.002
0.000
0.00
1.00
2.00
3.00
0.000
0.00
4.00
1.00
FIGURE 26-6:
VOL – 4x DRIVER PINS
FIGURE 26-8:
3.00
4.00
VOL – 16x DRIVER PINS
0.120
0.040
0.035
3.6V
0.030
3.6V
0.100
3.3V
0.025
3.3V
0.080
3V
IOL (A)
2009-2012 Microchip Technology Inc.
IOL (A)
2.00
VOL (V)
VOL (V)
0.020
0.015
3V
0.060
0.040
0.010
0.020
0.005
0.000
0.00
1.00
2.00
VOL (V)
3.00
4.00
0.000
0.00
1.00
2.00
VOL (V)
3.00
4.00
PIC24HJXXXGPX06A/X08A/X10A
DS70592D-page 298
FIGURE 26-5:
TYPICAL FRC FREQUENCY @ VDD = 3.3V
FIGURE 26-10:
7450
50
7400
45
7350
40
Frequency (kHz)
Frequency (kHz)
TYPICAL LPRC FREQUENCY @ VDD = 3.3V
7300
7250
7200
35
30
25
7150
20
7100
-40 -30 -20 -10
0
10
20 30 40 50 60 70
Temperature Celsius
80
90 100 110 120
40 30 20 10
0
10
20
30
40
50
60
TemperatureCelsius
70
80
90 100 110 120
DS70592D-page 299
PIC24HJXXXGPX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
FIGURE 26-9:
PIC24HJXXXGPX06A/X08A/X10A
NOTES:
DS70592D-page 300
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
27.0
PACKAGING INFORMATION
27.1
Package Marking Information
64-Lead QFN (9x9x0.9mm)
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
e3
Note:
Example
PIC24HJ256
GP710A-I/PT e3
0510017
100-Lead TQFP (14x14x1 mm)
*
Example
PIC24HJ
256GP706A
-I/PT e3
0510017
100-Lead TQFP (12x12x1 mm)
Legend: XX...X
Y
YY
WW
NNN
24HJ64GP
206A-I/MR e3
0610017
64-Lead TQFP (10x10x1 mm)
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Example
Example
PIC24HJ256
GP710A-I/PF e3
0510017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2009-2012 Microchip Technology Inc.
DS70592D-page 301
PIC24HJXXXGPX06A/X08A/X10A
27.2
Note:
Package Details
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70592D-page 302
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2012 Microchip Technology Inc.
DS70592D-page 303
PIC24HJXXXGPX06A/X08A/X10A
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70592D-page 304
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
E
e
E1
N
b
NOTE 1
123
NOTE 2
α
A
φ
c
A2
β
A1
L
L1
Units
Dimension Limits
Number of Leads
MILLIMETERS
MIN
N
NOM
MAX
64
Lead Pitch
e
Overall Height
A
–
0.50 BSC
–
Molded Package Thickness
A2
0.95
1.00
1.05
Standoff
A1
0.05
–
0.15
Foot Length
L
0.45
0.60
0.75
Footprint
L1
1.20
1.00 REF
Foot Angle
φ
Overall Width
E
12.00 BSC
Overall Length
D
12.00 BSC
Molded Package Width
E1
10.00 BSC
Molded Package Length
D1
10.00 BSC
0°
3.5°
7°
Lead Thickness
c
0.09
–
0.20
Lead Width
b
0.17
0.22
0.27
Mold Draft Angle Top
α
11°
12°
13°
Mold Draft Angle Bottom
β
11°
12°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085B
2009-2012 Microchip Technology Inc.
DS70592D-page 305
PIC24HJXXXGPX06A/X08A/X10A
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70592D-page 306
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
100-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
e
E
E1
N
b
NOTE 1
1 23
NOTE 2
α
c
A
φ
L
β
A1
Units
Dimension Limits
Number of Leads
A2
L1
MILLIMETERS
MIN
N
NOM
MAX
100
Lead Pitch
e
Overall Height
A
–
0.40 BSC
–
Molded Package Thickness
A2
0.95
1.00
1.05
Standoff
A1
0.05
–
0.15
Foot Length
L
0.45
0.60
0.75
Footprint
L1
1.20
1.00 REF
Foot Angle
φ
Overall Width
E
14.00 BSC
Overall Length
D
14.00 BSC
Molded Package Width
E1
12.00 BSC
Molded Package Length
D1
12.00 BSC
0°
3.5°
7°
Lead Thickness
c
0.09
–
0.20
Lead Width
b
0.13
0.18
0.23
Mold Draft Angle Top
α
11°
12°
13°
Mold Draft Angle Bottom
β
11°
12°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-100B
2009-2012 Microchip Technology Inc.
DS70592D-page 307
PIC24HJXXXGPX06A/X08A/X10A
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70592D-page 308
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
100-Lead Plastic Thin Quad Flatpack (PF) – 14x14x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
e
E1
E
b
N
α
NOTE 1
1 23
NOTE 2
A
φ
c
β
A2
A1
L
L1
Units
Dimension Limits
Number of Leads
MILLIMETERS
MIN
N
NOM
MAX
100
Lead Pitch
e
Overall Height
A
–
0.50 BSC
–
Molded Package Thickness
A2
0.95
1.00
1.05
Standoff
A1
0.05
–
0.15
Foot Length
L
0.45
0.60
0.75
Footprint
L1
1.20
1.00 REF
Foot Angle
φ
Overall Width
E
16.00 BSC
Overall Length
D
16.00 BSC
Molded Package Width
E1
14.00 BSC
Molded Package Length
D1
14.00 BSC
0°
3.5°
7°
Lead Thickness
c
0.09
–
0.20
Lead Width
b
0.17
0.22
0.27
Mold Draft Angle Top
α
11°
12°
13°
Mold Draft Angle Bottom
β
11°
12°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-110B
2009-2012 Microchip Technology Inc.
DS70592D-page 309
PIC24HJXXXGPX06A/X08A/X10A
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70592D-page 310
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
APPENDIX A:
MIGRATING FROM
PIC24HJXXXGPX06/
X08/X10 DEVICES TO
PIC24HJXXXGPX06A/
X08A/X10A DEVICES
The PIC24HJXXXGPX06A/X08A/X10A devices were
designed to enhance the PIC24HJXXXGPX06/X08/
X10 families of devices.
In general, the PIC24HJXXXGPX06A/X08A/X10A
devices are backward-compatible with
PIC24HJXXXGPX06/X08/X10 devices; however,
manufacturing differences may cause
PIC24HJXXXGPX06A/X08A/X10A devices to behave
differently from PIC24HJXXXGPX06/X08/X10 devices.
Therefore, complete system test and characterization
is recommended if PIC24HJXXXGPX06A/X08A/X10A
devices are used to replace PIC24HJXXXGPX06/X08/
X10 devices.
The following enhancements were introduced:
• Extended temperature support of up to +125ºC
• Enhanced Flash module with higher endurance
and retention
• New PLL Lock Enable configuration bit
• Added Timer5 trigger for ADC1 and Timer3 trigger
for ADC2
2009-2012 Microchip Technology Inc.
DS70592D-page 311
PIC24HJXXXGPX06A/X08A/X10A
APPENDIX B:
REVISION HISTORY
Revision B (October 2009)
The revision includes the following global update:
Revision A (April 2009)
This is the initial released version of the document.
• Added Note 2 to the shaded table that appears at
the beginning of each chapter. This new note
provides information regarding the availability of
registers and their associated bits
This revision also includes minor typographical and
formatting changes throughout the data sheet text.
All other major changes are referenced by their
respective section in the following table.
TABLE B-1:
MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, 16-bit
Microcontrollers”
Added information on high temperature operation (see “Operating
Range:”).
Section 10.0 “Power-Saving Features”
Updated the last paragraph to clarify the number of cycles that occur
prior to the start of instruction execution (see Section 10.2.2 “Idle
Mode”).
Section 11.0 “I/O Ports”
Changed the reference to digital-only pins to 5V tolerant pins in the
second paragraph of Section 11.2 “Open-Drain Configuration”.
Section 18.0 “Universal Asynchronous
Receiver Transmitter (UART)”
Updated the two baud rate range features to: 10 Mbps to 38 bps at
40 MIPS.
Section 20.0 “10-bit/12-bit Analog-to-Digital Updated the ADCx block diagram (see Figure 20-1).
Converter (ADC)”
Section 21.0 “Special Features”
Updated the second paragraph and removed the fourth paragraph in
Section 21.1 “Configuration Bits”.
Updated the Device Configuration Register Map (see Table 21-1).
Section 24.0 “Electrical Characteristics”
Updated the Absolute Maximum Ratings for high temperature and
added Note 4.
Updated Power-Down Current parameters DC60d, DC60a, DC60b,
and DC60d (see Table 24-7).
Added I2Cx Bus Data Timing Requirements (Master Mode)
parameter IM51 (see Table 24-36).
Updated the SPIx Module Slave Mode (CKE = 1) Timing
Characteristics (see Figure 24-12).
Updated the Internal LPRC Accuracy parameters (see Table 24-18
and Table 24-19).
Updated the ADC Module Specifications (12-bit Mode) parameters
AD23a and AD24a (see Table 24-40).
Updated the ADC Module Specifications (10-bit Mode) parameters
AD23b and AD24b (see Table 24-41).
Section 25.0 “High Temperature Electrical
Characteristics”
Added new chapter with high temperature specifications.
“Product Identification System”
Added the “H” definition for high temperature.
DS70592D-page 312
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Revision C (March 2011)
This revision includes typographical and formatting
changes throughout the data sheet text. In addition, all
occurrences of VDDCORE have been removed.
All other major changes are referenced by their
respective section in the following table.
TABLE B-2:
MAJOR SECTION UPDATES
Section Name
Section 2.0 “Guidelines for Getting Started
with 16-Bit Microcontrollers”
Update Description
The frequency limitation for device PLL start-up conditions was
updated in Section 2.7 “Oscillator Value Conditions on Device
Start-up”.
The second paragraph in Section 2.9 “Unused I/Os” was updated.
Section 4.0 “Memory Organization”
The All Resets values for the following SFRs in the Timer Register
Map were changed (see Table 4-6):
• TMR1
• TMR2
• TMR3
• TMR4
• TMR5
• TMR6
• TMR7
• TMR8
• TMR9
Section 9.0 “Oscillator Configuration”
Added Note 3 to the OSCCON: Oscillator Control Register (see
Register 9-1).
Added Note 2 to the CLKDIV: Clock Divisor Register (see
Register 9-2).
Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see
Register 9-3).
Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see
Register 9-4).
Section 20.0 “10-bit/12-bit Analog-to-Digital Updated the VREFL references in the ADC1 module block diagram
Converter (ADC)”
(see Figure 20-1).
Section 21.0 “Special Features”
Added a new paragraph and removed the third paragraph in
Section 21.1 “Configuration Bits”.
Added the column “RTSP Effects” to the Configuration Bits
Descriptions (see Table 21-2).
2009-2012 Microchip Technology Inc.
DS70592D-page 313
PIC24HJXXXGPX06A/X08A/X10A
TABLE B-2:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Section 24.0 “Electrical Characteristics”
Update Description
Removed Note 4 from the DC Temperature and Voltage
Specifications (see Table 24-4).
Updated the maximum value for parameter DI19 and added
parameters DI28, DI29, DI60a, DI60b, and DI60c to the I/O Pin Input
Specifications (see Table 24-9).
Removed Note 2 from the AC Characteristics: Internal RC Accuracy
(see Table 24-18).
Updated the characteristic description for parameter DI35 in the I/O
Timing Requirements (see Table 24-20).
Updated the ADC Module Specification minimum values for
parameters AD05 and AD07, and updated the maximum value for
parameter AD06 (see Table 24-39).
Added Note 1 to the ADC Module Specifications (12-bit Mode) (see
Table 24-40).
Added Note 1 to the ADC Module Specifications (10-bit Mode) (see
Table 24-41).
Added DMA Read/Write Timing Requirements (see Table 24-44).
Section 25.0 “High Temperature Electrical
Characteristics”
Updated all ambient temperature end range values to +150ºC
throughout the chapter.
Updated the storage temperature end range to +160ºC.
Updated the maximum junction temperature from +145ºC to +155ºC.
Updated the maximum values for High Temperature Devices in the
Thermal Operating Conditions (see Table 25-2).
Added Note 3 and updated the ADC Module Specifications (12-bit
Mode), removing all parameters with the exception of HAD33a (see
Table 25-15).
Added Note 3 and updated the ADC Module Specifications (10-bit
Mode), removing all parameters with the exception of HAD33b (see
Table 25-16).
DS70592D-page 314
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Revision D (June 2012)
This revision includes typographical and formatting
changes throughout the data sheet text.
All other major changes are referenced by their
respective section in the following table.
TABLE B-3:
MAJOR SECTION UPDATES
Section Name
Update Description
Section 2.0 “Guidelines for Getting Started Updated the Recommended Minimum Connection (see Figure 2-1).
with 16-Bit Microcontrollers”
Section 9.0 “Oscillator Configuration”
Updated the COSC and NOSC bit value definitions for
‘001’ (see Register 9-1).
Section 20.0 “10-bit/12-bit Analog-to-Digital Updated the Analog-to-Digital Conversion Clock Period Block
Converter (ADC)”
Diagram (see Figure 20-2).
Section 21.0 “Special Features”
Added Note 3 to the On-chip Voltage Regulator Connections (see
Figure 21-1).
Section 24.0 “Electrical Characteristics”
Updated “Absolute Maximum Ratings”.
Updated Operating MIPS vs. Voltage (see Table 24-1).
Removed parameter DC18 from the DC Temperature and Voltage
Specifications (see Table 24-4).
Updated the notes in the following tables:
•
•
•
•
Table 24-5
Table 24-6
Table 24-7
Table 24-8
Updated the I/O Pin Output Specifications (see Table 24-10).
Updated the Conditions for parameter BO10 (see Table 24-11).
Updated the Conditions for parameters D136b, D137b, and D138b
(TA = 150ºC) (see Table 24-12).
Section 25.0 “High Temperature Electrical
Characteristics”
Updated “Absolute Maximum Ratings”.
Updated the I/O Pin Output Specifications (see Table 25-6).
Removed Table 25-7: DC Characteristics: Program Memory.
2009-2012 Microchip Technology Inc.
DS70592D-page 315
PIC24HJXXXGPX06A/X08A/X10A
NOTES:
DS70592D-page 316
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
INDEX
A
AC Characteristics .................................................... 252, 291
ADC Module.............................................................. 294
ADC Module (10-bit Mode) ....................................... 294
ADC Module (12-bit Mode) ....................................... 294
Internal RC Accuracy ................................................ 254
Load Conditions ................................................ 252, 291
ADC Module
ADC1 Register Map .................................................... 42
ADC2 Register Map .................................................... 42
Alternate Interrupt Vector Table (AIVT) .............................. 69
Analog-to-Digital Converter............................................... 207
DMA .......................................................................... 207
Initialization ............................................................... 207
Key Features............................................................. 207
Arithmetic Logic Unit (ALU)................................................. 28
Assembler
MPASM Assembler................................................... 238
Automatic Clock Stretch.................................................... 166
B
Block Diagrams
16-bit Timer1 Module ................................................ 145
ADC1 Module............................................................ 208
Connections for On-Chip Voltage Regulator............. 226
ECAN Module ........................................................... 180
Input Capture ............................................................ 153
Output Compare ....................................................... 155
PIC24H ....................................................................... 16
PIC24H CPU Core ...................................................... 24
PIC24H Oscillator System Diagram.......................... 123
PIC24H PLL .............................................................. 125
Reset System.............................................................. 65
Shared Port Structure ............................................... 141
SPI ............................................................................ 159
Timer2 (16-bit) .......................................................... 149
Timer2/3 (32-bit) ....................................................... 148
UART ........................................................................ 173
Watchdog Timer (WDT) ............................................ 227
C
C Compilers
MPLAB C18 .............................................................. 238
Clock Switching................................................................. 131
Enabling .................................................................... 131
Sequence.................................................................. 131
Code Examples
Erasing a Program Memory Page............................... 62
Initiating a Programming Sequence............................ 63
Loading Write Buffers ................................................. 63
Port Write/Read ........................................................ 142
PWRSAV Instruction Syntax..................................... 133
Code Protection ........................................................ 221, 228
Configuration Bits.............................................................. 221
Description (Table).................................................... 222
Configuration Register Map .............................................. 221
Configuring Analog Port Pins ............................................ 142
CPU
Control Register .......................................................... 26
CPU Clocking System....................................................... 124
PLL Configuration ..................................................... 124
Selection ................................................................... 124
Sources..................................................................... 124
Customer Change Notification Service ............................. 321
2009-2012 Microchip Technology Inc.
Customer Notification Service .......................................... 321
Customer Support............................................................. 321
D
Data Address Space........................................................... 31
Alignment.................................................................... 31
Memory Map for PIC24HJXXXGPX06A/X08A/X10A
Devices with 16 KB RAM.................................... 33
Memory Map for PIC24HJXXXGPX06A/X08A/X10A
Devices with 8 KB RAM...................................... 32
Near Data Space ........................................................ 31
Software Stack ........................................................... 53
Width .......................................................................... 31
DC and AC Characteristics
Graphs and Tables ................................................... 297
DC Characteristics............................................................ 242
Doze Current (IDOZE)................................................ 289
High Temperature..................................................... 288
I/O Pin Input Specifications ...................................... 248
I/O Pin Output Specifications............................ 250, 290
Idle Current (IDOZE) .................................................. 247
Idle Current (IIDLE) .................................................... 245
Operating Current (IDD) ............................................ 244
Operating MIPS vs. Voltage ..................................... 288
Power-Down Current (IPD)........................................ 246
Power-down Current (IPD) ........................................ 288
Program Memory...................................................... 251
Temperature and Voltage......................................... 288
Temperature and Voltage Specifications.................. 243
Thermal Operating Conditions.................................. 288
Development Support ....................................................... 237
DMA Module
DMA Register Map ..................................................... 43
DMAC Registers ............................................................... 114
DMAxCNT ................................................................ 114
DMAxCON................................................................ 114
DMAxPAD ................................................................ 114
DMAxREQ ................................................................ 114
DMAxSTA ................................................................. 114
DMAxSTB ................................................................. 114
E
ECAN Module
CiFMSKSEL2 register .............................................. 199
ECAN1 Register Map (C1CTRL1.WIN = 0 or 1)......... 44
ECAN1 Register Map (C1CTRL1.WIN = 0)................ 45
ECAN1 Register Map (C1CTRL1.WIN = 1)................ 45
ECAN2 Register Map (C2CTRL1.WIN = 0 or 1)......... 47
ECAN2 Register Map (C2CTRL1.WIN = 0)................ 47
ECAN2 Register Map (C2CTRL1.WIN = 1)................ 48
Frame Types ............................................................ 179
Modes of Operation .................................................. 181
Overview................................................................... 179
ECAN Registers
Filter 15-8 Mask Selection Register
(CiFMSKSEL2) ................................................. 199
Electrical Characteristics .................................................. 241
AC..................................................................... 252, 291
Enhanced CAN Module .................................................... 179
Equations
Device Operating Frequency.................................... 124
FOSC Calculation..................................................... 124
XT with PLL Mode Example ..................................... 125
Errata .................................................................................. 13
DS70592D-page 317
PIC24HJXXXGPX06A/X08A/X10A
F
M
Flash Program Memory....................................................... 59
Control Registers ........................................................ 60
Operations .................................................................. 60
Programming Algorithm .............................................. 62
RTSP Operation.......................................................... 60
Table Instructions........................................................ 59
Flexible Configuration ....................................................... 221
FSCM
Delay for Crystal and PLL Clock Sources ................... 68
Device Resets ............................................................. 68
Memory Organization ......................................................... 29
Microchip Internet Web Site.............................................. 321
Modes of Operation
Disable...................................................................... 181
Initialization ............................................................... 181
Listen All Messages.................................................. 181
Listen Only................................................................ 181
Loopback .................................................................. 181
Normal Operation ..................................................... 181
MPLAB ASM30 Assembler, Linker, Librarian ................... 238
MPLAB Integrated Development
Environment Software .............................................. 237
MPLAB PM3 Device Programmer .................................... 240
MPLAB REAL ICE In-Circuit Emulator System ................ 239
MPLINK Object Linker/MPLIB Object Librarian ................ 238
Multi-Bit Data Shifter........................................................... 28
H
High Temperature Electrical Characteristics..................... 287
I
I/O Ports ............................................................................ 141
Parallel I/O (PIO)....................................................... 141
Write/Read Timing .................................................... 142
I2C
Operating Modes ...................................................... 165
Registers ................................................................... 167
I2C Module
I2C1 Register Map ...................................................... 40
I2C2 Register Map ...................................................... 40
In-Circuit Debugger ........................................................... 228
In-Circuit Emulation........................................................... 221
In-Circuit Serial Programming (ICSP) ....................... 221, 228
Input Capture
Registers ................................................................... 154
Input Change Notification Module ..................................... 142
Instruction Addressing Modes............................................. 53
File Register Instructions ............................................ 53
Fundamental Modes Supported.................................. 54
MCU Instructions ........................................................ 53
Move and Accumulator Instructions ............................ 54
Other Instructions........................................................ 54
Instruction Set
Overview ................................................................... 231
Summary................................................................... 229
Instruction-Based Power-Saving Modes ........................... 133
Idle ............................................................................ 134
Sleep ......................................................................... 133
Internal RC Oscillator
Use with WDT ........................................................... 227
Internet Address................................................................ 321
Interrupt Control and Status Registers................................ 73
IECx ............................................................................ 73
IFSx............................................................................. 73
INTCON1 .................................................................... 73
INTCON2 .................................................................... 73
INTTREG .................................................................... 73
IPCx ............................................................................ 73
Interrupt Setup Procedures ............................................... 111
Initialization ............................................................... 111
Interrupt Disable........................................................ 111
Interrupt Service Routine .......................................... 111
Trap Service Routine ................................................ 111
Interrupt Vector Table (IVT) ................................................ 69
Interrupts Coincident with Power Save Instructions.......... 134
J
JTAG Boundary Scan Interface ........................................ 221
DS70592D-page 318
N
NVM Module
Register Map .............................................................. 52
O
Open-Drain Configuration................................................. 142
Output Compare ............................................................... 155
P
Packaging ......................................................................... 301
Details....................................................................... 304
Marking ..................................................................... 301
Peripheral Module Disable (PMD) .................................... 134
Pinout I/O Descriptions (table)............................................ 17
PMD Module
Register Map .............................................................. 52
POR and Long Oscillator Start-up Times ........................... 68
PORTA
Register Map .............................................................. 50
PORTB
Register Map .............................................................. 50
PORTC
Register Map .............................................................. 50
PORTD
Register Map .............................................................. 50
PORTE
Register Map .............................................................. 51
PORTF
Register Map .............................................................. 51
PORTG
Register Map .............................................................. 51
Power-Saving Features .................................................... 133
Clock Frequency and Switching ............................... 133
Program Address Space..................................................... 29
Construction ............................................................... 55
Data Access from Program Memory Using
Program Space Visibility..................................... 58
Data Access from Program Memory
Using Table Instructions ..................................... 57
Data Access from, Address Generation ..................... 56
Memory Map............................................................... 29
Table Read Instructions
TBLRDH ............................................................. 57
TBLRDL.............................................................. 57
Visibility Operation ...................................................... 58
Program Memory
Interrupt Vector ........................................................... 30
Organization ............................................................... 30
Reset Vector ............................................................... 30
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
R
Reader Response ............................................................. 322
Registers
ADxCHS0 (ADCx Input Channel 0 Select................. 217
ADxCHS123 (ADCx Input
Channel 1, 2, 3 Select) ..................................... 216
ADxCON1 (ADCx Control 1)..................................... 211
ADxCON2 (ADCx Control 2)..................................... 213
ADxCON3 (ADCx Control 3)..................................... 214
ADxCON4 (ADCx Control 4)..................................... 215
ADxCSSH (ADCx Input Scan Select High)............... 218
ADxCSSL (ADCx Input Scan Select Low) ................ 218
ADxPCFGH (ADCx Port Configuration High) ........... 219
ADxPCFGL (ADCx Port Configuration Low)............. 220
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer)........... 193
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer)........... 194
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer)......... 195
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer)....... 196
CiCFG1 (ECAN Baud Rate Configuration 1) ............ 190
CiCFG2 (ECAN Baud Rate Configuration 2) ............ 191
CiCTRL1 (ECAN Control 1) ...................................... 182
CiCTRL2 (ECAN Control 2) ...................................... 183
CiEC (ECAN Transmit/Receive Error Count)............ 189
CiFCTRL (ECAN FIFO Control)................................ 185
CiFEN1 (ECAN Acceptance Filter Enable) ............... 192
CiFIFO (ECAN FIFO Status)..................................... 186
CiFMSKSEL1 (ECAN Filter 7-0 Mask
Selection) .................................................. 198, 199
CiINTE (ECAN Interrupt Enable) .............................. 188
CiINTF (ECAN Interrupt Flag)................................... 187
CiRXFnEID (ECAN Acceptance Filter n
Extended Identifier)........................................... 197
CiRXFnSID (ECAN Acceptance Filter n
Standard Identifier) ........................................... 197
CiRXFUL1 (ECAN Receive Buffer Full 1) ................. 201
CiRXFUL2 (ECAN Receive Buffer Full 2) ................. 201
CiRXMnEID (ECAN Acceptance Filter Mask n
Extended Identifier)........................................... 200
CiRXMnSID (ECAN Acceptance Filter Mask n
Standard Identifier) ........................................... 200
CiRXOVF1 (ECAN Receive Buffer Overflow 1) ........ 202
CiRXOVF2 (ECAN Receive Buffer Overflow 2) ........ 202
CiTRBnDLC (ECAN Buffer n Data
Length Control) ................................................. 205
CiTRBnEID (ECAN Buffer n Extended Identifier) ..... 204
CiTRBnSID (ECAN Buffer n Standard Identifier) ...... 204
CiTRBnSTAT (ECAN Receive Buffer n Status) ........ 206
CiTRmnCON (ECAN TX/RX Buffer m Control)......... 203
CiVEC (ECAN Interrupt Code).................................. 184
CLKDIV (Clock Divisor)............................................. 128
CORCON (Core Control) ...................................... 27, 74
DMACS0 (DMA Controller Status 0)......................... 119
DMACS1 (DMA Controller Status 1)......................... 121
DMAxCNT (DMA Channel x Transfer Count) ........... 118
DMAxCON (DMA Channel x Control) ....................... 115
DMAxPAD (DMA Channel x Peripheral Address)..... 118
DMAxREQ (DMA Channel x IRQ Select) ................. 116
DMAxSTA (DMA Channel x RAM Start
Address A) ........................................................ 117
DMAxSTB (DMA Channel x RAM Start
Address B) ........................................................ 117
DSADR (Most Recent DMA RAM Address).............. 122
I2CxCON (I2Cx Control) ........................................... 168
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 172
I2CxSTAT (I2Cx Status) ........................................... 170
2009-2012 Microchip Technology Inc.
ICxCON (Input Capture x Control)............................ 154
IEC0 (Interrupt Enable Control 0) ............................... 85
IEC1 (Interrupt Enable Control 1) ............................... 87
IEC2 (Interrupt Enable Control 2) ............................... 89
IEC3 (Interrupt Enable Control 3) ............................... 91
IEC4 (Interrupt Enable Control 4) ............................... 92
IFS0 (Interrupt Flag Status 0) ..................................... 77
IFS1 (Interrupt Flag Status 1) ..................................... 79
IFS2 (Interrupt Flag Status 2) ..................................... 81
IFS3 (Interrupt Flag Status 3) ..................................... 83
IFS4 (Interrupt Flag Status 4) ..................................... 84
INTCON1 (Interrupt Control 1) ................................... 75
INTCON2 (Interrupt Control 2) ................................... 76
IPC0 (Interrupt Priority Control 0) ............................... 93
IPC1 (Interrupt Priority Control 1) ............................... 94
IPC10 (Interrupt Priority Control 10) ......................... 103
IPC11 (Interrupt Priority Control 11) ......................... 104
IPC12 (Interrupt Priority Control 12) ......................... 105
IPC13 (Interrupt Priority Control 13) ......................... 106
IPC14 (Interrupt Priority Control 14) ......................... 107
IPC15 (Interrupt Priority Control 15) ......................... 107
IPC16 (Interrupt Priority Control 16) ................. 108, 110
IPC17 (Interrupt Priority Control 17) ......................... 109
IPC2 (Interrupt Priority Control 2) ............................... 95
IPC3 (Interrupt Priority Control 3) ............................... 96
IPC4 (Interrupt Priority Control 4) ............................... 97
IPC5 (Interrupt Priority Control 5) ............................... 98
IPC6 (Interrupt Priority Control 6) ............................... 99
IPC7 (Interrupt Priority Control 7) ............................. 100
IPC8 (Interrupt Priority Control 8) ............................. 101
IPC9 (Interrupt Priority Control 9) ............................. 102
NVMCON (Flash Memory Control)............................. 61
OCxCON (Output Compare x Control) ..................... 157
OSCCON (Oscillator Control)................................... 126
OSCTUN (FRC Oscillator Tuning)............................ 130
PLLFBD (PLL Feedback Divisor) ............................. 129
PMD1 (Peripheral Module Disable Control
Register 1) ........................................................ 135
PMD1 (Peripheral Module Disable Control
Register 1) ........................................................ 135
PMD2 (Peripheral Module Disable Control
Register 2) ........................................................ 137
PMD3 (Peripheral Module Disable Control
Register 3) ........................................................ 139
RCON (Reset Control)................................................ 66
SPIxCON1 (SPIx Control 1) ..................................... 162
SPIxCON2 (SPIx Control 2) ..................................... 164
SPIxSTAT (SPIx Status and Control) ....................... 161
SR (CPU Status) .................................................. 26, 74
T1CON (Timer1 Control) .......................................... 146
TxCON (T2CON, T4CON, T6CON or
T8CON Control)................................................ 150
TyCON (T3CON, T5CON, T7CON or
T9CON Control)................................................ 151
UxMODE (UARTx Mode) ......................................... 175
UxSTA (UARTx Status and Control) ........................ 177
Reset
Clock Source Selection .............................................. 67
Special Function Register Reset States ..................... 68
Times.......................................................................... 67
Reset Sequence ................................................................. 69
Resets ................................................................................ 65
DS70592D-page 319
PIC24HJXXXGPX06A/X08A/X10A
S
Serial Peripheral Interface (SPI) ....................................... 159
Software Simulator (MPLAB SIM)..................................... 239
Software Stack Pointer, Frame Pointer
CALL Stack Frame...................................................... 53
Special Features ............................................................... 221
SPI Module
SPI1 Register Map ...................................................... 41
SPI2 Register Map ...................................................... 41
Symbols Used in Opcode Descriptions............................. 230
System Control
Register Map............................................................... 52
T
Temperature and Voltage Specifications
AC ..................................................................... 252, 291
Timer1 ............................................................................... 145
Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ..................... 147
Timing Characteristics
CLKO and I/O ........................................................... 255
Timing Diagrams
10-bit Analog-to-Digital Conversion (CHPS = 01,
SIMSAM = 0, ASAM = 1, SSRC = 111,
SAMC = 00001) ....................................... 284
10-bit Analog-to-Digtial Conversion (CHPS = 01,
SIMSAM = 0, ASAM = 0,
SSRC = 000) ........................................... 284
12-bit Analog-to-Digital Conversion
(ASAM = 0, SSRC = 000) ........................ 282
ECAN I/O .................................................................. 278
External Clock ........................................................... 253
I2Cx Bus Data (Master Mode) .................................. 274
I2Cx Bus Data (Slave Mode) .................................... 276
I2Cx Bus Start/Stop Bits (Master Mode) ................... 274
I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 276
Input Capture (CAPx)................................................ 260
OC/PWM ................................................................... 261
Output Compare (OCx) ............................................. 260
Reset, Watchdog Timer, Oscillator Start-up Timer
and Power-up Timer ......................................... 256
Timer1, 2 and 3 External Clock................................. 258
Timing Requirements
ADC Conversion (10-bit mode) ................................. 295
ADC Conversion (12-bit Mode) ................................. 295
CLKO and I/O ........................................................... 255
External Clock ........................................................... 253
Input Capture ............................................................ 260
SPIx Master Mode (CKE = 0).................................... 292
SPIx Module Master Mode (CKE = 1)....................... 292
SPIx Module Slave Mode (CKE = 0)......................... 293
SPIx Module Slave Mode (CKE = 1)......................... 293
DS70592D-page 320
Timing Specifications
10-bit Analog-to-Digital Conversion
Requirements ................................................... 285
CAN I/O Requirements ............................................. 278
I2Cx Bus Data Requirements (Master Mode)........... 275
I2Cx Bus Data Requirements (Slave Mode)............. 277
Output Compare Requirements................................ 260
PLL Clock ......................................................... 254, 291
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out
Reset Requirements......................................... 257
Simple OC/PWM Mode Requirements ..................... 261
Timer1 External Clock Requirements ....................... 258
Timer2 External Clock Requirements ....................... 259
Timer3 External Clock Requirements ....................... 259
U
UART Module
UART1 Register Map.................................................. 40
UART2 Register Map.................................................. 41
V
Voltage Regulator (On-Chip) ............................................ 226
W
Watchdog Timer (WDT)............................................ 221, 227
Programming Considerations ................................... 227
WWW Address ................................................................. 321
WWW, On-Line Support ..................................................... 13
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQs), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2009-2012 Microchip Technology Inc.
DS70592D-page 321
PIC24HJXXXGPX06A/X08A/X10A
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
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Application (optional):
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Y
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Device: PIC24HJXXXGPX06A/X08A/X10A
Literature Number: DS70592D
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS70592D-page 322
2009-2012 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PIC 24 HJ 256 GP6 10 A T I/PT - XXX
Examples:
a)
Microchip Trademark
Architecture
b)
Flash Memory Family
Program Memory Size (KB)
Product Group
PIC24HJ256GP210AI/PT:
General-purpose PIC24H, 256 KB program
memory, 100-pin, Industrial temp.,
TQFP package.
PIC24HJ64GP506AI/PT-ES:
General-purpose PIC24H, 64 KB program
memory, 64-pin, Industrial temp.,
TQFP package, Engineering Sample.
Pin Count
Revision Level
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture:
24
=
16-bit Microcontroller
Flash Memory Family: HJ
=
Flash program memory, 3.3V, High-speed
Product Group:
GP2
GP3
GP5
GP6
=
=
=
=
General purpose family
General purpose family
General purpose family
General purpose family
Pin Count:
06
10
=
=
64-pin
100-pin
Temperature Range:
I
E
H
=
=
=
-40C to+85C(Industrial)
-40C to+125C(Extended)
-40C to+150C(High)
Package:
PT
PF
MR
=
=
=
10x10 or 12x12 mm TQFP (Thin Quad Flatpack)
14x14 mm TQFP (Thin Quad Flatpack)
9x9x0.9 mm QFN (Thin Quad Flatpack)
Pattern:
Three-digit QTP, SQTP, Code or Special Requirements
(blank otherwise)
ES
= Engineering Sample
2009-2012 Microchip Technology Inc.
DS70592D-page 323
PIC24HJXXXGPX06A/X08A/X10A
NOTES:
DS70592D-page 324
2009-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-345-2
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2009-2012 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70592D-page 325
Worldwide Sales and Service
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DS70592D-page 326
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11/29/11
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