PIC24HJXXXGPX06/X08/X10
Data Sheet
High-Performance,
16-Bit Microcontrollers
© 2009 Microchip Technology Inc.
DS70175H
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Total Endurance, TSHARC, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70175H-page ii
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
High-Performance, 16-Bit Microcontrollers
Operating Range:
On-Chip Flash and SRAM:
• Up to 40 MIPS operation (at 3.0-3.6V):
- Industrial temperature range
(-40°C to +85°C)
• Flash program memory, up to 256 Kbytes
• Data SRAM, up to 16 Kbytes (includes 2 Kbytes
of DMA RAM)
High-Performance CPU:
•
•
•
•
•
•
•
•
•
•
•
•
•
Modified Harvard architecture
C compiler optimized instruction set
16-bit wide data path
24-bit wide instructions
Linear program memory addressing up to 4M
instruction words
Linear data memory addressing up to 64 Kbytes
71 base instructions: mostly 1 word/1 cycle
Sixteen 16-bit General Purpose Registers
Flexible and powerful Indirect Addressing modes
Software stack
16 x 16 multiply operations
32/16 and 16/16 divide operations
Up to ±16-bit data shifts
Direct Memory Access (DMA):
• 8-channel hardware DMA
• 2 Kbytes dual ported DMA buffer area
(DMA RAM) to store data transferred via DMA:
- Allows data transfer between RAM and a
peripheral while CPU is executing code
(no cycle stealing)
• Most peripherals support DMA
Interrupt Controller:
•
•
•
•
•
5-cycle latency
Up to 61 available interrupt sources
Up to five external interrupts
Seven programmable priority levels
FIve processor exceptions
System Management:
• Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated PLL
- Extremely low jitter PLL
• Power-up Timer
• Oscillator Start-up Timer/Stabilizer
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor
• Reset by multiple sources
Power Management:
• On-chip 2.5V voltage regulator
• Switch between clock sources in real time
• Idle, Sleep and Doze modes with fast wake-up
Timers/Capture/Compare/PWM:
• Timer/Counters, up to nine 16-bit timers:
- Can pair up to make four 32-bit timers
- One timer runs as Real-Time Clock with
external 32.768 kHz oscillator
- Programmable prescaler
• Input Capture (up to eight channels):
- Capture on up, down or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
• Output Compare (up to eight channels):
- Single or Dual 16-Bit Compare mode
- 16-bit Glitchless PWM mode
Digital I/O:
•
•
•
•
•
Up to 85 programmable digital I/O pins
Wake-up/Interrupt-on-Change on up to 24 pins
Output pins can drive from 3.0V to 3.6V
All digital input pins are 5V tolerant
4 mA sink on all I/O pins
© 2009 Microchip Technology Inc.
DS70175H-page 1
PIC24HJXXXGPX06/X08/X10
Communication Modules:
Analog-to-Digital Converters:
• 3-wire SPI (up to two modules):
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
• I2C™ (up to two modules):
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
• UART (up to two modules):
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
- IrDA® encoding and decoding in hardware
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
• Enhanced CAN (ECAN™ module) 2.0B active
(up to two modules):
- Up to eight transmit and up to 32 receive buffers
- 16 receive filters and 3 masks
- Loopback, Listen Only and Listen All
Messages modes for diagnostics and bus
monitoring
- Wake-up on CAN message
- Automatic processing of Remote
Transmission Requests
- FIFO mode using DMA
- DeviceNet™ addressing support
• Up to two Analog-to-Digital Converter (ADC)
modules in a device
• 10-bit, 1.1 Msps or 12-bit, 500 ksps conversion:
- Two, four, or eight simultaneous samples
- Up to 32 input channels with auto-scanning
- Conversion start can be manual or
synchronized with one of four trigger sources
- Conversion possible in Sleep mode
- ±1 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
DS70175H-page 2
CMOS Flash Technology:
•
•
•
•
•
Low-power, high-speed Flash technology
Fully static design
3.3V (±10%) operating voltage
Industrial temperature
Low-power consumption
Packaging:
• 100-pin TQFP (14x14x1 mm and 12x12x1 mm)
• 64-pin TQFP (10x10x1 mm)
Note:
See the device variant tables for exact
peripheral features per device.
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
PIC24H PRODUCT FAMILIES
The PIC24H Family of devices is ideal for a wide variety of 16-bit MCU embedded applications. The device
names, pin counts, memory sizes and peripheral availability of each device are listed below, followed by their
pinout diagrams.
Program
Flash
Memory (KB)
DMA Channels
Timer 16-bit
Input Capture
Output Compare
Std. PWM
Codec
Interface
ADC
UART
SPI
I C™
CAN
I/O Pins (Max)(2)
Packages
PIC24HJ64GP206
64
64
8
8
9
8
8
0
1 ADC,
18 ch
2
2
1
0
53
PT
PIC24HJ64GP210
100
64
8
8
9
8
8
0
1 ADC,
32 ch
2
2
2
0
85
PF, PT
PIC24HJ64GP506
64
64
8
8
9
8
8
0
1 ADC,
18 ch
2
2
2
1
53
PT
PIC24HJ64GP510
100
64
8
8
9
8
8
0
1 ADC,
32 ch
2
2
2
1
85
PF, PT
PIC24HJ128GP206
64
128
8
8
9
8
8
0
1 ADC,
18 ch
2
2
2
0
53
PT
PIC24HJ128GP210
100
128
8
8
9
8
8
0
1 ADC,
32 ch
2
2
2
0
85
PF, PT
PIC24HJ128GP506
64
128
8
8
9
8
8
0
1 ADC,
18 ch
2
2
2
1
53
PT
PIC24HJ128GP510
100
128
8
8
9
8
8
0
1 ADC,
32 ch
2
2
2
1
85
PF, PT
PIC24HJ128GP306
64
128
16
8
9
8
8
0
1 ADC,
18 ch
2
2
2
0
53
PT
PIC24HJ128GP310
100
128
16
8
9
8
8
0
1 ADC,
32 ch
2
2
2
0
85
PF, PT
PIC24HJ256GP206
64
256
16
8
9
8
8
0
1 ADC,
18 ch
2
2
2
0
53
PT
PIC24HJ256GP210
100
256
16
8
9
8
8
0
1 ADC,
32 ch
2
2
2
0
85
PF, PT
PIC24HJ256GP610
100
256
16
8
9
8
8
0
2 ADC,
32 ch
2
2
2
2
85
PF, PT
Device
Note 1:
2:
2
Pins
RAM(1) (KB)
PIC24H Family Controllers
RAM size is inclusive of 2 Kbytes DMA RAM.
Maximum I/O pin count includes pins shared by the peripheral functions.
© 2009 Microchip Technology Inc.
DS70175H-page 3
PIC24HJXXXGPX06/X08/X10
Pin Diagrams
64-Pin TQFP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RG13
RG12
RG14
RG0
RG1
RF1
RF0
VDD
VCAP/VDDCORE
OC8/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC24HJ64GP206
PIC24HJ128GP206
PIC24HJ256GP206
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/SDA2/CN17/RF4
U2TX/SCL2/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
Note:
DS70175H-page 4
The PIC24HJ64GP206 device does not have the SCL2 and SDA2 pins.
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
Pin Diagrams (Continued)
64-Pin TQFP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RG13
RG12
RG14
RG0
RG1
RF1
RF0
VDD
VCAP/VDDCORE
OC8/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC24HJ128GP306
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/SDA2/CN17/RF4
U2TX/SCL2/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
© 2009 Microchip Technology Inc.
DS70175H-page 5
PIC24HJXXXGPX06/X08/X10
Pin Diagrams (Continued)
64-Pin TQFP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RG13
RG12
RG14
RG0
RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP/VDDCORE
OC8/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC24HJ64GP506
PIC24HJ128GP506
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/SDA2/CN17/RF4
U2TX/SCL2/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
DS70175H-page 6
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AN28/RE4
AN27/RE3
AN26/RE2
RG13
RG12
RG14
AN25/RE1
AN24/RE0
AN23/CN23/RA7
AN22/CN22/RA6
RG0
RG1
RF1
RF0
VDD
VCAP/VDDCORE
OC8/CN16/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
100-Pin TQFP
RG15
VDD
AN29/RE5
AN30/RE6
AN31/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/CN3/RB1
75
VSS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
74
PGEC2/SOSCO/T1CK/CN0/RC14
73
PGED2/SOSCI/CN1/RC13
72
71
OC1/RD0
IC4/RD11
70
IC3/RD10
69
68
IC2/RD9
IC1/RD8
INT4/RA15
INT3/RA14
23
24
25
67
66
65
64
PIC24HJ64GP210
PIC24HJ128GP210
PIC24HJ128GP310
PIC24HJ256GP210
VSS
OSC2/CLKO/RC15
63
62
OSC1/CLKIN/RC12
VDD
61
60
TDO/RA5
TDI/RA4
59
SDA2/RA3
SCL2/RA2
58
57
56
SCL1/RG2
SDA1/RG3
55
SCK1/INT0/RF6
54
53
SDI1/RF7
SDO1/RF8
U1RX/RF2
52
51
U1TX/RF3
PGEC1/AN6/OCFA/RB6
26
PGED1PGED1/AN7/RB727
VREF-/RA9
28
VREF+/RA10
29
30
AVDD
31
AVSS
32
AN8/RB8
33
AN9/RB9
34
AN10/RB10
35
AN11/RB11
36
VSS
VDD
37
38
TCK/RA1
U2RTS/RF13
39
40
U2CTS/RF12
41
AN12/RB12
42
AN13/RB13
43
AN14/RB14
44
AN15/OCFB/CN12/RB15
45
VSS
46
VDD
47
IC7/U1CTS/CN20/RD14
48
IC8/U1RTS/CN21/RD15
49
U2RX/CN17/RF4
50
U2TX/CN18/RF5
PGED3/AN0/CN2/RB0
1
© 2009 Microchip Technology Inc.
DS70175H-page 7
PIC24HJXXXGPX06/X08/X10
Pin Diagrams (Continued)
100-Pin TQFP
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AN28/RE4
AN27/RE3
AN26/RE2
RG13
RG12
RG14
AN25/RE1
AN24/RE0
AN23/CN23/RA7
AN22/CN22/RA6
RG0
RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP/VDDCORE
OC8/CN16/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
RG15
VDD
AN29/RE5
AN30/RE6
AN31/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/CN3/RB1
75
2
3
4
74
5
6
7
8
9
71
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
66
65
64
INT3/RA14
VSS
OSC2/CLKO/RC15
63
62
61
OSC1/CLKIN/RC12
VDD
73
72
70
69
68
67
PIC24HJ64GP510
PIC24HJ128GP510
VSS
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/CN1/RC13
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
IC1/RD8
INT4/RA15
60
TDO/RA5
TDI/RA4
59
SDA2/RA3
58
57
56
SCL2/RA2
55
54
53
SCK1/INT0/RF6
52
51
SCL1/RG2
SDA1/RG3
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
VREF-/RA9
VREF+/RA10
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
VSS
VDD
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PGED3/AN0/CN2/RB0
1
DS70175H-page 8
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
Pin Diagrams (Continued)
100-Pin TQFP
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AN28/RE4
AN27/RE3
AN26/RE2
RG13
RG12
RG14
AN25/RE1
AN24/RE0
AN23/CN23/RA7
AN22/CN22/RA6
C2RX/RG0
C2TX/RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP/VDDCORE
OC8/CN16/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
RG15
VDD
AN29/RE5
AN30/RE6
AN31/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
73
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/CN1/RC13
72
OC1/RD0
71
IC4/RD11
IC3/RD10
IC2/RD9
70
69
68
67
PIC24HJ256GP610
VSS
IC1/RD8
INT4/RA15
66
65
INT3/RA14
VSS
64
63
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
62
61
60
59
58
57
56
55
54
53
52
51
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
VREF-/RA9
VREF+/RA10
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
VSS
VDD
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
75
74
1
© 2009 Microchip Technology Inc.
DS70175H-page 9
PIC24HJXXXGPX06/X08/X10
Table of Contents
PIC24H Product Families....................................................................................................................................................................... 3
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers ........................................................................................................ 15
3.0 CPU............................................................................................................................................................................................ 19
4.0 Memory Organization ................................................................................................................................................................. 25
5.0 Flash Program Memory .............................................................................................................................................................. 55
6.0 Reset ......................................................................................................................................................................................... 61
7.0 Interrupt Controller ..................................................................................................................................................................... 65
8.0 Direct Memory Access (DMA) .................................................................................................................................................. 109
9.0 Oscillator Configuration ............................................................................................................................................................ 119
10.0 Power-Saving Features............................................................................................................................................................ 129
11.0 I/O Ports ................................................................................................................................................................................... 137
12.0 Timer1 ...................................................................................................................................................................................... 139
13.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................ 141
14.0 Input Capture............................................................................................................................................................................ 147
15.0 Output Compare....................................................................................................................................................................... 149
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 153
17.0 Inter-Integrated Circuit™ (I2C™) .............................................................................................................................................. 159
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 167
19.0 Enhanced CAN (ECAN™) Module ........................................................................................................................................... 173
20.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) ...................................................................................................................... 199
21.0 Special Features ...................................................................................................................................................................... 211
22.0 Instruction Set Summary .......................................................................................................................................................... 219
23.0 Development Support............................................................................................................................................................... 227
24.0 Electrical Characteristics .......................................................................................................................................................... 231
25.0 Packaging Information.............................................................................................................................................................. 267
Appendix A: Revision History............................................................................................................................................................. 275
Index ................................................................................................................................................................................................. 281
The Microchip Web Site ..................................................................................................................................................................... 285
Customer Change Notification Service .............................................................................................................................................. 285
Customer Support .............................................................................................................................................................................. 285
Reader Response .............................................................................................................................................................................. 286
Product Identification System............................................................................................................................................................. 287
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS70175H-page 10
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
1.0
Note:
DEVICE OVERVIEW
This data sheet summarizes the features
of the PIC24HJXXXGPX06/X08/X10 family of devices. However, it is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to the latest family reference
sections of the “PIC24H Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
This makes these families suitable for a wide variety of
high-performance digital signal control applications.
The devices are pin compatible with the dsPIC33F family of devices, and also share a very high degree of
compatibility with the dsPIC30F family devices. This
allows easy migration between device families as may
be necessitated by the specific functionality, computational resource and system cost requirements of the
application.
This document contains device specific information for
the following devices:
The PIC24HJXXXGPX06/X08/X10 device family
employs a powerful 16-bit architecture, ideal for
applications that rely on high-speed, repetitive
computations, as well as control.
•
•
•
•
•
•
•
•
•
•
•
•
•
The 17 x 17 multiplier, hardware support for division
operations, multi-bit data shifter, a large array of 16-bit
working registers and a wide variety of data addressing
modes,
together
provide
the
PIC24HJXXXGPX06/X08/X10 Central Processing Unit
(CPU) with extensive mathematical processing
capability. Flexible and deterministic interrupt handling,
coupled with a powerful array of peripherals, renders
the PIC24HJXXXGPX06/X08/X10 devices suitable for
control applications. Further, Direct Memory Access
(DMA) enables overhead-free transfer of data between
several peripherals and a dedicated DMA RAM.
Reliable, field programmable Flash program memory
ensures scalability of applications that use
PIC24HJXXXGPX06/X08/X10 devices.
PIC24HJ64GP206
PIC24HJ64GP210
PIC24HJ64GP506
PIC24HJ64GP510
PIC24HJ128GP206
PIC24HJ128GP210
PIC24HJ128GP506
PIC24HJ128GP510
PIC24HJ128GP306
PIC24HJ128GP310
PIC24HJ256GP206
PIC24HJ256GP210
PIC24HJ256GP610
The PIC24HJXXXGPX06/X08/X10 device family
includes devices with different pin counts (64 and 100
pins), different program memory sizes (64 Kbytes, 128
Kbytes and 256 Kbytes) and different RAM sizes (8
Kbytes and 16 Kbytes).
© 2009 Microchip Technology Inc.
Figure 1-1 shows a general block diagram of the
various core and peripheral modules in the
PIC24HJXXXGPX06/X08/X10 family of devices, while
Table 1-1 lists the functions of the various pins shown
in the pinout diagrams.
DS70175H-page 11
PIC24HJXXXGPX06/X08/X10
FIGURE 1-1:
PIC24HJXXXGPX06/X08/X10 GENERAL BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Data Bus
Interrupt
Controller
16
8
16
PORTA
16
DMA
RAM
Data Latch
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
23
X RAM
PORTB
Address
Latch
DMA
23
Controller
16
PORTC
Address Generator Units
Address Latch
16
Program Memory
EA MUX
Data Latch
24
Instruction Reg
Control Signals
to Various Blocks
Timing
Generation
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
Voltage
Regulator
VCAP/VDDCORE
Timers
1-9
IC1-8
Note:
Literal Data
16
Instruction
Decode and
Control
OSC2/CLKO
OSC1/CLKI
PORTD
ROM Latch
16
PORTE
16
17 x 17 Multiplier
Power-up
Timer
Divide Support
16 x 16
W Register Array
16
Oscillator
Start-up Timer
Power-on
Reset
16-bit ALU
Watchdog
Timer
16
Brown-out
Reset
VDD, VSS
ADC1,2
OC/
PWM1-8
PORTF
PORTG
MCLR
ECAN1,2
UART1,2
CN1-23
SPI1,2
I2C1,2
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins
and features present on each device.
DS70175H-page 12
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin
Type
Buffer
Type
AN0-AN31
I
Analog
AVDD
P
P
Positive supply for analog modules. This pin must be connected at all times.
AVSS
P
P
Ground reference for analog modules.
CLKI
CLKO
I
O
CN0-CN23
I
ST
Input change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
C1RX
C1TX
C2RX
C2TX
I
O
I
O
ST
—
ST
—
ECAN1 bus receive pin.
ECAN1 bus transmit pin.
ECAN2 bus receive pin.
ECAN2 bus transmit pin.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
IC1-IC8
I
ST
Capture inputs 1 through 8.
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.
Pin Name
Description
Analog input channels.
ST/CMOS External clock source input. Always associated with OSC1 pin function.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
MCLR
I/P
ST
Master Clear (Reset) input. This pin is an active-low Reset to the device.
OCFA
OCFB
OC1-OC8
I
I
O
ST
ST
—
Compare Fault A input (for Compare Channels 1, 2, 3 and 4).
Compare Fault B input (for Compare Channels 5, 6, 7 and 8).
Compare outputs 1 through 8.
OSC1
I
OSC2
I/O
RA0-RA7
RA9-RA10
RA12-RA15
I/O
I/O
I/O
ST
ST
ST
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
PORTB is a bidirectional I/O port.
RC1-RC4
RC12-RC15
I/O
I/O
ST
ST
PORTC is a bidirectional I/O port.
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
RD0-RD15
I/O
ST
PORTD is a bidirectional I/O port.
RE0-RE7
I/O
ST
PORTE is a bidirectional I/O port.
RF0-RF8
RF12-RF13
I/O
ST
PORTF is a bidirectional I/O port.
RG0-RG3
RG6-RG9
RG12-RG15
I/O
I/O
I/O
ST
ST
ST
PORTG is a bidirectional I/O port.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
© 2009 Microchip Technology Inc.
Analog = Analog input
O = Output
P = Power
I = Input
DS70175H-page 13
PIC24HJXXXGPX06/X08/X10
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2
I/O
I
O
I/O
I/O
I
O
I/O
ST
ST
—
ST
ST
ST
—
ST
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
Synchronous serial clock input/output for SPI2.
SPI2 data in.
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.
SCL1
SDA1
SCL2
SDA2
I/O
I/O
I/O
I/O
ST
ST
ST
ST
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Synchronous serial clock input/output for I2C2.
Synchronous serial data input/output for I2C2.
SOSCI
SOSCO
I
O
TMS
TCK
TDI
TDO
I
I
I
O
ST
ST
ST
—
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
T1CK
T2CK
T3CK
T4CK
T5CK
T6CK
T7CK
T8CK
T9CK
I
I
I
I
I
I
I
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
Timer6 external clock input.
Timer7 external clock input.
Timer8 external clock input.
Timer9 external clock input.
U1CTS
U1RTS
U1RX
U1TX
U2CTS
U2RTS
U2RX
U2TX
I
O
I
O
I
O
I
O
ST
—
ST
—
ST
—
ST
—
UART1 clear to send.
UART1 ready to send.
UART1 receive.
UART1 transmit.
UART2 clear to send.
UART2 ready to send.
UART2 receive.
UART2 transmit.
VDD
P
—
Positive supply for peripheral logic and I/O pins.
VCAP/VDDCORE
P
—
CPU logic filter capacitor connection.
VSS
P
—
VREF+
I
Analog
Analog voltage reference (high) input.
VREF-
I
Analog
Analog voltage reference (low) input.
Pin Name
Description
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
—
32.768 kHz low-power oscillator crystal output.
Ground reference for logic and I/O pins.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
DS70175H-page 14
Analog = Analog input
O = Output
P = Power
I = Input
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
2.0
Note:
2.1
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
MICROCONTROLLERS
This data sheet summarizes the features
of the PIC24HJXXXGPX06/X08/X10
family of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “PIC24H Family
Reference Manual”, which is available
from
the
Microchip
website
(www.microchip.com).
Basic Connection Requirements
Getting started with the PIC24HJXXXGPX06/X08/X10
family of 16-bit Microcontrollers (MCUs) requires
attention to a minimal set of device pin connections
before proceeding with development. The following is a
list of pin names, which must always be connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2 “Decoupling Capacitors”)
• VCAP/VDDCORE
(see Section 2.3 “Capacitor on Internal Voltage
Regulator (VCAP/VDDCORE)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Additionally, the following pins may be required:
• VREF+/VREF- pins used when external voltage
reference for ADC module is implemented
Note:
2.2
Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
The AVDD and AVSS pins must be
connected independent of the ADC
voltage reference source.
© 2009 Microchip Technology Inc.
DS70175H-page 15
PIC24HJXXXGPX06/X08/X10
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
R1
MCLR
C
PIC24H
VSS
10 Ω
2.2.1
VDD
0.1 µF
Ceramic
VSS
VDD
AVSS
VDD
AVDD
0.1 µF
Ceramic
VSS
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
• Device Reset
• Device programming and debugging
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
VSS
R
VDD
VCAP/VDDCORE
VDD
2.4
0.1 µF
Ceramic
0.1 µF
Ceramic
TANK CAPACITORS
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including MCUs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that connects the power supply source to the device, and the
maximum current drawn by the device in the application. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
2.3
Capacitor on Internal Voltage
Regulator (VCAP/VDDCORE)
A low-ESR (< 5 Ohms) capacitor is required on the
VCAP/VDDCORE pin, which is used to stabilize the
voltage regulator output voltage. The VCAP/VDDCORE
pin must not be connected to VDD, and must have a
capacitor between 4.7 µF and 10 µF, 16V connected to
ground. The type can be ceramic or tantalum. Refer to
Section 24.0 “Electrical Characteristics” for
additional information.
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R
R1
JP
MCLR
PIC24H
C
Note 1:
R ≤ 10 kΩ is recommended. A suggested
starting value is 10 kΩ. Ensure that the
MCLR pin VIH and VIL specifications are met.
2:
R1 ≤ 470Ω will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
The placement of this capacitor should be close to the
VCAP/VDDCORE. It is recommended that the trace
length not exceed one-quarter inch (6 mm). Refer to
Section 21.2 “On-Chip Voltage Regulator” for
details.
DS70175H-page 16
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
2.5
ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 2, MPLAB ICD 3, or MPLAB REAL
ICE™.
For more information on ICD 2, ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip website.
• “MPLAB® ICD 2 In-Circuit Debugger User’s
Guide” DS51331
• “Using MPLAB® ICD 2” (poster) DS51265
• “MPLAB® ICD 2 Design Advisory” DS51566
• “Using MPLAB® ICD 3 In-Circuit Debugger”
(poster) DS51765
• “MPLAB® ICD 3 Design Advisory” DS51764
• “MPLAB® REAL ICE™ In-Circuit Emulator User’s
Guide” DS51616
• “Using MPLAB® REAL ICE™” (poster) DS51749
© 2009 Microchip Technology Inc.
2.6
External Oscillator Pins
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 9.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Main Oscillator
13
Guard Ring
14
15
Guard Trace
Secondary
Oscillator
16
17
18
19
20
DS70175H-page 17
PIC24HJXXXGPX06/X08/X10
2.7
Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < FIN < 8 MHz to comply with device PLL
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration word.
2.8
Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a
debugger, it automatically initializes all of the A/D input
pins (ANx) as “digital” pins, by setting all bits in the
AD1PCFGL register.
The bits in this register that correspond to the A/D pins
that are initialized by MPLAB ICD 2, ICD 3, or REAL
ICE, must not be cleared by the user application
firmware; otherwise, communication errors will result
between the debugger and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 2, ICD 3 or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the AD1PCFGL register. Automatic
initialization of this register is only done during
debugger operation. Failure to correctly configure the
register(s) will result in all A/D pins being recognized as
analog input pins, resulting in the port value being read
as a logic ‘0’, which may affect user application
functionality.
2.9
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternatively, connect a 1k to 10k resistor to VSS on
unused pins and drive the output to logic low.
DS70175H-page 18
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
3.0
Note:
CPU
This data sheet summarizes the features
of the PIC24HJXXXGPX06/X08/X10 family of devices. However, it is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to the “PIC24H Family Reference Manual”, Section 2. “CPU”
(DS70245), which is available from the
Microchip website (www.microchip.com).
The PIC24HJXXXGPX06/X08/X10 CPU module has a
16-bit (data) modified Harvard architecture with an
enhanced instruction set and addressing modes. The
CPU has a 24-bit instruction word with a variable length
opcode field. The Program Counter (PC) is 23 bits wide
and addresses up to 4M x 24 bits of user program
memory space. The actual amount of program memory
implemented varies by device. A single-cycle instruction
prefetch mechanism is used to help maintain throughput
and provides predictable execution. All instructions
execute in a single cycle, with the exception of
instructions that change the program flow, the double
word move (MOV.D) instruction and the table instructions.
Overhead-free, single-cycle program loop constructs are
supported using the REPEAT instruction, which is
interruptible at any point.
The PIC24HJXXXGPX06/X08/X10 devices have
sixteen, 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a data,
address or address offset register. The 16th working
register (W15) operates as a software Stack Pointer (SP)
for interrupts and calls.
3.1
Data Addressing Overview
The data space can be linearly addressed as 32K words
or 64 Kbytes using an Address Generation Unit (AGU).
The upper 32 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space
Visibility Page (PSVPAG) register. The program to data
space mapping feature lets any instruction access program space as if it were data space.
The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers, but may
be used as general purpose RAM.
3.2
Special MCU Features
The PIC24HJXXXGPX06/X08/X10 features a 17-bit by
17-bit, single-cycle multiplier. The multiplier can
perform
signed,
unsigned
and
mixed-sign
multiplication. Using a 17-bit by 17-bit multiplier for
16-bit by 16-bit multiplication makes mixed-sign
multiplication possible.
The PIC24HJXXXGPX06/X08/X10 supports 16/16 and
32/16 integer divide operations. All divide instructions
are iterative operations. They must be executed within
a REPEAT loop, resulting in a total execution time of 19
instruction cycles. The divide operation can be
interrupted during any of those 19 cycles without loss
of data.
A multi-bit data shifter is used to perform up to a 16-bit,
left or right shift in a single cycle.
The PIC24HJXXXGPX06/X08/X10 instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
the PIC24HJXXXGPX06/X08/X10 is capable of
executing a data (or program data) memory read, a
working register (data) read, a data memory write and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in Figure 3-1,
and
the
programmer’s
model
for
the
PIC24HJXXXGPX06/X08/X10 is shown in Figure 3-2.
© 2009 Microchip Technology Inc.
DS70175H-page 19
PIC24HJXXXGPX06/X08/X10
FIGURE 3-1:
PIC24HJXXXGPX06/X08/X10 CPU CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
X Data Bus
Interrupt
Controller
8
16
16
16
Data Latch
23
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
DMA
X RAM
RAM
16
Address
Latch
23
16
DMA
Controller
Address Generator Units
Address Latch
Program Memory
EA MUX
Data Latch
ROM Latch
24
Control Signals
to Various Blocks
Instruction Reg
Literal Data
Instruction
Decode and
Control
16
16
16
17 x 17
Multiplier
Divide Support
16 x 16
W Register Array
16
16-bit ALU
16
To Peripheral Modules
DS70175H-page 20
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
FIGURE 3-2:
PIC24HJXXXGPX06/X08/X10 PROGRAMMER’S MODEL
D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
W5
W6
W7
Working Registers
W8
W9
W10
W11
W12
W13
W14/Frame Pointer
W15/Stack Pointer
Stack Pointer Limit Register
SPLIM
PC22
PC0
Program Counter
0
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
RCOUNT
REPEAT Loop Counter
15
0
Core Configuration Register
CORCON
—
—
—
—
—
—
— DC
SRH
3.3
IPL2 IPL1 IPL0 RA
N
OV
Z
C
STATUS Register
SRL
CPU Control Registers
© 2009 Microchip Technology Inc.
DS70175H-page 21
PIC24HJXXXGPX06/X08/X10
REGISTER 3-1:
SR: CPU STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
DC
bit 15
bit 8
R/W-0(1)
R/W-0(2)
R/W-0(2)
IPL(2)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RA
N
OV
Z
C
bit 7
bit 0
Legend:
C = Clear only bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
S = Set only bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented: Read as ‘0’
bit 8
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized
data) of the result occurred
bit 7-5
IPL: CPU Interrupt Priority Level Status bits(2)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4
RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3
N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1
Z: MCU ALU Zero bit
1 = An operation which affects the Z bit has set it at some time in the past
0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result)
bit 0
C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit (MSb) of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when
IPL = 1.
2: The IPL Status bits are read only when NSTDIS = 1 (INTCON1).
DS70175H-page 22
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER
U-0
—
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 8
U-0
—
U-0
—
R/C-0
IPL3(1)
R/W-0
PSV
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
0’ = Bit is cleared
bit 15-4
bit 3
bit 2
bit 1-0
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
Unimplemented: Read as ‘0’
IPL3: CPU Interrupt Priority Level Status bit 3(1)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
Unimplemented: Read as ‘0’
Note 1: The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level.
© 2009 Microchip Technology Inc.
DS70175H-page 23
PIC24HJXXXGPX06/X08/X10
3.4
Arithmetic Logic Unit (ALU)
The PIC24HJXXXGPX06/X08/X10 ALU is 16 bits wide
and is capable of addition, subtraction, bit shifts and
logic operations. Unless otherwise mentioned,
arithmetic operations are 2’s complement in nature.
Depending on the operation, the ALU may affect the
values of the Carry (C), Zero (Z), Negative (N),
Overflow (OV) and Digit Carry (DC) Status bits in the
SR register. The C and DC Status bits operate as
Borrow and Digit Borrow bits, respectively, for
subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from
the ALU can be written to the W register array or a data
memory location.
Refer to the “dsPIC30F/33F Programmer’s Reference
Manual” (DS70157) for information on the SR bits
affected by each instruction.
The PIC24HJXXXGPX06/X08/X10 CPU incorporates
hardware support for both multiplication and division.
This includes a dedicated hardware multiplier and
support hardware for 16-bit divisor division.
3.4.1
MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier, the ALU
supports unsigned, signed or mixed-sign operation in
several multiplication modes:
1.
2.
3.
4.
5.
6.
7.
3.4.2
DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
1.
2.
3.
4.
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. Sixteen-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn) and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
3.4.3
MULTI-BIT DATA SHIFTER
The multi-bit data shifter is capable of performing up to
16-bit arithmetic or logic right shifts, or up to 16-bit left
shifts in a single cycle. The source can be either a
working register or a memory location.
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
DS70175H-page 24
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
4.0
MEMORY ORGANIZATION
Note:
4.1
This data sheet summarizes the features
of the PIC24HJXXXGPX06/X08/X10 family of devices. However, it is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to the “PIC24H Family Reference Manual”, Section 3. “Data Memory”
(DS70237), which is available from the
Microchip website (www.microchip.com).
The PIC24HJXXXGPX06/X08/X10 architecture features separate program and data memory spaces and
buses. This architecture also allows the direct access
of program memory from the data space during code
execution.
FIGURE 4-1:
The program address memory space of the
PIC24HJXXXGPX06/X08/X10 devices is 4M instructions.
The space is addressable by a 24-bit value derived from
either the 23-bit Program Counter (PC) during program
execution, or from table operation or data space remapping as described in Section 4.4 “Interfacing Program
and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (0x000000 to
0x7FFFFF). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24HJXXXGPX06/X08/X10
family of devices are shown in Figure 4-1.
PROGRAM MEMORY MAP FOR PIC24HJXXXGPX06/X08/X10 FAMILY DEVICES
PIC24HJ64XXXXX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Memory Space
Program Address Space
User Program
Flash Memory
(22K instructions)
PIC24HJ128XXXXX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
PIC24HJ256XXXXX
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(44K instructions)
User Program
Flash Memory
(88K instructions)
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x00ABFE
0x00AC00
0x0157FE
0x015800
Unimplemented
(Read ‘0’s)
Unimplemented
0x02ABFE
0x02AC00
(Read ‘0’s)
Unimplemented
(Read ‘0’s)
Configuration Memory Space
0x7FFFFE
0x800000
Reserved
Reserved
Reserved
Device Configuration
Registers
Device Configuration
Registers
Device Configuration
Registers
Reserved
Reserved
Reserved
DEVID (2)
DEVID (2)
DEVID (2)
© 2009 Microchip Technology Inc.
0xF7FFFE
0xF80000
0xF80017
0xF80010
0xFEFFFE
0xFF0000
0xFFFFFE
DS70175H-page 25
PIC24HJXXXGPX06/X08/X10
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.2
All PIC24HJXXXGPX06/X08/X10 devices reserve the
addresses between 0x00000 and 0x000200 for hardcoded program execution vectors. A hardware Reset
vector is provided to redirect code execution from the
default value of the PC on device Reset to the actual
start of code. A GOTO instruction is programmed by the
user at 0x000000, with the actual address for the start
of code at 0x000002.
The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-2).
PIC24HJXXXGPX06/X08/X10 devices also have two
interrupt vector tables, located from 0x000004 to
0x0000FF and 0x000100 to 0x0001FF. These vector
tables allow each of the many device interrupt sources
to be handled by separate Interrupt Service Routines
(ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector
Table”.
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
FIGURE 4-2:
msw
Address
PROGRAM MEMORY ORGANIZATION
16
8
PC Address
(lsw Address)
0
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
DS70175H-page 26
least significant word
most significant word
23
0x000001
0x000003
0x000005
0x000007
INTERRUPT AND TRAP VECTORS
Instruction Width
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
4.2
Data Address Space
The PIC24HJXXXGPX06/X08/X10 CPU has a separate 16-bit wide data memory space. The data space is
accessed using separate Address Generation Units
(AGUs) for read and write operations. Data memory
maps of devices with different RAM sizes are shown in
Figure 4-3 and Figure 4-4.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA = 0) is used for
implemented memory addresses, while the upper half
(EA = 1) is reserved for the Program Space
Visibility area (see Section 4.4.3 “Reading Data from
Program Memory Using Program Space Visibility”).
PIC24HJXXXGPX06/X08/X10 devices implement up
to 16 Kbytes of data memory. Should an EA point to a
location outside of this area, an all-zero word or byte
will be returned.
4.2.1
DATA SPACE WIDTH
The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes of each word have even addresses, while the
Most Significant Bytes have odd addresses.
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCU
devices and improve data space memory usage
efficiency, the PIC24HJXXXGPX06/X08/X10 instruction set supports both word and byte operations. As a
consequence of byte accessibility, all effective address
calculations are internally scaled to step through wordaligned memory. For example, the core recognizes that
Post-Modified Register Indirect Addressing mode
[Ws++] will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
Data byte reads will read the complete word that
contains the byte, using the Least Significant bit (LSb)
of any EA to determine which byte to select. The
selected byte is placed onto the Least Significant Byte
(LSB) of the data path. That is, data memory and registers are organized as two parallel byte-wide entities
with shared (word) address decode but separate write
lines. Data byte writes only write to the corresponding
side of the array or register which matches the byte
address.
© 2009 Microchip Technology Inc.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed; if it occurred on a
write, the instruction will be executed but the write does
not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine
state prior to execution of the address Fault.
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte
(MSB) is not modified.
A sign-extend instruction (SE) is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the Most Significant Byte of any W register by
executing a zero-extend (ZE) instruction on the
appropriate address.
4.2.3
SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
PIC24HJXXXGPX06/X08/X10 core and peripheral
modules for controlling the operation of the device.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A complete listing of implemented
SFRs, including their addresses, is shown in Table 4-1
through Table 4-33.
Note:
4.2.4
The actual set of peripheral features and
interrupts varies by the device. Please
refer to the corresponding device tables
and pinout diagrams for device-specific
information.
NEAR DATA SPACE
The 8-Kbyte area between 0x0000 and 0x1FFF is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an Address Pointer.
DS70175H-page 27
PIC24HJXXXGPX06/X08/X10
FIGURE 4-3:
DATA MEMORY MAP FOR PIC24HJXXXGPX06/X08/X10 DEVICES WITH 8 KBS RAM
MSB
Address
MSB
2 Kbyte
SFR Space
LSB
Address
16 bits
LSB
0x0000
0x0001
SFR Space
0x07FE
0x0800
0x07FF
0x0801
8 Kbyte
Near
Data
Space
X Data RAM (X)
8 Kbyte
SRAM Space
0x1FFF
0x2001
0x27FF
0x2801
0x1FFE
0x2000
DMA RAM
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
DS70175H-page 28
0x27FE
0x2800
0xFFFE
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
FIGURE 4-4:
DATA MEMORY MAP FOR PIC24HJXXXGPX06/X08/X10 DEVICES WITH 16 KBS
RAM
MSB
Address
LSB
Address
16 bits
MSB
LSB
0x0000
0x0001
2 Kbyte
SFR Space
SFR Space
0x07FE
0x0800
0x07FF
0x0801
0x1FFF
8 Kbyte
Near
Data
Space
0x1FFE
X Data RAM (X)
16 Kbyte
SRAM Space
0x3FFF
0x4001
0x47FF
0x4801
0x3FFE
0x4000
DMA RAM
0x47FE
0x4800
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
4.2.5
DMA RAM
Every PIC24HJXXXGPX06/X08/X10 device contains 2
Kbytes of dual ported DMA RAM located at the end of
data space. Memory locations in the DMA RAM space
are accessible simultaneously by the CPU and the DMA
controller module. DMA RAM is utilized by the DMA
controller to store data to be transferred to various
peripherals using DMA, as well as data transferred from
0xFFFE
various peripherals using DMA. The DMA RAM can be
accessed by the DMA controller without having to steal
cycles from the CPU.
When the CPU and the DMA controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.
Note:
© 2009 Microchip Technology Inc.
DMA RAM can be used for general
purpose data storage if the DMA function
is not required in an application.
DS70175H-page 29
CPU CORE REGISTERS MAP
All
Resets
SFR Name
SFR
Addr
WREG0
0000
Working Register 0
0000
WREG1
0002
Working Register 1
0000
WREG2
0004
Working Register 2
0000
WREG3
0006
Working Register 3
0000
WREG4
0008
Working Register 4
0000
WREG5
000A
Working Register 5
0000
WREG6
000C
Working Register 6
0000
WREG7
000E
Working Register 7
0000
WREG8
0010
Working Register 8
0000
WREG9
0012
Working Register 9
0000
WREG10
0014
Working Register 10
0000
WREG11
0016
Working Register 11
0000
WREG12
0018
Working Register 12
0000
WREG13
001A
Working Register 13
0000
WREG14
001C
Working Register 14
0000
WREG15
001E
Working Register 15
0800
SPLIM
0020
Stack Pointer Limit Register
xxxx
PCL
002E
Program Counter Low Word Register
PCH
0030
—
—
—
—
—
—
—
—
Program Counter High Byte Register
0000
TBLPAG
0032
—
—
—
—
—
—
—
—
Table Page Address Pointer Register
0000
PSVPAG
0034
—
—
—
—
—
—
—
—
Program Memory Visibility Page Address Pointer Register
0000
RCOUNT
0036
SR
0042
—
—
—
—
—
—
—
DC
CORCON
0044
—
—
—
—
—
—
—
—
DISICNT
0052
—
—
BSRAM
0750
—
—
—
—
—
—
—
—
—
SSRAM
0752
—
—
—
—
—
—
—
—
—
© 2009 Microchip Technology Inc.
Legend:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000
Repeat Loop Counter Register
xxxx
IPL
—
—
RA
N
OV
Z
C
0000
—
IPL3
PSV
—
—
0000
—
—
—
IW_BSR
IR_BSR
RL_BSR
0000
—
—
—
IW_SSR
IR_SSR
RL_SSR
0000
—
Disable Interrupts Counter Register
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
xxxx
PIC24HJXXXGPX06/X08/X10
DS70175H-page 30
TABLE 4-1:
© 2009 Microchip Technology Inc.
TABLE 4-2:
CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJXXXGPX10 DEVICES
SFR
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
CNEN1
0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CNEN2
0062
—
—
—
—
—
—
—
—
CN23IE
CN22IE
CN21IE
CN20IE
CN19IE
CN18IE
CNPU1
0068
CN9PUE
CN8PUE
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CNPU2
006A
—
—
Legend:
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE
—
—
—
—
—
—
Bit 0
All
Resets
CN1IE
CN0IE
0000
CN17IE
CN16IE
0000
CN0PUE
0000
CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-3:
CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJXXXGPX08 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
CNEN1
0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CNEN2
0062
—
—
—
—
—
—
—
—
—
—
CN21IE
CN20IE
CN19IE
CN18IE
CNPU1
0068
CN9PUE
CN8PUE
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CNPU2
006A
—
—
—
—
Legend:
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE
—
—
—
—
—
—
Bit 0
All
Resets
CN1IE
CN0IE
0000
CN17IE
CN16IE
0000
CN0PUE
0000
CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
0000
Bit 5
Bit 3
Bit 2
Bit 1
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-4:
CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJXXXGPX06 DEVICES
SFR
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
CNEN1
0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CNEN2
0062
—
—
—
—
—
—
—
—
—
—
CNPU1
0068
CN9PUE
CN8PUE
CN7PUE
CN6PUE
CN5PUE
CNPU2
006A
—
—
—
—
Legend:
Bit 4
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 5
Bit 0
All
Resets
CN1IE
CN0IE
0000
CN17IE
CN16IE
0000
CN0PUE
0000
CN18PUE CN17PUE CN16PUE
0000
Bit 4
Bit 3
CN5IE
CN4IE
CN3IE
CN2IE
CN21IE
CN20IE
—
CN18IE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN21PUE CN20PUE
—
Bit 2
Bit 1
DS70175H-page 31
PIC24HJXXXGPX06/X08/X10
SFR
Name
INTERRUPT CONTROLLER REGISTER MAP
SFR
Name
SFR
Addr
Bit 15
INTCON1
0080
INTCON2
0082
IFS0
IFS1
Bit 5
Bit 4
Bit 3
All
Resets
OSCFAIL
—
0000
INT1EP
INT0EP
0000
OC1IF
IC1IF
INT0IF
0000
—
MI2C1IF
SI2C1IF
0000
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
NSTDIS
—
—
—
—
—
—
—
—
ALTIVT
DISI
—
—
—
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
0084
—
DMA1IF
AD1IF
U1TXIF
U1RXIF
T3IF
T2IF
OC2IF
IC2IF
DMA0IF
T1IF
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
DMA2IF
IC8IF
IC7IF
AD2IF
INT1IF
CNIF
SPI1IF SPI1EIF
Bit 6
Bit 0
Bit 14
Bit 2
Bit 1
DIV0ERR DMACERR MATHERR ADDRERR STKERR
IFS2
0088
T6IF
DMA4IF
—
OC8IF
OC7IF
OC6IF
OC5IF
IC6IF
IC5IF
IC4IF
IC3IF
DMA3IF
C1IF
C1RXIF
SPI2IF
SPI2EIF
0000
IFS3
008A
—
—
DMA5IF
—
—
—
—
C2IF
C2RXIF
INT4IF
INT3IF
T9IF
T8IF
MI2C2IF
SI2C2IF
T7IF
0000
IFS4
008C
—
—
—
—
—
—
—
—
C2TXIF
C1TXIF
DMA7IF
DMA6IF
—
U2EIF
U1EIF
—
0000
IEC0
0094
—
DMA1IE
AD1IE
U1TXIE
U1RXIE
T3IE
T2IE
OC2IE
IC2IE
DMA0IE
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
DMA2IE
IC8IE
IC7IE
AD2IE
INT1IE
CNIE
—
MI2C1IE SI2C1IE
0000
SPI1IE SPI1EIE
IEC2
0098
T6IE
DMA4IE
—
OC8IE
OC7IE
OC6IE
OC5IE
IC6IE
IC5IE
IC4IE
IC3IE
DMA3IE
C1IE
C1RXIE
SPI2IE
SPI2EIE
0000
IEC3
009A
—
—
DMA5IE
—
—
—
—
C2IE
C2RXIE
INT4IE
INT3IE
T9IE
T8IE
MI2C2IE
SI2C2IE
T7IE
0000
IEC4
009C
—
—
—
—
—
—
—
—
C2TXIE
C1TXIE
DMA7IE
DMA6IE
—
U2EIE
U1EIE
—
IPC0
00A4
—
IPC1
00A6
IPC2
00A8
IPC3
00AA
—
IPC4
00AC
—
CNIP
—
IPC5
00AE
—
IC8IP
—
IPC6
00B0
—
T4IP
IPC7
00B2
—
IPC8
00B4
IPC9
—
© 2009 Microchip Technology Inc.
—
INT0IP
4444
—
T2IP
—
U1RXIP
—
IC2IP
—
DMA0IP
4444
—
SPI1EIP
—
T3IP
4444
—
AD1IP
—
U1TXIP
0444
—
MI2C1IP
—
SI2C1IP
4044
IC7IP
—
AD2IP
—
INT1IP
4444
—
OC4IP
—
OC3IP
—
DMA2IP
4444
U2TXIP
—
U2RXIP
—
INT2IP
—
T5IP
4444
—
C1IP
—
C1RXIP
—
SPI2IP
—
SPI2EIP
4444
00B6
—
IC5IP
—
IC4IP
—
IC3IP
—
DMA3IP
4444
IPC10
00B8
—
OC7IP
—
OC6IP
—
OC5IP
—
IC6IP
4444
IPC11
00BA
—
T6IP
—
DMA4IP
—
—
OC8IP
4404
IPC12
00BC
—
T8IP
—
MI2C2IP
—
SI2C2IP
—
T7IP
4444
IPC13
00BE
—
C2RXIP
—
INT4IP
—
INT3IP
—
T9IP
4444
IPC14
00C0
—
—
—
—
—
—
—
—
—
—
C2IP
IPC15
00C2
—
—
—
—
—
—
—
—
—
DMA5IP
—
—
—
—
IPC16
00C4
—
—
—
—
—
U2EIP
—
U1EIP
—
—
—
—
IPC17
00C6
—
—
C1TXIP
—
DMA7IP
—
INTTREG
00E0
—
—
—
—
C2TXIP
—
—
—
OC1IP
—
—
OC2IP
—
SPI1IP
—
DMA1IP
0000
IC1IP
Legend:
T1IP
—
—
ILR
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
—
—
VECNUM
DMA6IP
0004
0040
0440
4444
0000
PIC24HJXXXGPX06/X08/X10
DS70175H-page 32
TABLE 4-5:
© 2009 Microchip Technology Inc.
TABLE 4-6:
SFR
Name
SFR
Addr
TIMER REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0100
Timer1 Register
PR1
0102
Period Register 1
T1CON
0104
TMR2
0106
Timer2 Register
xxxx
TMR3HLD
0108
Timer3 Holding Register (for 32-bit timer operations only)
xxxx
TMR3
010A
Timer3 Register
xxxx
PR2
010C
Period Register 2
FFFF
PR3
010E
Period Register 3
T2CON
0110
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
T3CON
0112
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
—
—
TCS
—
0000
TMR4
0114
Timer4 Register
xxxx
TMR5HLD
0116
Timer5 Holding Register (for 32-bit operations only)
xxxx
TMR5
0118
Timer5 Register
xxxx
PR4
011A
Period Register 4
FFFF
PR5
011C
Period Register 5
T4CON
011E
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
T5CON
0120
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
—
—
TCS
—
0000
TMR6
0122
Timer6 Register
xxxx
TMR7HLD
0124
Timer7 Holding Register (for 32-bit operations only)
xxxx
TMR7
0126
Timer7 Register
xxxx
PR6
0128
Period Register 6
FFFF
PR7
012A
Period Register 7
T6CON
012C
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
T7CON
012E
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
—
—
TCS
—
0000
TMR8
0130
Timer8 Register
xxxx
TMR9HLD
0132
Timer9 Holding Register (for 32-bit operations only)
xxxx
TMR9
0134
Timer9 Register
xxxx
PR8
0136
Period Register 8
FFFF
PR9
0138
Period Register 9
T8CON
013A
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
T9CON
013C
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
—
—
TCS
—
0000
Legend:
TON
—
TSIDL
—
—
—
—
—
—
xxxx
FFFF
TGATE
TCKPS
—
TSYNC
TCS
—
0000
FFFF
FFFF
FFFF
FFFF
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
PIC24HJXXXGPX06/X08/X10
DS70175H-page 33
TMR1
SFR Name
SFR
Addr
IC1BUF
0140
IC1CON
0142
IC2BUF
0144
IC2CON
0146
IC3BUF
0148
IC3CON
014A
IC4BUF
014C
IC4CON
014E
IC5BUF
0150
IC5CON
0152
IC6BUF
0154
IC6CON
0156
IC7BUF
0158
IC7CON
015A
IC8BUF
015C
IC8CON
015E
Legend:
INPUT CAPTURE REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
—
ICSIDL
—
—
—
—
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
Input 1 Capture Register
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
0000
xxxx
Input 8 Capture Register
—
0000
xxxx
Input 7 Capture Register
—
0000
xxxx
Input 6 Capture Register
—
0000
xxxx
Input 5 Capture Register
—
0000
xxxx
Input 4 Capture Register
—
0000
xxxx
Input 3 Capture Register
—
All
Resets
xxxx
Input 2 Capture Register
—
Bit 0
0000
xxxx
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
0000
PIC24HJXXXGPX06/X08/X10
DS70175H-page 34
TABLE 4-7:
© 2009 Microchip Technology Inc.
© 2009 Microchip Technology Inc.
TABLE 4-8:
SFR Name
OUTPUT COMPARE REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
0180
Output Compare 1 Secondary Register
OC1R
0182
Output Compare 1 Register
OC1CON
0184
OC2RS
0186
Output Compare 2 Secondary Register
OC2R
0188
Output Compare 2 Register
OC2CON
018A
OC3RS
018C
Output Compare 3 Secondary Register
OC3R
018E
Output Compare 3 Register
OC3CON
0190
OC4RS
0192
Output Compare 4 Secondary Register
OC4R
0194
Output Compare 4 Register
OC4CON
0196
OC5RS
0198
Output Compare 5 Secondary Register
OC5R
019A
Output Compare 5 Register
OC5CON
019C
OC6RS
019E
Output Compare 6 Secondary Register
OC6R
01A0
Output Compare 6 Register
OC6CON
01A2
OC7RS
01A4
Output Compare 7 Secondary Register
OC7R
01A6
Output Compare 7 Register
OC7CON
01A8
OC8RS
01AA
Output Compare 8 Secondary Register
OC8R
01AC
Output Compare 8 Register
OC8CON
01AE
Legend:
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
OCFLT
OCTSEL
OCM
0000
DS70175H-page 35
PIC24HJXXXGPX06/X08/X10
OC1RS
Bit 5
I2C1 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
I2C1RCV
0200
—
—
—
—
—
—
—
—
Receive Register
0000
I2C1TRN
0202
—
—
—
—
—
—
—
—
Transmit Register
00FF
I2C1BRG
0204
—
—
—
—
—
—
—
I2C1CON
0206
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
I2C1STAT
0208
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
0000
I2C1ADD
020A
—
—
—
—
—
—
Address Register
0000
I2C1MSK
020C
—
—
—
—
—
—
Address Mask Register
0000
SFR Name
Legend:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Baud Rate Generator Register
All
Resets
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-10:
I2C2 REGISTER MAP
All
Resets
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
I2C2RCV
0210
—
—
—
—
—
—
—
—
Receive Register
0000
I2C2TRN
0212
—
—
—
—
—
—
—
—
Transmit Register
00FF
I2C2BRG
0214
—
—
—
—
—
—
—
I2C2CON
0216
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
I2C2STAT
0218
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
0000
I2C2ADD
021A
—
—
—
—
—
—
Address Register
0000
I2C2MSK
021C
—
—
—
—
—
—
Address Mask Register
0000
SFR Name
Legend:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Baud Rate Generator Register
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-11:
SFR Name
Bit 7
SFR
Addr
UART1 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
© 2009 Microchip Technology Inc.
Bit 8
Bit 7
Bit 6
WAKE
LPBACK
Bit 5
Bit 4
Bit 3
ABAUD
URXINV
BRGH
ADDEN
RIDLE
PERR
Bit 2
Bit 1
All
Resets
STSEL
0000
URXDA
0110
U1MODE
0220
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
U1STA
0222
UTXISEL1
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
U1TXREG
0224
—
—
—
—
—
—
—
UART Transmit Register
xxxx
U1RXREG
0226
—
—
—
—
—
—
—
UART Receive Register
0000
U1BRG
0228
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
URXISEL
Baud Rate Generator Prescaler
PDSEL
Bit 0
FERR
OERR
0000
PIC24HJXXXGPX06/X08/X10
DS70175H-page 36
TABLE 4-9:
© 2009 Microchip Technology Inc.
TABLE 4-12:
SFR
Name
SFR
Addr
UART2 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
WAKE
LPBACK
Bit 5
Bit 4
Bit 3
ABAUD
URXINV
BRGH
ADDEN
RIDLE
PERR
Bit 2
Bit 1
All
Resets
STSEL
0000
URXDA
0110
U2MODE
0230
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
U2STA
0232
UTXISEL1
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
U2TXREG
0234
—
—
—
—
—
—
—
UART Transmit Register
xxxx
U2RXREG
0236
—
—
—
—
—
—
—
UART Receive Register
0000
U2BRG
0238
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-13:
SFR
Name
URXISEL
OERR
0000
SPI1 REGISTER MAP
Bit 14
Bit 13
SPI1STAT
0240
SPIEN
—
SPISIDL
—
—
—
—
SPI1CON1
0242
—
—
—
DISSCK
DISSDO
MODE16
SMP
SPI1CON2
0244
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
SPI1BUF
0248
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
—
—
CKE
SSEN
SPIROV
—
—
CKP
MSTEN
—
—
—
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
SPITBF
SPIRBF
0000
SPRE
—
—
PPRE
—
FRMDLY
—
SPI1 Transmit and Receive Buffer Register
0000
0000
0000
SPI2 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
SPI2STAT
0260
SPIEN
—
SPISIDL
—
—
—
—
SPI2CON1
0262
—
—
—
DISSCK
DISSDO
MODE16
SMP
SPI2CON2
0264
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
SPI2BUF
0268
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
—
—
CKE
SSEN
SPIROV
—
—
CKP
MSTEN
—
—
—
SPI2 Transmit and Receive Buffer Register
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
SPITBF
SPIRBF
0000
SPRE
—
—
PPRE
—
FRMDLY
—
0000
0000
0000
DS70175H-page 37
PIC24HJXXXGPX06/X08/X10
Bit 15
SFR Name
FERR
Baud Rate Generator Prescaler
SFR
Addr
TABLE 4-14:
PDSEL
Bit 0
File Name
ADC1 REGISTER MAP
Addr
ADC1BUF0
0300
AD1CON1
0320
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
ADON
—
ADSIDL
ADDMABM
—
AD12B
FORM
—
—
CSCNA
CHPS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
SIMSAM
ASAM
SAMP
DONE
0000
BUFM
ALTS
0000
CH123SA
0000
ADC Data Buffer 0
AD1CON2
0322
AD1CON3
0324
ADRC
VCFG
—
—
AD1CHS123
0326
—
—
—
—
xxxx
SSRC
BUFS
—
SMPI
SAMC
—
—
ADCS
CH123NB
CH123SB
—
—
—
—
—
0000
CH123NA
AD1CHS0
0328
CH0NB
CH0NA
—
—
AD1PCFGH(1)
032A
PCFG31 PCFG30
PCFG29
PCFG28
PCFG27 PCFG26 PCFG25
PCFG24
PCFG23
PCFG22
PCFG21
PCFG20
PCFG19 PCFG18 PCFG17
PCFG16
0000
AD1PCFGL
032C
PCFG15 PCFG14
PCFG13
PCFG12
PCFG11 PCFG10
PCFG9
PCFG8
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000
AD1CSSH(1)
032E
CSS31
CSS30
CSS29
CSS28
CSS27
CSS26
CSS25
CSS24
CSS23
CSS22
CSS21
CSS20
CSS19
CSS18
CSS17
CSS16
0000
AD1CSSL
0330
CSS15
CSS14
CSS13
CSS12
CSS11
CSS10
CSS9
CSS8
CSS7
CSS6
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
AD1CON4
0332
—
—
—
—
—
—
—
—
—
—
—
—
—
Reserved
0334033E
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
SIMSAM
ASAM
SAMP
DONE
BUFM
ALTS
Legend:
Note 1:
Addr
ADC2BUF0
0340
AD2CON1
0360
AD2CON2
0362
AD2CON3
0364
AD2CHS123
AD2CHS0
CH0SA
0000
DMABL
0000
0000
ADC2 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
ADON
—
ADSIDL
ADDMABM
—
AD12B
FORM
Bit 9
Bit 8
—
—
CSCNA
CHPS
Bit 7
Bit 6
ADC Data Buffer 0
VCFG
© 2009 Microchip Technology Inc.
ADRC
—
—
0366
—
—
—
—
0368
CH0NB
—
—
—
—
—
Reserved
036A
AD2PCFGL
036C
Reserved
036E
—
AD2CSSL
0370
AD2CON4
0372
Reserved
0374037E
Legend:
CH0SB
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Not all ANx inputs are available on all devices. See the device pin diagrams for available ANx inputs.
TABLE 4-16:
File Name
—
BUFS
—
SMPI
SAMC
—
ADCS
CH123NB
CH123SB
CH0SB
—
—
PCFG13
PCFG12
—
—
—
—
CSS15
CSS14
CSS13
CSS12
—
—
—
—
—
—
—
—
PCFG15 PCFG14
xxxx
SSRC
—
—
—
—
—
—
CH0NA
—
—
—
—
0000
0000
0000
CH123NA
CH123SA
CH0SA
0000
0000
—
—
—
—
—
—
—
—
—
—
PCFG9
PCFG8
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000
—
—
—
—
—
—
—
—
—
—
—
0000
CSS11
CSS10
CSS9
CSS8
CSS7
CSS6
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
PCFG11 PCFG10
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
DMABL
—
—
0000
0000
PIC24HJXXXGPX06/X08/X10
DS70175H-page 38
TABLE 4-15:
© 2009 Microchip Technology Inc.
TABLE 4-17:
File Name Addr
DMA REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DMA0CON 0380
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
—
DMA0REQ 0382
FORCE
—
—
—
—
—
—
—
—
Bit 5
Bit 4
AMODE
Bit 3
Bit 2
—
—
Bit 1
Bit 0
MODE
IRQSEL
All
Resets
0000
0000
DMA0STA
0384
STA
0000
DMA0STB
0386
STB
0000
DMA0PAD
0388
PAD
DMA0CNT
038A
—
—
—
—
—
—
DMA1CON 038C
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA1REQ 038E
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA1STA
0390
STA
0000
DMA1STB
0392
STB
0000
DMA1PAD
0394
PAD
DMA1CNT
0396
—
—
—
—
—
DMA2CON 0398
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA2REQ 039A
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA2STA
039C
STA
0000
DMA2STB
039E
STB
0000
DMA2PAD
03A0
PAD
DMA2CNT
03A2
—
—
—
—
—
—
DMA3CON 03A4
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA3REQ 03A6
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA3STA
03A8
STA
0000
DMA3STB
03AA
STB
0000
DMA3PAD
03AC
PAD
DMA3CNT 03AE
—
—
—
—
—
—
DMA4CON 03B0
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA4REQ 03B2
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA4STA
03B4
STA
0000
DMA4STB
03B6
STB
0000
DMA4PAD
03B8
PAD
DMA4CNT 03BA
DS70175H-page 39
—
—
—
—
—
—
DMA5CON 03BC
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA5REQ 03BE
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
IRQSEL
—
MODE
0000
0000
DMA5STA
03C0
STA
0000
DMA5STB
03C2
STB
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
PIC24HJXXXGPX06/X08/X10
—
File Name Addr
DMA REGISTER MAP (CONTINUED)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
DMA5CNT 03C6
—
—
—
—
—
—
DMA6CON 03C8
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
—
—
—
—
—
—
—
—
DMA5PAD
Bit 9
Bit 8
03C4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PAD
DMA6REQ 03CA FORCE
All
Resets
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA6STA
03CC
STA
0000
DMA6STB
03CE
STB
0000
DMA6PAD
03D0
PAD
DMA6CNT 03D2
—
—
—
—
—
—
DMA7CON 03D4
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA7REQ 03D6
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA7STA
03D8
STA
0000
DMA7STB
03DA
STB
0000
DMA7PAD 03DC
PAD
DMA7CNT 03DE
—
—
—
—
—
CNT
DMACS0
03E0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0
DMACS1
03E2
DSADR
03E4
Legend:
—
—
—
—
0000
—
LSTCH
XWCOL7
PPST7
DSADR
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
XWCOL6 XWCOL5
PPST6
PPST5
0000
XWCOL4
XWCOL3
XWCOL2
PPST4
PPST3
PPST2
XWCOL1 XWCOL0
PPST1
PPST0
0000
0000
0000
PIC24HJXXXGPX06/X08/X10
DS70175H-page 40
TABLE 4-17:
© 2009 Microchip Technology Inc.
© 2009 Microchip Technology Inc.
TABLE 4-18:
File Name
ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 OR 1 FOR PIC24HJXXXGP506/510/610 DEVICES ONLY
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
C1CTRL1
0400
—
—
CSIDL
ABAT
—
C1CTRL2
0402
—
—
—
—
—
C1VEC
0404
—
—
—
C1FCTRL
0406
DMABS
Bit 10
Bit 9
Bit 8
Bit 7
—
—
REQOP
—
—
TXBP
—
Bit 5
OPMODE
—
FILHIT
—
Bit 6
—
—
—
—
RXBP
TXWAR
RXWAR
EWARN
IVRIF
WAKIF
ERRIF
—
—
—
—
IVRIE
WAKIE
ERRIE
0408
—
—
—
—
TXBO
C1INTE
040C
—
—
—
C1EC
040E
C1CFG1
0410
—
—
—
—
—
C1CFG2
0412
—
WAKFIL
—
—
—
C1FEN1
0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10
CANCAP
FBP
Bit 2
Bit 1
Bit 0
All
Resets
—
—
WIN
0480
DNCNT
0000
ICODE
—
040A
—
—
—
C1INTF
Bit 3
—
—
C1FIFO
Bit 4
—
—
0000
FSA
0000
FNRB
TERRCNT
0000
—
FIFOIF
RBOVIF
RBIF
TBIF
—
FIFOIE
RBOVIE
RBIE
TBIE
RERRCNT
—
—
—
SEG2PH
FLTEN9
FLTEN8
SJW
SAM
FLTEN7
FLTEN6
SEG1PH
FLTEN5
FLTEN4
0000
PRSEG
FLTEN3
0000
0000
BRP
SEG2PHTS
0000
FLTEN2
FLTEN1
0000
FLTEN0
FFFF
F7MSK
F6MSK
F5MSK
F4MSK
F3MSK
F2MSK
F1MSK
F0MSK
0000
C1FMSKSEL2 041A
F15MSK
F14MSK
F13MSK
F12MSK
F11MSK
F10MSK
F9MSK
F8MSK
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-19:
File Name
Addr
ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 FOR PIC24HJXXXGP506/510/610 DEVICES ONLY
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
0400041E
Bit 9
Bit 8
Bit 7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RXFUL5
RXFUL4
RXFUL3
RXFUL2
RXFUL1
Bit 6
See definition when WIN = x
DS70175H-page 41
C1RXFUL1
0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9
RXFUL0
0000
C1RXFUL2
0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16
0000
C1RXOVF1
0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9
RXOVF0
0000
C1RXOVF2
042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16
0000
C1TR01CO
N
0430
TXEN1
TX
ABT1
TX
LARB1
TX
ERR1
TX
REQ1
RTREN1
TX1PRI
TXEN0
TX
ABAT0
TX
LARB0
TX
ERR0
TX
REQ0
RTREN0
TX0PRI
0000
C1TR23CO
N
0432
TXEN3
TX
ABT3
TX
LARB3
TX
ERR3
TX
REQ3
RTREN3
TX3PRI
TXEN2
TX
ABAT2
TX
LARB2
TX
ERR2
TX
REQ2
RTREN2
TX2PRI
0000
C1TR45CO
N
0434
TXEN5
TX
ABT5
TX
LARB5
TX
ERR5
TX
REQ5
RTREN5
TX5PRI
TXEN4
TX
ABAT4
TX
LARB4
TX
ERR4
TX
REQ4
RTREN4
TX4PRI
0000
C1TR67CO
N
0436
TXEN7
TX
ABT7
TX
LARB7
TX
ERR7
TX
REQ7
RTREN7
TX7PRI
TXEN6
TX
ABAT6
TX
LARB6
TX
ERR6
TX
REQ6
RTREN6
TX6PRI
xxxx
C1RXD
0440
Recieved Data Word
xxxx
C1TXD
0442
Transmit Data Word
xxxx
Legend:
RXFUL8
RXOVF8
RXFUL7
RXOVF7
RXFUL6
RXOVF6
RXOVF5
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
RXOVF4
RXOVF3
RXOVF2
RXOVF1
PIC24HJXXXGPX06/X08/X10
C1FMSKSEL1 0418
File Name
ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 FOR PIC24HJXXXGP506/510/610 DEVICES ONLY
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
0400041E
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
See definition when WIN = x
© 2009 Microchip Technology Inc.
C1BUFPNT1
0420
F3BP
F2BP
F1BP
F0BP
0000
C1BUFPNT2
0422
F7BP
F6BP
F5BP
F4BP
0000
C1BUFPNT3
0424
F11BP
F10BP
F9BP
F8BP
0000
C1BUFPNT4
0426
F15BP
F14BP
F13BP
F12BP
0000
C1RXM0SID
0430
SID
—
EID
xxxx
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
—
EID
C1RXM0EID
0432
EID
C1RXM1SID
0434
SID
C1RXM1EID
0436
EID
C1RXM2SID
0438
SID
C1RXM2EID
043A
EID
C1RXF0SID
0440
SID
C1RXF0EID
0442
EID
C1RXF1SID
0444
SID
C1RXF1EID
0446
EID
C1RXF2SID
0448
SID
C1RXF2EID
044A
EID
C1RXF3SID
044C
SID
C1RXF3EID
044E
EID
C1RXF4SID
0450
SID
C1RXF4EID
0452
EID
C1RXF5SID
0454
SID
C1RXF5EID
0456
EID
C1RXF6SID
0458
SID
C1RXF6EID
045A
EID
C1RXF7SID
045C
SID
C1RXF7EID
045E
EID
C1RXF8SID
0460
SID
C1RXF8EID
0462
EID
C1RXF9SID
0464
SID
C1RXF9EID
0466
EID
C1RXF10SID
0468
SID
C1RXF10EID
046A
EID
C1RXF11SID
046C
SID
Legend:
SID
—
SID
—
MIDE
EID
MIDE
xxxx
EID
SID
—
MIDE
xxxx
EID
SID
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
—
EXIDE
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
xxxx
xxxx
PIC24HJXXXGPX06/X08/X10
DS70175H-page 42
TABLE 4-20:
© 2009 Microchip Technology Inc.
TABLE 4-20:
File Name
ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 FOR PIC24HJXXXGP506/510/610 DEVICES ONLY (CONTINUED)
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
C1RXF11EID
046E
EID
C1RXF12SID
0470
SID
C1RXF12EID
0472
EID
C1RXF13SID
0474
SID
C1RXF13EID
0476
EID
C1RXF14SID
0478
SID
C1RXF14EID
047A
EID
C1RXF15SID
047C
SID
C1RXF15EID
047E
EID
Legend:
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EID
SID
—
SID
—
EXIDE
xxxx
—
EID
—
EID
—
EID
—
EID
EID
EXIDE
—
EXIDE
—
EXIDE
EID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
All
Resets
xxxx
xxxx
xxxx
xxxx
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
PIC24HJXXXGPX06/X08/X10
DS70175H-page 43
File Name
ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0 OR 1 FOR PIC24HJ256GP610 DEVICES ONLY
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
C2CTRL1
0500
—
—
CSIDL
ABAT
—
C2CTRL2
0502
—
—
—
—
—
C2VEC
0504
—
—
—
C2FCTRL
0506
C2FIFO
0508
—
—
C2INTF
050A
—
—
TXBO
TXBP
RXBP
TXWAR
C2INTE
050C
—
—
—
—
—
—
C2EC
050E
C2CFG1
0510
Bit 8
Bit 7
—
—
REQOP
—
—
—
—
Bit 5
OPMODE
FILHIT
DMABS
Bit 6
—
—
—
—
CANCAP
—
—
—
RXWAR EWARN
—
—
Bit 2
Bit 1
Bit 0
All
Resets
—
—
WIN
0480
DNCNT
—
FBP
—
Bit 3
—
0000
ICODE
—
—
—
—
—
0000
FSA
0000
FNRB
0000
IVRIF
WAKIF
ERRIF
—
FIFOIF
RBOVIF
RBIF
TBIF
0000
IVRIE
WAKIE
ERRIE
—
FIFOIE
RBOVIE
RBIE
TBIE
0000
TERRCNT
—
Bit 4
RERRCNT
—
—
—
—
SJW
0000
BRP
0000
C2CFG2
0512
—
WAKFIL
—
—
—
SEG2PH
SEG2PHTS
C2FEN1
0514
FLTEN15
FLTEN14
FLTEN13
FLTEN12
FLTEN11
FLTEN10 FLTEN9 FLTEN8
FLTEN7
C2FMSKSEL1
0518
F7MSK
F6MSK
F5MSK
F4MSK
F3MSK
F2MSK
F1MSK
F0MSK
0000
C2FMSKSEL2
051A
F15MSK
F14MSK
F13MSK
F12MSK
F11MSK
F10MSK
F9MSK
F8MSK
0000
Legend:
SEG1PH
PRSEG
FLTEN2 FLTEN1
0000
FLTEN0
FFFF
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-22:
File Name
SAM
FLTEN6 FLTEN5 FLTEN4 FLTEN3
Addr
ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0 FOR PIC24HJ256GP610 DEVICES ONLY
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
0500051E
Bit 9
Bit 8
Bit 7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RXFUL5
RXFUL4
RXFUL3
RXFUL2
RXFUL1
Bit 6
See definition when WIN = x
C2RXFUL1
0520 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10
RXFUL0
0000
C2RXFUL2
0522 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16
RXFUL9
RXFUL8
RXFUL7
RXFUL6
0000
C2RXOVF1
0528 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF09 RXOVF08 RXOVF7
0000
C2RXOVF2
052A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0
0000
© 2009 Microchip Technology Inc.
C2TR01CON 0530
TXEN1
TX
ABAT1
TX
LARB1
TX
ERR1
TX
REQ1
RTREN1
TX1PRI
TXEN0
TX
ABAT0
TX
LARB0
TX
ERR0
TX
REQ0
RTREN0
TX0PRI
0000
C2TR23CON 0532
TXEN3
TX
ABAT3
TX
LARB3
TX
ERR3
TX
REQ3
RTREN3
TX3PRI
TXEN2
TX
ABAT2
TX
LARB2
TX
ERR2
TX
REQ2
RTREN2
TX2PRI
0000
C2TR45CON 0534
TXEN5
TX
ABAT5
TX
LARB5
TX
ERR5
TX
REQ5
RTREN5
TX5PRI
TXEN4
TX
ABAT4
TX
LARB4
TX
ERR4
TX
REQ4
RTREN4
TX4PRI
0000
C2TR67CON 0536
TXEN7
TX
ABAT7
TX
LARB7
TX
ERR7
TX
REQ7
RTREN7
TX7PRI
TXEN6
TX
ABAT6
TX
LARB6
TX
ERR6
TX
REQ6
RTREN6
TX6PRI
xxxx
C2RXD
0540
Recieved Data Word
xxxx
C2TXD
0542
Transmit Data Word
xxxx
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
PIC24HJXXXGPX06/X08/X10
DS70175H-page 44
TABLE 4-21:
© 2009 Microchip Technology Inc.
TABLE 4-23:
File Name
ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR PIC24HJ256GP610 DEVICES ONLY
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
0500051E
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
See definition when WIN = x
C2BUFPNT1
0520
F3BP
F2BP
F1BP
F0BP
0000
C2BUFPNT2
0522
F7BP
F6BP
F5BP
F4BP
0000
C2BUFPNT3
0524
F12BP
F10BP
F9BP
F8BP
0000
C2BUFPNT4
0526
F15BP
F14BP
F13BP
F12BP
0000
C2RXM0SID
0530
SID
—
EID
xxxx
C2RXM0EID
0532
EID
C2RXM1SID
0534
SID
—
EID
xxxx
C2RXM1EID
0536
EID
C2RXM2SID
0538
SID
—
EID
xxxx
C2RXM2EID
053A
EID
C2RXF0SID
0540
SID
—
EID
xxxx
C2RXF0EID
0542
EID
0544
SID
0546
EID
C2RXF2SID
0548
SID
C2RXF2EID
054A
EID
C2RXF3SID
054C
SID
C2RXF3EID
054E
EID
C2RXF4SID
0550
SID
C2RXF4EID
0552
EID
C2RXF5SID
0554
SID
C2RXF5EID
0556
EID
C2RXF6SID
0558
SID
C2RXF6EID
055A
EID
C2RXF7SID
055C
SID
C2RXF7EID
055E
EID
C2RXF8SID
0560
SID
C2RXF8EID
0562
EID
C2RXF9SID
0564
SID
C2RXF9EID
0566
EID
C2RXF10SID
0568
SID
C2RXF10EID
056A
EID
C2RXF11SID
056C
SID
Legend:
—
SID
—
SID
—
SID
—
MIDE
EID
MIDE
xxxx
EID
MIDE
xxxx
EID
EXIDE
xxxx
EID
SID
—
EXIDE
xxxx
—
EID
xxxx
—
EID
xxxx
—
EID
xxxx
—
EID
xxxx
—
EID
xxxx
—
EID
xxxx
—
EID
xxxx
—
EID
xxxx
—
EID
xxxx
—
EID
xxxx
—
EID
xxxx
EID
SID
—
SID
—
SID
—
SID
—
SID
—
SID
—
SID
—
SID
—
SID
—
SID
—
EXIDE
xxxx
EID
EXIDE
xxxx
EID
EXIDE
xxxx
EID
EXIDE
xxxx
EID
EXIDE
xxxx
EID
EXIDE
xxxx
EID
EXIDE
xxxx
EID
EXIDE
xxxx
EID
EXIDE
xxxx
EID
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
EXIDE
xxxx
PIC24HJXXXGPX06/X08/X10
DS70175H-page 45
C2RXF1SID
C2RXF1EID
SID
ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR PIC24HJ256GP610 DEVICES ONLY (CONTINUED)
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
C2RXF11EID
056E
EID
C2RXF12SID
0570
SID
C2RXF12EID
0572
EID
C2RXF13SID
0574
SID
C2RXF13EID
0576
EID
C2RXF14SID
0578
SID
C2RXF14EID
057A
EID
C2RXF15SID
057C
SID
057E
EID
C2RXF15EID
Legend:
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EID
SID
—
SID
—
SID
—
SID
—
EXIDE
xxxx
—
EID
xxxx
—
EID
xxxx
—
EID
xxxx
—
EID
xxxx
EID
EXIDE
xxxx
EID
EXIDE
xxxx
EID
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
EXIDE
EID
All
Resets
xxxx
xxxx
PIC24HJXXXGPX06/X08/X10
DS70175H-page 46
TABLE 4-23:
© 2009 Microchip Technology Inc.
© 2009 Microchip Technology Inc.
TABLE 4-24:
File Name
PORTA REGISTER MAP(1)
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISA9
—
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
F6FF
RA9
—
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx
LATA10
LATA9
—
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
xxxx
—
—
—
—
—
ODCA5
ODCA4
ODCA3
ODCA2
ODCA1
ODCA0
0000
Addr
Bit 15
Bit 14
Bit 13
Bit 12
TRISA
02C0
TRISA15
TRISA14
TRISA13
PORTA
02C2
RA15
RA14
RA13
LATA
02C4
LATA15
LATA14
ODCA
06C0
ODCA15
ODCA14
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
TABLE 4-25:
Bit 11
Bit 10
Bit 9
TRISA12
—
TRISA10
RA12
—
RA10
LATA13
LATA12
—
—
—
—
PORTB REGISTER MAP(1)
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISB
02C6
TRISB15
TRISB14
TRISB13
TRISB12
TRISB11
TRISB10
TRISB9
TRISB8
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
FFFF
PORTB
02C8
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx
LATB
02CA
LATB15
LATB14
LATB13
LATB12
LATB11
LATB10
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
TABLE 4-26:
PORTC REGISTER MAP(1)
Bit 14
Bit 13
Bit 12
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
—
—
—
—
TRISC4
TRISC3
TRISC2
TRISC1
—
F01E
—
—
—
—
—
—
—
RC4
RC3
RC2
RC1
—
xxxx
—
—
—
—
—
—
—
LATC4
LATC3
LATC2
LATC1
—
xxxx
Addr
TRISC
02CC
PORTC
02CE
RC15
RC14
RC13
RC12
LATC
02D0
LATC15
LATC14
LATC13
LATC12
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
TABLE 4-27:
Bit 15
Bit 11
File Name
TRISC15 TRISC14 TRISC13 TRISC12
PORTD REGISTER MAP(1)
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISD
02D2
TRISD15
TRISD14
TRISD13
TRISD12
TRISD11
TRISD10
TRISD9
TRISD8
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
FFFF
PORTD
02D4
RD15
RD14
RD13
RD12
RD11
RD10
RD9
RD8
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx
LATD
02D6
LATD15
LATD14
LATD13
LATD12
LATD11
LATD10
LATD9
LATD8
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx
ODCD
06D2
ODCD15
ODCD14
ODCD13
ODCD12
ODCD11
ODCD10
ODCD9
ODCD8
ODCD7
ODCD6
ODCD5
ODCD4
ODCD3
ODCD2
ODCD1
ODCD0
0000
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
File Name
DS70175H-page 47
PIC24HJXXXGPX06/X08/X10
File Name
PORTE REGISTER MAP(1)
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISE
02D8
—
—
—
—
—
—
—
—
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
00FF
PORTE
02DA
—
—
—
—
—
—
—
—
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
xxxx
LATE
02DC
—
—
—
—
—
—
—
—
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
xxxx
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
File Name
TABLE 4-29:
PORTF REGISTER MAP(1)
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
TRISF
02DE
—
—
TRISF13
TRISF12
—
—
—
TRISF8
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0
31FF
PORTF
02E0
—
—
RF13
RF12
—
—
—
RF8
RF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
xxxx
LATF
02E2
—
—
LATF13
LATF12
—
—
—
LATF8
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
xxxx
ODCF(2)
06DE
—
—
ODCF13
ODCF12
—
—
—
ODCF8
ODCF7
ODCF6
ODCF5
ODCF4
ODCF3
ODCF2
ODCF1
ODCF0
0000
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
TABLE 4-30:
PORTG REGISTER MAP(1)
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISG
02E4
TRISG15
TRISG14
TRISG13
TRISG12
—
—
TRISG9
TRISG8
TRISG7
TRISG6
—
—
TRISG3
TRISG2
TRISG1
TRISG0
F3CF
PORTG
02E6
RG15
RG14
RG13
RG12
—
—
RG9
RG8
RG7
RG6
—
—
RG3
RG2
RG1
RG0
xxxx
LATG
02E8
LATG15
LATG14
LATG13
LATG12
—
—
LATG9
LATG8
LATG7
LATG6
—
—
LATG3
LATG2
LATG1
LATG0
xxxx
ODCG(2)
06E4
ODCG15
ODCG14
ODCG13
ODCG12
—
—
ODCG9
ODCG8
ODCG7
ODCG6
—
—
ODCG3
ODCG2
ODCG1
ODCG0
0000
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
PIC24HJXXXGPX06/X08/X10
DS70175H-page 48
TABLE 4-28:
© 2009 Microchip Technology Inc.
© 2009 Microchip Technology Inc.
TABLE 4-31:
File Name
SYSTEM CONTROL REGISTER MAP
Addr
Bit 15
Bit 14
RCON
0740
TRAPR
IOPUWR
OSCCON
0742
—
CLKDIV
0744
ROI
PLLFBD
0746
—
—
—
—
—
—
—
OSCTUN
0748
—
—
—
—
—
—
—
Legend:
Note 1:
2:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
TABLE 4-32:
Bit 13
Bit 12
—
—
COSC
Bit 11
Bit 10
—
—
—
DOZE
Bit 9
Bit 8
—
VREGS
NOSC
DOZEN
FRCDIV
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
EXTR
SWR
SWDTEN
WDTO
SLEEP
IDLE
BOR
POR
xxxx(1)
CLKLOCK
—
LOCK
—
CF
—
LPOSCEN
OSWEN
0300(2)
PLLPOST
—
PLLPRE
—
—
3040
0030
—
TUN
0000
NVM REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
NVMCON
0760
WR
WREN
WRERR
—
—
—
—
—
—
ERASE
—
—
0766
—
—
—
—
—
—
—
—
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000(1)
NVMOP
NVMKEY
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-33:
File Name
Addr
PMD REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PMD1
0770
T5MD
T4MD
T3MD
T2MD
T1MD
—
—
—
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
C2MD
C1MD
AD1MD
0000
PMD2
0772
IC8MD
IC7MD
IC6MD
IC5MD
IC4MD
IC3MD
IC2MD
IC1MD
OC8MD
OC7MD
OC6MD
OC5MD
OC4MD
OC3MD
OC2MD
OC1MD
0000
PMD3
0774
T9MD
T8MD
T7MD
T6MD
—
—
—
—
—
—
—
—
—
—
I2C2MD
AD2MD
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
DS70175H-page 49
PIC24HJXXXGPX06/X08/X10
Addr
Legend:
Note 1:
Bit 0
PLLDIV
File Name
NVMKEY
Bit 1
All
Resets
Bit 7
PIC24HJXXXGPX06/X08/X10
4.2.6
4.2.7
SOFTWARE STACK
In addition to its use as a working register, the W15
register in the PIC24HJXXXGPX06/X08/X10 devices is
also used as a software Stack Pointer. The Stack
Pointer always points to the first available free word
and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack
pushes, as shown in Figure 4-5. For a PC push during
any CALL instruction, the MSB of the PC is zeroextended before the push, ensuring that the MSB is
always clear.
Note:
A PC push during exception processing
concatenates the SRL register to the MSB
of the PC prior to the push.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM is forced to ‘0’
because all stack operations must be word-aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error
trap will not occur. The stack error trap will occur on a
subsequent push operation. Thus, for example, if it is
desirable to cause a stack error trap when the stack
grows beyond address 0x2000 in RAM, initialize the
SPLIM with the value 0x1FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-5:
Stack Grows Towards
Higher Address
0x0000
15
CALL STACK FRAME
0
PC
000000000 PC
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
DS70175H-page 50
DATA RAM PROTECTION FEATURE
The PIC24H product family supports Data RAM protection features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessible only from the Boot Segment Flash code, when enabled. SSRAM (Secure
RAM segment for RAM) is accessible only from the
Secure Segment Flash code, when enabled. See
Table 4-1 for an overview of the BSRAM and SSRAM
SFRs.
4.3
Instruction Addressing Modes
The addressing modes in Table 4-34 form the basis of
the addressing modes optimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
4.3.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (Near Data Space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
4.3.2
MCU INSTRUCTIONS
The 3-operand MCU instructions are of the form:
Operand 3 = Operand 1 Operand 2
where Operand 1 is always a working register (i.e., the
addressing mode can only be Register Direct) which is
referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or a data memory
location. The following addressing modes are
supported by MCU instructions:
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
5-bit or 10-bit Literal
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
TABLE 4-34:
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
File Register Direct
Description
The address of the file register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the EA.
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
4.3.3
The sum of Wn and a literal forms the EA.
MOVE INSTRUCTIONS
Move instructions provide a greater degree of addressing flexibility than other instructions. In addition to the
Addressing modes supported by most MCU instructions, move instructions also support Register Indirect
with Register Offset Addressing mode, also referred to
as Register Indexed mode.
Note:
For the MOV instructions, the Addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (Register Offset)
field is shared between both source and
destination (but typically only used by
one).
In summary, the following Addressing modes are
supported by move instructions:
•
•
•
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
Note:
4.3.4
Not all instructions support all the
Addressing modes given above. Individual
instructions may support different subsets
of these Addressing modes.
OTHER INSTRUCTIONS
Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, the source of an operand or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
© 2009 Microchip Technology Inc.
4.4
Interfacing Program and Data
Memory Spaces
The PIC24HJXXXGPX06/X08/X10 architecture uses a
24-bit wide program space and a 16-bit wide data
space. The architecture is also a modified Harvard
scheme, meaning that data can also be present in the
program space. To use this data successfully, it must
be accessed in a way that preserves the alignment of
information in both spaces.
Aside
from
normal
execution,
the
PIC24HJXXXGPX06/X08/X10 architecture provides
two methods by which program space can be accessed
during operation:
• Using table instructions to access individual bytes
or words anywhere in the program space
• Remapping a portion of the program space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated from time to time. It also allows
access to all bytes of the program word. The remapping method allows an application to access a large
block of data on a read-only basis, which is ideal for
look ups from a large table of static data. It can only
access the least significant word of the program word.
4.4.1
ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the Most Significant bit of TBLPAG is used
to determine if the operation occurs in the user memory
(TBLPAG = 0) or the configuration memory
(TBLPAG = 1).
DS70175H-page 51
PIC24HJXXXGPX06/X08/X10
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the Most
Significant bit of the EA is ‘1’, PSVPAG is concatenated
with the lower 15 bits of the EA to form a 23-bit program
space address. Unlike table operations, this limits
remapping operations strictly to the user memory area.
TABLE 4-35:
Table 4-35 and Figure 4-6 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P refers to a program
space word, whereas D refers to a data space
word.
PROGRAM SPACE ADDRESS CONSTRUCTION
Access
Space
Access Type
Program Space Address
Instruction Access
(Code Execution)
User
TBLRD/TBLWT
(Byte/Word Read/Write)
User
TBLPAG
Configuration
TBLPAG
Data EA
1xxx xxxx
xxxx xxxx xxxx xxxx
Program Space Visibility
(Block Remap/Read)
Note 1:
PC
0
0xxx
xxxx
0xxx xxxx
User
xxxx
0
xxxx
xxxx xxx0
Data EA
xxxx xxxx xxxx xxxx
0
PSVPAG
0
xxxx xxxx
Data EA(1)
xxx xxxx xxxx xxxx
Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG.
DS70175H-page 52
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
FIGURE 4-6:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
0
0
23 bits
EA
Table Operations(2)
1/0
1/0
TBLPAG
8 bits
16 bits
24 bits
Select
Program Space Visibility(1)
(Remapping)
0
EA
1
0
PSVPAG
8 bits
15 bits
23 bits
User/Configuration
Space Select
Byte Select
Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word
alignment of data in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted
in the configuration memory space.
© 2009 Microchip Technology Inc.
DS70175H-page 53
PIC24HJXXXGPX06/X08/X10
4.4.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
2.
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going
through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper
8 bits of a program space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit,
word wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word and TBLRDH and TBLWTH access the space
which contains the upper data byte.
Two table instructions are provided to move byte or
word sized (16-bit) data to and from program space.
Both function as either byte or word operations.
1.
TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space
location (P) to a data address (D).
TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
(P) to a data address. Note that
D, the ‘phantom byte’, will always be ‘0’.
In Byte mode, it maps the upper or lower byte of
the program word to D of the data
address, as above. Note that the data will
always be ‘0’ when the upper ‘phantom’ byte is
selected (Byte Select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user and configuration spaces. When TBLPAG = 0, the table page
is located in the user memory space. When
TBLPAG = 1, the page is located in configuration
space.
In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when Byte Select is ‘1’; the lower byte
is selected when it is ‘0’.
FIGURE 4-7:
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
23
15
0
0x000000
23
16
8
0
00000000
0x020000
0x030000
00000000
00000000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn = 0)
TBLRDL.B (Wn = 1)
TBLRDL.B (Wn = 0)
TBLRDL.W
0x800000
DS70175H-page 54
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
4.4.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This option provides transparent access of stored constant data from the data space without the need to use
special instructions (i.e., TBLRDL/H).
Program space access through the data space occurs
if the Most Significant bit of the data space EA is ‘1’ and
program space visibility is enabled by setting the PSV
bit in the Core Control register (CORCON). The
location of the program memory space to be mapped
into the data space is determined by the Program
Space Visibility Page register (PSVPAG). This 8-bit
register defines any one of 256 possible pages of
16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory
address, with the 15 bits of the EA functioning as the
lower bits. Note that by incrementing the PC by 2 for
each program memory word, the lower 15 bits of data
space addresses directly map to the lower 15 bits in the
corresponding program space addresses.
Data reads to this area add an additional cycle to the
instruction being executed, since two program memory
fetches are required.
Although each data space address, 8000h and higher,
maps directly into a corresponding program memory
address (see Figure 4-8), only the lower 16 bits of the
FIGURE 4-8:
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
Note:
PSV access is temporarily disabled during
table reads/writes.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions
require one instruction cycle in addition to the specified
execution time. All other instructions require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV, which are executed inside
a REPEAT loop, there will be some instances that
require two instruction cycles in addition to the
specified execution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction accessing data, using PSV, to execute in a
single cycle.
PROGRAM SPACE VISIBILITY OPERATION
When CORCON = 1 and EA = 1:
Program Space
PSVPAG
02
23
15
Data Space
0
0x000000
0x0000
Data EA
0x010000
0x018000
The data in the page
designated by PSVPAG is mapped into
the upper half of the
data memory
space...
0x8000
PSV Area
0x800000
© 2009 Microchip Technology Inc.
...while the lower 15 bits
of the EA specify an
exact address within
0xFFFF the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
DS70175H-page 55
PIC24HJXXXGPX06/X08/X10
NOTES:
DS70175H-page 56
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
5.0
FLASH PROGRAM MEMORY
Note:
signal controller just before shipping the product. This
also allows the most recent firmware or a custom firmware to be programmed.
This data sheet summarizes the features
of the PIC24HJXXXGPX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”, Section 5.
“Flash Programming” (DS70228), which
is available from the Microchip website
(www.microchip.com).
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
can write program memory data either in blocks or
‘rows’ of 64 instructions (192 bytes) at a time, or single
instructions and erase program memory in blocks or
‘pages’ of 512 instructions (1536 bytes) at a time.
5.1
The PIC24HJXXXGPX06/X08/X10 devices contain
internal Flash program memory for storing and executing application code. The memory is readable, writable
and erasable during normal operation over the entire
VDD range.
Flash memory can be programmed in two ways:
1.
2.
In-Circuit Serial Programming™ (ICSP™)
programming capability
Run-Time Self-Programming (RTSP)
ICSP
programming
capability
allows
a
PIC24HJXXXGPX06/X08/X10 device to be serially
programmed while in the end application circuit. This is
simply done with two lines for programming clock and
programming data (one of the alternate programming
pin pairs: PGECx/PGEDx, and three other lines for
power (VDD), ground (VSS) and Master Clear (MCLR).
This allows customers to manufacture boards with
unprogrammed devices and then program the digital
FIGURE 5-1:
Table Instructions and Flash
Programming
Regardless of the method used, all programming of
Flash memory is done with the table read and table
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 5-1.
The TBLRDL and the TBLWTL instructions are used to
read or write to bits of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to read
or write to bits of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
ADDRESSING FOR TABLE REGISTERS
24 bits
Using
Program Counter
Program Counter
0
0
Working Reg EA
Using
Table Instruction
1/0
TBLPAG Reg
8 bits
User/Configuration
Space Select
© 2009 Microchip Technology Inc.
16 bits
24-bit EA
Byte
Select
DS70175H-page 57
PIC24HJXXXGPX06/X08/X10
5.2
RTSP Operation
The PIC24HJXXXGPX06/X08/X10 Flash program
memory array is organized into rows of 64 instructions
or 192 bytes. RTSP allows the user to erase a page of
memory, which consists of eight rows (512 instructions)
at a time, and to program one row or one word at a
time. Table 24-12 displays typical erase and programming times. The 8-row erase pages and single row
write rows are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192
bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers in sequential order. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of
64 TBLWTL and TBLWTH instructions are required to
load the instructions.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
written. A programming cycle is required for
programming each row.
5.3
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
programming operation is finished.
The programming time depends on the FRC accuracy
(see Table 24-19) and the value of the FRC Oscillator
Tuning register (see Register 9-4). Use the following
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time and Word
Write Cycle Time parameters (see Table 24-12).
EQUATION 5-1:
PROGRAMMING TIME
T
------------------------------------------------------------------------------------------------------------------------7.37 MHz × ( FRC Accuracy )% × ( FRC Tuning )%
For example, if the device is operating at +85°C, the
FRC accuracy will be ±2%. If the TUN bits (see
Register 9-4) are set to ‘b111111, the Minimum
Row Write Time is:
11064 Cycles
T RW = ---------------------------------------------------------------------------------------------- = 1.48ms
7.37 MHz × ( 1 + 0.02 ) × ( 1 – 0.00375 )
and, the Maximum Row Write Time is:
11064 Cycles
T RW = ---------------------------------------------------------------------------------------------- = 1.54ms
7.37 MHz × ( 1 – 0.02 ) × ( 1 – 0.00375 )
Setting the WR bit (NVMCON) starts the operation, and the WR bit is automatically cleared when the
operation is finished.
5.4
Control Registers
There are two SFRs used to read and write the
program Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 0x55 and 0xAA to the
NVMKEY register. Refer to Section 5.3 “Programming
Operations” for further details.
DS70175H-page 58
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
REGISTER 5-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0(1)
R/W-0(1)
R/W-0(1)
U-0
U-0
U-0
U-0
U-0
WR
WREN
WRERR
—
—
—
—
—
bit 15
bit 8
R/W-0(1)
U-0
—
ERASE
U-0
—
R/W-0(1)
U-0
R/W-0(1)
R/W-0(1)
R/W-0(1)
(2)
—
NVMOP
bit 7
bit 0
Legend:
SO = Settable only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete.
0 = Program or erase operation is complete and inactive
bit 14
WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
bit 13
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12-7
Unimplemented: Read as ‘0’
bit 6
ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP on the next WR command
0 = Perform the program operation specified by NVMOP on the next WR command
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
NVMOP: NVM Operation Select bits(2)
1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)
1110 = Reserved
1101 = Erase General Segment and FGS Configuration Register
(ERASE = 1) or no operation (ERASE = 0)
1100 = Erase Secure Segment and FSS Configuration Register
(ERASE = 1) or no operation (ERASE = 0)
1011-0100 = Reserved
0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1)
0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)
0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)
0000 = Program or erase a single Configuration register byte
Note 1: These bits can only be reset on POR.
2: All other combinations of NVMOP are unimplemented.
© 2009 Microchip Technology Inc.
DS70175H-page 59
PIC24HJXXXGPX06/X08/X10
5.4.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
4.
5.
The user can program one row of program Flash
memory at a time. To do this, it is necessary to erase
the 8-row erase page that contains the desired row.
The general process is:
1.
2.
3.
Read eight rows of program memory
(512 instructions) and store in data RAM.
Update the program data in RAM with the
desired new data.
Erase the page (see Example 5-1):
a) Set the NVMOP bits (NVMCON) to
‘0010’ to configure for block erase. Set the
ERASE (NVMCON) and WREN
(NVMCON) bits.
b) Write the starting address of the page to be
erased into the TBLPAG and W registers.
c) Perform a dummy table write operation
(TBLWTL) to any address within the page
that needs to be erased.
d) Write 0x55 to NVMKEY.
e) Write 0xAA to NVMKEY.
f) Set the WR bit (NVMCON). The erase
cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
EXAMPLE 5-1:
Note:
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 5-3.
ERASING A PROGRAM MEMORY PAGE
; Set up NVMCON for block erase operation
MOV
#0x4042, W0
MOV
W0, NVMCON
; Init pointer to row to be ERASED
MOV
#tblpage(PROG_ADDR), W0
MOV
W0, TBLPAG
MOV
#tbloffset(PROG_ADDR), W0
TBLWTL W0, [W0]
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
6.
Write the first 64 instructions from data RAM into
the program memory buffers (see Example 5-2).
Write the program block to Flash memory:
a) Set the NVMOP bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
b) Write 0x55 to NVMKEY.
c) Write 0xAA to NVMKEY.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash memory is done, the WR bit is cleared
automatically.
Repeat steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash memory.
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
;
; Initialize NVMCON
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PM Page Boundary SFR
Initialize in-page EA pointer
Set base address of erase block
Block all interrupts with priority -1
—
-1
—
-1
—
-1
—
工商网监
湘ICP备2023018690号
