PIC32CM MC00 Family
5-Volt Motor Control MCU
5-Volt, 128-KB Flash, 16-KB SRAM with Advanced Analog
Operating Conditions
•
2.7V – 5.5V, -40°C to +85°C, DC to 48 MHz
•
2.7V – 5.5V, -40°C to +125°C, DC to 48 MHz
Motor Control
•
Qualification
•
AEC-Q100 Grade 1 (-40°C to 125°C)
Core: Arm® Cortex®-M0+ CPU running at up to 48 MHz
•
Single-cycle hardware multiplier
•
Memory Protection Unit (MPU)
Memories
•
Up to 128 KB in-system self-programmable Flash
•
Up to 4 KB independent self-programmable Flash for Data Flash
•
Up to 16 KB SRAM main memory
•
•
Power-on Reset (POR) and Brown-out Detection (BOD)
•
Internal and external clock options with 48 MHz to 96 MHz Fractional
Digital Phase Locked Loop (FDPLL96M)
External Interrupt Controller (EIC)
•
One non-maskable interrupt
Idle and Standby sleep modes
•
SleepWalking peripherals
Input/Output (I/O)
•
Up to 38 programmable I/O pins
•
Up to 16 external interrupts
•
Up to two parallel Input/Output Controllers (PIO)
Debugger Development Support
Up to four compare channels with optional
complementary output
–
Generation of synchronized pulse width modulation
(PWM) pattern across port pins
–
Deterministic fault protection, fast decay and
configurable dead-time between complementary
output
–
Dithering that increase resolution with up to 5 bit
and reduce quantization error
–
Up to 8 waveform output channels
Two 12-bit, 1 Msps Analog-to-Digital Converter (ADC)
–
Differential and single-ended input
–
Automatic offset and gain error compensation
–
Oversampling and decimation in hardware to
support 13-bit, 14-bit, 15-bit or 16-bit resolution
•
One 16-bit Sigma-Delta Analog-to-Digital Converter
(SDADC)
•
One 10-bit, 350 ksps Digital-to-Analog Converter (DAC)
•
Two Analog Comparators (AC) with Window Compare
function
Low Power
•
–
Advanced Analog
System
•
Two 24-bit Timer/Counters and one 16-bit Timer/Counter
for Control (TCC) with extended functions:
–
2 differential channels
Peripherals
•
Hardware Divide and Square Root Accelerator (DIVAS)
•
12-channel Direct Memory Access Controller (DMAC)
•
In-circuit and in-application programming
•
12-channel Event System
•
2-wire Serial Wire Debug Port Interface
•
Up to five 16-bit Timer/Counters (TC)
•
Four hardware breakpoints, two data watchpoints
–
One 16-bit TC with compare/capture channels
•
Micro Trace Buffer (MTB) for instruction trace in SRAM
–
One 8-bit TC with compare/capture channels
–
One 32-bit TC with compare/capture channels using
two TCs
© 2021 Microchip Technology Inc.
and its subsidiaries
•
Frequency Meter
•
32-bit Real Time Counter (RTC) with clock/calendar
function
•
Watchdog Timer (WDT)
Datasheet
DS60001638D-page 1
PIC32CM MC00 Family
Peripherals (Continued)
•
CRC-32 generator
•
Up to four Serial Communication Interfaces (SERCOM), each configurable
to operate as:
–
–
USART with full-duplex and single-wire half-duplex configuration
I2C up to 3.4 MHz
–
SPI
–
LIN host/client
–
RS-485
•
Configurable Custom Logic (CCL)
•
Integrated Temperature Sensor
Table 1. Packages
Type
TQFP
VQFN
Pin Count
32
48
32
48
I/O Pins (max)
26
38
26
38
Lead Pitch (mm)
0.8
0.5
0.5
0.5
Dimensions (mm)
7.0x7.0x1.0
7.0x7.0x1.0
5.0x5.0x0.9
7.0x7.0x0.9
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 2
PIC32CM MC00 Family
Table of Contents
5-Volt, 128-KB Flash, 16-KB SRAM with Advanced Analog.......................................................................... 1
1.
Configuration Summary.......................................................................................................................... 5
2.
Ordering Information............................................................................................................................... 7
3.
Block Diagram.........................................................................................................................................8
4.
Pinout and Packaging............................................................................................................................. 9
5.
Signal Description................................................................................................................................. 19
6.
Power Supply and Start-Up Considerations..........................................................................................21
7.
Product Mapping................................................................................................................................... 24
8.
Memories.............................................................................................................................................. 25
9.
Processor and Architecture...................................................................................................................28
10. Peripherals Configuration Summary..................................................................................................... 35
11. Clock System........................................................................................................................................ 38
12. Generic Clock Controller (GCLK)..........................................................................................................43
13. Main Clock (MCLK)............................................................................................................................... 58
14. Oscillators Controller (OSCCTRL)........................................................................................................ 74
15. 32.768 kHz Oscillators Controller (OSC32KCTRL).............................................................................108
16. Power Manager (PM).......................................................................................................................... 128
17. Supply Controller (SUPC)................................................................................................................... 135
18. Reset Controller (RSTC)..................................................................................................................... 149
19. Peripheral Access Controller (PAC).................................................................................................... 153
20. Device Service Unit (DSU)..................................................................................................................171
21. Divide and Square Root Accelerator (DIVAS)..................................................................................... 206
22. Watchdog Timer (WDT).......................................................................................................................217
23. Real-Time Counter (RTC)................................................................................................................... 231
24. Direct Memory Access Controller (DMAC)..........................................................................................282
25. External Interrupt Controller (EIC).......................................................................................................337
26. Nonvolatile Memory Controller (NVMCTRL)....................................................................................... 354
27. I/O Pin Controller (PORT)................................................................................................................... 377
28. Event System (EVSYS).......................................................................................................................404
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 3
PIC32CM MC00 Family
29. Serial Communication Interface (SERCOM).......................................................................................421
30. SERCOM Synchronous and Asynchronous Receiver and Transmitter (SERCOM USART).............. 428
31. SERCOM Serial Peripheral Interface (SERCOM SPI)........................................................................461
32. SERCOM Inter-Integrated Circuit (SERCOM I2C).............................................................................. 485
33. Timer Counter (TC)............................................................................................................................. 534
34. Timer/Counter for Control (TCC) Applications.................................................................................... 610
35. Configurable Custom Logic (CCL)...................................................................................................... 684
36. Analog-to-Digital Converter (ADC)......................................................................................................701
37. Sigma-Delta Analog-to-Digital Converter (SDADC)............................................................................ 741
38. Analog Comparators (AC)...................................................................................................................773
39. Digital-to-Analog Converter (DAC)......................................................................................................799
40. Temperature Sensor (TSENS)............................................................................................................ 816
41. Frequency Meter (FREQM).................................................................................................................837
42. Position Decoder (PDEC)................................................................................................................... 850
43. Electrical Characteristics 85℃............................................................................................................ 886
44. Electrical Characteristics 125°C..........................................................................................................936
45. Packaging Information........................................................................................................................ 950
46. Schematic Checklist............................................................................................................................967
47. Appendix............................................................................................................................................. 978
48. Revision History.................................................................................................................................. 980
The Microchip Website...............................................................................................................................987
Product Change Notification Service..........................................................................................................987
Customer Support...................................................................................................................................... 987
Microchip Devices Code Protection Feature.............................................................................................. 987
Legal Notice............................................................................................................................................... 988
Trademarks................................................................................................................................................ 988
Quality Management System..................................................................................................................... 989
Worldwide Sales and Service.....................................................................................................................990
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 4
PIC32CM MC00 Family
Configuration Summary
1.
Configuration Summary
Table 1-1. PIC32CM MC00 Common Features
PIC32CM MC00
Maximum CPU frequency
48 MHz
Memory Protection Unit
8 regions
Systick timer
1
Serial Wire Debug Interface
Yes
Oscillators
32.768 kHz crystal oscillator (XOSC32K)
0.4-32 MHz crystal oscillator (XOSC)
32.768 kHz internal oscillator (OSC32K)
32.768 kHz ultra low-power internal oscillator
(OSCULP32K)
48 MHz high-accuracy internal oscillator (OSC48M)
96 MHz Fractional Digital Phased Locked Loop
(FDPLL96M)
Generic Clock (GCLK)
9
DMA channels
12
Event System channels
12
External Interrupt lines
16 + 1 non-maskable
Divide and Square Root Accelerator (DIVAS)
Yes
Waveform outputs/Capture inputs channels per TC instance
TC Maximum and Minimum Capture
2
Yes
Timer Counter for Control (TCC) instances
3
Waveform output channels per TCC
8 for TCC0, 4 for TCC1, 2 for TCC2
Configurable Custom Logic (CCL) (number of LUTs)
4
Analog-to-Digital Converter (ADC) instances
2
Sigma-Delta Analog-to-Digital Converter (SDADC)
instances
1
Analog Comparators (AC)
1 AC made of 2 Comparators
Digital-to-Analog Converter (DAC) channels
1
Real-Time Counter (RTC)
Yes
RTC alarms
1
RTC compare values
One 32-bit value or two 16-bit values
Frequency Meter (FREQM) reference clock divider
Yes
Watchdog Timer (WDT)
Yes
Position Decoder (PDEC)
Yes
Memories CRC32 computation (DSU)
© 2021 Microchip Technology Inc.
and its subsidiaries
Yes (SRAM, Flash, Data Flash)
Datasheet
DS60001638D-page 5
PIC32CM MC00 Family
Configuration Summary
...........continued
PIC32CM MC00
Brown-out Detection (BOD)
© 2021 Microchip Technology Inc.
and its subsidiaries
VDD, VDDCORE
Datasheet
DS60001638D-page 6
PIC32CM MC00 Family
Ordering Information
2.
Ordering Information
Figure 2-1. PIC32CM MC Family Ordering Information
Microchip Brand
PIC32 CM XXXX MC00 XXX T - I / PT -XXX
Product Family
Pattern
CM - Cortex M0+
Three-digit QTP, SQTP code
or special requirement
(blank otherwise)
Memory Size
Package Type
1216 - 128-KB Flash and 16-KB RAM
6408 - 64-KB Flash and 8-KB RAM
PT - 32-pin TQFP
RTB - 32-pin VQFN(1)
Y8X - 48-pin TQFP
U5B - 48-pin VQFN(1)
Key Feature Set
MC00 = Motor Control
Temperature Range
I = -40°C to + 85°C (Industrial)
E = -40°C to + 125°C (Extended)(2)
Pin Count
032 = 32 pin
048 = 48 pin
Tape and Reel Flag
T = Tape and Reel
No Character = Tray/Tube (Default)
Notes:
1. VQFN packages have wettable flanks.
2. Extended Temp devices are AEC-Q100 Qualified.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 7
PIC32CM MC00 Family
Block Diagram
Block Diagram
SWCLK
CORTEX®-M0+
PROCESSOR
Fmax 48 MHz
SERIAL
WIRE
SWDIO
MICRO
TRACE BUFFER
IOBUS
DEVICE
SERVICE
UNIT
M
Divide Accellerator
S
AHB-APB
BRIDGE B
128-KB
RWW
NVM
16-KB
RAM
NVM
CONTROLLER
Cache
SRAM
CONTROLLER
M
M
S
S
S
M
HIGH-SPEED
BUS MATRIX
S
PERIPHERAL
ACCESS CONTROLLER
DMA
S
AHB-APB
BRIDGE A
AHB-APB
BRIDGE C
MAIN CLOCKS
CONTROLLER
PORT
OUT [3..0]
OSCILLATORS CONTROLLER
4x CCL
IN[11..0]
XIN
XOUT
DMA
XOSC
GCLK_IO[7..0]
FDPLL96M
GENERIC CLOCK
CONTROLLER
WATCHDOG
TIMER
EXTINT[15..0]
NMI
4x6SERCOM
x SERCOM
EXTERNAL INTERRUPT
CONTROLLER
DMA
5x TIMER/COUNTER
8 x Timer Counter
DMA
3x TIMER/COUNTER
FOR CONTROL
POWER
MANAGER
XIN32
XOUT32
OSC32K CONTROLLER
XOSC32K
PAD0
PAD1
PAD2
PAD3
WO0
PORT
OSC48M
EVENT SYSTEM
3.
WO1
WO0
WO1
WOn
AIN[11..0]
DMA
2x 12-CHANNEL
12-bit ADC 1MSPS
OSCULP32K
VREFA
OSC32K
2x ANALOG
COMPARATORS
SUPPLY CONTROLLER
BOD55
VREF
3.3V VREG
VREG
DMA
VOUT
10-bit DAC
RESETN
RESET
CONTROLLER
REAL TIME
COUNTER
FREQUENCY
METER
PDEC
DMA
2-CHANNEL
16-bit SDADC 3KSPS
TEMPERATURE
SENSOR
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
AIN[3..0]
CMP[1:0]
VREFA
QDI[2..0]
INN[1:0]
INP[1:0]
VREFB
DS60001638D-page 8
PIC32CM MC00 Family
Pinout and Packaging
4.
Pinout and Packaging
Each pin is controlled by the I/O Pin Controller (PORT) as a general purpose I/O and alternatively can be assigned to
one of the peripheral functions: A, B, C, D, E, F, G, H, I, or J.
The following tables describe the peripheral signals multiplexed to the PORT I/O pins for each package.
The column “Reset State” indicates the reset state of the line with mnemonics:
•
•
•
"I/O" or "Function" indicates whether the I/O pin resets in I/O mode or in peripheral function mode.
“I” / ”O” / "Hi-Z" indicates whether the I/O is configured as an input, output or is tri-stated.
“PU” / “PD” indicates whether pull up, pull down or nothing is enabled.
Note: The schematic checklist chapter provides the user with the requirements regarding the different pin
connections that must be considered before starting any new board design, and information on the minimum
hardware resources required to develop an application.
4.1
32-pin VQFN/32-pin TQFP
32-pin VQFN Top View
32-pin TQFP Top View
PIC32CM1216MC00032
PIC32CM6408MC00032
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 9
G
H
I
J
Datasheet
PDEC
AC/
GCLK
CCL
CCL/PDEC
SERCOM1/
PAD[1]
TCC2/
WO[1]
VDDANA
I/O,
HIZ
3
PA02
EXTINT[2]
VDDANA
I/O,
HIZ
4
PA03
EXTINT[3]
VREFA
AIN[1]
VDDANA
I/O,
HIZ
5
PA04
EXTINT[4]
VREFB
AIN[4]
AIN[0]
SERCOM0/
PAD[0]
TCC0/
WO[0]
CCL/
IN[0]
VDDANA
I/O,
HIZ
6
PA05
EXTINT[5]
AIN[5]
AIN[1]
SERCOM0/
PAD[1]
TCC0/
WO[1]
CCL/
IN[1]
VDDANA
I/O,
HIZ
7
PA06
EXTINT[6]
AIN[6]
INN[0]
AIN[2]
SERCOM0/
PAD[2]
TCC1/
WO[0]
CCL/
IN[2]
VDDANA
I/O,
HIZ
8
PA07
EXTINT[7]
AIN[7]
INP[0]
AIN[3]
SERCOM0/
PAD[3]
TCC1/
WO[1]
CCL/
OUT[0]
VDDANA
I/O,
HIZ
9
VDDANA
VDDANA
10
GNDANA
GNDANA
11
PA08(1)
NMI
AIN[0]
AIN[8]
SERCOM
EXTINT[1]
DAC
PA01/
XOUT32
AC
2
SDADC
I/O,
HIZ
ADC1
VDDANA
ADC0
TCC2/
WO[0]
REF
SERCOM1/
PAD[0]
EIC
EXTINT[0]
Pin name
PA00/
XIN32
VOUT
AIN[10]
SERCOM0/
PAD[0]
SERCOM2/
PAD[0]
TCC0/
WO[0]
TCC1/
WO[2]
CCL/
IN[3]
CCL/
OUT[3]
PDEC[0]
VDDIO
I/O,
HIZ
PIC32CM MC00 Family
1
rotatethispage90
Pinout and Packaging
DS60001638D-page 10
Reset State
F
Supply
E
TC/TCC
D
SERCOM-ALT
32-pin QFP
C
32-pin VQFN/32-pin TQFP Pinout and Multiplexing
B
TCC
4.2
© 2021 Microchip Technology Inc.
and its subsidiaries
A
G
H
I
J
CCL/
IN[5]
PDEC[2]
VDDIO
I/O,
HIZ
TCC0/
WO[3]
GCLK/
IO[5]
CCL/
OUT[1]
VDDIO
I/O,
HIZ
TC4/
WO[0]
TCC0/
WO[4]
GCLK/
IO[0]
VDDIO
I/O,
HIZ
TC4/
WO[1]
TCC0/
WO[5]
GCLK/
IO[1]
VDDIO
I/O,
HIZ
SERCOM3/
PAD[0]
TCC2/
WO[0]
TCC0/
WO[6]
PDEC/
QDI[0]
GCLK/
IO[2]
CCL/
IN[0]
VDDIO
I/O,
HIZ
SERCOM1/
PAD[1]
SERCOM3/
PAD[1]
TCC2/
WO[1]
TCC0/
WO[7]
PDEC/
QDI[1]
GCLK/
IO[3]
CCL/
IN[1]
VDDIO
I/O,
HIZ
EXTINT[2]
SERCOM1/
PAD[2]
SERCOM3/
PAD[2]
TC4/
WO[0]
TCC0/
WO[2]
PDEC/
QDI[2]
AC/
CMP[0]
CCL/
IN[2]
VDDIO
I/O,
HIZ
PA19
EXTINT[3]
SERCOM1/
PAD[3]
SERCOM3/
PAD[3]
TC4/
WO[1]
TCC0/
WO[3]
AC/
CMP[1]
CCL/
OUT[0]
VDDIO
I/O,
HIZ
PA22(1)
EXTINT[6]
SERCOM3/
PAD[0]
TC0/
WO[0]
TCC0/
WO[4]
GCLK/
IO[6]
CCL/
IN[6]
VDDIO
I/O,
HIZ
13
PA10(2)
EXTINT[10]
14
PA11(2)
EXTINT[11]
15
PA14/
XIN
EXTINT[14]
16
PA15/
XOUT
17
TCC1/
WO[3]
AIN[10]
SERCOM0/
PAD[2]
SERCOM2/
PAD[2]
TCC1/
WO[0]
TCC0/
WO[2]
AIN[11]
SERCOM0/
PAD[3]
SERCOM2/
PAD[3]
TCC1/
WO[1]
SERCOM2/
PAD[2]
EXTINT[15]
SERCOM2/
PAD[3]
PA16(1)
EXTINT[0]
SERCOM1/
PAD[0]
18
PA17(1)
EXTINT[1]
19
PA18
20
21
DAC
TCC0/
WO[1]
AC
SERCOM2/
PAD[1]
SDADC
SERCOM0/
PAD[1]
REF
TCC
AIN[11]
TC/TCC
AIN[9]
SERCOM-ALT
EXTINT[9]
SERCOM
ADC1
GCLK/
IO[4]
ADC0
I/O,
HIZ
EIC
VDDIO
PA09(1)
PIC32CM MC00 Family
PDEC[1]
12
rotatethispage90
Pinout and Packaging
DS60001638D-page 11
CCL/
IN[4]
Pin name
Datasheet
Reset State
F
Supply
E
CCL/PDEC
D
CCL
C
AC/
GCLK
B
PDEC
A
32-pin QFP
© 2021 Microchip Technology Inc.
and its subsidiaries
...........continued
Reset State
TCC1/
WO[2]
CCL/
IN[8]
VDDIO
I/O,
HIZ
TCC1/
WO[3]
CCL/
OUT[2]
VDDIO
I/O,
HIZ
VDDIN
I/O,
HIZ
VDDIN
I,
PU
VDDIN
I/O,
HIZ
EXTINT[12]
SERCOM3/
PAD[2]
TC1/
WO[0]
24
PA25
EXTINT[13]
SERCOM3/
PAD[3]
TC1/
WO[1]
25
PA27
EXTINT[15]
26
RESET(3)
27
PA28
28
GND
29
VDDCORE
30
VDDIN
31
PA30/
SWCLK
EXTINT[10]
SERCOM1/
PAD[2]
TCC1/
WO[0]
32
PA31/
SWDIO
EXTINT[11]
SERCOM1/
PAD[3]
TCC1/
WO[1]
DAC
PA24
AC
23
SDADC
TCC0/
WO[5]
GCLK/
IO[0]
CCL/
IN[10]
GCLK/
IO[0]
EXTINT[8]
CCL/
IN[11]
GND
VDDIN
SWCLK
GCLK/
IO[0]
CCL/
IN[3]
VDDIN
I/O,
HIZ
CCL/
OUT[1]
VDDIN
I/O,
HIZ
Pinout and Packaging
DS60001638D-page 12
TC0/
WO[1]
ADC1
CCL/PDEC
PDEC
I/O,
HIZ
SERCOM3/
PAD[1]
PIC32CM MC00 Family
Supply
Datasheet
VDDIO
EXTINT[7]
ADC0
J
CCL/
IN[7]
PA23(1)
REF
I
GCLK/
IO[7]
22
rotatethispage90
H
CCL
G
AC/
GCLK
F
TCC
SERCOM-ALT
E
TC/TCC
D
EIC
C
Pin name
B
SERCOM
A
32-pin QFP
© 2021 Microchip Technology Inc.
and its subsidiaries
...........continued
F
G
H
I
J
TC/TCC
TCC
PDEC
AC/
GCLK
CCL
CCL/PDEC
Reset State
E
Supply
D
SERCOM-ALT
DAC
C
SERCOM
rotatethispage90
AC
SDADC
ADC1
ADC0
B
REF
EIC
Pin name
A
32-pin QFP
© 2021 Microchip Technology Inc.
and its subsidiaries
...........continued
Notes:
1.
PA08, PA09, PA16, PA17, PA22, PA23 are TWIHS pins and have the same properties as standard pins when not used as SERCOM I2C pins. Refer to the Electrical Characteristics
section for additional information.
2.
PA10, PA11 are high-sink pins and have different properties than all other GPIO. Refer to the electrical characteristics section for additional information.
3.
The RESET pin has the same properties as standard GPIO.
Datasheet
PIC32CM MC00 Family
Pinout and Packaging
DS60001638D-page 13
PIC32CM MC00 Family
Pinout and Packaging
4.3
48-pin VQFN/48-pin TQFP
48-pin VQFN Top View
48-pin TQFP Top View
PIC32CM1216MC00048
PIC32CM6408MC00048
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 14
F
G
H
I
J
Datasheet
TCC
PDEC
AC/
GCLK
CCL
CCL/PDEC
SERCOM1/ TCC2/
PAD[1]
WO[1]
VDDANA
I/O, HI-Z
3
PA02
EXTINT[2]
VDDANA
I/O, HI-Z
4
PA03
EXTINT[3]
VDDANA
I/O, HI-Z
5
GNDANA
GNDANA
6
VDDANA
VDDANA
7
PB08
EXTINT[8]
AIN[2]
AIN[4]
INN[1]
TC0/
WO[0]
CCL/
IN[8]
VDDANA
I/O, HI-Z
8
PB09
EXTINT[9]
AIN[3]
AIN[5]
INP[1]
TC0/
WO[1]
CCL/
OUT[2]
VDDANA
I/O, HI-Z
9
PA04
EXTINT[4]
10
PA05
11
AIN[0]
VREFA
SERCOM
EXTINT[1]
DAC
PA01/
XOUT32
AC
2
SDADC
I/O, HI-Z
ADC1
VDDANA
ADC0
SERCOM1/ TCC2/
PAD[0]
WO[0]
REF
EXTINT[0]
EIC
PA00/
XIN32
Pin name
1
rotatethispage90
VOUT
AIN[1]
AIN[0]
SERCOM0/ TCC0/
PAD[0]
WO[0]
CCL/
IN[0]
VDDANA
I/O, HI-Z
EXTINT[5]
AIN[5]
AIN[1]
SERCOM0/ TCC0/
PAD[1]
WO[1]
CCL/
IN[1]
VDDANA
I/O, HI-Z
PA06
EXTINT[6]
AIN[6]
INN[0] AIN[2]
SERCOM0/ TCC1/
PAD[2]
WO[0]
CCL/
IN[2]
VDDANA
I/O, HI-Z
12
PA07
EXTINT[7]
AIN[7]
INP[0] AIN[3]
SERCOM0/ TCC1/
PAD[3]
WO[1]
CCL/
OUT[0]
CCL/
OUT[3]
VDDANA
I/O, HI-Z
13
PA08(1)
NMI
AIN[8]
AIN[10]
SERCOM0/ SERCOM2/ TCC0/ TCC1/
PAD[0]
PAD[0]
WO[0] WO[2]
CCL/
IN[3]
PDEC[0]
VDDIO
I/O, HI-Z
14
PA09(1)
EXTINT[9]
AIN[9]
AIN[11]
SERCOM0/ SERCOM2/ TCC0/ TCC1/
PAD[1]
PAD[1]
WO[1] WO[3]
CCL/
IN[4]
PDEC[1]
VDDIO
I/O, HI-Z
15
PA10(2)
EXTINT[10]
AIN[10]
CCL/
IN[5]
PDEC[2]
VDDIO
I/O, HI-Z
SERCOM0/ SERCOM2/ TCC1/ TCC0/
PAD[2]
PAD[2]
WO[0] WO[2]
GCLK/
IO[4]
Pinout and Packaging
DS60001638D-page 15
AIN[4]
VREFB
PIC32CM MC00 Family
Reset State
E
Supply
D
TC/TCC
48-pin QFN
C
48-pin VQFN/48-pin TQFP Pinout and Multiplexing
B
SERCOM-ALT
4.4
© 2021 Microchip Technology Inc.
and its subsidiaries
A
TC/TCC
TCC
PDEC
I
J
GCLK/
IO[5]
CCL/
OUT[1]
Reset State
SERCOM-ALT
H
Supply
G
CCL/PDEC
F
CCL
E
AC/
GCLK
D
VDDIO
I/O, HI-Z
Datasheet
GND
GND
19
PB10(2)
EXTINT[10]
TC1/ TCC0/
WO[0] WO[4]
GCLK/
IO[4]
CCL/
IN[5]
VDDIO
I/O, HI-Z
20
PB11(2)
EXTINT[11]
TC1/ TCC0/
WO[1] WO[5]
GCLK/
IO[5]
CCL/
OUT[1]
VDDIO
I/O, HI-Z
21
PA12(1)
EXTINT[12]
SERCOM2/
PAD[0]
TCC2/ TCC0/
WO[0] WO[6]
AC/
CMP[0]
VDDIO
I/O, HI-Z
22
PA13(1)
EXTINT[13]
SERCOM2/
PAD[1]
TCC2/ TCC0/
WO[1] WO[7]
AC/
CMP[1]
VDDIO
I/O, HI-Z
23
PA14/
XIN
EXTINT[14]
SERCOM2/
PAD[2]
TC4/ TCC0/
WO[0] WO[4]
GCLK/
IO[0]
VDDIO
I/O, HI-Z
24
PA15/
XOUT
EXTINT[15]
SERCOM2/
PAD[3]
TC4/ TCC0/
WO[1] WO[5]
GCLK/
IO[1]
VDDIO
I/O, HI-Z
25
PA16(1)
EXTINT[0]
SERCOM1/ SERCOM3/ TCC2/ TCC0/
PAD[0]
PAD[0]
WO[0] WO[6]
PDEC/
QDI[0]
GCLK/
IO[2]
CCL/
IN[0]
VDDIO
I/O, HI-Z
26
PA17(1)
EXTINT[1]
SERCOM1/ SERCOM3/ TCC2/ TCC0/
PAD[1]
PAD[1]
WO[1] WO[7]
PDEC/
QDI[1]
GCLK/
IO[3]
CCL/
IN[1]
VDDIO
I/O, HI-Z
27
PA18
EXTINT[2]
SERCOM1/ SERCOM3/ TC4/ TCC0/
PAD[2]
PAD[2]
WO[0] WO[2]
PDEC/
QDI[2]
AC/
CMP[0]
CCL/
IN[2]
VDDIO
I/O, HI-Z
28
PA19
EXTINT[3]
SERCOM1/ SERCOM3/ TC4/ TCC0/
PAD[3]
PAD[3]
WO[1] WO[3]
AC/
CCL/
CMP[1] OUT[0]
VDDIO
I/O, HI-Z
29
PA20
EXTINT[4]
SERCOM3/ TC3/ TCC0/
PAD[2]
WO[0] WO[6]
GCLK/
IO[4]
VDDIO
I/O, HI-Z
DAC
18
AC
VDDIO
SDADC
VDDIO
AIN[11]
ADC1
17
ADC0
EXTINT[11]
REF
PA11(2)
SERCOM0/ SERCOM2/ TCC1/ TCC0/
PAD[3]
PAD[3]
WO[1] WO[3]
CCL/
OUT[3]
PIC32CM MC00 Family
16
rotatethispage90
Pinout and Packaging
DS60001638D-page 16
EIC
C
Pin name
B
SERCOM
A
48-pin QFN
© 2021 Microchip Technology Inc.
and its subsidiaries
...........continued
J
VDDIO
I/O, HI-Z
CCL/
IN[6]
VDDIO
I/O, HI-Z
CCL/
IN[7]
VDDIO
I/O, HI-Z
TC1/ TCC1/
WO[0] WO[2]
CCL/
IN[8]
VDDIO
I/O, HI-Z
TC1/ TCC1/
WO[1] WO[3]
CCL/
OUT[2]
VDDIO
I/O, HI-Z
CCL/PDEC
Reset State
I
Supply
PDEC
H
CCL
G
AC/
GCLK
F
TCC
33
E
TC/TCC
PA23(1)
D
SERCOM-ALT
32
SERCOM
EXTINT[6]
DAC
PA22(1)
AC
31
C
SDADC
EXTINT[5]
ADC1
EIC
PA21
ADC0
Pin name
30
rotatethispage90
B
REF
A
48-pin QFN
© 2021 Microchip Technology Inc.
and its subsidiaries
...........continued
Datasheet
CCL/
IN[9]
SERCOM3/
PAD[0]
TC0/ TCC0/
WO[0] WO[4]
GCLK/
IO[6]
EXTINT[7]
SERCOM3/
PAD[1]
TC0/ TCC0/
WO[1] WO[5]
GCLK/
IO[7]
PA24
EXTINT[12]
SERCOM3/
PAD[2]
34
PA25
EXTINT[13]
SERCOM3/
PAD[3]
35
GND
GND
36
VDDIO
VDDIO
37
PB22
EXTINT[6]
TC3/
WO[0]
GCLK/
IO[0]
CCL/
IN[0]
VDDIO
I/O, HI-Z
38
PB23
EXTINT[7]
TC3/
WO[1]
GCLK/
IO[1]
CCL/
OUT[0]
VDDIO
I/O, HI-Z
39
PA27
EXTINT[15]
VDDIN
I/O, HI-Z
40
RESET(3)
VDDIN
I, PU
41
PA28
VDDIN
I/O, HI-Z
42
GND
GCLK/
IO[0]
CCL/
IN[10]
GCLK/
IO[0]
EXTINT[8]
CCL/
IN[11]
GND
43 VDDCORE
44
VDDIN
45
PA30/
SWCLK
VDDIN
EXTINT[10]
SERCOM1/ TCC1/
PAD[2]
WO[0]
SWCLK
GCLK/
IO[0]
CCL/
IN[3]
VDDIN
SWCLK,
I, PU
PIC32CM MC00 Family
GCLK/
IO[5]
Pinout and Packaging
DS60001638D-page 17
SERCOM3/ TC3/ TCC0/
PAD[3]
WO[1] WO[7]
47
PB02
EXTINT[2]
48
PB03
EXTINT[3]
TC/TCC
TCC
PDEC
AC/
GCLK
I
J
CCL/PDEC
H
CCL
G
TC2/
WO[0]
CCL/
OUT[0]
VDDANA
I/O, HI-Z
AIN[3]
TC2/
WO[1]
VDDANA
I/O, HI-Z
SERCOM
AIN[2]
DAC
I/O, HI-Z
AC
VDDIN
SDADC
Reset State
EXTINT[11]
F
Supply
PA31/
SWDIO
E
CCL/
OUT[1]
rotatethispage90
46
D
SERCOM-ALT
C
SERCOM1/ TCC1/
PAD[3]
WO[1]
ADC1
ADC0
B
REF
Pin name
EIC
A
48-pin QFN
© 2021 Microchip Technology Inc.
and its subsidiaries
...........continued
Notes:
Datasheet
1.
PA08, PA09, PA12, PA13, PA16, PA17, PA22, PA23 are TWIHS pins and have the same properties as standard pins when not used as SERCOM I2C pins. Refer to the Electrical
Characteristics section for additional information.
2.
PA10, PA11, PB10, PB11 are high-sink pins and have different properties than all other GPIO. Refer to the electrical characteristics section for additional information.
3.
The RESET pin has the same properties as standard GPIO.
PIC32CM MC00 Family
Pinout and Packaging
DS60001638D-page 18
PIC32CM MC00 Family
Signal Description
5.
Signal Description
The following tables provide the details on signal names classified by the peripheral.
Table 5-1. Signal Descriptions List
Signal Name
Function
Type
AIN[3:0]
AC Analog Inputs
Analog Input
CMP[1:0]
AC Comparator Outputs
Digital Output
AIN[11:0]
ADC Analog Inputs
Analog Input
VREFA(1)
ADC Voltage External Reference A
Analog Input
VOUT
DAC Voltage output
Analog Output
VREFA(1)
DAC Voltage External Reference A
Analog Input
INN[1:0]
SDADC Analog Negative Inputs
Analog Input
INP[1:0]
SDADC Analog Positive Inputs
Analog Input
VREFB
SDADC Voltage External Reference B
Analog Input
EXTINT[15:0]
External Interrupts inputs
Digital Input
NMI
External Non-Maskable Interrupt input
Digital Input
PA31-PA30, PA28-PA27, PA25-PA00
General Purpose I/O Pin in Port A
Digital I/O
PB23-PB22,PB11-PB08,PB03-PB02
General Purpose I/O Pin in Port B
Digital I/O
Generic Clock Source (Input) or Generic Clock Signal (Output)
Digital I/O
IN[11:0]
Inputs to lookup table
Digital Input
OUT[3:0]
Outputs from lookup table
Digital Output
External Reset Pin (Active Level: LOW)
Digital Input
SERCOM Inputs/Outputs Pads
Digital I/O
XIN
Crystal Input or External Clock Input
Analog Input (Crystal Oscillator) Digital Input (External Clock)
XOUT
Crystal Output
Analog Output
XIN32
32 kHz Crystal Input or External Clock Input
Analog Input (Crystal Oscillator) Digital Input (External Clock)
XOUT32
32 kHz Crystal Output
Analog Output
Waveform Outputs
Digital I/O
Analog Comparators (AC)
Analog-to- Digital Converter ( ADCx)
Digital-to-Analog Converter (DAC)
Sigma-Delta Analog-to-Digital Converter (SDADC)
External Interrupt Controller (EIC)
General Purpose I/O (PORT)
Generic Clock Generator (GCLK)
GCLK_IO[8:0] (2)
Custom Control Logic (CCL)
Power Manager (PM)
RESET_N
Serial Communication Interface (SERCOMx)
PAD[3:0]
Oscillators Control (OSCCTRL)
32 kHz Oscillators Control (OSC32KCTRL)
Timer Counter (TCx)
WO[1:0]
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 19
PIC32CM MC00 Family
Signal Description
...........continued
Signal Name
Function
Type
Waveform Outputs
Digital I/O
PDEC Input
Digital Input
SWCLK
Serial Wire Debug Clock
Digital Input
SWDIO
Serial Wire Debug Data
Digital I/O
Timer Counter (TCCx)
WO[7:0]
Position Decoder (PDEC)
PDEC[2:0]
Serial Wire Debug Interface
Notes:
1. VREFA is shared between the ADC and DAC peripherals.
2. GCLK8 does not support an input/output on a pin.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 20
PIC32CM MC00 Family
Power Supply and Start-Up Considerations
6.
Power Supply and Start-Up Considerations
6.1
Power Domain Overview
VDDIO
PA[28:27]
PA[31:30]
VDDIN
GND
VDDCORE
VDDANA
GNDANA
Figure 6-1. Power Domain Overview, PIC32MC
ADC0
PA[7:2]
PB[3:2]
ADC1
AC
PB[9:8]
Voltage
Regulator
OSC48M
TOSC(1)
BODCORE
DAC
SDADC
PA[25:16]
Digital Logic
(CPU, PD1
Peripherals)
POR
BOD50
OSCULP32K
OSC32K
PA[1:0]
POR
Digital Logic
PA[13:8]
PB[23:22]
SERCOM[4:0],
TCC[2:0]
FDPLL96M
TC[3:0], DAC,
I2S,
AES,
TRNG
LOW
POWER
NVM
PAC,
DMAC
RAM
PB[11:10]
XOSC
PA[15:14]
LOW POWER
SRAM
RAM
XOSC32K
Note:
1. TOSC is an independent Oscillator for the internal Temperature Sensor.
6.2
Power Supply Considerations
6.2.1
Power Supplies PIC32CM MC
The PIC32CM MC has the following power supply pins:
•
•
•
•
VDDIO: Powers I/O lines and XOSC
VDDIN: Powers I/O lines and the OSC48M, TOSC and internal regulator
VDDANA: Powers I/O lines and the ADC, AC, DAC, OSCULP32K, OSC32K, and XOSC32K
VDDCORE: Internal regulated voltage output. Powers the core, memories, peripherals, and FDPLL96M
The same voltage must be applied to both the VDDIN and VDDANA pins. This common voltage is referred to as VDD
in the data sheet. VDDIO must always be less than or equal to VDDIN.
The ground pins, GND, are common to VDDCORE, VDDIO and VDDIN. The ground pin for VDDANA is GNDANA.
For decoupling recommendations for the different power supplies, refer to the 43. Electrical Characteristics 85℃.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 21
PIC32CM MC00 Family
Power Supply and Start-Up Considerations
6.2.2
Voltage Regulator
The PIC32CM MC voltage regulators have these two modes:
•
•
6.2.3
Normal mode: This is the default mode when CPU and peripherals are running.
Low Power (LP) mode: This default mode is used when the chip is in standby mode.
Typical Powering Schematics
The PIC32CM MC uses a single supply from 2.70V to 5.50V or dual-supply mode where VDDIO is supplied
separately from VDDIN. See the Schematic Checklist chapter.
6.2.4
Power-Up Sequence
6.2.4.1
Minimum Rise Rate
The integrated Power-on Reset (POR) circuitry monitoring the VDDIN = VDDANA, and the VDDIO power supplies
require a minimum rise rate, which is described in the 43. Electrical Characteristics 85℃.
6.2.4.2
Maximum Rise Rate
The rise rate of the power supply must not exceed the values described in Electrical Characteristics.
6.3
Power-Up
This section summarizes the power-up sequence of the PIC32CM MC. The behavior after power-up is controlled by
the Power Manager.
6.3.1
Starting of Clocks
After power-up, the device is set to its initial state and kept in reset, until the power has stabilized throughout the
device. Once the power has stabilized, the device will use a 4 MHz clock. This clock is derived from the 48 MHz
Internal Oscillator (OSC48M), which is configured to provide a 4 MHz clock and used as a clock source for generic
clock generator 0. Generic clock generator 0 is the main clock for the Power Manager (PM).
Some synchronous system clocks are active, allowing software execution.
Refer to the Clock Mask Register in the MCLK - Main Clock for the list of default peripheral clocks running.
Synchronous system clocks that are running are by default not divided and receive a 4 MHz clock through generic
clock generator 0. Other generic clocks are disabled.
6.3.2
I/O Pins
After power-up, the I/O pins are tri-stated.
6.3.3
Fetching of Initial Instructions
After reset is released, the CPU starts fetching PC and SP values from the reset address, which is 0x00000000.
This address points to the first executable address in the internal Flash. The code read from the internal Flash is
free to configure the clock system and clock sources. Refer to the Arm Architecture Reference Manual for additional
information on CPU startup (http://www.arm.com).
6.4
Power-on Reset (POR) and Brown-out Detector (BOD)
The following features are used to monitor, warn, and reset the device:
•
•
•
POR: Power-on Reset on VDDIN and VDDIO
BODVDD: Brown-out Detector on VDDIN
BODCORE: Voltage Regulator Internal Brown-out Detector on VDDCORE. The Voltage Regulator Internal BOD
is calibrated in production and its calibration configuration is stored in the NVM User Row (See 8.3 NVM User
Row Mapping). This configuration must not be changed if the user row is written to assure the correct behavior
of the BODCORE. This configuration is automatically copied at boot-up in the BODCORE registers.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 22
PIC32CM MC00 Family
Power Supply and Start-Up Considerations
6.4.1
Power-on Reset on VDDIN
POR monitors VDDIN. It is always activated and monitors voltage at startup and also during all the sleep modes. If
VDDIN goes below the threshold voltage, the entire chip is reset.
6.4.2
Power-on Reset on VDDIO
POR monitors VDDIO. It is always activated and monitors voltage at startup and also during all the sleep modes. If
VDDIO goes below the threshold voltage, all I/Os supplied by VDDIO are reset.
6.4.3
Brown-out Detector on VDDIN
BODVDD monitors VDDIN.
6.4.4
Brown-out Detector on VDDCORE
Once the device has started up, BODCORE monitors the internal VDDCORE.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 23
PIC32CM MC00 Family
Product Mapping
7.
Product Mapping
Figure 7-1. PIC32CM MC00 Product Mapping
Global Memory Space
Code
0x00000000
0x00000000
FLASH
0x20000000
SRAM
0x00020000
0x00400000
Internal Flash
0x00401000 (Data Flash) 4KB
0x00800000
Internal Flash
CAL/AUX
0x0080A04C
Reserved
0x22008000
0x1FFFFFFF
Undefined
0x40000000
SRAM
0x60000000
Reserved
AHB-APB
Bridge B
AHB-APB
Bridge C
AHB-APB Bridge A
0x44000000
PAC
0x40000400
0x40000800
MCLK
RSTC
0x40001000
OSCCTRL
0x40001400
OSC32KCTRL
0x40001800
SUPC
GCLK
0x40002000
WDT
RTC
0x40002800
0x40003000
0x40003400
0x40FFFFFF
© 2021 Microchip Technology Inc.
and its subsidiaries
0x42002800
EIC
0x42002C00
0x42003400
Reserved
0x48000000
AHB
DIVAS
0x480001FF
AHB-APB Bridge B
0x41000000
SERCOM2
SERCOM3
Reserved
Reserved
Reserved
TCC0
TCC1
TCC2
TC0
TC1
TC2
0x42004000
0x42004400
0x42004800
0x42004C00
PORT
0x42005000
DSU
0x42005400
0x41002000
0x41004000
SERCOM1
0x42003800
0x45000000
0x40000C00
SERCOM0
Reserved
0x42003C00
PM
EVSYS
0x42002000
Reserved
0x40000000
0x40002C00
0x42001800
0x42003000
0x42000000
0xFFFFFFFF
0x40002400
0x42001400
0x42002400
AHB-APB
Bridge A
Reserved
0x40001C00
0x42000C00
0x41000000
0x60000400
DIVAS
0x600003FF
AHB-APB
0x40000000
IOBUS
0x60000220
0x42000800
0x42001C00
0x20004000
Reserved
PORT
0x42000400
0x20000000
0x48000200
0x60000200
AHB-APB Bridge C
0x42000000
0x42001000
SRAM
Peripherals
0x60000000
Internal Flash
NVM MAIN 128KB
NVMCTRL
TC3
TC4
ADC0
ADC1
SDADC
AC
DAC
0x42005800
Reserved
0x41006000
DMAC
0x42005C00
MTB
0x42006000
CCL
0x41008000
0x4100A000
Reserved
Reserved
0x42006400
Reserved
0x41FFFFFF
0x42006800
FREQM
0x42006C00
TSENS
PDEC
Reserved
0x42FFFFFF
Reserved
Datasheet
DS60001638D-page 24
PIC32CM MC00 Family
Memories
8.
Memories
8.1
Embedded Memories
•
•
8.2
Internal high-speed Flash with read-while-write capability on section of the array
Internal high-speed SRAM, single-cycle access at full speed
Physical Memory Map
The high-speed bus is implemented as a bus matrix. All high-speed bus addresses are fixed, and they are never
remapped in any way, even during boot. The 32-bit physical address space is mapped as shown in the following
table:
Table 8-1. Memory Map
Memory
StartAddress
PIC32CM1216
PIC32CM6408
128KB
64KB
2048
1024
size
Embedded Flash
0x00000000
page number
page size
64 bytes
size
Embedded Data Flash section
page number
0x00400000
4KB
2KB
64
32
page size
8.3
64 bytes
Embedded high-speed SRAM
0x20000000
16KB
8KB
AHB-APB Bridge A
0x40000000
16KB
AHB-APB Bridge B
0x41000000
64KB
AHB-APB Bridge C
0x42000000
32KB
AHB DIVAS
0x48000000
32B
IOBUS
0x60000000
512B
NVM User Row Mapping
The first two 32-bit words of the NVM User Row contains calibration data that are automatically read at device power
on.
The NVM User Row can be read at address 0x00804000.
To write the NVM User Row, refer to the NVMCTRL - Non-Volatile Memory Controller.
Note that when writing to the user row the values do not get loaded by the other modules on the device until a device
reset occurs.
Table 8-2. NVM User Row Mapping
Bit Position Name
Usage
2:0
BOOTPROT
Used to select one of eight
different bootloader sizes.
7:3
Reserved
-
© 2021 Microchip Technology Inc.
and its subsidiaries
Production
setting
0x7
0x1F
Datasheet
Related Peripheral Register
NVMCTRL
-
DS60001638D-page 25
PIC32CM MC00 Family
Memories
...........continued
Bit Position Name
Usage
Production
setting
13:8
BODVDD Level
BODVDD Threshold Level at
power on.
0x8
SUPC.BODVDD.LEVEL
14
BODVDD Disable
BODVDD Disable at power
on.
0x0
SUPC.BODVDD.ENABLE
16:15
BODVDD Action
BODVDD Action at power
on.
0x1
SUPC.BODVDD.ACTION
25:17
BODCORE
calibration
DO NOT CHANGE (1)
26
WDT Enable
WDT Enable at power on.
0x0
WDT.CTRLA.ENABLE
27
WDT Always-On
WDT Always-On at power
on.
0x0
WDT.CTRLA.ALWAYSON
31:28
WDT Period
WDT Period at power on.
0xB
WDT.CONFIG.PER
35:32
WDT Window
WDT Window mode time-out
at power on.
0xB
WDT.CONFIG.WINDOW
39:36
WDT EWOFFSET
WDT Early Warning Interrupt
Time Offset at power on.
0xB
WDT.EWCTRL.EWOFFSET
40
WDT WEN
WDT Timer Window Mode
Enable at power on.
0x0
WDT.CTRLA.WEN
41
BODVDD
Hysteresis
BODVDD Hysteresis
configuration at power on.
0x0
SUPC.BODVDD.HYSTERESIS
42
BODCORE
calibration
DO NOT CHANGE (1)
0x0
-
47:43
Reserved
-
0x1F
-
63:48
LOCK
NVM Region Lock Bits.
0x0A8
0xFFFF
Related Peripheral Register
-
NVMCTRL.LOCK
Note:
1. BODCORE is calibrated in production and its calibration parameters must not be changed to ensure the
correct device behavior.
8.4
NVM Software Calibration Area Mapping
The NVM Software Calibration Area contains calibration data that are measured and written during production test.
These calibration values should be read by the application software and written back to the corresponding register.
The NVM Software Calibration Area can be read at address 0x00806020.
The NVM Software Calibration Area can not be written.
Table 8-3. NVM Software Calibration Area Mapping
Bit Position Name
Description
2:0
ADC0 BIASREFBUF ADC0 Linearity Calibration. Should be written to ADC0 CALIB.BIASREFBUF.
5:3
ADC0 BIASCOMP
8:6
ADC1 BIASREFBUF ADC1 Linearity Calibration. Should be written to ADC1 CALIB.BIASREFBUF.
11:9
ADC1 BIASCOMP
© 2021 Microchip Technology Inc.
and its subsidiaries
ADC0 Bias Calibration. Should be written to ADC0 CALIB.BIASCOMP.
ADC1 Bias Calibration. Should be written to ADC1 CALIB.BIASCOMP.
Datasheet
DS60001638D-page 26
PIC32CM MC00 Family
Memories
...........continued
8.5
Bit Position Name
Description
18:12
OSC32K CAL
OSC32K Calibration. Should be written to OSC32KCTRL OSC32K.CALIB.
40:19
CAL48M
OSC48M Calibration: Should be written to OSCCTRL.CAL48M[21:0].
63:41
Reserved
Reserved
NVM Temperature Calibration Area Mapping
The NVM Temperature Calibration Area contains calibration data that are measured and written during production
test. These calibration values should be read by the application software and written back to the corresponding
register.
The NVM Temperature Calibration Area can be read at address 0x806030.
The NVM Temperature Calibration Area can not be written.
Table 8-4. NVM Temperature Calibration Area Mapping
8.6
Bit Position Name
Description
5:0
TSENS TCAL
TSENS Temperature Calibration. Should be written to the TSENS CAL register.
11:6
TSENS FCAL
TSENS Frequency Calibration. Should be written to the TSENS CAL register.
35:12
TSENS GAIN
TSENS Gain Calibration. Should be written to the TSENS GAIN register.
59:36
TSENS OFFSET TSENS Offset Calibration. Should be written to TSENS OFFSET register.
63:60
Reserved
Serial Number
Each device has a unique 128-bit serial number which is a concatenation of four 32-bit words contained at the
following addresses:
Word 0: 0x0080A00C
Word 1: 0x0080A040
Word 2: 0x0080A044
Word 3: 0x0080A048
The uniqueness of the serial number is guaranteed only when using all 128 bits.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 27
PIC32CM MC00 Family
Processor and Architecture
9.
Processor and Architecture
9.1
Cortex M0+ Processor
The PIC32CM MC00 implements the Arm Cortex-M0+ processor, based on the ARMv6 Architecture and Thumb®-2
ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and upward
compatible to Cortex-M3 and M4 cores. The implemented Arm Cortex-M0+ is revision r0p1. For more information
refer to www.arm.com.
9.1.1
Cortex M0+ Configuration
Table 9-1. Cortex M0+ Configuration
Features
PIC32CM MC00 configurations
Interrupts
32
Data endianness
Little-endian
SysTick timer
Present
Number of watchpoint comparators
2
Number of breakpoint comparators
4
Halting debug support
Present
Multiplier
Fast (single cycle)
Single-cycle I/O port
Present
Wake-up interrupt controller
Not supported
Vector Table Offset Register
Present
Unprivileged/Privileged support
Present
Memory Protection Unit
8-region
Reset all registers
Absent
Instruction fetch width
32-bit
The Arm Cortex-M0+ core has the following bus interfaces:
•
•
9.1.2
Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system
memory, which includes Flash and RAM.
Single 32-bit I/O port bus interfacing to the PORT and DIVAS with 1-cycle loads and stores.
Cortex-M0+ Peripherals
•
•
•
System Control Space (SCS)
– The processor provides debug through registers in the SCS. Refer to the Cortex-M0+ Technical Reference
Manual for details (www.arm.com).
Nested Vectored Interrupt Controller (NVIC)
– External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the
priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely coupled, providing low
latency interrupt processing and efficient processing of late arriving interrupts. Refer to 9.2 Nested Vector
Interrupt Controller and Cortex-M0+ Technical Reference Manual for details (www.arm.com).
System Timer (SysTick)
– The System Timer is a 24-bit timer clocked by CLK_CPU that extends the functionality of both the
processor and the NVIC. Refer to Cortex-M0+ Technical Reference Manual for details (www.arm.com).
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 28
PIC32CM MC00 Family
Processor and Architecture
•
•
•
9.1.3
When the SysTick Overflow Interrupt is enabled, the RAM Back Bias Control must be disabled (PM>STDBYCFG.bit.BBIASHS = 0) before entering Standby Sleep mode.
System Control Block (SCB)
– The System Control Block provides system implementation information, and system control. This includes
configuration, control, and reporting of the system exceptions. Refer to Cortex-M0+ Devices Generic User
Guide for details (www.arm.com).
Micro Trace Buffer (MTB)
– The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-M0+ processor.
Refer to the section 9.3 Micro Trace Buffer and CoreSight MTB-M0+ Technical Reference Manual for
details (www.arm.com).
Memory Protection Unit (MPU)
– The Memory Protection Unit divides the memory map into a number of regions, and defines the location,
size, access permissions and memory attributes of each region. Refer to Cortex-M0+ Devices Generic
User Guide for details (http://www.arm.com)
Cortex-M0+ Address Map
Table 9-2. Cortex-M0+ Address Map
Address
Peripheral
0xE000E000
System Control Space (SCS)
0xE000E010
System Timer (SysTick)
0xE000E100
Nested Vectored Interrupt Controller (NVIC)
0xE000ED00
System Control Block (SCB)
0xE000ED90
Memory Protection Unit (MPU)
0x41008000
Micro Trace Buffer (MTB)
9.1.4
I/O Interface
9.1.4.1
Overview
Because accesses to the AMBA® AHB-Lite™ and the single cycle I/O interface can be made concurrently, the
Cortex-M0+ processor can fetch the next instructions while accessing the I/Os. This enables single cycle I/O
accesses to be sustained for as long as needed.
9.1.4.2
Description
Direct access to PORT registers and DIVAS registers.
9.2
Nested Vector Interrupt Controller
9.2.1
Overview
The Nested Vectored Interrupt Controller (NVIC) in the PIC32CM MC00 supports 32 interrupt lines with four different
priority levels. For more details, refer to the Cortex-M0+ Technical Reference Manual (www.arm.com).
9.2.2
Interrupt Line Mapping
Each of the interrupt lines is connected to one peripheral instance, as shown in the table below. Each peripheral can
have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register.
The interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually
enabled by writing a one to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and
disabled by writing a one to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register.
An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is
enabled.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 29
PIC32CM MC00 Family
Processor and Architecture
The interrupt requests for one peripheral are ORed together on system level, generating one interrupt request for
each peripheral. An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending
registers (SETPEND/CLRPEND bits in ISPR/ICPR).
For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/CLRENA
bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt.
Table 9-3. Interrupt Line Mapping, PIC32CM MC00
Peripheral Source
NVIC Line
External Interrupt Controller (EIC NMI)
NMI
Power Manager (PM)
Main Clock (MCLK)
0
Oscillators Controller (OSCCTRL)
32 kHz Oscillators Controller (OSC32KCTRL)
Supply Controller (SUPC)
Protection Access Controller (PAC)
Watchdog Timer (WDT)
1
Real Time Clock (RTC)
2
External Interrupt Controller (EIC)
3
Frequency Meter (FREQM)
4
Temperature Sensor (TSENS)
5
Non-Volatile Memory Controller (NVMCTRL)
6
Direct Memory Access Controller (DMAC)
7
Event System (EVSYS)
8
Serial Communication Controller 0 (SERCOM0)
9
Serial Communication Controller 1 (SERCOM1)
10
Serial Communication Controller 2 (SERCOM2)
11
Serial Communication Controller 3 (SERCOM3)
12
Timer Counter for Control 0 (TCC0)
13
Timer Counter for Control 1 (TCC1)
14
Timer Counter for Control 2 (TCC2 )
15
Timer Counter 0 (TC0)
16
Timer Counter 1 (TC1)
17
Timer Counter 2 (TC2 )
18
Timer Counter 3 (TC3)
19
Timer Counter 4 (TC4 )
20
Analog-to-Digital Converter 0 (ADC0)
21
Analog-to-Digital Converter 1 (ADC1)
22
Analog Comparator (AC )
23
Digital-to-Analog Converter (DAC)
24
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 30
PIC32CM MC00 Family
Processor and Architecture
...........continued
Peripheral Source
NVIC Line
SDADC
25
Position Decoder (PDEC)
26
Reserved
27-31
Note:
1. These modules are not available on all variants. Refer to 1. Configuration Summary.
9.3
Micro Trace Buffer
9.3.1
Features
•
•
•
•
9.3.2
Program flow tracing for the Cortex-M0+ processor
MTB SRAM can be used for both trace and general purpose storage by the processor
The position and size of the trace buffer in SRAM is configurable by software
CoreSight compliant
Overview
When enabled, the MTB records changes in program flow, reported by the Cortex-M0+ processor over the execution
trace interface shared between the Cortex-M0+ processor and the CoreSight MTB-M0+. This information is stored
as trace packets in the SRAM by the MTB. An off-chip debugger can extract the trace information using the Debug
Access Port to read the trace information from the SRAM. The debugger can then reconstruct the program flow from
this information.
The MTB simultaneously stores trace information into the SRAM, and gives the processor access to the SRAM. The
MTB ensures that trace write accesses have priority over processor accesses.
The execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects the processor
PC value changes non-sequentially. A non-sequential PC change can occur during branch instructions or during
exception entry. Refer to the CoreSight MTB-M0+ Technical Reference Manual for details on the MTB execution trace
packet format.
Tracing is enabled when the MASTER.EN bit in the Host Trace Control Register is 1. There are various ways to set
the bit to 1 to start tracing, or to 0 to stop tracing. Refer to the CoreSight Cortex-M0+ Technical Reference Manual
for details on the Trace start and stop and for a detailed description of the MTB’s MASTER register. The MTB can
be programmed to stop tracing automatically when the memory fills to a specified watermark level or to start or stop
tracing by writing directly to the MASTER.EN bit. If the watermark mechanism is not being used and the trace buffer
overflows, then the buffer wraps around overwriting previous trace packets.
The base address of the MTB registers is 0x41008000, and this address is also written in the CoreSight ROM table.
The offset of each register from the base address is fixed and as defined by the CoreSight MTB-M0+ Technical
Reference Manual. The MTB has 4 programmable registers to control the behavior of the trace features:
•
•
•
•
POSITION: Contains the trace write pointer and the wrap bit
MASTER: Contains the main trace enable bit and other trace control fields
FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits
BASE: Indicates where the SRAM is located in the processor memory map. This register is provided to enable
auto discovery of the MTB SRAM location, by a debug agent.
Refer to the “CoreSight MTB-M0+ Technical Reference Manual” for a detailed description of these registers.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 31
PIC32CM MC00 Family
Processor and Architecture
9.4
High-Speed Bus System
9.4.1
Features
High-Speed Bus Matrix has the following features:
•
•
•
•
Configuration
Figure 9-1. Host/Client Relation High-Speed Bus Matrix, PIC32CM MC00
High-Speed Bus CLIENTS
CM0+
0
DSU
DSU
1
DSUData
DMAC
2
DMAC Fetch
DMAC Data
DSU
CM0+
DIVAS
7
DMAC WB
AHB-APB Bridge C
5
Reserved
AHB-APB Bridge B
3
Reserved
AHB-APB Bridge A
4
MTB
Internal Flash
SRAM
0
HOST ID
Multi-Client
HOSTS
Priviledged
FlexRAM-access
HOSTS
9.4.2
Symmetric crossbar bus switch implementation
Allows concurrent accesses from different hosts to different clients
32-bit data bus
Operation at a 1-to-1 clock frequency with the bus hosts
9
8
7
5-6
3-4
6
2
2
1
1
0
CLIENT ID
FlexRAM PORT ID
MTB
DMAC WB
DMAC Fetch
Table 9-4. Bus Matrix Hosts
Bus Matrix Hosts
Cortex M0+ Processor (CM0+)
Device Service Unit (DSU)
Direct Memory Access Controller/Data Access (DMAC)
Table 9-5. Bus Matrix Clients
Bus Matrix Clients
Internal Flash Memory
SRAM - CM0+ Access
SRAM - DSU Access
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 32
PIC32CM MC00 Family
Processor and Architecture
...........continued
Bus Matrix Clients
AHB-APB Bridge A
AHB-APB Bridge B
AHB-APB Bridge C
SRAM - DMAC Data Access
DIVAS - Divide Accelerator
Table 9-6. SRAM Port Connections
SRAM Port Connection
Port ID
Connection Type
Cortex M0+ (CM0+) Processor
0
Bus Matrix
Device Service Unit (DSU)
1
Bus Matrix
Direct Memory Access Controller (DMAC) - Data Access
2
Bus Matrix
Direct Memory Access Controller (DMAC) - Fetch Access 0
3
Direct
Direct Memory Access Controller (DMAC) - Fetch Access 1
4
Direct
Direct Memory Access Controller (DMAC) - Write-Back Access 0
5
Direct
Direct Memory Access Controller (DMAC) - Write-Back Access 1
6
Direct
Reserved
7
Reserved
8
Micro Trace Buffer (MTB)
9
Direct
Note: The SMBIST has a direct access to SRAM, by passing the SRAM ports.
9.4.3
SRAM Quality of Service
To ensure that hosts with latency requirements get sufficient priority when accessing SRAM, the different hosts can
be configured to have a given priority for different type of access.
The Quality of Service (QoS) level is independently selected for each host accessing the SRAM. For any access to
the SRAM the SRAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS
level configuration is shown in the following table.
Table 9-7. Quality of Service Level Configuration
Value
Name
0x0
DISABLE
0x1
LOW
0x2
MEDIUM
0x3
HIGH
Description
Background (no sensitive operation)
Sensitive Bandwidth
Sensitive Latency
Critical Latency
If a host is configured with QoS level DISABLE (0x0) or LOW (0x1) there will be minimum latency of one cycle for the
SRAM access.
The priority order for concurrent accesses are decided by two factors. First, the QoS level for the host and second, a
static priority given by the SRAM Port ID as defined in SRAM Port Connections. The lowest port ID has the highest
static priority.
The MTB has fixed QoS level HIGH (0x3) and the DSU has fixed QoS level LOW (0x1).
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 33
PIC32CM MC00 Family
Processor and Architecture
The CPU QoS level can be written/read at address 0x4100A110, bits [1:0]. Its reset value is 0x0.
Refer to the different host registers for configuring their QoS (MRCFG, QoS, and QOSCTRL for DMAC).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 34
PIC32CM MC00 Family
Peripherals Configuration Summary
10.
Peripherals Configuration Summary
Table 10-1. Peripherals Configuration Summary for PIC32CM MC00
Peripheral
Base Address
AHB
CLK
APB
CLK
Generic
CLK
Enabled
at reset
Enabled
at reset
Index
PAC
Events
DMA
Sleep
Walking
IRQ
Index
Prot at
reset
User
Generator
Index
AHB-APB-Bridge A
0x40000000
-
Y
-
-
-
-
-
-
-
N/A
PAC
0x40000000
0
Y
Y
-
0
N
-
81:ACCERR
-
N/A
PM
0x40000400
0
-
Y
-
1
N
-
-
-
N/A
MCLK
0x40000800
0
-
Y
-
2
N
-
-
-
Y
RSTC
0x40000C00
-
-
Y
-
3
N
-
-
-
N/A
OSCCTRL
0x40001000
0
-
Y
4
N
-
1:XOSC_FAIL
-
Y
0:FDPLL96M clk source
1:FDPLL96M 32kHz
OSC32KCTRL
0x40001400
0
-
Y
-
5
N
-
2:XOSC32K_FAIL
-
Y
SUPC
0x40001800
0
-
Y
-
6
N
-
-
-
N/A
GCLK
0x40001C00
-
-
Y
-
7
N
-
-
-
N/A
WDT
0x40002000
1
-
Y
-
8
N
-
-
-
Y
-
Y
3: CMP0/ALARM0
4: CMP1
RTC
0x40002400
2
-
Y
-
9
N
5: OVF
6:13: PER0-7
EIC
0x40002800
3, NMI
-
Y
FREQM
0x40002C00
4
-
Y
2
10
N
-
14-29:EXTINT0-15
-
Y
11
N
-
-
-
N/A
12
N
0: START
30: WINMON
1: RESRDY
N/A
3: Measure
4: Reference
TSENS
0x40003000
5
-
AHB-APB-Bridge B
0x41000000
-
Y
PORT
0x41000000
-
DSU
0x41002000
-
NVMCTRL
0x41004000
DMAC
MTB
N
5: TSENS
-
-
-
-
-
-
-
N/A
Y
-
0
N
1-4: EV0-3
-
-
Y
Y
Y
-
1
Y
-
-
-
N/A
6
Y
Y
-
2
N
-
-
-
Y
0x41006000
7
Y
N/A
-
3
N
5-8: CH0-3
31-34: CH0-3
-
Y
0x41008000
-
-
N/A
-
4
N
-
-
N/A
42: START
43: STOP
AHB-APB-Bridge C
0x42000000
-
Y
-
-
-
-
-
-
-
N/A
EVSYS
0x42000000
8
-
N
6-17: one per Channel
0
N
-
-
-
Y
SERCOM0
0x42000400
9
-
N
1
N
-
-
19: CORE
2: RX
18: SLOW
20: CORE
SERCOM1
0x42000800
10
-
N
4: RX
2
N
-
-
18: SLOW
0x42000C00
11
-
N
6: RX
3
18: SLOW
© 2021 Microchip Technology Inc.
and its subsidiaries
Y
5: TX
21: CORE
SERCOM2
Y
3: TX
N
-
-
Y
7: TX
Datasheet
DS60001638D-page 35
PIC32CM MC00 Family
Peripherals Configuration Summary
...........continued
Peripheral
Base Address
AHB
CLK
APB
CLK
Generic
CLK
Enabled
at reset
Enabled
at reset
Index
-
N
PAC
Events
DMA
Sleep
Walking
IRQ
Index
Prot at
reset
User
Generator
4
N
-
-
22: CORE
SERCOM3
0x42001000
12
8: RX
Y
18: SLOW
Reserved
0x42001400
-
-
-
-
Index
9: TX
-
-
-
-
-
-
35: OVF
9-10: EV0-1
10: OVF
36: TRG
TCC0
0x42002400
13
-
N
23
9
N
Y
37: CNT
11-14: MC0-3
11-14: MC0-3
38-41: MC0-3
42: OVF
15-16: EV0-1
15: OVF
43: TRG
TCC1
0x42002800
14
-
N
23
10
N
Y
44: CNT
17-18: MC0-1
16-17: MC0-1
45-46: MC0-1
47: OVF
19-20: EV0-1
18: OVF
48: TRG
TCC2
0x42002C00
15
-
N
24
11
N
Y
49: CNT
21-22: MC0-1
19-20: MC0-1
50-51: MC0-1
TC0
0x42003000
TC1
0x42003400
TC2
0x42003800
TC3
0x42003C00
TC4
0x42004000
ADC0
ADC1
SDADC
0x42004400
0x42004800
0x42004C00
16
17
18
19
20
21
22
25
-
-
-
-
-
-
-
-
N
N
N
N
N
N
N
N
25
25
26
26
27
28
29
30
12
13
14
15
16
17
18
19
N
N
N
N
N
52: OVF
21: OVF
53-54: MC0-1
22-23: MC0-1
55: OVF
24: OVF
56-57: MC0-1
25-26: MC0-1
58: OVF
27: OVF
59-60: MC0-1
28-29: MC0-1
61: OVF
30: OVF
62-63: MC0-1
31-32: MC0-1
64: OVF
33: OVF
65-66: MC0-1
34-35: MC0-1
23: EVU
Y
24: EVU
Y
25: EVU
Y
26: EVU
Y
27: EVU
Y
28: START
67: RESRDY
29: FLUSH
68: WINMON
30: START
69: RESRDY
31: FLUSH
70: WINMON
32: START
71: RESRDY
33: FLUSH
72: WINMON
N
36: RESRDY
Y
37: RESRDY
Y
38: RESRDY
Y
-
Y
76: EMPTY
39: EMPTY
Y
N
N
73-74: COMP0-1
AC
0x42005000
23
-
N
33
20
N
34-35: SOC0-1
75: WIN0
DAC
0x42005400
24
-
Reserved
0x42005800
-
-
-
-
-
-
-
-
-
-
CCL
0x42005C00
-
-
N
32
23
N
37-40: LUTIN0-3
77-80: LUTOUT0-3
-
Y
Reserved
0x42006000
-
-
-
-
-
-
-
-
-
-
© 2021 Microchip Technology Inc.
and its subsidiaries
N
31
21
Datasheet
N
36: START
DS60001638D-page 36
PIC32CM MC00 Family
Peripherals Configuration Summary
...........continued
Peripheral
Base Address
AHB
CLK
APB
CLK
Generic
CLK
Enabled
at reset
Enabled
at reset
Index
PAC
Events
DMA
Sleep
Walking
IRQ
Index
Prot at
reset
User
Generator
Index
83: OVF
44: EVU0
84: ERR
85: DIR
PDEC
0x42006800
26
-
N
34
26
N
45: EVU1
-
Y
-
N/A
86: VLC
87: MC0
46: EVU2
88: MC1
DIVAS
0x48000000
-
Y
-
-
-
-
-
-
Registers can be 8, 16, or 32 bits wide. Atomic 8-bit, 16-bit, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
PAC Write-Protection Register Property:
Some registers are optionally write-protected by the Peripheral Access Controller (PAC).
PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description. For
more details, refer to the PAC - Peripheral Access Controller.
Read-Synchronized, Write-Synchronized Register Property:
Some registers or bit fields within a register require synchronization when read and/or written.
Synchronization is denoted by the "Read-Synchronized" ("Read-Synchronized Bits”) and "Write-Synchronized"
("Write-Synchronized Bits”) property in each individual register description. For more details, refer to Register
Synchronization.
Enable-Protected Register Property:
Some registers or bit fields within a register can only be written when the peripheral is disabled.
Such protection is denoted by the "Enable-Protected" ("Enable-Protected Bits") property in each individual register
description.
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PIC32CM MC00 Family
Clock System
11.
Clock System
This chapter only aims to summarize the clock distribution and terminology in the PIC32CM MC00 device. It will not
explain every detail of its configuration. For in-depth details, refer to the referenced module chapters.
Clock Distribution
Figure 11-1. Clock distribution
MCLK
GCLK_MAIN
GCLK
OSCCTRL
XOSC
Syncronous Clock
Controller
GCLK Generator 0
Peripheral Channel 0
GCLK Generator 1
Peripheral Channel 1
(FDPLL96M Reference)
GCLK_DPLL
GCLK Generator x
Peripheral Channel 2
(FDPLL96M Reference)
GCLK_DPLL_32K
OSC48M
GCLK_DPLL
GCLK_DPLL_32K
FDPLL96M
OSCK32CTRL
OSC32K
Peripheral Channel 3
32kHz
XOSC32K
32kHz
1kHz
OSCULP32K
Peripheral 0
Generic
Clocks
1kHz
Peripheral Channel y
32kHz
Peripheral z
1kHz
AHB/APB System Clocks
11.1
RTC
CLK_RTC_OSC
CLK_WDT_OSC
CLK_ULP32K
WDT
EIC
The clock system on the PIC32CM MC00 consists of these key features:
•
•
•
Clock sources, controlled by OSCCTRL and OSC32KCTRL
– A Clock source is the base clock signal used in the system. Example clock sources are the internal 48 MHz
oscillator (OSC48M), External crystal oscillator (XOSC) and the Digital phase-locked loop (FDPLL96M).
Generic Clock Controller (GCLK) which controls the clock distribution system, made up of the following:
– Generic Clock generators: A programmable prescaler, that can use any of the system clock sources as
its source clock. The Generic Clock Generator 0, also called GCLK_MAIN, is the clock feeding the Power
Manager used to generate synchronous clocks.
– Generic Clocks: Typically the clock input of a peripheral on the system. The generic clocks, through the
Generic Clock Multiplexer, can use any of the Generic Clock generators as its clock source. Multiple
instances of a peripheral will typically have a separate generic clock for each instance.
Main Clock controller (MCLK)
– The MCLK controls synchronous clocks on the system. This includes the CPU, bus clocks (APB, AHB) as
well as the synchronous (to the CPU) user interfaces of the peripherals. It contains clock masks that can
turn on/off the user interface of a peripheral as well as prescalers for the CPU and bus clocks.
The figure below shows an example where SERCOM0 is clocked by the OSC48M. The OSC48M is enabled,
the Generic Clock Generator 1 uses the OSC48M as its clock source, and the generic clock 19, also called
GCLK_SERCOM0_CORE, that is connected to SERCOM0 uses generator 1 as its source. The SERCOM0 interface,
clocked by CLK_SERCOM0_APB, has been unmasked in the APBC Mask register in the MCLK.
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PIC32CM MC00 Family
Clock System
Figure 11-2. Example of SERCOM clock
MCLK
Syncronous Clock
Controller
Generic Clock
Generator 1
OSC48M
11.2
CLK_SERCOM0_APB
GCLK
OSCCTRL
Peripheral
Channel 19
GCLK_SERCOM0_CORE
SERCOM 0
Synchronous and Asynchronous Clocks
As the CPU and the peripherals can be clocked from different clock sources, possibly with widely different clock
speeds, some peripheral accesses by the CPU needs to be synchronized between the different clock domains. In
these cases the peripheral includes a SYNCBUSY status register that can be used to check if a sync operation is in
progress. As the nature of the synchronization might vary between different peripherals, detailed description for each
peripheral can be found in the sub-chapter “synchronization” for each peripheral where this is necessary.
In the datasheet references to synchronous clocks are referring to the CPU and bus clocks, while asynchronous
clocks are clock generated by generic clocks.
11.3
Register Synchronization
11.3.1
Overview
All peripherals are composed of one digital bus interface, which is connected to the APB or AHB bus and
clocked using a corresponding synchronous clock, and one core clock, which is clocked using a generic clock.
Access between these clock domains must be synchronized. As this mechanism is implemented in hardware the
synchronization process takes place even if the different clocks domains are clocked from the same source and on
the same frequency. All registers in the bus interface are accessible without synchronization. All core registers in the
generic clock domain must be synchronized when written. Some core registers must be synchronized when read.
Registers that need synchronization has this denoted in each individual register description.
11.3.2
General Write-Synchronization
Inside the same module, each core register, denoted by the Write-Synchronized property, use its own synchronization
mechanism so that writing to different core registers can be done without waiting for the end of synchronization of
previous core register access.
However, a second write access to the same core register, while synchronization is on going, is discarded and an
error is reported through the PAC. To write again to the same core register in the same module, user must wait for the
end of synchronization.
For each core register, that can be written, a synchronization status bit is associated
Example:
REGA, REGB are 8-bit core registers. REGC is 16-bit core register.
Offset
Register
0x00
REGA
0x01
REGB
0x02
REGC
0x03
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PIC32CM MC00 Family
Clock System
Since synchronization is per register, users can write REGA (8-bit access) then immediately write REGB (8-bit
access) without error.
Users can write REGC (16-bit access) without affecting REGA or REGB. But if user writes REGC in two consecutive
8-bit accesses, second write will be discarded and generate an error.
When users makes a 32-bit access to offset 0x00, all registers are written but REGA, REGB, REGC can be updated
at a different time because of independent write synchronization
11.3.3
General Read-Synchronization
Before any read of a core register, the user must check the related bit in the SYNCBUSY register is cleared.
Read access to core register is always immediate but the return value is reliable only if a synchronization of this core
register is not going.
11.3.4
Completion of Synchronization
The user can either poll the SYNCBUSY register or use the Synchronization Ready interrupt (if available) to check
when the synchronization is complete.
11.3.5
Enable Write-Synchronization
Writing to the Enable bit in the Control register (CTRL.ENABLE) will also trigger write-synchronization and set
SYNCBUSY.ENABLE. CTRL.ENABLE will read its new value immediately after being written. The Synchronization
Ready interrupt (if available) cannot be used for Enable write-synchronization.
11.3.6
Software Reset Write-Synchronization
Writing a one to the Software Reset bit in CTRL (CTRL.SWRST) will also trigger write-synchronization and set
SYNCBUSY.SWRST. When writing a one to the CTRL.SWRST bit it will immediately read as one. CTRL.SWRST
and SYNCBUSY.SWRST will be cleared by hardware when the peripheral has been reset. Writing a zero to the
CTRL.SWRST bit has no effect. The Synchronization Ready interrupt (if available) cannot be used for Software
Reset write-synchronization.
11.3.7
Synchronization Delay
The synchronization will delay the read/write access duration by a delay D, as shown in the equation below:
5 ⋅ PGCLK + 2 ⋅ PAPB < D < 6 ⋅ PGCLK + 3 ⋅ PAPB
Where:
PGCLK is the period of the generic clock and PAPB is the period of the peripheral bus clock. A normal peripheral bus
register access duration is 2 ⋅ PAPB.
11.4
Enabling a Peripheral
To enable a peripheral clocked by a generic clock, the following parts of the system needs to be configured:
•
•
•
•
A running clock source.
A clock from the Generic Clock Generator must be configured to use one of the running clock sources, and the
generator must be enabled.
The generic clock, through the Generic Clock Multiplexer, that connects to the peripheral needs to be configured
with a running clock from the Generic Clock Generator, and the generic clock must be enabled.
The user interface of the peripheral needs to be unmasked in the Main Clock Controller (MCLK). If this is not
done the peripheral registers will read as all 0’s and any writes to the peripheral will be discarded.
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PIC32CM MC00 Family
Clock System
11.5
On-demand, Clock Requests
Figure 11-3. Clock request routing
Clock request
OSC48
Generic Clock
Generator
ENABLE
GENEN
RUNSTDBY
RUNSTDBY
Clock request
Generic Clock
Periph. Channel
Clock request
Peripheral
ENABLE
CHEN
RUNSTDBY
ONDEMAND
All the clock sources in the system can be run in an on-demand mode, where the clock source is in a stopped state
when no peripherals are requesting the clock source. Clock requests propagate from the peripheral, through the
GCLK, to the clock source. If one or more peripheral is using a clock source, the clock source will be started/kept
running. As soon as the clock source is no longer needed and no peripheral have an active request the clock source
will be stopped until requested again. For the clock request to reach the clock source, the peripheral, the generic
clock and the clock from the Generic Clock Generator in-between must be enabled. The time taken from a clock
request being asserted to the clock source being ready is dependent on the clock source startup time, clock source
frequency as well as the divider used in the Generic Clock Generator. The total startup time from a clock request to
the clock is available for the peripheral is given below:
Delay_start_max = Clock source startup time + 2 * clock source periods + 2 * divided clock
source periods
Delay_start_min = Clock source startup time + 1 * clock source period + 1 * divided clock
source periodDelay_start_min = Clock source startup time + 1 * clock source period + 1 *
divided clock source period
The delay for shutting down the clock source when there is no longer an active request is given below:
Delay_stop_min = 1 * divided clock source period + 1 * clock source period
Delay_stop_max = 2 * divided clock source periods + 2 * clock source periods
The On-Demand principle can be disabled individually for each clock source by clearing the ONDEMAND bit located
in each clock source controller. The clock is always running whatever is the clock request. This has the effect to
remove the clock source startup time at the cost of the power consumption.
In standby mode, the clock request mechanism is still working if the modules are configured to run in Standby mode
(RUNSTDBY bit).
11.6
Power Consumption vs. Speed
Due to the nature of the asynchronous clocking of the peripherals, users need to consider either targeting a lowpower or a fast-acting system. If clocking a peripheral with a very low clock, the active power consumption of the
peripheral will be lower. At the same time the synchronization to the synchronous (CPU) clock domain is dependent
on the peripheral clock speed, and will be longer with a slower peripheral clock, giving lower response time and more
time waiting for the synchronization to complete.
11.7
Clocks after Reset
On any reset, the synchronous clocks start to their initial state:
•
•
•
OSC48M is enabled and divided by 12
GCLK_MAIN uses OSC48M as source
CPU and BUS clocks are undivided
On a power reset the GCLK starts to their initial state:
•
All generic clock generators disabled except:
– The generator 0 (GCLK_MAIN) using OSC48M as source, with no division
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PIC32CM MC00 Family
Clock System
•
All generic clocks disabled
On a user reset the GCLK starts to their initial state, except for:
•
Generic clocks that are write-locked (WRTLOCK is written to one prior to reset)
On any reset, the clock sources are reset to their initial state except the 32.768 kHz clock sources which are reset
only by a power reset.
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PIC32CM MC00 Family
Generic Clock Controller (GCLK)
12.
Generic Clock Controller (GCLK)
12.1
Overview
Depending on the application, peripherals may require specific clock frequencies to operate correctly. The Generic
Clock controller (GCLK) features 9 Generic Clock Generators 0..8 that can provide a wide range of clock frequencies.
Generators can be set to use different external and internal oscillators as source. The clock of each Generator can
be divided. The outputs from the Generators are used as sources for the Peripheral Channels, which provide the
Generic Clocks (GCLK_PERIPH) to the peripheral modules, as shown in the 12.3 Block Diagram. The number of
peripheral clocks depends on how many peripherals the device has.
Note: The Generic Clock Generator 0 is always the direct source of the GCLK_MAIN signal.
12.2
Features
•
•
12.3
Provides a device-defined, configurable number of Peripheral Channel clocks
Wide frequency range:
– Various clock sources
– Embedded dividers
Block Diagram
The generation of Peripheral Clock signals (GCLK_PERIPH) and the Main Clock (GCLK_MAIN) can be seen in the
figure below.
Figure 12-1. Device Clocking Diagram
GENERIC CLOCK CONTROLLER
OSCCTRL
Generic Clock Generator
XOSC
FDPLL96M
Peripheral Channel
OSC48M
GCLK_PERIPH
OSC32KCTRL
XOSC32K
Clock
Divider &
Masker
Clock
Gate
PERIPHERAL
OSCULP32K
OSC32K
GCLK_IO
GCLK_MAIN
MCLK
The GCLK block diagram is shown below:
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PIC32CM MC00 Family
Generic Clock Controller (GCLK)
Figure 12-2. Generic Clock Controller Block Diagram
GCLK_MAIN
Generic Clock Generator 0
Clock Sources
Clock
Divider &
Masker
GCLK_IO[0]
(I/O input)
GCLK_IO[0]
(I/O output)
GCLK_GEN[0]
GCLK_IO[1]
(I/O output)
Generic Clock Generator 1
Clock
Divider &
Masker
GCLK_IO[1]
(I/O input)
GCLK_GEN[1]
GCLK_IO[x]
(I/O output)
Generic Clock Generator x
Clock
Divider &
Masker
GCLK_IO[x]
(I/O input)
GCLK_GEN[x]
Peripheral Channel m
Clock
Divider &
Masker
12.4
GCLK_PERIPH[m]
Clock
Gate
Generic Clock Generator 8
GCLK_GEN[8]
x from 2 to 7
m from 0 to 34
Signal Description
Table 12-1. GCLK Signal Description
Signal Name
Type
Description
GCLK_IO[7:0](1,2,3)
Digital I/O
Clock source for Generators when
input
Generic Clock signal when output
Notes:
1. One signal can be mapped on several pins.
2. Each GCLK_IO[x] signal is connected to the related Generic Clock Generator x, for x in [7:0].
3. There is no GCLK_IO8 input or output for the Generic Clock Generator 8.
12.5
Peripheral Dependencies
Peripheral
GCLK
Base Address
0x40001C00
AHB CLK
APB CLK
Generic CLK
PAC
Events
DMA
Enabled at reset
Enabled at reset
Index
Index
Prot at reset
User
Generator
Index
-
Y
-
7
N
-
-
-
IRQ
Sleep Walking
-
12.6
Functional Description
12.6.1
Principle of Operation
-
The GCLK module is comprised of nine Generic Clock Generators (Generators) sourcing up to 34 Peripheral
Channels and the Main Clock signal GCLK_MAIN.
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PIC32CM MC00 Family
Generic Clock Controller (GCLK)
A clock source selected as input to a Generator can either be used directly, or it can be prescaled in the Generator.
A generator output is used by one or more Peripheral Channels to provide a peripheral generic clock signal
(GCLK_PERIPH) to the peripherals.
12.6.2
Basic Operation
12.6.2.1 Initialization
Before a Generator is enabled, the corresponding clock source should be enabled. The Peripheral clock must be
configured as outlined by the following steps:
1. The Generator must be enabled (GENCTRLn.GENEN=1) and the division factor must be set
(GENTRLn.DIVSEL and GENCTRLn.DIV) by performing a single 32-bit write to the Generator Control register
(GENCTRLn).
2. The Generic Clock for a peripheral must be configured by writing to the respective Peripheral Channel Control
register (PCHCTRLm). The Generator used as the source for the Peripheral Clock must be written to the
GEN bit field in the Peripheral Channel Control register (PCHCTRLm.GEN). Ensure the Peripheral Channel is
enabled (PCHCTRLm.CHEN=1) before configuring the associated peripheral.
Note: Each Generator n is configured by one dedicated register GENCTRLn. Each Peripheral Channel m is
configured by one dedicated register PCHCTRLm. Refer to the Table 12-9 for the mapping of a peripheral to index m.
12.6.2.2 Enabling, Disabling, and Resetting
The GCLK module has no enable/disable bit to enable or disable the whole module.
The GCLK is reset by setting the Software Reset bit in the Control A register (CTRLA.SWRST) to 1. All registers in
the GCLK will be reset to their initial state, except for Peripheral Channels and associated Generators that have their
Write Lock bit set to 1 (PCHCTRLm.WRTLOCK). For further details, refer to 12.6.2.10.4 Configuration Lock.
12.6.2.3 Generic Clock Generator
Each Generator (GCLK_GEN) can be set to run from one of nine different clock sources except GCLK_GEN[1],
which can be set to run from one of eight sources. GCLK_GEN[1] is the only Generator that can be selected as
source to others Generators.
Each generator GCLK_GEN[x] (except GCLK_GEN[8]) can be connected to one specific pin GCLK_IO[x]. A pin
GCLK_IO[x] can be set either to act as source to GCLK_GEN[x] or to output the clock signal generated by
GCLK_GEN[x].
The selected source can be divided. Each Generator can be enabled or disabled independently.
Each GCLK_GEN clock signal can then be used as clock source for Peripheral Channels. Each Generator output can
be allocated to one or more Peripherals.
GCLK_GEN[0] is used as GCLK_MAIN for the synchronous clock controller inside the 13. Main Clock (MCLK). Refer
to the Main Clock Controller description for details on the synchronous clock generation.
Figure 12-3. Generic Clock Generator
Clock Sources
GCLKGENSRC
Clock
Gate
GCLKGEN
DIVIDER
GCLK_IO
GENCTRL.GENEN
(Except for Generator 8)
GENCTRL.DIVSEL
GENCTRL.SRC
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PIC32CM MC00 Family
Generic Clock Controller (GCLK)
12.6.2.4 Enabling a Generator
A Generator is enabled by writing a '1' to the Generator Enable bit in the Generator Control register
(GENCTRLn.GENEN = 1).
12.6.2.5 Disabling a Generator
A Generator is disabled by writing a '0' to GENCTRLn.GENEN. When GENCTRLn.GENEN = 0, the GCLK_GEN[n]
clock is disabled and gated.
12.6.2.6 Selecting a Clock Source for the Generator
Each Generator can individually select a clock source by setting the Source Select bit group in the Generator Control
register (GENCTRLn.SRC).
Changing from one clock source, for example A, to another clock source, B, can be done on the fly: If clock source
B is not ready, the Generator will continue using clock source A. As soon as source B is ready, the Generator
will switch to it. During the switching operation, the Generator maintains clock requests to both clock sources A
and B, and will release source A as soon as the switch is done. The according bit in the SYNCBUSY register
(SYNCBUSY.GENCTRLn) will remain '1' until the switch operation is completed.
Before switching the Generic Clock Generator 0 (GCLKGEN0) from a clock source A to another clock source B,
enable the ONDEMAND feature of the clock source A to ensure a proper transition from clock source A to clock
source B.
Only Generator 1 can be used as a common source for all other generators.
12.6.2.7 Changing the Clock Frequency
The selected source for a Generator can be divided by writing a division value in the Division Factor bit field of the
Generator Control register (GENCTRLn.DIV). How the actual division factor is calculated is depending on the Divide
Selection bit (GENCTRLn.DIVSEL).
If GENCTRLn.DIVSEL= 0 and GENCTRLn.DIV is either 0 or 1, the output clock will be undivided.
Note: The number of available DIV bits may vary from Generator to Generator.
12.6.2.8 Duty Cycle
When dividing a clock with an odd division factor, the duty-cycle will not be 50/50. Setting the Improve Duty Cycle bit
of the Generator Control register (GENCTRLn.IDC) will result in a 50/50 duty cycle.
12.6.2.9 External Clock
The output clock (GCLK_GEN) of each Generator can be sent to I/O pins (GCLK_IO).
If the Output Enable bit in the Generator Control register is set (GENCTRLn.OE = 1) and the generator is enabled
(GENCTRLn.GENEN=1), the Generator requests its clock source and the GCLK_GEN clock is output to an I/O pin.
If GCLK_IO is selected as a generator source in the GENCTRLn.SRC bit field, the external clock will be used as
a source for GCLKn. When using an external GCLK_IO as a source for Generic Clock Generator 0 (GCLKGEN0),
ensure the external source has stabilized before assigning to the GCLKGEN0 and disabling the previous clock
source. The GCLK_IO does not have a status ready signal for an external input source. This can be achieved in
software by counting clock pulses for a known time period (eg: using RTC or FREQM).
Note: The I/O pin (GCLK/IO[n]) must first be configured as a GCLK output by writing the corresponding 27. I/O Pin
Controller (PORT) registers.
If GENCTRLn.OE is 0, the according I/O pin is set to an Output Off Value, which is selected by GENCTRLn.OOV: If
GENCTRLn.OOV is '0', the output clock will be low. If this bit is '1', the output clock will be high.
In Standby mode, if the clock is output (GENCTRLn.OE=1), the clock on the I/O pin is frozen to the OOV value if the
Run In Standby bit of the Generic Control register (GENCTRLn.RUNSTDBY) is zero. If GENCTRLn.RUNSTDBY is
'1', the GCLKGEN clock is kept running and output to the I/O pin.
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PIC32CM MC00 Family
Generic Clock Controller (GCLK)
12.6.2.10 Peripheral Clock
Figure 12-4. Peripheral Clock
GCLKGEN[0]
GCLKGEN[1]
GCLKGEN[2]
GCLKGEN[8]
Clock
Gate
GCLK_PERIPHm
PCHCTRLm.CHEN
PCHCTRLm.GEN
12.6.2.10.1 Enabling a Peripheral Clock
Before a Peripheral Clock is enabled, one of the Generators must be enabled (GENCTRLn.GENEN) and selected as
source for the Peripheral Channel by setting the Generator Selection bits in the Peripheral Channel Control register
(PCHCTRLm.GEN). Any available Generator can be selected as clock source for each Peripheral Channel. Refer to
Table 12-9 for the mapping of the peripheral to index m.)
When a Generator has been selected, the peripheral clock is enabled by setting the Channel Enable bit in the
Peripheral Channel Control register, PCHCTRLm.CHEN = 1. The PCHCTRLm.CHEN bit must be synchronized to
the generic clock domain. PCHCTRLm.CHEN will continue to read as its previous state until the synchronization is
complete.
12.6.2.10.2 Disabling a Peripheral Clock
A Peripheral Clock is disabled by writing PCHCTRLm.CHEN = 0. The PCHCTRLm.CHEN bit must be synchronized
to the Generic Clock domain. PCHCTRLm.CHEN will stay in its previous state until the synchronization is complete.
The Peripheral Clock is gated when disabled.
12.6.2.10.3 Selecting the Clock Source for a Peripheral
When changing a peripheral clock source by writing to PCHCTRLm.GEN, the peripheral clock must be disabled
before re-enabling it with the new clock source setting. The following actions prevent glitches during the transition:
1. Disable the Peripheral Channel by writing PCHCTRLm.CHEN = 0.
2. Assert that PCHCTRLm.CHEN reads '0'.
3. Change the source of the Peripheral Channel by writing PCHCTRLm.GEN.
4. Re-enable the Peripheral Channel by writing PCHCTRLm.CHEN = 1.
12.6.2.10.4 Configuration Lock
The peripheral clock configuration can be locked for further write accesses by setting the Write Lock bit in the
Peripheral Channel Control register PCHCTRLm.WRTLOCK = 1). After this, all writing to the PCHCTRLm register will
be ignored. It can only be unlocked by a Power Reset.
The Generator source of a locked Peripheral Channel will be locked, too: The corresponding GENCTRLn register is
locked, and can be unlocked only by a Power Reset.
This rule does not apply to Generator 0, as it is used as GCLK_MAIN, it cannot be locked. It is reset by any Reset
and will start up in a known configuration. The software reset (CTRLA.SWRST) can not unlock the registers.
In case of an external Reset, the Generator source will be disabled. Even if the WRTLOCK bit is written to '1' the
peripheral channels are disabled (PCHCTRLm.CHEN set to '0') until the Generator source is enabled again. Then,
the PCHCTRLm.CHEN are set to '1' again.
12.6.2.11 Additional Features
12.6.2.11.1 Peripheral Clock Enable after Reset
The Generic Clock Controller must be able to provide a generic clock to some specific peripherals after a Reset. That
means that the configuration of the Generators and Peripheral Channels after Reset is device-dependent.
Refer to GENCTRLn.SRC for details on GENCTRLn reset.
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PIC32CM MC00 Family
Generic Clock Controller (GCLK)
Refer to PCHCTRLm.SRC for details on PCHCTRLm reset.
12.6.2.12 Sleep Mode Operation
12.6.2.12.1 SleepWalking
The GCLK module supports the SleepWalking feature.
If the system is in a Sleep mode where the Generic Clocks are stopped, a peripheral that needs its clock in order to
execute a process must first request it from the Generic Clock Controller.
The Generic Clock Controller receives this request, determines which Generic Clock Generator is involved and which
clock source needs to be awakened. It then wakes up the respective clock source, enables the Generator and
Peripheral Channel stages successively, and delivers the clock to the peripheral.
The RUNSTDBY bit in the Generator Control register controls clock output to pin during Standby Sleep mode. If the
bit is cleared, the Generator output is not available on the pin. When set, the GCLK can continuously output the
generator output to the GCLK_IO[n] pin. Refer to 12.6.2.9 External Clock for details.
12.6.2.12.2 Minimize Power Consumption in Standby
The following table identifies when a Clock Generator is off in Standby mode, minimizing the power consumption:
Table 12-2. Clock Generator n Activity in Standby Mode
Request for Clock n present
GENCTRLn.RUNSTDBY
GENCTRLn.OE
Clock Generator n
yes
-
-
active
no
1
1
active
no
1
0
OFF
no
0
1
OFF
no
0
0
OFF
12.6.2.12.3 Entering Standby Mode
There may occur a delay when the device is put into Standby mode, before the power is turned off. This
delay is caused by running Clock Generators: if the Run in the Standby bit in the Generator Control register
(GENCTRLn.RUNSTDBY) is '0', GCLK must verify that the clock is turned off. The duration of this verification is
frequency-dependent.
12.6.2.13 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers must be
synchronized when written or read.
An exception is the Channel Enable bit in the Peripheral Channel Control registers (PCHCTRLm.CHEN). When
changing this bit, the bit value must be read-back to ensure the synchronization is complete and to assert glitch free
internal operation. Note that changing the bit value under ongoing synchronization will not generate an error.
Synchronization is denoted by the "Read-Synchronized" and "Write-Synchronized" property in each individual register
description.
For more details, refer to Register Synchronization.
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PIC32CM MC00 Family
Generic Clock Controller (GCLK)
12.7
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
...
0x03
CTRLA
7:0
SYNCBUSY
0x08
...
0x1F
Reserved
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
GENCTRL0
GENCTRL1
GENCTRL2
GENCTRL3
GENCTRL4
GENCTRL5
GENCTRL6
GENCTRL7
0x40
GENCTRL8
0x44
...
0x7F
Reserved
0x80
6
5
4
3
2
1
0
SWRST
Reserved
0x04
0x20
7
PCHCTRL0
7:0
15:8
23:16
31:24
GENCTRL5
GENCTRL4
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
WRTLOCK
GENCTRL3
GENCTRL2
GENCTRL1
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
CHEN
GENCTRL0
GENCTRL8
GENCTRL7
SWRST
GENCTRL6
SRC[4:0]
OOV
IDC
GENEN
SRC[4:0]
OOV
IDC
GENEN
SRC[4:0]
OOV
IDC
GENEN
SRC[4:0]
OOV
IDC
GENEN
SRC[4:0]
OOV
IDC
GENEN
SRC[4:0]
OOV
IDC
GENEN
SRC[4:0]
OOV
IDC
GENEN
SRC[4:0]
OOV
IDC
GENEN
SRC[4:0]
OOV
IDC
GENEN
GEN[3:0]
...
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 49
PIC32CM MC00 Family
Generic Clock Controller (GCLK)
...........continued
Offset
Name
Bit Pos.
7
6
CHEN
PCHCTRL34
7:0
15:8
23:16
31:24
WRTLOCK
0x0108
© 2021 Microchip Technology Inc.
and its subsidiaries
5
4
3
2
1
0
GEN[3:0]
Datasheet
DS60001638D-page 50
PIC32CM MC00 Family
Generic Clock Controller (GCLK)
12.7.1
Control A
Name:
Offset:
Reset:
Property:
Bit
CTRLA
0x00
0x00
PAC Write-Protection, Write-Synchronized Bits
7
6
5
4
3
Access
Reset
2
1
0
SWRST
R/W
0
Bit 0 – SWRST Software Reset
Writing a zero to this bit has no effect.
Setting this bit to ‘1’ will reset all registers in the GCLK to their initial state after a Power Reset, except for generic
clocks and associated Generators that have their WRTLOCK bit in PCHCTRLm set to ‘1’.
Refer to GENCTRL Reset Value for details on GENCTRLn register reset.
Refer to PCHCTRL Reset Value for details on PCHCTRLm register reset.
Note: CTRLA.SWRST is a write-synchronized bit: SYNCBUSY.SWRST must be checked to ensure the
CTRLA.SWRST synchronization is complete.
Value
0
1
Description
There is no Reset operation ongoing.
A Reset operation is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 51
PIC32CM MC00 Family
Generic Clock Controller (GCLK)
12.7.2
Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x04
0x00000000
–
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
GENCTRL8
R
0
9
GENCTRL7
R
0
8
GENCTRL6
R
0
7
GENCTRL5
R
0
6
GENCTRL4
R
0
5
GENCTRL3
R
0
4
GENCTRL2
R
0
3
GENCTRL1
R
0
2
GENCTRL0
R
0
1
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 2, 3, 4, 5, 6, 7, 8, 9, 10 – GENCTRLx Generator Control n Synchronization Busy [x = 8..0]
This bit is cleared when the synchronization of the Generator Control n register (GENCTRLn) between clock domains
is complete, or when clock switching operation is complete.
This bit is set when the synchronization of the Generator Control n register (GENCTRLn) between clock domains is
started.
Bit 0 – SWRST Software Reset Synchronization Busy
This bit is cleared when the synchronization of the CTRLA.SWRST register bit between clock domains is complete.
This bit is set when the synchronization of the CTRLA.SWRST register bit between clock domains is started.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 52
PIC32CM MC00 Family
Generic Clock Controller (GCLK)
12.7.3
Generator Control
Name:
Offset:
Reset:
Property:
GENCTRLn
0x20 + n*0x04 [n=0..8]
0x00000106 for GENCTRL0, 0x00000000 for others
-
GENCTRLn controls the settings of Generic Generator n (n=0..8). The reset value is 0x00000106 for Generator n=0,
else 0x00000000
Note: GENCTRLn is a write-synchronized register: SYNCBUSY.GENCTRLn must be checked to ensure the
GENCTRLn synchronization is complete.
Bit
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
DIV[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
DIV[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
RUNSTDBY
R/W
0
12
DIVSEL
R/W
0
11
OE
R/W
0
10
OOV
R/W
0
9
IDC
R/W
0
8
GENEN
R/W
x
7
6
5
4
3
1
0
R/W
0
R/W
0
2
SRC[4:0]
R/W
0
R/W
0
R/W
x
Access
Reset
Bit
Access
Reset
Bits 31:16 – DIV[15:0] Division Factor
These bits represent a division value for the corresponding Generator. The actual division factor used is dependent
on the state of DIVSEL. The number of relevant DIV bits for each Generator can be seen in this table. Written bits
outside of the specified range will be ignored.
Table 12-3. Division Factor Bits
Generic Clock Generator
Division Factor Bits
Generator 0
Generator 1
Generator 2-8
8 division factor bits - DIV[7:0]
16 division factor bits - DIV[15:0]
8 division factor bits - DIV[7:0]
Bit 13 – RUNSTDBY Run in Standby
This bit is used to keep the Generator running in Standby as long as it is configured to output to a dedicated
GCLK_IO pin. If GENCTRLn.OE is zero, this bit has no effect and the generator will only be running if a peripheral
requires the clock.
Value
Description
0
The Generator is stopped in Standby and the GCLK_IO pin state (one or zero) will be dependent on
the setting in GENCTRL.OOV.
1
The Generator is kept running and output to its dedicated GCLK_IO pin during Standby mode.
Bit 12 – DIVSEL Divide Selection
This bit determines how the division factor of the clock source of the Generator will be calculated from DIV. If the
clock source should not be divided, DIVSEL must be 0 and the GENCTRLn.DIV value must be either 0 or 1.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 53
PIC32CM MC00 Family
Generic Clock Controller (GCLK)
Value
0
1
Description
The Generator clock frequency equals the clock source frequency divided by GENCTRLn.DIV.
The Generator clock frequency equals the clock source frequency divided by 2^(GENCTRLn.DIV+1).
Bit 11 – OE Output Enable
This bit is used to output the Generator clock output to the corresponding pin (GCLK_IO), as long as GCLK_IO
is not defined as the Generator source in the GENCTRLn.SRC bit field. This feature only applies to GCLK Clock
Generators 0 to 7. (GCLK Generator 8 does not have a GCLK_IO pin)
Value
Description
0
No Generator clock signal on pin GCLK_IO.
1
The Generator clock signal is output on the corresponding GCLK_IO, unless GCLK_IO is selected as a
generator source in the GENCTRLn.SRC bit field.
Bit 10 – OOV Output Off Value
This bit is used to control the clock output value on pin (GCLK_IO) when the Generator is turned off or the OE bit is
zero, as long as GCLK_IO is not defined as the Generator source in the GENCTRLn.SRC bit field. This feature only
applies to GCLK Clock Generators 0 to 7. (GCLK Generator 8 does not have a GCLK_IO pin)
Value
Description
0
The GCLK_IO will be LOW when generator is turned off or when the OE bit is zero.
1
The GCLK_IO will be HIGH when generator is turned off or when the OE bit is zero.
Bit 9 – IDC Improve Duty Cycle
This bit is used to improve the duty cycle of the Generator output to 50/50 for odd division factors.
Value
Description
0
Generator output clock duty cycle is not balanced to 50/50 for odd division factors.
1
Generator output clock duty cycle is 50/50.
Bit 8 – GENEN Generator Enable
This bit is used to enable and disable the Generator.
Value
Description
0
Generator is disabled.
1
Generator is enabled.
Bits 4:0 – SRC[4:0] Generator Clock Source Selection
These bits select the Generator clock source, as shown in this table.
Table 12-4. Generator Clock Source Selection
Value
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8-0x1F
XOSC
GCLKIN
GCLKGEN1
OSCULP32K
OSC32K
XOSC32K
OSC48M
FDPLL96M
Reserved
XOSC oscillator output
Generator input pad (GCLK_IO)
Generic clock generator 1 output
OSCULP32K oscillator output
OSC32K oscillator output
XOSC32K oscillator output
OSC48M oscillator output
DPLL96M output
-
A Power Reset will reset all GENCTRLn registers. the Reset values of the GENCTRLn registers are shown in table
below.
Table 12-5. GENCTRLn Reset Value after a Power Reset
GCLK Generator
Reset Value after a Power Reset
0
others
0x00000106
0x00000000
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 54
PIC32CM MC00 Family
Generic Clock Controller (GCLK)
A User Reset will reset the associated GENCTRL register unless the Generator is the source of a locked Peripheral
Channel (PCHCTRLm.WRTLOCK=1). The reset values of the GENCTRL register are as shown in the table below.
Table 12-6. GENCTRLn Reset Value after a User Reset
GCLK Generator Reset Value after a User Reset
0
others
0x00000106
No change if the generator is used by a Peripheral Channel m with PCHCTRLm.WRTLOCK=1
else 0x00000000
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 55
PIC32CM MC00 Family
Generic Clock Controller (GCLK)
12.7.4
Peripheral Channel Control
Name:
Offset:
Reset:
Property:
PCHCTRLm
0x80 + m*0x04 [m=0..34]
0x00000000
PAC Write-Protection
PCHTRLm controls the settings of Peripheral Channel number m (m=0..34).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
WRTLOCK
R/W
0
6
CHEN
R/W
0
5
4
3
2
1
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
GEN[3:0]
R/W
0
R/W
0
Bit 7 – WRTLOCK Write Lock
After this bit is set to '1', further writes to the PCHCTRLm register will be discarded. The control register of the
corresponding Generator n (GENCTRLn), as assigned in PCHCTRLm.GEN, will also be locked. It can only be
unlocked by a Power Reset.
Note that Generator 0 cannot be locked.
Value
Description
0
The Peripheral Channel register and the associated Generator register are not locked
1
The Peripheral Channel register and the associated Generator register are locked
Bit 6 – CHEN Channel Enable
This bit is used to enable and disable a Peripheral Channel.
Value
Description
0
The Peripheral Channel is disabled
1
The Peripheral Channel is enabled
Bits 3:0 – GEN[3:0] Generator Selection
This bit field selects the Generator to be used as the source of a peripheral clock, as shown in the table below:
Table 12-7. Generator Selection
Value
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
Generic Clock Generator 0
Generic Clock Generator 1
Generic Clock Generator 2
Generic Clock Generator 3
Generic Clock Generator 4
Generic Clock Generator 5
Generic Clock Generator 6
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 56
PIC32CM MC00 Family
Generic Clock Controller (GCLK)
...........continued
Value
Description
0x7
0x8
0x9 - 0xF
Generic Clock Generator 7
Generic Clock Generator 8
Reserved
Table 12-8. Reset Value after a User Reset or a Power Reset
Reset
PCHCTRLm.GEN
PCHCTRLm.CHEN
PCHCTRLm.WRTLOCK
Power Reset
User Reset
0x0
If WRTLOCK = 0
: 0x0
0x0
If WRTLOCK = 0
: 0x0
0x0
No change
If WRTLOCK = 1: no change
If WRTLOCK = 1: no change
A Power Reset will reset all the PCHCTRLm registers.
A User Reset will reset a PCHCTRL if WRTLOCK=0, or else, the content of that PCHCTRL remains unchanged.
PCHCTRL register Reset values are shown in the table PCHCTRLm Mapping.
Table 12-9. PCHCTRLm Mapping
index(m)
Name
Description
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GCLK_DPLL
GCLK_DPLL_32K
GCLK_EIC
GCLK_FREQM_MSR
GCLK_FREQM_REF
GCLK_TSENS
GCLK_EVSYS_CHANNEL_0
GCLK_EVSYS_CHANNEL_1
GCLK_EVSYS_CHANNEL_2
GCLK_EVSYS_CHANNEL_3
GCLK_EVSYS_CHANNEL_4
GCLK_EVSYS_CHANNEL_5
GCLK_EVSYS_CHANNEL_6
GCLK_EVSYS_CHANNEL_7
GCLK_EVSYS_CHANNEL_8
GCLK_EVSYS_CHANNEL_9
GCLK_EVSYS_CHANNEL_10
GCLK_EVSYS_CHANNEL_11
GCLK_SERCOM[0:3]_SLOW
GCLK_SERCOM0_CORE
GCLK_SERCOM1_CORE
GCLK_SERCOM2_CORE
GCLK_SERCOM3_CORE
GCLK_TCC0, GCLK_TCC1
GCLK_TCC2
GCLK_TC0, GCLK_TC1
GCLK_TC2, GCLK_TC3
GCLK_TC4
GCLK_ADC0
GCLK_ADC1
GCLK_SDADC
GCLK_DAC
GCLK_CCL
GCLK_AC
GCLK_PDEC
FDPLL96M input clock source for reference
FDPLL96M 32kHz clock for FDPLL96M internal lock timer
EIC
FREQM Measure
FREQM Reference
TSENS
EVSYS_CHANNEL_0
EVSYS_CHANNEL_1
EVSYS_CHANNEL_2
EVSYS_CHANNEL_3
EVSYS_CHANNEL_4
EVSYS_CHANNEL_5
EVSYS_CHANNEL_6
EVSYS_CHANNEL_7
EVSYS_CHANNEL_8
EVSYS_CHANNEL_9
EVSYS_CHANNEL_10
EVSYS_CHANNEL_11
SERCOM[0:3]_SLOW
SERCOM0_CORE
SERCOM1_CORE
SERCOM2_CORE
SERCOM3_CORE
TCC0,TCC1
TCC2
TC0,TC1
TC2,TC3
TC4
ADC0
ADC1
SDADC
DAC
CCL
AC
PDEC
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 57
PIC32CM MC00 Family
Main Clock (MCLK)
13.
Main Clock (MCLK)
13.1
Overview
The Main Clock (MCLK) controls the synchronous clock generation of the device.
Using a clock provided by the Generic Clock Module (GCLK_MAIN), the Main Clock Controller provides synchronous
system clocks to the CPU and the modules connected to the AHBx and the APBx buses. The synchronous system
clocks are divided into a number of clock domains. Each clock domain can run at different frequencies, enabling
the user to save power by running peripherals at a relatively low clock frequency, while maintaining high CPU
performance or vice versa. In addition, the clock can be masked for individual modules, enabling the user to minimize
power consumption.
13.2
Features
•
•
•
13.3
Generates CPU, AHB, and APB system clocks
– Clock source and division factor from GCLK
– Clock prescaler with 1x to 128x division
Safe run-time clock switching from GCLK
Module-level clock gating through maskable peripheral clocks
Block Diagram
Figure 13-1. MCLK Block Diagram
CLK_APBx
GCLK
GCLK_MAIN
CLK_AHBx
MAIN
CLOCK CONTROLLER
PERIPHERALS
CLK_CPU
CPU
13.4
Peripheral Dependencies
Peripheral
MCLK
Base Address
AHB CLK
APB CLK
Generic CLK
PAC
Events
DMA
Enabled at reset
Enabled at reset
Index
Index
Prot at reset
User
Generator
Index
-
Y
-
2
N
-
-
-
IRQ
0x40000800
0
Sleep Walking
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
Y
DS60001638D-page 58
PIC32CM MC00 Family
Main Clock (MCLK)
13.5
13.5.1
Functional Description
Principle of Operation
The GCLK_MAIN clock signal from the GCLK module is the source for the main clock, which in turn is the common
root for the synchronous clocks for the CPU, APBx, and AHBx modules. The GCLK_MAIN is divided by an 8-bit
prescaler. Each of the derived clocks can run from any divided or undivided main clock, ensuring synchronous clock
sources for each clock domain. The clock domain (CPU) can be changed on the fly to respond to variable load in the
application. The clocks for each module in a clock domain can be masked individually to avoid power consumption in
inactive modules. Depending on the Sleep mode, some clock domains can be turned off.
13.5.2
Basic Operation
13.5.2.1 Initialization
After a Reset, the default clock source of the GCLK_MAIN clock is started and calibrated before the CPU starts
running. The GCLK_MAIN clock is selected as the main clock without any prescaler division.
By default, only the necessary clocks are enabled.
13.5.2.2 Enabling, Disabling, and Resetting
The MCLK module is always enabled and cannot be reset.
13.5.2.3 Selecting the Main Clock Source
Refer to the Generic Clock Controller description for details on how to configure the clock source of the GCLK_MAIN
clock.
13.5.2.4 Selecting the Synchronous Clock Division Ratio
The main clock GCLK_MAIN feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By
default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU
clock domain by writing the Division (DIV) bits in the CPU Clock Division register CPUDIV, resulting in a CPU clock
domain frequency determined by this equation:
fCPU =
fmain
CPUDIV
If the application attempts to write forbidden values in the CPUDIV register, the register is written but these bad
values are not used and a violation is reported to the PAC module.
Division bits (DIV) can be written without halting or disabling peripheral modules. Writing DIV bits allows a new clock
setting to be written to all synchronous clocks belonging to the corresponding clock domain at the same time.
Figure 13-2. Synchronous Clock Selection and Prescaler
Sleep Controller
Sleep mode
MASK
Clock
gate
CLK_APB_HS
Clock
gate
clk_apb_ipn
clk_apb_ip1
clk_apb_ip0
gate
Clock
gate
Clock
Clock
gate
clk_ahb_ipn
clk_ahb_ip1
clk_ahb_ip0
MASK
GCLKMAIN
GCLK
Prescaler
Clock
gate
CLK_AHB_HS
Clock
gate
CLK_CPU
CPU
Clock Domain: fCPU
PERIPHERALS
CPU
CPUDIV
13.5.2.5 Clock Ready Flag
There is a slight delay between writing to CPUDIV until the new clock settings become effective.
During this interval, the Clock Ready flag in the Interrupt Flag Status and Clear register (INTFLAG.CKRDY) will return
zero when read. If CKRDY in the INTENSET register is set to '1', the Clock Ready interrupt will be triggered when the
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Datasheet
DS60001638D-page 59
PIC32CM MC00 Family
Main Clock (MCLK)
new clock setting is effective. The clock settings (CLKCFG) must not be re-written while INTFLAG.CKRDY reads '0'.
The system may become unstable or hang, and a violation is reported to the PAC module.
13.5.2.6 Peripheral Clock Masking
It is possible to disable/enable the AHB or APB clock for a peripheral by writing the corresponding bit in the Clock
Mask registers (AHBMASK and APBxMASK) to '0'/'1'. The default state of the peripheral clocks is given by the
peripheral bit reset value in AHBMASK and APBxMASK registers.
When the APB clock is not provided to a module, its registers cannot be read or written. The module can be
re-enabled later by writing the corresponding mask bit to '1'.
A module may be connected to several clock domains (for instance, AHB and APB), in which case it will have several
mask bits.
Clocks must be switched off only if it is certain that the module will not be used: Switching off the clock for the NVM
Controller (NVMCTRL) will cause a problem if the CPU needs to read from the Flash memory. Switching off the clock
to the MCLK module (which contains the mask registers) or the corresponding APBx bridge, will make it impossible to
write the mask registers again. In this case, they can only be re-enabled by a system reset.
13.5.3
Interrupts
The peripheral has the following interrupt sources:
•
Clock Ready (CKRDY): indicates that CPU clocks are ready. This interrupt is a synchronous wake-up source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(13.6.3 INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be enabled individually by
writing a '1' to the corresponding enabling bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing
a '1' to the corresponding clearing bit in the Interrupt Enable Clear (INTENCLR) register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the peripheral is reset.
An interrupt flag is cleared by writing a '1' to the corresponding bit in the 13.6.3 INTFLAG register. Each peripheral
can have one interrupt request line per interrupt source or one common interrupt request line for all the interrupt
sources. If the peripheral has one common interrupt request line for all the interrupt sources, the user must read the
13.6.3 INTFLAG register to determine which interrupt condition is present.
13.5.4
Sleep Mode Operation
In Idle Sleep mode, the MCLK is still running on the selected main clock.
In Standby Sleep mode, the MCLK is frozen if no synchronous clock is required.
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Datasheet
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PIC32CM MC00 Family
Main Clock (MCLK)
13.6
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
...
0x0F
Reserved
INTENCLR
INTENSET
INTFLAG
CPUDIV
7:0
7:0
7:0
7:0
0x10
0x14
0x18
0x1C
7
6
5
4
3
2
1
0
CKRDY
CKRDY
CKRDY
CPUDIV[7:0]
Reserved
AHBMASK
APBAMASK
APBBMASK
APBCMASK
7:0
15:8
23:16
31:24
DMAC
HSRAM
NVMCTRL
HMATRIXHS
DSU
APBC
DIVAS
APBB
APBA
PAC
7:0
GCLK
SUPC
OSC32KCTR
L
OSCCTRL
RSTC
MCLK
PM
PAC
TSENS
FREQM
EIC
RTC
WDT
NVMCTRL
DSU
PORT
SERCOM1
TCC1
ADC1
PDEC
SERCOM0
TCC0
ADC0
EVSYS
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
HMATRIXHS
TC3
CCL
© 2021 Microchip Technology Inc.
and its subsidiaries
TC2
TC1
DAC
SERCOM3
TC0
AC
Datasheet
SERCOM2
TCC2
SDADC
TC4
DS60001638D-page 61
PIC32CM MC00 Family
Main Clock (MCLK)
13.6.1
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x01
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
7
6
5
4
3
Access
Reset
2
1
0
CKRDY
R/W
0
Bit 0 – CKRDY Clock Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Clock Ready Interrupt Enable bit and the corresponding interrupt request.
Value
Description
0
The Clock Ready interrupt is enabled and will generate an interrupt request when the Clock Ready
Interrupt Flag is set.
1
The Clock Ready interrupt is disabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 62
PIC32CM MC00 Family
Main Clock (MCLK)
13.6.2
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x02
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
7
6
5
4
3
2
1
0
CKRDY
R/W
0
Access
Reset
Bit 0 – CKRDY Clock Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Clock Ready Interrupt Enable bit and enable the Clock Ready interrupt.
Value
Description
0
The Clock Ready interrupt is disabled.
1
The Clock Ready interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 63
PIC32CM MC00 Family
Main Clock (MCLK)
13.6.3
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
INTFLAG
0x03
0x01
–
7
6
5
4
3
Access
Reset
2
1
0
CKRDY
R/W
1
Bit 0 – CKRDY Clock Ready
This flag is set when the synchronous CPU, APBx, and AHBx clocks have frequencies as indicated in the CLKCFG
registers and will generate an interrupt if INTENCLR/SET.CKRDY is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Clock Ready interrupt flag.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 64
PIC32CM MC00 Family
Main Clock (MCLK)
13.6.4
CPU Clock Division
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
CPUDIV
0x04
0x01
PAC Write-Protection
7
6
5
R/W
0
R/W
0
R/W
0
4
3
CPUDIV[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
1
Bits 7:0 – CPUDIV[7:0] CPU Clock Division Factor
These bits define the division ratio of the main clock prescaler related to the CPU clock domain.
Frequencies must never exceed the specified maximum frequency for each clock domain.
Value
Name
Description
0x01
DIV1
Divide by 1
0x02
DIV2
Divide by 2
0x04
DIV4
Divide by 4
0x08
DIV8
Divide by 8
0x10
DIV16
Divide by 16
0x20
DIV32
Divide by 32
0x40
DIV64
Divide by 64
0x80
DIV128
Divide by 128
others
Reserved
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 65
PIC32CM MC00 Family
Main Clock (MCLK)
13.6.5
AHB Mask
Name:
Offset:
Reset:
Property:
Bit
AHBMASK
0x10
0x0000005FF
PAC Write-Protection
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
DIVAS
R/W
1
9
8
PAC
R/W
1
7
DMAC
R/W
1
6
HSRAM
R/W
1
5
NVMCTRL
R/W
1
4
HMATRIXHS
R/W
1
3
DSU
R/W
1
2
APBC
R/W
1
1
APBB
R/W
1
0
APBA
R/W
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 10 – DIVAS DIVAS AHB Clock Enable
Value
Description
0
The AHB clock for the DIVAS is stopped.
1
The AHB clock for the DIVAS is enabled.
Bit 8 – PAC PAC AHB Clock Enable
Value
Description
0
The AHB clock for the PAC is stopped.
1
The AHB clock for the PAC is enabled.
Bit 7 – DMAC DMAC AHB Clock Enable
Value
Description
0
The AHB clock for the DMAC is stopped.
1
The AHB clock for the DMAC is enabled.
Bit 6 – HSRAM HSRAM AHB Clock Enable
Value
Description
0
The AHB clock for the HSRAM is stopped.
1
The AHB clock for the HSRAM is enabled.
Bit 5 – NVMCTRL NVMCTRL AHB Clock Enable
Value
Description
0
The AHB clock for the NVMCTRL is stopped.
1
The AHB clock for the NVMCTRL is enabled.
Bit 4 – HMATRIXHS HMATRIXHS AHB Clock Enable
Value
Description
0
The AHB clock for the HMATRIXHS is stopped.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 66
PIC32CM MC00 Family
Main Clock (MCLK)
Value
1
Description
The AHB clock for the HMATRIXHS is enabled.
Bit 3 – DSU DSU AHB Clock Enable
Value
Description
0
The AHB clock for the DSU is stopped.
1
The AHB clock for the DSU is enabled.
Bit 2 – APBC APBC AHB Clock Enable
Value
Description
0
The AHB clock for the APBC is stopped.
1
The AHB clock for the APBC is enabled
Bit 1 – APBB APBB AHB Clock Enable
Value
Description
0
The AHB clock for the APBB is stopped.
1
The AHB clock for the APBB is enabled.
Bit 0 – APBA APBA AHB Clock Enable
Value
Description
0
The AHB clock for the APBA is stopped.
1
The AHB clock for the APBA is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 67
PIC32CM MC00 Family
Main Clock (MCLK)
13.6.6
APBA Mask
Name:
Offset:
Reset:
Property:
Bit
APBAMASK
0x14
0x00000FFF
PAC Write-Protection
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
TSENS
R/W
0
11
FREQM
R/W
1
10
EIC
R/W
1
9
RTC
R/W
1
8
WDT
R/W
1
7
GCLK
R/W
1
6
SUPC
R/W
1
5
OSC32KCTRL
R/W
1
4
OSCCTRL
R/W
1
3
RSTC
R/W
1
2
MCLK
R/W
1
1
PM
R/W
1
0
PAC
R/W
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 12 – TSENS TSENS APBA Clock Enable
Value
Description
0
The APBA clock for the TSENS is disabled.
1
The APBA clock for the TSENS is enabled.
Bit 11 – FREQM FREQM APBA Clock Enable
Value
Description
0
The APBA clock for the FREQM is disabled.
1
The APBA clock for the FREQM is enabled.
Bit 10 – EIC EIC APBA Clock Enable
Value
Description
0
The APBA clock for the EIC is disabled.
1
The APBA clock for the EIC is enabled.
Bit 9 – RTC RTC APBA Clock Enable
Value
Description
0
The APBA clock for the RTC is disabled.
1
The APBA clock for the RTC is enabled.
Bit 8 – WDT WDT APBA Clock Enable
Value
Description
0
The APBA clock for the WDT is disabled.
1
The APBA clock for the WDT is enabled.
Bit 7 – GCLK GCLK APBA Clock Enable
Value
Description
0
The APBA clock for the GCLK is disabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 68
PIC32CM MC00 Family
Main Clock (MCLK)
Value
1
Description
The APBA clock for the GCLK is enabled.
Bit 6 – SUPC SUPC APBA Clock Enable
Value
Description
0
The APBA clock for the SUPC is disabled.
1
The APBA clock for the SUPC is enabled.
Bit 5 – OSC32KCTRL OSC32KCTRL APBA Clock Enable
Value
Description
0
The APBA clock for the OSC32KCTRL is disabled.
1
The APBA clock for the OSC32KCTRL is enabled.
Bit 4 – OSCCTRL OSCCTRL APBA Clock Enable
Value
Description
0
The APBA clock for the OSCCTRL is disabled.
1
The APBA clock for the OSCCTRL is enabled.
Bit 3 – RSTC RSTC APBA Clock Enable
Value
Description
0
The APBA clock for the RSTC is disabled.
1
The APBA clock for the RSTC is enabled.
Bit 2 – MCLK MCLK APBA Clock Enable
Value
Description
0
The APBA clock for the MCLK is disabled.
1
The APBA clock for the MCLK is enabled.
Bit 1 – PM PM APBA Clock Enable
Value
Description
0
The APBA clock for the PM is disabled.
1
The APBA clock for the PM is enabled.
Bit 0 – PAC PAC APBA Clock Enable
Value
Description
0
The APBA clock for the PAC is disabled.
1
The APBA clock for the PAC is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 69
PIC32CM MC00 Family
Main Clock (MCLK)
13.6.7
APBB Mask
Name:
Offset:
Reset:
Property:
Bit
APBBMASK
0x18
0x00000007
PAC Write-Protection
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
HMATRIXHS
R/W
0
4
3
2
NVMCTRL
R/W
1
1
DSU
R/W
1
0
PORT
R/W
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 5 – HMATRIXHS HMATRIXHS APBB Clock Enable
Value
Description
0
The APBB clock for the HMATRIXHS is stopped
1
The APBB clock for the HMATRIXHS is enabled
Bit 2 – NVMCTRL NVMCTRL APBB Clock Enable
Value
Description
0
The APBB clock for the NVMCTRL is stopped
1
The APBB clock for the NVMCTRL is enabled
Bit 1 – DSU DSU APBB Clock Enable
Value
Description
0
The APBB clock for the DSU is stopped
1
The APBB clock for the DSU is enabled
Bit 0 – PORT PORT APBB Clock Enable
Value
Description
0
The APBB clock for the PORT is stopped.
1
The APBB clock for the PORT is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 70
PIC32CM MC00 Family
Main Clock (MCLK)
13.6.8
APBC Mask
Name:
Offset:
Reset:
Property:
Bit
APBCMASK
0x1C
0x00000000
PAC Write-Protection
31
30
29
28
27
26
PDEC
R/W
0
25
24
23
CCL
R/W
0
22
21
DAC
R/W
0
20
AC
R/W
0
19
SDADC
R/W
0
18
ADC1
R/W
0
17
ADC0
R/W
0
16
TC4
R/W
0
15
TC3
R/W
0
14
TC2
R/W
0
13
TC1
R/W
0
12
TC0
R/W
0
11
TCC2
R/W
0
10
TCC1
R/W
0
9
TCC0
R/W
0
8
7
6
5
4
SERCOM3
R/W
0
3
SERCOM2
R/W
0
2
SERCOM1
R/W
0
1
SERCOM0
R/W
0
0
EVSYS
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 26 – PDEC PDEC APBC Clock Enable
Value
Description
0
The APBC clock for the PDEC is stopped.
1
The APBC clock for the PDEC is enabled.
Bit 23 – CCL CCL APBC Clock Enable
Value
Description
0
The APBC clock for the CCL is stopped.
1
The APBC clock for the CCL is enabled.
Bit 21 – DAC DAC APBC Mask Clock Enable
Value
Description
0
The APBC clock for the DAC is stopped.
1
The APBC clock for the DAC is enabled.
Bit 20 – AC AC APBC Mask Clock Enable
Value
Description
0
The APBC clock for the AC is stopped.
1
The APBC clock for the AC is enabled.
Bit 19 – SDADC SDADC APBC Clock Enable
Value
Description
0
The APBC clock for the SDADC is stopped.
1
The APBC clock for the SDADC is enabled.
Bit 18 – ADC1 ADC1 APBC Clock Enable
Value
Description
0
The APBC clock for the ADC1 is stopped.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 71
PIC32CM MC00 Family
Main Clock (MCLK)
Value
1
Description
The APBC clock for the ADC1 is enabled.
Bit 17 – ADC0 ADC0 APBC Clock Enable
Value
Description
0
The APBC clock for the ADC0 is stopped.
1
The APBC clock for the ADC0 is enabled.
Bit 16 – TC4 TC4 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TC4 is stopped.
1
The APBC clock for the TC4 is enabled.
Bit 15 – TC3 TC3 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TC3 is stopped.
1
The APBC clock for the TC3 is enabled.
Bit 14 – TC2 TC2 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TC2 is stopped.
1
The APBC clock for the TC2 is enabled.
Bit 13 – TC1 TC1 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TC1 is stopped.
1
The APBC clock for the TC1 is enabled.
Bit 12 – TC0 TC0 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TC0 is stopped.
1
The APBC clock for the TC0 is enabled.
Bit 11 – TCC2 TCC2 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TCC2 is stopped.
1
The APBC clock for the TCC2 is enabled.
Bit 10 – TCC1 TCC1 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TCC1 is stopped.
1
The APBC clock for the TCC1 is enabled.
Bit 9 – TCC0 TCC0 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TCC0 is stopped.
1
The APBC clock for the TCC0 is enabled.
Bit 4 – SERCOM3 SERCOM3 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the SERCOM3 is stopped.
1
The APBC clock for the SERCOM3 is enabled.
Bit 3 – SERCOM2 SERCOM2 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the SERCOM2 is stopped.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 72
PIC32CM MC00 Family
Main Clock (MCLK)
Value
1
Description
The APBC clock for the SERCOM2 is enabled.
Bit 2 – SERCOM1 SERCOM1 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the SERCOM1 is stopped.
1
The APBC clock for the SERCOM1 is enabled.
Bit 1 – SERCOM0 SERCOM0 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the SERCOM0 is stopped.
1
The APBC clock for the SERCOM0 is enabled.
Bit 0 – EVSYS EVSYS APBC Clock Enable
Value
Description
0
The APBC clock for the EVSYS is stopped.
1
The APBC clock for the EVSYS is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 73
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.
Oscillators Controller (OSCCTRL)
14.1
Overview
The Oscillators Controller (OSCCTRL) provides a user interface to the XOSC, OSC48M and FDPLL96M modules,
refer to the OSC32KCTRL chapter for the user interface to the 32.768 kHz oscillators.
Through the interface registers, it is possible to enable, disable, calibrate, and monitor the OSCCTRL oscillators.
All oscillators statuses are collected in the Status register (STATUS). They can additionally trigger interrupts upon
status changes through the INTENSET, INTENCLR, and INTFLAG registers.
14.2
Features
•
•
•
14.3
0.4-32 MHz Crystal Oscillator (XOSC)
– Tunable gain control
– Programmable start-up time
– Crystal or external input clock on XIN I/O
– Clock failure detection with safe clock switch
– Clock failure event output
48 MHz Internal Oscillator (OSC48M)
– Fast start-up
– Programmable start-up time
– 4-bit linear divider available
Fractional Digital Phase Locked Loop (FDPLL96M)
– 48 MHz to 96 MHz output frequency
– 32 kHz to 2 MHz reference clock
– A selection of sources for the reference clock
– Adjustable proportional integral controller
– Fractional part used to achieve 1/16th of reference clock step
Block Diagram
Figure 14-1. OSCCTRL Block Diagram
XOUT
XIN
OSCCTRL
CFD
XOSC
OSCILLATORS
CONTROL
OSC48M
FDPLL96M
CFD Event
CLK_XOSC
CLK_OSC48M
CLK_DPLL
STATUS
register
INTERRUPTS
GENERATOR
© 2021 Microchip Technology Inc.
and its subsidiaries
Interrupts
Datasheet
DS60001638D-page 74
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.4
Signal Description
Signal
Description
Type
XIN
Multipurpose Crystal Oscillator or external clock generator input
Analog input
XOUT
Multipurpose Crystal Oscillator output
Analog output
The I/O lines are automatically selected when XOSC is enabled.
14.5
Peripheral Dependencies
AHB CLK
APB CLK
Generic CLK
PAC
Events
DMA
Peripheral Base Address IRQ
Sleep Walking
Enabled at reset Enabled at reset
OSCCTRL
0x40001000
0
-
Y
Index
0: FDPLL96M clk
source
Index Prot at reset User Generator Index
4
N
-
-
-
Y
1: FDPLL96M 32kHz
14.6
14.6.1
Functional Description
Principle of Operation
The XOSC, OSC48M, and FDPLL96M are configured through the OSCCTRL Control registers. Through this
interface these oscillators are enabled, disabled, or have their calibration values updated.
The Status register gathers different status signals coming from the oscillators controlled by the OSCCTRL. These
status signals can be used to generate system interrupts, and in some cases wake the system from Sleep mode,
provided the corresponding interrupt is enabled.
14.6.2
External Multipurpose Crystal Oscillator (XOSC) Operation
The XOSC can operate in the following different modes:
•
•
External clock, with an external clock signal connected to the XIN pin
Crystal oscillator, with an external 0.4-32MHz crystal connected to the XIN and XOUT pins
The XOSC can be used as a clock source for generic clock generators. This is configured by the Generic Clock
Controller (GCLK).
At reset, the XOSC is disabled, and the XIN/XOUT pins can be used as General Purpose I/O (GPIO) pins or by other
peripherals in the system. When XOSC is enabled, the operating mode determines the GPIO usage. When in crystal
oscillator mode, the XIN and XOUT pins are controlled by the OSCCTRL, and GPIO functions are overridden on both
pins. When in external clock mode, only the XIN pin will be overridden and controlled by the OSCCTRL, while the
XOUT pin can still be used as a GPIO pin.
The XOSC is enabled by writing a '1' to the Enable bit in the External Multipurpose Crystal Oscillator Control register
(XOSCCTRL.ENABLE). The XOSC is disabled by clearing the Enable bit. When disabling the XOSC it is important
only to write the Enable bit to '0' before additional changes are made to the XOSC register.
To enable XOSC as an external crystal oscillator, the XTAL Enable bit (XOSCCTRL.XTALEN) must be written to '1'. If
XOSCCTRL.XTALEN is zero, the external clock input on XIN will be enabled.
When in crystal oscillator mode (XOSCCTRL.XTALEN = 1), the External Multipurpose Crystal Oscillator Gain
(XOSCCTRL.GAIN) must be set to match the external crystal oscillator frequency. If the External Multipurpose
Crystal Oscillator Automatic Amplitude Gain Control (XOSCCTRL.AMPGC) is '1', the oscillator amplitude will be
automatically adjusted, and in most cases result in a lower power consumption. Setting the XOSCCTRL.AMPGC still
requires the proper gain setting (XOSCCTRL.GAIN) for the external crystal.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 75
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
The XOSC will behave differently in different sleep modes, based on the settings of XOSCCTRL.RUNSTDBY,
XOSCCTRL.ONDEMAND, and XOSCCTRL.ENABLE. If XOSCCTRL.ENABLE = 0, the XOSC will be always
stopped. For XOSCCTRL.ENABLE = 1, this table is valid:
Table 14-1. XOSC Sleep Behavior
CPU Mode
XOSCCTRL.RUNSTDB
Y
XOSCCTRL.ONDEMA
ND
Sleep Behavior
Active or Idle
-
0
Always run
Active or Idle
-
1
Run if requested by peripheral
Standby
1
0
Always run
Standby
1
1
Run if requested by peripheral
Standby
0
-
Run if requested by peripheral
After a hard reset, or when waking up from a Sleep mode where the XOSC was disabled, the XOSC will need
time to stabilize on the correct frequency, depending on the external crystal specification. This start-up time can be
configured by changing the Oscillator Start-Up Time bit group (XOSCCTRL.STARTUP) in the External Multipurpose
Crystal Oscillator Control register. During the start-up time, the oscillator output is masked to ensure that no unstable
clock propagates to the digital logic.
The External Multipurpose Crystal Oscillator Ready bit in the Status register (STATUS.XOSCRDY) is set once the
external clock or crystal oscillator is stable and ready to be used as a clock source. An interrupt is generated on a
zero-to-one transition on STATUS.XOSCRDY if the External Multipurpose Crystal Oscillator Ready bit in the Interrupt
Enable Set register (INTENSET.XOSCRDY) is set.
14.6.3
Clock Failure Detection Operation
The Clock Failure Detector (CFD) allows the user to monitor the external clock or crystal oscillator signal provided
by the external oscillator (XOSC). The CFD detects failing operation of the XOSC clock with reduced latency, and
supports switching to a safe clock source in case of clock failure. The user can also switch from the safe clock back
to XOSC in case of recovery. The safe clock is derived from the OSC48M oscillator with a configurable prescaler.
This allows configuring the safe clock in order to fulfill the operative conditions of the microcontroller.
In sleep modes, CFD operation is automatically disabled when the external oscillator is not requested to run by a
peripheral. See the Sleep Behavior table above when this is the case.
The user interface registers allow to enable, disable, and configure the CFD. The Status register provides status
flags on failure and clock switch conditions. The CFD can optionally trigger an interrupt or an event when a failure is
detected.
Clock Failure Detection
The CFD is disabled at reset. The CFD does not monitor the XOSC clock when the oscillator is disabled
(XOSCCTRL.ENABLE = 0).
Before starting CFD operation, the user must start and enable the safe clock source (OSC48M oscillator).
CFD operation is started by writing a '1' to the CFD Enable bit in the External Oscillator Control register
(XOSCCTRL.CFDEN). After starting or restarting the XOSC, the CFD does not detect failure until the start-up time
has elapsed. The start-up time is configured by the Oscillator Start-Up Time in the External Multipurpose Crystal
Oscillator Control register (XOSCCTRL.STARTUP). Once the XOSC Start-Up Time is elapsed, the XOSC clock is
constantly monitored.
During a period of 4 safe clocks (monitor period), the CFD watches for a clock activity from the XOSC. There must
be at least one rising and one falling XOSC clock edge during 4 safe clock periods to meet non-failure conditions.
If no or insufficient activity is detected, the failure status is asserted: The Clock Failure Detector status bit in the
Status register (STATUS.XOSCFAIL) and the Clock Failure Detector interrupt flag bit in the Interrupt Flag register
(INTFLAG.XOSCFAIL) are set. If the XOSCFAIL bit in the Interrupt Enable Set register (INTENSET.XOSCFAIL) is
set, an interrupt is generated. If the Event Output enable bit in the Event Control register (EVCTRL.CFDEO) is set, an
output event is generated.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
After a clock failure is issued the monitoring of the XOSC clock continues, and the Clock Failure Detector
status bit in the Status register (STATUS.XOSCFAIL) reflects the current XOSC activity. If the CFD is disabled
(XOSCCTRL.CFDEN=0) the XOSC must be disabled (XOSCCTRL.ENABLE=0) before re-enabling the CFD. Not
following this guideline can lead to a false clock failure detection.
When the XOSC Clock Failure Detector is enabled (XOSCCTRL.CFDEN=1) and a failure is detected
(STATUS.XOSCFAIL=1), the XOSC ready bit is not cleared (STATUS.XOSCRDY=1). When checking the XOSC
ready status, the state of the XOSC clock failure status (STATUS.XOSCFAIL) must be checked before the XOSC
ready status bit and dismiss the XOSC ready status if the XOSC clock failure status is set (STATUS.XOSCFAIL=1).
Clock Switch
When a clock failure is detected, the XOSC clock is replaced by the safe clock in order to maintain an active
clock during the XOSC clock failure. The safe clock source is the OSC48M oscillator clock. The safe clock source
frequency can be scaled down by a configurable prescaler to ensure that the safe clock frequency does not exceed
the operating conditions selected by the application. When the XOSC clock is switched to the safe clock, the Clock
Switch bit in the Status register (STATUS.XOSCCKSW) is set.
When the CFD has switched to the safe clock, the XOSC is not disabled. If desired, the application must take the
necessary actions to disable the oscillator. The application must also take the necessary actions to configure the
system clocks to continue normal operations.
In case the application can recover the XOSC, the application can switch back to the XOSC clock by writing a '1' to
Switch Back Enable bit in the Clock Failure Control register (XOSCCTRL.SWBEN). Once the XOSC clock is switched
back, the Switch Back bit (XOSCCTRL.SWBEN) is cleared by hardware.
Prescaler
The CFD has an internal configurable prescaler to generate the safe clock from the OSC48M oscillator. The prescaler
size allows to scale down the OSC48M oscillator so the safe clock frequency is not higher than the XOSC clock
frequency monitored by the CFD. The division factor is 2^P, with P being the value of the CFD Prescaler bits in the
CFD Prescaler Register (CFDPRESC.CFDPRESC).
Example 14-1.
For an external crystal oscillator at 0.4 MHz and the OSC48M frequency at 16 MHz, the
CFDPRESC.CFDPRESC value must be set scale down by more than factor 16/0.4 = 80, for
example, to 128, for a safe clock of adequate frequency.
Event
If the Event Output Enable bit in the Event Control register (EVCTRL.CFDEO) is set, the CFD clock failure will be
output on the Event Output. When the CFD is switched to the safe clock, the CFD clock failure will not be output on
the Event Output.
Sleep Mode
The CFD is halted depending on configuration of the XOSC and the peripheral clock request. For further details, refer
to the Sleep Behavior table above. The CFD interrupt can be used to wake up the device from sleep modes.
14.6.4
48 MHz Internal Oscillator (OSC48M) Operation
The OSC48M is an internal oscillator operating in open-loop mode and generating 48 MHz frequency. The OSC48M
frequency is selected by writing to the Division Factor field in the OSC48MDIV register (OSC48MDIV.DIV). OSC48M
is enabled by writing '1' to the Oscillator Enable bit in the OSC48M Control register (OSC48MCTRL.ENABLE), and
disabled by writing a '0' to this bit.
After enabling OSC48M, the OSC48M clock is output as soon as the oscillator is ready (STATUS.OSC48MRDY = 1).
User must ensure that the OSC48M is disabled before enabling it by reading STATUS.OSC48MRDY = 0.
After reset, OSC48M is enabled and serves as the default clock source at 4MHz.
OSC48M will behave differently in different sleep modes based on the settings of OSC48MCTRL.RUNSTDBY,
OSC48MCTRL.ONDEMAND, and OSC48MCTRL.ENABLE. If OSC48MCTRL.ENABLE = 0, the OSC48M will be
always stopped. For OSC48MCTRL.ENABLE = 1, the table below is valid:
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 77
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
Table 14-2. OSC48M Sleep Behavior
CPU Mode
OSC48MCTRL.RUNST OSC48MCTRL.ONDEM Sleep Behavior
DBY
AND
Active or Idle
-
0
Always run
Active or Idle
-
1
Run if requested by peripheral
Standby
1
0
Always run
Standby
1
1
Run if requested by peripheral
Standby
0
-
Run if requested by peripheral
After a hard reset, or when waking up from a Sleep mode where the OSC48M was disabled, the OSC48M will need
time to stabilize on the correct frequency (refer to 43. Electrical Characteristics 85℃). This start-up time can be
configured by changing the Oscillator Start-Up Delay bit group (OSC48MSTUP.STARTUP) in the OSC48M Startup
register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to
the digital logic. The OSC48M Ready bit in the Status register (STATUS.OSC48MRDY) is set when the oscillator
is stable and ready to be used as a clock source. An interrupt is generated on a zero-to-one transition on
STATUS.OSC48MRDY if the OSC48M Ready bit in the Interrupt Enable Set register (INTENSET.OSC48MRDY)
is set.
Faster start-up times are achievable by selecting shorter delays. However, the oscillator frequency may not stabilize
within tolerances when short delays are used. If a fast start-up time is desired at the expense of initial accuracy, the
division factor should be set to two or higher (OSC48MDIV.DIV > 0).
The OSC48M is used as a clock source for the generic clock generators. The OSC48M supports the change of
frequency while running with a write to the OSC48M Divider register (OSC48MDIV.DIV). The OSC48M must be
running and the OSC48M on demand bit (OSC48MCTRL.ONDEMAND) must be cleared when the OSC48MDIV.DIV
is changed, to ensure synchronization is complete. The OSC48M must remain enabled until the sync busy flag
returns to '0' (OSC48MSYNCBUSY.OSC48MDIV = 0).
14.6.5
Digital Phase-Locked Loop (FDPLL96M) Operation
The task of the DPLL is to maintain coherence between the input (reference) signal and the respective output
frequency, CLK_DPLL through phase comparison. The DPLL controller supports three independent sources of
reference clocks:
•
•
•
XOSC32K: This clock is provided by the 32.768 kHz External Crystal Oscillator (XOSC32K).
XOSC: This clock is provided by the External Multipurpose Crystal Oscillator (XOSC).
GCLK: This clock is provided by the Generic Clock Controller.
When the controller is enabled, the relationship between the reference clock frequency and the output clock
frequency is calculated as below:
1
fCK = fCKR × LDR + 1 + LDRFRAC × PRESC
16
2
Where, fCK is the frequency of the DPLL output clock, LDR is the loop divider ratio integer part, LDRFRAC is the loop
divider ratio fractional part, fCKR is the frequency of the selected reference clock, and PRESC is the output prescaler
value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 78
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
Figure 14-2. DPLL Block Diagram
XIN32
XOUT32
XOSC32K
XIN
XOUT
XOSC
DIVIDER
DPLLPRESC
DPLLCTRLB.FILTER
DPLLCTRLB.DIV
CKR
TDC
GCLK
DIGITAL FILTER
DCO
RATIO
DPLLCTRLB.REFCLK
CKDIV4
CKDIV2
CKDIV1
CG
CLK_DPLL
CK
DPLLRATIO
When the controller is disabled, the output clock is low. If the Loop Divider Ratio Fractional part bit field in the DPLL
Ratio register (DPLLRATIO.LDRFRAC) is zero, the DPLL works in integer mode. Otherwise, the fractional mode is
activated. The fractional part has a negative impact on the jitter of the DPLL.
For example (integer mode only): assuming FCKR = 32 kHz and FCK = 48 MHz, the multiplication
ratio is 1500. It means that LDR shall be set to 1499.
For example (fractional mode): assuming FCKR = 32 kHz and FCK = 48.006 MHz, the multiplication
ratio is 1500.1875 (1500 + 3/16). Thus LDR is set to 1499 and LDRFRAC to 3.
14.6.5.1 Basic Operation
14.6.5.1.1 Initialization, Enabling, Disabling, and Resetting
The DPLL is enabled by writing a '1' to the Enable bit in the DPLL Control A register (DPLLCTRLA.ENABLE). The
DPLL is disabled by writing a zero to this bit.
The DPLLSYNCBUSY.ENABLE is set when the DPLLCTRLA.ENABLE bit is modified. It is cleared when the
DPLL output clock CK has sampled the bit at the high level after enabling the DPLL. When disabling the DPLL,
DPLLSYNCBUSY.ENABLE is cleared when the output clock is no longer running.
Figure 14-3. Enable Synchronization Busy Operation
CLK_APB_OSCCTRL
ENABLE
CK
SYNCBUSY.ENABLE
The frequency of the DPLL output clock CK is stable when the module is enabled and when the Lock bit in the DPLL
Status register is set (DPLLSTATUS.LOCK).
When the Lock Time bit field in the DPLL Control B register (DPLLCTRLB.LTIME) is non-zero, a user defined lock
time is used to validate the lock operation. In this case the lock time is constant. If DPLLCTRLB.LTIME = 0, the lock
signal is linked with the status bit of the DPLL, and the lock time varies depending on the filter selection and the final
target frequency.
When the Wake Up Fast bit (DPLLCTRLB.WUF) is set, the wake up fast mode is activated. In this mode the clock
gating cell is enabled at the end of the startup time. At this time the final frequency is not stable, as it is still during the
acquisition period, but it allows to save several milliseconds. After first acquisition, the clock gater (CG) generating
the output clock CLK_DPLL is gated by the LOCK signal when the Lock Bypass bit (DPLLCTRLB.LBYPASS) is
cleared or is not gated and delivers the output clock CLK_DPLL immediately when DPLLCTRLB.LBYPASS is set.
Table 14-3. CLK_DPLL Behavior from Startup to First Edge Detection
WUF
LTIME
0
0
© 2021 Microchip Technology Inc.
and its subsidiaries
CLK_DPLL Behavior
Normal Mode: First Edge when lock is asserted
Datasheet
DS60001638D-page 79
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
...........continued
WUF
LTIME
CLK_DPLL Behavior
0
Not Equal To Zero
1
X
Lock Timer Timeout mode: First Edge when the timer down-counts to 0.
Wake Up Fast Mode: First Edge when CK is active (startup time)
Table 14-4. CLK_DPLL Behavior after First Edge Detection
LBYPASS
CLK_DPLL Behavior
0
Normal Mode: the CLK_DPLL is turned off when lock signal is low.
1
Lock Bypass Mode: the CLK_DPLL is always running, lock is irrelevant.
Figure 14-4. CK and CLK_DPLL Output from DPLL Off Mode to Running Mode
CKR
ENABLE
CK
CLK_DPLL
LOCK
t startup_time
t lock_time
CK STABLE
14.6.5.1.2 Reference Clock Switching
When a software operation requires reference clock switching, the recommended procedure is to turn the DPLL into
the Standby mode, modify the DPLLCTRLB.REFCLK to select the desired reference source, and activate the DPLL
again.
14.6.5.1.3 Output Clock Prescaler
The DPLL controller includes an output prescaler. This prescaler provides three selectable output clocks CK, CKDIV2
and CKDIV4. The Prescaler bit field in the DPLL Prescaler register (DPLLPRESC.PRESC) is used to select a new
output clock prescaler. When the prescaler field is modified, the DPLLSYNCBUSY.DPLLPRESC bit is set. It will be
cleared by hardware when the synchronization is over.
Figure 14-5. Output Clock Switching Operation
CKR
PRESC
0
1
CK
CKDIV2
CLK_DPLL
SYNCBUSY.PRESC
DPLL_LOCK
CK STABLE
© 2021 Microchip Technology Inc.
and its subsidiaries
CK SWITCHING
Datasheet
CK STABLE
DS60001638D-page 80
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.6.5.1.4 Loop Divider Ratio Updates
The DPLL Controller supports on-the-fly update of the DPLL Ratio Control (DPLLRATIO) register only
when the GCLK_DPLL_32K (GCLK.PCHCTRL1) is configured and enabled. The FDPLL reference clock
(DPLLCTRLB.REFCLK) can still be set to one of the three options (XOSC, XOSC32K, GCLK) as long as
GCLK_DPLL_32K is active.
STATUS.DPLLLDRTO is set when the DPLLRATIO register has been modified and the DPLL analog cell has
successfully sampled the updated value. At that time the DPLLSTATUS.LOCK bit is cleared and set again by
hardware when the output frequency reached a stable state.
Figure 14-6. RATIOCTRL register update operation
CKR
LDR
LDRFRAC
mult0
mult1
CK
CLK_DPLL
LOCK
LOCKL
14.6.5.1.5 Digital Filter Selection
The PLL digital filter (PI controller) is automatically adjusted to provide a good compromise between stability and
jitter. However, a software operation can override the filter setting using the Filter bit field in the DPLL Control B
register (DPLLCTRLB.FILTER). The Low-Power Enable bit (DPLLCTRLB.LPEN) can be used to bypass the Time to
Digital Converter (TDC) module.
14.6.6
Interrupts
The OSCCTRL has the following interrupt sources:
•
•
•
•
XOSCRDY - Multipurpose Crystal Oscillator Ready: A 0-to-1 transition on the STATUS.XOSCRDY bit is
detected
XOSCFAIL - Clock Failure. A 0-to-1 transition on the STATUS.XOSCFAIL bit is detected
OSC48MRDY - 48 MHz Internal Oscillator Ready: A 0-to-1 transition on the STATUS.OSC48MRDY bit is
detected
DPLL-related:
– DPLLLOCKR - DPLL Lock Rise: A 0-to-1 transition of the STATUS.DPLLLOCKR bit is detected
– DPLLLOCKF - DPLL Lock Fall: A 0-to-1 transition of the STATUS.DPLLLOCKF bit is detected
– DPLLLTTO - DPLL Lock Timer Time-out: A 0-to-1 transition of the STATUS.DPLLLTTO bit is detected
– DPLLLDRTO - DPLL Loop Divider Ratio Update Complete. A 0-to-1 transition of the STATUS.DPLLLDRTO
bit is detected
All these interrupts are synchronous wake-up sources.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs.
Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set register
(INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).
As both INTENSET and INTENCLR always reflect the same value, the status of interrupt enablement can be read
from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the OSCCTRL is reset.
Refer to the INTFLAG register for details on how to clear interrupt flags.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 81
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
The OSCCTRL has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG
register to determine which interrupt condition is present. Refer to the INTFLAG register for details.
Note: The interrupts must be globally enabled for interrupt requests to be generated.
14.6.7
Events
The CFD can generate the following output event:
• Clock Failure (XOSCFAIL): Generated when the Clock Failure status bit is set in the Status register
(STATUS.XOSCFAIL). The CFD event is not generated when the Clock Switch bit (STATUS.XOSCCKSW) in the
Status register is set.
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.CFDEO) enables the CFD output event.
Writing a '0' to this bit disables the CFD output event. Refer to the Event System chapter for details on configuring the
event system.
14.6.8
Synchronization
OSC48M
Due to the multiple clock domains, values in the OSC48M control registers need to be synchronized to other clock
domains.
When executing an operation that requires synchronization, the relevant synchronization bit in the Synchronization
Busy register (OSC48MSYNCBUSY) will be set immediately, and cleared when synchronization is complete.
The following registers need synchronization when written:
• OSC48M Divider register (OSC48MDIV)
FDPLL96M
Due to the multiple clock domains, some registers in the FDPLL96M must be synchronized when accessed.
When executing an operation that requires synchronization, the relevant synchronization bit in the Synchronization
Busy register (DPLLSYNCBUSY) will be set immediately, and cleared when synchronization is complete.
The following bits need synchronization when written:
• Enable bit in control register A (DPLLCTRLA.ENABLE)
• DPLL Ratio register (DPLLRATIO)
• DPLL Prescaler register (DPLLPRESC)
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 82
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7
Register Summary
Offset
Name
0x00
INTENCLR
0x04
INTENSET
0x08
INTFLAG
0x0C
STATUS
0x10
XOSCCTRL
0x12
0x13
0x14
0x15
0x16
0x17
CFDPRESC
EVCTRL
OSC48MCTRL
OSC48MDIV
OSC48MSTUP
Reserved
0x18
OSC48MSYNCBUS
Y
0x1C
0x1D
...
0x1F
0x20
DPLLCTRLA
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
7:0
7:0
7:0
7:0
7:0
7:0
15:8
23:16
31:24
7:0
7
6
5
4
3
2
1
0
DPLLLDRTO
DPLLLTO
XOSCFAIL
DPLLLCKF
XOSCRDY
DPLLLCKR
DPLLLDRTO
DPLLLTO
XOSCFAIL
DPLLLCKF
XOSCRDY
DPLLLCKR
DPLLLDRTO
DPLLLTO
XOSCFAIL
DPLLLCKF
XOSCRDY
DPLLLCKR
DPLLLDRTO
XOSCCKSW
DPLLLTO
XOSCFAIL
DPLLLCKF
XOSCRDY
DPLLLCKR
OSC48MRDY
OSC48MRDY
OSC48MRDY
OSC48MRDY
ONDEMAND RUNSTDBY
STARTUP[3:0]
SWBEN
CFDEN
AMPGC
XTALEN
ENABLE
GAIN[2:0]
CFDPRESC[2:0]
CFDEO
ONDEMAND RUNSTDBY
ENABLE
DIV[3:0]
STARTUP[2:0]
OSC48MDIV
ONDEMAND RUNSTDBY
ENABLE
Reserved
DPLLRATIO
0x24
DPLLCTRLB
0x28
0x29
...
0x2B
0x2C
0x2D
...
0x2F
0x30
0x31
...
0x37
DPLLPRESC
0x38
Bit Pos.
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
LDR[7:0]
LDR[11:8]
LDRFRAC[3:0]
REFCLK[1:0]
WUF
LBYPASS
DIV[7:0]
LPEN
FILTER[1:0]
LTIME[2:0]
DIV[10:8]
PRESC[1:0]
Reserved
DPLLSYNCBUSY
7:0
DPLLPRESC DPLLRATIO
ENABLE
Reserved
DPLLSTATUS
7:0
CLKRDY
LOCK
Reserved
CAL48M
7:0
15:8
23:16
31:24
© 2021 Microchip Technology Inc.
and its subsidiaries
FCAL[5:0]
FRANGE[1:0]
TCAL[5:0]
Datasheet
DS60001638D-page 83
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.1
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x00
0x00000000
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
DPLLLDRTO
R/W
0
10
DPLLLTO
R/W
0
9
DPLLLCKF
R/W
0
8
DPLLLCKR
R/W
0
7
6
5
4
OSC48MRDY
R/W
0
3
2
1
XOSCFAIL
R/W
0
0
XOSCRDY
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DPLL Loop Divider Ratio Update Complete Interrupt Enable bit, which disables the
DPLL Loop Divider Ratio Update Complete interrupt.
Value
Description
0
The DPLL Loop Divider Ratio Update Complete interrupt is disabled.
1
The DPLL Loop Divider Ratio Update Complete interrupt is enabled, and an interrupt request will be
generated when the DPLL Loop Divider Ratio Update Complete Interrupt flag is set.
Bit 10 – DPLLLTO DPLL Lock Timeout Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DPLL Lock Timeout Interrupt Enable bit, which disables the DPLL Lock Timeout
interrupt.
Value
Description
0
The DPLL Lock Timeout interrupt is disabled.
1
The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL
Lock Timeout Interrupt flag is set.
Bit 9 – DPLLLCKF DPLL Lock Fall Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DPLL Lock Fall Interrupt Enable bit, which disables the DPLL Lock Fall interrupt.
Value
Description
0
The DPLL Lock Fall interrupt is disabled.
1
The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL
Lock Fall Interrupt flag is set.
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and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
Bit 8 – DPLLLCKR DPLL Lock Rise Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DPLL Lock Rise Interrupt Enable bit, which disables the DPLL Lock Rise interrupt.
Value
Description
0
The DPLL Lock Rise interrupt is disabled.
1
The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL
Lock Rise Interrupt flag is set.
Bit 4 – OSC48MRDY OSC48M Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the OSC48M Ready Interrupt Enable bit, which disables the OSC48M Ready interrupt.
Value
Description
0
The OSC48M Ready interrupt is disabled.
1
The OSC48M Ready interrupt is enabled, and an interrupt request will be generated when the
OSC48M Ready Interrupt flag is set.
Bit 1 – XOSCFAIL Clock Failure Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the XOSC Clock Failure Interrupt Enable bit, which disables the XOSC Clock Failure
interrupt.
Value
Description
0
The XOSC Clock Failure interrupt is disabled.
1
The XOSC Clock Failure interrupt is enabled, and an interrupt request will be generated when the
XOSC Clock Failure Interrupt flag is set.
Bit 0 – XOSCRDY XOSC Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the XOSC Ready Interrupt Enable bit, which disables the XOSC Ready interrupt.
Value
Description
0
The XOSC Ready interrupt is disabled.
1
The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC
Ready Interrupt flag is set.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 85
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.2
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x04
0x00000000
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
DPLLLDRTO
R/W
0
10
DPLLLTO
R/W
0
9
DPLLLCKF
R/W
0
8
DPLLLCKR
R/W
0
7
6
5
4
OSC48MRDY
R/W
0
3
2
1
XOSCFAIL
R/W
0
0
XOSCRDY
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the DPLL Loop Ratio Update Complete Interrupt Enable bit, which enables the DPLL
Loop Ratio Update Complete interrupt.
Value
Description
0
The DPLL Loop Divider Ratio Update Complete interrupt is disabled.
1
The DPLL Loop Ratio Update Complete interrupt is enabled, and an interrupt request will be generated
when the DPLL Loop Ratio Update Complete Interrupt flag is set.
Bit 10 – DPLLLTO DPLL Lock Timeout Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the DPLL Lock Timeout Interrupt Enable bit, which enables the DPLL Lock Timeout
interrupt.
Value
Description
0
The DPLL Lock Timeout interrupt is disabled.
1
The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL
Lock Timeout Interrupt flag is set.
Bit 9 – DPLLLCKF DPLL Lock Fall Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the DPLL Lock Fall Interrupt Enable bit, which enables the DPLL Lock Fall interrupt.
Value
Description
0
The DPLL Lock Fall interrupt is disabled.
1
The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL
Lock Fall Interrupt flag is set.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 86
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
Bit 8 – DPLLLCKR DPLL Lock Rise Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the DPLL Lock Rise Interrupt Enable bit, which enables the DPLL Lock Rise interrupt.
Value
Description
0
The DPLL Lock Rise interrupt is disabled.
1
The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL
Lock Rise Interrupt flag is set.
Bit 4 – OSC48MRDY OSC48M Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the OSC48M Ready Interrupt Enable bit, which enables the OSC48M Ready interrupt.
Value
Description
0
The OSC48M Ready interrupt is disabled.
1
The OSC48M Ready interrupt is enabled, and an interrupt request will be generated when the
OSC48M Ready Interrupt flag is set.
Bit 1 – XOSCFAIL XOSC Clock Failure Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the XOSC Clock Failure Interrupt Enable bit, which enables the XOSC Clock Failure
Interrupt.
Value
Description
0
The XOSC Clock Failure Interrupt is disabled.
1
The XOSC Clock Failure Interrupt is enabled, and an interrupt request will be generated when the
XOSC Clock Failure Interrupt flag is set.
Bit 0 – XOSCRDY XOSC Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the XOSC Ready Interrupt Enable bit, which enables the XOSC Ready interrupt.
Value
Description
0
The XOSC Ready interrupt is disabled.
1
The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC
Ready Interrupt flag is set.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 87
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.3
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
INTFLAG
0x08
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
DPLLLDRTO
R/W
0
10
DPLLLTO
R/W
0
9
DPLLLCKF
R/W
0
8
DPLLLCKR
R/W
0
7
6
5
4
OSC48MRDY
R/W
0
3
2
1
XOSCFAIL
R/W
0
0
XOSCRDY
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete
This flag is cleared by writing '1' to it.
This flag is set on a high to low transition of the DPLL Loop Divider Ratio Update Complete bit in the Status register
(STATUS.DPLLLDRTO) and will generate an interrupt request if INTENSET.DPLLLDRTO is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DPLL Loop Divider Ratio Update Complete interrupt flag.
Bit 10 – DPLLLTO DPLL Lock Timeout
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DPLL Lock Timeout bit in the Status register (STATUS.DPLLLTO) and will
generate an interrupt request if INTENSET.DPLLLTO is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DPLL Lock Timeout interrupt flag.
Bit 9 – DPLLLCKF DPLL Lock Fall
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DPLL Lock Fall bit in the Status register (STATUS.DPLLLCKF) and will
generate an interrupt request if INTENSET.DPLLLCKF is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DPLL Lock Fall interrupt flag.
Bit 8 – DPLLLCKR DPLL Lock Rise
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DPLL Lock Rise bit in the Status register (STATUS.DPLLLCKR) and will
generate an interrupt request if INTENSET.DPLLLCKR is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DPLL Lock Rise interrupt flag.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 88
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
Bit 4 – OSC48MRDY OSC48M Ready
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the OSC48M Ready bit in the Status register (STATUS.OSC48MRDY) and will
generate an interrupt request if INTENSET.OSC48MRDY is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the OSC48M Ready interrupt flag.
Bit 1 – XOSCFAIL XOSC Failure Detection
This flag is cleared by writing '1' to it.
This flag is set on a 0-to-1 transition of the XOSC Clock Failure bit in the Status register (STATUS.XOSCFAIL) and
will generate an interrupt request if INTENSET.XOSCFAIL is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the XOSC Clock Fail interrupt flag.
Bit 0 – XOSCRDY XOSC Ready
This flag is cleared by writing '1' to it.
This flag is set on a 0-to-1 transition of the XOSC Ready bit in the Status register (STATUS.XOSCRDY) and will
generate an interrupt request if INTENSET.XOSCRDY is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the XOSC Ready interrupt flag.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 89
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.4
Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x0C
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
DPLLLDRTO
R
0
10
DPLLLTO
R
0
9
DPLLLCKF
R
0
8
DPLLLCKR
R
0
7
6
5
4
OSC48MRDY
R
0
3
2
XOSCCKSW
R
0
1
XOSCFAIL
R
0
0
XOSCRDY
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete
Value
Description
0
DPLL Loop Divider Ratio Update Complete is not detected.
1
DPLL Loop Divider Ratio Update Complete is detected.
Bit 10 – DPLLLTO DPLL Lock Timeout
Value
Description
0
DPLL Lock time-out is not detected.
1
DPLL Lock time-out is detected.
Bit 9 – DPLLLCKF DPLL Lock Fall
Value
Description
0
DPLL Lock fall edge is not detected.
1
DPLL Lock fall edge is detected.
Bit 8 – DPLLLCKR DPLL Lock Rise
Value
Description
0
DPLL Lock rise edge is not detected.
1
DPLL Lock fall edge is detected.
Bit 4 – OSC48MRDY OSC48M Ready
Value
Description
0
OSC48M is not ready.
1
OSC48M is stable and ready to be used as a clock source.
Bit 2 – XOSCCKSW XOSC Clock Switch
Value
Description
0
XOSC is not switched and provides the external clock or crystal oscillator clock.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 90
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
Value
1
Description
XOSC is switched and provides the safe clock.
Bit 1 – XOSCFAIL XOSC Clock Failure
Value
Description
0
XOSC failure is not detected.
1
A XOSC failure is detected.
Bit 0 – XOSCRDY XOSC Ready
Value
Description
0
XOSC is not ready.
1
XOSC is stable and ready to be used as a clock source.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 91
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.5
External Multipurpose Crystal Oscillator (XOSC) Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
XOSCCTRL
0x10
0x0080
PAC Write-Protection
15
14
13
STARTUP[3:0]
R/W
R/W
0
0
R/W
0
7
ONDEMAND
R/W
1
6
RUNSTDBY
R/W
0
5
12
R/W
0
11
AMPGC
R/W
0
10
R/W
0
9
GAIN[2:0]
R/W
0
4
SWBEN
R/W
0
3
CFDEN
R/W
0
2
XTALEN
R/W
0
1
ENABLE
R/W
0
8
R/W
0
0
Bits 15:12 – STARTUP[3:0] Start-Up Time
These bits select start-up time for the oscillator.
The OSCULP32K oscillator is used to clock the start-up counter.
Table 14-5. Start-Up Time for External Multipurpose Crystal Oscillator
STARTUP[3:0]
Number of OSCULP32K Clock
Cycles
Number of XOSC Clock
Cycles
Approximate Equivalent Time
[µs]
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
31
61
122
244
488
977
1953
3906
7813
15625
31250
62500
125000
250000
500000
1000000
Notes:
1. Actual startup time is 1 OSCULP32K cycle + 3 XOSC cycles.
2. The given time neglects the three XOSC cycles before OSCULP32K cycle.
Bit 11 – AMPGC Automatic Amplitude Gain Control
Note: The configuration of the oscillator gain is mandatory even if AMPGC feature is enabled at startup.
Value
0
1
Description
The automatic amplitude gain control is disabled.
The automatic amplitude gain control is enabled. Amplitude gain will be automatically adjusted during
Crystal Oscillator operation.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 92
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
Bits 10:8 – GAIN[2:0] Oscillator Gain
These bits select the gain for the oscillator. The listed maximum frequencies are recommendations, and might
vary based on capacitive load and crystal characteristics. Those bits must be properly configured even when the
Automatic Amplitude Gain Control is active.
Value
Recommended Max Frequency [MHz]
0x0
0x1
0x2
0x3
0x4
0x5-0x7
2
4
8
16
32
Reserved
Bit 7 – ONDEMAND On Demand Control
The On Demand operation mode allows the oscillator to be enabled or disabled, depending on peripheral clock
requests.
If the ONDEMAND bit has been previously written to '1', the oscillator will be running only when requested by a
peripheral. If there is no peripheral requesting the oscillator’s clock source, the oscillator will be in a disabled state.
If On Demand is disabled, the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active.
Value
Description
0
The oscillator is always on, if enabled.
1
The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source.
The oscillator is disabled if no peripheral is requesting the clock source.
Bit 6 – RUNSTDBY Run in Standby
This bit controls how the XOSC behaves during Standby Sleep mode, together with the ONDEMAND bit:
Value
Description
0
The XOSC is not running in Standby Sleep mode if no peripheral requests the clock.
1
The XOSC is running in Standby Sleep mode. If ONDEMAND = 1, the XOSC will be running when
a peripheral is requesting the clock. If ONDEMAND = 0, the clock source will always be running in
Standby sleep mode.
Bit 4 – SWBEN Clock Switch Back Enable
This bit controls the XOSC output switch back to the external clock or crystal oscillator in case of clock recovery:
Value
Description
0
The clock switch back is disabled.
1
The clock switch back is enabled. This bit is reset once the XOSC putput clock is switched back to the
external clock or crystal oscillator.
Bit 3 – CFDEN Clock Failure Detector Enable
This bit controls the clock failure detector:
Value
Description
0
The Clock Failure Detector is disabled.
1
the Clock Failure Detector is enabled.
Bit 2 – XTALEN Crystal Oscillator Enable
This bit controls the connections between the I/O pads and the external clock or crystal oscillator:
Value
Description
0
External clock connected on XIN. XOUT can be used as general-purpose I/O.
1
Crystal connected to XIN/XOUT.
Bit 1 – ENABLE Oscillator Enable
Value
Description
0
The oscillator is disabled.
1
The oscillator is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 93
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.6
Clock Failure Detector Prescaler
Name:
Offset:
Reset:
Property:
Bit
7
CFDPRESC
0x12
0x00
PAC Write-Protection
6
5
4
3
Access
Reset
2
R/W
0
1
CFDPRESC[2:0]
R/W
0
0
R/W
0
Bits 2:0 – CFDPRESC[2:0] Clock Failure Detector Prescaler
These bits select the prescaler for the clock failure detector.
The OSC48M oscillator is used to clock the CFD prescaler. The CFD safe clock frequency is the OSC48M frequency
divided by 2^CFDPRESC.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 94
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.7
Event Control
Name:
Offset:
Reset:
Property:
Bit
7
EVCTRL
0x13
0x00
PAC Write-Protection
6
5
4
3
Access
Reset
2
1
0
CFDEO
R/W
0
Bit 0 – CFDEO Clock Failure Detector Event Output Enable
This bit indicates whether the Clock Failure detector event output is enabled or not and an output event will be
generated when the Clock Failure detector detects a clock failure
Value
Description
0
Clock Failure detector event output is disabled and no event will be generated.
1
Clock Failure detector event output is enabled and an event will be generated.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 95
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.8
48MHz Internal Oscillator (OSC48M) Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
ONDEMAND
R/W
1
OSC48MCTRL
0x14
0x82
PAC Write-Protection
6
RUNSTDBY
R/W
0
5
4
3
2
1
ENABLE
R/W
1
0
Bit 7 – ONDEMAND On Demand Control
The On Demand operation mode allows the oscillator to be enabled or disabled depending on peripheral clock
requests.
If the ONDEMAND bit has been previously written to '1', the oscillator will only be running when requested by a
peripheral. If there is no peripheral requesting the oscillator’s clock source, the oscillator will be in a disabled state.
If On Demand is disabled the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active.
Value
Description
0
The oscillator is always on, if enabled.
1
The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source.
The oscillator is disabled if no peripheral is requesting the clock source.
Bit 6 – RUNSTDBY Run in Standby
This bit controls how the OSC48M behaves during standby sleep mode.
Value
Description
0
The OSC48M is disabled in Standby Sleep mode if no peripheral requests the clock.
1
The OSC48M is not stopped in Standby Sleep mode. If ONDEMAND=1, the OSC48M will be running
when a peripheral is requesting the clock. If ONDEMAND=0, the clock source will always be running in
Standby Sleep mode.
Bit 1 – ENABLE Oscillator Enable
Value
Description
0
The oscillator is disabled.
1
The oscillator is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 96
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.9
OSC48M Divider
Name:
Offset:
Reset:
Property:
OSC48MDIV
0x15
0x0B
PAC Write-Protection, Write-Synchronized
Note: OSC48MDIV is a write-synchronized register: OSC48MSYNCBUSY.OSC48MDIV must be checked to
ensure the OSC48MDIV synchronization is complete. The OSC48M supports the change of frequency while
running with a write to the OSC48M Divider register (OSC48MDIV.DIV). The OSC48M must be running and the
OSC48M on demand bit (OSC48MCTRL.ONDEMAND) must be cleared when the OSC48MDIV.DIV is changed,
to ensure synchronization is complete. The OSC48M must remain enabled until the sync busy flag returns to '0'
(OSC48MSYNCBUSY.OSC48MDIV = 0).
Bit
7
6
5
4
3
2
1
0
R/W
1
R/W
1
DIV[3:0]
Access
Reset
R/W
1
R/W
0
Bits 3:0 – DIV[3:0] Oscillator Divider Selection
These bits control the oscillator frequency range by adjusting the division ratio. The oscillator frequency is 48 MHz
divided by DIV+1.
Value
Description
0000
48 MHz
0001
24 MHz
0010
16 MHz
0011
12 MHz
0100
9.6 MHz
0101
8 MHz
0110
6.86 MHz
0111
6 MHz
1000
5.33 MHz
1001
4.8 MHz
1010
4.36 MHz
1011
4 MHz
1100
3.69 MHz
1101
3.43 MHz
1110
3.2 MHz
1111
3 MHz
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 97
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.10 OSC48M Startup
Name:
Offset:
Reset:
Property:
Bit
7
OSC48MSTUP
0x16
0x07
PAC Write-Protection
6
5
4
3
Access
Reset
2
R/W
1
1
STARTUP[2:0]
R/W
1
0
R/W
1
Bits 2:0 – STARTUP[2:0] Oscillator Startup Delay
These bits select the oscillator start-up delay in oscillator cycles.
Table 14-6. Oscillator Divider Selection
STARTUP[2:0]
Number of OSCM48M Clock Cycles
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
8
16
32
64
128
256
512
1024
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 98
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.11 OSC48M Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
OSC48MSYNCBUSY
0x18
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
OSC48MDIV
R
0
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 2 – OSC48MDIV Oscillator Divider Synchronization Status
This bit is set when OSC48MDIV register is written.
This bit is cleared when OSC48MDIV synchronization is completed.
Value
Description
0
No synchronized access.
1
Synchronized access is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 99
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.12 DPLL Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
ONDEMAND
R/W
1
DPLLCTRLA
0x1C
0x80
PAC Write-Protection, Write-Synchronized Bits
6
RUNSTDBY
R/W
0
5
4
3
2
1
ENABLE
R/W
0
0
Bit 7 – ONDEMAND On Demand Clock Activation
The On Demand operation mode allows the DPLL to be enabled or disabled depending on peripheral clock requests.
If the ONDEMAND bit has been previously written to '1', the DPLL will only be running when requested by a
peripheral. If there is no peripheral requesting the DPLL’s clock source, the DPLL will be in a disabled state.
If On Demand is disabled the DPLL will always be running when enabled.
In Standby Sleep mode, the On Demand operation is still active.
Note: This bit is not synchronized.
Value
0
1
Description
The DPLL is always on, if enabled.
The DPLL is enabled when a peripheral is requesting the DPLL to be used as a clock source. The
DPLL is disabled if no peripheral is requesting the clock source.
Bit 6 – RUNSTDBY Run in Standby
This bit controls how the DPLL behaves during Standby Sleep mode:
Note: This bit is not synchronized.
Value
0
1
Description
The DPLL is disabled in Standby Sleep mode if no peripheral requests the clock.
The DPLL is not stopped in Standby Sleep mode. If ONDEMAND = 1, the DPLL will be running when
a peripheral is requesting the clock. If ONDEMAND = 0, the clock source will always be running in
Standby Sleep mode.
Bit 1 – ENABLE DPLL Enable
Note: This bit is write-synchronized: DPLLSYNCBUSY.ENABLE must be checked to ensure the
DPLLCTRLA.ENABLE synchronization is complete.
Value
0
1
Description
The DPLL is disabled.
The DPLL is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 100
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.13 DPLL Ratio Control
Name:
Offset:
Reset:
Property:
DPLLRATIO
0x20
0x00
PAC Write-Protection, Write-Synchronized
Note: DPLLRATIO is a write-synchronized register: DPLLSYNCBUSY.DPLLRATIO must be checked to ensure the
DPLLRATIO synchronization is complete.
Bit
31
30
29
28
27
23
22
21
20
19
26
25
24
Access
Reset
Bit
Access
Reset
Bit
R/W
0
15
14
13
12
11
18
17
LDRFRAC[3:0]
R/W
R/W
0
0
10
16
R/W
0
9
8
LDR[11:8]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
LDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 19:16 – LDRFRAC[3:0] Loop Divider Ratio Fractional Part
Writing these bits selects the fractional part of the frequency multiplier.
Bits 11:0 – LDR[11:0] Loop Divider Ratio
Writing these bits selects the integer part of the frequency multiplier.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 101
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.14 DPLL Control B
Name:
Offset:
Reset:
Property:
Bit
31
DPLLCTRLB
0x24
0x00
PAC Write-Protection
30
29
28
27
R/W
0
25
DIV[10:8]
R/W
0
R/W
0
19
18
17
16
Access
Reset
Bit
23
22
21
20
26
24
DIV[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
LBYPASS
R/W
0
11
10
9
LTIME[2:0]
R/W
0
8
R/W
0
1
0
Access
Reset
Bit
7
6
Access
Reset
5
4
REFCLK[1:0]
R/W
R/W
0
0
R/W
0
3
WUF
R/W
0
2
LPEN
R/W
0
FILTER[1:0]
R/W
0
R/W
0
Bits 26:16 – DIV[10:0] Clock Divider
These bits set the XOSC clock division factor and can be calculated with following formula:
fXOSC
f DIV =
2x DIV + 1
Bit 12 – LBYPASS Lock Bypass
Value
Description
0
DPLL Lock signal drives the DPLL controller internal logic.
1
DPLL Lock signal is always asserted.
Bits 10:8 – LTIME[2:0] Lock Time
These bits select the lock time-out value:
Value
Name
Description
0x0
Default
No time-out. Automatic lock.
0x1
Reserved
0x2
Reserved
0x3
Reserved
0x4
8MS
Time-out if no lock within 8ms
0x5
9MS
Time-out if no lock within 9ms
0x6
10MS
Time-out if no lock within 10ms
0x7
11MS
Time-out if no lock within 11ms
Bits 5:4 – REFCLK[1:0] Reference Clock Selection
Write these bits to select the DPLL clock reference:
Value
Name
Description
0x0
XOSC32K
XOSC32K clock reference
0x1
XOSC
XOSC clock reference
0x2
GCLK
GCLK clock reference
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 102
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
Value
0x3
Name
Reserved
Description
Bit 3 – WUF Wake Up Fast
Value
Description
0
DPLL clock is output after startup and lock time.
1
DPLL clock is output after startup time.
Bit 2 – LPEN Low-Power Enable
Value
Description
0
The low-power mode is disabled. Time to Digital Converter is enabled.
1
The low-power mode is enabled. Time to Digital Converter is disabled. This will improve power
consumption but increase the output jitter.
Bits 1:0 – FILTER[1:0] Proportional Integral Filter Selection
These bits select the DPLL filter type:
Value
Name
Description
0x0
DEFAULT
Default filter mode
0x1
LBFILT
Low bandwidth filter
0x2
HBFILT
High bandwidth filter
0x3
HDFILT
High damping filter
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Datasheet
DS60001638D-page 103
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.15 DPLL Prescaler
Name:
Offset:
Reset:
Property:
DPLLPRESC
0x28
0x00
PAC Write-Protection, Write-Synchronized
Note: DPLLPRESC is a write-synchronized register: DPLLSYNCBUSY.DPLLPRESC must be checked to ensure
the DPLLPRESC synchronization is complete.
Bit
7
6
5
4
3
Access
Reset
2
1
0
PRESC[1:0]
R/W
R/W
0
0
Bits 1:0 – PRESC[1:0] Output Clock Prescaler
These bits define the output clock prescaler setting.
Value
Name
Description
0x0
DIV1
DPLL output is divided by 1
0x1
DIV2
DPLL output is divided by 2
0x2
DIV4
DPLL output is divided by 4
0x3
Reserved
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PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.16 DPLL Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
7
DPLLSYNCBUSY
0x2C
0x00
–
6
Access
Reset
5
4
3
DPLLPRESC
R
0
2
DPLLRATIO
R
0
1
ENABLE
R
0
0
Bit 3 – DPLLPRESC DPLL Prescaler Synchronization Status
Value
Description
0
The DPLLRESC register has been synchronized.
1
The DPLLRESC register value has changed and its synchronization is in progress.
Bit 2 – DPLLRATIO DPLL Loop Divider Ratio Synchronization Status
Value
Description
0
The DPLLRATIO register has been synchronized.
1
The DPLLRATIO register value has changed and its synchronization is in progress.
Bit 1 – ENABLE DPLL Enable Synchronization Status
Value
Description
0
The DPLLCTRLA.ENABLE bit has been synchronized.
1
The DPLLCTRLA.ENABLE bit value has changed and its synchronization is in progress.
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Datasheet
DS60001638D-page 105
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.17 DPLL Status
Name:
Offset:
Reset:
Property:
Bit
7
DPLLSTATUS
0x30
0x00
–
6
5
4
3
Access
Reset
2
1
CLKRDY
R
0
0
LOCK
R
0
Bit 1 – CLKRDY Output Clock Ready
Value
Description
0
The DPLL output clock is off.
1
The DPLL output clock in on.
Bit 0 – LOCK DPLL Lock status bit
Value
Description
0
The DPLL Lock signal is cleared, when the DPLL is disabled or when the DPLL is trying to reach the
target frequency.
1
The DPLL Lock signal is asserted when the desired frequency is reached.
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Datasheet
DS60001638D-page 106
PIC32CM MC00 Family
Oscillators Controller (OSCCTRL)
14.7.18 OSC48M Calibration
Name:
Offset:
Reset:
Property:
CAL48M
0x38
Calibrated value for VDD range 3.6 V to 5.5 V
PAC Write-Protection
This register (bits 0 to 21) must be updated with the CAL48M bit field from the NVM Software Calibration Area. Refer
to 8.4 NVM Software Calibration Area Mapping.
Bit
31
30
29
28
27
23
22
21
20
19
26
25
24
18
17
16
R/W
x
Access
Reset
Bit
TCAL[5:0]
Access
Reset
Bit
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
10
9
15
14
13
12
11
7
6
5
4
3
Access
Reset
Bit
8
FRANGE[1:0]
R/W
R/W
x
x
2
1
0
R/W
x
R/W
x
R/W
x
FCAL[5:0]
Access
Reset
R/W
x
R/W
x
R/W
x
Bits 21:16 – TCAL[5:0] Temperature Calibration
Bits 9:8 – FRANGE[1:0] Frequency Range
Bits 5:0 – FCAL[5:0] Frequency Calibration
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Datasheet
DS60001638D-page 107
PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
15.
15.1
32.768 kHz Oscillators Controller (OSC32KCTRL)
Overview
The 32.768 kHz Oscillators Controller (OSC32KCTRL) provides a user interface to the 32.768 kHz oscillators:
XOSC32K, OSC32K, and OSCULP32K.
The OSC32KCTRL sub-peripherals can be enabled, disabled, calibrated, and monitored through interface registers.
All sub-peripheral statuses are collected in the Status register (STATUS). They can additionally trigger interrupts upon
status changes through the INTENSET, INTENCLR, and INTFLAG registers.
15.2
Features
•
•
•
•
32.768 kHz Crystal Oscillator (XOSC32K)
– Programmable start-up time
– Crystal or external input clock on XIN32 I/O
– Clock failure detection with safe clock switch
– Clock failure event output
32.768 kHz High Accuracy Internal Oscillator (OSC32K)
– Frequency fine tuning
– Programmable start-up time
32.768 kHz Ultra Low-Power Internal Oscillator (OSCULP32K)
– Ultra low-power, always-on oscillator
– Frequency fine tuning
1.024 kHz clock outputs available
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Datasheet
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PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
15.3
Block Diagram
Figure 15-1. OSC32KCTRL Block Diagram
OSC32KCTRL
XOUT32
XIN32
CFD Event
CFD
CLK_XOSC32K
XOSC32K
32K OSCILLATORS
CONTROL
CLK_OSCULP32K
OSCULP32K
CLK_OSC32K
OSC32K
STATUS
register
INTERRUPTS
GENERATOR
15.4
Interrupts
Signal Description
Signal
Description
Type
XIN32
Analog Input
32.768 kHz Crystal Oscillator or external clock input
XOUT32
Analog Output
32.768 kHz Crystal Oscillator output
The I/O lines are automatically selected when XOSC32K is enabled.
Note: The signal of the external crystal oscillator may affect the jitter of neighboring pads.
15.5
Peripheral Dependencies
Peripheral
OSC32KCTRL
AHB CLK
APB CLK
Generic CLK
Enabled at reset
Enabled at reset
Index
-
Y
-
PAC
Events
DMA
Base Address IRQ
0x40001400
0
Sleep Walking
© 2021 Microchip Technology Inc.
and its subsidiaries
Index Prot at reset User
Datasheet
5
N
-
Generator
Index
1: XOSC_FAIL
-
Y
DS60001638D-page 109
PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
15.6
15.6.1
Functional Description
Principle of Operation
The XOSC32K, OSC32K, and OSCULP32K are configured through the OSC32KCTRL Control registers. Through
this interface, the sub-peripherals are enabled, disabled, or have their calibration values updated.
The STATUS register gathers different status signals coming from the sub-peripherals of the OSC32KCTRL Control
register. The status signals can be used to generate system interrupts, and in some cases wake up the system from
Standby mode, provided the corresponding interrupt is enabled.
15.6.2
32.768 kHz External Crystal Oscillator (XOSC32K) Operation
The XOSC32K can operate in these modes:
•
•
External clock, with an external clock signal connected to XIN32
Crystal oscillator, with an external 32.768 kHz crystal connected between XIN32 and XOUT32
At reset, the XOSC32K is disabled, and the XIN32/XOUT32 pins can either be used as General Purpose I/O (GPIO)
pins or by other peripherals in the system.
When XOSC32K is enabled, the operating mode determines the GPIO usage. When in crystal oscillator mode, the
XIN32 and XOUT32 pins are controlled by the OSC32KCTRL, and GPIO functions are overridden on both pins.
When in external clock mode, the only XIN32 pin will be overridden and controlled by the OSC32KCTRL, while the
XOUT32 pin can still be used as a GPIO pin.
The XOSC32K is enabled by writing a '1' to the Enable bit in the 32.768 kHz External Crystal Oscillator Control
register (XOSC32K.ENABLE = 1). The XOSC32K is disabled by writing a '0' to the Enable bit in the 32.768 kHz
External Crystal Oscillator Control register (XOSC32K.ENABLE = 0). When disabling the XOSC32K it is important
only to write the Enable bit to '0' before additional changes are made to the XOSC32K register.
To enable the XOSC32K as a crystal oscillator, the XTALEN bit in the 32.768 kHz External Crystal Oscillator Control
register must be set (XOSC32K.XTALEN = 1). If XOSC32K.XTALEN is '0', the external clock input will be enabled.
The XOSC32K 32.768 kHz output is enabled by setting the 32.768 kHz Output Enable bit in the 32.768 kHz External
Crystal Oscillator Control register (XOSC32K.EN32K = 1). The XOSC32K also has a 1.024 kHz clock output. This
is enabled by setting the 1.024 kHz Output Enable bit in the 32.768 kHz External Crystal Oscillator Control register
(XOSC32K.EN1K = 1).
It is also possible to lock the XOSC32K configuration by setting the Write Lock bit in the 32.768 kHz External Crystal
Oscillator Control register (XOSC32K.WRTLOCK = 1). If set, the XOSC32K configuration is locked until a Power-On
Reset (POR) is detected.
The XOSC32K will behave differently in different sleep modes based on the settings of XOSC32K.RUNSTDBY,
XOSC32K.ONDEMAND, and XOSC32K.ENABLE. If XOSC32KCTRL.ENABLE = 0, the XOSC32K will be always
stopped. For XOS32KCTRL.ENABLE = 1, the table below is valid:
Table 15-1. XOSC32K Sleep Behavior
CPU Mode
XOSC32K.
XOSC32K.
Sleep Behavior of XOSC32K and CFD
RUNSTDBY
ONDEMAND
Active or Idle
-
0
Always run
Active or Idle
-
1
Run if requested by peripheral
Standby
1
0
Always run
Standby
1
1
Run if requested by peripheral
Standby
0
-
Run if requested by peripheral
As a crystal oscillator usually requires a very long start-up time, the 32.768 kHz External Crystal Oscillator will keep
running across resets when XOSC32K.ONDEMAND = 0, except for Power-on Reset (POR). After a reset or when
waking up from a sleep mode where the XOSC32K was disabled, the XOSC32K will need time to stabilize on the
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Datasheet
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PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
correct frequency, depending on the external crystal specification. This start-up time can be configured by changing
the Oscillator Start-Up Time bit group (XOSC32K.STARTUP) in the 32.768 kHz External Crystal Oscillator Control
register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the
digital logic.
Once the external clock or crystal oscillator is stable and ready to be used as a clock source, the XOSC32K
Ready bit in the Status register is set (STATUS.XOSC32KRDY = 1). The transition of STATUS.XOSC32KRDY
from '0' to '1' generates an interrupt if the XOSC32K Ready bit in the Interrupt Enable Set register is set
(INTENSET.XOSC32KRDY = 1).
The XOSC32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time Counter
(RTC). Before enabling the GCLK or the RTC module, the corresponding oscillator output must be enabled
(XOSC32K.EN32K or XOSC32K.EN1K) in order to ensure proper operation. In the same way, the GCLK or RTC
modules must be disabled before the clock selection is changed. For details on RTC clock configuration, refer also to
15.6.7 Real-Time Counter Clock Selection.
When the XOSC32K 1024 Hz clock output is used to clock the RTC (RTCCTRL.RTCSEL=4), ensure the XOSC32K
is in the 'Always run' ( as shown above in Table 15-1 XOSC32K Sleep Behavior) configuration.
15.6.3
Clock Failure Detection Operation
The Clock Failure Detector (CFD) allows the user to monitor the external clock or crystal oscillator signal provided
by the external oscillator (XOSC32K). The CFD detects failing operation of the XOSC32K clock with reduced latency,
and supports switching to a safe clock source in case of clock failure. The user can also switch from the safe clock
back to XOSC32K in case of recovery. The safe clock is derived from the OSCULP32K oscillator with a configurable
prescaler. This allows configuring the safe clock in order to fulfill the operative conditions of the microcontroller.
In sleep modes, CFD operation is automatically disabled when the external oscillator is not requested to run by a
peripheral. See the Sleep Behavior table above when this is the case.
The user interface registers allow to enable, disable, and configure the CFD. The Status register provides status
flags on failure and clock switch conditions. The CFD can optionally trigger an interrupt or an event when a failure is
detected.
Clock Failure Detection
The CFD is reset only at power-on (POR). The CFD does not monitor the XOSC32K clock when the oscillator is
disabled (XOSC32K.ENABLE = 0).
Before starting CFD operation, the user must start and enable the safe clock source (OSCULP32K oscillator).
CFD operation is started by writing a '1' to the CFD Enable bit in the External Oscillator Control register
(CFDCTRL.CFDEN). After starting or restarting the XOSC32K, the CFD does not detect failure until the start-up
time has elapsed. The start-up time is configured by the Oscillator Start-Up Time in the External Multipurpose Crystal
Oscillator Control register (XOSC32K.STARTUP). Once the XOSC32K Start-Up Time is elapsed, the XOSC32K clock
is constantly monitored.
During a period of 4 safe clocks (monitor period), the CFD watches for a clock activity from the XOSC32K. There
must be at least one rising and one falling XOSC32K clock edge during 4 safe clock periods to meet non-failure
conditions. If no or insufficient activity is detected, the failure status is asserted: The Clock Failure Detector status bit
in the Status register (STATUS.CLKFAIL) and the Clock Failure Detector interrupt flag bit in the Interrupt Flag register
(INTFLAG.CLKFAIL) are set. If the CLKFAIL bit in the Interrupt Enable Set register (INTENSET.CLKFAIL) is set, an
interrupt is generated as well. If the Event Output enable bit in the Event Control register (EVCTRL.CFDEO) is set, an
output event is generated, too.
After a clock failure was issued the monitoring of the XOSC32K clock is continued, and the Clock Failure Detector
status bit in the Status register (STATUS.CLKFAIL) reflects the current XOSC32K activity.
If the CFD is disabled (CFDCTRL.CFDEN=0) the XOSC32K must be disabled before re-enabling the CFD. Not
following this guideline can lead to a false clock failure detection.
Clock Switch
When a clock failure is detected, the XOSC32K clock is replaced by the safe clock in order to maintain an active
clock during the XOSC32K clock failure. The safe clock source is the OSCULP32K oscillator clock. Both 32.768
kHz and 1.024 kHz outputs of the XOSC32K are replaced by the respective OSCULP32K 32.768 kHz and 1.024
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PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
kHz outputs. The safe clock source can be scaled down by a configurable prescaler to ensure that the safe clock
frequency does not exceed the operating conditions selected by the application. When the XOSC32K clock is
switched to the safe clock, the Clock Switch bit in the Status register (STATUS.CLKSW) is set.
When the CFD has switched to the safe clock, the XOSC32K is not disabled. If desired, the application must take
the necessary actions to disable the oscillator. The application must also take the necessary actions to configure the
system clocks to continue normal operations. In the case the application can recover the XOSC32K, the application
can switch back to the XOSC32K clock by writing a '1' to Switch Back Enable bit in the Clock Failure Control register
(CFDCTRL.SWBACK). Once the XOSC32K clock is switched back, the Switch Back bit (CFDCTRL.SWBACK) is
cleared by hardware.
Prescaler
The CFD has an internal configurable prescaler to generate the safe clock from the OSCULP32K oscillator. The
prescaler size allows to scale down the OSCULP32K oscillator so the safe clock frequency is not higher than the
XOSC32K clock frequency monitored by the CFD. The maximum division factor is 2.
The prescaler is applied on both outputs (32.768 kHz and 1.024 kHz) of the safe clock.
Example 15-1.
For an external crystal oscillator at 32.768 kHz and the OSCULP32K frequency is 32.768 kHz, the
XOSC32K.CFDPRESC should be set to 0 for a safe clock of equal frequency.
Event
If the Event Output Enable bit in the Event Control register (EVCTRL.CFDEO) is set, the CFD clock failure will be
output on the Event Output. When the CFD is switched to the safe clock, the CFD clock failure will not be output on
the Event Output.
Sleep Mode
The CFD is halted depending on configuration of the XOSC32K and the peripheral clock request. For further details,
refer to the Sleep Behavior table above. The CFD interrupt can be used to wake up the device from sleep modes.
15.6.4
32.768 kHz Internal Oscillator (OSC32K) Operation
The OSC32K provides a tunable, low-speed, and low-power clock source.
At reset, the OSC32K is disabled. It can be enabled by setting the Enable bit in the 32.768 kHz Internal Oscillator
Control register (OSC32K.ENABLE = 1). The OSC32K is disabled by clearing the Enable bit in the 32.768 kHz
Internal Oscillator Control register (OSC32K.ENABLE = 0).
The frequency of the OSC32K oscillator is controlled by OSC32K.CALIB. Before using the OSC32K, this Calibration
field must be loaded with production calibration values from the NVM Software Calibration Area. When writing the
Calibration bits, the user must wait for the STATUS.OSC32KRDY bit to go high before the new value is committed to
the oscillator.
The OSC32K has a 32.768 kHz output which is enabled by setting the EN32K bit in the 32.768 kHz Internal Oscillator
Control register (OSC32K.EN32K = 1). The OSC32K also has a 1.024 kHz clock output. This is enabled by setting
the EN1K bit in the 32.768 kHz Internal Oscillator Control register (OSC32K.EN1K).
The OSC32K will behave differently in different sleep modes based on the settings of OSC32K.RUNSTDBY,
OSC32K.ONDEMAND, and OSC32K.ENABLE. If OSC32KCTRL.ENABLE = 0, the OSC32K will be always stopped.
For OS32KCTRL.ENABLE = 1, this table is valid:
Table 15-2. OSC32K Sleep Behavior
CPU Mode
OSC32KCTRL.RUNST
DBY
OSC32KCTRL.ONDEM Sleep Behavior
AND
Active or Idle
-
0
Always run
Active or Idle
-
1
Run if requested by peripheral
Standby
1
0
Always run
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PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
...........continued
CPU Mode
OSC32KCTRL.RUNST
DBY
OSC32KCTRL.ONDEM Sleep Behavior
AND
Standby
1
1
Run if requested by peripheral
Standby
0
-
Run if requested by peripheral
The OSC32K requires a start-up time. For this reason, OSC32K will keep running across resets when
OSC32K.ONDEMAND = 0, except for Power-on Reset (POR).
After such a reset, or when waking up from a Sleep mode where the OSC32K was disabled, the OSC32K will need
time to stabilize on the correct frequency.
This startup time can be configured by changing the Oscillator Start-Up Time bit group (OSC32K.STARTUP) in the
OSC32K Control register. During the start-up time, the oscillator output is masked to ensure that no unstable clock
propagates to the digital logic.
Once the oscillator is stable and ready to be used as a clock source, the OSC32K Ready bit in the Status register
is set (STATUS.OSC32KRDY=1). The transition of STATUS.OSC32KRDY from '0' to '1' generates an interrupt if the
OSC32K Ready bit in the Interrupt Enable Set register is set (INTENSET.OSC32KRDY = 1).
The OSC32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time Counter (RTC).
Before enabling the GCLK or the RTC module, the corresponding oscillator output must be enabled (OSC32K.EN32K
or OSC32K.EN1K) in order to ensure proper operation. In the same way, the GCLK or RTC modules must be
disabled before the clock selection is changed.
15.6.5
32.768 kHz Ultra-Low Power Internal Oscillator (OSCULP32K) Operation
The OSCULP32K provides a tunable, low-speed, and ultra-low power clock source. The OSCULP32K is factorycalibrated under typical voltage and temperature conditions. The OSCULP32K should be preferred to the OSC32K
whenever the power requirements are prevalent over frequency stability and accuracy.
The OSCULP32K is enabled by default after a Power-on Reset (POR) and will always run except during POR.
The frequency of the OSCULP32K Oscillator is controlled by the value in the Calibration bits in the 32.768 kHz
Ultra-Low Power Internal Oscillator Control register (OSCULP32K.CALIB). This data is used to compensate for
process variations.
OSCULP32K.CALIB is automatically loaded from Flash Factory Calibration during start-up. The calibration value can
be overridden by the user by writing to OSCULP32K.CALIB.
It is also possible to lock the OSCULP32K configuration by setting the Write Lock bit in the 32.768 kHz Ultra-Low
Power Internal Oscillator Control register (OSCULP32K.WRTLOCK = 1). If set, the OSCULP32K configuration is
locked until a Power-on Reset (POR) is detected.
The OSCULP32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time Counter
(RTC). To ensure proper operation, the GCLK or RTC modules must be disabled before the clock selection is
changed.
15.6.6
Watchdog Timer Clock Selection
The Watchdog Timer (WDT) uses the internal 1.024 kHz OSCULP32K output clock. This clock is running all the time
and internally enabled when requested by the WDT module.
15.6.7
Real-Time Counter Clock Selection
Before enabling the RTC module, the RTC clock must be selected first. All oscillator outputs are valid as RTC
clock. The selection is done in the RTC Control register (RTCCTRL). To ensure a proper operation, it is highly
recommended to disable the RTC module first, before the RTC clock source selection is changed.
15.6.8
Interrupts
The OSC32KCTRL has the following interrupt sources:
•
XOSC32KRDY - 32.768 kHz Crystal Oscillator Ready: A 0-to-1 transition on the STATUS.XOSC32KRDY bit is
detected
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PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
•
•
CLKFAIL - Clock Failure Detector: A 0-to-1 transition on the STATUS.CLKFAIL bit is detected
OSC32KRDY - 32.768 kHz Internal Oscillator Ready: A 0-to-1 transition on the STATUS.OSC32KRDY bit is
detected
All these interrupts are synchronous wake-up source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be enabled individually by setting
the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by setting the corresponding
bit in the Interrupt Enable Clear register (INTENCLR). As both INTENSET and INTENCLR always reflect the same
value, the status of interrupt enablement can be read from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the OSC32KCTRL is
reset. See the INTFLAG register for details on how to clear interrupt flags.
The OSC32KCTRL has one common interrupt request line for all the interrupt sources. The user must read the
INTFLAG register to determine which interrupt condition is present. Refer to the INTFLAG register for details.
Note: Interrupts must be globally enabled for interrupt requests to be generated.
15.6.9
Events
The CFD can generate the following output event:
• Clock Failure Detector (CLKFAIL): Generated when the Clock Failure Detector status bit is set in the Status
register (STATUS.CLKFAIL). The CFD event is not generated when the Clock Switch bit (STATUS.SWBACK) in
the Status register is set.
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.CFDEO) enables the CFD output event.
Writing a '0' to this bit disables the CFD output event. Refer to the Event System chapter for details on configuring the
event system.
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
15.7
Offset
Register Summary
Name
Bit Pos.
7
6
5
4
3
7:0
0x00
INTENCLR
INTENSET
INTFLAG
STATUS
0x10
RTCCTRL
0x14
XOSC32K
0x16
0x17
CFDCTRL
EVCTRL
0x18
OSC32K
0x1C
OSCULP32K
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
7:0
7:0
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
CLKSW
OSC32KRDY
XOSC32KRD
Y
CLKFAIL
OSC32KRDY
XOSC32KRD
Y
CLKFAIL
OSC32KRDY
XOSC32KRD
Y
CLKFAIL
OSC32KRDY
XOSC32KRD
Y
RTCSEL[2:0]
ONDEMAND RUNSTDBY
EN1K
WRTLOCK
ONDEMAND RUNSTDBY
EN32K
EN1K
XTALEN
ENABLE
STARTUP[2:0]
CFDPRESC
SWBACK
EN32K
ENABLE
STARTUP[2:0]
EN1K
CALIB[4:0]
EN32K
WRTLOCK
CFDEN
CFDEO
CALIB[6:0]
WRTLOCK
© 2021 Microchip Technology Inc.
and its subsidiaries
CLKFAIL
15:8
23:16
31:24
7:0
0x0C
0
15:8
23:16
31:24
7:0
0x08
1
15:8
23:16
31:24
7:0
0x04
2
Datasheet
DS60001638D-page 115
PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
15.7.1
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x00
0x00000000
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
CLKFAIL
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
1
0
OSC32KRDY XOSC32KRDY
R/W
R/W
0
0
Bit 2 – CLKFAIL XOSC32K Clock Failure Detection Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the XOSC32K Clock Failure Interrupt Enable bit, which disables the XOSC32K Clock
Failure interrupt.
Value
Description
0
The XOSC32K Clock Failure Detection is disabled.
1
The XOSC32K Clock Failure Detection is enabled. An interrupt request will be generated when the
XOSC32K Clock Failure Detection interrupt flag is set.
Bit 1 – OSC32KRDY OSC32K Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the OSC32K Ready Interrupt Enable bit, which disables the OSC32K Ready interrupt.
Value
Description
0
The OSC32K Ready interrupt is disabled.
1
The OSC32K Ready interrupt is enabled.
Bit 0 – XOSC32KRDY XOSC32K Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the XOSC32K Ready Interrupt Enable bit, which disables the XOSC32K Ready
interrupt.
Value
Description
0
The XOSC32K Ready interrupt is disabled.
1
The XOSC32K Ready interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 116
PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
15.7.2
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x04
0x00000000
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
CLKFAIL
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
1
0
OSC32KRDY XOSC32KRDY
R/W
R/W
0
0
Bit 2 – CLKFAIL XOSC32K Clock Failure Detection Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the XOSC32K Clock Failure Interrupt Enable bit, which enables the XOSC32K Clock
Failure interrupt.
Value
Description
0
The XOSC32K Clock Failure Detection is disabled.
1
The XOSC32K Clock Failure Detection is enabled. An interrupt request will be generated when the
XOSC32K Clock Failure Detection interrupt flag is set.
Bit 1 – OSC32KRDY OSC32K Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the OSC32K Ready Interrupt Enable bit, which enables the OSC32K Ready interrupt.
Value
Description
0
The OSC32K Ready interrupt is disabled.
1
The OSC32K Ready interrupt is enabled.
Bit 0 – XOSC32KRDY XOSC32K Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the XOSC32K Ready Interrupt Enable bit, which enables the XOSC32K Ready
interrupt.
Value
Description
0
The XOSC32K Ready interrupt is disabled.
1
The XOSC32K Ready interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 117
PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
15.7.3
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
INTFLAG
0x08
0x00000000
–
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
CLKFAIL
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
1
0
OSC32KRDY XOSC32KRDY
R/W
R/W
0
0
Bit 2 – CLKFAIL XOSC32K Clock Failure Detection
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the XOSC32K Clock Failure Detection bit in the Status register
(STATUS.CLKFAIL) and will generate an interrupt request if INTENSET.CLKFAIL is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the XOSC32K Clock Failure Detection flag.
Bit 1 – OSC32KRDY OSC32K Ready
This flag is cleared by writing a '1' to it.
This flag is set by a zero-to-one transition of the OSC32K Ready bit in the Status register (STATUS.OSC32KRDY),
and will generate an interrupt request if INTENSET.OSC32KRDY=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the OSC32K Ready interrupt flag.
Bit 0 – XOSC32KRDY XOSC32K Ready
This flag is cleared by writing a '1' to it.
This flag is set by a zero-to-one transition of the XOSC32K Ready bit in the Status register (STATUS.XOSC32KRDY),
and will generate an interrupt request if INTENSET.XOSC32KRDY=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the XOSC32K Ready interrupt flag.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 118
PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
15.7.4
Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x0C
0x00000000
–
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
CLKSW
R
0
2
CLKFAIL
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
1
0
OSC32KRDY XOSC32KRDY
R
R
0
0
Bit 3 – CLKSW XOSC32K Clock Switch
Value
Description
0
XOSC32K is not switched and provided the crystal oscillator.
1
XOSC32K is switched to be provided by the safe clock.
Bit 2 – CLKFAIL XOSC32K Clock Failure Detector
Value
Description
0
XOSC32K is passing failure detection.
1
XOSC32K is not passing failure detection.
Bit 1 – OSC32KRDY OSC32K Ready
Value
Description
0
OSC32K is not ready.
1
OSC32K is stable and ready to be used as a clock source.
Bit 0 – XOSC32KRDY XOSC32K Ready
Value
Description
0
XOSC32K is not ready.
1
XOSC32K is stable and ready to be used as a clock source.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 119
PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
15.7.5
RTC Clock Selection Control
Name:
Offset:
Reset:
Property:
Bit
RTCCTRL
0x10
0x00000000
PAC Write-Protection
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RTCSEL[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
Bits 2:0 – RTCSEL[2:0] RTC Clock Source Selection
These bits select the source for the RTC.
Value
Name
Description
0x0
ULP1K
1.024 kHz from 32.768 kHz internal ULP oscillator
0x1
ULP32K
32.768 kHz from 32.768 kHz internal ULP oscillator
0x2
OSC1K
1.024 kHz from 32.768 kHz internal oscillator
0x3
OSC32K
32.768 kHz from 32.768 kHz internal oscillator
0x4
XOSC1K
1.024 kHz from 32.768 kHz external oscillator
0x5
XOSC32K
32.768 kHz from 32.768 kHz external crystal oscillator
0x6
Reserved
0x7
Reserved
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 120
PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
15.7.6
32.768 kHz External Crystal Oscillator (XOSC32K) Control
Name:
Offset:
Reset:
Property:
Bit
XOSC32K
0x14
0x0080
PAC Write-Protection
15
14
13
Access
Reset
Bit
Access
Reset
7
ONDEMAND
R/W
1
6
RUNSTDBY
R/W
0
5
12
WRTLOCK
R/W
0
11
4
EN1K
R/W
0
3
EN32K
R/W
0
10
R/W
0
9
STARTUP[2:0]
R/W
0
2
XTALEN
R/W
0
1
ENABLE
R/W
0
8
R/W
0
0
Bit 12 – WRTLOCK Write Lock
This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration.
Value
Description
0
The XOSC32K configuration is not locked.
1
The XOSC32K configuration is locked.
Bits 10:8 – STARTUP[2:0] Oscillator Start-Up Time
This bit field configures the time after which the XOSC32K clock will be propagated in the design. In order to let a
stable clock propagate in the design, the right STARTUP time should be configured after considering the external
crystal characteristics and the information provided in the 43.12 External 32 kHz Crystal Oscillator (XOSC32K)
Electrical Specifications section of the 43. Electrical Characteristics 85℃ chapter. The actual startup time is the
number of selected OSCULP32K cycles + 3 XOSC32K cycles.
Table 15-3. Start-up Time for 32.768 kHz External Crystal Oscillator
STARTUP[2:0] Number of OSCULP32K Clock
Cycles
Number of XOSC32K Clock
Cycles
Approximate Equivalent Time
[s]
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
3
3
3
3
3
3
3
3
0.000031
0.00098
0.06
0.125
0.5
1
2
4
1
32
2048
4096
16384
32768
65536
131072
Bit 7 – ONDEMAND On Demand Control
This bit controls how the XOSC32K behaves when a peripheral clock request is detected. For details, refer to
XOSC32K Sleep Behavior.
Bit 6 – RUNSTDBY Run in Standby
This bit controls how the XOSC32K behaves during standby sleep mode. For details, refer to XOSC32K Sleep
Behavior.
Bit 4 – EN1K 1.024 kHz Output Enable
Value
Description
0
The 1.024 kHz output is disabled.
1
The 1.024 kHz output is enabled, and available internally only for RTC.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 121
PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
Bit 3 – EN32K 32.768 kHz Output Enable
Value
Description
0
The 32.768 kHz output is disabled.
1
The 32.768 kHz output is enabled, and can be routed to GCLK/GCLK_IO.
Bit 2 – XTALEN Crystal Oscillator Enable
This bit controls the connections between the I/O pads and the external clock or crystal oscillator.
Value
Description
0
External clock connected on XIN32. XOUT32 can be used as general-purpose I/O.
1
Crystal connected to XIN32/XOUT32.
Bit 1 – ENABLE Oscillator Enable
Value
Description
0
The oscillator is disabled.
1
The oscillator is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 122
PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
15.7.7
Clock Failure Detector Control
Name:
Offset:
Reset:
Property:
Bit
CFDCTRL
0x16
0x00
PAC Write-Protection
7
6
5
4
3
Access
Reset
2
CFDPRESC
R/W
0
1
SWBACK
R/W
0
0
CFDEN
R/W
0
Bit 2 – CFDPRESC Clock Failure Detector Prescaler
This bit selects the prescaler for the Clock Failure Detector.
Value
Description
0
The CFD safe clock frequency is the OSCULP32K frequency
1
The CFD safe clock frequency is the OSCULP32K frequency divided by 2
Bit 1 – SWBACK Clock Switch Back
This bit clontrols the XOSC32K output switch back to the external clock or crystal oscillator in case of clock recovery.
Value
Description
0
The clock switch is disabled.
1
The clock switch is enabled. This bit is reset when the XOSC32K output is switched back to the
external clock or crystal oscillator.
Bit 0 – CFDEN Clock Failure Detector Enable
This bit selects the Clock Failure Detector state.
Value
Description
0
The CFD is disabled.
1
The CFD is enabled.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 123
PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
15.7.8
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x17
0x00
PAC Write-Protection
7
6
5
4
3
Access
Reset
2
1
0
CFDEO
R/W
0
Bit 0 – CFDEO Clock Failure Detector Event Out Enable
This bit controls whether the Clock Failure Detector event output is enabled and an event will be generated when the
CFD detects a clock failure.
Value
Description
0
Clock Failure Detector Event output is disabled, no event will be generated.
1
Clock Failure Detector Event output is enabled, an event will be generated.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 124
PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
15.7.9
32.768 kHz Internal Oscillator (OSC32K) Control
Name:
Offset:
Reset:
Property:
Bit
OSC32K
0x18
0x003F 0080 (Writing action by User required)
PAC Write-Protection
31
30
29
28
27
26
25
24
23
22
21
20
18
17
16
R/W
0
R/W
1
R/W
1
19
CALIB[6:0]
R/W
1
R/W
1
R/W
1
R/W
1
14
13
12
WRTLOCK
R/W
0
11
10
8
R/W
0
9
STARTUP[2:0]
R/W
0
4
3
EN1K
R/W
0
2
EN32K
R/W
0
1
ENABLE
R/W
0
Access
Reset
Bit
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
7
ONDEMAND
R/W
1
6
RUNSTDBY
R/W
0
5
R/W
0
0
Bits 22:16 – CALIB[6:0] Oscillator Calibration
These bits control the oscillator calibration. The calibration values must be loaded by the user from the NVM Software
Calibration Area.
Bit 12 – WRTLOCK Write Lock
This bit locks the OSC32K register for future writes, effectively freezing the OSC32K configuration.
Value
Description
0
The OSC32K configuration is not locked.
1
The OSC32K configuration is locked.
Bits 10:8 – STARTUP[2:0] Oscillator Start-Up Time
These bits select start-up time for the oscillator.
The OSCULP32K oscillator is used as input clock to the start-up counter.
Table 15-4. Start-Up Time for 32.768 kHz Internal Oscillator
STARTUP[2:0]
Number of OSC32K clock cycles
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
3
4
6
10
18
34
66
130
Bit 7 – ONDEMAND On Demand Control
This bit controls how the OSC32K behaves when a peripheral clock request is detected. For details, refer to OSC32K
Sleep Behavior.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 125
PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
Bit 6 – RUNSTDBY Run in Standby
This bit controls how the OSC32K behaves during standby sleep mode. For details, refer to OSC32K Sleep Behavior.
Bit 3 – EN1K 1.024 kHz Output Enable
Value
Description
0
The 1.024 kHz output is disabled.
1
The 1.024 kHz output is enabled, and available internally only for RTC.
Bit 2 – EN32K 32.768 kHz Output Enable
Value
Description
0
The 32.768 kHz output is disabled.
1
The 32.768 kHz output is enabled, and can be routed to GCLK/GCLK_IO.
Bit 1 – ENABLE Oscillator Enable
Value
Description
0
The oscillator is disabled.
1
The oscillator is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 126
PIC32CM MC00 Family
32.768 kHz Oscillators Controller (OSC32KCTR...
15.7.10 32.768 kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
Name:
Offset:
Reset:
Property:
Bit
OSCULP32K
0x1C
0x0000XX06
PAC Write-Protection
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
WRTLOCK
R/W
0
14
13
12
11
9
8
R/W
x
R/W
x
10
CALIB[4:0]
R/W
x
R/W
x
R/W
x
7
6
4
3
2
EN1K
R/W
1
1
EN32K
R/W
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
5
Access
Reset
Bit 15 – WRTLOCK Write Lock
This bit locks the OSCULP32K register for future writes to fix the OSCULP32K configuration.
Value
Description
0
The OSCULP32K configuration is not locked.
1
The OSCULP32K configuration is locked.
Bits 12:8 – CALIB[4:0] Oscillator Calibration
These bits control the oscillator calibration.
These bits are automatically loaded from the Flash Factory Calibration at startup.
Bit 2 – EN1K 1kHz Output Enable
Value
Description
0
The 1kHz output is disabled
1
The 1kHz output is enabled.
Bit 1 – EN32K
Value
Description
0
The 32kHz output is disabled.
1
The 32kHz output is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 127
PIC32CM MC00 Family
Power Manager (PM)
16.
Power Manager (PM)
16.1
Overview
The Power Manager (PM) controls the sleep modes of the device.
Various sleep modes are provided in order to fit power consumption requirements. This enables the PM to stop
unused modules in order to save power. In active mode, the CPU is executing application code. When the device
enters a sleep mode, program execution is stopped and some modules and clock domains are automatically
switched off by the PM according to the sleep mode. The application code decides which sleep mode to enter
and when. Interrupts from enabled peripherals and all enabled reset sources can restore the device from a sleep
mode to active mode.
16.2
Features
•
16.3
Power management control:
– Sleep modes: Idle, Standby
Block Diagram
Figure 16-1. PM Block Diagram
POWER MANAGER
SLEEP MODE
CONTROLLER
MAIN CLOCK
CONTROLLER
SUPPLY
CONTROLLER
SLEEPCFG
POWER DOMAIN
CONTROLLER
STDBYCFG
16.4
Peripheral Dependencies
Peripheral
Base Address
PM
AHB CLK
APB CLK
Generic CLK
PAC
Events
DMA
Enabled at reset
Enabled at reset
Index
Index
Prot at reset
User
Generator
Index
-
Y
-
1
N
-
-
-
IRQ
0x40000400
0
Sleep Walking
16.5
Functional Description
16.5.1
Terminology
-
The following is a list of terms used to describe the Power Managemement features of this microcontroller.
16.5.1.1 Sleep Modes
The device can be set in a sleep mode. In Sleep mode, the CPU is stopped and the peripherals are either active or
idle, according to the Sleep mode depth:
•
Idle Sleep mode: The CPU is stopped. Synchronous clocks are stopped except when requested. The logic is
retained.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 128
PIC32CM MC00 Family
Power Manager (PM)
•
16.5.2
Standby Sleep mode: The CPU is stopped as well as the peripherals.
Principle of Operation
In active mode, all clock domains and power domains are active, allowing software execution and peripheral
operation. The PM Sleep Mode Controller allows to save power by choosing between different sleep modes
depending on application requirements, see 16.5.3.3 Sleep Mode Controller.
The PM Power Domain Controller allows to reduce the power consumption in standby mode even further.
16.5.3
Basic Operation
16.5.3.1 Initialization
After a Power-on Reset (POR), the PM is enabled and the device is in Active mode.
16.5.3.2 Enabling, Disabling and Resetting
The PM is always enabled and can not be reset.
16.5.3.3 Sleep Mode Controller
A Sleep mode is entered by executing the Wait For Interrupt instruction (WFI). The Sleep Mode bits in the Sleep
Configuration register (SLEEPCFG.SLEEPMODE) select the level of the Sleep mode.
Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG register due to
bridges. Software must ensure that the SLEEPCFG register reads the desired value before issuing a WFI instruction.
Table 16-1. Sleep Mode Entry and Exit Table
Mode
Mode Entry
Wake-Up Sources
IDLE
SLEEPCFG.SLEEPMODE = IDLE
Synchronous (2), asynchronous (1)
STANDBY
SLEEPCFG.SLEEPMODE = STANDBY
Synchronous(3), Asynchronous(1)
Notes:
1. Asynchronous: interrupt generated on GCLK generic clock, external clock, or external event.
2. Synchronous: interrupt generated on the APB clock.
3. Synchronous interrupt only for peripherals configured to run in standby.
Note: The type of wake-up sources (synchronous or asynchronous) is given in each module interrupt section.
The sleep modes (idle, standby) and their effect on the clocks activity, the regulator and the SRAM state are
described in the table and the sections below.
Table 16-2. Sleep Mode Overview
Mode
CPU
clock
AHB/A
PB
clocks
Main
clock
GCLK0
clock
IDLE
Stop
Run(1)
Run
Run
STANDBY
Stop
Stop (4)
© 2021 Microchip Technology Inc.
and its subsidiaries
Stop
(4)
GCLK1-8
clocks
Clock Sources
ONDEMAND
=0
ONDEMAND
=1
Regulator
SRAM
Run
Run/Stop (3)
Main
Normal
LPVREG
Low
Power
Run/Stop
(2)
Stop if RUNSTDBY =
0
Stop if RUNSTDBY = 0
Stop/Run if
RUNSTDBY = 1 (5)
Run if
Stop/Run if
RUNSTDBY = RUNSTDBY =
1
1 (6)
Datasheet
(7)
(8)
DS60001638D-page 129
PIC32CM MC00 Family
Power Manager (PM)
Notes:
1. The AHB/APB clocks are running up to MCLK, and then provided only to the IPs requesting them. For the
other IPs not requesting the clocks, they are gated at MCLK output.
2. Each GCLK1 to GCLK8 is running if the associated generated clock is requested by at least one IP. It is
stopped if no IP is requesting this clock.
3. The clock source is running if the clock is requested by at least one GCLK Generator. It is stopped if no GCLK
Generator is requesting this clock and will be restarted as soon as an IP requests a clock coming from a GCLK
fed by this clock source.
4. The AHB/APB clocks are stopped, except if requested by at least one IP, and in this case, only provided to
this/these IP(s) through GCLK0 and MCLK.
5. Each GCLK generators is stopped, except if the clock it generates is requested by at least one IP.
6. Each Clock Source is stopped, except if the clock it generates is requested by at least one GCLK Generator.
7. Regulator state is programmable by using STDBYCFG.VREGSMOD bits.
8. SRAM state is programmable by using STDBYCFG.BBIASHS bit.
16.5.3.3.1 IDLE Mode
The IDLE mode allows power optimization with the fastest wake-up time.
The CPU is stopped.
The clock source feeding the GCLK generator 0, the GCLK generator 0, and the MCLK are kept active. The
AHB/APB clocks are gated at the MCLK output, unless requested by a peripheral.
The other clock sources and the GCLK generators can be running or stopped depending on each clock source
ONDEMAND bit, and depending on the peripherals requesting these clocks.
If an AHB/APB clock is masked in MCLK.AHBMASK or MCLK.APBxMASK, then it is gated at the output of the MCLK
and not provided to the related peripheral (regardless of the related peripheral requesting it or not).
•
•
Entering IDLE mode: The IDLE mode is entered by setting SLEEPCFG.SLEEPMODE = IDLE and by executing
the WFI instruction. Additionally, if the SLEEPONEXIT bit in the ARM Cortex System Control register (SCR) is
set, the IDLE mode will also be entered when the CPU exits the lowest priority ISR. This mechanism can be
useful for applications that only require the processor to run when an interrupt occurs. Before entering the IDLE
mode, the user must configure the Sleep Configuration register.
Exiting IDLE mode: The processor wakes the system up when it detects any non-masked interrupt with sufficient
priority to cause exception entry. The system goes back to the ACTIVE mode. The CPU and affected modules
are restarted.
In IDLE mode, the regulator and SRAM operate in normal mode.
16.5.3.3.2 Standby Mode
The Standby mode is the lowest power configuration while keeping the state of the logic and the content of the
SRAM.
This mode depends on (As depicted in the previous table):
•
•
•
The peripherals running in standby and requesting their asynchronous GCLK clock or their synchronous
AHB/APB clock
The RUNSTDBY bit of the GCLK generators
The RUNSTDBY/ONDEMAND bit combination of the clock sources
Each clock source and GCLK generator can be:
•
•
•
Stopped during the whole standby
Running during the whole standby
Automatically woken up and switched off depending on the clocks requested by the peripherals during standby
(SleepWalking). For example a peripheral can run during standby and request its GCLK asynchronous clock,
which will wake up the related GCLK and clock source. Another peripheral may request its APB clock, which will
wake up the MCLK, GCLK generator 0 and the related clock source running. (In this case the other AHB/APB
clocks are kept gated at the MCLK output).
As described above, depending on the configuration, the current consumption of the device in Standby mode can be
slightly different.
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and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Power Manager (PM)
All features that don’t require CPU intervention are supported in Standby mode. Here are examples:
•
•
•
•
Autonomous peripherals features.
Features relying on Event System allowing autonomous communication between peripherals.
Features relying on on-demand clock.
DMA transfers.
Entering Standby mode: This mode is entered by setting SLEEPCFG.SLEEPMODE = STANDBY and by executing
the WFI instruction. The SLEEPONEXIT feature is also available as in IDLE mode.
Exiting Standby mode: Any peripheral able to generate an asynchronous interrupt can wake up the system. For
example, a peripheral running on a GCLK clock can trigger an interrupt. When the enabled asynchronous wake-up
event occurs and the system is woken up, the device will either execute the interrupt service routine or continue the
normal program execution according to the Priority Mask Register (PRIMASK) configuration of the CPU.
16.5.4
Advanced Features
16.5.4.1 SRAM Automatic Low-Power Mode
The SRAM is by default put in Low-Power mode (back-biased) if the device is in Standby Sleep mode.
This behavior can be changed by configuring the Back Bias bit in the Standby Configuration register
(STDBYCFG.BBIASHS), refer to the table below for details.
Note: In Standby Sleep mode, the SRAM is put in Low-Power mode by default. This means that the SRAM is
back-biased, and the DMAC cannot access it. The DMAC can only access the SRAM when it is not back biased
(PM.STDBYCFG.BBIASHS=0x0). When the SysTick Overflow Interrupt is enabled the RAM Back Bias Control must
be disabled (PM->STDBYCFG.bit.BBIASHS = 0) before entering Standby sleep mode.
Table 16-3. RAM Back-Biasing Mode
STBYCDFG.BBIASHS
SRAM
0x0
No Back Biasing
SRAM is not back-biased if the device is in Standby Sleep mode.
0x1
Standby Back Biasing mode
SRAM is back-biased if the device is in Standby Sleep mode.
16.5.4.2 Regulator Automatic Low-Power Mode
In Standby mode, the PM selects either the main or the low-power voltage regulator to supply the VDDCORE. By
default the low-power voltage regulator is used.
If a sleepwalking task is working on either asynchronous clocks (generic clocks) or synchronous clock (APB/AHB
clocks), the main voltage regulator is used. This behavior can be changed by writing the Voltage Regulator Standby
Mode bits in the Standby Configuration register (STDBYCFG.VREGSMOD). Refer to the following table for details.
Table 16-4. Regulator State in Sleep Mode
16.5.5
Sleep
Mode
STDBYCFG.
VREGSMOD
SleepWalking
Regulator state for VDDCORE
Active
-
-
main-voltage regulator
Idle
-
-
main-voltage regulator
Standby
0x0: Auto
No
low-power regulator
Yes
main-voltage regulator
0x1: Performance
-
main-voltage regulator
0x2: LP
-
low-power regulator
Sleep Mode Operation
The Power Manager is always active.
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Datasheet
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PIC32CM MC00 Family
Power Manager (PM)
16.6
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
...
0x07
Reserved
SLEEPCFG
7:0
0x08
STDBYCFG
7
6
5
4
3
2
1
0
SLEEPMODE[2:0]
Reserved
7:0
15:8
VREGSMOD[1:0]
© 2021 Microchip Technology Inc.
and its subsidiaries
BBIASHS
Datasheet
DS60001638D-page 132
PIC32CM MC00 Family
Power Manager (PM)
16.6.1
Sleep Configuration
Name:
Offset:
Reset:
Property:
Bit
SLEEPCFG
0x01
0x00
PAC Write-Protection
7
6
5
4
3
Access
Reset
2
R/W
0
1
SLEEPMODE[2:0]
R/W
0
0
R/W
0
Bits 2:0 – SLEEPMODE[2:0] Sleep Mode
Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG register due to
bridges. Software has to make sure the SLEEPCFG register reads the wanted value before issuing Wait For Interrupt
(WFI) instruction.
Value
Name
0x0
0x1
0x2
0x3
0x4
0x5 - 0x7
Reserved
Reserved
IDLE
Reserved
STANDBY
Reserved
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Datasheet
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PIC32CM MC00 Family
Power Manager (PM)
16.6.2
Standby Configuration
Name:
Offset:
Reset:
Property:
Bit
STDBYCFG
0x08
0x0400
PAC Write-Protection
15
14
13
12
11
10
BBIASHS
R/W
1
9
8
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
7
6
VREGSMOD[1:0]
R/W
R/W
0
0
Bit 10 – BBIASHS Back Bias for SRAM
Refer to 16.5.4.1 SRAM Automatic Low-Power Mode for details.
Value
Description
0
No Back Biasing Mode
1
Standby Back Biasing Mode
Bits 7:6 – VREGSMOD[1:0] VREG Switching Mode
Refer to for 16.5.4.2 Regulator Automatic Low-Power Mode details.
Value
Name
Description
0x0
AUTO
Automatic Mode
0x1
PERFORMANCE
Performance oriented
0x2
LP
Low-Power consumption oriented
0x3
Reserved
Reserved
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Datasheet
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PIC32CM MC00 Family
Supply Controller (SUPC)
17.
Supply Controller (SUPC)
17.1
Overview
The Supply Controller (SUPC) manages the voltage reference and power supply of the device. The SUPC controls
the voltage regulators for the core (VDDCORE) domain. It sets the voltage regulators according to the sleep modes,
or the user configuration.
The SUPC embeds two Brown-out Detectors: BODVDD monitors the voltage applied to the device (VDD) and
BODCORE monitors the internal voltage to the core (VDDCORE). The BOD can monitor the supply voltage
continuously (continuous mode) or periodically (sampling mode).
The SUPC generates also a selectable reference voltage which can be used by analog modules, such as the ADC,
SDADC or DAC.
17.2
Features
•
•
•
•
Voltage Regulator System
– Main voltage regulator: LDO in Active mode (MAINVREG)
– Low-power voltage regulator in Standby mode (LPVREG)
Voltage Reference System
– Reference voltage for ADC, SDADC and DAC
VDD Brown-out Detector (BODVDD)
– Programmable threshold
– Threshold value loaded from NVM User Row at startup
– Triggers resets or interrupts. Action loaded from NVM User Row
– Operating modes:
• Continuous mode
• Sampled mode for low-power applications with programmable sample frequency
– Hysteresis value from Flash User Calibration
VDDCORE Brown-out Detector (BODCORE)
– Internal non-configurable Brown-out Detector
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and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Supply Controller (SUPC)
17.3
Block Diagram
Figure 17-1. SUPC Block Diagram
VDD
BODVDD
BODVDD
BODCORE
Main VREG
BODCORE
LDO
VREG
VDDCORE
PM
sleep mode
LP VREG
Core
domain
VREFA
17.4
VREF
reference voltage
Peripheral Dependencies
AHB CLK
APB CLK
Generic CLK
PAC
Events
DMA
Peripheral Base Address IRQ
Sleep Walking
Enabled at reset Enabled at reset
SUPC
0x40001800
0
-
Y
17.5
Functional Description
17.5.1
Voltage Regulator System Operation
Index
-
Index Prot at reset User
6
N
-
Generator
Index
2: XOSC32K_FAIL
-
-
17.5.1.1 Enabling, Disabling, and Resetting
The LDO main voltage regulator is enabled after any Reset. The main voltage regulator (MAINVREG) can be
disabled by writing the Enable bit in the VREG register (VREG.ENABLE) to zero. The main voltage regulator output
supply level is automatically defined by the sleep mode selected in the Power Manager module.
17.5.1.2 Initialization
After a Reset, the LDO voltage regulator supplying VDDCORE is enabled.
17.5.1.3 Sleep Mode Operation
In Standby mode, the low-power voltage regulator (LPVREG) is used to supply VDDCORE.
When the Run in Standby bit in the VREG register (VREG.RUNSTDBY) is written to '1', VDDCORE is supplied by the
main voltage regulator. The VDDCORE level is set to the active mode voltage level.
17.5.2
Voltage Reference System Operation
The INTREF internal reference voltage is generated by the bandgap in the SUPC. Refer to the SEL bit in the VREF
register for voltage level selection.
17.5.2.1 Initialization
The voltage reference output is disabled after any Reset.
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and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Supply Controller (SUPC)
17.5.2.2 Enabling, Disabling, and Resetting
The voltage reference output is enabled/disabled by setting/clearing the Voltage Reference Output Enable bit in the
Voltage Reference register (VREF.VREFOE).
17.5.2.3 Selecting a Voltage Reference
The Voltage Reference Selection bit field in the VREF register (VREF.SEL) selects the voltage of INTREF (supplied
by the bandgap) to be applied to analog modules, for example, the ADC.
17.5.2.4 Sleep Mode Operation
The Voltage Reference output behavior during Sleep mode can be configured using the Run in Standby bit and the
On Demand bit in the Voltage Reference register (VREF.RUNSTDBY, VREF.ONDEMAND), see the following table:
Table 17-1. VREF Sleep Mode Operation
VREF.ONDEMAND VREF.RUNSTDBY Voltage Reference Sleep behavior
17.5.3
0
0
Always run in all sleep modes except Standby Sleep mode.
0
1
Always run in all sleep modes including Standby Sleep mode.
1
0
Only run if requested by the ADC, in all sleep modes except Standby
Sleep mode.
1
1
Only run if requested by the ADC, in all sleep modes including Standby
Sleep mode.
Brown-out Detectors
17.5.3.1 Initialization
Before a Brown-out Detector (BODVDD) is enabled, it must be configured, as outlined by the following:
• Set the BOD threshold level (BODVDD.LEVEL)
• Set the configuration in Active, Standby (BODVDD.ACTION, BODVDD.STDBYCFG)
• Set the prescaling value if the BOD will run in sampling mode (BODVDD.PSEL)
• Set the action and hysteresis (BODVDD.ACTION and BODVDD.HYST)
The BODVDD register is Enable-Protected, meaning that they can only be written when the BOD is disabled
(BODVDD.ENABLE = 0 and STATUS.BVDDSRDY = 0). As long as the Enable bit is '1', any writes to EnableProtected registers will be discarded, and an APB error will be generated. The Enable bits are not Enable-Protected.
17.5.3.2 Enabling, Disabling, and Resetting
After power or user reset, the BODVDD and BODCORE register values are loaded from the NVM User Row.
The BODVDD is enabled by writing a '1' to the Enable bit in the BOD control register (BODVDD.ENABLE). The BOD
is disabled by writing a '0' to the BODVDD.ENABLE.
17.5.3.3 VDD Brown-out Detector (BODVDD)
The VDD Brown-out Detector (BODVDD) is able to monitor the VDD supply and compares the voltage with the
brown-out threshold level set in the BODVDD Level field (BODVDD.LEVEL) in the BODVDD register.
When VDD crosses below the brown-out threshold level, the BODVDD can generate either an interrupt or a Reset,
depending on the BODVDD Action bit field (BODVDD.ACTION).
The BODVDD detection status can be read from the BODVDD Detection bit in the Status register
(STATUS.BODVDDDET).
At start-up or at Power-on Reset (POR), the BODVDD register values are loaded from the NVM User Row.
17.5.3.4 VDDCORE Brown-Out Detector (BODCORE)
The BODCORE is calibrated in production and its calibration configuration is stored in the NVM User Row. This
configuration must not be changed to assure the correct behavior of the BODCORE. The BODCORE generates a
reset when VDDCORE crosses below the preset brown-out level. The BODCORE is always disabled in Standby
Sleep mode.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Supply Controller (SUPC)
17.5.3.5 Continuous Mode
Continuous mode is the default mode for BODVDD.
The BODVDD is continuously monitoring the VDD supply voltage if it is enabled (BODVDD.ENABLE = 1) and
if the BODVDD Configuration bit in the BODVDD register is cleared (BODVDD.ACTCFG = 0 for active mode,
BODVDD.STDBYCFG = 0 for Standby mode).
17.5.3.6 Sampling Mode
The Sampling Mode is a Low-Power mode where the BODVDD is being repeatedly enabled on a sampling clock’s
ticks. The BODVDD will monitor the supply voltage for a short period of time and then go to a low-power disabled
state until the next sampling clock tick.
Sampling mode is enabled in Active mode for BODVDD by writing the ACTCFG bit (BODVDD.ACTCFG = 1).
Sampling mode is enabled in Standby mode by writing to the STDBYCFG bit (BODVDD.STBYCFG = 1). The
frequency of the clock ticks (Fclksampling) is controlled by the Prescaler Select bit groups in the BODVDD register
(BODVDD.PSEL).
Fclksampling =
Fclkprescaler
2 PSEL + 1
The prescaler signal (Fclkprescaler) is a 1.024 kHz clock, output by the 32.768 kHz Ultra Low-Power Oscillator
OSCULP32K.
As the sampling clock is different from the APB clock domain, synchronization among the clocks is necessary. See
also 17.5.5 Synchronization.
17.5.3.7 Hysteresis
A hysteresis on the trigger threshold of a BOD will reduce the sensitivity to ripples on the monitored voltage: instead
of switching RESET at each crossing of VBOD, the thresholds for switching RESET on and off are separated (VBODand VBOD+, respectively).
Figure 17-2. BOD Hysteresis Principle
Hysteresis OFF:
VCC
VBOD
RESET
Hysteresis ON:
VCC
VBOD+
VBOD-
RESET
Enabling the BODVDD hysteresis by writing the Hysteresis bit in the BODVDD register (BODVDD.HYST) to '1' will
add hysteresis to the BODVDD threshold level.
The hysteresis functionality can be used in both Continuous and Sampling Mode (Refer to the 43. Electrical
Characteristics 85℃ section for more information on the hysteresis values).
17.5.3.8 Sleep Mode Operation
17.5.3.8.1 Standby Mode
The BODVDD can be used in Standby mode if the BOD is enabled and the corresponding Run in Standby bit is
written to '1' (BODVDD.RUNSTDBY).
The BODVDD can be configured to work in either Continuous or Sampling Mode by writing a '1' to the Configuration
in Standby Sleep Mode bit (BODVDD.STDBYCFG).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Supply Controller (SUPC)
17.5.4
Interrupts
The SUPC has the following interrupt sources, which are either synchronous or asynchronous wake-up sources:
•
•
•
BODVDD Ready (BODVDDRDY), synchronous
BODVDD Detection (BODVDDDET), asynchronous
BODVDD Synchronization Ready (BVDDSRDY), synchronous
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs.
Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set register
(INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).
As both INTENSET and INTENCLR always reflect the same value, the status of interrupt enablement can be read
from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the SUPC is reset.
See the INTFLAG register for details on how to clear interrupt flags. The SUPC has one common interrupt request
line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is
present.
Note: Interrupts must be globally enabled for interrupt requests to be generated.
17.5.5
Synchronization
The prescaler counters that are used to trigger brown-out detections operate asynchronously from the peripheral bus.
As a consequence, the BODVDD Enable bit (BODVDD.ENABLE) need synchronization when written.
The Write-Synchronization of the Enable bit is triggered by writing a '1' to the Enable bit of the BODVDD Control
register. The Synchronization Ready bit (STATUS.BVDDSRDY) in the STATUS register will be cleared when the
Write-Synchronization starts, and set again when the Write-Synchronization is complete. Writing to the same register
while the Write-Synchronization is ongoing (STATUS.BVDDSRDY is '0') will generate a PAC error without stalling the
APB bus.
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and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Supply Controller (SUPC)
17.6
Register Summary
Offset
Name
0x00
INTENCLR
0x04
INTENSET
0x08
INTFLAG
0x0C
STATUS
0x10
BODVDD
0x14
...
0x17
Reserved
0x18
0x1C
VREG
VREF
Bit Pos.
7
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
6
5
4
3
2
1
0
BVDDSRDY BODVDDDET BODVDDRDY
BVDDSRDY BODVDDDET BODVDDRDY
BVDDSRDY BODVDDDET BODVDDRDY
BVDDSRDY BODVDDDET BODVDDRDY
RUNSTDBY STDBYCFG
PSEL[3:0]
ACTION[1:0]
HYST
ENABLE
ACTCFG
LEVEL[5:0]
RUNSTDBY
ENABLE
ONDEMAND RUNSTDBY
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VREFOE
SEL[3:0]
Datasheet
DS60001638D-page 140
PIC32CM MC00 Family
Supply Controller (SUPC)
17.6.1
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x00
0x00000000
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
BVDDSRDY
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
1
0
BODVDDDET BODVDDRDY
R/W
R/W
0
0
Bit 2 – BVDDSRDY BODVDD Synchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the BODVDD Synchronization Ready Interrupt Enable bit, which disables the
BODVDD Synchronization Ready interrupt.
Value
Description
0
The BODVDD Synchronization Ready interrupt is disabled.
1
The BODVDD Synchronization Ready interrupt is enabled, and an interrupt request will be generated
when the BODVDD Synchronization Ready Interrupt flag is set.
Bit 1 – BODVDDDET BODVDD Detection Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the BODVDD Detection Interrupt Enable bit, which disables the BODVDD Detection
interrupt.
Value
Description
0
The BODVDD Detection interrupt is disabled.
1
The BODVDD Detection interrupt is enabled, and an interrupt request will be generated when the
BODVDD Detection Interrupt flag is set.
Bit 0 – BODVDDRDY BODVDD Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the BODVDD Ready Interrupt Enable bit, which disables the BODVDD Ready
interrupt.
Value
Description
0
The BODVDD Ready interrupt is disabled.
1
The BODVDD Ready interrupt is enabled, and an interrupt request will be generated when the
BODVDD Ready Interrupt flag is set.
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Datasheet
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PIC32CM MC00 Family
Supply Controller (SUPC)
17.6.2
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x04
0x00000000
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
BVDDSRDY
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
1
0
BODVDDDET BODVDDRDY
R/W
R/W
0
0
Bit 2 – BVDDSRDY BODVDD Synchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the BODVDD Synchronization Ready Interrupt Enable bit, which enables the BODVDD
Synchronization Ready interrupt.
Value
Description
0
The BODVDD Synchronization Ready interrupt is disabled.
1
The BODVDD Synchronization Ready interrupt is enabled, and an interrupt request will be generated
when the BODVDD Synchronization Ready Interrupt flag is set.
Bit 1 – BODVDDDET BODVDD Detection Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the BODVDD Detection Interrupt Enable bit, which enables the BODVDD Detection
interrupt.
Value
Description
0
The BODVDD Detection interrupt is disabled.
1
The BODVDD Detection interrupt is enabled, and an interrupt request will be generated when the
BODVDD Detection Interrupt flag is set.
Bit 0 – BODVDDRDY BODVDD Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the BODVDD Ready Interrupt Enable bit, which enables the BODVDD Ready interrupt.
Value
Description
0
The BODVDD Ready interrupt is disabled.
1
The BODVDD Ready interrupt is enabled, and an interrupt request will be generated when the
BODVDD Ready Interrupt flag is set.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 142
PIC32CM MC00 Family
Supply Controller (SUPC)
17.6.3
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
INTFLAG
0x08
X determined from NVM User Row
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
BVDDSRDY
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
1
0
BODVDDDET BODVDDRDY
R/W
R/W
0
x
Bit 2 – BVDDSRDY BODVDD Synchronization Ready
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the BODVDD Synchronization Ready bit in the Status register
(STATUS.BVDDSRDY) and will generate an interrupt request if INTENSET.BVDDSRDY=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the BODVDD Synchronization Ready interrupt flag.
Bit 1 – BODVDDDET BODVDD Detection
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the BODVDD Detection bit in the Status register
(STATUS.BODVDDDET) and will generate an interrupt request if INTENSET.BODVDDDET=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the BODVDD Detection interrupt flag.
Bit 0 – BODVDDRDY BODVDD Ready
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the BODVDD Ready bit in the Status register (STATUS.BODVDDRDY)
and will generate an interrupt request if INTENSET.BODVDDRDY=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the BODVDD Ready interrupt flag.
The BODVDD can be enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 143
PIC32CM MC00 Family
Supply Controller (SUPC)
17.6.4
Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x0C
Determined from NVM User Row
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
BVDDSRDY
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
1
0
BODVDDDET BODVDDRDY
R
R
0
y
Bit 2 – BVDDSRDY BODVDD Synchronization Ready
Value
Description
0
BODVDD synchronization is ongoing.
1
BODVDD synchronization is complete.
Bit 1 – BODVDDDET BODVDD Detection
Value
Description
0
No BODVDD detection.
1
BODVDD has detected that the I/O power supply is going below the BODVDD reference value.
Bit 0 – BODVDDRDY BODVDD Ready
The BODVDD can be enabled at start-up from NVM User Row.
Value
Description
0
BODVDD is not ready.
1
BODVDD is ready.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 144
PIC32CM MC00 Family
Supply Controller (SUPC)
17.6.5
VDD Brown-Out Detector (BODVDD) Control
Name:
Offset:
Reset:
Property:
Bit
BODVDD
0x10
X determined from NVM User Row
Write-Synchronized Bits, Enable-Protected Bits, PAC Write-Protection
31
30
29
28
27
23
22
21
20
19
26
25
24
18
17
16
Access
Reset
Bit
LEVEL[5:0]
Access
Reset
Bit
15
14
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
13
12
11
10
9
8
ACTCFG
R/W
0
2
HYST
R/W
x
1
ENABLE
R/W
x
0
PSEL[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
7
6
RUNSTDBY
R/W
0
5
STDBYCFG
R/W
0
4
Bit
Access
Reset
3
ACTION[1:0]
R/W
R/W
x
x
Bits 21:16 – LEVEL[5:0] BODVDD Threshold Level on VDD
These bits set the triggering voltage threshold for the BODVDD when the BODVDD monitors the VDD.
These bits are loaded from NVM User Row at start-up. The use of the HYST setting can help in eliminating restarts at
startup when observed.
Note: This bit field is enable-protected. This bit field is not synchronized.
Bits 15:12 – PSEL[3:0] Prescaler Select
Selects the prescaler divide-by output for the BODVDD sampling mode. The input clock comes from the
OSCULP32K 1.024 kHz output.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
Name
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
DIV128
DIV256
DIV512
DIV1024
DIV2048
DIV4096
DIV8192
DIV16384
DIV32768
DIV65536
© 2021 Microchip Technology Inc.
and its subsidiaries
Description
Divide clock by 2
Divide clock by 4
Divide clock by 8
Divide clock by 16
Divide clock by 32
Divide clock by 64
Divide clock by 128
Divide clock by 256
Divide clock by 512
Divide clock by 1024
Divide clock by 2048
Divide clock by 4096
Divide clock by 8192
Divide clock by 16384
Divide clock by 32768
Divide clock by 65536
Datasheet
DS60001638D-page 145
PIC32CM MC00 Family
Supply Controller (SUPC)
Bit 8 – ACTCFG BODVDD Configuration in Active Mode
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
In active mode, the BODVDD operates in continuous mode.
In active mode, the BODVDD operates in sampling mode.
Bit 6 – RUNSTDBY Run in Standby
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
In standby sleep mode, the BODVDD is disabled.
In standby sleep mode, the BODVDD is enabled.
Bit 5 – STDBYCFG BODVDD Configuration in Standby Sleep Mode
If the RUNSTDBY bit is set to '1', the STDBYCFG bit sets the BODVDD configuration in standby sleep mode.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
In standby sleep mode, the BODVDD is configured in continuous mode.
In standby sleep mode, the BODVDD is configured in sampling mode.
Bits 4:3 – ACTION[1:0] BODVDD Action
These bits are used to select the BODVDD action when the supply voltage crosses below the BODVDD threshold.
These bits are loaded from NVM User Row at start-up.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
Name
0x0
0x1
0x2
0x3
NONE
RESET
INT
-
Description
No action
The BODVDD generates a reset
The BODVDD generates an interrupt
Reserved
Bit 2 – HYST Hysteresis
This bit indicates whether hysteresis is enabled for the BODVDD threshold voltage.
This bit is loaded from NVM User Row at start-up.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
No hysteresis.
Hysteresis enabled.
Bit 1 – ENABLE Enable
This bit is loaded from NVM User Row at start-up.
Notes:
1. This bit is write-synchronized: STATUS.BVDDSRDY must be checked to ensure the BODVDD.ENABLE
synchronization is complete.
2. This bit is not enable-protected.
Value
0
1
Description
BODVDD is disabled.
BODVDD is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 146
PIC32CM MC00 Family
Supply Controller (SUPC)
17.6.6
Voltage Regulator System (VREG) Control
Name:
Offset:
Reset:
Property:
VREG
0x18
0x00000002
PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
23
22
21
20
19
18
17
16
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
7
5
4
3
2
R
0
R
0
R
0
R
0
R
0
1
ENABLE
R/W
1
0
Access
Reset
6
RUNSTDBY
R/W
0
R
0
Bit 6 – RUNSTDBY Run in Standby
Value
Description
0
The voltage regulator is in Low-Power mode in Standby-Sleep mode.
1
The voltage regulator is in normal mode in Standby-Sleep mode.
Bit 1 – ENABLE Must be set to 1.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 147
PIC32CM MC00 Family
Supply Controller (SUPC)
17.6.7
Voltage References System (VREF) Control
Name:
Offset:
Reset:
Property:
Bit
VREF
0x1C
0x00000000
PAC Write-Protection
31
30
29
28
27
26
23
22
21
20
19
18
25
24
17
16
Access
Reset
Bit
SEL[3:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
ONDEMAND
R/W
0
6
RUNSTDBY
R/W
0
5
4
3
2
VREFOE
R/W
0
1
0
Access
Reset
Bit
Access
Reset
Bits 19:16 – SEL[3:0] Voltage Reference Selection
These bits select the Voltage Reference (INTREF) for the AC / ADC / DAC / SDADC.
Value
Description
0x0
1.024V voltage reference typical value.
0x2
2.048V voltage reference typical value.
0x3
4.096V voltage reference typical value.
Others
Reserved
Bit 7 – ONDEMAND On Demand Control
The On Demand operation mode allows to enable or disable the voltage reference depending on peripheral requests.
Value
Description
0
The voltage reference is always on, if enabled.
1
The voltage reference is enabled when a peripheral is requesting it. The voltage reference is disabled if
no peripheral is requesting it.
Bit 6 – RUNSTDBY Run In Standby
The bit controls how the voltage reference behaves during Standby Sleep mode.
Value
Description
0
The voltage reference is halted during Standby sleep mode.
1
The voltage reference is not stopped in Standby sleep mode. If VREF.ONDEMAND = 1, the voltage
reference will be running when a peripheral is requesting it. If VREF.ONDEMAND = 0, the voltage
reference will always be running in standby sleep mode.
Bit 2 – VREFOE Voltage Reference (INTREF) Output Enable
Value
Description
0
The Voltage Reference output (INTREF) is not available as an ADC input channel.
1
The Voltage Reference output (INTREF) is routed to an ADC input channel.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 148
PIC32CM MC00 Family
Reset Controller (RSTC)
18.
Reset Controller (RSTC)
18.1
Overview
The Reset Controller (RSTC) manages the reset of the microcontroller. It issues a microcontroller reset, sets the
device to its initial state and allows the reset source to be identified by software.
18.2
Features
•
•
•
18.3
Reset the microcontroller and set it to an initial state according to the reset source
Reset cause register for reading the reset source from the application code
Multiple reset sources
– Power supply reset sources: POR, BODCORE, BODVDD
– User reset sources: External reset (RESET), Watchdog reset, and System Reset Request
Block Diagram
Figure 18-1. Reset System
RESET SOURCES
RTC
32kHz clock sources
WDT with ALWAYSON
GCLK with WRTLOCK
RESET CONTROLLER
BODCORE
BODVDD
POR
Debug Logic
RESET
WDT
Other Modules
CPU
RCAUSE
18.4
Signal Description
18.5
Type
Description
RESET
Digital input
External reset pin
Peripheral Dependencies
Peripheral
RSTC
Signal Name
Base Address
AHB CLK
APB CLK
Generic CLK
PAC
Events
DMA
Enabled at reset
Enabled at reset
Index
Index
Prot at reset
User
Generator
Index
-
Y
-
3
N
-
-
-
IRQ
0x40000C00
-
Sleep Walking
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
-
DS60001638D-page 149
PIC32CM MC00 Family
Reset Controller (RSTC)
18.6
18.6.1
Functional Description
Principle of Operation
The Reset Controller collects the various Reset sources and generates Reset for the device.
18.6.2
Basic Operation
18.6.2.1 Initialization
After a power-on Reset, the RSTC is enabled and the Reset Cause (RCAUSE) register indicates the POR source.
18.6.2.2 Enabling, Disabling, and Resetting
The RSTC module is always enabled.
18.6.2.3 Reset Causes and Effects
The latest Reset cause is available in RCAUSE register, and can be read during the application boot sequence in
order to determine proper action.
These are the groups of Reset sources:
•
•
Power supply Reset: Resets caused by an electrical issue. It covers POR and BODs Resets
User Reset: Resets caused by the application. It covers external Resets, system Reset requests and watchdog
Resets
The following table lists the parts of the device that are reset, depending on the Reset type.
Table 18-1. Effects of the Different Reset Causes
Power Supply Reset
User Reset
POR, BODVDD, BODCORE External Reset WDT Reset, System Reset Request
RTC, OSC32KCTRL, RSTC
Reset
-
-
GCLK with WRTLOCK
Reset
-
-
Debug logic
Reset
Reset
-
Others
Reset
Reset
Reset
The external Reset is generated when pulling the RESET pin low.
The POR, BODCORE, and BODVDD Reset sources are generated by their corresponding module in the Supply
Controller Interface (SUPC).
The WDT Reset is generated by the Watchdog Timer.
The System Reset Request is a Reset generated by the CPU when asserting the SYSRESETREQ bit located in
the Reset Control register of the CPU (for details refer to the Arm Cortex Technical Reference Manual on http://
www.arm.com).
Note: Refer to the TRST specification in the Power Supply section of the Electrical Characteristics chapter.
18.6.3
Sleep Mode Operation
The RSTC module is active in all sleep modes.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 150
PIC32CM MC00 Family
Reset Controller (RSTC)
18.7
Register Summary
Offset
Name
Bit Pos.
0x00
RCAUSE
7:0
7
© 2021 Microchip Technology Inc.
and its subsidiaries
6
5
4
SYST
WDT
EXT
Datasheet
3
2
1
0
BODVDD
BODCORE
POR
DS60001638D-page 151
PIC32CM MC00 Family
Reset Controller (RSTC)
18.7.1
Reset Cause
Name:
Offset:
Property:
RCAUSE
0x00
–
When a Reset occurs, the bit corresponding to the Reset source is set to '1' and all other bits are written to '0'.
Bit
Access
Reset
7
6
SYST
R
x
5
WDT
R
x
4
EXT
R
x
3
2
BODVDD
R
x
1
BODCORE
R
x
0
POR
R
x
Bit 6 – SYST System Reset Request
This bit is set if a System Reset Request has occurred. Refer to the Cortex processor documentation for more
details.
Bit 5 – WDT Watchdog Reset
This bit is set if a Watchdog Timer Reset has occurred.
Bit 4 – EXT External Reset
This bit is set if an external Reset has occurred.
Bit 2 – BODVDD Brown Out VDD Detector Reset
This bit is set if a BODVDD Reset has occurred.
Bit 1 – BODCORE Brown Out CORE Detector Reset
This bit is set if a BODCORE Reset has occurred.
Bit 0 – POR Power On Reset
This bit is set if a POR has occurred.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 152
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
19.
Peripheral Access Controller (PAC)
19.1
Overview
The Peripheral Access Controller (PAC) provides an interface for the locking and unlocking of peripheral registers
within the device. It reports all violations that could happen when accessing a peripheral: write protected access,
illegal access, enable protected access, access when clock synchronization or software reset is on-going. These
errors are reported in a unique interrupt flag for a peripheral. The PAC module also reports errors occurring at the
client bus level, when an access to a non-existing address is detected.
19.2
Features
•
19.3
Manages write protection access and reports access errors for the peripheral modules or bridges.
Block Diagram
Figure 19-1. PAC Block Diagram
High-Speed BUS
PAC
IRQ
Client ERROR
CLIENTs
INTFLAG
APB
Peripheral ERROR
PERIPHERAL m
BUSn
PERIPHERAL 0
WRITE CONTROL
PAC CONTROL
Peripheral ERROR
PERIPHERAL m
BUS0
PERIPHERAL 0
WRITE CONTROL
19.4
Peripheral
PAC
19.5
19.5.1
Peripheral Dependencies
Base Address
AHB CLK
APB CLK
Generic CLK
PAC
Events
DMA
Enabled at reset
Enabled at reset
Index
Index
Prot at reset
User
Generator
Index
Y
Y
-
0
N
-
81: ACCERR
-
IRQ
0x40000000
Sleep Walking
0
-
Functional Description
Principle of Operation
The Peripheral Access Control module allows the user to set a write protection on peripheral modules and generate
an interrupt in case of a peripheral access violation. The peripheral’s protection can be set, cleared or locked at
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 153
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
the user discretion. A set of Interrupt Flag and Status registers informs the user on the status of the violation in the
peripherals. In addition, client bus errors can be also reported in the cases where reserved area is accessed by the
application.
19.5.2
Basic Operation
19.5.2.1 Initialization, Enabling and Resetting
The PAC is always enabled after reset.
Only a hardware reset will reset the PAC module.
19.5.2.2 Operations
The PAC module allows the user to set, clear or lock the write protection status of all peripherals on all Peripheral
Bridges.
If a peripheral register violation occurs, the Peripheral Interrupt Flag n registers (INTFLAGn) are updated to inform
the user on the status of the violation in the peripherals connected to the Peripheral Bridge n (n = A,B,C ...). The
corresponding Peripheral Write Control Status n register (STATUSn) gives the state of the write protection for all
peripherals connected to the corresponding Peripheral Bridge n. Refer to 19.5.2.3 Peripheral Access Errors for
details.
The PAC module also reports the errors occurring at client bus level when an access to reserved area is detected.
AHB Client Bus Interrupt Flag register (INTFLAGAHB) informs the user on the status of the violation in the
corresponding client. Refer to the 19.5.2.6 AHB Client Bus Errors for details.
19.5.2.3 Peripheral Access Errors
The following events will generate a Peripheral Access Error:
•
•
•
Protected write: To avoid unexpected writes to a peripheral's registers, each peripheral can be write protected.
Only the registers denoted as “PAC Write-Protection” in the module’s data sheet can be protected. If a
peripheral is not write protected, write data accesses are performed normally. If a peripheral is write protected
and if a write access is attempted, data will not be written and peripheral returns an access error. The
corresponding interrupt flag bit in the INTFLAGn register will be set.
Illegal access: Access to an unimplemented register within the module.
Synchronized write error: For write-synchronized registers an error will be reported if the register is written while
a synchronization is ongoing.
When any of the INTFLAGn registers bit are set, an interrupt will be requested if the PAC interrupt enable bit is set.
19.5.2.4 Write Access Protection Management
Peripheral access control can be enabled or disabled by writing to the WRCTRL register.
The data written to the WRCTRL register is composed of two fields; WRCTRL.PERID and WRCTRL.KEY. The
WRCTRL.PERID is an unique identifier corresponding to a peripheral. The WRCTRL.KEY is a key value that defines
the operation to be done on the control access bit. These operations can be “clear protection”, “set protection” and
“set and lock protection bit”.
The “clear protection” operation will remove the write access protection for the peripheral selected by
WRCTRL.PERID. Write accesses are allowed for the registers in this peripheral.
The “set protection” operation will set the write access protection for the peripheral selected by WRCTRL.PERID.
Write accesses are not allowed for the registers with write protection property in this peripheral.
The “set and lock protection” operation will set the write access protection for the peripheral selected by
WRCTRL.PERID and locks the access rights of the selected peripheral registers. The write access protection will
only be cleared by a hardware reset.
The peripheral access control status can be read from the corresponding STATUSn register.
19.5.2.5 Write Access Protection Management Errors
Only word-wise writes to the WRCTRL register will effectively change the access protection. Other type of accesses
will have no effect and will cause a PAC write access error. This error is reported in the INTFLAGA.PAC bit.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 154
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
PAC also offers an additional safety feature for correct program execution with an interrupt generated on double
write clear protection or double write set protection. If a peripheral is write protected and a subsequent set protection
operation is detected then the PAC returns an error, and similarly for a double clear protection operation.
In addition, an error is generated when writing a “set and lock” protection to a write-protected peripheral or when a
write access is done to a locked set protection. This can be used to ensure that the application follows the intended
program flow by always following a write protect with an unprotect and conversely. However in applications where a
write protected peripheral is used in several contexts, e.g. interrupt, care should be taken so that either the interrupt
can not happen while the main application or other interrupt levels manipulates the write protection status or when
the interrupt handler needs to unprotect the peripheral based on the current protection status by reading the STATUS
register.
The errors generated while accessing the PAC module registers (for example, key error, double protect error, and so
on) will set the INTFLAGA.PAC flag.
19.5.2.6 AHB Client Bus Errors
The PAC module reports errors occurring at the AHB Client bus level. These errors are generated when an access
is performed at an address where no client (bridge or peripheral) is mapped. These errors are reported in the
corresponding bits of the INTFLAGAHB register.
19.5.2.7 Generating Events
The PAC module can also generate an event when any of the Interrupt Flag registers bit are set. To enable the PAC
event generation, the control bit EVCTRL.ERREO must be set a '1'.
19.5.3
Interrupts
The PAC has the following interrupt source:
•
Error (ERR): Indicates that a peripheral access violation occurred in one of the peripherals controlled by the PAC
module, or a bridge error occurred in one of the bridges reported by the PAC
– This interrupt is a synchronous wake-up source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAGAHB and INTFLAGn) registers is set when the interrupt condition occurs.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the PAC is reset. All
interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request
to the NVIC 9.2 Nested Vector Interrupt Controller. The user must read the INTFLAGAHB and INTFLAGn registers
to determine which interrupt condition is present. Interrupts must be globally enabled for interrupt requests to be
generated.
19.5.4
Events
The PAC can generate the following output event:
• Error (ERR): Generated when one of the interrupt flag registers bits is set
Writing a '1' to an Event Output bit in the Event Control Register (EVCTRL.ERREO) enables the corresponding
output event. Writing a '0' to this bit disables the corresponding output event.
19.5.5
Sleep Mode Operation
In Sleep mode, the PAC is kept enabled if an available bus host (CPU, DMA) is running. The PAC will continue to
catch access errors from the module and generate interrupts or events.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 155
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
19.6
Register Summary
Offset
Name
0x00
WRCTRL
0x04
0x05
...
0x07
0x08
0x09
0x0A
...
0x0F
EVCTRL
0x10
0x14
0x18
Bit Pos.
INTENCLR
INTENSET
INTFLAGAHB
INTFLAGA
INTFLAGB
0x20
...
0x33
Reserved
4
7:0
15:8
23:16
31:24
7:0
3
2
1
0
PERID[7:0]
PERID[15:8]
KEY[7:0]
ERREO
7:0
7:0
ERR
ERR
7:0
15:8
23:16
31:24
DIVAS
SRAMDMAC
APBC
APBA
APBB
7:0
GCLK
SUPC
OSC32KCTR
L
OSCCTRL
RSTC
MCLK
PM
PAC
FREQM
EIC
RTC
WDT
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
0x3C
5
Reserved
INTFLAGC
0x38
6
Reserved
0x1C
0x34
7
STATUSA
STATUSB
STATUSC
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
TC3
CCL
TC2
GCLK
SUPC
TC3
CCL
© 2021 Microchip Technology Inc.
and its subsidiaries
TC2
HSRAMDSU HSRAMCM0P
FLASH
HMATRIXHS
MTB
DMAC
NVMCTRL
DSU
PORT
SERCOM3
TC0
AC
SERCOM2
TCC2
SDADC
SERCOM1
TCC1
ADC1
PDEC
SERCOM0
TCC0
ADC0
EVSYS
TC1
DAC
OSC32KCTR
L
OSCCTRL
TC4
RSTC
MCLK
PM
PAC
FREQM
EIC
RTC
WDT
HMATRIXHS
MTB
DMAC
NVMCTRL
DSU
PORT
SERCOM3
TC0
AC
SERCOM2
TCC2
SDADC
SERCOM1
TCC1
ADC1
PDEC
SERCOM0
TCC0
ADC0
EVSYS
TC1
DAC
Datasheet
TC4
DS60001638D-page 156
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
19.6.1
Write Control
Name:
Offset:
Reset:
Property:
Bit
WRCTRL
0x00
0x00000000
–
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
RW
0
RW
0
RW
0
RW
0
11
10
9
8
RW
0
RW
0
RW
0
RW
0
3
2
1
0
RW
0
RW
0
RW
0
RW
0
Access
Reset
Bit
KEY[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
PERID[15:8]
Access
Reset
Bit
RW
0
RW
0
RW
0
RW
0
7
6
5
4
PERID[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
Bits 23:16 – KEY[7:0] Peripheral Access Control Key
These bits define the peripheral access control key:
Value
Name
Description
0x0
OFF
No action
0x1
CLEAR
Clear the peripheral write control
0x2
SET
Set the peripheral write control
0x3
LOCK
Set and lock the peripheral write control until the next hardware reset
Bits 15:0 – PERID[15:0] Peripheral Identifier
The PERID represents the peripheral whose control is changed using the WRCTRL.KEY.
Table 19-1. Peripheral Identifier
Peripheral
Identifier
APBA Peripherals
PAC
PM
MCLK
RSTC
OSCCTRL
OSC32KCTRL
SUPC
GCLK
WDT
RTC
EIC
FREQM (4)
TEMPS (1)
0
1
2
3
4
5
6
7
8
9
10
11
12
APBB Peripherals
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 157
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
...........continued
Peripheral
Identifier
(2,3)
PORT
DSU
NVMCTRL
DMAC
MTB
HMATRIXHS
32
33
34
35
36
37
APBC Peripherals
EVSYS
SERCOM0
SERCOM1
SERCOM2
SERCOM3
TCC0
TCC1
TCC2
TC0
TC1
TC2
TC3
TC4
ADC0
ADC1
SDADC
AC
DAC
CCL
PDEC
64
65
66
67
68
73
74
75
76
77
78
79
80
81
82
83
84
85
87
90
Notes:
1. PAC protection for the TSENS should only be used when the TSENS is in Free Run mode.
2. IOBUS writes are not prevented to PAC write-protected registers when the PORT module is PAC protected.
3. PORT read/write attempts on non-implemented registers, including addresses beyond the last implemented
register group do not generate a PAC protection error.
4. Reading the Frequency Meter Control B register (FREQM.CTRLB) will result in a PAC error.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 158
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
19.6.2
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x04
0x00
-
7
6
5
4
3
Access
Reset
2
1
0
ERREO
RW
0
Bit 0 – ERREO Peripheral Access Error Event Output
This bit indicates if the Peripheral Access Error Event Output is enabled or disabled. When enabled, an event will be
generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set:
Value
Description
0
Peripheral Access Error Event Output is disabled.
1
Peripheral Access Error Event Output is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 159
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
19.6.3
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x08
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
6
5
4
3
Access
Reset
2
1
0
ERR
RW
0
Bit 0 – ERR Peripheral Access Error Interrupt Disable
This bit indicates that the Peripheral Access Error Interrupt is enabled and an interrupt request will be generated
when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set:
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Peripheral Access Error interrupt Enable bit and disables the corresponding
interrupt request.
Value
Description
0
Peripheral Access Error interrupt is disabled.
1
Peripheral Access Error interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 160
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
19.6.4
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x09
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENCLR).
Bit
7
6
5
4
3
Access
Reset
2
1
0
ERR
RW
0
Bit 0 – ERR Peripheral Access Error Interrupt Enable
This bit indicates that the Peripheral Access Error Interrupt is enabled and an interrupt request will be generated
when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set:
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Peripheral Access Error interrupt Enable bit and enables the corresponding interrupt
request.
Value
Description
0
Peripheral Access Error interrupt is disabled.
1
Peripheral Access Error interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 161
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
19.6.5
AHB Client Bus Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
INTFLAGAHB
0x10
0x000000
–
This flag is cleared by writing a '1' to the flag.
This flag is set when an access error is detected by the CLIENT n, and will generate an interrupt request if
INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
DIVAS
R/W
0
6
SRAMDMAC
R/W
0
5
APBC
R/W
0
4
APBA
R/W
0
3
APBB
R/W
0
2
HSRAMDSU
R/W
0
1
HSRAMCM0P
R/W
0
0
FLASH
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 7 – DIVAS Interrupt Flag for CLIENT DIVAS
Bit 6 – SRAMDMAC Interrupt Flag for CLIENT SRAMDMAC
Bit 5 – APBC Interrupt Flag for CLIENT APBC
Bit 4 – APBA Interrupt Flag for CLIENT APBA
Bit 3 – APBB Interrupt Flag for CLIENT APBB
Bit 2 – HSRAMDSU Interrupt Flag for CLIENT SRAMDSU
Bit 1 – HSRAMCM0P Interrupt Flag for CLIENT SRAMCM0P
Bit 0 – FLASH Interrupt Flag for CLIENT FLASH
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 162
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
19.6.6
Peripheral Interrupt Flag Status and Clear A
Name:
Offset:
Reset:
Property:
INTFLAGA
0x14
0x00000000
–
This flag is cleared by writing a one to the flag.
This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective
INTFLAGA bit, and will generate an interrupt request if INTENCLR/SET.ERR is one.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding INTFLAGA interrupt flag.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
FREQM
R/W
0
10
EIC
R/W
0
9
RTC
R/W
0
8
WDT
R/W
0
7
GCLK
R/W
0
6
SUPC
R/W
0
5
OSC32KCTRL
R/W
0
4
OSCCTRL
R/W
0
3
RSTC
R/W
0
2
MCLK
R/W
0
1
PM
R/W
0
0
PAC
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – FREQM Interrupt Flag for FREQM
Bit 10 – EIC Interrupt Flag for EIC
Bit 9 – RTC Interrupt Flag for RTC
Bit 8 – WDT Interrupt Flag for WDT
Bit 7 – GCLK Interrupt Flag for GCLK
Bit 6 – SUPC Interrupt Flag for SUPC
Bit 5 – OSC32KCTRL Interrupt Flag for OSC32KCTRL
Bit 4 – OSCCTRL Interrupt Flag for OSCCTRL
Bit 3 – RSTC Interrupt Flag for RSTC
Bit 2 – MCLK Interrupt Flag for MCLK
Bit 1 – PM Interrupt Flag for PM
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 163
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
Bit 0 – PAC Interrupt Flag for PAC
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 164
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
19.6.7
Peripheral Interrupt Flag Status and Clear B
Name:
Offset:
Reset:
Property:
INTFLAGB
0x18
0x00000000
–
This flag is cleared by writing a '1' to the flag.
This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective
INTFLAGB bit, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding INTFLAGB interrupt flag.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
HMATRIXHS
R/W
0
4
MTB
R/W
0
3
DMAC
R/W
0
2
NVMCTRL
R/W
0
1
DSU
R/W
0
0
PORT
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 5 – HMATRIXHS Interrupt Flag for HMATRIXHS
Bit 4 – MTB Interrupt Flag for MTB
Bit 3 – DMAC Interrupt Flag for DMAC
Bit 2 – NVMCTRL Interrupt Flag for NVMCTRL
Bit 1 – DSU Interrupt Flag for DSU
Bit 0 – PORT Interrupt Flag for PORT
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 165
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
19.6.8
Peripheral Interrupt Flag Status and Clear C
Name:
Offset:
Reset:
Property:
INTFLAGC
0x1C
0x00000000
–
This flag is cleared by writing a one to the flag.
This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective
INTFLAGC bit, and will generate an interrupt request if INTENCLR/SET.ERR is one.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding INTFLAGC interrupt flag.
Bit
31
30
29
28
27
26
PDEC
R/W
0
25
24
23
CCL
R/W
0
22
21
DAC
R/W
0
20
AC
R/W
0
19
SDADC
R/W
0
18
ADC1
R/W
0
17
ADC0
R/W
0
16
TC4
R/W
0
15
TC3
R/W
0
14
TC2
R/W
0
13
TC1
R/W
0
12
TC0
R/W
0
11
TCC2
R/W
0
10
TCC1
R/W
0
9
TCC0
R/W
0
8
7
6
5
4
SERCOM3
R/W
0
3
SERCOM2
R/W
0
2
SERCOM1
R/W
0
1
SERCOM0
R/W
0
0
EVSYS
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 26 – PDEC Interrupt Flag for the PDEC
Bit 23 – CCL Interrupt Flag for CCL
Bit 21 – DAC Interrupt Flag for the DAC
Bit 20 – AC Interrupt Flag for the AC
Bit 19 – SDADC Interrupt Flag for the SDADC
Bits 17, 18 – ADC Interrupt Flag for ADCn [n=1..0]
Bits 12, 13, 14, 15, 16 – TC Interrupt Flag for TCn [n = 4..0]
Bits 9, 10, 11 – TCC Interrupt Flag for TCCn [n = 2..0]
Bits 1, 2, 3, 4 – SERCOM Interrupt Flag for SERCOMn [n = 3..0]
Bit 0 – EVSYS Interrupt Flag for EVSYS
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 166
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
19.6.9
Peripheral Write Protection Status A
Name:
Offset:
Reset:
Property:
STATUSA
0x34
0x000000
–
Writing to this register has no effect.
Reading STATUS register returns peripheral write protection status:
Bit
Value
Description
0
Peripheral is not write protected.
1
Peripheral is write protected.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
FREQM
R
0
10
EIC
R
0
9
RTC
R
0
8
WDT
R
0
7
GCLK
R
0
6
SUPC
R
0
5
OSC32KCTRL
R
0
4
OSCCTRL
R
0
3
RSTC
R
0
2
MCLK
R
0
1
PM
R
0
0
PAC
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – FREQM Peripheral FREQM Write Protection Status
Bit 10 – EIC Peripheral EIC Write Protection Status
Bit 9 – RTC Peripheral RTC Write Protection Status
Bit 8 – WDT Peripheral WDT Write Protection Status
Bit 7 – GCLK Peripheral GCLK Write Protection Status
Bit 6 – SUPC Peripheral SUPC Write Protection Status
Bit 5 – OSC32KCTRL Peripheral OSC32KCTRL Write Protection Status
Bit 4 – OSCCTRL Peripheral OSCCTRL Write Protection Status
Bit 3 – RSTC Peripheral RSTC Write Protection Status
Bit 2 – MCLK Peripheral MCLK Write Protection Status
Bit 1 – PM Peripheral PM Write Protection Status
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 167
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
Bit 0 – PAC Peripheral PAC Write Protection Status
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 168
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
19.6.10 Peripheral Write Protection Status B
Name:
Offset:
Reset:
Property:
STATUSB
0x38
0x00000002
–
Writing to this register has no effect.
Reading STATUS register returns peripheral write protection status:
Bit
Value
Description
0
Peripheral is not write protected.
1
Peripheral is write protected.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
HMATRIXHS
R
0
4
MTB
R
0
3
DMAC
R
0
2
NVMCTRL
R
0
1
DSU
R
1
0
PORT
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 5 – HMATRIXHS Peripheral HMATRIXHS Write Protection Status
Bit 4 – MTB Peripheral MTB Write Protection Status
Bit 3 – DMAC Peripheral DMAC Write Protection Status
Bit 2 – NVMCTRL Peripheral NVMCTRL Write Protection Status
Bit 1 – DSU Peripheral DSU Write Protection Status
Bit 0 – PORT Peripheral PORT Write Protection Status
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 169
PIC32CM MC00 Family
Peripheral Access Controller (PAC)
19.6.11 Peripheral Write Protection Status C
Name:
Offset:
Reset:
Property:
STATUSC
0x3C
0x09000000
–
Writing to this register has no effect.
Reading STATUS register returns peripheral write protection status:
Bit
Value
Description
0
Peripheral is not write protected.
1
Peripheral is write protected.
31
30
29
28
27
26
PDEC
R
0
25
24
23
CCL
R
0
22
21
DAC
R
0
20
AC
R
0
19
SDADC
R
0
18
ADC1
R
0
17
ADC0
R
0
16
TC4
R
0
15
TC3
R
0
14
TC2
R
0
13
TC1
R
0
12
TC0
R
0
11
TCC2
R
0
10
TCC1
R
0
9
TCC0
R
0
8
7
6
5
4
SERCOM3
R
0
3
SERCOM2
R
0
2
SERCOM1
R
0
1
SERCOM0
R
0
0
EVSYS
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 26 – PDEC Peripheral PDEC Write Protection Status
Bit 23 – CCL Peripheral CCL Write Protection Status
Bit 21 – DAC Peripheral DAC Write Protection Status
Bit 20 – AC Peripheral AC Write Protection Status
Bit 19 – SDADC Peripheral SDADC Write Protection Status
Bits 17, 18 – ADC Peripheral ADCn [n=1..0] Write Protection Status
Bits 12, 13, 14, 15, 16 – TC Peripheral TCn Write Protection Status [n = 4..0]
Bits 9, 10, 11 – TCC Peripheral TCCn [n = 2..0] Write Protection Status TCCn [n = 2..0]
Bits 1, 2, 3, 4 – SERCOM Peripheral SERCOMn Write Protection Status [n = 3..0]
Bit 0 – EVSYS Peripheral EVSYS Write Protection Status
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 170
PIC32CM MC00 Family
Device Service Unit (DSU)
20.
20.1
Device Service Unit (DSU)
Overview
The Device Service Unit (DSU) provides a means of detecting debugger probes. It enables the Arm Debug Access
Port (DAP) to have control over multiplexed debug pads and CPU reset. The DSU also provides system-level
™
services to debug adapters in an Arm debug system. It implements a CoreSight Debug ROM that provides device
identification as well as identification of other debug components within the system. Hence, it complies with the Arm
Peripheral Identification specification. The DSU also provides system services to applications that need memory
testing, as required for IEC60730 Class B compliance, for example. The DSU can be accessed simultaneously by a
debugger and the CPU, as it is connected on the High-Speed Bus Matrix. For security reasons, some of the DSU
features will be limited or unavailable when the device is protected by the NVMCTRL security bit.
20.2
Features
•
•
•
•
•
•
•
•
•
20.3
CPU reset extension
Debugger probe detection (Cold-Plugging and Hot-Plugging)
Chip-Erase command and status
32-bit cyclic redundancy check (CRC32) of any memory accessible through the bus matrix
Arm® CoreSight™ compliant device identification
Two debug communications channels
Debug access port security filter
DMA connection
Onboard memory built-in self-test (MBIST)
Block Diagram
Figure 20-1. DSU Block Diagram
DSU
RESET
SWCLK
debugger_present
DEBUGGER PROBE
INTERFACE
DMA request
cpu_reset_extension
CPU
DAP
AHB-AP
DAP SECURITY FILTER
DBG
DMA
NVMCTRL
S
S
CORESIGHT ROM
PORT
M
CRC-32
SWDIO
MBIST
M
HIGH-SPEED
BUS MATRIX
CHIP ERASE
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 171
PIC32CM MC00 Family
Device Service Unit (DSU)
20.4
Signal Description
The DSU uses the following three signals to function.
20.5
20.6
20.6.1
Type
Description
RESET
Digital Input
External reset pin
SWCLK
Digital Input
SW clock pin
SWDIO
Digital I/O
SW bidirectional data pin
Peripheral Dependencies
Peripheral
DSU
Signal Name
Base Address
AHB CLK
APB CLK
Generic CLK
PAC
Events
DMA
Enabled at reset
Enabled at reset
Index
Index
Prot at reset
User
Generator
Index
Y
Y
-
1
Y
-
-
-
IRQ
0x41002000
Sleep Walking
-
-
Debug Operation
Principle of Operation
The DSU provides basic services to allow on-chip debug using the Arm Debug Access Port and the Arm processor
debug resources:
• CPU reset extension
• Debugger probe detection
For more details on the Arm debug components, refer to the “Arm Debug Interface v5 Architecture Specification”.
20.6.2
CPU Reset Extension
“CPU reset extension” refers to the extension of the reset phase of the CPU core after the external reset is released.
This ensures that the CPU is not executing code at startup while a debugger connects to the system. The debugger
is detected on a RESET release event when SWCLK is low. At startup, SWCLK is internally pulled up to avoid
false detection of a debugger if the SWCLK pin is left unconnected. When the CPU is held in the reset extension
phase, the CPU Reset Extension bit of the Status A register (STATUSA.CRSTEXT) is set. To release the CPU,
write a '1' to STATUSA.CRSTEXT. STATUSA.CRSTEXT will then be set to '0'. Writing a '0' to STATUSA.CRSTEXT
has no effect. For security reasons, it is not possible to release the CPU reset extension when the device is
protected by the NVMCTRL security bit. Trying to do so sets the Protection Error bit (PERR) of the Status A register
(STATUSA.PERR).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Device Service Unit (DSU)
Figure 20-2. Typical CPU Reset Extension Set and Clear Timing Diagram
SWCLK
RESET
DSU CRSTEXT
Clear
CPU reset
extension
reset
CPU_STATE
20.6.3
running
Debugger Probe Detection
20.6.3.1 Cold Plugging
Cold-Plugging is the detection of a debugger when the system is in reset. When Cold Plugging is detected the CPU
reset extension is requested, as described above.
20.6.3.2 Hot Plugging
Hot Plugging is the detection of a debugger probe when the system is not in reset. Hot Plugging is not possible
under reset because the detector is reset when POR or RESET are asserted. Hot Plugging is active when a SWCLK
falling edge is detected. The SWCLK pad is multiplexed with other functions and the user must ensure that its default
function is assigned to the debug system. If the SWCLK function is changed, the Hot Plugging feature is disabled
until a power-reset or external reset occurs. Availability of the Hot Plugging feature can be read from the Hot Plugging
Enable bit of the Status B register (STATUSB.HPE).
Figure 20-3. Hot-Plugging Detection Timing Diagram
SWCLK
RESET
CPU_STATE
reset
running
Hot-Plugging
The presence of a debugger probe is detected when either Hot Plugging or Cold Plugging is detected. Once
detected, the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For security reasons,
Hot-Plugging is not available when the device is protected by the NVMCTRL security bit.
This detection requires that pads are correctly powered. Thus, at cold startup, this detection cannot be done until
POR is released. If the device is protected, Cold Plugging is the only way to detect a debugger probe, and so the
external reset timing must be longer than the POR timing. If external reset is deasserted before POR release, the
user must retry the procedure above until it gets connected to the device.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Device Service Unit (DSU)
20.7
Chip Erase
Chip Erase consists of removing all sensitive information stored in the chip and clearing the NVMCTRL security bit.
Therefore, all volatile memories and the Flash memory Main array and Data Flash section will be erased. The Flash
auxiliary rows, including the user row, will not be erased.
Chip Erase is only possible as long as the Set Chip Erase Hard Lock (SCEHL) command has not been issued in the
NVMCTRL.
WARNING
Once the SCEHL command has been issued, STATUS2:CEHL will be set and it becomes permanently
impossible to perform a Chip-Erase.
When the device is protected, the debugger must first reset the device in order to be detected. This ensures that
internal registers are reset after the protected state is removed. The Chip Erase operation is triggered by writing a
'1' to the Chip Erase bit in the Control register (CTRL.CE). This command will be discarded if the DSU is protected
by the Peripheral Access Controller (PAC). Once issued, the module clears volatile memories prior to erasing the
Flash array. To ensure that the Chip Erase operation is completed, check the Done bit of the Status A register
(STATUSA.DONE).
The Chip Erase operation depends on clocks and power management features that can be altered by the CPU. For
that reason, it is recommended to issue a Chip Erase after a Cold Plugging procedure to ensure that the device is in
a known and safe state.
The recommended sequence is as follows:
1. Issue the Cold Plugging procedure (refer to 20.6.3.1 Cold Plugging). The device then:
1.1.
Detects the debugger probe.
1.2.
Holds the CPU in reset.
2. Issue the Chip Erase command by writing a '1' to CTRL.CE. The device then:
2.1.
Clears the system volatile memories.
2.2.
Erases the whole Flash array (including the main array and Data Flash section, not including auxiliary
rows).
2.3.
Clears the NVMCTRL security bit protection.
3. Check for completion by polling STATUSA.DONE (read as '1' when completed).
4. Reset the device to let the NVMCTRL update the fuses.
20.8
Programming
Programming the Flash or SRAM memories is only possible when the device is not protected by the NVMCTRL
security bit. The programming procedure is as follows:
1. At power up, RESET is driven low by a debugger. The on-chip regulator holds the system in a POR state
until the input supply is above the POR threshold (refer to Power-on Reset (POR) characteristics). The system
continues to be held in this static state until the internally regulated supplies have reached a safe operating
state.
2. The PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and any Bus
Clocks that do not have clock gate control). Internal resets are maintained due to the external reset.
3. The debugger maintains a low level on SWCLK. RESET is released, resulting in a debugger Cold-Plugging
procedure.
4. The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives a clock.
5. The CPU remains in Reset due to the Cold-Plugging procedure; meanwhile, the rest of the system is released.
6. A Chip-Erase is issued to ensure that the Flash is fully erased prior to programming.
7. Programming is available through the AHB-AP.
8. After the operation is completed, the chip can be restarted either by asserting RESET or toggling power. Make
sure that the SWCLK pin is high when releasing RESET to prevent extending the CPU reset.
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
Device Service Unit (DSU)
20.9
Intellectual Property Protection
Intellectual property protection consists of restricting access to internal memories from external tools when the device
is protected, and this is accomplished by setting the NVMCTRL security bit. This protected state can be removed
by issuing a Chip-Erase (refer to Chip Erase), as long as the Set Chip Erase Hard Lock (SCEHL) command has
not been issued in the NVMCTRL. Once the SCEHL command has been issued, STATUS2:CEHL will be set and
it becomes permanently impossible to perform a Chip-Erase, and therefore permanently impossible to remove the
protected state. When the device is protected, read/write accesses using the AHB-AP are limited to the DSU address
range and DSU commands are restricted. When issuing a Chip-Erase, sensitive information is erased from volatile
memory and Flash.
The DSU implements a security filter that monitors the AHB transactions inside the DAP. If the device is protected,
then AHB-AP read/write accesses outside the DSU external address range are discarded, causing an error response
that sets the Arm AHB-AP sticky error bits (refer to the Arm Debug Interface v5 Architecture Specification on
www.arm.com).
The DSU can be accessed using any one of these options:
• Internally from the CPU, without any limitation, even when the device is protected
• Externally from a debug adapter, with some restrictions when the device is protected
For security reasons, DSU features have limitations when used from a debug adapter. To differentiate external
accesses from internal ones, the first 0x100 bytes of the DSU register map has been mirrored at offset 0x100:
• The first 0x100 bytes form the internal address range
• The next 0x100 bytes form the external address range
When the device is protected, the DAP can only issue MEM-AP accesses in the DSU range 0x0100-0x1FFF.
The DSU operating registers are located in the 0x0000-0x00FF area and remapped in 0x0100-0x01FF to differentiate
accesses coming from a debugger and the CPU. If the device is protected and an access is issued in the region
0x0100-0x01FF, it is subject to security restrictions. For more information, refer to the Table 20-1.
Figure 20-4. APB Memory Mapping
0x0000
DSU operating
registers
Internal address range
(cannot be accessed from debug tools when the device is
protected by the NVMCTRL security bit)
0x00FF
0x0100
Mirrored
DSU operating
registers
0x01FF
Empty
External address range
(can be accessed from debug tools with some restrictions)
0x1000
DSU CoreSight
ROM
0x1FFF
Some features not activated by APB transactions are not available when the device is protected:
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 175
PIC32CM MC00 Family
Device Service Unit (DSU)
Table 20-1. Feature Availability Under Protection
20.10
Features
Availability when the device is protected
CPU Reset Extension
Yes
Clear CPU Reset Extension
No
Debugger Cold-Plugging
Yes
Debugger Hot-Plugging
No
Device Identification
Device identification relies on the Arm CoreSight component identification scheme, which allows the chip to be
identified as a PIC32C device implementing a DSU. The DSU contains identification registers to differentiate the
device.
20.10.1 CoreSight Identification
A system-level Arm CoreSight ROM table is present in the device to identify the vendor and the chip identification
method. Its address is provided in the MEM-AP BASE register inside the Arm Debug Access Port. The CoreSight
ROM implements a 64-bit conceptual ID composed as follows from the PID0 to PID7 CoreSight ROM Table registers:
Figure 20-5. Conceptual 64-bit Peripheral ID
Table 20-2. Conceptual 64-Bit Peripheral ID Bit Descriptions
Field
Size Description
Location
JEP-106 CC code 4
Continuation code: 0x0
PID4
JEP-106 ID code
7
Device ID: 0x1F
PID1+PID2
4KB count
4
Indicates that the CoreSight component is a ROM: 0x0
PID4
RevAnd
4
Not used; read as 0
PID3
CUSMOD
4
Not used; read as 0
PID3
PARTNUM
12
Contains 0xCD0 to indicate that DSU is present
PID0+PID1
REVISION
4
DSU revision (starts at 0x0 and increments by 1 at both major and
minor revisions). Identifies DSU identification method variants. If 0x0, this
indicates that device identification can be completed by reading the Device
Identification register (DID)
PID2
For more information, refer to the Arm Debug Interface Version 5 Architecture Specification.
20.10.2 Chip Identification Method
The DSU DID register identifies the device by implementing the following information:
•
Processor identification
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Datasheet
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PIC32CM MC00 Family
Device Service Unit (DSU)
•
•
•
20.11
Product family identification
Product series identification
Device select
Functional Description
20.11.1 Principle of Operation
The DSU provides a CRC32 or MBIST memory service. The Address, Length and Data registers (ADDR, LENGTH,
DATA) must be configured first; then a command can be issued by writing the Control register. When a command is
ongoing, other commands are discarded until the current operation is completed. Therefore, the user must wait for
the STATUSA.DONE bit to be set prior to issuing another one.
20.11.2 Basic Operation
20.11.2.1 Initialization
The module is enabled by enabling its clocks. The DSU registers can be PAC write-protected.
20.11.2.2 Operation From a Debug Adapter
Debug adapters should access the DSU registers in the external address range 0x100 – 0x1FFF. If the device is
protected by the NVMCTRL 26.5.6 Security Bit and Chip Erase Hard Lock Bit, accessing the first 0x100 bytes
causes the system to return an error. Refer to 20.9 Intellectual Property Protection.
20.11.2.3 Operation From the CPU
There are no restrictions when accessing DSU registers from the CPU. However, the user should access DSU
registers in the internal address range (0x0 – 0x100) to avoid external security restrictions. Refer to 20.9 Intellectual
Property Protection.
20.11.3 32-bit Cyclic Redundancy Check CRC32
The DSU unit provides support for calculating a cyclic redundancy check (CRC32) value for a memory area
(including Flash and SRAM).
When the CRC32 command is issued from:
• The internal range, the CRC32 can be operated at any memory location
• The external range, the CRC32 operation is restricted; DATA, ADDR, and LENGTH values are forced (see
below)
Table 20-3. AMOD Bit Descriptions when Operating CRC32
AMOD[1:0] Short name External range restrictions
0
ARRAY
CRC32 is restricted to the full Flash array area (Data Flash section not included). DATA
forced to 0xFFFFFFFF before calculation (no seed)
1
Data Flash
CRC32 of the whole Data Flash section. DATA forced to 0xFFFFFFFF before calculation
(no seed)
2-3
Reserved
The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial 0xEDB88320
(reversed representation).
20.11.3.1 Starting CRC32 Calculation
CRC32 calculation for a memory range is started after writing the start address into the Address register (ADDR) and
the size of the memory range into the Length register (LENGTH). Both must be word-aligned.
The initial value used for the CRC32 calculation must be written to the Data register (DATA). This value will usually be
0xFFFFFFFF, but can be, for example, the result of a previous CRC32 calculation if generating a common CRC32 of
separate memory blocks.
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
Device Service Unit (DSU)
Once completed, the calculated CRC32 value can be read out of the Data register. The read value must be
complemented to match standard CRC32 implementations or kept non-inverted if used as starting point for
subsequent CRC32 calculations.
The actual test is started by writing a '1' in the 32-bit Cyclic Redundancy Check bit of the Control register
(CTRL.CRC). A running CRC32 operation can be canceled by resetting the module (writing '1' to CTRL.SWRST).
20.11.3.2 Interpreting the Results
The user should monitor the Status A register. When the operation is completed, STATUSA.DONE is set. Then the
Bus Error bit of the Status A register (STATUSA.BERR) must be read to ensure that no bus error occurred.
20.11.4 Debug Communication Channels
The Debug Communication Channels (DCCO and DCC1) consist of a pair of registers with associated handshake
logic, accessible by both CPU and debugger even if the device is protected by the NVMCTRL security bit. The
registers can be used to exchange data between the CPU and the debugger, during run time as well as in debug
mode. This enables the user to build a custom debug protocol using only these registers.
The DCC0 and DCC1 registers are accessible when the protected state is active. When the device is protected,
however, it is not possible to connect a debugger while the CPU is running (STATUSA.CRSTEXT is not writable and
the CPU is held under Reset).
Two Debug Communication Channel status bits in the Status B registers (STATUS.DCCDx) indicate whether a new
value has been written in DCC0 or DCC1. These bits, DCC0D and DCC1D, are located in the STATUSB registers.
They are automatically set on write and cleared on read.
Note: The DCC0 and DCC1 registers are shared with the on-board memory testing logic (MBIST). Accordingly,
DCC0 and DCC1 must not be used while performing MBIST operations.
20.11.5 Testing of On-Board Memories MBIST
The DSU implements a feature for automatic testing of memory, also known as MBIST (memory built-in self test).
This is primarily intended for production test of on-board memories. MBIST cannot be operated from the external
address range when the device is protected by the NVMCTRL security bit. If an MBIST command is issued
when the device is protected, a protection error is reported in the Protection Error bit in the Status A register
(STATUSA.PERR).
1.
Algorithm
The algorithm used for testing is a type of March algorithm called "March LR". This algorithm is able to detect
a wide range of memory defects, while still keeping a linear run time. The algorithm is:
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
Write entire memory to '0', in any order.
Bit by bit read '0', write '1', in descending order.
Bit by bit read '1', write '0', read '0', write '1', in ascending order.
Bit by bit read '1', write '0', in ascending order.
Bit by bit read '0', write '1', read '1', write '0', in ascending order.
Read '0' from entire memory, in ascending order.
The specific implementation used as a run time which depends on the CPU clock frequency and the number of
bytes tested in the RAM. The detected faults are:
2.
– Address decoder faults
– Stuck-at faults
– Transition faults
– Coupling faults
– Linked Coupling faults
Starting MBIST
To test a memory, you need to write the start address of the memory to the ADDR.ADDR bit field, and the size
of the memory into the Length register.
For best test coverage, an entire physical memory block should be tested at once. It is possible to test only a
subset of a memory, but the test coverage will then be somewhat lower.
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
Device Service Unit (DSU)
3.
4.
The actual test is started by writing a '1' to CTRL.MBIST. A running MBIST operation can be canceled by
writing a '1' to CTRL.SWRST.
Interpreting the Results
The tester should monitor the STATUSA register. When the operation is completed, STATUSA.DONE is set.
There are two different modes:
– ADDR.AMOD=0: exit-on-error (default)
In this mode, the algorithm terminates either when a fault is detected or on successful completion. In both
cases, STATUSA.DONE is set. If an error was detected, STATUSA.FAIL will be set. User then can read
the DATA and ADDR registers to locate the fault.
– ADDR.AMOD=1: pause-on-error
In this mode, the MBIST algorithm is paused when an error is detected. In such a situation, only
STATUSA.FAIL is asserted. The state machine waits for user to clear STATUSA.FAIL by writing a '1' in
STATUSA.FAIL to resume. Prior to resuming, user can read the DATA and ADDR registers to locate the
fault.
Locating Faults
If the test stops with STATUSA.FAIL set, one or more bits failed the test. The test stops at the first detected
error. The position of the failing bit can be found by reading the following registers:
– ADDR: Address of the word containing the failing bit
– DATA: contains data to identify which bit failed, and during which phase of the test it failed. The DATA
register will in this case contains the following bit groups:
Figure 20-6. DATA bits Description When MBIST Operation Returns an Error
Bit
31
30
29
28
27
26
25
24
Bit
23
22
21
20
19
18
17
16
Bit
15
14
13
12
11
10
9
8
phase
Bit
7
6
5
4
3
2
0
1
bit_index
•
•
bit_index: contains the bit number of the failing bit
phase: indicates which phase of the test failed and the cause of the error, as listed in the following table.
Table 20-4. MBIST Operation Phases
Phase
Test actions
0
Write all bits to zero. This phase cannot fail.
1
Read '0', write '1', increment address
2
Read '1', write '0'
3
Read '0', write '1', decrement address
4
Read '1', write '0', decrement address
5
Read '0', write '1'
6
Read '1', write '0', decrement address
7
Read all zeros. bit_index is not used
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 179
PIC32CM MC00 Family
Device Service Unit (DSU)
Table 20-5. AMOD Bit Descriptions for MBIST
AMOD[1:0]
Description
0x0
Exit on Error
0x1
Pause on Error
0x2, 0x3
Reserved
20.11.6 System Services Availability when Accessed Externally and Device is Protected
External access: Access performed in the DSU address offset 0x100-0x1FFF range.
Internal access: Access performed in the DSU address offset 0x000-0x0FF range.
Table 20-6. Available Features when Operated From The External Address Range and Device is Protected
Features
Availability From The External Address Range and
Device is Protected
Chip-Erase command and status
Yes
CRC32
Yes, only full array or full Data Flash section
CoreSight Compliant Device identification
Yes
Debug communication channels
Yes
STATUSA.CRSTEXT clearing
No (STATUSA.PERR is set when attempting to do so)
Testing of onboard memories (MBIST)
No
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
Device Service Unit (DSU)
20.12
Register Summary
Offset
Name
Bit Pos.
7
6
0x00
0x01
0x02
0x03
CTRL
STATUSA
STATUSB
Reserved
7:0
7:0
7:0
Reserved
Reserved
0x04
ADDR
0x08
LENGTH
0x0C
DATA
0x10
DCC0
0x14
DCC1
0x18
DID
0x1C
...
0x0FFF
0x1000
ENTRY0
ENTRY1
0x1008
END
0x100C
...
0x1FCB
Reserved
0x1FD0
4
3
2
1
0
CEHL
CE
PERR
HPE
MBIST
FAIL
DCCD1
CRC
BERR
DCCD0
CRSTEXT
DBGPRES
SWRST
DONE
PROT
ADDR[5:0]
AMOD[1:0]
ADDR[13:6]
ADDR[21:14]
ADDR[29:22]
LENGTH[5:0]
LENGTH[13:6]
LENGTH[21:14]
LENGTH[29:22]
DATA[7:0]
DATA[15:8]
DATA[23:16]
DATA[31:24]
DATA[7:0]
DATA[15:8]
DATA[23:16]
DATA[31:24]
DATA[7:0]
DATA[15:8]
DATA[23:16]
DATA[31:24]
DEVSEL[7:0]
DIE[3:0]
REVISION[3:0]
FAMILY[0]
SERIES[5:0]
PROCESSOR[3:0]
FAMILY[4:1]
Reserved
0x1004
0x1FCC
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
5
MEMTYPE
PID4
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
© 2021 Microchip Technology Inc.
and its subsidiaries
FMT
EPRES
Reserved
Reserved
ADDOFF[3:0]
ADDOFF[11:4]
ADDOFF[19:12]
Reserved[3:0]
Reserved[11:4]
Reserved[19:12]
END[7:0]
END[15:8]
END[23:16]
END[31:24]
SMEMP
FKBC[3:0]
JEPCC[3:0]
Datasheet
DS60001638D-page 181
PIC32CM MC00 Family
Device Service Unit (DSU)
...........continued
Offset
Name
0x1FD4
...
0x1FDF
Reserved
0x1FE0
0x1FE4
0x1FE8
0x1FEC
0x1FF0
0x1FF4
0x1FF8
0x1FFC
Bit Pos.
PID0
PID1
PID2
PID3
CID0
CID1
CID2
CID3
7
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
© 2021 Microchip Technology Inc.
and its subsidiaries
6
5
4
3
2
1
0
PARTNBL[7:0]
JEPIDCL[3:0]
PARTNBH[3:0]
REVISION[3:0]
JEPU
REVAND[3:0]
JEPIDCH[2:0]
CUSMOD[3:0]
PREAMBLEB0[7:0]
CCLASS[3:0]
PREAMBLE[3:0]
PREAMBLEB2[7:0]
PREAMBLEB3[7:0]
Datasheet
DS60001638D-page 182
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.1 Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
CTRL
0x0000
0x00
PAC Write-Protection
7
Reserved
0
6
Reserved
0
5
4
CE
W
0
3
MBIST
W
0
2
CRC
W
0
1
0
SWRST
W
0
Bit 7 – Reserved
Must be set to 0.
Bit 6 – Reserved
Must be set to 0.
Bit 4 – CE Chip-Erase
Writing a '0' to this bit has no effect.
Writing a '1' to this bit starts the Chip-Erase operation.
Note: The chip erase operation can only be performed if the Chip Erase Hard Lock has not been set
(STATUS2:CEHL=0). Once STATUS2:CEHL=1, the chip erase feature becomes permanently disabled.
Bit 3 – MBIST Memory Built-In Self-Test
Writing a '0' to this bit has no effect.
Writing a '1' to this bit starts the memory BIST algorithm.
Bit 2 – CRC 32-bit Cyclic Redundancy Check
Writing a '0' to this bit has no effect.
Writing a '1' to this bit starts the cyclic redundancy check algorithm.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets the module.
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PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.2 Status A
Name:
Offset:
Reset:
Property:
Bit
7
STATUSA
0x0001
0x00
PAC Write-Protection
6
5
Access
Reset
4
PERR
R/W
0
3
FAIL
R/W
0
2
BERR
R/W
0
1
CRSTEXT
R/W
0
0
DONE
R/W
0
Bit 4 – PERR Protection Error
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Protection Error bit.
This bit is set when a command that is not allowed in protected state is issued.
Bit 3 – FAIL Failure
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Failure bit.
This bit is set when a DSU operation failure is detected.
Bit 2 – BERR Bus Error
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Bus Error bit.
This bit is set when a bus error is detected.
Bit 1 – CRSTEXT CPU Reset Phase Extension
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the CPU Reset Phase Extension bit.
This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPU reset phase.
Bit 0 – DONE Done
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Done bit.
This bit is set when a DSU operation is completed.
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PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.3 Status B
Name:
Offset:
Reset:
Property:
Bit
STATUSB
0x0002
x determined by Security Bit (SB) and Chip Erase Hard Lock (CEHL) bit configuration before reset
PAC Write-Protection
7
6
Access
Reset
5
CEHL
R
x
4
HPE
R
1
3
DCCD1
R
0
2
DCCD0
R
0
1
DBGPRES
R
0
0
PROT
R
x
Bit 5 – CEHL Chip Erase Hard Lock status bit
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
Reading 1 means the debugger chip erase hard lock is permanently set. It is no more possible to perform a debugger
chip erase.
Reading 0 means the debugger chip erase hard lock is not set and it is still possible to perform a debugger chip
erase.
Bit 4 – HPE Hot-Plugging Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set when Hot-Plugging is enabled.
This bit is cleared when Hot-Plugging is disabled. This is the case when the SWCLK function is changed. Only a
power-reset or a external reset can set it again.
Bits 2, 3 – DCCDx Debug Communication Channel x Dirty [x = 1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set when DCCx is written.
This bit is cleared when DCCx is read.
Bit 1 – DBGPRES Debugger Present
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set when a debugger probe is detected.
This bit is never cleared.
Bit 0 – PROT Protected
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set at power-up when the device is protected (Meaning the Security Bit has been set).
This bit is never cleared.
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Datasheet
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PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.4 Address
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
ADDR
0x0004
0x00000000
PAC Write-Protection
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
28
27
ADDR[29:22]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
4
3
2
1
20
19
ADDR[21:14]
R/W
R/W
0
0
12
ADDR[13:6]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
7
6
5
0
ADDR[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
AMOD[1:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:2 – ADDR[29:0] Address
Initial word start address needed for memory operations.
Bits 1:0 – AMOD[1:0] Access Mode
The functionality of these bits is dependent on the operation mode.
Bit description when operating CRC32: refer to 20.11.3 32-bit Cyclic Redundancy Check CRC32.
Bit description when testing onboard memories (MBIST): refer to Testing of On-Board Memories MBIST.
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.5 Length
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
LENGTH
0x0008
0x00000000
PAC Write-Protection
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
28
27
LENGTH[29:22]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
20
19
LENGTH[21:14]
R/W
R/W
0
0
12
11
LENGTH[13:6]
R/W
R/W
0
0
4
LENGTH[5:0]
R/W
R/W
0
0
Bits 31:2 – LENGTH[29:0] Length
Length in words needed for memory operations.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 187
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.6 Data
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
DATA
0x000C
0x00000000
PAC Write-Protection
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
28
27
DATA[31:24]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
20
19
DATA[23:16]
R/W
R/W
0
0
12
DATA[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DATA[31:0] Data
Memory operation initial value or result value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 188
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.7 Debug Communication Channel 0
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
DCC0
0x0010
0x00000000
-
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
28
27
DATA[31:24]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
20
19
DATA[23:16]
R/W
R/W
0
0
12
DATA[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DATA[31:0] Data
Data register. This register holds the last written data from either the DAP or the APB interface
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 189
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.8 Debug Communication Channel 1
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
DCC1
0x0014
0x00000000
-
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
28
27
DATA[31:24]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
20
19
DATA[23:16]
R/W
R/W
0
0
12
DATA[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DATA[31:0] Data
Data register. This register holds the last written data from either the DAP or the APB interface
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 190
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.9 Device Identification
Name:
Offset:
Property:
DID
0x0018
-
The information in this register is related to the 2. Ordering Information.
Bit
Access
Reset
Bit
Access
Reset
Bit
31
30
29
PROCESSOR[3:0]
R
R
0
0
28
R
1
R
0
23
FAMILY[0]
R
0
22
20
19
15
14
R
0
21
27
26
25
24
R
0
R
0
R
1
18
17
16
FAMILY[4:1]
SERIES[5:0]
R
0
R
0
R
0
R
1
R
1
R
0
13
12
11
8
R
r
10
9
REVISION[3:0]
R
R
r
r
R
r
3
2
1
0
R
x
R
x
R
x
R
x
DIE[3:0]
Access
Reset
R
d
R
d
R
d
R
d
Bit
7
6
5
4
DEVSEL[7:0]
Access
Reset
R
x
R
x
R
x
R
x
Bits 31:28 – PROCESSOR[3:0] Processor
The value of this field defines the processor used on the device. For this device, the value of this field is 0x1,
corresponding to a PIC32CM microcontroller embedding an ARM Cortex-M0+ processor.
Bits 27:23 – FAMILY[4:0] Product Family
The value of this field corresponds to the Product Family part of the Ordering Information. For this device, the value
of this field is 0x2, corresponding to the PIC32CM Entry Level 5V tolerant Family.
Bits 21:16 – SERIES[5:0] Product Series
The Series field is a subset of the Family field. For this device, the value of this field is 0x07.
Bits 15:12 – DIE[3:0] Die Number
Identifies the mask within a family and series. For this device, the value of this field is 0x0.
Bits 11:8 – REVISION[3:0] Revision Number
Identifies the die revision number. 0x0 = rev.A1, 0x1 = rev.A2, and so on.
Bits 7:0 – DEVSEL[7:0] Device Selection
This bit field identifies a device within a product family and product series. The value corresponds to the Flash
memory density, pin count and device variant parts of the ordering code.
Value
Description
0x00
128 KB Flash, 16 KB SRAM, 32-pin
0x01
64 KB Flash, 8 KB SRAM, 32-pin
0x02
Reserved
0x03-0x0 Reserved
5
0x06
128 KB Flash, 16 KB SRAM, 48-pin
0x07
64 KB Flash, 8 KB SRAM, 48-pin
0x08
Reserved
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 191
PIC32CM MC00 Family
Device Service Unit (DSU)
Value
Other
Description
Reserved
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 192
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.10 CoreSight ROM Table Entry 0
Name:
Offset:
Reset:
Property:
ENTRY0
0x1000
0x9F0FC002
-
Bit
31
30
29
28
27
ADDOFF[19:12]
R
R
x
x
26
25
24
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
Bit
23
22
21
18
17
16
R
x
20
19
ADDOFF[11:4]
R
R
x
x
Access
Reset
R
x
R
x
R
x
R
x
R
x
Bit
15
14
13
12
11
10
9
8
3
2
1
FMT
R
1
0
EPRES
R
x
ADDOFF[3:0]
Access
Reset
R
x
R
x
R
x
R
x
Bit
7
6
5
4
Access
Reset
Bits 31:12 – ADDOFF[19:0] Address Offset
The base address of the component, relative to the base address of this ROM table.
Bit 1 – FMT Format
Always reads as '1', indicating a 32-bit ROM table.
Bit 0 – EPRES Entry Present
This bit indicates whether an entry is present at this location in the ROM table.
This bit is set at power-up if the device is not protected indicating that the entry is present.
This bit is cleared at power-up if the device is protected indicating that the entry is not present.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 193
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.11 CoreSight ROM Table Entry 1
Name:
Offset:
Reset:
Property:
ENTRY1
0x1004
0xXXXXX00X
-
Bit
31
30
29
28
27
Reserved[19:12]
R
R
x
x
26
25
24
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
Bit
23
22
21
20
19
Reserved[11:4]
R
R
x
x
18
17
16
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
Bit
15
12
11
10
9
8
R
x
14
13
Reserved[3:0]
R
R
x
x
Access
Reset
Bit
7
6
4
3
2
1
Reserved
R
x
0
Reserved
R
x
5
R
x
Access
Reset
Bits 31:12 – Reserved[19:0]
Bit 1 – Reserved
Bit 0 – Reserved
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 194
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.12 CoreSight ROM Table End
Name:
Offset:
Reset:
Property:
Bit
31
END
0x1008
0x00000000
-
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
END[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
END[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
END[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
END[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – END[31:0] End Marker
Indicates the end of the CoreSight ROM table entries.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 195
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.13 CoreSight ROM Table Memory Type
Name:
Offset:
Reset:
Property:
Bit
MEMTYPE
0x1FCC
0x0000000x
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SMEMP
R
x
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – SMEMP System Memory Present
This bit indicates whether system memory is present on the bus that connects to the ROM table.
This bit is set at power-up if the device is not protected, indicating that the system memory is accessible from a
debug adapter.
This bit is cleared at power-up if the device is protected, indicating that the system memory is not accessible from a
debug adapter.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 196
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.14 Peripheral Identification 4
Name:
Offset:
Reset:
Property:
Bit
PID4
0x1FD0
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
FKBC[3:0]
Access
Reset
R
0
R
0
JEPCC[3:0]
R
0
R
0
R
0
R
0
Bits 7:4 – FKBC[3:0] 4KB Count
These bits will always return zero when read, indicating that this debug component occupies one 4KB block.
Bits 3:0 – JEPCC[3:0] JEP-106 Continuation Code
These bits will always return zero when read.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 197
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.15 Peripheral Identification 0
Name:
Offset:
Reset:
Property:
Bit
PID0
0x1FE0
0x000000D0
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
PARTNBL[7:0]
Access
Reset
R
1
R
1
R
0
R
1
Bits 7:0 – PARTNBL[7:0] Part Number Low
These bits will always return 0xD0 when read, indicating that this device implements a DSU module instance.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 198
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.16 Peripheral Identification 1
Name:
Offset:
Reset:
Property:
Bit
PID1
0x1FE4
0x000000FC
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
R
1
R
1
R
1
1
PARTNBH[3:0]
R
R
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
JEPIDCL[3:0]
Access
Reset
R
1
R
1
R
0
Bits 7:4 – JEPIDCL[3:0] Low part of the JEP-106 Identity Code
These bits will always return 0xF when read (JEP-106 identity code is 0x1F).
Bits 3:0 – PARTNBH[3:0] Part Number High
These bits will always return 0xC when read, indicating that this device implements a DSU module instance.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 199
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.17 Peripheral Identification 2
Name:
Offset:
Reset:
Property:
Bit
PID2
0x1FE8
0x00000009
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
4
1
JEPIDCH[2:0]
R
0
0
R
0
3
JEPU
R
1
2
Access
Reset
5
REVISION[3:0]
R
R
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R
0
R
0
R
1
Bits 7:4 – REVISION[3:0] Revision Number
Revision of the peripheral. Starts at 0x0 and increments by one at both major and minor revisions.
Bit 3 – JEPU JEP-106 Identity Code is used
This bit will always return one when read, indicating that JEP-106 code is used.
Bits 2:0 – JEPIDCH[2:0] JEP-106 Identity Code High
These bits will always return 0x1 when read, (JEP-106 identity code is 0x1F).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 200
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.18 Peripheral Identification 3
Name:
Offset:
Reset:
Property:
Bit
PID3
0x1FEC
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
REVAND[3:0]
Access
Reset
R
0
R
0
CUSMOD[3:0]
R
0
R
0
R
0
R
0
Bits 7:4 – REVAND[3:0] Revision Number
These bits will always return 0x0 when read.
Bits 3:0 – CUSMOD[3:0] ARM CUSMOD
These bits will always return 0x0 when read.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 201
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.19 Component Identification 0
Name:
Offset:
Reset:
Property:
Bit
CID0
0x1FF0
0x0000000D
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
5
2
1
0
Access
Reset
R
0
R
0
R
0
4
3
PREAMBLEB0[7:0]
R
R
0
1
R
1
R
0
R
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 7:0 – PREAMBLEB0[7:0] Preamble Byte 0
These bits will always return 0x0000000D when read.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 202
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.20 Component Identification 1
Name:
Offset:
Reset:
Property:
Bit
CID1
0x1FF4
0x00000010
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
0
R
0
R
1
R
0
2
1
PREAMBLE[3:0]
R
R
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
CCLASS[3:0]
Access
Reset
R
0
R
0
R
0
Bits 7:4 – CCLASS[3:0] Component Class
These bits will always return 0x1 when read indicating that this Arm CoreSight component is ROM table (refer to the
Arm Debug Interface v5 Architecture Specification at http://www.arm.com).
Bits 3:0 – PREAMBLE[3:0] Preamble
These bits will always return 0x00 when read.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 203
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.21 Component Identification 2
Name:
Offset:
Reset:
Property:
Bit
CID2
0x1FF8
0x00000005
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
5
2
1
0
Access
Reset
R
0
R
0
R
0
4
3
PREAMBLEB2[7:0]
R
R
0
0
R
1
R
0
R
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 7:0 – PREAMBLEB2[7:0] Preamble Byte 2
These bits will always return 0x00000005 when read.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 204
PIC32CM MC00 Family
Device Service Unit (DSU)
20.12.22 Component Identification 3
Name:
Offset:
Reset:
Property:
Bit
CID3
0x1FFC
0x000000B1
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
5
2
1
0
Access
Reset
R
1
R
0
R
1
4
3
PREAMBLEB3[7:0]
R
R
1
0
R
0
R
0
R
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 7:0 – PREAMBLEB3[7:0] Preamble Byte 3
These bits will always return 0x000000B1 when read.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 205
PIC32CM MC00 Family
Divide and Square Root Accelerator (DIVAS)
21.
Divide and Square Root Accelerator (DIVAS)
21.1
Overview
The Divide and Square Root Accelerator (DIVAS) is a programmable 32-bit signed or unsigned hardware divider and
a 32-bit unsigned square root hardware engine. The DIVAS is connected to the high-speed bus matrix and may also
be accessed using the low-latency CPU local bus (IOBUS; Arm single-cycle I/O port). The DIVAS takes dividend and
divisor values and returns the quotient and remainder when it is used as divider. The DIVAS takes unsigned input
value and returns its square root and remainder when it is used as square root function.
21.2
Features
•
•
•
•
•
•
•
•
•
21.3
Division accelerator for Cortex-M0+ systems
32-bit signed or unsigned integer division
32-bit unsigned square root
32-bit division in 2-16 cycles
Programmable leading zero optimization
Result includes quotient and remainder
Result includes square root and remainder
Busy and Divide-by-zero status
Automatic start of operation when divisor or square root input is loaded
Block Diagram
Figure 21-1. DIVAS Block Diagram
DIVAS
DEVIDE ENGINE
DIVIDEND
AHB
DIVISOR
CTRLA
QUOTIENT
REMAINDER
21.4
Peripheral Dependencies
Peripheral
DIVAS
21.5
21.5.1
IOBUS
INTERFACE
Base Address
0x48000000
AHB CLK
APB CLK
Generic CLK
PAC
Events
DMA
Enabled at reset
Enabled at reset
Index
Index
Prot at reset
User
Generator
Index
Y
-
-
-
-
-
-
-
IRQ
Sleep Walking
-
-
Functional Description
Principle of Operation
The Divide and Square Root Accelerator (DIVAS) supports signed or unsigned hardware division of 32-bit values
and unsigned square root of 32-bit value. It is accessible from the CPU via both the AHB bus and IOBUS. When
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 206
PIC32CM MC00 Family
Divide and Square Root Accelerator (DIVAS)
the dividend and divide registers are programmed, the division starts and the result will be stored in the Result and
Remainder registers. The Busy and Divide-by-zero status can be read from STATUS register.
When the square root input register (21.6.7 SQRNUM) is programmed, the square root function starts and the result
will be stored in the Result and Remainder registers. The Busy status can be read from STATUS register.
21.5.2
Basic Operation
21.5.2.1 Initialization
The DIVAS configuration cannot be modified while a divide operation is ongoing. The following bits must be written
prior to starting a division:
•
•
Sign selection bit in Control A register (21.6.1 CTRLA.SIGNED)
Leading zero mode bit in Control A register (21.6.1 CTRLA.DLZ)
21.5.2.2 Performing Division
First write the dividend to DIVIDEND register. Writing the divisor to DIVISOR register starts the division and sets the
busy bit in the Status register (STATUS.BUSY). When the division has completed, the STATUS.BUSY bit is cleared
and the result will be stored in RESULT and REM registers.
The RESULT and REM registers can be read directly through the high-speed bus without checking first
STATUS.BUSY. Wait states will be inserted on the high-speed bus until the operation is complete. The IOBUS does
not support wait states. For accesses through the IOBUS, the STATUS.BUSY bit must be polled before reading the
result from the RESULT and REM registers.
21.5.2.3 Operand Size
Divide
The DIVAS can perform 32-bit signed and unsigned division and the operation follows the equation as below.
RESULT 31: 0 = DIVIDEND 31: 0 /DIVISOR 31: 0
REMAINDER 31: 0 = DIVIDEND 31: 0 % DIVISOR 31: 0
DIVAS completes 32-bit division in 2-16 cycles.
Square Root
The DIVAS can perform 32-bit unsigned division and the operation follows the equation as below.
RESULT 31: 0 =
SQRNUM 31: 0
REMAINDER 31: 0 = SQRNUM 31: 0 − RESULT 31: 0
21.5.2.4 Signed Division
2
When CTRLA.SIGNED is one, both the input and the result will be in 2’s complement format. The results of signed
division are such that the remainder and dividend have the same sign and the quotient is negative if the dividend
and divisor have opposite signs. 16-bit results are sign extended to 32-bits. Note that when the maximum negative
number is divided by the minimum negative number, the resulting quotient overflows the signed integer range and will
return the maximum negative number with no indication of the overflow. This occurs for 0x80000000 / 0xFFFFFFFF
in 32-bit operation and 0x8000 / 0xFFFF in 16-bit operation.
21.5.2.5 Divide By Zero
A divide by zero fault occurs if the DIVISOR is programmed to zero. QUOTIENT will be zero and the REM is equal
to DIVIDEND. Divide by zero sets the Divide-by-zero bit in the Status register (STATUS.DBZ) to one. STATUS.DBZ
must be cleared by writing a one to it.
21.5.2.6 Leading Zero Optimization
Leading zero optimization can reduce the time it takes to complete a division by skipping leading zeros in the
DIVIDEND (or leading ones in signed mode). Leading zero optimization is enabled by default and can be disabled
by the Disable Leading Zero bit in the Control A register (CTRLA.DLZ). When CTRLA.DLZ is zero, 16-bit division
completes in 2-8 cycles and 32-bit division completes in 2-16 cycles, depending on the dividend value. If deterministic
timing is required, setting CTRLA.DLZ to one forces 16-bit division to always take 8 cycles and 32-bit division to
always take 16 cycles.
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and its subsidiaries
Datasheet
DS60001638D-page 207
PIC32CM MC00 Family
Divide and Square Root Accelerator (DIVAS)
21.5.2.7 Unsigned Square Root
When the square root input register (21.6.7 SQRNUM) is programmed, the square root function starts and the result
will be stored in the Result and Remainder registers. The Busy status can be read from STATUS register.
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Datasheet
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PIC32CM MC00 Family
Divide and Square Root Accelerator (DIVAS)
21.6
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
...
0x03
0x04
0x05
...
0x07
CTRLA
7
6
5
4
3
2
1
0
7:0
DLZ
SIGNED
7:0
DBZ
BUSY
Reserved
STATUS
Reserved
0x08
DIVIDEND
0x0C
DIVISOR
0x10
RESULT
0x14
REM
0x18
SQRNUM
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
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DIVIDEND[7:0]
DIVIDEND[15:8]
DIVIDEND[23:16]
DIVIDEND[31:24]
DIVISOR[7:0]
DIVISOR[15:8]
DIVISOR[23:16]
DIVISOR[31:24]
RESULT[7:0]
RESULT[15:8]
RESULT[23:16]
RESULT[31:24]
REM[7:0]
REM[15:8]
REM[23:16]
REM[31:24]
SQRNUM[7:0]
SQRNUM[15:8]
SQRNUM[23:16]
SQRNUM[31:24]
Datasheet
DS60001638D-page 209
PIC32CM MC00 Family
Divide and Square Root Accelerator (DIVAS)
21.6.1
Control A
Name:
Offset:
Reset:
Property:
Bit
CTRLA
0x00
0x00
-
7
6
5
4
3
Access
Reset
2
1
DLZ
R/W
0
0
SIGNED
R/W
0
Bit 1 – DLZ Disable Leading Zero Optimization
Value
Description
0
Enable leading zero optimization; 32-bit division takes 2-16 cycles.
1
Disable leading zero optimization; 32-bit division takes 16 cycles.
Bit 0 – SIGNED Signed Division Enable
Value
Description
0
Unsigned division.
1
Signed division.
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Datasheet
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PIC32CM MC00 Family
Divide and Square Root Accelerator (DIVAS)
21.6.2
Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x04
0x00
-
7
6
5
4
3
Access
Reset
2
1
DBZ
R/W
0
0
BUSY
R/W
0
Bit 1 – DBZ Disable-By-Zero
Writing a zero to this bit has no effect.
Writing a one to this bit clears DBZ to zero.
Value
Description
0
A divide-by-zero fault has not occurred
1
A divide-by-zero fault has occurred
Bit 0 – BUSY DIVAS Accelerator Busy
This bit is set when a value is written to the 21.6.4 DIVISOR or 21.6.7 SQRNUM registers.
This bit is cleared when either division or square root function completes and results are ready in the 21.6.5 RESULT
and REM registers.
Value
Description
0
DIVAS is idle
1
DIVAS is busy with an ongoing division
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Datasheet
DS60001638D-page 211
PIC32CM MC00 Family
Divide and Square Root Accelerator (DIVAS)
21.6.3
Dividend
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
DIVIDEND
0x08
0x0000
-
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
DIVIDEND[31:24]
R/W
R/W
0
0
20
19
DIVIDEND[23:16]
R/W
R/W
0
0
12
11
DIVIDEND[15:8]
R/W
R/W
0
0
4
3
DIVIDEND[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DIVIDEND[31:0] Dividend Value
Holds the 32-bit dividend for the divide operation. If the Signed bit in Control A register (CTRLA.SIGNED) is zero,
DIVIDEND is unsigned. If CTRLA.SIGNED = 1, DIVIDEND is signed two’s complement. Refer to 21.5.2.2 Performing
Division, 21.5.2.3 Operand Size and 21.5.2.4 Signed Division.
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Datasheet
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PIC32CM MC00 Family
Divide and Square Root Accelerator (DIVAS)
21.6.4
Divisor
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
DIVISOR
0x0C
0x0000
-
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
DIVISOR[31:24]
R/W
R/W
0
0
20
19
DIVISOR[23:16]
R/W
R/W
0
0
12
11
DIVISOR[15:8]
R/W
R/W
0
0
4
3
DIVISOR[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DIVISOR[31:0] Divisor Value
Holds the 32-bit divisor for the divide operation. If the Signed bit in Control A register (CTRLA.SIGNED) is zero,
DIVISOR is unsigned. If CTRLA.SIGNED = 1, DIVISOR is signed two’s complement. Writing the DIVISOR register
will start the divide function. Refer to 21.5.2.2 Performing Division, 21.5.2.3 Operand Size and 21.5.2.4 Signed
Division.
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Datasheet
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PIC32CM MC00 Family
Divide and Square Root Accelerator (DIVAS)
21.6.5
Result
Name:
Offset:
Reset:
Property:
RESULT
0x10
0x0000
-
Bit
31
30
29
28
27
RESULT[31:24]
R
R
0
0
26
25
24
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
Bit
23
22
21
20
19
RESULT[23:16]
R
R
0
0
18
17
16
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
10
9
8
R
0
12
11
RESULT[15:8]
R
R
0
0
Access
Reset
R
0
R
0
R
0
R
0
R
0
Bit
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
RESULT[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – RESULT[31:0] Result of Operation
Holds the 32-bit result of the last performed operation. For a divide operation this is the quotient. If the Signed bit
in Control A register (CTRLA.SIGNED) is zero, the quotient is unsigned. If CTRLA.SIGNED = 1, the quotient is
signed two’s complement. For a square root operation this is the square root. Refer to 21.5.2.2 Performing Division,
21.5.2.3 Operand Size and 21.5.2.4 Signed Division.
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Datasheet
DS60001638D-page 214
PIC32CM MC00 Family
Divide and Square Root Accelerator (DIVAS)
21.6.6
Remainder
Name:
Offset:
Reset:
Property:
Bit
REM
0x14
0x0000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
REM[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
REM[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
REM[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
REM[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – REM[31:0] Remainder of Operation
Holds the 32-bit remainder of the last performed operation. For a divide operation this is the division remainder.
If the Signed bit in Control A register (CTRLA.SIGNED) is zero, the quotient is unsigned. If CTRLA.SIGNED = 1,
the quotient is signed two’s complement. For a square root operation this is the square root remainder. Refer to
21.5.2.2 Performing Division, 21.5.2.3 Operand Size and 21.5.2.4 Signed Division.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 215
PIC32CM MC00 Family
Divide and Square Root Accelerator (DIVAS)
21.6.7
Square Root Input
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
SQRNUM
0x18
0x0000
-
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
SQRNUM[31:24]
R/W
R/W
0
0
20
19
SQRNUM[23:16]
R/W
R/W
0
0
12
11
SQRNUM[15:8]
R/W
R/W
0
0
4
3
SQRNUM[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – SQRNUM[31:0] Square Root Input
Holds the 32-bit unsigned input for the square root operation. Writing the SQRNUM register will start the square root
function. Refer to 21.5.2.7 Unsigned Square Root.
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Datasheet
DS60001638D-page 216
PIC32CM MC00 Family
Watchdog Timer (WDT)
22.
Watchdog Timer (WDT)
22.1
Overview
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it possible to
recover from error situations such as runaway or deadlocked code. The WDT is configured to a predefined time-out
period, and is constantly running when enabled. If the WDT is not cleared within the time-out period, it will issue a
system reset. An early-warning interrupt is available to indicate an upcoming watchdog time-out condition.
The window mode makes it possible to define a time slot or window inside the total time-out period during which
the WDT must be cleared. If the WDT is cleared outside this window, either too early or too late, a system reset will
be issued. Compared to the normal mode, this can also catch situations where a code error causes the WDT to be
cleared too frequently.
When enabled, the WDT will run in Active mode and all sleep modes. It is asynchronous and runs from a CPUindependent clock source. The WDT will continue operation and issue a system reset or interrupt even if the main
clocks fail.
22.2
Features
•
•
•
•
•
•
22.3
Issues a system reset if the Watchdog Timer is not cleared before its time-out period
Early Warning interrupt generation
Asynchronous operation from dedicated oscillator
Two types of operation
– Normal mode
– Window mode
Selectable time-out periods
– From 8 cycles to 16,384 cycles in Normal mode
– From 16 cycles to 32,768 cycles in Window mode
Always-On capability
Block Diagram
Figure 22-1. WDT Block Diagram
0xA5
0
CLEAR
OSC32KCTRL
CLK_WDT_OSC
(1.024 kHz)
COUNT
PER/WINDOWS/EWOFFSET
Early Warning Interrupt
Reset
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Datasheet
DS60001638D-page 217
PIC32CM MC00 Family
Watchdog Timer (WDT)
22.4
Peripheral Dependencies
Peripheral
Base Address
WDT
0x40002000
AHB CLK
APB CLK
Generic CLK
PAC
Events
DMA
Enabled at reset
Enabled at reset
Index
Index
Prot at reset
User
Generator
Index
-
Y
-
8
N
-
-
-
IRQ
Sleep Walking
1
22.5
Functional Description
22.5.1
Principle of Operation
Y
The Watchdog Timer (WDT) is a system for monitoring correct program operation, making it possible to recover from
error situations, such as runaway code, by issuing a Reset. When enabled, the WDT is a constantly running timer
that is configured to a predefined time-out period. Before the end of the time-out period, the WDT should be set back,
or else, a system Reset is issued.
The WDT has two modes of operation, Normal mode and Window mode. Both modes offer the option of Early
Warning interrupt generation. The description for each of the basic modes is given below. The settings in the Control
A register (CTRLA) and the Interrupt Enable register (handled by INTENCLR/INTENSET) determine the mode of
operation:
Table 22-1. WDT Operating Modes
22.5.2
CTRLA.ENABLE
CTRLA.WEN
Interrupt Enable
Mode
0
x
x
Stopped
1
0
0
Normal mode
1
0
1
Normal mode with Early Warning interrupt
1
1
0
Window mode
1
1
1
Window mode with Early Warning interrupt
Basic Operation
22.5.2.1 Initialization
The following bits are enable-protected, meaning that they can only be written when the WDT is disabled
(CTRLA.ENABLE=0):
•
•
•
Control A register (CTRLA), except the Enable bit (CTRLA.ENABLE)
Configuration register (CONFIG)
Early Warning Interrupt Control register (EWCTRL)
Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but
not at the same time as CTRLA.ENABLE is written to '0'.
The WDT can be configured only while the WDT is disabled. The WDT is configured by defining the required
Time-Out Period bits in the Configuration register (CONFIG.PER). If Window mode operation is desired, the Window
Enable bit in the Control A register must be set (CTRLA.WEN=1) and the Window Period bits in the Configuration
register (CONFIG.WINDOW) must be defined.
Enable-protection is denoted by the "Enable-Protected" property in the register description.
22.5.2.2 Configurable Reset Values
After a Power-on Reset, some registers will be loaded with initial values from the 8.3 NVM User Row Mapping.
This includes the following bits and bit groups:
•
Enable bit in the Control A register, CTRLA.ENABLE
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PIC32CM MC00 Family
Watchdog Timer (WDT)
•
•
•
•
•
Always-On bit in the Control A register, CTRLA.ALWAYSON
Watchdog Timer Windows Mode Enable bit in the Control A register, CTRLA.WEN
Watchdog Timer Windows Mode Time-Out Period bits in the Configuration register, CONFIG.WINDOW
Time-Out Period bits in the Configuration register, CONFIG.PER
Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register, EWCTRL.EWOFFSET
22.5.2.3 Enabling, Disabling, and Resetting
The WDT is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The WDT is
disabled by writing a '0' to CTRLA.ENABLE.
The WDT can be disabled only if the Always-On bit in the Control A register (CTRLA.ALWAYSON) is '0'.
22.5.2.4 Normal Mode
In Normal mode operation, the length of a time-out period is configured in CONFIG.PER. The WDT is enabled by
writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). Once enabled, the WDT will issue a system
reset if a time-out occurs. This can be prevented by clearing the WDT at any time during the time-out period.
The WDT is cleared and a new WDT time-out period is started by writing 0xA5 to the Clear register (CLEAR). Writing
any other value than 0xA5 to CLEAR will issue an immediate system reset.
There are 12 possible WDT time-out (TOWDT) periods, selectable from 8ms to 16s.
By default, the early warning interrupt is disabled. If it is desired, the Early Warning Interrupt Enable bit in the Interrupt
Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is disabled again by writing a '1'
to the Early Warning Interrupt bit in the Interrupt Enable Clear register (INTENCLR.EW).
If the Early Warning Interrupt is enabled, an interrupt is generated prior to a WDT time-out condition. In Normal
mode, the Early Warning Offset bits in the Early Warning Interrupt Control register, EWCTRL.EWOFFSET, define the
time when the early warning interrupt occurs. The Normal mode operation is illustrated in the figure Normal-Mode
Operation.
Figure 22-2. Normal-Mode Operation
WDT Count
Timely WDT Clear
PER[3:0] = 1
WDT Timeout
System Reset
EWOFFSET[3:0] = 0
Early Warning Interrupt
t[ms]
5
10
15
20
25
30
35
TOWDT
22.5.2.5 Window Mode
In Window mode operation, the WDT uses two different time specifications: the WDT can only be cleared by writing
0xA5 to the CLEAR register after the closed window time-out period (TOWDTW), during the subsequent Normal
time-out period (TOWDT). If the WDT is cleared before the time window opens (before TOWDTW is over), the WDT will
issue a system reset.
Both parameters TOWDTW and TOWDT are periods in a range from 8ms to 16s, so the total duration of the WDT
time-out period is the sum of the two parameters.
The closed window period is defined by the Window Period bits in the Configuration register (CONFIG.WINDOW),
and the open window period is defined by the Period bits in the Configuration register (CONFIG.PER).
By default, the Early Warning interrupt is disabled. If it is desired, the Early Warning Interrupt Enable bit in the
Interrupt Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is disabled again by
writing a '1' to the Early Warning Interrupt bit in the Interrupt Enable Clear (INTENCLR.EW) register.
If the Early Warning interrupt is enabled in Window mode, the interrupt is generated at the start of the open window
period, that is after TOWDTW. The Window mode operation is illustrated in figure Window-Mode Operation.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 219
PIC32CM MC00 Family
Watchdog Timer (WDT)
Figure 22-3. Window-Mode Operation
WDT Count
Timely WDT Clear
PER[3:0] = 0
Open
WDT Timeout
Early WDT Clear
WINDOW[3:0] = 0
Closed
Early Warning Interrupt
System Reset
t[ms]
5
10
15
20
TOWDTW
22.5.3
25
30
35
TOWDT
Interrupts
The WDT has the following interrupt source:
•
Early Warning (EW): Indicates that the counter is approaching the time-out condition.
– This interrupt is an asynchronous wake-up source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs.
Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set
(INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR)
register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the WDT is reset. See
the 22.6.6 INTFLAG register description for details on how to clear interrupt flags. All interrupt requests from the
peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. The user
must read the INTFLAG register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated.
22.5.4
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following registers are synchronized when written:
•
•
•
•
Enable bit in Control A register (CTRLA.ENABLE)
Window Enable bit in Control A register (CTRLA.WEN)
Always-On bit in control Control A (CTRLA.ALWAYSON)
Watchdog Clear register (CLEAR)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.
22.5.5
Additional Features
22.5.5.1 Always-On Mode
The Always-On mode is enabled by setting the Always-On bit in the Control A register (CTRLA.ALWAYSON=1).
When the Always-On mode is enabled, the WDT runs continuously, regardless of the state of CTRLA.ENABLE. Once
written, the Always-On bit can only be cleared by a power-on reset. The Configuration (CONFIG) and Early Warning
Control (EWCTRL) registers are read-only registers while the CTRLA.ALWAYSON bit is set. Thus, the time period
configuration bits (CONFIG.PER, CONFIG.WINDOW, EWCTRL.EWOFFSET) of the WDT cannot be changed.
Enabling or disabling Window mode operation by writing the Window Enable bit (CTRLA.WEN) is allowed while in
Always-On mode, but note that CONFIG.PER cannot be changed.
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PIC32CM MC00 Family
Watchdog Timer (WDT)
The Interrupt Clear and Interrupt Set registers are accessible in the Always-On mode. The Early Warning interrupt
can still be enabled or disabled while in the Always-On mode, but note that EWCTRL.EWOFFSET cannot be
changed.
Table WDT Operating Modes With Always-On shows the operation of the WDT for CTRLA.ALWAYSON=1.
Table 22-2. WDT Operating Modes With Always-On
WEN
Interrupt Enable
Mode
0
0
Always-on and normal mode
0
1
Always-on and normal mode with Early Warning interrupt
1
0
Always-on and window mode
1
1
Always-on and window mode with Early Warning interrupt
22.5.5.2 Early Warning
The Early Warning interrupt notifies that the WDT is approaching its time-out condition. The Early Warning interrupt
behaves differently in Normal mode and in Window mode.
In Normal mode, the Early Warning interrupt generation is defined by the Early Warning Offset in the Early Warning
Control register (EWCTRL.EWOFFSET). The Early Warning Offset bits define the number of CLK_WDT_OSC clocks
before the interrupt is generated, relative to the start of the watchdog time-out period.
The user must take caution when programming the Early Warning Offset bits. If these bits define an Early Warning
interrupt generation time greater than the watchdog time-out period, the watchdog time-out system reset is generated
prior to the Early Warning interrupt. Consequently, the Early Warning interrupt will never be generated.
In window mode, the Early Warning interrupt is generated at the start of the open window period. In a typical
application where the system is in sleep mode, the Early Warning interrupt can be used to wake up and clear the
Watchdog Timer, after which the system can perform other tasks or return to sleep mode.
Example:
If the WDT is operating in Normal mode with CONFIG.PER = 0x2 and EWCTRL.EWOFFSET =
0x1, the Early Warning interrupt is generated 16 CLK_WDT_OSC clock cycles after the start of the
time-out period. The time-out system reset is generated 32 CLK_WDT_OSC clock cycles after the
start of the watchdog time-out period.
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Datasheet
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PIC32CM MC00 Family
Watchdog Timer (WDT)
22.6
Register Summary
Offset
Name
Bit Pos.
7
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
CTRLA
CONFIG
EWCTRL
Reserved
INTENCLR
INTENSET
INTFLAG
Reserved
7:0
7:0
7:0
ALWAYSON
0x08
SYNCBUSY
0x0C
CLEAR
6
5
4
3
2
1
WEN
ENABLE
PER[3:0]
EWOFFSET[3:0]
WINDOW[3:0]
7:0
7:0
7:0
7:0
15:8
23:16
31:24
7:0
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0
EW
EW
EW
CLEAR
ALWAYSON
WEN
ENABLE
CLEAR[7:0]
Datasheet
DS60001638D-page 222
PIC32CM MC00 Family
Watchdog Timer (WDT)
22.6.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
ALWAYSON
R/W
x
CTRLA
0x00
X determined from NVM User Row
PAC Write-Protection, Write-Synchronized Bits
6
5
4
3
2
WEN
R/W
x
1
ENABLE
R/W
x
0
Bit 7 – ALWAYSON Always-On
This bit allows the WDT to run continuously. After being set, this bit cannot be written to '0', and the WDT will remain
enabled until a power-on Reset is received. When this bit is '1', the Control A register (CTRLA), the Configuration
register (CONFIG) and the Early Warning Control register (EWCTRL) will be read-only, and any writes to these
registers are not allowed.
Writing a '0' to this bit has no effect.
This bit is loaded from NVM user row at start-up.
Note: This bit is not synchronized.
Value
0
1
Description
The WDT is enabled and disabled through the ENABLE bit.
The WDT is enabled and can only be disabled by a Power-on Reset (POR).
Bit 2 – WEN Watchdog Timer Window Mode Enable
This bit enables Window mode. It can only be written if the peripheral is disabled unless CTRLA.ALWAYSON=1.
This bit is loaded from NVM User Row at startup.
Note: This bit is not synchronized.
Value
0
1
Description
Window mode is disabled (normal operation).
Window mode is enabled.
Bit 1 – ENABLE Enable
This bit enables or disables the WDT. It can only be written if CTRLA.ALWAYSON=0.
This bit is not Enable-Protected.
This bit is loaded from NVM User Row at startup.
Note: This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
Value
0
1
Description
The WDT is disabled.
The WDT is enabled.
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PIC32CM MC00 Family
Watchdog Timer (WDT)
22.6.2
Configuration
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
R/W
x
CONFIG
0x01
X determined from NVM User Row
PAC Write-Protection
6
5
WINDOW[3:0]
R/W
R/W
x
x
4
3
2
1
0
R/W
x
R/W
x
PER[3:0]
R/W
x
R/W
x
R/W
x
Bits 7:4 – WINDOW[3:0] Window Mode Time-Out Period
In Window mode, these bits determine the watchdog closed window period as a number of cycles of the 1.024kHz
CLK_WDT_OSC clock.
These bits are loaded from NVM User Row at start-up.
Value
Name
Description
0x0
CYC8
8 clock cycles
0x1
CYC16
16 clock cycles
0x2
CYC32
32 clock cycles
0x3
CYC64
64 clock cycles
0x4
CYC128
128 clock cycles
0x5
CYC256
256 clock cycles
0x6
CYC512
512 clock cycles
0x7
CYC1024
1024 clock cycles
0x8
CYC2048
2048 clock cycles
0x9
CYC4096
4096 clock cycles
0xA
CYC8192
8192 clock cycles
0xB
CYC16384
16384 clock cycles
0xC Reserved
0xF
Bits 3:0 – PER[3:0] Time-Out Period
These bits determine the watchdog time-out period as a number of 1.024kHz CLK_WDTOSC clock cycles. In
Window mode operation, these bits define the open window period.
These bits are loaded from NVM User Row at startup.
Value
Name
Description
0x0
CYC8
8 clock cycles
0x1
CYC16
16 clock cycles
0x2
CYC32
32 clock cycles
0x3
CYC64
64 clock cycles
0x4
CYC128
128 clock cycles
0x5
CYC256
256 clock cycles
0x6
CYC512
512 clock cycles
0x7
CYC1024
1024 clock cycles
0x8
CYC2048
2048 clock cycles
0x9
CYC4096
4096 clock cycles
0xA
CYC8192
8192 clock cycles
0xB
CYC16384
16384 clock cycles
0xC Reserved
0xF
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Datasheet
DS60001638D-page 224
PIC32CM MC00 Family
Watchdog Timer (WDT)
22.6.3
Early Warning Control
Name:
Offset:
Reset:
Property:
Bit
7
EWCTRL
0x02
X determined from NVM User Row
PAC Write-Protection
6
Access
Reset
5
4
3
R/W
x
2
1
EWOFFSET[3:0]
R/W
R/W
x
x
0
R/W
x
Bits 3:0 – EWOFFSET[3:0] Early Warning Interrupt Time Offset
These bits determine the number of GCLK_WDT clock cycles between the start of the watchdog time-out period and
the generation of the Early Warning interrupt. These bits are loaded from NVM User Row at start-up.
Value
Name
Description
0x0
CYC8
8 clock cycles
0x1
CYC16
16 clock cycles
0x2
CYC32
32 clock cycles
0x3
CYC64
64 clock cycles
0x4
CYC128
128 clock cycles
0x5
CYC256
256 clock cycles
0x6
CYC512
512 clock cycles
0x7
CYC1024
1024 clock cycles
0x8
CYC2048
2048 clock cycles
0x9
CYC4096
4096 clock cycles
0xA
CYC8192
8192 clock cycles
0xB Reserved
0xF
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PIC32CM MC00 Family
Watchdog Timer (WDT)
22.6.4
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x04
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
7
6
5
4
3
Access
Reset
2
1
0
EW
R/W
0
Bit 0 – EW Early Warning Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Early Warning Interrupt Enable bit, which disables the Early Warning interrupt.
Value
Description
0
The Early Warning interrupt is disabled.
1
The Early Warning interrupt is enabled.
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PIC32CM MC00 Family
Watchdog Timer (WDT)
22.6.5
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x05
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
7
6
5
4
3
2
1
0
EW
R/W
0
Access
Reset
Bit 0 – EW Early Warning Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit sets the Early Warning Interrupt Enable bit, which enables the Early Warning interrupt.
Value
Description
0
The Early Warning interrupt is disabled.
1
The Early Warning interrupt is enabled.
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Datasheet
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PIC32CM MC00 Family
Watchdog Timer (WDT)
22.6.6
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAG
0x06
0x00
-
6
5
4
3
Access
Reset
2
1
0
EW
R/W
0
Bit 0 – EW Early Warning
This flag is cleared by writing a '1' to it.
This flag is set when an Early Warning interrupt occurs, as defined by the EWOFFSET bit group in EWCTRL.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Early Warning interrupt flag.
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PIC32CM MC00 Family
Watchdog Timer (WDT)
22.6.7
Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x08
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
CLEAR
R
0
3
ALWAYSON
R
0
2
WEN
R
0
1
ENABLE
R
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 4 – CLEAR CLEAR Synchronization Busy
Value
Description
0
Write synchronization of the CLEAR register is complete.
1
Write synchronization of the CLEAR register is ongoing.
Bit 3 – ALWAYSON ALWAYSON Synchronization Busy
Value
Description
0
Write synchronization of the CTRLA.ALWAYSON bit is complete.
1
Write synchronization of the CTRLA.ALWAYSON bit is ongoing.
Bit 2 – WEN Window Enable Synchronization Busy
Value
Description
0
Write synchronization of the CTRLA.WEN bit is complete.
1
Write synchronization of the CTRLA.WEN bit is ongoing.
Bit 1 – ENABLE Enable Synchronization Busy
Value
Description
0
Write synchronization of the CTRLA.ENABLE bit is complete.
1
Write synchronization of the CTRLA.ENABLE bit is ongoing.
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
Watchdog Timer (WDT)
22.6.8
Clear
Name:
Offset:
Reset:
Property:
CLEAR
0x0C
0x00
Write-Synchronized
Note: CLEAR is a write-synchronized register: SYNCBUSY.CLEAR must be checked to ensure the CLEAR
synchronization is complete.
Bit
7
6
5
4
3
2
1
0
W
0
W
0
W
0
W
0
CLEAR[7:0]
Access
Reset
W
0
W
0
W
0
W
0
Bits 7:0 – CLEAR[7:0] Watchdog Clear
In Normal mode, writing 0xA5 to this register during the watchdog time-out period will clear the Watchdog Timer and
the watchdog time-out period is restarted.
In Window mode, any writing attempt to this register before the time-out period started (i.e., during TOWDTW) will
issue an immediate system Reset. Writing 0xA5 during the time-out period TOWDT will clear the Watchdog Timer and
the complete time-out sequence (first TOWDTW then TOWDT) is restarted.
In both modes, writing any other value than 0xA5 will issue an immediate system Reset.
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Datasheet
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PIC32CM MC00 Family
Real-Time Counter (RTC)
23.
Real-Time Counter (RTC)
23.1
Overview
The Real-Time Counter (RTC) is a 32-bit counter with a 10-bit programmable prescaler that typically runs
continuously to keep track of time. The RTC can wake up the device from sleep modes using the alarm/compare
wake up, periodic wake up, or overflow wake up mechanisms.
The RTC can generate periodic peripheral events from outputs of the prescaler, as well as alarm/compare interrupts
and peripheral events, which can trigger at any counter value. Additionally, the timer can trigger an overflow interrupt
and peripheral event, and can be reset on the occurrence of an alarm/compare match. This allows periodic interrupts
and peripheral events at very long and accurate intervals.
The 10-bit programmable prescaler can scale down the clock source. By this, a wide range of resolutions and
time-out periods can be configured. With a 32.768kHz clock source, the minimum counter tick interval is 30.5µs, and
time-out periods can range up to 36 hours. For a counter tick interval of 1s, the maximum time-out period is more
than 136 years.
23.2
Features
•
•
•
•
•
•
•
•
23.3
32-bit counter with 10-bit prescaler
Multiple clock sources
32-bit or 16-bit counter mode
One 32-bit or two 16-bit compare values
Clock/Calendar mode
– Time in seconds, minutes, and hours (12/24)
– Date in day of month, month, and year
– Leap year correction
Digital prescaler correction/tuning for increased accuracy
Overflow, alarm/compare match and prescaler interrupts and events
– Optional clear on alarm/compare match
Two GP Registers
Block Diagram
Figure 23-1. RTC Block Diagram (Mode 0 — 32-Bit Counter)
0x00000000
MATCHCLR
OSC32KCTRL
CLK_RTC_OSC
PRESCALER
CLK_RTC_CNT
OVF
COUNT
=
Periodic Events
CMPn
COMPn
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PIC32CM MC00 Family
Real-Time Counter (RTC)
Figure 23-2. RTC Block Diagram (Mode 1 — 16-Bit Counter)
0x0000
OSC32KCTRL
CLK_RTC_OSC
PRESCALER
CLK_RTC_CNT
COUNT
PER
Periodic Events
=
OVF
=
CMPn
COMPn
Figure 23-3. RTC Block Diagram (Mode 2 — Clock/Calendar)
0x00000000
MATCHCLR
OSC32KCTRL
CLK_RTC_OSC
CLK_RTC_CNT
PRESCALER
OVF
CLOCK
=
MASKn
Periodic Events
ALARMn
ALARMn
23.4
Peripheral Dependencies
AHB CLK
APB CLK
Generic CLK
Enabled at reset
Enabled at reset
Index
PAC
Events
DMA
Peripheral Base Address IRQ
Sleep Walking
Index Prot at reset User
Generator
Index
3: CMP0/ALARM0
4: CMP1
RTC
0x40002400
2
-
Y
-
9
N
-
-
Y
5: OVF
6-13: PER0-7
23.5
23.5.1
Functional Description
Principle of Operation
The RTC keeps track of time in the system and enables periodic events, as well as interrupts and events at a
specified time. The RTC consists of a 10-bit prescaler that feeds a 32-bit counter. The actual format of the 32-bit
counter depends on the RTC operating mode.
The RTC can function in one of these modes:
• Mode 0 - COUNT32: RTC serves as 32-bit counter
• Mode 1 - COUNT16: RTC serves as 16-bit counter
• Mode 2 - CLOCK: RTC serves as clock/calendar with alarm functionality
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PIC32CM MC00 Family
Real-Time Counter (RTC)
23.5.2
Basic Operation
23.5.2.1 Initialization
The following bits are enable-protected, meaning that they can only be written when the RTC is disabled
(CTRLA.ENABLE=0):
•
•
•
•
Operating Mode bits in the Control A register (CTRLA.MODE)
Prescaler bits in the Control A register (CTRLA.PRESCALER)
Clear on Match bit in the Control A register (CTRLA.MATCHCLR)
Clock Representation bit in the Control A register (CTRLA.CLKREP)
The following registers are enable-protected:
•
Event Control register (EVCTRL)
Enable-protected bits and registers can be changed only when the RTC is disabled (CTRLA.ENABLE=0). If the
RTC is enabled (CTRLA.ENABLE=1), these operations are necessary: first write CTRLA.ENABLE=0 and check
whether the write synchronization has finished, then change the desired bit field value. Enable-protected bits in
CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but not at the same time as
CTRLA.ENABLE is written to '0'.
Enable-protection is denoted by the "Enable-Protected" property in the register description.
The RTC prescaler divides the source clock for the RTC counter.
Note: In Clock/Calendar mode, the prescaler must be configured to provide a 1Hz clock to the counter for correct
operation.
The frequency of the RTC clock (CLK_RTC_CNT) is given by the following formula:
fCLK_RTC_CNT =
fCLK_RTC_OSC
2PRESCALER
The frequency of the oscillator clock, CLK_RTC_OSC, is given by fCLK_RTC_OSC, and fCLK_RTC_CNT is the frequency of
the internal prescaled RTC clock, CLK_RTC_CNT.
23.5.2.2 Enabling, Disabling, and Resetting
The RTC is enabled by setting the Enable bit in the Control A register (CTRLA.ENABLE=1). The RTC is disabled by
writing CTRLA.ENABLE=0.
The RTC is reset by setting the Software Reset bit in the Control A register (CTRLA.SWRST=1). All registers in the
RTC, except DEBUG, will be reset to their initial state, and the RTC will be disabled. The RTC must be disabled
before resetting it.
23.5.2.3 32-Bit Counter (Mode 0)
When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x0, the counter operates
in 32-bit Counter mode. The block diagram of this mode is shown in Figure 23-1. When the RTC is enabled, the
counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The counter will increment until it reaches the top
value of 0xFFFFFFFF, and then wrap to 0x00000000. This sets the Overflow Interrupt flag in the Interrupt Flag Status
and Clear register (INTFLAG.OVF).
The RTC counter value can be read from or written to the Counter Value register (COUNT) in 32-bit format. The
COUNT register requires synchronization when reading. This is achieved by setting the CTRLA.COUNTSYNC bit
and waiting for the SYNCBUSY.COUNTSYNC to complete. Disabling the synchronization will prevent reading valid
values from the COUNT register.
The counter value is continuously compared with the 32-bit Compare register (COMP0). When a compare match
occurs, the Compare 0 Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMP0) is set on the
next 0-to-1 transition of CLK_RTC_CNT.
If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is '1', the counter is cleared on the next
counter cycle when a compare match with COMP0 occurs. This allows the RTC to generate periodic interrupts or
events with longer periods than the prescaler events. Note that when CTRLA.MATCHCLR is '1', INTFLAG.CMP0 and
INTFLAG.OVF will both be set simultaneously on a compare match with COMP0.
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PIC32CM MC00 Family
Real-Time Counter (RTC)
23.5.2.4 16-Bit Counter (Mode 1)
When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x1, the counter operates
in 16-bit Counter mode as shown in Figure 23-2. When the RTC is enabled, the counter will increment on every
0-to-1 transition of CLK_RTC_CNT. In 16-bit Counter mode, the 16-bit Period register (PER) holds the maximum
value of the counter. The counter will increment until it reaches the PER value, and then wrap to 0x0000. This sets
the Overflow Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF).
The RTC counter value can be read from or written to the Counter Value register (COUNT) in 16-bit format. The
COUNT register requires synchronization when reading. This is achieved by setting the CTRLA.COUNTSYNC bit
and waiting for the SYNCBUSY.COUNTSYNC to complete. Disabling the synchronization will prevent reading valid
values from the COUNT register.
The counter value is continuously compared with the 16-bit Compare registers (COMPn, n=0..1). When a compare
match occurs, the Compare n Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn, n=0..1) is
set on the next 0-to-1 transition of CLK_RTC_CNT.
23.5.2.5 Clock/Calendar (Mode 2)
When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x2, the counter operates
in Clock/Calendar mode, as shown in Figure 23-3. When the RTC is enabled, the counter will increment on every
0-to-1 transition of CLK_RTC_CNT. The selected clock source and RTC prescaler must be configured to provide a
1Hz clock to the counter for correct operation in this mode.
The time and date can be read from or written to the Clock Value register (CLOCK) in a 32-bit time/date format. The
CLOCK register requires synchronization when reading. This is achieved by setting the CTRLA.COUNTSYNC bit and
waiting for the SYNCBUSY.COUNTSYNC to complete. Disabling the synchronization will prevent reading valid values
from the CLOCK register. Time is represented as:
•
•
•
Seconds
Minutes
Hours
Hours can be represented in either 12- or 24-hour format, selected by the Clock Representation bit in the Control A
register (CTRLA.CLKREP). This bit can be changed only while the RTC is disabled.
The date is represented in the following form:
•
•
•
Day as the numeric day of the month (starting at 1)
Month as the numeric month of the year (1 = January, 2 = February and so on)
Year as a value from 0x00 to 0x3F. This value must be added to a user-defined reference year. The reference
year must be a leap year (2016, 2020 and so on). For example, the year value 0x2D, added to a reference year
2016, represents the year 2061.
The RTC will increment until it reaches the top value of 23:59:59 December 31 of year value 0x3F, and then wrap to
00:00:00 January 1 of year value 0x00. This will set the Overflow Interrupt flag in the Interrupt Flag Status and Clear
registers (INTFLAG.OVF).
The clock value is continuously compared with the 32-bit Alarm register (ALARM0). When an alarm match occurs,
the Alarm 0 Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.ALARM0) is set on the next
0-to-1 transition of CLK_RTC_CNT. E.g. For a 1Hz clock counter, it means the Alarm 0 Interrupt flag is set with a
delay of 1s after the occurrence of alarm match.
A valid alarm match depends on the setting of the Alarm Mask Selection bits in the Alarm 0 Mask register
(MASK0.SEL). These bits determine which time/date fields of the clock and alarm values are valid for comparison
and which are ignored.
If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is set, the counter is cleared on the next
counter cycle when an alarm match with ALARM0 occurs. This allows the RTC to generate periodic interrupts or
events with longer periods than it would be possible with the prescaler events only (see 23.5.8.1 Periodic Intervals).
Note: When CTRLA.MATCHCLR is 1, INTFLAG.ALARM0 and INTFLAG.OVF will both be set simultaneously on an
alarm match with ALARM0.
© 2021 Microchip Technology Inc.
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DS60001638D-page 234
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.5.3
Clocks
The RTC bus clock (CLK_RTC_APB) can be enabled and disabled in the Main Clock module MCLK, and the default
state of CLK_RTC_APB can be found in the Peripheral Clock Masking section.
A 32.768 kHz or 1.024 kHz oscillator clock (CLK_RTC_OSC) is required to clock the RTC. This clock must be
configured and enabled in the 32.768 kHz oscillator controller (OSC32KCTRL) before using the RTC.
This oscillator clock is asynchronous to the bus clock (CLK_RTC_APB). Due to this asynchronicity, writing to certain
registers will require synchronization between the clock domains. Refer to Synchronization for further details.
23.5.4
Interrupts
The RTC has the following interrupt sources:
•
•
•
•
Overflow (OVF): Indicates that the counter has reached its top value and wrapped to zero.
Compare (CMP0-1): Indicates a match between the counter value and the compare register.
Alarm (ALARM0): Indicates a match between the clock value and the alarm register.
Period n (PER0-7): The corresponding bit in the prescaler has toggled. Refer to 23.5.8.1 Periodic Intervals for
details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by setting
the corresponding bit in the Interrupt Enable Set register (INTENSET=1), and disabled by setting the corresponding
bit in the Interrupt Enable Clear register (INTENCLR=1).
An interrupt request is generated when the interrupt flag is raised and the corresponding interrupt is enabled. The
interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled or the RTC is reset.
See the description of the INTFLAG registers for details on how to clear interrupt flags.
All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt
request to the NVIC. Refer to the Nested Vector Interrupt Controller for details. The user must read the INTFLAG
register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to the Nested Vector
Interrupt Controller for details.
23.5.5
Events
The RTC can generate the following output events:
•
•
•
•
•
Overflow (OVF): Generated when the counter has reached its top value and wrapped to zero.
Compare (CMP0-1): Indicates a match between the counter value and the compare register.
Alarm (ALARM0): Indicates a match between the clock value and the alarm register.
Period n (PER0-7): The corresponding bit in the prescaler has toggled. Refer to 23.5.8.1 Periodic Intervals for
details.
Periodic Daily (PERD): Generated when the COUNT/CLOCK has incremented at a fixed period of time.
Setting the Event Output bit in the Event Control Register (EVCTRL.xxxEO=1) enables the corresponding output
event. Writing a zero to this bit disables the corresponding output event. Refer to the EVSYS - Event System for
details on configuring the event system.
23.5.6
Sleep Mode Operation
The RTC will continue to operate in any sleep mode where the source clock is active. The RTC interrupts can be
used to wake up the device from a sleep mode. RTC events can trigger other operations in the system without exiting
the sleep mode.
An interrupt request will be generated after the wake-up if the Interrupt Controller is configured accordingly.
Otherwise the CPU will wake up directly, without triggering any interrupt. In this case, the CPU will continue executing
right from the first instruction that followed the entry into sleep.
The periodic events can also wake up the CPU through the interrupt function of the Event System. In this case, the
event must be enabled and connected to an event channel with its interrupt enabled. See Event System for more
information.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 235
PIC32CM MC00 Family
Real-Time Counter (RTC)
When the device is in STANDBY sleep mode the DMA is not able to write the COUNT register. To write the COUNT
register with the DMA the device must be in Active mode or IDLE sleep mode.
23.5.7
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
•
•
•
•
Software Reset bit in Control A register, CTRLA.SWRST
Enable bit in Control A register, CTRLA.ENABLE
Count Read Synchronization bit in Control A register (CTRLA.COUNTSYNC)
Clock Read Synchronization bit in Control A register (CTRLA.CLOCKSYNC)
The following registers are synchronized when written:
•
•
•
•
•
•
•
•
Counter Value register, COUNT
Clock Value register, CLOCK
Counter Period register, PER
Compare n Value registers, COMPn
Alarm n Value registers, ALARM0
Frequency Correction register, FREQCORR
Alarm n Mask register, MASK0
The General Purpose n registers (GP0, GP1)
The following registers are synchronized when read:
•
•
The Counter Value register, COUNT, if the Counter Read Sync Enable bit in CTRLA (CTRLA.COUNTSYNC) is
'1'
The Clock Value register, CLOCK, if the Clock Read Sync Enable bit in CTRLA (CTRLA.CLOCKSYNC) is '1'
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.
23.5.8
Additional Features
23.5.8.1 Periodic Intervals
The RTC prescaler can generate interrupts and events at periodic intervals, allowing flexible system tick creation.
Any of the upper eight bits of the prescaler (bits 2 to 9) can be the source of an interrupt/event. When one of the eight
Periodic Event Output bits in the Event Control register (EVCTRL.PEREO[n=0..7]) is '1', an event is generated on the
0-to-1 transition of the related bit in the prescaler, resulting in a periodic event frequency of:
fPERIODIC(n) =
fCLK_RTC_OSC
2n+3
fCLK_RTC_OSC is the frequency of the internal prescaler clock CLK_RTC_OSC, and n is the position of the
EVCTRL.PEREOx bit. For example, PER0 will generate an event every eight CLK_RTC_OSC cycles, PER1 every 16
cycles, etc. This is shown in the figure below.
Periodic events are independent of the prescaler setting used by the RTC counter, except if CTRLA.PRESCALER is
zero. Then, no periodic events will be generated.
Figure 23-4. Example Periodic Events
CLK_RTC_OSC
PER0
PER1
PER2
PER3
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PIC32CM MC00 Family
Real-Time Counter (RTC)
23.5.8.2 Frequency Correction
The RTC Frequency Correction module employs periodic counter corrections to compensate for a too-slow or
too-fast oscillator. Frequency correction requires that CTRLA.PRESCALER is greater than 1.
The digital correction circuit adds or subtracts cycles from the RTC prescaler to adjust the frequency in approximately
1ppm steps. Digital correction is achieved by adding or skipping a single count in the prescaler once every 8192
CLK_RTC_OSC cycles. The Value bit group in the Frequency Correction register (FREQCORR.VALUE) determines
the number of times the adjustment is applied over 128 of these periods. The resulting correction is as follows:
Correction in ppm =
FREQCORR.VALUE
⋅ 106ppm
8192 ⋅ 128
This results in a resolution of 0.95367 ppm.
The Sign bit in the Frequency Correction register (FREQCORR.SIGN) determines the direction of the correction. A
positive value will add counts and increase the period (reducing the frequency), and a negative value will reduce the
counts per period (speeding up the frequency).
Digital correction also affects the generation of the periodic events from the prescaler. When the correction is applied
at the end of the correction cycle period, the interval between the previous periodic event and the next occurrence
may also be shortened or lengthened depending on the correction value.
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
Real-Time Counter (RTC)
23.6
Register Summary - Mode 0 - 32-Bit Counter
Offset
Name
Bit Pos.
7
0x00
CTRLA
7:0
15:8
MATCHCLR
COUNTSYNC
0x02
...
0x03
Reserved
7:0
15:8
23:16
31:24
7:0
15:8
7:0
15:8
7:0
15:8
7:0
PEREO7
OVFEO
PEREO6
PEREO5
PEREO4
PEREO3
PEREO2
PEREO1
PEREO0
CMPEO0
PER7
OVF
PER7
OVF
PER7
OVF
PER6
PER5
PER4
PER3
PER2
PER1
PER6
PER5
PER4
PER3
PER2
PER1
PER6
PER5
PER4
PER3
PER2
PER1
PER0
CMP0
PER0
CMP0
PER0
CMP0
DBGRUN
COUNT
FREQCORR
ENABLE
0x04
EVCTRL
0x08
INTENCLR
0x0A
INTENSET
0x0C
INTFLAG
0x0E
0x0F
DBGCTRL
Reserved
0x10
SYNCBUSY
0x14
0x15
...
0x17
FREQCORR
7:0
15:8
23:16
31:24
7:0
6
5
4
3
2
MODE[1:0]
COMP0
1
ENABLE
PRESCALER[3:0]
0
SWRST
SWRST
COUNTSYNC
SIGN
VALUE[6:0]
Reserved
0x18
COUNT
0x1C
...
0x1F
Reserved
0x20
COMP
0x24
...
0x3F
Reserved
0x40
GP0
0x44
GP1
7:0
15:8
23:16
31:24
COUNT[7:0]
COUNT[15:8]
COUNT[23:16]
COUNT[31:24]
7:0
15:8
23:16
31:24
COMP[7:0]
COMP[15:8]
COMP[23:16]
COMP[31:24]
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
GP[7:0]
GP[15:8]
GP[23:16]
GP[31:24]
GP[7:0]
GP[15:8]
GP[23:16]
GP[31:24]
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 238
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.6.1
Control A in COUNT32 mode (CTRLA.MODE=0)
Name:
Offset:
Reset:
Property:
CTRLA
0x00
0x0000
PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
15
COUNTSYNC
Access
R/W
Reset
0
Bit
Access
Reset
7
MATCHCLR
R/W
0
14
13
12
11
10
9
PRESCALER[3:0]
R/W
R/W
0
0
R/W
0
6
5
4
3
2
MODE[1:0]
R/W
0
R/W
0
1
ENABLE
R/W
0
8
R/W
0
0
SWRST
R/W
0
Bit 15 – COUNTSYNC COUNT Read Synchronization Enable
The COUNT register requires synchronization when reading. Disabling the synchronization will prevent reading valid
values from the COUNT register.
This bit is not enable-protected.
Value
Description
0
COUNT read synchronization is disabled
1
COUNT read synchronization is enabled
Bits 11:8 – PRESCALER[3:0] Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock
(CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not
synchronized.
Value
Name
Description
0x0
OFF
CLK_RTC_CNT = GCLK_RTC/1
0x1
DIV1
CLK_RTC_CNT = GCLK_RTC/1
0x2
DIV2
CLK_RTC_CNT = GCLK_RTC/2
0x3
DIV4
CLK_RTC_CNT = GCLK_RTC/4
0x4
DIV8
CLK_RTC_CNT = GCLK_RTC/8
0x5
DIV16
CLK_RTC_CNT = GCLK_RTC/16
0x6
DIV32
CLK_RTC_CNT = GCLK_RTC/32
0x7
DIV64
CLK_RTC_CNT = GCLK_RTC/64
0x8
DIV128
CLK_RTC_CNT = GCLK_RTC/128
0x9
DIV256
CLK_RTC_CNT = GCLK_RTC/256
0xA
DIV512
CLK_RTC_CNT = GCLK_RTC/512
0xB
DIV1024
CLK_RTC_CNT = GCLK_RTC/1024
0xC-0xF Reserved
Bit 7 – MATCHCLR Clear on Match
This bit defines if the counter is cleared or not on a match.
This bit is not synchronized.
Value
Description
0
The counter is not cleared on a Compare/Alarm 0 match
1
The counter is cleared on a Compare/Alarm 0 match
Bits 3:2 – MODE[1:0] Operating Mode
This bit group defines the operating mode of the RTC.
This bit is not synchronized.
Value
Name
Description
0x0
COUNT32
Mode 0: 32-bit counter
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PIC32CM MC00 Family
Real-Time Counter (RTC)
Value
0x1
0x2
0x3
Name
COUNT16
CLOCK
-
Description
Mode 1: 16-bit counter
Mode 2: Clock/calendar
Reserved
Bit 1 – ENABLE Enable
Due to synchronization there is a delay between writing CTRLA.ENABLE and until the peripheral is enabled/disabled.
The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy
register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
Value
Description
0
The peripheral is disabled
1
The peripheral is enabled
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC will be
disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Due to synchronization there is a delay between writing CTRLA.SWRST and until the reset is complete.
CTRLA.SWRST will be cleared when the reset is complete.
Value
Description
0
There is not reset operation ongoing
1
The reset operation is ongoing
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PIC32CM MC00 Family
Real-Time Counter (RTC)
23.6.2
Event Control in COUNT32 mode (CTRLA.MODE=0)
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x04
0x00000000
PAC Write-Protection, Enable-Protected
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OVFEO
R/W
0
14
13
12
11
10
9
8
CMPEO0
R/W
0
7
PEREO7
R/W
0
6
PEREO6
R/W
0
5
PEREO5
R/W
0
4
PEREO4
R/W
0
3
PEREO3
R/W
0
2
PEREO2
R/W
0
1
PEREO1
R/W
0
0
PEREO0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 15 – OVFEO Overflow Event Output Enable
Value
Description
0
Overflow event is disabled and will not be generated.
1
Overflow event is enabled and will be generated for every overflow.
Bit 8 – CMPEO0 Compare 0 Event Output Enable
Value
Description
0
Compare 0 event is disabled and will not be generated.
1
Compare 0 event is enabled and will be generated for every compare match.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PEREOx Periodic Interval n Event Output Enable [x = 7..0]
Value
Description
0
Periodic Interval x event is disabled and will not be generated.
1
Periodic Interval x event is enabled and will be generated.
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Datasheet
DS60001638D-page 241
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.6.3
Interrupt Enable Clear in COUNT32 mode (CTRLA.MODE=0)
Name:
Offset:
Reset:
Property:
INTENCLR
0x08
0x0000
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
Access
Reset
Bit
Access
Reset
15
OVF
R/W
0
14
13
12
11
10
9
8
CMP0
R/W
0
7
PER7
R/W
0
6
PER6
R/W
0
5
PER5
R/W
0
4
PER4
R/W
0
3
PER3
R/W
0
2
PER2
R/W
0
1
PER1
R/W
0
0
PER0
R/W
0
Bit 15 – OVF Overflow Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
Bit 8 – CMP0 Compare 0 Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit will clear the Compare 0 Interrupt Enable bit, which disables the Compare 0 interrupt.
Value
Description
0
The Compare 0 interrupt is disabled.
1
The Compare 0 interrupt is enabled.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERx Periodic Interval n Interrupt Enable [x = 7..0]
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit will clear the Periodic Interval x Interrupt Enable bit, which disables the Periodic Interval n
interrupt.
Value
Description
0
Periodic Interval x interrupt is disabled.
1
Periodic Interval x interrupt is enabled.
© 2021 Microchip Technology Inc.
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PIC32CM MC00 Family
Real-Time Counter (RTC)
23.6.4
Interrupt Enable Set in COUNT32 mode (CTRLA.MODE=0)
Name:
Offset:
Reset:
Property:
INTENSET
0x0A
0x0000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
Access
Reset
Bit
Access
Reset
15
OVF
R/W
0
14
13
12
11
10
9
8
CMP0
R/W
0
7
PER7
R/W
0
6
PER6
R/W
0
5
PER5
R/W
0
4
PER4
R/W
0
3
PER3
R/W
0
2
PER2
R/W
0
1
PER1
R/W
0
0
PER0
R/W
0
Bit 15 – OVF Overflow Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
Bit 8 – CMP0 Compare 0 Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit will set the Compare 0 Interrupt Enable bit, which enables the Compare 0 interrupt.
Value
Description
0
The Compare 0 interrupt is disabled.
1
The Compare 0 interrupt is enabled.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERx Periodic Interval n Interrupt Enable [x = 7..0]
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval x
interrupt.
Value
Description
0
Periodic Interval x interrupt is disabled.
1
Periodic Interval x interrupt is enabled.
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
Real-Time Counter (RTC)
23.6.5
Interrupt Flag Status and Clear in COUNT32 mode (CTRLA.MODE=0)
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
INTFLAG
0x0C
0x0000
-
15
OVF
R/W
0
14
13
12
11
10
9
8
CMP0
R/W
0
7
PER7
R/W
0
6
PER6
R/W
0
5
PER5
R/W
0
4
PER4
R/W
0
3
PER3
R/W
0
2
PER2
R/W
0
1
PER1
R/W
0
0
PER0
R/W
0
Bit 15 – OVF Overflow
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be
generated if INTENCLR/SET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
Bit 8 – CMP0 Compare 0
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request
will be generated if INTENCLR/SET.COMP0 is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Compare 0 interrupt flag.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERx Periodic Interval x [x = 7..0]
This flag is cleared by writing a '1' to the flag.
This flag is set on the 0-to-1 transition of prescaler bit [x+2], and an interrupt request will be generated if INTENCLR/
SET.PERx is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Periodic Interval x interrupt flag.
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
Real-Time Counter (RTC)
23.6.6
Debug Control
Name:
Offset:
Reset:
Property:
Bit
DBGCTRL
0x0E
0x00
PAC Write-Protection
7
6
5
4
3
2
1
0
DBGRUN
R/W
0
Access
Reset
Bit 0 – DBGRUN Debug Run
This bit is not reset by a software reset.
This bit controls the functionality when the CPU is halted by an external debugger.
Value
Description
0
The RTC is halted when the CPU is halted by an external debugger.
1
The RTC continues normal operation when the CPU is halted by an external debugger.
© 2021 Microchip Technology Inc.
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PIC32CM MC00 Family
Real-Time Counter (RTC)
23.6.7
Synchronization Busy in COUNT32 mode (CTRLA.MODE=0)
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x10
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
14
13
12
11
10
9
8
6
5
COMP0
R
0
4
3
COUNT
R
0
2
FREQCORR
R
0
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
15
COUNTSYNC
Access
R
Reset
0
Bit
7
Access
Reset
Bit 15 – COUNTSYNC Count Read Sync Enable Synchronization Busy Status
Value
Description
0
Write synchronization for CTRLA.COUNTSYNC bit is complete.
1
Write synchronization for CTRLA.COUNTSYNC bit is ongoing.
Bit 5 – COMP0 Compare 0 Synchronization Busy Status
Value
Description
0
Write synchronization for COMP0 register is complete.
1
Write synchronization for COMP0 register is ongoing.
Bit 3 – COUNT Count Value Synchronization Busy Status
Value
Description
0
Read/write synchronization for COUNT register is complete.
1
Read/write synchronization for COUNT register is ongoing.
Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status
Value
Description
0
Write synchronization for FREQCORR register is complete.
1
Write synchronization for FREQCORR register is ongoing.
Bit 1 – ENABLE Enable Synchronization Busy Status
Value
Description
0
Write synchronization for CTRLA.ENABLE bit is complete.
1
Write synchronization for CTRLA.ENABLE bit is ongoing.
Bit 0 – SWRST Software Reset Synchronization Busy Status
Value
Description
0
Write synchronization for CTRLA.SWRST bit is complete.
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Real-Time Counter (RTC)
Value
1
Description
Write synchronization for CTRLA.SWRST bit is ongoing.
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Real-Time Counter (RTC)
23.6.8
Frequency Correction
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
FREQCORR
0x14
0x00
PAC Write-Protection, Write-Synchronized
7
SIGN
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
3
VALUE[6:0]
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bit 7 – SIGN Correction Sign
Value
Description
0
The correction value is positive, i.e., frequency will be decreased.
1
The correction value is negative, i.e., frequency will be increased.
Bits 6:0 – VALUE[6:0] Correction Value
These bits define the amount of correction applied to the RTC prescaler.
Value
Description
0
Correction is disabled and the RTC frequency is unchanged.
1 - 127 The RTC frequency is adjusted according to the value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 248
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.6.9
Counter Value in COUNT32 mode (CTRLA.MODE=0)
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
COUNT
0x18
0x00000000
PAC Write-Protection, Write-Synchronized, Read-Synchronized
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
COUNT[31:24]
R/W
R/W
0
0
20
19
COUNT[23:16]
R/W
R/W
0
0
12
11
COUNT[15:8]
R/W
R/W
0
0
4
3
COUNT[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – COUNT[31:0] Counter Value
These bits define the value of the 32-bit RTC counter in mode 0. This register must be written with a 32-bit write
access.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 249
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.6.10 Compare 0 Value in COUNT32 mode (CTRLA.MODE=0)
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
COMP
0x20
0x00000000
PAC Write-Protection, Write-Synchronized
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
28
27
COMP[31:24]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
20
19
COMP[23:16]
R/W
R/W
0
0
12
11
COMP[15:8]
R/W
R/W
0
0
4
COMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – COMP[31:0] Compare Value
The 32-bit value of COMP0 is continuously compared with the 32-bit COUNT value. When a match occurs, the
Compare 0 interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMP0) is set on the next counter
cycle, and the counter value is cleared if CTRLA.MATCHCLR is '1'.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 250
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.6.11 General Purpose n
Name:
Offset:
Reset:
Property:
Bit
31
GPn
0x40 + n*0x04 [n=0..1]
0x00000000
-
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
GP[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
GP[23:16]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
GP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
GP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – GP[31:0] General Purpose
These bits are for user-defined general purpose use.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 251
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.7
Register Summary - Mode 1 - 16-Bit Counter
Offset
Name
Bit Pos.
7
0x00
CTRLA
7:0
15:8
COUNTSYNC
0x02
...
0x03
Reserved
0x04
EVCTRL
0x08
INTENCLR
0x0A
INTENSET
0x0C
INTFLAG
0x0E
0x0F
DBGCTRL
Reserved
0x10
SYNCBUSY
0x14
0x15
...
0x17
FREQCORR
0x18
COUNT
0x1A
...
0x1B
Reserved
0x1C
PER
0x1E
...
0x1F
Reserved
0x20
COMP0
0x22
COMP1
0x24
...
0x3F
Reserved
0x40
GP0
0x44
GP1
7:0
15:8
23:16
31:24
7:0
15:8
7:0
15:8
7:0
15:8
7:0
7:0
15:8
23:16
31:24
7:0
6
5
4
3
2
MODE[1:0]
1
ENABLE
PRESCALER[3:0]
0
SWRST
PEREO7
OVFEO
PEREO6
PEREO5
PEREO4
PEREO3
PEREO2
PEREO1
CMPEO1
PEREO0
CMPEO0
PER7
OVF
PER7
OVF
PER7
OVF
PER6
PER5
PER4
PER3
PER2
PER6
PER5
PER4
PER3
PER2
PER6
PER5
PER4
PER3
PER2
PER1
CMP1
PER1
CMP1
PER1
CMP1
PER0
CMP0
PER0
CMP0
PER0
CMP0
DBGRUN
COMP1
COMP0
PER
COUNT
FREQCORR
ENABLE
SWRST
GP1
GP0
COUNTSYNC
SIGN
VALUE[6:0]
Reserved
7:0
15:8
COUNT[7:0]
COUNT[15:8]
7:0
15:8
PER[7:0]
PER[15:8]
7:0
15:8
7:0
15:8
COMP[7:0]
COMP[15:8]
COMP[7:0]
COMP[15:8]
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
GP[7:0]
GP[15:8]
GP[23:16]
GP[31:24]
GP[7:0]
GP[15:8]
GP[23:16]
GP[31:24]
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 252
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.7.1
Control A in COUNT16 mode (CTRLA.MODE=1)
Name:
Offset:
Reset:
Property:
CTRLA
0x00
0x0000
PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
15
COUNTSYNC
Access
R/W
Reset
0
Bit
7
14
13
12
11
10
9
PRESCALER[3:0]
R/W
R/W
0
0
R/W
0
6
5
4
3
2
MODE[1:0]
Access
Reset
R/W
0
R/W
0
1
ENABLE
R/W
0
8
R/W
0
0
SWRST
R/W
0
Bit 15 – COUNTSYNC COUNT Read Synchronization Enable
The COUNT register requires synchronization when reading. Disabling the synchronization will prevent reading valid
values from the COUNT register.
This bit is not enable-protected.
Value
Description
0
COUNT read synchronization is disabled
1
COUNT read synchronization is enabled
Bits 11:8 – PRESCALER[3:0] Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock
(CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not
synchronized.
Value
Name
Description
0x0
OFF
CLK_RTC_CNT = GCLK_RTC/1
0x1
DIV1
CLK_RTC_CNT = GCLK_RTC/1
0x2
DIV2
CLK_RTC_CNT = GCLK_RTC/2
0x3
DIV4
CLK_RTC_CNT = GCLK_RTC/4
0x4
DIV8
CLK_RTC_CNT = GCLK_RTC/8
0x5
DIV16
CLK_RTC_CNT = GCLK_RTC/16
0x6
DIV32
CLK_RTC_CNT = GCLK_RTC/32
0x7
DIV64
CLK_RTC_CNT = GCLK_RTC/64
0x8
DIV128
CLK_RTC_CNT = GCLK_RTC/128
0x9
DIV256
CLK_RTC_CNT = GCLK_RTC/256
0xA
DIV512
CLK_RTC_CNT = GCLK_RTC/512
0xB
DIV1024
CLK_RTC_CNT = GCLK_RTC/1024
0xC-0xF Reserved
Bits 3:2 – MODE[1:0] Operating Mode
This field defines the operating mode of the RTC. This bit is not synchronized.
Value
Name
Description
0x0
COUNT32
Mode 0: 32-bit counter
0x1
COUNT16
Mode 1: 16-bit counter
0x2
CLOCK
Mode 2: Clock/calendar
0x3
Reserved
Bit 1 – ENABLE Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register
(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 253
PIC32CM MC00 Family
Real-Time Counter (RTC)
Value
0
1
Description
The peripheral is disabled
The peripheral is enabled
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC will be
disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST will
be cleared when the reset is complete.
Value
Description
0
There is not reset operation ongoing
1
The reset operation is ongoing
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 254
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.7.2
Event Control in COUNT16 mode (CTRLA.MODE=1)
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x04
0x00000000
PAC Write-Protection, Enable-Protected
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OVFEO
R/W
0
14
13
12
11
10
9
CMPEO1
R/W
0
8
CMPEO0
R/W
0
7
PEREO7
R/W
0
6
PEREO6
R/W
0
5
PEREO5
R/W
0
4
PEREO4
R/W
0
3
PEREO3
R/W
0
2
PEREO2
R/W
0
1
PEREO1
R/W
0
0
PEREO0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 15 – OVFEO Overflow Event Output Enable
Value
Description
0
Overflow event is disabled and will not be generated.
1
Overflow event is enabled and will be generated for every overflow.
Bits 8, 9 – CMPEOx Compare x Event Output Enable [x = 1..0]
Value
Description
0
Compare x event is disabled and will not be generated.
1
Compare x event is enabled and will be generated for every compare match.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PEREOx Periodic Interval x Event Output Enable [x = 7..0]
Value
Description
0
Periodic Interval x event is disabled and will not be generated.
1
Periodic Interval x event is enabled and will be generated.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 255
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.7.3
Interrupt Enable Clear in COUNT16 mode (CTRLA.MODE=1)
Name:
Offset:
Reset:
Property:
INTENCLR
0x08
0x0000
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
Access
Reset
Bit
Access
Reset
15
OVF
R/W
0
14
13
12
11
10
9
CMP1
R/W
0
8
CMP0
R/W
0
7
PER7
R/W
0
6
PER6
R/W
0
5
PER5
R/W
0
4
PER4
R/W
0
3
PER3
R/W
0
2
PER2
R/W
0
1
PER1
R/W
0
0
PER0
R/W
0
Bit 15 – OVF Overflow Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables
the Overflow interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
Bits 8, 9 – CMPx Compare x Interrupt Enable [x = 1..0]
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Compare x Interrupt Enable bit, which
disables the Compare x interrupt.
Value
Description
0
The Compare x interrupt is disabled.
1
The Compare x interrupt is enabled.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERx Periodic Interval x Interrupt Enable [x = 7..0]
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval x Interrupt Enable bit, which
disables the Periodic Interval x interrupt.
Value
Description
0
Periodic Interval x interrupt is disabled.
1
Periodic Interval x interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 256
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.7.4
Interrupt Enable Set in COUNT16 mode (CTRLA.MODE=1)
Name:
Offset:
Reset:
Property:
INTENSET
0x0A
0x0000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
Access
Reset
Bit
Access
Reset
15
OVF
R/W
0
14
13
12
11
10
9
CMP1
R/W
0
8
CMP0
R/W
0
7
PER7
R/W
0
6
PER6
R/W
0
5
PER5
R/W
0
4
PER4
R/W
0
3
PER3
R/W
0
2
PER2
R/W
0
1
PER1
R/W
0
0
PER0
R/W
0
Bit 15 – OVF Overflow Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the
Overflow interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
Bits 8, 9 – CMPx Compare x Interrupt Enable [x = 1..0]
Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Compare x Interrupt Enable bit, which and
enables the Compare x interrupt.
Value
Description
0
The Compare x interrupt is disabled.
1
The Compare x interrupt is enabled.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERx Periodic Interval x Interrupt Enable [x = 7..0]
Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval x Interrupt Enable bit, which
enables the Periodic Interval x interrupt.
Value
Description
0
Periodic Interval x interrupt is disabled.
1
Periodic Interval x interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 257
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.7.5
Interrupt Flag Status and Clear in COUNT16 mode (CTRLA.MODE=1)
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
INTFLAG
0x0C
0x0000
-
15
OVF
R/W
0
14
13
12
11
10
9
CMP1
R/W
0
8
CMP0
R/W
0
7
PER7
R/W
0
6
PER6
R/W
0
5
PER5
R/W
0
4
PER4
R/W
0
3
PER3
R/W
0
2
PER2
R/W
0
1
PER1
R/W
0
0
PER0
R/W
0
Bit 15 – OVF Overflow
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be
generated if INTENCLR/SET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
Bits 8, 9 – CMPx Compare x [x = 1..0]
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request
will be generated if INTENCLR/SET.COMPx is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Compare x interrupt flag.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERx Periodic Interval x [x = 7..0]
This flag is cleared by writing a '1' to the flag.
This flag is set on the 0-to-1 transition of prescaler bit [x+2], and an interrupt request will be generated if INTENCLR/
SET.PERx is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Periodic Interval x interrupt flag.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 258
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.7.6
Debug Control
Name:
Offset:
Reset:
Property:
Bit
DBGCTRL
0x0E
0x00
PAC Write-Protection
7
6
5
4
3
2
1
0
DBGRUN
R/W
0
Access
Reset
Bit 0 – DBGRUN Debug Run
This bit is not reset by a software reset.
This bit controls the functionality when the CPU is halted by an external debugger.
Value
Description
0
The RTC is halted when the CPU is halted by an external debugger.
1
The RTC continues normal operation when the CPU is halted by an external debugger.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 259
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.7.7
Synchronization Busy in COUNT16 mode (CTRLA.MODE=1)
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x10
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GP1
R/W
0
16
GP0
R/W
0
14
13
12
11
10
9
8
6
COMP1
R/W
0
5
COMP0
R/W
0
4
PER
R
0
3
COUNT
R
0
2
FREQCORR
R
0
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
15
COUNTSYNC
Access
R
Reset
0
Bit
7
Access
Reset
Bits 16, 17 – GPn General Purpose n
These bits are for user-defined general purpose use.
Bit 15 – COUNTSYNC Count Read Sync Enable Synchronization Busy Status
Value
Description
0
Write synchronization for CTRLA.COUNTSYNC bit is complete.
1
Write synchronization for CTRLA.COUNTSYNC bit is ongoing.
Bits 5, 6 – COMPx Compare x Synchronization Busy Status [x = 1..0]
Value
Description
0
Write synchronization for COMPx register is complete.
1
Write synchronization for COMPx register is ongoing.
Bit 4 – PER Period Synchronization Busy Status
Value
Description
0
Write synchronization for PER register is complete.
1
Write synchronization for PER register is ongoing.
Bit 3 – COUNT Count Value Synchronization Busy Status
Value
Description
0
Read/write synchronization for COUNT register is complete.
1
Read/write synchronization for COUNT register is ongoing.
Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status
Value
Description
0
Write synchronization for FREQCORR register is complete.
1
Write synchronization for FREQCORR register is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 260
PIC32CM MC00 Family
Real-Time Counter (RTC)
Bit 1 – ENABLE Enable Synchronization Busy Status
Value
Description
0
Write synchronization for CTRLA.ENABLE bit is complete.
1
Write synchronization for CTRLA.ENABLE bit is ongoing.
Bit 0 – SWRST Software Reset Synchronization Busy Status
Value
Description
0
Write synchronization for CTRLA.SWRST bit is complete.
1
Write synchronization for CTRLA.SWRST bit is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 261
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.7.8
Frequency Correction
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
FREQCORR
0x14
0x00
PAC Write-Protection, Write-Synchronized
7
SIGN
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
3
VALUE[6:0]
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bit 7 – SIGN Correction Sign
Value
Description
0
The correction value is positive, i.e., frequency will be decreased.
1
The correction value is negative, i.e., frequency will be increased.
Bits 6:0 – VALUE[6:0] Correction Value
These bits define the amount of correction applied to the RTC prescaler.
Value
Description
0
Correction is disabled and the RTC frequency is unchanged.
1 - 127 The RTC frequency is adjusted according to the value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 262
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.7.9
Counter Value in COUNT16 mode (CTRLA.MODE=1)
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
COUNT
0x18
0x0000
PAC Write-Protection, Write-Synchronized, Read-Synchronized
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
COUNT[15:8]
R/W
R/W
0
0
4
3
COUNT[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – COUNT[15:0] Counter Value
These bits define the value of the 16-bit RTC counter in COUNT16 mode (CTRLA.MODE=1). This register must be
written with a 16-bit write access.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 263
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.7.10 Counter Period in COUNT16 mode (CTRLA.MODE=1)
Name:
Offset:
Reset:
Property:
Bit
PER
0x1C
0x0000
PAC Write-Protection, Write-Synchronized
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PER[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PER[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PER[15:0] Counter Period
These bits define the value of the 16-bit RTC period in COUNT16 mode (CTRLA.MODE=1).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 264
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.7.11 Compare n Value in COUNT16 mode (CTRLA.MODE=1)
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
COMP
0x20 + n*0x02 [n=0..1]
0x0000
PAC Write-Protection, Write-Synchronized
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
COMP[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
COMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – COMP[15:0] Compare Value
The 16-bit value of COMPn is continuously compared with the 16-bit COUNT value. When a match occurs, the
Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter
cycle.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 265
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.7.12 General Purpose n
Name:
Offset:
Reset:
Property:
Bit
31
GPn
0x40 + n*0x04 [n=0..1]
0x00000000
-
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
GP[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
GP[23:16]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
GP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
GP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – GP[31:0] General Purpose
These bits are for user-defined general purpose use.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 266
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.8
Register Summary - Mode 2 - Clock/Calendar
Offset
Name
Bit Pos.
7
6
0x00
CTRLA
7:0
15:8
MATCHCLR
CLOCKSYNC
CLKREP
0x02
...
0x03
Reserved
7:0
15:8
23:16
31:24
7:0
15:8
7:0
15:8
7:0
15:8
7:0
PEREO7
OVFEO
PEREO6
PEREO5
PEREO4
PEREO3
PEREO2
PEREO1
PEREO0
ALARMEO0
PER7
OVF
PER7
OVF
PER7
OVF
PER6
PER5
PER4
PER3
PER2
PER1
PER6
PER5
PER4
PER3
PER2
PER1
PER6
PER5
PER4
PER3
PER2
PER1
PER0
ALARM0
PER0
ALARM0
PER0
ALARM0
DBGRUN
CLOCK
MASK0
FREQCORR
ENABLE
SWRST
GP1
GP0
0x04
EVCTRL
0x08
INTENCLR
0x0A
INTENSET
0x0C
INTFLAG
0x0E
0x0F
DBGCTRL
Reserved
0x10
SYNCBUSY
0x14
0x15
...
0x17
FREQCORR
0x18
0x1C
...
0x1F
0x20
0x24
0x25
...
0x3F
7:0
15:8
23:16
31:24
7:0
5
4
3
2
MODE[1:0]
ALARM0
CLOCKSYNC
SIGN
1
0
ENABLE
PRESCALER[3:0]
SWRST
VALUE[6:0]
Reserved
CLOCK
7:0
15:8
23:16
31:24
MINUTE[1:0]
7:0
15:8
23:16
31:24
7:0
MINUTE[1:0]
SECOND[5:0]
HOUR[3:0]
MINUTE[5:2]
MONTH[1:0]
DAY[4:0]
HOUR[4]
MONTH[3:2]
YEAR[5:0]
Reserved
ALARM
MASK
SECOND[5:0]
HOUR[3:0]
MINUTE[5:2]
MONTH[1:0]
DAY[4:0]
YEAR[5:0]
HOUR[4]
MONTH[3:2]
SEL[2:0]
Reserved
0x40
GP0
0x44
GP1
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
© 2021 Microchip Technology Inc.
and its subsidiaries
GP[7:0]
GP[15:8]
GP[23:16]
GP[31:24]
GP[7:0]
GP[15:8]
GP[23:16]
GP[31:24]
Datasheet
DS60001638D-page 267
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.8.1
Control A in Clock/Calendar mode (CTRLA.MODE=2)
Name:
Offset:
Reset:
Property:
CTRLA
0x00
0x0000
PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
15
CLOCKSYNC
Access
R/W
Reset
0
Bit
Access
Reset
7
MATCHCLR
R/W
0
14
13
12
11
10
9
PRESCALER[3:0]
R/W
R/W
0
0
R/W
0
6
CLKREP
R/W
0
5
4
3
2
MODE[1:0]
R/W
0
R/W
0
1
ENABLE
R/W
0
8
R/W
0
0
SWRST
R/W
0
Bit 15 – CLOCKSYNC CLOCK Read Synchronization Enable
The CLOCK register requires synchronization when reading. Disabling the synchronization will prevent reading valid
values from the CLOCK register.
This bit is not enable-protected.
Value
Description
0
CLOCK read synchronization is disabled
1
CLOCK read synchronization is enabled
Bits 11:8 – PRESCALER[3:0] Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock
(CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not
synchronized.
Value
Name
Description
0x0
OFF
CLK_RTC_CNT = GCLK_RTC/1
0x1
DIV1
CLK_RTC_CNT = GCLK_RTC/1
0x2
DIV2
CLK_RTC_CNT = GCLK_RTC/2
0x3
DIV4
CLK_RTC_CNT = GCLK_RTC/4
0x4
DIV8
CLK_RTC_CNT = GCLK_RTC/8
0x5
DIV16
CLK_RTC_CNT = GCLK_RTC/16
0x6
DIV32
CLK_RTC_CNT = GCLK_RTC/32
0x7
DIV64
CLK_RTC_CNT = GCLK_RTC/64
0x8
DIV128
CLK_RTC_CNT = GCLK_RTC/128
0x9
DIV256
CLK_RTC_CNT = GCLK_RTC/256
0xA
DIV512
CLK_RTC_CNT = GCLK_RTC/512
0xB
DIV1024
CLK_RTC_CNT = GCLK_RTC/1024
0xC-0xF Reserved
Bit 7 – MATCHCLR Clear on Match
This bit is valid only in Mode 0 (COUNT32) and Mode 2 (CLOCK). This bit can be written only when the peripheral is
disabled. This bit is not synchronized.
Value
Description
0
The counter is not cleared on a Compare/Alarm 0 match
1
The counter is cleared on a Compare/Alarm 0 match
Bit 6 – CLKREP Clock Representation
This bit is valid only in Mode 2 and determines how the hours are represented in the Clock Value (CLOCK) register.
This bit can be written only when the peripheral is disabled. This bit is not synchronized.
Value
Description
0
24 Hour
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 268
PIC32CM MC00 Family
Real-Time Counter (RTC)
Value
1
Description
12 Hour (AM/PM)
Bits 3:2 – MODE[1:0] Operating Mode
This field defines the operating mode of the RTC. This bit is not synchronized.
Value
Name
Description
0x0
COUNT32
Mode 0: 32-bit counter
0x1
COUNT16
Mode 1: 16-bit counter
0x2
CLOCK
Mode 2: Clock/calendar
0x3
Reserved
Bit 1 – ENABLE Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register
(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
Value
Description
0
The peripheral is disabled
1
The peripheral is enabled
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be
disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST will
be cleared when the reset is complete.
Value
Description
0
There is not reset operation ongoing
1
The reset operation is ongoing
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 269
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.8.2
Event Control in Clock/Calendar mode (CTRLA.MODE=2)
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x04
0x00000000
PAC Write-Protection, Enable-Protected
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OVFEO
R/W
0
14
13
12
11
10
9
8
ALARMEO0
R/W
0
7
PEREO7
R/W
0
6
PEREO6
R/W
0
5
PEREO5
R/W
0
4
PEREO4
R/W
0
3
PEREO3
R/W
0
2
PEREO2
R/W
0
1
PEREO1
R/W
0
0
PEREO0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 15 – OVFEO Overflow Event Output Enable
Value
Description
0
Overflow event is disabled and will not be generated.
1
Overflow event is enabled and will be generated for every overflow.
Bit 8 – ALARMEO0 Alarm 0 Event Output Enable
Value
Description
0
Alarm 0 event is disabled and will not be generated.
1
Alarm 0 event is enabled and will be generated for every compare match.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PEREOx Periodic Interval x Event Output Enable [x = 7..0]
Value
Description
0
Periodic Interval x event is disabled and will not be generated.
1
Periodic Interval x event is enabled and will be generated.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 270
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.8.3
Interrupt Enable Clear in Clock/Calendar mode (CTRLA.MODE=2)
Name:
Offset:
Reset:
Property:
INTENCLR
0x08
0x0000
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
Access
Reset
Bit
Access
Reset
15
OVF
R/W
0
14
13
12
11
10
9
8
ALARM0
R/W
0
7
PER7
R/W
0
6
PER6
R/W
0
5
PER5
R/W
0
4
PER4
R/W
0
3
PER3
R/W
0
2
PER2
R/W
0
1
PER1
R/W
0
0
PER0
R/W
0
Bit 15 – OVF Overflow Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables
the Overflow interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
Bit 8 – ALARM0 Alarm 0 Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Alarm 0 Interrupt Enable bit, which disables
the Alarm interrupt.
Value
Description
0
The Alarm 0 interrupt is disabled.
1
The Alarm 0 interrupt is enabled.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERx Periodic Interval x Interrupt Enable [x = 7..0]
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval x Interrupt Enable bit, which
disables the Periodic Interval x interrupt.
Value
Description
0
Periodic Interval x interrupt is disabled.
1
Periodic Interval x interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 271
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.8.4
Interrupt Enable Set in Clock/Calendar mode (CTRLA.MODE=2)
Name:
Offset:
Reset:
Property:
INTENSET
0x0A
0x0000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
Access
Reset
Bit
Access
Reset
15
OVF
R/W
0
14
13
12
11
10
9
8
ALARM0
R/W
0
7
PER7
R/W
0
6
PER6
R/W
0
5
PER5
R/W
0
4
PER4
R/W
0
3
PER3
R/W
0
2
PER2
R/W
0
1
PER1
R/W
0
0
PER0
R/W
0
Bit 15 – OVF Overflow Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the
Overflow interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
Bit 8 – ALARM0 Alarm 0 Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Alarm 0 Interrupt Enable bit, which enables the
Alarm 0 interrupt.
Value
Description
0
The Alarm 0 interrupt is disabled.
1
The Alarm 0 interrupt is enabled.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERx Periodic Interval x Interrupt Enable [x = 7..0]
Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval x Interrupt Enable bit, which
enables the Periodic Interval x interrupt.
Value
Description
0
Periodic Interval x interrupt is disabled.
1
Periodic Interval x interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 272
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.8.5
Interrupt Flag Status and Clear in Clock/Calendar mode (CTRLA.MODE=2)
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
INTFLAG
0x0C
0x0000
-
15
OVF
R/W
0
14
13
12
11
10
9
8
ALARM0
R/W
0
7
PER7
R/W
0
6
PER6
R/W
0
5
PER5
R/W
0
4
PER4
R/W
0
3
PER3
R/W
0
2
PER2
R/W
0
1
PER1
R/W
0
0
PER0
R/W
0
Bit 15 – OVF Overflow
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be
generated if INTENCLR/SET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
Bit 8 – ALARM0 Alarm 0
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request
will be generated if INTENCLR/SET.ALARM0 is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Alarm 0 interrupt flag.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERx Periodic Interval x [x = 7..0]
This flag is cleared by writing a '1' to the flag.
This flag is set on the 0-to-1 transition of prescaler bit [x+2], and an interrupt request will be generated if INTENCLR/
SET.PERx is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Periodic Interval x interrupt flag.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 273
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.8.6
Debug Control
Name:
Offset:
Reset:
Property:
Bit
DBGCTRL
0x0E
0x00
PAC Write-Protection
7
6
5
4
3
2
1
0
DBGRUN
R/W
0
Access
Reset
Bit 0 – DBGRUN Debug Run
This bit is not reset by a software reset.
This bit controls the functionality when the CPU is halted by an external debugger.
Value
Description
0
The RTC is halted when the CPU is halted by an external debugger.
1
The RTC continues normal operation when the CPU is halted by an external debugger.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 274
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.8.7
Synchronization Busy in Clock/Calendar mode (CTRLA.MODE=2)
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x10
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GP1
R/W
0
16
GP0
R/W
0
14
13
12
11
MASK0
R
0
10
9
8
6
5
ALARM0
R
0
4
3
CLOCK
R
0
2
FREQCORR
R
0
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
15
CLOCKSYNC
Access
R
Reset
0
Bit
7
Access
Reset
Bits 16, 17 – GPn General Purpose n
These bits are for user-defined general purpose use.
Bit 15 – CLOCKSYNC Clock Read Sync Enable Synchronization Busy Status
Value
Description
0
Write synchronization for CTRLA.CLOCKSYNC bit is complete.
1
Write synchronization for CTRLA.CLOCKSYNC bit is ongoing.
Bit 11 – MASK0 Mask 0 Synchronization Busy Status
Value
Description
0
Write synchronization for MASK0 register is complete.
1
Write synchronization for MASK0 register is ongoing.
Bit 5 – ALARM0 Alarm 0 Synchronization Busy Status
Value
Description
0
Write synchronization for ALARM0 register is complete.
1
Write synchronization for ALARM0 register is ongoing.
Bit 3 – CLOCK Clock Register Synchronization Busy Status
Value
Description
0
Read/write synchronization for CLOCK register is complete.
1
Read/write synchronization for CLOCK register is ongoing.
Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status
Value
Description
0
Write synchronization for FREQCORR register is complete.
1
Write synchronization for FREQCORR register is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 275
PIC32CM MC00 Family
Real-Time Counter (RTC)
Bit 1 – ENABLE Enable Synchronization Busy Status
Value
Description
0
Write synchronization for CTRLA.ENABLE bit is complete.
1
Write synchronization for CTRLA.ENABLE bit is ongoing.
Bit 0 – SWRST Software Reset Synchronization Busy Status
Value
Description
0
Write synchronization for CTRLA.SWRST bit is complete.
1
Write synchronization for CTRLA.SWRST bit is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 276
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.8.8
Frequency Correction
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
FREQCORR
0x14
0x00
PAC Write-Protection, Write-Synchronized
7
SIGN
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
3
VALUE[6:0]
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bit 7 – SIGN Correction Sign
Value
Description
0
The correction value is positive, i.e., frequency will be decreased.
1
The correction value is negative, i.e., frequency will be increased.
Bits 6:0 – VALUE[6:0] Correction Value
These bits define the amount of correction applied to the RTC prescaler.
Value
Description
0
Correction is disabled and the RTC frequency is unchanged.
1 - 127 The RTC frequency is adjusted according to the value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 277
PIC32CM MC00 Family
Real-Time Counter (RTC)
23.8.9
Clock Value in Clock/Calendar mode (CTRLA.MODE=2)
Name:
Offset:
Reset:
Property:
CLOCK
0x18
0x00000000
PAC Write-Protection, Write-Synchronized, Read-Synchronized
Note: This register must be written with a 32-bit write access.
Bit
31
30
29
28
27
26
R/W
0
R/W
0
R/W
0
R/W
0
21
20
18
17
R/W
0
R/W
0
19
DAY[4:0]
R/W
0
R/W
0
R/W
0
13
12
11
10
R/W
0
R/W
0
R/W
0
5
4
3
R/W
0
R/W
0
YEAR[5:0]
Access
Reset
Bit
Access
Reset
Bit
R/W
0
R/W
0
23
22
MONTH[1:0]
R/W
R/W
0
0
15
14
HOUR[3:0]
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
7
6
MINUTE[1:0]
R/W
R/W
0
0
25
24
MONTH[3:2]
R/W
R/W
0
0
9
MINUTE[5:2]
R/W
R/W
0
0
2
SECOND[5:0]
R/W
R/W
0
0
16
HOUR[4]
R/W
0
8
R/W
0
1
0
R/W
0
R/W
0
Bits 31:26 – YEAR[5:0] Year
The year offset with respect to the reference year (defined in software).
The year is considered a leap year if YEAR[1:0] is zero.
Bits 25:22 – MONTH[3:0] Month
1 – January
2 – February
...
12 – December
Bits 21:17 – DAY[4:0] Day
Day starts at 1 and ends at 28, 29, 30, or 31, depending on the month and year.
Bits 16:12 – HOUR[4:0] Hour
When CTRLA.CLKREP=0, the Hour bit group is in 24-hour format, with values 0-23. When CTRLA.CLKREP=1,
HOUR[3:0] has values 1-12, and HOUR[4] represents AM (0) or PM (1).
Bits 11:6 – MINUTE[5:0] Minute
0 – 59
Bits 5:0 – SECOND[5:0] Second
0 – 59
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PIC32CM MC00 Family
Real-Time Counter (RTC)
23.8.10 Alarm Value in Clock/Calendar mode (CTRLA.MODE=2)
Name:
Offset:
Reset:
Property:
ALARM
0x20
0x00000000
PAC Write-Protection, Write-Synchronized
The 32-bit value of ALARM is continuously compared with the 32-bit CLOCK value, based on the masking set
by MASK.SEL. When a match occurs, the Alarm n interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.ALARM) is set on the next counter cycle, and the counter is cleared if CTRLA.MATCHCLR is '1'.
Bit
31
30
29
28
27
26
R/W
0
R/W
0
R/W
0
R/W
0
21
20
18
17
R/W
0
R/W
0
19
DAY[4:0]
R/W
0
R/W
0
R/W
0
13
12
11
10
R/W
0
R/W
0
R/W
0
5
4
3
R/W
0
R/W
0
YEAR[5:0]
Access
Reset
Bit
Access
Reset
Bit
R/W
0
R/W
0
23
22
MONTH[1:0]
R/W
R/W
0
0
15
14
HOUR[3:0]
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
7
6
MINUTE[1:0]
R/W
R/W
0
0
25
24
MONTH[3:2]
R/W
R/W
0
0
9
MINUTE[5:2]
R/W
R/W
0
0
2
SECOND[5:0]
R/W
R/W
0
0
16
HOUR[4]
R/W
0
8
R/W
0
1
0
R/W
0
R/W
0
Bits 31:26 – YEAR[5:0] Year
The alarm year. Years are only matched if MASK.SEL is 6
Bits 25:22 – MONTH[3:0] Month
The alarm month. Months are matched only if MASK.SEL is greater than 4.
Bits 21:17 – DAY[4:0] Day
The alarm day. Days are matched only if MASK.SEL is greater than 3.
Bits 16:12 – HOUR[4:0] Hour
The alarm hour. Hours are matched only if MASK.SEL is greater than 2.
Bits 11:6 – MINUTE[5:0] Minute
The alarm minute. Minutes are matched only if MASK.SEL is greater than 1.
Bits 5:0 – SECOND[5:0] Second
The alarm second. Seconds are matched only if MASK.SEL is greater than 0.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Real-Time Counter (RTC)
23.8.11 Alarm Mask in Clock/Calendar mode (CTRLA.MODE=2)
Name:
Offset:
Reset:
Property:
Bit
MASK
0x24
0x00
PAC Write-Protection, Write-Synchronized
7
6
5
4
3
Access
Reset
2
R/W
0
1
SEL[2:0]
R/W
0
0
R/W
0
Bits 2:0 – SEL[2:0] Alarm Mask Selection
These bits define which bit groups of ALARM are valid.
Value
Name
Description
0x0
OFF
Alarm Disabled
0x1
SS
Match seconds only
0x2
MMSS
Match seconds and minutes only
0x3
HHMMSS
Match seconds, minutes, and hours only
0x4
DDHHMMSS
Match seconds, minutes, hours, and days only
0x5
MMDDHHMMSS
Match seconds, minutes, hours, days, and months only
0x6
YYMMDDHHMMSS
Match seconds, minutes, hours, days, months, and years
0x7
Reserved
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Real-Time Counter (RTC)
23.8.12 General Purpose n
Name:
Offset:
Reset:
Property:
Bit
31
GPn
0x40 + n*0x04 [n=0..1]
0x00000000
-
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
GP[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
GP[23:16]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
GP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
GP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – GP[31:0] General Purpose
These bits are for user-defined general purpose use.
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Datasheet
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.
Direct Memory Access Controller (DMAC)
24.1
Overview
The Direct Memory Access Controller (DMAC) contains both a Direct Memory Access engine and a Cyclic
Redundancy Check (CRC) engine. The DMAC can transfer data between memories and peripherals, and thus
off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up
CPU time. With access to all peripherals, the DMAC can handle automatic transfer of data between communication
modules.
The DMA part of the DMAC has several DMA channels which can receive different types of transfer triggers and
generate transfer requests from the DMA channels to the arbiter (Refer to the Block Diagram). The arbiter will select
one DMA channel at a time to act as the active channel. When an active channel has been selected, the fetch engine
of the DMAC will fetch a transfer descriptor from the SRAM and store it in the internal memory of the active channel,
which will then execute the data transmission.
An ongoing data transfer of an active channel can be interrupted by a higher prioritized DMA channel. The DMAC
will write back the updated transfer descriptor from the internal memory of the active channel to SRAM, and grant the
higher prioritized channel to start transfer as the new active channel. Once a DMA channel is done with its transfer,
interrupts and events can be generated optionally.
The DMAC has four bus interfaces:
•
•
•
•
The data transfer bus is used for performing the actual DMA transfer.
The AHB/APB Bridge bus is used when writing and reading the I/O registers of the DMAC.
The descriptor fetch bus is used by the fetch engine to fetch transfer descriptors before data transfer can be
started or continued.
The write-back bus is used to write the transfer descriptor back to SRAM.
All buses are AHB host interfaces except the AHB/APB Bridge bus, which is an APB client interface.
The CRC engine can be used by software to detect an accidental error in the transferred data and to take corrective
action, such as requesting the data to be sent again or simply not using the incorrect data.
24.2
Features
•
•
•
•
•
Data transfer from:
– Peripheral-to-peripheral
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
Transfer trigger sources
– Software
– Events from Event System
– Dedicated requests from peripherals
SRAM-based transfer descriptors
– Single transfer using one descriptor
– Multi-buffer or circular buffer modes by linking multiple descriptors
Up to 12 channels
– Enable 12 independent transfers
– Automatic descriptor fetch for each channel
– Suspend/resume operation support for each channel
Flexible arbitration scheme
– 4 configurable priority levels for each channel
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and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
•
•
•
•
•
•
•
Block Diagram
Figure 24-1. DMAC Block Diagram
CPU
H
H
AHB/APB
Bridge
SRAM
Write-back
C
C
Descriptor Fetch
HIGH SPEED
BUS MATRIX
Data Transfer
24.3
– Fixed or round-robin priority scheme within each priority level
From 1 KB to 256 KB data transfer in a single block transfer
Multiple addressing modes:
– Static
– Configurable increment scheme
Optional interrupt generation
– On block transfer complete
– On error detection
– On channel suspend
4 event inputs
– One event input for each of the 4 least significant DMA channels
– Can be selected to trigger normal transfers, periodic transfers or conditional transfers
– Can be selected to suspend or resume channel operation
4 event outputs
– One output event for each of the 4 least significant DMA channels
– Selectable generation on AHB, block, or transaction transfer complete
Error management supported by write-back function
– Dedicated Write-Back memory section for each channel to store ongoing descriptor transfer
CRC polynomial software selectable to
– CRC-16 (CRC-CCITT)
– CRC-32 (IEEE® 802.3)
DMAC
HOST
Fetch
Engine
DMA Channels
Channel n
Transfer
Triggers
n
Channel 1
Channel 0
Interrupts
Arbiter
Active
Channel
Interrupt /
Events
Events
CRC
Engine
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.4
Peripheral Dependencies
AHB CLK
APB CLK
Generic CLK
PAC
Events
Index
Index Prot at reset
DMA
Peripheral Base Address IRQ
Sleep Walking
Enabled at reset Enabled at reset
DMAC
24.5
24.5.1
0x41006000
7
Y
N/A
-
3
N
User
Generator
5-8: CH0-3 31-34: CH0-3
Index
-
Y
Functional Description
Principle of Operation
The DMAC consists of a DMA module and a CRC module.
24.5.1.1 DMA
The DMAC can transfer data between memories and peripherals without interaction from the CPU. The data
transferred by the DMAC are called transactions, and these transactions can be split into smaller data transfers.
The following figure shows the relationship between the different transfer sizes:
Figure 24-2. DMA Transfer Sizes
Link Enabled
Beat transfer
•
•
•
Link Enabled
Burst transfer
Link Enabled
Block transfer
DMA transaction
Beat transfer: The size of one data transfer bus access, and the size is selected by writing the Beat Size bit
group in the Block Transfer Control register (BTCTRL.BEATSIZE)
Block transfer: The amount of data one transfer descriptor can transfer, and the amount can range from 1 to 64k
beats. A block transfer can be interrupted.
Transaction: The DMAC can link several transfer descriptors by having the first descriptor pointing to the second
and so forth, as shown in the figure above. A DMA transaction is the complete transfer of all blocks within a
linked list.
A transfer descriptor describes how a block transfer should be carried out by the DMAC, and it must remain in SRAM.
For further details on the transfer descriptor refer to 24.5.2.3 Transfer Descriptors.
The figure above shows several block transfers linked together, which are called linked descriptors. For further
information about linked descriptors, refer to 24.5.3.1 Linked Descriptors.
A DMA transfer is initiated by an incoming transfer trigger on one of the DMA channels. This trigger can be
configured to be either a software trigger, an event trigger, or one of the dedicated peripheral triggers. The transfer
trigger will result in a DMA transfer request from the specific channel to the arbiter. If there are several DMA channels
with pending transfer requests, the arbiter chooses which channel is granted access to become the active channel.
The DMA channel granted access as the active channel will carry out the transaction as configured in the transfer
descriptor. A current transaction can be interrupted by a higher prioritized channel, but will resume the block transfer
when the according DMA channel is granted access as the active channel again.
For each beat transfer, an optional output event can be generated. For each block transfer, optional interrupts and an
optional output event can be generated. When a transaction is completed, depending on the configuration, the DMA
channel will either be suspended or disabled.
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Datasheet
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.5.1.2 CRC
The internal CRC engine supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32 (IEEE
802.3). It can be used on a selectable DMA channel, or on the I/O interface. Refer to 24.5.3.7 CRC Operation for
details.
24.5.2
Basic Operation
24.5.2.1 Initialization
The following DMAC registers are enable-protected, meaning that they can only be written when the DMAC is
disabled (CTRL.DMAENABLE=0):
•
•
Descriptor Base Memory Address register (BASEADDR)
Write-Back Memory Base Address register (WRBADDR)
The following DMAC bit is enable-protected, meaning that it can only be written when both the DMAC and CRC are
disabled (CTRL.DMAENABLE=0 and CTRL.CRCENABLE=0):
•
Software Reset bit in Control register (CTRL.SWRST)
The following DMA channel register is enable-protected, meaning that it can only be written when the corresponding
DMA channel is disabled (CHCTRLA.ENABLE=0):
•
Channel Control B (CHCTRLB) register, except the Command bit (CHCTRLB.CMD) and the Channel Arbitration
Level bit (CHCTRLB.LVL)
The following DMA channel bit is enable-protected, meaning that it can only be written when the corresponding DMA
channel is disabled:
•
Channel Software Reset bit in Channel Control A register (CHCTRLA.SWRST)
The following CRC registers are enable-protected, meaning that they can only be written when the CRC is disabled
(CTRL.CRCENABLE=0):
•
•
CRC Control register (CRCCTRL)
CRC Checksum register (CRCCHKSUM)
Enable-protection is denoted by the "Enable-Protected" property in the register description.
Before the DMAC is enabled it must be configured, as outlined by the following steps:
•
•
•
The SRAM address of where the descriptor memory section is located must be written to the Description Base
Address (BASEADDR) register
The SRAM address of where the write-back section should be located must be written to the Write-Back
Memory Base Address (WRBADDR) register
Priority level x of the arbiter can be enabled by setting the Priority Level x Enable bit in the Control register
(CTRL.LVLENx=1)
Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must be
configured, as outlined by the following steps:
•
•
DMA channel configurations
– The channel number of the DMA channel to configure must be written to the Channel ID (CHID) register
– Trigger action must be selected by writing the Trigger Action bit group in the Channel Control B register
(CHCTRLB.TRIGACT)
– Trigger source must be selected by writing the Trigger Source bit group in the Channel Control B register
(CHCTRLB.TRIGSRC)
Transfer Descriptor
– The size of each access of the data transfer bus must be selected by writing the Beat Size bit group in the
Block Transfer Control register (BTCTRL.BEATSIZE)
– The transfer descriptor must be made valid by writing a one to the Valid bit in the Block Transfer Control
register (BTCTRL.VALID)
– Number of beats in the block transfer must be selected by writing the Block Transfer Count (BTCNT)
register
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
– Source address for the block transfer must be selected by writing the Block Transfer Source Address
(SRCADDR) register
– Destination address for the block transfer must be selected by writing the Block Transfer Destination
Address (DSTADDR) register
If CRC calculation is needed, the CRC engine must be configured before it is enabled, as outlined by the following
steps:
•
•
•
The CRC input source must selected by writing the CRC Input Source bit group in the CRC Control register
(CRCCTRL.CRCSRC)
The type of CRC calculation must be selected by writing the CRC Polynomial Type bit group in the CRC Control
register (CRCCTRL.CRCPOLY)
If I/O is selected as input source, the beat size must be selected by writing the CRC Beat Size bit group in the
CRC Control register (CRCCTRL.CRCBEATSIZE)
24.5.2.2 Enabling, Disabling, and Resetting
The DMAC is enabled by writing the DMA Enable bit in the Control register (CTRL.DMAENABLE) to '1'. The DMAC is
disabled by writing a '0' to CTRL.DMAENABLE.
A DMA channel is enabled by writing the Enable bit in the Channel Control A register (CHCTRLA.ENABLE) to '1',
after writing the corresponding channel id to the Channel ID bit group in the Channel ID register (CHID.ID). A DMA
channel is disabled by writing a '0' to CHCTRLA.ENABLE.
The CRC is enabled by writing a '1' to the CRC Enable bit in the Control register (CTRL.CRCENABLE). The CRC is
disabled by writing a '0' to CTRL.CRCENABLE.
The DMAC is reset by writing a '1' to the Software Reset bit in the Control register (CTRL.SWRST) while the DMAC
and CRC are disabled. All registers in the DMAC except DBGCTRL will be reset to their initial state.
A DMA channel is reset by writing a '1' to the Software Reset bit in the Channel Control A register
(CHCTRLA.SWRST), after writing the corresponding channel id to the Channel ID bit group in the Channel ID
register (CHID.ID). The channel registers will be reset to their initial state. The corresponding DMA channel must be
disabled in order for the reset to take effect.
24.5.2.3 Transfer Descriptors
Together with the channel configurations the transfer descriptors decides how a block transfer should be executed.
Before a DMA channel is enabled (CHCTRLA.ENABLE is written to one), and receives a transfer trigger, its first
transfer descriptor has to be initialized and valid (BTCTRL.VALID). The first transfer descriptor describes the first
block transfer of a transaction.
All transfer descriptors must reside in SRAM. The addresses stored in the Descriptor Memory Section Base Address
(BASEADDR) and Write-Back Memory Section Base Address (WRBADDR) registers tell the DMAC where to find the
descriptor memory section and the write-back memory section.
The descriptor memory section is where the DMAC expects to find the first transfer descriptors for all DMA channels.
As BASEADDR points only to the first transfer descriptor of channel 0 (see figure below), all first transfer descriptors
must be stored in a contiguous memory section, where the transfer descriptors must be ordered according to their
channel number. For further details on linked descriptors, refer to 24.5.3.1 Linked Descriptors.
The write-back memory section is the section where the DMAC stores the transfer descriptors for the ongoing block
transfers. WRBADDR points to the ongoing transfer descriptor of channel 0. All ongoing transfer descriptors will be
stored in a contiguous memory section where the transfer descriptors are ordered according to their channel number.
The figure below shows an example of linked descriptors on DMA channel 0. For further details on linked descriptors,
refer to 24.5.3.1 Linked Descriptors.
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
Figure 24-3. Memory Sections
0x00000000
DSTADDR
DESCADDR
Channel 0 – Last Descriptor
SRCADDR
BTCNT
BTCTRL
DESCADDR
DSTADDR
DESCADDR
Channel 0 – Descriptor n-1
SRCADDR
BTCNT
BTCTRL
Descriptor Section
Channel n – First Descriptor
DESCADDR
BASEADDR
Channel 2 – First Descriptor
Channel 1 – First Descriptor
Channel 0 – First Descriptor
DSTADDR
SRCADDR
BTCNT
BTCTRL
Write-Back Section
Channel n Ongoing Descriptor
WRBADDR
Channel 2 Ongoing Descriptor
Channel 1 Ongoing Descriptor
Channel 0 Ongoing Descriptor
Undefined
Undefined
Undefined
Undefined
Undefined
Device Memory Space
The size of the descriptor and write-back memory sections is dependent on the number of the most significant
enabled DMA channel m, as shown below:
Size = 128bits ⋅ m + 1
For memory optimization, it is recommended to always use the less significant DMA channels if not all channels are
required.
The descriptor and write-back memory sections can either be two separate memory sections, or they can share
memory section (BASEADDR=WRBADDR). The benefit of having them in two separate sections, is that the same
transaction for a channel can be repeated without having to modify the first transfer descriptor. The benefit of having
descriptor memory and write-back memory in the same section is that it requires less SRAM. In addition, the latency
from fetching the first descriptor of a transaction to the first burst transfer is executed, is reduced.
24.5.2.4 Arbitration
If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer request
to the arbiter. When the arbiter receives the transfer request it will include the DMA channel in the queue of
channels having pending transfers, and the corresponding Pending Channel x bit in the Pending Channels registers
(PENDCH.PENDCHx) will be set. Depending on the arbitration scheme, the arbiter will choose which DMA channel
will be the next active channel. The active channel is the DMA channel being granted access to perform its
next burst transfer. When the arbiter has granted a DMA channel access to the DMAC, the corresponding bit
PENDCH.PENDCHx will be cleared. See also the following figure.
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
If the upcoming burst transfer is the first for the transfer request, the corresponding Busy Channel x bit in the
Busy Channels register will be set (BUSYCH.BUSYCHx=1), and it will remain '1' for the subsequent granted burst
transfers.
When the channel has performed its granted burst transfer(s) it will be either fed into the queue of channels with
pending transfers, set to be waiting for a new transfer trigger, suspended, or disabled. This depends on the channel
and block transfer configuration. If the DMA channel is fed into the queue of channels with pending transfers, the
corresponding BUSYCH.BUSYCHx will remain '1'. If the DMA channel is set to wait for a new transfer trigger,
suspended, or disabled, the corresponding BUSYCH.BUSYCHx will be cleared.
If a DMA channel is suspended while it has a pending transfer, it will be removed from the queue of pending
channels, but the corresponding PENDCH.PENDCHx will remain set. When the same DMA channel is resumed, it
will be added to the queue of pending channels again.
If a DMA channel gets disabled (CHCTRLA.ENABLE=0) while it has a pending transfer, it will be removed from the
queue of pending channels, and the corresponding PENDCH.PENDCHx will be cleared.
Figure 24-4. Arbiter Overview
Arbiter
Channel Pending
Priority
decoder
Channel Suspend
Channel 0
Channel Priority Level
Channel Burst Done
Burst Done
Channel Pending
Transfer Request
Channel Number
Channel Suspend
Active
Channel
Channel N
Channel Priority Level
Channel Burst Done
Level Enable
Active.LVLEXx
PRICTRLx.LVLPRI
CTRL.LVLENx
Priority Levels
When a channel level is pending or the channel is transferring data, the corresponding Level Executing bit is set in
the Active Channel and Levels register (ACTIVE.LVLEXx).
Each DMA channel supports a 4-level priority scheme. The priority level for a channel is configured by writing to the
Channel Arbitration Level bit group in the Channel Control B register (CHCTRLB.LVL). As long as all priority levels
are enabled, a channel with a higher priority level number will have priority over a channel with a lower priority level
number. Each priority level x is enabled by setting the corresponding Priority Level x Enable bit in the Control register
(CTRL.LVLENx=1).
Within each priority level the DMAC's arbiter can be configured to prioritize statically or dynamically:
Static Arbitration within a priority level is selected by writing a '0' to the Level x Round-Robin Scheduling Enable bit in
the Priority Control 0 register (PRICTRL0.RRLVLENx).
When static arbitration is selected, the arbiter will prioritize a low channel number over a high channel number as
shown in the figure below. When using the static arbitration there is a risk of high channel numbers never being
granted access as the active channel. This can be avoided using a dynamic arbitration scheme.
© 2021 Microchip Technology Inc.
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
Figure 24-5. Static Priority Scheduling
Lowest Channel
Channel 0
Highest Priority
.
.
.
Channel x
Channel x+1
.
.
.
Highest Channel
Lowest Priority
Channel N
Dynamic Arbitration within a priority level is selected by writing a '1' to PRICTRL0.RRLVLENx.
The dynamic arbitration scheme in the DMAC is round-robin. With the round-robin scheme, the channel number of
the last channel being granted access will have the lowest priority the next time the arbiter has to grant access to
a channel within the same priority level, as shown in Figure 24-6. The channel number of the last channel being
granted access as the active channel is stored in the Level x Channel Priority Number bit group in the Priority Control
0 register (PRICTRL0.LVLPRIx) for the corresponding priority level.
Figure 24-6. Dynamic (Round-Robin) Priority Scheduling
Channel x last acknowledge request
Channel (x+1) last acknowledge request
Channel 0
Channel 0
.
.
.
Channel x
Lowest Priority
Channel x
Channel x+1
Highest Priority
Channel x+1
Lowest Priority
Channel x+2
Highest Priority
.
.
.
Channel N
Channel N
24.5.2.5 Data Transmission
Before the DMAC can perform a data transmission, a DMA channel has to be configured and enabled, its
corresponding transfer descriptor has to be initialized, and the arbiter has to grant the DMA channel access as
the active channel.
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
Once the arbiter has granted a DMA channel access as the active channel (refer to DMA Block Diagram section) the
transfer descriptor for the DMA channel will be fetched from SRAM using the fetch bus, and stored in the internal
memory for the active channel. For a new block transfer, the transfer descriptor will be fetched from the descriptor
memory section (BASEADDR); For an ongoing block transfer, the descriptor will be fetched from the write-back
memory section (WRBADDR). By using the data transfer bus, the DMAC will read the data from the current source
address and write it to the current destination address. For further details on how the current source and destination
addresses are calculated, refer to the section on Addressing.
The arbitration procedure is performed after each burst transfer. If the current DMA channel is granted access again,
the block transfer counter (BTCNT) of the internal transfer descriptor will be decremented by the number of beats in a
burst transfer, the optional output event Beat will be generated if configured and enabled, and the active channel will
perform a new burst transfer. If a different DMA channel than the current active channel is granted access, the block
transfer counter value will be written to the write-back section before the transfer descriptor of the newly granted DMA
channel is fetched into the internal memory of the active channel.
When a block transfer has come to its end (BTCNT is zero), the Valid bit in the Block Transfer Control register will
be cleared (BTCTRL.VALID=0) before the entire transfer descriptor is written to the write-back memory. The optional
interrupts, Channel Transfer Complete and Channel Suspend, and the optional output event Block, will be generated
if configured and enabled. After the last block transfer in a transaction, the Next Descriptor Address register
(DESCADDR) will hold the value 0x00000000, and the DMA channel will either be suspended or disabled, depending
on the configuration in the Block Action bit group in the Block Transfer Control register (BTCTRL.BLOCKACT). If
the transaction has further block transfers pending, DESCADDR will hold the SRAM address to the next transfer
descriptor to be fetched. The DMAC will fetch the next descriptor into the internal memory of the active channel and
write its content to the write-back section for the channel, before the arbiter gets to choose the next active channel.
24.5.2.6 Transfer Triggers and Actions
A DMA transfer through a DMA channel can be started only when a DMA transfer request is detected, and the
DMA channel has been granted access to the DMA. A transfer request can be triggered from software, from a
peripheral, or from an event. There are dedicated Trigger Source selections for each DMA Channel Control B
(CHCTRLB.TRIGSRC).
The trigger actions are available in the Trigger Action bit group in the Channel Control B register
(CHCTRLB.TRIGACT). By default, a trigger generates a request for a block transfer operation. If a single descriptor
is defined for a channel, the channel is automatically disabled when a block transfer has been completed. If a
list of linked descriptors is defined for a channel, the channel is automatically disabled when the last descriptor
in the list is executed. If the list still has descriptors to execute, the channel will be waiting for the next block
transfer trigger. When enabled again, the channel will wait for the next block transfer trigger. The trigger actions
can also be configured to generate a request for a beat transfer (CHCTRLB.TRIGACT=0x2) or transaction transfer
(CHCTRLB.TRIGACT=0x3) instead of a block transfer (CHCTRLB.TRIGACT=0x0).
Figure 24-7 shows an example where triggers are used with two linked block descriptors.
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Figure 24-7. Trigger Action and Transfers
Beat Trigger Action
CHENn
Trigger Lost
Trigger
PENDCHn
BUSYCHn
Block Transfer
Block Transfer
Data Transfer
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
Block Trigger Action
CHENn
Trigger Lost
Trigger
PENDCHn
BUSYCHn
Block Transfer
Block Transfer
Data Transfer
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
Transaction Trigger Action
CHENn
Trigger Lost
Trigger
PENDCHn
BUSYCHn
Block Transfer
Block Transfer
Data Transfer
BEAT
BEAT
If the trigger source generates a transfer request for a channel during an ongoing transfer, the new transfer request
will be kept pending (CHSTATUS.PEND=1), and the new transfer can start after the ongoing one is done. Only one
pending transfer can be kept per channel. If the trigger source generates more transfer requests while one is already
pending, the additional ones will be lost. All channels pending status flags are also available in the Pending Channels
register (PENDCH).
When the transfer starts, the corresponding Channel Busy status flag is set in Channel Status register
(CHSTATUS.BUSY). When the trigger action is complete, the Channel Busy status flag is cleared. All channel busy
status flags are also available in the Busy Channels register (BUSYCH) in DMAC.
24.5.2.7 Addressing
Each block transfer needs to have both a source address and a destination address defined. The source address
is set by writing the Transfer Source Address (SRCADDR) register, the destination address is set by writing the
Transfer Destination Address (SRCADDR) register.
The addressing of this DMAC module can be static or incremental, for either source or destination of a block transfer,
or both.
Incrementation for the source address of a block transfer is enabled by writing the Source Address Incrementation
Enable bit in the Block Transfer Control register (BTCTRL.SRCINC=1). The step size of the incrementation
is configurable and can be chosen by writing the Step Selection bit in the Block Transfer Control register
(BTCTRL.STEPSEL=1) and writing the desired step size in the Address Increment Step Size bit group in the Block
Transfer Control register (BTCTRL.STEPSIZE). If BTCTRL.STEPSEL=0, the step size for the source incrementation
will be the size of one beat.
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When source address incrementation is configured (BTCTRL.SRCINC=1), SRCADDR is calculated as follows:
If BTCTRL.STEPSEL=1:
SRCADDR = SRCADDRSTART + BTCNT ⋅ BEATSIZE + 1 ⋅ 2STEPSIZE
If BTCTRL.STEPSEL=0:
SRCADDR = SRCADDRSTART + BTCNT ⋅ BEATSIZE + 1
•
•
•
•
SRCADDRSTART is the source address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation
The following figure shows an example where DMA channel 0 is configured to increment the source address
by one beat after each beat transfer (BTCTRL.SRCINC=1), and DMA channel 1 is configured to increment the
source address by two beats (BTCTRL.SRCINC=1, BTCTRL.STEPSEL=1, and BTCTRL.STEPSIZE=0x1). As the
destination address for both channels are peripherals, destination incrementation is disabled (BTCTRL.DSTINC=0).
Figure 24-8. Source Address Increment
SRC Data Buffer
a
b
c
d
e
f
Incrementation for the destination address of a block transfer is enabled by setting the Destination Address
Incrementation Enable bit in the Block Transfer Control register (BTCTRL.DSTINC=1). The step size of the
incrementation is configurable by clearing BTCTRL.STEPSEL=0 and writing BTCTRL.STEPSIZE to the desired step
size. If BTCTRL.STEPSEL=1, the step size for the destination incrementation will be the size of one beat.
When the destination address incrementation is configured (BTCTRL.DSTINC=1), DSTADDR must be set and
calculated as follows:
DSTADDR = DSTADDRSTART + BTCNT • BEATSIZE + 1 • 2STEPSIZE
DSTADDR = DSTADDRSTART + BTCNT • BEATSIZE + 1
•
•
•
•
where BTCTRL.STEPSEL is zero
where BTCTRL.STEPSEL is one
DSTADDRSTART is the destination address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation
The followiong figure shows an example where DMA channel 0 is configured to increment destination address
by one beat (BTCTRL.DSTINC=1) and DMA channel 1 is configured to increment destination address by two
beats (BTCTRL.DSTINC=1, BTCTRL.STEPSEL=0, and BTCTRL.STEPSIZE=0x1). As the source address for both
channels are peripherals, source incrementation is disabled (BTCTRL.SRCINC=0).
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Figure 24-9. Destination Address Increment
DST Data Buffer
a
b
c
d
24.5.2.8 Error Handling
If a bus error is received from an AHB client during a DMA data transfer, the corresponding active channel is disabled
and the corresponding Channel Transfer Error Interrupt flag in the Channel Interrupt Status and Clear register
(CHINTFLAG.TERR) is set. If enabled, the optional transfer error interrupt is generated. The transfer counter will not
be decremented and its current value is written-back in the write-back memory section before the channel is disabled.
When the DMAC fetches an invalid descriptor (BTCTRL.VALID=0) or when the channel is resumed and the DMA
fetches the next descriptor with null address (DESCADDR=0x00000000), the corresponding channel operation
is suspended, the Channel Suspend Interrupt Flag in the Channel Interrupt Flag Status and Clear register
(CHINTFLAG.SUSP) is set, and the Channel Fetch Error bit in the Channel Status register (CHSTATUS.FERR)
is set. If enabled, the optional suspend interrupt is generated.
24.5.3
Additional Features
24.5.3.1 Linked Descriptors
A transaction can consist of either a single block transfer or of several block transfers. When a transaction consists of
several block transfers it is done with the help of linked descriptors.
Figure 24-3 illustrates how linked descriptors work. When the first block transfer is completed on DMA channel
0, the DMAC fetches the next transfer descriptor, which is pointed to by the value stored in the Next Descriptor
Address (DESCADDR) register of the first transfer descriptor. Fetching the next transfer descriptor (DESCADDR) is
continued until the last transfer descriptor. When the block transfer for the last transfer descriptor is executed and
DESCADDR=0x00000000, the transaction is terminated. For further details on how the next descriptor is fetched
from SRAM, refer to section 24.5.2.5 Data Transmission.
24.5.3.1.1 Adding Descriptor to the End of a List
To add a new descriptor at the end of the descriptor list, create the descriptor in SRAM, with
DESCADDR=0x00000000 indicating that it is the new last descriptor in the list, and modify the DESCADDR value of
the current last descriptor to the address of the newly created descriptor.
24.5.3.1.2 Modifying a Descriptor in a List
In order to add descriptors to a linked list, the following actions must be performed:
1.
2.
3.
4.
Enable the Suspend interrupt for the DMA channel.
Enable the DMA channel.
Reserve memory space in SRAM to configure a new descriptor.
Configure the new descriptor:
– Set the next descriptor address (DESCADDR)
– Set the destination address (DSTADDR)
– Set the source address (SRCADDR)
– Configure the block transfer control (BTCTRL) including
• Optionally enable the Suspend block action
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5.
6.
7.
• Set the descriptor VALID bit
Clear the VALID bit for the existing list and for the descriptor which has to be updated.
Read DESCADDR from the Write-Back memory.
– If the DMA has not already fetched the descriptor which requires changes (i.e., DESCADDR is wrong):
• Update the DESCADDR location of the descriptor from the List
• Optionally clear the Suspend block action
• Set the descriptor VALID bit to '1'
• Optionally enable the Resume software command
– If the DMA is executing the same descriptor as the one which requires changes:
• Set the Channel Suspend software command and wait for the Suspend interrupt
• Update the next descriptor address (DESCRADDR) in the write-back memory
• Clear the interrupt sources and set the Resume software command
• Update the DESCADDR location of the descriptor from the List
• Optionally clear the Suspend block action
• Set the descriptor VALID bit to '1'
Go to step 4 if needed.
24.5.3.1.3 Adding a Descriptor Between Existing Descriptors
To insert a new descriptor 'C' between two existing descriptors ('A' and 'B'), the descriptor currently executed by the
DMA must be identified.
1.
2.
3.
If DMA is executing descriptor B, descriptor C cannot be inserted.
If DMA has not started to execute descriptor A, follow the steps:
2.1.
Set the descriptor A VALID bit to '0'.
2.2.
Set the DESCADDR value of descriptor A to point to descriptor C instead of descriptor B.
2.3.
Set the DESCADDR value of descriptor C to point to descriptor B.
2.4.
Set the descriptor A VALID bit to '1'.
If DMA is executing descriptor A:
3.1.
Apply the software suspend command to the channel and
3.2.
Perform steps 2.1 through 2.4.
3.3.
Apply the software resume command to the channel.
24.5.3.2 Channel Suspend
The channel operation can be suspended at any time by software by writing a '1' to the Suspend command in the
Command bit field of Channel Control B register (CHCTRLB.CMD). After the ongoing burst transfer is completed, the
channel operation is suspended and the suspend command is automatically cleared.
When suspended, the Channel Suspend Interrupt flag in the Channel Interrupt Status and Clear register is set
(CHINTFLAG.SUSP=1) and the optional suspend interrupt is generated.
By configuring the block action to suspend by writing Block Action bit group in the Block Transfer Control register
(BTCTRL.BLOCKACT is 0x2 or 0x3), the DMA channel will be suspended after it has completed a block transfer.
The DMA channel will be kept enabled and will be able to receive transfer triggers, but it will be removed from the
arbitration scheme.
If an invalid transfer descriptor (BTCTRL.VALID=0) is fetched from SRAM, the DMA channel will be suspended, and
the Channel Fetch Error bit in the Channel Status register(CHASTATUS.FERR) will be set.
Note: Only enabled DMA channels can be suspended. If a channel is disabled when it is attempted to be
suspended, the internal suspend command will be ignored.
For more details on transfer descriptors, refer to section 24.5.2.3 Transfer Descriptors.
24.5.3.3 Channel Resume and Next Suspend Skip
A channel operation can be resumed by software by setting the Resume command in the Command bit field
of the Channel Control B register (CHCTRLB.CMD). If the channel is already suspended, the channel operation
resumes from where it previously stopped when the Resume command is detected. When the Resume command is
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issued before the channel is suspended, the next suspend action is skipped and the channel continues the normal
operation.
Figure 24-10. Channel Suspend/Resume Operation
CHENn
Memory Descriptor
Fetch
Transfer
Descriptor 2
(suspend enabled)
Descriptor 1
(suspend enabled)
Descriptor 0
(suspend disabled)
Block
Transfer 1
Block
Transfer 0
Channel
suspended
Descriptor 3
(last)
Block
Transfer 3
Block
Transfer 2
Resume Command
Suspend skipped
24.5.3.4 Event Input Actions
The event input actions are available only on the least significant DMA channels. For details on channels with event
input support, refer to the in the Event system documentation.
Before using event input actions, the event controller must be configured first according to the following table, and the
Channel Event Input Enable bit in the Channel Control B register (CHCTRLB.EVIE) must be written to '1'. Refer also
to 24.5.5 Events.
Table 24-1. Event Input Action
Action
CHCTRLB.EVACT
CHCTRLB.TRIGSRC
None
NOACT
-
Normal Transfer
TRIG
DISABLE
Conditional Transfer on Strobe
TRIG
any peripheral
Conditional Transfer
CTRIG
Conditional Block Transfer
CBLOCK
Channel Suspend
SUSPEND
Channel Resume
RESUME
Skip Next Block Suspend
SSKIP
Normal Transfer
The event input is used to trigger a beat or burst transfer on peripherals.
The event is acknowledged as soon as the event is received. When received, both the Channel Pending status bit
in the Channel Status register (CHSTATUS.PEND) and the corresponding Channel n bit in the Pending Channels
register (24.6.13 PENDCH.PENDCHn) are set. If the event is received while the channel is pending, the event
trigger is lost.
The figure below shows an example where beat transfers are enabled by internal events.
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Figure 24-11. Beat Event Trigger Action
CHENn
Peripheral Trigger
Trigger Lost
Event
PENDCHn
BUSYCHn
Block Transfer
Data Transfer
BEAT
Block Transfer
BEAT
BEAT
BEAT
BEAT
BEAT
Conditional Transfer on Strobe
The event input is used to trigger a transfer on peripherals with pending transfer requests. This event action is
intended to be used with peripheral triggers, e.g. for timed communication protocols or periodic transfers between
peripherals: only when the peripheral trigger coincides with the occurrence of a (possibly cyclic) event the transfer is
issued.
The event is acknowledged as soon as the event is received. The peripheral trigger request is stored internally when
the previous trigger action is completed (i.e. the channel is not pending) and when an active event is received. If the
peripheral trigger is active, the DMA will wait for an event before the peripheral trigger is internally registered. When
both event and peripheral transfer trigger are active, both CHSTATUS.PEND and 24.6.13 PENDCH.PENDCHn are
set. A software trigger will now trigger a transfer.
The figure below shows an example where the peripheral beat transfer is started by a conditional strobe event action.
Figure 24-12. Periodic Event with Beat Peripheral Triggers
Trigger Lost
Trigger Lost
Event
Peripheral Trigger
PENDCHn
Block Transfer
Data Transfer
BEAT
Conditional Transfer
The event input is used to trigger a conditional transfer on peripherals with pending transfer requests. For example,
this type of event can be used for peripheral-to-peripheral transfers, where one peripheral is the source of event and
the second peripheral is the source of the trigger.
Each peripheral trigger is stored internally when the event is received. When the peripheral trigger is stored internally,
the Channel Pending status bit is set (CHSTATUS.PEND), the respective Pending Channel n Bit in the Pending
Channels register is set (24.6.13 PENDCH.PENDCHn), and the event is acknowledged. A software trigger will now
trigger a transfer.
The figure below shows an example where conditional event is enabled with peripheral beat trigger requests.
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Figure 24-13. Conditional Event with Beat Peripheral Triggers
Event
Peripheral Trigger
PENDCHn
Data Transfer
Block Transfer
BEAT
BEAT
Conditional Block Transfer
The event input is used to trigger a conditional block transfer on peripherals.
Before starting transfers within a block, an event must be received. When received, the event is acknowledged when
the block transfer is completed. A software trigger will trigger a transfer.
The figure below shows an example where conditional event block transfer is started with peripheral beat trigger
requests.
Figure 24-14. Conditional Block Transfer with Beat Peripheral Triggers
Event
Peripheral Trigger
PENDCHn
Block Transfer
Data Transfer
Block Transfer
BEAT
BEAT
BEAT
BEAT
Channel Suspend
The event input is used to suspend an ongoing channel operation. The event is acknowledged when the current AHB
access is completed. For further details on Channel Suspend, refer to 24.5.3.2 Channel Suspend.
Channel Resume
The event input is used to resume a suspended channel operation. The event is acknowledged as soon as the
event is received and the Channel Suspend Interrupt Flag (CHINTFLAG.SUSP) is cleared. For further details refer to
24.5.3.2 Channel Suspend.
Skip Next Block Suspend
This event can be used to skip the next block suspend action. If the channel is suspended before the event rises,
the channel operation is resumed and the event is acknowledged. If the event rises before a suspend block action is
detected, the event is kept until the next block suspend detection. When the block transfer is completed, the channel
continues the operation (not suspended) and the event is acknowledged.
24.5.3.5 Event Output Selection
Event output selection is available only for the least significant DMA channels. The pulse width of an event output
from a channel is one AHB clock cycle.
The output of channel events is enabled by writing a '1' to the Channel Event Output Enable bit in the Control
B register (CHCTRLB.EVOE). The event output cause is selected by writing to the Event Output Selection bits in
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the Block Transfer Control register (BTCTRL.EVOSEL). It is possible to generate events after each block transfer
(BTCTRL.EVOSEL=0x1) or beat transfer (BTCTRL.EVOSEL=0x3). To enable an event being generated when a
transaction is complete, the block event selection must be set in the last transfer descriptor only.
Figure 24-15 shows an example where the event output generation is enabled in the first block transfer, and disabled
in the second block.
Figure 24-15. Event Output Generation
Beat Event Output
Block Transfer
Data Transfer
Block Transfer
BEAT
BEAT
BEAT
BEAT
Event Output
Block Event Output
Block Transfer
Data Transfer
BEAT
Block Transfer
BEAT
BEAT
BEAT
Event Output
24.5.3.6 Aborting Transfers
Transfers on any channel can be aborted gracefully by software by disabling the corresponding DMA channel. It is
also possible to abort all ongoing or pending transfers by disabling the DMAC.
When a DMA channel disable request or DMAC disable request is detected:
•
•
Ongoing transfers of the active channel will be disabled when the ongoing beat transfer is completed and the
write-back memory section is updated. This prevents transfer corruption before the channel is disabled.
All other enabled channels will be disabled in the next clock cycle.
The corresponding Channel Enable bit in the Channel Control A register is cleared (CHCTRLA.ENABLE=0) when the
channel is disabled.
The corresponding DMAC Enable bit in the Control register is cleared (CTRL.DMAENABLE=0) when the entire
DMAC module is disabled.
24.5.3.7 CRC Operation
A cyclic redundancy check (CRC) is an error detection technique used to find errors in data. It is commonly used
to determine whether the data during a transmission, or data present in data and program memories has been
corrupted or not. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can
be appended to the data and used as a checksum.
When the data is received, the device or application repeats the calculation: If the new CRC result does not match
the one calculated earlier, the block contains a data error. The application will then detect this and may take a
corrective action, such as requesting the data to be sent again or simply not using the incorrect data.
The CRC engine in DMAC supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32
(IEEE 802.3). Typically, applying CRC-n (CRC-16 or CRC-32) to a data block of arbitrary length will detect any single
alteration that is ≤n bits in length, and will detect the fraction 1-2-n of all longer error bursts.
•
CRC-16:
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•
– Polynomial: x16+ x12+ x5+ 1
– Hex value: 0x1021
CRC-32:
– Polynomial: x32+x26+ x23+ x22+x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x + 1
– Hex value: 0x04C11DB7
The data source for the CRC engine can either be one of the DMA channels or the APB bus interface, and must be
selected by writing to the CRC Input Source bits in the CRC Control register (CRCCTRL.CRCSRC). The CRC engine
then takes data input from the selected source and generates a checksum based on these data. The checksum is
available in the CRC Checksum register (CRCCHKSUM). When CRC-32 polynomial is used, the final checksum read
is bit reversed and complemented, as shown in Figure 24-16.
The CRC polynomial is selected by writing to the CRC Polynomial Type bit in the CRC Control register
(CRCCTRL.CRCPOLY), the default is CRC-16. The CRC engine operates on byte only. When the DMA is used as
data source for the CRC engine, the DMA channel beat size setting will be used. When used with APB bus interface,
the application must select the CRC Beat Size bit field of CRC Control register (CRCCTRL.CRCBEATSIZE). 8-, 16-,
or 32-bit bus transfer access type is supported. The corresponding number of bytes will be written in the CRCDATAIN
register and the CRC engine will operate on the input data in a byte by byte manner.
Figure 24-16. CRC Generator Block Diagram
DMAC
Channels
CRCDATAIN
CRCCTRL
8
16
8
CRC-16
32
CRC-32
crc32
CHECKSUM
bit-reverse +
complement
Checksum
read
CRC on
DMA
data
CRC-16 or CRC-32 calculations can be performed on data passing through any DMA channel. Once a
DMA channel is selected as the source, the CRC engine will continuously generate the CRC on the data
passing through the DMA channel. The checksum is available for readout once the DMA transaction is
completed or aborted. A CRC can also be generated on SRAM, Flash, or I/O memory by passing these
data through a DMA channel. If the latter is done, the destination register for the DMA data can be the
data input (CRCDATAIN) register in the CRC engine.
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CRC using the I/O
interface
Before using the CRC engine with the I/O interface, the application must set the CRC Beat
Size bits in the CRC Control register (CRCCTRL.CRCBEATSIZE). 8/16/32-bit bus transfer
type can be selected.
CRC can be performed on any data by loading them into the CRC engine using the CPU and writing the data to
the CRCDATAIN register. Using this method, an arbitrary number of bytes can be written to the register by the CPU,
and CRC is done continuously for each byte. This means if a 32-bit data is written to the CRCDATAIN register the
CRC engine takes four cycles to calculate the CRC. The CRC complete is signaled by a set CRCBUSY bit in the
CRCSTATUS register. New data can be written only when CRCBUSY flag is not set.
24.5.4
Interrupts
The DMAC channels have the following interrupt sources:
•
•
•
Transfer Complete (TCMPL): Indicates that a block transfer is completed on the corresponding channel. Refer to
24.5.2.5 Data Transmission for details.
Transfer Error (TERR): Indicates that a bus error has occurred during a burst transfer, or that an invalid
descriptor has been fetched. Refer to 24.5.2.8 Error Handling for details.
Channel Suspend (SUSP): Indicates that the corresponding channel has been suspended. Refer to
24.5.3.2 Channel Suspend and 24.5.2.5 Data Transmission for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Channel Interrupt Flag Status
and Clear (CHINTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually
enabled by setting the corresponding bit in the Channel Interrupt Enable Set register (CHINTENSET=1), and
disabled by setting the corresponding bit in the Channel Interrupt Enable Clear register (CHINTENCLR=1).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, the DMAC is reset or
the corresponding DMA channel is reset. See CHINTFLAG for details on how to clear interrupt flags. All interrupt
requests are ORed together on system level to generate one combined interrupt request to the NVIC.
The user must read the Channel Interrupt Status (INTSTATUS) register to identify the channels with pending
interrupts and must read the Channel Interrupt Flag Status and Clear (CHINTFLAG) register to determine which
interrupt condition is present for the corresponding channel. It is also possible to read the Interrupt Pending register
(INTPEND), which provides the lowest channel number with pending interrupt and the respective interrupt flags.
Note: Interrupts must be globally enabled for interrupt requests to be generated.
24.5.5
Events
The DMAC can generate the following output events:
•
Channel (CH): Generated when a block transfer for a given channel has been completed, or when a beat
transfer within a block transfer for a given channel has been completed. Refer to 28. Event System (EVSYS) for
details.
Setting the Channel Event Output Enable bit (CHEVCTRLx.EVOE = 1) enables the corresponding output event
configured in the Event Output Selection bit group in the Block Transfer Control register (BTCTRL.EVOSEL).
Clearing CHEVCTRLx.EVOE = 0 disables the corresponding output event.
The DMAC can take the following actions on an input event:
•
•
•
•
•
•
•
Transfer and Periodic Transfer Trigger (TRIG): normal transfer or periodic transfers on peripherals are enabled
Conditional Transfer Trigger (CTRIG): conditional transfers on peripherals are enabled
Conditional Block Transfer Trigger (CBLOCK): conditional block transfers on peripherals are enabled
Channel Suspend Operation (SUSPEND): suspend a channel operation
Channel Resume Operation (RESUME): resume a suspended channel operation
Skip Next Block Suspend Action (SSKIP): skip the next block suspend transfer condition
Increase Priority (INCPRI): increase channel priority
Setting the Channel Event Input Enable bit (CHEVCTRLx.EVIE = 1) enables the corresponding action on input event.
Clearing this bit disables the corresponding action on input event. Note that several actions can be enabled for
incoming events. If several events are connected to the peripheral, any enabled action will be taken for any of the
incoming events. For further details on event input actions, refer to Event Input Actions.
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Note: Event input and outputs are not available for every channel. Refer to the Features section for more
information.
24.5.6
Sleep Mode Operation
Each DMA channel can be configured to operate in any sleep mode. To be able to run in standby, the RUNSTDBY
bit in Channel Control A register (CHCTRLA.RUNSTDBY) must be written to '1'. The DMAC can wake up the device
using interrupts from any sleep mode or perform actions through the Event System.
For channels with CHCTRLA.RUNSTDBY = 0, it is up to software to stop DMA transfers on these channels and wait
for completion before going to Standby mode using the following sequence:
1.
2.
3.
4.
Suspend the DMAC channels for which CHCTRLA.RUNSTDBY = 0.
Check the SYNCBUSY bits of registers accessed by the DMAC channels being suspended.
Go to sleep.
When the device wakes up, resume the suspended channels.
Notes:
1. In Standby Sleep mode, the DMAC can only access RAM when it is not back biased
(PM.STDBYCFG.BBIASxx = 0x0).
2. When the device is in Standby Sleep mode, the DMAC cannot write the following peripheral registers. To write
these registers with the DMAC the device must be in active or idle modes.
ADC: SWTRIG
RTC: COUNT
TC: CTRLB, STATUS, COUNTH, COUNTL, PER, PERBUF, CC, CCBUF
TCC: CTRLB, STATUS, COUNT, PATT, WAVE, PER, PERBUF, CC, CCBUF
SDADC: SWTRIG
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 301
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6
Register Summary
Offset
Name
0x00
CTRL
0x02
CRCCTRL
0x04
CRCDATAIN
0x08
CRCCHKSUM
0x0C
0x0D
0x0E
0x0F
CRCSTATUS
DBGCTRL
QOSCTRL
Reserved
0x10
SWTRIGCTRL
0x14
PRICTRL0
0x18
...
0x1F
Reserved
0x20
INTPEND
0x22
...
0x23
Reserved
0x24
INTSTATUS
0x28
BUSYCH
0x2C
PENDCH
0x30
ACTIVE
0x34
BASEADDR
0x38
WRBADDR
Bit Pos.
7
7:0
15:8
7:0
15:8
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
7:0
7:0
5
4
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
RRLVLEN0
RRLVLEN1
RRLVLEN2
RRLVLEN3
7:0
15:8
PEND
BUSY
FERR
CHINT7
CHINT6
CHINT5
CHINT4
BUSYCH7
BUSYCH6
BUSYCH5
PENDCH7
PENDCH6
PENDCH5
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
3
2
1
0
CRCENABLE DMAENABLE
SWRST
LVLEN3
LVLEN2
LVLEN1
LVLEN0
CRCPOLY[1:0]
CRCBEATSIZE[1:0]
CRCSRC[5:0]
CRCDATAIN[7:0]
CRCDATAIN[15:8]
CRCDATAIN[23:16]
CRCDATAIN[31:24]
CRCCHKSUM[7:0]
CRCCHKSUM[15:8]
CRCCHKSUM[23:16]
CRCCHKSUM[31:24]
CRCZERO
CRCBUSY
DBGRUN
DQOS[1:0]
FQOS[1:0]
WRBQOS[1:0]
SWTRIG7
SWTRIG6
SWTRIG5
SWTRIG4
SWTRIG3
SWTRIG11
SWTRIG2
SWTRIG10
SWTRIG1
SWTRIG9
SWTRIG0
SWTRIG8
LVLPRI0[3:0]
LVLPRI1[3:0]
LVLPRI2[3:0]
LVLPRI3[3:0]
ID[3:0]
SUSP
TCMPL
TERR
CHINT3
CHINT11
CHINT2
CHINT10
CHINT1
CHINT9
CHINT0
CHINT8
BUSYCH4
BUSYCH3
BUSYCH11
BUSYCH2
BUSYCH10
BUSYCH1
BUSYCH9
BUSYCH0
BUSYCH8
PENDCH4
PENDCH3
PENDCH11
PENDCH2
PENDCH10
PENDCH1
PENDCH9
PENDCH0
PENDCH8
LVLEX3
LVLEX2
ID[4:0]
LVLEX1
LVLEX0
ABUSY
© 2021 Microchip Technology Inc.
and its subsidiaries
6
BTCNT[7:0]
BTCNT[15:8]
BASEADDR[7:0]
BASEADDR[15:8]
BASEADDR[23:16]
BASEADDR[31:24]
WRBADDR[7:0]
WRBADDR[15:8]
WRBADDR[23:16]
WRBADDR[31:24]
Datasheet
DS60001638D-page 302
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
...........continued
Offset
0x3C
...
0x3E
0x3F
0x40
0x41
...
0x43
0x44
0x48
...
0x4B
0x4C
0x4D
0x4E
0x4F
Name
Bit Pos.
7
6
5
4
3
2
1
0
Reserved
CHID
CHCTRLA
7:0
7:0
ID[3:0]
ENABLE
RUNSTDBY
SWRST
Reserved
CHCTRLB
7:0
15:8
23:16
31:24
LVL[1:0]
EVOE
EVIE
TRIGSRC[5:0]
EVACT[2:0]
TRIGACT[1:0]
CMD[1:0]
Reserved
CHINTENCLR
CHINTENSET
CHINTFLAG
CHSTATUS
7:0
7:0
7:0
7:0
© 2021 Microchip Technology Inc.
and its subsidiaries
SUSP
SUSP
SUSP
FERR
Datasheet
TCMPL
TCMPL
TCMPL
BUSY
TERR
TERR
TERR
PEND
DS60001638D-page 303
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.1
Control
Name:
Offset:
Reset:
Property:
Bit
CTRL
0x00
0x00X0
PAC Write-Protection, Enable-Protected Bits
15
14
13
12
11
LVLEN3
R/W
0
10
LVLEN2
R/W
0
9
LVLEN1
R/W
0
8
LVLEN0
R/W
0
7
6
5
4
3
2
CRCENABLE
R/W
0
1
DMAENABLE
R/W
0
0
SWRST
R/W
0
Access
Reset
Bit
Access
Reset
Bits 8, 9, 10, 11 – LVLENx Priority Level x Enable [x = 3..0]
When this bit is set, all requests with the corresponding level will be fed into the arbiter block. When cleared, all
requests with the corresponding level will be ignored.
For details on arbitration schemes, refer to the Arbitration section.
Note: This bit is not enable-protected.
Value
0
1
Description
Transfer requests for Priority level x will not be handled.
Transfer requests for Priority level x will be handled.
Bit 2 – CRCENABLE CRC Enable
Writing a '0' to this bit will disable the CRC calculation when the CRC Status Busy flag is cleared (CRCSTATUS.
CRCBUSY). The bit is zero when the CRC is disabled.
Writing a '1' to this bit will enable the CRC calculation.
Note: This bit is not enable-protected.
Value
0
1
Description
The CRC calculation is disabled.
The CRC calculation is enabled.
Bit 1 – DMAENABLE DMA Enable
Setting this bit will enable the DMA module.
Writing a '0' to this bit will disable the DMA module. When writing a '0' during an ongoing transfer, the bit will not
be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer
buffer will be empty once the ongoing burst transfer is completed.
Note: This bit is not enable-protected.
Value
0
1
Description
The peripheral is disabled.
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit when both the DMAC and the CRC module are disabled (DMAENABLE and CRCENABLE are
'0') resets all registers in the DMAC (except DBGCTRL) to their initial state. If either the DMAC or CRC module is
enabled, the Reset request will be ignored and the DMAC will return an access error.
Value
Description
0
There is no Reset operation ongoing.
1
A Reset operation is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 304
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.2
CRC Control
Name:
Offset:
Reset:
Property:
Bit
CRCCTRL
0x02
0x0000
PAC Write-Protection, Enable-Protected
15
14
Access
Reset
Bit
7
6
Access
Reset
13
12
R/W
0
R/W
0
5
4
11
10
CRCSRC[5:0]
R/W
R/W
0
0
3
2
CRCPOLY[1:0]
R/W
R/W
0
0
9
8
R/W
0
R/W
0
1
0
CRCBEATSIZE[1:0]
R/W
R/W
0
0
Bits 13:8 – CRCSRC[5:0] CRC Input Source
These bits select the input source for generating the CRC, as shown in the table below. The selected source is
locked until either the CRC generation is completed or the CRC module is disabled. This means the CRCSRC cannot
be modified when the CRC operation is ongoing. The lock is signaled by the CRCBUSY status bit. CRC generation
complete is generated and signaled from the selected source when used with the DMA channel.
Value
Name
Description
0x00
NOACT
No action
0x01
IO
I/O interface
0x02-0x1 Reserved
F
0x20
CHN0
DMA channel 0
0x21
CHN1
DMA channel 1
0x22
CHN2
DMA channel 2
0x23
CHN3
DMA channel 3
0x24
CHN4
DMA channel 4
0x25
CHN5
DMA channel 5
0x26
CHN6
DMA channel 6
0x27
CHN7
DMA channel 7
0x28
CHN8
DMA channel 8
0x29
CHN9
DMA channel 9
0x2A
CHN10
DMA channel 10
0x2B
CHN11
DMA channel 11
Bits 3:2 – CRCPOLY[1:0] CRC Polynomial Type
These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface, as
shown in the table below.
Value
Name
Description
0x0
CRC16
CRC-16 (CRC-CCITT)
0x1
CRC32
CRC32 (IEEE 802.3)
0x2-0x3
Reserved
Bits 1:0 – CRCBEATSIZE[1:0] CRC Beat Size
These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface.
Value
Name
Description
0x0
BYTE
8-bit bus transfer
0x1
HWORD
16-bit bus transfer
0x2
WORD
32-bit bus transfer
0x3
Reserved
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 305
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.3
CRC Data Input
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
CRCDATAIN
0x04
0x00000000
PAC Write-Protection
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
CRCDATAIN[31:24]
R/W
R/W
0
0
20
19
CRCDATAIN[23:16]
R/W
R/W
0
0
12
11
CRCDATAIN[15:8]
R/W
R/W
0
0
4
3
CRCDATAIN[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – CRCDATAIN[31:0] CRC Data Input
These bits store the data for which the CRC checksum is computed. A new CRC Checksum is ready (CRCBEAT+ 1)
clock cycles after the CRCDATAIN register is written.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 306
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.4
CRC Checksum
Name:
Offset:
Reset:
Property:
CRCCHKSUM
0x08
0x00000000
PAC Write-Protection, Enable-Protected
The CRCCHKSUM represents the 16- or 32-bit checksum value and the generated CRC. The register is reset to zero
by default, but it is possible to reset all bits to one by writing the CRCCHKSUM register directly. It is possible to write
this register only when the CRC module is disabled. If CRC-32 is selected and the CRC Status Busy flag is cleared
(i.e., CRC generation is completed or aborted), the bit reversed (bit 31 is swapped with bit 0, bit 30 with bit 1, etc.)
and complemented result will be read from CRCCHKSUM. If CRC-16 is selected or the CRC Status Busy flag is set
(i.e., CRC generation is ongoing), CRCCHKSUM will contain the actual content.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
CRCCHKSUM[31:24]
R/W
R/W
0
0
20
19
CRCCHKSUM[23:16]
R/W
R/W
0
0
12
11
CRCCHKSUM[15:8]
R/W
R/W
0
0
4
3
CRCCHKSUM[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – CRCCHKSUM[31:0] CRC Checksum
These bits store the generated CRC result. The 16 MSB bits are always read zero when CRC-16 is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 307
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.5
CRC Status
Name:
Offset:
Reset:
Property:
Bit
CRCSTATUS
0x0C
0x00
PAC Write-Protection
7
6
5
4
3
Access
Reset
2
1
CRCZERO
R
0
0
CRCBUSY
R/W
0
Bit 1 – CRCZERO CRC Zero
This bit is cleared when a new CRC source is selected.
This bit is set when the CRC generation is complete and the CRC Checksum is zero.
When running CRC-32 and appending the checksum at the end of the packet (as little endian), the final checksum
should be 0x2144df1c, and not zero. However, if the checksum is complemented before it is appended (as little
endian) to the data, the final result in the checksum register will be zero. See the description of CRCCHKSUM to read
out different versions of the checksum.
Bit 0 – CRCBUSY CRC Module Busy
This flag is cleared by writing a one to it when used with I/O interface. When used with a DMA channel, the bit is
set when the corresponding DMA channel is enabled, and cleared when the corresponding DMA channel is disabled.
This register bit cannot be cleared by the application when the CRC is used with a DMA channel.
This bit is set when a source configuration is selected and as long as the source is using the CRC module.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 308
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.6
Debug Control
Name:
Offset:
Reset:
Property:
Bit
DBGCTRL
0x0D
0x00
PAC Write-Protection
7
6
5
4
3
2
1
0
DBGRUN
R/W
0
Access
Reset
Bit 0 – DBGRUN Debug Run
This bit is reset by a software reset.
This bit controls the functionality when the CPU is halted by an external debugger.
Value
Description
0
The DMAC is halted when the CPU is halted by an external debugger.
1
The DMAC continues normal operation when the CPU is halted by an external debugger.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 309
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.7
Quality of Service Control
Name:
Offset:
Reset:
Property:
Bit
QOSCTRL
0x0E
0x2A
PAC Write-Protection
7
6
5
4
3
DQOS[1:0]
Access
Reset
R/W
1
2
FQOS[1:0]
R/W
0
R/W
1
R/W
0
1
0
WRBQOS[1:0]
R/W
R/W
1
0
Bits 5:4 – DQOS[1:0] Data Transfer Quality of Service
These bits define the memory priority access during the data transfer operation.
DQOS[1:0]
Name
Description
0x0
0x1
0x2
0x3
DISABLE
LOW
MEDIUM
HIGH
Background (no sensitive operation)
Sensitive Bandwidth
Sensitive Latency
Critical Latency
Bits 3:2 – FQOS[1:0] Fetch Quality of Service
These bits define the memory priority access during the fetch operation.
FQOS[1:0]
Name
Description
0x0
0x1
0x2
0x3
DISABLE
LOW
MEDIUM
HIGH
Background (no sensitive operation)
Sensitive Bandwidth
Sensitive Latency
Critical Latency
Bits 1:0 – WRBQOS[1:0] Write-Back Quality of Service
These bits define the memory priority access during the write-back operation.
WRBQOS[1:0]
Name
Description
0x0
0x1
0x2
0x3
DISABLE
LOW
MEDIUM
HIGH
Background (no sensitive operation)
Sensitive Bandwidth
Sensitive Latency
Critical Latency
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 310
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.8
Software Trigger Control
Name:
Offset:
Reset:
Property:
Bit
SWTRIGCTRL
0x10
0x00000000
PAC Write-Protection
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
SWTRIG11
R/W
0
10
SWTRIG10
R/W
0
9
SWTRIG9
R/W
0
8
SWTRIG8
R/W
0
7
SWTRIG7
R/W
0
6
SWTRIG6
R/W
0
5
SWTRIG5
R/W
0
4
SWTRIG4
R/W
0
3
SWTRIG3
R/W
0
2
SWTRIG2
R/W
0
1
SWTRIG1
R/W
0
0
SWTRIG0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – SWTRIGx Channel x Software Trigger [x = 11..0]
This bit is cleared when the Channel Pending bit in the Channel Status register (CHSTATUS.PEND) for the
corresponding channel is either set, or by writing a '1' to it.
This bit is set if CHSTATUS.PEND is already '1' when writing a '1' to that bit.
Writing a '0' to this bit will clear the bit.
Writing a '1' to this bit will generate a DMA software trigger on channel x, if CHSTATUS.PEND=0 for channel x.
CHSTATUS.PEND will be set and SWTRIGx will remain cleared.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 311
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.9
Priority Control 0
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PRICTRL0
0x14
0x00000000
PAC Write-Protection
31
RRLVLEN3
R/W
0
30
23
RRLVLEN2
R/W
0
22
15
RRLVLEN1
R/W
0
14
7
RRLVLEN0
R/W
0
6
29
28
27
R/W
0
21
20
19
R/W
0
13
12
11
R/W
0
5
4
3
R/W
0
26
25
LVLPRI3[3:0]
R/W
R/W
0
0
18
17
LVLPRI2[3:0]
R/W
R/W
0
0
10
9
LVLPRI1[3:0]
R/W
R/W
0
0
2
1
LVLPRI0[3:0]
R/W
R/W
0
0
24
R/W
0
16
R/W
0
8
R/W
0
0
R/W
0
Bit 31 – RRLVLEN3 Level 3 Round-Robin Arbitration Enable
This bit controls which arbitration scheme is selected for DMA channels with priority level 3. For details on arbitration
schemes, refer to 24.5.2.4 Arbitration.
Value
Description
0
Static arbitration scheme for channels with level 3 priority.
1
Round-robin arbitration scheme for channels with level 3 priority.
Bits 27:24 – LVLPRI3[3:0] Level 3 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN3=1) for priority level 3, this register holds the channel
number of the last DMA channel being granted access as the active channel with priority level 3.
When static arbitration is enabled (PRICTRL0.RRLVLEN3=0) for priority level 3, and the value of this bit group is
non-zero, it will not affect the static priority scheme.
This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN3 written to '0').
Bit 23 – RRLVLEN2 Level 2 Round-Robin Arbitration Enable
This bit controls which arbitration scheme is selected for DMA channels with priority level 2. For details on arbitration
schemes, refer to 24.5.2.4 Arbitration.
Value
Description
0
Static arbitration scheme for channels with level 2 priority.
1
Round-robin arbitration scheme for channels with level 2 priority.
Bits 19:16 – LVLPRI2[3:0] Level 2 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN2=1) for priority level 2, this register holds the channel
number of the last DMA channel being granted access as the active channel with priority level 2.
When static arbitration is enabled (PRICTRL0.RRLVLEN2=0) for priority level 2, and the value of this bit group is
non-zero, it will not affect the static priority scheme.
This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN2 written to '0').
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 312
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
Bit 15 – RRLVLEN1 Level 1 Round-Robin Scheduling Enable
For details on arbitration schemes, refer to 24.5.2.4 Arbitration.
Value
Description
0
Static arbitration scheme for channels with level 1 priority.
1
Round-robin arbitration scheme for channels with level 1 priority.
Bits 11:8 – LVLPRI1[3:0] Level 1 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN1=1) for priority level 1, this register holds the channel
number of the last DMA channel being granted access as the active channel with priority level 1.
When static arbitration is enabled (PRICTRL0.RRLVLEN1=0) for priority level 1, and the value of this bit group is
non-zero, it will not affect the static priority scheme.
This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN1 written to '0').
Bit 7 – RRLVLEN0 Level 0 Round-Robin Scheduling Enable
For details on arbitration schemes, refer to 24.5.2.4 Arbitration.
Value
Description
0
Static arbitration scheme for channels with level 0 priority.
1
Round-robin arbitration scheme for channels with level 0 priority.
Bits 3:0 – LVLPRI0[3:0] Level 0 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN0=1) for priority level 0, this register holds the channel
number of the last DMA channel being granted access as the active channel with priority level 0.
When static arbitration is enabled (PRICTRL0.RRLVLEN0=0) for priority level 0, and the value of this bit group is
non-zero, it will not affect the static priority scheme.
This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN0 written to '0').
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 313
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.10 Interrupt Pending
Name:
Offset:
Reset:
Property:
INTPEND
0x20
0x0000
-
This register allows the user to identify the lowest DMA channel with pending interrupt.
Bit
Access
Reset
Bit
15
PEND
R
0
14
BUSY
R
0
13
FERR
R
0
12
11
10
SUSP
R/W
0
7
6
5
4
3
2
9
TCMPL
R/W
0
8
TERR
R/W
0
1
0
R/W
0
R/W
0
ID[3:0]
Access
Reset
R/W
0
R/W
0
Bit 15 – PEND Pending
This bit will read '1' when the channel selected by Channel ID field (ID) is pending.
Bit 14 – BUSY Busy
This bit will read '1' when the channel selected by Channel ID field (ID) is busy.
Bit 13 – FERR Fetch Error
This bit will read '1' when the channel selected by Channel ID field (ID) fetched an invalid descriptor.
Bit 10 – SUSP Channel Suspend
This bit will read '1' when the channel selected by Channel ID field (ID) has pending Suspend interrupt.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel ID (ID) Suspend interrupt flag.
Bit 9 – TCMPL Transfer Complete
This bit will read '1' when the channel selected by Channel ID field (ID) has pending Transfer Complete interrupt.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel ID (ID) Transfer Complete interrupt flag.
Bit 8 – TERR Transfer Error
This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Error interrupt.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel ID (ID) Transfer Error interrupt flag.
Bits 3:0 – ID[3:0] Channel ID
These bits store the lowest channel number with pending interrupts. The number is valid if Suspend (SUSP), Transfer
Complete (TCMPL) or Transfer Error (TERR) bits are set. The Channel ID field is refreshed when a new channel
(with channel number less than the current one) with pending interrupts is detected, or when the application clears
the corresponding channel interrupt sources. When no pending channels interrupts are available, these bits will
always return zero value when read.
When the bits are written, indirect access to the corresponding Channel Interrupt Flag register is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 314
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.11 Interrupt Status
Name:
Offset:
Reset:
Property:
Bit
INTSTATUS
0x24
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
CHINT11
R
0
10
CHINT10
R
0
9
CHINT9
R
0
8
CHINT8
R
0
7
CHINT7
R
0
6
CHINT6
R
0
5
CHINT5
R
0
4
CHINT4
R
0
3
CHINT3
R
0
2
CHINT2
R
0
1
CHINT1
R
0
0
CHINT0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – CHINTx Channel x Pending Interrupt [x = 11..0]
This bit is set when Channel x has a pending interrupt/the interrupt request is received.
This bit is cleared when the corresponding Channel x interrupts are disabled or the interrupts sources are cleared.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 315
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.12 Busy Channels
Name:
Offset:
Reset:
Property:
Bit
BUSYCH
0x28
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
BUSYCH11
R
0
10
BUSYCH10
R
0
9
BUSYCH9
R
0
8
BUSYCH8
R
0
7
BUSYCH7
R
0
6
BUSYCH6
R
0
5
BUSYCH5
R
0
4
BUSYCH4
R
0
3
BUSYCH3
R
0
2
BUSYCH2
R
0
1
BUSYCH1
R
0
0
BUSYCH0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – BUSYCHx Busy Channel x [x = 11..0]
This bit is cleared when the channel trigger action for DMA channel x is complete, when a bus error for DMA channel
x is detected, or when DMA channel x is disabled.
This bit is set when DMA channel x starts a DMA transfer.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 316
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.13 Pending Channels
Name:
Offset:
Reset:
Property:
Bit
PENDCH
0x2C
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
PENDCH11
R
0
10
PENDCH10
R
0
9
PENDCH9
R
0
8
PENDCH8
R
0
7
PENDCH7
R
0
6
PENDCH6
R
0
5
PENDCH5
R
0
4
PENDCH4
R
0
3
PENDCH3
R
0
2
PENDCH2
R
0
1
PENDCH1
R
0
0
PENDCH0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – PENDCHx Pending Channel x [x = 11..0]
This bit is cleared when trigger execution defined by channel trigger action settings for DMA channel x is started,
when a bus error for DMA channel x is detected or when DMA channel x is disabled. For details on trigger action
settings, refer to CHCTRLB.TRIGACT.
This bit is set when a transfer is pending on DMA channel x.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 317
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.14 Active Channel and Levels
Name:
Offset:
Reset:
Property:
Bit
31
ACTIVE
0x30
0x00000000
-
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
BTCNT[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
BTCNT[7:0]
Access
Reset
Bit
Access
Reset
Bit
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
15
ABUSY
R
0
14
13
12
11
9
8
R
0
R
0
10
ID[4:0]
R
0
R
0
R
0
7
6
4
3
LVLEX3
R
0
2
LVLEX2
R
0
1
LVLEX1
R
0
0
LVLEX0
R
0
Access
Reset
5
Bits 31:16 – BTCNT[15:0] Active Channel Block Transfer Count
These bits hold the 16-bit block transfer count of the ongoing transfer. This value is stored in the active channel
and written back in the corresponding Write-Back channel memory location when the arbiter grants a new channel
access. The value is valid only when the active channel active busy flag (ABUSY) is set.
Bit 15 – ABUSY Active Channel Busy
This bit is cleared when the active transfer count is written back in the write-back memory section.
This bit is set when the next descriptor transfer count is read from the write-back memory section.
Bits 12:8 – ID[4:0] Active Channel ID
These bits hold the channel index currently stored in the active channel registers. The value is updated each time the
arbiter grants a new channel transfer access request.
Bits 0, 1, 2, 3 – LVLEXx Level x Channel Trigger Request Executing [x = 3..0]
This bit is set when a level-x channel trigger request is executing or pending.
This bit is cleared when no request is pending or being executed.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 318
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.15 Descriptor Memory Section Base Address
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
BASEADDR
0x34
0x00000000
PAC Write-Protection, Enable-Protected
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
BASEADDR[31:24]
R/W
R/W
0
0
20
19
BASEADDR[23:16]
R/W
R/W
0
0
12
11
BASEADDR[15:8]
R/W
R/W
0
0
4
3
BASEADDR[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – BASEADDR[31:0] Descriptor Memory Base Address
These bits store the Descriptor memory section base address. The value must be 128-bit aligned.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 319
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.16 Write-Back Memory Section Base Address
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
WRBADDR
0x38
0x00000000
PAC Write-Protection, Enable-Protected
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
WRBADDR[31:24]
R/W
R/W
0
0
20
19
WRBADDR[23:16]
R/W
R/W
0
0
12
11
WRBADDR[15:8]
R/W
R/W
0
0
4
3
WRBADDR[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – WRBADDR[31:0] Write-Back Memory Base Address
These bits store the Write-Back memory base address. The value must be 128-bit aligned.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 320
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.17 Channel ID
Name:
Offset:
Reset:
Property:
Bit
CHID
0x3F
0x00
-
7
6
5
4
3
2
1
0
R/W
0
R/W
0
ID[3:0]
Access
Reset
R/W
0
R/W
0
Bits 3:0 – ID[3:0] Channel ID
These bits define the channel number that will be affected by the channel registers (CH*). Before reading or writing a
channel register, the channel ID bit group must be written first.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 321
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.18 Channel Control A
Name:
Offset:
Reset:
Property:
CHCTRLA
0x40
0x00
PAC Write-Protection, Enable-Protected Bits
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit
7
Access
Reset
R
0
6
RUNSTDBY
R/W
0
5
4
3
2
R
0
R
0
R
0
R
0
1
ENABLE
R/W
0
0
SWRST
R/W
0
Bit 6 – RUNSTDBY Channel run in standby
This bit is used to keep the DMAC channel running in standby mode.
Note: This bit is not enable-protected.
Value
0
1
Description
The DMAC channel is halted in standby.
The DMAC channel continues to run in standby.
Bit 1 – ENABLE Channel Enable
Writing a '0' to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is
empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst transfer
is completed.
Writing a '1' to this bit will enable the DMA channel.
Note: This bit is not enable-protected.
Value
0
1
Description
DMA channel is disabled.
DMA channel is enabled.
Bit 0 – SWRST Channel Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets the channel registers to their initial state. The bit can be set when the channel is
disabled (ENABLE=0). Writing a '1' to this bit will be ignored as long as ENABLE=1. This bit is automatically cleared
when the reset is completed.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 322
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.19 Channel Control B
Name:
Offset:
Reset:
Property:
CHCTRLB
0x44
0x00000000
PAC Write-Protection, Enable-Protected Bits
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit
31
30
29
28
27
26
25
24
CMD[1:0]
Access
Reset
Bit
23
22
TRIGACT[1:0]
R/W
R/W
0
0
Access
Reset
Bit
15
14
Access
Reset
Bit
7
6
21
20
13
12
R/W
0
R/W
0
5
4
EVOE
R/W
0
LVL[1:0]
Access
Reset
R/W
0
R/W
0
19
18
11
10
TRIGSRC[5:0]
R/W
R/W
0
0
3
EVIE
R/W
0
2
R/W
0
R/W
0
R/W
0
17
16
9
8
R/W
0
R/W
0
1
EVACT[2:0]
R/W
0
0
R/W
0
Bits 25:24 – CMD[1:0] Software Command
These bits define the software commands. Refer to 24.5.3.2 Channel Suspend and 24.5.3.3 Channel Resume and
Next Suspend Skip.
Note: This bit field is not enable-protected.
CMD[1:0]
Name
Description
0x0
0x1
0x2
0x3
NOACT
SUSPEND
RESUME
-
No action
Channel suspend operation
Channel resume operation
Reserved
Bits 23:22 – TRIGACT[1:0] Trigger Action
These bits define the trigger action used for a transfer.
Note: This bit field is enable-protected.
TRIGACT[1:0]
Name
Description
0x0
0x1
0x2
0x3
BLOCK
BEAT
TRANSACTION
One trigger required for each block transfer
Reserved
One trigger required for each beat transfer
One trigger required for each transaction
Bits 13:8 – TRIGSRC[5:0] Trigger Source
These bits define the peripheral trigger which is source of the transfer. For details on trigger selection and trigger
modes, refer to Transfer Triggers and Actions and CHCTRLB.TRIGACT.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 323
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
Table 24-2. Peripheral Trigger Source
Value
Name
Description
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28-0x3F
DISABLE
TSENS
SERCOM0 RX
SERCOM0 TX
SERCOM1 RX
SERCOM1 TX
SERCOM2 RX
SERCOM2 TX
SERCOM3 RX
SERCOM3 TX
TCC0 OVF
TCC0 MC0
TCC0 MC1
TCC0 MC2
TCC0 MC3
TCC1 OVF
TCC1 MC0
TCC1 MC1
TCC2 OVF
TCC2 MC0
TCC2 MC1
TC0 OVF
TC0 MC0
TC0 MC1
TC1 OVF
TC1 MC0
TC1 MC1
TC2 OVF
TC2 MC0
TC2 MC1
TC3 OVF
TC3 MC0
TC3 MC1
TC4 OVF
TC4 MC0
TC4 MC1
ADC0 RESRDY
ADC1 RESRDY
SDADC RESRDY
DAC EMPTY
Reserved
Only software/event triggers
TSENS Result Ready Trigger
SERCOM0 RX Trigger
SERCOM0TX Trigger
SERCOM1 RX Trigger
SERCOM1 TX Trigger
SERCOM2 RX Trigger
SERCOM2 TX Trigger
SERCOM3 RX Trigger
SERCOM3 TX Trigger
TCC0 Overflow Trigger
TCC0 Match/Compare 0 Trigger
TCC0 Match/Compare 1 Trigger
TCC0 Match/Compare 2 Trigger
TCC0 Match/Compare 3 Trigger
TCC1 Overflow Trigger
TCC1 Match/Compare 0 Trigger
TCC1 Match/Compare 1 Trigger
TCC2 Overflow Trigger
TCC2 Match/Compare 0 Trigger
TCC2 Match/Compare 1 Trigger
TC0 Overflow Trigger
TC0 Match/Compare 0 Trigger
TC0 Match/Compare 1 Trigger
TC1 Overflow Trigger
TC1 Match/Compare 0 Trigger
TC1 Match/Compare 1 Trigger
TC2 Overflow Trigger
TC2 Match/Compare 0 Trigger
TC2 Match/Compare 1 Trigger
TC3 Overflow Trigger
TC3 Match/Compare 0 Trigger
TC3 Match/Compare 1 Trigger
TC4 Overflow Trigger
TC4 Match/Compare 0 Trigger
TC4 Match/Compare 1 Trigger
ADC0 Result Ready Trigger
ADC1 Result Ready Trigger
SDADC Result Ready Trigger
DAC Empty Trigger
Reserved
Bits 6:5 – LVL[1:0] Channel Arbitration Level
These bits define the arbitration level used for the DMA channel, where a high level has priority over a low level. For
further details on arbitration schemes, refer to 24.5.2.4 Arbitration.
Note: This bit field is not enable-protected.
TRIGACT[1:0]
Name
Description
0x0
0x1
0x2
0x3
LVL0
LVL1
LVL2
LVL3
Channel Priority Level 0
Channel Priority Level 1
Channel Priority Level 2
Channel Priority Level 3
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
Bit 4 – EVOE Channel Event Output Enable
This bit indicates if the Channel event generation is enabled. The event will be generated for every condition defined
in the descriptor Event Output Selection (BTCTRL.EVOSEL).
This bit is available only for the least significant DMA channels. Refer to table: User Multiplexer Selection and Event
Generator Selection of the Event System for details.
Value
Description
0
Channel event generation is disabled.
1
Channel event generation is enabled.
Bit 3 – EVIE Channel Event Input Enable
This bit is available only for the least significant DMA channels. Refer to table: User Multiplexer Selection and Event
Generator Selection of the Event System for details.
Value
Description
0
Channel event action will not be executed on any incoming event.
1
Channel event action will be executed on any incoming event.
Bits 2:0 – EVACT[2:0] Event Input Action
These bits define the event input action, as shown below. The action is executed only if the corresponding EVIE bit in
CHCTRLB register of the channel is set.
This bit is available only for the least significant DMA channels. Refer to table: User Multiplexer Selection and Event
Generator Selection of the Event System for details.
EVACT[2:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
NOACT
TRIG
CTRIG
CBLOCK
SUSPEND
RESUME
SSKIP
-
No action
Normal Transfer and Conditional Transfer on Strobe trigger
Conditional transfer trigger
Conditional block transfer
Channel suspend operation
Channel resume operation
Skip next block suspend action
Reserved
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.20 Channel Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
CHINTENCLR
0x4C
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Channel Interrupt Enable Set (CHINTENSET) register.
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit
7
6
5
4
3
Access
Reset
2
SUSP
R/W
0
1
TCMPL
R/W
0
0
TERR
R/W
0
Bit 2 – SUSP Channel Suspend Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel Suspend Interrupt Enable bit, which disables the Channel Suspend
interrupt.
Value
Description
0
The Channel Suspend interrupt is disabled.
1
The Channel Suspend interrupt is enabled.
Bit 1 – TCMPL Channel Transfer Complete Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel Transfer Complete Interrupt Enable bit, which disables the Channel
Transfer Complete interrupt.
Value
Description
0
The Channel Transfer Complete interrupt is disabled. When block action is set to none, the TCMPL flag
will not be set when a block transfer is completed.
1
The Channel Transfer Complete interrupt is enabled.
Bit 0 – TERR Channel Transfer Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel Transfer Error Interrupt Enable bit, which disables the Channel Transfer
Error interrupt.
Value
Description
0
The Channel Transfer Error interrupt is disabled.
1
The Channel Transfer Error interrupt is enabled.
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.21 Channel Interrupt Enable Set
Name:
Offset:
Reset:
Property:
CHINTENSET
0x4D
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Channel Interrupt Enable Clear (CHINTENCLR) register.
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit
7
6
5
4
3
Access
Reset
2
SUSP
R/W
0
1
TCMPL
R/W
0
0
TERR
R/W
0
Bit 2 – SUSP Channel Suspend Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Channel Suspend Interrupt Enable bit, which enables the Channel Suspend
interrupt.
Value
Description
0
The Channel Suspend interrupt is disabled.
1
The Channel Suspend interrupt is enabled.
Bit 1 – TCMPL Channel Transfer Complete Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Channel Transfer Complete Interrupt Enable bit, which enables the Channel
Transfer Complete interrupt.
Value
Description
0
The Channel Transfer Complete interrupt is disabled.
1
The Channel Transfer Complete interrupt is enabled.
Bit 0 – TERR Channel Transfer Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Channel Transfer Error Interrupt Enable bit, which enables the Channel Transfer
Error interrupt.
Value
Description
0
The Channel Transfer Error interrupt is disabled.
1
The Channel Transfer Error interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.22 Channel Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
CHINTFLAG
0x4E
0x00
-
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit
7
6
5
4
3
Access
Reset
2
SUSP
R/W
0
1
TCMPL
R/W
0
0
TERR
R/W
0
Bit 2 – SUSP Channel Suspend
This flag is cleared by writing a '1' to it.
This flag is set when a block transfer with suspend block action is completed, when a software suspend command is
executed, when a suspend event is received or when an invalid descriptor is fetched by the DMA.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel Suspend interrupt flag for the corresponding channel.
For details on available software commands, refer to CHCTRLB.CMD.
For details on available event input actions, refer to CHCTRLB.EVACT.
For details on available block actions, refer to BTCTRL.BLOCKACT.
Bit 1 – TCMPL Channel Transfer Complete
This flag is cleared by writing a '1' to it.
This flag is set when a block transfer is completed and the corresponding interrupt block action is enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Transfer Complete interrupt flag for the corresponding channel.
Bit 0 – TERR Channel Transfer Error
This flag is cleared by writing a '1' to it.
This flag is set when a bus error is detected during a beat transfer or when the DMAC fetches an invalid descriptor.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Transfer Error interrupt flag for the corresponding channel.
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and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.6.23 Channel Status
Name:
Offset:
Reset:
Property:
CHSTATUS
0x4F
0x00
-
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit
7
6
5
4
3
Access
Reset
2
FERR
R
0
1
BUSY
R
0
0
PEND
R
0
Bit 2 – FERR Channel Fetch Error
This bit is cleared when a software resume command is executed.
This bit is set when an invalid descriptor is fetched.
Bit 1 – BUSY Channel Busy
This bit is cleared when the channel trigger action is completed, when a bus error is detected or when the channel is
disabled.
This bit is set when the DMA channel starts a DMA transfer.
Bit 0 – PEND Channel Pending
This bit is cleared when the channel trigger action is started, when a bus error is detected or when the channel is
disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT.
This bit is set when a transfer is pending on the DMA channel, as soon as the transfer request is received.
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Datasheet
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.7
Register Summary - SRAM
Offset
Name
0x00
BTCTRL
0x02
BTCNT
0x04
SRCADDR
0x08
DSTADDR
0x0C
DESCADDR
Bit Pos.
7
7:0
15:8
7:0
15:8
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
© 2021 Microchip Technology Inc.
and its subsidiaries
6
STEPSIZE[2:0]
5
4
3
BLOCKACT[1:0]
STEPSEL
DSTINC
BTCNT[7:0]
BTCNT[15:8]
SRCADDR[7:0]
SRCADDR[15:8]
SRCADDR[23:16]
SRCADDR[31:24]
DSTADDR[7:0]
DSTADDR[15:8]
DSTADDR[23:16]
DSTADDR[31:24]
DESCADDR[7:0]
DESCADDR[15:8]
DESCADDR[23:16]
DESCADDR[31:24]
Datasheet
2
1
0
EVOSEL[1:0]
VALID
SRCINC
BEATSIZE[1:0]
DS60001638D-page 330
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.7.1
Block Transfer Control
Name:
Offset:
Property:
BTCTRL
0x00
-
The BTCTRL register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Bit
15
14
STEPSIZE[2:0]
13
6
5
12
STEPSEL
11
DSTINC
10
SRCINC
9
2
1
8
BEATSIZE[1:0]
Access
Reset
Bit
7
4
3
BLOCKACT[1:0]
EVOSEL[1:0]
0
VALID
Access
Reset
Bits 15:13 – STEPSIZE[2:0] Address Increment Step Size
These bits select the address increment step size. The setting apply to source or destination address, depending on
STEPSEL setting.
Value
Name
Description
0x0
X1
Next ADDR = ADDR + (Beat size in byte) * 1
0x1
X2
Next ADDR = ADDR + (Beat size in byte) * 2
0x2
X4
Next ADDR = ADDR + (Beat size in byte) * 4
0x3
X8
Next ADDR = ADDR + (Beat size in byte) * 8
0x4
X16
Next ADDR = ADDR + (Beat size in byte) * 16
0x5
X32
Next ADDR = ADDR + (Beat size in byte) * 32
0x6
X64
Next ADDR = ADDR + (Beat size in byte) * 64
0x7
X128
Next ADDR = ADDR + (Beat size in byte) * 128
Bit 12 – STEPSEL Step Selection
This bit selects if source or destination addresses are using the step size settings.
Value
Name
Description
0x0
DST
Step size settings apply to the destination address
0x1
SRC
Step size settings apply to the source address
Bit 11 – DSTINC Destination Address Increment Enable
Writing a '0' to this bit will disable the destination address incrementation. The address will be kept fixed during the
data transfer.
Writing a '1' to this bit will enable the destination address incrementation. By default, the destination address is
incremented by 1. If the STEPSEL bit is cleared, flexible step-size settings are available in the STEPSIZE register.
Value
Description
0
The Destination Address Increment is disabled.
1
The Destination Address Increment is enabled.
Bit 10 – SRCINC Source Address Increment Enable
Writing a '0' to this bit will disable the source address incrementation. The address will be kept fixed during the data
transfer.
Writing a '1' to this bit will enable the source address incrementation. By default, the source address is incremented
by 1. If the STEPSEL bit is set, flexible step-size settings are available in the STEPSIZE register.
Value
Description
0
The Source Address Increment is disabled.
1
The Source Address Increment is enabled.
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Datasheet
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
Bits 9:8 – BEATSIZE[1:0] Beat Size
These bits define the size of one beat. A beat is the size of one data transfer bus access, and the setting apply to
both read and write accesses.
Value
Name
Description
0x0
BYTE
8-bit bus transfer
0x1
HWORD
16-bit bus transfer
0x2
WORD
32-bit bus transfer
other
Reserved
Bits 4:3 – BLOCKACT[1:0] Block Action
These bits define what actions the DMAC should take after a block transfer has completed.
BLOCKACT[1:0] Name
0x0
0x1
0x2
0x3
Description
NOACT
INT
Channel will be disabled if it is the last block transfer in the transaction
Channel will be disabled if it is the last block transfer in the transaction and block
interrupt
SUSPEND Channel suspend operation is completed
BOTH
Both channel suspend operation and block interrupt
Bits 2:1 – EVOSEL[1:0] Event Output Selection
These bits define the event output selection.
EVOSEL[1:0]
Name
Description
0x0
0x1
0x2
0x3
DISABLE
BLOCK
Event generation disabled
Event strobe when block transfer complete
Reserved
Event strobe when beat transfer complete
BEAT
Bit 0 – VALID Descriptor Valid
Writing a '0' to this bit in the Descriptor or Write-Back memory will suspend the DMA channel operation when fetching
the corresponding descriptor.
The bit is automatically cleared in the Write-Back memory section when channel is aborted, when an error is detected
during the block transfer, or when the block transfer is completed.
Value
Description
0
The descriptor is not valid.
1
The descriptor is valid.
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Datasheet
DS60001638D-page 332
PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.7.2
Block Transfer Count
Name:
Offset:
Property:
BTCNT
0x02
-
The BTCNT register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Bit
15
14
13
12
11
10
9
8
3
2
1
0
BTCNT[15:8]
Access
Reset
Bit
7
6
5
4
BTCNT[7:0]
Access
Reset
Bits 15:0 – BTCNT[15:0] Block Transfer Count
This bit group holds the 16-bit block transfer count.
During a transfer, the internal counter value is decremented by one after each beat transfer. The internal counter is
written to the corresponding write-back memory section for the DMA channel when the DMA channel loses priority,
is suspended or gets disabled. The DMA channel can be disabled by a complete transfer, a transfer error or by
software.
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Datasheet
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.7.3
Block Transfer Source Address
Name:
Offset:
Property:
SRCADDR
0x04
-
The SRCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Bit
31
30
29
28
27
SRCADDR[31:24]
26
25
24
23
22
21
20
19
SRCADDR[23:16]
18
17
16
15
14
13
12
11
SRCADDR[15:8]
10
9
8
7
6
5
4
3
SRCADDR[7:0]
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 31:0 – SRCADDR[31:0] Transfer Source Address
This bit field holds the block transfer source address.
When source address incrementation is disabled (BTCTRL.SRCINC=0), SRCADDR corresponds to the last beat
transfer address in the block transfer.
When source address incrementation is enabled (BTCTRL.SRCINC=1), SRCADDR is calculated as follows:
If BTCTRL.STEPSEL=1:
SRCADDR = SRCADDRSTART + BTCNT ⋅ BEATSIZE + 1 ⋅ 2STEPSIZE
If BTCTRL.STEPSEL=0:
SRCADDR = SRCADDRSTART + BTCNT ⋅ BEATSIZE + 1
•
•
•
•
SRCADDRSTART is the source address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.7.4
Block Transfer Destination Address
Name:
Offset:
Property:
DSTADDR
0x08
-
The DSTADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Bit
31
30
29
28
27
DSTADDR[31:24]
26
25
24
23
22
21
20
19
DSTADDR[23:16]
18
17
16
15
14
13
12
11
DSTADDR[15:8]
10
9
8
7
6
5
4
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
3
DSTADDR[7:0]
Access
Reset
Bits 31:0 – DSTADDR[31:0] Transfer Destination Address
This bit field holds the block transfer destination address.
When destination address incrementation is disabled (BTCTRL.DSTINC=0), DSTADDR corresponds to the last beat
transfer address in the block transfer.
When destination address incrementation is enabled (BTCTRL.DSTINC=1), DSTADDR is calculated as follows:
If BTCTRL.STEPSEL=1:
DSTADDR = DSTADDRSTART + BTCNT • BEATSIZE + 1
If BTCTRL.STEPSEL=0:
DSTADDR = DSTADDRSTART + BTCNT • BEATSIZE + 1 • 2STEPSIZE
•
•
•
•
DSTADDRSTART is the destination address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
Direct Memory Access Controller (DMAC)
24.7.5
Next Descriptor Address
Name:
Offset:
Property:
DESCADDR
0x0C
-
The DESCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Bit
31
30
29
28
27
DESCADDR[31:24]
26
25
24
23
22
21
20
19
DESCADDR[23:16]
18
17
16
15
14
13
12
11
DESCADDR[15:8]
10
9
8
7
6
5
4
3
DESCADDR[7:0]
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 31:0 – DESCADDR[31:0] Next Descriptor Address
This bit group holds the SRAM address of the next descriptor. The value must be 128-bit aligned. If the value of
this SRAM register is 0x00000000, the transaction will be terminated when the DMAC tries to load the next transfer
descriptor.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 336
PIC32CM MC00 Family
External Interrupt Controller (EIC)
25.
External Interrupt Controller (EIC)
25.1
Overview
The External Interrupt Controller (EIC) allows external pins to be configured as interrupt lines. Each interrupt line can
be individually masked and can generate an interrupt on rising, falling, or both edges, or on high or low levels. Each
external pin has a configurable filter to remove spikes. Each external pin can also be configured to be asynchronous
in order to wake up the device from sleep modes where all clocks have been disabled. External pins can also
generate an event.
A separate non-maskable interrupt (NMI) is also supported. It has properties similar to the other external interrupts,
but is connected to the NMI request of the CPU, enabling it to interrupt any other interrupt mode.
25.2
Features
•
•
•
•
•
•
•
•
•
25.3
Up to 16 external pins (EXTINTx), plus one non-maskable pin (NMI)
Dedicated, individually maskable interrupt for each pin
Interrupt on rising, falling, or both edges
Synchronous or asynchronous edge detection mode
Interrupt pin debouncing
Interrupt on high or low levels
Asynchronous interrupts for sleep modes without clock
Filtering of external pins
Event generation from EXTINTx
Block Diagram
Figure 25-1. EIC Block Diagram
FILTENx
SENSEx[2:0]
Interrupt
EXTINTx
Filter
Edge/Level
Detection
Wake
Event
NMIFILTEN
NMI
Edge/Level
Detection
Wake
25.4
inwake_extint
evt_extint
NMISENSE[2:0]
Interrupt
Filter
intreq_extint
intreq_nmi
inwake_nmi
Signal Description
Signal Name
Type
Description
EXTINT[15..0]
Digital Input
External interrupt pin
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Datasheet
DS60001638D-page 337
PIC32CM MC00 Family
External Interrupt Controller (EIC)
...........continued
Signal Name
Type
Description
NMI
Digital Input
Non-maskable interrupt pin
One signal may be available on several pins.
25.5
Peripheral Dependencies
Peripheral Base Address
EIC
0x40002800
IRQ
AHB CLK
APB CLK
Generic CLK
Enabled at
reset
Enabled at
reset
Index
Index
Prot at
reset
User
Generator
Index
-
Y
2
10
N
-
14-29:
EXTINT0-15
-
3, NMI
25.6
Functional Description
25.6.1
Principle of Operation
PAC
Events
DMA
Sleep Walking
Y
The EIC detects edge or level condition to generate interrupts to the CPU interrupt controller or events to the Event
System. Each external interrupt pin (EXTINT) can be filtered using majority vote filtering, clocked by GCLK_EIC or by
CLK_ULP32K.
25.6.2
Basic Operation
25.6.2.1 Initialization
The EIC must be initialized in the following order:
1.
2.
3.
Enable CLK_EIC_APB
If required, configure the NMI by writing the Non-Maskable Interrupt Control register (NMICTRL)
Enable GCLK_EIC or CLK_ULP32K when one of the following configuration is selected:
– The NMI uses edge detection or filtering.
– One or more EXTINT uses filtering.
– One or more EXTINT uses edge detection.
– One or more EXTINT uses debouncing.
GCLK_EIC is used when a frequency higher than 32.768 kHz is required for filtering.
4.
5.
6.
7.
CLK_ULP32K is recommended when power consumption is the priority. For CLK_ULP32K write a '1' to the
Clock Selection bit in the Control A register (CTRLA.CKSEL).
Configure the EIC input sense and filtering by writing the configuration register (CONFIG0 or CONFIG1).
Optionally, enable the asynchronous mode.
Optionally, enable the debouncer mode.
Enable the EIC by writing a ‘1’ to CTRLA.ENABLE.
The following bits are enable-protected, meaning that it can only be written when the EIC is disabled
(CTRLA.ENABLE=0):
•
Clock Selection bit in Control A register (CTRLA.CKSEL)
The following registers are enable-protected:
•
•
•
•
Event Control register (EVCTRL)
Configuration register (CONFIGn).
External Interrupt Asynchronous Mode register (25.7.9 ASYNCH)
Debouncer Enable register (DEBOUNCEN)
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PIC32CM MC00 Family
External Interrupt Controller (EIC)
•
Debounce Prescaler register (DPRESCALER)
Enable-protected bits in the CTRLA register can be written at the same time when setting CTRLA.ENABLE to '1', but
not at the same time as CTRLA.ENABLE is being cleared.
Enable-protection is denoted by the "Enable-Protected" property in the register description.
25.6.2.2 Enabling, Disabling, and Resetting
The EIC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The EIC is disabled
by writing CTRLA.ENABLE to '0'.
The EIC is reset by setting the Software Reset bit in the Control register (CTRLA.SWRST). All registers in the EIC will
be reset to their initial state, and the EIC will be disabled.
Refer to the CTRLA register description for details.
25.6.3
External Pin Processing
Each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or both edges) or
level detection (high or low). The sense of external interrupt pins is configured by writing the Input Sense x bits in the
configuration register (CONFIGn.SENSEx). The corresponding interrupt flag (INTFLAG.EXTINT[x]) in the Interrupt
Flag Status and Clear register (25.7.8 INTFLAG) is set when the interrupt condition is met.
When the interrupt flag has been cleared in edge-sensitive mode, INTFLAG.EXTINT[x] will only be set if a new
interrupt condition is met.
In level-sensitive mode, when interrupt has been cleared, INTFLAG.EXTINT[x] will be set immediately if the EXTINTx
pin still matches the interrupt condition.
Each external pin can be filtered by a majority vote filtering, clocked by GCLK_EIC or CLK_ULP32K. Filtering is
enabled if bit Filter Enable x in the configuration register (CONFIGn.FILTENx) is written to '1'. The majority vote filter
samples the external pin three times with GCLK_EIC or CLK_ULP32K and outputs the value when two or more
samples are equal.
Table 25-1. Majority Vote Filter Logic
Samples [0, 1, 2]
Filter Output
[0,0,0]
0
[0,0,1]
0
[0,1,0]
0
[0,1,1]
1
[1,0,0]
0
[1,0,1]
1
[1,1,0]
1
[1,1,1]
1
When an external interrupt is configured for level detection and when filtering is disabled, detection is done
asynchronously. Level detection and asynchronous edge detection do not require GCLK_EIC or CLK_ULP32K and
can generate asynchronous interrupts and events.
If filtering, synchronous edge detection, or debouncing is enabled, the EIC automatically requests GCLK_EIC or
CLK_ULP32K to operate. The selection between these two clocks is done by writing the Clock Selection bits in the
Control A register (CTRLA.CKSEL). GCLK_EIC must be enabled in the GCLK module. In these modes the external
pin is sampled at the EIC clock rate, thus pulses with duration lower than two EIC clock periods may not be properly
detected.
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PIC32CM MC00 Family
External Interrupt Controller (EIC)
Figure 25-2. Interrupt Detection Latency by modes (Rising Edge)
GCLK_EIC
CLK_EIC_APB
EXTINTx
intreq_extint[x]
(level detection / no filter)
No interrupt
intreq_extint[x]
(level detection / filter)
intreq_extint[x]
(edge detection / no filter)
No interrupt
intreq_extint[x]
(edge detection / filter)
clear INTFLAG.EXTINT[x]
Detection latency depends on the detection mode.
Table 25-2. Detection Latency
25.6.4
Detection mode
Latency (worst case)
Level without filter
Five CLK_EIC_APB periods
Level with filter
Four GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods
Edge without filter
Four GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods
Edge with filter
Six GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods
Additional Features
25.6.4.1 Non-Maskable Interrupt (NMI)
The non-maskable interrupt pin can also generate an interrupt on edge or level detection, but it is configured with
the dedicated NMI Control register (NMICTRL). To select the sense for NMI, write to the NMISENSE bit group in
the NMI Control register (NMICTRL.NMISENSE). NMI filtering is enabled by writing a '1' to the NMI Filter Enable bit
(NMICTRL.NMIFILTEN).
If edge detection or filtering is required, enable GCLK_EIC or CLK_ULP32K.
NMI detection is enabled only by the NMICTRL.NMISENSE value, and the EIC module is not required to be enabled.
When an NMI is detected, the non-maskable interrupt flag in the NMI Flag Status and Clear register is set
(NMIFLAG.NMI). NMI interrupt generation is always enabled, and NMIFLAG.NMI generates an interrupt request
when set.
25.6.4.2 Asynchronous Edge Detection Mode
The EXTINT edge detection operates synchronously or asynchronously, as selected by the Asynchronous Control
Mode bit for external pin ‘x’ in the External Interrupt Asynchronous Mode register (ASYNCH.ASYNCH[x]). The EIC
edge detection is operated synchronously when the Asynchronous Control Mode bit (ASYNCH.ASYNCH[x]) is '0'
(default value). It is operated asynchronously when ASYNCH.ASYNCH[x] is written to '1'.
In Synchronous Edge Detection Mode, the external interrupt (EXTINT) or the non-maskable interrupt (NMI) pins are
sampled using the EIC clock as defined by the Clock Selection bit in the Control A register (CTRLA.CKSEL). The
External Interrupt flag (INTFLAG.EXTINT[x]) or Non-Maskable Interrupt flag (NMIFLAG.NMI) is set when the last
sampled state of the pin differs from the previously sampled state. The EIC clock is needed in this mode.
The Synchronous Edge Detection Mode can be used in Idle and Standby sleep modes.
In Asynchronous Edge Detection Mode, the external interrupt (EXTINT) pins or the non-maskable interrupt (NMI) pins
set the External Interrupt flag or Non-Maskable Interrupt flag (INTFLAG.EXTINT[x] or NMIFLAG) directly. The EIC
clock is not needed in this mode.
The asynchronous edge detection mode can be used in Idle and Standby sleep modes. When asynchronous edge
detection is enabled in Standby sleep mode, only the first edge detected will trigger an event in the Event System.
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PIC32CM MC00 Family
External Interrupt Controller (EIC)
Subsequent asynchronous edges will not generate events until Standby sleep mode is exited. Synchronous edge
detection will not exhibit this behavior.
25.6.5
Interrupts
The EIC has the following interrupt sources:
•
•
External interrupt pins (EXTINTx). See 25.6.2 Basic Operation.
Non-maskable interrupt pin (NMI). See 25.6.4 Additional Features.
Each interrupt source has an associated interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when an interrupt condition occurs (NMIFLAG for NMI). Each interrupt, except NMI, can
be individually enabled by setting the corresponding bit in the Interrupt Enable Set register (INTENSET=1), and
disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR=1). As both INTENSET
and INTENCLR always reflect the same value, the status of interrupt enablement can be read from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the EIC is reset. See the
INTFLAG register for details on how to clear interrupt flags. The EIC has one interrupt request line for each external
interrupt (EXTINTx) and one line for NMI. The user must read the INTFLAG (or NMIFLAG) register to determine
which interrupt condition is present.
Notes:
1. Interrupts must be globally enabled for interrupt requests to be generated.
2. If an external interrupt (EXTINT) is common on two or more I/O pins, only one will be active (the first one
programmed).
25.6.6
Events
The EIC can generate the following output events:
•
External event from pin (EXTINTx).
Setting an Event Output Control register (EVCTRL.EXTINTEO) enables the corresponding output event. Clearing this
bit disables the corresponding output event. Refer to Event System for details on configuring the Event System.
When the condition on pin EXTINTx matches the configuration in the CONFIGn.SENSEx bit field, the corresponding
event is generated, if enabled.
25.6.7
Sleep Mode Operation
In sleep modes, an EXTINTx pin can wake up the device if the corresponding condition matches the configuration in
the CONFIGn register, and the corresponding bit in the Interrupt Enable Set register (25.7.7 INTENSET) is written to
'1'.
Figure 25-3. Wake-up Operation Example (High-Level Detection, No Filter, Interrupt Enable Set)
CLK_EIC_APB
EXTINTx
intwake_extint[x]
intreq_extint[x]
wake from sleep mode
25.6.8
clear INTFLAG.EXTINT[x]
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
•
•
Software Reset bit in control register (CTRLA.SWRST)
Enable bit in control register (CTRLA.ENABLE)
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DS60001638D-page 341
PIC32CM MC00 Family
External Interrupt Controller (EIC)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 342
PIC32CM MC00 Family
External Interrupt Controller (EIC)
25.7
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
CTRLA
NMICTRL
0x02
NMIFLAG
7:0
7:0
7:0
15:8
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
0x04
SYNCBUSY
0x08
EVCTRL
0x0C
INTENCLR
0x10
INTENSET
0x14
INTFLAG
0x18
ASYNCH
0x1C
CONFIG0
0x20
CONFIG1
7
6
5
4
3
CKSEL
NMIASYNCH
NMIFILTEN
2
1
0
ENABLE
NMISENSE[2:0]
SWRST
NMI
ENABLE
EXTINTEO7 EXTINTEO6 EXTINTEO5 EXTINTEO4 EXTINTEO3 EXTINTEO2 EXTINTEO1
EXTINTEO15 EXTINTEO14 EXTINTEO13 EXTINTEO12 EXTINTEO11 EXTINTEO10 EXTINTEO9
SWRST
EXTINTEO0
EXTINTEO8
EXTINT7
EXTINT15
EXTINT6
EXTINT14
EXTINT5
EXTINT13
EXTINT4
EXTINT12
EXTINT3
EXTINT11
EXTINT2
EXTINT10
EXTINT1
EXTINT9
EXTINT0
EXTINT8
EXTINT7
EXTINT15
EXTINT6
EXTINT14
EXTINT5
EXTINT13
EXTINT4
EXTINT12
EXTINT3
EXTINT11
EXTINT2
EXTINT10
EXTINT1
EXTINT9
EXTINT0
EXTINT8
EXTINT7
EXTINT15
EXTINT6
EXTINT14
EXTINT5
EXTINT13
EXTINT4
EXTINT12
EXTINT3
EXTINT11
EXTINT2
EXTINT10
EXTINT1
EXTINT9
EXTINT0
EXTINT8
ASYNCH7
ASYNCH15
ASYNCH6
ASYNCH14
ASYNCH5
ASYNCH13
ASYNCH4
ASYNCH12
ASYNCH3
ASYNCH11
ASYNCH2
ASYNCH10
ASYNCH1
ASYNCH9
ASYNCH0
ASYNCH8
FILTEN1
FILTEN3
FILTEN5
FILTEN7
FILTEN1
FILTEN3
FILTEN5
FILTEN7
© 2021 Microchip Technology Inc.
and its subsidiaries
SENSE1[2:0]
SENSE3[2:0]
SENSE5[2:0]
SENSE7[2:0]
SENSE1[2:0]
SENSE3[2:0]
SENSE5[2:0]
SENSE7[2:0]
Datasheet
FILTEN0
FILTEN2
FILTEN4
FILTEN6
FILTEN0
FILTEN2
FILTEN4
FILTEN6
SENSE0[2:0]
SENSE2[2:0]
SENSE4[2:0]
SENSE6[2:0]
SENSE0[2:0]
SENSE2[2:0]
SENSE4[2:0]
SENSE6[2:0]
DS60001638D-page 343
PIC32CM MC00 Family
External Interrupt Controller (EIC)
25.7.1
Control A
Name:
Offset:
Reset:
Property:
Bit
7
CTRLA
0x00
0x00
PAC Write-Protection, Write-Synchronized Bits
6
Access
Reset
5
4
CKSEL
RW
0
3
2
1
ENABLE
RW
0
0
SWRST
W
0
Bit 4 – CKSEL Clock Selection
The EIC can be clocked either by GCLK_EIC (when a frequency higher than 32.768 kHz is required for filtering) or by
CLK_ULP32K (when power consumption is the priority).
Note: This bit is not synchronized.
Value
0
1
Description
The EIC is clocked by GCLK_EIC.
The EIC is clocked by CLK_ULP32K.
Bit 1 – ENABLE Enable
Note: This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
Value
0
1
Description
The EIC is disabled.
The EIC is enabled.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the EIC to their initial state, and the EIC will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write operation
will be discarded.
Note: This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST
synchronization is complete.
Value
0
1
Description
There is no ongoing reset operation.
The reset operation is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 344
PIC32CM MC00 Family
External Interrupt Controller (EIC)
25.7.2
Non-Maskable Interrupt Control
Name:
Offset:
Reset:
Property:
Bit
7
NMICTRL
0x01
0x00
PAC Write-Protection
6
Access
Reset
5
4
NMIASYNCH
R/W
0
3
NMIFILTEN
R/W
0
2
R/W
0
1
NMISENSE[2:0]
R/W
0
0
R/W
0
Bit 4 – NMIASYNCH NMI Asynchronous Edge Detection Mode
The NMI edge detection can be operated synchronously or asynchronously to the EIC clock.
Value
Description
0
The NMI edge detection is synchronously operated.
1
The NMI edge detection is asynchronously operated.
Bit 3 – NMIFILTEN Non-Maskable Interrupt Filter Enable
Value
Description
0
NMI filter is disabled.
1
NMI filter is enabled.
Bits 2:0 – NMISENSE[2:0] Non-Maskable Interrupt Sense Configuration
These bits define on which edge or level the NMI triggers.
Value
Name
Description
0x0
NONE
No detection
0x1
RISE
Rising-edge detection
0x2
FALL
Falling-edge detection
0x3
BOTH
Both-edge detection
0x4
HIGH
High-level detection
0x5
LOW
Low-level detection
0x6 Reserved
0x7
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 345
PIC32CM MC00 Family
External Interrupt Controller (EIC)
25.7.3
Non-Maskable Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
NMIFLAG
0x02
0x0000
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NMI
RW
0
Access
Reset
Bit
Access
Reset
Bit 0 – NMI Non-Maskable Interrupt
This flag is cleared by writing a '1' to it.
This flag is set when the NMI pin matches the NMI sense configuration, and will generate an interrupt request.
Writing a '0' to this bit has no effect.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 346
PIC32CM MC00 Family
External Interrupt Controller (EIC)
25.7.4
Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x04
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – ENABLE Enable Synchronization Busy Status
Value
Description
0
Write synchronization for CTRLA.ENABLE bit is complete.
1
Write synchronization for CTRLA.ENABLE bit is ongoing.
Bit 0 – SWRST Software Reset Synchronization Busy Status
Value
Description
0
Write synchronization for CTRLA.SWRST bit is complete.
1
Write synchronization for CTRLA.SWRST bit is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 347
PIC32CM MC00 Family
External Interrupt Controller (EIC)
25.7.5
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x08
0x00000000
PAC Write-Protection, Enable-Protected
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
14
EXTINTEO14
R/W
0
13
EXTINTEO13
R/W
0
12
EXTINTEO12
R/W
0
11
EXTINTEO11
R/W
0
10
EXTINTEO10
R/W
0
9
EXTINTEO9
R/W
0
8
EXTINTEO8
R/W
0
6
EXTINTEO6
R/W
0
5
EXTINTEO5
R/W
0
4
EXTINTEO4
R/W
0
3
EXTINTEO3
R/W
0
2
EXTINTEO2
R/W
0
1
EXTINTEO1
R/W
0
0
EXTINTEO0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
15
EXTINTEO15
Access
R/W
Reset
0
Bit
Access
Reset
7
EXTINTEO7
R/W
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTEOx External Interrupt Event Output Enable [x = 15..0]
The bit x of EXTINTEO enables the event associated with the EXTINTx pin.
Value
Description
0
Event from pin EXTINTx is disabled.
1
Event from pin EXTINTx is enabled and will be generated when EXTINTx pin matches the external
interrupt sensing configuration.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 348
PIC32CM MC00 Family
External Interrupt Controller (EIC)
25.7.6
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x0C
0x00000000
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
EXTINT15
R/W
0
14
EXTINT14
R/W
0
13
EXTINT13
R/W
0
12
EXTINT12
R/W
0
11
EXTINT11
R/W
0
10
EXTINT10
R/W
0
9
EXTINT9
R/W
0
8
EXTINT8
R/W
0
7
EXTINT7
R/W
0
6
EXTINT6
R/W
0
5
EXTINT5
R/W
0
4
EXTINT4
R/W
0
3
EXTINT3
R/W
0
2
EXTINT2
R/W
0
1
EXTINT1
R/W
0
0
EXTINT0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTx External Interrupt Enable [x = 15..0]
The bit x of EXTINT disables the interrupt associated with the EXTINTx pin.
Writing a '0' to bit x has no effect.
Writing a '1' to bit x will clear the External Interrupt Enable bit x, which disables the external interrupt EXTINTx.
Value
Description
0
The external interrupt x is disabled.
1
The external interrupt x is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 349
PIC32CM MC00 Family
External Interrupt Controller (EIC)
25.7.7
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x10
0x00000000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
EXTINT15
R/W
0
14
EXTINT14
R/W
0
13
EXTINT13
R/W
0
12
EXTINT12
R/W
0
11
EXTINT11
R/W
0
10
EXTINT10
R/W
0
9
EXTINT9
R/W
0
8
EXTINT8
R/W
0
7
EXTINT7
R/W
0
6
EXTINT6
R/W
0
5
EXTINT5
R/W
0
4
EXTINT4
R/W
0
3
EXTINT3
R/W
0
2
EXTINT2
R/W
0
1
EXTINT1
R/W
0
0
EXTINT0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTx External Interrupt Enable [x = 15..0]
The bit x of EXTINT enables the interrupt associated with the EXTINTx pin.
Writing a '0' to bit x has no effect.
Writing a '1' to bit x will set the External Interrupt Enable bit x, which enables the external interrupt EXTINTx.
Value
Description
0
The external interrupt x is disabled.
1
The external interrupt x is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 350
PIC32CM MC00 Family
External Interrupt Controller (EIC)
25.7.8
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
INTFLAG
0x14
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
EXTINT15
R/W
0
14
EXTINT14
R/W
0
13
EXTINT13
R/W
0
12
EXTINT12
R/W
0
11
EXTINT11
R/W
0
10
EXTINT10
R/W
0
9
EXTINT9
R/W
0
8
EXTINT8
R/W
0
7
EXTINT7
R/W
0
6
EXTINT6
R/W
0
5
EXTINT5
R/W
0
4
EXTINT4
R/W
0
3
EXTINT3
R/W
0
2
EXTINT2
R/W
0
1
EXTINT1
R/W
0
0
EXTINT0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTx External Interrupt [x = 15..0]
The flag bit x is cleared by writing a '1' to it.
This flag is set when EXTINTx pin matches the external interrupt sense configuration and will generate an interrupt
request if INTENCLR/SET.EXTINT[x] is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the External Interrupt x flag.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 351
PIC32CM MC00 Family
External Interrupt Controller (EIC)
25.7.9
External Interrupt Asynchronous Mode
Name:
Offset:
Reset:
Property:
Bit
ASYNCH
0x18
0x00000000
PAC Write-Protection, Enable-Protected
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ASYNCH15
RW
0
14
ASYNCH14
RW
0
13
ASYNCH13
RW
0
12
ASYNCH12
RW
0
11
ASYNCH11
RW
0
10
ASYNCH10
RW
0
9
ASYNCH9
RW
0
8
ASYNCH8
RW
0
7
ASYNCH7
RW
0
6
ASYNCH6
RW
0
5
ASYNCH5
RW
0
4
ASYNCH4
RW
0
3
ASYNCH3
RW
0
2
ASYNCH2
RW
0
1
ASYNCH1
RW
0
0
ASYNCH0
RW
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – ASYNCH Asynchronous Edge Detection Mode [x = 15..0]
The bit x of ASYNCH set the Asynchronous Edge Detection Mode for the interrupt associated with the EXTINTx pin.
Value
Description
0
The EXTINT x edge detection is synchronously operated.
1
The EXTINT x edge detection is asynchronously operated.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 352
PIC32CM MC00 Family
External Interrupt Controller (EIC)
25.7.10 External Interrupt Sense Configuration n
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
FILTEN7
RW
0
23
FILTEN5
RW
0
15
FILTEN3
RW
0
7
FILTEN1
RW
0
CONFIGn
0x1C + n*0x04 [n=0..1]
0x00000000
PAC Write-Protection, Enable-Protected
30
RW
0
22
RW
0
14
RW
0
6
RW
0
29
SENSE7[2:0]
RW
0
21
SENSE5[2:0]
RW
0
13
SENSE3[2:0]
RW
0
5
SENSE1[2:0]
RW
0
28
RW
0
20
RW
0
12
RW
0
4
RW
0
27
FILTEN6
RW
0
19
FILTEN4
RW
0
11
FILTEN2
RW
0
3
FILTEN0
RW
0
26
RW
0
18
RW
0
10
RW
0
2
RW
0
25
SENSE6[2:0]
RW
0
17
SENSE4[2:0]
RW
0
9
SENSE2[2:0]
RW
0
1
SENSE0[2:0]
RW
0
24
RW
0
16
RW
0
8
RW
0
0
RW
0
Bits 3, 7, 11, 15, 19, 23, 27, 31 – FILTENx Filter Enable x [x = 7..0]
Note: The filter must be disabled if the asynchronous detection is enabled.
Value
0
1
Description
Filter is disabled for EXTINT[n*8+x] input.
Filter is enabled for EXTINT[n*8+x] input.
Bits 0:2, 4:6, 8:10, 12:14, 16:18, 20:22, 24:26, 28:30 – SENSEx Input Sense Configuration x [x = 7..0]
These bits define on which edge or level the interrupt or event for EXTINT[n*8+x] will be generated.
Value
Name
Description
0x0
NONE
No detection
0x1
RISE
Rising-edge detection
0x2
FALL
Falling-edge detection
0x3
BOTH
Both-edge detection
0x4
HIGH
High-level detection
0x5
LOW
Low-level detection
0x6 Reserved
0x7
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 353
PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.
Nonvolatile Memory Controller (NVMCTRL)
26.1
Overview
Nonvolatile Memory (NVM) is a reprogrammable Flash memory that retains program and data storage even with
power off. It embeds a main array and a separate smaller Data Flash array, which can be programmed while reading
the main array. A size-configurable section at the beginning of the main array can be configured as write protected,
thus providing an immutable boot section. The NVM Controller (NVMCTRL) connects to the AHB and APB bus
interfaces for system access to the NVM block. The AHB interface is used for reads and writes to the NVM block,
while the APB interface is used for commands and configuration.
26.2
Features
•
•
•
•
•
•
•
•
•
•
•
•
26.3
32-bit AHB interface for reads and writes
Data Flash
All NVM sections are memory mapped to the AHB, including calibration and system configuration
32-bit APB interface for commands and control
Programmable wait states
16 regions can be individually protected or unprotected against erase and writes
Additional protection for bootloader against erase and writes
Supports device protection through a security bit
Supports permanent disabling of the Chip-Erase feature
Interface to Power Manager for power-down of Flash blocks in sleep modes
Can optionally wake up on exit from sleep or on first access
Direct-mapped cache for the main array and the Data Flash section
Block Diagram
Figure 26-1. Block Diagram
NVM Block
NVMCTRL
Calibration and
AHB
Auxillary Space
Cache
Data Flash array
NVM Interface
APB
Command and
Control
© 2021 Microchip Technology Inc.
and its subsidiaries
Main Array
Datasheet
DS60001638D-page 354
PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.4
Peripheral Dependencies
Peripheral
NVMCTRL
26.5
26.5.1
Base Address
0x41004000
AHB CLK
APB CLK
Generic CLK
PAC
Events
DMA
Enabled at reset
Enabled at reset
Index
Index
Prot at reset
User
Generator
Index
Y
Y
-
2
N
-
-
-
IRQ
Sleep Walking
6
Y
Functional Description
Principle of Operation
The NVM Controller is a client on the AHB and APB buses. It responds to commands, read requests and write
requests, based on user configuration.
26.5.1.1 Initialization
After power up, the NVM Controller goes through a power-up sequence. During this time, access to the NVM
Controller from the AHB bus is halted. Upon power-up completion, the NVM Controller is operational without any
need for user configuration.
26.5.2
Memory Organization
Refer to the Physical Memory Map for memory sizes and addresses for each device.
The NVM is organized into rows, where each row contains four pages, as shown in the NVM Row Organization
figure. One page is made of 64 bytes, that is sixteen 32bits words, or height 64bits double words. One row is made
of 4 pages, that is 256 bytes, or sixty four 32bits words, or sixteen 64bits double words. The NVM has a row-erase
granularity, while the write granularity is by page. In other words, a single row erase will erase all four pages in the
row, while four write operations are used to write the complete row.
Figure 26-2. NVM Row Organization
Row n
Page (n*4) + 3
Page (n*4) + 2
Page (n*4) + 1
Page (n*4) + 0
The NVM block contains a calibration and auxiliary space, a Data Flash section, and a main array that is memory
mapped. Refer to the NVM Organization figure below for details.
The calibration and auxiliary space contains factory calibration and system configuration information. These spaces
can be read from the AHB bus in the same way as the main NVM main address space.
In addition, the lower rows in the NVM main address space can be allocated as a boot loader section. Its size is
configured thanks to the BOOTPROT fuses (refer to Table 26-2) in the user row. Once BOOTPROT is defined and
after the next reboot, the content of the section becomes write-protected from the debugger or the processor write
accesses.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
Figure 26-3. NVM Memory Address Space
Calibration and
Auxillary Space
0x0080A100
0x00800000
0x00400000 + Data Flash Size
Data Flash
Address Space
0x00400000
0x00000000 + NVM Size
NVM Main
Address Space
0x00000000 + BOOTPROT Size
0x00000000
26.5.3
Region Lock Bits
The NVM main array is split into 16 equally sized regions. The region size is dependent on the Flash memory size,
and is given in the table below. Each region has a dedicated lock bit preventing writing and erasing pages in the
region. After production, all regions will be unlocked.
Table 26-1. Region Size
Memory Size [KB]
Region Size [KB]
128
8
64
4
To temporarily lock or unlock a region, the Lock Region and Unlock Region commands are provided. Writing one of
these commands will temporarily lock/unlock the region containing the address loaded in the ADDR register. ADDR
can be written by software, or the automatically loaded value from a write operation can be used. The new setting will
stay in effect until the next Reset, or until the setting is changed again using the Lock and Unlock commands. The
current status of the lock can be determined by reading the LOCK register.
To change the default lock/unlock setting for a region, the user configuration section of the auxiliary space must be
written using the Write Auxiliary Page command. Writing to the auxiliary space will take effect after the next Reset.
Therefore, a boot of the device is needed for changes in the lock/unlock setting to take effect. Refer to the Physical
Memory Map for calibration and auxiliary space address mapping.
Notes:
1. The Data Flash is outside of the regions lock bits range, and consequently cannot be write protected.
2. The boot loader section is write protected by the BOOTPROT fuse and by the lock bit(s) corresponding to its
address space.
26.5.4
Command and Data Interface
The NVM Controller is addressable from the APB bus, while the NVM main address space is addressable from the
AHB bus. Read and automatic page write operations are performed by addressing the NVM main address space or
© 2021 Microchip Technology Inc.
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
the Data Flash address space directly, while other operations such as manual page writes and row erases must be
performed by issuing commands through the NVM Controller.
To issue a command, the CTRLA.CMD bits must be written along with the CTRLA.CMDEX value. When a command
is issued, INTFLAG.READY will be cleared until the command has completed. Any commands written while
INTFLAG.READY is low will be ignored. Before entering any sleep mode, ensure any commands written to the
NVM controller have completed by confirming the INTFLAG.READY is '1'.
The CTRLB register must be used to control the power reduction mode, read wait states, and write mode.
26.5.4.1 NVM Read
Reading from the NVM main address space is performed via the AHB bus by addressing the NVM main address
space or auxiliary address space directly. Read data is available after the configured number of read wait states
(CTRLB.RWS) set in the NVM Controller.
The number of cycles data are delayed to the AHB bus is determined by the read wait states. Examples of using zero
and one wait states are shown in the following figure.
Reading the NVM main address space while a programming or erase operation is ongoing on the NVM main array
results in an AHB bus stall until the end of the operation. Reading the NVM main array does not stall the bus when
the Data Flash array is being programmed or erased.
Figure 26-4. Read Wait State Examples
0 Wait States
AHB Command
Rd 0
Idle
Rd 1
AHB Client Ready
AHB Client Data
Data 1
Data 0
1 Wait States
AHB Command
Rd 0
Idle
Rd 1
AHB Client Ready
AHB Client Data
Data 0
Data 1
26.5.4.2 Data Flash Read
Reading from the Data Flash address space is performed via the AHB bus by addressing the Data Flash address
space directly.
Read timings are similar to regular NVM read timings when access size is Byte or half-Word. The AHB data phase is
twice as long in case of full-Word-size access.
It is not possible to read the Data Flash area while the NVM main array is being written or erased, whereas the Data
Flash area can be written or erased while the main array is being read.
26.5.4.3 NVM Write
The NVM Controller requires that an erase must be done before programming. The entire NVM main address space
and the Data Flash address space can be erased by a debugger Chip Erase command. Alternatively, rows can be
individually erased by the Erase Row command or the Data Flash Erase Row command to erase the NVM main
address space or the Data Flash address space, respectively.
After programming the NVM main array, the region that the page resides in can be locked to prevent spurious write or
erase sequences. Locking is performed on a per-region basis, and so, locking a region will lock all pages inside the
region. Refer to Region Lock Bits for more information.
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
Data to be written to the NVM block are first written to and stored in an internal buffer called the page buffer. The
page buffer contains the same number of bytes as an NVM page. Writes to the page buffer must be 32 bits. 16-bit
and 8-bit writes to the page buffer are not allowed and will cause a system exception.
Internally, writes to the page buffer are on a 64-bit basis through the page buffer load data register (PBLDATA1 and
PBLDATA0). The PBLDATA register is a holding register for writes to the same 64-bit page buffer section. Data within
a 64-bit section can be written in any order. Crossing a 64-bit boundary will reset the PBLDATA register to all ones.
The following example assumes startup from reset where the current address is 0 and PBLDATA is all ones. Only 64
bits of the page buffer are written at a time, but 128 bits are shown for reference.
Sequential 32-bit Write Example:
• 32-bit 0x1 written to address 0
– Page buffer[127:0] = {0xFFFFFFFF_FFFFFFFF, PBLDATA[63:32], 0x00000001}
– PBLDATA[63:0] = {PBLDATA[63:32], 0x00000001}
• 32-bit 0x2 written to address 1
– Page buffer[127:0] = {0xFFFFFFFF_FFFFFFFF, 0x00000002, PBLDATA[31:0]}
– PBLDATA[63:0] = {0x00000002, PBLDATA[31:0]}
• 32-bit 0x3 written to address 2 (crosses 64-bit boundary)
– Page buffer[127:0] = 0xFFFFFFFF_00000003_00000002_00000001
– PBLDATA[63:0] = 0xFFFFFFFF_00000003
Random access writes to 32-bit words within the page buffer will overwrite the opposite word within the same 64-bit
section with ones. In the following example, notice that 0x00000001 is overwritten with 0xFFFFFFFF from the third
write due to the 64-bit boundary crossing. Only 64 bits of the page buffer are written at a time, but 128 bits are shown
for reference.
Random Access 32-bit Write Example:
• 32-bit 0x1 written to address 2
– Page buffer[127:0] = 0xFFFFFFFF_00000001_FFFFFFFF_FFFFFFFF
– PBLDATA[63:0] = 0xFFFFFFFF_00000001
• 32-bit 0x2 written to address 1
– Page buffer[127:0] = 0xFFFFFFFF_00000001_00000002_FFFFFFFF
– PBLDATA[63:0] = 0x00000002_FFFFFFFF
• 32-bit 0x3 written to address 3
– Page buffer[127:0] = 0x00000003_FFFFFFFF_00000002_FFFFFFFF
– PBLDATA[63:0] = 0x00000003_0xFFFFFFFF
Both the NVM main array and the Data Flash array share the same page buffer. Writing to the NVM block via
the AHB bus is performed by a load operation to the page buffer. For each AHB bus write, the address is stored
in the ADDR register. After the page buffer has been loaded with the required number of bytes, the page can be
written to the NVM main array or the Data Flash by setting CTRLA.CMD to 'Write Page' or 'Data Flash Write Page',
respectively, and setting the key value to CMDEX. The LOAD bit in the STATUS register indicates whether the page
buffer has been loaded or not. Before writing the page to memory, the accessed row must be erased.
Automatic page writes are enabled by writing the manual write bit to zero (CTRLB.MANW=0). This will trigger a write
operation to the page addressed by ADDR when the last location of the page is written.
Because the address is automatically stored in ADDR during the I/O bus write operation, the last given address will
be present in the ADDR register. There is no need to load the ADDR register manually, unless a different page in
memory is to be written.
26.5.4.3.1 Procedure for Manual Page Writes (CTRLB.MANW=1)
The row containing the page to be written must be erased before the write command is given.
•
•
•
Write to the page buffer by addressing the NVM main address space directly
Write the page buffer to memory: CTRL.CMD='Write Page' and CMDEX
The READY bit in the INTFLAG register will be low while programming is in progress, and access through the
AHB will be stalled
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.5.4.3.2 Procedure for Automatic Page Writes (CTRLB.MANW=0)
The row containing the page to be written must be erased before the last write to the page buffer is performed.
•
•
Write to the page buffer by addressing the NVM main address space directly.
When the last location in the page buffer is written, the page is automatically written to NVM main address
space. (Partial page writes are possible and require writing 0xFF in the remaining bytes of the page buffer)
INTFLAG.READY will be zero while programming is in progress and access through the AHB will be stalled.
26.5.4.4 Page Buffer Clear
The page buffer is automatically set to all '1' after a page write is performed. If the page buffer has been partially
written and if it is desired to clear its content, the Page Buffer Clear command can be used.
26.5.4.5 Erase Row
Before a page can be written, the row containing that page must be erased. The Erase Row command can be used
to erase the desired row in the NVM main address space. The Data Flash Erase Row command can be used to
erase the desired row in the Data Flash array. Erasing the row sets all bits to '1'. If the row resides in a region that is
locked, the erase will not be performed and the Lock Error bit in the Status register (STATUS.LOCKE) will be set.
26.5.4.5.1 Procedure for Erase Row
• Write the address of the row to erase to ADDR. Any address within the row can be used.
• Issue an Erase Row command.
Note: The NVM Address bit field in the Address register (ADDR.ADDR) uses 16-bit addressing.
26.5.4.6 Lock and Unlock Region
These commands are used to lock and unlock regions as detailed in section 26.5.3 Region Lock Bits.
26.5.4.7 Set and Clear Power Reduction Mode
The NVM Controller and block can be taken in and out of power reduction mode through the Set and Clear Power
Reduction Mode commands. When the NVM Controller and block are in power reduction mode, the Power Reduction
Mode bit in the Status register (STATUS.PRM) is set.
26.5.5
NVM User Configuration
The NVM user configuration resides in the auxiliary space. Refer to the Physical Memory Map of the device for
calibration and auxiliary space address mapping (Refer to 8.3 NVM User Row Mapping for more information).
The bootloader resides in the main array starting at offset zero. The allocated boot loader section is write-protected.
Table 26-2. Boot Loader Size
BOOTPROT [2:0]
Rows Protected by BOOTPROT
Boot Loader Size in Bytes
0x7(1)
None
0
0x6
2
512
0x5
4
1024
0x4
8
2048
0x3
16
4096
0x2
32
8192
0x1
64
16384
0x0
128
32768
Note:
1. Default value is 0x7.
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.5.6
Security Bit and Chip Erase Hard Lock Bit
The security bit allows the entire chip to be locked from external access for code security. The security bit can be
written by a dedicated command, Set Security Bit (SSB). Once set, the only way to clear the security bit is through a
debugger Chip Erase command. After issuing the SSB command, the STATUS.PROGE error bit can be checked.
In order to increase the security level it is recommended to enable the internal BODVDD when the security bit is set.
The CEHL bit allows to permanently disable the debugger chip erase feature. It can be written by a dedicated
command, Set Chip Erase Hard Lock (SCEHL). CEHL can only be set after the Security Bit has been set. This is a
permanent fuse, meaning that once it is set, it is set forever and cannot be reset anymore, therefore removing any
possibility to perform a chip erase, reprogram or debug the chip.
The four possible combinations of both bits and their implications are described as follows:
Security Bit = 0 and CEHL = 0:
•
•
•
•
Full debugger access is allowed
If a boot section has been defined in the user row BOOTPROT bit field, then this section is write and erase
protected (from the debugger and from the application code running on the target). Note that changes to
BOOTPROT are only taken into account after the next reset. Consequently, if a boot code was previously
programmed and secured with a BOOTPROT value, then in order to reprogram it and secure it again, the user
shall:
– Disable the boot section protection(BOOTPROT = 0xF) and reset the potentially related region lock bit(s)
– Reset the chip for the new BOOTPROT value to be taken into account
– Reprogram the boot section, protect it again by setting BOOTPROT to the appropriate value depending on
the boot code size
– Reset again
The application code (outside of the boot section) can be reprogrammed
A debugger chip erase is possible. It will erase the main array (even the potentially protected boot section), the
Data Flash, the volatile memory, and the Security Bit.
Note: The user row containing BOOTPROT is not reset by a debugger chip erase.
Security Bit = 0 and CEHL = 1: this combination is not possible, CEHL cannot be set when Security Bit=0. (This will
result in STATUS.PROGE being set)
Security Bit = 1 and CEHL = 0:
•
•
•
Once Security Bit is set, the only way to clear it is through a debugger chip erase
The debug access and actions are restricted in this mode (For more information, refer to the DSU Intellectual
Property Protection chapter and table 13-6):
– The debugger chip erase is possible
– The debugger is not allowed to read and dump the code and data contained in the Flash memory
– Programming (write/erase) of the Flash (boot code, application code, Data Flash section, auxiliary rows (in
particular BOOTPROT in the user row)) is not allowed. It will only be possible after a debugger chip erase,
when Security Bit is back to 0.
The boot and application codes running on the target have full read/write/erase access to the main array, Data
Flash section and user and auxiliary rows, except if a boot section is defined with BOOTPROT, in which case,
the boot section becomes write/erase protected from the boot code itself and from the application code.
Security Bit = 1 and CEHL = 1:
•
•
•
Once CEHL is set, it is not possible to reset it. This is a permanent fuse. The part is locked forever and there is
no way to come back.
The same as above still applies, except that chip erase functionality is disabled forever
CEHL status is visible in DSU STATUS2:CEHL
Defining a protected boot section, setting the Security Bit and the CEHL bit allows for a global secure boot solution
with an immutable boot loader section. The boot loader may for example embed public keys or certificates for
supporting secure boot loading algorithms or secure update of the main application code.
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Datasheet
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.5.7
Cache
The NVM Controller cache reduces the device power consumption and improves system performance when wait
states are required. The NVM main array and the Data Flash address spaces are cached. It is a direct-mapped cache
that implements 8 lines of 64 bits (i.e., 64 Bytes). NVM Controller cache can be enabled by writing a '0' to the Cache
Disable bit in the Control B register (CTRLB.CACHEDIS).
The cache can be configured to three different modes using the Read Mode bit group in the Control B register
(CTRLB.READMODE).
The INVALL command can be issued using the Command bits in the Control A register to invalidate all cache lines
(CTRLA.CMD = INVALL). Commands affecting NVM content automatically invalidate cache lines.
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.6
Register Summary
Offset
Name
Bit Pos.
0x00
CTRLA
7:0
15:8
0x02
...
0x03
Reserved
0x04
0x08
0x0C
0x10
CTRLB
PARAM
INTENCLR
INTENSET
0x14
INTFLAG
0x18
STATUS
0x1A
...
0x1B
Reserved
0x1C
ADDR
0x20
LOCK
0x22
...
0x27
Reserved
0x28
PBLDATA0
0x2C
PBLDATA1
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
7
5
4
3
2
1
0
CMD[6:0]
CMDEX[7:0]
MANW
RWS[3:0]
CACHEDIS[1:0]
SLEEPPRM[1:0]
READMODE[1:0]
NVMP[7:0]
NVMP[15:8]
DFP[3:0]
PSZ[2:0]
DFP[11:4]
NVME
LOCKE
7:0
15:8
23:16
31:24
7:0
15:8
ADDR[7:0]
ADDR[15:8]
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
PBLDATA[7:0]
PBLDATA[15:8]
PBLDATA[23:16]
PBLDATA[31:24]
PBLDATA[7:0]
PBLDATA[15:8]
PBLDATA[23:16]
PBLDATA[31:24]
© 2021 Microchip Technology Inc.
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6
PROGE
ERROR
READY
ERROR
READY
ERROR
READY
LOAD
PRM
SB
ADDR[21:16]
LOCK[7:0]
LOCK[15:8]
Datasheet
DS60001638D-page 362
PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.6.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
CTRLA
0x00
0x0000
PAC Write-Protection
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
4
R/W
0
R/W
0
R/W
0
Bit
Access
Reset
12
11
CMDEX[7:0]
R/W
R/W
0
0
3
CMD[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – CMDEX[7:0] Command Execution
When this bit group is written to the key value 0xA5, the command written to CMD will be executed. If a value
different from the key value is tried, the write will not be performed and the Programming Error bit in the Status
register (STATUS.PROGE) will be set. PROGE is also set if a previously written command is not completed yet.
The key value must be written at the same time as CMD. If a command is issued through the APB bus on the same
cycle as an AHB bus access, the AHB bus access will be given priority. The command will then be executed when
the NVM block and the AHB bus are idle.
INTFLAG.READY must be '1' when the command is issued.
Bit 0 of the CMDEX bit group will read back as '1' until the command is issued.
Note: The NVM Address bit field in the Address register (ADDR.ADDR) uses 16-bit addressing.
Bits 6:0 – CMD[6:0] Command
These bits define the command to be executed when the CMDEX key is written.
CMD[6:0]
Group
Configuration
0x00-0x01 0x02
ER
0x03
0x04
WP
0x05
EAR
0x06
WAP
0x07-0x19 0x1A
DFER
0x1B
0x1C
DFWP
0x1D-0x3F 0x40
LR
0x41
UR
© 2021 Microchip Technology Inc.
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Description
Reserved
Erase Row - Erases the row addressed by the ADDR register in the NVM main
array.
Reserved
Write Page - Writes the contents of the page buffer to the page addressed by the
ADDR register.
Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register.
This command can be given only when the Security bit is not set and only to the
User Configuration Row.
Write Auxiliary Page - Writes the contents of the page buffer to the page
addressed by the ADDR register. This command can be given only when the
Security bit is not set and only to the User Configuration Row.
Reserved
Data Flash Erase Row - Erases the row addressed by the ADDR register in the
Data Flash.
Reserved
Data Flash Write Page - Writes the contents of the page buffer to the page
addressed by the ADDR register in the Data Flash.
Reserved
Lock Region - Locks the region containing the address location in the ADDR
register.
Unlock Region - Unlocks the region containing the address location in the ADDR
register.
Datasheet
DS60001638D-page 363
PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
...........continued
CMD[6:0]
Group
Configuration
Description
0x42
0x43
0x44
0x45
0x46
0x47-0x7E
0x7F
SPRM
CPRM
PBC
SSB
INVALL
SCEHL
Sets the Power Reduction mode.
Clears the Power Reduction mode.
Page Buffer Clear - Clears the page buffer.
Set Security Bit - Sets the Security bit.
Invalidates all cache lines.
Reserved
Set Chip Erase Hard Lock. Sets the CEHL bit and permanently disables the
Chip-Erase feature. This command can only be issued once the Security Bit
has been set with the SSB command. Once set, it is not possible to erase it
anymore.
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.6.2
Control B
Name:
Offset:
Reset:
Property:
Bit
CTRLB
0x04
0x00000080
PAC Write-Protection
31
30
29
28
27
23
22
21
20
15
14
13
12
11
7
MANW
R/W
1
6
5
4
3
26
25
24
Access
Reset
Bit
Access
Reset
Bit
19
18
CACHEDIS[1:0]
R/W
R/W
0
0
10
Access
Reset
Bit
Access
Reset
17
16
READMODE[1:0]
R/W
R/W
0
0
9
8
SLEEPPRM[1:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
RWS[3:0]
R/W
0
R/W
0
Bits 19:18 – CACHEDIS[1:0] Cache Disable
This bit is used to disable the cache.
Value
Description
0x3
The Data Flash cache is enabled, the main array cache is disabled
0x2
The Data Flash cache is enabled, the main array cache is enabled
0x1
The Data Flash cache is disabled, the main array cache is disabled
0x0
The Data Flash cache is disabled, the main array cache is enabled
Bits 17:16 – READMODE[1:0] NVMCTRL Read Mode
Value
Name
Description
0x0
NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a cache
miss. Gives the best system performance.
0x1
LOW_POWER
Reduces power consumption of the cache system, but inserts a wait state each
time there is a cache miss. This mode may not be relevant if CPU performance
is required, as the application will be stalled and may lead to increased run
time.
0x2
DETERMINISTIC
The cache system ensures that a cache hit or miss takes the same amount
of time, determined by the number of programmed Flash wait states. This
mode can be used for real-time applications that require deterministic execution
timings.
0x3
Reserved
Bits 9:8 – SLEEPPRM[1:0] Power Reduction Mode during Sleep
Indicates the Power Reduction Mode during sleep.
Value
Name
Description
0x0
WAKEONACCESS
NVM block enters low-power mode when entering sleep.
NVM block exits low-power mode upon first access.
0x1
WAKEUPINSTANT
NVM block enters low-power mode when entering sleep.
NVM block exits low-power mode when exiting sleep.
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Datasheet
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
Value
0x2
0x3
Name
Reserved
DISABLED
Description
Auto power reduction disabled.
Bit 7 – MANW Manual Write
Note that reset value of this bit is '1'.
Value
Description
0
Writing to the last word in the page buffer will initiate a write operation to the page addressed by the
last write operation. This includes writes to memory and auxiliary rows.
1
Write commands must be issued through the CTRLA.CMD register.
Bits 4:1 – RWS[3:0] NVM Read Wait States
These bits control the number of wait states for a read operation. '0' indicates zero wait states, '1' indicates one wait
state, etc., up to 15 wait states.
This register is initialized to 0 wait states. Software can change this value based on the NVM access time and system
frequency. Refer to NVM Max Speed Characteristics in the 43. Electrical Characteristics 85℃ chapter.
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.6.3
NVM Parameter
Name:
Offset:
Reset:
Property:
Bit
PARAM
0x08
0x000XXXXX
PAC Write-Protection
31
30
29
28
27
26
25
24
DFP[11:4]
Access
Reset
R
0
R
0
Bit
23
22
R
0
R
0
R
0
R
0
R
0
R
0
21
20
19
18
16
R
x
17
PSZ[2:0]
R
x
11
10
9
8
R
x
R
x
R
x
R
x
3
2
1
0
R
x
R
x
R
x
R
x
DFP[3:0]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
R
x
NVMP[15:8]
Access
Reset
R
x
R
x
R
x
R
x
Bit
7
6
5
4
NVMP[7:0]
Access
Reset
R
x
R
x
R
x
R
x
Bits 31:20 – DFP[11:0] Data Flash Pages
Indicates the number of pages in the Data Flash section.
Bits 18:16 – PSZ[2:0] Page Size
Indicates the page size. Not all devices of the device families will provide all the page sizes indicated in the table.
Value
Name
Description
0x0
8
8 bytes
0x1
16
16 bytes
0x2
32
32 bytes
0x3
64
64 bytes
0x4
128
128 bytes
0x5
256
256 bytes
0x6
512
512 bytes
0x7
1024
1024 bytes
Bits 15:0 – NVMP[15:0] NVM Pages
Indicates the number of pages in the NVM main array.
© 2021 Microchip Technology Inc.
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.6.4
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x0C
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ERROR
R/W
0
0
READY
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – ERROR Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the ERROR interrupt enable.
This bit will read as the current value of the ERROR interrupt enable.
Bit 0 – READY NVM Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the READY interrupt enable.
This bit will read as the current value of the READY interrupt enable.
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.6.5
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x10
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ERROR
R/W
0
0
READY
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – ERROR Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit sets the ERROR interrupt enable.
This bit will read as the current value of the ERROR interrupt enable.
Bit 0 – READY NVM Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit sets the READY interrupt enable.
This bit will read as the current value of the READY interrupt enable.
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.6.6
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
INTFLAG
0x14
0x00
–
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ERROR
R/W
0
0
READY
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – ERROR Error
This flag is set on the occurrence of an NVME, LOCKE or PROGE error.
This bit can be cleared by writing a '1' to its bit location.
Value
Description
0
No errors have been received since the last clear.
1
At least one error has occurred since the last clear.
Bit 0 – READY NVM Ready
Value
Description
0
The NVM controller is busy programming or erasing.
1
The NVM controller is ready to accept a new command.
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.6.7
Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x18
0x0X00
–
15
14
13
12
11
10
9
8
SB
R
x
7
6
5
4
NVME
R/W
0
3
LOCKE
R/W
0
2
PROGE
R/W
0
1
LOAD
R/W
0
0
PRM
R
0
Access
Reset
Bit
Access
Reset
Bit 8 – SB Security Bit Status
Important: Once set, this bit can only be cleared by a debugger chip erase.
Value
0
1
Description
The Security bit is inactive.
The Security bit is active.
Bit 4 – NVME NVM Error
This bit can be cleared by writing a '1' to its bit location.
Value
Description
0
No programming or erase errors have been received from the NVM controller since this bit was last
cleared.
1
At least one error has been registered from the NVM Controller since this bit was last cleared.
Bit 3 – LOCKE Lock Error Status
This bit can be cleared by writing a '1' to its bit location.
Value
Description
0
No programming of any locked lock region has happened since this bit was last cleared.
1
Programming of at least one locked lock region has happened since this bit was last cleared.
Bit 2 – PROGE Programming Error Status
This bit can be cleared by writing a '1' to its bit location.
Value
Description
0
No invalid commands or bad keywords were written in the NVM Command register since this bit was
last cleared.
1
An invalid command and/or a bad keyword was/were written in the NVM Command register since this
bit was last cleared.
Bit 1 – LOAD NVM Page Buffer Active Loading
This bit indicates that the NVM page buffer has been loaded with one or more words. Immediately after an NVM load
has been performed, this flag is set. It remains set until a page write or a page buffer clear (PBCLR) command is
given.
This bit can be cleared by writing a '1' to its bit location.
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
Bit 0 – PRM Power Reduction Mode
This bit indicates the current NVM power reduction state. The NVM block can be set in power reduction mode in two
ways: through the command interface or automatically when entering sleep with SLEEPPRM set accordingly.
PRM can be cleared in three ways: through AHB access to the NVM block, through the command interface (SPRM
and CPRM) or when exiting sleep with SLEEPPRM set accordingly.
Value
Description
0
NVM is not in power reduction mode.
1
NVM is in power reduction mode.
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.6.8
Address
Name:
Offset:
Reset:
Property:
Bit
ADDR
0x1C
0x00000000
PAC Write-Protection
31
30
29
28
27
23
22
21
20
19
R/W
0
R/W
0
13
12
26
25
24
17
16
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
15
14
18
ADDR[21:16]
R/W
R/W
0
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ADDR[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 21:0 – ADDR[21:0] NVM Address
ADDR drives the hardware (16-bit) address to the NVM when a command is executed using CMDEX. This register is
also automatically updated when writing to the page buffer.
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.6.9
Lock Section
Name:
Offset:
Reset:
Property:
Bit
LOCK
0x20
X determined from NVM User Row
–
15
14
13
12
11
10
9
8
R
x
R
x
R
x
R
x
3
2
1
0
R
x
R
x
R
x
R
x
LOCK[15:8]
Access
Reset
R
x
R
x
R
x
R
x
Bit
7
6
5
4
LOCK[7:0]
Access
Reset
R
x
R
x
R
x
R
x
Bits 15:0 – LOCK[15:0] Region Lock Bits
To set or clear these bits, the CMD register must be used.
Default state after erase will be unlocked (0xFFFF).
Value
Description
0
The corresponding lock region is locked.
1
The corresponding lock region is not locked.
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.6.10 Page Buffer Load Data 0
Name:
Offset:
Reset:
Property:
PBLDATA0
0x28
0xFFFFFFFF
-
Bit
31
30
29
28
27
PBLDATA[31:24]
R
R
1
1
26
25
24
Access
Reset
R
1
R
1
R
1
R
1
R
1
R
1
Bit
23
22
21
20
19
PBLDATA[23:16]
R
R
1
1
18
17
16
Access
Reset
R
1
R
1
R
1
R
1
R
1
R
1
Bit
15
14
13
10
9
8
R
1
12
11
PBLDATA[15:8]
R
R
1
1
Access
Reset
R
1
R
1
R
1
R
1
R
1
Bit
7
6
5
4
3
2
1
0
R
1
R
1
R
1
R
1
PBLDATA[7:0]
Access
Reset
R
1
R
1
R
1
R
1
Bits 31:0 – PBLDATA[31:0] Page Buffer Load Data
The PBLDATA register is a holding register for partial AHB writes to the same 64-bit page buffer section. Page buffer
loads are performed on a 64-bit basis.
This is a read only register.
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PIC32CM MC00 Family
Nonvolatile Memory Controller (NVMCTRL)
26.6.11 Page Buffer Load Data 1
Name:
Offset:
Reset:
Property:
PBLDATA1
0x2C
0xFFFFFFFF
-
Bit
31
30
29
28
27
PBLDATA[31:24]
R
R
1
1
26
25
24
Access
Reset
R
1
R
1
R
1
R
1
R
1
R
1
Bit
23
22
21
20
19
PBLDATA[23:16]
R
R
1
1
18
17
16
Access
Reset
R
1
R
1
R
1
R
1
R
1
R
1
Bit
15
14
13
10
9
8
R
1
12
11
PBLDATA[15:8]
R
R
1
1
Access
Reset
R
1
R
1
R
1
R
1
R
1
Bit
7
6
5
4
3
2
1
0
R
1
R
1
R
1
R
1
PBLDATA[7:0]
Access
Reset
R
1
R
1
R
1
R
1
Bits 31:0 – PBLDATA[31:0] Page Buffer Load Data (Bits 63:32])
The PBLDATA register is a holding register for partial AHB writes to the same 64-bit page buffer section. Page buffer
loads are performed on a 64-bit basis.
This is a read only register.
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PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.
I/O Pin Controller (PORT)
27.1
Overview
The I/O Pin Controller (PORT) controls the I/O pins of the device. The I/O pins are organized in a series of groups,
collectively referred to as a PORT group. Each PORT group can have up to 32 pins that can be configured and
controlled individually or as a group. The number of PORT groups on a device may depend on the package/number
of pins. Each pin may either be used for general-purpose I/O under direct application control or be assigned to an
embedded device peripheral. When used for general-purpose I/O, each pin can be configured as input or output, with
highly configurable driver and pull settings.
All I/O pins have true read-modify-write functionality when used for general-purpose I/O; the direction or the output
value of one or more pins may be changed (set, reset or toggled) explicitly without unintentionally changing the state
of any other pins in the same port group by a single, atomic 8-, 16- or 32-bit write.
The PORT is connected to the high-speed bus matrix through an AHB/APB bridge. The Pin Direction, Data Output
Value and Data Input Value registers may also be accessed using the low-latency CPU local bus (IOBUS; ARM®
single-cycle I/O port).
27.2
Features
•
•
•
•
•
•
Selectable Input and Output Configuration for Each Individual Pin
Software-controlled Multiplexing of Peripheral Functions on I/O Pins
Flexible Pin Configuration Through a Dedicated Pin Configuration Register
Configurable Output Driver and Pull Settings:
– Totem-pole (push-pull)
– Pull configuration
– Driver strength
Configurable Input Buffer and Pull Settings:
– Internal pull-up or pull-down
– Input sampling criteria
– Input buffer can be disabled if not needed for lower power consumption
– Read-Modify-Write support for output value (OUTCLR/OUTSET/OUTTGL) and pin direction (DIRCLR/
DIRSET/DIRTGL)
Input Event:
– Up to four input event pins for each PORT group
– SET/CLEAR/TOGGLE event actions for each event input on output value of a pin
– Can be output to pin
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PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.3
Block Diagram
Figure 27-1. PORT Block Diagram
PORT
Peripheral Mux Select
Control
and
Port Line
Bundles
Status
Pad Line
Bundles
I/O
PADS
PORTMUX
IP Line Bundles
PERIPHERALS
Analog Pad
Connections
Digital Controls of Analog Blocks
27.4
ANALOG
BLOCKS
Signal Description
Table 27-1. Signal description for PORT
Signal name
Type
Description
Pxy
Digital I/O
General-purpose I/O pin y in group x
Refer to the Pinout for details on the pin mapping for this peripheral. One signal can be mapped on several pins.
27.5
Peripheral
PORT
Peripheral Dependencies
Base Address
0x41000000
AHB CLK
APB CLK
Generic CLK
PAC
Events
DMA
Enabled at reset
Enabled at reset
Index
Index
Prot at reset
User
Generator
Index
-
Y
-
0
N
1-4: EV0-3
-
-
IRQ
-
Sleep Walking
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PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.6
Functional Description
Figure 27-2. Overview of the PORT
PORT
PAD
PULLEN
PULLENx
DRIVE
DRIVEx
Pull
Resistor
PG
OUT
OUTx
PAD
APB Bus
VDD
OE
DIRx
NG
INEN
INENx
IN
INx
Q
D
R
Q
D
R
Synchronizer
Input to Other Modules
27.6.1
Analog Input/Output
Principle of Operation
Each PORT group of up to 32 pins is controlled by the registers in PORT, as described in the figure. These registers
in PORT are duplicated for each PORT group, with increasing base addresses using an offset of 0x80 between
groups. The number of PORT groups may depend on the package/number of pins.
Figure 27-3. Overview of the peripheral functions multiplexing
PORTMUX
PORT bit y
Port y PINCFG
PMUXEN
Port y
Data+Config
Port y
PMUX[3:0]
Port y Peripheral
Mux Enable
Port y Line Bundle
0
Port y PMUX Select
Pad y
PAD y
Line Bundle
Periph Signal 0
0
Periph Signal 1
1
1
Peripheral Signals to
be muxed to Pad y
Periph Signal 15
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PIC32CM MC00 Family
I/O Pin Controller (PORT)
The I/O pins of the device are controlled by PORT peripheral registers. Each port pin has a corresponding bit in the
Data Direction (DIR) and Data Output Value (OUT) registers to enable that pin as an output and to define the output
state.
The direction of each pin in a PORT group is configured by the DIR register. If a bit in DIR is set to '1', the
corresponding pin is configured as an output pin. If a bit in DIR is set to '0', the corresponding pin is configured as an
input pin.
When the direction is set as output, the corresponding bit in the OUT register will set the level of the pin. If bit y in
OUT is written to '1', pin y is driven HIGH. If bit y in OUT is written to '0', pin y is driven LOW. Pin configuration can be
set by Pin Configuration (PINCFGy) registers, with y=00, 01, ..31 representing the pin position within the group.
The Data Input Value (IN) is set as the input value of a port pin with resynchronization to the PORT clock. To reduce
power consumption, these input synchronizers can be clocked only when system requires reading the input value, as
specified in the SAMPLING field of the Control register (CTRL). The value of the pin can always be read, whether the
pin is configured as input or output. If the Input Enable bit in the Pin Configuration registers (PINCFGy.INEN) is '0',
the input value will not be sampled.
In PORT, the Peripheral Multiplexer Enable bit in the PINCFGy register (PINCFGy.PMUXEN) can be written to '1' to
enable the connection between peripheral functions and individual I/O pins. The Peripheral Multiplexing n (PMUXn)
registers select the peripheral function for the corresponding pin. This will override the connection between the PORT
and that I/O pin, and connect the selected peripheral signal to the particular I/O pin instead of the PORT line bundle.
27.6.2
Basic Operation
27.6.2.1 Initialization
After reset, all standard function device I/O pads are connected to the PORT with outputs tri-stated and input buffers
disabled, even if there is no clock running.
However, specific pins, such as those used for connection to a debugger, may be configured differently, as required
by their special function.
27.6.2.2 Operation
Each I/O pin Pxy can be controlled by the registers in PORT. Each PORT group x has its own set of PORT registers,
with a base address at byte address (PORT + 0x80 * group index) (A corresponds to group index 0, B to 1, etc...).
Within that set of registers, the pin index is y, from 0 to 31.
Refer to the 4. Pinout and Packaging for details on available pin configuration and PORT groups.
Configuring Pins as Output
To use pin Pxy as an output, write bit y of the DIR register to '1'. This can also be done by writing bit y in the DIRSET
register to '1' - this will avoid disturbing the configuration of other pins in that group. The y bit in the OUT register must
be written to the desired output value.
Similarly, writing an OUTSET bit to '1' will set the corresponding bit in the OUT register to '1'. Writing a bit in OUTCLR
to '1' will set that bit in OUT to zero. Writing a bit in OUTTGL to '1' will toggle that bit in OUT.
Configuring Pins as Input
To use pin Pxy as an input, bit y in the DIR register must be written to '0'. This can also be done by writing bit y in the
DIRCLR register to '1' - this will avoid disturbing the configuration of other pins in that group. The input value can be
read from bit y in register IN as soon as the INEN bit in the Pin Configuration register (PINCFGy.INEN) is written to
'1'.
By default, the input synchronizer is clocked only when an input read is requested. This will delay the read operation
by two cycles of the PORT clock. To remove the delay, the input synchronizers for each PORT group of eight pins
can be configured to be always active, but this will increase power consumption. This is enabled by writing '1' to the
corresponding SAMPLINGn bit field of the CTRL register, see CTRL.SAMPLING for details.
Using Alternative Peripheral Functions
To use pin Pxy as one of the available peripheral functions, the corresponding PMUXEN bit of the PINCFGy register
must be '1'. The PINCFGy register for pin Pxy is at byte offset (PINCFG0 + y).
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PIC32CM MC00 Family
I/O Pin Controller (PORT)
The peripheral function can be selected by setting the PMUXO or PMUXE in the PMUXn register. The PMUXO/
PMUXE is at byte offset PMUX0 + (y/2). The chosen peripheral must also be configured and enabled.
27.6.3
I/O Pin Configuration
The Pin Configuration register (PINCFGy) is used for additional I/O pin configuration. A pin can be set in a totem-pole
or pull configuration.
As pull configuration is done through the Pin Configuration register, all intermediate PORT states during switching of
pin direction and pin values are avoided.
The I/O pin configurations are described further in this chapter, and summarized in Table 27-2.
27.6.3.1 Pin Configurations Summary
Table 27-2. Pin Configurations Summary
DIR
INEN
PULLEN
OUT
Configuration
0
0
0
X
Reset or analog I/O: all digital disabled
0
0
1
0
Pull-down; input buffer disabled
0
0
1
1
Pull-up; input buffer disabled
0
1
0
X
Input
0
1
1
0
Input with pull-down
0
1
1
1
Input with pull-up
1
0
X
X
Output; input buffer disabled
1
1
X
X
Output; input enabled
27.6.3.2 Input Configuration
Figure 27-4. I/O configuration - Standard Input
PULLEN
PULLEN
INEN
DIR
0
1
0
PULLEN
INEN
DIR
1
1
0
DIR
OUT
IN
INEN
Figure 27-5. I/O Configuration - Input with Pull
PULLEN
DIR
OUT
IN
INEN
Note: When pull is enabled, the pull value is defined by the OUT value.
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PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.6.3.3 Totem-Pole Output
When configured for totem-pole (push-pull) output, the pin is driven low or high according to the corresponding bit
setting in the OUT register. In this configuration there is no current limitation for sink or source other than what the pin
is capable of. If the pin is configured for input, the pin will float if no external pull is connected.
Note: Enabling the output driver will automatically disable pull.
Figure 27-6. I/O Configuration - Totem-Pole Output with Disabled Input
PULLEN
PULLEN
INEN
DIR
0
0
1
PULLEN
INEN
DIR
0
1
1
PULLEN
INEN
DIR
1
0
0
DIR
OUT
IN
INEN
Figure 27-7. I/O Configuration - Totem-Pole Output with Enabled Input
PULLEN
DIR
OUT
IN
INEN
Figure 27-8. I/O Configuration - Output with Pull
PULLEN
DIR
OUT
IN
INEN
27.6.3.4 Digital Functionality Disabled
Neither Input nor Output functionality are enabled.
Figure 27-9. I/O Configuration - Reset or Analog I/O: Digital Output, Input and Pull Disabled
PULLEN
PULLEN
INEN
DIR
0
0
0
DIR
OUT
IN
INEN
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PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.6.4
Events
The PORT allows input events to control individual I/O pins. These input events are generated by the EVSYS module
and can originate from a different clock domain than the clock domain of the PORT module.
The PORT can perform the following actions:
•
•
•
•
Output (OUT): I/O pin will be set when the incoming event has a high level ('1') and cleared when the incoming
event has a low-level ('0').
Set (SET): I/O pin will be set when an incoming event is detected.
Clear (CLR): I/O pin will be cleared when an incoming event is detected.
Toggle (TGL): I/O pin will toggle when an incoming event is detected.
The OUTPUT event is sent to the pin without any internal latency. For SET, CLEAR and TOGGLE event actions, the
action will be executed up to three clock cycles after a rising edge.
The event actions can be configured with the Event Action m bit group in the Event Input Control
register( EVCTRL.EVACTm). Writing a '1' to a PORT Event Enable Input m of the Event Control register
(EVCTRL.PORTEIm) enables the corresponding action on input event. Writing '0' to this bit disables the
corresponding action on input event. Note that several actions can be enabled for incoming events. If several events
are connected to the peripheral, any enabled action will be taken for any of the incoming events. Refer to EVSYS –
Event System. for details on configuring the Event System.
Each event input can address one and only one I/O pin at a time. The selection of the pin is indicated by the
PORT Event Pin Identifier of the Event Input Control register (EVCTR.PIDn). On the other hand, one I/O pin can be
addressed by up to four different input events. To avoid action conflict on the output value of the register (OUT) of this
particular I/O pin, only one action is performed according to the table below.
Note that this truth table can be applied to any SET/CLR/TGL configuration from two to four active input events.
Table 27-3. Priority on Simultaneous SET/CLR/TGL Event Actions
EVACT0
EVACT1
EVACT2
EVACT3
Executed Event Action
SET
SET
SET
SET
SET
CLR
CLR
CLR
CLR
CLR
All Other Combinations
TGL
Be careful when the event is output to pin. Due to the fact the events are received asynchronously, the I/O pin may
have unpredictable levels, depending on the timing of when the events are received. When several events are output
to the same pin, the lowest event line will get the access. All other events will be ignored.
27.6.5
PORT Access Priority
The PORT is accessed by the following systems:
•
•
•
The Arm CPU through the Arm single-cycle I/O port (IOBUS)
The Arm CPU through the high-speed matrix and the AHB/APB bridge (APB)
EVSYS through four asynchronous input events
The CPU local bus (IOBUS) is an interface that connects the CPU to the PORT. It is a single-cycle bus interface,
which does not support wait states. It supports 8-bit, 16-bit and 32-bit sizes.
This bus is generally used for low-latency operation. The Data Direction (DIR) and Data Output Value (OUT) registers
can be read, write, set, cleared or toggled using this bus, and the Data Input Value (IN) registers can be read.
Because the IOBUS cannot wait for the IN register resynchronization, the Control register (CTRL) must be configured
to continuous sampling of all pins that need to be read through the IOBUS to prevent stale data from being read.
IOBUS writes are not prevented to PAC write-protected registers when the PORT module is PAC protected.
Note: Refer to 7. Product Mapping for the PORT IOBUS address.
The following priority is adopted:
1.
Arm CPU IOBUS (No wait tolerated)
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 383
PIC32CM MC00 Family
I/O Pin Controller (PORT)
2.
3.
APB
EVSYS input events, except for events with EVCTRL.EVACTx = OUT, where the output pin follows the event
input signal, independently of the OUT register value.
Note: One clock cycle latency can be observed on the APB access in case of concurrent PORT accesses.
For input events that require different actions on the same I/O pin, refer to 27.6.4 Events.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 384
PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.7
Register Summary
The I/O pins are assembled in pin groups with up to 32 pins. Group 0 consists of the PA pins, and group 1 is for
the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing between groups. For
example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the
register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.
Offset
Name
Bit Pos.
0x2C
EVCTRL
0x30
...
0x3F
0x40
PMUX0
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
PMUX15
PINCFG0
7:0
7:0
0x00
DIR
0x04
DIRCLR
0x08
DIRSET
0x0C
DIRTGL
0x10
OUT
0x14
OUTCLR
0x18
OUTSET
0x1C
OUTTGL
0x20
IN
0x24
CTRL
0x28
WRCONFIG
7
5
4
3
2
1
0
DIR[7:0]
DIR[15:8]
DIR[23:16]
DIR[31:24]
DIRCLR[7:0]
DIRCLR[15:8]
DIRCLR[23:16]
DIRCLR[31:24]
DIRSET[7:0]
DIRSET[15:8]
DIRSET[23:16]
DIRSET[31:24]
DIRTGL[7:0]
DIRTGL[15:8]
DIRTGL[23:16]
DIRTGL[31:24]
OUT[7:0]
OUT[15:8]
OUT[23:16]
OUT[31:24]
OUTCLR[7:0]
OUTCLR[15:8]
OUTCLR[23:16]
OUTCLR[31:24]
OUTSET[7:0]
OUTSET[15:8]
OUTSET[23:16]
OUTSET[31:24]
OUTTGL[7:0]
OUTTGL[15:8]
OUTTGL[23:16]
OUTTGL[31:24]
IN[7:0]
IN[15:8]
IN[23:16]
IN[31:24]
SAMPLING[7:0]
SAMPLING[15:8]
SAMPLING[23:16]
SAMPLING[31:24]
PINMASK[7:0]
PINMASK[15:8]
HWSEL
PORTEI0
PORTEI1
PORTEI2
PORTEI3
© 2021 Microchip Technology Inc.
and its subsidiaries
6
DRVSTR
WRPINCFG
EVACT0[1:0]
EVACT1[1:0]
EVACT2[1:0]
EVACT3[1:0]
PMUXO[3:0]
WRPMUX
PMUXO[3:0]
DRVSTR
PULLEN
INEN
PMUX[3:0]
PID0[4:0]
PID1[4:0]
PID2[4:0]
PID3[4:0]
PMUXE[3:0]
PMUXE[3:0]
PULLEN
INEN
Datasheet
PMUXEN
PMUXEN
DS60001638D-page 385
PIC32CM MC00 Family
I/O Pin Controller (PORT)
...........continued
Offset
Name
Bit Pos.
...
0x5F
PINCFG31
7:0
7
© 2021 Microchip Technology Inc.
and its subsidiaries
6
5
4
DRVSTR
Datasheet
3
2
1
0
PULLEN
INEN
PMUXEN
DS60001638D-page 386
PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.7.1
Data Direction
Name:
Offset:
Reset:
Property:
DIR
0x00
0x00000000
PAC Write-Protection
This register allows the user to configure one or more I/O pins as an input or output. This register can be manipulated
without doing a read-modify-write operation by using the Data Direction Toggle (DIRTGL), Data Direction Clear
(DIRCLR) and Data Direction Set (DIRSET) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
28
27
26
25
24
RW
0
RW
0
RW
0
RW
0
19
18
17
16
RW
0
RW
0
RW
0
RW
0
11
10
9
8
RW
0
RW
0
RW
0
RW
0
3
2
1
0
RW
0
RW
0
RW
0
RW
0
DIR[31:24]
Access
Reset
RW
0
RW
0
RW
0
RW
0
Bit
23
22
21
20
DIR[23:16]
Access
Reset
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
DIR[15:8]
Access
Reset
Bit
RW
0
RW
0
RW
0
RW
0
7
6
5
4
DIR[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
Bits 31:0 – DIR[31:0] Port Data Direction
These bits set the data direction for the individual I/O pins in the PORT group.
Value
Description
0
The corresponding I/O pin in the PORT group is configured as an input.
1
The corresponding I/O pin in the PORT group is configured as an output.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 387
PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.7.2
Data Direction Clear
Name:
Offset:
Reset:
Property:
DIRCLR
0x04
0x00000000
PAC Write-Protection
This register allows the user to set one or more I/O pins as an input, without doing a read-modify-write operation.
Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data
Direction Set (DIRSET) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
Access
Reset
RW
0
RW
0
RW
0
Bit
23
22
21
Access
Reset
RW
0
RW
0
RW
0
Bit
15
14
13
Access
Reset
RW
0
RW
0
RW
0
7
6
5
RW
0
RW
0
RW
0
Bit
Access
Reset
28
27
DIRCLR[31:24]
RW
RW
0
0
20
19
DIRCLR[23:16]
RW
RW
0
0
12
11
DIRCLR[15:8]
RW
RW
0
0
4
3
DIRCLR[7:0]
RW
RW
0
0
26
25
24
RW
0
RW
0
RW
0
18
17
16
RW
0
RW
0
RW
0
10
9
8
RW
0
RW
0
RW
0
2
1
0
RW
0
RW
0
RW
0
Bits 31:0 – DIRCLR[31:0] Port Data Direction Clear
Writing a '0' to a bit has no effect.
Writing a '1' to a bit will clear the corresponding bit in the DIR register, which configures the I/O pin as an input.
Value
Description
0
The corresponding I/O pin in the PORT group will keep its configuration.
1
The corresponding I/O pin in the PORT group is configured as input.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 388
PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.7.3
Data Direction Set
Name:
Offset:
Reset:
Property:
DIRSET
0x08
0x00000000
PAC Write-Protection
This register allows the user to set one or more I/O pins as an output, without doing a read-modify-write operation.
Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data
Direction Clear (DIRCLR) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
Access
Reset
RW
0
RW
0
RW
0
Bit
23
22
21
Access
Reset
RW
0
RW
0
Bit
15
Access
Reset
Bit
28
27
DIRSET[31:24]
RW
RW
0
0
26
25
24
RW
0
RW
0
RW
0
18
17
16
RW
0
20
19
DIRSET[23:16]
RW
RW
0
0
RW
0
RW
0
RW
0
14
13
12
10
9
8
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
7
6
5
3
2
1
0
RW
0
RW
0
RW
0
RW
0
11
DIRSET[15:8]
RW
RW
0
0
4
DIRSET[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
Bits 31:0 – DIRSET[31:0] Port Data Direction Set
Writing '0' to a bit has no effect.
Writing '1' to a bit will set the corresponding bit in the DIR register, which configures the I/O pin as an output.
Value
Description
0
The corresponding I/O pin in the PORT group will keep its configuration.
1
The corresponding I/O pin in the PORT group is configured as an output.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 389
PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.7.4
Data Direction Toggle
Name:
Offset:
Reset:
Property:
DIRTGL
0x0C
0x00000000
PAC Write-Protection
This register allows the user to toggle the direction of one or more I/O pins, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Set (DIRSET) and
Data Direction Clear (DIRCLR) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
Access
Reset
RW
0
RW
0
RW
0
Bit
23
22
21
Access
Reset
RW
0
RW
0
Bit
15
Access
Reset
Bit
28
27
DIRTGL[31:24]
RW
RW
0
0
26
25
24
RW
0
RW
0
RW
0
18
17
16
RW
0
20
19
DIRTGL[23:16]
RW
RW
0
0
RW
0
RW
0
RW
0
14
13
12
10
9
8
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
7
6
5
3
2
1
0
RW
0
RW
0
RW
0
RW
0
11
DIRTGL[15:8]
RW
RW
0
0
4
DIRTGL[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
Bits 31:0 – DIRTGL[31:0] Port Data Direction Toggle
Writing '0' to a bit has no effect.
Writing '1' to a bit will toggle the corresponding bit in the DIR register, which reverses the direction of the I/O pin.
Value
Description
0
The corresponding I/O pin in the PORT group will keep its configuration.
1
The direction of the corresponding I/O pin is toggled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 390
PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.7.5
Data Output Value
Name:
Offset:
Reset:
Property:
OUT
0x10
0x00000000
PAC Write-Protection
This register sets the data output drive value for the individual I/O pins in the PORT.
This register can be manipulated without doing a read-modify-write operation by using the Data Output Value Clear
(OUTCLR), Data Output Value Set (OUTSET), and Data Output Value Toggle (OUTTGL) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
28
27
26
25
24
RW
0
RW
0
RW
0
RW
0
19
18
17
16
RW
0
RW
0
RW
0
RW
0
11
10
9
8
RW
0
RW
0
RW
0
RW
0
3
2
1
0
RW
0
RW
0
RW
0
RW
0
OUT[31:24]
Access
Reset
RW
0
RW
0
RW
0
RW
0
Bit
23
22
21
20
OUT[23:16]
Access
Reset
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
OUT[15:8]
Access
Reset
Bit
RW
0
RW
0
RW
0
RW
0
7
6
5
4
OUT[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
Bits 31:0 – OUT[31:0] PORT Data Output Value
For pins configured as outputs via the Data Direction register (DIR), these bits set the logical output drive level.
For pins configured as inputs via the Data Direction register (DIR) and with pull enabled via the Pull Enable bit in the
Pin Configuration register (PINCFG.PULLEN), these bits will set the input pull direction.
Value
Description
0
The I/O pin output is driven low, or the input is connected to an internal pull-down.
1
The I/O pin output is driven high, or the input is connected to an internal pull-up.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 391
PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.7.6
Data Output Value Clear
Name:
Offset:
Reset:
Property:
OUTCLR
0x14
0x00000000
PAC Write-Protection
This register allows the user to set one or more output I/O pin drive levels low, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle
(OUTTGL) and Data Output Value Set (OUTSET) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
Access
Reset
RW
0
RW
0
RW
0
Bit
23
22
21
Access
Reset
RW
0
RW
0
RW
0
Bit
15
14
13
Access
Reset
RW
0
RW
0
RW
0
7
6
5
RW
0
RW
0
RW
0
Bit
Access
Reset
28
27
OUTCLR[31:24]
RW
RW
0
0
20
19
OUTCLR[23:16]
RW
RW
0
0
12
11
OUTCLR[15:8]
RW
RW
0
0
4
3
OUTCLR[7:0]
RW
RW
0
0
26
25
24
RW
0
RW
0
RW
0
18
17
16
RW
0
RW
0
RW
0
10
9
8
RW
0
RW
0
RW
0
2
1
0
RW
0
RW
0
RW
0
Bits 31:0 – OUTCLR[31:0] PORT Data Output Value Clear
Writing '0' to a bit has no effect.
Writing '1' to a bit will clear the corresponding bit in the OUT register. Pins configured as outputs via the Data
Direction register (DIR) will be set to low output drive level. Pins configured as inputs via DIR and with pull enabled
via the Pull Enable bit in the Pin Configuration register (PINCFG.PULLEN) will set the input pull direction to an
internal pull-down.
Value
Description
0
The corresponding I/O pin in the PORT group will keep its configuration.
1
The corresponding I/O pin output is driven low, or the input is connected to an internal pull-down.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 392
PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.7.7
Data Output Value Set
Name:
Offset:
Reset:
Property:
OUTSET
0x18
0x00000000
PAC Write-Protection
This register allows the user to set one or more output I/O pin drive levels high, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle
(OUTTGL) and Data Output Value Clear (OUTCLR) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
Access
Reset
RW
0
RW
0
RW
0
Bit
23
22
21
Access
Reset
RW
0
RW
0
RW
0
Bit
15
14
13
Access
Reset
RW
0
RW
0
RW
0
7
6
5
RW
0
RW
0
RW
0
Bit
Access
Reset
28
27
OUTSET[31:24]
RW
RW
0
0
20
19
OUTSET[23:16]
RW
RW
0
0
12
11
OUTSET[15:8]
RW
RW
0
0
4
3
OUTSET[7:0]
RW
RW
0
0
26
25
24
RW
0
RW
0
RW
0
18
17
16
RW
0
RW
0
RW
0
10
9
8
RW
0
RW
0
RW
0
2
1
0
RW
0
RW
0
RW
0
Bits 31:0 – OUTSET[31:0] PORT Data Output Value Set
Writing '0' to a bit has no effect.
Writing '1' to a bit will set the corresponding bit in the OUT register, which sets the output drive level high for I/O pins
configured as outputs via the Data Direction register (DIR). For pins configured as inputs via Data Direction register
(DIR) with pull enabled via the Pull Enable register (PULLEN), these bits will set the input pull direction to an internal
pull-up.
Value
Description
0
The corresponding I/O pin in the group will keep its configuration.
1
The corresponding I/O pin output is driven high, or the input is connected to an internal pull-up.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 393
PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.7.8
Data Output Value Toggle
Name:
Offset:
Reset:
Property:
OUTTGL
0x1C
0x00000000
PAC Write-Protection
This register allows the user to toggle the drive level of one or more output I/O pins, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Set
(OUTSET) and Data Output Value Clear (OUTCLR) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
Access
Reset
RW
0
RW
0
RW
0
Bit
23
22
21
Access
Reset
RW
0
RW
0
RW
0
Bit
15
14
13
Access
Reset
RW
0
RW
0
RW
0
7
6
5
RW
0
RW
0
RW
0
Bit
Access
Reset
28
27
OUTTGL[31:24]
RW
RW
0
0
20
19
OUTTGL[23:16]
RW
RW
0
0
12
11
OUTTGL[15:8]
RW
RW
0
0
4
3
OUTTGL[7:0]
RW
RW
0
0
26
25
24
RW
0
RW
0
RW
0
18
17
16
RW
0
RW
0
RW
0
10
9
8
RW
0
RW
0
RW
0
2
1
0
RW
0
RW
0
RW
0
Bits 31:0 – OUTTGL[31:0] PORT Data Output Value Toggle
Writing '0' to a bit has no effect.
Writing '1' to a bit will toggle the corresponding bit in the OUT register, which inverts the output drive level for I/O pins
configured as outputs via the Data Direction register (DIR). For pins configured as inputs via Data Direction register
(DIR) with pull enabled via the Pull Enable register (PULLEN), these bits will toggle the input pull direction.
Value
Description
0
The corresponding I/O pin in the PORT group will keep its configuration.
1
The corresponding OUT bit value is toggled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 394
PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.7.9
Data Input Value
Name:
Offset:
Reset:
Property:
IN
0x20
0x00000000
-
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
IN[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
IN[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
IN[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
IN[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – IN[31:0] PORT Data Input Value
These bits are cleared when the corresponding I/O pin input sampler detects a logical low level on the input pin.
These bits are set when the corresponding I/O pin input sampler detects a logical high level on the input pin.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 395
PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.7.10 Control
Name:
Offset:
Reset:
Property:
CTRL
0x24
0x00000000
PAC Write-Protection
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
Access
Reset
RW
0
RW
0
RW
0
Bit
23
22
21
Access
Reset
RW
0
RW
0
RW
0
Bit
15
14
13
Access
Reset
RW
0
RW
0
RW
0
7
6
5
RW
0
RW
0
RW
0
Bit
Access
Reset
28
27
SAMPLING[31:24]
RW
RW
0
0
20
19
SAMPLING[23:16]
RW
RW
0
0
12
11
SAMPLING[15:8]
RW
RW
0
0
4
3
SAMPLING[7:0]
RW
RW
0
0
26
25
24
RW
0
RW
0
RW
0
18
17
16
RW
0
RW
0
RW
0
10
9
8
RW
0
RW
0
RW
0
2
1
0
RW
0
RW
0
RW
0
Bits 31:0 – SAMPLING[31:0] Input Sampling Mode
Configures the input sampling functionality of the I/O pin input samplers, for pins configured as inputs via the Data
Direction register (DIR).
The input samplers are enabled and disabled in sub-groups of eight. Thus if any pins within a byte request
continuous sampling, all pins in that eight pin sub-group will be continuously sampled.
Value
Description
0
On demand sampling of I/O pin is enabled.
1
Continuous sampling of I/O pin is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 396
PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.7.11 Write Configuration
Name:
Offset:
Reset:
Property:
WRCONFIG
0x28
0x00000000
PAC Write-Protection, Write-Only
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
This write-only register is used to configure several pins simultaneously with the same configuration and peripheral
multiplexing.
In order to avoid side effect of non-atomic access, 8-bit or 16-bit writes to this register will have no effect. Reading
this register always returns zero.
Bit
31
HWSEL
W
0
30
WRPINCFG
W
0
29
28
WRPMUX
W
0
27
W
0
23
22
DRVSTR
W
0
21
20
19
Bit
15
14
13
Access
Reset
W
0
W
0
Bit
7
Access
Reset
W
0
Access
Reset
Bit
Access
Reset
26
25
24
W
0
W
0
W
0
18
PULLEN
W
0
17
INEN
W
0
16
PMUXEN
W
0
10
9
8
W
0
12
11
PINMASK[15:8]
W
W
0
0
W
0
W
0
W
0
6
5
4
2
1
0
W
0
W
0
W
0
W
0
W
0
PMUX[3:0]
3
PINMASK[7:0]
W
W
0
0
Bit 31 – HWSEL Half-Word Select
This bit selects the half-word field of a 32-PORT group to be reconfigured in the atomic write operation.
This bit will always read as zero.
Value
Description
0
The lower 16 pins of the PORT group will be configured.
1
The upper 16 pins of the PORT group will be configured.
Bit 30 – WRPINCFG Write PINCFG
This bit determines whether the atomic write operation will update the Pin Configuration register (PINCFGy) or not for
all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.
Writing '0' to this bit has no effect.
Writing '1' to this bit updates the configuration of the selected pins with the written WRCONFIG.DRVSTR,
WRCONFIG.PULLEN, WRCONFIG.INEN, WRCONFIG.PMUXEN, and WRCONFIG.PINMASK values.
This bit will always read as zero.
Value
Description
0
The PINCFGy registers of the selected pins will not be updated.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 397
PIC32CM MC00 Family
I/O Pin Controller (PORT)
Value
1
Description
The PINCFGy registers of the selected pins will be updated.
Bit 28 – WRPMUX Write PMUX
This bit determines whether the atomic write operation will update the Peripheral Multiplexing register (PMUXn) or not
for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.
Writing '0' to this bit has no effect.
Writing '1' to this bit updates the pin multiplexer configuration of the selected pins with the written WRCONFIG. PMUX
value.
This bit will always read as zero.
Value
Description
0
The PMUXn registers of the selected pins will not be updated.
1
The PMUXn registers of the selected pins will be updated.
Bits 27:24 – PMUX[3:0] Peripheral Multiplexing
These bits determine the new value written to the Peripheral Multiplexing register (PMUXn) for all pins selected by
the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPMUX bit is set.
These bits will always read as zero.
Bit 22 – DRVSTR Output Driver Strength Selection
This bit determines the new value written to PINCFGy.DRVSTR for all pins selected by the WRCONFIG.PINMASK
and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
Bit 18 – PULLEN Pull Enable
This bit determines the new value written to PINCFGy.PULLEN for all pins selected by the WRCONFIG.PINMASK
and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
Bit 17 – INEN Input Enable
This bit determines the new value written to PINCFGy.INEN for all pins selected by the WRCONFIG.PINMASK and
WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
Bit 16 – PMUXEN Peripheral Multiplexer Enable
This bit determines the new value written to PINCFGy.PMUXEN for all pins selected by the WRCONFIG.PINMASK
and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
Bits 15:0 – PINMASK[15:0] Pin Mask for Multiple Pin Configuration
These bits select the pins to be configured within the half-word group selected by the WRCONFIG.HWSEL bit.
These bits will always read as zero.
Value
Description
0
The configuration of the corresponding I/O pin in the half-word group will be left unchanged.
1
The configuration of the corresponding I/O pin in the half-word PORT group will be updated.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 398
PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.7.12 Event Input Control
Name:
Offset:
Reset:
Property:
EVCTRL
0x2C
0x00000000
PAC Write-Protection
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
There are up to four input event pins for each PORT group. Each byte of this register addresses one Event input pin.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
PORTEI3
RW
0
29
EVACT3[1:0]
RW
RW
0
0
28
27
RW
0
RW
0
23
PORTEI2
RW
0
22
21
EVACT2[1:0]
RW
RW
0
0
20
19
RW
0
RW
0
15
PORTEI1
RW
0
14
12
11
RW
0
RW
0
4
3
RW
0
RW
0
7
PORTEI0
RW
0
30
13
EVACT1[1:0]
RW
RW
0
0
6
5
EVACT0[1:0]
RW
RW
0
0
26
PID3[4:0]
RW
0
18
PID2[4:0]
RW
0
10
PID1[4:0]
RW
0
2
PID0[4:0]
RW
0
25
24
RW
0
RW
0
17
16
RW
0
RW
0
9
8
RW
0
RW
0
1
0
RW
0
RW
0
Bits 7, 15, 23, 31 – PORTEIx PORT Event Input Enable x [x = 3..0]
Value
Description
0
The event action x (EVACTx) will not be triggered on any incoming event.
1
The event action x (EVACTx) will be triggered on any incoming event.
Bits 5:6, 13:14, 21:22, 29:30 – EVACTx PORT Event Action x [x = 3..0]
These bits define the event action the PORT will perform on event input x. See also Table 27-4.
Bits 0:4, 8:12, 16:20, 24:28 – PIDx PORT Event Pin Identifier x [x = 3..0]
These bits define the I/O pin on which the event action will be performed, according to Table 27-5.
Table 27-4. PORT Event x Action ( x = [3..0] )
Value
Name
Description
0x0
OUT
0x1
0x2
0x3
SET
CLR
TGL
Output register of pin will be set to
level of event.
Set output register of pin on event.
Clear output register of pin on event.
Toggle output register of pin on
event.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 399
PIC32CM MC00 Family
I/O Pin Controller (PORT)
Table 27-5. PORT Event x Pin Identifier ( x = [3..0] )
Value
Name
Description
0x0
PIN0
0x1
PIN1
...
0x31
...
PIN31
Event action to be executed on PIN
0.
Event action to be executed on PIN
1.
...
Event action to be executed on PIN
31.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 400
PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.7.13 Peripheral Multiplexing n
Name:
Offset:
Reset:
Property:
PMUX
0x30 + n*0x01 [n=0..15]
0x00 except group 0 PMUX15 = 0x06
PAC Write-Protection
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
There are up to 16 Peripheral Multiplexing registers in each group, one for every set of two subsequent I/O lines. The
n denotes the number of the set of I/O lines.
Bit
7
6
5
4
3
2
PMUXO[3:0]
Access
Reset
RW
0
RW
0
1
0
RW
0
RW
0
PMUXE[3:0]
RW
0
RW
0
RW
0
RW
0
Bits 7:4 – PMUXO[3:0] Peripheral Multiplexing for Odd-Numbered Pin
These bits select the peripheral function for odd-numbered pins (2*n + 1) of a PORT group, if the corresponding
PINCFGy.PMUXEN bit is '1'.
Not all possible values for this selection may be valid. For more details, refer to the Pinout.
PMUXO[3:0]
Name
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA-0xF
A
B
C
D
E
F
G
H
I
J
-
Description
Peripheral function A selected
Peripheral function B selected
Peripheral function C selected
Peripheral function D selected
Peripheral function E selected
Peripheral function F selected
Peripheral function G selected
Peripheral function H selected
Peripheral function I selected
Peripheral function J selected
Reserved
Bits 3:0 – PMUXE[3:0] Peripheral Multiplexing for Even-Numbered Pin
These bits select the peripheral function for even-numbered pins (2*n) of a PORT group, if the corresponding
PINCFGy.PMUXEN bit is '1'.
Not all possible values for this selection may be valid. For more details, refer to the Pinout.
PMUXE[3:0]
Name
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
A
B
C
D
E
F
G
H
I
© 2021 Microchip Technology Inc.
and its subsidiaries
Description
Peripheral function A selected
Peripheral function B selected
Peripheral function C selected
Peripheral function D selected
Peripheral function E selected
Peripheral function F selected
Peripheral function G selected
Peripheral function H selected
Peripheral function I selected
Datasheet
DS60001638D-page 401
PIC32CM MC00 Family
I/O Pin Controller (PORT)
...........continued
PMUXE[3:0]
Name
0x9
0xA-0xF
J
-
© 2021 Microchip Technology Inc.
and its subsidiaries
Description
Peripheral function J selected
Reserved
Datasheet
DS60001638D-page 402
PIC32CM MC00 Family
I/O Pin Controller (PORT)
27.7.14 Pin Configuration
Name:
Offset:
Reset:
Property:
PINCFG
0x40 + n*0x01 [n=0..31]
0x00
PAC Write-Protection
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
There are up to 32 Pin Configuration registers in each PORT group, one for each I/O line.
Bit
7
Access
Reset
6
DRVSTR
RW
0
5
4
3
2
PULLEN
RW
0
1
INEN
RW
0
0
PMUXEN
RW
0
Bit 6 – DRVSTR Output Driver Strength Selection
This bit controls the output driver strength of an I/O pin configured as an output.
Value
Description
0
Pin drive strength is set to normal drive strength.
1
Pin drive strength is set to stronger drive strength.
Bit 2 – PULLEN Pull Enable
This bit enables the internal pull-up or pull-down resistor of an I/O pin configured as an input.
Value
Description
0
Internal pull resistor is disabled, and the input is in a high-impedance configuration.
1
Internal pull resistor is enabled, and the input is driven to a defined logic level in the absence of
external input.
Bit 1 – INEN Input Buffer Enable
This bit controls the input buffer of an I/O pin configured as either an input or output.
Writing a zero to this bit disables the input buffer completely, preventing read-back of the physical pin state when the
pin is configured as either an input or output.
Value
Description
0
Input buffer for the I/O pin is disabled, and the input value will not be sampled.
1
Input buffer for the I/O pin is enabled, and the input value will be sampled when required.
Bit 0 – PMUXEN Peripheral Multiplexer Enable
This bit enables or disables the peripheral multiplexer selection set in the Peripheral Multiplexing register (PMUXn) to
enable or disable alternative peripheral control over an I/O pin direction and output drive value.
Writing a zero to this bit allows the PORT to control the pad direction via the Data Direction register (DIR) and output
drive value via the Data Output Value register (OUT). The peripheral multiplexer value in PMUXn is ignored. Writing
'1' to this bit enables the peripheral selection in PMUXn to control the pad. In this configuration, the physical pin state
may still be read from the Data Input Value register (IN) if PINCFGn.INEN is set.
Value
Description
0
The peripheral multiplexer selection is disabled, and the PORT registers control the direction and
output drive value.
1
The peripheral multiplexer selection is enabled, and the selected peripheral function controls the
direction and output drive value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 403
PIC32CM MC00 Family
Event System (EVSYS)
28.
28.1
Event System (EVSYS)
Overview
The Event System (EVSYS) allows autonomous, low-latency and configurable communication between peripherals.
Several peripherals can be configured to generate and/or respond to signals known as events. The exact condition
to generate an event, or the action taken upon receiving an event, is specific to each peripheral. Peripherals that
respond to events are called event users. Peripherals that generate events are called event generators. A peripheral
can have one or more event generators and can have one or more event users.
Communication is made without CPU intervention and without consuming system resources such as bus or SRAM
bandwidth. This reduces the load on the CPU and other system resources, compared to a traditional interrupt-based
system.
28.2
Features
•
•
•
•
•
•
•
•
28.3
12 configurable event channels, where each channel can:
– Be connected to any event generator
– Provide a pure asynchronous, resynchronized or synchronous path
88 event generators
47 event users
Configurable edge detector
Peripherals can be event generators, event users, or both
SleepWalking and interrupt for operation in sleep modes
Software event generation
Each event user can choose which channel to respond to
Block Diagram
Figure 28-1. Event System Block Diagram
Clock Request [m:0]
Event Channel m
Event Channel 1
USER x+1
USER x
Event Channel 0
Asynchronous Path
USER.CHANNELx
CHANNEL0.PATH
SleepWalking
Detector
Synchronized Path
Edge Detector
PERIPHERAL0
Channel_EVT_m
EVT
D Q
To Peripheral x
R
EVT ACK
PERIPHERAL n
Channel_EVT_0
Q
D
Q
D
Q
D
Peripheral x
Event Acknowledge
Resynchronized Path
R
CHANNEL0.EVGEN
SWEVT.CHANNEL0
CHANNEL0.EDGSEL
D Q
D Q
D Q
R
R
R
R
R
GCLK_EVSYS_0
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 404
PIC32CM MC00 Family
Event System (EVSYS)
28.4
Peripheral Dependencies
AHB CLK
APB CLK
Generic CLK
PAC
Events
DMA
Peripheral Base Address IRQ
Sleep Walking
Enabled at reset Enabled at reset
EVSYS
28.5
28.5.1
0x42000000
8
-
N
Index
6-17: one per channel
Index Prot at reset User Generator Index
0
N
-
-
-
Y
Functional Description
Principle of Operation
The Event System consists of several channels which route the internal events from peripherals (generators) to other
internal peripherals or I/O pins (users). Each event generator can be selected as source for multiple channels, but a
channel cannot be set to use multiple event generators at the same time.
A channel path can be configured in asynchronous, synchronous or resynchronized mode of operation. The mode of
operation must be selected based on the requirements of the application.
When using synchronous or resynchronized path, the Event System includes options to transfer events to users
when rising, falling or both edges are detected on event generators.
For further details, refer to the Channel Path section of this chapter.
28.5.2
Basic Operation
28.5.2.1 Initialization
Before enabling event routing within the system, the Event Users Multiplexer and Event Channels must be selected
in the Event System (EVSYS), and the two peripherals that generate and use the event have to be configured. The
recommended sequence is:
1. In the peripheral generating the event, enable output of event by writing a '1' to the respective
Event Output Enable bit ("EO") in the peripheral's Event Control register (e.g., TCC.EVCTRL.MCEO1,
AC.EVCTRL.WINEO0, or RTC.EVCTRL.OVFEO).
2. Configure the EVSYS:
2.1.
Configure the Event User multiplexer by writing the respective EVSYS.USERm register, see also
28.5.2.3 User Multiplexer Setup.
2.2.
Configure the Event Channel by writing the respective EVSYS.CHANNELn register, see also
28.5.2.4 Event System Channel.
3. Configure the action to be executed by the event user peripheral by writing to the Event Action bits (EVACT)
in the respective Event control register (e.g., TC.EVCTRL.EVACT, PDEC.EVCTRL.EVACT). Note: not all
peripherals require this step.
4. In the event user peripheral, enable event input by writing a '1' to the respective Event Input Enable bit ("EI") in
the peripheral's Event Control register (e.g., AC.EVCTRL.IVEI0, ADC.EVCTRL.STARTEI).
28.5.2.2 Enabling, Disabling, and Resetting
The EVSYS is always enabled.
The EVSYS is reset by writing a ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers
in the EVSYS will be reset to their initial state and all ongoing events will be canceled.
Refer to CTRLA.SWRST register for details.
28.5.2.3 User Multiplexer Setup
The user multiplexer defines the channel to be connected to which event user. Each user multiplexer is dedicated to
one event user. A user multiplexer receives all event channels output and must be configured to select one of these
channels, as shown in Block Diagram section. The channel is selected with the Channel bit group in the User register
(USERm.CHANNEL).
The user multiplexer must always be configured before the channel. A list of all the user multiplexers is found in the
User (USERm) register description.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 405
PIC32CM MC00 Family
Event System (EVSYS)
28.5.2.4 Event System Channel
An event channel can select one event from a list of event generators. Depending on configuration, the
selected event could be synchronized, resynchronized or asynchronously sent to users. When synchronization or
resynchronization is required, the channel includes an internal edge detector, allowing the Event System to generate
internal events when rising, falling or both edges are detected on the selected event generator. After the event
channel is configured and enabled, the Channel Busy bit (CHSTATUS.CHBUSYn) will not be set for one generic
clock (GCLK_EVSYS_CHANNELn) cycle. Before the first event is exercised, the application must wait one clock
cycle for the channel to finalize the configuration when synchronous channels are used.
An event channel is able to generate internal events for specific software commands, see channel Block Diagram.
28.5.2.5 Event Generators
Each event channel can receive the events form all event generators. All event generators are listed in the Event
Generator bit field in the Channel n register (CHANNELn.EVGEN). For details on event generation, refer to the
corresponding module chapter. The channel event generator is selected by the Event Generator bit group in the
Channel register (CHANNELn.EVGEN). By default, the channels are not connected to any event generators (i.e.,
CHANNELn.EVGEN = 0)
28.5.2.6 Channel Path
The following are different ways to propagate the event from an event generator:
•
•
•
Asynchronous path
Synchronous path
Resynchronized path
The path is decided by writing to the Path Selection bit group of the Channel register (CHANNELn.PATH).
Asynchronous Path
When using the asynchronous path, the events are propagated from the event generator to the event user without
intervention from the Event System. The GCLK for this channel (GCLK_EVSYS_CHANNEL_n) is not mandatory,
meaning that an event will be propagated to the user without any clock latency.
When the asynchronous path is selected, the channel cannot generate any interrupts, and the Channel Status
register (CHSTATUS) is always zero. The edge detection is not required and must be disabled by software. Each
peripheral event user must select which event edge must trigger internal actions. For further details, refer to each
peripheral chapter description.
Synchronous Path
The synchronous path must be used when the event generator and the event channel share the same generator for
the generic clock. If they do not share the same clock, a logic change from the event generator to the event channel
might not be detected in the channel, which means that the event will not be propagated to the event user. For details
on generic clock generators, refer to GCLK - Generic Clock Controller.
When using the synchronous path, the channel is able to generate interrupts. The channel busy ‘n’ bit in the Channel
Status register (CHSTATUS.CHBUSYn) are also updated and available for use. If many events are received by the
event system in less than 2.5 GCLK_EVSYS periods, only the first event will be serviced and the overrun flag will not
be set.
Resynchronized Path
The resynchronized path are used when the event generator and the event channel do not share the same generator
for the generic clock. When the resynchronized path is used, resynchronization of the event from the event generator
is done in the channel. For details on generic clock generators, refer to GCLK - Generic Clock Controller.
When the resynchronized path is used, the channel is able to generate interrupts. The channel busy ‘n’ bits in the
Channel Status register (CHSTATUS.CHBUSYn) are also updated and available for use. If many events are received
by the event system in less than 2.5 GCLK_EVSYS periods, only the first event will be serviced and the overrun flag
will not be set. Additionally, the resynchronized channel busy flag (CHSTATUS.CHBUSYn) will not be set for three
clock cycles after the event is received.
28.5.2.7 Edge Detection
When synchronous or resynchronized paths are used, edge detection must be enabled. The event system can
execute edge detection in three different ways:
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 406
PIC32CM MC00 Family
Event System (EVSYS)
•
•
•
Generate an event only on the rising edge
Generate an event only on the falling edge
Generate an event on rising and falling edges.
Edge detection is selected by writing to the Edge Selection bit group of the Channel register (CHANNELn.EDGSEL).
28.5.2.8 Event Latency
The latency from the event generator to the event user depends on the configuration of the channel:
•
•
•
Asynchronous Path: The maximum routing latency of an external event is related to the internal signal routing
and it is device dependent.
Synchronous Path: The maximum routing latency of an external event is one GCLK_EVSYS_CHANNEL_n
clock cycle.
Resynchronized Path: The maximum routing latency of an external event is three GCLK_EVSYS_CHANNEL_n
clock cycles.
The maximum propagation latency of a user event to the peripheral clock core domain is three peripheral clock
cycles.
The event generators, event channel and event user clocks ratio must be selected in relation with the internal event
latency constraints. Events propagation or event actions in peripherals may be lost if the clock setup violates the
internal latencies.
28.5.2.9 The Overrun Channel n Interrupt
The Overrun Channel n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAGn.OVR) will be set, and
the optional interrupt will be generated in the following cases:
•
•
Many event users on channel ‘n’ is not ready when there is a new event.
An event occurs when the previous event on channel ‘m’ is not handled by all event users connected to that
channel.
The flag will only be set when using synchronous or resynchronized paths. In the case of asynchronous path,
the INTFLAGn.OVR is always read as zero. When using the synchronous path ensure the generic clock (GCLK)
is always on by setting the event systems channel to be on demand (CHANNELn.ONDEMAND). Following this
configuration will prevent spurious overrun interrupts.
28.5.2.10 The Event Detected Channel n Interrupt
The Event Detected Channel n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAGn.EVD) is set
when an event coming from the event generator configured on channel n is detected.
The flag will only be set when using a synchronous or resynchronized path. In the case of asynchronous path, the
INTFLAGn.EVD is always zero.
28.5.2.11 Channel Status
The Channel Status register (CHSTATUS) shows the status of the channels when using a synchronous or
resynchronized path. There are two different status bits in CHSTATUS for each of the available channels:
•
•
The CHSTATUSn.BUSYCH bit will be set when an event on the corresponding channel n has not been handled
by all event users connected to that channel.
The CHSTATUSn.RDYUSR bit will be set when all event users connected to the corresponding channel are
ready to handle incoming events on that channel.
28.5.2.12 Software Event
A software event can be initiated on a channel by setting the Channel ‘n’ bit in the Software Event register
(SWEVT.CHANNELn) to ‘1’. Then the software event can be serviced as any event generator; that is, when a bit
is set to ‘1’, an event will be generated on the respective channel.
When using a software event on a channel with resynchronized path, the CHSTATUS.CHBUSYn bit will not be set
immediately. Wait three GCLK_EVSYS_CHANNEL_n clock cycles for the CHSTATUS.CHBUSYn bit to be set, before
issuing a new software event.
28.5.3
Interrupts
The EVSYS has the following interrupt sources:
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 407
PIC32CM MC00 Family
Event System (EVSYS)
•
•
Overrun Channel n interrupt (OVRn): for details, refer to 28.5.2.9 The Overrun Channel n Interrupt.
Event Detected Channel n interrupt (EVDn): for details, refer to 28.5.2.10 The Event Detected Channel n
Interrupt.
These interrupts events are asynchronous wake-up sources. Refer to 16.5.3.3 Sleep Mode Controller. Each interrupt
source has an interrupt flag which is in the Interrupt Flag Status and Clear (INTFLAG) register. The flag is set
when the interrupt is issued. Each interrupt event can be individually enabled by setting a ‘1’ to the corresponding
bit in the Interrupt Enable Set (INTENSET) register, and disabled by setting a ‘1’ to the corresponding bit in the
Interrupt Enable Clear (INTENCLR) register. An interrupt event is generated when the interrupt flag is set and the
corresponding interrupt is enabled. The interrupt event is active until the interrupt flag is cleared, the interrupt is
disabled, or the Event System is reset. See 28.6.5 INTFLAG for details on how to clear interrupt flags.
All interrupt events from the peripheral are ORed together on system level to generate one combined interrupt
request to the NVIC. Refer to the 9.2 Nested Vector Interrupt Controller for details. The event user must read the
INTFLAG register to determine what the interrupt condition is.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt
Controller for details.
28.5.4
Sleep Mode Operation
The EVSYS can generate interrupts to wake up the device from any sleep mode.
To be able to run in standby, the Run in Standby bit in the Channel register (CHANNELn.RUNSTDBY) must be
set to ‘1’. When the Generic Clock On Demand bit in Channel register (CHANNELn.ONDEMAND) is set to ‘1’ and
the event generator is detected, the event channel will request its clock (GCLK_EVSYS_CHANNEL_n). The event
latency for a resynchronized channel path will increase by two GCLK_EVSYS_CHANNEL_n clock (i.e., up to five
GCLK_EVSYS_CHANNEL_n clock cycles).
A channel will behave differently in different sleep modes regarding to CHANNELn.RUNSTDBY and
CHANNELn.ONDEMAND, as shown in the table below:
Table 28-1. Event Channel Sleep Behavior
CHANNELn.ONDEMAND
CHANNELn.RUNSTDBY
Sleep Behavior
0
0
Only run in Idle sleep mode if an event must be
propagated. Disabled in Standby Sleep mode.
0
1
Always run in Idle and Standby Sleep modes.
1
0
Only run in Idle sleep mode if an event must be
propagated. Disabled in Standby Sleep mode. Two
GCLK_EVSYS_n latency added in RESYNC path before
the event is propagated internally.
1
1
Always run in Idle and Standby Sleep modes. Two
GCLK_EVSYS_n latency added in RESYNC path before
the event is propagated internally.
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and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Event System (EVSYS)
28.6
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
...
0x0B
CTRLA
7:0
0x0C
0x10
0x14
0x18
0x1C
0x20
7
6
5
4
3
2
1
0
SWRST
Reserved
CHSTATUS
INTENCLR
INTENSET
INTFLAG
SWEVT
CHANNEL0
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
USRRDY7
USRRDY6
USRRDY5
USRRDY4
CHBUSY7
CHBUSY6
CHBUSY5
CHBUSY4
OVR7
OVR6
OVR5
OVR4
EVD7
EVD6
EVD5
EVD4
OVR7
OVR6
OVR5
OVR4
EVD7
EVD6
EVD5
EVD4
OVR7
OVR6
OVR5
OVR4
EVD7
EVD6
EVD5
EVD4
CHANNEL7
CHANNEL6
CHANNEL5
CHANNEL4
USRRDY3
USRRDY2
USRRDY11 USRRDY10
CHBUSY3
CHBUSY2
CHBUSY11 CHBUSY10
OVR3
OVR2
OVR11
OVR10
EVD3
EVD2
EVD11
EVD10
OVR3
OVR2
OVR11
OVR10
EVD3
EVD2
EVD11
EVD10
OVR3
OVR2
OVR11
OVR10
EVD3
EVD2
EVD11
EVD10
CHANNEL3 CHANNEL2
CHANNEL11 CHANNEL10
USRRDY1
USRRDY9
CHBUSY1
CHBUSY9
OVR1
OVR9
EVD1
EVD9
OVR1
OVR9
EVD1
EVD9
OVR1
OVR9
EVD1
EVD9
CHANNEL1
CHANNEL9
USRRDY0
USRRDY8
CHBUSY0
CHBUSY8
OVR0
OVR8
EVD0
EVD8
OVR0
OVR8
EVD0
EVD8
OVR0
OVR8
EVD0
EVD8
CHANNEL0
CHANNEL8
ONDEMAND RUNSTDBY
EVGEN[6:0]
EDGSEL[1:0]
PATH[1:0]
ONDEMAND RUNSTDBY
EVGEN[6:0]
EDGSEL[1:0]
PATH[1:0]
...
7:0
15:8
23:16
31:24
0x4C
CHANNEL11
0x50
...
0x7F
Reserved
USER0
7:0
15:8
23:16
31:24
CHANNEL[4:0]
0x80
CHANNEL[4:0]
USER46
7:0
15:8
23:16
31:24
...
0x0138
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 409
PIC32CM MC00 Family
Event System (EVSYS)
28.6.1
Control A
Name:
Offset:
Reset:
Property:
Bit
CTRLA
0x00
0x00
PAC Write-Protection
7
6
5
4
3
2
Access
Reset
1
0
SWRST
W
0
Bit 0 – SWRST Software Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the EVSYS to their initial state.
Note: Before applying a Software Reset it is recommended to disable the event generators.
© 2021 Microchip Technology Inc.
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PIC32CM MC00 Family
Event System (EVSYS)
28.6.2
Channel Status
Name:
Offset:
Reset:
Property:
Bit
CHSTATUS
0x0C
0x00000000
–
31
30
29
28
27
CHBUSY11
R
0
26
CHBUSY10
R
0
25
CHBUSY9
R
0
24
CHBUSY8
R
0
23
CHBUSY7
R
0
22
CHBUSY6
R
0
21
CHBUSY5
R
0
20
CHBUSY4
R
0
19
CHBUSY3
R
0
18
CHBUSY2
R
0
17
CHBUSY1
R
0
16
CHBUSY0
R
0
15
14
13
12
11
USRRDY11
R
0
10
USRRDY10
R
0
9
USRRDY9
R
0
8
USRRDY8
R
0
7
USRRDY7
R
0
6
USRRDY6
R
0
5
USRRDY5
R
0
4
USRRDY4
R
0
3
USRRDY3
R
0
2
USRRDY2
R
0
1
USRRDY1
R
0
0
USRRDY0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 – CHBUSYx Channel Busy x [x = 11..0]
This bit is cleared when channel x is idle.
This bit is set if an event on channel x has not been handled by all event users connected to channel x.
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – USRRDYx User Ready for Channel x [x = 11..0]
This bit is cleared when at least one of the event users connected to the channel is not ready.
This bit is set when all event users connected to channel x are ready to handle incoming events on channel x.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 411
PIC32CM MC00 Family
Event System (EVSYS)
28.6.3
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x10
0x00000000
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
31
30
29
28
27
EVD11
R/W
0
26
EVD10
R/W
0
25
EVD9
R/W
0
24
EVD8
R/W
0
23
EVD7
R/W
0
22
EVD6
R/W
0
21
EVD5
R/W
0
20
EVD4
R/W
0
19
EVD3
R/W
0
18
EVD2
R/W
0
17
EVD1
R/W
0
16
EVD0
R/W
0
15
14
13
12
11
OVR11
R/W
0
10
OVR10
R/W
0
9
OVR9
R/W
0
8
OVR8
R/W
0
7
OVR7
R/W
0
6
OVR6
R/W
0
5
OVR5
R/W
0
4
OVR4
R/W
0
3
OVR3
R/W
0
2
OVR2
R/W
0
1
OVR1
R/W
0
0
OVR0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 – EVDx Event Detected Channel x Interrupt Enable [x = 11..0]
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Event Detected Channel x Interrupt Enable bit, which disables the Event Detected
Channel x interrupt.
Value
Description
0
The Event Detected Channel x interrupt is disabled.
1
The Event Detected Channel x interrupt is enabled.
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – OVRx Overrun Channel x Interrupt Enable[x = 11..0]
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Overrun Channel x Interrupt Enable bit, which disables the Overrun Channel x
interrupt.
Value
Description
0
The Overrun Channel x interrupt is disabled.
1
The Overrun Channel x interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Event System (EVSYS)
28.6.4
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x14
0x00000000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
31
30
29
28
27
EVD11
R/W
0
26
EVD10
R/W
0
25
EVD9
R/W
0
24
EVD8
R/W
0
23
EVD7
R/W
0
22
EVD6
R/W
0
21
EVD5
R/W
0
20
EVD4
R/W
0
19
EVD3
R/W
0
18
EVD2
R/W
0
17
EVD1
R/W
0
16
EVD0
R/W
0
15
14
13
12
11
OVR11
R/W
0
10
OVR10
R/W
0
9
OVR9
R/W
0
8
OVR8
R/W
0
7
OVR7
R/W
0
6
OVR6
R/W
0
5
OVR5
R/W
0
4
OVR4
R/W
0
3
OVR3
R/W
0
2
OVR2
R/W
0
1
OVR1
R/W
0
0
OVR0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 – EVDx Event Detected Channel x Interrupt Enable [x = 11..0]
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Event Detected Channel x Interrupt Enable bit, which enables the Event Detected
Channel x interrupt.
Value
Description
0
The Event Detected Channel x interrupt is disabled.
1
The Event Detected Channel x interrupt is enabled.
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – OVRx Overrun Channel x Interrupt Enable [x = 11..0]
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Overrun Channel x Interrupt Enable bit, which disables the Overrun Channel x
interrupt.
Value
Description
0
The Overrun Channel x interrupt is disabled.
1
The Overrun Channel x interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Event System (EVSYS)
28.6.5
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
INTFLAG
0x18
0x00000000
–
31
30
29
28
27
EVD11
R/W
0
26
EVD10
R/W
0
25
EVD9
R/W
0
24
EVD8
R/W
0
23
EVD7
R/W
0
22
EVD6
R/W
0
21
EVD5
R/W
0
20
EVD4
R/W
0
19
EVD3
R/W
0
18
EVD2
R/W
0
17
EVD1
R/W
0
16
EVD0
R/W
0
15
14
13
12
11
OVR11
R/W
0
10
OVR10
R/W
0
9
OVR9
R/W
0
8
OVR8
R/W
0
7
OVR7
R/W
0
6
OVR6
R/W
0
5
OVR5
R/W
0
4
OVR4
R/W
0
3
OVR3
R/W
0
2
OVR2
R/W
0
1
OVR1
R/W
0
0
OVR0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 – EVDx Event Detected Channel x [x = 11..0]
This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an
interrupt request will be generated if INTENCLR/SET.EVDx is '1'.
When the event channel path is asynchronous, the EVDx interrupt flag will not be set.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Event Detected Channel x interrupt flag.
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – OVRx Overrun Channel x [x = 11..0]
This flag is set on the next CLK_EVSYS_APB cycle after an overrun channel condition occurs, and an interrupt
request will be generated if INTENCLR/SET.OVRx is '1'.
There are two possible overrun channel conditions:
• One or more of the event users on channel x are not ready when a new event occurs.
• An event happens when the previous event on channel x has not yet been handled by all event users.
When the event channel path is asynchronous, the OVRx interrupt flag will not be set.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Overrun Detected Channel x interrupt flag.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Event System (EVSYS)
28.6.6
Software Event
Name:
Offset:
Reset:
Property:
Bit
SWEVT
0x1C
0x00000000
PAC Write-Protection
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
CHANNEL11
R/W
0
10
CHANNEL10
R/W
0
9
CHANNEL9
R/W
0
8
CHANNEL8
R/W
0
7
CHANNEL7
R/W
0
6
CHANNEL6
R/W
0
5
CHANNEL5
R/W
0
4
CHANNEL4
R/W
0
3
CHANNEL3
R/W
0
2
CHANNEL2
R/W
0
1
CHANNEL1
R/W
0
0
CHANNEL0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – CHANNELx Channel x Software [x = 11..0] Selection
Writing '0' to this bit has no effect.
Writing '1' to this bit will trigger a software event for the channel x.
These bits will always return zero when read.
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Datasheet
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PIC32CM MC00 Family
Event System (EVSYS)
28.6.7
Channel n Control
Name:
Offset:
Reset:
Property:
CHANNELn
0x20 + n*0x04 [n=0..11]
0x00008000
PAC Write-Protection
This register allows the user to configure channel n. To write to this register, do a single, 32-bit write of all the
configuration data.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ONDEMAND
R/W
1
14
RUNSTDBY
R/W
0
13
12
11
7
6
5
4
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
10
EDGSEL[1:0]
R/W
R/W
0
0
3
EVGEN[6:0]
R/W
0
9
8
PATH[1:0]
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bit 15 – ONDEMAND Generic Clock On Demand
Value
Description
0
Generic clock for a channel is always on, if the channel is configured and generic clock source is
enabled.
1
Generic clock is requested on demand while an event is handled
Bit 14 – RUNSTDBY Run in Standby
This bit is used to define the behavior during standby sleep mode.
Value
Description
0
The channel is disabled in standby sleep mode.
1
The channel is not stopped in standby sleep mode and depends on the CHANNEL.ONDEMAND
Bits 11:10 – EDGSEL[1:0] Edge Detection Selection
These bits set the type of edge detection to be used on the channel.
These bits must be written to zero when using the asynchronous path.
Value
Name
Description
0x0
NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path
0x1
RISING_EDGE
Event detection only on the rising edge of the signal from the event generator
0x2
FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator
0x3
BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator
Bits 9:8 – PATH[1:0] Path Selection
These bits are used to choose which path will be used by the selected channel.
The path choice can be limited by the channel source, see the table in USERm.
Value
Name
Description
0x0
SYNCHRONOUS
Synchronous path
0x1
RESYNCHRONIZED
Resynchronized path
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
Event System (EVSYS)
Value
0x2
0x3
Name
ASYNCHRONOUS
-
Description
Asynchronous path
Reserved
Bits 6:0 – EVGEN[6:0] Event Generator
These bits are used to choose the event generator to connect to the selected channel.
Table 28-2. Event Generators
Value
Event Generator
Description
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
NONE
OSCCTRL FAIL
OSC32KCTRL FAIL
RTC CMP0
RTC CMP1
RTC OVF
RTC PER0
RTC PER1
RTC PER2
RTC PER3
RTC PER4
RTC PER5
RTC PER6
RTC PER7
EIC EXTINT0
EIC EXTINT1
EIC EXTINT2
EIC EXTINT3
EIC EXTINT4
EIC EXTINT5
EIC EXTINT6
EIC EXTINT7
EIC EXTINT8
EIC EXTINT9
EIC EXTINT10
EIC EXTINT11
EIC EXTINT12
EIC EXTINT13
EIC EXTINT14
EIC EXTINT15
TSENS
DMAC CH0
DMAC CH1
DMAC CH2
DMAC CH3
TCC0 OVF
TCC0 TRG
TCC0 CNT
TCC0 MC0
TCC0 MC1
TCC0 MC2
TCC0 MC3
TCC1 OVF
TCC1 TRG
TCC1 CNT
TCC1 MC0
TCC1 MC1
No event generator selected
XOSC Clock Failure
XOSC32K Clock Failure
Compare 0 (mode 0 and 1) or Alarm0 (mode 2)
Compare 1
Overflow
Period 0
Period 1
Period 2
Period 3
Period 4
Period 5
Period 6
Period 7
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
External Interrupt 8
External Interrupt 9
External Interrupt 10
External Interrupt 11
External Interrupt 12
External Interrupt 13
External Interrupt 14
External Interrupt 15
Window Monitor
Channel 0
Channel 1
Channel 2
Channel 3
Overflow
Trig
Counter
Match/Capture 1
Match/Capture 1
Match/Capture 2
Match/Capture 3
Overflow
Trig
Counter
Match/Capture 0
Match/Capture 1
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 417
PIC32CM MC00 Family
Event System (EVSYS)
...........continued
Value
Event Generator
Description
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59-0x7
F
TCC2 OVF
TCC2 TRG
TCC2 CNT
TCC2 MC0
TCC2 MC1
TC0 OVF
TC0 MC0
TC0 MC1
TC1 OVF
TC1 MC0
TC1 MC1
TC2 OVF
TC2 MC1
TC2 MC0
TC3 OVF
TC3 MC0
TC3 MC1
TC4 OVF
TC4 MC0
TC4 MC1
ADC0 RESRDY
ADC0 WINMON
ADC1 RESRDY
ADC1 WINMON
SDADC RESRDY
SDADC WINMON
AC COMP0
AC COMP1
AC WIN0
DAC EMPTY
CCL LUTOUT0
CCL LUTOUT1
CCL LUTOUT2
CCL LUTOUT3
PAC ACCERR
PDEC_OVF
PDEC_ERR
PDEC_DIR
PDEC_VLC
PDEC_MC0
PDEC_MC1
Reserved
Overflow
Trig
Counter
Match/Capture 0
Match/Capture 1
Overflow/Underflow
Match/Capture 0
Match/Capture 1
Overflow/Underflow
Match/Capture 0
Match/Capture 1
Overflow/Underflow
Match/Capture 0
Match/Capture 1
Overflow/Underflow
Match/Capture 0
Match/Capture 1
Overflow/Underflow
Match/Capture 0
Match/Capture 1
Result Ready
Window Monitor
Result Ready
Window Monitor
Result Ready
Window Monitor
Comparator 0
Comparator 1
Window 0
Data Buffer Empty
CCL output
CCL output
CCL output
CCL output
Access Error
Reserved
PDEC Overflow
PDEC Error
PDEC Direction
PDEC VLC
PDEC MC0
PDEC MC1
Reserved
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 418
PIC32CM MC00 Family
Event System (EVSYS)
28.6.8
Event User m
Name:
Offset:
Reset:
Property:
Bit
USERm
0x80 + m*0x04 [m=0..46]
0x00000000
PAC Write-Protection
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
R/W
0
R/W
0
2
CHANNEL[4:0]
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 4:0 – CHANNEL[4:0] Channel Event Selection
These bits are used to select the channel to connect to the event user.
Note that to select channel m, the value (m+1) must be written to the USER.CHANNEL bit group.
Value
Channel Number
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD-0x1F
No channel output selected
0
1
2
3
4
5
6
7
8
9
10
11
Reserved
Table 28-3. User Multiplexer Number
USERm User Multiplexer Description
Path Type
m=0
m=1
m=2
m=3
m=4
m=5
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous, synchronous, and resynchronized paths
TSENS
PORT EV0
PORT EV1
PORT EV2
PORT EV3
DMAC CH0
© 2021 Microchip Technology Inc.
and its subsidiaries
Start
Event 0
Event 1
Event 2
Event 3
Channel 0
Datasheet
DS60001638D-page 419
PIC32CM MC00 Family
Event System (EVSYS)
...........continued
USERm User Multiplexer Description
m=6
m=7
m=8
m=9
m = 10
m = 11
m = 12
m = 13
m = 14
m = 15
m = 16
m = 17
m = 18
m = 19
m = 20
m = 21
m = 22
m = 23
DMAC CH1
DMAC CH2
DMAC CH3
TCC0 EV0
TCC0 EV1
TCC0 MC0
TCC0 MC1
TCC0 MC2
TCC0 MC3
TCC1 EV0
TCC1 EV1
TCC1 MC0
TCC1 MC1
TCC2 EV0
TCC2 EV1
TCC2 MC0
TCC2 MC1
TC0EV
m = 24
m = 25
m = 26
m = 27
m = 28
m = 29
m = 30
m = 31
m = 32
m = 33
m = 34
m = 35
m = 36
m = 37
m = 38
m = 39
m = 40
m = 41
m = 42
m = 43
m = 44
m = 45
m = 46
TC1EV
TC2EV
TC3EV
TC4EV
ADC0 START
ADC0 FLUSH
ADC1 START
ADC1 FLUSH
SDADC START
SDADC FLUSH
AC COMP0
AC COMP1
DAC START
CCL LUTIN 0
CCL LUTIN 1
CCL LUTIN 2
CCL LUTIN 3
Reserved
MTB START
MTB STOP
PDEC EVU0
PDEC EVU1
PDEC EVU2
© 2021 Microchip Technology Inc.
and its subsidiaries
Path Type
Channel 1
Channel 2
Channel 3
Input Event 0
Input Event 1
Match/Capture 0
Match/Capture 1
Match/Capture 2
Match/Capture 3
Input Event 0
Input Event 1
Match/Capture 0
Match/Capture 1
Input Event 0
Input Event 1
Match/Capture 0
Match/Capture 1
Input Event
Asynchronous, synchronous, and resynchronized paths
Asynchronous, synchronous, and resynchronized paths
Asynchronous, synchronous, and resynchronized paths
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous path only, synchronous, and resynchronized
paths
Input Event
Asynchronous, synchronous, and resynchronized paths
Input Event
Asynchronous, synchronous, and resynchronized paths
Input Event
Asynchronous, synchronous, and resynchronized paths
Input Event
Asynchronous, synchronous, and resynchronized paths
ADC start conversion
Asynchronous path only
Flush ADC
Asynchronous path only
ADC start conversion
Asynchronous path only
Flush ADC
Asynchronous path only
ADC start
Asynchronous path only
Flush ADC
Asynchronous path only
Start comparator 0
Asynchronous path only
Start comparator 1
Asynchronous path only
DAC start conversion
Asynchronous path only
CCL input
Asynchronous path only
CCL input
Asynchronous path only
CCL input
Asynchronous path only
CCL input
Asynchronous path only
Reserved
Micro Trace Buffer Start Asynchronous path only
Micro Trace Buffer Stop Asynchronous path only
QDEC_EV0
Asynchronous path only
QDEC_EV1
Asynchronous path only
QDEC_EV2
Asynchronous path only
Datasheet
DS60001638D-page 420
PIC32CM MC00 Family
Serial Communication Interface (SERCOM)
29.
Serial Communication Interface (SERCOM)
29.1
Overview
There are up to four instances of the serial communication interface (SERCOM) peripheral.
A SERCOM can be configured to support a number of modes: I2C, SPI, and USART. When an instance of SERCOM
is configured and enabled, all of the resources of that SERCOM instance will be dedicated to the selected mode.
The SERCOM serial engine consists of a transmitter and receiver, baud-rate generator and address matching
functionality. It can use the internal generic clock or an external clock. Using an external clock allows the SERCOM to
be operated in all Sleep modes.
29.2
Features
•
Interface for configuring into one of the following:
•
•
•
•
•
– Inter-Integrated Circuit (I2C) Two-wire Serial Interface
– System Management Bus (SMBus™) compatible
– Serial Peripheral Interface (SPI)
– Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
Single transmit buffer and double receive buffer
Baud-rate generator
Address match/mask logic
Operational in all Sleep modes with an external clock source
Can be used with DMA
For further information, see the following chapters:
• SERCOM SPI
• SERCOM USART
• SERCOM I2C
29.3
Block Diagram
Figure 29-1. SERCOM Block Diagram
SERCOM
Register Interface
CONTROL/STATUS
Mode Specific
BAUD/ADDR
TX/RX DATA
Serial Engine
Mode n
Mode 1
Transmitter
Baud Rate
Generator
Mode 0
Receiver
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
PAD[3:0]
Address
Match
DS60001638D-page 421
PIC32CM MC00 Family
Serial Communication Interface (SERCOM)
29.4
Signal Description
See the respective SERCOM mode chapters for details.
For further information, see the following chapters:
• SERCOM SPI
• SERCOM USART
• SERCOM I2C
29.5
Peripheral Dependencies
Peripheral
Base Address
AHB CLK
APB CLK
Generic CLK
Enabled at reset
Enabled at reset
Index
-
N
PAC
Events
Sleep Walking
Index
Prot at reset
User
Generator
1
N
-
-
19: CORE
SERCOM0
0x42000400
9
10
-
N
4: RX
2
N
-
-
18: SLOW
0x42000C00
11
-
N
6: RX
3
N
-
-
18: SLOW
0x42001000
12
-
N
29.6
29.6.1
8:RX
4
18: SLOW
Y
7: TX
22: CORE
SERCOM3
Y
5: TX
21: CORE
SERCOM2
Y
3: TX
20: CORE
0x42000800
Index
2: RX
18: SLOW
SERCOM1
DMA
IRQ
N
-
-
Y
9:TX
Functional Description
Principle of Operation
The basic structure of the SERCOM serial engine is shown in Figure 29-2. Labels in capital letters are synchronous
to the system clock and accessible by the CPU; labels in lowercase letters can be configured to run on the
GCLK_SERCOMx_CORE clock or an external clock.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 422
PIC32CM MC00 Family
Serial Communication Interface (SERCOM)
Figure 29-2. SERCOM Serial Engine
Address Match
Transmitter
BAUD
Selectable
Internal Clk
(GCLK)
TX DATA
ADDR/ADDRMASK
Baud Rate Generator
Ext Clk
1/- /2- /16
TX Shift Register
Receiver
RX Shift Register
Equal
Status
RX Buffer
STATUS
Baud Rate Generator
RX DATA
The transmitter consists of a single write buffer and a shift register.
The receiver consists of a one-level (I2C), two-level (USART, SPI) receive buffer and a shift register.
The baud-rate generator is capable of running on the GCLK_SERCOMx_CORE clock or an external clock.
Address matching logic is included for SPI and I2C operation.
For further information, see the following chapters:
• SERCOM SPI
• SERCOM USART
• SERCOM I2C
29.6.2
Basic Operation
29.6.2.1 Initialization
The SERCOM must be configured to the desired mode by writing the Operating Mode bits in the Control A register
(CTRLA.MODE). Refer to table SERCOM Modes for details.
Table 29-1. SERCOM Modes
CTRLA.MODE
Description
0x0
USART with external clock
0x1
USART with internal clock
0x2
SPI in client operation
0x3
SPI in host operation
0x4
I2C client operation
0x5
I2C host operation
0x6-0x7
Reserved
For further initialization information, see the respective SERCOM mode chapters:
•
•
SERCOM SPI
SERCOM USART
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 423
PIC32CM MC00 Family
Serial Communication Interface (SERCOM)
•
SERCOM I2C
29.6.2.2 Enabling, Disabling, and Resetting
This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by
writing '0' to it.
Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral
to their initial states, except the DBGCTRL register, only when CRTLA.ENABLE is '1'.
Refer to the CTRLA register description for details.
29.6.2.3 Clock Generation – Baud-Rate Generator
The baud-rate generator, as shown in Figure 29-3, generates internal clocks for asynchronous and synchronous
communication. The output frequency (fBAUD) is determined by the Baud register (BAUD) setting and the baud
reference frequency (fref). The baud reference clock is the serial engine clock, and it can be internal or external.
For asynchronous communication, the /16 (divide-by-16) output is used when transmitting, whereas the /1 (divideby-1) output is used while receiving.
For synchronous communication, the /2 (divide-by-2) output is used.
This functionality is automatically configured, depending on the selected operating mode.
Figure 29-3. Baud Rate Generator
Selectable
Internal Clk
(GCLK)
Baud Rate Generator
1
Ext Clk
fref
0
Base
Period
/2
/1
CTRLA.MODE[0]
/8
/2
/16
0
Tx Clk
1
1
CTRLA.MODE
0
1
Clock
Recovery
Rx Clk
0
Table 29-2 contains equations for the baud rate (in bits per second) and the BAUD register value for each operating
mode.
For asynchronous operation, the BAUD register value is 16 bits (0 to 65,535).
For synchronous operation, the BAUD register value is 8 bits (0 to 255).
Table 29-2. Baud Rate Equations
Operating Mode
Asynchronous
Arithmetic
Asynchronous
Fractional
Synchronous
Condition
fBAUD ≤
fBAUD ≤
fBAUD ≤
fref
16
fref
S
fref
2
Baud Rate (Bits Per Second)
fBAUD =
fBAUD =
fBAUD =
fref
1 − BAUD
16
65536
fref
S ⋅ BAUD + FP
8
fref
2 ⋅ BAUD + 1
S - Number of samples per bit, which can be 16, 8, or 3.
BAUD Register Value Calculation
f
BAUD = 65536 ⋅ 1 − 16 ⋅ BAUD
fref
BAUD =
BAUD =
fref
FP
−
8
S ⋅ fBAUD
fref
−1
2 ⋅ fBAUD
The Asynchronous Fractional option is used for auto-baud detection.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 424
PIC32CM MC00 Family
Serial Communication Interface (SERCOM)
The baud rate error is represented by the following formula:
Error = 1 −
ExpectedBaudRate
ActualBaudRate
29.6.2.3.1 Asynchronous Arithmetic Mode BAUD Value Selection
The formula given for fBAUD calculates the average frequency over 65536 fref cycles. Although the BAUD register
can be set to any value between 0 and 65536, the actual average frequency of fBAUD over a single frame is more
granular. The BAUD register values that will affect the average frequency over a single frame lead to an integer
increase in the cycles per frame (CPF)
CPF =
where
•
•
fref
D+S
fBAUD
D represent the data bits per frame
S represent the sum of start and first stop bits, if present.
Table 29-3 shows the BAUD register value versus baud frequency fBAUD at a serial engine frequency of 48MHz. This
assumes a D value of 8 bits and an S value of 2 bits (10 bits, including start and stop bits).
Table 29-3. BAUD Register Value vs. Baud Frequency
29.6.3
BAUD Register Value
Serial Engine CPF
fBAUD at 48MHz Serial Engine Frequency (fREF)
0 – 406
160
3MHz
407 – 808
161
2.981MHz
809 – 1205
162
2.963MHz
...
...
...
65206
31775
15.11kHz
65207
31871
15.06kHz
65208
31969
15.01kHz
Additional Features
29.6.3.1 Address Match and Mask
The SERCOM address match and mask feature is capable of matching either one address, two unique addresses, or
a range of addresses with a mask, based on the mode selected. The match uses seven or eight bits, depending on
the mode.
29.6.3.1.1 Address With Mask
An address written to the Address bits in the Address register (ADDR.ADDR), and a mask written to the Address
Mask bits in the Address register (ADDR.ADDRMASK) will yield an address match. All bits that are masked are not
included in the match. Note that writing the ADDR.ADDRMASK to 'all zeros' will match a single unique address, while
writing ADDR.ADDRMASK to 'all ones' will result in all addresses being accepted.
Figure 29-4. Address With Mask
ADDR
ADDRMASK
==
Match
rx shift register
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and its subsidiaries
Datasheet
DS60001638D-page 425
PIC32CM MC00 Family
Serial Communication Interface (SERCOM)
29.6.3.1.2 Two Unique Addresses
The two addresses written to ADDR and ADDRMASK will cause a match.
Figure 29-5. Two Unique Addresses
ADDR
==
Match
rx shift register
==
ADDRMASK
29.6.3.1.3 Address Range
The range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK will cause a match.
ADDR.ADDR and ADDR.ADDRMASK can be set to any two addresses, with ADDR.ADDR acting as the upper
limit and ADDR.ADDRMASK acting as the lower limit.
Figure 29-6. Address Range
ADDRMASK
29.6.4
rx shift register
ADDR
== Match
DMA Operation
The available DMA interrupts and their function depend on the operation mode of the SERCOM peripheral. Refer to
the Functional Description sections of the respective SERCOM mode.
For further information, see the following chapters:
• SERCOM SPI
• SERCOM USART
• SERCOM I2C
29.6.5
Interrupts
Interrupt sources are mode-specific. See the respective SERCOM mode chapters for details.
•
•
•
SERCOM SPI
SERCOM USART
SERCOM I2C
Each interrupt source has its own interrupt flag.
The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt condition is
met.
Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register
(INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).
As both INTENSET and INTENCLR always reflect the same value, the status of interrupt enablement can be read
from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the SERCOM is
reset. For details on clearing interrupt flags, refer to the INTFLAG register description.
The value of INTFLAG indicates which interrupt condition occurred. The user must read the INTFLAG register to
determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests.
For further information on Interrupts, refer to the NVIC.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 426
PIC32CM MC00 Family
Serial Communication Interface (SERCOM)
29.6.6
Sleep Mode Operation
The peripheral can operate in any sleep mode where the selected serial clock is running. This clock can be external
or generated by the internal baud-rate generator.
The SERCOM interrupts can be used to wake up the device from sleep modes. Refer to the different SERCOM mode
chapters for details.
• SERCOM SPI
• SERCOM USART
• SERCOM I2C
29.6.7
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 427
PIC32CM MC00 Family
SERCOM Synchronous and Asynchronous Receiver ...
30.
SERCOM Synchronous and Asynchronous Receiver and Transmitter
(SERCOM USART)
30.1
Overview
The Universal Synchronous and Asynchronous Receiver and Transmitter (USART) is one of the available modes in
the 29. Serial Communication Interface (SERCOM).
The USART uses the SERCOM transmitter and receiver, see 30.3 Block Diagram. Labels in uppercase letters are
synchronous to CLK_SERCOMx_APB and accessible for CPU. Labels in lowercase letters can be programmed to
run on the internal generic clock or an external clock.
The transmitter consists of a single write buffer, a shift register, and control logic for different frame formats. The
write buffer support data transmission without any delay between frames. The receiver consists of a two-level receive
buffer and a shift register. Status information of the received data is available for error checking. Data and clock
recovery units ensure robust synchronization and noise filtering during asynchronous data reception.
30.2
USART Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Full-duplex operation
Asynchronous (with clock reconstruction) or synchronous operation
Internal or external clock source for asynchronous and synchronous operation
Baud-rate generator
Supports serial frames with 5, 6, 7, 8 or 9 data bits and 1 or 2 stop bits
Odd or even parity generation and parity check
Selectable LSB or MSB first data transfer
Buffer overflow and frame error detection
Noise filtering, including false start-bit detection and digital low-pass filter
Collision detection
Can operate in all sleep modes
Operation at speeds up to half the system clock for internally generated clocks
Operation at speeds up to the system clock for externally generated clocks
RTS and CTS flow control
IrDA modulation and demodulation up to 115.2 kbps
LIN host support
LIN client support
– Auto-baud and break character detection
RS485 Support
Start-of-frame detection
Can work with DMA
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 428
PIC32CM MC00 Family
SERCOM Synchronous and Asynchronous Receiver ...
30.3
Block Diagram
Figure 30-1. USART Block Diagram
BAUD
GCLK
(internal)
TX DATA
Baud Rate Generator
/1 - /2 - /16
CTRLA.MODE
TX Shift Register
TxD
RX Shift Register
RxD
XCK
CTRLA.MODE
30.4
Status
RX Buffer
STATUS
RX DATA
Signal Description
Table 30-1. SERCOM USART Signals
Signal Name
Type
Description
PAD[3:0]
Digital I/O
General SERCOM pins
One signal can be mapped to one of several pins.
For additional information, refer to the Pinout.
30.5
Peripheral Dependencies
Refer to section 29.5 SERCOM Peripheral Dependencies.
30.6
Functional Description
30.6.1
Principle of Operation
The USART uses the following lines for data transfer:
•
•
•
RxD for receiving
TxD for transmitting
XCK for the transmission clock in synchronous operation
USART data transfer is frame based. A serial frame consists of:
•
•
•
•
1 start bit
From 5 to 9 data bits (MSB or LSB first)
No, even or odd parity bit
1 or 2 stop bits
A frame starts with the start bit followed by one character of data bits. If enabled, the parity bit is inserted after the
data bits and before the first stop bit. After the stop bit(s) of a frame, either the next frame can follow immediately,
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Datasheet
DS60001638D-page 429
PIC32CM MC00 Family
SERCOM Synchronous and Asynchronous Receiver ...
or the communication line can return to the idle (high) state. The figure below illustrates the possible frame formats.
Values inside brackets ([x]) denote optional bits.
Figure 30-2. Frame Formats
Frame
(IDLE)
St
St
0
1
3
4
[5]
[6]
[7]
[8]
[P]
Sp1
[Sp2]
[St/IDL]
Start bit. Signal is always low.
n, [n]
Data bits. 0 to [5..9]
[P]
Parity bit. Either odd or even.
Sp, [Sp]
IDLE
30.6.2
2
Stop bit. Signal is always high.
No frame is transferred on the communication line. Signal is always high in this state.
Basic Operation
30.6.2.1 Initialization
The following registers are enable-protected, meaning they can only be written when the USART is disabled
(CTRL.ENABLE=0):
•
•
•
Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits.
Control B register (CTRLB), except the Receiver Enable (RXEN) and Transmitter Enable (TXEN) bits.
Baud register (BAUD)
When the USART is enabled or is being enabled (CTRLA.ENABLE=1), any writing attempt to these registers will be
discarded. If the peripheral is being disabled, writing to these registers will be executed after disabling is completed.
Enable-protection is denoted by the "Enable-Protection" property in the register description.
Before the USART is enabled, it must be configured by these steps:
1.
Select either external (0x0) or internal clock (0x1) by writing the Operating Mode value in the CTRLA register
(CTRLA.MODE).
2. Select either asynchronous (0) or or synchronous (1) communication mode by writing the Communication
Mode bit in the CTRLA register (CTRLA.CMODE).
3. Select pin for receive data by writing the Receive Data Pinout value in the CTRLA register (CTRLA.RXPO).
4. Select pads for the transmitter and external clock by writing the Transmit Data Pinout bit in the CTRLA register
(CTRLA.TXPO).
5. Configure the Character Size field in the CTRLB register (CTRLB.CHSIZE) for character size.
6. Set the Data Order bit in the CTRLA register (CTRLA.DORD) to determine MSB- or LSB-first data
transmission.
7. To use parity mode:
7.1.
Enable parity mode by writing 0x1 to the Frame Format field in the CTRLA register (CTRLA.FORM).
7.2.
Configure the Parity Mode bit in the CTRLB register (CTRLB.PMODE) for even or odd parity.
8. Configure the number of stop bits in the Stop Bit Mode bit in the CTRLB register (CTRLB.SBMODE).
9. When using an internal clock, write the Baud register (BAUD) to generate the desired baud rate.
10. Enable the transmitter and receiver by writing '1' to the Receiver Enable and Transmitter Enable bits in the
CTRLB register (CTRLB.RXEN and CTRLB.TXEN).
30.6.2.2 Enabling, Disabling, and Resetting
This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by
writing '0' to it.
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SERCOM Synchronous and Asynchronous Receiver ...
The peripheral must be enabled (CTRLA.ENABLE = 1) before issuing the Software Reset.
Refer to the CTRLA register description for details.
30.6.2.3 Clock Generation and Selection
For both synchronous and asynchronous modes, the clock used for shifting and sampling data can be generated
internally by the SERCOM baud-rate generator or supplied externally through the XCK line.
The synchronous mode is selected by writing a '1' to the Communication Mode bit in the Control A register
(CTRLA.CMODE), the asynchronous mode is selected by writing a ‘0’ to CTRLA.CMODE.
The internal clock source is selected by writing a ‘1’ to the Operation Mode bit field in the Control A register
(CTRLA.MODE), the external clock source is selected by writing a ‘0’ to CTRLA.MODE.
The SERCOM baud-rate generator is configured as in the figure below.
In asynchronous mode (CTRLA.CMODE=0), the 16-bit Baud register value is used.
In synchronous mode (CTRLA.CMODE=1), the eight LSBs of the Baud register are used. Refer to Clock Generation
– Baud-Rate Generator for details on configuring the baud rate.
Figure 30-3. Clock Generation
XCKInternal Clk
(GCLK)
Baud Rate Generator
1
0
CTRLA.MODE[0]
Base
Period
/2
/1
/8
/2
/8
0 Tx Clk
1
1
0
XCK
CTRLA.CMODE
1 Rx Clk
0
30.6.2.3.1 Synchronous Clock Operation
In synchronous mode, the CTRLA.MODE bit field determines whether the transmission clock line (XCK) serves either
as input or output. The dependency between clock edges, data sampling, and data change is the same for internal
and external clocks. Data input on the RxD pin is sampled at the opposite XCK clock edge when data is driven on the
TxD pin.
The Clock Polarity bit in the Control A register (CTRLA.CPOL) selects which XCK clock edge is used for RxD
sampling, and which is used for TxD change:
When CTRLA.CPOL is '0', the data will be changed on the rising edge of XCK, and sampled on the falling edge of
XCK.
When CTRLA.CPOL is '1', the data will be changed on the falling edge of XCK, and sampled on the rising edge of
XCK.
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SERCOM Synchronous and Asynchronous Receiver ...
Figure 30-4. Synchronous Mode XCK Timing
Change
XCK
CTRLA.CPOL=1
RxD / TxD
Change
Sample
XCK
CTRLA.CPOL=0
RxD / TxD
Sample
When the clock is provided through XCK (CTRLA.MODE=0x0), the shift registers operate directly on the XCK clock.
This means that XCK is not synchronized with the system clock and, therefore, can operate at frequencies up to the
system frequency.
30.6.2.4 Data Register
The USART Transmit Data register (TxDATA) and USART Receive Data register (RxDATA) share the same I/O
address, referred to as the Data register (DATA). Writing the DATA register will update the TxDATA register. Reading
the DATA register will return the contents of the RxDATA register.
30.6.2.5 Data Transmission
Data transmission is initiated by writing the data to be sent into the DATA register. Then, the data in TxDATA will be
moved to the shift register when the shift register is empty and ready to send a new frame. After the shift register is
loaded with data, the data frame will be transmitted.
When the entire data frame including stop bit(s) has been transmitted and no new data was written to DATA, the
Transmit Complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set, and the
optional interrupt will be generated.
The Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) indicates that the
register is empty and ready for new data. The DATA register should only be written to when INTFLAG.DRE is set.
30.6.2.5.1 Disabling the Transmitter
The transmitter is disabled by writing '0' to the Transmitter Enable bit in the CTRLB register (CTRLB.TXEN).
Disabling the transmitter will complete only after any ongoing and pending transmissions are completed, i.e., there is
no data in the transmit shift register and TxDATA to transmit.
30.6.2.6 Data Reception
The receiver accepts data when a valid Start bit is detected. Each bit following the Start bit will be sampled according
to the baud rate or XCK clock, and shifted into the receive shift register until the first Stop bit of a frame is received.
The second Stop bit will be ignored by the receiver.
When the first Stop bit is received and a complete serial frame is present in the Receive Shift register, the contents
of the Shift register will be moved into the two-level receive buffer. Then, the Receive Complete Interrupt flag in the
Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set, and the optional interrupt can be generated.
The received data can be read from the DATA register when the Receive Complete Interrupt flag is set.
30.6.2.6.1 Disabling the Receiver
Writing '0' to the Receiver Enable bit in the CTRLB register (CTRLB.RXEN) will disable the receiver, flush the
two-level receive buffer, and data from ongoing receptions will be lost.
30.6.2.6.2 Error Bits
The USART receiver has three error bits in the Status (STATUS) register: Frame Error (FERR), Buffer Overflow
(BUFOVF), and Parity Error (PERR). Once an error happens, the corresponding error bit will be set until it is cleared
by writing ‘1’ to it. These bits are also cleared automatically when the receiver is disabled.
There are two methods for buffer overflow notification, selected by the Immediate Buffer Overflow Notification bit in
the Control A register (CTRLA.IBON):
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When CTRLA.IBON=1, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the
receive FIFO by reading RxDATA, until the Receiver Complete Interrupt flag (INTFLAG.RXC) is cleared.
When CTRLA.IBON=0, the Buffer Overflow condition is attending data through the receive FIFO. After the received
data is read, STATUS.BUFOVF and INTFLAG.ERROR will be set along with INTFLAG.RXC.
30.6.2.6.3 Asynchronous Data Reception
The USART includes a clock recovery and data recovery unit for handling asynchronous data reception.
The clock recovery logic can synchronize the incoming asynchronous serial frames at the RxD pin to the internally
generated baud-rate clock.
The data recovery logic samples and applies a low-pass filter to each incoming bit, thereby improving the noise
immunity of the receiver.
30.6.2.6.4 Asynchronous Operational Range
The operational range of the asynchronous reception depends on the accuracy of the internal baud-rate clock, the
rate of the incoming frames, and the frame size (in number of bits). In addition, the operational range of the receiver
is depending on the difference between the received bit rate and the internally generated baud rate. If the baud rate
of an external transmitter is too high or too low compared to the internally generated baud rate, the receiver will not
be able to synchronize the frames to the start bit.
There are two possible sources for a mismatch in baud rate: First, the reference clock will always have some minor
instability. Second, the baud-rate generator cannot always do an exact division of the reference clock frequency to
get the baud rate desired. In this case, the BAUD register value should be set to give the lowest possible error. Refer
to Clock Generation – Baud-Rate Generator for details.
The recommended maximum receiver baud-rate errors for various character sizes are shown in the following table.
Table 30-2. Asynchronous Receiver Error for 16-fold Oversampling
D
(Data bits+Parity)
RSLOW [%]
RFAST [%]
Max. total error [%]
Recommended max. Rx error [%]
5
94.12
107.69
+5.88/-7.69
±2.5
6
94.92
106.67
+5.08/-6.67
±2.0
7
95.52
105.88
+4.48/-5.88
±2.0
8
96.00
105.26
+4.00/-5.26
±2.0
9
96.39
104.76
+3.61/-4.76
±1.5
10
96.70
104.35
+3.30/-4.35
±1.5
The following equations calculate the ratio of the incoming data rate and internal receiver baud rate:
RSLOW =
•
•
•
•
•
•
D+ 1 S
S − 1 + D ⋅ S + SF
,
RFAST =
D+ 2 S
D + 1 S + SM
RSLOW is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate
RFAST is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate
D is the sum of character size and parity size (D = 5 to 10 bits)
S is the number of samples per bit (S = 16, 8 or 3)
SF is the first sample number used for majority voting (SF = 7, 3, or 2) when CTRLA.SAMPA=0.
SM is the middle sample number used for majority voting (SM = 8, 4, or 2) when CTRLA.SAMPA=0.
The recommended maximum Rx Error assumes that the receiver and transmitter equally divide the maximum total
error. Its connection to the SERCOM Receiver error acceptance is depicted in this figure:
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SERCOM Synchronous and Asynchronous Receiver ...
Figure 30-5. USART Rx Error Calculation
SERCOM Receiver error acceptance
from RSLOW and RFAST formulas
Error Max (%)
+
+ offset error
Baud Generator
depends on BAUD register value
Clock source error
+
Recommended max. Rx Error (%)
Baud Rate
Error Min (%)
The recommendation values in the table above accommodate errors of the clock source and the baud generator. The
following figure gives an example for a baud rate of 3Mbps:
Figure 30-6. USART Rx Error Calculation Example
SERCOM Receiver error acceptance
sampling = x16
data bits = 10
parity = 0
start bit = stop bit = 1
Error Max 3.3%
+
No baud generator offset error
Accepted
Receiver
Error
+
+
Fbaud(2Mbps) = 32MHz *1(BAUD=0) /16
Transmitter Error*
Error Max 3.3%
Error Max 3.0%
Baud Rate 2Mbps
Error Min -4.05%
Error Min -4.35%
Error Min -4.35%
security margin
*Transmitter Error depends on the external transmitter used in the application.
It is advised that it is within the Recommended max. Rx Error (+/-1.5% in this example).
Larger Transmitter Errors are acceptable but must lie within the Accepted Receiver Error.
30.6.3
Recommended
max. Rx Error +/-1.5%
(example)
Additional Features
30.6.3.1 Parity
Even or odd parity can be selected for error checking by writing 0x1 to the Frame Format bit field in the Control A
register (CTRLA.FORM).
If even parity is selected (CTRLB.PMODE=0), the parity bit of an outgoing frame is '1' if the data contains an odd
number of bits that are '1', making the total number of '1' even.
If odd parity is selected (CTRLB.PMODE=1), the parity bit of an outgoing frame is '1' if the data contains an even
number of bits that are '0', making the total number of '1' odd.
When parity checking is enabled, the parity checker calculates the parity of the data bits in incoming frames and
compares the result with the parity bit of the corresponding frame. If a parity error is detected, the Parity Error bit in
the Status register (STATUS.PERR) is set.
30.6.3.2 Hardware Handshaking
The USART features an out-of-band hardware handshaking flow control mechanism, implemented by connecting the
RTS and CTS pins with the remote device, as shown in the figure below.
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Figure 30-7. Connection with a Remote Device for Hardware Handshaking
USART
Remote
Device
TXD
RXD
RXD
TXD
CTS
RTS
CTS
RTS
Hardware handshaking is only available in the following configuration:
•
•
•
USART with internal clock (CTRLA.MODE=1),
Asynchronous mode (CTRLA.CMODE=0),
and Flow control pinout (CTRLA.TXPO=2).
When the receiver is disabled or the receive FIFO is full, the receiver will drive the RTS pin high. This notifies
the remote device to stop transfer after the ongoing transmission. Enabling and disabling the receiver by writing to
CTRLB.RXEN will set/clear the RTS pin after a synchronization delay. When the receive FIFO goes full, RTS will be
set immediately and the frame being received will be stored in the shift register until the receive FIFO is no longer full.
Figure 30-8. Receiver Behavior when Operating with Hardware Handshaking
RXD
RXEN
RTS
Rx FIFO Full
The current CTS Status is in the STATUS register (STATUS.CTS). Character transmission will start only if
STATUS.CTS=0. When CTS is set, the transmitter will complete the ongoing transmission and stop transmitting.
Figure 30-9. Transmitter Behavior when Operating with Hardware Handshaking
CTS
TXD
30.6.3.3 IrDA Modulation and Demodulation
Transmission and reception can be encoded IrDA compliant up to 115.2 kb/s. IrDA modulation and demodulation
work in the following configuration:
•
•
•
IrDA encoding enabled (CTRLB.ENC = 1),
Asynchronous mode (CTRLA.CMODE = 0),
and 16x sample rate (CTRLA.SAMPR[0] = 0).
During transmission, each low bit is transmitted as a high pulse. The pulse width is 3/16 of the baud rate period, as
illustrated in the figure below.
Figure 30-10. IrDA Transmit Encoding
1 baud clock
TXD
IrDA encoded TXD
3/16 baud clock
The reception decoder has two main functions.
The first is to synchronize the incoming data to the IrDA baud rate counter. Synchronization is performed at the start
of each zero pulse.
The second main function is to decode incoming Rx data. If a pulse width meets the minimum length set by
configuration (RXPL.RXPL), it is accepted. When the baud rate counter reaches its middle value (1/2 bit length), it is
transferred to the receiver.
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Note: The polarity of the transmitter and receiver are opposite: During transmission, a '0' bit is transmitted as a '1'
pulse. During reception, an accepted '0' pulse is received as a '0' bit.
Example: The figure below illustrates reception where RXPL.RXPL is set to 19. This indicates that
the pulse width should be at least 20 SE clock cycles. When using BAUD = 0xE666 or 160 SE
cycles per bit, this corresponds to 2/16 baud clock as minimum pulse width required. In this case
the first bit is accepted as a '0', the second bit is a '1', and the third bit is also a '1'. A low pulse is
rejected since it does not meet the minimum requirement of 2/16 baud clock.
Figure 30-11. IrDA Receive Decoding
Baud clock
0
0.5
1
1.5
2
2.5
IrDA encoded RXD
RXD
20 SE clock cycles
30.6.3.4 Break Character Detection and Auto-Baud
Break character detection and auto-baud are available in the following configuration:
•
•
•
Auto-baud frame format (CTRLA.FORM = 0x04 or 0x05),
Asynchronous mode (CTRLA.CMODE = 0),
16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1).
The USART uses a break detection threshold of greater than 11 nominal bit times at the configured baud rate. At any
time, if more than 11 consecutive dominant bits are detected on the bus, the USART detects a Break Field. When a
Break Field has been detected, the Receive Break interrupt flag (INTFLAG.RXBRK) is set and the USART expects
the Sync Field character to be 0x55. This field is used to update the actual baud rate in order to stay synchronized.
If the received Sync character is not 0x55, then the Inconsistent Sync Field error flag (STATUS.ISF) is set along with
the Error interrupt flag (INTFLAG.ERROR), and the baud rate is unchanged.
After a break field is detected and the start bit of the Sync Field is detected, a counter is started. The counter is then
incremented for the next 8 bit times of the Sync Field. At the end of these 8 bit times, the counter is stopped. At this
moment, the 13 most significant bits of the counter (value divided by 8) give the new clock divider (BAUD.BAUD),
and the 3 least significant bits of this value (the remainder) give the new Fractional Part (BAUD.FP).
When the Sync Field has been received, the clock divider (BAUD.BAUD) and the Fractional Part (BAUD.FP) are
updated after a synchronization delay. After the Break and Sync Fields are received, multiple characters of data can
be received.
30.6.3.5 LIN Host
LIN host is available with the following configuration:
•
•
•
LIN host format (CTRLA.FORM = 0x02)
Asynchronous mode (CTRLA.CMODE = 0)
16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1)
LIN frames start with a header transmitted by the host. The header consists of the break, sync, and identifier fields.
After the host transmits the header, the addressed client will respond with 1-8 bytes of data plus checksum.
Figure 30-12. LIN Frame Format
TxD
RxD
Header
Break Sync
ID
Client response
1-8 Data bytes
Checksum
Using the LIN command field (CTRLB.LINCMD), the complete header can be automatically transmitted, or software
can control transmission of the various header components.
When CTRLB.LINCMD=0x1, software controls transmission of the LIN header. In this case, software uses the
following sequence.
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SERCOM Synchronous and Asynchronous Receiver ...
•
•
•
•
CTRLB.LINCMD is written to 0x1.
DATA register written to 0x00. This triggers transmission of the break field by hardware. Note that writing the
DATA register with any other value will also result in the transmission of the break field by hardware.
DATA register written to 0x55. The 0x55 value (sync) is transmitted.
DATA register written to the identifier. The identifier is transmitted.
When CTRLB.LINCMD=0x2, hardware controls transmission of the LIN header. In this case, software uses the
following sequence.
•
•
CTRLB.LINCMD is written to 0x2.
DATA register written to the identifier. This triggers transmission of the complete header by hardware. First the
break field is transmitted. Next, the sync field is transmitted, and finally the identifier is transmitted.
In LIN host mode, the length of the break field is programmable using the break length field (CTRLC.BRKLEN). When
the LIN header command is used (CTRLB.LINCMD=0x2), the delay between the break and sync fields, in addition
to the delay between the sync and ID fields are configurable using the header delay field (CTRLC.HDRDLY). When
manual transmission is used (CTRLB.LINCMD=0x1), software controls the delay between break and sync.
Figure 30-13. LIN Header Generation
Configurable
Break Field Length
LIN Header
Sync Field
Identifier Field
Configurable delay using CTRLC.HDRDLY
After header transmission is complete, the client responds with 1-8 data bytes plus checksum.
30.6.3.6 RS485
RS485 is available with the following configuration:
• USART frame format (CTRLA.FORM = 0x00 or 0x01)
• RS485 pinout (CTRLA.TXPO=0x3).
The RS485 feature enables control of an external line driver as shown in the figure below. While operating in RS485
mode, the transmit enable pin (TE) is driven high when the transmitter is active.
Figure 30-14. RS485 Bus Connection
USART
RXD
Differential
Bus
TXD
TE
The TE pin will remain high for the complete frame including stop bit(s). If a Guard Time is programmed in the Control
C register (CTRLC.GTIME), the line will remain driven after the last character completion. The following figure shows
a transfer with one stop bit and CTRLC.GTIME=3.
Figure 30-15. Example of TE Drive with Guard Time
Start
Data
Stop GTIME=3
TXD
TE
The Transmit Complete interrupt flag (INTFLAG.TXC) will be raised after the guard time is complete and TE goes
low.
30.6.3.7 Collision Detection
When the receiver and transmitter are connected either through pin configuration or externally, transmit collision can
be detected after selecting the Collision Detection Enable bit in the CTRLB register (CTRLB.COLDEN = 1). To detect
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collision, the receiver and transmitter must be enabled (CTRLB.RXEN = 1 and CTRLB.TXEN = 1) and the peripheral
bus (APB) must operate at or above the SERCOMx GCLK frequency.
Collision detection is performed for each bit transmitted by comparing the received value with the transmit value, as
shown in the figure below. While the transmitter is idle (no transmission in progress), characters can be received on
RxD without triggering a collision.
Figure 30-16. Collision Checking
8-bit character, single stop bit
TXD
RXD
Collision checked
The figure below illustrates the conditions for a collision detection. In this case, the start bit and the first data bit
are received with the same value as transmitted. The second received data bit is found to be different than the
transmitted bit at the detection point, which indicates a collision.
Figure 30-17. Collision Detected
Collision checked and ok
Tri-state
TXD
RXD
TXEN
Collision detected
When a collision is detected, the USART follows these sequence:
1. Abort the current transfer.
2. Flush the transmit buffer.
3. Disable transmitter (CTRLB.TXEN = 0).
– This is done after a synchronization delay. The CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB)
will be set until this is complete.
– After disabling, the TxD pin will be tri-stated.
4. Set the Collision Detected bit (STATUS.COLL) along with the Error interrupt flag (INTFLAG.ERROR).
5. Set the Transmit Complete interrupt flag (INTFLAG.TXC), becasue the transmit buffer no longer contains data.
After a collision, software must manually enable the transmitter again before continuing, after assuring that the
CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) is not set.
30.6.3.8 Loop-Back Mode
For loop-back mode, configure the Receive Data Pinout (CTRLA.RXPO) and Transmit Data Pinout (CTRLA.TXPO)
to use the same data pins for transmit and receive. The loop-back is through the pad, so the signal is also available
externally.
30.6.3.9 Start-of-Frame Detection
The USART start-of-frame detector can wake up the CPU when it detects a start bit. In standby sleep mode, the
internal fast startup oscillator must be selected as the GCLK_SERCOMx_CORE source.
When a 1-to-0 transition is detected on RxD, the 8MHz Internal Oscillator is powered up and the USART clock is
enabled. After startup, the rest of the data frame can be received, provided that the baud rate is slow enough in
relation to the fast startup internal oscillator start-up time. Refer to 43. Electrical Characteristics 85℃ for details. The
start-up time of this oscillator varies with supply voltage and temperature.
The USART start-of-frame detection works both in asynchronous and synchronous modes. It is enabled by writing ‘1’
to the Start of Frame Detection Enable bit in the Control B register (CTRLB.SFDE).
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If the Receive Start Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.RXS) is set, the Receive Start
interrupt is generated immediately when a start is detected.
When using start-of-frame detection without the Receive Start interrupt, start detection will force the 8MHz Internal
Oscillator and USART clock active while the frame is being received. In this case, the CPU will not wake up until the
Receive Complete interrupt is generated.
30.6.3.10 Sample Adjustment
In asynchronous mode (CTRLA.CMODE=0), three samples in the middle are used to determine the value based on
majority voting. The three samples used for voting can be selected using the Sample Adjustment bit field in Control
A register (CTRLA.SAMPA). When CTRLA.SAMPA=0, samples 7-8-9 are used for 16x oversampling, and samples
3-4-5 are used for 8x oversampling.
30.6.4
DMA, Interrupts and Events
Table 30-3. Module Request for SERCOM USART
Condition
Request
DMA
Interrupt
Event
Data Register Empty (DRE)
Yes
(request cleared when data is written)
Yes
NA
Receive Complete (RXC)
Yes
(request cleared when data is read)
Yes
Transmit Complete (TXC)
NA
Yes
Receive Start (RXS)
NA
Yes
Clear to Send Input Change (CTSIC)
NA
Yes
Receive Break (RXBRK)
NA
Yes
Error (ERROR)
NA
Yes
30.6.4.1 DMA Operation
The USART generates the following DMA requests:
•
•
Data received (RX): The request is set when data is available in the receive FIFO. The request is cleared when
DATA is read.
Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when
DATA is written.
30.6.4.2 Interrupts
The USART has the following interrupt sources. These are asynchronous interrupts, and can wake up the device
from any sleep mode:
•
•
•
•
•
•
•
Data Register Empty (DRE)
Receive Complete (RXC)
Transmit Complete (TXC)
Receive Start (RXS)
Clear to Send Input Change (CTSIC)
Received Break (RXBRK)
Error (ERROR)
Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG) will be set when the interrupt condition is met. Each interrupt can be individually enabled by writing
'1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing '1' to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). As both the INTENSET and INTENCLR
registers always reflect the same value, the status of interrupt enablement can be read from either register.
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An interrupt request is generated when the interrupt flag is set and if the corresponding interrupt is enabled. The
interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the USART is
reset. For details on clearing interrupt flags, refer to the INTFLAG register description.
The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for
interrupt requests. Refer to Nested Vector Interrupt Controller for details.
When the Data Register Empty (DRE) interrupt is enabled, it is necessary to write the DATA register before entering
standby mode.
30.6.5
Sleep Mode Operation
The behavior in Sleep mode is depending on the clock source and the Run In Standby bit in the Control A register
(CTRLA.RUNSTDBY):
• Internal clocking, CTRLA.RUNSTDBY = 1: GCLK_SERCOMx_CORE can be enabled in all sleep modes. Any
interrupt can wake up the device (except Frame error (FERR) and Parity error (PERR) that are part of the
ERROR interrupt).
• External clocking, CTRLA.RUNSTDBY = 1: The Receive Start and the Receive Complete interrupts can wake
up the device. Any interrupt can wake up the device (except Frame error (FERR) and Parity error (PERR) that
are part of the ERROR interrupt).
• Internal clocking, CTRLA.RUNSTDBY = 0: Internal clock will be disabled, after any ongoing transfer was
completed. The Receive Start and the Receive Complete interrupt(s) can wake up the device.
• External clocking, CTRLA.RUNSTDBY = 0: External clock will be disconnected, after any ongoing transfer was
completed. All reception will be dropped.
When targeting the lowest STANDBY power consumption for a transmit only application, the Receiver must remain
disabled, but the receiver data pinout (CTRLA.RXPO) must be set to match the transmit data pinout (CTRLA.TXPO).
30.6.6
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
•
•
•
•
Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Receiver Enable bit in the CTRLB register (CTRLB.RXEN)
Transmitter Enable bit in the Control B register (CTRLB.TXEN)
Note: CTRLB.RXEN is write-synchronized somewhat differently. See also 30.7.2 CTRLB for details.
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 440
PIC32CM MC00 Family
SERCOM Synchronous and Asynchronous Receiver ...
30.7
Register Summary
Offset
Name
0x00
CTRLA
0x04
CTRLB
0x08
CTRLC
0x0C
BAUD
0x0E
0x0F
...
0x13
0x14
0x15
0x16
0x17
0x18
0x19
RXPL
INTENCLR
Reserved
INTENSET
Reserved
INTFLAG
Reserved
0x1A
STATUS
0x1C
SYNCBUSY
0x20
...
0x27
Reserved
0x28
DATA
Bit Pos.
7
6
5
4
3
2
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
7:0
RUNSTDBY
7:0
ERROR
RXBRK
CTSIC
RXS
RXC
TXC
DRE
7:0
ERROR
RXBRK
CTSIC
RXS
RXC
TXC
DRE
7:0
ERROR
RXBRK
CTSIC
RXS
RXC
TXC
DRE
COLL
ISF
CTS
BUFOVF
FERR
PERR
CTRLB
ENABLE
SWRST
MODE[2:0]
SAMPR[2:0]
SAMPA[1:0]
DORD
SBMODE
RXPO[1:0]
CPOL
CMODE
1
0
ENABLE
SWRST
IBON
TXPO[1:0]
FORM[3:0]
CHSIZE[2:0]
ENC
SFDE
COLDEN
RXEN
TXEN
LINCMD[1:0]
GTIME[2:0]
HDRDLY[1:0]
BRKLEN[1:0]
PMODE
BAUD[7:0]
BAUD[15:8]
RXPL[7:0]
Reserved
7:0
15:8
7:0
15:8
23:16
31:24
7:0
15:8
© 2021 Microchip Technology Inc.
and its subsidiaries
TXE
DATA[7:0]
DATA[8]
Datasheet
DS60001638D-page 441
PIC32CM MC00 Family
SERCOM Synchronous and Asynchronous Receiver ...
30.7.1
Control A
Name:
Offset:
Reset:
Property:
Bit
31
Access
Reset
Bit
29
CPOL
R/W
0
28
CMODE
R/W
0
R/W
0
21
20
19
22
SAMPA[1:0]
R/W
R/W
0
0
Bit
15
Access
Reset
Access
Reset
30
DORD
R/W
0
23
Access
Reset
Bit
CTRLA
0x00
0x00000000
PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits
R/W
0
7
RUNSTDBY
R/W
0
27
26
25
24
R/W
0
R/W
0
R/W
0
18
17
FORM[3:0]
RXPO[1:0]
R/W
0
R/W
0
13
12
11
4
3
MODE[2:0]
R/W
0
14
SAMPR[2:0]
R/W
0
R/W
0
6
5
16
TXPO[1:0]
R/W
0
R/W
0
R/W
0
10
9
8
IBON
R/W
0
2
1
ENABLE
R/W
0
0
SWRST
R/W
0
R/W
0
Bit 30 – DORD Data Order
This bit selects the data order when a character is shifted out from the Data register.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
MSB is transmitted first.
LSB is transmitted first.
Bit 29 – CPOL Clock Polarity
This bit selects the relationship between data output change and data input sampling in synchronous mode.
Note: This bit is enable-protected. This bit is not synchronized.
CPOL
TxD Change
RxD Sample
0x0
0x1
Rising XCK edge
Falling XCK edge
Falling XCK edge
Rising XCK edge
Bit 28 – CMODE Communication Mode
This bit selects asynchronous or synchronous communication.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
Asynchronous communication.
Synchronous communication.
Bits 27:24 – FORM[3:0] Frame Format
These bits define the frame format.
Note: This bit field is enable-protected. This bit field is not synchronized.
FORM[3:0]
Description
0x0
USART frame
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 442
PIC32CM MC00 Family
SERCOM Synchronous and Asynchronous Receiver ...
...........continued
FORM[3:0]
Description
0x1
0x2
0x3
0x4
0x5
0x6-0xF
USART frame with parity
LIN Host - Break and sync generation. See LIN Command (CTRLB.LINCMD).
Reserved
Auto-baud (LIN Client) - break detection and auto-baud.
Auto-baud - break detection and auto-baud with parity
Reserved
Bits 23:22 – SAMPA[1:0] Sample Adjustment
These bits define the sample adjustment.
Note: This bit field is enable-protected. This bit field is not synchronized.
SAMPA[1:0]
16x Over-sampling (CTRLA.SAMPR=0 or 1)
8x Over-sampling (CTRLA.SAMPR=2 or 3)
0x0
0x1
0x2
0x3
7-8-9
9-10-11
11-12-13
13-14-15
3-4-5
4-5-6
5-6-7
6-7-8
Bits 21:20 – RXPO[1:0] Receive Data Pinout
These bits define the receive data (RxD) pin configuration.
Note: This bit field is enable-protected. This bit field is not synchronized.
RXPO[1:0]
Name
Description
0x0
0x1
0x2
0x3
PAD[0]
PAD[1]
PAD[2]
PAD[3]
SERCOM PAD[0] is used for data reception
SERCOM PAD[1] is used for data reception
SERCOM PAD[2] is used for data reception
SERCOM PAD[3] is used for data reception
Bits 17:16 – TXPO[1:0] Transmit Data Pinout
These bits define the transmit data (TxD) and XCK pin configurations.
Note: This bit field is enable-protected. This bit field is not synchronized.
TXPO
TxD Pin Location
XCK Pin Location (When Applicable)
RTS/TE
CTS
0x0
0x1
0x2
0x3
SERCOM PAD[0]
SERCOM PAD[2]
SERCOM PAD[0]
SERCOM_PAD[0]
SERCOM PAD[1]
SERCOM PAD[3]
N/A
SERCOM_PAD[1]
N/A
N/A
SERCOM PAD[2]
SERCOM_PAD[2]
N/A
N/A
SERCOM PAD[3]
N/A
Bits 15:13 – SAMPR[2:0] Sample Rate
These bits select the sample rate.
Note: This bit field is enable-protected. This bit field is not synchronized.
SAMPR[2:0]
Description
0x0
0x1
0x2
0x3
0x4
0x5-0x7
16x over-sampling using arithmetic baud rate generation.
16x over-sampling using fractional baud rate generation.
8x over-sampling using arithmetic baud rate generation.
8x over-sampling using fractional baud rate generation.
3x over-sampling using arithmetic baud rate generation.
Reserved
Bit 8 – IBON Immediate Buffer Overflow Notification
This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs.
Note: This bit is enable-protected. This bit is not synchronized.
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and its subsidiaries
Datasheet
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PIC32CM MC00 Family
SERCOM Synchronous and Asynchronous Receiver ...
Value
0
1
Description
STATUS.BUFOVF is asserted when it occurs in the data stream.
STATUS.BUFOVF is asserted immediately upon buffer overflow.
Bit 7 – RUNSTDBY Run In Standby
This bit defines the functionality in standby sleep mode.
Note: This bit is enable-protected. This bit is not synchronized.
RUNSTDBY External Clock
0x0
0x1
Internal Clock
External clock is disconnected when Generic clock is disabled when ongoing transfer is finished.
ongoing transfer is finished. All
The device will not wake up on either Receive Start or Transfer
reception is dropped.
Complete interrupt unless the appropriate ONDEMAND bits are
set in the clocking chain.
Wake on Receive Start or Receive
Generic clock is enabled in all sleep modes. Any interrupt can
Complete interrupt.
wake up the device.
Bits 4:2 – MODE[2:0] Operating Mode
These bits select the USART serial communication interface of the SERCOM.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
Description
USART with external clock
USART with internal clock
Bit 1 – ENABLE Enable
Notes:
1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
2. This bit is not enable-protected.
Value
0
1
Description
The peripheral is disabled or being disabled.
The peripheral is enabled or being enabled.
Bit 0 – SWRST Software Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will
be disabled.
Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register
will return the reset value of the register.
Notes:
1. This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST
synchronization is complete.
2. This bit is not enable-protected.
Value
0
1
Description
There is no reset operation ongoing.
The reset operation is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 444
PIC32CM MC00 Family
SERCOM Synchronous and Asynchronous Receiver ...
30.7.2
Control B
Name:
Offset:
Reset:
Property:
Bit
CTRLB
0x04
0x00000000
PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits
31
30
29
28
27
26
23
22
21
20
19
18
17
RXEN
R/W
0
16
TXEN
R/W
0
15
14
13
PMODE
R/W
0
12
11
10
ENC
R/W
0
9
SFDE
R/W
0
8
COLDEN
R/W
0
7
6
SBMODE
R/W
0
5
4
3
2
1
CHSIZE[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R/W
0
25
24
LINCMD[1:0]
R/W
R/W
0
0
R/W
0
Bits 25:24 – LINCMD[1:0] LIN Command
These bits define the LIN header transmission control. This field is only valid in LIN host mode (CTRLA.FORM= LIN
Host).
These are strobe bits and will always read back as zero.
Notes:
1. This bit field is write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the CTRLB.LINCMD
synchronization is complete.
2. This bit field is enable-protected.
Value
0x0
0x1
0x2
0x3
Description
Normal USART transmission.
Break field is transmitted when DATA is written.
Break, sync and identifier are automatically transmitted when DATA is written with the identifier.
Reserved
Bit 17 – RXEN Receiver Enable
Writing '0' to this bit will disable the USART receiver. Disabling the receiver will flush the receive buffer and clear the
FERR, PERR and BUFOVF bits in the STATUS register.
Writing '1' to CTRLB.RXEN when the USART is disabled will set CTRLB.RXEN immediately. When the USART
is enabled, CTRLB.RXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the receiver is
enabled. When the receiver is enabled, CTRLB.RXEN will read back as '1'.
Writing '1' to CTRLB.RXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the
receiver is enabled, and CTRLB.RXEN will read back as '1'.
Notes:
1. This bit is write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the CTRLB.RXEN
synchronization is complete.
2. This bit is not enable-protected.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 445
PIC32CM MC00 Family
SERCOM Synchronous and Asynchronous Receiver ...
Value
0
1
Description
The receiver is disabled or being enabled.
The receiver is enabled or will be enabled when the USART is enabled.
Bit 16 – TXEN Transmitter Enable
Writing '0' to this bit will disable the USART transmitter. Disabling the transmitter will not become effective until
ongoing and pending transmissions are completed.
Writing '1' to CTRLB.TXEN when the USART is disabled will set CTRLB.TXEN immediately. When the USART is
enabled, CTRLB.TXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the transmitter is
enabled. When the transmitter is enabled, CTRLB.TXEN will read back as '1'.
Writing '1' to CTRLB.TXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the
transmitter is enabled, and CTRLB.TXEN will read back as '1'.
Notes:
1. This bit is write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the CTRLB.TXEN
synchronization is complete.
2. This bit is not enable-protected.
Value
0
1
Description
The transmitter is disabled or being enabled.
The transmitter is enabled or will be enabled when the USART is enabled.
Bit 13 – PMODE Parity Mode
This bit selects the type of parity used when parity is enabled (CTRLA.FORM is '1'). The transmitter will automatically
generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value
for the incoming data and parity bit, compare it to the parity mode and, if a mismatch is detected, STATUS.PERR will
be set.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
Even parity.
Odd parity.
Bit 10 – ENC Encoding Format
This bit selects the data encoding format.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
Data is not encoded.
Data is IrDA encoded.
Bit 9 – SFDE Start of Frame Detection Enable
This bit controls whether the start-of-frame detector will wake up the device when a start bit is detected on the RxD
line.
Note: This bit is enable-protected. This bit is not synchronized.
SFDE INTENSET.RXS INTENSET.RXC Description
0
1
1
X
0
0
X
0
1
1
1
0
1
1
1
Start-of-frame detection disabled.
Reserved
Start-of-frame detection enabled. RXC wakes up the device from all
sleep modes.
Start-of-frame detection enabled. RXS wakes up the device from all
sleep modes.
Start-of-frame detection enabled. Both RXC and RXS wake up the
device from all sleep modes.
Bit 8 – COLDEN Collision Detection Enable
This bit enables collision detection.
Note: This bit is enable-protected. This bit is not synchronized.
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Datasheet
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PIC32CM MC00 Family
SERCOM Synchronous and Asynchronous Receiver ...
Value
0
1
Description
Collision detection is not enabled.
Collision detection is enabled.
Bit 6 – SBMODE Stop Bit Mode
This bit selects the number of stop bits transmitted.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
One stop bit.
Two stop bits.
Bits 2:0 – CHSIZE[2:0] Character Size
These bits select the number of bits in a character.
Note: This bit is enable-protected. This bit is not synchronized.
CHSIZE[2:0]
Description
0x0
0x1
0x2-0x4
0x5
0x6
0x7
8 bits
9 bits
Reserved
5 bits
6 bits
7 bits
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 447
PIC32CM MC00 Family
SERCOM Synchronous and Asynchronous Receiver ...
30.7.3
Control C
Name:
Offset:
Reset:
Property:
Bit
CTRLC
0x08
0x00000000
PAC Write-Protection, Enable-Protected
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
7
6
5
4
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
10
HDRDLY[1:0]
R/W
R/W
0
0
3
Access
Reset
2
R/W
0
9
8
BRKLEN[1:0]
R/W
R/W
0
0
1
GTIME[2:0]
R/W
0
0
R/W
0
Bits 11:10 – HDRDLY[1:0] LIN Host Header Delay
These bits define the delay between break and sync transmission in addition to the delay between the sync and
identifier (ID) fields when in LIN host mode (CTRLA.FORM=0x2).
This field is only valid when using the LIN header command (CTRLB.LINCMD=0x2).
Value
Description
0x0
Delay between break and sync transmission is 1 bit time.
0x1
Delay between sync and ID transmission is 1 bit time.
Delay between break and sync transmission is 4 bit time.
0x2
Delay between sync and ID transmission is 4 bit time.
Delay between break and sync transmission is 8 bit time.
0x3
Delay between sync and ID transmission is 4 bit time.
Delay between break and sync transmission is 14 bit time.
Delay between sync and ID transmission is 4 bit time.
Bits 9:8 – BRKLEN[1:0] LIN Host Break Length
These bits define the length of the break field transmitted when in LIN host mode (CTRLA.FORM=0x2).
Value
Description
0x0
Break field transmission is 13 bit times
0x1
Break field transmission is 17 bit times
0x2
Break field transmission is 21 bit times
0x3
Break field transmission is 26 bit times
Bits 2:0 – GTIME[2:0] Guard Time
These bits define the guard time when using RS485 mode (CTRLA.FORM=0x0 or CTRLA.FORM=0x1, and
CTRLA.TXPO=0x3).
For RS485 mode, the guard time is programmable from 0-7 bit times and defines the time that the transmit enable pin
(TE) remains high after the last stop bit is transmitted and there is no remaining data to be transmitted.
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
SERCOM Synchronous and Asynchronous Receiver ...
30.7.4
Baud
Name:
Offset:
Reset:
Property:
Bit
15
BAUD
0x0C
0x0000
Enable-Protected, PAC Write-Protection
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BAUD[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BAUD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BAUD[15:0] Baud Value
Arithmetic Baud Rate Generation (CTRLA.SAMPR[0]=0):
These bits control the clock generation, as described in the SERCOM Baud Rate section.
If Fractional Baud Rate Generation (CTRLA.SAMPR[0]=1) bit positions 15 to 13 are replaced by FP[2:0] Fractional
Part:
• Bits 15:13 - FP[2:0]: Fractional Part
•
These bits control the clock generation, as described in the SERCOM Clock Generation – Baud-Rate Generator
section.
Bits 12:0 - BAUD[12:0]: Baud Value
These bits control the clock generation, as described in the SERCOM Clock Generation – Baud-Rate Generator
section.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 449
PIC32CM MC00 Family
SERCOM Synchronous and Asynchronous Receiver ...
30.7.5
Receive Pulse Length Register
Name:
Offset:
Reset:
Property:
Bit
7
RXPL
0x0E
0x00
Enable-Protected, PAC Write-Protection
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
RXPL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – RXPL[7:0] Receive Pulse Length
When the encoding format is set to IrDA (CTRLB.ENC=1), these bits control the minimum pulse length that is
required for a pulse to be accepted by the IrDA receiver with regards to the serial engine clock period SEper.
PULSE ≥ RXPL + 2 ⋅ SEper
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Datasheet
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PIC32CM MC00 Family
SERCOM Synchronous and Asynchronous Receiver ...
30.7.6
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x14
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
Access
Reset
7
ERROR
R/W
0
6
5
RXBRK
R/W
0
4
CTSIC
R/W
0
3
RXS
R/W
0
2
RXC
R/W
0
1
TXC
R/W
0
0
DRE
R/W
0
Bit 7 – ERROR Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 5 – RXBRK Receive Break Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Receive Break Interrupt Enable bit, which disables the Receive Break interrupt.
Value
Description
0
Receive Break interrupt is disabled.
1
Receive Break interrupt is enabled.
Bit 4 – CTSIC Clear to Send Input Change Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Clear To Send Input Change Interrupt Enable bit, which disables the Clear To Send
Input Change interrupt.
Value
Description
0
Clear To Send Input Change interrupt is disabled.
1
Clear To Send Input Change interrupt is enabled.
Bit 3 – RXS Receive Start Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Receive Start Interrupt Enable bit, which disables the Receive Start interrupt.
Value
Description
0
Receive Start interrupt is disabled.
1
Receive Start interrupt is enabled.
Bit 2 – RXC Receive Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete
interrupt.
Value
Description
0
Receive Complete interrupt is disabled.
1
Receive Complete interrupt is enabled.
Bit 1 – TXC Transmit Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Transmit Complete Interrupt Enable bit, which disables the Receive Complete
interrupt.
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PIC32CM MC00 Family
SERCOM Synchronous and Asynchronous Receiver ...
Value
0
1
Description
Transmit Complete interrupt is disabled.
Transmit Complete interrupt is enabled.
Bit 0 – DRE Data Register Empty Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty
interrupt.
Value
Description
0
Data Register Empty interrupt is disabled.
1
Data Register Empty interrupt is enabled.
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Datasheet
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PIC32CM MC00 Family
SERCOM Synchronous and Asynchronous Receiver ...
30.7.7
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x16
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
Access
Reset
7
ERROR
R/W
0
6
5
RXBRK
R/W
0
4
CTSIC
R/W
0
3
RXS
R/W
0
2
RXC
R/W
0
1
TXC
R/W
0
0
DRE
R/W
0
Bit 7 – ERROR Error Interrupt Enable
The Frame Error (FERR) and Parity Error (PERR) error interrupts will not wake the device from Standby mode.
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 5 – RXBRK Receive Break Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Receive Break Interrupt Enable bit, which enables the Receive Break interrupt.
Value
Description
0
Receive Break interrupt is disabled.
1
Receive Break interrupt is enabled.
Bit 4 – CTSIC Clear to Send Input Change Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Clear To Send Input Change Interrupt Enable bit, which enables the Clear To Send
Input Change interrupt.
Value
Description
0
Clear To Send Input Change interrupt is disabled.
1
Clear To Send Input Change interrupt is enabled.
Bit 3 – RXS Receive Start Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Receive Start Interrupt Enable bit, which enables the Receive Start interrupt.
Value
Description
0
Receive Start interrupt is disabled.
1
Receive Start interrupt is enabled.
Bit 2 – RXC Receive Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete
interrupt.
Value
Description
0
Receive Complete interrupt is disabled.
1
Receive Complete interrupt is enabled.
Bit 1 – TXC Transmit Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete
interrupt.
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Value
0
1
Description
Transmit Complete interrupt is disabled.
Transmit Complete interrupt is enabled.
Bit 0 – DRE Data Register Empty Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty
interrupt.
Value
Description
0
Data Register Empty interrupt is disabled.
1
Data Register Empty interrupt is enabled.
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30.7.8
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
INTFLAG
0x18
0x00
-
7
ERROR
R/W
0
6
5
RXBRK
R/W
0
4
CTSIC
R/W
0
3
RXS
R/W
0
2
RXC
R
0
1
TXC
R/W
0
0
DRE
R
0
Bit 7 – ERROR Error
This flag is cleared by writing '1' to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS
register. Errors that will set this flag are COLL, ISF, BUFOVF, FERR, and PERR.
The Frame Error (FERR) and Parity Error (PERR) error interrupts will not wake the device from Standby mode.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 5 – RXBRK Receive Break
This flag is cleared by writing '1' to it.
This flag is set when auto-baud is enabled (CTRLA.FORM) and a break character is received.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 4 – CTSIC Clear to Send Input Change
This flag is cleared by writing a '1' to it.
This flag is set when a change is detected on the CTS pin.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 3 – RXS Receive Start
This flag is cleared by writing '1' to it.
This flag is set when a start condition is detected on the RxD line and start-of-frame detection is enabled
(CTRLB.SFDE is '1').
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Receive Start interrupt flag.
Bit 2 – RXC Receive Complete
This flag is cleared by reading the Data register (DATA) or by disabling the receiver.
This flag is set when there are unread data in DATA.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
Bit 1 – TXC Transmit Complete
This flag is cleared by writing '1' to it or by writing new data to DATA.
This flag is set when the entire frame in the transmit shift register has been shifted out and there are no new data in
DATA.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 0 – DRE Data Register Empty
This flag is cleared by writing new data to DATA.
This flag is set when DATA is empty and ready to be written.
Writing '0' to this bit has no effect.
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SERCOM Synchronous and Asynchronous Receiver ...
Writing '1' to this bit has no effect.
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30.7.9
Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x1A
0x0000
-
15
14
13
12
11
10
9
8
7
6
TXE
R/W
0
5
COLL
R/W
0
4
ISF
R/W
0
3
CTS
R
0
2
BUFOVF
R/W
0
1
FERR
R/W
0
0
PERR
R/W
0
Access
Reset
Bit
Access
Reset
Bit 6 – TXE Transmitter Empty
When CTRLA.FORM is set to LIN host mode, this bit is set when any ongoing transmission is complete and TxDATA
is empty.
When CTRLA.FORM is not set to LIN host mode, this bit will always read back as zero.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Bit 5 – COLL Collision Detected
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set when collision detection is enabled (CTRLB.COLDEN) and a collision is detected.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Bit 4 – ISF Inconsistent Sync Field
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set when the frame format is set to auto-baud (CTRLA.FORM) and a sync field not equal to 0x55 is
received.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Bit 3 – CTS Clear to Send
This bit indicates the current level of the CTS pin when flow control is enabled (CTRLA.TXPO).
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
Bit 2 – BUFOVF Buffer Overflow
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set when a buffer overflow condition is detected. A buffer overflow occurs when the receive buffer is full,
there is a new character waiting in the receive shift register and a new start bit is detected.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Bit 1 – FERR Frame Error
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set if the received character had a frame error, i.e., when the first stop bit is zero.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
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SERCOM Synchronous and Asynchronous Receiver ...
Bit 0 – PERR Parity Error
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set if parity checking is enabled (CTRLA.FORM is 0x1, 0x5) and a parity error is detected.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
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30.7.10 Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x1C
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
CTRLB
R
0
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 2 – CTRLB CTRLB Synchronization Busy
Writing to the CTRLB register when the SERCOM is enabled requires synchronization. When writing to CTRLB the
SYNCBUSY.CTRLB bit will be set until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB is
asserted, an APB error will be generated.
Value
Description
0
CTRLB synchronization is not busy.
1
CTRLB synchronization is busy.
Bit 1 – ENABLE SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the
SYNCBUSY.ENABLE bit will be set until synchronization is complete.
Value
Description
0
Enable synchronization is not busy.
1
Enable synchronization is busy.
Bit 0 – SWRST Software Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will
be set until synchronization is complete.
Value
Description
0
SWRST synchronization is not busy.
1
SWRST synchronization is busy.
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30.7.11 Data
Name:
Offset:
Reset:
Property:
Bit
DATA
0x28
0x0000
-
15
14
13
12
7
6
5
4
11
10
9
8
DATA[8]
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 8:0 – DATA[8:0] Data
Reading these bits will return the contents of the Receive Data register. The register should be read only when the
Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set. The status
bits in STATUS should be read before reading the DATA value in order to get any corresponding error.
Writing these bits will write the Transmit Data register. This register should be written only when the Data Register
Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set.
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SERCOM Serial Peripheral Interface (SERCOM S...
31.
31.1
SERCOM Serial Peripheral Interface (SERCOM SPI)
Overview
The serial peripheral interface (SPI) is one of the available modes in the Serial Communication Interface (SERCOM).
The SPI uses the SERCOM transmitter and receiver configured as shown in 31.3 Block Diagram. Each side, host
and client, depicts a separate SPI containing a shift register, a transmit buffer and a two-level receive buffer. In
addition, the SPI host uses the SERCOM baud-rate generator, while the SPI client can use the SERCOM address
match logic. Labels in capital letters are synchronous to CLK_SERCOMx_APB and accessible by the CPU, while
labels in lowercase letters are synchronous to the SCK clock.
31.2
Features
SERCOM SPI includes the following features:
•
•
•
•
•
•
•
Full-duplex, four-wire interface (MISO, MOSI, SCK, SS)
One-level transmit buffer, two-level receive buffer
Supports all four SPI modes of operation
Single data direction operation allows alternate function on MISO or MOSI pin
Selectable LSB- or MSB-first data transfer
Can be used with DMA
Host operation:
– Serial clock speed, fSCK=1/tSCK(1)
– 8-bit clock generator
– Hardware controlled SS
Client Operation:
– Serial clock speed, fSCK=1/tSSCK(1)
– Optional 8-bit address match operation
– Operation in all sleep modes
– Wake on SS transition
•
1.
31.3
For tSCK and tSSCK values, refer to the SPI Mode Electrical Specifications.
Block Diagram
Figure 31-1. Full-Duplex SPI Host Client Interconnection
Host
BAUD
Client
Tx DATA
Tx DATA
ADDR/ADDRMASK
SCK
SS
baud rate generator
shift register
MISO
shift register
MOSI
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rx buffer
rx buffer
Rx DATA
Rx DATA
Datasheet
==
Address Match
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SERCOM Serial Peripheral Interface (SERCOM S...
31.4
Signal Description
Table 31-1. SERCOM SPI Signals
Signal Name
Type
Description
PAD[3:0]
Digital I/O
General SERCOM pins
One signal can be mapped to one of several pins. For further information, refer to the Pinout Chapter.
31.5
Peripheral Dependencies
Refer to section 29.5 SERCOM Peripheral Dependencies.
31.6
Functional Description
31.6.1
Principle of Operation
The SPI is a high-speed synchronous data transfer interface. It allows high-speed communication between the device
and peripheral devices.
The SPI can operate as host or client. As host, the SPI initiates and controls all data transactions. The SPI is single
buffered for transmitting and double buffered for receiving.
When transmitting data, the Data register can be loaded with the next character to be transmitted during the current
transmission.
When receiving, the data is transferred to the two-level receive buffer, and the receiver is ready for a new character.
The SPI transaction format is shown in SPI Transaction Format. Each transaction can contain one or more
characters. The character size is configurable, and can be either 8 or 9 bits.
Figure 31-2. SPI Transaction Format
Transaction
Character
MOSI/MISO
Character 0
Character 1
Character 2
_
SS
The SPI host must pull the SPI select line (SS) of the desired client low to initiate a transaction if multiple clients are
connected to the bus. The SPI select line can be wired low if there is only one SPI client on the bus. The host and
client prepare data to send via their respective Shift registers, and the host generates the serial clock on the SCK
line.
Data is always shifted from host to client on the Host Output Client Input line (MOSI); data is shifted from client to
host on the Host Input Client Output line (MISO).
Each time character is shifted out from the host, a character will be shifted out from the client simultaneously. To
signal the end of a transaction, the host will pull the SS line high.
31.6.2
Basic Operation
31.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the SPI is disabled
(CTRL.ENABLE=0):
•
•
Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST)
Control B register (CTRLB), except Receiver Enable (CTRLB.RXEN)
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•
•
Baud register (BAUD)
Address register (ADDR)
When the SPI is enabled or is being enabled (CTRLA.ENABLE=1), any writing to these registers will be discarded.
When the SPI is being disabled, writing to these registers will be completed after the disabling.
Enable-protection is denoted by the Enable-Protection property in the register description.
Initialize the SPI by following these steps:
1. Select SPI mode in host / client operation in the Operating Mode bit group in the CTRLA register
(CTRLA.MODE= 0x2 or 0x3 ).
2. Select transfer mode for the Clock Polarity bit and the Clock Phase bit in the CTRLA register (CTRLA.CPOL
and CTRLA.CPHA) if desired.
3. Select the Frame Format value in the CTRLA register (CTRLA.FORM).
4. Configure the Data In Pinout field in the Control A register (CTRLA.DIPO) for SERCOM pads of the receiver.
5. Configure the Data Out Pinout bit group in the Control A register (CTRLA.DOPO) for SERCOM pads of the
transmitter.
6. Select the Character Size value in the CTRLB register (CTRLB.CHSIZE).
7. Write the Data Order bit in the CTRLA register (CTRLA.DORD) for data direction.
8. If the SPI is used in host mode:
8.1.
Select the desired baud rate by writing to the Baud register (BAUD).
8.2.
If Hardware SS control is required, write '1' to the Host SPI Select Enable bit in CTRLB register
(CTRLB.MSSEN).
9. Enable the receiver by writing the Receiver Enable bit in the CTRLB register (CTRLB.RXEN=1).
31.6.2.2 Enabling, Disabling, and Resetting
This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by
writing '0' to it.
Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral
to their initial states, except the DBGCTRL register, only when CRTLA.ENABLE is '1'.
Refer to the CTRLA register description for details.
31.6.2.3 Clock Generation
In SPI host operation (CTRLA.MODE=0x3), the serial clock (SCK) is generated internally by the SERCOM baud-rate
generator.
In SPI mode, the baud-rate generator is set to synchronous mode. The 8-bit Baud register (BAUD) value is used for
generating SCK and clocking the shift register. Refer to Clock Generation – Baud-Rate Generator for more details.
In SPI client operation (CTRLA.MODE is 0x2), the clock is provided by an external host on the SCK pin. This clock is
used to directly clock the SPI shift register.
31.6.2.4 Data Register
The SPI Transmit Data register (TxDATA) and SPI Receive Data register (RxDATA) share the same I/O address,
referred to as the SPI Data register (DATA). Writing DATA register will update the Transmit Data register. Reading the
DATA register will return the contents of the Receive Data register.
31.6.2.5 SPI Transfer Modes
There are four combinations of SCK phase and polarity to transfer serial data. The SPI data transfer modes are
shown in SPI Transfer Modes (Table) and SPI Transfer Modes (Figure).
SCK phase is configured by the Clock Phase bit in the CTRLA register (CTRLA.CPHA). SCK polarity is programmed
by the Clock Polarity bit in the CTRLA register (CTRLA.CPOL). Data bits are shifted out and latched in on opposite
edges of the SCK signal. This ensures sufficient time for the data signals to stabilize.
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Table 31-2. SPI Transfer Modes
Mode
CPOL
CPHA
Leading Edge
Trailing Edge
0
0
0
Rising, sample
Falling, setup
1
0
1
Rising, setup
Falling, sample
2
1
0
Falling, sample
Rising, setup
3
1
1
Falling, setup
Rising, sample
Note:
Leading edge is the first clock edge in a clock cycle.
Trailing edge is the second clock edge in a clock cycle.
Figure 31-3. SPI Transfer Modes
Mode 0
Mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) MSB
LSB first (DORD = 1) LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
Mode 1
Mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
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MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Datasheet
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
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31.6.2.6 Transferring Data
31.6.2.6.1 Host
In host mode (CTRLA.MODE=0x3), when Host SPI Select Enable (CTRLB.MSSEN) is ‘1’, hardware will control the
SS line.
When Host SPI Select Enable (CTRLB.MSSEN) is '0', the SS line must be configured as an output. SS can be
assigned to any general purpose I/O pin. When the SPI is ready for a data transaction, software must pull the SS line
low.
When writing a character to the Data register (DATA), the character will be transferred to the shift register. Once the
content of TxDATA has been transferred to the shift register, the Data Register Empty flag in the Interrupt Flag Status
and Clear register (INTFLAG.DRE) will be set. And a new character can be written to DATA.
Each time one character is shifted out from the host, another character will be shifted in from the client
simultaneously. If the receiver is enabled (CTRLA.RXEN=1), the contents of the shift register will be transferred
to the two-level receive buffer. The transfer takes place in the same clock cycle as the last data bit is shifted in. Then
the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set. The
received data can be retrieved by reading DATA.
When the last character has been transmitted and there is no valid data in DATA, the Transmit Complete Interrupt
flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set. When the transaction is finished,
the host must pull the SS line high to notify the client. If Host SPI Select Enable (CTRLB.MSSEN) is set to '0', the
software must pull the SS line high.
31.6.2.6.2 Client
In client mode (CTRLA.MODE=0x2), the SPI interface will remain inactive with the MISO line tri-stated as long as the
SS pin is pulled high. Software may update the contents of DATA at any time as long as the Data Register Empty flag
in the Interrupt Status and Clear register (INTFLAG.DRE) is set.
When SS is pulled low and SCK is running, the client will sample and shift out data according to the transaction mode
set. When the content of TxDATA has been loaded into the shift register, INTFLAG.DRE will be set, and new data can
be written to DATA.
Similar to the host, the client will receive one character for each character transmitted. A character will be transferred
into the two-level receive buffer within the same clock cycle its last data bit is received. The received character can
be retrieved from DATA when the Receive Complete interrupt flag (INTFLAG.RXC) is set.
When the host pulls the SS line high, the transaction is done and the Transmit Complete Interrupt flag in the Interrupt
Flag Status and Clear register (INTFLAG.TXC) will be set.
After DATA is written it takes up to three SCK clock cycles until the content of DATA is ready to be loaded into the
shift register on the next character boundary. As a consequence, the first character transferred in a SPI transaction
will not be the content of DATA. This can be avoided by using the preloading feature. Refer to Preloading of the Client
Shift Register.
When transmitting several characters in one SPI transaction, the data has to be written into DATA register with
at least three SCK clock cycles left in the current character transmission. If this criteria is not met, the previously
received character will be transmitted.
Once the DATA register is empty, it takes three CLK_SERCOM_APB cycles for INTFLAG.DRE to be set.
31.6.2.7 Receiver Error Bit
The SPI receiver has one error bit: the Buffer Overflow bit (BUFOVF), which can be read from the Status register
(STATUS). Once an error happens, the bit will stay set until it is cleared by writing '1' to it. The bit is also automatically
cleared when the receiver is disabled.
There are two methods for buffer overflow notification, selected by the immediate buffer overflow notification bit in the
Control A register (CTRLA.IBON):
If CTRLA.IBON=1, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the
receive FIFO by reading RxDATA until the receiver complete interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG.RXC) goes low.
If CTRLA.IBON=0, the buffer overflow condition travels with data through the receive FIFO. After the received data is
read, STATUS.BUFOVF and INTFLAG.ERROR will be set along with INTFLAG.RXC, and RxDATA will be zero.
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31.6.3
Additional Features
31.6.3.1 Address Recognition
When the SPI is configured for client operation (CTRLA.MODE=0x2) with address recognition (CTRLA.FORM is
0x2), the SERCOM address recognition logic is enabled: the first character in a transaction is checked for an address
match.
If there is a match, the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.RXC) is set, the MISO output is enabled, and the transaction is processed. If the device is in sleep
mode, an address match can wake up the device in order to process the transaction.
If there is no match, the complete transaction is ignored.
If a 9-bit frame format is selected, only the lower 8 bits of the shift register are checked against the Address register
(ADDR).
Preload must be disabled (CTRLB.PLOADEN=0) in order to use this mode.
31.6.3.2 Preloading of the Client Shift Register
When starting a transaction, the client will first transmit the contents of the shift register before loading new data from
DATA. The first character sent can be either the reset value of the shift register (if this is the first transmission since
the last reset) or the last character in the previous transmission.
Preloading can be used to preload data into the shift register while SS is high: this eliminates sending a dummy
character when starting a transaction. If the shift register is not preloaded, the current contents of the shift register will
be shifted out.
Only one data character will be preloaded into the shift register while the synchronized SS signal is high. If the next
character is written to DATA before SS is pulled low, the second character will be stored in DATA until transfer begins.
For proper preloading, sufficient time must elapse between SS going low and the first SCK sampling edge, as in
Timing Using Preloading. See also 43. Electrical Characteristics 85℃ for timing details.
Preloading is enabled by writing '1' to the Client Data Preload Enable bit in the CTRLB register (CTRLB.PLOADEN).
The Preload function (CTRLB.PLOADEN) must not be used when the Host cannot maintain the SS in a low state
until transmission is complete.
Figure 31-4. Timing Using Preloading
Required SS-to-SCK time
using PRELOADEN
SS
SS synchronized
to system domain
SCK
Synchronization
to system domain
MISO to SCK
setup time
31.6.3.3 Host with Several Clients
Host with multiple clients in parallel is only available when Host SPI Select Enable (CTRLB.MSSEN) is set to zero
and hardware SS control is disabled. If the bus consists of several SPI clients, a SPI host can use general purpose
I/O pins to control the SS line to each of the clients on the bus, as shown in the following figure. In this configuration,
the single selected SPI client will drive the tri-state MISO line.
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Figure 31-5. Multiple Clients in Parallel
shift register
MOSI
MOSI
MISO
MISO
SCK
SCK
SS
SS[0]
shift register
SPI Client 0
SPI Host
MOSI
MISO
SCK
SS
SS[n-1]
shift register
SPI Client n-1
Another configuration is multiple clients in series, as in the following figure. In this configuration, all n attached clients
are connected in series. A common SS line is provided to all clients, enabling them simultaneously. The host must
shift n characters for a complete transaction. Depending on the Host SPI Select Enable bit (CTRLB.MSSEN), the SS
line can be controlled either by hardware or user software and normal GPIO.
Figure 31-6. Multiple Clients in Series
shift register
SPI Host
MOSI
MISO
SCK
SS
MOSI
MISO
SCK
SS
shift register
MOSI
MISO
SCK
SS
shift register
SPI Client 0
SPI Client n-1
31.6.3.4 Loop-Back Mode
For Loop-Back mode, configure the Data In Pinout (CTRLA.DIPO) and Data Out Pinout (CTRLA.DOPO) to use
the same data pins for transmit and receive. The loop-back is through the pad, hence the signal is also available
externally.
31.6.3.5 Hardware Controlled SS
In host mode, a single SS chip select can be controlled by hardware by writing the Host SPI Select Enable
(CTRLB.MSSEN) bit to '1'. In this mode, the SS pin is driven low for a minimum of one baud cycle before
transmission begins, and stays low for a minimum of one baud cycle after transmission completes. If back-to-back
frames are transmitted, the SS pin will always be driven high for a minimum of one baud cycle between frames.
In Hardware Controlled SS, the time T is between one and two baud cycles depending on the SPI transfer mode.
Figure 31-7. Hardware Controlled SS
T
T
T
T
T
SS
SCK
T = 1 to 2 baud cycles
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When CTRLB.MSSEN=0, the SS pin(s) is/are controlled by user software and normal GPIO.
31.6.3.6 SPI Select Low Detection
In client mode, the SPI can wake the CPU when the SPI select (SS) goes low. When the SPI Select Low Detect is
enabled (CTRLB.SSDE=1), a high-to-low transition will set the SPI Select Low interrupt flag (INTFLAG.SSL) and the
device will wake up if applicable.
31.6.4
DMA, Interrupts, and Events
Table 31-3. Module Request for SERCOM SPI
Condition
Request
DMA
Interrupt
Event
Data Register Empty (DRE)
Yes
(request cleared when data is written)
Yes
NA
Receive Complete (RXC)
Yes
(request cleared when data is read)
Yes
Transmit Complete (TXC)
NA
Yes
SPI Select low (SSL)
NA
Yes
Error (ERROR)
NA
Yes
31.6.4.1 DMA Operation
The SPI generates the following DMA requests:
•
•
Data received (RX): The request is set when data is available in the receive FIFO. The request is cleared when
DATA is read.
Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when
DATA is written.
31.6.4.2 Interrupts
The SPI has the following interrupt sources. These are asynchronous interrupts, and can wake-up the device from
any Sleep mode:
•
•
•
•
•
Data Register Empty (DRE)
Receive Complete (RXC)
Transmit Complete (TXC)
SPI Select Low (SSL)
Error (ERROR)
Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG) will be set when the Interrupt condition is met. Each interrupt can be individually enabled by writing
'1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing '1' to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). As both INTENSET and INTENCLR always
reflect the same value, the status of interrupt enablement can be read from either register.
An interrupt request is generated when the Interrupt flag is set and if the corresponding interrupt is enabled. The
interrupt request remains active until either the Interrupt flag is cleared, the interrupt is disabled, or the SPI is reset.
For details on clearing Interrupt flags, refer to the INTFLAG register description.
The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for
interrupt requests. Refer to Nested Vector Interrupt Controller for details.
When the Data Register Empty (DRE) interrupt is enabled, it is necessary to write the DATA register before entering
standby mode.
31.6.5
Sleep Mode Operation
The behavior in sleep mode is depending on the host/client configuration and the Run In Standby bit in the Control A
register (CTRLA.RUNSTDBY):
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•
•
•
•
31.6.6
Host operation, CTRLA.RUNSTDBY=1: The peripheral clock GCLK_SERCOM_CORE will continue to run in idle
sleep mode and in standby sleep mode. Any interrupt can wake up the device.
Host operation, CTRLA.RUNSTDBY=0: GLK_SERCOMx_CORE will be disabled after the ongoing transaction is
finished. Any interrupt can wake up the device.
Client operation, CTRLA.RUNSTDBY=1: The Receive Complete interrupt can wake up the device.
Client operation, CTRLA.RUNSTDBY=0: All reception will be dropped, including the ongoing transaction.
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
•
•
•
Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Receiver Enable bit in the CTRLB register (CTRLB.RXEN)
Note: CTRLB.RXEN is write-synchronized somewhat differently. See the 31.7.2 CTRLB register for details.
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
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31.7
Register Summary
Offset
Name
0x00
CTRLA
0x04
7
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
RUNSTDBY
CTRLB
0x08
...
0x0B
0x0C
0x0D
...
0x13
0x14
0x15
0x16
0x17
0x18
0x19
INTENCLR
Reserved
INTENSET
Reserved
INTFLAG
Reserved
0x1A
STATUS
6
DORD
PLOADEN
AMODE[1:0]
5
4
3
2
1
MODE[2:0]
DIPO[1:0]
CPOL
CPHA
0
ENABLE
SWRST
IBON
DOPO[1:0]
FORM[3:0]
CHSIZE[2:0]
SSDE
RXEN
MSSEN
Reserved
BAUD
7:0
BAUD[7:0]
Reserved
0x1C
SYNCBUSY
0x20
...
0x23
Reserved
0x24
ADDR
0x28
DATA
0x2A
...
0x2F
0x30
Bit Pos.
7:0
ERROR
SSL
RXC
TXC
DRE
7:0
ERROR
SSL
RXC
TXC
DRE
7:0
ERROR
SSL
RXC
TXC
DRE
ENABLE
SWRST
7:0
15:8
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
BUFOVF
CTRLB
ADDR[7:0]
ADDRMASK[7:0]
DATA[7:0]
DATA[8]
Reserved
DBGCTRL
7:0
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31.7.1
Control A
Name:
Offset:
Reset:
Property:
Bit
CTRLA
0x00
0x00000000
PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits
31
Access
Reset
Bit
23
30
DORD
R/W
0
29
CPOL
R/W
0
22
21
28
CPHA
R/W
0
27
R/W
0
20
19
26
25
24
R/W
0
R/W
0
R/W
0
18
17
FORM[3:0]
DIPO[1:0]
Access
Reset
Bit
16
DOPO[1:0]
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
IBON
R/W
0
7
RUNSTDBY
R/W
0
6
5
4
3
MODE[2:0]
R/W
0
2
1
ENABLE
R/W
0
0
SWRST
R/W
0
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
Bit 30 – DORD Data Order
This bit selects the data order when a character is shifted out from the shift register.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
MSB is transferred first.
LSB is transferred first.
Bit 29 – CPOL Clock Polarity
In combination with the Clock Phase bit (CPHA), this bit determines the SPI transfer mode.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
SCK is low when idle. The leading edge of a clock cycle is a rising edge, while the trailing edge is a
falling edge.
SCK is high when idle. The leading edge of a clock cycle is a falling edge, while the trailing edge is a
rising edge.
Bit 28 – CPHA Clock Phase
In combination with the Clock Polarity bit (CPOL), this bit determines the SPI transfer mode.
Note: This bit is enable-protected. This bit is not synchronized.
Mode
CPOL
CPHA
Leading Edge
Trailing Edge
0x0
0x1
0x2
0x3
0
0
1
1
0
1
0
1
Rising, sample
Rising, change
Falling, sample
Falling, change
Falling, change
Falling, sample
Rising, change
Rising, sample
Value
0
Description
The data is sampled on a leading SCK edge and changed on a trailing SCK edge.
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Value
1
Description
The data is sampled on a trailing SCK edge and changed on a leading SCK edge.
Bits 27:24 – FORM[3:0] Frame Format
This bit field selects the various frame formats supported by the SPI in client mode. When the 'SPI frame with
address' format is selected, the first byte received is checked against the ADDR register.
Note: This bit field is enable-protected. This bit field is not synchronized.
FORM[3:0]
Name
Description
0x0
0x1
0x2
0x3-0xF
SPI_FRAME
SPI_FRAME_WITH_ADDR
-
SPI frame
Reserved
SPI frame with address
Reserved
Bits 21:20 – DIPO[1:0] Data In Pinout
These bits define the data in (DI) pad configurations.
In host operation, DI is MISO.
In client operation, DI is MOSI.
Note: This bit field is enable-protected. This bit field is not synchronized.
DIPO[1:0]
Name
Description
0x0
0x1
0x2
0x3
PAD[0]
PAD[1]
PAD[2]
PAD[3]
SERCOM PAD[0] is used as data input
SERCOM PAD[1] is used as data input
SERCOM PAD[2] is used as data input
SERCOM PAD[3] is used as data input
Bits 17:16 – DOPO[1:0] Data Out Pinout
This bit defines the available pad configurations for data out (DO), the serial clock (SCK) and the SPI select (SS). In
client operation, the SPI select line (SS) is controlled by DOPO. In host operation, the SPI select line (SS) is either
controlled by DOPO when CTRLB.MSSEN = 1, or by a GPIO driven by the application when CTRLB.MSSEN = 0.
In host operation, DO is MOSI.
In client operation, DO is MISO.
Note: This bit field is enable-protected. This bit field is not synchronized.
DOPO DO
SCK
Client SS Host SS (MSSEN =1)
0x0
PAD[0] PAD[1] PAD[2]
0x1
PAD[2] PAD[3] PAD[1]
0x2
PAD[3] PAD[1] PAD[2]
0x3
PAD[0] PAD[3] PAD[1]
PAD[2] when CTRLB.MSSEN = 1, else any
GPIO configured by the application
PAD[1] when CTRLB.MSSEN = 1, else any
GPIO configured by the application
PAD[2] when CTRLB.MSSEN = 1, else any
GPIO configured by the application
PAD[1] when CTRLB.MSSEN = 1, else any
GPIO configured by the application
Host SS (MSSEN = 0)
Any GPIO configured by the
application
Any GPIO configured by the
application
Any GPIO configured by the
application
Any GPIO configured by the
application
Bit 8 – IBON Immediate Buffer Overflow Notification
This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is set when a buffer overflow occurs.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
STATUS.BUFOVF is set when it occurs in the data stream.
STATUS.BUFOVF is set immediately upon buffer overflow.
Bit 7 – RUNSTDBY Run In Standby
This bit defines the functionality in standby sleep mode.
Note: This bit is enable-protected. This bit is not synchronized.
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RUNSTDBY
Client
Host
0x0
Disabled. All reception is dropped, including
the ongoing transaction.
Ongoing transaction continues, wake on
Receive Complete interrupt.
Generic clock is disabled when ongoing transaction
is finished. All interrupts can wake up the device.
Generic clock is enabled while in sleep modes. All
interrupts can wake up the device.
0x1
Bits 4:2 – MODE[2:0] Operating Mode
These bits must be written to 0x2 or 0x3 to select the SPI serial communication interface of the SERCOM.
0x2: SPI client operation
0x3: SPI host operation
Note: This bit field is enable-protected. This bit field is not synchronized.
Bit 1 – ENABLE Enable
Notes:
1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
2. This bit is not enable-protected.
Value
0
1
Description
The peripheral is disabled or being disabled.
The peripheral is enabled or being enabled.
Bit 0 – SWRST Software Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will
be disabled.
Writing ''1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register
will return the reset value of the register.
Notes:
1. This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST
synchronization is complete.
2. This bit is not enable-protected.
Value
0
1
Description
There is no reset operation ongoing.
The reset operation is ongoing.
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31.7.2
Control B
Name:
Offset:
Reset:
Property:
Bit
CTRLB
0x04
0x00000000
PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RXEN
R/W
0
16
13
MSSEN
R/W
0
12
11
10
9
SSDE
R/W
0
8
5
4
3
2
1
CHSIZE[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
15
14
AMODE[1:0]
R/W
R/W
0
0
Access
Reset
Bit
7
6
PLOADEN
R/W
0
Access
Reset
R/W
0
R/W
0
Bit 17 – RXEN Receiver Enable
Writing '0' to this bit will disable the SPI receiver immediately. The receive buffer will be flushed, data from ongoing
receptions will be lost and STATUS.BUFOVF will be cleared.
Writing '1' to CTRLB.RXEN when the SPI is disabled will set CTRLB.RXEN immediately. When the SPI is enabled,
CTRLB.RXEN will be cleared, SYNCBUSY.CTRLB will be set and remain set until the receiver is enabled. When the
receiver is enabled CTRLB.RXEN will read back as '1'.
Writing '1' to CTRLB.RXEN when the SPI is enabled will set SYNCBUSY.CTRLB, which will remain set until the
receiver is enabled, and CTRLB.RXEN will read back as '1'.
This bit is not enable-protected.
Value
Description
0
The receiver is disabled or being enabled.
1
The receiver is enabled or it will be enabled when SPI is enabled.
Bits 15:14 – AMODE[1:0] Address Mode
These bits set the client addressing mode when the frame format (CTRLA.FORM) with address is used. They are
unused in host mode.
Note: This bit field is enable-protected. This bit field is not synchronized.
AMODE[1:0] Name
0x0
0x1
0x2
0x3
Description
MASK
ADDRMASK is used as a mask to the ADDR register
2ADDRS The client responds to the two unique addresses in ADDR and ADDRMASK
RANGE The client responds to the range of addresses between and including ADDR and
ADDRMASK. ADDR is the upper limit
Reserved
Bit 13 – MSSEN Host SPI Select Enable
This bit enables hardware SPI select (SS) control.
Note: This bit is enable-protected. This bit is not synchronized.
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Value
0
1
Description
Hardware SS control is disabled.
Hardware SS control is enabled.
Bit 9 – SSDE SPI Select Low Detect Enable
This bit enables wake up when the SPI select (SS) pin transitions from high to low.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
SS low detector is disabled.
SS low detector is enabled.
Bit 6 – PLOADEN Client Data Preload Enable
Setting this bit will enable preloading of the client shift register when there is no transfer in progress. If the SS line is
high when DATA is written, it will be transferred immediately to the shift register.
The Preload function should not be used if the Host cannot maintain the SS low until transmission is complete.
Note: This bit is enable-protected. This bit is not synchronized.
Bits 2:0 – CHSIZE[2:0] Character Size
Note: This bit field is enable-protected. This bit field is not synchronized.
CHSIZE[2:0]
Name
Description
0x0
0x1
0x2-0x7
8BIT
9BIT
-
8 bits
9 bits
Reserved
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31.7.3
Baud Rate
Name:
Offset:
Reset:
Property:
Bit
BAUD
0x0C
0x00
PAC Write-Protection, Enable-Protected
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BAUD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – BAUD[7:0] Baud Register
These bits control the clock generation, as described in the SERCOM Clock Generation – Baud-Rate Generator.
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31.7.4
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x14
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will
also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
Access
Reset
7
ERROR
R/W
0
6
5
4
3
SSL
R/W
0
2
RXC
R/W
0
1
TXC
R/W
0
0
DRE
R/W
0
Bit 7 – ERROR Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 3 – SSL SPI Select Low Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the SPI Select Low Interrupt Enable bit, which disables the SPI Select Low interrupt.
Value
Description
0
SPI Select Low interrupt is disabled.
1
SPI Select Low interrupt is enabled.
Bit 2 – RXC Receive Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete
interrupt.
Value
Description
0
Receive Complete interrupt is disabled.
1
Receive Complete interrupt is enabled.
Bit 1 – TXC Transmit Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Transmit Complete Interrupt Enable bit, which disable the Transmit Complete
interrupt.
Value
Description
0
Transmit Complete interrupt is disabled.
1
Transmit Complete interrupt is enabled.
Bit 0 – DRE Data Register Empty Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty
interrupt.
Value
Description
0
Data Register Empty interrupt is disabled.
1
Data Register Empty interrupt is enabled.
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31.7.5
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x16
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will
also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
Access
Reset
7
ERROR
R/W
0
6
5
4
3
SSL
R/W
0
2
RXC
R/W
0
1
TXC
R/W
0
0
DRE
R/W
0
Bit 7 – ERROR Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 3 – SSL SPI Select Low Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the SPI Select Low Interrupt Enable bit, which enables the SPI Select Low interrupt.
Value
Description
0
SPI Select Low interrupt is disabled.
1
SPI Select Low interrupt is enabled.
Bit 2 – RXC Receive Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete
interrupt.
Value
Description
0
Receive Complete interrupt is disabled.
1
Receive Complete interrupt is enabled.
Bit 1 – TXC Transmit Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete
interrupt.
Value
Description
0
Transmit Complete interrupt is disabled.
1
Transmit Complete interrupt is enabled.
Bit 0 – DRE Data Register Empty Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty
interrupt.
Value
Description
0
Data Register Empty interrupt is disabled.
1
Data Register Empty interrupt is enabled.
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31.7.6
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
INTFLAG
0x18
0x00
-
7
ERROR
R/W
0
6
5
4
3
SSL
R/W
0
2
RXC
R
0
1
TXC
R/W
0
0
DRE
R
0
Bit 7 – ERROR Error
This flag is cleared by writing '1' to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS
register. The BUFOVF error will set this interrupt flag.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 3 – SSL SPI Select Low
This flag is cleared by writing '1' to it.
This bit is set when a high to low transition is detected on the SS pin in client mode and SPI Select Low Detect
(CTRLB.SSDE) is enabled.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 2 – RXC Receive Complete
This flag is cleared by reading the Data (DATA) register or by disabling the receiver.
This flag is set when there are unread data in the receive buffer. If address matching is enabled, the first data
received in a transaction will be an address.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
Bit 1 – TXC Transmit Complete
This flag is cleared by writing '1' to it or by writing new data to DATA.
In host mode, this flag is set when the data have been shifted out and there are no new data in DATA.
In client mode, this flag is set when the SS pin is pulled high. If address matching is enabled, this flag is only set if the
transaction was initiated with an address match.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 0 – DRE Data Register Empty
This flag is cleared by writing new data to DATA.
This flag is set when DATA is empty and ready for new data to transmit.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
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SERCOM Serial Peripheral Interface (SERCOM S...
31.7.7
Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x1A
0x0000
–
15
14
13
12
11
10
9
8
7
6
5
4
3
2
BUFOVF
R/W
0
1
0
Access
Reset
Bit
Access
Reset
Bit 2 – BUFOVF Buffer Overflow
Reading this bit before reading DATA will indicate the error status of the next character to be read.
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set when a buffer overflow condition is detected. See also CTRLA.IBON for overflow handling.
When set, the corresponding RxDATA will be zero.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Value
Description
0
No Buffer Overflow has occurred.
1
A Buffer Overflow has occurred.
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SERCOM Serial Peripheral Interface (SERCOM S...
31.7.8
Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x1C
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
CTRLB
R
0
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 2 – CTRLB CTRLB Synchronization Busy
Writing to the CTRLB when the SERCOM is enabled requires synchronization. Ongoing synchronization is indicated
by SYNCBUSY.CTRLB=1 until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB=1, an APB
error will be generated.
Value
Description
0
CTRLB synchronization is not busy.
1
CTRLB synchronization is busy.
Bit 1 – ENABLE SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. Ongoing synchronization is
indicated by SYNCBUSY.ENABLE=1 until synchronization is complete.
Value
Description
0
Enable synchronization is not busy.
1
Enable synchronization is busy.
Bit 0 – SWRST Software Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. Ongoing synchronization is indicated by
SYNCBUSY.SWRST=1 until synchronization is complete.
Value
Description
0
SWRST synchronization is not busy.
1
SWRST synchronization is busy.
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SERCOM Serial Peripheral Interface (SERCOM S...
31.7.9
Address
Name:
Offset:
Reset:
Property:
Bit
ADDR
0x24
0x00000000
PAC Write-Protection, Enable-Protected
31
30
29
28
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
12
7
6
5
4
27
26
25
24
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
20
19
ADDRMASK[7:0]
R/W
R/W
0
0
Access
Reset
Bit
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 23:16 – ADDRMASK[7:0] Address Mask
These bits hold the address mask when the transaction format with address is used (CTRLA.FORM,
CTRLB.AMODE).
Bits 7:0 – ADDR[7:0] Address
These bits hold the address when the transaction format with address is used (CTRLA.FORM, CTRLB.AMODE).
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SERCOM Serial Peripheral Interface (SERCOM S...
31.7.10 Data
Name:
Offset:
Reset:
Property:
Bit
DATA
0x28
0x0000
–
15
14
13
12
7
6
5
4
11
10
9
8
DATA[8]
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 8:0 – DATA[8:0] Data
Reading these bits will return the contents of the receive data buffer. The register should be read only when the
Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set.
Writing these bits will write the transmit data buffer. This register should be written only when the Data Register
Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set.
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31.7.11 Debug Control
Name:
Offset:
Reset:
Property:
Bit
DBGCTRL
0x30
0x00
PAC Write-Protection
7
6
5
4
3
Access
Reset
2
1
0
DBGSTOP
R/W
0
Bit 0 – DBGSTOP Debug Stop Mode
This bit controls the functionality when the CPU is halted by an external debugger.
This bit will be reset after a software system reset.
Value
Description
0
The baud-rate generator continues normal operation when the CPU is halted by an external debugger.
1
The baud-rate generator is halted when the CPU is halted by an external debugger.
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PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.1
Overview
The inter-integrated circuit (I2C) interface is one of the available modes in the Serial Communication Interface
(SERCOM)..
The I2C interface uses the SERCOM transmitter and receiver configured as shown in Figure 32-1. Labels in capital
letters are registers accessible by the CPU, while lowercase labels are internal to the SERCOM.
A SERCOM instance can be configured to be either an I2C host or an I2C client. Both host and client have an
interface containing a shift register, a transmit buffer and a receive buffer. In addition, the I2C host uses the SERCOM
baud-rate generator, while the I2C client uses the SERCOM address match logic.
32.2
Features
SERCOM I2C includes the following features:
•
•
•
•
•
•
•
•
•
Host or client operation
Can be used with DMA
Philips I2C compatible
SMBus™ compatible
PMBus compatible
Support of 100 kHz and 400 kHz, 1 MHz and 3.4 MHz I2C mode
4-Wire operation supported
Physical interface includes:
– Slew-rate limited outputs
– Filtered inputs
Client operation:
– Operation in all sleep modes
– Wake-up on address match
– 7-bit Address match in hardware for:
• Unique address and/or 7-bit general call address
• Address range
• Two unique addresses can be used with DMA
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SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.3
Block Diagram
Figure 32-1. I2C Single-Host Single-Client Interconnection
Host
BAUD
TxDATA
TxDATA
0
baud rate generator
Client
SCL
SCL hold low
0
SCL hold low
shift register
shift register
0
SDA
0
RxDATA
32.4
ADDR/ADDRMASK
RxDATA
==
Signal Description
Signal Name
Type
Description
PAD[0]
Digital I/O
SDA
PAD[1]
Digital I/O
SCL
PAD[2]
Digital I/O
SDA_OUT (4-wire operation)
PAD[3]
Digital I/O
SCL_OUT (4-wire operation)
One signal can be mapped on several pins.
All SERCOM I2C pins support the Fast Mode frequency. The High Speed frequency is only supported by the following
pins:
Table 32-1. SERCOM Pins Supporting I2C High Speed Frequency
Package
Pins Supporting I2C
32-pin
PA08, PA09, PA16, PA17, PA22, PA23
48-pin
PA08, PA09, PA12, PA13, PA16, PA17, PA22, PA23
Refer to the Pinout chapter for more information.
32.5
Peripheral Dependencies
Refer to section 29.5 SERCOM Peripheral Dependencies.
32.6
Functional Description
32.6.1
Principle of Operation
The I2C interface uses two physical lines for communication:
• Serial Data Line (SDA) for data transfer
• Serial Clock Line (SCL) for the bus clock
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SERCOM Inter-Integrated Circuit (SERCOM I2C)
A transaction starts with the I2C host sending the start condition, followed by a 7-bit address and a direction bit (read
or write to/from the client).
The addressed I2C client will then acknowledge (ACK) the address, and data packet transactions can begin. Every
9-bit data packet consists of 8 data bits followed by a one-bit reply indicating whether the data was acknowledged or
not.
If a data packet is not acknowledged (NACK), whether by the I2C client or host, the I2C host takes action by either
terminating the transaction by sending the stop condition, or by sending a repeated start to transfer more data.
The following figure illustrates the possible transaction formats and explains the transaction symbols. These symbols
will be used in the following descriptions.
Figure 32-2. Transaction Diagram Symbols
Bus Driver
Special Bus Conditions
Host driving bus
S
START condition
Client driving bus
Sr
repeated START condition
Either Host or Client driving bus
P
STOP condition
Data Package Direction
R
Acknowledge
Host Read
'0'
'1'
W
Acknowledge (ACK)
A
A
Host Write
Not Acknowledge (NACK)
'1'
'0'
Figure 32-3. Basic I2C Transaction Diagram
SDA
SCL
6..0
S
ADDRESS
S
ADDRESS
7..0
R/W
R/W
ACK
A
DATA
DATA
7..0
ACK
A
DATA
ACK/NACK
DATA
A/A
P
P
Direction
Address Packet
Data Packet #0
Data Packet #1
Transaction
32.6.2
Basic Operation
32.6.2.1 Initialization
The following registers are enable-protected, meaning they can be written only when the I2C interface is disabled
(CTRLA.ENABLE is ‘0’):
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SERCOM Inter-Integrated Circuit (SERCOM I2C)
•
•
•
•
Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST) bits
Control B register (CTRLB), except Acknowledge Action (CTRLB.ACKACT) and Command (CTRLB.CMD) bits
Baud register (BAUD)
Address register (ADDR) in client operation.
When the I2C is enabled or is being enabled (CTRLA.ENABLE=1), writing to these registers will be discarded. If the
I2C is being disabled, writing to these registers will be completed after the disabling.
Enable-protection is denoted by the "Enable-Protection" property in the register description.
Before I2C is enabled it must be configured by the following these steps:
1. Select I2C Host or Client mode by writing 0x4 (Client mode) or 0x5 (Host mode) to the Operating Mode bits in
the CTRLA register (CTRLA.MODE).
2. If required, select the SDA Hold Time value in the CTRLA register (CTRLA.SDAHOLD).
3. If required, enable smart operation by setting the Smart Mode Enable bit in the CTRLB register
(CTRLB.SMEN).
4. If required, enable SCL low time-out by setting the SCL Low Time-Out bit in the Control A register
(CTRLA.LOWTOUTEN).
5. In Host mode:
5.1.
Select the inactive bus time-out in the Inactive Time-Out bit group in the CTRLA register
(CTRLA.INACTOUT).
5.2.
Write the Baud Rate register (BAUD) to generate the desired baud rate.
In Client mode:
5.1.
Configure the address match configuration by writing the Address Mode value in the CTRLB register
(CTRLB.AMODE).
5.2.
Set the Address and Address Mask value in the Address register (ADDR.ADDR and
ADDR.ADDRMASK) according to the address configuration.
32.6.2.2 Enabling, Disabling, and Resetting
This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by
writing '0' to it.
Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral
to their initial states, except the DBGCTRL register, only when CRTLA.ENABLE is '1'.
32.6.2.3 I2C Bus State Logic
The bus state logic includes several logic blocks that continuously monitor the activity on the I2C bus lines in
all sleep modes with running GCLK_SERCOM_x clocks. The start and stop detectors and the bit counter are
all essential in the process of determining the current bus state. The bus state is determined according to Bus
State Diagram. Software can get the current bus state by reading the Host Bus State bits in the Status register
(STATUS.BUSSTATE). The value of STATUS.BUSSTATE in the figure is shown in binary.
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SERCOM Inter-Integrated Circuit (SERCOM I2C)
Figure 32-4. Bus State Diagram
RESET
UNKNOWN
(0b00)
Timeout or Stop Condition
Start Condition
IDLE
(0b01)
Timeout or Stop Condition
BUSY
(0b11)
Write ADDR to generate
Start Condition
OWNER
(0b10)
Lost Arbitration
Repeated
Start Condition
Stop Condition
Write ADDR to generate
Repeated Start Condition
The bus state machine is active when the I2C host is enabled.
After the I2C host has been enabled, the bus state is UNKNOWN (0b00). From the UNKNOWN state, the bus will
transition to IDLE (0b01) by either:
• Forcing by writing 0b01 to STATUS.BUSSTATE
• A stop condition is detected on the bus
• If the inactive bus time-out is configured for SMBus compatibility (CTRLA.INACTOUT) and a time-out occurs.
Note: Once a known bus state is established, the bus state logic will not re-enter the UNKNOWN state.
When the bus is IDLE it is ready for a new transaction. If a start condition is issued on the bus by another I2C host
in a multi-host setup, the bus becomes BUSY (0b11). The bus will re-enter IDLE either when a stop condition is
detected, or when a time-out occurs (inactive bus time-out needs to be configured).
If a start condition is generated internally by writing the Address bit group in the Address register (ADDR.ADDR)
while IDLE, the OWNER state (0b10) is entered. If the complete transaction was performed without interference, i.e.,
arbitration was not lost, the I2C host can issue a stop condition, which will change the bus state back to IDLE.
However, if a packet collision is detected while in OWNER state, the arbitration is assumed lost and the bus state
becomes BUSY until a stop condition is detected. A repeated start condition will change the bus state only if
arbitration is lost while issuing a repeated start.
Note: Violating the protocol may cause the I2C to hang. If this happens it is possible to recover from this state by a
software reset (CTRLA.SWRST='1').
32.6.2.4 I2C Host Operation
The I2C host is byte-oriented and interrupt based. The number of interrupts generated is kept at a minimum by
automatic handling of most incidents. The software driver complexity and code size are reduced by auto-triggering
of operations, and smart mode, which can be enabled by the Smart Mode Enable bit in the Control B register
(CTRLB.SMEN).
The I2C host has two interrupt strategies.
When SCL Clock Stretch Mode (CTRLA.SCLSM) is '0', SCL is stretched before or after the Acknowledge bit . In this
mode the I2C host operates according to Host Behavioral Diagram (SCLSM=0). The circles labeled "Mn" (M1, M2..)
indicate the nodes the bus logic can jump to, based on software or hardware interaction.
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SERCOM Inter-Integrated Circuit (SERCOM I2C)
This diagram is used as reference for the description of the I2C host operation throughout the document.
Figure 32-5. I2C Host Behavioral Diagram (SCLSM=0)
Host Bus INTERRUPT + SCL HOLD
APPLICATION
M1
M2
BUSY
P
M3
IDLE
S
M4
ADDRESS
Wait for
IDLE
SW
R/W BUSY
SW
R/W A
SW
P
SW
Sr
W
A
M1
BUSY
M2
IDLE
M3
BUSY
DATA
SW
A/A
Client Bus INTERRUPT + SCL HOLD
SW
Software interaction
SW
A
BUSY
The host provides data on the bus
A/A
P
Addressed client provides data on the bus
A/A Sr
IDLE
M4
M2
M3
A/A
R
A
DATA
In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit, as in Host Behavioral Diagram
(SCLSM=1). This strategy can be used when it is not necessary to check DATA before acknowledging.
Note: I2C High-speed (Hs) mode requires CTRLA.SCLSM=1.
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Figure 32-6. I2C Host Behavioral Diagram (SCLSM=1)
Host Bus INTERRUPT + SCL HOLD
APPLICATION
M1
M2
BUSY
P
M3
IDLE
S
M4
ADDRESS
Wait for
IDLE
SW
R/W BUSY
SW
R/W A
SW
P
SW
Sr
W
A
M1
BUSY
M2
IDLE
M3
BUSY
DATA
SW
A/A
Client Bus INTERRUPT + SCL HOLD
SW
Software interaction
SW
The host provides data on the bus
BUSY
P
Addressed client provides data on the bus
Sr
R
A
IDLE
M4
M2
M3
DATA
A/A
32.6.2.4.1 Host Clock Generation
The SERCOM peripheral supports several I2C bidirectional modes:
• Standard mode (Sm) up to 100 kHz
• Fast mode (Fm) up to 400 kHz
• Fast mode Plus (Fm+) up to 1 MHz
• High-speed mode (Hs) up to 3.4 MHz
The Host clock configuration for Sm, Fm, and Fm+ are described in Clock Generation (Standard-Mode, Fast-Mode,
and Fast-Mode Plus). For Hs, refer to Host Clock Generation (High-Speed Mode).
Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus)
In I2C Sm, Fm, and Fm+ mode, the Host clock (SCL) frequency is determined as described in this section:
The low (TLOW) and high (THIGH) times are determined by the Baud Rate register (BAUD), while the rise (TRISE)
and fall (TFALL) times are determined by the bus topology. Because of the wired-AND logic of the bus, TFALL will be
considered as part of TLOW. Likewise, TRISE will be in a state between TLOW and THIGH until a high state has been
detected.
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SERCOM Inter-Integrated Circuit (SERCOM I2C)
Figure 32-7. SCL Timing
TRISE
P
S
Sr
TLOW
SCL
THIGH
TFALL
TBUF
SDA
TSU;STO
THD;STA
TSU;STA
The following parameters are timed using the SCL low time period TLOW. This comes from the Host Baud Rate Low
bit group in the Baud Rate register (BAUD.BAUDLOW). When BAUD.BAUDLOW=0, or the Host Baud Rate bit group
in the Baud Rate register (BAUD.BAUD) determines it.
• TLOW – Low period of SCL clock
• TSU;STO – Set-up time for stop condition
• TBUF – Bus free time between stop and start conditions
• THD;STA – Hold time (repeated) start condition
• TSU;STA – Set-up time for repeated start condition
• THIGH is timed using the SCL high time count from BAUD.BAUD
• TRISE is determined by the bus impedance; for internal pull-ups. Refer to 43. Electrical Characteristics 85℃.
• TFALL is determined by the open-drain current limit and bus impedance; can typically be regarded as zero. Refer
to 43. Electrical Characteristics 85℃ for details.
The SCL frequency is given by:
fSCL =
1
TLOW + THIGH + TRISE
fSCL =
fGCLK
10 + 2BAUD + fGCLK ⋅ TRISE
fSCL =
fGCLK
10 + BAUD + BAUDLOW + fGCLK ⋅ TRISE
When BAUD.BAUDLOW is zero, the BAUD.BAUD value is used to time both SCL high and SCL low. In this case the
following formula will give the SCL frequency:
When BAUD.BAUDLOW is non-zero, the following formula determines the SCL frequency:
The following formulas can determine the SCL TLOW and THIGH times:
TLOW = BAUDLOW + 5
fGCLK
THIGH = BAUD + 5
fGCLK
Note: The I2C standard Fm+ (Fast-mode plus) requires a nominal high to low SCL ratio of 1:2, and BAUD should be
set accordingly. At a minimum, BAUD.BAUD and/or BAUD.BAUDLOW must be non-zero.
Startup Timing The minimum time between SDA transition and SCL rising edge is 6 APB cycles when the DATA
register is written in smart mode. If a greater startup time is required due to long rise times, the time between DATA
write and IF clear must be controlled by software.
Note: When timing is controlled by user, the Smart Mode cannot be enabled.
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SERCOM Inter-Integrated Circuit (SERCOM I2C)
Host Clock Generation (High-Speed Mode)
For I2C Hs transfers, there is no SCL synchronization. Instead, the SCL frequency is determined by
the GCLK_SERCOMx_CORE frequency (fGCLK) and the High-Speed Baud setting in the Baud register
(BAUD.HSBAUD). When BAUD.HSBAUDLOW=0, the HSBAUD value will determine both SCL high and SCL low. In
this case the following formula determines the SCL frequency.
fSCL =
fGCLK
2 + 2 ⋅ HS BAUD
fSCL =
fGCLK
2 + HS BAUD + HSBAUDLOW
When HSBAUDLOW is non-zero, the following formula determines the SCL frequency.
Note: The I2C standard Hs (High-speed) requires a nominal high to low SCL ratio of 1:2, and HSBAUD should be
set accordingly. At a minimum, BAUD.HSBAUD and/or BAUD.HSBAUDLOW must be non-zero.
32.6.2.4.2 Transmitting Address Packets
The I2C host starts a bus transaction by writing the I2C client address to ADDR.ADDR and the direction bit, as
described in 32.6.1 Principle of Operation. If the bus is busy, the I2C host will wait until the bus becomes idle before
continuing the operation. When the bus is idle, the I2C host will issue a start condition on the bus. The I2C host
will then transmit an address packet using the address written to ADDR.ADDR. After the address packet has been
transmitted by the I2C host, one of four cases will arise according to arbitration and transfer direction.
Case 1: Arbitration lost or bus error during address packet transmission
If arbitration was lost during transmission of the address packet, the Host on Bus bit in the Interrupt Flag Status and
Clear register (INTFLAG.MB) and the Arbitration Lost bit in the Status register (STATUS.ARBLOST) are both set.
Serial data output to SDA is disabled, and the SCL is released, which disables clock stretching. In effect the I2C
host is no longer allowed to execute any operation on the bus until the bus is idle again. A bus error will behave
similarly to the arbitration lost condition. In this case, the MB interrupt flag and Host Bus Error bit in the Status
register (STATUS.BUSERR) are both set in addition to STATUS.ARBLOST.
The Host Received Not Acknowledge bit in the Status register (STATUS.RXNACK) will always contain the last
successfully received acknowledge or not acknowledge indication.
In this case, software will typically inform the application code of the condition and then clear the interrupt flag before
exiting the interrupt routine. No other flags have to be cleared at this moment, because all flags will be cleared
automatically the next time the ADDR.ADDR register is written.
Case 2: Address packet transmit complete – No ACK received
If there is no I2C client device responding to the address packet, then the INTFLAG.MB interrupt flag and
STATUS.RXNACK will be set. The clock hold is active at this point, preventing further activity on the bus.
The missing ACK response can indicate that the I2C client is busy with other tasks or sleeping. Therefore, it is not
able to respond. In this event, the next step can be either issuing a stop condition (recommended) or resending the
address packet by a repeated start condition. When using SMBus logic, the client must ACK the address. If there is
no response, it means that the client is not available on the bus.
Case 3: Address packet transmit complete – Write packet, Host on Bus set
If the I2C host receives an acknowledge response from the I2C client, INTFLAG.MB will be set and STATUS.RXNACK
will be cleared. The clock hold is active at this point, preventing further activity on the bus.
In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the
I2C operation to continue:
• Initiate a data transmit operation by writing the data byte to be transmitted into DATA.DATA.
• Transmit a new address packet by writing ADDR.ADDR. A repeated start condition will automatically be inserted
before the address packet.
• Issue a stop condition, consequently terminating the transaction.
Case 4: Address packet transmit complete – Read packet, Client on Bus set
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SERCOM Inter-Integrated Circuit (SERCOM I2C)
If the I2C host receives an ACK from the I2C client, the I2C host proceeds to receive the next byte of data from the I2C
client. When the first data byte is received, the Client on Bus bit in the Interrupt Flag register (INTFLAG.SB) will be
set and STATUS.RXNACK will be cleared. The clock hold is active at this point, preventing further activity on the bus.
In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the
I2C operation to continue:
• Let the I2C host continue to read data by acknowledging the data received. ACK can be sent by software, or
automatically in smart mode.
• Transmit a new address packet.
• Terminate the transaction by issuing a stop condition.
Note: An ACK or NACK will be automatically transmitted if smart mode is enabled. The Acknowledge Action bit in
the Control B register (CTRLB.ACKACT) determines whether ACK or NACK should be sent.
32.6.2.4.3 Transmitting Data Packets
When an address packet with direction Host Write (see Figure 32-3) was transmitted successfully , INTFLAG.MB will
be set. The I2C host will start transmitting data via the I2C bus by writing to DATA.DATA, and monitor continuously for
packet collisions. I
If a collision is detected, the I2C host will lose arbitration and STATUS.ARBLOST will be set. If the transmit
was successful, the I2C host will receive an ACK bit from the I2C client, and STATUS.RXNACK will be cleared.
INTFLAG.MB will be set in both cases, regardless of arbitration outcome.
It is recommended to read STATUS.ARBLOST and handle the arbitration lost condition in the beginning of the
I2C Host on Bus interrupt. This can be done as there is no difference between handling address and data packet
arbitration.
STATUS.RXNACK must be checked for each data packet transmitted before the next data packet transmission can
commence. The I2C host is not allowed to continue transmitting data packets if a NACK is received from the I2C
client.
32.6.2.4.4 Receiving Data Packets (SCLSM=0)
When INTFLAG.SB is set, the I2C host will already have received one data packet. The I2C host must respond
by sending either an ACK or NACK. Sending a NACK may be unsuccessful when arbitration is lost during the
transmission. In this case, a lost arbitration will prevent setting INTFLAG.SB. Instead, INTFLAG.MB will indicate a
change in arbitration. Handling of lost arbitration is the same as for data bit transmission.
32.6.2.4.5 Receiving Data Packets (SCLSM=1)
When INTFLAG.SB is set, the I2C host will already have received one data packet and transmitted an ACK or NACK,
depending on CTRLB.ACKACT. At this point, CTRLB.ACKACT must be set to the correct value for the next ACK bit,
and the transaction can continue by reading DATA and issuing a command if not in the smart mode.
32.6.2.4.6 High-Speed Mode
High-speed transfers are a multi-step process, see High Speed Transfer.
First, a host code (0b00001nnn, where 'nnn' is a unique host code) is transmitted in Full-speed mode, followed by a
NACK since no client should acknowledge. Arbitration is performed only during the Full-speed Host Code phase. The
host code is transmitted by writing the host code to the address register (ADDR.ADDR) and writing the high-speed bit
(ADDR.HS) to '0'.
After the host code and NACK have been transmitted, the host write interrupt will be asserted. In the meanwhile,
the client address can be written to the ADDR.ADDR register together with ADDR.HS=1. Now in High-speed mode,
the host will generate a repeated start, followed by the client address with RW-direction. The bus will remain in
High-speed mode until a stop is generated. If a repeated start is desired, the ADDR.HS bit must again be written to
'1', along with the new address ADDR.ADDR to be transmitted.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
Figure 32-8. High Speed Transfer
F/S-mode
S
Host Code
Hs-mode
A
ADDRESS
Sr
F/S-mode
R/W A
DATA
A/A
P
Hs-mode continues
N Data Packets
Sr
ADDRESS
Transmitting in High-speed mode requires the I2C host to be configured in High-speed mode (CTRLA.SPEED=0x2)
and the SCL clock stretch mode (CTRLA.SCLSM) bit set to '1'.
32.6.2.4.7 10-Bit Addressing
When 10-bit addressing is enabled by the Ten Bit Addressing Enable bit in the Address register
(ADDR.TENBITEN=1) and the Address bit field ADDR.ADDR is written, the two address bytes will be transmitted,
see 10-bit Address Transmission for a Read Transaction. The addressed client acknowledges the two address bytes,
and the transaction continues. Regardless of whether the transaction is a read or write, the host must start by
sending the 10-bit address with the direction bit (ADDR.ADDR[0]) being zero.
If the host receives a NACK after the first byte, the write interrupt flag will be raised and the STATUS.RXNACK bit
will be set. If the first byte is acknowledged by one or more clients, then the host will proceed to transmit the second
address byte and the host will first see the write interrupt flag after the second byte is transmitted. If the transaction
direction is read-from-client, the 10-bit address transmission must be followed by a repeated start and the first 7 bits
of the address with the read/write bit equal to '1'.
Figure 32-9. 10-bit Address Transmission for a Read Transaction
MB INTERRUPT
1
S 11110 addr[9:8]
W
A
addr[7:0]
A
S
W
Sr 11110 addr[9:8]
R
A
This implies the following procedure for a 10-bit read operation:
1. Write the 10-bit address to ADDR.ADDR[10:1]. ADDR.TENBITEN must be '1', the direction bit
(ADDR.ADDR[0]) must be '0' (can be written simultaneously with ADDR).
2. Once the Host on Bus interrupt is asserted, Write ADDR[7:0] register to '11110 address[9:8] 1'.
ADDR.TENBITEN must be cleared (can be written simultaneously with ADDR).
3. Proceed to transmit data.
32.6.2.5 I2C Client Operation
The I2C client is byte-oriented and interrupt-based. The number of interrupts generated is kept at a minimum by
automatic handling of most events. The software driver complexity and code size are reduced by auto-triggering of
operations, and a special smart mode, which can be enabled by the Smart Mode Enable bit in the Control B register
(CTRLB.SMEN).
The I2C client has two interrupt strategies.
When SCL Stretch Mode bit (CTRLA.SCLSM) is '0', SCL is stretched before or after the acknowledge bit. In this
mode, the I2C client operates according to I2C Client Behavioral Diagram (SCLSM=0). The circles labeled "Sn" (S1,
S2..) indicate the nodes the bus logic can jump to, based on software or hardware interaction.
This diagram is used as reference for the description of the I2C client operation throughout the document.
© 2021 Microchip Technology Inc.
and its subsidiaries
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PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
Figure 32-10. I2C Client Behavioral Diagram (SCLSM=0)
AMATCH INTERRUPT
S1
S3
S2
S
DRDY INTERRUPT
A
ADDRESS
S
W
R
S1
S2
Sr
S3
S
W
A
A
P
S1
P
S2
Sr
S3
DATA
A/A
PREC INTERRUPT
S
W
W
Interrupt on STOP
Condition Enabled
S
W
A
S
W
DATA
A/A
S
W
Software interaction
The host provides data on the bus.
Addressed client provides data on the bus.
In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit is sent as shown in Client
Behavioral Diagram (SCLSM=1). This strategy can be used when it is not necessary to check DATA before
acknowledging. For host reads, an address and data interrupt will be issued simultaneously after the address
acknowledge. However, for host writes, the first data interrupt will be seen after the first data byte has been received
by the client and the acknowledge bit has been sent to the host.
Note: For I2C High-speed mode (Hs), SCLSM=1 is required.
Figure 32-11. I2C Client Behavioral Diagram (SCLSM=1)
AMATCH INTERRUPT (+ DRDY INTERRUPT in Host Read mode)
S1
S3
S2
S
ADDRESS
R
A/A
DRDY INTERRUPT
S
W
P
S2
Sr
S3
DATA
P
S2
Sr
S3
A/A
PREC INTERRUPT
W
Interrupt on STOP
Condition Enabled
S
W
A/A
S
W
DATA
A/A
S
W
S
W
Software interaction
The host provides data on the bus.
Addressed client provides data on the bus.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.6.2.5.1 Receiving Address Packets (SCLSM=0)
When CTRLA.SCLSM=0, the I2C client stretches the SCL line according to Figure 32-10. When the I2C client is
properly configured, it will wait for a start condition.
When a start condition is detected, the successive address packet will be received and checked by the address
match logic. If the received address is not a match, the packet will be rejected, and the I2C client will wait for
a new start condition. If the received address is a match, the Address Match bit in the Interrupt Flag register
(INTFLAG.AMATCH) will be set.
SCL will be stretched until the I2C client clears INTFLAG.AMATCH. As the I2C client holds the clock by forcing SCL
low, the software has unlimited time to respond.
The direction of a transaction is determined by reading the Read / Write Direction bit in the Status register
(STATUS.DIR). This bit will be updated only when a valid address packet is received.
If the Transmit Collision bit in the Status register (STATUS.COLL) is set, this indicates that the last packet addressed
to the I2C client had a packet collision. A collision causes the SDA and SCL lines to be released without any
notification to software. Therefore, the next AMATCH interrupt is the first indication of the previous packet’s collision.
Collisions are intended to follow the SMBus Address Resolution Protocol (ARP).
After the address packet has been received from the I2C host, one of two cases will arise based on transfer direction.
Case 1: Address packet accepted – Read flag set
The STATUS.DIR bit is ‘1’, indicating an I2C host read operation. The SCL line is forced low, stretching the bus clock.
If an ACK is sent, I2C client hardware will set the Data Ready bit in the Interrupt Flag register (INTFLAG.DRDY),
indicating data are needed for transmit. If a NACK is sent, the I2C client will wait for a new start condition and address
match.
Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The I2C client
Command bit field in the Control B register (CTRLB.CMD) can be written to '0x3' for both read and write operations
as the command execution is dependent on the STATUS.DIR bit. Writing ‘1’ to INTFLAG.AMATCH will also cause an
ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit.
Case 2: Address packet accepted – Write flag set
The STATUS.DIR bit is cleared, indicating an I2C host write operation. The SCL line is forced low, stretching the bus
clock. If an ACK is sent, the I2C client will wait for data to be received. Data, repeated start or stop can be received.
If a NACK is sent, the I2C client will wait for a new start condition and address match. Typically, software will
immediately acknowledge the address packet by sending an ACK/NACK. The I2C client command CTRLB.CMD = 3
can be used for both read and write operation as the command execution is dependent on STATUS.DIR.
Writing ‘1’ to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit.
32.6.2.5.2 Receiving Address Packets (SCLSM=1)
When SCLSM=1, the I2C client will stretch the SCL line only after an ACK, see Client Behavioral Diagram
(SCLSM=1). When the I2C client is properly configured, it will wait for a start condition to be detected.
When a start condition is detected, the successive address packet will be received and checked by the address
match logic.
If the received address is not a match, the packet will be rejected and the I2C client will wait for a new start condition.
If the address matches, the acknowledge action as configured by the Acknowledge Action bit Control B register
(CTRLB.ACKACT) will be sent and the Address Match bit in the Interrupt Flag register (INTFLAG.AMATCH) is set.
SCL will be stretched until the I2C client clears INTFLAG.AMATCH. As the I2C client holds the clock by forcing SCL
low, the software is given unlimited time to respond to the address.
The direction of a transaction is determined by reading the Read/Write Direction bit in the Status register
(STATUS.DIR). This bit will be updated only when a valid address packet is received.
If the Transmit Collision bit in the Status register (STATUS.COLL) is set, the last packet addressed to the I2C client
had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to software.
The next AMATCH interrupt is, therefore, the first indication of the previous packet’s collision. Collisions are intended
to follow the SMBus Address Resolution Protocol (ARP).
After the address packet has been received from the I2C host, INTFLAG.AMATCH be set to ‘1’ to clear it.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.6.2.5.3 Receiving and Transmitting Data Packets
After the I2C client has received an address packet, it will respond according to the direction either by waiting for the
data packet to be received or by starting to send a data packet by writing to DATA.DATA. When a data packet is
received or sent, INTFLAG.DRDY will be set. After receiving data, the I2C client will send an acknowledge according
to CTRLB.ACKACT.
Case 1: Data received
INTFLAG.DRDY is set, and SCL is held low, pending for SW interaction.
Case 2: Data sent
When a byte transmission is successfully completed, the INTFLAG.DRDY interrupt flag is set. If NACK is received,
indicated by STATUS.RXNACK=1, the I2C client must expect a stop or a repeated start to be received. The I2C client
must release the data line to allow the I2C host to generate a stop or repeated start. Upon detecting a stop condition,
the Stop Received bit in the Interrupt Flag register (INTFLAG.PREC) will be set and the I2C client will return to IDLE
state.
32.6.2.5.4 High-Speed Mode
When the I2C client is configured in High-speed mode (Hs, CTRLA.SPEED=0x2) and CTRLA.SCLSM=1, switching
between Full-speed and High-speed modes is automatic. When the client recognizes a START followed by a host
code transmission and a NACK, it automatically switches to High-speed mode and sets the High-speed status bit
(STATUS.HS). The client will then remain in High-speed mode until a STOP is received.
32.6.2.5.5 10-Bit Addressing
10-bit Addressing is not available in Client mode.
32.6.2.5.6 PMBus Group Command
When the PMBus Group Command bit in the CTRLB register is set (CTRLB.GCMD=1) and 7-bit addressing is used,
INTFLAG.PREC will be set if the client has been addressed since the last STOP condition. When CTRLB.GCMD=0,
a STOP condition without address match will not be set INTFLAG.PREC.
The group command protocol is used to send commands to more than one device. The commands are sent in one
continuous transmission with a single STOP condition at the end. When the STOP condition is detected by the clients
addressed during the group command, they all begin executing the command they received.
PMBus Group Command Example shows an example where this client, bearing ADDRESS 1, is addressed after a
repeated START condition. There can be multiple clients addressed before and after this client. Eventually, at the end
of the group command, a single STOP is generated by the host. At this point a STOP interrupt is asserted.
Figure 32-12. PMBus Group Command Example
Command/Data
S
ADDRESS 0
W
A
n Bytes
A
AMATCH INTERRUPT
DRDY INTERRUPT
Command/Data
Sr
ADDRESS 1
(this client)
S
W
W
A
ADDRESS 2
© 2021 Microchip Technology Inc.
and its subsidiaries
W
A
n Bytes
Datasheet
A
PREC INTERRUPT
Command/Data
Sr
S
W
n Bytes
A
P
S
W
DS60001638D-page 498
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.6.3
Additional Features
32.6.3.1 SMBus
The I2C includes three hardware SCL low time-outs which allow a time-out to occur for SMBus SCL low time-out,
host extend time-out, and client extend time-out. This allows for SMBus functionality These time-outs are driven by
the GCLK_SERCOM_SLOW clock. The GCLK_SERCOM_SLOW clock is used to accurately time the time-out and
must be configured to use a 32.768 kHz oscillator. The I2C interface also allows for a SMBus compatible SDA hold
time.
•
•
•
TTIMEOUT: SCL low time of 25..35ms – Measured for a single SCL low period. It is enabled by
CTRLA.LOWTOUTEN.
TLOW:SEXT: Cumulative clock low extend time of 25 ms – Measured as the cumulative SCL low extend time by a
client device in a single message from the initial START to the STOP. It is enabled by CTRLA.SEXTTOEN.
TLOW:MEXT: Cumulative clock low extend time of 10 ms – Measured as the cumulative SCL low extend time
by the host device within a single byte from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is enabled by
CTRLA.MEXTTOEN.
32.6.3.2 Smart Mode
The I2C interface has a smart mode that simplifies application code and minimizes the user interaction needed to
adhere to the I2C protocol. The smart mode accomplishes this by automatically issuing an ACK or NACK (based on
the content of CTRLB.ACKACT) as soon as DATA.DATA is read.
32.6.3.3 4-Wire Mode
Writing a '1' to the Pin Usage bit in the Control A register (CTRLA.PINOUT) will enable 4-wire mode operation. In this
mode, the internal I2C tri-state drivers are bypassed, and an external I2C compliant tri-state driver is needed when
connecting to an I2C bus.
Figure 32-13. I2C Pad Interface
SCL_OUT/
SDA_OUT
SCL_OUT/
SDA_OUT
pad
PINOUT
I2C
Driver
SCL/SDA
pad
SCL_IN/
SDA_IN
PINOUT
32.6.3.4 Quick Command
Setting the Quick Command Enable bit in the Control B register (CTRLB.QCEN) enables quick command. When
quick command is enabled, the corresponding interrupt flag (INTFLAG.SB or INTFLAG.MB) is set immediately after
the client acknowledges the address. At this point, the software can either issue a stop command or a repeated start
by writing CTRLB.CMD or ADDR.ADDR.
The use of the Quick Command mode (CTRLB.QCEN = 1) is only allowed if SCL Stretch Mode is CTRLA.SCLSM
=0. The Quick Command feature is not available in High-Speed mode.
32.6.4
DMA, Interrupts and Events
Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG) will be set when the interrupt condition is meet. Each interrupt can be individually enabled by writing
‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing ‘1’ to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). As both INTENSET and INTENCLR always
reflect the same value, the status of interrupt enablement can be read from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request is active until the interrupt flag is cleared, the interrupt is disabled or the I2C is reset. See the
32.7.5 INTFLAG (Client) or 32.8.6 INTFLAG (Host) register for details on how to clear interrupt flags.
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PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
Table 32-2. Module Request for SERCOM I2C Client
Condition
Request
DMA
Data needed for transmit (TX) (Client transmit mode)
Yes
(request cleared when data is written)
Data received (RX) (Client receive mode)
Yes
(request cleared when data is read)
Interrupt Event
NA
Data Ready (DRDY)
Yes
Address Match (AMATCH)
Yes
Stop received (PREC)
Yes
Error (ERROR)
Yes
Table 32-3. Module Request for SERCOM I2C Host
Condition
Request
DMA
Data needed for transmit (TX) (Host transmit mode)
Yes
(request cleared when data is written)
Data needed for transmit (RX) (Host transmit mode)
Yes
(request cleared when data is read)
Interrupt Event
NA
Host on Bus (MB)
Yes
Stop received (SB)
Yes
Error (ERROR)
Yes
32.6.4.1 DMA Operation
Smart mode must be enabled for DMA operation in the Control B register by writing CTRLB.SMEN=1.
32.6.4.1.1 Client DMA
When using the I2C client with DMA, an address match will cause the address interrupt flag
(INTFLAG.ADDRMATCH) to be raised. After the interrupt has been serviced, data transfer will be performed through
DMA.
The I2C client generates the following requests:
•
•
Write data received (RX): The request is set when host write data is received. The request is cleared when
DATA is read.
Read data needed for transmit (TX): The request is set when data is needed for a host read operation. The
request is cleared when DATA is written.
When using the DMA with client mode, the client requires the transaction length of data that will be requested by the
Host so the DMA can be configured properly.
32.6.4.1.2 Host DMA
When using the I2C host with DMA, the ADDR register must be written with the desired address (ADDR.ADDR),
transaction length (ADDR.LEN), and transaction length enable (ADDR.LENEN). When ADDR.LENEN is written to 1
along with ADDR.ADDR, ADDR.LEN determines the number of data bytes in the transaction from 0 to 255. DMA is
then used to transfer ADDR.LEN bytes followed by an automatically generated NACK (for host reads) and a STOP.
If a NACK is received by the client for a host write transaction before ADDR.LEN bytes, a STOP will be automatically
generated and the length error (STATUS.LENERR) will be raised along with the INTFLAG.ERROR interrupt.
The I2C host generates the following requests:
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PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
•
•
Read data received (RX): The request is set when host read data is received. The request is cleared when
DATA is read.
Write data needed for transmit (TX): The request is set when data is needed for a host write operation. The
request is cleared when DATA is written.
32.6.4.2 Interrupts
The I2C client has the following interrupt sources. These are asynchronous interrupts. The DRDY, AMATCH, AND
PREC will wake the device from any sleep mode.
•
•
•
•
Error (ERROR)
Data Ready (DRDY)
Address Match (AMATCH)
Stop Received (PREC)
The I2C host has the following interrupt sources. These are asynchronous interrupts. The SB and MB interrupts can
wake the device from any sleep mode.
•
•
•
Error (ERROR)
Client on Bus (SB)
Host on Bus (MB)
Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG) will be set when the interrupt condition is meet. Each interrupt can be individually enabled by writing
‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing ‘1’ to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). As both INTENSET and INTENCLR always
reflect the same value, the status of interrupt enablement can be read from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request active until the interrupt flag is cleared, the interrupt is disabled or the I2C is reset. See the INTFLAG
register for details on how to clear interrupt flags.
The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for
interrupt requests. Refer to the 9.2 Nested Vector Interrupt Controller for details.
32.6.5
Sleep Mode Operation
I2C Host Operation
The generic clock (GCLK_SERCOMx_CORE) will continue to run in idle sleep mode. If the Run In Standby bit in the
Control A register (CTRLA.RUNSTDBY) is '1', the GLK_SERCOMx_CORE will also run in standby sleep mode. Any
interrupt can wake up the device.
If CTRLA.RUNSTDBY=0, the GLK_SERCOMx_CORE will be disabled after any ongoing transaction is finished. Any
interrupt can wake up the device.
I2C Client Operation
Writing CTRLA.RUNSTDBY=1 will allow the Address Match interrupt to wake up the device.
When CTRLA.RUNSTDBY=0, all receptions will be dropped.
32.6.6
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
•
•
•
•
•
Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Command bits in CTRLB register (CTRLB.CMD)
Write to Bus State bits in the Status register (STATUS.BUSSTATE)
Address bits in the Address register (ADDR.ADDR) when in host operation.
The following registers are synchronized when written:
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PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
•
Data (DATA) when in host operation
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
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PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.7
Register Summary - I2C Client
Offset
Name
0x00
CTRLA
0x04
Bit Pos.
7
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
RUNSTDBY
7:0
ERROR
DRDY
AMATCH
PREC
7:0
ERROR
DRDY
AMATCH
PREC
7:0
ERROR
DRDY
AMATCH
PREC
7:0
15:8
7:0
15:8
23:16
31:24
CLKHOLD
RXNACK
HS
COLL
SEXTTOUT
ENABLE
BUSERR
CTRLB
0x08
...
0x13
0x14
0x15
0x16
0x17
0x18
0x19
INTENCLR
Reserved
INTENSET
Reserved
INTFLAG
Reserved
0x1A
STATUS
6
5
4
3
2
MODE[2:0]
SEXTTOEN
SDAHOLD[1:0]
LOWTOUTEN
0
ENABLE
SWRST
PINOUT
SPEED[1:0]
SCLSM
AMODE[1:0]
1
AACKEN
ACKACT
GCMD
SMEN
CMD[1:0]
Reserved
0x1C
SYNCBUSY
0x20
...
0x23
Reserved
0x24
ADDR
0x28
DATA
7:0
15:8
23:16
31:24
7:0
15:8
© 2021 Microchip Technology Inc.
and its subsidiaries
LOWTOUT
SR
DIR
ADDR[6:0]
SWRST
GENCEN
ADDRMASK[6:0]
DATA[7:0]
Datasheet
DS60001638D-page 503
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.7.1
Control A
Name:
Offset:
Reset:
Property:
Bit
31
Access
Reset
Bit
Access
Reset
Bit
CTRLA
0x00
0x00000000
PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits
30
LOWTOUTEN
R/W
0
29
28
21
20
SDAHOLD[1:0]
R/W
R/W
0
0
27
SCLSM
R/W
0
26
19
25
24
SPEED[1:0]
R/W
0
R/W
0
18
17
16
PINOUT
R/W
0
23
SEXTTOEN
R/W
0
22
15
14
13
12
11
10
9
8
7
RUNSTDBY
R/W
0
6
5
4
3
MODE[2:0]
R/W
0
2
1
ENABLE
R/W
0
0
SWRST
R/W
0
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
Bit 30 – LOWTOUTEN SCL Low Time-Out
This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the client will release its clock hold, if
enabled, and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
Time-out disabled.
Time-out enabled.
Bit 27 – SCLSM SCL Clock Stretch Mode
This bit controls when SCL will be stretched for software interaction.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
SCL stretch according to Figure 32-10
SCL stretch only after ACK bit according to Figure 32-11
Bits 25:24 – SPEED[1:0] Transfer Speed
These bits define bus speed.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
Description
Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz
Fast-mode Plus (Fm+) up to 1 MHz
High-speed mode (Hs-mode) up to 3.4 MHz
Reserved
Bit 23 – SEXTTOEN Client SCL Low Extend Time-Out
This bit enables the client SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the
initial START to a STOP, the client will release its clock hold if enabled and reset the internal state machine. Any
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 504
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
interrupt flags set at the time of time-out will remain set. If the address was recognized, PREC will be set when a
STOP is received.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
Time-out disabled
Time-out enabled
Bits 21:20 – SDAHOLD[1:0] SDA Hold Time
These bits define the SDA hold time with respect to the negative edge of SCL.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
Name
DIS
75NS
450NS
600NS
Description
Disabled
50-100ns hold time
300-600ns hold time
400-800ns hold time
Bit 16 – PINOUT Pin Usage
This bit sets the pin usage to either two- or four-wire operation:
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
4-wire operation disabled
4-wire operation enabled
Bit 7 – RUNSTDBY Run in Standby
This bit defines the functionality in standby sleep mode.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
Disabled – All reception is dropped.
Wake on address match, if enabled.
Bits 4:2 – MODE[2:0] Operating Mode
These bits must be written to 0x04 to select the I2C client serial communication interface of the SERCOM.
Note: This bit field is enable-protected. This bit field is not synchronized.
Bit 1 – ENABLE Enable
Notes:
1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
2. This bit is not enable-protected.
Value
0
1
Description
The peripheral is disabled or being disabled.
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will
be disabled.
Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register
will return the reset value of the register.
Notes:
1. This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST
synchronization is complete.
2. This bit is not enable-protected.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 505
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
Value
0
1
Description
There is no reset operation ongoing.
The reset operation is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 506
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.7.2
Control B
Name:
Offset:
Reset:
Property:
Bit
CTRLB
0x04
0x00000000
PAC Write-Protection, Enable-Protected Bits
31
30
29
28
27
26
25
24
23
22
21
20
19
18
ACKACT
R/W
0
17
W
0
W
0
Access
Reset
Bit
Access
Reset
Bit
15
14
AMODE[1:0]
R/W
R/W
0
0
Access
Reset
Bit
7
6
16
CMD[1:0]
13
12
11
10
AACKEN
R/W
0
9
GCMD
R/W
0
8
SMEN
R/W
0
5
4
3
2
1
0
Access
Reset
Bit 18 – ACKACT Acknowledge Action
This bit defines the client's acknowledge behavior after an address or data byte is received from the host.
The acknowledge action is executed when a command is written to the CMD bits. If smart mode is enabled
(CTRLB.SMEN=1), the acknowledge action is performed when the DATA register is read.
Note: This bit is not enable-protected.
Value
0
1
Description
Send ACK
Send NACK
Bits 17:16 – CMD[1:0] Command
This bit field triggers the client operation as the below. The CMD bits are strobe bits, and always read as zero.
The operation is dependent on the client interrupt flags, INTFLAG.DRDY and INTFLAG.AMATCH, in addition to
STATUS.DIR.
All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared when a
command is given.
Note: This bit is not enable-protected.
Table 32-4. Command Description
CMD[1:0]
DIR
0x0
0x1
0x2
X
(No action)
X
(Reserved)
Used to complete a transaction in response to a data interrupt (DRDY)
0 (Host write) Execute acknowledge action succeeded by waiting for any start (S/Sr) condition
1 (Host read) Wait for any start (S/Sr) condition
© 2021 Microchip Technology Inc.
and its subsidiaries
Action
Datasheet
DS60001638D-page 507
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
...........continued
CMD[1:0]
DIR
Action
0x3
Used in response to an address interrupt (AMATCH)
0 (Host write) Execute acknowledge action succeeded by reception of next byte
1 (Host read) Execute acknowledge action succeeded by client data interrupt
Used in response to a data interrupt (DRDY)
0 (Host write) Execute acknowledge action succeeded by reception of next byte
1 (Host read) Execute a byte read operation followed by ACK/NACK reception
Bits 15:14 – AMODE[1:0] Address Mode
These bits set the addressing mode.
Note: This bit field is enable-protected.
Value
0x0
0x1
0x2
0x3
Name
MASK
Description
The client responds to the address written in ADDR.ADDR masked by the value in
ADDR.ADDRMASK.
See SERCOM – Serial Communication Interface for additional information.
2ADDRS The client responds to the two unique addresses in ADDR.ADDR and ADDR.ADDRMASK.
RANGE The client responds to the range of addresses between and including ADDR.ADDR and
ADDR.ADDRMASK. ADDR.ADDR is the upper limit.
Reserved.
Bit 10 – AACKEN Automatic Acknowledge Enable
This bit enables the address to be automatically acknowledged if there is an address match.
Note: This bit is enable-protected.
Value
0
1
Description
Automatic acknowledge is disabled.
Automatic acknowledge is enabled.
Bit 9 – GCMD PMBus Group Command
This bit enables PMBus group command support. When enabled, the Stop Received interrupt flag (INTFLAG.PREC)
will be set when a STOP condition is detected if the client has been addressed since the last STOP condition on the
bus.
Note: This bit is enable-protected.
Value
0
1
Description
Group command is disabled.
Group command is enabled.
Bit 8 – SMEN Smart Mode Enable
When smart mode is enabled, data is acknowledged automatically when DATA.DATA is read.
Note: This bit is enable-protected.
Value
0
1
Description
Smart mode is disabled.
Smart mode is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 508
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.7.3
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x14
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
Access
Reset
7
ERROR
R/W
0
6
5
4
3
2
DRDY
R/W
0
1
AMATCH
R/W
0
0
PREC
R/W
0
Bit 7 – ERROR Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 2 – DRDY Data Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Data Ready bit, which disables the Data Ready interrupt.
Value
Description
0
The Data Ready interrupt is disabled.
1
The Data Ready interrupt is enabled.
Bit 1 – AMATCH Address Match Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Address Match Interrupt Enable bit, which disables the Address Match interrupt.
Value
Description
0
The Address Match interrupt is disabled.
1
The Address Match interrupt is enabled.
Bit 0 – PREC Stop Received Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Stop Received Interrupt Enable bit, which disables the Stop Received interrupt.
Value
Description
0
The Stop Received interrupt is disabled.
1
The Stop Received interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 509
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.7.4
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x16
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
Access
Reset
7
ERROR
R/W
0
6
5
4
3
2
DRDY
R/W
0
1
AMATCH
R/W
0
0
PREC
R/W
0
Bit 7 – ERROR Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 2 – DRDY Data Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Data Ready bit, which enables the Data Ready interrupt.
Value
Description
0
The Data Ready interrupt is disabled.
1
The Data Ready interrupt is enabled.
Bit 1 – AMATCH Address Match Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Address Match Interrupt Enable bit, which enables the Address Match interrupt.
Value
Description
0
The Address Match interrupt is disabled.
1
The Address Match interrupt is enabled.
Bit 0 – PREC Stop Received Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Stop Received Interrupt Enable bit, which enables the Stop Received interrupt.
Value
Description
0
The Stop Received interrupt is disabled.
1
The Stop Received interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 510
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.7.5
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
INTFLAG
0x18
0x00
-
7
ERROR
R/W
0
6
5
4
3
2
DRDY
R/W
0
1
AMATCH
R/W
0
0
PREC
R/W
0
Bit 7 – ERROR Error
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS
register. The corresponding bits in STATUS are SEXTTOUT, LOWTOUT, COLL, and BUSERR.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 2 – DRDY Data Ready
This flag is set when a I2C client byte transmission is successfully completed.
The flag is cleared by hardware when either:
• Writing to the DATA register.
• Reading the DATA register with smart mode enabled.
• Writing a valid command to the CMD register.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Data Ready interrupt flag.
Bit 1 – AMATCH Address Match
This flag is set when the I2C client address match logic detects that a valid address has been received.
The flag is cleared by hardware when CTRL.CMD is written.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Address Match interrupt flag. When cleared, an ACK/NACK will be sent according to
CTRLB.ACKACT.
Bit 0 – PREC Stop Received
This flag is set when a stop condition is detected for a transaction being processed. A stop condition detected
between a bus host and another client will not set this flag, unless the PMBus Group Command is enabled in the
Control B register (CTRLB.GCMD=1).
This flag is cleared by hardware after a command is issued on the next address match.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Stop Received interrupt flag.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 511
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.7.6
Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x1A
0x0000
-
15
14
13
12
11
10
HS
R/W
0
9
SEXTTOUT
R/W
0
8
7
CLKHOLD
R/W
0
6
LOWTOUT
R/W
0
5
4
SR
R
0
3
DIR
R
0
2
RXNACK
R
0
1
COLL
R/W
0
0
BUSERR
R/W
0
Access
Reset
Bit
Access
Reset
Bit 10 – HS High-speed
This bit is set if the client detects a START followed by a Host Code transmission.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the status. However, this flag is automatically cleared when a STOP is received.
Bit 9 – SEXTTOUT Client SCL Low Extend Time-Out
This bit is set if a client SCL low extend time-out occurs.
This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD).
This bit is not cleared when INTFLAG.AMATCH is cleared. Write to '1' to clear SEXTTOUT status.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the status.
Value
Description
0
No SCL low extend time-out has occurred.
1
SCL low extend time-out has occurred.
Bit 7 – CLKHOLD Clock Hold
The client Clock Hold bit (STATUS.CLKHOLD) is set when the client is holding the SCL line low, stretching
the I2C clock. Software should consider this bit a read-only status flag that is set when INTFLAG.DRDY or
INTFLAG.AMATCH is set. Do not clear the STATUS.CLKHOLD bit to preserve the current clock hold state.
This bit is automatically cleared when the corresponding interrupt is also cleared.
Bit 6 – LOWTOUT SCL Low Time-out
This bit is set if an SCL low time-out occurs.
This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD).
This bit is not cleared when INTFLAG.AMATCH is cleared. Write to '1' to clear LOWTOUT status.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the status.
Value
Description
0
No SCL low time-out has occurred.
1
SCL low time-out has occurred.
Bit 4 – SR Repeated Start
When INTFLAG.AMATCH is raised due to an address match, SR indicates a repeated start or start condition.
This flag is only valid while the INTFLAG.AMATCH flag is one.
Value
Description
0
Start condition on last address match
1
Repeated start condition on last address match
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 512
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
Bit 3 – DIR Read / Write Direction
The Read/Write Direction (STATUS.DIR) bit stores the direction of the last address packet received from a host.
Value
Description
0
Host write operation is in progress.
1
Host read operation is in progress.
Bit 2 – RXNACK Received Not Acknowledge
This bit indicates whether the last data packet sent was acknowledged or not.
Value
Description
0
Host responded with ACK.
1
Host responded with NACK.
Bit 1 – COLL Transmit Collision
If set, the I2C client was not able to transmit a high data or NACK bit, the I2C client will immediately release the SDA
and SCL lines and wait for the next packet addressed to it.
This flag is intended for the SMBus address resolution protocol (ARP). A detected collision in non-ARP situations
indicates that there has been a protocol violation, and should be treated as a bus error.
Note that this status will not trigger any interrupt, and should be checked by software to verify that the data were sent
correctly. This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to
CTRLB.CMD). This bit is not cleared when INTFLAG.AMATCH is cleared. Write to '1' to clear COLL status.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the status.
Value
Description
0
No collision detected on last data byte sent.
1
Collision detected on last data byte sent.
Bit 0 – BUSERR Bus Error
The Bus Error bit (STATUS.BUSERR) indicates that an illegal bus condition has occurred on the bus, regardless of
bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start or stop is detected on
the I2C bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If a
time-out occurs during a frame, this is also considered a protocol violation, and will set STATUS.BUSERR.
This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to
CTRLB.CMD). This bit is not cleared when INTFLAG.AMATCH is cleared. Write to '1' to clear BUSERR status.
Writing a '1' to this bit will clear the status.
Writing a '0' to this bit has no effect.
Value
Description
0
No bus error detected.
1
Bus error detected.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 513
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.7.7
Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x1C
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – ENABLE SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the
SYNCBUSY.ENABLE bit will be set until synchronization is complete.
Value
Description
0
Enable synchronization is not busy.
1
Enable synchronization is busy.
Bit 0 – SWRST Software Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will
be set until synchronization is complete.
Value
Description
0
SWRST synchronization is not busy.
1
SWRST synchronization is busy.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 514
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.7.8
Address
Name:
Offset:
Reset:
Property:
Bit
ADDR
0x24
0x00000000
PAC Write-Protection, Enable-Protected
31
30
29
28
27
26
25
24
23
22
21
19
18
17
16
R/W
0
R/W
0
R/W
0
20
ADDRMASK[6:0]
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
3
2
1
R/W
0
R/W
0
R/W
0
4
ADDR[6:0]
R/W
0
R/W
0
R/W
0
R/W
0
0
GENCEN
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 23:17 – ADDRMASK[6:0] Address Mask
These bits act as a second address match register, an address mask register or the lower limit of an address range,
depending on the CTRLB.AMODE setting.
Bits 7:1 – ADDR[6:0] Address
These bits contain the I2C client address used by the client address match logic to determine if a host has addressed
the client.
When using 7-bit addressing, the client address is represented by ADDR[6:0].
When the address match logic detects a match, INTFLAG.AMATCH is set and STATUS.DIR is updated to indicate
whether it is a read or a write transaction.
Bit 0 – GENCEN General Call Address Enable
A general call address is an address consisting of all-zeroes, including the direction bit (host write).
Value
Description
0
General call address recognition is disabled.
1
General call address recognition is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 515
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.7.9
Data
Name:
Offset:
Reset:
Property:
Bit
DATA
0x28
0x0000
Write-Synchronized, Read-Synchronized
15
14
13
12
7
6
5
4
11
10
9
8
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DATA[7:0] Data
The client data register I/O location (DATA.DATA) provides access to the host transmit and receive data buffers.
Reading valid data or writing data to be transmitted can be successfully done only when SCL is held low by the client
(STATUS.CLKHOLD is set). An exception occurs when reading the last data byte after the stop condition has been
received.
Accessing DATA.DATA auto-triggers I2C bus operations. The operation performed depends on the state of
CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write).
Writing or reading DATA.DATA when not in smart mode does not require synchronization.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 516
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.8
Register Summary - I2C Host
Offset
Name
0x00
CTRLA
0x04
CTRLB
0x08
...
0x0B
Reserved
0x0C
7
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
RUNSTDBY
BAUD
0x10
...
0x13
0x14
0x15
0x16
0x17
0x18
0x19
INTENCLR
Reserved
INTENSET
Reserved
INTFLAG
Reserved
0x1A
STATUS
0x1C
SYNCBUSY
0x20
...
0x23
Reserved
SEXTTOEN
6
5
4
3
2
MODE[2:0]
MEXTTOEN
LOWTOUTEN
SDAHOLD[1:0]
INACTOUT[1:0]
0
ENABLE
SWRST
PINOUT
SPEED[1:0]
SCLSM
ACKACT
7:0
15:8
23:16
31:24
1
QCEN
SMEN
CMD[1:0]
BAUD[7:0]
BAUDLOW[7:0]
HSBAUD[7:0]
HSBAUDLOW[7:0]
Reserved
0x24
ADDR
0x28
DATA
0x2A
...
0x2F
0x30
Bit Pos.
7:0
ERROR
SB
MB
7:0
ERROR
SB
MB
7:0
ERROR
SB
MB
7:0
15:8
7:0
15:8
23:16
31:24
CLKHOLD
LOWTOUT
ARBLOST
SEXTTOUT
ENABLE
BUSERR
MEXTTOUT
SWRST
TENBITEN
HS
7:0
15:8
23:16
31:24
7:0
15:8
BUSSTATE[1:0]
RXNACK
LENERR
SYSOP
ADDR[7:0]
LENEN
ADDR[10:8]
LEN[7:0]
DATA[7:0]
Reserved
DBGCTRL
7:0
© 2021 Microchip Technology Inc.
and its subsidiaries
DBGSTOP
Datasheet
DS60001638D-page 517
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.8.1
Control A
Name:
Offset:
Reset:
Property:
Bit
31
30
LOWTOUTEN
R/W
0
29
28
INACTOUT[1:0]
R/W
R/W
0
0
27
SCLSM
R/W
0
26
23
SEXTTOEN
R/W
0
22
MEXTTOEN
R/W
0
21
20
SDAHOLD[1:0]
R/W
R/W
0
0
19
15
14
13
12
7
RUNSTDBY
R/W
0
6
5
4
Access
Reset
Bit
Access
Reset
Bit
CTRLA
0x00
0x00000000
PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits
25
24
SPEED[1:0]
R/W
0
R/W
0
18
17
16
PINOUT
R/W
0
11
10
9
8
3
MODE[2:0]
R/W
0
2
1
ENABLE
R/W
0
0
SWRST
R/W
0
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
Bit 30 – LOWTOUTEN SCL Low Time-Out
This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the host will release its clock hold, if
enabled, and complete the current transaction. A stop condition will automatically be transmitted.
INTFLAG.SB or INTFLAG.MB will be set as normal, but the clock hold will be released. The STATUS.LOWTOUT and
STATUS.BUSERR status bits will be set.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
Time-out disabled.
Time-out enabled.
Bits 29:28 – INACTOUT[1:0] Inactive Time-Out
If the inactive bus time-out is enabled and the bus is inactive for longer than the time-out setting, the bus state logic
will be set to idle. An inactive bus arise when either an I2C host or client is holding the SCL low.
Enabling this option is necessary for SMBus compatibility, but can also be used in a non-SMBus set-up.
Calculated time-out periods are based on a 100kHz baud rate.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0x0
0x1
0x2
0x3
Name
DIS
55US
105US
205US
Description
Disabled
5-6 SCL cycle time-out (50-60µs)
10-11 SCL cycle time-out (100-110µs)
20-21 SCL cycle time-out (200-210µs)
Bit 27 – SCLSM SCL Clock Stretch Mode
This bit controls when SCL will be stretched for software interaction.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
Description
SCL stretch according to Figure 32-5.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 518
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
Value
1
Description
SCL stretch only after ACK bit, Figure 32-6.
Bits 25:24 – SPEED[1:0] Transfer Speed
These bits define bus speed.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
Description
Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz
Fast-mode Plus (Fm+) up to 1 MHz
High-speed mode (Hs-mode) up to 3.4 MHz
Reserved
Bit 23 – SEXTTOEN Client SCL Low Extend Time-Out
This bit enables the client SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the
initial START to a STOP, the host will release its clock hold if enabled, and complete the current transaction. A STOP
will automatically be transmitted.
SB or MB will be set as normal, but CLKHOLD will be release. The MEXTTOUT and BUSERR status bits will be set.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
Time-out disabled
Time-out enabled
Bit 22 – MEXTTOEN Host SCL Low Extend Time-Out
This bit enables the host SCL low extend time-out. If SCL is cumulatively held low for greater than 10ms from
START-to-ACK, ACK-to-ACK, or ACK-to-STOP the host will release its clock hold if enabled, and complete the
current transaction. A STOP will automatically be transmitted.
SB or MB will be set as normal, but CLKHOLD will be released. The MEXTTOUT and BUSERR status bits will be set.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
Time-out disabled
Time-out enabled
Bits 21:20 – SDAHOLD[1:0] SDA Hold Time
These bits define the SDA hold time with respect to the negative edge of SCL.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
Name
DIS
75NS
450NS
600NS
Description
Disabled
50-100ns hold time
300-600ns hold time
400-800ns hold time
Bit 16 – PINOUT Pin Usage
This bit set the pin usage to either two- or four-wire operation:
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
4-wire operation disabled.
4-wire operation enabled.
Bit 7 – RUNSTDBY Run in Standby
This bit defines the functionality in standby sleep mode.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
GCLK_SERCOMx_CORE is disabled and the I2C host will not operate in standby sleep mode.
GCLK_SERCOMx_CORE is enabled in all sleep modes.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 519
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
Bits 4:2 – MODE[2:0] Operating Mode
These bits must be written to 0x5 to select the I2C host serial communication interface of the SERCOM.
Note: This bit field is enable-protected. This bit field is not synchronized.
Bit 1 – ENABLE Enable
Notes:
1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
2. This bit is not enable-protected.
Value
0
1
Description
The peripheral is disabled or being disabled.
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will
be disabled.
Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register
will return the reset value of the register.
Notes:
1. This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST
synchronization is complete.
2. This bit is not enable-protected.
Value
0
1
Description
There is no reset operation ongoing.
The reset operation is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 520
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.8.2
Control B
Name:
Offset:
Reset:
Property:
Bit
CTRLB
0x04
0x00000000
PAC Write-Protection, Enable-Protected Bits
31
30
29
28
27
26
25
24
23
22
21
20
19
18
ACKACT
R/W
0
17
W
0
W
0
Access
Reset
Bit
Access
Reset
Bit
16
CMD[1:0]
15
14
13
12
11
10
9
QCEN
R/W
0
8
SMEN
R/W
0
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit 18 – ACKACT Acknowledge Action
This bit defines the I2C host's acknowledge behavior after a data byte is received from the I2C client. The
acknowledge action is executed when a command is written to CTRLB.CMD, or if smart mode is enabled
(CTRLB.SMEN is written to one), when DATA.DATA is read.
Note: This bit is not enable-protected.
Value
0
1
Description
Send ACK.
Send NACK.
Bits 17:16 – CMD[1:0] Command
Writing these bits triggers a host operation as described below. The CMD bits are strobe bits, and always read as
zero. The acknowledge action is only valid in host read mode. In host write mode, a command will only result in a
repeated start or stop condition. The CTRLB.ACKACT bit and the CMD bits can be written at the same time, and then
the acknowledge action will be updated before the command is triggered.
Commands can only be issued when either the Client on Bus interrupt flag (INTFLAG.SB) or Host on Bus interrupt
flag (INTFLAG.MB) is '1'.
If CMD 0x1 is issued, a repeated start will be issued followed by the transmission of the current address in
ADDR.ADDR. If another address is desired, ADDR.ADDR must be written instead of the CMD bits. This will trigger a
repeated start followed by transmission of the new address.
Issuing a command will set the System Operation bit in the Synchronization Busy register (SYNCBUSY.SYSOP).
Note: This bit field is not enable-protected.
Table 32-5. Command Description
CMD[1:0]
Direction
Action
0x0
0x1
0x2
X
X
0 (Write)
1 (Read)
(No action)
Execute acknowledge action succeeded by repeated Start
No operation
Execute acknowledge action succeeded by a byte read operation
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 521
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
...........continued
CMD[1:0]
Direction
Action
0x3
X
Execute acknowledge action succeeded by issuing a stop condition
Bit 9 – QCEN Quick Command Enable
Note: This bit is enable-protected.
Value
0
1
Description
Quick Command is disabled.
Quick Command is enabled.
Bit 8 – SMEN Smart Mode Enable
When smart mode is enabled, acknowledge action is sent when DATA.DATA is read.
Note: This bit is enable-protected.
Value
0
1
Description
Smart mode is disabled.
Smart mode is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 522
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.8.3
Baud Rate
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
BAUD
0x0C
0x0000
PAC Write-Protection, Enable-Protected
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
28
27
HSBAUDLOW[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
20
19
HSBAUD[7:0]
R/W
R/W
0
0
12
11
BAUDLOW[7:0]
R/W
R/W
0
0
4
BAUD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:24 – HSBAUDLOW[7:0] High Speed Host Baud Rate Low
HSBAUDLOW non-zero: HSBAUDLOW indicates the SCL low time in High-speed mode according to
HSBAUDLOW = fGCLK ⋅ TLOW − 1
HSBAUDLOW equal to zero: The HSBAUD register is used to time TLOW, THIGH, TSU;STO, THD;STA and TSU;STA.. TBUF is
timed by the BAUD register.
Bits 23:16 – HSBAUD[7:0] High Speed Host Baud Rate
This bit field indicates the SCL high time in High-speed mode according to the following formula. When
HSBAUDLOW is zero, TLOW, THIGH, TSU;STO, THD;STA and TSU;STA are derived using this formula. TBUF is timed by
the BAUD register.
HSBAUD = fGCLK ⋅ THIGH − 1
Bits 15:8 – BAUDLOW[7:0] Host Baud Rate Low
If this bit field is non-zero, the SCL low time will be described by the value written.
For more information on how to calculate the frequency, see SERCOM 29.6.2.3 Clock Generation – Baud-Rate
Generator.
Bits 7:0 – BAUD[7:0] Host Baud Rate
This bit field is used to derive the SCL high time if BAUD.BAUDLOW is non-zero. If BAUD.BAUDLOW is zero, BAUD
will be used to generate both high and low periods of the SCL.
For more information on how to calculate the frequency, see SERCOM 29.6.2.3 Clock Generation – Baud-Rate
Generator.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 523
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.8.4
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x14
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
Access
Reset
7
ERROR
R/W
0
6
5
4
3
2
1
SB
R/W
0
0
MB
R/W
0
Bit 7 – ERROR Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 1 – SB Client on Bus Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Client on Bus Interrupt Enable bit, which disables the Client on Bus interrupt.
Value
Description
0
The Client on Bus interrupt is disabled.
1
The Client on Bus interrupt is enabled.
Bit 0 – MB Host on Bus Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Host on Bus Interrupt Enable bit, which disables the Host on Bus interrupt.
Value
Description
0
The Host on Bus interrupt is disabled.
1
The Host on Bus interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 524
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.8.5
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x16
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
Access
Reset
7
ERROR
R/W
0
6
5
4
3
2
1
SB
R/W
0
0
MB
R/W
0
Bit 7 – ERROR Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 1 – SB Client on Bus Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Client on Bus Interrupt Enable bit, which enables the Client on Bus interrupt.
Value
Description
0
The Client on Bus interrupt is disabled.
1
The Client on Bus interrupt is enabled.
Bit 0 – MB Host on Bus Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Host on Bus Interrupt Enable bit, which enables the Host on Bus interrupt.
Value
Description
0
The Host on Bus interrupt is disabled.
1
The Host on Bus interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 525
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.8.6
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
INTFLAG
0x18
0x00
-
7
ERROR
R/W
0
6
5
4
3
2
1
SB
R/W
0
0
MB
R/W
0
Bit 7 – ERROR Error
This flag is cleared by writing '1' to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status bits in the STATUS
register. These status bits are LENERR, SEXTTOUT, MEXTTOUT, LOWTOUT, ARBLOST, and BUSERR.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 1 – SB Client on Bus
The Client on Bus flag (SB) is set when a byte is successfully received in host read mode, i.e., no arbitration lost or
bus error occurred during the operation. When this flag is set, the host forces the SCL line low, stretching the I2C
clock period. The SCL line will be released and SB will be cleared on one of the following actions:
• Writing to ADDR.ADDR
• Writing to DATA.DATA
• Reading DATA.DATA when smart mode is enabled (CTRLB.SMEN)
• Writing a valid command to CTRLB.CMD
Writing '1' to this bit location will clear the SB flag. The transaction will not continue or be terminated until one of the
above actions is performed.
Writing '0' to this bit has no effect.
Bit 0 – MB Host on Bus
This flag is set when a byte is transmitted in host write mode. The flag is set regardless of the occurrence of a bus
error or an arbitration lost condition. MB is also set when arbitration is lost during sending of NACK in host read
mode, or when issuing a start condition if the bus state is unknown. When this flag is set and arbitration is not lost,
the host forces the SCL line low, stretching the I2C clock period. The SCL line will be released and MB will be cleared
on one of the following actions:
• Writing to ADDR.ADDR
• Writing to DATA.DATA
• Reading DATA.DATA when smart mode is enabled (CTRLB.SMEN)
• Writing a valid command to CTRLB.CMD
Writing '1' to this bit location will clear the MB flag. The transaction will not continue or be terminated until one of the
above actions is performed.
Writing '0' to this bit has no effect.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 526
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.8.7
Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x1A
0x0000
Write-Synchronized
15
14
7
CLKHOLD
R/W
0
6
LOWTOUT
R/W
0
13
12
11
10
LENERR
R/W
0
9
SEXTTOUT
R/W
0
8
MEXTTOUT
R/W
0
3
2
RXNACK
R
0
1
ARBLOST
R/W
0
0
BUSERR
R/W
0
Access
Reset
Bit
Access
Reset
5
4
BUSSTATE[1:0]
R/W
R/W
0
0
Bit 10 – LENERR Transaction Length Error
This bit is set when automatic length is used for a DMA transaction and the client sends a NACK before ADDR.LEN
bytes have been written by the host.
Writing '1' to this bit location will clear STATUS.LENERR. This flag is automatically cleared when writing to the ADDR
register.
Writing '0' to this bit has no effect.
Note: This bit is not synchronized.
Bit 9 – SEXTTOUT Client SCL Low Extend Time-Out
This bit is set if a client SCL low extend time-out occurs.
This bit is automatically cleared when writing to the ADDR register.
Writing '1' to this bit location will clear SEXTTOUT. Normal use of the I2C interface does not require the SEXTTOUT
flag to be cleared by this method.
Writing '0' to this bit has no effect.
Note: This bit is not synchronized.
Bit 8 – MEXTTOUT Host SCL Low Extend Time-Out
This bit is set if a host SCL low time-out occurs.
Writing '1' to this bit location will clear STATUS.MEXTTOUT. This flag is automatically cleared when writing to the
ADDR register.
Writing '0' to this bit has no effect.
Note: This bit is not synchronized.
Bit 7 – CLKHOLD Clock Hold
This bit is set when the host is holding the SCL line low, stretching the I2C clock. Software should consider this bit
when INTFLAG.SB or INTFLAG.MB is set. Do not clear the STATUS.CLKHOLD bit to preserve the current clock hold
state.
This bit is cleared when the corresponding interrupt flag is cleared and the next operation is given.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
Note: This bit is not synchronized.
Bit 6 – LOWTOUT SCL Low Time-Out
This bit is set if an SCL low time-out occurs.
Writing '1' to this bit location will clear this bit. This flag is automatically cleared when writing to the ADDR register.
Writing '0' to this bit has no effect.
Note: This bit is not synchronized.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 527
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
Bits 5:4 – BUSSTATE[1:0] Bus State
These bits indicate the current I2C bus state.
When in UNKNOWN state, writing 0x1 to BUSSTATE forces the bus state into the IDLE state. The bus state cannot
be forced into any other state.
Note: This bit field is write-synchronized: SYNCBUSY.SYSOP must be checked to ensure the STATUS.BUSSTATE
synchronization is complete.
Value
0x0
0x1
0x2
0x3
Name
Description
UNKNOWN The bus state is unknown to the I2C host and will wait for a stop condition to be detected
or wait to be forced into an idle state by software
IDLE
The bus state is waiting for a transaction to be initialized
OWNER
The I2C host is the current owner of the bus
BUSY
Some other I2C host owns the bus
Bit 2 – RXNACK Received Not Acknowledge
This bit indicates whether the last address or data packet sent was acknowledged or not.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
Note: This bit is not synchronized.
Value
0
1
Description
Client responded with ACK.
Client responded with NACK.
Bit 1 – ARBLOST Arbitration Lost
This bit is set if arbitration is lost while transmitting a high data bit or a NACK bit, or while issuing a start or repeated
start condition on the bus. The Host on Bus interrupt flag (INTFLAG.MB) will be set when STATUS.ARBLOST is set.
Writing the ADDR.ADDR register will automatically clear STATUS.ARBLOST.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Note: This bit is not synchronized.
Bit 0 – BUSERR Bus Error
This bit indicates that an illegal bus condition has occurred on the bus, regardless of bus ownership. An illegal bus
condition is detected if a protocol violating start, repeated start or stop is detected on the I2C bus lines. A start
condition directly followed by a stop condition is one example of a protocol violation. If a time-out occurs during a
frame, this is also considered a protocol violation, and will set BUSERR.
If the I2C host is the bus owner at the time a bus error occurs, STATUS.ARBLOST and INTFLAG.MB will be set in
addition to BUSERR.
Writing the ADDR.ADDR register will automatically clear the BUSERR flag.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Note: This bit is not synchronized.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 528
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.8.8
Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x1C
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
SYSOP
R
0
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 2 – SYSOP System Operation Synchronization Busy
Writing CTRLB.CMD, STATUS.BUSSTATE, ADDR, or DATA when the SERCOM is enabled requires synchronization.
When written, the SYNCBUSY.SYSOP bit will be set until synchronization is complete.
Value
Description
0
System operation synchronization is not busy.
1
System operation synchronization is busy.
Bit 1 – ENABLE SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the
SYNCBUSY.ENABLE bit will be set until synchronization is complete.
Value
Description
0
Enable synchronization is not busy.
1
Enable synchronization is busy.
Bit 0 – SWRST Software Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will
be set until synchronization is complete.
Value
Description
0
SWRST synchronization is not busy.
1
SWRST synchronization is busy.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 529
PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.8.9
Address
Name:
Offset:
Reset:
Property:
Bit
ADDR
0x24
0x0000
Write-Synchronized Bits
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
Access
Reset
Bit
LEN[7:0]
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
TENBITEN
R/W
0
14
HS
R/W
0
13
LENEN
R/W
0
12
11
10
8
R/W
0
9
ADDR[10:8]
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 23:16 – LEN[7:0] Transaction Length
These bits define the transaction length of a DMA transaction from 0 to 255 bytes. The Transfer Length Enable
(LENEN) bit must be written to '1' in order to use DMA.
Note: This bit field is not synchronized.
Bit 15 – TENBITEN Ten Bit Addressing Enable
This bit enables 10-bit addressing. This bit can be written simultaneously with ADDR to indicate a 10-bit or 7-bit
address transmission.
Note: This bit is not synchronized.
Value
0
1
Description
10-bit addressing disabled.
10-bit addressing enabled.
Bit 14 – HS High Speed
This bit enables High-speed mode for the current transfer from repeated START to STOP. This bit can be written
simultaneously with ADDR for a high speed transfer.
Note: This bit is not synchronized.
Value
0
1
Description
High-speed transfer disabled.
High-speed transfer enabled.
Bit 13 – LENEN Transfer Length Enable
Note: This bit is not synchronized.
Value
0
1
Description
Automatic transfer length disabled.
Automatic transfer length enabled.
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PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
Bits 10:0 – ADDR[10:0] Address
When ADDR is written, the consecutive operation will depend on the bus state:
UNKNOWN: INTFLAG.MB and STATUS.BUSERR are set, and the operation is terminated.
BUSY: The I2C host will await further operation until the bus becomes IDLE.
IDLE: The I2C host will issue a start condition followed by the address written in ADDR. If the address is
acknowledged, SCL is forced and held low, and STATUS.CLKHOLD and INTFLAG.MB are set.
OWNER: A repeated start sequence will be performed. If the previous transaction was a read, the acknowledge
action is sent before the repeated start bus condition is issued on the bus. Writing ADDR to issue a repeated start is
performed while INTFLAG.MB or INTFLAG.SB is set.
STATUS.BUSERR, STATUS.ARBLOST, INTFLAG.MB and INTFLAG.SB will be cleared when ADDR is written.
The ADDR register can be read at any time without interfering with ongoing bus activity, as a read access does not
trigger the host logic to perform any bus protocol related operations.
The I2C host control logic uses bit 0 of ADDR as the bus protocol’s read/write flag (R/W); 0 for write and 1 for read.
Note: This bit field is write-synchronized: SYNCBUSY.SYSOP must be checked to ensure the ADDR.ADDR
synchronization is complete.
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SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.8.10 Data
Name:
Offset:
Reset:
Property:
DATA
0x28
0x0000
Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.SYSOP must be checked to ensure the DATA register
synchronization is complete.
Bit
15
14
13
12
7
6
5
4
11
10
9
8
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DATA[7:0] Data
The host data register I/O location (DATA) provides access to the host transmit and receive data buffers. Reading
valid data or writing data to be transmitted can be successfully done only when SCL is held low by the host
(STATUS.CLKHOLD is set). An exception is reading the last data byte after the stop condition has been sent.
Accessing DATA.DATA auto-triggers I2C bus operations. The operation performed depends on the state of
CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write).
Writing or reading DATA.DATA when not in Smart mode does not require synchronization.
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PIC32CM MC00 Family
SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.8.11 Debug Control
Name:
Offset:
Reset:
Property:
Bit
DBGCTRL
0x30
0x00
PAC Write-Protection
7
6
5
4
3
Access
Reset
2
1
0
DBGSTOP
R/W
0
Bit 0 – DBGSTOP Debug Stop Mode
This bit controls functionality when the CPU is halted by an external debugger.
This bit will be reset after a software system reset.
Value
Description
0
The baud-rate generator continues normal operation when the CPU is halted by an external debugger.
1
The baud-rate generator is halted when the CPU is halted by an external debugger.
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PIC32CM MC00 Family
Timer Counter (TC)
33.
Timer Counter (TC)
33.1
Overview
There are up to five TC peripheral instances. Each TC consists of a counter, a prescaler, compare/capture channels
and control logic. The counter can be set to count events or clock pulses. The counter, together with the compare/
capture channels, can be configured to timestamp input events or I/O pin edges, allowing for capturing of frequency
and pulse width.
A TC can also perform waveform generation, such as frequency generation and pulse-width modulation.
33.2
Features
•
•
•
•
•
•
•
•
Selectable configuration
– 8, 16, or 32-bit TC operation with compare/capture channels
2 compare/capture channels (CC) with:
– Double buffered timer period setting
– Double buffered compare channel
Waveform generation
– Frequency generation
– Single-slope pulse-width modulation
Input capture
– Event or I/O pin edge capture
– Frequency capture
– Pulse-width capture
– Time-stamp capture
– Minimum and maximum capture
One input event
Interrupts/output events on:
– Counter overflow or underflow
– Compare match or capture
Internal prescaler
DMA support
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PIC32CM MC00 Family
Timer Counter (TC)
33.3
Block Diagram
Figure 33-1. Timer/Counter Block Diagram
Base Counter
BUFV
PERBUF
Prescaler
PER
"count"
Counter
OVF (INT/Event/DMA Req.)
"clear"
ERR (INT Req.)
"load"
COUNT
Control Logic
"direction"
TC Input Event
Event
System
"event"
BOTTOM
=0
UPDATE
TOP
=
Compare/Capture
(Unit x = {0,1}
BUFV
"capture"
CCBUFx
Control Logic
WO[1]
CCx
Waveform
Generation
"match"
=
33.4
WO[0]
MCx (INT/Event/DMA Req.)
Signal Description
Table 33-1. Signal Description for TC.
Signal Name
Type
Description
WO[1:0]
Digital output
Waveform output
Digital input
Capture input
Refer to 4. Pinout and Packaging for details on the pin mapping for this peripheral. One signal can be mapped on
several pins. TC2 and TC3 WO[1:0] signals are not available on the 32-pin variants.
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PIC32CM MC00 Family
Timer Counter (TC)
33.5
Peripheral Dependencies
Peripheral Base Address IRQ
TC0
0x42003000
16
AHB CLK
APB CLK
Generic CLK
Enabled at
reset
Enabled at
reset
Index
-
N
25
PAC
Events
Index
Prot at
reset
User
12
N
23: EVU
DMA
Generator
Index
52: OVF
21: OVF
Sleep
Walking
Y
53-54: MC0-1 22-23: MC0-1
55: OVF
TC1
0x42003400
17
-
N
25
13
N
24: OVF
24: EVU
Y
56-57: MC0-1 25-26: MC0-1
58:OVF
TC2
0x42003800
18
-
N
26
14
N
27: OVF
25: EVU
Y
59-60: MC0-1 28-29: MC0-1
61: OVF
TC3
0x42003C00
19
-
N
26
15
N
30: OVF
26: EVU
Y
62-63: MC0-1 31-32: MC0-1
64:OVF
TC4
0x42004000
20
-
N
27
16
N
33: OVF
27: EVU
Y
65-66: MC0-1 34-35: MC0-1
33.6
Functional Description
33.6.1
Principle of Operation
The following definitions are used throughout the documentation:
Table 33-2. Timer/Counter Definitions
Name
Description
TOP
The counter reaches TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be the same as Period (PER) or the
Compare Channel 0 (CC0) register value depending on the waveform generator
mode in 33.6.2.6.1 Waveform Output Operations.
ZERO
The counter is ZERO when it contains all zeroes
MAX
The counter reaches MAX when it contains all ones
UPDATE
The timer/counter signals an update when it reaches ZERO or TOP, depending
on the direction settings.
Timer
Increment / decrement / clear / reload steps are performed on each prescaled
clock cycle.
Counter
Increment / decrement / clear / reload steps are performed on each detected
event.
CC
For compare operations, the CC are referred to as “compare channels”
For capture operations, the CC are referred to as “capture channels.”
Each TC instance has up to two compare/capture channels (CC0 and CC1).
The counter in the TC can either count events from the Event System, or clock ticks of the GCLK_TCx clock, which
may be divided by the prescaler.
The counter value is passed to the CCx where it can be either compared to user-defined values or captured.
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Timer Counter (TC)
For optimized timing the CCx and CCBUFx registers share a common resource. When writing into CCBUFx, lock the
access to the corresponding CCx register (SYNCBUSY.CCX = 1) till the CCBUFx register value is not loaded into the
CCx register (BUFVx = 1). Each buffer register has a buffer valid (BUFV) flag that indicates when the buffer contains
a new value.
The Counter register (COUNT) and the Compare and Capture registers with buffers (CCx and CCBUFx) can be
configured as 8, 16, or 32-bit registers, with according MAX values. Mode settings (CTRLA.MODE) determine the
maximum range of the Counter register.
In 8-bit mode, a Period Value (PER) register and its Period Buffer Value (PERBUF) register are also available.
The counter range and the operating frequency determine the maximum time resolution achievable with the TC
peripheral.
The TC can be set to count up or down. Under normal operation, the counter value is continuously compared to the
TOP or ZERO value to determine whether the counter has reached that value. On a comparison match the TC can
request DMA transactions, or generate interrupts or events for the Event System.
In compare operation, the counter value is continuously compared to the values in the CCx registers. In case of a
match the TC can request DMA transactions, or generate interrupts or events for the Event System. In waveform
generator mode, these comparisons are used to set the waveform period or pulse width.
Capture operation can be enabled to perform input signal period and pulse width measurements, or to capture
selectable edges from an IO pin or internal event from Event System.
33.6.2
Basic Operation
33.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the TC is disabled
(CTRLA.ENABLE = 0):
•
•
•
•
Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits
Drive Control register (DRVCTRL)
Wave register (WAVE)
Event Control register (EVCTRL)
Writing to Enable-Protected bits and setting the CTRLA.ENABLE bit can be performed in a single 32-bit access of
the CTRLA register. Writing to Enable-Protected bits and clearing the CTRLA.ENABLE bit cannot be performed in a
single 32-bit access.
Before enabling the TC, the peripheral must be configured by the following steps:
1. Enable the TC bus clock (CLK_TCx_APB).
2. Select 8, 16, or 32-bit counter mode through the TC Mode bit group in the Control A register (CTRLA.MODE).
The default mode is 16-bit.
3. Select one wave generation operation in the Waveform Generation Operation bit group in the WAVE register
(WAVE.WAVEGEN).
4. If required, the GCLK_TCx clock can be prescaled via the Prescaler bit group in the Control A register
(CTRLA.PRESCALER).
– If the prescaler is used, select a prescaler synchronization operation via the Prescaler and Counter
Synchronization bit group in the Control A register (CTRLA.PRESYNC).
5. If required, select one-shot operation by writing a '1' to the One-Shot bit in the Control B Set register
(CTRLBSET.ONESHOT).
6. If required, configure the counting direction 'down' (starting from the TOP value) by writing a '1' to the Counter
Direction bit in the Control B register (CTRLBSET.DIR).
7. For capture operation, enable the individual channels to capture in the Capture Channel x Enable bit group in
the Control A register (CTRLA.CAPTEN).
8. If required, enable inversion of the waveform output or IO pin input signal for individual channels via the Invert
Enable bit group in the Drive Control register (DRVCTRL.INVEN).
Note: Two instances of the TC may share a peripheral clock channel. In this case, they cannot be set to different
clock frequencies. Refer to the peripheral clock channel mapping of the Generic Clock Controller (GCLK.PCHTRLm)
to identify shared peripheral clocks.
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PIC32CM MC00 Family
Timer Counter (TC)
33.6.2.2 Enabling, Disabling, and Resetting
The TC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The TC is disabled by
writing a zero to CTRLA.ENABLE.
The TC is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in
the TC, except DBGCTRL, will be reset to their initial state. Refer to the CTRLA register for details.
The TC should be disabled before the TC is reset in order to avoid undefined behavior.
33.6.2.3 Prescaler Selection
The GCLK_TCx is fed into the internal prescaler.
The prescaler consists of a counter that counts up to the selected prescaler value, whereupon the output of the
prescaler toggles.
If the prescaler value is higher than one, the counter update condition can be optionally executed on
the next GCLK_TCx clock pulse or the next prescaled clock pulse. For further details, refer to Prescaler
(CTRLA.PRESCALER) and Counter Synchronization (CTRLA.PRESYNC) description.
Prescaler outputs from 1 to 1/1024 are available. For a complete list of available prescaler outputs, see the register
description for the Prescaler bit group in the Control A register (CTRLA.PRESCALER).
Note: When counting events, the prescaler is bypassed.
The joint stream of prescaler ticks and event action ticks is called CLK_TC_CNT.
Figure 33-2. Prescaler
PRESCALER
GCLK_TC
Prescaler
EVACT
GCLK_TC /
{1,2,4,8,16,64,256,1024}
CLK_TC_CNT
COUNT
EVENT
33.6.2.4 Counter Mode
The counter mode is selected by the Mode bit group in the Control A register (CTRLA.MODE). By default, the counter
is enabled in the 16-bit counter resolution. Three counter resolutions are available:
• COUNT8: The 8-bit TC has its own Period Value and Period Buffer Value registers (PER and PERBUF).
• COUNT16: 16-bit is the default counter mode. There is no dedicated period register in this mode.
• COUNT32: This mode is achieved by pairing two 16-bit TC peripherals. TC0 is paired with TC1, TC2 is paired
with TC3. TC4 cannot be paired.
When paired, the TC peripherals are configured using the registers of the even-numbered TC. The oddnumbered partner will act as a client, and the Client bit in the Status register (STATUS.SLAVE) will be set.
The register values of a client will not reflect the registers of the 32-bit counter. Writing to any of the client
registers will not affect the 32-bit counter. Normal access to the client COUNT and CCx registers is not allowed.
33.6.2.5 Counter Operations
Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each TC
clock input (CLK_TC_CNT). A counter clear or reload marks the end of the current counter cycle and the start of a
new one.
The counting direction is set by the Direction bit in the Control B register (CTRLB.DIR). If this bit is zero the counter
is counting up, and counting down if CTRLB.DIR=1. The counter will count up or down for each tick (clock or event)
until it reaches TOP or ZERO. When it is counting up and TOP is reached, the counter will be set to zero at the next
tick (overflow) and the Overflow Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF) will be
set. When it is counting down, the counter is reloaded with the TOP value when ZERO is reached (underflow), and
INTFLAG.OVF is set.
INTFLAG.OVF can be used to trigger an interrupt, a DMA request, or an event. An overflow/underflow occurrence
(i.e., a compare match with TOP/ZERO) will stop counting if the One-Shot bit in the Control B register is set
(CTRLBSET.ONESHOT).
It is possible to change the counter value (by writing directly in the COUNT register) even when the counter is
running. When starting the TC, the COUNT value will be either ZERO or TOP (depending on the counting direction
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PIC32CM MC00 Family
Timer Counter (TC)
set by CTRLBSET.DIR or CTRLBCLR.DIR), unless a different value has been written to it, or the TC has been
stopped at a value other than ZERO. The write access has higher priority than count, clear, or reload. The direction of
the counter can also be changed when the counter is running. See also the following figure.
Figure 33-3. Counter Operation
Period (T)
Direction Change
COUNT written
MAX
"reload" update
"clear" update
COUNT
TOP
ZERO
DIR
Due to asynchronous clock domains, the internal counter settings are written when the synchronization is complete.
Normal operation must be used when using the counter as timer base for the capture channels.
33.6.2.5.1 Stop Command and Event Action
A Stop command can be issued from software by using Command bits in the Control B Set register
(CTRLBSET.CMD = 0x2, STOP). When a Stop is detected while the counter is running, the counter will be loaded
with the starting value (ZERO or TOP, depending on direction set by CTRLBSET.DIR or CTRLBCLR.DIR). All
waveforms are cleared and the Stop bit in the Status register is set (STATUS.STOP).
33.6.2.5.2 Re-Trigger Command and Event Action
A re-trigger command can be issued from software by writing the Command bits in the Control B Set register
(CTRLBSET.CMD = 0x1, RETRIGGER), or from event when a re-trigger event action is configured in the Event
Control register (EVCTRL.EVACT = 0x1, RETRIGGER).
When the command is detected during counting operation, the counter will be reloaded or cleared, depending on the
counting direction (CTRLBSET.DIR or CTRLBCLR.DIR). When the re-trigger command is detected while the counter
is stopped, the counter will resume counting from the current value in the COUNT register.
Note: When a re-trigger event action is configured in the Event Action bits in the Event Control register
(EVCTRL.EVACT=0x1, RETRIGGER), enabling the counter will not start the counter. The counter will start on the
next incoming event and restart on corresponding following event.
33.6.2.5.3 Count Event Action
The TC can count events. When an event is received, the counter increases or decreases the value, depending on
direction settings (CTRLBSET.DIR or CTRLBCLR.DIR). The count event action can be selected by the Event Action
bit group in the Event Control register (EVCTRL.EVACT=0x2, COUNT).
Note: If this operation mode is selected, PWM generation is not supported.
33.6.2.5.4 Start Event Action
The TC can start counting operation on an event when previously stopped. In this configuration, the event has no
effect if the counter is already counting. When the peripheral is enabled, the counter operation starts when the event
is received or when a re-trigger software command is applied.
The Start TC on Event action can be selected by the Event Action bit group in the Event Control register
(EVCTRL.EVACT=0x3, START).
33.6.2.6 Compare Operations
By default, the Compare/Capture channel is configured for compare operations.
When using the TC and the Compare/Capture Value registers (CCx) for compare operations, the counter value is
continuously compared to the values in the CCx registers. This can be used for timer or for waveform operation.
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PIC32CM MC00 Family
Timer Counter (TC)
The Channel x Compare Buffer (CCBUFx) registers provide double buffer capability. The double buffering
synchronizes the update of the CCx register with the buffer value at the UPDATE condition or a forced update
command (CTRLBSET.CMD=UPDATE). For further details, refer to 33.6.2.7 Double Buffering. The synchronization
prevents the occurrence of odd-length, non-symmetrical pulses and ensures glitch-free output.
33.6.2.6.1 Waveform Output Operations
The compare channels can be used for waveform generation on output port pins. To make the waveform available on
the connected pin, the following requirements must be fulfilled:
1. Choose a waveform generation mode in the Waveform Generation Operation bit in Waveform register
(WAVE.WAVEGEN).
2. Optionally invert the waveform output WO[x] by writing the corresponding Output Waveform x Invert Enable bit
in the Driver Control register (DRVCTRL.INVENx).
3. Configure the pins with the I/O Pin Controller. Refer to PORT - I/O Pin Controller for details.
Note: Event MCx must not be used when the compare channel is set in waveform output operating mode, except
when used as non-recoverable fault input.
The counter value is continuously compared with each CCx value. On a comparison match, the Match or Capture
Channel x bit in the Interrupt Flag Status and Clear register (INTFLAG.MCx) will be set (see Normal Frequency
Operation). An interrupt/and or event can be generated on comparison match if enabled. The same condition
generates a DMA request.
There are four waveform configurations for the Waveform Generation Operation bit group in the Waveform register
(WAVE.WAVEGEN). This will influence how the waveform is generated and impose restrictions on the top value. The
configurations are:
• Normal frequency (NFRQ)
• Match frequency (MFRQ)
• Normal pulse-width modulation (NPWM)
• Match pulse-width modulation (MPWM)
When using NPWM or NFRQ configuration, the TOP will be determined by the counter resolution. In 8-bit Counter
mode, the Period register (PER) is used as TOP, and the TOP can be changed by writing to the PER register. In 16and 32-bit Counter mode, TOP is fixed to the maximum (MAX) value of the counter.
Normal Frequency Generation (NFRQ)
For Normal Frequency Generation, the period time (T) is controlled by the period register (PER) for 8-bit Counter
mode and MAX for 16- and 32-bit mode. The waveform generation output (WO[x]) is toggled on each compare match
between COUNT and CCx, and the corresponding Match or Capture Channel x Interrupt Flag (INTFLAG.MCx) will be
set.
Figure 33-4. Normal Frequency Operation
Period (T)
Direction Change
MAX
COUNT
COUNT Written
"reload" update
"clear" update
"match"
TOP
CCx
ZERO
WO[x]
Match Frequency Generation (MFRQ)
For Match Frequency Generation, the period time (T) is controlled by the CC0 register instead of PER or MAX. WO[0]
toggles on each update condition.
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PIC32CM MC00 Family
Timer Counter (TC)
Figure 33-5. Match Frequency Operation
Period (T)
Direction Change
COUNT Written
MAX
"reload" update
"clear" update
COUNT
CC0
ZERO
WO[0]
Normal Pulse-Width Modulation Operation (NPWM)
NPWM uses single-slope PWM generation.
For single-slope PWM generation, the period time (T) is controlled by the TOP value, and CCx controls the duty
cycle of the generated waveform output. When up-counting, the WO[x] is set at start or compare match between
the COUNT and TOP values, and cleared on compare match between COUNT and CCx register values. When
down-counting, the WO[x] is cleared at start or compare match between the COUNT and ZERO values, and set on
compare match between COUNT and CCx register values.
The following equation calculates the exact resolution for a single-slope PWM (RPWM_SS) waveform:
RPWM_SS =
log(TOP+1)
log(2)
fPWM_SS =
fGCLK_TC
N(TOP+1)
The PWM frequency (fPWM_SS) depends on TOP value and the peripheral clock frequency (fGCLK_TC), and can be
calculated by the following equation:
Where N represents the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024).
Match Pulse-Width Modulation Operation (MPWM)
In MPWM, the output of WO[1] is depending on CC1 as shown in the figure below. On every overflow/underflow, a
one-TC-clock-cycle negative pulse is put out on WO[0] (not shown in the figure).
Figure 33-6. Match PWM Operation
Period(T)
CCx= Zero
CCx= TOP
" clear" update
" match"
MAX
CC0
COUNT
CC1
ZERO
WO[1]
The table below shows the Update Counter and Overflow Event/Interrupt Generation conditions in different operation
modes.
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PIC32CM MC00 Family
Timer Counter (TC)
Table 33-3. Counter Update and Overflow Event/interrupt Conditions in TC
Name
Operation
TOP
Update
Output Waveform
OVFIF/Event
On Match
On Update
Up
Down
NFRQ
Normal Frequency
PER
TOP/ ZERO
Toggle
Stable
TOP
ZERO
MFRQ
Match Frequency
CC0
TOP/ ZERO
Toggle
Stable
TOP
ZERO
NPWM
Single-slope PWM
PER
TOP/ ZERO
See description above
TOP
ZERO
MPWM
Single-slope PWM
CC0
TOP/ ZERO
See description above
TOP
ZERO
33.6.2.7 Double Buffering
The Compare Channels (CCx) registers, and the Period (PER) register in 8-bit mode are double buffered. Each
buffer register has a buffer valid bit (CCBUFVx or PERBUFV) in the STATUS register, which indicates that the buffer
register contains a new valid value that can be copied into the corresponding register. As long as the respective
buffer valid status flag (PERBUFV or CCBUFVx) are set to '1', related syncbusy bits are set (SYNCBUSY.PER or
SYNCBUSY.CCx), a write to the respective PER/PERBUF or CCx/CCBUFx registers will generate a PAC error, and
access to the respective PER or CCx register is invalid.
When the buffer valid flag bit in the STATUS register is '1' and the Lock Update bit in the CTRLB register is set to
'0', (writing CTRLBCLR.LUPD to '1'), double buffering is enabled: the data from buffer registers will be copied into
the corresponding register under hardware UPDATE conditions, then the buffer valid flags bit in the STATUS register
are automatically cleared by hardware. The buffer valid flag bits in the STATUS register can be cleared manually, but
must be cleared two times successively.
Note: The software update command (CTRLBSET.CMD=0x3) is acting independently of the LUPD value.
A compare register is double buffered as in the following figure.
Figure 33-7. Compare Channel Double Buffering
"write enable"
CCBUFVx
UPDATE
"data write"
EN
CCBUFx
EN
CCx
COUNT
=
"match"
Both the registers (PER/CCx) and corresponding buffer registers (PERBUF/CCBUFx) are available in the I/O
register map, and the double buffering feature is not mandatory. The double buffering is disabled by writing a '1'
to CTRLBSET.LUPD.
Note: In NFRQ, MFRQ or PWM down-counting counter mode (CTRLBSET.DIR=1), when double buffering is
enabled (CTRLBCLR.LUPD=1), PERBUF register is continously copied into the PER independently of update
conditions.
Changing the Period
The counter period can be changed by writing a new TOP value to the Period register (PER or CC0, depending on
the waveform generation mode), which is available in 8-bit mode. Any period update on registers (PER or CCx) is
effective after the synchronization delay.
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Timer Counter (TC)
Figure 33-8. Unbuffered Single-Slope Up-Counting Operation
Counter Wraparound
MAX
"clear" update
"write"
COUNT
ZERO
New TOP written to
PER that is higher
than current COUNT
New TOP written to
PER that is lower
than current COUNT
A counter wraparound can occur in any operation mode when up-counting without buffering, see the following figure.
COUNT and TOP are continuously compared, so when a new TOP value that is lower than current COUNT is written
to TOP, COUNT will wrap before a compare match.
Figure 33-9. Unbuffered Single-Slope Down-Counting Operation
MAX
"reload" update
"write"
COUNT
ZERO
New TOP written to
PER that is higher
than current COUNT
New TOP written to
PER that is lower
than current COUNT
When double buffering is used, the buffer can be written at any time and the counter will still maintain correct
operation. The period register is always updated on the update condition, as shown in the following figure. This
prevents wraparound and the generation of odd waveforms.
Figure 33-10. Changing the Period Using Buffering
MAX
" clear" update
" write"
COUNT
ZERO
New TOP written to
PER that is higher
than current COUNT
© 2021 Microchip Technology Inc.
and its subsidiaries
New TOP written to
PER that is lower
than current COUNT
Datasheet
DS60001638D-page 543
PIC32CM MC00 Family
Timer Counter (TC)
33.6.2.8 Capture Operations
To enable and use capture operations, the corresponding Capture Channel x Enable bit in the Control A register
(CTRLA.CAPTENx) must be written to '1'.
A capture trigger can be provided by input event line TC_EV or by asynchronous IO pin WO[x] for each capture
channel or by a TC event. To enable the capture from input event line, Event Input Enable bit in the Event Control
register (EVCTRL.TCEI) must be written to '1'. To enable the capture from the IO pin, the Capture On Pin x Enable bit
in CTRLA register (CTRLA.COPENx) must be written to '1'.
Notes:
1. The RETRIGGER, COUNT and START event actions are available only on an event from the Event System.
2. Event system channels must be configured to operate in asynchronous mode of operation when used for
capture operations.
By default, a capture operation is done when a rising edge is detected on the input signal. Capture on falling edge is
available, its activation is depending on the input source:
• When the channel is used with a IO pin, write a '1' to the corresponding Invert Enable bit in the Drive Control
register (DRVCTRL.INVENx).
• When the channel is counting events from the Event System, write a '1' to the TC Event Input Invert Enable bit
in Event Control register (EVCTRL.TCINV).
Figure 33-11. Capture Double Buffering
"capture"
COUNT
BV
EN
CCBx
IF
EN
CCx
"INT/DMA
request"
data read
For input capture, the buffer register and the corresponding CCx act like a FIFO. When CCx is empty or read,
any content in CCBUFx is transferred to CCx. The buffer valid flag is passed to set the CCx interrupt flag (IF) and
generate the optional interrupt, event or DMA request. The CCBUFx register value can't be read, all captured data
must be read from CCx register.
33.6.2.8.1 Event Capture Action
The compare/capture channels can be used as input capture channels to capture events from the Event System and
give them a timestamp. The following figure shows four capture events for one capture channel.
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and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Timer Counter (TC)
Figure 33-12. Input Capture Timing
events
TOP
COUNT
ZERO
Capture 0
Capture 1
Capture 2
Capture 3
The TC can detect capture overflow of the input capture channels: When a new capture event is detected while the
Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set.
33.6.2.8.2 Period and Pulse-Width (PPW) Capture Action
The TC can perform two input captures and restart the counter on one of the edges. This enables the TC to measure
the pulse width and period and to characterize the frequency f and duty cycle of an input signal:
f= 1
T
dutyCycle =
tp
T
Figure 33-13. PWP Capture
Period (T)
external signal
Pulsewitdh (tp)
events
MAX
"capture"
COUNT
ZERO
CC0
CC1
CC0
CC1
Selecting PWP in the Event Action bit group in the Event Control register (EVCTRL.EVACT) enables the TC to
perform one capture action on the rising edge and the other one on the falling edge. The period T will be captured
into CC1 and the pulse width tp in CC0. EVCTRL.EVACT=PPW (period and pulse-width) offers identical functionality,
but will capture T into CC0 and tp into CC1.
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Datasheet
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PIC32CM MC00 Family
Timer Counter (TC)
The TC Event Input Invert Enable bit in the Event Control register (EVCTRL.TCINV) is used to select whether
the wraparound should occur on the rising edge or the falling edge. If EVCTRL.TCINV=1, the wraparound will
happen on the falling edge. In case pin capture is enabled, this can also be achieved by modifying the value of the
DRVCTRL.INVENx bit.
The TC can detect capture overflow of the input capture channels: When a new capture event is detected while the
Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set.
Note: The corresponding capture is working only if the channel is enabled in capture mode (CTRLA.CAPTENx=1).
If not, the capture action is ignored and the channel is enabled in compare mode of operation. Consequently, both
channels must be enabled in order to fully characterize the input.
33.6.2.8.3 Pulse-Width Capture Action
The TC performs the input capture on the falling edge of the input signal. When the edge is detected, the counter
value is cleared and the TC stops counting. When a rising edge is detected on the input signal, the counter restarts
the counting operation. To enable the operation on opposite edges, the input signal to capture must be inverted (refer
to DRVCTRL.INVEN or EVCTRL.TCEINV).
Figure 33-14. Pulse-Width Capture on Channel 0
external signal
Pulsewitdh (tp)
events
MAX
"capture"
"restart"
COUNT
ZERO
CC0
CC0
The TC can detect capture overflow of the input capture channels: When a new capture event is detected while the
Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set.
33.6.3
Additional Features
33.6.3.1 One-Shot Operation
When one-shot is enabled, the counter automatically stops on the next counter overflow or underflow condition.
When the counter is stopped, the Stop bit in the Status register (STATUS.STOP) is automatically set and the
waveform outputs are set to zero.
One-shot operation is enabled by writing a '1' to the One-Shot bit in the Control B Set register
(CTRLBSET.ONESHOT), and disabled by writing a '1' to CTRLBCLR.ONESHOT. When enabled, the TC will count
until an overflow or underflow occurs and stops counting operation. The one-shot operation can be restarted
by a re-trigger software command, a re-trigger event, or a start event. When the counter restarts its operation,
STATUS.STOP is automatically cleared.
33.6.3.2 Time-Stamp Capture
This feature is enabled when the Capture Time Stamp (STAMP) Event Action in Event Control register
(EVCTRL.EVACT) is selected. The counter TOP value must be smaller than MAX.
When a capture event is detected, the COUNT value is copied into the corresponding Channel x Compare/Capture
Value (CCx) register. In case of an overflow, the MAX value is copied into the corresponding CCx register.
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PIC32CM MC00 Family
Timer Counter (TC)
When a valid captured value is present in the capture channel register, the corresponding Capture Channel x
Interrupt Flag (INTFLAG.MCx) is set.
The timer/counter can detect capture overflow of the input capture channels: When a new capture event is detected
while the Capture Channel interrupt flag (INTFLAG.MCx) is still set, the new time-stamp will not be stored and
INTFLAG.ERR will be set.
Figure 33-15. Time-Stamp
Capture Events
MAX
TOP
"capture"
"overflow"
COUNT
ZERO
CCx Value
COUNT
COUNT
TOP
COUNT
MAX
33.6.3.3 Minimum Capture
The minimum capture is enabled by writing the CAPTMIN mode in the Channel n Capture Mode bits in the Control A
register (CTRLA.CAPTMODEn = CAPTMIN).
CCx Content:
In CAPTMIN operations, CCx keeps the Minimum captured values. Before enabling this mode of capture, the user
must initialize the corresponding CCx register value to a value different from zero. If the CCx register initial value is
zero, no captures will be performed using the corresponding channel.
MCx Behaviour:
In CAPTMIN operation, capture is performed only when on capture event time, the counter value is lower than the
last captured value. The MCx interrupt flag is set only when on capture event time, the counter value is upper or
equal to the value captured on the previous event. So interrupt flag is set when a new absolute local Minimum value
has been detected.
33.6.3.4 Maximum Capture
The maximum capture is enabled by writing the CAPTMAX mode in the Channel n Capture Mode bits in the Control
A register (CTRLA.CAPTMODEn = CAPTMAX).
CCx Content:
In CAPTMAX operations, CCx keeps the Maximum captured values. Before enabling this mode of capture, the user
must initialize the corresponding CCx register value to a value different from TOP. If the CCx register initial value is
TOP, no captures will be performed using the corresponding channel.
MCx Behaviour:
In CAPTMAX operation, capture is performed only when on capture event time, the counter value is upper than the
last captured value. The MCx interrupt flag is set only when on capture event time, the counter value is lower or equal
to the value captured on the previous event. So interrupt flag is set when a new absolute local Maximum value has
been detected.
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and its subsidiaries
Datasheet
DS60001638D-page 547
PIC32CM MC00 Family
Timer Counter (TC)
Figure 33-16. Maximum Capture Operation with CC0 Initialized with ZERO Value
TOP
COUNT
"clear" update
"match"
CC0
ZERO
Input event
CC0 Event/
Interrupt
33.6.4
DMA Operation
The TC can generate the following DMA requests:
• Overflow (OVF): The request is set when an update condition (overflow, underflow, or re-trigger) is detected, the
request is cleared by hardware on DMA acknowledge.
• Match or Capture Channel x (MCx): For a compare channel, the request is set on each compare match
detection, the request is cleared by hardware on DMA acknowledge. For a capture channel, the request is set
when valid data is present in the CCx register, and cleared when the CCx register is read.
Note: Updates to the PER register are not possible with the DMA while in Standby mode.
33.6.5
Interrupts
The TC has the following interrupt sources:
•
•
•
Overflow/Underflow (OVF)
Match or Capture Channel x (MCx)
Capture Overflow Error (ERR)
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs.
Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set register
(INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).
As both INTENSET and INTENCLR always reflect the same value, the status of interrupt enablement can be read
from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the TC is reset.
See INTFLAG for details on how to clear interrupt flags.
The TC has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register
to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to 9.2 Nested Vector
Interrupt Controller for details.
33.6.6
Events
The TC can generate the following output events:
•
•
Overflow/Underflow (OVF)
Match or Capture Channel x (MCx)
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.MCEOx) enables the corresponding output
event. The output event is disabled by writing EVCTRL.MCEOx=0.
One of the following event actions can be selected by the Event Action bit group in the Event Control register
(EVCTRL.EVACT):
• Disable event action (OFF)
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Datasheet
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PIC32CM MC00 Family
Timer Counter (TC)
•
•
•
•
•
•
Start TC (START)
Re-trigger TC (RETRIGGER)
– If a re-trigger event occurs exactly at the time a Channel Compare Match occurs, the next waveform will
be corrupted. To avoid this issue, use two channels to store two successive CC register values (n and n+1)
and combine the related waveform outputs to provide signal redundancy.
Count on event (COUNT)
Capture time stamp (STAMP)
Capture Period (PPW and PWP)
Capture Pulse Width (PW)
Writing a '1' to the TC Event Input bit in the Event Control register (EVCTRL.TCEI) enables input events (EVU) to
the TC. Writing a '0' to this bit disables input events to the TC. The TC requires only asynchronous event inputs. For
additional information on how configuring the asynchronous events, refer to the 28. Event System (EVSYS).
33.6.7
Sleep Mode Operation
The TC can be configured to operate in any sleep mode. To be able to run in standby, the RUNSTDBY bit in the
Control A register (CTRLA.RUNSTDBY) must be '1'. This peripheral can wake up the device from any sleep mode
using interrupts or perform actions through the Event System.
If the On Demand bit in the Control A register (CTRLA.ONDEMAND) is written to '1', the module stops requesting
its peripheral clock when the STOP bit in STATUS register (STATUS.STOP) is set to '1'. When a re-trigger or start
condition is detected, the TC requests the clock before the operation starts.
When the device is in STANDBY sleep mode the DMA is not able to write the CTRLB, STATUS, COUNT, PER,
PERBUF, CC, CCBUF registers. To write these registers with the DMA the device must be in Active mode or IDLE
sleep mode.
33.6.8
Debug Operation
When the CPU is halted in Debug mode, this peripheral will halt normal operation. This peripheral can be forced to
continue operation during debugging. Refer to the Debug Control (DBGCTRL) register for details.
33.6.9
Synchronization
Some registers (or bit fields within a register) require synchronization when read and/or written.
Synchronization is denoted by the "Read-Synchronized" (or "Read-Synchronized Bits”) and/or "Write-Synchronized"
(or "Write-Synchronized Bits”) property in each individual register description.
For more details, refer to Register Synchronization.
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Datasheet
DS60001638D-page 549
PIC32CM MC00 Family
Timer Counter (TC)
33.7
Register Summary - 8-bit Mode
Offset
Name
0x00
CTRLA
0x04
0x05
CTRLBCLR
CTRLBSET
0x06
EVCTRL
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
INTENCLR
INTENSET
INTFLAG
STATUS
WAVE
DRVCTRL
Reserved
DBGCTRL
0x10
SYNCBUSY
0x14
0x15
...
0x1A
0x1B
0x1C
0x1D
0x1E
...
0x2E
0x2F
0x30
0x31
COUNT
Bit Pos.
7:0
15:8
23:16
31:24
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
23:16
31:24
7:0
7
6
ONDEMAND RUNSTDBY
5
4
3
PRESCSYNC[1:0]
CC0
1
0
MODE[1:0]
ALOCK
COPEN1
COPEN0
CAPTMODE1[1:0]
TCEI
MCEO1
MC1
MC1
MC1
CCBUFV1
TCINV
MCEO0
MC0
MC0
MC0
CCBUFV0
PERBUFV
PER
COUNT
STATUS
CMD[2:0]
CMD[2:0]
CC1
2
ENABLE
SWRST
PRESCALER[2:0]
CAPTEN1
CAPTEN0
CAPTMODE0[1:0]
ONESHOT
LUPD
DIR
ONESHOT
LUPD
DIR
EVACT[2:0]
OVFEO
ERR
OVF
ERR
OVF
ERR
OVF
SLAVE
STOP
WAVEGEN[1:0]
INVEN1
INVEN0
CTRLB
ENABLE
DBGRUN
SWRST
COUNT[7:0]
Reserved
PER
CC0
CC1
7:0
7:0
7:0
PER[7:0]
CC[7:0]
CC[7:0]
7:0
7:0
7:0
PERBUF[7:0]
CCBUF[7:0]
CCBUF[7:0]
Reserved
PERBUF
CCBUF0
CCBUF1
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Datasheet
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PIC32CM MC00 Family
Timer Counter (TC)
33.7.1
Control A
Name:
Offset:
Reset:
Property:
Bit
CTRLA
0x00
0x00000000
PAC Write-Protection, Write-Synchronized Bits, Enable-Protected Bits
31
30
29
23
22
21
COPEN1
R/W
0
20
COPEN0
R/W
0
19
18
17
CAPTEN1
R/W
0
16
CAPTEN0
R/W
0
15
14
13
12
11
ALOCK
R/W
0
10
8
R/W
0
9
PRESCALER[2:0]
R/W
0
R/W
0
3
2
1
ENABLE
R/W
0
0
SWRST
W
0
Access
Reset
Bit
Access
Reset
Bit
28
27
CAPTMODE1[1:0]
R/W
R/W
0
0
Access
Reset
Bit
Access
Reset
7
ONDEMAND
R/W
0
6
RUNSTDBY
R/W
0
5
4
PRESCSYNC[1:0]
R/W
R/W
0
0
26
MODE[1:0]
R/W
0
R/W
0
25
24
CAPTMODE0[1:0]
R/W
R/W
0
0
Bits 28:27 – CAPTMODE1[1:0] Capture mode Channel 1
These bits select the channel 1 capture mode.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
Name
DEFAULT
CAPTMIN
CAPTMAX
Description
Default capture
Minimum capture
Maximum capture
Reserved
Bits 25:24 – CAPTMODE0[1:0] Capture mode Channel 0
These bits select the channel 0 capture mode.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
Name
DEFAULT
CAPTMIN
CAPTMAX
Description
Default capture
Minimum capture
Maximum capture
Reserved
Bits 20, 21 – COPENx Capture On Pin x Enable [x = 1..0]
Bit x of COPEN[1:0] selects the trigger source for capture operation, either events or I/O pin input.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
Event from Event System is selected as trigger source for capture operation on channel x.
I/O pin is selected as trigger source for capture operation on channel x.
Bits 16, 17 – CAPTENx Capture Channel x Enable [x = 1..0]
Bit x of CAPTEN[1:0] selects whether channel x is a capture or a compare channel.
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PIC32CM MC00 Family
Timer Counter (TC)
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
CAPTEN disables capture on channel x.
CAPTEN enables capture on channel x.
Bit 11 – ALOCK Auto Lock
When this bit is set, Lock bit update (LUPD) is set to '1' on each overflow/underflow or re-trigger event.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
The LUPD bit is not affected on overflow/underflow, and re-trigger event.
The LUPD bit is set on each overflow/underflow or re-trigger event.
Bits 10:8 – PRESCALER[2:0] Prescaler
These bits select the counter prescaler factor.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
DIV1
DIV2
DIV4
DIV8
DIV16
DIV64
DIV256
DIV1024
Description
Prescaler: GCLK_TC
Prescaler: GCLK_TC/2
Prescaler: GCLK_TC/4
Prescaler: GCLK_TC/8
Prescaler: GCLK_TC/16
Prescaler: GCLK_TC/64
Prescaler: GCLK_TC/256
Prescaler: GCLK_TC/1024
Bit 7 – ONDEMAND Clock On Demand
This bit selects the clock requirements when the TC is stopped.
In standby mode, if the Run in Standby bit (CTRLA.RUNSTDBY) is '0', ONDEMAND is forced to '0'.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
The On Demand is disabled. If On Demand is disabled, the TC will continue to request the clock when
its operation is stopped (STATUS.STOP=1).
The On Demand is enabled. When On Demand is enabled, the stopped TC will not request the
clock. The clock is requested when a software re-trigger command is applied or when an event with
start/re-trigger action is detected.
Bit 6 – RUNSTDBY Run in Standby
This bit is used to keep the TC running in standby mode.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
The TC is halted in standby.
The TC continues to run in standby.
Bits 5:4 – PRESCSYNC[1:0] Prescaler and Counter Synchronization
These bits select whether the counter should wrap around on the next GCLK_TCx clock or the next prescaled
GCLK_TCx clock. It also makes it possible to reset the prescaler.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
Name
GCLK
PRESC
RESYNC
-
Description
Reload or reset the counter on next generic clock
Reload or reset the counter on next prescaler clock
Reload or reset the counter on next generic clock. Reset the prescaler counter
Reserved
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PIC32CM MC00 Family
Timer Counter (TC)
Bits 3:2 – MODE[1:0] Timer Counter Mode
These bits select the counter mode.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
Name
COUNT16
COUNT8
COUNT32
-
Description
Counter in 16-bit mode
Counter in 8-bit mode
Counter in 32-bit mode
Reserved
Bit 1 – ENABLE Enable
Notes:
1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
2. This bit is not enable protected.
Value
0
1
Description
The peripheral is disabled.
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be
disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be
discarded.
Notes:
1. This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST
synchronization is complete.
2. This bit is not enable protected.
Value
0
1
Description
There is no reset operation ongoing.
The reset operation is ongoing.
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PIC32CM MC00 Family
Timer Counter (TC)
33.7.2
Control B Clear
Name:
Offset:
Reset:
Property:
CTRLBCLR
0x04
0x00
PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Set register (CTRLBSET).
Note: This register is read- and write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the
CTRLBCLR register synchronization is complete.
Bit
Access
Reset
7
R/W
0
6
CMD[2:0]
R/W
0
5
4
3
R/W
0
2
ONESHOT
R/W
0
1
LUPD
R/W
0
0
DIR
R/W
0
Bits 7:5 – CMD[2:0] Command
These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC
clock cycle. When a command has been executed, the CMD bit group will be read back as zero.
Writing 0x0 to these bits has no effect.
Writing a value different from 0x0 to this bit field bits will clear the pending command.
Bit 2 – ONESHOT One-Shot on Counter
This bit controls one-shot operation of the TC.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will disable one-shot operation.
Value
Description
0
The TC will wrap around and continue counting on an overflow/underflow condition.
1
The TC will wrap around and stop on the next underflow/overflow condition.
Bit 1 – LUPD Lock Update
This bit controls the update operation of the TC buffered registers.
When CTRLB.LUPD is set, no any update of the registers with value of its buffered register is performed on hardware
UPDATE condition. Locking the update ensures that all buffer registers are valid before an hardware update is
performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked.
This bit has no effect when input capture operation is enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the LUPD bit.
Value
Description
0
The CCBUFx and PERBUF buffer registers value are copied into CCx and PER registers on hardware
update condition.
1
The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on
hardware update condition.
Bit 0 – DIR Counter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the bit and make the counter count up.
Value
Description
0
The timer/counter is counting up (incrementing).
1
The timer/counter is counting down (decrementing).
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PIC32CM MC00 Family
Timer Counter (TC)
33.7.3
Control B Set
Name:
Offset:
Reset:
Property:
CTRLBSET
0x05
0x00
PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Clear register (CTRLBCLR).
Note: This register is read- and write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the
CTRLBSET register synchronization is complete.
Bit
Access
Reset
7
6
CMD[2:0]
R/W
0
R/W
0
5
4
3
R/W
0
2
ONESHOT
R/W
0
1
LUPD
R/W
0
0
DIR
R/W
0
Bits 7:5 – CMD[2:0] Command
These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC
clock cycle. When a command has been executed, the CMD bit group will be read back as zero.
Writing 0x0 to these bits has no effect.
Writing a value different from 0x0 to these bits will issue a command for execution.
Important: This command requires synchronization before being executed. A valid sequence is:
• Issue CMD command (CTRLBSET.CMD = command)
• Wait for CMD synchronization (SYNCBUSY.CTRLB = 0)
• Wait for CMD read back as zero (CTRLBSET.CMD = 0)
Value
0x0
0x1
0x2
0x3
0x4
Name
NONE
RETRIGGER
STOP
UPDATE
READSYNC
Description
No action
Force a start, restart or retrigger
Force a stop
Force update of double buffered registers
Force a read synchronization of COUNT
Bit 2 – ONESHOT One-Shot on Counter
This bit controls one-shot operation of the TC.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will enable one-shot operation.
Value
Description
0
The TC will wrap around and continue counting on an overflow/underflow condition.
1
The TC will wrap around and stop on the next underflow/overflow condition.
Bit 1 – LUPD Lock Update
This bit controls the update operation of the TC buffered registers.
When CTRLB.LUPD is set, no any update of the registers with value of its buffered register is performed on hardware
UPDATE condition. Locking the update ensures that all buffer registers are valid before an hardware update is
performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the LUPD bit.
This bit has no effect when input capture operation is enabled.
Value
Description
0
The CCBUFx and PERBUF buffer registers value are copied into CCx and PER registers on hardware
update condition.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 555
PIC32CM MC00 Family
Timer Counter (TC)
Value
1
Description
The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on
hardware update condition.
Bit 0 – DIR Counter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will set the bit and make the counter count down.
Value
Description
0
The timer/counter is counting up (incrementing).
1
The timer/counter is counting down (decrementing).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 556
PIC32CM MC00 Family
Timer Counter (TC)
33.7.4
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x06
0x0000
PAC Write-Protection, Enable-Protected
15
14
13
MCEO1
R/W
0
12
MCEO0
R/W
0
11
10
9
8
OVFEO
R/W
0
7
6
5
TCEI
R/W
0
4
TCINV
R/W
0
3
2
1
EVACT[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
Bits 12, 13 – MCEOx Match or Capture Channel x Event Output Enable [x = 1..0]
These bits enable the generation of an event for every match or capture on channel x.
Value
Description
0
Match/Capture event on channel x is disabled and will not be generated.
1
Match/Capture event on channel x is enabled and will be generated for every compare/capture.
Bit 8 – OVFEO Overflow/Underflow Event Output Enable
This bit enables the Overflow/Underflow event. When enabled, an event will be generated when the counter
overflows/underflows.
Value
Description
0
Overflow/Underflow event is disabled and will not be generated.
1
Overflow/Underflow event is enabled and will be generated for every counter overflow/underflow.
Bit 5 – TCEI TC Event Enable
This bit is used to enable asynchronous input events to the TC.
Value
Description
0
Incoming events are disabled.
1
Incoming events are enabled.
Bit 4 – TCINV TC Inverted Event Input Polarity
This bit inverts the asynchronous input event source.
Value
Description
0
Input event source is not inverted.
1
Input event source is inverted.
Bits 2:0 – EVACT[2:0] Event Action
These bits define the event action the TC will perform on an event.
Value
Name
Description
0x0
OFF
Event action disabled
0x1
RETRIGGER
Start, restart or retrigger TC on event
0x2
COUNT
Count on event (not a valid selection for waveform generation)
0x3
START
Start TC on event
0x4
STAMP
Time stamp capture
0x5
PPW
Period captured in CC0, pulse width in CC1
0x6
PWP
Period captured in CC1, pulse width in CC0
0x7
PW
Pulse width capture
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 557
PIC32CM MC00 Family
Timer Counter (TC)
33.7.5
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x08
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
6
Access
Reset
5
MC1
R/W
0
4
MC0
R/W
0
3
2
1
ERR
R/W
0
0
OVF
R/W
0
Bits 4, 5 – MCx Match or Capture Channel x Interrupt Disable [x = 1..0]
Writing a '0' to these bits has no effect.
Writing a '1' to MCx will clear the corresponding Match or Capture Channel x Interrupt Enable bit, which disables the
Match or Capture Channel x interrupt.
Value
Description
0
The Match or Capture Channel x interrupt is disabled.
1
The Match or Capture Channel x interrupt is enabled.
Bit 1 – ERR Error Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
The Error interrupt is disabled.
1
The Error interrupt is enabled.
Bit 0 – OVF Overflow Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt request.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 558
PIC32CM MC00 Family
Timer Counter (TC)
33.7.6
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x09
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
7
6
Access
Reset
5
MC1
R/W
0
4
MC0
R/W
0
3
2
1
ERR
R/W
0
0
OVF
R/W
0
Bits 4, 5 – MCx Match or Capture Channel x Interrupt Enable [x = 1..0]
Writing a '0' to these bits has no effect.
Writing a '1' to MCx will set the corresponding Match or Capture Channel x Interrupt Enable bit, which enables the
Match or Capture Channel x interrupt.
Value
Description
0
The Match or Capture Channel x interrupt is disabled.
1
The Match or Capture Channel x interrupt is enabled.
Bit 1 – ERR Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
The Error interrupt is disabled.
1
The Error interrupt is enabled.
Bit 0 – OVF Overflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt request.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 559
PIC32CM MC00 Family
Timer Counter (TC)
33.7.7
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAG
0x0A
0x00
-
6
Access
Reset
5
MC1
R/W
0
4
MC0
R/W
0
3
2
1
ERR
R/W
0
0
OVF
R/W
0
Bits 4, 5 – MCx Match or Capture Channel x Interrupt Flag [x = 1..0]
This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture value. This
flag will generate an interrupt request if the corresponding INTENCLR.MCx or INTENSET.MCx bit is '1'.
Writing a '0' to one of these bits has no effect.
Writing a '1' to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag.
In capture operation, this flag is automatically cleared when CCx register is read.
Bit 1 – ERR Error Interrupt Flag
This flag is set when a new capture occurs on a channel while the corresponding Match or Capture Channel x
interrupt flag is set, in which case there is nowhere to store the new capture.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Error interrupt flag.
Bit 0 – OVF Overflow Interrupt Flag
This flag is set after an overflow condition occurs, and will generate an interrupt request if INTENCLR.OVF or
INTENSET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 560
PIC32CM MC00 Family
Timer Counter (TC)
33.7.8
Status
Name:
Offset:
Reset:
Property:
STATUS
0x0B
0x01
Read-Synchronized, Write-Synchronized
Note: This register is read- and write-synchronized: SYNCBUSY.STATUS must be checked to ensure the STATUS
register synchronization is complete.
Bit
7
6
Access
Reset
5
CCBUFV1
R/W
0
4
CCBUFV0
R/W
0
3
PERBUFV
R/W
0
2
1
SLAVE
R/W
0
0
STOP
R
1
Bits 4, 5 – CCBUFVx Channel x Compare or Capture Buffer Valid
For a compare channel x, the bit x is set when a new value is written to the corresponding CCBUFx register.
The bit x is cleared by writing a '1' to it when CTRLB.LUPD is set, or it is cleared automatically by hardware on
UPDATE condition. If clearing this bit manually to force an update of the PER register, it is necessary to clear the bit
two times successively.
For a capture channel x, the bit x is set when a valid capture value is stored in the CCBUFx register. The bit x is
cleared automatically when the CCx register is read.
Bit 3 – PERBUFV Period Buffer Valid
This bit is set when a new value is written to the PERBUF register. The bit is cleared by writing '1' to the
corresponding location when CTRLB.LUPD is set, or automatically cleared by hardware on UPDATE condition. This
bit is available only in 8-bit mode and will always read zero in 16- and 32-bit modes. If clearing this bit manually to
force an update of the CCx register, it is necessary to clear the bit two times successively.
Bit 1 – SLAVE Client Status Flag
This bit is only available in 32-bit mode on the client TC (i.e., TC1 and/or TC3). The bit is set when the associated
host TC (TC0 and TC2, respectively) is set to run in 32-bit mode.
Bit 0 – STOP Stop Status Flag
This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when the
One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is '1'.
Value
Description
0
Counter is running.
1
Counter is stopped.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 561
PIC32CM MC00 Family
Timer Counter (TC)
33.7.9
Waveform Generation Control
Name:
Offset:
Reset:
Property:
Bit
WAVE
0x0C
0x00
PAC Write-Protection, Enable-Protected
7
6
5
4
3
2
Access
Reset
1
0
WAVEGEN[1:0]
R/W
R/W
0
0
Bits 1:0 – WAVEGEN[1:0] Waveform Generation Mode
These bits select the waveform generation operation. They affect the top value, as shown in 33.6.2.6.1 Waveform
Output Operations. They also control whether frequency or PWM waveform generation should be used. The
waveform generation operations are explained in 33.6.2.6.1 Waveform Output Operations.
Note: This bit field is not synchronized.
Value
Name
Operation
Top Value
Output Waveform
on Match
Output Waveform
on Wraparound
0x0
0x1
0x2
0x3
NFRQ
MFRQ
NPWM
MPWM
Normal frequency
Match frequency
Normal PWM
Match PWM
PER(1)/Max.
CC0
PER(1)/ Max.
CC0
Toggle
Toggle
Set
Set
No action
Toggle
Clear
Clear
1) This depends on the TC mode: In 8-bit mode, the top value is the Period Value register (PER). In 16- and 32-bit
mode it is the respective MAX value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 562
PIC32CM MC00 Family
Timer Counter (TC)
33.7.10 Driver Control
Name:
Offset:
Reset:
Property:
Bit
DRVCTRL
0x0D
0x00
PAC Write-Protection, Enable-Protected
7
6
5
4
3
2
Access
Reset
1
INVEN1
R/W
0
0
INVEN0
R/W
0
Bits 0, 1 – INVENx Output Waveform x Invert Enable [x = 1..0]
The INVENx bit selects inversion of the output or capture trigger input of channel x.
Value
Description
0
Disable inversion of the WO[x] output and IO input pin.
1
Enable inversion of the WO[x] output and IO input pin.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 563
PIC32CM MC00 Family
Timer Counter (TC)
33.7.11 Debug Control
Name:
Offset:
Reset:
Property:
Bit
DBGCTRL
0x0F
0x00
PAC Write-Protection
7
6
5
4
3
Access
Reset
2
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Run in Debug Mode
This bit is affected by a software system Reset, and should not be changed by software while the TC is enabled.
Value
Description
0
The TC is halted when the device is halted in debug mode.
1
The TC continues normal operation when the device is halted in debug mode.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 564
PIC32CM MC00 Family
Timer Counter (TC)
33.7.12 Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x10
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
CC1
R
0
6
CC0
R
0
5
PER
R
0
4
COUNT
R
0
3
STATUS
R
0
2
CTRLB
R
0
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 6, 7 – CCx Compare/Capture Channel x Synchronization Busy [x = 1..0]
For details on CC channels number, refer to each TC feature list.
This bit is set when the synchronization of CCx between clock domains is started.
This bit is also set when the CCBUFx is written, and cleared on update condition. The bit is automatically cleared
when the STATUS.CCBUFx bit is cleared.
This bit is cleared when the synchronization of CCx between the clock domains is complete.
Bit 5 – PER PER Synchronization Busy
This bit is cleared when the synchronization of PER between the clock domains is complete.
This bit is set when the synchronization of PER between clock domains is started.
This bit is also set when the PERBUF is written, and cleared on update condition. The bit is automatically cleared
when the STATUS.PERBUF bit is cleared.
Bit 4 – COUNT COUNT Synchronization Busy
This bit is cleared when the synchronization of COUNT between the clock domains is complete.
This bit is set when the synchronization of COUNT between clock domains is started.
Bit 3 – STATUS STATUS Synchronization Busy
This bit is cleared when the synchronization of STATUS between the clock domains is complete.
This bit is set when a '1' is written to the Capture Channel Buffer Valid status flags (STATUS.CCBUFVx) and the
synchronization of STATUS between clock domains is started.
Bit 2 – CTRLB CTRLB Synchronization Busy
This bit is cleared when the synchronization of CTRLBSET or CTRLBCLR between the clock domains is complete.
This bit is set when the synchronization of CTRLBSET or CTRLBCLR between clock domains is started.
Bit 1 – ENABLE ENABLE Synchronization Busy
This bit is cleared when the synchronization of ENABLE bit between the clock domains is complete.
This bit is set when the synchronization of ENABLE bit between clock domains is started.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 565
PIC32CM MC00 Family
Timer Counter (TC)
Bit 0 – SWRST SWRST Synchronization Busy
This bit is cleared when the synchronization of SWRST bit between the clock domains is complete.
This bit is set when the synchronization of SWRST bit between clock domains is started.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 566
PIC32CM MC00 Family
Timer Counter (TC)
33.7.13 Counter Value, 8-bit Mode
Name:
Offset:
Reset:
Property:
COUNT
0x14
0x0000
PAC Write-Protection, Write-Synchronized, Read-Synchronized
Notes:
1. This register is read-synchronized: Prior to any read access, this register must be synchronized by user by
writing the according TC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC).
2. This register is write-synchronized: SYNCBUSY.COUNT must be checked to ensure the COUNT register
synchronization is complete.
Bit
Access
Reset
7
6
5
R/W
0
R/W
0
R/W
0
4
3
COUNT[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – COUNT[7:0] Counter Value
These bits contain the current counter value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 567
PIC32CM MC00 Family
Timer Counter (TC)
33.7.14 Period Value, 8-bit Mode
Name:
Offset:
Reset:
Property:
PER
0x1B
0xFF
Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.PER must be checked to ensure the PER register
synchronization is complete.
Bit
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
PER[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 7:0 – PER[7:0] Period Value
These bits hold the value of the TC period count.
Note: Updates to the PER register are not possible with the DMA while in Standby mode.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 568
PIC32CM MC00 Family
Timer Counter (TC)
33.7.15 Channel x Compare/Capture Value, 8-bit Mode
Name:
Offset:
Reset:
Property:
CCx
0x1C + x*0x01 [x=0..1]
0x00
Write-Synchronized, Read-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCx register
synchronization is complete.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CC[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – CC[7:0] Channel x Compare/Capture Value
These bits contain the compare/capture value in 8-bit TC mode. In Match frequency (MFRQ) or Match PWM
(MPWM) waveform operation (WAVE.WAVEGEN), the CC0 register is used as a period register.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 569
PIC32CM MC00 Family
Timer Counter (TC)
33.7.16 Period Buffer Value, 8-bit Mode
Name:
Offset:
Reset:
Property:
PERBUF
0x2F
0xFF
Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.PER must be checked to ensure the PER register
synchronization is complete.
Bit
Access
Reset
7
6
5
R/W
1
R/W
1
R/W
1
4
3
PERBUF[7:0]
R/W
R/W
1
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 7:0 – PERBUF[7:0] Period Buffer Value
These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE condition.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 570
PIC32CM MC00 Family
Timer Counter (TC)
33.7.17 Channel x Compare Buffer Value, 8-bit Mode
Name:
Offset:
Reset:
Property:
CCBUFx
0x30 + x*0x01 [x=0..1]
0x00
Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCx register
synchronization is complete.
Bit
Access
Reset
7
6
5
R/W
0
R/W
0
R/W
0
4
3
CCBUF[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – CCBUF[7:0] Channel x Compare Buffer Value
These bits hold the value of the Channel x Compare Buffer Value. When the buffer valid flag is '1' and double
buffering is enabled (CTRLBCLR.LUPD=1), the data from buffer registers will be copied into the corresponding CCx
register under UPDATE condition, including the software update command (CTRLBSET.CMD=0x3).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 571
PIC32CM MC00 Family
Timer Counter (TC)
33.8
Register Summary - 16-bit Mode
Offset
Name
0x00
CTRLA
0x04
0x05
CTRLBCLR
CTRLBSET
0x06
EVCTRL
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
INTENCLR
INTENSET
INTFLAG
STATUS
WAVE
DRVCTRL
Reserved
DBGCTRL
0x10
SYNCBUSY
0x14
COUNT
0x16
...
0x1B
Reserved
0x1C
CC0
0x1E
CC1
0x20
...
0x2F
Reserved
0x30
CCBUF0
0x32
CCBUF1
Bit Pos.
7:0
15:8
23:16
31:24
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
23:16
31:24
7:0
15:8
7
ONDEMAND RUNSTDBY
5
4
3
PRESCSYNC[1:0]
CC1
CC0
2
1
0
MODE[1:0]
ALOCK
COPEN1
COPEN0
CAPTMODE1[1:0]
TCEI
MCEO1
MC1
MC1
MC1
CCBUFV1
TCINV
MCEO0
MC0
MC0
MC0
CCBUFV0
CMD[2:0]
CMD[2:0]
COUNT
STATUS
ENABLE
SWRST
PRESCALER[2:0]
CAPTEN1
CAPTEN0
CAPTMODE0[1:0]
ONESHOT
LUPD
DIR
ONESHOT
LUPD
DIR
EVACT[2:0]
OVFEO
ERR
OVF
ERR
OVF
ERR
OVF
SLAVE
STOP
WAVEGEN[1:0]
INVEN1
INVEN0
CTRLB
ENABLE
DBGRUN
SWRST
COUNT[7:0]
COUNT[15:8]
7:0
15:8
7:0
15:8
CC[7:0]
CC[15:8]
CC[7:0]
CC[15:8]
7:0
15:8
7:0
15:8
CCBUF[7:0]
CCBUF[15:8]
CCBUF[7:0]
CCBUF[15:8]
© 2021 Microchip Technology Inc.
and its subsidiaries
6
Datasheet
DS60001638D-page 572
PIC32CM MC00 Family
Timer Counter (TC)
33.8.1
Control A
Name:
Offset:
Reset:
Property:
Bit
CTRLA
0x00
0x00000000
PAC Write-Protection, Write-Synchronized Bits, Enable-Protected Bits
31
30
29
23
22
21
COPEN1
R/W
0
20
COPEN0
R/W
0
19
18
17
CAPTEN1
R/W
0
16
CAPTEN0
R/W
0
15
14
13
12
11
ALOCK
R/W
0
10
8
R/W
0
9
PRESCALER[2:0]
R/W
0
R/W
0
3
2
1
ENABLE
R/W
0
0
SWRST
W
0
Access
Reset
Bit
Access
Reset
Bit
28
27
CAPTMODE1[1:0]
R/W
R/W
0
0
Access
Reset
Bit
Access
Reset
7
ONDEMAND
R/W
0
6
RUNSTDBY
R/W
0
5
4
PRESCSYNC[1:0]
R/W
R/W
0
0
26
MODE[1:0]
R/W
0
R/W
0
25
24
CAPTMODE0[1:0]
R/W
R/W
0
0
Bits 28:27 – CAPTMODE1[1:0] Capture mode Channel 1
These bits select the channel 1 capture mode.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
Name
DEFAULT
CAPTMIN
CAPTMAX
Description
Default capture
Minimum capture
Maximum capture
Reserved
Bits 25:24 – CAPTMODE0[1:0] Capture mode Channel 0
These bits select the channel 0 capture mode.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
Name
DEFAULT
CAPTMIN
CAPTMAX
Description
Default capture
Minimum capture
Maximum capture
Reserved
Bits 20, 21 – COPENx Capture On Pin x Enable [x = 1..0]
Bit x of COPEN[1:0] selects the trigger source for capture operation, either events or I/O pin input.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
Event from Event System is selected as trigger source for capture operation on channel x.
I/O pin is selected as trigger source for capture operation on channel x.
Bits 16, 17 – CAPTENx Capture Channel x Enable [x = 1..0]
Bit x of CAPTEN[1:0] selects whether channel x is a capture or a compare channel.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 573
PIC32CM MC00 Family
Timer Counter (TC)
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
CAPTEN disables capture on channel x.
CAPTEN enables capture on channel x.
Bit 11 – ALOCK Auto Lock
When this bit is set, Lock bit update (LUPD) is set to '1' on each overflow/underflow or re-trigger event.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
The LUPD bit is not affected on overflow/underflow, and re-trigger event.
The LUPD bit is set on each overflow/underflow or re-trigger event.
Bits 10:8 – PRESCALER[2:0] Prescaler
These bits select the counter prescaler factor.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
DIV1
DIV2
DIV4
DIV8
DIV16
DIV64
DIV256
DIV1024
Description
Prescaler: GCLK_TC
Prescaler: GCLK_TC/2
Prescaler: GCLK_TC/4
Prescaler: GCLK_TC/8
Prescaler: GCLK_TC/16
Prescaler: GCLK_TC/64
Prescaler: GCLK_TC/256
Prescaler: GCLK_TC/1024
Bit 7 – ONDEMAND Clock On Demand
This bit selects the clock requirements when the TC is stopped.
In Standby mode, if the Run in Standby bit (CTRLA.RUNSTDBY) is '0', ONDEMAND is forced to '0'.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
The On Demand is disabled. If On Demand is disabled, the TC will continue to request the clock when
its operation is stopped (STATUS.STOP=1).
The On Demand is enabled. When On Demand is enabled, the stopped TC will not request the
clock. The clock is requested when a software re-trigger command is applied or when an event with
start/re-trigger action is detected.
Bit 6 – RUNSTDBY Run in Standby
This bit is used to keep the TC running in standby mode.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
The TC is halted in standby.
The TC continues to run in standby.
Bits 5:4 – PRESCSYNC[1:0] Prescaler and Counter Synchronization
These bits select whether the counter should wrap around on the next GCLK_TCx clock or the next prescaled
GCLK_TCx clock. It also makes it possible to reset the prescaler.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
Name
GCLK
PRESC
RESYNC
-
Description
Reload or reset the counter on next generic clock
Reload or reset the counter on next prescaler clock
Reload or reset the counter on next generic clock. Reset the prescaler counter
Reserved
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 574
PIC32CM MC00 Family
Timer Counter (TC)
Bits 3:2 – MODE[1:0] Timer Counter Mode
These bits select the counter mode.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
Name
COUNT16
COUNT8
COUNT32
-
Description
Counter in 16-bit mode
Counter in 8-bit mode
Counter in 32-bit mode
Reserved
Bit 1 – ENABLE Enable
Notes:
1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
2. This bit is not enable protected.
Value
0
1
Description
The peripheral is disabled.
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be
disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be
discarded.
Notes:
1. This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST
synchronization is complete.
2. This bit is not enable protected.
Value
0
1
Description
There is no reset operation ongoing.
The reset operation is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 575
PIC32CM MC00 Family
Timer Counter (TC)
33.8.2
Control B Clear
Name:
Offset:
Reset:
Property:
CTRLBCLR
0x04
0x00
PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Set register (CTRLBSET).
Note: This register is read- and write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the
CTRLBCLR register synchronization is complete.
Bit
Access
Reset
7
R/W
0
6
CMD[2:0]
R/W
0
5
4
3
R/W
0
2
ONESHOT
R/W
0
1
LUPD
R/W
0
0
DIR
R/W
0
Bits 7:5 – CMD[2:0] Command
These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC
clock cycle. When a command has been executed, the CMD bit group will be read back as zero.
Writing 0x0 to these bits has no effect.
Writing a value different from 0x0 to this bit field bits will clear the pending command.
Bit 2 – ONESHOT One-Shot on Counter
This bit controls one-shot operation of the TC.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will disable one-shot operation.
Value
Description
0
The TC will wrap around and continue counting on an overflow/underflow condition.
1
The TC will wrap around and stop on the next underflow/overflow condition.
Bit 1 – LUPD Lock Update
This bit controls the update operation of the TC buffered registers.
When CTRLB.LUPD is set, no any update of the registers with value of its buffered register is performed on hardware
UPDATE condition. Locking the update ensures that all buffer registers are valid before an hardware update is
performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked.
This bit has no effect when input capture operation is enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the LUPD bit.
Value
Description
0
The CCBUFx and PERBUF buffer registers value are copied into CCx and PER registers on hardware
update condition.
1
The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on
hardware update condition.
Bit 0 – DIR Counter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the bit and make the counter count up.
Value
Description
0
The timer/counter is counting up (incrementing).
1
The timer/counter is counting down (decrementing).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 576
PIC32CM MC00 Family
Timer Counter (TC)
33.8.3
Control B Set
Name:
Offset:
Reset:
Property:
CTRLBSET
0x05
0x00
PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Clear register (CTRLBCLR).
Note: This register is read- and write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the
CTRLBSET register synchronization is complete.
Bit
Access
Reset
7
6
CMD[2:0]
R/W
0
R/W
0
5
4
3
R/W
0
2
ONESHOT
R/W
0
1
LUPD
R/W
0
0
DIR
R/W
0
Bits 7:5 – CMD[2:0] Command
These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC
clock cycle. When a command has been executed, the CMD bit group will be read back as zero.
Writing 0x0 to these bits has no effect.
Writing a value different from 0x0 to these bits will issue a command for execution.
Important: This command requires synchronization before being executed. A valid sequence is:
• Issue CMD command (CTRLBSET.CMD = command)
• Wait for CMD synchronization (SYNCBUSY.CTRLB = 0)
• Wait for CMD read back as zero (CTRLBSET.CMD = 0)
Value
0x0
0x1
0x2
0x3
0x4
Name
NONE
RETRIGGER
STOP
UPDATE
READSYNC
Description
No action
Force a start, restart or retrigger
Force a stop
Force update of double buffered registers
Force a read synchronization of COUNT
Bit 2 – ONESHOT One-Shot on Counter
This bit controls one-shot operation of the TC.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will enable one-shot operation.
Value
Description
0
The TC will wrap around and continue counting on an overflow/underflow condition.
1
The TC will wrap around and stop on the next underflow/overflow condition.
Bit 1 – LUPD Lock Update
This bit controls the update operation of the TC buffered registers.
When CTRLB.LUPD is set, no any update of the registers with value of its buffered register is performed on hardware
UPDATE condition. Locking the update ensures that all buffer registers are valid before an hardware update is
performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the LUPD bit.
This bit has no effect when input capture operation is enabled.
Value
Description
0
The CCBUFx and PERBUF buffer registers value are copied into CCx and PER registers on hardware
update condition.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 577
PIC32CM MC00 Family
Timer Counter (TC)
Value
1
Description
The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on
hardware update condition.
Bit 0 – DIR Counter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will set the bit and make the counter count down.
Value
Description
0
The timer/counter is counting up (incrementing).
1
The timer/counter is counting down (decrementing).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 578
PIC32CM MC00 Family
Timer Counter (TC)
33.8.4
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x06
0x0000
PAC Write-Protection, Enable-Protected
15
14
13
MCEO1
R/W
0
12
MCEO0
R/W
0
11
10
9
8
OVFEO
R/W
0
7
6
5
TCEI
R/W
0
4
TCINV
R/W
0
3
2
1
EVACT[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
Bits 12, 13 – MCEOx Match or Capture Channel x Event Output Enable [x = 1..0]
These bits enable the generation of an event for every match or capture on channel x.
Value
Description
0
Match/Capture event on channel x is disabled and will not be generated.
1
Match/Capture event on channel x is enabled and will be generated for every compare/capture.
Bit 8 – OVFEO Overflow/Underflow Event Output Enable
This bit enables the Overflow/Underflow event. When enabled, an event will be generated when the counter
overflows/underflows.
Value
Description
0
Overflow/Underflow event is disabled and will not be generated.
1
Overflow/Underflow event is enabled and will be generated for every counter overflow/underflow.
Bit 5 – TCEI TC Event Enable
This bit is used to enable asynchronous input events to the TC.
Value
Description
0
Incoming events are disabled.
1
Incoming events are enabled.
Bit 4 – TCINV TC Inverted Event Input Polarity
This bit inverts the asynchronous input event source.
Value
Description
0
Input event source is not inverted.
1
Input event source is inverted.
Bits 2:0 – EVACT[2:0] Event Action
These bits define the event action the TC will perform on an event.
Value
Name
Description
0x0
OFF
Event action disabled
0x1
RETRIGGER
Start, restart or retrigger TC on event
0x2
COUNT
Count on event (not a valid selection for waveform generation)
0x3
START
Start TC on event
0x4
STAMP
Time stamp capture
0x5
PPW
Period captured in CC0, pulse width in CC1
0x6
PWP
Period captured in CC1, pulse width in CC0
0x7
PW
Pulse width capture
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 579
PIC32CM MC00 Family
Timer Counter (TC)
33.8.5
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x08
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
6
Access
Reset
5
MC1
R/W
0
4
MC0
R/W
0
3
2
1
ERR
R/W
0
0
OVF
R/W
0
Bits 4, 5 – MCx Match or Capture Channel x Interrupt Disable [x = 1..0]
Writing a '0' to these bits has no effect.
Writing a '1' to MCx will clear the corresponding Match or Capture Channel x Interrupt Enable bit, which disables the
Match or Capture Channel x interrupt.
Value
Description
0
The Match or Capture Channel x interrupt is disabled.
1
The Match or Capture Channel x interrupt is enabled.
Bit 1 – ERR Error Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
The Error interrupt is disabled.
1
The Error interrupt is enabled.
Bit 0 – OVF Overflow Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt request.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 580
PIC32CM MC00 Family
Timer Counter (TC)
33.8.6
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x09
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
7
6
Access
Reset
5
MC1
R/W
0
4
MC0
R/W
0
3
2
1
ERR
R/W
0
0
OVF
R/W
0
Bits 4, 5 – MCx Match or Capture Channel x Interrupt Enable [x = 1..0]
Writing a '0' to these bits has no effect.
Writing a '1' to MCx will set the corresponding Match or Capture Channel x Interrupt Enable bit, which enables the
Match or Capture Channel x interrupt.
Value
Description
0
The Match or Capture Channel x interrupt is disabled.
1
The Match or Capture Channel x interrupt is enabled.
Bit 1 – ERR Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
The Error interrupt is disabled.
1
The Error interrupt is enabled.
Bit 0 – OVF Overflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt request.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 581
PIC32CM MC00 Family
Timer Counter (TC)
33.8.7
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAG
0x0A
0x00
-
6
Access
Reset
5
MC1
R/W
0
4
MC0
R/W
0
3
2
1
ERR
R/W
0
0
OVF
R/W
0
Bits 4, 5 – MCx Match or Capture Channel x Interrupt Flag [x = 1..0]
This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture value. This
flag will generate an interrupt request if the corresponding INTENCLR.MCx or INTENSET.MCx bit is '1'.
Writing a '0' to one of these bits has no effect.
Writing a '1' to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag.
In capture operation, this flag is automatically cleared when CCx register is read.
Bit 1 – ERR Error Interrupt Flag
This flag is set when a new capture occurs on a channel while the corresponding Match or Capture Channel x
interrupt flag is set, in which case there is nowhere to store the new capture.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Error interrupt flag.
Bit 0 – OVF Overflow Interrupt Flag
This flag is set after an overflow condition occurs, and will generate an interrupt request if INTENCLR.OVF or
INTENSET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 582
PIC32CM MC00 Family
Timer Counter (TC)
33.8.8
Status
Name:
Offset:
Reset:
Property:
STATUS
0x0B
0x01
Read-Synchronized, Write-Synchronized
Note: This register is read- and write-synchronized: SYNCBUSY.STATUS must be checked to ensure the STATUS
register synchronization is complete.
Bit
7
6
Access
Reset
5
CCBUFV1
R/W
0
4
CCBUFV0
R/W
0
3
2
1
SLAVE
R/W
0
0
STOP
R
1
Bits 4, 5 – CCBUFVx Channel x Compare or Capture Buffer Valid
For a compare channel x, the bit x is set when a new value is written to the corresponding CCBUFx register.
The bit x is cleared by writing a '1' to it when CTRLB.LUPD is set, or it is cleared automatically by hardware on
UPDATE condition. If clearing this bit manually to force an update of the CCx register, it is necessary to clear the bit
two times successively.
For a capture channel x, the bit x is set when a valid capture value is stored in the CCBUFx register. The bit x is
cleared automatically when the CCx register is read.
Bit 1 – SLAVE Client Status Flag
This bit is only available in 32-bit mode on the Client TC (i.e., TC1 and/or TC3). The bit is set when the associated
host TC (TC0 and TC2, respectively) is set to run in 32-bit mode.
Bit 0 – STOP Stop Status Flag
This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when the
One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is '1'.
Value
Description
0
Counter is running.
1
Counter is stopped.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 583
PIC32CM MC00 Family
Timer Counter (TC)
33.8.9
Waveform Generation Control
Name:
Offset:
Reset:
Property:
Bit
WAVE
0x0C
0x00
PAC Write-Protection, Enable-Protected
7
6
5
4
3
2
Access
Reset
1
0
WAVEGEN[1:0]
R/W
R/W
0
0
Bits 1:0 – WAVEGEN[1:0] Waveform Generation Mode
These bits select the waveform generation operation. They affect the top value, as shown in 33.6.2.6.1 Waveform
Output Operations. They also control whether frequency or PWM waveform generation should be used. The
waveform generation operations are explained in 33.6.2.6.1 Waveform Output Operations.
Note: This bit field is not synchronized.
Value
Name
Operation
Top Value
Output Waveform
on Match
Output Waveform
on Wraparound
0x0
0x1
0x2
0x3
NFRQ
MFRQ
NPWM
MPWM
Normal frequency
Match frequency
Normal PWM
Match PWM
PER(1)/Max.
CC0
PER(1)/Max.
CC0
Toggle
Toggle
Set
Set
No action
Toggle
Clear
Clear
1) This depends on the TC mode: In 8-bit mode, the top value is the Period Value register (PER). In 16-bit and 32-bit
mode it is the respective Max. value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 584
PIC32CM MC00 Family
Timer Counter (TC)
33.8.10 Driver Control
Name:
Offset:
Reset:
Property:
Bit
DRVCTRL
0x0D
0x00
PAC Write-Protection, Enable-Protected
7
6
5
4
3
2
Access
Reset
1
INVEN1
R/W
0
0
INVEN0
R/W
0
Bits 0, 1 – INVENx Output Waveform x Invert Enable [x = 1..0]
The INVENx bit selects inversion of the output or capture trigger input of channel x.
Value
Description
0
Disable inversion of the WO[x] output and IO input pin.
1
Enable inversion of the WO[x] output and IO input pin.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 585
PIC32CM MC00 Family
Timer Counter (TC)
33.8.11 Debug Control
Name:
Offset:
Reset:
Property:
Bit
DBGCTRL
0x0F
0x00
PAC Write-Protection
7
6
5
4
3
Access
Reset
2
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Run in Debug Mode
This bit is affected by a software system Reset, and should not be changed by software while the TC is enabled.
Value
Description
0
The TC is halted when the device is halted in debug mode.
1
The TC continues normal operation when the device is halted in debug mode.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 586
PIC32CM MC00 Family
Timer Counter (TC)
33.8.12 Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x10
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
CC1
R
0
6
CC0
R
0
5
4
COUNT
R
0
3
STATUS
R
0
2
CTRLB
R
0
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 6, 7 – CCx Compare/Capture Channel x Synchronization Busy [x = 1..0]
For details on CC channels number, refer to each TC feature list.
This bit is set when the synchronization of CCx between clock domains is started.
This bit is also set when the CCBUFx is written, and cleared on update condition. The bit is automatically cleared
when the STATUS.CCBUFx bit is cleared.
This bit is cleared when the synchronization of CCx between the clock domains is complete.
Bit 4 – COUNT COUNT Synchronization Busy
This bit is cleared when the synchronization of COUNT between the clock domains is complete.
This bit is set when the synchronization of COUNT between clock domains is started.
Bit 3 – STATUS STATUS Synchronization Busy
This bit is cleared when the synchronization of STATUS between the clock domains is complete.
This bit is set when a '1' is written to the Capture Channel Buffer Valid status flags (STATUS.CCBUFVx) and the
synchronization of STATUS between clock domains is started.
Bit 2 – CTRLB CTRLB Synchronization Busy
This bit is cleared when the synchronization of CTRLBSET or CTRLBCLR between the clock domains is complete.
This bit is set when the synchronization of CTRLBSET or CTRLBCLR between clock domains is started.
Bit 1 – ENABLE ENABLE Synchronization Busy
This bit is cleared when the synchronization of ENABLE bit between the clock domains is complete.
This bit is set when the synchronization of ENABLE bit between clock domains is started.
Bit 0 – SWRST SWRST Synchronization Busy
This bit is cleared when the synchronization of SWRST bit between the clock domains is complete.
This bit is set when the synchronization of SWRST bit between clock domains is started.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 587
PIC32CM MC00 Family
Timer Counter (TC)
33.8.13 Counter Value, 16-bit Mode
Name:
Offset:
Reset:
Property:
COUNT
0x14
0x00
PAC Write-Protection, Write-Synchronized, Read-Synchronized
Notes:
1. This register is read-synchronized: prior to any read access, this register must be synchronized by user by
writing the according TC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC).
2. This register is write-synchronized: SYNCBUSY.COUNT must be checked to ensure the COUNT register
synchronization is complete.
Bit
Access
Reset
Bit
Access
Reset
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
COUNT[15:8]
R/W
R/W
0
0
4
3
COUNT[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – COUNT[15:0] Counter Value
These bits contain the current counter value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 588
PIC32CM MC00 Family
Timer Counter (TC)
33.8.14 Channel x Compare/Capture Value, 16-bit Mode
Name:
Offset:
Reset:
Property:
CCx
0x1C + x*0x02 [x=0..1]
0x0000
Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCx register
synchronization is complete.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CC[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CC[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CC[15:0] Channel x Compare/Capture Value
These bits contain the compare/capture value in 16-bit TC mode. In Match frequency (MFRQ) or Match PWM
(MPWM) waveform operation (WAVE.WAVEGEN), the CC0 register is used as a period register.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 589
PIC32CM MC00 Family
Timer Counter (TC)
33.8.15 Channel x Compare Buffer Value, 16-bit Mode
Name:
Offset:
Reset:
Property:
CCBUFx
0x30 + x*0x02 [x=0..1]
0x0000
Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCx register
synchronization is complete.
Bit
Access
Reset
Bit
Access
Reset
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
CCBUF[15:8]
R/W
R/W
0
0
4
3
CCBUF[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CCBUF[15:0] Channel x Compare Buffer Value
These bits hold the value of the Channel x Compare Buffer Value. When the buffer valid flag is '1' and double
buffering is enabled (CTRLBCLR.LUPD=1), the data from buffer registers will be copied into the corresponding CCx
register under UPDATE condition, including the software update command (CTRLBSET.CMD=0x3).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 590
PIC32CM MC00 Family
Timer Counter (TC)
33.9
Register Summary - 32-bit Mode
Offset
Name
0x00
CTRLA
0x04
0x05
CTRLBCLR
CTRLBSET
0x06
EVCTRL
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
INTENCLR
INTENSET
INTFLAG
STATUS
WAVE
DRVCTRL
Reserved
DBGCTRL
0x10
Bit Pos.
SYNCBUSY
0x14
COUNT
0x18
...
0x1B
Reserved
0x1C
CC0
0x20
CC1
0x24
...
0x2F
Reserved
0x30
CCBUF0
0x34
CCBUF1
7:0
15:8
23:16
31:24
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7
ONDEMAND RUNSTDBY
5
4
3
PRESCSYNC[1:0]
CC1
CC0
2
1
0
MODE[1:0]
ALOCK
COPEN1
COPEN0
CAPTMODE1[1:0]
TCEI
MCEO1
MC1
MC1
MC1
CCBUFV1
TCINV
MCEO0
MC0
MC0
MC0
CCBUFV0
CMD[2:0]
CMD[2:0]
COUNT
STATUS
ENABLE
SWRST
PRESCALER[2:0]
CAPTEN1
CAPTEN0
CAPTMODE0[1:0]
ONESHOT
LUPD
DIR
ONESHOT
LUPD
DIR
EVACT[2:0]
OVFEO
ERR
OVF
ERR
OVF
ERR
OVF
SLAVE
STOP
WAVEGEN[1:0]
INVEN1
INVEN0
CTRLB
ENABLE
DBGRUN
SWRST
COUNT[7:0]
COUNT[15:8]
COUNT[23:16]
COUNT[31:24]
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
CC[7:0]
CC[15:8]
CC[23:16]
CC[31:24]
CC[7:0]
CC[15:8]
CC[23:16]
CC[31:24]
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
CCBUF[7:0]
CCBUF[15:8]
CCBUF[23:16]
CCBUF[31:24]
CCBUF[7:0]
CCBUF[15:8]
CCBUF[23:16]
CCBUF[31:24]
© 2021 Microchip Technology Inc.
and its subsidiaries
6
Datasheet
DS60001638D-page 591
PIC32CM MC00 Family
Timer Counter (TC)
33.9.1
Control A
Name:
Offset:
Reset:
Property:
Bit
CTRLA
0x00
0x00000000
PAC Write-Protection, Write-Synchronized Bits, Enable-Protected Bits
31
30
29
23
22
21
COPEN1
R/W
0
20
COPEN0
R/W
0
19
18
17
CAPTEN1
R/W
0
16
CAPTEN0
R/W
0
15
14
13
12
11
ALOCK
R/W
0
10
8
R/W
0
9
PRESCALER[2:0]
R/W
0
R/W
0
3
2
1
ENABLE
R/W
0
0
SWRST
W
0
Access
Reset
Bit
Access
Reset
Bit
28
27
CAPTMODE1[1:0]
R/W
R/W
0
0
Access
Reset
Bit
Access
Reset
7
ONDEMAND
R/W
0
6
RUNSTDBY
R/W
0
5
4
PRESCSYNC[1:0]
R/W
R/W
0
0
26
MODE[1:0]
R/W
0
R/W
0
25
24
CAPTMODE0[1:0]
R/W
R/W
0
0
Bits 28:27 – CAPTMODE1[1:0] Capture mode Channel 1
These bits select the channel 1 capture mode.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
Name
DEFAULT
CAPTMIN
CAPTMAX
Description
Default capture
Minimum capture
Maximum capture
Reserved
Bits 25:24 – CAPTMODE0[1:0] Capture mode Channel 0
These bits select the channel 0 capture mode.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
Name
DEFAULT
CAPTMIN
CAPTMAX
Description
Default capture
Minimum capture
Maximum capture
Reserved
Bits 20, 21 – COPENx Capture On Pin x Enable [x = 1..0]
Bit x of COPEN[1:0] selects the trigger source for capture operation, either events or I/O pin input.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
Event from Event System is selected as trigger source for capture operation on channel x.
I/O pin is selected as trigger source for capture operation on channel x.
Bits 16, 17 – CAPTENx Capture Channel x Enable [x = 1..0]
Bit x of CAPTEN[1:0] selects whether channel x is a capture or a compare channel.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 592
PIC32CM MC00 Family
Timer Counter (TC)
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
CAPTEN disables capture on channel x.
CAPTEN enables capture on channel x.
Bit 11 – ALOCK Auto Lock
When this bit is set, Lock bit update (LUPD) is set to '1' on each overflow/underflow or re-trigger event.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
The LUPD bit is not affected on overflow/underflow, and re-trigger event.
The LUPD bit is set on each overflow/underflow or re-trigger event.
Bits 10:8 – PRESCALER[2:0] Prescaler
These bits select the counter prescaler factor.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
DIV1
DIV2
DIV4
DIV8
DIV16
DIV64
DIV256
DIV1024
Description
Prescaler: GCLK_TC
Prescaler: GCLK_TC/2
Prescaler: GCLK_TC/4
Prescaler: GCLK_TC/8
Prescaler: GCLK_TC/16
Prescaler: GCLK_TC/64
Prescaler: GCLK_TC/256
Prescaler: GCLK_TC/1024
Bit 7 – ONDEMAND Clock On Demand
This bit selects the clock requirements when the TC is stopped.
In standby mode, if the Run in Standby bit (CTRLA.RUNSTDBY) is '0', ONDEMAND is forced to '0'.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
The On Demand is disabled. If On Demand is disabled, the TC will continue to request the clock when
its operation is stopped (STATUS.STOP=1).
The On Demand is enabled. When On Demand is enabled, the stopped TC will not request the
clock. The clock is requested when a software re-trigger command is applied or when an event with
start/re-trigger action is detected.
Bit 6 – RUNSTDBY Run in Standby
This bit is used to keep the TC running in standby mode.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
The TC is halted in standby.
The TC continues to run in standby.
Bits 5:4 – PRESCSYNC[1:0] Prescaler and Counter Synchronization
These bits select whether the counter should wrap around on the next GCLK_TCx clock or the next prescaled
GCLK_TCx clock. It also makes it possible to reset the prescaler.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
Name
GCLK
PRESC
RESYNC
-
Description
Reload or reset the counter on next generic clock
Reload or reset the counter on next prescaler clock
Reload or reset the counter on next generic clock. Reset the prescaler counter
Reserved
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 593
PIC32CM MC00 Family
Timer Counter (TC)
Bits 3:2 – MODE[1:0] Timer Counter Mode
These bits select the counter mode.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
0x3
Name
COUNT16
COUNT8
COUNT32
-
Description
Counter in 16-bit mode
Counter in 8-bit mode
Counter in 32-bit mode
Reserved
Bit 1 – ENABLE Enable
Notes:
1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
2. This bit is not enable protected.
Value
0
1
Description
The peripheral is disabled.
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be
disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be
discarded.
Notes:
1. This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST
synchronization is complete.
2. This bit is not enable protected.
Value
0
1
Description
There is no reset operation ongoing.
The reset operation is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 594
PIC32CM MC00 Family
Timer Counter (TC)
33.9.2
Control B Clear
Name:
Offset:
Reset:
Property:
CTRLBCLR
0x04
0x00
PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Set register (CTRLBSET).
Note: This register is read- and write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the
CTRLBCLR register synchronization is complete.
Bit
Access
Reset
7
R/W
0
6
CMD[2:0]
R/W
0
5
4
3
R/W
0
2
ONESHOT
R/W
0
1
LUPD
R/W
0
0
DIR
R/W
0
Bits 7:5 – CMD[2:0] Command
These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC
clock cycle. When a command has been executed, the CMD bit group will be read back as zero.
Writing 0x0 to these bits has no effect.
Writing a value different from 0x0 to this bit field bits will clear the pending command.
Bit 2 – ONESHOT One-Shot on Counter
This bit controls one-shot operation of the TC.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will disable one-shot operation.
Value
Description
0
The TC will wrap around and continue counting on an overflow/underflow condition.
1
The TC will wrap around and stop on the next underflow/overflow condition.
Bit 1 – LUPD Lock Update
This bit controls the update operation of the TC buffered registers.
When CTRLB.LUPD is set, no any update of the registers with value of its buffered register is performed on hardware
UPDATE condition. Locking the update ensures that all buffer registers are valid before an hardware update is
performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked.
This bit has no effect when input capture operation is enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the LUPD bit.
Value
Description
0
The CCBUFx and PERBUF buffer registers value are copied into CCx and PER registers on hardware
update condition.
1
The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on
hardware update condition.
Bit 0 – DIR Counter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the bit and make the counter count up.
Value
Description
0
The timer/counter is counting up (incrementing).
1
The timer/counter is counting down (decrementing).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 595
PIC32CM MC00 Family
Timer Counter (TC)
33.9.3
Control B Set
Name:
Offset:
Reset:
Property:
CTRLBSET
0x05
0x00
PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Clear register (CTRLBCLR).
Note: This register is read- and write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the
CTRLBSET register synchronization is complete.
Bit
Access
Reset
7
6
CMD[2:0]
R/W
0
R/W
0
5
4
3
R/W
0
2
ONESHOT
R/W
0
1
LUPD
R/W
0
0
DIR
R/W
0
Bits 7:5 – CMD[2:0] Command
These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC
clock cycle. When a command has been executed, the CMD bit group will be read back as zero.
Writing 0x0 to these bits has no effect.
Writing a value different from 0x0 to these bits will issue a command for execution.
Important: This command requires synchronization before being executed. A valid sequence is:
• Issue CMD command (CTRLBSET.CMD = command)
• Wait for CMD synchronization (SYNCBUSY.CTRLB = 0)
• Wait for CMD read back as zero (CTRLBSET.CMD = 0)
Value
0x0
0x1
0x2
0x3
0x4
Name
NONE
RETRIGGER
STOP
UPDATE
READSYNC
Description
No action
Force a start, restart or retrigger
Force a stop
Force update of double buffered registers
Force a read synchronization of COUNT
Bit 2 – ONESHOT One-Shot on Counter
This bit controls one-shot operation of the TC.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will enable one-shot operation.
Value
Description
0
The TC will wrap around and continue counting on an overflow/underflow condition.
1
The TC will wrap around and stop on the next underflow/overflow condition.
Bit 1 – LUPD Lock Update
This bit controls the update operation of the TC buffered registers.
When CTRLB.LUPD is set, no any update of the registers with value of its buffered register is performed on hardware
UPDATE condition. Locking the update ensures that all buffer registers are valid before an hardware update is
performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the LUPD bit.
This bit has no effect when input capture operation is enabled.
Value
Description
0
The CCBUFx and PERBUF buffer registers value are copied into CCx and PER registers on hardware
update condition.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 596
PIC32CM MC00 Family
Timer Counter (TC)
Value
1
Description
The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on
hardware update condition.
Bit 0 – DIR Counter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will set the bit and make the counter count down.
Value
Description
0
The timer/counter is counting up (incrementing).
1
The timer/counter is counting down (decrementing).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 597
PIC32CM MC00 Family
Timer Counter (TC)
33.9.4
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x06
0x0000
PAC Write-Protection, Enable-Protected
15
14
13
MCEO1
R/W
0
12
MCEO0
R/W
0
11
10
9
8
OVFEO
R/W
0
7
6
5
TCEI
R/W
0
4
TCINV
R/W
0
3
2
1
EVACT[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
Bits 12, 13 – MCEOx Match or Capture Channel x Event Output Enable [x = 1..0]
These bits enable the generation of an event for every match or capture on channel x.
Value
Description
0
Match/Capture event on channel x is disabled and will not be generated.
1
Match/Capture event on channel x is enabled and will be generated for every compare/capture.
Bit 8 – OVFEO Overflow/Underflow Event Output Enable
This bit enables the Overflow/Underflow event. When enabled, an event will be generated when the counter
overflows/underflows.
Value
Description
0
Overflow/Underflow event is disabled and will not be generated.
1
Overflow/Underflow event is enabled and will be generated for every counter overflow/underflow.
Bit 5 – TCEI TC Event Enable
This bit is used to enable asynchronous input events to the TC.
Value
Description
0
Incoming events are disabled.
1
Incoming events are enabled.
Bit 4 – TCINV TC Inverted Event Input Polarity
This bit inverts the asynchronous input event source.
Value
Description
0
Input event source is not inverted.
1
Input event source is inverted.
Bits 2:0 – EVACT[2:0] Event Action
These bits define the event action the TC will perform on an event.
Value
Name
Description
0x0
OFF
Event action disabled
0x1
RETRIGGER
Start, restart or retrigger TC on event
0x2
COUNT
Count on event (not a valid selection for waveform generation)
0x3
START
Start TC on event
0x4
STAMP
Time stamp capture
0x5
PPW
Period captured in CC0, pulse width in CC1
0x6
PWP
Period captured in CC1, pulse width in CC0
0x7
PW
Pulse width capture
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 598
PIC32CM MC00 Family
Timer Counter (TC)
33.9.5
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x08
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
6
Access
Reset
5
MC1
R/W
0
4
MC0
R/W
0
3
2
1
ERR
R/W
0
0
OVF
R/W
0
Bits 4, 5 – MCx Match or Capture Channel x Interrupt Disable [x = 1..0]
Writing a '0' to these bits has no effect.
Writing a '1' to MCx will clear the corresponding Match or Capture Channel x Interrupt Enable bit, which disables the
Match or Capture Channel x interrupt.
Value
Description
0
The Match or Capture Channel x interrupt is disabled.
1
The Match or Capture Channel x interrupt is enabled.
Bit 1 – ERR Error Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
The Error interrupt is disabled.
1
The Error interrupt is enabled.
Bit 0 – OVF Overflow Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt request.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 599
PIC32CM MC00 Family
Timer Counter (TC)
33.9.6
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x09
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
7
6
Access
Reset
5
MC1
R/W
0
4
MC0
R/W
0
3
2
1
ERR
R/W
0
0
OVF
R/W
0
Bits 4, 5 – MCx Match or Capture Channel x Interrupt Enable [x = 1..0]
Writing a '0' to these bits has no effect.
Writing a '1' to MCx will set the corresponding Match or Capture Channel x Interrupt Enable bit, which enables the
Match or Capture Channel x interrupt.
Value
Description
0
The Match or Capture Channel x interrupt is disabled.
1
The Match or Capture Channel x interrupt is enabled.
Bit 1 – ERR Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
The Error interrupt is disabled.
1
The Error interrupt is enabled.
Bit 0 – OVF Overflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt request.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 600
PIC32CM MC00 Family
Timer Counter (TC)
33.9.7
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAG
0x0A
0x00
-
6
Access
Reset
5
MC1
R/W
0
4
MC0
R/W
0
3
2
1
ERR
R/W
0
0
OVF
R/W
0
Bits 4, 5 – MCx Match or Capture Channel x Interrupt Flag [x = 1..0]
This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture value. This
flag will generate an interrupt request if the corresponding INTENCLR.MCx or INTENSET.MCx bit is '1'.
Writing a '0' to one of these bits has no effect.
Writing a '1' to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag.
In capture operation, this flag is automatically cleared when CCx register is read.
Bit 1 – ERR Error Interrupt Flag
This flag is set when a new capture occurs on a channel while the corresponding Match or Capture Channel x
interrupt flag is set, in which case there is nowhere to store the new capture.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Error interrupt flag.
Bit 0 – OVF Overflow Interrupt Flag
This flag is set after an overflow condition occurs, and will generate an interrupt request if INTENCLR.OVF or
INTENSET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Timer Counter (TC)
33.9.8
Status
Name:
Offset:
Reset:
Property:
STATUS
0x0B
0x01
Read-Synchronized, Write-Synchronized
Note: This register is read- and write-synchronized: SYNCBUSY.STATUS must be checked to ensure the STATUS
register synchronization is complete.
Bit
7
6
Access
Reset
5
CCBUFV1
R/W
0
4
CCBUFV0
R/W
0
3
2
1
SLAVE
R/W
0
0
STOP
R
1
Bits 4, 5 – CCBUFVx Channel x Compare or Capture Buffer Valid
For a compare channel x, the bit x is set when a new value is written to the corresponding CCBUFx register.
The bit x is cleared by writing a '1' to it when CTRLB.LUPD is set, or it is cleared automatically by hardware on
UPDATE condition. If clearing this bit manually to force an update of the CCx register, it is necessary to clear the bit
two times successively.
For a capture channel x, the bit x is set when a valid capture value is stored in the CCBUFx register. The bit x is
cleared automatically when the CCx register is read.
Bit 1 – SLAVE Client Status Flag
This bit is only available in 32-bit mode on the client TC (i.e., TC1 and/or TC3). The bit is set when the associated
host TC (TC0 and TC2, respectively) is set to run in 32-bit mode.
Bit 0 – STOP Stop Status Flag
This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when the
One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is '1'.
Value
Description
0
Counter is running.
1
Counter is stopped.
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Datasheet
DS60001638D-page 602
PIC32CM MC00 Family
Timer Counter (TC)
33.9.9
Waveform Generation Control
Name:
Offset:
Reset:
Property:
Bit
WAVE
0x0C
0x00
PAC Write-Protection, Enable-Protected
7
6
5
4
3
2
Access
Reset
1
0
WAVEGEN[1:0]
R/W
R/W
0
0
Bits 1:0 – WAVEGEN[1:0] Waveform Generation Mode
These bits select the waveform generation operation. They affect the top value, as shown in 33.6.2.6.1 Waveform
Output Operations. They also control whether frequency or PWM waveform generation should be used. The
waveform generation operations are explained in 33.6.2.6.1 Waveform Output Operations.
Note: This bit field is not synchronized.
Value
Name
Operation
Top Value
Output Waveform
on Match
Output Waveform
on Wraparound
0x0
0x1
0x2
0x3
NFRQ
MFRQ
NPWM
MPWM
Normal frequency
Match frequency
Normal PWM
Match PWM
PER(1)/Max.
CC0
PER(1)/Max.
CC0
Toggle
Toggle
Set
Set
No action
Toggle
Clear
Clear
1) This depends on the TC mode: In 8-bit mode, the top value is the Period Value register (PER). In 16-bit and 32-bit
mode it is the respective Max. value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 603
PIC32CM MC00 Family
Timer Counter (TC)
33.9.10 Driver Control
Name:
Offset:
Reset:
Property:
Bit
DRVCTRL
0x0D
0x00
PAC Write-Protection, Enable-Protected
7
6
5
4
3
2
Access
Reset
1
INVEN1
R/W
0
0
INVEN0
R/W
0
Bits 0, 1 – INVENx Output Waveform x Invert Enable [x = 1..0]
The INVENx bit selects inversion of the output or capture trigger input of channel x.
Value
Description
0
Disable inversion of the WO[x] output and IO input pin.
1
Enable inversion of the WO[x] output and IO input pin.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 604
PIC32CM MC00 Family
Timer Counter (TC)
33.9.11 Debug Control
Name:
Offset:
Reset:
Property:
Bit
DBGCTRL
0x0F
0x00
PAC Write-Protection
7
6
5
4
3
Access
Reset
2
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Run in Debug Mode
This bit is affected by a software system Reset, and should not be changed by software while the TC is enabled.
Value
Description
0
The TC is halted when the device is halted in debug mode.
1
The TC continues normal operation when the device is halted in debug mode.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 605
PIC32CM MC00 Family
Timer Counter (TC)
33.9.12 Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x10
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
CC1
R
0
6
CC0
R
0
5
4
COUNT
R
0
3
STATUS
R
0
2
CTRLB
R
0
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 6, 7 – CCx Compare/Capture Channel x Synchronization Busy [x = 1..0]
For details on CC channels number, refer to each TC feature list.
This bit is set when the synchronization of CCx between clock domains is started.
This bit is also set when the CCBUFx is written, and cleared on update condition. The bit is automatically cleared
when the STATUS.CCBUFx bit is cleared.
This bit is cleared when the synchronization of CCx between the clock domains is complete.
Bit 4 – COUNT COUNT Synchronization Busy
This bit is cleared when the synchronization of COUNT between the clock domains is complete.
This bit is set when the synchronization of COUNT between clock domains is started.
Bit 3 – STATUS STATUS Synchronization Busy
This bit is cleared when the synchronization of STATUS between the clock domains is complete.
This bit is set when a '1' is written to the Capture Channel Buffer Valid status flags (STATUS.CCBUFVx) and the
synchronization of STATUS between clock domains is started.
Bit 2 – CTRLB CTRLB Synchronization Busy
This bit is cleared when the synchronization of CTRLBSET or CTRLBCLR between the clock domains is complete.
This bit is set when the synchronization of CTRLBSET or CTRLBCLR between clock domains is started.
Bit 1 – ENABLE ENABLE Synchronization Busy
This bit is cleared when the synchronization of ENABLE bit between the clock domains is complete.
This bit is set when the synchronization of ENABLE bit between clock domains is started.
Bit 0 – SWRST SWRST Synchronization Busy
This bit is cleared when the synchronization of SWRST bit between the clock domains is complete.
This bit is set when the synchronization of SWRST bit between clock domains is started.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 606
PIC32CM MC00 Family
Timer Counter (TC)
33.9.13 Counter Value, 32-bit Mode
Name:
Offset:
Reset:
Property:
COUNT
0x14
0x00000000
PAC Write-Protection, Write-Synchronized, Read-Synchronized
Notes:
1. This register is read-synchronized: prior to any read access, this register must be synchronized by user by
writing the according TC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC).
2. This register is write-synchronized: SYNCBUSY.COUNT must be checked to ensure the COUNT register
synchronization is complete.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
COUNT[31:24]
R/W
R/W
0
0
20
19
COUNT[23:16]
R/W
R/W
0
0
12
11
COUNT[15:8]
R/W
R/W
0
0
4
3
COUNT[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – COUNT[31:0] Counter Value
These bits contain the current counter value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 607
PIC32CM MC00 Family
Timer Counter (TC)
33.9.14 Channel x Compare/Capture Value, 32-bit Mode
Name:
Offset:
Reset:
Property:
CCx
0x1C + x*0x04 [x=0..1]
0x00000000
Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCx register
synchronization is complete.
Bit
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CC[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
CC[23:16]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
CC[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CC[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – CC[31:0] Channel x Compare/Capture Value
These bits contain the compare/capture value in 32-bit TC mode. In Match frequency (MFRQ) or Match PWM
(MPWM) waveform operation (WAVE.WAVEGEN), the CC0 register is used as a period register.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 608
PIC32CM MC00 Family
Timer Counter (TC)
33.9.15 Channel x Compare Buffer Value, 32-bit Mode
Name:
Offset:
Reset:
Property:
CCBUFx
0x30 + x*0x04 [x=0..1]
0x00000000
Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCx register
synchronization is complete.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
CCBUF[31:24]
R/W
R/W
0
0
20
19
CCBUF[23:16]
R/W
R/W
0
0
12
11
CCBUF[15:8]
R/W
R/W
0
0
4
3
CCBUF[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – CCBUF[31:0] Channel x Compare Buffer Value
These bits hold the value of the Channel x Compare Buffer Value. When the buffer valid flag is '1' and double
buffering is enabled (CTRLBCLR.LUPD=1), the data from buffer registers will be copied into the corresponding CCx
register under UPDATE condition, including the software update command (CTRLBSET.CMD=0x3).
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 609
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.
Timer/Counter for Control (TCC) Applications
34.1
Overview
The device provides three instances of the Timer/Counter for Control (TCC) applications peripheral, TCC[2:0].
Each TCC instance consists of a counter, a prescaler, compare/capture channels and control logic. The counter can
be set to count events or clock pulses. The counter together with the compare/capture channels can be configured
to time stamp input events, allowing capture of frequency and pulse-width. It can also perform waveform generation,
such as frequency generation and pulse-width modulation.
Waveform extensions are featured for motor control, ballast, LED, H-bridge, power converters, and other types of
power control applications. They allow for low-side and high-side output with optional dead-time insertion. Waveform
extensions can also generate a synchronized bit pattern across the waveform output pins. The fault options enable
fault protection for safe and deterministic handling, disabling and/or shut down of external drivers.
Note: The TCC configurations, such as channel numbers and features, may be reduced for some of the TCC
instances.
34.2
Features
•
•
•
•
•
•
•
•
Up to four compare/capture channels (CC) with:
– Double buffered period setting
– Double buffered compare or capture channel
– Circular buffer on period and compare channel registers
Waveform generation:
– Frequency generation
– Single-slope pulse-width modulation (PWM)
– Dual-slope PWM with half-cycle reload capability
Input capture:
– Event capture
– Frequency capture
– Pulse-width capture
Waveform extensions:
– Configurable distribution of compare channels outputs across port pins
– Low-side and high-side output with programmable dead-time insertion
– Waveform swap option with double buffer support
– Pattern generation with double buffer support
– Dithering support
Fault protection for safe disabling of drivers:
– Two recoverable fault sources
– Two non-recoverable fault sources
– Debugger can be a source of non-recoverable fault
Input events:
– Two input events (EVx) for counter
– One input event (MCx) for each channel
Output events:
– Three output events (Count, Re-Trigger and Overflow) are available for counter
– One Compare Match/Input Capture event output for each channel
Interrupts:
– Overflow and Re-Trigger interrupt
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 610
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
•
– Compare Match/Input Capture interrupt
– Interrupt on fault detection
– Counter cycle interrupt (INTFLAG.CNT)
– Error condition interrupt (INTFLAG.ERR)
Can be used with DMA and can trigger DMA transactions
Table 34-1. TCC Configuration Summary
TCC#
Channels
(CC_NUM)
Waveform
Output
(WO_NUM)
Counter size
Fault
Dithering
Output
matrix
Dead Time
Insertion
(DTI)
SWAP
Pattern
generation
0
4
8
24-bit
Yes
Yes
Yes
Yes
Yes
Yes
1
2
4
16-bit
Yes
Yes
2
2
2
16-bit
Yes
Yes
Note: The number of CC registers (CC_NUM) for each TCC corresponds to the number of compare/capture
channels, therefore a TCC can have more Waveform Outputs (WO_NUM) than CC registers.
34.3
Block Diagram
Figure 34-1. Timer/Counter for Control Applications - Block Diagram
Base Counter
PERBUFx
PER
Prescaler
"count"
"clear"
"load"
"direction"
Counter
COUNT
=
OVF (INT/Event/DMA Req.)
ERR (INT Req.)
Control Logic
TOP
BOTTOM
=0
"TCCx_EV0" (TCE0)
"TCCx_EV1" (TCE1)
"event"
UPDATE
BV
"TCCx_MCx"
Event
System
WO[7]
CCx
=
34.4
Waveform
Generation
Pattern
Generation
Control Logic
Dead-Time
Insertion
"capture"
Output
Matrix
CCBUFx
Recoverable
Faults
BV
SWAP
Compare/Capture
(Unit x = {0,1,…,3})
Non-recoverable
Faults
WO[6]
WO[5]
WO[4]
WO[3]
WO[2]
WO[1]
WO[0]
"match"
MCx (INT/Event/DMA Req.)
Signal Description
Pin Name
Type
Description
TCCx/WO[0]
Digital output
Compare channel 0 waveform output
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Datasheet
DS60001638D-page 611
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
...........continued
Pin Name
Type
Description
TCCx/WO[1]
Digital output
Compare channel 1 waveform output
…
...
...
TCCx/WO[WO_NUM-1]
Digital output
Compare channel n waveform output
Refer to the 4. Pinout and Packaging for details on the pin mapping for this peripheral. One signal can be mapped on
several pins.
34.5
Peripheral Dependencies
AHB CLK
APB CLK
Generic
CLK
PAC
Events
DMA
Sleep
Walking
Peripheral Base Address IRQ
Enabled at
reset
Enabled at
reset
Index
Index
Prot at
reset
User
Generator
Index
35: OVF
9-10: EV0-1
10: OVF
36: TRG
TCC0
0x42002400
13
-
N
23
9
N
Y
37: NT
11-14: MC0-3
11-14: MC0-3
38-41: MC0-3
42: OVF
15-16: EV0-1
15: OVF
43: TRG
TCC1
0x42002800
14
-
N
23
10
N
Y
44:CNT
17-18: MC0-1
16-17: MC0-1
45-46: MC0-1
47: OVF
19-20: EV0-1
18: OVF
48: TRG
TCC2
0x42002C00
15
-
N
24
11
N
Y
49: CNT
21-22: MC0-1
19-20: MC0-1
50-51 MC0-1
34.6
Functional Description
34.6.1
Principle of Operation
The following definitions are used throughout the documentation:
Table 34-2. Timer/Counter for Control Applications - Definitions
Name
Description
TOP
The counter reaches TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be the same as Period (PER) or the
Compare Channel 0 (CC0) register value depending on the waveform generator
mode in 34.6.2.5.1 Waveform Output Generation Operations.
ZERO
The counter reaches ZERO when it contains all zeroes.
MAX
The counter reaches maximum when it contains all ones.
UPDATE
The timer/counter signals an update when it reaches ZERO or TOP, depending
on the direction settings.
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Datasheet
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PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
...........continued
Name
Description
Timer
Increment / decrement / clear / reload steps are done on each prescaled clock.
Counter
Increment / decrement / clear / reload steps is done on each detected events.
CC
For compare operations, the CC are referred to as "compare channels."
For capture operations, the CC are referred to as "capture channels."
Each TCC instance has up to four compare/capture channels (CCx).
The counter register (COUNT), period registers with buffer (PER and PERBUF), and compare and capture registers
with buffers (CCx and CCBUFx) are 16- or 24-bit registers, depending on each TCC instance. Each buffer register
has a buffer valid (BUFV) flag that indicates when the buffer contains a new value.
Under normal operation, the counter value is continuously compared to the TOP or ZERO value to determine
whether the counter has reached TOP or ZERO. In either case, the TCC can generate interrupt requests, request
DMA transactions, or generate events for the Event System. In waveform generator mode, these comparisons are
used to set the waveform period or pulse alignment.
A prescaled generic clock (GCLK_TCCx) and events from the event system can be used to control the counter. The
event system is also used as a source to the input capture.
The Recoverable Fault Unit enables event controlled waveforms by acting directly on the generated waveforms of
the TCC compare channels output. These events can restart, halt the timer/counter period, shorten the output pulse
active time, or disable waveform output as long as the fault condition is present. This can typically be used for current
sensing regulation, and zero-crossing and demagnetization re-triggering.
The MCE0 and MCE1 asynchronous event sources are shared with the Recoverable Fault Unit. Only asynchronous
events are used internally when fault unit extension is enabled. For further details on how to configure asynchronous
events routing, refer to EVSYS – Event System.
Recoverable fault sources can be filtered and/or windowed to avoid false triggering, for example from I/O pin glitches,
by using digital filtering, input blanking, and qualification options. See also 34.6.3.5 Recoverable Faults.
In order to support applications with different types of motor control, ballast, LED, H-bridge, power converter, and
other types of power switching applications, the following independent units are implemented in some of the TCC
instances as optional and successive units:
• Recoverable faults and non-recoverable faults
• Output matrix
• Dead-time insertion
• Swap
• Pattern generation
• Dithering
See the TCC Block Diagram for more information.
The output matrix (OTMX) can distribute and route out the TCC waveform outputs across the port pins in different
configurations, each optimized for different application types. The Dead-Time Insertion (DTI) unit splits the four lower
OTMX outputs into two non-overlapping signals: the non-inverted low side (LS) and inverted high side (HS) of the
waveform output with optional dead-time insertion between LS and HS switching. The SWAP unit can swap the LS
and HS pin outputs, and can be used for fast decay motor control.
The pattern generation unit can be used to generate synchronized waveforms with constant logic level on TCC
UPDATE conditions. This is useful for easy stepper motor and full bridge control.
The non-recoverable fault module enables event controlled fault protection by acting directly on the generated
waveforms of the timer/counter compare channel outputs. When a non-recoverable fault condition is detected, the
output waveforms are forced to a preconfigured value that is safe for the application. This is typically used for instant
and predictable shut down and disabling high current or voltage drives.
The count event sources (TCE0 and TCE1) are shared with the non-recoverable fault extension. The events can be
optionally filtered.
© 2021 Microchip Technology Inc.
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PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Note: MCE0 and MCE1 can also be used as non-recoverable event source.
If the filter options are not used, the non-recoverable faults provide an immediate asynchronous action on waveform
output, even for cases where the clock is not present. For further details on how to configure asynchronous events
routing, refer to section EVSYS – Event System.
34.6.2
Basic Operation
34.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the TCC is
disabled(CTRLA.ENABLE=0):
• Control A (CTRLA) register, except Run Standby (RUNSTDBY), Enable (ENABLE) and Software Reset
(SWRST) bits
• Recoverable Fault n Control registers (FCTRLA and FCTRLB)
• Waveform Extension Control register (WEXCTRL)
• Drive Control register (DRVCTRL)
• Event Control register (EVCTRL)
Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1',
but not at the same time as CTRLA.ENABLE is written to '0'. Enable-protection is denoted by the “Enable-Protected”
property in the register description.
Before the TCC is enabled, it must be configured as outlined by the following steps:
1. Enable the TCC bus clock (CLK_TCCx_APB).
2. If Capture mode is required, enable the channel in capture mode by writing a '1' to the Capture Enable bit in
the Control A register (CTRLA.CPTEN).
Optionally, the following configurations can be set before enabling TCC:
1. Select PRESCALER setting in the Control A register (CTRLA.PRESCALER).
2. Select Prescaler Synchronization setting in Control A register (CTRLA.PRESCSYNC).
3. If down-counting operation is desired, write the Counter Direction bit in the Control B Set register
(CTRLBSET.DIR) to '1'.
4. Select the Waveform Generation operation in the WAVE register (WAVE.WAVEGEN).
5. Select the Waveform Output Polarity in the WAVE register (WAVE.POL).
6. The waveform output can be inverted for the individual channels using the Waveform Output Invert Enable bit
group in the Driver register (DRVCTRL.INVEN).
Note: Two instances of the TCC (TCC0 and TCC1) may share a peripheral clock channel. In this case, they cannot
be set to different clock frequencies. Refer to the peripheral clock channel mapping of the Generic Clock Controller
(GCLK.PCHTRLm) to identify shared peripheral clocks.
34.6.2.2 Enabling, Disabling, and Resetting
The TCC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The TCC is disabled
by writing a zero to CTRLA.ENABLE.
The TCC is reset by writing '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers
in the TCC, except DBGCTRL, will be reset to their initial state, and the TCC will be disabled. Refer to Control A
(34.7.1 CTRLA) register for details.
The TCC should be disabled before the TCC is reset to avoid undefined behavior.
34.6.2.3 Prescaler Selection
The GCLK_TCCx clock is fed into the internal prescaler.
The prescaler consists of a counter that counts up to the selected prescaler value, whereupon the output of the
prescaler toggles.
If the prescaler value is higher than one, the counter update condition can be optionally executed on the
next GCLK_TCC clock pulse or the next prescaled clock pulse. For further details, refer to the Prescaler
(CTRLA.PRESCALER) and Counter Synchronization (CTRLA.PRESYNC) descriptions.
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Timer/Counter for Control (TCC) Applications
Prescaler outputs from 1 to 1/1024 are available. For a complete list of available prescaler outputs, see the register
description for the Prescaler bit group in the Control A register (CTRLA.PRESCALER).
Note: When counting events, the prescaler is bypassed.
The joint stream of prescaler ticks and event action ticks is called CLK_TCC_COUNT.
Figure 34-2. Prescaler
PRESCALER
GCLK_TCC
PRESCALER
GCLK_TCC /
{1,2,4,8,64,256,1024 }
EVACT 0/1
TCCx EV0/1
CLK_TCC_COUNT
COUNT
34.6.2.4 Counter Operation
Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each TCC
clock input (CLK_TCC_COUNT). A counter clear or reload mark the end of current counter cycle and the start of a
new one.
The counting direction is set by the Direction bit in the Control B register (CTRLB.DIR). If the bit is zero, it's counting
up and one if counting down.
The counter will count up or down for each tick (clock or event) until it reaches TOP or ZERO. When it's counting
up and TOP is reached, the counter will be set to zero at the next tick (overflow) and the Overflow Interrupt Flag in
the Interrupt Flag Status and Clear register (INTFLAG.OVF) will be set. When down-counting, the counter is reloaded
with the TOP value when ZERO is reached (underflow), and INTFLAG.OVF is set.
INTFLAG.OVF can be used to trigger an interrupt, a DMA request, or an event. An overflow/underflow occurrence
(i.e. a compare match with TOP/ZERO) will stop counting if the One-Shot bit in the Control B register is set
(CTRLBSET.ONESHOT). The One-Shot feature is explained in the Additional Features section.
Figure 34-3. Counter Operation
Direction Change
COUNT written
MAX
"reload" update
"clear" update
COUNT
TOP
ZERO
DIR
It is possible to change the counter value (by writing directly in the COUNT register) even when the counter
is running. The COUNT value will always be ZERO or TOP, depending on direction set by CTRLBSET.DIR or
CTRLBCLR.DIR, when starting the TCC, unless a different value has been written to it, or the TCC has been stopped
at a value other than ZERO. The write access has higher priority than count, clear, or reload. The direction of the
counter can also be changed during normal operation. See the figure 34-3 above for further information.
Stop Command
A stop command can be issued from software by using TCC Command bits in Control B Set register
(CTRLBSET.CMD=0x2, STOP).
When a stop is detected while the counter is running, the counter will maintain its current value. If the waveform
generation (WG) is used, all waveforms are set to a state defined in Non-Recoverable State x Output Enable bit and
Non- Recoverable State x Output Value bit in the Driver Control register (DRVCTRL.NREx and DRVCTRL.NRVx),
and the Stop bit in the Status register is set (STATUS.STOP).
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Timer/Counter for Control (TCC) Applications
Pause Event Action
A pause command can be issued when the stop event action is configured in the Input Event Action 1 bits in Event
Control register (EVCTRL.EVACT1=0x3, STOP).
When a pause is detected, the counter can stop immediately maintaining its current value and all waveforms keep
their current state, as long as a start event action is detected: Input Event Action 0 bits in Event Control register
(EVCTRL.EVACT0=0x3, START).
Re-Trigger Command and Event Action
A re-trigger command can be issued from software by using TCC Command bits in Control B Set register
(CTRLBSET.CMD=0x1, RETRIGGER), or from event when the re-trigger event action is configured in the Input
Event 0/1 Action bits in Event Control register (EVCTRL.EVACTx=0x1, RETRIGGER).
When the command is detected during counting operation, the counter will be reloaded or cleared, depending on
the counting direction (CTRLBSET.DIR or CTRLBCLR.DIR). The Re-Trigger bit in the Interrupt Flag Status and Clear
register will be set (INTFLAG.TRG). It is also possible to generate an event by writing a '1' to the Re-Trigger Event
Output Enable bit in the Event Control register (EVCTRL.TRGEO). If the re-trigger command is detected when the
counter is stopped, the counter will resume counting operation from the value in COUNT.
Note:
When a re-trigger event action is configured in the Event Action bits in the Event Control register
(EVCTRL.EVACTx=0x1, RETRIGGER), enabling the counter will not start the counter. The counter will start on
the next incoming event and restart on corresponding following event.
Start Event Action
The start action can be selected in the Event Control register (EVCTRL.EVACT0=0x3, START) and can start the
counting operation when previously stopped. The event has no effect if the counter is already counting. When the
module is enabled, the counter operation starts when the event is received or when a re-trigger software command is
applied.
Note:
When a start event action is configured in the Event Action bits in the Event Control register (EVCTRL.EVACT0=0x3,
START), enabling the counter will not start the counter. The counter will start on the next incoming event, but it will
not restart on subsequent events.
Count Event Action
The TCC can count events. When an event is received, the counter increases or decreases the value, depending on
direction settings (CTRLBSET.DIR or CTRLBCLR.DIR).
The count event action is selected by the Event Action 0 bit group in the Event Control register
(EVCTRL.EVACT0=0x5, COUNT).
Count on Active State of Asynchronous Event
The TCC counts during the active state of an asynchronous event (increment or decrement, depending on counter
direction).
Direction Event Action
The direction event action can be selected in the Event Control register (EVCTRL.EVACT1=0x2, DIR). When this
event is used, the asynchronous event path specified in the event system must be configured or selected. The
direction event action can be used to control the direction of the counter operation, depending on external events
level. When received, the event level overrides the Direction settings (CTRLBSET.DIR or CTRLBCLR.DIR) and the
direction bit value is updated accordingly.
Increment Event Action
The increment event action can be selected in the Event Control register (EVCTRL.EVACT0=0x4, INC) and can
change the counter state when an event is received. When the TCE0 event (TCCx_EV0) is received, the counter
increments, whatever the direction setting (CTRLBSET.DIR or CTRLBCLR.DIR) is.
Decrement Event Action
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Timer/Counter for Control (TCC) Applications
The decrement event action can be selected in the Event Control register (EVCTRL.EVACT1=0x4, DEC) and can
change the counter state when an event is received. When the TCE1 (TCCx_EV1) event is received, the counter
decrements, whatever the direction setting (CTRLBSET.DIR or CTRLBCLR.DIR) is.
Non-recoverable Fault Event Action
Non-recoverable fault actions can be selected in the Event Control register (EVCTRL.EVACTx=0x7, FAULT). When
received, the counter will be stopped and the output of the compare channels is overridden according to the
Driver Control register settings (DRVCTRL.NREx and DRVCTRL.NRVx). TCE0 and TCE1 must be configured as
asynchronous events.
Event Action Off
If the event action is disabled (EVCTRL.EVACTx=0x0, OFF), enabling the counter will also start the counter.
34.6.2.5 Compare Operations
By default, the Compare/Capture channel is configured for compare operations. To perform capture operations, it
must be re-configured.
When using the TCC with the Compare/Capture Value registers (CCx) for compare operations, the counter value is
continuously compared to the values in the CCx registers. This can be used for timer or for waveform operation.
The Channel x Compare/Capture Buffer Value (CCBUFx) registers provide double buffer capability. The double
buffering synchronizes the update of the CCx register with the buffer value at the UPDATE condition or a force
update command (CTRLBSET.CMD=0x3, UPDATE). For further details, refer to 34.6.2.6 Double Buffering. The
synchronization prevents the occurrence of odd-length, non-symmetrical pulses and ensures glitch-free output.
34.6.2.5.1 Waveform Output Generation Operations
The compare channels can be used for waveform generation on output port pins. To make the waveform available on
the connected pin, the following requirements must be fulfilled:
1. Choose a waveform generation mode in the Waveform Generation Operation bit in Waveform register
(WAVE.WAVEGEN).
2. Optionally invert the waveform output WO[x] by writing the corresponding Waveform Output x Inversion bit in
the Driver Control register (DRVCTRL.INVENx).
3. Configure the pins with the I/O Pin Controller. Refer to the PORT - I/O Pin Controller for details.
Note: Event MCx must not be used when the compare channel is set in waveform output operating mode, except
when used as non-recoverable fault input.
The counter value is continuously compared with each CCx value. On a comparison match, the Match or Capture
Channel x bit in the Interrupt Flag Status and Clear register (INTFLAG.MCx) will be set on the next zero-to-one
transition of CLK_TCC_COUNT (see Normal Frequency Operation). An interrupt and/or event can be generated on
the same condition if Match/Capture occurs, i.e. INTENSET.MCx and/or EVCTRL.MCEOx is '1'. Both interrupt and
event can be generated simultaneously. The same condition generates a DMA request.
There are seven waveform configurations for the Waveform Generation Operation bit group in the Waveform register
(WAVE.WAVEGEN). This will influence how the waveform is generated and impose restrictions on the top value. The
configurations are:
• Normal Frequency (NFRQ)
• Match Frequency (MFRQ)
• Normal Pulse-Width Modulation (NPWM)
• Dual-slope, interrupt/event at TOP (DSTOP)
• Dual-slope, interrupt/event at ZERO (DSBOTTOM)
• Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
• Dual-slope, critical interrupt/event at ZERO (DSCRITICAL)
When using MFRQ configuration, the TOP value is defined by the CC0 register value. For the other waveform
operations, the TOP value is defined by the Period (PER) register value.
For dual-slope waveform operations, the update time occurs when the counter reaches ZERO. For the other
waveforms generation modes, the update time occurs on counter wraparound, on overflow, underflow, or re-trigger.
The table below shows the update counter and overflow event/interrupt generation conditions in different operation
modes.
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PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Table 34-3. Counter Update and Overflow Event/interrupt Conditions
Name
Operation
TOP
Update
Output Waveform
OVFIF/Event
On Match
On Update
Up
Down
NFRQ
Normal
Frequency
PER
TOP/ ZERO
Toggle
Stable
TOP
ZERO
MFRQ
Match
Frequency
CC0
TOP/ ZERO
Toggle
Stable
TOP
ZERO
NPWM
Single-slope
PWM
PER
TOP/ ZERO
See section 'Output Polarity' TOP
below
ZERO
DSCRITICAL
Dual-slope
PWM
PER
ZERO
-
ZERO
DSBOTTOM
Dual-slope
PWM
PER
ZERO
-
ZERO
DSBOTH
Dual-slope
PWM
PER
TOP(1) &
ZERO
TOP
ZERO
DSTOP
Dual-slope
PWM
PER
ZERO
TOP
–
1.
The UPDATE condition on TOP only will occur when circular buffer is enabled for the channel.
34.6.2.5.2 Normal Frequency (NFRQ)
For Normal Frequency generation, the period time (T) is controlled by the period register (PER). The waveform
generation output (WO[x]) is toggled on each compare match between COUNT and CCx, and the corresponding
Match or Capture Channel x Interrupt Flag (EVCTRL.MCEOx) will be set.
Figure 34-4. Normal Frequency Operation
Period (T)
Direction Change
COUNT Written
MAX
COUNT
"reload" update
"clear" update
"match"
TOP
CCx
ZERO
WO[x]
34.6.2.5.3 Match Frequency (MFRQ)
For Match Frequency generation, the period time (T) is controlled by CC0 register instead of PER. WO[0] toggles on
each update condition.
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Figure 34-5. Match Frequency Operation
Direction Change
COUNT Written
MAX
"reload" update
"clear" update
COUNT
CC0
ZERO
WO[0]
34.6.2.5.4 Normal Pulse-Width Modulation (NPWM)
NPWM uses single-slope PWM generation.
34.6.2.5.5 Single-Slope PWM Operation
For single-slope PWM generation, the period time (T) is controlled by Top value, and CCx controls the duty cycle of
the generated waveform output. When up-counting, the WO[x] is set at start or compare match between the COUNT
and TOP values, and cleared on compare match between COUNT and CCx register values. When down-counting,
the WO[x] is cleared at start or compare match between the COUNT and ZERO values, and set on compare match
between COUNT and CCx register values.
Figure 34-6. Single-Slope PWM Operation
CCx=ZERO
CCx=TOP
"clear" update
"match"
MAX
TOP
COUNT
CCx
ZERO
WO[x]
The following equation calculates the exact resolution for a single-slope PWM (RPWM_SS) waveform:
RPWM_SS =
log(TOP+1)
log(2)
fPWM_SS =
fGCLK_TCC
N(TOP+1)
The PWM frequency depends on the Period register value (PER) and the peripheral clock frequency (fGCLK_TCC), and
can be calculated by the following equation:
Where N represents the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024).
34.6.2.5.6 Dual-Slope PWM Generation
For dual-slope PWM generation, the period setting (TOP) is controlled by PER, while CCx control the duty cycle of
the generated waveform output. The figure below shows how the counter repeatedly counts from ZERO to PER and
then from PER to ZERO. The waveform generator output is set on compare match when up-counting, and cleared
on compare match when down-counting. An interrupt and/or event is generated on TOP (when counting upwards)
and/or ZERO (when counting up or down).
In DSBOTH operation, the circular buffer must be enabled to enable the update condition on TOP.
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Timer/Counter for Control (TCC) Applications
Figure 34-7. Dual-Slope Pulse Width Modulation
CCx=ZERO
CCx=TOP
"update"
"match"
MAX
CCx
TOP
COUNT
ZERO
WO[x]
Using dual-slope PWM results in a lower maximum operation frequency compared to single-slope PWM generation.
The period (TOP) defines the PWM resolution. The minimum resolution is 1 bit (TOP=0x00000001).
The following equation calculates the exact resolution for dual-slope PWM (RPWM_DS):
RPWM_DS =
log(TOP+1)
.
log(2)
fPWM_DS =
fGCLK_TCC
2N ⋅ TOP
The PWM frequency fPWM_DS depends on the period setting (TOP) and the peripheral clock frequency fGCLK_TCC, and
can be calculated by the following equation (outside of DSBOTH mode):
N represents the prescaler divider used. The waveform generated will have a maximum frequency of half of the TCC
clock frequency (fGCLK_TCC) when TOP is set to 0x00000001 and no prescaling is used.
The pulse width (PPWM_DS) depends on the compare channel (CCx) register value and the peripheral clock frequency
(fGCLK_TCC), and can be calculated by the following equation:
PPWM_DS =
2N ⋅ TOP − CCx
fGCLK_TCC
N represents the prescaler divider used.
Note: In DSTOP, DSBOTTOM and DSBOTH operation, when TOP is lower than MAX/2, the CCx MSB bit defines
the ramp on which the CCx Match interrupt or event is generated. (Rising if CCx[MSB] = 0, falling if CCx[MSB] = 1.)
34.6.2.5.7 Dual-Slope Critical PWM Generation
Critical mode generation allows generation of non-aligned centered pulses. In this mode, the period time (TOP) is
controlled by PER while CCx control the generated waveform output edge during up-counting and CC(x+CC_NUM/2)
control the generated waveform output edge during down-counting.
Figure 34-8. Dual-Slope Critical Pulse Width Modulation (N=CC_NUM)
"reload" update
"match"
MAX
CCx
COUNT
CC(x+N/2)
CCx
CC(x+N/2)
CCx
CC(x+N/2)
TOP
ZERO
WO[x]
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PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.6.2.5.8 Output Polarity
The polarity (WAVE.POLx) is available in all waveform output generation. In single-slope and dual-slope PWM
operation, it is possible to invert the pulse edge alignment individually on start or end of a PWM cycle for each
compare channels. The table below shows the waveform output set/clear conditions, depending on the settings of
timer/counter, direction, and polarity.
Table 34-4. Waveform Generation Set/Clear Conditions
Waveform Generation
operation
Single-Slope PWM
DIR POLx Waveform Generation Output Update
0
1
Dual-Slope PWM
x
Set
Clear
0
Timer/counter matches TOP
Timer/counter matches CCx
1
Timer/counter matches CC
Timer/counter matches TOP
0
Timer/counter matches CC
Timer/counter matches ZERO
1
Timer/counter matches ZERO
Timer/counter matches CC
0
Timer/counter matches CC when
counting up
Timer/counter matches CC when
counting down
1
Timer/counter matches CC when
counting down
Timer/counter matches CC when
counting up
In Normal and Match Frequency, the WAVE.POLx value represents the initial state of the waveform output.
34.6.2.6 Double Buffering
The Pattern (PATT), Period (PER) and Compare Channels (CCx) registers are all double buffered. Each buffer
register has a buffer valid (PATTBUFV, PERBUFV and CCBUFVx) bit in the STATUS register, which indicates that
the Buffer register contains a valid value that can be copied into the corresponding register. As long as the respective
Buffer Valid Status flag (PATTBUFV, PERBUFV or CCBUFVx) are set to '1', the related SYNCBUSY bits are set
(SYNCBUSY.PATT, SYNCBUSY.PER or SYNCBUSY.CCx), a write to the respective PATT/PATTBUF, PER/PERBUF
or CCx/CCBUFx registers will generate a PAC error, and read access to the respective PATT, PER or CCx register is
invalid.
When the Buffer Valid Flag bit in the STATUS register is '1' and the Lock Update bit in the CTRLB register is set to
'0', (writing CTRLBCLR.LUPD to '1'), double buffering is enabled: the data from buffer registers will be copied into the
corresponding register under hardware UPDATE conditions, then the Buffer Valid Flags bit in the STATUS register
are automatically cleared by hardware. The buffer valid flag bits in the STATUS register can be cleared manually, but
must be cleared two times successively.
Note: Software update command (CTRLBSET.CMD=0x3) act independently of LUPD value.
A compare register is double buffered as in the following figure.
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Figure 34-9. Compare Channel Double Buffering
"APB write enable"
BV
UPDATE
"data write"
EN
CCBUFx
EN
CCx
COUNT
"match"
=
Both the registers (PATT/PER/CCx) and corresponding Buffer registers (PATTBUF/PERBUF/CCBUFx) are available
in the I/O register map, and the double buffering feature is not mandatory. The double buffering is disabled by writing
a '1' to CTRLSET.LUPD.
Note: When NFRQ, MFRQ or PWM down-counting counter mode (CTRLBSET.DIR=1), is enabled and double
buffering is enabled (CTRLBCLR.LUPD=1), PERBUF register is continuously copied into the PER independently of
update conditions.
Figure 34-10. Unbuffered Single-Slope Up-Counting Operation
Counter Wraparound
MAX
"clear" update
"write"
COUNT
ZERO
New value written to
PER that is higher
than current COUNT
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New value written to
PER that is lower
than current COUNT
Datasheet
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Timer/Counter for Control (TCC) Applications
Figure 34-11. Unbuffered Single-Slope Down-Counting Operation
MAX
"reload" update
"write"
COUNT
ZERO
New value written to
PER that is higher
than current COUNT
New value written to
PER that is lower
than current COUNT
A counter wraparound can occur in any operation mode when up-counting without buffering. COUNT and TOP are
continuously compared, so when a new value that is lower than the current COUNT is written to TOP, COUNT will
wrap before a compare match.
Figure 34-12. Unbuffered Dual-Slope Operation
Counter Wraparound
MAX
"reload" update
"write"
COUNT
ZERO
New value written to
PER that is higher
than current COUNT
New value written to
PER that is lower
than current COUNT
When double buffering is used, the buffer can be written at any time and the counter will still maintain correct
operation. The period register is always updated on the update condition, as shown in the following figure. This
prevents wraparound and the generation of odd waveforms.
Figure 34-13. Changing the Period Using Buffering
MAX
"reload" update
"write"
COUNT
ZERO
New value written to
PERBUF that is higher
than current COUNT
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New value written to
PERBUF that is lower
than current COUNT
Datasheet
PER is updated with
PERBUF value
DS60001638D-page 623
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.6.2.7 Capture Operations
To enable and use capture operations, the Match or Capture Channel x Event Input Enable bit in the Event Control
register (EVCTRL.MCEIx) must be written to '1'. The capture channels to be used must also be enabled in the
Capture Channel x Enable bit in the Control A register (CTRLA.CPTENx) before capturing can be performed.
Event system channels must be configured to operate in asynchronous mode of operation when used for capture
operations.
Event Capture Action
The compare/capture channels can be used as input capture channels to capture events from the Event System, and
give them a timestamp. The following figure shows four capture events for one capture channel.
Figure 34-14. Input Capture Timing
events
MAX
COUNT
ZERO
Capture 0
Capture 1
Capture 2
Capture 3
For input capture, the buffer register and the corresponding CCx act like a FIFO. When CCx is empty or read,
any content in CCBUFx is transferred to CCx. The buffer valid flag is passed to set the CCx interrupt flag (IF) and
generate the optional interrupt, event or DMA request. CCBUFx register value can't be read, all captured data must
be read from CCx register.
Figure 34-15. Capture Double Buffering
"capture"
COUNT
BUFV
EN
CCBUFx
IF
EN
CCx
"INT/DMA
request"
data read
The TCC can detect capture overflow of the input capture channels: When a new capture event is detected while the
Capture Buffer Valid flag (STATUS.CCBUFV) is still set, the new timestamp will not be stored and INTFLAG.ERR will
be set.
Period and Pulse-Width (PPW) Capture Action
The TCC can perform two input captures and restart the counter on one of the edges. This enables the TCC to
measure the pulse-width and period and to characterize the frequency f and dutyCycle of an input signal:
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f= 1
T
,
dutyCycle =
tp
T
Figure 34-16. PWP Capture
Period (T)
external
signal /event
capture times
MAX
"capture"
COUNT
ZERO
CC0
CC1
CC0
CC1
Selecting PWP or PPW in the Timer/Counter Event Input 1 Action bit group in the Event Control register
(EVCTRL.EVACT1) enables the TCC to perform one capture action on the rising edge and the other one on the
falling edge. When using PPW (period and pulse-width) event action, period T will be captured into CC0 and the
pulse-width tp into CC1. The PWP (Pulse-width and Period) event action offers the same functionality, but T will be
captured into CC1 and tp into CC0.
The Timer/Counter Event x Invert Enable bit in Event Control register (EVCTRL.TCEINVx) is used for event source
x to select whether the wraparound should occur on the rising edge or the falling edge. If EVCTRL.TCEINVx=1, the
wraparound will happen on the falling edge.
The corresponding capture is done only if the channel is enabled in capture mode (CTRLA.CPTENx=1). If not, the
capture action will be ignored and the channel will be enabled in compare mode of operation. When only one of these
channel is required, the other channel can be used for other purposes.
The TCC can detect capture overflow of the input capture channels: When a new capture event is detected while the
INTFLAG.MCx is still set, the new timestamp will not be stored and INTFLAG.ERR will be set.
Note: When up-counting (CTRLBSET.DIR=0), counter values lower than 1 cannot be captured in Capture Minimum
mode (FCTRLn.CAPTURE=CAPTMIN). To capture the full range including value 0, the TCC must be configured in
down-counting mode (CTRLBSET.DIR=0).
Note: In dual-slope PWM operation, and when TOP is lower than MAX/2, the CCx MSB captures the CTRLB.DIR
state to identify the ramp on which the capture has been done. For rising ramps CCx[MSB] is zero, for falling ramps
CCx[MSB]=1.
34.6.3
Additional Features
34.6.3.1 One-Shot Operation
When one-shot is enabled, the counter automatically stops on the next counter overflow or underflow condition.
When the counter is stopped, the Stop bit in the Status register (STATUS.STOP) is set and the waveform outputs are
set to the value defined by DRVCTRL.NREx and DRVCTRL.NRVx.
One-shot operation can be enabled by writing a '1' to the One-Shot bit in the Control B Set register
(CTRLBSET.ONESHOT) and disabled by writing a '1' to CTRLBCLR.ONESHOT. When enabled, the TCC will count
until an overflow or underflow occurs and stop counting. The one-shot operation can be restarted by a re-trigger
software command, a re-trigger event or a start event. When the counter restarts its operation, STATUS.STOP is
automatically cleared.
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Timer/Counter for Control (TCC) Applications
34.6.3.2 Circular Buffer
The Period register (PER) and the compare channels register (CC0 to CC3) support circular buffer operation. When
circular buffer operation is enabled, the PER or CCx values are copied into the corresponding buffer registers at each
update condition. Circular buffering is dedicated to RAMP2, RAMP2A, and DSBOTH operations.
Figure 34-17. Circular Buffer on Channel 0
"write enable"
BUFV
UPDATE
"data write"
EN
CCBUF0
EN
CC0
UPDATE
CIRCC0EN
COUNT
=
"ma tch"
34.6.3.3 Dithering Operation
The TCC supports dithering on Pulse-width or Period on a 16, 32 or 64 PWM cycles frame. The TCC does not
support dithering with any RAMP2 operation.
Dithering consists in adding some extra clocks cycles in a frame of several PWM cycles, and can improve the
accuracy of the average output pulse width and period. The extra clock cycles are added on some of the compare
match signals, one at a time, through a "blue noise" process that minimizes the flickering on the resulting dither
patterns. The use of dithering with an external retrigger event (EVCTRL.EVACTx) is not possible as the event can
lead to unexpected stretch of right aligned pulses, or shrinking of left aligned pulses.
Dithering is enabled by writing the corresponding configuration in the Enhanced Resolution bits in CTRLA register
(CTRLA.RESOLUTION):
•
•
•
DITH4 enable dithering every 16 PWM frames
DITH5 enable dithering every 32 PWM frames
DITH6 enable dithering every 64 PWM frames
The DITHERCY bits of COUNT, PER and CCx define the dithercy increment value and so the number of extra cycles
to add into the frame (DITHERCY bits from the respective COUNT, PER or CCx registers). The remaining bits of
COUNT, PER, CCx define the compare value itself.
The pseudo code, giving the extra cycles insertion regarding the cycle is:
int extra_cycle(resolution, dithercy, cycle){
int MASK;
int value
switch (resolution){
DITH4: MASK = 0x0f;
DITH5: MASK = 0x1f;
DITH6: MASK = 0x3f;
}
value = cycle * dithercy;
if (((MASK & value) + dithercy) > MASK)
return 1;
return 0;
}
Dithering on Period
Writing DITHERCY in PER will lead to an average PWM period configured by the following formulas.
DITH4 mode:
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PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
PwmPeriod = DITHERCY + PER
16
1
fGCLK_TCC
Note: If DITH4 mode is enabled, the last 4 significant bits from PER/CCx register correspond to the DITHERCY
value (the last 4 significant bits from COUNT are always read as 0), rest of the bits corresponds to PER/CCx or
COUNT value.
DITH5 mode:
PwmPeriod = DITHERCY + PER
32
DITH6 mode:
1
fGCLK_TCC
PwmPeriod = DITHERCY + PER
64
1
fGCLK_TCC
Dithering on Pulse Width
Writing DITHERCY in CCx will lead to an average PWM pulse width configured by the following formula.
DITH4 mode:
PwmPulseWidtℎ = DITHERCY + CCx
16
DITH5 mode:
1
fGCLK_TCC
PwmPulseWidtℎ = DITHERCY + CCx
32
DITH6 mode:
1
fGCLK_TCC
PwmPulseWidtℎ = DITHERCY + CCx
64
1
fGCLK_TCC
Note: The PWM period will remain static in this case.
34.6.3.4 Ramp Operations
Three ramp operation modes are supported. All of them require the timer/counter running in single-slope PWM
generation. The ramp mode is selected by writing to the Ramp Mode bits in the Waveform Control register
(WAVE.RAMP).
RAMP1 Operation
This is the default PWM operation, described in Single-Slope PWM Generation.
RAMP2 Operation
These operation modes are dedicated for power factor correction (PFC), Half-Bridge and Push-Pull SMPS
topologies, where two consecutive timer/counter cycles are interleaved. In cycle A, odd channel output is disabled,
and in cycle B, even channel output is disabled. The ramp index changes after each update, but can be software
modified using the Ramp index command bits in Control B Set register (CTRLBSET.IDXCMD). All RAMP2 operations
only support counting up mode (CTRLB.DIR = 0).
Standard RAMP2 (RAMP2) Operation
Ramp A and B periods are controlled by the PER register value. The PER value can be different on each ramp by
the Circular Period buffer option in the Wave register (WAVE.CIPEREN=1). This mode uses a two-channel TCC to
generate two output signals.
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Datasheet
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PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Figure 34-18. RAMP2 Standard Operation
Ramp
A
B
A
B
Retrigger
on
FaultA
TOP(B)
TOP(A)
CC0
TOP(B)
CIPEREN = 1
CC1
CC1
COUNT
"clear" update
"match"
CC0
ZERO
WO[0]
POL0 = 1
WO[1]
Keep on FaultB
POL1 = 1
FaultA input
FaultB input
Alternate RAMP2 (RAMP2A) Operation
Alternate RAMP2 operation is similar to RAMP2, but CC0 controls both WO[0] and WO[1] waveforms when the
corresponding circular buffer option is enabled (CIPEREN=1). The waveform polarity is the same on both outputs.
Channel 1 can be used in capture mode.
Figure 34-19. RAMP2 Alternate Operation
Ramp
A
B
A
TOP(B)
TOP(A)
B
Retrigger
on
FaultA
CC0(B)
COUNT
CC0(A)
"clear" update
"match"
TOP(B)
CIPEREN = 1
CC0(B)
CICCEN0 = 1
CC0(A)
ZERO
WO[0]
Keep on FaultB
WO[1]
POL0 = 1
FaultA input
FaultB input
Critical RAMP2 (RAMP2C) Operation
Critical RAMP2 operation provides a way to cover RAMP2 operation requirements without the update constraint
associated with the use of circular buffers. In this mode, CC0 is controlling the period of ramp A and PER is
controlling the period of ramp B. When using more than two channels, WO[0] output is controlled by CC2 (HIGH) and
CC0 (LOW). On TCC with 2 channels, a pulse on WO[0] will last the entire period of ramp A, if WAVE.POL0=0.
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and its subsidiaries
Datasheet
DS60001638D-page 628
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Figure 34-20. RAMP2 Critical Operation With More Than 2 Channels
Ramp
A
B
A
B
Retrigger
on
FaultA
TOP
CC0
CC1
COUNT
"clear" update
"match"
TOP
CC1
CC2
CC2
ZERO
WO[0]
POL2 = 1
WO[1]
Keep on FaultB
POL1 = 1
FaultA input
FaultB input
Figure 34-21. RAMP2 Critical Operation With 2 Channels
Ramp
A
B
A
TOP
CC0
B
Retrigger
on
FaultA
CC1
COUNT
"clear" update
"match"
TOP
CC1
ZERO
WO[0]
POL0 = 0
WO[1]
Keep on FaultB
POL1 = 1
FaultA input
FaultB input
34.6.3.5 Recoverable Faults
Recoverable faults can restart or halt the timer/counter. Two faults, called Fault A and Fault B, can trigger recoverable
fault actions on the compare channels CC0 and CC1 of the TCC. The compare channels' outputs can be clamped to
inactive state either as long as the fault condition is present, or from the first valid fault condition detection on until the
end of the timer/counter cycle.
Fault Inputs
The first two channel input events (TCCxMC0 and TCCxMC1) can be used as Fault A and Fault B inputs,
respectively. Event system channels connected to these fault inputs must be configured as asynchronous. The TCC
must work in a PWM mode.
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PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Fault Filtering
There are three filters available for each input Fault A and Fault B. They are configured by the corresponding
Recoverable Fault n Configuration registers (FCTRLA and FCTRLB). The three filters can either be used
independently or in any combination.
Input
Filtering
By default, the event detection is asynchronous. When the event occurs, the fault system will
immediately and asynchronously perform the selected fault action on the compare channel output,
also in device power modes where the clock is not available. To avoid false fault detection on external
events (e.g. due to a glitch on an I/O port) a digital filter can be enabled and configured by the Fault
B Filter Value bits in the Fault n Configuration registers (FCTRLn.FILTERVAL). If the event width is
less than FILTERVAL (in clock cycles), the event will be discarded. A valid event will be delayed by
FILTERVAL clock cycles.
Fault
Blanking
This ignores any fault input for a certain time just after a selected waveform output edge. This can be
used to prevent false fault triggering due to signal bouncing, as shown in the figure below. Blanking
can be enabled by writing an edge triggering configuration to the Fault n Blanking Mode bits in the
Recoverable Fault n Configuration register (FCTRLn.BLANK). The desired duration of the blanking
must be written to the Fault n Blanking Time bits (FCTRLn.BLANKVAL).
The blanking time, tb is calculated by
tb = 1 + BLANKVAL
fGCLK_TCCx_PRESC
Where,
fGCLK_TCCx_PRESC is the frequency of the prescaled peripheral clock frequency fGCLK_TCCx. The
prescaler is enabled by writing '1' to the Fault n Blanking Prescaler bit (FCTRLn.BLANKPRESC).
When disabled, fGCLK_TCCx_PRESC=fGCLK_TCCx. When enabled, fGCLK_TCCx_PRESC=fGCLK_TCCx/64.
The maximum blanking time (FCTRLn.BLANKVAL=
255) at fGCLK_TCCx=96MHz is 2.67µs (no prescaler) or 170µs (prescaling). For fGCLK_TCCx=1MHz, the
maximum blanking time is either 170µs (no prescaling) or 10.9ms (prescaling enabled).
Figure 34-22. Fault Blanking in RAMP1 Operation with Inverted Polarity
"clear" update
"match"
TOP
"Fault input enabled"
- "Fault input disabled"
CC0
x
"Fault discarded"
COUNT
ZERO
CMP0
FCTRLA.BLANKVAL = 0
FaultA Blanking
FCTRLA.BLANKVAL > 0
FCTRLA.BLANKVAL > 0
x
-
xxx
FaultA Input
WO[0]
Fault
Qualification
This is enabled by writing a '1' to the Fault n Qualification bit in the Recoverable Fault n
Configuration register (FCTRLn.QUAL). When the recoverable fault qualification is enabled
(FCTRLn.QUAL=1), the fault input is disabled all the time the corresponding channel output
has an inactive level, as shown in the figures below.
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PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Figure 34-23. Fault Qualification in RAMP1 Operation
MAX
"clear" update
TOP
"match"
CC0
COUNT
"Fault input enabled"
- "Fault input disabled"
CC1
x
"Fault discarded"
ZERO
-
Fault A Input Qual
-
-
-
-
x x x
x x x x x x
Fault Input A
Fault B Input Qual
-
-
-
x x x
-
x x x x x
-
x x x x x x x
-
x x x x
Fault Input B
Figure 34-24. Fault Qualification in RAMP2 Operation with Inverted Polarity
Cycle
"clear" update
MAX
"match"
TOP
"Fault input enabled"
CC0
COUNT
- "Fault input disabled"
x
CC1
"Fault discarded"
ZERO
Fault A Input Qual
-
-
x
x
-
x
x
x
x
x
x
x
x
x
x
Fault Input A
-
Fault B Input Qual
x
x
x
x
-
x
x
x
x
-
x
x
x
x
x
x
x
Fault Input B
Fault Actions
Different fault actions can be configured individually for Fault A and Fault B. Most fault actions are not mutually
exclusive; therefore two or more actions can be enabled at the same time to achieve a result that is a combination of
fault actions.
Keep
Action
This is enabled by writing the Fault n Keeper bit in the Recoverable Fault n Configuration register
(FCTRLn.KEEP) to '1'. When enabled, the corresponding channel output will be clamped to zero as
long as the fault condition is present. The clamp will be released on the start of the first cycle after the
fault condition is no longer present, see next Figure.
Figure 34-25. Waveform Generation with Fault Qualification and Keep Action
MAX
"clear" update
TOP
"match"
COUNT
"Fault input enabled"
CC0
- "Fault input disabled"
x
"Fault discarded"
ZERO
Fault A Input Qual
-
-
-
-
x
-
x
x
x
Fault Input A
WO[0]
© 2021 Microchip Technology Inc.
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KEEP
KEEP
Datasheet
DS60001638D-page 631
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Restart
Action
This is enabled by writing the Fault n Restart bit in Recoverable Fault n Configuration register
(FCTRLn.RESTART) to '1'. When enabled, the timer/counter will be restarted as soon as the
corresponding fault condition is present. The ongoing cycle is stopped and the timer/counter starts a
new cycle, see the following figures. In Ramp 1 mode, when the new cycle starts, the compare outputs
will be clamped to inactive level as long as the fault condition is present.
Note: For RAMP2 operation, when a new timer/counter cycle starts the cycle index will change
automatically, see the following figures. Fault A and Fault B are qualified only during the cycle A and
cycle B respectively: Fault A is disabled during cycle B, and Fault B is disabled during cycle A.
Figure 34-26. Waveform Generation in RAMP1 mode with Restart Action
MAX
"clear" update
"match"
TOP
CC0
COUNT
CC1
ZERO
Restart
Restart
Fault Input A
WO[0]
WO[1]
Figure 34-27. Waveform Generation in RAMP2 mode with Restart Action
Cycle
CCx=ZERO
CCx=TOP
"clear" update
"match"
MAX
TOP
COUNT
CC0/CC1
ZERO
No fault A action
in cycle B
Restart
Fault Input A
WO[0]
WO[1]
Capture
Action
Several capture actions can be selected by writing the Fault n Capture Action bits in the Fault n Control
register (FCTRLn.CAPTURE). When one of the capture operations is selected, the counter value is
captured when the fault occurs. These capture operations are available:
• CAPT - The equivalent to a standard capture operation, for further details refer to 34.6.2.7 Capture
Operations
• CAPTMIN - Gets the minimum time stamped value: on each new local minimum captured value, an
event or interrupt is issued.
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PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
•
•
•
•
CAPTMAX - Gets the maximum time stamped value: on each new local maximum captured value,
an event or interrupt (IT) is issued. For additional information, refer to the following figure Capture
Action “CAPTMAX”.
LOCMIN - Notifies by event or interrupt when a local minimum captured value is detected.
LOCMAX - Notifies by event or interrupt when a local maximum captured value is detected.
DERIV0 - Notifies by event or interrupt when a local extreme captured value is detected, For more
information, reference the following figure Capture Action “DERIV0”.
CCx Content:
In CAPTMIN and CAPTMAX operations, CCx keeps the respective extreme captured values, For
more information, reference the following figure Capture Action “CAPTMAX”. In LOCMIN, LOCMAX
or DERIV0 operation, CCx follows the counter value at fault time, For more information, reference the
following figure Capture Action “DERIV0”.
Before enabling CAPTMIN or CAPTMAX mode of capture, the user must initialize the corresponding
CCx register value to a value different from zero (for CAPTMIN) or top (for CAPTMAX). If the CCx
register initial value is zero (for CAPTMIN) or top (for CAPTMAX), no captures will be performed using
the corresponding channel.
When using advanced capture functions like CAPTMIN, CAPTMAX, LOCMIN, LOCMAX and DERIV0,
standard capture functions (CAPT) must be assigned to the lower CCx channels when used. See the
example below.
Example: CC[0] = CAPT, CC[1] = CAPT, CC[2] = CAPTMIN, CC[3] = CAPTMAX.
MCx Behaviour:
In LOCMIN and LOCMAX operation, capture is performed on each capture event. The MCx interrupt
flag is set only when the captured value is above or equal (for LOCMIN) or below or equal (for
LOCMAX) to the previous captured value. So interrupt flag is set when a new relative local Minimum
(for CAPTMIN) or Maximum (for CAPTMAX) value has been detected. DERIV0 is equivalent to an OR
function of (LOCMIN, LOCMAX).
In CAPT operation, capture is performed on each capture event. The MCx interrupt flag is set on each
new capture.
In CAPTMIN and CAPTMAX operation, capture is performed only when on capture event time, the
counter value is lower (for CAPTMIN) or higher (for CAPMAX) than the last captured value. The MCx
interrupt flag is set only when on capture event time, the counter value is higher or equal (for CAPTMIN)
or lower or equal (for CAPTMAX) to the value captured on the previous event. So interrupt flag is
set when a new absolute local Minimum (for CAPTMIN) or Maximum (for CAPTMAX) value has been
detected.
Interrupt Generation
In CAPT mode, an interrupt is generated on each filtered Fault n and each dedicated CCx channel
capture counter value. In other modes, an interrupt is only generated on an extreme captured value.
Figure 34-28. Capture Action “CAPTMAX”
TOP
"clear" update
COUNT
CC0
ZERO
FaultA Input
CC0 Event/
Interrupt
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PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Figure 34-29. Capture Action “DERIV0”
TOP
COUNT
"update"
"match"
CC0
ZERO
WO[0]
FaultA Input
CC0 Event/
Interrupt
Hardware
Halt Action
This is configured by writing 0x1 to the Fault n Halt mode bits in the Recoverable Fault n
Configuration register (FCTRLn.HALT). When enabled, the timer/counter is halted and the cycle is
extended as long as the corresponding fault is present.
The next figure ('Waveform Generation with Halt and Restart Actions') shows an example where
both restart action and hardware halt action are enabled for Fault A. The compare channel 0 output
is clamped to inactive level as long as the timer/counter is halted. The timer/counter resumes the
counting operation as soon as the fault condition is no longer present. As the restart action is enabled
in this example, the timer/counter is restarted after the fault condition is no longer present.
The figure after that ('Waveform Generation with Fault Qualification, Halt, and Restart Actions') shows
a similar example, but with additionally enabled fault qualification. Here, counting is resumed after the
fault condition is no longer present.
Note that in RAMP2 and RAMP2A operations, when a new timer/counter cycle starts, the cycle index
will automatically change.
Figure 34-30. Waveform Generation with Halt and Restart Actions
MAX
"clear" update
"match"
TOP
COUNT
CC0
HALT
ZERO
Restart
Restart
Fault Input A
WO[0]
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PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Figure 34-31. Waveform Generation with Fault Qualification, Halt, and Restart Actions
MAX
"update"
"match"
TOP
CC0
COUNT
HALT
ZERO
Resume
Fault A Input Qual
-
-
-
-
x
x
-
x
Fault Input A
KEEP
WO[0]
Software
Halt Action
This is configured by writing 0x2 to the Fault n Halt mode bits in the Recoverable Fault n
configuration register (FCTRLn.HALT). Software halt action is similar to hardware halt action, but
in order to restart the timer/counter, the corresponding fault condition must not be present anymore,
and the corresponding FAULT n bit in the STATUS register must be cleared by software.
Figure 34-32. Waveform Generation with Software Halt, Fault Qualification, Keep and Restart Actions
MAX
"update"
"match"
TOP
COUNT
CC0
HALT
ZERO
Restart
Fault A Input Qual
-
-
Restart
x
-
x
Fault Input A
Software Clear
WO[0]
NO
KEEP
KEEP
FCTRLA.KEEP = 1
FCTRLA.KEEP = 0
34.6.3.6 Non-Recoverable Faults
The non-recoverable fault action will force all the compare outputs to a pre-defined level programmed into the Driver
Control register (DRVCTRL.NRE and DRVCTRL.NRV). The non-recoverable fault input (EV0 and EV1) actions are
enabled in Event Control register (EVCTRL.EVACT0 and EVCTRL.EVACT1).
To avoid false fault detection on external events (e.g. a glitch on an I/O port) a digital filter can be enabled using
Non-Recoverable Fault Input x Filter Value bits in the Driver Control register (DRVCTRL.FILTERVALn). Therefore, the
event detection is synchronous, and event action is delayed by the selected digital filter value clock cycles.
When the Fault Detection on Debug Break Detection bit in Debug Control register (DGBCTRL.FDDBD) is written
to '1', a non-recoverable Debug Faults State and an interrupt (DFS) is generated when the system goes in debug
operation.
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PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
In RAMP2, RAMP2A, or DSBOTH operation, when the Lock Update bit in the Control B register is set by writing
CTRLBSET.LUPD=1 and the ramp index or counter direction changes, a non-recoverable Update Fault State and the
respective interrupt (UFS) are generated.
34.6.3.7 Waveform Extension
Figure 34-33 shows a schematic diagram of actions of the four optional units that follow the recoverable fault stage
on a port pin pair: Output Matrix (OTMX), Dead-Time Insertion (DTI), SWAP and Pattern Generation. The DTI and
SWAP units can be seen as a four port pair slices:
• Slice 0 DTI0 / SWAP0 acting on port pins (WO[0], WO[WO_NUM/2 +0])
• Slice 1 DTI1 / SWAP1 acting on port pins (WO[1], WO[WO_NUM/2 +1])
And more generally:
• Slice n DTIx / SWAPx acting on port pins (WO[x], WO[WO_NUM/2 +x])
Figure 34-33. Waveform Extension Stage Details
WEX
OTMX
DTI
PORTS
SWAP
OTMX[x+WO_NUM/2]
PATTERN
PGV[x+WO_NUM/2]
P[x+WO_NUM/2]
LS
OTMX
DTIx
PGO[x+WO_NUM/2]
DTIxEN
INV[x+WO_NUM/2]
SWAPx
INV[x]
PGO[x]
HS
P[x]
OTMX[x]
PGV[x]
The output matrix (OTMX) unit distributes compare channels, according to the selectable configurations in the table
below.
Table 34-5. Output Matrix Channel Pin Routing Configuration
Value
OTMX[x]
0x0
CC3
CC2
CC1
CC0
CC3
CC2
CC1
CC0
0x1
CC1
CC0
CC1
CC0
CC1
CC0
CC1
CC0
0x2
CC0
CC0
CC0
CC0
CC0
CC0
CC0
CC0
0x3
CC1
CC1
CC1
CC1
CC1
CC1
CC1
CC0
The following comments provide an explanation for each of the four Output Matrix Chanel Pin Routing
Configurations.
:
•
•
•
Configuration 0x0 is the default configuration. The channel location is the default one, and channels are
distributed on outputs modulo the number of channels. Channel 0 is routed to the Output matrix output
OTMX[0], and Channel 1 to OTMX[1]. If there are more outputs than channels, then channel 0 is duplicated
to the Output matrix output OTMX[CC_NUM], channel 1 to OTMX[CC_NUM+1] and so on.
Configuration 0x1 distributes the channels on output modulo half the number of channels. This assigns twice the
number of output locations to the lower channels than the default configuration. This can be used, for example,
to control the four transistors of a full bridge using only two compare channels.
Using pattern generation, some of these four outputs can be overwritten by a constant level, enabling flexible
drive of a full bridge in all quadrant configurations.
Configuration 0x2 distributes compare channel 0 (CC0) to all port pins. With pattern generation, this
configuration can control a stepper motor.
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PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
•
Configuration 0x3 distributes the compare channel CC0 to the first output, and the channel CC1 to all other
outputs. Together with pattern generation and the fault extension, this configuration can control up to seven LED
strings, with a boost stage.
Table
•
34-6. Example: four compare channels on four outputs
Value
OTMX[3]
OTMX[2]
OTMX[1]
OTMX[0]
0x0
CC3
CC2
CC1
CC0
0x1
CC1
CC0
CC1
CC0
0x2
CC0
CC0
CC0
CC0
0x3
CC1
CC1
CC1
CC0
The dead-time insertion (DTI) unit generates OFF time with the non-inverted low side (LS) and inverted high side
(HS) of the wave generator output forced at low level. This OFF time is called dead time. Dead-time insertion ensures
that the LS and HS will never switch simultaneously.
The DTI stage consists of four equal dead-time insertion generators; one for each of the first four compare channels.
Figure 34-34 shows the block diagram of one DTI generator. The four channels have a common register which
controls the dead time, which is independent of high side and low side setting.
Figure 34-34. Dead-Time Generator Block Diagram
DTHS
DTLS
Dead Time Generator
LOAD
EN
Counter
=0
OTMX output
D
"DTLS"
Q
(To PORT)
"DTHS"
Edge Detect
(To PORT)
As shown in Figure 34-35, the 8-bit dead-time counter is decremented by one for each peripheral clock cycle until it
reaches zero. A non-zero counter value will force both the low side and high side outputs into their OFF state. When
the output matrix (OTMX) output changes, the dead-time counter is reloaded according to the edge of the input.
When the output changes from low to high (positive edge) it initiates a counter reload of the DTLS register. When the
output changes from high to low (negative edge) it reloads the DTHS register.
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PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Figure 34-35. Dead-Time Generator Timing Diagram
"dti_cnt"
T
tP
tDTILS
t DTIHS
"OTMX output"
"DTLS"
"DTHS"
The pattern generator unit produces a synchronized bit pattern across the port pins it is connected to. The pattern
generation features are primarily intended for handling the commutation sequence in brushless DC motors (BLDC),
stepper motors, and full bridge control. See also Figure 34-36.
Figure 34-36. Pattern Generator Block Diagram
COUNT
UPDATE
BV
PGEB[7:0]
EN
BV
PGE[7:0]
PGVB[7:0]
EN
SWAP output
PGV[7:0]
WOx[7:0]
As with other double-buffered timer/counter registers, the register update is synchronized to the UPDATE condition
set by the timer/counter waveform generation operation. If synchronization is not required by the application, the
software can simply access directly the PATT.PGE, PATT.PGV bits registers.
34.6.4
Host/Client Operation
Two TCC instances sharing the same GCLK_TCC clock, can be linked to provide more synchronized CC channels.
The operation is enabled by setting the Host Synchronization bit in Control A register (CTRLA.MSYNC) in the Client
instance. When the bit is set, the client TCC instance will synchronize the CC channels to the Host counter.
34.6.5
DMA, Interrupts, and Events
Table 34-7. Module Requests for TCC
Condition
Interrupt
request
Event
output
Overflow / Underflow
Yes
Yes
© 2021 Microchip Technology Inc.
and its subsidiaries
Event input DMA
request
Yes(1)
Datasheet
DMA request is cleared
On DMA acknowledge
DS60001638D-page 638
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
...........continued
Condition
Interrupt
request
Event
output
Event input DMA
request
DMA request is cleared
Channel Compare Match or Yes
Capture
Yes
Yes(2)
For circular buffering: on
DMA acknowledge
For capture channel:
when CCx register is
read
Retrigger
Yes
Yes
Count
Yes
Yes
Capture Overflow Error
Yes
Debug Fault State
Yes
Recoverable Faults
Yes
Non-Recoverable Faults
Yes
TCCx Event 0 input
Yes(4)
TCCx Event 1 input
Yes(5)
Yes(3)
Notes:
1. DMA request set on overflow, underflow or re-trigger conditions.
2. Can perform capture or generate recoverable fault on an event input.
3. In capture or circular modes.
4. On event input, either action can be executed:
– Re-trigger counter
– Control counter direction
– Stop the counter
– Decrement the counter
– Perform period and pulse width capture
– Generate non-recoverable fault
5. On event input, either action can be executed:
– Re-trigger counter
– Increment or decrement counter depending on direction
– Start the counter
– Increment or decrement counter based on direction
– Increment counter regardless of direction
– Generate non-recoverable fault
34.6.5.1 DMA Operation
The TCC can generate the following DMA requests:
Counter
overflow
(OVF)
If the Ones-shot Trigger mode in the control A register (CTRLA.DMAOS) is written to '0', the
TCC generates a DMA request on each cycle when an update condition (overflow, underflow or
re-trigger) is detected.
When an update condition (overflow, underflow or re-trigger) is detected while CTRLA.DMAOS=1,
the TCC generates a DMA trigger on the cycle following the DMA One-Shot Command written to
the Control B register (CTRLBSET.CMD=DMAOS).
In both cases, the request is cleared by hardware on DMA acknowledge.
Channel
Match (MCx)
A DMA request is set only on a compare match if CTRLA.DMAOS=0. The request is cleared by
hardware on DMA acknowledge.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 639
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
When CTRLA.DMAOS=1, the DMA requests are not generated.
Channel
Capture
(MCx)
For a capture channel, the request is set when valid data is present in the CCx register, and cleared
once the CCx register is read.
In this operation mode, the CTRLA.DMAOS bit value is ignored.
DMA Operation with Circular Buffer
When circular buffer operation is enabled, the buffer registers must be written in a correct order and synchronized to
the update times of the timer. The DMA triggers of the TCC provide a way to ensure a safe and correct update of
circular buffers.
Note: Circular buffer are intended to be used with RAMP2, RAMP2A and DSBOTH operation only.
DMA Operation with Circular Buffer in RAMP2 and RAMP2A Mode
When a CCx channel is selected as a circular buffer, the related DMA request is not set on a compare match
detection, but on start of ramp B.
If at least one circular buffer is enabled, the DMA overflow request is conditioned to the start of ramp A with an
effective DMA transfer on previous ramp B (DMA acknowledge).
The update of all circular buffer values for ramp A can be done through a DMA channel triggered on a MC trigger.
The update of all circular buffer values for ramp B, can be done through a second DMA channel triggered by the
overflow DMA request.
Figure 34-37. DMA Triggers in RAMP and RAMP2 Operation Mode and Circular Buffer Enabled
Ramp
Cycle
A
B
N-2
A
B
A
N-1
B
N
"update"
COUNT
ZERO
STATUS.IDX
DMA_CCx_req
DMA Channel i
Update ramp A
DMA_OVF_req
DMA Channel j
Update ramp B
DMA Operation with Circular Buffer in DSBOTH Mode
When a CC channel is selected as a circular buffer, the related DMA request is not set on a compare match
detection, but on start of down-counting phase.
If at least one circular buffer is enabled, the DMA overflow request is conditioned to the start of up-counting phase
with an effective DMA transfer on previous down-counting phase (DMA acknowledge).
When up-counting, all circular buffer values can be updated through a DMA channel triggered by MC trigger. When
down-counting, all circular buffer values can be updated through a second DMA channel, triggered by the OVF DMA
request.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 640
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Figure 34-38. DMA Triggers in DSBOTH Operation Mode and Circular Buffer Enabled
Cycle
N-2
N
N-1
New Parameter Set
Old Parameter Set
"update"
COUNT
ZERO
CTRLB.DIR
DMA_CCx_req
DMA Channel i
Update Rising
DMA_OVF_req
DMA Channel j
Update Rising
34.6.5.2 Interrupts
The TCC has the following interrupt sources:
•
•
•
•
•
•
•
•
•
Overflow/Underflow (OVF)
Retrigger (TRG)
Count (CNT), also refer to the description of EVCTRL.CNTSEL.
Capture Overflow Error (ERR)
Non-Recoverable Update Fault (UFS)
Debug Fault State (DFS)
Recoverable Faults (FAULTn)
Non-recoverable Faults (FAULTx)
Compare Match or Capture Channels (MCx)
These interrupts are asynchronous wake-up sources. See Sleep Mode Entry and Exit Table in PM/Sleep Mode
Controller section for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing
a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the
corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the
interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt
flag is cleared, the interrupt is disabled, or the TCC is reset. See 34.7.12 INTFLAG for details on how to clear
interrupt flags. The TCC has one common interrupt request line for all the interrupt sources. The user must read the
INTFLAG register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt
Controller for more details.
34.6.5.3 Events
The TCC can generate the following output events:
• Overflow/Underflow (OVF)
• Trigger (TRG)
• Counter (CNT) For additional information, refer to EVCTRL.CNTSEL description.
• Compare Match or Capture on compare/capture channels: MCx
Writing a '1' ('0') to an Event Output bit in the Event Control Register (EVCTRL.xxEO) enables (disables) the
corresponding output event. For further information, refer to the EVSYS – Event System.
The TCC can take the following actions on a channel input event (MCx):
• Capture event
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 641
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
•
Generate a recoverable or non-recoverable fault
The TCC can take the following actions on counter Event 1 (TCCx EV1):
• Counter re-trigger
– Not supported with dithering or if RAMP2 operation is used with a prescaler (CTRLA.PRESCALER !=0).
RAMP2 operation can use the re-trigger option only if the counter re-trigger of the counter is synchronized
with the next prescaler clock (CTRLA.PRESCYNC = PRESC).
– If a re-trigger event occurs exactly at the time a Channel Compare Match occurs, the next waveform will
be corrupted. To avoid this issue, use two channels to store two successive CC register values (n and n+1)
and combine the related waveform outputs to provide signal redundancy.
• Counter direction control
• Stop the counter
• Decrement the counter on event
• Period and pulse width capture
• Non-recoverable fault
The TCC can take the following actions on counter Event 0 (TCCx EV0):
• Counter re-trigger
– Not supported with dithering or if RAMP2 operation is used with a prescaler (CTRLA.PRESCALER !=0).
RAMP2 operation can use the re-trigger option only if the counter re-trigger of the counter is synchronized
with the next prescaler clock (CTRLA.PRESCYNC = PRESC).
– If a re-trigger event occurs exactly at the time a Channel Compare Match occurs, the next waveform will
be corrupted. To avoid this issue, use two channels to store two successive CC register values (n and n+1)
and combine the related waveform outputs to provide signal redundancy.
• Count on event (increment or decrement, depending on counter direction)
• Counter start - Start counting on the event rising edge. Further events will not restart the counter; the counter
will keep on counting using prescaled GCLK_TCCx, until it reaches TOP or ZERO, depending on the direction.
• Counter increment on event. This will increment the counter, irrespective of the counter direction.
• Count during active state of an asynchronous event (increment or decrement, depending on counter direction).
In this case, the counter will be incremented or decremented on each cycle of the prescaled clock, as long as
the event is active.
• Non-recoverable fault
The counter Event Actions are available in the Event Control registers (EVCTRL.EVACT0 and EVCTRL.EVACT1).
For additional information, refer to EVCTRL.
Writing a '1' ('0') to an Event Input bit in the Event Control register (EVCTRL.MCEIx or EVCTRL.TCEIx) enables
(disables) the corresponding action on input event. When TCC input events are used, the respective channel path of
the Event System must be configured as Asynchronous path (CHANNELx.PATH = 0x2).
Note: When several events are connected to the TCC, the enabled action will apply for each of the incoming events.
Refer to the EVSYS – Event System for details on how to configure the event system.
34.6.6
Sleep Mode Operation
The TCC can be configured to operate in any sleep mode. To be able to run in standby the RUNSTDBY bit in the
Control A register (CTRLA.RUNSTDBY) must be '1'. The MODULE can in any sleep mode wake up the device using
interrupts or perform actions through the Event System.
When the device is in Standby Sleep mode the DMA is not able to write the CTRLB, STATUS, COUNT, PATT, WAVE,
PER, PERBUF, CC, CCBUF registers. To write these registers with the DMA the device must be in Active mode or
Idle Sleep mode.
34.6.7
Debug Operation
When the CPU is halted in Debug mode, this peripheral will halt normal operation. This peripheral can be forced to
continue operation during debugging. Refer to the Debug Control (DBGCTRL) register for details.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 642
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.6.8
Synchronization
Some registers (or bit fields within a register) require synchronization when read and/or written. Synchronization
is denoted by the "Read-Synchronized" (or Read-Synchronized Bits) and/or "Write-Synchronized" (or WriteSynchronized Bits) property in each individual register description. For more details, refer to Register
Synchronization.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 643
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7
Register Summary
Offset
Name
0x00
CTRLA
0x04
0x05
0x06
...
0x07
CTRLBCLR
CTRLBSET
0x08
0x0C
Bit Pos.
7:0
15:8
23:16
31:24
7:0
7:0
0x14
0x18
0x1C
...
0x1D
0x1E
0x1F
MSYNC
DMAOS
SYNCBUSY
FCTRLA
FCTRLB
WEXCTRL
DRVCTRL
DBGCTRL
Reserved
EVCTRL
0x24
INTENCLR
0x30
4
3
RESOLUTION[1:0]
PRESCSYNC[1:0]
2
0
ENABLE
SWRST
PRESCALER[2:0]
RUNSTDBY
CPTEN3
IDXCMD[1:0]
IDXCMD[1:0]
1
CPTEN2
ONESHOT
ONESHOT
CPTEN1
LUPD
LUPD
CPTEN0
DIR
DIR
7:0
15:8
23:16
31:24
7:0
15:8
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
PER
RESTART
BLANKPRES
C
WAVE
PATT
BLANK[1:0]
COUNT
STATUS
CC3
CTRLB
CC2
ENABLE
CC1
SWRST
CC0
QUAL
KEEP
CAPTURE[2:0]
SRC[1:0]
CHSEL[1:0]
HALT[1:0]
BLANKVAL[7:0]
FILTERVAL[3:0]
RESTART
BLANKPRES
C
BLANK[1:0]
QUAL
KEEP
CAPTURE[2:0]
SRC[1:0]
CHSEL[1:0]
HALT[1:0]
BLANKVAL[7:0]
FILTERVAL[3:0]
NRE7
NRV7
INVEN7
DTIEN3
DTLS[7:0]
DTHS[7:0]
NRE4
NRE3
NRV4
NRV3
INVEN4
INVEN3
NRE6
NRE5
NRV6
NRV5
INVEN6
INVEN5
FILTERVAL1[3:0]
DTIEN2
OTMX[1:0]
DTIEN1
DTIEN0
NRE2
NRE1
NRV2
NRV1
INVEN2
INVEN1
FILTERVAL0[3:0]
NRE0
NRV0
INVEN0
Reserved
0x20
0x2C
5
CMD[2:0]
CMD[2:0]
7:0
FDDBD
7:0
0x28
6
Reserved
23:16
31:24
7:0
0x10
7
INTENSET
INTFLAG
STATUS
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
CNTSEL[1:0]
TCEI0
TCEI1
FAULT1
FAULT1
FAULT1
PERBUFV
FAULT1
© 2021 Microchip Technology Inc.
and its subsidiaries
FAULT0
FAULT0
FAULT0
FAULT0
EVACT1[2:0]
TCINV0
TCINV1
FAULTB
FAULTA
FAULTB
FAULTA
FAULTB
FAULTA
PATTBUFV
FAULTB
SLAVE
FAULTA
Datasheet
DBGRUN
EVACT0[2:0]
TRGEO
MCEI1
MCEO1
TRG
OVFEO
MCEI0
MCEO0
OVF
MC1
MC0
MCEI3
MCEO3
ERR
DFS
MC3
CNTEO
MCEI2
MCEO2
CNT
UFS
MC2
ERR
DFS
MC3
CNT
UFS
MC2
TRG
OVF
MC1
MC0
ERR
DFS
MC3
CNT
UFS
MC2
TRG
OVF
MC1
MC0
DFS
FAULT1IN
CCBUFV3
CMP3
UFS
FAULT0IN
CCBUFV2
CMP2
IDX
FAULTBIN
CCBUFV1
CMP1
STOP
FAULTAIN
CCBUFV0
CMP0
DS60001638D-page 644
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
...........continued
Offset
Name
0x34
COUNT
0x38
PATT
0x3A
...
0x3B
Reserved
0x3C
0x40
0x44
0x48
0x4C
WAVE
PER
CC0
CC1
CC2
0x50
CC3
0x54
...
0x63
Reserved
0x64
PATTBUF
0x66
...
0x6B
Reserved
0x6C
0x70
0x74
0x78
PERBUF
CCBUF0
CCBUF1
CCBUF2
Bit Pos.
7
6
5
4
3
7:0
15:8
COUNT[7:0]
COUNT[15:8]
23:16
31:24
7:0
15:8
COUNT[23:16]
PGE7
PGV7
PGE6
PGV6
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
CIPEREN
7:0
15:8
PGEB7
PGVB7
PGE5
PGV5
PGE4
PGV4
PGE3
PGV3
2
1
0
PGE2
PGV2
PGE1
PGV1
PGE0
PGV0
RAMP[1:0]
CICCEN3
CICCEN2
POL3
POL2
SWAP3
SWAP2
DITHER[5:0]
PER[9:2]
PER[17:10]
PER[1:0]
CC[1:0]
WAVEGEN[2:0]
CICCEN1
CICCEN0
POL1
POL0
SWAP1
SWAP0
DITHER[5:0]
CC[9:2]
CC[17:10]
CC[1:0]
DITHER[5:0]
CC[9:2]
CC[17:10]
CC[1:0]
DITHER[5:0]
CC[9:2]
CC[17:10]
CC[1:0]
DITHER[5:0]
CC[9:2]
CC[17:10]
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
© 2021 Microchip Technology Inc.
and its subsidiaries
PGEB6
PGVB6
PGEB5
PGVB5
PGEB4
PGVB4
PGEB3
PGVB3
PGEB2
PGVB2
PERBUF[1:0]
DITHERBUF[5:0]
PERBUF[9:2]
PERBUF[17:10]
CCBUF[1:0]
DITHERBUF[5:0]
CCBUF[9:2]
CCBUF[17:10]
CCBUF[1:0]
DITHERBUF[5:0]
CCBUF[9:2]
CCBUF[17:10]
CCBUF[1:0]
DITHERBUF[5:0]
CCBUF[9:2]
CCBUF[17:10]
Datasheet
PGEB1
PGVB1
PGEB0
PGVB0
DS60001638D-page 645
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
...........continued
Offset
Name
Bit Pos.
0x7C
CCBUF3
7:0
15:8
23:16
31:24
7
© 2021 Microchip Technology Inc.
and its subsidiaries
6
CCBUF[1:0]
5
4
3
2
1
0
DITHERBUF[5:0]
CCBUF[9:2]
CCBUF[17:10]
Datasheet
DS60001638D-page 646
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.1
Control A
Name:
Offset:
Reset:
Property:
Bit
CTRLA
0x00
0x00000000
PAC Write-Protection, Enable-Protected, Write-Synchronized (ENABLE, SWRST)
31
30
29
28
27
CPTEN3
R/W
0
26
CPTEN2
R/W
0
25
CPTEN1
R/W
0
24
CPTEN0
R/W
0
23
DMAOS
R/W
0
22
21
20
19
18
17
16
15
MSYNC
R/W
0
14
11
RUNSTDBY
R/W
0
10
8
R/W
0
9
PRESCALER[2:0]
R/W
0
R/W
0
3
2
1
ENABLE
R/W
0
0
SWRST
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
Access
Reset
13
12
PRESCSYNC[1:0]
R/W
R/W
0
0
6
5
RESOLUTION[1:0]
R/W
R/W
0
0
4
Bits 24, 25, 26, 27 – CPTENx Capture Channel x Enable
These bits are used to select the capture or compare operation on channel x.
Writing a '1' to CPTENx enables capture on channel x.
Writing a '0' to CPTENx disables capture on channel x.
Bit 23 – DMAOS DMA One-Shot Trigger Mode
This bit enables the DMA One-shot Trigger Mode.
Writing a '1' to this bit will generate a DMA trigger on TCC cycle following a TCC_CTRLBSET_CMD_DMAOS
command.
Writing a '0' to this bit will generate DMA triggers on each TCC cycle.
This bit is not synchronized.
Bit 15 – MSYNC Host Synchronization (only for TCC client instance)
This bit must be set if the TCC counting operation must be synchronized on its Host TCC.
This bit is not synchronized.
Value
Description
0
The TCC controls its own counter.
1
The counter is controlled by its Host TCC.
Bits 13:12 – PRESCSYNC[1:0] Prescaler and Counter Synchronization
These bits select if on re-trigger event, the Counter is cleared or reloaded on either the next GCLK_TCCx clock, or on
the next prescaled GCLK_TCCx clock. It is also possible to reset the prescaler on re-trigger event.
These bits are not synchronized.
Value
0x0
Name
GCLK
© 2021 Microchip Technology Inc.
and its subsidiaries
Description
Counter Reloaded
Prescaler
Reload or reset Counter on next GCLK
-
Datasheet
DS60001638D-page 647
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
...........continued
Value
Name
0x1
PRESC
0x2
0x3
RESYNC
Reserved
Description
Counter Reloaded
Prescaler
Reload or reset Counter on next
prescaler clock
Reload or reset Counter on next GCLK
Reset prescaler counter
Bit 11 – RUNSTDBY Run in Standby
This bit is used to keep the TCC running in standby mode.
This bit is not synchronized.
Value
Description
0
The TCC is halted in standby.
1
The TCC continues to run in standby.
Bits 10:8 – PRESCALER[2:0] Prescaler
These bits select the Counter prescaler factor.
These bits are not synchronized.
Value
Name
Description
0x0
DIV1
Prescaler: GCLK_TCC
0x1
DIV2
Prescaler: GCLK_TCC/2
0x2
DIV4
Prescaler: GCLK_TCC/4
0x3
DIV8
Prescaler: GCLK_TCC/8
0x4
DIV16
Prescaler: GCLK_TCC/16
0x5
DIV64
Prescaler: GCLK_TCC/64
0x6
DIV256
Prescaler: GCLK_TCC/256
0x7
DIV1024
Prescaler: GCLK_TCC/1024
Bits 6:5 – RESOLUTION[1:0] Dithering Resolution
These bits increase the TCC resolution by enabling the dithering options.
These bits are not synchronized.
Table 34-8. Dithering
Value Name Description
0x0
0x1
0x2
0x3
NONE
DITH4
DITH5
DITH6
The dithering is disabled.
Dithering is done every 16 PWM frames. PER[3:0] and CCx[3:0] contain dithering pattern selection.
Dithering is done every 32 PWM frames. PER[4:0] and CCx[4:0] contain dithering pattern selection.
Dithering is done every 64 PWM frames. PER[5:0] and CCx[5:0] contain dithering pattern selection.
Bit 1 – ENABLE Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the SYNCBUSY register
(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
Value
Description
0
The peripheral is disabled.
1
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the TCC (except DBGCTRL) to their initial state, and the TCC will be
disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be
discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY.SWRST will both be cleared when the reset is complete.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 648
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Value
0
1
Description
There is no reset operation ongoing.
The reset operation is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 649
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.2
Control B Clear
Name:
Offset:
Reset:
Property:
CTRLBCLR
0x04
0x00
PAC Write-Protection, Write-Synchronized, Read-Synchronized
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Control B Set (CTRLBSET) register.
Bit
Access
Reset
7
R/W
0
6
CMD[2:0]
R/W
0
5
R/W
0
4
3
IDXCMD[1:0]
R/W
R/W
0
0
2
ONESHOT
R/W
0
1
LUPD
R/W
0
0
DIR
R/W
0
Bits 7:5 – CMD[2:0] TCC Command
These bits can be used for software control of re-triggering and stop commands of the TCC. When a command
has been executed, the CMD bit field will read back zero. The commands are executed on the next prescaled
GCLK_TCC clock cycle.
Writing zero to this bit group has no effect.
Writing a value different from 0x0 to this bit field bits will clear the pending command.
Bits 4:3 – IDXCMD[1:0] Ramp Index Command
These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation. On timer/counter
update condition, the command is executed, the IDX flag in STATUS register is updated and the IDXCMD command
is cleared.
Writing zero to these bits has no effect.
Writing a value different from 0x0 to this bit field bits will clear the pending command.
Value
Name
Description
0x0
DISABLE
DISABLE Command disabled: IDX toggles between cycles A and B
0x1
SET
Set IDX: cycle B will be forced in the next cycle
0x2
CLEAR
Clear IDX: cycle A will be forced in next cycle
0x3
HOLD
Hold IDX: the next cycle will be the same as the current cycle.
Bit 2 – ONESHOT One-Shot
This bit controls one-shot operation of the TCC. When one-shot operation is enabled, the TCC will stop counting on
the next overflow/underflow condition or on a stop command.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will disable the one-shot operation.
Value
Description
0
The TCC will update the counter value on overflow/underflow condition and continue operation.
1
The TCC will stop counting on the next underflow/overflow condition.
Bit 1 – LUPD Lock Update
This bit controls the update operation of the TCC buffered registers.
When CTRLB.LUPD is cleared, the hardware UPDATE registers with value from their buffered registers is enabled.
This bit has no effect when input capture operation is enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will enable the registers updates on hardware UPDATE condition.
Value
Description
0
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are copied into the
corresponding CCx, PER, PGV, PGO and SWAPx registers on hardware update condition.
1
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are not copied into the
corresponding CCx, PER, PGV, PGO and SWAPx registers on hardware update condition.
Bit 0 – DIR Counter Direction
This bit is used to change the direction of the counter.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 650
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Writing a '0' to this bit has no effect
Writing a '1' to this bit will clear the bit and make the counter count up.
Value
Description
0
The timer/counter is counting up (incrementing).
1
The timer/counter is counting down (decrementing).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 651
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.3
Control B Set
Name:
Offset:
Reset:
Property:
CTRLBSET
0x05
0x00
PAC Write-Protection, Write-Synchronized, Read-Synchronized
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Control B Clear (CTRLBCLR) register.
Bit
Access
Reset
7
R/W
0
6
CMD[2:0]
R/W
0
5
R/W
0
4
3
IDXCMD[1:0]
R/W
R/W
0
0
2
ONESHOT
R/W
0
1
LUPD
R/W
0
0
DIR
R/W
0
Bits 7:5 – CMD[2:0] TCC Command
These bits can be used for software control of re-triggering and stop commands of the TCC. When a command has
been executed, the CMD bit field will be read back as zero. The commands are executed on the next prescaled
GCLK_TCC clock cycle.
Writing zero to this bit group has no effect
Writing a value different from 0x0 to this bit field will issue a command for execution.
Important: This command requires synchronization before being executed. A valid sequence is:
• Issue CMD command (CTRLBSET.CMD = command)
• Wait for CMD synchronization (SYNCBUSY.CTRLB = 0)
• Wait for CMD read back as zero (CTRLBSET.CMD = 0)
Value
0x0
0x1
0x2
0x3
0x4
0x5
Name
NONE
RETRIGGER
STOP
UPDATE
READSYNC
DMAOS
Description
No action
Force start, restart or retrigger
Force stop
Force update of double buffered registers
Force a read synchronization of COUNT
One-shot DMA trigger
Bits 4:3 – IDXCMD[1:0] Ramp Index Command
These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation. On timer/counter
update condition, the command is executed, the IDX flag in STATUS register is updated and the IDXCMD command
is cleared.
Writing a zero to these bits has no effect.
Writing a valid value to these bits will set a command.
Value
Name
Description
0x0
DISABLE
Command disabled: IDX toggles between cycles A and B
0x1
SET
Set IDX: cycle B will be forced in the next cycle
0x2
CLEAR
Clear IDX: cycle A will be forced in next cycle
0x3
HOLD
Hold IDX: the next cycle will be the same as the current cycle.
Bit 2 – ONESHOT One-Shot
This bit controls one-shot operation of the TCC. When in one-shot operation, the TCC will stop counting on the next
overflow/underflow condition or a stop command.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will enable the one-shot operation.
Value
Description
0
The TCC will count continuously.
1
The TCC will stop counting on the next underflow/overflow condition.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 652
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Bit 1 – LUPD Lock Update
This bit controls the update operation of the TCC buffered registers.
When CTRLB.LUPD is set, the hardware UPDATE registers with value from their buffered registers is disabled.
Disabling the update ensures that all buffer registers are valid before a hardware update is performed. After all the
buffer registers are loaded correctly, the buffered registers can be unlocked.
This bit has no effect when input capture operation is enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will disable the registers updates on hardware UPDATE condition.
Value
Description
0
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are copied into the
corresponding CCx, PER, PGV, PGO and SWAPx registers on hardware update condition.
1
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are not copied into CCx, PER,
PGV, PGO and SWAPx registers on hardware update condition.
Bit 0 – DIR Counter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will clear the bit and make the counter count up.
Value
Description
0
The timer/counter is counting up (incrementing).
1
The timer/counter is counting down (decrementing).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 653
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.4
Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x08
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
CC3
R
0
10
CC2
R
0
9
CC1
R
0
8
CC0
R
0
7
PER
R
0
6
WAVE
R
0
5
PATT
R
0
4
COUNT
R
0
3
STATUS
R
0
2
CTRLB
R
0
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 8, 9, 10, 11 – CC Compare/Capture Channel x Synchronization Busy
This bit is cleared when the synchronization of Compare/Capture Channel x register between the clock domains is
complete.
This bit is set when the synchronization of Compare/Capture Channel x register between clock domains is started.
CCx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to each
TCC feature list.
Bit 7 – PER PER Synchronization Busy
This bit is cleared when the synchronization of PER register between the clock domains is complete.
This bit is set when the synchronization of PER register between clock domains is started.
Bit 6 – WAVE WAVE Synchronization Busy
This bit is cleared when the synchronization of WAVE register between the clock domains is complete.
This bit is set when the synchronization of WAVE register between clock domains is started.
Bit 5 – PATT PATT Synchronization Busy
This bit is cleared when the synchronization of PATTERN register between the clock domains is complete.
This bit is set when the synchronization of PATTERN register between clock domains is started.
Bit 4 – COUNT COUNT Synchronization Busy
This bit is cleared when the synchronization of COUNT register between the clock domains is complete.
This bit is set when the synchronization of COUNT register between clock domains is started.
Bit 3 – STATUS STATUS Synchronization Busy
This bit is cleared when the synchronization of STATUS register between the clock domains is complete.
This bit is set when the synchronization of STATUS register between clock domains is started.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 654
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Bit 2 – CTRLB CTRLB Synchronization Busy
This bit is cleared when the synchronization of CTRLBSET or CTRLBCLR register between the clock domains is
complete.
This bit is set when the synchronization of CTRLBSET or CTRLBCLR register between clock domains is started.
Bit 1 – ENABLE ENABLE Synchronization Busy
This bit is cleared when the synchronization of ENABLE bit between the clock domains is complete.
This bit is set when the synchronization of ENABLE bit between clock domains is started.
Bit 0 – SWRST SWRST Synchronization Busy
This bit is cleared when the synchronization of SWRST bit between the clock domains is complete.
This bit is set when the synchronization of SWRST bit between clock domains is started.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 655
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.5
Fault Control A and B
Name:
Offset:
Reset:
Property:
Bit
FCTRLA, FCTRLB
0x0C + n*0x04 [n=0..1]
0x00000000
PAC Write-Protection, Enable-Protected
31
30
29
28
Access
Reset
23
22
21
R/W
0
R/W
0
R/W
0
14
13
CAPTURE[2:0]
R/W
0
Bit
15
BLANKPRESC
Access
R/W
Reset
0
Bit
Access
Reset
26
25
FILTERVAL[3:0]
R/W
R/W
0
0
R/W
0
Bit
Access
Reset
27
7
RESTART
R/W
0
R/W
0
6
5
BLANK[1:0]
R/W
0
R/W
0
20
19
BLANKVAL[7:0]
R/W
R/W
0
0
12
11
24
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
CHSEL[1:0]
HALT[1:0]
R/W
0
R/W
0
R/W
0
R/W
0
4
QUAL
R/W
0
3
KEEP
R/W
0
2
1
R/W
0
0
SRC[1:0]
R/W
0
R/W
0
Bits 27:24 – FILTERVAL[3:0] Recoverable Fault n Filter Value
These bits define the filter value applied on MCEx (x=0,1) event input line. The value must be set to zero when MCEx
event is used as synchronous event.
Bits 23:16 – BLANKVAL[7:0] Recoverable Fault n Blanking Value
These bits determine the duration of the blanking of the fault input source. Activation and edge selection of the blank
filtering are done by the BLANK bits (FCTRLn.BLANK).
When enabled, the fault input source is internally disabled for BLANKVAL* prescaled GCLK_TCC periods after the
detection of the waveform edge.
Bit 15 – BLANKPRESC Recoverable Fault n Blanking Value Prescaler
This bit enables a factor 64 prescaler factor on used as base frequency of the BLANKVAL value.
Value
Description
0
Blank time is BLANKVAL* prescaled GCLK_TCCx.
1
Blank time is BLANKVAL* 64 * prescaled GCLK_TCCx.
Bits 14:12 – CAPTURE[2:0] Recoverable Fault n Capture Action
These bits select the capture and Fault n interrupt/event conditions.
When using advanced capture functions like CAPTMIN, CAPTMAX, LOCMIN, LOCMAX and DERIV0, standard
capture functions (CAPT) must be assigned to the lower CCx channels when used. See the example below.
Example: CC[0] = CAPT, CC[1] = CAPT, CC[2] = CAPTMIN, CC[3] = CAPTMAX.
Table 34-9. Fault n Capture Action
Value
Name
0x0
0x1
DISABLE
CAPT
Description
Capture on valid recoverable Fault n is disabled
On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each new captured value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 656
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
...........continued
Value
Name
0x2
CAPTMIN
0x3
0x4
0x5
0x6
0x7
Description
On rising edge of a valid recoverable Fault n, capture counter value on channel selected
by CHSEL[1:0], if COUNT value is lower than the last stored capture value (CC).
INTFLAG.FAULTn flag rises on each local minimum detection.
CAPTMAX On rising edge of a valid recoverable Fault n, capture counter value on channel selected
by CHSEL[1:0], if COUNT value is higher than the last stored capture value (CC).
INTFLAG.FAULTn flag rises on each local maximun detection.
LOCMIN
On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local minimum value detection.
LOCMAX On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local maximun detection.
DERIV0
On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local maximun or minimum detection.
CAPTMARK Capture with ramp index as MSB value.
Bits 11:10 – CHSEL[1:0] Recoverable Fault n Capture Channel
These bits select the channel for capture operation triggered by recoverable Fault n.
Value
Name
Description
0x0
CC0
Capture value stored into CC0
0x1
CC1
Capture value stored into CC1
0x2
CC2
Capture value stored into CC2
0x3
CC3
Capture value stored into CC3
Bits 9:8 – HALT[1:0] Recoverable Fault n Halt Operation
These bits select the halt action for recoverable Fault n.
Value
Name
Description
0x0
DISABLE
Halt action disabled
0x1
HW
Hardware halt action
0x2
SW
Software halt action
0x3
NR
Non-recoverable fault
Bit 7 – RESTART Recoverable Fault n Restart
Setting this bit enables restart action for Fault n.
Value
Description
0
Fault n restart action is disabled.
1
Fault n restart action is enabled.
Bits 6:5 – BLANK[1:0] Recoverable Fault n Blanking Operation
These bits, select the blanking start point for recoverable Fault n.
Value
Name
Description
0x0
START
Blanking applied from start of the Ramp period
0x1
RISE
Blanking applied from rising edge of the waveform output
0x2
FALL
Blanking applied from falling edge of the waveform output
0x3
BOTH
Blanking applied from each toggle of the waveform output
Bit 4 – QUAL Recoverable Fault n Qualification
Setting this bit enables the recoverable Fault n input qualification.
Value
Description
0
The recoverable Fault n input is not disabled on CMPx value condition.
1
The recoverable Fault n input is disabled when output signal is at inactive level (CMPx == 0).
Bit 3 – KEEP Recoverable Fault n Keep
Setting this bit enables the Fault n keep action.
Value
Description
0
The Fault n state is released as soon as the recoverable Fault n is released.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 657
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Value
1
Description
The Fault n state is released at the end of TCC cycle.
Bits 1:0 – SRC[1:0] Recoverable Fault n Source
These bits select the TCC event input for recoverable Fault n.
Event system channel connected to MCEx event input, must be configured to route the event asynchronously, when
used as a recoverable Fault n input.
Value
Name
Description
0x0
DISABLE
Fault input disabled
0x1
ENABLE
MCEx (x=0,1) event input
0x2
INVERT
Inverted MCEx (x=0,1) event input
0x3
ALTFAULT
Alternate fault (A or B) state at the end of the previous period.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 658
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.6
Waveform Extension Control
Name:
Offset:
Reset:
Property:
Bit
31
WEXCTRL
0x14
0x00000000
PAC Write-Protection, Enable-Protected
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
DTHS[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
DTLS[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
DTIEN3
R/W
0
10
DTIEN2
R/W
0
9
DTIEN1
R/W
0
8
DTIEN0
R/W
0
7
6
5
4
3
2
1
0
Access
Reset
Bit
OTMX[1:0]
Access
Reset
R/W
0
R/W
0
Bits 31:24 – DTHS[7:0] Dead-Time High Side Outputs Value
This register holds the number of GCLK_TCC clock cycles for the dead-time high side.
Bits 23:16 – DTLS[7:0] Dead-time Low Side Outputs Value
This register holds the number of GCLK_TCC clock cycles for the dead-time low side.
Bits 8, 9, 10, 11 – DTIEN Dead-time Insertion Generator x Enable
Setting any of these bits enables the dead-time insertion generator for the corresponding output matrix. This will
override the output matrix [x] and [x+WO_NUM/2], with the low side and high side waveform respectively.
Value
Description
0
No dead-time insertion override.
1
Dead time insertion override on signal outputs[x] and [x+WO_NUM/2], from matrix outputs[x] signal.
Bits 1:0 – OTMX[1:0] Output Matrix
These bits define the matrix routing of the TCC waveform generation outputs to the port pins, according to Table
34-5.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 659
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.7
Driver Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
R/W
0
DRVCTRL
0x18
0x00000000
PAC Write-Protection, Enable-Protected
30
29
FILTERVAL1[3:0]
R/W
R/W
0
0
28
27
R/W
0
R/W
0
26
25
FILTERVAL0[3:0]
R/W
R/W
0
0
24
R/W
0
23
INVEN7
R/W
0
22
INVEN6
R/W
0
21
INVEN5
R/W
0
20
INVEN4
R/W
0
19
INVEN3
R/W
0
18
INVEN2
R/W
0
17
INVEN1
R/W
0
16
INVEN0
R/W
0
15
NRV7
R/W
0
14
NRV6
R/W
0
13
NRV5
R/W
0
12
NRV4
R/W
0
11
NRV3
R/W
0
10
NRV2
R/W
0
9
NRV1
R/W
0
8
NRV0
R/W
0
7
NRE7
R/W
0
6
NRE6
R/W
0
5
NRE5
R/W
0
4
NRE4
R/W
0
3
NRE3
R/W
0
2
NRE2
R/W
0
1
NRE1
R/W
0
0
NRE0
R/W
0
Bits 31:28 – FILTERVAL1[3:0] Non-Recoverable Fault Input 1 Filter Value
These bits define the filter value applied on TCE1 event input line. When the TCE1 event input line is configured as a
synchronous event, this value must be 0x0.
Bits 27:24 – FILTERVAL0[3:0] Non-Recoverable Fault Input 0 Filter Value
These bits define the filter value applied on TCE0 event input line. When the TCE0 event input line is configured as a
synchronous event, this value must be 0x0.
Bits 16, 17, 18, 19, 20, 21, 22, 23 – INVEN Waveform Output x Inversion
These bits are used to select inversion on the output of channel x.
Writing a '1' to INVENx inverts output from WO[x].
Writing a '0' to INVENx disables inversion of output from WO[x].
Bits 8, 9, 10, 11, 12, 13, 14, 15 – NRV NRVx Non-Recoverable State x Output Value
These bits define the value of the enabled override outputs, under non-recoverable fault condition.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – NRE Non-Recoverable State x Output Enable
These bits enable the override of individual outputs by NRVx value, under non-recoverable fault condition.
Value
Description
0
Non-recoverable fault tri-state the output.
1
Non-recoverable faults set the output to NRVx level.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 660
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.8
Debug control
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x1E
0x00
PAC Write-Protection
6
5
4
3
Access
Reset
2
FDDBD
R/W
0
1
0
DBGRUN
R/W
0
Bit 2 – FDDBD Fault Detection on Debug Break Detection
This bit is not affected by software reset and should not be changed by software while the TCC is enabled.
By default this bit is zero, and the on-chip debug (OCD) fault protection is disabled. When this bit is written to ‘1’,
OCD break request from the OCD system will trigger non-recoverable fault. When this bit is set, OCD fault protection
is enabled and OCD break request from the OCD system will trigger a non-recoverable fault.
Value
Description
0
No faults are generated when TCC is halted in debug mode.
1
A non recoverable fault is generated and FAULTD flag is set when TCC is halted in debug mode.
Bit 0 – DBGRUN Debug Running State
This bit is affected by system software reset and should not be changed by software while the TCC is enabled.
Value
Description
0
The TCC is halted when the device is halted in debug mode.
1
The TCC continues normal operation when the device is halted in debug mode.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 661
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.9
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x20
0x00000000
PAC Write-Protection, Enable-Protected
31
30
29
28
27
MCEO3
R/W
0
26
MCEO2
R/W
0
25
MCEO1
R/W
0
24
MCEO0
R/W
0
23
22
21
20
19
MCEI3
R/W
0
18
MCEI2
R/W
0
17
MCEI1
R/W
0
16
MCEI0
R/W
0
15
TCEI1
R/W
0
14
TCEI0
R/W
0
13
TCINV1
R/W
0
12
TCINV0
R/W
0
11
10
CNTEO
R/W
0
9
TRGEO
R/W
0
8
OVFEO
R/W
0
5
4
EVACT1[2:0]
R/W
0
3
2
0
R/W
0
R/W
0
1
EVACT0[2:0]
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
6
CNTSEL[1:0]
R/W
R/W
0
0
R/W
0
R/W
0
Bits 24, 25, 26, 27 – MCEO Match or Capture Channel x Event Output Enable
These bits control if the match/capture event on channel x is enabled and will be generated for every match or
capture.
Value
Description
0
Match/capture x event is disabled and will not be generated.
1
Match/capture x event is enabled and will be generated for every compare/capture on channel x.
Bits 16, 17, 18, 19 – MCEI Match or Capture Channel x Event Input Enable
These bits indicate if the match/capture x incoming event is enabled
These bits are used to enable match or capture input events to the CCx channel of TCC.
Value
Description
0
Incoming events are disabled.
1
Incoming events are enabled.
Bits 14, 15 – TCEI Timer/Counter Event Input x Enable
This bit is used to enable input event x to the TCC.
Value
Description
0
Incoming event x is disabled.
1
Incoming event x is enabled.
Bits 12, 13 – TCINV Timer/Counter Event x Invert Enable
This bit inverts the event x input.
Value
Description
0
Input event source x is not inverted.
1
Input event source x is inverted.
Bit 10 – CNTEO Timer/Counter Event Output Enable
This bit is used to enable the counter cycle event. When enabled, an event will be generated on begin or end of
counter cycle depending of CNTSEL[1:0] settings.
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and its subsidiaries
Datasheet
DS60001638D-page 662
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Value
0
1
Description
Counter cycle output event is disabled and will not be generated.
Counter cycle output event is enabled and will be generated depend of CNTSEL[1:0] value.
Bit 9 – TRGEO Retrigger Event Output Enable
This bit is used to enable the counter retrigger event. When enabled, an event will be generated when the counter
retriggers operation.
Value
Description
0
Counter retrigger event is disabled and will not be generated.
1
Counter retrigger event is enabled and will be generated for every counter retrigger.
Bit 8 – OVFEO Overflow/Underflow Event Output Enable
This bit is used to enable the overflow/underflow event. When enabled an event will be generated when the counter
reaches the TOP or the ZERO value.
Value
Description
0
Overflow/underflow counter event is disabled and will not be generated.
1
Overflow/underflow counter event is enabled and will be generated for every counter overflow/
underflow.
Bits 7:6 – CNTSEL[1:0] Timer/Counter Interrupt and Event Output Selection
These bits define on which part of the counter cycle the counter event output is generated.
Value
Name
Description
0x0
BEGIN
An interrupt/event is generated at begin of each counter cycle
0x1
END
An interrupt/event is generated at end of each counter cycle
0x2
BETWEEN An interrupt/event is generated between each counter cycle.
0x3
BOUNDARY An interrupt/event is generated at begin of first counter cycle, and end of last counter
cycle.
Bits 5:3 – EVACT1[2:0] Timer/Counter Event Input 1 Action
These bits define the action the TCC will perform on TCEI1 event input.
Value
Name
Description
0x0
OFF
Event action disabled.
0x1
RETRIGGER Start, restart or re-trigger TCC on event (do not use with dithering mode or RAMP2
operation)
0x2
DIR (asynch) Direction control
0x3
STOP
Stop TCC on event
0x4
DEC
Decrement TCC on event
0x5
PPW
Period captured into CC0 Pulse Width on CC1
0x6
PWP
Period captured into CC1 Pulse Width on CC0
0x7
FAULT
Non-recoverable Fault
Bits 2:0 – EVACT0[2:0] Timer/Counter Event Input 0 Action
These bits define the action the TCC will perform on TCEI0 event input 0.
Value
Name
Description
0x0
OFF
Event action disabled.
0x1
RETRIGGER
Start, restart or re-trigger TCC on event (do not use with dithering mode or RAMP2
operation)
0x2
COUNTEV
Count on event. (not a valid selection for waveform generation)
0x3
START
Start TCC on event
0x4
INC
Increment TCC on EVENT
0x5
COUNT (async) Count on active state of asynchronous event (not a valid selection for waveform
generation)
0x6
Reserved
0x7
FAULT
Non-recoverable Fault
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 663
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.10 Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x24
0x00000000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
MC3
R/W
0
18
MC2
R/W
0
17
MC1
R/W
0
16
MC0
R/W
0
15
FAULT1
R/W
0
14
FAULT0
R/W
0
13
FAULTB
R/W
0
12
FAULTA
R/W
0
11
DFS
R/W
0
10
UFS
R/W
0
9
8
7
6
5
4
3
ERR
R/W
0
2
CNT
R/W
0
1
TRG
R/W
0
0
OVF
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 16, 17, 18, 19 – MC Match or Capture Channel x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which
disables the Match or Capture Channel x interrupt.
Value
Description
0
The Match or Capture Channel x interrupt is disabled.
1
The Match or Capture Channel x interrupt is enabled.
Bit 15 – FAULT1 Non-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the
Non-Recoverable Fault x interrupt.
Value
Description
0
The Non-Recoverable Fault x interrupt is disabled.
1
The Non-Recoverable Fault x interrupt is enabled.
Bit 14 – FAULT0 Non-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the
Non-Recoverable Fault x interrupt.
Value
Description
0
The Non-Recoverable Fault x interrupt is disabled.
1
The Non-Recoverable Fault x interrupt is enabled.
Bit 13 – FAULTB Recoverable Fault B Interrupt Enable
Writing a '0' to this bit has no effect.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 664
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Writing a '1' to this bit will clear the Recoverable Fault B Interrupt Disable/Enable bit, which disables the Recoverable
Fault B interrupt.
Value
Description
0
The Recoverable Fault B interrupt is disabled.
1
The Recoverable Fault B interrupt is enabled.
Bit 12 – FAULTA Recoverable Fault A Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Recoverable Fault A Interrupt Disable/Enable bit, which disables the Recoverable
Fault A interrupt.
Value
Description
0
The Recoverable Fault A interrupt is disabled.
1
The Recoverable Fault A interrupt is enabled.
Bit 11 – DFS Non-Recoverable Debug Fault Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Debug Fault State Interrupt Disable/Enable bit, which disables the Debug Fault
State interrupt.
Value
Description
0
The Debug Fault State interrupt is disabled.
1
The Debug Fault State interrupt is enabled.
Bit 10 – UFS Non-Recoverable Update Fault Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Non-Recoverable Update Fault Interrupt Disable/Enable bit, which disables the
Non-Recoverable Update Fault interrupt.
Note: This bit is only available on variant L devices. Refer to the Configuration Summary for more information.
Value
0
1
Description
The Non-Recoverable Update Fault interrupt is disabled.
The Non-Recoverable Update Fault interrupt is enabled.
Bit 3 – ERR Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Error Interrupt Disable/Enable bit, which disables the Compare interrupt.
Value
Description
0
The Error interrupt is disabled.
1
The Error interrupt is enabled.
Bit 2 – CNT Counter Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Counter Interrupt Disable/Enable bit, which disables the Counter interrupt.
Value
Description
0
The Counter interrupt is disabled.
1
The Counter interrupt is enabled.
Bit 1 – TRG Retrigger Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Retrigger Interrupt Disable/Enable bit, which disables the Retrigger interrupt.
Value
Description
0
The Retrigger interrupt is disabled.
1
The Retrigger interrupt is enabled.
Bit 0 – OVF Overflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overflow Interrupt Disable/Enable bit, which disables the Overflow interrupt
request.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 665
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Value
0
1
Description
The Overflow interrupt is disabled.
The Overflow interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 666
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.11 Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x28
0x00000000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
MC3
R/W
0
18
MC2
R/W
0
17
MC1
R/W
0
16
MC0
R/W
0
15
FAULT1
R/W
0
14
FAULT0
R/W
0
13
FAULTB
R/W
0
12
FAULTA
R/W
0
11
DFS
R/W
0
10
UFS
R/W
0
9
8
7
6
5
4
3
ERR
R/W
0
2
CNT
R/W
0
1
TRG
R/W
0
0
OVF
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 16, 17, 18, 19 – MC Match or Capture Channel x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which
enables the Match or Capture Channel x interrupt.
Value
Description
0
The Match or Capture Channel x interrupt is disabled.
1
The Match or Capture Channel x interrupt is enabled.
Bit 15 – FAULT1 Non-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Non-Recoverable Fault x Interrupt Disable/Enable bit, which enables the NonRecoverable Fault x interrupt.
Value
Description
0
The Non-Recoverable Fault x interrupt is disabled.
1
The Non-Recoverable Fault x interrupt is enabled.
Bit 14 – FAULT0 Non-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the
Non-Recoverable Fault x interrupt.
Value
Description
0
The Non-Recoverable Fault x interrupt is disabled.
1
The Non-Recoverable Fault x interrupt is enabled.
Bit 13 – FAULTB Recoverable Fault B Interrupt Enable
Writing a '0' to this bit has no effect.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 667
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Writing a '1' to this bit will set the Recoverable Fault B Interrupt Disable/Enable bit, which enables the Recoverable
Fault B interrupt.
Value
Description
0
The Recoverable Fault B interrupt is disabled.
1
The Recoverable Fault B interrupt is enabled.
Bit 12 – FAULTA Recoverable Fault A Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Recoverable Fault A Interrupt Disable/Enable bit, which enables the Recoverable
Fault A interrupt.
Value
Description
0
The Recoverable Fault A interrupt is disabled.
1
The Recoverable Fault A interrupt is enabled.
Bit 11 – DFS Non-Recoverable Debug Fault Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Debug Fault State Interrupt Disable/Enable bit, which enables the Debug Fault
State interrupt.
Value
Description
0
The Debug Fault State interrupt is disabled.
1
The Debug Fault State interrupt is enabled.
Bit 10 – UFS Non-Recoverable Update Fault Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Non-Recoverable Update Fault Interrupt Disable/Enable bit, which enables the
Non-Recoverable Update Fault interrupt.
Note: This bit is only available on variant L devices. Refer to the Configuration Summary for more information.
Value
0
1
Description
The Non-Recoverable Update Fault interrupt is disabled.
The Non-Recoverable Update Fault interrupt is enabled.
Bit 3 – ERR Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Error Interrupt Disable/Enable bit, which enables the Compare interrupt.
Value
Description
0
The Error interrupt is disabled.
1
The Error interrupt is enabled.
Bit 2 – CNT Counter Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Counter interrupt.
Value
Description
0
The Counter interrupt is disabled.
1
The Counter interrupt is enabled.
Bit 1 – TRG Retrigger Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Retrigger interrupt.
Value
Description
0
The Retrigger interrupt is disabled.
1
The Retrigger interrupt is enabled.
Bit 0 – OVF Overflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Overflow Interrupt Disable/Enable bit, which enables the Overflow interrupt request.
Value
Description
0
The Overflow interrupt is disabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Value
1
Description
The Overflow interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 669
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.12 Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
INTFLAG
0x2C
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
MC3
R/W
0
18
MC2
R/W
0
17
MC1
R/W
0
16
MC0
R/W
0
15
FAULT1
R/W
0
14
FAULT0
R/W
0
13
FAULTB
R/W
0
12
FAULTA
R/W
0
11
DFS
R/W
0
10
UFS
R/W
0
9
8
7
6
5
4
3
ERR
R/W
0
2
CNT
R/W
0
1
TRG
R/W
0
0
OVF
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 16, 17, 18, 19 – MC Match or Capture Channel x Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a match with the compare condition or once CCx register
contain a valid capture value.
Writing a '0' to one of these bits has no effect.
Writing a '1' to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag
In Capture operation, this flag is automatically cleared when CCx register is read.
Bit 15 – FAULT1 Non-Recoverable Fault x Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a Non-Recoverable Fault x occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Non-Recoverable Fault x interrupt flag.
Bit 14 – FAULT0 Non-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the
Non-Recoverable Fault x interrupt.
Value
Description
0
The Non-Recoverable Fault x interrupt is disabled.
1
The Non-Recoverable Fault x interrupt is enabled.
Bit 13 – FAULTB Recoverable Fault B Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Recoverable Fault B interrupt flag.
Bit 12 – FAULTA Recoverable Fault A Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Recoverable Fault B interrupt flag.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 670
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Bit 11 – DFS Non-Recoverable Debug Fault State Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after an Debug Fault State occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Debug Fault State interrupt flag.
Bit 10 – UFS Non-Recoverable Update Fault
This flag is set when the RAMP index changes and the Lock Update bit is set (CTRLBSET.LUPD).
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Non-Recoverable Update Fault interrupt flag.
Note: This bit is only available on variant L devices. Refer to the Configuration Summary for more information.
Bit 3 – ERR Error Interrupt Flag
This flag is set if a new capture occurs on a channel when the corresponding Match or Capture Channel x interrupt
flag is one. In which case there is nowhere to store the new capture.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the error interrupt flag.
Bit 2 – CNT Counter Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a counter event occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the CNT interrupt flag.
Bit 1 – TRG Retrigger Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a counter retrigger occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the re-trigger interrupt flag.
Bit 0 – OVF Overflow Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after an overflow condition occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 671
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.13 Status
Name:
Offset:
Reset:
Property:
STATUS
0x30
0x00000001
-
When writing the STATUS register ensure only 32-bit writes are made.
Bit
31
30
29
28
27
CMP3
R/W
0
26
CMP2
R/W
0
25
CMP1
R/W
0
24
CMP0
R/W
0
23
22
21
20
19
CCBUFV3
R/W
0
18
CCBUFV2
R/W
0
17
CCBUFV1
R/W
0
16
CCBUFV0
R/W
0
15
FAULT1
R/W
0
14
FAULT0
R/W
0
13
FAULTB
R/W
0
12
FAULTA
R/W
0
11
FAULT1IN
R
0
10
FAULT0IN
R
0
9
FAULTBIN
R
0
8
FAULTAIN
R
0
7
PERBUFV
R/W
0
6
5
PATTBUFV
R/W
0
4
SLAVE
R
0
3
DFS
R/W
0
2
UFS
R/W
0
1
IDX
R
0
0
STOP
R
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 24, 25, 26, 27 – CMP Channel x Compare Value
This bit reflects the channel x output compare value.
Value
Description
0
Channel compare output value is 0.
1
Channel compare output value is 1.
Bits 16, 17, 18, 19 – CCBUFV Channel x Compare or Capture Buffer Valid
For a compare channel, this bit is set when a new value is written to the corresponding CCBUFx register. The bit
is cleared either by writing a '1' to the corresponding location when CTRLB.LUPD is set, or automatically on an
UPDATE condition. If clearing this bit manually to force an update of the CCx register, it is necessary to clear the bit
two times successively.
For a capture channel, the bit is set when a valid capture value is stored in the CCBUFx register. The bit is
automatically cleared when the CCx register is read.
Bits 14, 15 – FAULT Non-recoverable Fault x State
This bit is set by hardware as soon as non-recoverable Fault x condition occurs.
This bit is cleared by writing a one to this bit and when the corresponding FAULTxIN status bit is low.
Once this bit is clear, the timer/counter will restart from the last COUNT value. To restart the timer/counter from
BOTTOM, the timer/counter restart command must be executed before clearing the corresponding STATEx bit. For
further details on timer/counter commands, refer to available commands description (34.7.3 CTRLBSET.CMD).
Bit 13 – FAULTB Recoverable Fault B State
This bit is set by hardware as soon as recoverable Fault B condition occurs.
This bit can be clear by hardware when Fault B action is resumed, or by writing a '1' to this bit when the
corresponding FAULTBIN bit is low. If software halt command is enabled (FAULTB.HALT=SW), clearing this bit will
release the timer/counter.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 672
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Bit 12 – FAULTA Recoverable Fault A State
This bit is set by hardware as soon as recoverable Fault A condition occurs.
This bit can be clear by hardware when Fault A action is resumed, or by writing a '1' to this bit when the
corresponding FAULTAIN bit is low. If software halt command is enabled (FAULTA.HALT=SW), clearing this bit will
release the timer/counter.
Bit 11 – FAULT1IN Non-Recoverable Fault 1 Input
This bit is set while an active Non-Recoverable Fault 1 input is present.
Bit 10 – FAULT0IN Non-Recoverable Fault 0 Input
This bit is set while an active Non-Recoverable Fault 0 input is present.
Bit 9 – FAULTBIN Recoverable Fault B Input
This bit is set while an active Recoverable Fault B input is present.
Bit 8 – FAULTAIN Recoverable Fault A Input
This bit is set while an active Recoverable Fault A input is present.
Bit 7 – PERBUFV Period Buffer Valid
This bit is set when a new value is written to the PERBUF register. This bit is automatically cleared by hardware on
UPDATE condition when CTRLB.LUPD is set, or by writing a '1' to this bit. If clearing this bit manually to force an
update of the PER register, it is necessary to clear the bit two times successively.
Bit 5 – PATTBUFV Pattern Generator Value Buffer Valid
This bit is set when a new value is written to the PATTBUF register. This bit is automatically cleared by hardware on
UPDATE condition when CTRLB.LUPD is set, or by writing a '1' to this bit. If clearing this bit manually to force an
update of the PATT register, it is necessary to clear the bit two times successively.
Bit 4 – SLAVE Client
This bit is set when TCC is set in Client mode. This bit follows the CTRLA.MSYNC bit state.
Bit 3 – DFS Debug Fault State
This bit is set by hardware in Debug mode when DDBGCTRL.FDDBD bit is set. The bit is cleared by writing a '1' to
this bit and when the TCC is not in Debug mode.
When the bit is set, the counter is halted and the Waveforms state depend on DRVCTRL.NRE and DRVCTRL.NRV
registers.
Bit 2 – UFS Non-recoverable Update Fault State
This bit is set by hardware when the RAMP index changes and the Lock Update bit is set (CTRLBSET.LUPD). The bit
is cleared by writing a one to this bit.
When the bit is set, the waveforms state depend on DRVCTRL.NRE and DRVCTRL.NRV registers.
Bit 1 – IDX Ramp Index
In RAMP2 and RAMP2A operation, the bit is cleared during the cycle A and set during the cycle B. In RAMP1
operation, the bit always reads zero. For details on ramp operations, refer to 34.6.3.4 Ramp Operations.
Bit 0 – STOP Stop
This bit is set when the TCC is disabled either on a STOP command or on an UPDATE condition when One-Shot
operation mode is enabled (CTRLBSET.ONESHOT=1).
This bit is clear on the next incoming counter increment or decrement.
Value
Description
0
Counter is running.
1
Counter is stopped.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 673
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.14 Counter Value
Name:
Offset:
Reset:
Property:
COUNT
0x34
0x00000000
PAC Write-Protection, Write-Synchronized, Read-Synchronized
Note: Prior to any read access, this register must be synchronized by user by writing the according TCC Command
value to the Control B Set register (CTRLBSET.CMD=READSYNC).
Bit
31
30
29
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
26
25
24
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
20
19
COUNT[23:16]
R/W
R/W
0
0
12
11
COUNT[15:8]
R/W
R/W
0
0
4
3
COUNT[7:0]
R/W
R/W
0
0
Bits 23:0 – COUNT[23:0] Counter Value
These bits hold the value of the counter register.
Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
23:0 (depicted)
23:4
23:5
23:6
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 674
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.15 Pattern
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
PATT
0x38
0x0000
Write-Synchronized
15
PGV7
R/W
0
14
PGV6
R/W
0
13
PGV5
R/W
0
12
PGV4
R/W
0
11
PGV3
R/W
0
10
PGV2
R/W
0
9
PGV1
R/W
0
8
PGV0
R/W
0
7
PGE7
R/W
0
6
PGE6
R/W
0
5
PGE5
R/W
0
4
PGE4
R/W
0
3
PGE3
R/W
0
2
PGE2
R/W
0
1
PGE1
R/W
0
0
PGE0
R/W
0
Bits 8, 9, 10, 11, 12, 13, 14, 15 – PGV Pattern Generation Output Value
This register holds the values of pattern for each waveform output.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PGE Pattern Generation Output Enable
This register holds the enable status of pattern generation for each waveform output. A bit written to '1' will override
the corresponding SWAP output with the corresponding PGVn value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 675
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.16 Waveform
Name:
Offset:
Reset:
Property:
Bit
WAVE
0x3C
0x00000000
Write-Synchronized
31
30
29
28
27
SWAP3
R/W
0
26
SWAP2
R/W
0
25
SWAP1
R/W
0
24
SWAP0
R/W
0
23
22
21
20
19
POL3
R/W
0
18
POL2
R/W
0
17
POL1
R/W
0
16
POL0
R/W
0
15
14
13
12
11
CICCEN3
R/W
0
10
CICCEN2
R/W
0
9
CICCEN1
R/W
0
8
CICCEN0
R/W
0
7
CIPEREN
R/W
0
6
5
4
3
2
1
WAVEGEN[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
RAMP[1:0]
R/W
0
R/W
0
R/W
0
R/W
0
Bits 24, 25, 26, 27 – SWAP Swap DTI Output Pair x
Setting these bits enables output swap of DTI outputs [x] and [x+WO_NUM/2]. Note the DTIxEN settings will not
affect the swap operation.
Bits 16, 17, 18, 19 – POL Channel Polarity x
Setting these bits enables the output polarity in single-slope and dual-slope PWM operations.
Value
Name
Description
0
(single-slope PWM waveform
Compare output is initialized to ~DIR and set to DIR when TCC
generation)
counter matches CCx value
1
(single-slope PWM waveform
Compare output is initialized to DIR and set to ~DIR when TCC
generation)
counter matches CCx value.
0
(dual-slope PWM waveform
Compare output is set to ~DIR when TCC counter matches CCx
generation)
value
1
(dual-slope PWM waveform
Compare output is set to DIR when TCC counter matches CCx
generation)
value.
Bits 8, 9, 10, 11 – CICCEN Circular CC Enable x
Setting this bits enables the compare circular buffer option on channel. When the bit is set, CCx register value is
copied-back into the CCx register on UPDATE condition.
Bit 7 – CIPEREN Circular Period Enable
Setting this bits enable the period circular buffer option. When the bit is set, the PER register value is copied-back
into the PERB register on UPDATE condition.
Bits 5:4 – RAMP[1:0] Ramp Operation
These bits select Ramp operation (RAMP). These bits are not synchronized.
Value
Name
Description
0x0
RAMP1
RAMP1 operation
0x1
RAMP2A
Alternative RAMP2 operation
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 676
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Value
0x2
Name
RAMP2
Description
RAMP2 operation
Bits 2:0 – WAVEGEN[2:0] Waveform Generation Operation
These bits select the waveform generation operation. The settings impact the top value and control if frequency or
PWM waveform generation should be used. These bits are not synchronized.
Value
Name
Description
Operation
Top
Update
Waveform Output
On Match
Waveform Output
On Update
OVFIF/Event
Up Down
0x0
NFRQ
Normal Frequency
PER
TOP/Zero
Toggle
Stable
TOP
Zero
0x1
MFRQ
Match Frequency
CC0
TOP/Zero
Toggle
Stable
TOP
Zero
0x2
NPWM
Normal PWM
PER
TOP/Zero
Set
Clear
TOP
Zero
0x3
Reserved
-
-
-
-
-
TOP
-
0x4
DSCRITICAL
Dual-slope PWM
PER
Zero
~DIR
Stable
–
Zero
0x5
DSBOTTOM
Dual-slope PWM
PER
Zero
~DIR
Stable
–
Zero
0x6
DSBOTH
Dual-slope PWM
PER
TOP & Zero
~DIR
Stable
TOP
Zero
0x7
DSTOP
Dual-slope PWM
PER
Zero
~DIR
Stable
TOP
–
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 677
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.17 Period Value
Name:
Offset:
Reset:
Property:
Bit
PER
0x40
0xFFFFFFFF
Write-Synchronized
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
11
10
9
8
R/W
1
R/W
1
R/W
1
1
0
R/W
1
R/W
1
Access
Reset
Bit
PER[17:10]
Access
Reset
Bit
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
PER[9:2]
Access
Reset
Bit
R/W
1
7
R/W
1
R/W
1
R/W
1
R/W
1
6
5
4
3
R/W
1
R/W
1
R/W
1
PER[1:0]
Access
Reset
R/W
1
2
DITHER[5:0]
R/W
R/W
1
1
Bits 23:6 – PER[17:0] Period Value
These bits hold the value of the period buffer register.
Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
23:0
23:4
23:5
23:6 (depicted)
Bits 5:0 – DITHER[5:0] Dithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM pulse period every 64 PWM frames.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
3:0
4:0
5:0 (depicted)
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 678
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.18 Compare/Capture Channel x
Name:
Offset:
Reset:
Property:
CC
0x44 + n*0x04 [n=0..3]
0x00000000
Write-Synchronized, Read-Synchronized
The CCx register represents the 16-, 24- bit value, CCx. The register has two functions, depending of the mode of
operation.
For capture operation, this register represents the second buffer level and access point for the CPU and DMA.
For compare operation, this register is continuously compared to the counter value. Normally, the output form the
comparator is then used for generating waveforms.
CCx register is updated with the buffer value from their corresponding CCBUFx register when an UPDATE condition
occurs.
In addition, in match frequency operation, the CC0 register controls the counter period.
Bit
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Access
Reset
Bit
CC[17:10]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
CC[9:2]
Access
Reset
Bit
R/W
0
7
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
3
R/W
0
R/W
0
R/W
0
CC[1:0]
Access
Reset
R/W
0
2
DITHER[5:0]
R/W
R/W
0
0
Bits 23:6 – CC[17:0] Channel x Compare/Capture Value
These bits hold the value of the Channel x compare/capture register.
Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the m MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
23:0
23:4
23:5
23:6 (depicted)
Bits 5:0 – DITHER[5:0] Dithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM pulse width every 64 PWM frames.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 679
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
3:0
4:0
5:0 (depicted)
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 680
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.19 Pattern Buffer
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
PATTBUF
0x64
0x0000
Write-Synchronized, Read-Synchronized
15
PGVB7
R/W
0
14
PGVB6
R/W
0
13
PGVB5
R/W
0
12
PGVB4
R/W
0
11
PGVB3
R/W
0
10
PGVB2
R/W
0
9
PGVB1
R/W
0
8
PGVB0
R/W
0
7
PGEB7
R/W
0
6
PGEB6
R/W
0
5
PGEB5
R/W
0
4
PGEB4
R/W
0
3
PGEB3
R/W
0
2
PGEB2
R/W
0
1
PGEB1
R/W
0
0
PGEB0
R/W
0
Bits 8, 9, 10, 11, 12, 13, 14, 15 – PGVB Pattern Generation Output Value Buffer
This register is the buffer for the PGV register. If double buffering is used, valid content in this register is copied to the
PGV register on an UPDATE condition.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PGEB Pattern Generation Output Enable Buffer
This register is the buffer of the PGE register. If double buffering is used, valid content in this register is copied into
the PGE register at an UPDATE condition.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 681
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.20 Period Buffer Value
Name:
Offset:
Reset:
Property:
Bit
PERBUF
0x6C
0xFFFFFFFF
Write-Synchronized, Read-Synchronized
31
30
29
23
22
21
R/W
1
R/W
1
R/W
1
15
14
13
R/W
1
R/W
1
R/W
1
28
27
26
25
24
18
17
16
R/W
1
R/W
1
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
1
0
R/W
1
R/W
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
6
PERBUF[1:0]
R/W
R/W
1
1
20
19
PERBUF[17:10]
R/W
R/W
1
1
12
11
PERBUF[9:2]
R/W
R/W
1
1
5
4
R/W
1
R/W
1
3
2
DITHERBUF[5:0]
R/W
R/W
1
1
Bits 23:6 – PERBUF[17:0] Period Buffer Value
These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE condition.
Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
23:0
23:4
23:5
23:6 (depicted)
Bits 5:0 – DITHERBUF[5:0] Dithering Buffer Cycle Number
These bits represent the PER.DITHER bits buffer. When the double buffering is enabled, the value of this bit field is
copied to the PER.DITHER bits on an UPDATE condition.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
3:0
4:0
5:0 (depicted)
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 682
PIC32CM MC00 Family
Timer/Counter for Control (TCC) Applications
34.7.21 Channel x Compare/Capture Buffer Value
Name:
Offset:
Reset:
Property:
CCBUF
0x70 + n*0x04 [n=0..3]
0x00000000
Write-Synchronized, Read-Synchronized
CCBUFx is copied into CCx at TCC update time
Bit
31
30
29
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
28
27
26
25
24
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
6
CCBUF[1:0]
R/W
R/W
0
0
20
19
CCBUF[17:10]
R/W
R/W
0
0
12
11
CCBUF[9:2]
R/W
R/W
0
0
5
4
R/W
0
R/W
0
3
2
DITHERBUF[5:0]
R/W
R/W
0
0
Bits 23:6 – CCBUF[17:0] Channel x Compare/Capture Buffer Value
These bits hold the value of the Channel x Compare/Capture Buffer Value register. The register serves as the buffer
for the associated compare or capture registers (CCx). Accessing this register using the CPU or DMA will affect the
corresponding CCBUFVx status bit.
Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
23:0
23:4
23:5
23:6 (depicted)
Bits 5:0 – DITHERBUF[5:0] Dithering Buffer Cycle Number
These bits represent the CCx.DITHER bits buffer. When the double buffering is enable, DITHERBUF bits value is
copied to the CCx.DITHER bits on an UPDATE condition.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
3:0
4:0
5:0 (depicted)
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 683
PIC32CM MC00 Family
Configurable Custom Logic (CCL)
35.
35.1
Configurable Custom Logic (CCL)
Overview
The Configurable Custom Logic (CCL) is a programmable logic peripheral which can be connected to the device
pins, events, or other internal peripherals. This enables the user to eliminate logic gates for simple glue logic
functions on the PCB.
Each LookUp Table (LUT) consists of three inputs: a truth table, an optional synchronizer/filter, and an optional edge
detector. Each LUT can generate an output as a user programmable logic expression with three inputs. Inputs can be
individually masked.
The output can be combinatorially generated from the inputs, and can be filtered to remove spikes. Optional
sequential logic can be used. The inputs of the sequential module are individually controlled by two independent,
adjacent LUT (LUT0/LUT1, LUT2/LUT3 and so on) outputs, enabling complex waveform generation.
35.2
Features
•
•
•
•
•
•
•
Glue logic for general purpose PCB design
Up to 4 programmable LookUp Tables (LUTs)
Combinatorial logic functions:
AND, NAND, OR, NOR, XOR, XNOR, NOT
Sequential logic functions:
Gated D Flip-Flop, JK Flip-Flop, gated D Latch, RS Latch
Flexible LUT inputs selection:
– I/Os
– Events
– Internal peripherals
– Subsequent LUT output
Output can be connected to the I/O pins or the Event System
Optional synchronizer, filter, or edge detector available on each LUT output
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 684
PIC32CM MC00 Family
Configurable Custom Logic (CCL)
35.3
Block Diagram
Figure 35-1. Configurable Custom Logic
LUT0
LUTCTRL0
(INSEL)
Internal
LUTCTRL0
(FILTSEL)
Events
SEQCTRL
(SEQSEL0)
CTRL
(ENABLE)
Event System
I/O
Truth Table
8
Peripherals
CLK_CCL_APB
GCLK_CCL
LUTCTRL0
(EDGESEL)
Filter / Synch
Edge Detector
CLR
CLR
OUT0
Sequential
I/O
CLR
LUTCTRL0
(ENABLE)
D Q
LUT1
LUTCTRL1
(INSEL)
Internal
LUTCTRL1
(FILTSEL)
Events
CTRL
(ENABLE)
Event System
I/O
Truth Table
8
Peripherals
CLK_CCL_APB
GCLK_CCL
LUTCTRL1
(EDGESEL)
LUTCTRL1
(ENABLE)
Filter / Synch
Edge Detector
CLR
CLR
OUT1
I/O
D Q
UNIT 0
...
.
.
Event System
35.4
UNIT x
OUT2x-1
I/O
Signal Description
Pin Name
Type
Description
OUT[n:0]
Digital output
Output from lookup table
IN[3n+2:0]
Digital input
Input to lookup table
1.
n is the number of CCL groups.
Refer to the 4. Pinout and Packaging for details on the pin mapping for this peripheral. One signal can be mapped on
several pins.
35.5
Peripheral Dependencies
Generic
CLK
AHB CLK
APB CLK
Enabled at
reset
Enabled at
reset
Index
-
N
32
PAC
Events
DMA
Sleep
Walking
Peripheral Base Address IRQ
CCL
0x42005C00
-
35.6
Functional Description
35.6.1
Principle of Operation
Index
Prot at
reset
User
Generator
Index
23
N
37-40:
LUTIN0-3
77-80:
LUTOUT0-3
-
Y
Configurable Custom Logic (CCL) is a programmable logic block that can use the device port pins, internal
peripherals, and the internal Event System as both input and output channels. The CCL can serve as glue logic
between the device and external devices. The CCL can eliminate the need for external logic component and can also
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 685
PIC32CM MC00 Family
Configurable Custom Logic (CCL)
help the designer overcome challenging real-time constrains by combining core independent peripherals in clever
ways to handle the most time critical parts of the application independent of the CPU.
35.6.2
Operation
35.6.2.1 Initialization
The CCL bus clock (CLK_CCL_APB) is required to access the CCL registers. This clock can be enabled in the MCLK
- Main Clock module.
A generic clock (GCLK_CCL) is optionally required to clock the CCL. This clock must be configured and enabled in
the GCLK - Generic Clock Controller before using input events, filter, edge detection or sequential logic.
The following bits are enable-protected, meaning that they can only be written when the CCL module is disabled
(CTRL.ENABLE=0):
•
•
Sequential Selection bits in the Sequential Control x (SEQCTRLx.SEQSEL) register
LUT Control n (LUTCTRLn) register, except the ENABLE bit
Enable-protected bits in the LUTCTRLn registers can be written at the same time as LUTCTRLn.ENABLE is written
to '1', but not at the same time as LUTCTRLn.ENABLE is written to '0'.
Enable-protection is denoted by the Enable-Protected property in the register description.
35.6.2.2 Enabling, Disabling, and Resetting
The CCL is enabled by writing a '1' to the Enable bit in the Control register (CTRL.ENABLE). The CCL is disabled
by writing a '0' to CTRL.ENABLE. When using sequential logic the control register enable must be written twice when
enabling (CTRL.ENABLE = 1).
Each LUT is enabled by writing a '1' to the Enable bit in the LUT Control n register (LUTCTRLn.ENABLE). Each LUT
is disabled by writing a '0' to LUTCTRLn.ENABLE.
The CCL is reset by writing a '1' to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the
CCL will be reset to their initial state, and the CCL will be disabled. Refer to 35.7.1 CTRL for details.
When the Peripheral Access Controller (PAC) is enabled for the CCL module (WRCTRL.PERID = 87) and a Software
Reset (CTRL.SWRST) is executed, a PAC protection error will be generated. If the PAC interrupt is enabled, the
interrupt flag for the CCL module (INTFLAGC.CCL) should be cleared.
35.6.2.3 Lookup Table Logic
The lookup table in each LUT unit can generate any logic expression OUT as a function of three inputs (IN[2:0]), as
shown in Figure 35-2. One or more inputs can be masked. The truth table for the expression is defined by TRUTH
bits in LUT Control n register (LUTCTRLn.TRUTH).
Figure 35-2. Truth Table Output Value Selection
LUT
TRUTH[0]
TRUTH[1]
TRUTH[2]
TRUTH[3]
TRUTH[4]
TRUTH[5]
TRUTH[6]
TRUTH[7]
OUT
LUTCTRL
(ENABLE)
IN[2:0]
Table 35-1. Truth Table of LUT
IN[2]
IN[1]
IN[0]
OUT
0
0
0
TRUTH[0]
0
0
1
TRUTH[1]
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Datasheet
DS60001638D-page 686
PIC32CM MC00 Family
Configurable Custom Logic (CCL)
...........continued
IN[2]
IN[1]
IN[0]
OUT
0
1
0
TRUTH[2]
0
1
1
TRUTH[3]
1
0
0
TRUTH[4]
1
0
1
TRUTH[5]
1
1
0
TRUTH[6]
1
1
1
TRUTH[7]
35.6.2.4 Truth Table Inputs Selection
Input Overview
The inputs can be individually:
•
•
•
•
Masked
Driven by peripherals:
– Analog comparator output (AC)
– Timer/Counters waveform outputs (TC)
– Serial Communication output transmit interface (SERCOM)
– Timer/Counters for Control Applications waveform outputs (TCC)
Driven by internal events from Event System
Driven by other CCL sub-modules
The Input Selection for each input y of LUT n is configured by writing the Input x Source Selection bit in the LUT n
Control register (LUTCTRLn.INSELx).
Masked Inputs (MASK)
When a LUT input is masked (LUTCTRLn.INSELx=MASK), the corresponding TRUTH input (IN) is internally tied to
zero, as shown in this figure:
Figure 35-3. Masked Input Selection
Internal Feedback Inputs (FEEDBACK)
When selected (LUTCTRLn.INSELx=FEEDBACK), the Sequential (SEQ) output is used as input for the
corresponding LUT.
The output from an internal sequential sub-module can be used as input source for the LUT, see figure below for an
example for LUT0 and LUT1. The sequential selection for each LUT follows the formula:
IN 2n x = SEQ n
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and its subsidiaries
Datasheet
DS60001638D-page 687
PIC32CM MC00 Family
Configurable Custom Logic (CCL)
IN 2n+1 x = SEQ n
With n representing the sequencer number and x=0,1,2 representing the LUT input index.
Figure 35-4. Feedback Input Selection
Linked LUT (LINK)
When selected (LUTCTRLn.INSELx=LINK), the subsequent LUT output is used as the LUT input (e.g., LUT2 is the
input for LUT1), as shown in this figure:
Figure 35-5. Linked LUT Input Selection
LUT0
SEQ 0
CTRL
(ENABLE)
LUT1
LUT2
SEQ 1
CTRL
(ENABLE)
LUT3
LUT(2n – 2)
SEQ n
CTRL
(ENABLE)
LUT(2n-1)
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 688
PIC32CM MC00 Family
Configurable Custom Logic (CCL)
Internal Events Inputs Selection (EVENT)
Asynchronous events from the Event System can be used as input selection, as shown in the following figure. For
each LUT, one event input line is available and can be selected on each LUT input. Before enabling the event
selection by writing LUTCTRLn.INSELx = EVENT, the Event System must be configured first.
By default CCL includes an edge detector. When the event is received, an internal strobe is generated when
a rising edge is detected. The pulse duration is one GCLK_CCL clock cycle. Writing the LUTCTRLn.INSELx =
ASYNCEVENT will disable the edge detector. In this case, it is possible to combine an asynchronous event input
with any other input source. This is typically useful with event levels inputs (external IO pin events, as example). The
following steps ensure proper operation:
1.
2.
3.
4.
5.
Enable the GCLK_CCL clock.
Configure the Event System to route the event asynchronously.
Select the event input type (LUTCTRLn.INSEL=ASYNCEVENT).
If a strobe must be generated on the event input falling edge, write a '1' to the Inverted Event Input Enable bit
in LUT Control register (LUTCTRLn.INVEI) .
Enable the event input by writing the Event Input Enable bit in LUT Control register (LUTCTRLn.LUTEI) to '1'.
Figure 35-6. Event Input Selection
FILTSEL
Input
OUT
Q
D
R
Q
D
R
Q
D
R
D
G
Q
R
GCLK_CCL
CLR
I/O Pin Inputs (IO)
When the IO pin is selected as LUT input (LUTCTRLn.INSELx = IO), the corresponding LUT input will be connected
to the pin, as shown in the figure below.
Figure 35-7. I/O Pin Input Selection
Analog Comparator Inputs (AC)
The AC outputs can be used as input source for the LUT (LUTCTRLn.INSELx = AC).
The analog comparator outputs are distributed following the formula:
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Datasheet
DS60001638D-page 689
PIC32CM MC00 Family
Configurable Custom Logic (CCL)
IN[n][x]= AC[n % ComparatorOutput_Number]
With n representing the LUT number and x=[0,1,2] representing the LUT input index.
Before selecting the comparator output, the AC must be configured first.
Figure 35-8. AC Input Selection
Timer/Counter Inputs (TC)
The TC waveform output WO[0] can be used as input source for the LUT (LUTCTRLn.INSELx=TC). TCn, TC(n+1),
and TC(n+4) are available respectively as default, alternative TC and second alternative TC selections (i.e., TC0,
TC1 and TC4 are sources for LUT0, TC1, TC2 and TC5 are sources for LUT1, etc). See the figure below for an
example for LUT0. More general, the Timer/Counter selection for each LUT follows the formula:
IN n x = DefaultTC n
IN n x = AlternativeTC n + 1
IN n x = SecondAlternativeTC n + 4
Where n represents the LUT number and x represents the LUT input index (x=0,1,2).
Before selecting the waveform outputs, the 33. Timer Counter (TC) must be configured.
Figure 35-9. TC Input Selection
TC0
(default)
WO[0]
TC1
(alternative)
WO[0]
TC4
(second alternative)
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WO[0]
Datasheet
DS60001638D-page 690
PIC32CM MC00 Family
Configurable Custom Logic (CCL)
Timer/Counter for Control Application Inputs (TCC)
The TCC waveform outputs can be used as input source for the LUT. Only WO[2:0] outputs can be selected and
routed to the respective LUT input (i.e., IN0 is connected to WO0, IN1 to WO1, and IN2 to WO2), as shown in the
figure below.
Note:
The TCC selection for each LUT follows the formula:
IN n x = TCC n % TCC_Instance_Number .WO x
Where n represents the LUT number and x represents the LUT input index (i=0,1,2).
Before selecting the waveform outputs, the TCC must be configured.
Note: TCC2 only outputs 2 WO signals, so TCC2.WO[0] is connected to both LUT2.IN[0] and LUT2.IN[2], and
TCC2.WO[1] is connected to LUT2.IN[1].
Figure 35-10. TCC Input Selection
Serial Communication Output Transmit Inputs (SERCOM)
The serial engine transmitter output from Serial Communication Interface (SERCOM TX, TXd for USART, MOSI
for SPI) can be used as input source for the LUT. The figure below shows an example for LUT0 and LUT1. The
SERCOM selection for each LUT follows the formula:
IN n x = SERCOM[n % SERCOM_Instance_Number
With n representing the LUT number and x=0,1,2 representing the LUT input index.
Before selecting the SERCOM as input source, the SERCOM must be configured first: the SERCOM TX signal must
be output on SERCOMn/pad[0], which serves as input pad to the CCL.
Figure 35-11. SERCOM Input Selection
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Datasheet
DS60001638D-page 691
PIC32CM MC00 Family
Configurable Custom Logic (CCL)
35.6.2.5 Filter
By default, the LUT output is a combinatorial function of the LUT inputs. This may cause some short glitches when
the inputs change value. These glitches can be removed by clocking through filters, if demanded by application
needs.
The Filter Selection bits in LUT Control register (LUTCTRLn.FILTSEL) define the synchronizer or digital filter options.
When a filter is enabled, the OUT output will be delayed by two to five GCLK cycles. One APB clock after the
corresponding LUT is disabled, all internal filter logic is cleared.
Note: Events used as LUT input will also be filtered, if the filter is enabled.
Figure 35-12. Filter
FILTSEL
Input
OUT
Q
D
R
Q
D
R
Q
D
R
D
G
Q
R
GCLK_CCL
CLR
35.6.2.6 Edge Detector
The edge detector can be used to generate a pulse when detecting a rising edge on its input. To detect a falling edge,
the TRUTH table should be inverted.
The edge detector is enabled by writing '1' to the Edge Selection bit in LUT Control register (LUTCTRLn.EDGESEL).
In order to avoid unpredictable behavior, either the filter or synchronizer must be enabled.
Edge detection is disabled by writing a '0' to LUTCTRLn.EDGESEL. After disabling a LUT, the corresponding internal
Edge Detector logic is cleared one APB clock cycle later.
Figure 35-13. Edge Detector
35.6.2.7 Sequential Logic
Each LUT pair can be connected to the internal sequential logic which can be configured to work as D flip flop, JK
flip flop, gated D-latch or RS-latch by writing the Sequential Selection bits on the corresponding Sequential Control x
register (SEQCTRLx.SEQSEL). Before using sequential logic, the GCLK_CCL clock and optionally each LUT filter or
edge detector must be enabled.
Note: While configuring the sequential logic, the even LUT must be disabled. When configured the even LUT must
be enabled.
Gated D Flip-Flop (DFF)
When the DFF is selected, the D-input is driven by the even LUT output (LUT0 and LUT2), and the G-input is driven
by the odd LUT output (LUT1 and LUT3), as shown in Figure 35-14.
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Datasheet
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PIC32CM MC00 Family
Configurable Custom Logic (CCL)
Figure 35-14. D Flip Flop
When the even LUT is disabled (LUTCTRL0.ENABLE=0 / LUTCTRL2.ENABLE=0), the flip-flop is asynchronously
cleared. The reset command (R) is kept enabled for one APB clock cycle. In all other cases, the flip-flop output (OUT)
is refreshed on rising edge of the GCLK_CCL, as shown in Table 35-2.
Table 35-2. DFF Characteristics
R
G
D
OUT
1
X
X
Clear
0
1
1
Set
0
Clear
X
Hold state (no change)
0
JK Flip-Flop (JK)
When this configuration is selected, the J-input is driven by the even LUT output (LUT0 and LUT2), and the K-input is
driven by the odd LUT output (LUT1 and LUT3), as shown in Figure 35-15.
Figure 35-15. JK Flip Flop
When the even LUT is disabled (LUTCTRL0.ENABLE=0 / LUTCTRL2.ENABLE=0), the flip-flop is asynchronously
cleared. The reset command (R) is kept enabled for one APB clock cycle. In all other cases, the flip-flop output (OUT)
is refreshed on rising edge of the GCLK_CCL, as shown in Table 35-3.
Table 35-3. JK Characteristics
R
J
K
OUT
1
X
X
Clear
0
0
0
Hold state (no change)
0
0
1
Clear
0
1
0
Set
0
1
1
Toggle
Gated D-Latch (DLATCH)
When the DLATCH is selected, the D-input is driven by the even LUT output (LUT0 and LUT2), and the G-input is
driven by the odd LUT output (LUT1 and LUT3), as shown in Figure 35-14.
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Datasheet
DS60001638D-page 693
PIC32CM MC00 Family
Configurable Custom Logic (CCL)
Figure 35-16. D-Latch
even LUT
D
odd LUT
G
Q
OUT
When the even LUT is disabled (LUTCTRL0.ENABLE=0 /
LUTCTRL2.ENABLE=0), the latch output will be cleared. The G-input is forced enabled for one more APB clock
cycle, and the D-input to zero. In all other cases, the latch output (OUT) is refreshed as shown in Table 35-4.
Table 35-4. D-Latch Characteristics
G
D
OUT
0
X
Hold state (no change)
1
0
Clear
1
1
Set
RS Latch (RS)
When this configuration is selected, the S-input is driven by the even LUT output (LUT0 and LUT2), and the R-input
is driven by the odd LUT output (LUT1 and LUT3), as shown in Figure 35-17.
Figure 35-17. RS-Latch
even LUT
S
odd LUT
R
Q
OUT
When the even LUT is disabled LUTCTRL0.ENABLE=0 / LUTCTRL2.ENABLE=0), the latch output will be cleared.
The R-input is forced enabled for one more APB clock cycle and S-input to zero. In all other cases, the latch output
(OUT) is refreshed as shown in Table 35-5.
Table 35-5. RS-Latch Characteristics
35.6.3
S
R
OUT
0
0
Hold state (no change)
0
1
Clear
1
0
Set
1
1
Forbidden state
Events
The CCL can generate the following output events:
•
OUTn: Lookup Table Output Value
Writing a '1' to the LUT Control Event Output Enable bit (LUTCTRLn.LUTEO) enables the corresponding output
event. Writing a '0' to this bit disables the corresponding output event.
The CCL can take the following actions on an input event:
•
INSELx: The event is used as input for the TRUTH table.
Writing a '1' to the LUT Control Event Input Enable bit (LUTCTRLn.LUTEI) enables the corresponding action on input
event. Writing a '0' to this bit disables the corresponding action on input event.
For further information, refer to the 28. Event System (EVSYS).
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Datasheet
DS60001638D-page 694
PIC32CM MC00 Family
Configurable Custom Logic (CCL)
35.6.4
Sleep Mode Operation
When using the GCLK_CCL internal clocking, writing the Run In Standby bit in the Control register
(CTRL.RUNSTDBY) to '1' will allow GCLK_CCL to be enabled in Standby Sleep mode.
If CTRL.RUNSTDBY=0, the GCLK_CCL will be disabled in Standby Sleep mode. If the Filter, Edge Detector or
Sequential logic are enabled, the LUT output will be forced to zero in STANDBY mode. In all other cases, the TRUTH
table decoder will continue operation and the LUT output will be refreshed accordingly.
For further information, refer to the 16. Power Manager (PM).
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Datasheet
DS60001638D-page 695
PIC32CM MC00 Family
Configurable Custom Logic (CCL)
35.7
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
...
0x03
0x04
0x05
0x06
...
0x07
CTRL
7:0
0x08
0x0C
0x10
0x14
7
6
5
4
RUNSTDBY
3
2
1
0
ENABLE
SWRST
Reserved
SEQCTRL0
SEQCTRL1
7:0
7:0
SEQSEL[3:0]
SEQSEL[3:0]
Reserved
LUTCTRL0
LUTCTRL1
LUTCTRL2
LUTCTRL3
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
EDGESEL
EDGESEL
EDGESEL
EDGESEL
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FILTSEL[1:0]
INSEL1[3:0]
LUTEO
LUTEI
INVEI
TRUTH[7:0]
FILTSEL[1:0]
INSEL1[3:0]
LUTEO
LUTEI
INVEI
TRUTH[7:0]
FILTSEL[1:0]
INSEL1[3:0]
LUTEO
LUTEI
INVEI
TRUTH[7:0]
FILTSEL[1:0]
INSEL1[3:0]
LUTEO
LUTEI
INVEI
TRUTH[7:0]
Datasheet
ENABLE
INSEL0[3:0]
INSEL2[3:0]
ENABLE
INSEL0[3:0]
INSEL2[3:0]
ENABLE
INSEL0[3:0]
INSEL2[3:0]
ENABLE
INSEL0[3:0]
INSEL2[3:0]
DS60001638D-page 696
PIC32CM MC00 Family
Configurable Custom Logic (CCL)
35.7.1
Control
Name:
Offset:
Reset:
Property:
CTRL
0x00
0x00
PAC Write-Protection
Note: CTRL register (except the bits ENABLE & SWRST) is Enable Protected when CCL.CTRL.ENABLE = 1.
Bit
7
Access
Reset
6
RUNSTDBY
R/W
0
5
4
3
2
1
ENABLE
R/W
0
0
SWRST
W
0
Bit 6 – RUNSTDBY Run in Standby
This bit indicates if the GCLK_CCL clock must be kept running in standby mode. The setting is ignored for
configurations where the generic clock is not required. For details refer to 35.6.4 Sleep Mode Operation.
Important: This bit must be written before enabling the CCL.
Value
0
1
Description
Generic clock is not required in standby sleep mode.
Generic clock is required in standby sleep mode.
Bit 1 – ENABLE Enable
Value
Description
0
The peripheral is disabled.
1
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the CCL to their initial state.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 697
PIC32CM MC00 Family
Configurable Custom Logic (CCL)
35.7.2
Sequential Control x
Name:
Offset:
Reset:
Property:
SEQCTRL
0x04 + n*0x01 [n=0..1]
0x00
PAC Write-Protection, Enable-Protected
Note: The SEQCTRL0 (SEQCTRL1) register is Enable-protected when CCL.CTRL.ENABLE = 1.
Bit
7
6
Access
Reset
5
4
3
R/W
0
2
1
SEQSEL[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 3:0 – SEQSEL[3:0] Sequential Selection
These bits select the sequential configuration:
Sequential Selection
Value
Name
Description
0x0
DISABLE
Sequential logic is disabled
0x1
DFF
D flip flop
0x2
JK
JK flip flop
0x3
LATCH
D latch
0x4
RS
RS latch
0x5 Reserved
0xF
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 698
PIC32CM MC00 Family
Configurable Custom Logic (CCL)
35.7.3
LUT Control n
Name:
Offset:
Reset:
Property:
LUTCTRLn
0x08 + n*0x04 [n=0..3]
0x00000000
PAC Write-Protection, Enable-protected
Note: The LUTCTRLn register is Enable Protected when CCL.CTRL.ENABLE = 1.
Bit
31
30
29
28
27
26
25
24
R/W
0
R/W
0
TRUTH[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
LUTEO
R/W
0
21
LUTEI
R/W
0
20
INVEI
R/W
0
19
18
R/W
0
12
11
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
15
R/W
0
7
EDGESEL
R/W
0
14
13
INSEL1[3:0]
R/W
R/W
0
0
6
5
4
FILTSEL[1:0]
R/W
R/W
0
0
3
17
INSEL2[3:0]
R/W
R/W
0
0
10
9
INSEL0[3:0]
R/W
R/W
0
0
2
1
ENABLE
R/W
0
16
R/W
0
8
R/W
0
0
Bits 31:24 – TRUTH[7:0] Truth Table
These bits define the value of truth logic as a function of inputs IN[2:0].
Bit 22 – LUTEO LUT Event Output Enable
Value
Description
0
LUT event output is disabled.
1
LUT event output is enabled.
Bit 21 – LUTEI LUT Event Input Enable
Value
Description
0
LUT incoming event is disabled.
1
LUT incoming event is enabled.
Bit 20 – INVEI Inverted Event Input Enable
Value
Description
0
Incoming event is not inverted.
1
Incoming event is inverted.
Bits 8:11, 12:15, 16:19 – INSELx LUT Input x Source Selection
These bits select the LUT input x source:
Value
Name
Description
0x0
MASK
Masked input
0x1
FEEDBACK Feedback input source
0x2
LINK
Linked LUT input source
0x3
EVENT
Event input source
0x4
IO
I/O pin input source
0x5
AC
AC input source: CMP[0] (LUT0) / CMP[1] (LUT1)
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Datasheet
DS60001638D-page 699
PIC32CM MC00 Family
Configurable Custom Logic (CCL)
Value
0x6
0x7
0x8
0x9
Name
TC
ALTTC
TCC
SERCOM
0xA 0xF
Reserved
Description
TC input source: TC0 (LUT0) / TC1 (LUT1)/ TC2 (LUT2) / TC3 (LUT3)
Alternative TC input source: TC1 (LUT0) / TC2 (LUT1) / TC3 (LUT2) / TC4 (LUT3)
TCC input source: TCC0 (LUT0) / TCC1 (LUT1)/ TCC2 (LUT2)
SERCOM input source: SERCOM0 (LUT0) / SERCOM1 (LUT1)/ SERCOM2 (LUT2) /
SERCOM3 (LUT3)
Reserved
Bit 7 – EDGESEL Edge Selection
Value
Description
0
Edge detector is disabled.
1
Edge detector is enabled.
Bits 5:4 – FILTSEL[1:0] Filter Selection
These bits select the LUT output filter options:
Filter Selection
Value
Name
0x0
DISABLE
0x1
SYNCH
0x2
FILTER
0x3
-
Description
Filter disabled
Synchronizer enabled
Filter enabled
Reserved
Bit 1 – ENABLE LUT Enable
Value
Description
0
The LUT is disabled.
1
The LUT is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 700
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.
36.1
Analog-to-Digital Converter (ADC)
Overview
The Analog-to-Digital Converter (ADC) converts analog signals to digital values. The ADC has up to 12-bit resolution,
and is capable of a sampling rate of up to 1 Msps. The input selection is flexible, and both differential and singleended measurements can be performed. In addition, several internal signal inputs are available. The ADC can
provide both signed and unsigned results.
ADC measurements can be started by either application software or an incoming event from another peripheral in the
device. ADC measurements can be started with predictable timing and without software intervention.
Both internal and external reference voltages can be used.
The INTREF voltage reference (supplied by the bandgap), as well as the scaled I/O and core voltages, can be
measured by the ADC.
The ADC has a compare function for accurate monitoring of user-defined thresholds, with minimum software
intervention required. The ADC can be configured for 8, 10, or 12-bit results. ADC conversion results are provided
left- or right-adjusted, which eases calculation when the result is represented as a signed value. It is possible to use
DMA to move ADC results directly to memory or peripherals when conversions are done.
The device has two ADC instances, ADC0 and ADC1. The two inputs can be sampled simultaneously, as each ADC
includes a dedicated sample and hold circuit.
36.2
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Two Analog-to-Digital Converters (ADC): ADC0 and ADC1
8-bit, 10-bit, or 12-bit resolution
Up to 1,000,000 samples per second (1 MSPS)
Differential and single-ended inputs
– Up to 14 analog inputs on ADC
Up to 12 external analog inputs and 3 internal inputs
Internal inputs:
– INTREF voltage reference, supplied by the bandgap
– Scaled core supply
– Scaled I/O supply
– DAC
Single, continuous, and sequencing options
Windowing monitor with selectable channel
Conversion range: Vref = [2.0V to VDDANA ]
Built-in internal reference and external reference options
Event-triggered conversion for accurate timing (one event input)
Optional DMA transfer of conversion settings or result
Hardware gain and offset compensation
Averaging and oversampling with decimation to support up to 16-bit result
Selectable sampling time
Flexible Power or Throughput rate management
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 701
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.3
Block Diagram
Figure 36-1. ADC Block Diagram
CTRLB
SEQCTRL
AVGCTRL
WINLT
SAMPCTRL
WINUT
EVCTRL
OFFSETCORR
SWTRIG
GAINCORR
INPUTCTRL
AIN0
...
AINn
INT.SIG
ADC
POST
PROCESSING
RESULT
AIN0
...
AINn
INTREF
INTVCC0
INTVCC1
VREFA
DAC
INTVCC2
CTRLA
SEQSTATUS
PRESCALER
REFCTRL
36.4
Signal Description
Signal
Description
Type
VREFA
Analog input
External reference voltage
AIN[11..0]
Analog input
Analog input channels
Note: One signal can be mapped on several pins.
For further information, refer to the Pinout.
36.5
Peripheral Dependencies
Peripheral Base Address IRQ
ADC0
0x42004400
21
AHB CLK
APB CLK
Generic CLK
PAC
Events
Enabled at
reset
Enabled at
reset
Index
Index
Prot at
reset
-
N
28
17
N
DMA
User
Generator
28: START
67: RESRDY
Index
Sleep
Walking
36: RESRDY
Y
29: FLUSH 68: WINMON
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PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
...........continued
Peripheral Base Address IRQ
ADC1
0x42004800
22
AHB CLK
APB CLK
Generic CLK
PAC
Events
Enabled at
reset
Enabled at
reset
Index
Index
Prot at
reset
-
N
29
18
N
DMA
User
Generator
30: START
69: RESRDY
Index
Sleep
Walking
37: RESRDY
Y
31: FLUSH 70: WINMON
36.6
Functional Description
36.6.1
Principle of Operation
By default, the ADC provides results with 12-bit resolution. 8-bit or 10-bit results can be selected in order to reduce
the conversion time, see 36.6.2.8 Conversion Timing and Sampling Rate.
The ADC has an oversampling with decimation option that can extend its resolution to 16 bits. The input values can
be either internal or external (connected I/O pins). The user can also configure whether the conversion should be
single-ended or differential.
36.6.2
Basic Operation
36.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the ADC is disabled
(CTRLA.ENABLE=0):
•
•
•
•
Control B register (CTRLB)
Reference Control register (REFCTRL)
Event Control register (EVCTRL)
Calibration register (CALIB)
Enable-protection is denoted by the "Enable-Protected" property in the register description.
36.6.2.2 Enabling, Disabling and Resetting
The ADC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The ADC is disabled
by writing CTRLA.ENABLE=0.
The ADC is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in
the ADC, except DBGCTRL, will be reset to their initial state, and the ADC will be disabled. Refer to 36.7.1 CTRLA
for details.
36.6.2.3 Operation
In the most basic configuration, the ADC samples values from the configured internal or external sources
(INPUTCTRL register). The rate of the conversion depends on the combination of the GCLK_ADCx frequency and
the clock prescaler.
To convert analog values to digital values, the ADC needs to be initialized first, as described in the Initialization
section. Data conversion can be started either manually by setting the Start bit in the Software Trigger register
(SWTRIG.START=1), or automatically by configuring an automatic trigger to initiate the conversions. The ADC starts
sampling the input only after the start of conversion is triggered. This means that even after the MUX selection
is made, sample and hold (S&H) operation starts only on the conversion trigger. Free-running mode can be used
to continuously convert an input channel. When using free-running mode, conversions will start after the ADC is
enabled.
The ADC starts sampling the input only after the start of a conversion is triggered. This means that even after the
MUX selection is made, sample and hold operation starts only on the conversion trigger.
The result of the conversion is stored in the Result register (RESULT) overwriting the result from the previous
conversion.
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Analog-to-Digital Converter (ADC)
To avoid data loss, if more than one channel is enabled, the conversion result must be read as soon as it is available
(INTFLAG.RESRDY). Failing to do so will result in an overrun error condition, indicated by the OVERRUN bit in the
Interrupt Flag Status and Clear register (INTFLAG.OVERRUN).
To enable one of the available interrupts sources, the corresponding bit in the Interrupt Enable Set register
(INTENSET) must be written to '1'.
36.6.2.4 Prescaler Selection
The ADC is clocked by GCLK_ADCx. There is also a prescaler in the ADC to enable conversion at lower clock rates.
Refer to CTRLB for details on prescaler settings. Refer to 36.6.2.8 Conversion Timing and Sampling Rate for details
on timing and sampling rate.
Figure 36-2. ADC Prescaler
DIV256
DIV128
DIV64
DIV32
DIV16
DIV8
DIV4
9-BIT PRESCALER
DIV2
GCLK_ADCx
CTRLB.PRESCALER[2:0]
CLK_ADCx
Note: The minimum prescaling factor is DIV2.
36.6.2.5 Reference Configuration
The ADC has various sources for its reference voltage VREF. The Reference Voltage Selection bit field in the
Reference Control register (REFCTRL.REFSEL) determines which reference is selected. By default, the internal
voltage reference INTREF, supplied by the bandgap, is selected. Based on customer application requirements, the
external or internal reference can be selected. Refer to REFCTRL.REFSEL for further details on available selections.
36.6.2.6 ADC Resolution
The ADC supports 8-bit, 10-bit or 12-bit resolution. Resolution can be changed by writing the Resolution bit group in
the Control C register (CTRLC.RESSEL). By default, the ADC resolution is set to 12 bits. The resolution affects the
propagation delay, see also 36.6.2.8 Conversion Timing and Sampling Rate.
36.6.2.7 Differential and Single-Ended Conversions
The ADC has two conversion options: differential and single-ended:
If the positive input is always positive, the single-ended conversion should be used in order to have full 12-bit
resolution in the conversion.
If the positive input may go below the negative input, the differential mode should be used in order to get correct
results.
The differential mode is enabled by setting DIFFMODE bit in the Control C register (CTRLC.DIFFMODE). Both
conversion types could be run in single mode or in free-running mode. When the free-running mode is selected, an
ADC input will continuously sample the input and perform a new conversion. The INTFLAG.RESRDY bit will be set at
the end of each conversion.
36.6.2.8 Conversion Timing and Sampling Rate
The following figure shows the ADC timing for a single conversion. A conversion starts after the software or event
start are synchronized with the GCLK_ADCx clock. The input channel is sampled in the first half of the CLK_ADCx
period.
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Analog-to-Digital Converter (ADC)
Figure 36-3. ADC Timing for One Conversion in 12-bit Resolution
CLK_ADC
START
STATE
SAMPLING
MSB
10
9
8
7
6
5
4
3
2
1
LSB
INT
The sampling time can be increased by using the Sampling Time Length bit group in the Sampling Time Control
register (SAMPCTRL.SAMPLEN). As example, the next figure is showing the timing conversion with sampling time
increased to six CLK_ADC cycles.
Figure 36-4. ADC Timing for One Conversion with Increased Sampling Time, 12-bit
CLK_ADC
START
STATE
SAMPLING
MSB
10
9
8
7
6
5
4
3
2
1
LSB
INT
The ADC can also provide compensation, as shown in the following figure. The offset compensation is enabled by
the Offset Compensation bit in the Sampling Control register (SAMPCTRL.OFFCOMP).
Note: ADC sampling time is fixed to 4 ADC Clock cycles when offset compensation (OFFCOMP=1) is used.
In free running mode, the sampling rate RS is calculated by
RS = fCLK_ADC / ( nSAMPLING + nOFFCOMP + nDATA)
Here, nSAMPLING is the sampling duration in CLK_ADC cycles, nOFFCOMP is the offset compensation duration in clock
cycles, and nDATA is the bit resolution. fCLK_ADC is the ADC clock frequency from the internal prescaler: fCLK_ADC =
fGCLK_ADC / 2^(1 + CTRLB.PRESCALER)
Figure 36-5. ADC Timing for One Conversion with Offset Compensation, 12-bit
CLK_ADC
START
STATE
Offset Compensation and Sampling
MSB
10
9
8
7
6
5
4
3
2
1
LSB
INT
The impact of resolution on the sampling rate is seen in the next two figures, where free-running sampling in 12-bit
and 8-bit resolution are compared.
Figure 36-6. ADC Timing for Free Running in 12-bit Resolution
CLK_ADC
CONVERT
STATE
LSB
SAMPLING
MSB
10
9
8
7
6
5
4
3
2
1
LSB
SAMPLING
MSB
10
9
8
7
6
INT
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PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
Figure 36-7. ADC Timing for Free Running in 8-bit Resolution
CLK_ADC
CONVERT
STATE
LSB
SAMPLING
MSB
6
5
4
3
2
1
LSB
SAMPLING
MSB
6
5
4
3
2
1
LSB
SAMPLING
MSB
INT
The propagation delay of an ADC measurement is given by:
PropagationDelay = 1 + Resolution
fADC
Example. In order to obtain 1 MSPS in 12-bit resolution with a sampling time length of four
CLK_ADC cycles, fCLK_ADC must be 1 MSPS * (4 + 12) = 16 MHz. As the minimal division factor of
the prescaler is 2, GCLK_ADC must be 32 MHz.
36.6.2.9 Accumulation
The result from multiple consecutive conversions can be accumulated. The number of samples to be accumulated is
specified by the Sample Number field in the Average Control register (AVGCTRL.SAMPLENUM). When accumulating
more than 16 samples, the result will be too large to match the 16-bit RESULT register size. To avoid overflow, the
result is right shifted automatically to fit within the available register size. The number of automatic right shifts is
specified in the table below.
Note: To perform the accumulation of two or more samples, the Conversion Result Resolution field in the Control C
register (CTRLC.RESSEL) must be set depending on the final result precision. For resolutions strictly higher than 12
bits, RESSEL must be set to 16 bits.
Table 36-1. Accumulation
Number of
Accumulated
Samples
AVGCTRL.
SAMPLENUM
Number of
Automatic Right
Shifts
Final Result
Precision
Automatic
Division Factor
1
0x0
0
12 bits
0
2
0x1
0
13 bits
0
4
0x2
0
14 bits
0
8
0x3
0
15 bits
0
16
0x4
0
16 bits
0
32
0x5
1
16 bits
2
64
0x6
2
16 bits
4
128
0x7
3
16 bits
8
256
0x8
4
16 bits
16
512
0x9
5
16 bits
32
1024
0xA
6
16 bits
64
Reserved
0xB –0xF
12 bits
0
36.6.2.10 Averaging
Averaging is a feature that increases the sample accuracy, at the cost of a reduced sampling rate. This feature is
suitable when operating in noisy conditions.
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Analog-to-Digital Converter (ADC)
Averaging is done by accumulating m samples, as described in 36.6.2.9 Accumulation, then dividing the result by m.
The averaged result is available in the RESULT register. The number of samples to be accumulated is specified by
writing to AVGCTRL.SAMPLENUM as shown in Table 36-2.
The division is obtained by a combination of the automatic right shift described above, and an additional right shift
that must be specified by writing to the Adjusting Result/Division Coefficient field in AVGCTRL (AVGCTRL.ADJRES),
as described in Table 36-2.
Note: To perform the averaging of two or more samples, the Conversion Result Resolution field in the Control C
register (CTRLC.RESSEL) must be set.
Averaging AVGCTRL.SAMPLENUM samples will reduce the un-averaged sampling rate by a factor
1
.
AVGCTRL.SAMPLENUM
When the averaged result is available, the INTFLAG.RESRDY bit will be set.
Table 36-2. Averaging
Number of
Accumulated
Samples
AVGCTRL.
SAMPLENUM
Intermediate
Result
Precision
Number of
Automatic
Right Shifts
Division
Factor
AVGCTRL.ADJRES Total
Number
of Right
Shifts
Final Result
Precision
Automatic
Division
Factor
1
0x0
12 bits
0
1
0x0
12 bits
0
2
0x1
13
0
2
0x1
1
12 bits
0
4
0x2
14
0
4
0x2
2
12 bits
0
8
0x3
15
0
8
0x3
3
12 bits
0
16
0x4
16
0
16
0x4
4
12 bits
0
32
0x5
17
1
16
0x4
5
12 bits
2
64
0x6
18
2
16
0x4
6
12 bits
4
128
0x7
19
3
16
0x4
7
12 bits
8
256
0x8
20
4
16
0x4
8
12 bits
16
512
0x9
21
5
16
0x4
9
12 bits
32
1024
0xA
22
6
16
0x4
10
12 bits
64
Reserved
0xB –0xF
12 bits
0
0x0
36.6.2.11 Oversampling and Decimation
By using oversampling and decimation, the ADC resolution can be increased from 12 bits up to 16 bits, for the cost of
reduced effective sampling rate.
Note: To perform oversampling and decimation, the Conversion Result Resolution field in the Control C register
(CTRLC.RESSEL) must be set to 16-bit mode.
To increase the resolution by n bits, 4n samples must be accumulated. The result must then be right-shifted by n bits.
This right-shift is a combination of the automatic right-shift and the value written to AVGCTRL.ADJRES. To obtain the
correct resolution, the ADJRES must be configured as described in the table below. This method will result in n bit
extra LSB resolution.
Table 36-3. Configuration Required for Oversampling and Decimation
Result
Resolution
Number of
Samples to
Average
AVGCTRL.SAMPLENUM[3:0]
Number of
Automatic
Right Shifts
AVGCTRL.ADJRES[2:0]
13 bits
41 = 4
0x2
0
0x1
14 bits
42
0x4
0
0x2
= 16
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PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
...........continued
Result
Resolution
Number of
Samples to
Average
AVGCTRL.SAMPLENUM[3:0]
Number of
Automatic
Right Shifts
AVGCTRL.ADJRES[2:0]
15 bits
43 = 64
0x6
2
0x1
16 bits
44 = 256
0x8
4
0x0
36.6.2.12 Automatic Sequences
The ADC has the ability to automatically sequence a series of conversions. This means that each time the ADC
receives a start-of-conversion request, it can perform multiple conversions automatically. All of the positive inputs can
be included in a sequence by writing to corresponding bits in the Sequence Control register (SEQCTRL). The order
of the conversion in a sequence is the lower positive MUX selection to upper positive MUX (AIN0, AIN1, AIN2 ...). In
differential mode, the negative inputs selected by MUXNEG field, will be used for the entire sequence.
When a sequence starts, the Sequence Busy status bit in Sequence Status register (SEQSTATUS.SEQBUSY) will be
set. When the sequence is complete, the Sequence Busy status bit will be cleared.
Each time a conversion is completed, the Sequence State bit in Sequence Status register (SEQSTATUS.SEQSTATE)
will store the input number from which the conversion is done. The result will be stored in the RESULT register, and
the Result Ready Interrupt Flag (INTFLAG.RESRDY) is set.
If additional inputs must be scanned, the ADC will automatically start a new conversion on the next input present in
the sequence list.
Note that if SEQCTRL register has no bits set to '1', the conversion is done with the selected MUXPOS input.
36.6.2.13 Window Monitor
The window monitor feature allows the conversion result in the RESULT register to be compared to predefined
threshold values. The window mode is selected by setting the Window Monitor Mode bits in the Control C register
(CTRLC.WINMODE). Threshold values must be written in the Window Monitor Lower Threshold register (WINLT) and
Window Monitor Upper Threshold register (WINUT).
If differential input is selected, the WINLT and WINUT are evaluated as signed values. Otherwise they are evaluated
as unsigned values. The significant WINLT and WINUT bits are given by the precision selected in the Conversion
Result Resolution bit group in the Control C register (CTRLC.RESSEL). This means that for example in 8-bit mode,
only the eight lower bits will be considered. In addition, in differential mode, the eighth bit will be considered as the
sign bit, even if the ninth bit is zero.
The INTFLAG.WINMON interrupt flag will be set if the conversion result matches the window monitor condition.
36.6.2.14 Offset and Gain Correction
Inherent gain and offset errors affect the absolute accuracy of the ADC.
The offset error is defined as the deviation of the actual ADC transfer function from an ideal straight line at zero
input voltage. The offset error cancellation is handled by the Offset Correction register (OFFSETCORR). The offset
correction value is subtracted from the converted data before writing the Result register (RESULT). Offset correction
is only to be used with 12-bit conversion resolution.
The gain error is defined as the deviation of the last output step’s midpoint from the ideal straight line, after
compensating for offset error. The gain error cancellation is handled by the Gain Correction register (GAINCORR).
To correct these two errors, the Digital Correction Logic Enabled bit in the Control C register (CTRLC.CORREN) must
be set.
Offset and gain error compensation results are both calculated according to:
Result = Conversion value+ − OFFSETCORR ⋅ GAINCORR
The correction will introduce a latency of 13 CLK_ADC clock cycles. In free running mode this latency is introduced
on the first conversion only, since its duration is always less than the propagation delay. In single conversion mode
this latency is introduced for each conversion.
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Analog-to-Digital Converter (ADC)
Figure 36-8. ADC Timing Correction Enabled
START
CONV0
CONV1
CORR0
CONV2
CORR1
CONV3
CORR2
CORR3
36.6.2.15 Reference Buffer Compensation Offset
A hardware compensation using a reference buffer can be used. When the REFCTRL.REFCOMP bit is set, the
offset of the reference buffer is sensed during the ADC sampling phase. This offset will be then canceled during the
conversion phase. This feature allows for the decrease of the overall gain error of the ADC.
There is a digital gain correction (refer to Offset and Gain Correction) but contrary to that digital gain correction, the
hardware compensation will not introduce any latency. However, when using REFCOMP and if the ADC reference
selection is not using VDDANA (REFCTRL.REFSEL != INTVCC2), the first 5 conversions of the ADC must be
discarded after the ADC is enabled.
36.6.3
Additional Features
36.6.3.1 Host/Client Operation
The host/client operation is available only on devices with two ADC instances. The ADC1 will be enabled as a
client of ADC0 instance when writing a one to the Client Enable bit in Control A register of the ADC1 instance
(ADC1.CTRLA.SLAVEEN). When enabled, GCLK_ADC0 clock and ADC0 controls are internally routed to the ADC1
instance.
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Analog-to-Digital Converter (ADC)
Figure 36-9. ADC Host - Client Block Diagram
ADC0.SEQCTRL
ADC0.AVGCTRL
ADC0.WINLT
ADC0.SAMPCTRL
ADC0.WINUT
ADC0.EVCTRL
ADC0.OFFSETCORR
ADC0.SWTRIG
ADC0.GAINCORR
ADC0_AIN0
...
ADC0_AINn
INT.SIG
ADC 0
ADC0.INPUTCTRL
POST
PROCESSING
ADC0.RESULT
ADC0.SEQSTATUS
ADC0_AIN0
...
ADC0_AINn
ADC0.CTRLA
INTREF
INTVCC0
INTVCC1
VREFA
DAC
INTVCC2
ADC0.CTRLB
PRESCALER
ADC0.REFCTRL
ADC1_AIN0
...
ADC1_AINn
INT.SIG
ADC 1
ADC1.INPUTCTRL
ADC1.RESULT
POST
PROCESSING
ADC1.SEQSTATUS
ADC1_AIN0
...
ADC1_AINn
INTREF
INTVCC0
INTVCC1
VREFA
DAC
INTVCC2
ADC1.CTRLA
SLAVEEN
ADC1.GAINCORR
ADC1.AVGCTRL
ADC1.OFFSETCORR
ADC1.SAMPCTRL
ADC1.WINUT
ADC1.SWTRIG
ADC1.WINLT
ADC1.REFCTRL
ADC1.SEQCTRL
In this mode of operation, the client ADC is enabled by accessing the CTRLA register of host ADC. In the same way,
the host ADC event inputs will be automatically routed to the client ADC, meaning that the input events configuration
must be done in the host ADC (ADC0.EVCTRL).
ADC measurements can be started simultaneously on both ADC’s or interleaved. The trigger mode selection is
available in the host ADC Control C register (ADC0.CTRLC.DUALSEL).
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Analog-to-Digital Converter (ADC)
To restart an interleaved sequence, the user can apply different options:
• Flush the host ADC (ADC0.SWTRIG.FLUSH = 1)
• Disable/re-enable the host ADC (ADC0.CTRLA.ENABLE)
• Reset and reconfigure host ADC (ADC0.CTRLA.SWRST = 1)
Figure 36-10. Interleaved Dual-Mode Trigger Selection
Start Trigger
(Software or Event)
ADC0 Start Conversion
ADC1 Start Conversion
ADC0 Start Conversion
ADC1 Start Conversion
ADC0 Start Conversion
36.6.3.2 Rail-to-Rail Operation
The accuracy of the ADC is highest when the input common mode voltage (VCMIN) is close to VREF/2. To enable a
full range of common mode voltages (rail-to-rail operation), the Rail-to-Rail bit in the Control C register (CTRLC.R2R)
should be written to one. Rail-to-rail operation requires a sampling period of four cycles. This is achieved by
enabling offset compensation (SAMPCTRL.OFFCOMP = 1). Rail-to-rail operation should not be used when offset
compensation is disabled.
36.6.3.3 Double Buffering
The following registers are double buffered:
•
•
•
•
•
•
•
•
Input Control (INPUTCTRL)
Control C (CTRLC)
Average Control (AVGCTRL)
Sampling Time Control (SAMPCTRL)
Window Monitor Lower Threshold (WINLT)
Window Monitor Upper Threshold (WINUT)
Gain Correction (GAINCORR)
Offset Correction (OFFSETCORR)
When one of these registers is written, the data is stored in the corresponding buffer as long as the current
conversion is not impacted, and the corresponding busy status will be set in the Synchronization Busy register
(SYNCBUSY). When a new RESULT is available, data stored in the buffer registers will be transfered to the ADC and
a new conversion can start.
36.6.4
DMA Operation
The ADC generates the following DMA request:
•
36.6.5
Result Conversion Ready (RESRDY): the request is set when a conversion result is available and cleared
when the RESULT register is read. When the averaging operation is enabled, the DMA request is set when the
averaging is completed and result is available.
Interrupts
The ADC has the following interrupt sources:
•
•
•
Result Conversion Ready: RESRDY
Window Monitor: WINMON
Overrun: OVERRUN
These interrupts, except the OVERRUN interrupt, are asynchronous wake-up sources. Refer to 16.5.3.3 Sleep Mode
Controller for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing
a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to
the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when
the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the
interrupt flag is cleared, the interrupt is disabled, or the ADC is reset. See INTFLAG register for details on how to
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Analog-to-Digital Converter (ADC)
clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one
combined interrupt request to the NVIC. Refer to 9.2 Nested Vector Interrupt Controller for details. The user must
read the 13.6.3 INTFLAG register to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt
Controller for details.
36.6.6
Events
The ADC can generate the following output events:
•
•
Result Ready (RESRDY): Generated when the conversion is complete and the result is available. Refer to
36.7.4 EVCTRL for details.
Window Monitor (WINMON): Generated when the window monitor condition match. Refer to 36.7.10 CTRLC for
details.
Setting an Event Output bit in the Event Control Register (EVCTRL.xxEO=1) enables the corresponding output event.
Clearing this bit disables the corresponding output event. Refer to the Event System chapter for details on configuring
the event system.
The ADC can take the following actions on an input event:
•
•
Start conversion (START): Start a conversion. Refer to 36.7.17 SWTRIG for details.
Conversion flush (FLUSH): Flush the conversion. Refer to 36.7.17 SWTRIG for details.
Setting an Event Input bit in the Event Control register (EVCTRL.xxEI=1) enables the corresponding action on input
event. Clearing this bit disables the corresponding action on input event.
The ADC uses only asynchronous events, so the asynchronous Event System channel path must be configured. By
default, the ADC will detect a rising edge on the incoming event. If the ADC action must be performed on the falling
edge of the incoming event, the event line must be inverted first. This is done by setting the corresponding Event
Invert Enable bit in Event Control register (EVCTRL.xINV=1).
Note: If several events are connected to the ADC, the enabled action will be taken on any of the incoming events. If
FLUSH and START events are available at the same time, the FLUSH event has priority.
For further information, refer to the 28. Event System (EVSYS).
36.6.7
Sleep Mode Operation
The ONDEMAND and RUNSTDBY bits in the Control A register (CTRLA) control the behavior of the ADC during
Standby Sleep mode, in cases where the ADC is enabled (CTRLA.ENABLE = 1). When exiting Standby Sleep mode
the software trigger bit in the Synchronization Busy register (SYNCBUSY.SWTRIG) will be '1'. After the next RESULT,
start the ADC again by writing the Software Trigger Start bit (SWTRIG.START) to '1'. For further details on available
options, refer to the following table.
When the device is in Standby Sleep mode, the DMA is not able to write the SWTRIG register. To write the SWTRIG
register with the DMA the device must be in Active mode or in Idle Sleep mode.
Note: When CTRLA.ONDEMAND = 1, the analog block is powered off when the conversion is complete. When a
start request is detected, the system returns from sleep and starts a new conversion after the start-up time delay.
Table 36-4. ADC Sleep Behavior
CTRLA.RUNSTDBY CTRLA.ONDEMAND CTRLA.ENABLE
Description
x
x
0
Disabled
0
0
1
Run in all sleep modes except Standby mode.
0
1
1
Run in all sleep modes on request, except
Standby mode.
1
0
1
Run in all sleep modes.
1
1
1
Run in all sleep modes on request.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 712
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.6.8
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
•
•
Software Reset bit in Control A register (CTRLA.SWRST)
Enable bit in Control A register (CTRLA.ENABLE)
The following registers are synchronized when written:
•
•
•
•
•
•
•
•
•
Input Control register (INPUTCTRL)
Control C register (CTRLC)
Average control register (AVGCTRL)
Sampling time control register (SAMPCTRL)
Window Monitor Lower Threshold register (WINLT)
Window Monitor Upper Threshold register (WINUT)
Gain correction register (GAINCORR)
Offset Correction register (OFFSETCORR)
Software Trigger register (SWTRIG)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 713
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.7
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
CTRLA
CTRLB
REFCTRL
EVCTRL
INTENCLR
INTENSET
INTFLAG
SEQSTATUS
0x08
INPUTCTRL
0x0A
CTRLC
0x0C
0x0D
AVGCTRL
SAMPCTRL
0x0E
WINLT
0x10
WINUT
0x12
GAINCORR
0x14
OFFSETCORR
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
7:0
15:8
7:0
7:0
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
0x16
...
0x17
0x18
0x19
...
0x1B
0x1C
0x1D
...
0x1F
7
6
ONDEMAND RUNSTDBY
REFCOMP
SEQBUSY
R2R
OFFCOMP
5
4
3
2
1
0
SLAVEEN
ENABLE
SWRST
PRESCALER[2:0]
REFSEL[3:0]
WINMONEO RESRDYEO STARTINV
FLUSHINV
STARTEI
FLUSHEI
WINMON
OVERRUN
RESRDY
WINMON
OVERRUN
RESRDY
WINMON
OVERRUN
RESRDY
SEQSTATE[4:0]
MUXPOS[4:0]
MUXNEG[4:0]
RESSEL[1:0]
CORREN
FREERUN
LEFTADJ
DIFFMODE
DUALSEL[1:0]
WINMODE[2:0]
ADJRES[2:0]
SAMPLENUM[3:0]
SAMPLEN[5:0]
WINLT[7:0]
WINLT[15:8]
WINUT[7:0]
WINUT[15:8]
GAINCORR[7:0]
GAINCORR[11:8]
OFFSETCORR[7:0]
OFFSETCORR[11:8]
Reserved
SWTRIG
7:0
START
FLUSH
Reserved
DBGCTRL
7:0
DBGRUN
Reserved
7:0
0x20
SYNCBUSY
0x22
...
0x23
Reserved
0x24
RESULT
0x26
...
0x27
Reserved
0x28
SEQCTRL
0x2C
CALIB
WINUT
SAMPCTRL
AVGCTRL
CTRLC
15:8
INPUTCTRL
SWTRIG
7:0
15:8
RESULT[7:0]
RESULT[15:8]
7:0
15:8
23:16
31:24
7:0
15:8
SEQEN[7:0]
SEQEN[15:8]
SEQEN[23:16]
SEQEN[31:24]
© 2021 Microchip Technology Inc.
and its subsidiaries
WINLT
ENABLE
SWRST
OFFSETCOR
GAINCORR
R
BIASCOMP[2:0]
BIASREFBUF[2:0]
Datasheet
DS60001638D-page 714
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.7.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
CTRLA
0x00
0x00
PAC Write-Protection, Write-Synchronized Bits
7
ONDEMAND
R/W
0
6
RUNSTDBY
R/W
0
5
SLAVEEN
R/W
0
4
3
2
1
ENABLE
R/W
0
0
SWRST
R/W
0
Bit 7 – ONDEMAND On Demand Control
The On Demand operation mode allows the ADC to be enabled or disabled, depending on other peripheral requests.
In On Demand operation mode, i.e., if the ONDEMAND bit has been previously set, the ADC will only be running
when requested by a peripheral. If there is no peripheral requesting the ADC will be in a disabled state.
If On Demand is disabled the ADC will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the CTRLA.RUNSTDBY bit is '1'. If
CTRLA.RUNSTDBY is '0', the ADC is disabled.
Note: This bit is not synchronized.
For the client ADC, this bit has no effect when the SLAVEEN bit is set (CTRLA.SLAVEEN= 1). ONDEMAND bit from
host ADC instance will control the On Demand operation mode.
Value
Description
0
The ADC is always on , if enabled.
1
The ADC is enabled, when a peripheral is requesting the ADC conversion. The ADC is disabled if no
peripheral is requesting it.
Bit 6 – RUNSTDBY Run in Standby
This bit controls how the ADC behaves during standby sleep mode.
Note: This bit is not synchronized.
For the client ADC, this bit has no effect when the SLAVEEN bit is set (CTRLA.SLAVEEN= 1). RUNSTDBY bit from
host ADC instance will control the client ADC operation in standby sleep mode.
Value
Description
0
The ADC is halted during standby sleep mode.
1
The ADC is not stopped in standby sleep mode. If CTRLA.ONDEMAND=1, the ADC will be running
when a peripheral is requesting it. If CTRLA.ONDEMAND=0, the ADC will always be running in
standby sleep mode.
Bit 5 – SLAVEEN Client Enable
This bit enables the host/client operation and it is available only in the client ADC instance (ADC1).
Note: This bit is not synchronized.
This bit can be set only for the client ADC (ADC1). For the host ADC (ADC0), this bit is always read zero.
Value
Description
0
The host-client operation is disabled.
1
The ADC1 is enabled as a client of ADC0
Bit 1 – ENABLE Enable
Note: This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE.
For the client ADC, this bit has no effect when the SLAVEEN bit is set (CTRLA.SLAVEEN= 1).
Value
Description
0
The ADC is disabled.
1
The ADC is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 715
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the ADC, except DBGCTRL, to their initial state, and the ADC will be
disabled.
Writing a '1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Note: This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST
synchronization is complete.
Value
0
1
Description
There is no reset operation ongoing.
The reset operation is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 716
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.7.2
Control B
Name:
Offset:
Reset:
Property:
Bit
CTRLB
0x01
0x00
PAC Write-Protection, Enable-Protected
7
6
5
4
3
Access
Reset
2
R/W
0
1
PRESCALER[2:0]
R/W
0
0
R/W
0
Bits 2:0 – PRESCALER[2:0] Prescaler Configuration
This field defines the ADC clock relative to the peripheral clock.
This field is not synchronized. For the client ADC, these bits have no effect when the SLAVEEN bit is set
(CTRLA.SLAVEEN= 1).
Value
Name
Description
0x0
DIV2
Peripheral clock divided by 2
0x1
DIV4
Peripheral clock divided by 4
0x2
DIV8
Peripheral clock divided by 8
0x3
DIV16
Peripheral clock divided by 16
0x4
DIV32
Peripheral clock divided by 32
0x5
DIV64
Peripheral clock divided by 64
0x6
DIV128
Peripheral clock divided by 128
0x7
DIV256
Peripheral clock divided by 256
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 717
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.7.3
Reference Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
REFCTRL
0x02
0x00
PAC Write-Protection, Enable-Protected
7
REFCOMP
R/W
0
6
5
4
3
R/W
0
2
1
REFSEL[3:0]
R/W
R/W
0
0
0
R/W
0
Bit 7 – REFCOMP Reference Buffer Offset Compensation Enable
The gain error can be reduced by enabling the reference buffer offset compensation. This will increase the
start-up time of the reference. When using REFCOMP and if the ADC reference selection is not using VDDANA
(REFCTRL.REFSEL != INTVCC2), the first 5 conversions of the ADC must be discarded after the ADC is enabled.
Value
Description
0
Reference buffer offset compensation is disabled.
1
Reference buffer offset compensation is enabled.
Bits 3:0 – REFSEL[3:0] Reference Selection
These bits select the reference for the ADC.
Value
Name
Description
0x0
INTREF internal reference voltage, supplied by the bandgap (refer to SUPC.VREF.SEL) for voltage
level information)
x01
INTVCC0 1/1.6 VDDANA
0x2
INTVCC1 1/2 VDDANA (only for VDDANA > 4.0V)
0x3
VREFA
External reference
0x4
DAC
DAC internal output
0x5
INTVCC2 VDDANA
0x6 Reserved
0xF
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 718
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.7.4
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x03
0x00
PAC Write-Protection, Enable-Protected
7
6
Access
Reset
5
WINMONEO
R/W
0
4
RESRDYEO
R/W
0
3
STARTINV
R/W
0
2
FLUSHINV
R/W
0
1
STARTEI
R/W
0
0
FLUSHEI
R/W
0
Bit 5 – WINMONEO Window Monitor Event Out
This bit indicates whether the Window Monitor event output is enabled or not and an output event will be generated
when the window monitor detects something.
Value
Description
0
Window Monitor event output is disabled and an event will not be generated.
1
Window Monitor event output is enabled and an event will be generated.
Bit 4 – RESRDYEO Result Ready Event Out
This bit indicates whether the Result Ready event output is enabled or not and an output event will be generated
when the conversion result is available.
Value
Description
0
Result Ready event output is disabled and an event will not be generated.
1
Result Ready event output is enabled and an event will be generated.
Bit 3 – STARTINV Start Conversion Event Invert Enable
For the client ADC, this bit has no effect when the SLAVEEN bit is set (CTRLA.SLAVEEN= 1).
Value
Description
0
Start event input source is not inverted.
1
Start event input source is inverted.
Bit 2 – FLUSHINV Flush Event Invert Enable
For the client ADC, this bit has no effect when the SLAVEEN bit is set (CTRLA.SLAVEEN= 1).
Value
Description
0
Flush event input source is not inverted.
1
Flush event input source is inverted.
Bit 1 – STARTEI Start Conversion Event Input Enable
For the client ADC, this bit has no effect when the SLAVEEN bit is set (CTRLA.SLAVEEN= 1).
Value
Description
0
A new conversion will not be triggered on any incoming event.
1
A new conversion will be triggered on any incoming event.
Bit 0 – FLUSHEI Flush Event Input Enable
For the client ADC, this bit has no effect when the SLAVEEN bit is set (CTRLA.SLAVEEN= 1).
Value
Description
0
A flush and new conversion will not be triggered on any incoming event.
1
A flush and new conversion will be triggered on any incoming event.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 719
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.7.5
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x04
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
7
6
5
4
3
Access
Reset
2
WINMON
R/W
0
1
OVERRUN
R/W
0
0
RESRDY
R/W
0
Bit 2 – WINMON Window Monitor Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Window Monitor Interrupt Enable bit, which disables the corresponding interrupt
request.
Value
Description
0
The window monitor interrupt is disabled.
1
The window monitor interrupt is enabled, and an interrupt request will be generated when the Window
Monitor interrupt flag is set.
Bit 1 – OVERRUN Overrun Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overrun Interrupt Enable bit, which disables the corresponding interrupt request.
Value
Description
0
The Overrun interrupt is disabled.
1
The Overrun interrupt is enabled, and an interrupt request will be generated when the Overrun interrupt
flag is set.
Bit 0 – RESRDY Result Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Result Ready Interrupt Enable bit, which disables the corresponding interrupt
request.
Value
Description
0
The Result Ready interrupt is disabled.
1
The Result Ready interrupt is enabled, and an interrupt request will be generated when the Result
Ready interrupt flag is set.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 720
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.7.6
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x05
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
7
6
5
4
3
Access
Reset
2
WINMON
R/W
0
1
OVERRUN
R/W
0
0
RESRDY
R/W
0
Bit 2 – WINMON Window Monitor Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Window Monitor Interrupt bit, which enables the Window Monitor interrupt.
Value
Description
0
The Window Monitor interrupt is disabled.
1
The Window Monitor interrupt is enabled.
Bit 1 – OVERRUN Overrun Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Overrun Interrupt bit, which enables the Overrun interrupt.
Value
Description
0
The Overrun interrupt is disabled.
1
The Overrun interrupt is enabled.
Bit 0 – RESRDY Result Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Result Ready Interrupt bit, which enables the Result Ready interrupt.
Value
Description
0
The Result Ready interrupt is disabled.
1
The Result Ready interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 721
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.7.7
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAG
0x06
0x00
–
6
5
4
3
Access
Reset
2
WINMON
R/W
0
1
OVERRUN
R/W
0
0
RESRDY
R/W
0
Bit 2 – WINMON Window Monitor
This flag is cleared by writing a '1' to the flag or by reading the RESULT register.
This flag is set on the next GCLK_ADC cycle after a match with the window monitor condition, and an interrupt
request will be generated if INTENCLR/SET.WINMON is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Window Monitor interrupt flag.
Bit 1 – OVERRUN Overrun
This flag is cleared by writing a '1' to the flag.
This flag is set if RESULT is written before the previous value has been read by CPU, and an interrupt request will be
generated if INTENCLR/SET.OVERRUN=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overrun interrupt flag.
Bit 0 – RESRDY Result Ready
This flag is cleared by writing a '1' to the flag or by reading the RESULT register.
This flag is set when the conversion result is available, and an interrupt will be generated if INTENCLR/
SET.RESRDY=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Result Ready interrupt flag.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 722
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.7.8
Sequence Status
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
SEQBUSY
R
0
SEQSTATUS
0x07
0x00
-
6
5
4
3
R
0
R
0
2
SEQSTATE[4:0]
R
0
1
0
R
0
R
0
Bit 7 – SEQBUSY Sequence busy
This bit is set when the sequence start.
This bit is clear when the last conversion in a sequence is done.
Bits 4:0 – SEQSTATE[4:0] Sequence State
These bit fields are the pointer of sequence. This value identifies the last conversion done in the sequence.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 723
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.7.9
Input Control
Name:
Offset:
Reset:
Property:
INPUTCTRL
0x08
0x0000
PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.INPUTCTRL must be checked to ensure the INPUTCTRL
register synchronization is complete.
Bit
15
14
13
Access
Reset
Bit
7
6
Access
Reset
5
12
11
R/W
0
R/W
0
4
3
R/W
0
R/W
0
10
MUXNEG[4:0]
R/W
0
2
MUXPOS[4:0]
R/W
0
9
8
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Bits 12:8 – MUXNEG[4:0] Negative MUX Input Selection
These bits define the MUX selection for the negative ADC input.
Value
Name
Description
0x00
AIN0
ADC AIN0 pin
0x01
AIN1
ADC AIN1 pin
0x02
AIN2
ADC AIN2 pin
0x03
AIN3
ADC AIN3 pin
0x04
AIN4
ADC AIN4 pin
0x05
AIN5
ADC AIN5 pin
0x06 Reserved
0x17
0x18
GND
Internal ground
0x19 Reserved
0x1F
Bits 4:0 – MUXPOS[4:0] Positive MUX Input Selection
These bits define the MUX selection for the positive ADC input. If the internal INTREF voltage input channel
is selected, then the Sampling Time Length bit group in the Sampling Control register must be written with a
corresponding value.
Value
Name
Description
0x00
AIN0
ADC AIN0 pin
0x01
AIN1
ADC AIN1 pin
0x02
AIN2
ADC AIN2 pin
0x03
AIN3
ADC AIN3 pin
0x04
AIN4
ADC AIN4 pin
0x05
AIN5
ADC AIN5 pin
0x06
AIN6
ADC AIN6 pin
0x07
AIN7
ADC AIN7 pin
0x08
AIN8
ADC AIN8 pin
0x09
AIN9
ADC AIN9 pin
0x0A
AIN10
ADC AIN10 pin
0x0B
AIN11
ADC AIN11 pin
0xC Reserved
0x18
0x19
INTREF
Internal voltage reference, supplied by the bandgap (refer to SUPC.VREF.SEL
for voltage level information)
0x1A
SCALEDVDDCORE 1/4 Scaled VDDCORE Supply
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 724
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
Value
0x1B
0x1C
0x1D
0x1E
0x1F
Name
SCALEDVDDANA
-
© 2021 Microchip Technology Inc.
and its subsidiaries
Description
1/4 Scaled VDDANA Supply
Reserved
Reserved
Reserved
Reserved
Datasheet
DS60001638D-page 725
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.7.10 Control C
Name:
Offset:
Reset:
Property:
CTRLC
0x0A
0x0000
PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CTRLC must be checked to ensure the CTRLC register
synchronization is complete.
Bit
15
14
Access
Reset
Bit
Access
Reset
7
R2R
R/W
0
6
13
12
DUALSEL[1:0]
R/W
R/W
0
0
5
4
RESSEL[1:0]
R/W
R/W
0
0
11
3
CORREN
R/W
0
10
R/W
0
9
WINMODE[2:0]
R/W
0
8
R/W
0
2
FREERUN
R/W
0
1
LEFTADJ
R/W
0
0
DIFFMODE
R/W
0
Bits 13:12 – DUALSEL[1:0] Dual Mode Trigger Selection
These bits define the trigger mode. These bits are available in the host ADC and have no effect if the host-client
operation is disabled (ADC1.CTRLA.SLAVEEN=0).
Value
Name
Description
0x0
BOTH
Start event or software trigger will start a conversion on both ADCs.
0x1
INTERLEAVE Start event or software trigger will alternatively start a conversion on ADC0 and ADC1.
0x2 Reserved
0x3
Bits 10:8 – WINMODE[2:0] Window Monitor Mode
These bits enable and define the window monitor mode.
Value
Name
Description
0x0
DISABLE
No window mode (default)
0x1
MODE1
RESULT > WINLT
0x2
MODE2
RESULT < WINUT
0x3
MODE3
WINLT < RESULT < WINUT
0x4
MODE4
WINUT < RESULT < WINLT
0x5 Reserved
0x7
Bit 7 – R2R Rail-to-Rail Operation
Value
Description
0
Disable rail-to-rail operation.
1
Enable rail-to-rail operation to increase the allowable range of the input common mode voltage
(VCMIN). When R2R is one, a sampling period of four cycles is required. Offset compensation
(SAMPCTRL.OFFCOMP) must be written to one when using this period.
Bits 5:4 – RESSEL[1:0] Conversion Result Resolution
These bits define whether the ADC completes the conversion 12-, 10- or 8-bit result resolution.
Value
Name
Description
0x0
12BIT
12-bit result
0x1
16BIT
Accumulation or Oversampling and Decimation modes
0x2
10BIT
10-bit result
0x3
8BIT
8-bit result
Bit 3 – CORREN Digital Correction Logic Enabled
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 726
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
Value
0
1
Description
Disable the digital result correction.
Enable the digital result correction. The ADC conversion result in the RESULT register is then
corrected for gain and offset based on the values in the GAINCORR and OFFSETCORR registers.
Conversion time will be increased by 13 cycles according to the value in the Offset Correction Value bit
group in the Offset Correction register.
Bit 2 – FREERUN Free Running Mode
Value
Description
0
The ADC run in single conversion mode.
1
The ADC is in free running mode and a new conversion will be initiated when a previous conversion
completes.
Bit 1 – LEFTADJ Left-Adjusted Result
Value
Description
0
The ADC conversion result is right-adjusted in the RESULT register.
1
The ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result
will be present in the upper part of the result register.
Bit 0 – DIFFMODE Differential Mode
Value
Description
0
The ADC is running in singled-ended mode.
1
The ADC is running in differential mode. In this mode, the voltage difference between the MUXPOS
and MUXNEG inputs will be converted by the ADC.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 727
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.7.11 Average Control
Name:
Offset:
Reset:
Property:
AVGCTRL
0x0C
0x00
PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.AVGCTRL must be checked to ensure the AVGCTRL register
synchronization is complete.
Bit
7
Access
Reset
6
R/W
0
5
ADJRES[2:0]
R/W
0
4
3
R/W
0
R/W
0
2
1
SAMPLENUM[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 6:4 – ADJRES[2:0] Adjusting Result / Division Coefficient
These bits define the division coefficient in 2n steps.
Bits 3:0 – SAMPLENUM[3:0] Number of Samples to be Collected
These bits define how many samples are added together. The result will be available in the Result register
(RESULT). Note: if the result width increases, CTRLC.RESSEL must be changed.
Value
Description
0x0
1 sample
0x1
2 samples
0x2
4 samples
0x3
8 samples
0x4
16 samples
0x5
32 samples
0x6
64 samples
0x7
128 samples
0x8
256 samples
0x9
512 samples
0xA
1024 samples
0xB Reserved
0xF
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 728
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.7.12 Sampling Time Control
Name:
Offset:
Reset:
Property:
SAMPCTRL
0x0D
0x00
PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.SAMPCTRL must be checked to ensure the SAMPCTRL
register synchronization is complete.
Bit
Access
Reset
7
OFFCOMP
R/W
0
6
5
4
R/W
0
R/W
0
3
2
SAMPLEN[5:0]
R/W
R/W
0
0
1
0
R/W
0
R/W
0
Bit 7 – OFFCOMP Comparator Offset Compensation Enable
Setting this bit enables the offset compensation for each sampling period to ensure low offset and immunity to
temperature or voltage drift. This compensation increases the sampling time by three clock cycles that results in a
fixed sampling duration of 4 CLK_ADC cycles.
This bit must be set to zero to validate the SAMPLEN value. It’s not possible to use OFFCOMP=1 and SAMPLEN>0.
Bits 5:0 – SAMPLEN[5:0] Sampling Time Length
These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus
controlling the ADC input impedance. Sampling time is set according to the equation:
Sampling time = SAMPLEN+1 ⋅ CLKADC
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 729
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.7.13 Window Monitor Lower Threshold
Name:
Offset:
Reset:
Property:
WINLT
0x0E
0x0000
PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.WINLT must be checked to ensure the WINLT register
synchronization is complete.
Bit
Access
Reset
Bit
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
WINLT[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
WINLT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WINLT[15:0] Window Lower Threshold
If the window monitor is enabled (CTRLC.WINMODE != 0), these bits define the lower threshold value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 730
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.7.14 Window Monitor Upper Threshold
Name:
Offset:
Reset:
Property:
WINUT
0x10
0x0000
PAV Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.WINUT must be checked to ensure the WINUT register
synchronization is complete.
Bit
Access
Reset
Bit
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
WINUT[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
WINUT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WINUT[15:0] Window Upper Threshold
If the window monitor is enabled (CTRLC.WINMODE != 0), these bits define the upper threshold value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 731
PIC32CM MC00 Family
Analog-to-Digital Converter (ADC)
36.7.15 Gain Correction
Name:
Offset:
Reset:
Property:
GAINCORR
0x12
0x0000
PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.GAINCORR must be checked to ensure the GAINCORR
register synchronization is complete.
Bit
15
14
13
Access
Reset
Bit
Access
Reset
12
11
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
4
3
GAINCORR[7:0]
R/W
R/W
0
0
10
9
GAINCORR[11:8]
R/W
R/W
0
0
8
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 11:0 – GAINCORR[11:0] Gain Correction Value
If CTRLC.CORREN=1, these bits define how the ADC conversion result is compensated for gain error before being
written to the result register. The gain correction is a fractional value, a 1-bit integer plus an 11-bit fraction, and
therefore ½ WINLT
0x2
BELOW
RESULT < WINUT
0x3
INSIDE
WINLT < RESULT < WINUT
0x4
OUTSIDE
WINUT < RESULT or RESULT < WINLT
0x5 Reserved
0x7
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 760
PIC32CM MC00 Family
Sigma-Delta Analog-to-Digital Converter (SDA...
37.7.12 Window Monitor Lower Threshold
Name:
Offset:
Reset:
Property:
Bit
WINLT
0x0C
0x00000000
PAC Write-Protection, Write-Synchronized
31
30
29
28
23
22
21
20
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
27
26
25
24
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
19
WINLT[23:16]
R/W
R/W
0
0
12
11
WINLT[15:8]
R/W
R/W
0
0
4
WINLT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 23:0 – WINLT[23:0] Window Lower Threshold
If the window monitor is enabled, these bits define the lower threshold value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 761
PIC32CM MC00 Family
Sigma-Delta Analog-to-Digital Converter (SDA...
37.7.13 Window Monitor Upper Threshold
Name:
Offset:
Reset:
Property:
Bit
WINUT
0x10
0x00000000
PAC Write-Protection, Write-Synchronized
31
30
29
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
28
27
26
25
24
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
20
19
WINUT[23:16]
R/W
R/W
0
0
12
11
WINUT[15:8]
R/W
R/W
0
0
4
WINUT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 23:0 – WINUT[23:0] Window Upper Threshold
If the window monitor is enabled, these bits define the upper threshold value.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 762
PIC32CM MC00 Family
Sigma-Delta Analog-to-Digital Converter (SDA...
37.7.14 Offset Correction
Name:
Offset:
Reset:
Property:
Bit
OFFSETCORR
0x14
0x00000000
PAC Write-Protection, Write-Synchronized
31
30
29
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
26
25
24
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
20
19
OFFSETCORR[23:16]
R/W
R/W
0
0
12
11
OFFSETCORR[15:8]
R/W
R/W
0
0
4
3
OFFSETCORR[7:0]
R/W
R/W
0
0
Bits 23:0 – OFFSETCORR[23:0] Offset Correction
The OFFSETCORR is a signed integer value.
A specific offset, gain and shift can be applied to SDADC by performing the following operation:
(RESULT + OFFSETCORR)*GAINCORR/2^SHIFTCORR
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 763
PIC32CM MC00 Family
Sigma-Delta Analog-to-Digital Converter (SDA...
37.7.15 Gain Correction
Name:
Offset:
Reset:
Property:
Bit
15
GAINCORR
0x18
0x0001
PAC Write-Protection, Write-Synchronized
14
Access
Reset
13
12
R
0
R
0
4
3
GAINCORR[7:0]
R
R
0
0
Bit
7
6
5
Access
Reset
R
1
R
0
R
0
11
10
GAINCORR[13:8]
R
R
0
0
9
8
R
0
R
0
2
1
0
R
0
R
0
R
0
Bits 13:0 – GAINCORR[13:0] Gain Correction
A specific offset, gain and shift can be applied to SDADC by performing the following operation:
(RESULT + OFFSETCORR)*GAINCORR/2^SHIFTCORR
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 764
PIC32CM MC00 Family
Sigma-Delta Analog-to-Digital Converter (SDA...
37.7.16 Shift Correction
Name:
Offset:
Reset:
Property:
Bit
7
SHIFTCORR
0x1A
0x00
PAC Write-Protection, Write-Synchronized
6
Access
Reset
5
4
3
R/W
0
2
1
SHIFTCORR[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 3:0 – SHIFTCORR[3:0] Shift Correction
A specific offset, gain and shift can be applied to SDADC by performing the following operation:
(RESULT + OFFSETCORR)*GAINCORR/2^SHIFTCORR
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 765
PIC32CM MC00 Family
Sigma-Delta Analog-to-Digital Converter (SDA...
37.7.17 Software Trigger
Name:
Offset:
Reset:
Property:
Bit
7
SWTRIG
0x1C
0x00
PAC Write-Protection, Write-Synchronized
6
5
4
3
Access
Reset
2
1
START
W
0
0
FLUSH
W
0
Bit 1 – START SDADC Start Conversion
Writing a one to this bit will start a conversion or sequence. The bit is cleared by hardware when the conversion has
started. Setting this bit when it is already set has no effect.
Writing this bit to zero will have no effect.
Bit 0 – FLUSH SDADC Conversion Flush
Writing a one to this bit will be flush the SDADC pipeline. A flush will restart the SDADC conversion and all
conversions in progress will be aborted and lost. This bit is cleared until the SDADC has been flushed.
After the flush, the ADC will resume where it left off; i.e., if a conversion was pending, the ADC will start a new
conversion.
Writing this bit to zero will have no effect.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 766
PIC32CM MC00 Family
Sigma-Delta Analog-to-Digital Converter (SDA...
37.7.18 Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x20
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
ANACTRL
R
0
10
SWTRIG
R
0
9
SHIFTCORR
R
0
8
GAINCORR
R
0
6
WINUT
R
0
5
WINLT
R
0
4
WINCTRL
R
0
3
MUXCTRL
R
0
2
CTRLC
R
0
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
OFFSETCORR
Access
R
Reset
0
Bit 11 – ANACTRL Analog Control Synchronization Busy
This bit is cleared when the synchronization of ANACTRL register between the clock domains is complete.
This bit is set when the synchronization of ANACTRL register between clock domains is started.
Bit 10 – SWTRIG Software Trigger Synchronization Busy
This bit is cleared when the synchronization of SWTRIG register between the clock domains is complete.
This bit is set when the synchronization of SWTRIG register between clock domains is started.
Bit 9 – SHIFTCORR Shift Correction Synchronization Busy
This bit is cleared when the synchronization of SHIFTCORR register between the clock domains is complete.
This bit is set when the synchronization of SHIFTCORR register between clock domains is started.
Bit 8 – GAINCORR Gain Correction Synchronization Busy
This bit is cleared when the synchronization of GAINCORR register between the clock domains is complete.
This bit is set when the synchronization of GAINCORR register between clock domains is started.
Bit 7 – OFFSETCORR Offset Correction Synchronization Busy
This bit is cleared when the synchronization of OFFSETCORR register between the clock domains is complete.
This bit is set when the synchronization of OFFSETCORR register between clock domains is started.
Bit 6 – WINUT Window Monitor Lower Threshold Synchronization Busy
This bit is cleared when the synchronization of WINUT register between the clock domains is complete.
This bit is set when the synchronization of WINUT register between clock domains is started.
Bit 5 – WINLT Window Monitor Upper Threshold Synchronization Busy
This bit is cleared when the synchronization of WINLT register between the clock domains is complete.
This bit is set when the synchronization of WINLT register between clock domains is started.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 767
PIC32CM MC00 Family
Sigma-Delta Analog-to-Digital Converter (SDA...
Bit 4 – WINCTRL Window Monitor Control Synchronization Busy
This bit is cleared when the synchronization of WINCTRL register between the clock domains is complete.
This bit is set when the synchronization of WINCTRL register between clock domains is started.
Bit 3 – MUXCTRL Mux Control Synchronization Busy
This bit is cleared when the synchronization of MUXCTRL register between the clock domains is complete.
This bit is set when the synchronization of MUXCTRL register between clock domains is started.
Bit 2 – CTRLC Control C Synchronization Busy
This bit is cleared when the synchronization of CTRLC register between the clock domains is complete.
This bit is set when the synchronization of CTRLC register between clock domains is started.
Bit 1 – ENABLE ENABLE Synchronization Busy
This bit is cleared when the synchronization of ENABLE register between the clock domains is complete.
This bit is set when the synchronization of ENABLE register between clock domains is started.
Bit 0 – SWRST SWRST Synchronization Busy
This bit is cleared when the synchronization of SWRST register between the clock domains is complete.
This bit is set when the synchronization of SWRST register between clock domains is started
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 768
PIC32CM MC00 Family
Sigma-Delta Analog-to-Digital Converter (SDA...
37.7.19 Result
Name:
Offset:
Reset:
Property:
Bit
RESULT
0x24
0x00000000
-
31
30
29
28
27
26
25
24
Bit
23
22
21
18
17
16
Access
Reset
R
0
R
0
R
0
20
19
RESULT[23:16]
R
R
0
0
R
0
R
0
R
0
Bit
15
14
13
10
9
8
Access
Reset
R
0
R
0
R
0
12
11
RESULT[15:8]
R
R
0
0
R
0
R
0
R
0
Bit
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
RESULT[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 23:0 – RESULT[23:0] Result Conversion Value
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new
conversion is completed.
The RESULT is a signed integer value with 24-bit size. The SDADC conversion result is left-adjusted in the RESULT
register.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 769
PIC32CM MC00 Family
Sigma-Delta Analog-to-Digital Converter (SDA...
37.7.20 Sequence Control
Name:
Offset:
Reset:
Property:
Bit
7
SEQCTRL
0x28
0x00
PAC Write-Protection
6
5
4
3
Access
Reset
2
R/W
0
1
SEQENn[2:0]
R/W
0
0
R/W
0
Bits 2:0 – SEQENn[2:0] Enable Positive Input in the Sequence
For details on available mux selections, refer to 37.7.9 INPUTCTRL.
The sequence start from the lowest input, and go to the next enabled input automatically when the conversion is
done. If no bits are set the sequence is disabled.
Value
Description
0
Disable the positive input mux n selection from the sequence.
1
Enable the positive input mux n selection to the sequence.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 770
PIC32CM MC00 Family
Sigma-Delta Analog-to-Digital Converter (SDA...
37.7.21 Analog Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
ANACTRL
0x2C
0x00
PAC Write-Protection, Write-Synchronized.
7
BUFTEST
R/W
0
6
ONCHOP
R/W
0
5
4
3
R/W
0
R/W
0
2
CTLSDADC[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bit 7 – BUFTEST Buffer Test
Bit 6 – ONCHOP ONCHOP
Value
Description
0
No Chopper at SDADC input
1
Chopper at SDADC input
Bits 4:0 – CTLSDADC[4:0] CTLSDADC
SDADC Bias Current Control and used for Debugg/Characterization
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 771
PIC32CM MC00 Family
Sigma-Delta Analog-to-Digital Converter (SDA...
37.7.22 Debug Control
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x2E
0x00
PAC Write-Protectedion
6
5
4
3
2
1
0
DBGRUN
R/W
0
Access
Reset
Bit 0 – DBGRUN Debug Run
This bit is reset by a system software reset.
This bit controls the functionality when the CPU is halted by an external debugger.
This bit should be written only while a conversion is not ongoing.
Value
Description
0
The SDADC is halted when the CPU is halted by an external debugger.
1
The SDADC continues normal operation when the CPU is halted by an external debugger.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 772
PIC32CM MC00 Family
Analog Comparators (AC)
38.
38.1
Analog Comparators (AC)
Overview
The Analog Comparator (AC) supports multiple individual comparators. Each comparator (COMP) compares the
voltage levels on two inputs, and provides a digital output based on this comparison. Each comparator may be
configured to generate interrupt requests and peripheral events upon several combinations of input change.
Hysteresis and propagation delay can be adjusted to achieve optimal operation for each application.
The input selection includes four shared analog port pins and several internal signals. Each Comparator Output state
can also be output on a pin for use by external devices.
The comparators are grouped in pairs on each port. The AC peripheral implements one pair of comparators and one
stand alone comparator. These are called Comparator 0 (COMP0) and Comparator 1 (COMP1). The pair can be set
in Window mode to compare a signal to a voltage range instead of a single voltage level.
38.2
Features
•
•
•
•
•
•
•
•
•
•
Two individual comparators
Selectable propagation delay versus current consumption
Hysteresis: On or Off
Analog comparator outputs available on pins
– Asynchronous or synchronous
Flexible input selection:
– Four pins selectable for positive or negative inputs
– Ground (for zero crossing)
– INTREF reference voltage, supplied by the bandgap
– 64-level programmable VDD scaler per comparator
– DAC (if available)
Interrupt generation on:
– Rising or falling edge
– Toggle
– End of comparison
Window function interrupt generation on:
– Signal above window
– Signal inside window
– Signal below window
– Signal outside window
Event generation on:
– Comparator output
– Window function inside/outside window
Optional digital filter on comparator output
Low-power option
– Single-shot support
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 773
PIC32CM MC00 Family
Analog Comparators (AC)
38.3
Block Diagram
Figure 38-1. Analog Comparator Block Diagram (First Pair)
AIN0
+
CMP0
COMP0
AIN1
-
VDD
SCALER
HYSTERESIS
ENABLE
DAC
INTERRUPTS
INTERRUPT MODE
COMPCTRLn
WINCTRL
ENABLE
INTREF
38.4
GCLK_AC
CMP1
COMP1
AIN3
EVENTS
HYSTERESIS
+
AIN2
INTERRUPT
SENSITIVITY
CONTROL
&
WINDOW
FUNCTION
-
Signal Description
Signal
Description
Type
AIN[3..0]
Analog input
Comparator inputs
CMP[1..0]
Digital output
Comparator outputs
Refer to the Pinout for details on the pin mapping for this peripheral. One signal can be mapped on several pins.
38.5
Peripheral Dependencies
Peripheral Base Address IRQ
AC
0x42005000
23
AHB CLK
APB CLK
Generic CLK
PAC
Events
Enabled at
reset
Enabled at
reset
Index
Index
Prot at
reset
User
-
N
33
20
N
34-35:
SOC0-1
DMA
Generator
Index
Sleep
Walking
73-74:
COMP0-1
-
Y
75: WIN0
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 774
PIC32CM MC00 Family
Analog Comparators (AC)
38.6
Functional Description
38.6.1
Principle of Operation
Each comparator has one positive input and one negative input. Each positive input may be chosen from a selection
of analog input pins. Each negative input may be chosen from a selection of both analog input pins and internal
inputs, such as INTREF voltage reference.
The digital output from the comparator is '1' when the difference between the positive and the negative input voltage
is positive, and '0' otherwise.
The individual comparators can be used independently (Normal mode) or paired to form a window comparison
(Window mode).
38.6.2
Basic Operation
38.6.2.1 Initialization
Some registers are enable-protected, meaning they can only be written when the module is disabled.
The following register is enable-protected:
•
Event Control register (EVCTRL)
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
38.6.2.2 Enabling, Disabling and Resetting
The AC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The AC is disabled
writing a '0' to CTRLA.ENABLE.
The AC is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in
the AC will be reset to their initial state, and the AC will be disabled. Refer to CTRLA for details.
38.6.2.3 Comparator Configuration
Each individual comparator must be configured by its respective Comparator Control register (COMPCTRLx) before
that comparator is enabled. These settings cannot be changed while the comparator is enabled.
•
•
•
•
•
•
•
Select the desired measurement mode with COMPCTRLx.SINGLE. See Starting a Comparison for more details.
Select the desired hysteresis with COMPCTRLx.HYSTEN. See Input Hysteresis for more details.
Select the comparator speed versus power with COMPCTRLx.SPEED. See Propagation Delay vs. Power
Consumption for more details.
Select the interrupt source with COMPCTRLx.INTSEL.
Select the positive and negative input sources with the COMPCTRLx.MUXPOS and COMPCTRLx.MUXNEG
bits. See Selecting Comparator Inputs for more details.
Select the filtering option with COMPCTRLx.FLEN.
Select standby operation with Run in Standby bit (COMPCTRLx.RUNSTDBY).
The individual comparators are enabled by writing a '1' to the Enable bit in the Comparator x Control registers
(COMPCTRLx.ENABLE). The individual comparators are disabled by writing a '0' to COMPCTRLx.ENABLE. Writing
a '0' to CTRLA.ENABLE will also disable all the comparators, but will not clear their COMPCTRLx.ENABLE bits.
38.6.2.4 Starting a Comparison
Each comparator channel can be in one of two different measurement modes, determined by the
COMPCTRLx.SINGLE bit:
•
•
Continuous measurement
Single-shot
After being enabled, a start-up delay is required before the result of the comparison is ready. This start-up time is
measured automatically to account for environmental changes, such as temperature or voltage supply level, and is
specified in 43. Electrical Characteristics 85℃. During the start-up time, the COMP output is not available.
The comparator can be configured to generate interrupts when the output toggles, when the output changes from
'0' to '1' (rising edge), when the output changes from '1' to '0' (falling edge) or at the end of the comparison. An end-
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PIC32CM MC00 Family
Analog Comparators (AC)
of-comparison interrupt can be used with the single-shot mode to chain further events in the system, regardless of
the state of the comparator outputs. The interrupt mode is set by the Interrupt Selection bit group in the Comparator
Control register (COMPCTRLx.INTSEL). Events are generated using the comparator output state, regardless of
whether the interrupt is enabled or not.
38.6.2.4.1 Continuous Measurement
Continuous measurement is selected by writing COMPCTRLx.SINGLE to zero. In continuous mode, the comparator
is continuously enabled and performing comparisons. This ensures that the result of the latest comparison is always
available in the Current State bit in the Status A register (STATUSA.STATEx).
After the start-up time has passed, a comparison is done and STATUSA is updated. The Comparator x Ready bit
in the Status B register (STATUSB.READYx) is set, and the appropriate peripheral events and interrupts are also
generated. New comparisons are performed continuously until the COMPCTRLx.ENABLE bit is written to zero. The
start-up time applies only to the first comparison.
In continuous operation, edge detection of the comparator output for interrupts is done by comparing the current and
previous sample. The sampling rate is the GCLK_AC frequency. An example of continuous measurement is shown in
the Figure 38-2.
Figure 38-2. Continuous Measurement Example
GCLK_AC
Write ‘1’
2-3 cycles
COMPCTRLx.ENABLE
tSTARTUP
STATUSB.READYx
Sampled
Comparator Output
For low-power operation, comparisons can be performed during sleep modes without a clock. The comparator is
enabled continuously, and changes of the comparator state are detected asynchronously. When a toggle occurs, the
Power Manager will start GCLK_AC to register the appropriate peripheral events and interrupts. The GCLK_AC clock
is then disabled again automatically, unless configured to wake up the system from sleep.
38.6.2.4.2 Single-Shot
Single-shot operation is selected by writing COMPCTRLx.SINGLE to '1'. During single-shot operation, the
comparator is normally idle. The user starts a single comparison by writing '1' to the respective Start Comparison
bit in the write-only Control B register (CTRLB.STARTx). The comparator is enabled, and after the start-up time has
passed, a single comparison is done and STATUSA.STATEx is updated. Appropriate peripheral events and interrupts
are also generated. No new comparisons will be performed.
Writing '1' to CTRLB.STARTx also clears the Comparator x Ready bit in the Status B register (STATUSB.READYx).
STATUSB.READYx is set automatically by hardware after the single comparison has completed.
A single-shot measurement can also be triggered by the Event System. Setting the Comparator x Event Input bit in
the Event Control Register (EVCTRL.COMPEIx) enables triggering on incoming peripheral events. Each comparator
can be triggered independently by separate events. Event-triggered operation is similar to user-triggered operation;
the difference is that a peripheral event from another hardware module causes the hardware to automatically start the
comparison and clear STATUSB.READYx.
To detect an edge of the comparator output in single-shot operation for the purpose of interrupts, the result of the
current measurement is compared with the result of the previous measurement (one sampling period earlier). An
example of single-shot operation is shown in Figure 38-3.
Figure 38-3. Single-Shot Example
GCLK_AC
Write ‘1’
CTRLB.STARTx
Write ‘1’
2-3 cycles
STATUSB.READYx
2-3 cycles
tSTARTUP
tSTARTUP
Sampled
Comparator Output
For low-power operation, event-triggered measurements can be performed during sleep modes. When the event
occurs, the Power Manager will start GCLK_AC. The comparator is enabled, and after the startup time has passed,
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PIC32CM MC00 Family
Analog Comparators (AC)
a comparison is done and appropriate peripheral events and interrupts are also generated. The comparator and
GCLK_AC are then disabled again automatically, unless configured to wake up the system from sleep.
38.6.3
Selecting Comparator Inputs
Each comparator has one positive and one negative input. The positive input is one of the external input pins (AINx).
The negative input can be fed either from an external input pin (AINx) or from one of the several internal reference
voltage sources common to all comparators. The user selects the input source as follows:
•
•
The positive input is selected by the Positive Input MUX Select bit group in the Comparator Control register
(COMPCTRLx.MUXPOS)
The negative input is selected by the Negative Input MUX Select bit group in the Comparator Control register
(COMPCTRLx.MUXNEG)
In the case of using an external I/O pin, the selected pin must be configured for analog use in the PORT Controller by
disabling the digital input and output. The switching of the analog input multiplexers is controlled to minimize crosstalk
between the channels. The input selection must be changed only while the individual comparator is disabled.
Note: For internal use of the comparison results by the CCL, this bit must be 0x1 or 0x2.
38.6.4
Window Operation
Each comparator pair can be configured to work together in window mode. In this mode, a voltage range is
defined, and the comparators give information about whether an input signal is within this range or not. Window
mode is enabled by the Window Enable x bit in the Window Control register (WINCTRL.WENx). Both comparators
in a pair must have the same measurement mode setting in their respective Comparator Control Registers
(COMPCTRLx.SINGLE).
To physically configure the pair of comparators for window mode, the same I/O pin must be chosen as positive input
for each comparator, providing a shared input signal. The negative inputs define the range for the window. In Figure
38-4, COMP0 defines the upper limit and COMP1 defines the lower limit of the window, as shown but the window
will also work in the opposite configuration with COMP0 lower and COMP1 higher. The current state of the window
function is available in the Window x State bit group of the Status register (STATUSA.WSTATEx).
Window mode can be configured to generate interrupts when the input voltage reaches values below the window,
above the window, inside the window or outside of the window. The interrupt selections are set by the Window
Interrupt Selection bit field in the Window Control register (WINCTRL.WINTSEL). Events are generated using the
inside/outside state of the window, regardless of whether the interrupt is enabled or not. Note that the individual
comparator outputs, interrupts and events continue to function normally during window mode.
When the comparators are configured for window mode and single-shot mode, measurements are performed
simultaneously on both comparators. Writing '1' to either Start Comparison bit in the Control B register
(CTRLB.STARTx) will start a measurement. Likewise either peripheral event can start a measurement.
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PIC32CM MC00 Family
Analog Comparators (AC)
Figure 38-4. Comparators in Window Mode
+
STATE0
COMP0
-
UPPER LIMIT OF WINDOW
WSTATE[1:0]
INTERRUPT
SENSITIVITY
CONTROL
&
WINDOW
FUNCTION
INPUT SIGNAL
INTERRUPTS
EVENTS
+
STATE1
COMP1
-
LOWER LIMIT OF WINDOW
38.6.5
VDD Scaler
The VDD scaler generates a reference voltage that is a fraction of the device’s supply voltage, with 64 levels.
One independent voltage channel is dedicated for each comparator. The scaler of a comparator is enabled
when the Negative Input Mux bit field or the Positive Input Mux in the respective Comparator Control register
(COMPCTRLx.MUXNEG, or COMPCTRLx.MUXPOS) is set to 0x5 for Negative Input or 0x04 for Positive Input and
the comparator is enabled. The voltage of each channel is selected by the Value bit field in the SCALERx registers
(SCALERx.VALUE).
Figure 38-5. VDD Scaler
COMPCTRLx.MUXNEG == 5
OR
COMPCTRLx.MUXPOS == 4
SCALERx.
VALUE
6
to
COMPx
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PIC32CM MC00 Family
Analog Comparators (AC)
38.6.6
Input Hysteresis
Application software can selectively enable/disable hysteresis for the comparison. Applying hysteresis will help
prevent constant toggling of the output, which can be caused by noise when the input signals are close to each other.
Hysteresis is enabled for each comparator individually by the Hysteresis Enable bit in the Comparator x Control
register (COMPCTRLx.HYSTEN). Hysteresis is available only in continuous mode (COMPCTRLx.SINGLE=0).
38.6.7
Propagation Delay vs. Power Consumption
It is possible to trade off comparison speed for power efficiency to get the shortest possible propagation delay or
the lowest power consumption. The speed setting is configured for each comparator individually by the Speed bit
group in the Comparator x Control register (COMPCTRLx.SPEED). The Speed bits select the amount of bias current
provided to the comparator, and as such will also affect the start-up time.
38.6.8
Filtering
The output of the comparators can be filtered digitally to reduce noise. The filtering is determined by the Filter Length
bits in the Comparator Control x register (COMPCTRLx.FLEN), and is independent for each comparator. Filtering is
selectable from none, 3-bit majority (N=3) or 5-bit majority (N=5) functions. Any change in the comparator output is
considered valid only if N/2+1 out of the last N samples agree. The filter sampling rate is the GCLK_AC frequency.
Note that filtering creates an additional delay of N-1 sampling cycles from when a comparison is started until the
comparator output is validated. For continuous mode, the first valid output will occur when the required number of
filter samples is taken. Subsequent outputs will be generated every cycle based on the current sample plus the
previous N-1 samples, as shown in Figure 38-6. For single-shot mode, the comparison completes after the Nth filter
sample, as shown in Figure 38-7.
Figure 38-6. Continuous Mode Filtering
Sampling Clock
Sampled
Comparator Output
3-bit Majority
Filter Output
5-bit Majority
Filter Output
Figure 38-7. Single-Shot Filtering
Sampling Clock
Start
3-bit Sampled
Comparator Output
tSTARTUP
3-bit Majority
Filter Output
5-bit Sampled
Comparator Output
5-bit Majority
Filter Output
During sleep modes, filtering is supported only for single-shot measurements. Filtering must be disabled if continuous
measurements will be done during sleep modes, or the resulting interrupt/event may be generated incorrectly.
38.6.9
Comparator Output
The output of each comparator can be routed to an I/O pin by setting the Output bit group in the Comparator
Control x register (COMPCTRLx.OUT). This allows the comparator to be used by external circuitry. Either the raw,
non-synchronized output of the comparator or the CLK_AC-synchronized version, including filtering, can be used as
the I/O signal source. The output appears on the corresponding CMP[x] pin.
38.6.10 Offset Compensation
The Swap bit in the Comparator Control registers (COMPCTRLx.SWAP) controls switching of the input signals to a
comparator's positive and negative terminals. When the comparator terminals are swapped, the output signal from
the comparator is also inverted, as shown in Figure 38-8. This allows the user to measure or compensate for the
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PIC32CM MC00 Family
Analog Comparators (AC)
comparator input offset voltage. As part of the input selection, COMPCTRLx.SWAP can be changed only while the
comparator is disabled.
Figure 38-8. Input Swapping for Offset Compensation
+
MUXPOS
COMPx
-
CMPx
HYSTERESIS
ENABLE
SWAP
MUXNEG
COMPCTRLx
SWAP
38.6.11 Interrupts
The AC has the following interrupt sources:
•
•
Comparator (COMP0 and COMP1): Indicates a change in comparator status.
Window (WIN0): Indicates a change in the window status.
Comparator interrupts are generated based on the conditions selected by the Interrupt Selection bit group in the
Comparator Control registers (COMPCTRLx.INTSEL). Window interrupts are generated based on the conditions
selected by the Window Interrupt Selection bit group in the Window Control register (WINCTRL.WINTSEL[1:0]).
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and
Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by
writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a
one to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated
when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until
the interrupt flag is cleared, the interrupt is disabled, or the AC is reset. See the INTFLAG register for details on
how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate
one combined interrupt request to the NVIC. The user must read the INTFLAG register to determine which interrupt
condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated.
38.6.12 Events
The AC can generate the following output events:
•
•
Comparator (COMP0 and COMP1): Generated as a copy of the comparator status
Window (WIN0): Generated as a copy of the window inside/outside status
Writing a one to an Event Output bit in the Event Control Register (EVCTRL.xxEO) enables the corresponding output
event. Writing a zero to this bit disables the corresponding output event. Refer to the Event System chapter for details
on configuring the event system.
The AC can take the following action on an input event:
•
Start comparison (START0 and START1): Start a comparison.
Writing a one to an Event Input bit into the Event Control register (EVCTRL.COMPEIx) enables the corresponding
action on input event. Writing a zero to this bit disables the corresponding action on input event. Note that if several
events are connected to the AC, the enabled action will be taken on any of the incoming events. Refer to the Event
System chapter for details on configuring the event system.
When EVCTRL.COMPEIx is one, the event will start a comparison on COMPx after the start-up time delay. In
normal mode, each comparator responds to its corresponding input event independently. For a pair of comparators in
window mode, either comparator event will trigger a comparison on both comparators simultaneously.
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Analog Comparators (AC)
38.6.13 Sleep Mode Operation
The Run in Standby bits in the Comparator x Control registers (COMPCTRLx.RUNSTDBY) control the behavior
of the AC during standby sleep mode. Each RUNSTDBY bit controls one comparator. When the bit is zero, the
comparator is disabled during sleep, but maintains its current configuration. When the bit is one, the comparator
continues to operate during sleep. Note that when RUNSTDBY is zero, the analog blocks are powered off for the
lowest power consumption. This necessitates a start-up time delay when the system returns from sleep.
For Window Mode operation, both comparators in a pair must have the same RUNSTDBY configuration.
When RUNSTDBY is one, any enabled AC interrupt source can wake up the CPU. The AC can also be used during
sleep modes where the clock used by the AC is disabled, provided that the AC is still powered (not in shutdown). In
this case, the behavior is slightly different and depends on the measurement mode, as listed in Table 38-1.
Table 38-1. Sleep Mode Operation
COMPCTRLx.MODE RUNSTDBY=0
RUNSTDBY=1
0 (Continuous)
COMPx disabled GCLK_AC stopped, COMPx enabled
1 (Single-shot)
COMPx disabled GCLK_AC stopped, COMPx enabled only when triggered by an input
event
38.6.13.1 Continuous Measurement during Sleep
When a comparator is enabled in continuous measurement mode and GCLK_AC is disabled during sleep, the
comparator will remain continuously enabled and will function asynchronously. The current state of the comparator
is asynchronously monitored for changes. If an edge matching the interrupt condition is found, GCLK_AC is started
to register the interrupt condition and generate events. If the interrupt is enabled in the Interrupt Enable registers
(INTENCLR/SET), the AC can wake up the device; otherwise GCLK_AC is disabled until the next edge detection.
Filtering is not possible with this configuration.
Figure 38-9. Continuous Mode SleepWalking
GCLK_AC
Write ‘1’
2-3 cycles
COMPCTRLx.ENABLE
tSTARTUP
STATUSB.READYx
Sampled
Comparator Output
38.6.13.2 Single-Shot Measurement during Sleep
For low-power operation, event-triggered measurements can be performed during sleep modes. When the event
occurs, the Power Manager will start GCLK_AC. The comparator is enabled, and after the start-up time has
passed, a comparison is done, with filtering if desired, and the appropriate peripheral events and interrupts are
also generated, as shown in Figure 38-10. The comparator and GCLK_AC are then disabled again automatically,
unless configured to wake the system from sleep. Filtering is allowed with this configuration.
Figure 38-10. Single-Shot SleepWalking
GCLK_AC
tSTARTUP
tSTARTUP
Input Event
Comparator
Output or Event
38.6.14 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
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PIC32CM MC00 Family
Analog Comparators (AC)
•
•
•
Software Reset bit in control register (CTRLA.SWRST)
Enable bit in control register (CTRLA.ENABLE)
Enable bit in Comparator Control register (COMPCTRLn.ENABLE)
The following registers are synchronized when written:
•
Window Control register (WINCTRL)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
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PIC32CM MC00 Family
Analog Comparators (AC)
38.7
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
CTRLA
CTRLB
0x02
EVCTRL
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
...
0x0F
INTENCLR
INTENSET
INTFLAG
STATUSA
STATUSB
DBGCTRL
WINCTRL
Reserved
SCALER0
SCALER1
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
7:0
7:0
7:0
0x10
0x14
7
6
5
4
3
2
WINEO0
INVEI0
WIN0
WIN0
WIN0
WSTATE0[1:0]
INVEI1
1
0
ENABLE
START1
COMPEO1
COMPEI1
COMP1
COMP1
COMP1
STATE1
READY1
SWRST
START0
COMPEO0
COMPEI0
COMP0
COMP0
COMP0
STATE0
READY0
DBGRUN
WEN0
WINTSEL0[1:0]
7:0
7:0
VALUE[5:0]
VALUE[5:0]
Reserved
COMPCTRL0
COMPCTRL1
0x18
...
0x1F
Reserved
0x20
SYNCBUSY
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
RUNSTDBY
SWAP
SINGLE
HYSTEN
OUT[1:0]
RUNSTDBY
SWAP
7:0
15:8
23:16
31:24
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INTSEL[1:0]
MUXPOS[2:0]
INTSEL[1:0]
SINGLE
MUXPOS[2:0]
HYSTEN
OUT[1:0]
COMPCTRL1 COMPCTRL0
Datasheet
WINCTRL
ENABLE
MUXNEG[2:0]
SPEED[1:0]
FLEN[2:0]
ENABLE
MUXNEG[2:0]
SPEED[1:0]
FLEN[2:0]
ENABLE
SWRST
DS60001638D-page 783
PIC32CM MC00 Family
Analog Comparators (AC)
38.7.1
Control A
Name:
Offset:
Reset:
Property:
Bit
CTRLA
0x00
0x00
PAC Write-Protection, Write-Synchronized Bits
7
6
5
4
3
Access
Reset
2
1
ENABLE
R/W
0
0
SWRST
W
0
Bit 1 – ENABLE Enable
Note: This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
Value
0
1
Description
The AC is disabled.
The AC is enabled. Each comparator must also be enabled individually by the Enable bit in the
Comparator Control register (COMPCTRLn.ENABLE).
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the AC to their initial state, and the AC will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Note: This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST
synchronization is complete.
Value
0
1
Description
There is no reset operation ongoing.
The reset operation is ongoing.
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PIC32CM MC00 Family
Analog Comparators (AC)
38.7.2
Control B
Name:
Offset:
Reset:
Property:
Bit
CTRLB
0x01
0x00
-
7
6
5
4
3
Access
Reset
2
1
START1
R/W
0
0
START0
R/W
0
Bits 0, 1 – STARTx Comparator x Start Comparison
Writing a '0' to this field has no effect.
Writing a '1' to STARTx starts a single-shot comparison on COMPx if both the Single-Shot and Enable bits in the
Comparator x Control Register are '1' (COMPCTRLx.SINGLE and COMPCTRLx.ENABLE). If comparator x is not
enabled in single-shot mode, writing a '1' has no effect.
This bit always reads as zero.
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PIC32CM MC00 Family
Analog Comparators (AC)
38.7.3
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x02
0x0000
PAC Write-Protection, Enable-Protected
15
14
13
INVEI1
R/W
0
12
INVEI0
R/W
0
11
10
9
COMPEI1
R/W
0
8
COMPEI0
R/W
0
7
6
5
4
WINEO0
R/W
0
3
2
1
COMPEO1
R/W
0
0
COMPEO0
R/W
0
Access
Reset
Bit
Access
Reset
Bits 12, 13 – INVEIx Inverted Event Input Enable x
Value
Description
0
Incoming event is not inverted for comparator x.
1
Incoming event is inverted for comparator x.
Bits 8, 9 – COMPEIx Comparator x Event Input
Note that several actions can be enabled for incoming events. If several events are connected to the peripheral, the
enabled action will be taken for any of the incoming events. There is no way to tell which of the incoming events
caused the action.
These bits indicate whether a comparison will start or not on any incoming event.
Value
Description
0
Comparison will not start on any incoming event.
1
Comparison will start on any incoming event.
Bit 4 – WINEOx Window x Event Output Enable
These bits indicate whether the window x function can generate a peripheral event or not.
Value
Description
0
Window x Event is disabled.
1
Window x Event is enabled.
Bits 0, 1 – COMPEOx Comparator x Event Output Enable
These bits indicate whether the comparator x output can generate a peripheral event or not.
Value
Description
0
COMPx event generation is disabled.
1
COMPx event generation is enabled.
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PIC32CM MC00 Family
Analog Comparators (AC)
38.7.4
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x04
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
6
Access
Reset
5
4
WIN0
R/W
0
3
2
1
COMP1
R/W
0
0
COMP0
R/W
0
Bit 4 – WINx Window x Interrupt Enable
Reading this bit returns the state of the Window x interrupt enable.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit disables the Window x interrupt.
Value
Description
0
The Window x interrupt is disabled.
1
The Window x interrupt is enabled.
Bits 0, 1 – COMPx Comparator x Interrupt Enable
Reading this bit returns the state of the Comparator x interrupt enable.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit disables the Comparator x interrupt.
Value
Description
0
The Comparator x interrupt is disabled.
1
The Comparator x interrupt is enabled.
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PIC32CM MC00 Family
Analog Comparators (AC)
38.7.5
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x05
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
7
6
Access
Reset
5
4
WIN0
R/W
0
3
2
1
COMP1
R/W
0
0
COMP0
R/W
0
Bit 4 – WINx Window x Interrupt Enable
Reading this bit returns the state of the Window x interrupt enable.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit enables the Window x interrupt.
Value
Description
0
The Window x interrupt is disabled.
1
The Window x interrupt is enabled.
Bits 0, 1 – COMPx Comparator x Interrupt Enable
Reading this bit returns the state of the Comparator x interrupt enable.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Ready interrupt bit and enable the Ready interrupt.
Value
Description
0
The Comparator x interrupt is disabled.
1
The Comparator x interrupt is enabled.
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Datasheet
DS60001638D-page 788
PIC32CM MC00 Family
Analog Comparators (AC)
38.7.6
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAG
0x06
0x00
–
6
Access
Reset
5
4
WIN0
R/W
0
3
2
1
COMP1
R/W
0
0
COMP0
R/W
0
Bit 4 – WINx Window x
This flag is set according to the Window x Interrupt Selection bit group in the 37.7.11 WINCTRL register
(WINCTRL.WINTSELx) and will generate an interrupt if INTENCLR/SET.WINx is also one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Window x interrupt flag.
Bits 0, 1 – COMPx Comparator x
Reading this bit returns the status of the Comparator x interrupt flag. If comparator x is not implemented, COMPx
always reads as zero.
This flag is set according to the Interrupt Selection bit group in the Comparator x Control register
(COMPCTRLx.INTSEL) and will generate an interrupt if INTENCLR/SET.COMPx is also one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Comparator x interrupt flag.
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Datasheet
DS60001638D-page 789
PIC32CM MC00 Family
Analog Comparators (AC)
38.7.7
Status A
Name:
Offset:
Reset:
Property:
Bit
7
STATUSA
0x07
0x00
Read-Only
6
5
4
3
WSTATE0[1:0]
Access
Reset
R
0
R
0
2
1
STATE1
R
0
0
STATE0
R
0
Bits 5:4 – WSTATE0[1:0] Window 0 Current State
These bits show the current state of the signal if the window 0 mode is enabled.
Value
Name
Description
0x0
ABOVE
Signal is above window
0x1
INSIDE
Signal is inside window
0x2
BELOW
Signal is below window
0x3
Reserved
Bits 0, 1 – STATEx Comparator x Current State
This bit shows the current state of the output signal from COMPx. STATEx is valid only when STATUSB.READYx is
one.
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Datasheet
DS60001638D-page 790
PIC32CM MC00 Family
Analog Comparators (AC)
38.7.8
Status B
Name:
Offset:
Reset:
Property:
Bit
STATUSB
0x08
0x00
Read-Only
7
6
5
4
3
Access
Reset
2
1
READY1
R
0
0
READY0
R
0
Bits 0, 1 – READYx Comparator x Ready
This bit is cleared when the comparator x output is not ready.
This bit is set when the comparator x output is ready.
If comparator x is not implemented, READYx always reads as zero.
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Datasheet
DS60001638D-page 791
PIC32CM MC00 Family
Analog Comparators (AC)
38.7.9
Debug Control
Name:
Offset:
Reset:
Property:
Bit
DBGCTRL
0x09
0x00
PAC Write-Protection
7
6
5
4
3
Access
Reset
2
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Debug Run
This bit is reset by a system software reset.
This bits controls the functionality when the CPU is halted by an external debugger.
Value
Description
0
The AC is halted when the CPU is halted by an external debugger. Any on-going comparison will
complete.
1
The AC continues normal operation when the CPU is halted by an external debugger.
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Datasheet
DS60001638D-page 792
PIC32CM MC00 Family
Analog Comparators (AC)
38.7.10 Window Control
Name:
Offset:
Reset:
Property:
WINCTRL
0x0A
0x00
PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.WINCTRL must be checked to ensure the WINCTRL register
synchronization is complete.
Bit
7
6
5
4
3
Access
Reset
2
1
WINTSEL0[1:0]
R/W
R/W
0
0
0
WEN0
R/W
0
Bits 2:1 – WINTSEL0[1:0] Window 0 Interrupt Selection
These bits configure the interrupt mode for the comparator window 0 mode.
Value
Name
Description
0x0
ABOVE
Interrupt on signal above window
0x1
INSIDE
Interrupt on signal inside window
0x2
BELOW
Interrupt on signal below window
0x3
OUTSIDE
Interrupt on signal outside window
Bit 0 – WEN0 Window 0 Mode Enable
Value
Description
0
Window mode is disabled for comparators 0 and 1.
1
Window mode is enabled for comparators 0 and 1.
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Datasheet
DS60001638D-page 793
PIC32CM MC00 Family
Analog Comparators (AC)
38.7.11 Scaler n
Name:
Offset:
Reset:
Property:
Bit
7
SCALERn
0x0C + n*0x01 [n=0..1]
0x00
Write-Protected
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
VALUE[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 5:0 – VALUE[5:0] Scaler Value
These bits define the scaling factor for channel n of the VDD voltage scaler. The output voltage, VSCALE, is:
V ⋅ VALUE+1
VSCALE = DD
64
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Datasheet
DS60001638D-page 794
PIC32CM MC00 Family
Analog Comparators (AC)
38.7.12 Comparator Control n
Name:
Offset:
Reset:
Property:
Bit
COMPCTRL
0x10 + n*0x04 [n=0..1]
0x00000000
PAC Write-Protection, Write-Synchronized
31
30
29
28
27
26
R/W
0
25
FLEN[2:0]
R/W
0
R/W
0
19
HYSTEN
R/W
0
18
17
16
11
10
OUT[1:0]
Access
Reset
Bit
23
22
R/W
0
R/W
0
21
20
Access
Reset
Bit
Access
Reset
Bit
15
SWAP
R/W
0
7
Access
Reset
14
R/W
0
6
RUNSTDBY
R/W
0
12
SPEED[1:0]
R/W
0
R/W
0
8
13
MUXPOS[2:0]
R/W
0
R/W
0
R/W
0
9
MUXNEG[2:0]
R/W
0
5
4
2
SINGLE
R/W
0
1
ENABLE
R/W
0
3
INTSEL[1:0]
R/W
R/W
0
0
24
R/W
0
0
Bits 29:28 – OUT[1:0] Output
These bits configure the output selection for comparator n. COMPCTRLn.OUT can be written only while
COMPCTRLn.ENABLE is zero.
Note: For internal use of the comparison results by the CCL, this bit must be 0x1 or 0x2.
These bits are not synchronized.
Value
Name
Description
0x0
OFF
The output of COMPn is not routed to the COMPn I/O port
0x1
ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port
0x2
SYNC
The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port
0x3
N/A
Reserved
Bits 26:24 – FLEN[2:0] Filter Length
These bits configure the filtering for comparator n. COMPCTRLn.FLEN can only be written while
COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Value
Name
Description
0x0
OFF
No filtering
0x1
MAJ3
3-bit majority function (2 of 3)
0x2
MAJ5
5-bit majority function (3 of 5)
0x3-0x7 N/A
Reserved
Bit 19 – HYSTEN Hysteresis Enable
This bit indicates the hysteresis mode of comparator n. Hysteresis is available only for continuous mode
(COMPCTRLn.SINGLE=0).
This bit is not synchronized.
Value
Description
0
Hysteresis is disabled.
1
Hysteresis is enabled.
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Datasheet
DS60001638D-page 795
PIC32CM MC00 Family
Analog Comparators (AC)
Bits 17:16 – SPEED[1:0] Speed Selection
This bit indicates the speed/propagation delay mode of comparator n. COMPCTRLn.SPEED can be written only
while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Value
Name
Description
0x0
0x3
LOW
HIGH
Low speed
High speed
Bit 15 – SWAP Swap Inputs and Invert
This bit swaps the positive and negative inputs to COMPn and inverts the output. This function can be used for offset
cancellation. COMPCTRLn.SWAP can be written only while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Value
Description
0
The output of MUXPOS connects to the positive input, and the output of MUXNEG connects to the
negative input.
1
The output of MUXNEG connects to the positive input, and the output of MUXPOS connects to the
negative input.
Bits 14:12 – MUXPOS[2:0] Positive Input Mux Selection
These bits select which input will be connected to the positive input of comparator n. COMPCTRLn.MUXPOS can be
written only while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Value
Name
Description
0x0
PIN0
I/O pin 0
0x1
PIN1
I/O pin 1
0x2
PIN2
I/O pin 2
0x3
PIN3
I/O pin 3
0x4
VSCALE
VDD scaler
0x5–0x7
Reserved
Bits 10:8 – MUXNEG[2:0] Negative Input Mux Selection
These bits select which input will be connected to the negative input of comparator n. COMPCTRLn.MUXNEG can
only be written while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Value
Name
Description
0x0
PIN0
I/O pin 0
0x1
PIN1
I/O pin 1
0x2
PIN2
I/O pin 2
0x3
PIN3
I/O pin 3
0x4
GND
Ground
0x5
VSCALE VDD scaler
0x6
INTREF Internal voltage reference, supplied by the bandgap (refer to SUPC.VREF.SEL for voltage
level information)
0x7
DAC
DAC output
Bit 6 – RUNSTDBY Run in Standby
This bit controls the behavior of the comparator during standby sleep mode.
This bit is not synchronized
Value
Description
0
The comparator is disabled during sleep.
1
The comparator continues to operate during sleep.
Bits 4:3 – INTSEL[1:0] Interrupt Selection
These bits select the condition for comparator n to generate an interrupt or event. COMPCTRLn.INTSEL can be
written only while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
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PIC32CM MC00 Family
Analog Comparators (AC)
Value
0x0
0x1
0x2
0x3
Name
TOGGLE
RISING
FALLING
EOC
Description
Interrupt on comparator output toggle
Interrupt on comparator output rising
Interrupt on comparator output falling
Interrupt on end of comparison (single-shot mode only)
Bit 2 – SINGLE Single-Shot Mode
This bit determines the operation of comparator n. COMPCTRLn.SINGLE can be written only while
COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Value
Description
0
Comparator n operates in continuous measurement mode.
1
Comparator n operates in single-shot mode.
Bit 1 – ENABLE Enable
Writing a zero to this bit disables comparator n.
Writing a one to this bit enables comparator n.
Due to synchronization, there is delay from updating the register until the comparator is enabled/disabled. The value
written to COMPCTRLn.ENABLE will read back immediately after being written. SYNCBUSY.COMPCTRLn is set.
SYNCBUSY.COMPCTRLn is cleared when the peripheral is enabled/disabled.
Writing a one to COMPCTRLn.ENABLE will prevent further changes to the other bits in COMPCTRLn. These bits
remain protected until COMPCTRLn.ENABLE is written to zero and the write is synchronized.
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PIC32CM MC00 Family
Analog Comparators (AC)
38.7.13 Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x20
0x00000000
Read-Only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
COMPCTRL1
R
0
3
COMPCTRL0
R
0
2
WINCTRL
R
0
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 3, 4 – COMPCTRLx COMPCTRLx Synchronization Busy [x = 1..0]
This bit is cleared when the synchronization of the COMPCTRLx register between the clock domains is complete.
This bit is set when the synchronization of the COMPCTRLx register between clock domains is started.
Bit 2 – WINCTRL WINCTRL Synchronization Busy
This bit is cleared when the synchronization of the WINCTRL register between the clock domains is complete.
This bit is set when the synchronization of the WINCTRL register between clock domains is started.
Bit 1 – ENABLE Enable Synchronization Busy
This bit is cleared when the synchronization of the CTRLA.ENABLE bit between the clock domains is complete.
This bit is set when the synchronization of the CTRLA.ENABLE bit between clock domains is started.
Bit 0 – SWRST Software Reset Synchronization Busy
This bit is cleared when the synchronization of the CTRLA.SWRST bit between the clock domains is complete.
This bit is set when the synchronization of the CTRLA.SWRST bit between clock domains is started.
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Datasheet
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PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
39.
Digital-to-Analog Converter (DAC)
39.1
Overview
The Digital-to-Analog Converter (DAC) converts a digital value to a voltage. The DAC has one channel with 10-bit
resolution, and it is capable of converting up to 350,000 samples per second (350 ksps).
39.2
Features
•
•
•
•
•
•
•
39.3
DAC with 10-bit resolution
Up to 350 ksps conversion rate
Hardware support for 14-bit using dithering
Multiple trigger sources
High-drive capabilities
Output can be used as input to the Analog Comparator (AC), SDADC, or ADC
DMA support
Block Diagram
Figure 39-1. DAC Block Diagram
DATABUF
DATA
Internal input
Output
Buffer
DAC10
VOUT
VREFA
VDDANA
DAC Controller
INTREF
39.4
Signal Description
Signal Name
Type
Description
VOUT
Analog output
DAC output
VREFA
Analog input
External reference
For further information, refer to the 4. Pinout and Packaging.
39.5
Peripheral Dependencies
Peripheral Base Address IRQ
DAC
0x42005400
24
AHB CLK
APB CLK
Generic CLK
Enabled at
reset
Enabled at
reset
Index
Index
Prot at
reset
-
N
31
21
N
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PAC
Datasheet
Events
DMA
Sleep Walking
User
Generator
Index
36: START 76: EMPTY 39: EMPTY
Y
DS60001638D-page 799
PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
39.6
Functional Description
39.6.1
Principle of Operation
The DAC converts the digital value located in the Data register (DATA) into an analog voltage on the DAC output
(VOUT).
A conversion is started when new data is written to the Data register. The resulting voltage is available on the DAC
output after the conversion time. A conversion can also be started by input events from the Event System.
39.6.2
Basic Operation
39.6.2.1 Initialization
The following registers are enable-protected, meaning they can only be written when the DAC is disabled
(CTRLA.ENABLE is zero):
•
•
Control B register (CTRLB)
Event Control register (EVCTRL)
Enable-protection is denoted by the Enable-Protected property in the register description.
Before enabling the DAC, it must be configured by selecting the voltage reference using the Reference Selection bits
in the Control B register (CTRLB.REFSEL).
39.6.2.2 Enabling, Disabling and Resetting
The DAC Controller is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The DAC
Controller is disabled by writing a '0' to CTRLA.ENABLE.
The DAC Controller is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All
registers in the DAC will be reset to their initial state, and the DAC Controller will be disabled. Refer to the CTRLA
register for details.
39.6.2.3 Enabling the Output Buffer
To enable the DAC output on the VOUT pin, the output driver must be enabled by writing a one to the External Output
Enable bit in the Control B register (CTRLB.EOEN).
The DAC output buffer provides a high-drive-strength output, and is capable of driving both resistive and capacitive
loads. To minimize power consumption, the output buffer should be enabled only when external output is needed.
39.6.2.4 Digital-to-Analog Conversion (DAC)
The DAC converts a digital value (stored in the DATA register) into an analog voltage. The conversion range is
between GND and the selected DAC voltage reference. The default voltage reference is the internal reference
voltage. Other voltage reference options are the analog supply voltage (VDDANA) and the external voltage reference
(VREFA). The voltage reference is selected by writing to the Reference Selection bits in the Control B register
(CTRLB.REFSEL).
The output voltage from the DAC can be calculated using the following formula:
VOUT = DATA ⋅ VREF
0x3FF
A new conversion starts as soon as a new value is loaded into DATA. DATA can either be loaded via the APB bus
during a CPU write operation, using DMA, or from the DATABUF register when a START event occurs. Refer to
39.6.5 Events for details. As there is no automatic indication that a conversion is done, the sampling period must be
greater than or equal to the specified conversion time.
For further information, refer to the Supply Controller - SUPC.
39.6.3
DMA Operation
The DAC generates the following DMA request:
•
Data Buffer Empty (EMPTY): The request is set when data is transferred from DATABUF to the internal data
buffer of DAC. The request is cleared when DATABUF register is written, or by writing a one to the EMPTY bit in
the Interrupt Flag register (INTFLAG.EMPTY).
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PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
For each Start Conversion event, DATABUF is transferred into DATA and the conversion starts. When DATABUF
is empty, the DAC generates the DMA request for new data. As DATABUF is initially empty, a DMA request is
generated whenever the DAC is enabled.
If the CPU accesses the registers that are the source of a DMA request set/clear condition, the DMA request can be
lost or the DMA transfer can be corrupted, if enabled.
39.6.4
Interrupts
The DAC Controller has the following interrupt sources:
•
•
Data Buffer Empty (EMPTY): Indicates that the internal data buffer of the DAC is empty.
Underrun (UNDERRUN): Indicates that the internal data buffer of the DAC is empty and a DAC start of
conversion event occurred. Refer to 39.6.5 Events for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing
a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to
the corresponding bit in the Interrupt Enable Clear register (INTENCLR). As both INTENSET and INTENCLR always
reflect the same value, the status of interrupt enablement can be read from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the DAC is reset. See
INTFLAG register for details on how to clear interrupt flags.
All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt
request to the 9.2 Nested Vector Interrupt Controller. The user must read the INTFLAG register to determine which
interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated.
39.6.5
Events
The DAC Controller can generate the following output events:
•
Data Buffer Empty (EMPTY): Generated when the internal data buffer of the DAC is empty. Refer to
39.6.3 DMA Operation for details.
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.EMPTYEO) enables the corresponding
output event. Writing a '0' to this bit disables the corresponding output event.
The DAC can take the following action on an input event:
•
Start Conversion (START): DATABUF value is transferred into DATA as soon as the DAC is ready for the next
conversion, and then conversion is started. START is considered as asynchronous to GCLK_DAC thus it is
resynchronized in DAC Controller. Refer to 39.6.2.4 Digital-to-Analog Conversion (DAC) for details.
Writing a '1' to an Event Input bit in the Event Control register (EVCTRL.STARTEI) enables the corresponding action
on an input event. Writing a '0' to this bit disables the corresponding action on input event.
Note: When several events are connected to the DAC Controller, the enabled action will be taken on any of the
incoming events.
By default, DAC Controller detects rising edge events. Falling edge detection can be enabled by writing a '1' to
EVCTRL.INVEIx.
For further information, refer to the 28. Event System (EVSYS).
39.6.6
Sleep Mode Operation
The generic clock for the DAC is running in idle sleep mode. If the Run In Standby bit in the Control A register
(CTRLA.RUNSTDBY) is one, the DAC output buffer will keep its value in standby sleep mode. If CTRLA.RUNSTDBY
is zero, the DAC output buffer will be disabled in standby sleep mode. Additionally, when the CTRLA.RUNTDBY is '0',
upon exiting from STANDBY, the empty interrupt flag (INTFLAG.EMPTY) will be set if a conversion was ongoing at
STANDBY entry. This can be ignored and cleared when necessary.
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PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
39.6.7
Synchronization
Due to the asynchronicity between main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read. A register can require:
•
•
•
•
Synchronization when written
Synchronization when read
Synchronization when written and read
No synchronization
When executing an operation that requires synchronization, the corresponding status bit in the Synchronization Busy
register (SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while its busy bit is one, the operation is discarded and an
error is generated.
The following bits need synchronization when written:
•
•
•
•
Software Reset bit in the Control A register (CTRLA.SWRST)
Enable bit in the Control A register (CTRLA.ENABLE)
All bits in the Data register (DATA)
All bits in the Data Buffer register (DATABUF)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
No bits need synchronization when read.
39.6.8
Additional Features
39.6.8.1 DAC as an Internal Reference
The DAC output can be internally enabled as input to the analog comparator. This is enabled by writing a one to the
Internal Output Enable bit in the Control B register (CTRLB.IOEN). It is possible to have the internal and external
output enabled simultaneously.
The DAC output can also be enabled as input to the Analog-to-Digital Converter. In this case, the output buffer must
be enabled.
39.6.8.2 Data Buffer
The Data Buffer register (DATABUF) and the Data register (DATA) are linked together to form a two-stage FIFO.
The DAC uses the Start Conversion event to load data from DATABUF into DATA and start a new conversion.
The Start Conversion event is enabled by writing a one to the Start Event Input bit in the Event Control register
(EVCTRL.STARTEI). If a Start Conversion event occurs when DATABUF is empty, an Underrun interrupt request is
generated if the Underrun interrupt is enabled.
The DAC can generate a Data Buffer Empty event when DATABUF becomes empty and new data can be loaded
to the buffer. The Data Buffer Empty event is enabled by writing a one to the Empty Event Output bit in the Event
Control register (EVCTRL.EMPTYEO). A Data Buffer Empty interrupt request is generated if the Data Buffer Empty
interrupt is enabled.
39.6.8.3 Voltage Pump
When the DAC is used at operating voltages lower than 2.5V, the voltage pump must be enabled. This enabling is
done automatically, depending on operating voltage.
The voltage pump can be disabled by writing a one to the Voltage Pump Disable bit in the Control B register
(CTRLB.VPD). This can be used to reduce power consumption when the operating voltage is above 2.5V.
The voltage pump uses the asynchronous GCLK_DAC clock, and requires that the clock frequency be at least four
times higher than the sampling period.
39.6.8.4 Dithering mode
Dithering is enabled by setting CTRLB.DITHER to 1. In dithering mode, DATA is a 14-bit unsigned value where
DATA[13:4] is the 10-bit data converted by DAC and DATA[3:0] represents the dither bits, used for minimizing
the quantization error. The principle is to make 16 sub-conversions of the DATA[13:4] value or the (DATA[13:4] +
1) value, so that by averaging those values, the conversion result of the 14-bit value (DATA[13:0]) has improved
accuracy due to minimized quantization error.
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PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
To use the dithering feature, EVSYS is used for generating a periodic STARTEI. And the STARTEI event must be
configured (EVCTRL.STARTEI = 1) to generate 16 events for each DATA[13:0] conversion, and DATABUFx must be
loaded every 16 DAC conversions. EMPTYx event and DMA request are therefore generated every 16 DATABUF
to DATA transfers. Using the DMA with dithering is optional. If the DMA is not used, it is required to poll the
INTFLAG.EMTPY flag, or use an interrupt on EMPTY to add a new value in DATABUF.
Note that the input value for DAC is positioned in the DATA register based on CTRLB.LEFTADJ as shown in
the following figure. Refer to 41.8.8 DATA register description for further details. If LEFTADJ = 0: the user writes
DATA[13:4], and the dithering function will take care of bit DATA[3:0] during the 16 sub-conversions.
If LEFTADJ = 1: the user writes DATA[15:6], and the dithering function will take care of bit DATA[5:2] during the 16
sub-conversions.
Following timing diagram shows examples with DATA[15:0] = 0x1210 then DATA[15:0] = 0x12E0 and
CTRLB.LEFTADJ=1.
Figure 39-2. DAC Conversions in Dithering Mode (CTRLB.LEFTADJ=1)
DATA [15:0]
0x1300
0x12E0
0x12C0
VOUT0
0x1240
0x1210
0x1200
sub-conversion
1
2
© 2021 Microchip Technology Inc.
and its subsidiaries
3
4
5
6
7
8
9 10 11 12 13 14 15 16 1
2
Datasheet
3
4
5
6
7
8
9 10 11 12 13 14 15 16
DS60001638D-page 803
PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
39.7
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
CTRLA
CTRLB
EVCTRL
Reserved
INTENCLR
INTENSET
INTFLAG
STATUS
7:0
7:0
7:0
0x08
DATA
0x0A
...
0x0B
Reserved
0x0C
DATABUF
0x0E
...
0x0F
Reserved
0x10
SYNCBUSY
0x14
DBGCTRL
7
RUNSTDBY
REFSEL[1:0]
5
4
DITHER
3
2
1
0
VPD
LEFTADJ
INVEI
ENABLE
IOEN
EMPTYEO
SWRST
EOEN
STARTEI
EMPTY
EMPTY
EMPTY
UNDERRUN
UNDERRUN
UNDERRUN
READY
ENABLE
SWRST
7:0
7:0
7:0
7:0
7:0
15:8
DATA[7:0]
DATA[15:8]
7:0
15:8
DATABUF[7:0]
DATABUF[15:8]
7:0
15:8
23:16
31:24
7:0
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and its subsidiaries
6
DATABUF
DATA
DBGRUN
Datasheet
DS60001638D-page 804
PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
39.7.1
Control A
Name:
Offset:
Reset:
Property:
Bit
CTRLA
0x00
0x00
PAC Write-Protection, Write-Synchronized Bits
7
6
RUNSTDBY
R/W
0
Access
Reset
5
4
3
2
1
ENABLE
R/W
0
0
SWRST
R/W
0
Bit 6 – RUNSTDBY Run in Standby
Note: This bit is not synchronized
Value
0
1
Description
The DAC output buffer is disabled in standby sleep mode.
The DAC output buffer can be enabled in standby sleep mode.
Bit 1 – ENABLE Enable DAC Controller
Note: This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
Value
0
1
Description
The peripheral is disabled or being disabled.
The peripheral is enabled or being enabled.
Bit 0 – SWRST Software Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the DAC to their initial state, and the DAC will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Note: This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST
synchronization is complete.
Value
0
1
Description
There is no reset operation ongoing.
The reset operation is ongoing.
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Datasheet
DS60001638D-page 805
PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
39.7.2
Control B
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
CTRLB
0x01
0x00
PAC Write-Protection, Enable-Protected
7
6
REFSEL[1:0]
R/W
R/W
0
0
5
DITHER
R/W
0
4
3
VPD
R/W
0
2
LEFTADJ
R/W
0
1
IOEN
R/W
0
0
EOEN
R/W
0
Bits 7:6 – REFSEL[1:0] Reference Selection
This bit field selects the Reference Voltage for the DAC.
Value
Name
Description
0x0
INTREF Internal voltage reference, supplied by the bandgap (refer to SUPC.VREF.SEL for voltage
level information)
0x1
VDDANA Analog voltage supply
0x2
VREFA
External Voltage Reference
0x3
Reserved
Bit 5 – DITHER Dithering Mode
This bit controls dithering operation according to 39.6.8.4 Dithering mode.
Value
Description
0
Dithering mode is disabled.
1
Dithering mode is enabled.
Bit 3 – VPD Voltage Pump Disabled
This bit controls the behavior of the voltage pump.
Value
Description
0
Voltage pump is turned on/off automatically
1
Voltage pump is disabled.
Bit 2 – LEFTADJ Left-Adjusted Data
This bit controls how the 10-bit conversion data is adjusted in the Data and Data Buffer registers.
Value
Description
0
DATA and DATABUF registers are right-adjusted.
1
DATA and DATABUF registers are left-adjusted.
Bit 1 – IOEN Internal Output Enable
Value
Description
0
Internal DAC output not enabled.
1
Internal DAC output enabled to be used by the AC or ADC.
Bit 0 – EOEN External Output Enable
Value
Description
0
The DAC output is turned off.
1
The high-drive output buffer drives the DAC output to the VOUT pin.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 806
PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
39.7.3
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x02
0x00
PAC Write-Protection
7
6
5
4
3
Access
Reset
2
INVEI
R/W
0
1
EMPTYEO
R/W
0
0
STARTEI
R/W
0
Bit 2 – INVEI Enable Inversion of Start Event Input
This bit defines the edge detection of the input event for STARTEI.
Value
Description
0
Rising edge.
1
Falling edge.
Bit 1 – EMPTYEO Data Buffer Empty Event Output
This bit indicates whether or not the Data Buffer Empty event is enabled and will be generated when the Data Buffer
register is empty.
Value
Description
0
Data Buffer Empty event is disabled and will not be generated.
1
Data Buffer Empty event is enabled and will be generated.
Bit 0 – STARTEI Start Conversion Event Input
This bit indicates whether or not the Start Conversion event is enabled and data are loaded from the Data Buffer
register to the Data register upon event reception.
Value
Description
0
A new conversion will not be triggered on any incoming event.
1
A new conversion will be triggered on any incoming event.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 807
PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
39.7.4
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x04
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
6
5
4
3
Access
Reset
2
1
EMPTY
R/W
0
0
UNDERRUN
R/W
0
Bit 1 – EMPTY Data Buffer Empty Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Data Buffer Empty Interrupt Enable bit, which disables the Data Buffer Empty
interrupt.
Value
Description
0
The Data Buffer Empty interrupt is disabled.
1
The Data Buffer Empty interrupt is enabled.
Bit 0 – UNDERRUN Underrun Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Data Buffer Underrun Interrupt Enable bit, which disables the Data Buffer
Underrun interrupt.
Value
Description
0
The Data Buffer Underrun interrupt is disabled.
1
The Data Buffer Underrun interrupt is enabled.
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Datasheet
DS60001638D-page 808
PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
39.7.5
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x05
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
7
6
5
4
3
Access
Reset
2
1
EMPTY
R/W
0
0
UNDERRUN
R/W
0
Bit 1 – EMPTY Data Buffer Empty Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Data Buffer Empty Interrupt Enable bit, which enables the Data Buffer Empty
interrupt.
Value
Description
0
The Data Buffer Empty interrupt is disabled.
1
The Data Buffer Empty interrupt is enabled.
Bit 0 – UNDERRUN Underrun Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Data Buffer Underrun Interrupt Enable bit, which enables the Data Buffer Underrun
interrupt.
Value
Description
0
The Data Buffer Underrun interrupt is disabled.
1
The Data Buffer Underrun interrupt is enabled.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 809
PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
39.7.6
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAG
0x06
0x00
-
6
5
4
3
Access
Reset
2
1
EMPTY
R/W
0
0
UNDERRUN
R/W
0
Bit 1 – EMPTY Data Buffer Empty
This flag is cleared by writing a '1' to it or by writing new data to DATABUF.
This flag is set when data is transferred from DATABUF to DATA, and the DAC is ready to receive new data in
DATABUF, and will generate an interrupt request if INTENCLR/SET.EMPTY is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Data Buffer Empty interrupt flag.
If the DAC is not set to run in standby sleep mode (CTRLA.RUNSTDBY=0) then the Data Buffer Empty
(INTFLAG.EMPTY) bit will be set when exiting standby sleep mode. This flag can be ignored and cleared when
necessary.
Bit 0 – UNDERRUN Underrun
This flag is cleared by writing a '1' to it.
This flag is set when a start conversion event occurs when DATABUF is empty, and will generate an interrupt request
if INTENCLR/SET.UNDERRUN is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Underrun interrupt flag.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 810
PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
39.7.7
Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x07
0x00
-
7
6
5
4
3
Access
Reset
2
1
0
READY
R
0
Bit 0 – READY DAC Ready
Value
Description
0
DAC is not ready for conversion.
1
Startup time has elapsed, DAC is ready for conversion.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 811
PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
39.7.8
Data DAC
Name:
Offset:
Reset:
Property:
DATA
0x08
0x0000
PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.DATA must be checked to ensure the DATA register
synchronization is complete.
Bit
15
14
13
12
11
10
9
8
W
0
W
0
W
0
W
0
3
2
1
0
W
0
W
0
W
0
W
0
DATA[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
7
6
5
4
DATA[7:0]
Access
Reset
W
0
W
0
W
0
W
0
Bits 15:0 – DATA[15:0] Data value to be converted
DATA register contains the 10-bit value that is converted to a voltage by the DAC. The adjustment of these 10 bits
within the 16-bit register is controlled by CTRLB.LEFTADJ.
Four additional bits are also used for the dithering feature according to 39.6.8.4 Dithering mode.
Table 39-1. Valid Data Bits
CTRLB.DITHER
CTRLB.LEFTADJ
0
0
1
1
0
1
0
1
© 2021 Microchip Technology Inc.
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DATA
Description
DATA[9:0]
DATA[15:6]
DATA[13:4], DATA[3:0]
DATA[15:6], DATA[5:2]
Right adjusted, 10-bits
Left adjusted, 10-bits
Right adjusted, 14-bits
Left adjusted, 14-bits
Datasheet
DS60001638D-page 812
PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
39.7.9
Data Buffer
Name:
Offset:
Reset:
Property:
DATABUF
0x0C
0x0000
Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.DATABUF must be checked to ensure the DATABUF register
synchronization is complete.
Bit
15
14
13
10
9
8
W
0
12
11
DATABUF[15:8]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
2
1
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
3
DATABUF[7:0]
W
W
0
0
Bits 15:0 – DATABUF[15:0] Data Buffer
DATABUF contains the value to be transferred into DATA register.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 813
PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
39.7.10 Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x10
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
DATABUF
R
0
2
DATA
R
0
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 3 – DATABUF Data Buffer DAC0
This bit is set when DATABUF register is written.
This bit is cleared when DATABUF synchronization is completed.
Value
Description
0
No ongoing synchronized access.
1
Synchronized access is ongoing.
Bit 2 – DATA Data
This bit is set when DATA register is written.
This bit is cleared when DATA synchronization is completed.
Value
Description
0
No ongoing synchronized access.
1
Synchronized access is ongoing.
Bit 1 – ENABLE DAC Enable Status
This bit is set when CTRLA.ENABLE bit is written.
This bit is cleared when CTRLA.ENABLE synchronization is completed.
Value
Description
0
No ongoing synchronization.
1
Synchronization is ongoing.
Bit 0 – SWRST Software Reset
This bit is set when CTRLA.SWRST bit is written.
This bit is cleared when CTRLA.SWRST synchronization is completed.
Value
Description
0
No ongoing synchronization.
1
Synchronization is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 814
PIC32CM MC00 Family
Digital-to-Analog Converter (DAC)
39.7.11 Debug Control
Name:
Offset:
Reset:
Property:
Bit
DBGCTRL
0x14
0x00
PAC Write-Protection
7
6
5
4
3
Access
Reset
2
1
0
DBGRUN
0
Bit 0 – DBGRUN Debug Run
This bit is reset by a system software reset.
This bits controls the functionality when the CPU is halted by an external debugger.
Value
Description
0
The DAC is halted when the CPU is halted by an external debugger. Any ongoing conversion will
complete.
1
The DAC continues normal operation when the CPU is halted by an external debugger.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 815
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.
Temperature Sensor (TSENS)
40.1
Overview
The TSENS can be used to measure the operating temperature of the device.
40.2
Features
•
•
40.3
Measures temperature
A selectable reference clock source
Block Diagram
Figure 40-1. Temperature Sensor Block Diagram.
GAIN
GCLK_TSENS
TIME AMPLIFIER
EN
ENABLE
FCAL
TOSC
RESRDY
COUNTER
EN
OFFSET
START
INTFLAG
VALUE
40.4
Peripheral Dependencies
Peripheral
TSENS
Base Address
AHB CLK
APB CLK
Generic CLK
PAC
Events
DMA
Enabled at reset
Enabled at reset
Index
Index
Prot at reset
User
Generator
Index
-
N
5
12
N
-
-
-
IRQ
0x40003000
5
Sleep Walking
© 2021 Microchip Technology Inc.
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Datasheet
-
DS60001638D-page 816
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.5
Functional Description
40.5.1
Principle of Operation
The TSENS measures the operating temperature of the device by comparing the difference in two temperature
dependent frequencies to a known frequency. The frequency of the temperature dependent oscillator (TOSC) is
measured twice: first with the min configuration and next with the max configuration. The number of periods of
GCLK_TSENS used for the measurement is defined by the GAIN register. The width of the resulting pulse is
measured using a counter clocked by GCLK_TSENS in the up direction for the 1st phase and in the down 2nd phase.
The resulting signed value is proportional to the temperature and is corrected for offset by the contents of the
OFFSET register.
VALUE = OFFSET+GAIN ×
fTOSCMIN
f
+ − TOSCMAX
fGCLK
fGCLK
Notes:
• The values of GAIN and OFFSET are factory programmed to give a specific temperature slope when using the
undivided internal 48 MHz oscillator (OSC48M) as the GCLK_TSENS source. Other frequencies/sources may
be used, but the GAIN setting and/or expected slope will need to be scaled accordingly.
• The calibration value should be copied and written into the GAIN and OFFSET registers to get the specified
accuracy.
40.5.2
Basic Operation
40.5.2.1 Initialization
The generic clocks (GCLK_TSENS) should be configured and enabled. Refer to the Generic Clock Controller chapter
for details.
The following bits are enable-protected, meaning that they can only be written when the TSENS is disabled
(40.6.1 CTRLA.ENABLE is zero):
•
Run in Standby bit in Control A register (40.6.1 CTRLA.RUNSTDBY)
The following registers are enable-protected:
•
•
•
•
•
•
•
Control C (40.6.3 CTRLC)
Event Control (40.6.4 EVCTRL)
Window Monitor Lower Threhold (40.6.11 WINLT)
Window Monitor Upper Threshold (40.6.12 WINUT)
Gain Correction (40.6.13 GAIN)
Offset Correction (40.6.14 OFFSET)
Calibration (40.6.15 CAL)
Enable-protection is denoted by the Enable-Protected property in the register description.
40.5.2.2 Enabling, Disabling and Resetting
The TSENS is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The TSENS is
disabled by writing a zero to CTRLA.ENABLE.
The TSENS is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All
registers in the TSENS will be reset to their initial state, and the TSENS will be disabled. Refer to 40.6.1 CTRLA for
details.
40.5.2.3 Measurement
After the TSENS is enabled, a measurement can be started either manually, by writing a one to the START bit in
Control B register (CTRLB.START), or automatically by configuring an event input. A free-running mode can be used
to continuously measure the temperature. When the Free running bit in the Control C register (CTRLC.FREERUN) is
written to one, there is no need for a trigger to start the measurement. It will start automatically at the end of previous
measurement.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 817
PIC32CM MC00 Family
Temperature Sensor (TSENS)
The result of the measurement is stored in the Value register (VALUE), overwriting the result from the previous
measurement and setting the Result Ready flag in the Interrupt Flag Status and Clear register (INTFLAG.RESRDY).
To avoid data loss, the conversion result must be read as soon as it is available. Failing to do so will result
in an overrun error condition, indicated by the OVERRUN bit in the Interrupt Flag Status and Clear register
(INTFLAG.OVERRUN).
To use an interrupt handler, the corresponding bit in the Interrupt Enable Set register (INTENSET) must be written to
one.
To prevent any discrepancies in the temperature measurement, an average on 10 measurements is recommended.
40.5.2.4 Window Monitor
The window monitor feature allows the measurement result in the VALUE register to be compared to predefined
threshold values. The window mode is selected by writing the Window Monitor Mode bits in the Control C register
(CTRLC.WINMODE). Threshold values must be written in the Window Monitor Lower Threshold register (WINLT) and
Window Monitor Upper Threshold register (WINUT).
40.5.3
DMA Operation
The TSENS generates the following DMA request:
•
40.5.4
Result Ready (RESRDY): the request is set when a measurement result is available, and cleared when the
VALUE register is read. The request is generated independent of any Window Monitor condition.
Interrupts
The TSENS has the following interrupt sources:
•
•
•
•
Result Ready (RESRDY): Indicates when a measurement result is available.
Window Monitor (WINMON): Generated when the measurement result matches the window monitor condition.
Refer to 40.6.3 CTRLC for details.
Overrun (OVERRUN): Indicates that a new result is ready before the previous result has been read.
Overflow (OVF): Indicates that the result is invalid because the result required more than 16 bits and overflowed
the VALUE register.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and
Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by
writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a
one to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated
when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until
the interrupt flag is cleared, the interrupt is disabled, or the TSENS is reset. See 40.6.7 INTFLAG for details on
how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate
one combined interrupt request to the NVIC. The user must read the INTFLAG register to determine which interrupt
condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated.
40.5.5
Events
The TSENS can generate the following output event:
•
Window Monitor (WINMON): Generated when the measurement results matches the window monitor condition.
Refer to 40.6.3 CTRLC for details.
Writing a one to an Event Output bit in the Event Control Register (EVCTRL.WINEO) enables the corresponding
output event. Writing a zero to this bit disables the corresponding output event. Refer to the Event System chapter for
details on configuring the event system.
The TSENS can take the following action on an input event:
•
Start measurement (START): Start a measurement. Refer to 40.6.2 CTRLB for details.
Writing a one to an Event Input bit into the Event Control register (EVCTRL.STARTEI) enables the corresponding
action on input event. Writing a zero to this bit disables the corresponding action on input event. Refer to the Event
System chapter for details. By default, the TSENS will detect a rising edge on the incoming event. If the TSENS
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 818
PIC32CM MC00 Family
Temperature Sensor (TSENS)
action must be performed on the falling edge of the incoming event, the event line must be inverted first, by writing to
one the corresponding Event Invert Enable bit in Event Control register (EVCTRL.STARTINV).
40.5.6
Sleep Mode Operation
The Run in Standby bit in the Control A register (40.6.1 CTRLA.RUNSTDBY) controls the behavior of the TSENS
during standby sleep mode, in cases where the TSENS is enabled (CTRLA.ENABLE = 1).
Table 40-1. TSENS Sleep Behavior
CTRLA.RUNSTDBY CTRLC.FREERUN CTRLA.ENABLE Description
40.5.7
x
x
0
Disabled
0
0
1
Run in all sleep modes on request, except Standby
mode.
0
1
1
Run in all sleep modes, except Standby mode.
1
0
1
Run in all sleep modes on request.
1
1
1
Run in all sleep modes.
Synchronization
Due to the asynchronicity between the main clock domain (CLK_TSENS_APB) and the peripheral clock domain
(GCLK_TSENS) some registers are synchronized when written. When a write-synchronized register is written,
the corresponding bit in the Synchronization Busy register (SYNCBUSY) is set immediately. When the writesynchronization is complete, this bit is cleared. Reading a write-synchronized register while the synchronization
is ongoing will return the value written, and not the current value in the peripheral clock domain. To read the current
value in the peripheral clock domain after writing a register, the user must wait for the corresponding SYNCBUSY bit
to be cleared before reading the value.
If an operation that require synchronization is executed while its busy bit is on, the operation is discarded and a bus
error is generated.
The following bits need synchronization when written:
•
•
Software Reset bit in Control A register (40.6.1 CTRLA.SWRST)
Enable bit in Control A register (40.6.1 CTRLA.ENABLE)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 819
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
CTRLA
CTRLB
CTRLC
EVCTRL
INTENCLR
INTENSET
INTFLAG
STATUS
0x08
SYNCBUSY
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
0x0C
VALUE
0x10
WINLT
0x14
WINUT
0x18
GAIN
0x1C
OFFSET
0x20
CAL
0x24
DBGCTRL
7
© 2021 Microchip Technology Inc.
and its subsidiaries
6
5
4
3
2
RUNSTDBY
FREERUN
OVF
OVF
OVF
WINEO
WINMON
WINMON
WINMON
1
0
ENABLE
SWRST
START
WINMODE[2:0]
STARTINV
OVERRUN
OVERRUN
OVERRUN
ENABLE
STARTEI
RESRDY
RESRDY
RESRDY
OVF
SWRST
VALUE[7:0]
VALUE[15:8]
VALUE[23:16]
WINLT[7:0]
WINLT[15:8]
WINLT[23:16]
WINUT[7:0]
WINUT[15:8]
WINUT[23:16]
GAIN[7:0]
GAIN[15:8]
GAIN[23:16]
OFFSETC[7:0]
OFFSETC[15:8]
OFFSETC[23:16]
FCAL[5:0]
TCAL[5:0]
DBGRUN
Datasheet
DS60001638D-page 820
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6.1
Control A
Name:
Offset:
Reset:
Property:
Bit
CTRLA
0x00
0x00
PAC Write-Protection, Write-Synchronized (ENABLE, SWRST)
7
Access
Reset
6
RUNSTDBY
R/W
0
5
4
3
2
1
ENABLE
R/W
0
0
SWRST
R/W
0
Bit 6 – RUNSTDBY Run in Standby
This bit controls how the TSENS behaves during Standby Sleep mode:
This bit is not synchronized.
Value
Description
0
The TSENS is halted during Standby Sleep mode.
1
The TSENS is not stopped in Standby Sleep mode. If CTRLC.FREERUN is zero, the TSENS will be
running when a peripheral is requesting it. If CTRLC.FREERUN is one, the TSENS will always be
running in Standby Sleep mode.
Bit 1 – ENABLE Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value
written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the Synchronization Busy register
(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
This bit is not enable-protected.
Value
Description
0
The peripheral is disabled.
1
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the TSENS, except GAIN, OFFSET, CAL and DBGCTRL, to their initial
state, and the TSENS will be disabled.
Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same writeoperation will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 821
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6.2
Control B
Name:
Offset:
Reset:
Property:
CTRLB
0x01
0x00
PAC Write-Protection
Note: PAC write protection will prevent the CTRLB register from write access, but will not trigger a PAC interrupt.
Bit
7
6
5
4
3
Access
Reset
2
1
0
START
W
0
Bit 0 – START Start Measurement
Value
Description
0
Writing a zero to this bit has no effect.
1
Writing a one to this bit starts a measurement
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 822
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6.3
Control C
Name:
Offset:
Reset:
Property:
Bit
CTRLC
0x02
0x00
PAC Write-Protection, Enable-protected
7
6
Access
Reset
5
4
FREERUN
R/W
0
3
2
R/W
0
1
WINMODE[2:0]
R/W
0
0
R/W
0
Bit 4 – FREERUN Free Running Measurement
Value
Description
0
TSENS operates in single measurement mode.
1
TSENS is in free running mode and a new measurement will be initiated when the previous
measurement completes.
Bits 2:0 – WINMODE[2:0] Window Monitor Mode
These bits enable and define the window monitor mode.
Value
Name
Description
0x0
DISABLE
No window mode (default)
0x1
ABOVE
VALUE > WINLT
0x2
BELOW
VALUE < WINUT
0x3
INSIDE
WINLT < VALUE < WINUT
0x4
OUTSIDE
WINUT < VALUE < WINLT
0x5
HYST_ABOVE
VALUE > WINUT with hysteresis to WINLT
0x6
HYST_BELOW
VALUE < WINLT with hysteresis to WINUT
0x07
Reserved
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 823
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6.4
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x03
0x00
PAC Write-Protection, Enable-protected
7
6
5
4
3
Access
Reset
2
WINEO
R/W
0
1
STARTINV
R/W
0
0
STARTEI
R/W
0
Bit 2 – WINEO Window Monitor Event Out
This bit indicates whether the Window Monitor event output is enabled or not and an output event will be generated
when the window monitor detects something.
Value
Description
0
Window Monitor event output is disabled and an event will not be generated.
1
Window Monitor event output is enabled and an event will be generated.
Bit 1 – STARTINV Start Conversion Event Invert Enable
Value
Description
0
start event input source is not inverted.
1
start event input source is inverted.
Bit 0 – STARTEI Start Conversion Event Input Enable
Value
Description
0
A new conversion will not be triggered on any incoming event.
1
A new conversion will be triggered on any incoming event.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 824
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6.5
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x04
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
7
6
Access
Reset
5
4
3
OVF
R/W
0
2
WINMON
R/W
0
1
OVERRUN
R/W
0
0
RESRDY
R/W
0
Bit 3 – OVF Overflow Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Enable bit, which disables the corresponding interrupt
request.
Value
Description
0
The overflow interrupt is disabled.
1
The overflow interrupt is enabled, and an interrupt request will be generated when the Overflow
interrupt flag is set.
Bit 2 – WINMON Window Monitor Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Window Monitor Interrupt Enable bit, which disables the corresponding interrupt
request.
Value
Description
0
The window monitor interrupt is disabled.
1
The window monitor interrupt is enabled, and an interrupt request will be generated when the Window
Monitor interrupt flag is set.
Bit 1 – OVERRUN Overrun Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Interrupt Enable bit, which disables the corresponding interrupt request.
Value
Description
0
The Overrun interrupt is disabled.
1
The Overrun interrupt is enabled, and an interrupt request will be generated when the Overrun interrupt
flag is set.
Bit 0 – RESRDY Result Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Result Ready Interrupt Enable bit, which disables the corresponding interrupt
request.
Value
Description
0
The Result Ready interrupt is disabled.
1
The Result Ready interrupt is enabled, and an interrupt request will be generated when the Result
Ready interrupt flag is set.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 825
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6.6
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x05
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
7
6
Access
Reset
5
4
3
OVF
R/W
0
2
WINMON
R/W
0
1
OVERRUN
R/W
0
0
RESRDY
R/W
0
Bit 3 – OVF Overflow Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow Interrupt bit, which enables the Overflow interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
Bit 2 – WINMON Window Monitor Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Window Monitor Interrupt bit, which enables the Window Monitor interrupt.
Value
Description
0
The Window Monitor interrupt is disabled.
1
The Window Monitor interrupt is enabled.
Bit 1 – OVERRUN Overrun Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overrun Interrupt Enable bit, which enables the corresponding interrupt request.
Value
Description
0
The Overrun interrupt is disabled.
1
The Overrun interrupt is enabled.
Bit 0 – RESRDY Result Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Result Ready Interrupt bit, which enables the Result Ready interrupt.
Value
Description
0
The Result Ready interrupt is disabled.
1
The Result Ready interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 826
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6.7
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAG
0x06
0x00
–
6
Access
Reset
5
4
3
OVF
R/W
0
2
WINMON
R/W
0
1
OVERRUN
R/W
0
0
RESRDY
R/W
0
Bit 3 – OVF Overflow
This flag is cleared by writing a one to the flag.
This flag is set when the conversion result requires more than 24 bits and overflows the VALUE register, and an
interrupt request will be generated if INTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
Bit 2 – WINMON Window Monitor
This flag is cleared by writing a one to the flag or by reading the VALUE register.
This flag is set on the next cycle after a match with the window monitor condition, and an interrupt request will be
generated if INTENCLR/SET.WINMON is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Window Monitor interrupt flag.
Bit 1 – OVERRUN Overrun
This flag is cleared by writing a one to the flag.
This flag is set if a valid VALUE is updated before the previous valid value has been read by the CPU, and an
interrupt will be generated if INTENCLR/SET.OVERRUN is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overrun interrupt flag.
Bit 0 – RESRDY Result Ready
This flag is cleared by writing a one to the flag or by reading the VALUE register.
This flag is set when the conversion result is available, and an interrupt will be generated if INTENCLR/SET.RESRDY
is one.
This flag will not set if an overflow occurs during the conversion.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Result Ready interrupt flag.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 827
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6.8
Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x07
0x00
–
7
6
5
4
3
2
Access
Reset
1
0
OVF
R
0
Bit 0 – OVF Result Overflow
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
Value
Description
0
No overflow in the VALUE register has occurred. The result is valid.
1
An overflow occurred in the VALUE register. The result is not valid.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 828
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6.9
Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x08
0x00000000
–
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – ENABLE Enable Busy
This bit is cleared when the synchronization of CTRLA.ENABLE is complete.
This bit is set when the synchronization of CTRLA.ENABLE is started.
Bit 0 – SWRST Software Reset Busy
This bit is cleared when the synchronization of CTRLA.SWRST is complete.
This bit is set when the synchronization of CTRLA.SWRST is started.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 829
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6.10 Value
Name:
Offset:
Reset:
Property:
Bit
VALUE
0x0C
0x0000
–
31
30
29
28
27
26
25
24
Bit
23
22
21
18
17
16
Access
Reset
R
0
R
0
R
0
20
19
VALUE[23:16]
R
R
0
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
VALUE[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
VALUE[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 23:0 – VALUE[23:0] Measurement Value
Result from measurement. This VALUE is in two’s complement format.
Example: If the TSENS GAIN and OFFSET registers are setup with values stored in the 8.5 NVM Temperature
Calibration Area Mapping, the TSENS resolution is set at 100 which will result in the following values
Temperature
VALUE
T = 25°C
T = -25°C
2500 = 0x09C4
-2500 = 0xFFF63C
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 830
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6.11 Window Monitor Lower Threshold
Name:
Offset:
Reset:
Property:
Bit
WINLT
0x10
0x0000
PAC Write-Protection, Enable-Protected
31
30
29
28
23
22
21
20
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
27
26
25
24
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
19
WINLT[23:16]
R/W
R/W
0
0
12
11
WINLT[15:8]
R/W
R/W
0
0
4
WINLT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 23:0 – WINLT[23:0] Window Lower Threshold
If the window monitor is enabled, these bits define the lower threshold value. This WINLT value is in two’s
complement format.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 831
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6.12 Window Monitor Upper Threshold
Name:
Offset:
Reset:
Property:
Bit
WINUT
0x14
0x0000
PAC Write-Protection, Enable-Protected
31
30
29
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
28
27
26
25
24
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
20
19
WINUT[23:16]
R/W
R/W
0
0
12
11
WINUT[15:8]
R/W
R/W
0
0
4
WINUT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 23:0 – WINUT[23:0] Window Upper Threshold
If the window monitor is enabled, these bits define the upper threshold value. This WINUT value is in two’s
complement format.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 832
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6.13 Gain
Name:
Offset:
Reset:
Property:
Bit
GAIN
0x18
0x0000
Enable-Protected, PAC Write-Protection, not reset by a software reset
31
30
29
28
23
22
21
20
R/W
0
R/W
0
R/W
0
15
14
13
27
26
25
24
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
19
GAIN[23:16]
R/W
R/W
0
0
12
GAIN[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
GAIN[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 23:0 – GAIN[23:0] Time Amplifier Gain
This value from production test must be loaded from the NVM temperature calibration row into the register by
software to achieve the specified accuracy.
The bitfield can also be written by CPU.
The GAIN value defines the number of GCLK_TSENS periods that will be used for a measurement cycle.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 833
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6.14 Offset
Name:
Offset:
Reset:
Property:
Bit
OFFSET
0x1C
0x0000
Enable-Protected, PAC Write-Protection, not reset by a software reset
31
30
29
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
26
25
24
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
20
19
OFFSETC[23:16]
R/W
R/W
0
0
12
11
OFFSETC[15:8]
R/W
R/W
0
0
4
3
OFFSETC[7:0]
R/W
R/W
0
0
Bits 23:0 – OFFSETC[23:0] Offset Correction
This value from production test must be loaded from the NVM temperature calibration row into the register by
software to achieve the specified accuracy.
The bitfield can also be written by CPU.
These bits define how the TSENS measurement result is compensated for offset error before being written to the
VALUE register. This OFFSET value is in two’s complement format.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 834
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6.15 Calibration
Name:
Offset:
Reset:
Property:
Bit
CAL
0x20
0x00000000
Enable-Protected, PAC Write-Protection, not reset by a software reset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
TCAL[5:0]
Access
Reset
Bit
7
6
R/W
0
R/W
0
R/W
0
5
4
3
FCAL[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 13:8 – TCAL[5:0] Temperature Calibration
This value from production test must be loaded from the NVM software calibration row into the CAL register by
software to achieve the specified accuracy. The value must be copied only, and must not be changed.
Bits 5:0 – FCAL[5:0] Frequency Calibration
This value from production test must be loaded from the NVM software calibration row into the CAL register by
software to achieve the specified accuracy. The value must be copied only, and must not be changed.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 835
PIC32CM MC00 Family
Temperature Sensor (TSENS)
40.6.16 Debug Control
Name:
Offset:
Reset:
Property:
Bit
DBGCTRL
0x24
0x00
–
7
6
5
4
3
Access
Reset
2
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Debug Run
This bit is reset by a system software reset.
This bits controls the functionality when the CPU is halted by an external debugger.
Value
Description
0
The TSENS is halted when the CPU is halted by an external debugger. Any on-going measurement will
complete.
1
The TSENS continues normal operation when the CPU is halted by an external debugger.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 836
PIC32CM MC00 Family
Frequency Meter (FREQM)
41.
Frequency Meter (FREQM)
41.1
Overview
The Frequency Meter (FREQM) can be used to accurately measure the frequency of a clock by comparing it to a
known reference clock.
41.2
Features
•
•
•
•
41.3
Ratio can be measured with 24-bit accuracy
Accurately measures the frequency of an input clock with respect to a reference clock
Reference clock can be selected from the available GCLK_FREQM_REF sources
Measured clock can be selected from the available GCLK_FREQM_MSR sources
Block Diagram
Figure 41-1. FREQM Block Diagram
GCLK_FREQM_MSR
EN
CLK_MSR
COUNTER
VALUE
START
GCLK_FREQM_REF
CLK_REF
EN
TIMER
DONE
REFNUM
INTFLAG
ENABLE
41.4
Peripheral Dependencies
Peripheral
Base Address
AHB CLK
APB CLK
Generic CLK
Enabled at reset
Enabled at reset
Index
-
Y
PAC
Events
DMA
IRQ
Sleep Walking
Index
Prot at reset
User
Generator
Index
11
N
-
-
-
3: Measure
FREQM
0x40002C00
4
-
4: Reference
41.5
41.5.1
Functional Description
Principle of Operation
FREQM counts the number of periods of the measured clock (GCLK_FREQM_MSR) with respect to the reference
clock (GCLK_FREQM_REF). The measurement is done for a period of REFNUM/fCLK_REF and stored in the Value
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Datasheet
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PIC32CM MC00 Family
Frequency Meter (FREQM)
register (VALUE.VALUE). REFNUM is the number of Reference clock cycles selected in the Configuration A register
(CFGA.REFNUM).
The frequency of the measured clock, fCLK_MSR, is calculated by
41.5.2
fCLK_MSR =
VALUE f
REFNUM CLK_REF
Basic Operation
41.5.2.1 Initialization
Before enabling FREQM, the device and peripheral must be configured:
• Each of the generic clocks (GCLK_FREQM_REF and GCLK_FREQM_MSR) must be configured and enabled.
Find CLK_FREQM_REF and GCLK_FREQM_MSR values listed in Table 12-9. PCHCTRLm Mapping.
Important: The reference clock must be slower than the measurement clock.
•
Write the number of Reference clock cycles for which the measurement is to be done in the Configuration A
register (CFGA.REFNUM). This must be a non-zero number.
The following register is enable-protected, that is it can only be written when the FREQM is disabled:
(CTRLA.ENABLE=0):The Configuration A register (CFGA)
Enable-protection is denoted by the "Enable-Protected" property in the register description.
41.5.2.2 Enabling, Disabling and Resetting
The FREQM is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The peripheral is
disabled by writing CTRLA.ENABLE=0.
The FREQM is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). On software
reset, all registers in the FREQM will be reset to their initial state, and the FREQM will be disabled.
Then ENABLE and SWRST bits are write-synchronized.
For more information, refer to FREQM - Synchronization.
41.5.2.3 Measurement
In the Configuration A register, the Number of Reference Clock Cycles field (CFGA.REFNUM) selects the duration of
the measurement. The measurement is given in number of GCLK_FREQM_REF periods.
Note: The REFNUM field must be written before the FREQM is enabled.
After the FREQM is enabled, writing a '1' to the START bit in the Control B register (CTRLB.START) starts the
measurement. The BUSY bit in Status register (STATUS.BUSY) is set when the measurement starts, and cleared
when the measurement is complete.
There is also an interrupt request for Measurement Done: When the Measurement Done bit in Interrupt Enable Set
register (INTENSET.DONE) is '1' and a measurement is finished, the Measurement Done bit in the Interrupt Flag
Status and Clear register (INTFLAG.DONE) will be set and an interrupt request is generated.
The result of the measurement can be read from the Value register (VALUE.VALUE). The frequency of the measured
clock GCLK_FREQM_MSR is then:
fCLK_MSR =
VALUE f
REFNUM CLK_REF
Note: In order to make sure the measurement result (VALUE.VALUE[23:0]) is valid, the overflow status
(STATUS.OVF) should be checked.
In case an overflow condition occurred, indicated by the Overflow bit in the STATUS register (STATUS.OVF), either
the number of reference clock cycles must be reduced (CFGA.REFNUM), or a faster reference clock must be
configured. Once the configuration is adjusted, clear the overflow status by writing a '1' to STATUS.OVF. Then
another measurement can be started by writing a '1' to CTRLB.START.
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Datasheet
DS60001638D-page 838
PIC32CM MC00 Family
Frequency Meter (FREQM)
41.5.3
Interrupts
The FREQM has one interrupt source:
•
DONE: A frequency measurement is done.
The interrupt flag in the Interrupt Flag Status and Clear (41.6.6 INTFLAG) register is set when the interrupt
condition occurs. The interrupt can be enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set
(41.6.5 INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear
(41.6.4 INTENCLR) register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the FREQM is reset. See
41.6.6 INTFLAG for details on how to clear interrupt flags.
This interrupt is a synchronous wake-up source.
Note that interrupts must be globally enabled for interrupt requests to be generated.
41.5.4
Sleep Mode Operation
The FREQM will continue to operate in Idle Sleep mode where the selected source clock is running. The FREQM’s
interrupts can be used to wake up the device from Idle Sleep mode.
For lowest chip power consumption in sleep modes, FREQM should be disabled before entering a Sleep mode.
For more information, refer to the 16. Power Manager (PM).
41.5.5
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits and registers are write-synchronized:
•
•
Software Reset bit in Control A register (CTRLA.SWRST)
Enable bit in Control A register (CTRLA.ENABLE)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description
For more information, refer to 11.3 Register Synchronization.
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Datasheet
DS60001638D-page 839
PIC32CM MC00 Family
Frequency Meter (FREQM)
41.6
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
CTRLA
CTRLB
0x02
CFGA
7:0
7:0
7:0
15:8
0x04
...
0x07
0x08
0x09
0x0A
0x0B
INTENCLR
INTENSET
INTFLAG
STATUS
0x0C
SYNCBUSY
0x10
7
6
5
4
3
2
1
0
ENABLE
SWRST
START
REFNUM[7:0]
Reserved
VALUE
7:0
7:0
7:0
7:0
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
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OVF
ENABLE
DONE
DONE
DONE
BUSY
SWRST
VALUE[7:0]
VALUE[15:8]
VALUE[23:16]
Datasheet
DS60001638D-page 840
PIC32CM MC00 Family
Frequency Meter (FREQM)
41.6.1
Control A
Name:
Offset:
Reset:
Property:
Bit
CTRLA
0x00
0x00
PAC Write-Protection, Write-Synchronized Bits
7
6
5
4
3
Access
Reset
2
1
ENABLE
R/W
0
0
SWRST
R/W
0
Bit 1 – ENABLE Enable
Note: This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
Value
0
1
Description
The peripheral is disabled.
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the FREQM to their initial state, and the FREQM will be disabled.
Writing a '1' to this bit will always take precedence, meaning that all other writes in the same write-operation will be
discarded.
Note: This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST
synchronization is complete.
Value
0
1
Description
There is no ongoing Reset operation.
The Reset operation is ongoing.
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Datasheet
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PIC32CM MC00 Family
Frequency Meter (FREQM)
41.6.2
Control B
Name:
Offset:
Reset:
Property:
Bit
CTRLB
0x01
0x00
–
7
6
5
4
3
2
1
0
START
W
0
Access
Reset
Bit 0 – START Start Measurement
Note: Reading the START bit will result in a PAC error when PAC protection is enabled for the FREQM.
Value
0
1
Description
Writing a '0' has no effect.
Writing a '1' starts a measurement.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 842
PIC32CM MC00 Family
Frequency Meter (FREQM)
41.6.3
Configuration A
Name:
Offset:
Reset:
Property:
Bit
CFGA
0x02
0x0000
PAC Write-Protection, Enable-protected
15
14
13
12
7
6
5
4
R/W
0
R/W
0
R/W
0
11
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
3
REFNUM[7:0]
R/W
R/W
0
0
Bits 7:0 – REFNUM[7:0] Number of Reference Clock Cycles
Selects the duration of a measurement in number of CLK_FREQM_REF cycles. This must be a non-zero value, i.e.
0x01 (one cycle) to 0xFF (255 cycles).
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Datasheet
DS60001638D-page 843
PIC32CM MC00 Family
Frequency Meter (FREQM)
41.6.4
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
Bit
INTENCLR
0x08
0x00
PAC Write-Protection
7
6
5
4
3
Access
Reset
2
1
0
DONE
R/W
0
Bit 0 – DONE Measurement Done Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Measurement Done Interrupt Enable bit, which disables the Measurement Done
interrupt.
Value
Description
0
The Measurement Done interrupt is disabled.
1
The Measurement Done interrupt is enabled.
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Datasheet
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PIC32CM MC00 Family
Frequency Meter (FREQM)
41.6.5
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
Bit
INTENSET
0x09
0x00
PAC Write-Protection
7
6
5
4
3
Access
Reset
2
1
0
DONE
R/W
0
Bit 0 – DONE Measurement Done Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Measurement Done Interrupt Enable bit, which enables the Measurement Done
interrupt.
Value
Description
0
The Measurement Done interrupt is disabled.
1
The Measurement Done interrupt is enabled.
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Datasheet
DS60001638D-page 845
PIC32CM MC00 Family
Frequency Meter (FREQM)
41.6.6
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAG
0x0A
0x00
–
6
5
4
3
Access
Reset
2
1
0
DONE
R/W
0
Bit 0 – DONE Mesurement Done
This flag is cleared by writing a '1' to it.
This flag is set when the STATUS.BUSY bit has a one-to-zero transition.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the DONE interrupt flag.
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Datasheet
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PIC32CM MC00 Family
Frequency Meter (FREQM)
41.6.7
Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x0B
0x00
–
7
6
5
4
3
Access
Reset
2
1
OVF
R/W
0
0
BUSY
R
0
Bit 1 – OVF Sticky Count Value Overflow
This bit is cleared by writing a '1' to it.
This bit is set when an overflow condition occurs to the value counter.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the OVF status.
Bit 0 – BUSY FREQM Status
Value
Description
0
No ongoing frequency measurement.
1
Frequency measurement is ongoing.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 847
PIC32CM MC00 Family
Frequency Meter (FREQM)
41.6.8
Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x0C
0x00000000
–
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – ENABLE Enable
This bit is cleared when the synchronization of CTRLA.ENABLE is complete.
This bit is set when the synchronization of CTRLA.ENABLE is started.
Bit 0 – SWRST Synchronization Busy
This bit is cleared when the synchronization of CTRLA.SWRST is complete.
This bit is set when the synchronization of CTRLA.SWRST is started.
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
Frequency Meter (FREQM)
41.6.9
Value
Name:
Offset:
Reset:
Property:
Bit
VALUE
0x10
0x00000000
–
31
30
29
28
27
26
25
24
Bit
23
22
21
18
17
16
Access
Reset
R
0
R
0
R
0
20
19
VALUE[23:16]
R
R
0
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
VALUE[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
VALUE[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 23:0 – VALUE[23:0] Measurement Value
Result from measurement.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 849
PIC32CM MC00 Family
Position Decoder (PDEC)
42.
Position Decoder (PDEC)
42.1
Overview
The PDEC consists of a Quadrature / Hall decoder, followed by a counter, with two compare channels. The counter
can be split into two parts to report the angular position and the number of revolutions. If the quadrature decoder
feature is not suitable for specific applications, the PDEC module can be used as an additional time base.
42.2
Features
•
•
•
•
•
Internal prescaler
Selectable mode of operation:
– QDEC, HALL or COUNTER
QDEC
– Angular and revolution counts
– Synchronous and asynchronous velocity measurements
– Direction change detection
– Check valid quadrature transitions
– Check index position versus angular position
– Auto correction mode
HALL
– Window validation of Hall transitions
– Hall code detection
– Direction change detection
– Check valid Hall transitions
– Programmable event generation delay after a Hall transition
COUNTER
– 16-bit counter with two compare channels
– One of the compare channels can be configured with period settings
– Counter overflow interrupt and event generation option
– Compare match interrupt and event generation option
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 850
PIC32CM MC00 Family
Position Decoder (PDEC)
42.3
Block Diagram
Figure 42-1. Block Diagram
CC1
MC1 (Interrupt or Event)
CC0
MC0 (Interrupt or Event)
COUNT
OVF (Interrupt or Event)
sync
Signal 0
PINVE
PDEC_EV[0]
PINEN
EVINV
EVEI
0
PDEC[0]
Control
Logic
Filter
sync
Signal 1
PINVE
PDEC_EV[1]
PINEN
EVINV
EVEI
0
PDEC[1]
PDEC[2]
42.4
VLC (Interrupt or Event)
PINEN
sync
DIR (Interrupt or Event)
Signal 2
ERR (Interrupt or Event)
PINVE
PDEC_EV[2]
EVEI
EVINV
0
Signal Description
Signal Name
Type
Description
PDEC[2:0]
Digital input
PDEC inputs
Note: One signal can be mapped on one of several pins.
42.5
Peripheral
Peripheral Dependencies
Base Address
AHB CLK
APB CLK
Generic CLK
Enabled at reset
Enabled at reset
Index
PAC
Events
DMA
IRQ
Sleep Walking
Index
Prot at reset
User
Generator
Index
83: OVF
44: EVU0
84: ERR
85: DIR
PDEC
0x42006800
26
-
N
34
26
N
45: EVU1
-
Y
86: VLC
87:MC0
46:EVU2
88: MC1
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 851
PIC32CM MC00 Family
Position Decoder (PDEC)
42.6
Functional Description
42.6.1
Principle of Operation
The PDEC control logic can be driven by a set of three inputs signal coming from Event System channels or I/O
input pins. These three inputs can be filtered prior to down-stream processing. The input polarity, phase definition and
other factors are configurable. QDEC, HALL or COUNTER mode of operation are supported.
Depending of the mode configuration, specific input sequences can generate:
•
•
•
•
42.6.2
State change
Counter increment or decrement
Interrupts
Output events
Basic Operation
42.6.2.1 Initialization
The following PDEC registers are enable-protected, meaning they can only be written when the PDEC is disabled
(CTRLA.ENABLE is zero):
•
Event Control register (EVCTRL)
Enable-protection is denoted by the 'Enable-Protected' property in the register description.
The following register bits are enable-protected, meaning that they can only be written when the PDEC is disabled
(CTRLA.ENABLE=0):
•
•
•
•
•
•
•
•
•
•
Maximum Consecutive Missing Pulses bits in Control A register (CTRLA.MAXCMP[3:0])
Angular Counter Length bits in Control A register (CTRLA.ANGULAR[2:0])
I/O Pin x Invert Enable bits in Control A register (CTRLA.PINVEN[2:0])
PDEC Input From Pin x Enable bits in Control A register (CTRLA.PINEN[2:0])
Period Enable bit in Control A register (CTRLA.PEREN)
PDEC Phase A and B Swap bit in Control A register (CTRLA.SWAP)
Auto Lock bit in Control A register (CTRLA.ALOCK)
PDEC Configuration bits in Control A register (CTRLA.CONF[2:0])
Run in Standby bit in Control A register (CTRLA.RUNSTDBY)
Operation Mode bits in Control A register (CTRLA.MODE[1:0])
Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but
not at the same time as CTRLA.ENABLE is written to '0'.
42.6.2.2 Enabling, Disabling, and Resetting
The PDEC must be configured before it is enabled by the following steps:
1.
2.
3.
4.
5.
Enable the PDEC bus clock (CLK_PDEC_APB).
Select the mode of operation by writing the Mode bits in the Control A register (CTRLA.MODE).
Select the PDEC mode configuration by writing the Configuration bits in the Control A register (CTRLA.CONF).
Select the PDEC event or pin input signal source by writing the Event Enable Input bit in the Event Control
register (EVCTRL.EVEI) or the Pin Enable bit in Control A register (CTRLA.PINEN).
Select the angular counter length value by writing the Angular bits in the Control A register
(CTRLA.ANGULAR).
Optionally, the following configurations can be set before enabling PDEC:
•
•
•
The GCLK_PDEC clock can be prescaled by writing to the Prescaler register (PRESC).
A filter can be applied to the input signal by writing a corresponding value to the Filter register (FILTER).
If the resolution of the rotary sensor is not a power of 2, an Angular period can be set (CTRLA.PEREN and CC0
register).
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Datasheet
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PIC32CM MC00 Family
Position Decoder (PDEC)
The PDEC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The PDEC is
disabled by writing a '0' to CTRLA.ENABLE.
In QDEC or HALL operation modes, PDEC decoding is enabled writing a START command in the Control B Set
register (CTRLBSET.CMD=START). The PDEC decoding is disabled writing a STOP command in the Control B Set
register (CTRLBSET.CMD=STOP).
The PDEC is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in
the PDEC, except DBGCTRL, will be reset to their initial state, and the PDEC will be disabled.
The PDEC should be disabled before the PDEC is reset to avoid undefined behavior.
42.6.2.3 Prescaler Selection
The GCLK_PDEC is fed into the internal prescaler. Prescaler outputs from 1 to 1/1024 are directly available for
selection by the counter and all selections are available in Prescaler register (PRESC). If the prescaler value is higher
than 0x01, the counter update condition is executed on the next prescaled clock pulse.
The prescaler clock is also enabled when the input filtering is required.
Figure 42-2. Prescaler Selection
PRESC
GCLK_PDEC
Prescaler
GCLK_PDEC /
{1,2,4,8,64,256,1024 }
EVENT
EVACT
CLK_PDEC
COUNT
42.6.2.4 Input Selection and Filtering
The QDEC and HALL operations require three inputs, as shown in the Block Diagram. Each input can either be a
dedicated I/O pin or an Event system channel. This is selected by writing to the corresponding Event x Enable bit in
the Event Control register (EVCTRL.EVEIx) or the Pin x Enable bit in the Control A register (CTRLA.PINENx).
The I/O input pin active level can be inverted by writing to the corresponding Pin x Inversion Enable bit in the Control
A register (CTRLA.PINVENx). Similarly, the event input active level can be inverted by writing to the corresponding
Inverted Event x Input Enable bit in the Event Control register (EVCTRL.EVINVx).
All input signals can be filtered before they are fed into the control logic. The FILTER register is used to configure the
minimum duration for which the input signal must be valid. The input signal minimum duration must be (FILTER +1)*
tGCLK_PDEC .
Figure 42-3. Input Signal Filtering
Prescaled Clock
(Signal 0, Signal 1, Signal 2)
Filter Out
Only the first two input signals can be swapped by writing to the SWAP bit in the Control A register (CTRLA.SWAP).
42.6.2.5 Period Control
The Channel Compare 0 register (CC0) can act as a period register (PER) by writing the PEREN bit in the Control A
register (CTRLA.PEREN) to '1'. The PER can be used to control the top value (TOP) of the counting operation:
When up-counting and the counter reaches the value of CC0, the counter is cleared to zero. When down-counting
and the counter reaches zero, the counter is reloaded with the CC0 value.
42.6.2.6 QDEC Operation Mode
In QDEC mode of operation, Signal 0 and Signal 1 control logic inputs refer to Phase A and Phase B in X4 mode,
and to count/direction in X2 mode. The Signal 2 control logic input refers to the Index, in both X4 and X2 mode
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PIC32CM MC00 Family
Position Decoder (PDEC)
of operation. In X4 mode, a simultaneous transition on Phase A and Phase B will cause a QDEC error detection
(STATUS.QERR).
Signal 0
Phase A
Count
sync
Figure 42-4. QDEC Block Diagram
Quadrature
Decoder
Filter
Signal 1
Phase B
Direction
sync
Position Clock
Position Direction
Count
DIR
CC1
MC1 (Interrupt or Event)
CC0
MC0 (Interrupt or Event)
Angular
Reset Counter (n-bits)
ovf
Revolution
Counter (16/32-n-bits)
Revolution Check
Velocity Clock
Index
VLC (Interrupt or Event)
Direction Change Detection
sync
Signal 2
OVF (Interrupt or Event)
First Index Sync
Error Detection
DIR (Interrupt or Event)
ERR (Interrupt)
42.6.2.6.1 Position and Rotation Measurement
After filtering, the quadrature signals are analyzed to extract the rotation direction and edges in order to be counted
by the counter.
The counter is split in two parts. The LSB part of the counter is used as Angular counter. The Phase A and B define
the motor deplacement direction, which define the Angular and Revolution counting direction.
The Index can be enabled in two different ways:
• Set the PINEN[2] bit in the Control A register (CTRLA.PINEN[2]), if the Index is provided by the PIN2 IO pin
directly
• Set the EVEI[2] bit in Event Control register (EVCTRL.EVEI[2]), if the INDEX is provided by a channel
connected to the Event System
• If the signal polarity must be inverted, the user must program the PINVEN[2] in Control A register
(CTRLA.PINVEN[2]) or EVINV[2] in Event Control register (EVCTRL.EVINV[2])
A valid Index is qualified with the two other inputs (PhaseA, PhaseB) at low level.
Each counter has a TOP value, defined as follows:
•
•
If the Period is disabled (CTRLA.PEREN = 0), the TOP value for each counter represents the MAX value (all bit
are one)
If the Period is enabled (CTRLA.PEREN = 1), the Angular counter TOP value is the CC0 LSB portion, and the
Revolution counter TOP value is the CC0 MSB portion. Refer to CTRLA.ANGULAR settings for details.
The "Signal 0" and "Signal 1" (refer to Figure 2-1 for details) edge detections define the motor axis position, which
increments or decrements the Angular counter. The Angular counter will count up or down, depending on the
counting direction. The counter is reloaded with its TOP or ZERO value depending on counting direction.
When the Index detection is disabled, the Angular counter is reloaded with its TOP or ZERO, depending on counter
direction only, when the overflow (angular counter equals its TOP) or underflow (angular counter equals zero)
conditions are met.
•
•
When the counter is counting up and its TOP value is reached, the counter will be reloaded with ZERO value
on the next tick (overflow) and the Overflow Interrupt Flag in the Interrupt Flag Status and Clear register
(INTFLAG.OVF) will be set.
When the counter is counting down and ZERO is reached, the counter will be reloaded with its TOP value on the
next tick (underflow), and the INTFLAG.OVF will be set. INTFLAG.OVF can be used to trigger an interrupt or an
event.
When the Index is enabled, additional actions will occur, depending on operating configuration (CTRLA.CONF):
•
•
In X2 and X4 confirmation operating mode:
– When the counter is counting up, a valid Index detection will reload the counter with ZERO value
– When the counter is counting down, a valid Index detection will reload the counter with its TOP value
In X2S and X4S confirmation operating mode:
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and its subsidiaries
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PIC32CM MC00 Family
Position Decoder (PDEC)
– The first valid Index detection after the module is enabled, will reload the counter with ZERO value
– Any other valid Index detection which does not match the Angular counter overflow or underflow,
will set the Index Error flag in Status register (STATUS.IDXERR). The Error Interrupt Flag is set
(INTFLAG.ERR)and an optional interrupt can be generated.
The Revolution counter will count up or down, depending on the counting direction and configuration modes:
•
•
In X2 and X4 confirmation operating mode:
– If the Index is enabled, the counter is incremented (or decremented depending on counting direction) on
each index detection
– If the Index is disabled, the counter is incremented (or decremented depending on counting direction) on
each Angular counter overflow/underflow
In X2S and X4S confirmation operating mode, the counter is incremented (or decremented depending on
counting direction) on each Angular counter overflow/underflow
– If the Index is not detected after one Angular counter revolution, the Index Error flag in Status register
(STATUS.IDXERR) is set. The Error Interrupt Flag is set (INTFLAG.ERR) and an optional interrupt can be
generated.
When counting-up and its TOP value is reached, the Channel 0 Compare Match Interrupt Flag in the Interrupt
Flag Status and Clear register (INTFLAG.MC0) will be set. When counting-down and ZERO is reached, the
INTFLAG.MC0 will be set. The Channel 0 Compare Match condition can be enabled as source of interrupt or event
generation.
Figure 42-5. Position and Rotation Measurement
PhaseA
PhaseB
Index
DIR Event
Angle OVF
ERR
CC0 (LSB)
CC1 (LSB)
Anglular
Counter
CC1 (MSB)
Revolution
Counter
MC1 Event
In X4 and X4S configuration, a valid index is detected when the three inputs (PhaseA, PhaseB and Index) are at low
level.
In X2 and X2S configuration, a valid index is detected when the two inputs (Count and Index) are at low level.
In X2 and X4 configuration, depending on current detected direction, Index will reset or reload the Angular counter
and increment or decrement the Revolution counter.
In X2S and X4S configuration, the Angular counter is reset on the first Index occurrence after the PDEC decoding
is enabled. When any next Index occurrence does not match an Angular counter overflow or underflow, the Index
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and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Position Decoder (PDEC)
Error flag in Status register is set (STATUS.IDXERR). The Error Interrupt Flag is set (INTFLAG.ERR) and an optional
interrupt can be generated.
An Index Error is also generated after the PDEC decoding is enabled and no Index has been detected after one
Angular counter revolution.
42.6.2.6.2 Secure Decoder Detection
Position decoders are generally implemented using external photo-detectors, detecting a transmitted or reflected
beam. Error detections or no detections may happen, and are due to:
•
•
•
A transmitted bean locally stopped by a dust
A reflected beam lost by a mat dust
An additional parasitic reflected beam, due to a gloss metallic dust
When secure detection is enabled (CTRLA.CONF = X4S or CTRLA.CONF = X2S), the Index must be enabled. The
Angular counter is restarted on the detection of each overflow. When the Angular counter value reaches its maximum
period value (TOP), an Index is expected to be detected. In the same way, if the Index is detected, the Angular
counter value is expected to be TOP. If one of these conditions is not met, an error is generated.
Note: The first error generation is masked, as the initial position of the wheel is in unknown state. The first index is
used to synchronize the Angular counter on Revolution counter increment.
Figure 42-6. Secure Decoder Detections
First error detection is ignored
Missing Angular Step
Detection
Extra Index Detection
Missing Index
Detection
Phase A
Phase B
Index
ERR
Match Angular
Max Value
Angular
Counter
Revolution
Counter
42.6.2.6.3 Direction Status and Change Detection
The direction (DIR) status can be directly read anytime in the STATUS register (STATUS.DIR). The polarity of the
direction flag status depends of the input signal swap and active level configuration.
Each time a rotation direction change is detected, the Direction Change Interrupt Flag is set (INTFLAG.DIR) and an
optional interrupt can be generated. The same interrupt condition is source of Direction event output.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 856
PIC32CM MC00 Family
Position Decoder (PDEC)
Figure 42-7. Rotation Direction Change
PhaseA
PhaseB
Anglular
Counter
DIR Event
DIRCHG Interrupt
VLC Event
To avoid spurious interrupts when coding wheel is stopped, the direction change condition is reported as an interrupt,
only on the second edge confirming the direction change.
Velocity output event is generated on each QDEC transition except when the direction changes.
42.6.2.6.4 Speed Measurement
Three types of speed measurement can be done using velocity event output (VLC) and Timer/Counter (TC/TCC)
device resources.
•
•
•
Continuous velocity measurement: TCz measures the time on which n VLC (TCy) output events occur
Synchronous Velocity measurement: On a specific motor position TCCz, the time is measured on which n VLC
(TCCy) output events occur.
Slow Velocity measurement: measure the number of VLC output events (TCCy) plus the delay since the last
VLC output event (TCCz) within a given time slot (TCk).
Figure 42-8. Speed Measurement
Continuous Velocity Measurement
(Figure A)
PhaseA
PhaseB
Index
Count
Capture &
Retrigger
WO[0]
WO[1]
EV
QDEC
MC1
MC0
OVF
VLC
EV
TCy
MC1
MC0
OVF
EV
TCz
MC1
MC0
OVF
Synchronous Velocity Measurement
(Figure B)
PhaseA
PhaseB
Index
Count
Retrigger
Capture
Retrigger
WO[0]
WO[1]
EV
QDEC
MC1
MC0
OVF
VLC
EV0
EV1
TCCy
MC1
MC0
OVF
MC0
EV1
TCCz
MC1
MC0
OVF
Slow Velocity Measurement
(Figure C)
PhaseA
PhaseB
Index
Count
Capture &
Retriger
Capture
Retrigger
WO[0]
WO[1]
EV
QDEC
MC1
MC0
OVF
VLC
EV0
MC0
TCCy
MC1
MC0
OVF
MC0
EV1
TCCz
MC1
MC0
OVF
EV
TCk
MC1
MC0
OVF
42.6.2.6.5 Missing Pulse Detection and Auto-Correction
The PDEC embeds circuitry to detect and correct errors that may result from contamination on optical disks or other
sources producing quadrature phase signals.
The auto-correction works in QDEC X4 mode only. A missing pulse on a phase signal is automatically detected, and
the pulse count reported in the Angular part of COUNT is automatically corrected.
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Datasheet
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PIC32CM MC00 Family
Position Decoder (PDEC)
There is no autocorrection if both phase signals are affected at the same location on the input signals, because the
autocorrection requires a valid phase signal to detect contamination on the other phase signal.
If the quadrature source is undamaged, the number of pulses counted for a predefined period of time must be the
same with or without detection and auto-correction. Therefore, if the measurement results differ, a contamination
exists on the source producing the quadrature signals. This does not substitute the measurements of the number
of pulses between two index pulses (if available) but provides an additional method to detect damaged quadrature
sources.
When the source providing quadrature signals is strongly damaged, potentially leading to a number of consecutive
missing pulses greater than 1, the quadrature decoder processing may be affected.
The Maximum Consecutive Missing Pulses bits in Control A register (CTRLA.MAXCMP) define the maximum
acceptable number of consecutive missing pulses. If the limit is reached, the Missing Pulse Error flag in Status
register (STATUS.MPERR) is set. The Error Interrupt flag is set (INTFLAG.ERR) and an optional interrupt can be
generated.
Note: When the MAXCMP value is zero, the MPERR error flag is never set.
42.6.3
Additional Features
42.6.3.1 HALL Operation Mode
In HALL operation mode, control logic signal 0, 1 and 2 inputs represent the phase A, B and C of a Hall sensor,
respectively.
A programmable delayed event can be generated to update a TCC pattern generator.
Hall
Decoder
Phase B
Filter
Signal 1
Phase A
sync
Signal 0
sync
Figure 42-9. HALL Block Diagram
Reset
CC1(MSB)
Window Max
CC1[2:0]
(Unused)
MC1 (Interrupt/Event)
CC0(MSB)
Window Min
CC0[2:0]
Hall Code Trigger
MC0 (Interrupt/Event)
COUNT(LSB)
Delay Counter
OVF (Interrupt/Event)
COUNT(MSB)
Window Counter
Signal 2
Phase C
sync
Velocity Clock
VLC (Interrupt/Event)
Direction Change Detection
Error Detection
DIR (Interrupt/Event)
ERR (Interrupt/Event)
When positive rotation is detected, the DIR status bit is set (STATUS.DIR = 1). When a negative rotation sequence is
detected, the DIR status bit is set (STATUS.DIR = 0).
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PIC32CM MC00 Family
Position Decoder (PDEC)
Figure 42-10. Hall States Overview
42.6.3.1.1 Hall Sensor Control
On any update of the filter output:
•
•
•
•
•
The filter output value is checked to be a valid Hall value. If an invalid Hall code is reported, the Hall Error bit in
Status register will be set (STATUS.HERR).
The OVF Interrupt Flag bit is set (INTFLAG.OVF) if CC0[2:0] matches the filter output value, stored in LSB part
of the COUNTER. An optional overflow interrupt or Event output is generated on the same condition detection.
The window counter is checked to be between the value of the MSB part of CC0 and CC1, and reset to 0 value.
If an error is detected, the Window Error bit in Status register (STATUS.WINERR) is set.
The delay counter is started, and MC0 optional interrupt or event is generated when the delay counter matches
the MSB part of CC0.
Optional MC1 interrupt or event is generated when the delay counter matches the MSB part of CC1
Any error condition will set the Error Interrupt Flag (INTFLAG.ERR). An optional interrupt or event output is generated
on the same condition detection.
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Datasheet
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PIC32CM MC00 Family
Position Decoder (PDEC)
Figure 42-11. Hall Waveforms
State
101
001
101
100
110
010
011
000
CC1(MSB)
CC0(MSB)
Counter(MSB)
ERR
VLC Event
MC0 Event
OVF Event
DIR Event
DIR Interrupt
42.6.3.2 Counter Operation Mode
Depending on the mode of operation, the counter (Counter Value register COUNT) is cleared, reloaded, or
incremented at each counter clock input.
The counter will count for each clock tick until it reaches TOP. When TOP is reached, the counter will be set to zero
on the next clock input.
This comparison will set the Overflow Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF)
and can be used to trigger an interrupt or an event.
It is possible to change the counter value when the counter is running. The write access has higher priority than
count, or clear. The COUNT value will always be zero when starting the PDEC, unless a different value has been
written to it, or the PDEC has been disabled at a value other than zero. Due to asynchronous clock domains, the
internal counter settings are written once the synchronization is complete.
42.6.3.3 Register Lock Update
Prescaler (PRESC), FILTER, and CCx registers are buffered (PRESCBUF, FILTERBUF, CCBUFx registers,
respectively). When a new value is written in a buffer register, the corresponding Buffer Valid bit is set in the Buffer
Status register (STATUS.FILTERBUFV, STATUS.PRESCBUFV, STATUS.CCBUFVx).
By default, a register is updated with its buffer register's value on UPDATE condition, which represents:
•
•
The next filter transition in QDEC and HALL mode of operation
The overflow/underflow or re-trigger event detection in COUNT mode of operation
The buffer valid flags in the STATUS register are automatically cleared by hardware when the data is copied from the
buffer to the corresponding register.
It is possible to lock the updates by writing a '1' to the Lock Update bit in Control B Set register (CTRLBSET.LUPD).
The lock feature is disabled by writing a '1' to the Lock Update bit in Control B Clear register (CTRLBCLR.LUPD).
When a buffer valid status flag is '1' and updating is not locked, the data from the buffer register will be copied into the
corresponding register on UPDATE condition.
It is also possible to modify the LUPD bit behavior by hardware, by writing a '1' to the Auto-lock bit in Control A
register (CTRLA.ALOCK). When the bit is '1', the Lock Update bit in Control B register (CTRLBSET.LUPD) is set
when the UPDATE condition is detected.
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and its subsidiaries
Datasheet
DS60001638D-page 860
PIC32CM MC00 Family
Position Decoder (PDEC)
42.6.3.4 Software Command and Event Actions
The PDEC peripheral supports software commands and event actions. The software commands are applied by the
Software Command bit field in the Control B register (CTRLBSET.CMD, CTRLBCLR.CMD). The event actions are
available in the Event Action bit-field in Event Control register (EVCTRL.EVACT).
42.6.3.4.1 Re-trigger Software Command or Event Action
A re-trigger command can be issued from software by using PDEC Command bits in Control B Set register
(CTRLBSET.CMD = RETRIGGER) or when the re-trigger event action is configured in the Input Event Action bits in
Event Control register (EVCTRL.EVACT = RETRIGGER) and an event is detected by hardware.
When the re-trigger command is detected during counting operation, the counter will be reloaded or cleared,
depending on the counting direction (DIR). If the re-trigger command is detected when the counter is stopped,
the counter will resume counting operation from the value in the COUNT register.
Note: When re-trigger event action is enabled, enabling the counter will start the counter. The counter will be reset
on the next incoming event and restart on any following event.
42.6.3.4.2 Force Update Software Command
A Force Update command can be issued by writing the PDEC Command bits in Control B Set register
(CTRLBSET.CMD = UPDATE). When the command is issued, the buffered registers will be updated.
42.6.3.4.3 Force Read Synchronization Software Command
A Force Read Synchronization command can be issued writing the PDEC Command bits in Control B Set register
(CTRLBSET.CMD = READSYNC). When the command is issued, a COUNT register read synchronization is forced.
Note: This command should be used to read the most updated COUNT internal value.
42.6.4
Interrupts
The PDEC has the following interrupt sources:
•
•
•
•
•
Overflow/Underflow: OVF
Compare Channels: COMPx
Error: ERR
Velocity: VLC. This interrupt is available only in QDEC and HALL operation modes.
Direction: DIR. This interrupt is available only in QDEC and HALL operation modes.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing
a '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a '1' to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). As both INTENSET and INTENCLR always
reflect the same value, the status of interrupt enablement can be read from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the PDEC is reset. See
the INTFLAG register description for details on how to clear interrupt flags.
The user must read the INTFLAG register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated. See the Nested Vector Interrupt
Controller.
42.6.5
Events
The PDEC can generate the following output events:
•
•
•
•
•
Overflow/Underflow: OVF
Channel x Compare Match: MCx
Error: ERR
Velocity: VLC. This interrupt is available only in QDEC and HALL operation modes.
Direction: DIR. This interrupt is available only in QDEC and HALL operation modes.
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.MCEO) enables the corresponding output
event. Writing a '0' to this bit disables the corresponding output event.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 861
PIC32CM MC00 Family
Position Decoder (PDEC)
In counter mode the PDEC can take action on an input event. PDEC counter event input are available for each of the
three PDEC channels.
•
Retrigger: Restart/retrigger on event
See the EVSYS for further information.
42.6.6
Sleep Mode Operation
The PDEC can be configured to operate in any sleep mode. To be able to run in standby, the RUNSTDBY bit in the
Control A register (CTRLA.RUNSTDBY) must be written to '1'. The PDEC can wake up the device using interrupts
from any sleep mode or perform actions through the Event System.
For more information, refer to:
• 16. Power Manager (PM)
• 16.5.3.3 Sleep Mode Controller
42.6.7
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
•
•
Software Reset bit in the Control A register (CTRLA.SWRST)
Enable bit in the Control A register (CTRLA.ENABLE)
The following registers need synchronization when written:
•
•
•
•
•
•
Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
Status register (STATUS)
Prescaler and Prescaler Buffer registers (PRESC and PRESCBUF)
Compare Value x and Compare Value x Buffer registers (CCx and CCBUFx)
Filter Value and Filter Buffer Value registers (FILTER and FILTERBUF)
Counter Value register (COUNT)
Required write synchronization is denoted by the "Write-Synchronized" property in the register description.
The following registers are synchronized when read:
•
Counter Value register (COUNT): the synchronization is done on demand through READSYNC software
command (CTRLBSET.CMD)
Required read synchronization is denoted by the "Read-Synchronized" property in the register description.
© 2021 Microchip Technology Inc.
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Datasheet
DS60001638D-page 862
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7
Register Summary
Offset
Name
0x00
CTRLA
0x04
0x05
CTRLBCLR
CTRLBSET
0x06
EVCTRL
0x08
0x09
0x0A
0x0B
INTENCLR
INTENSET
INTFLAG
Reserved
0x0C
STATUS
0x0E
0x0F
Reserved
DBGCTRL
0x10
SYNCBUSY
0x14
0x15
0x16
...
0x17
0x18
0x19
0x1A
...
0x1B
PRESC
FILTER
0x1C
0x20
PRESCBUF
FILTERBUF
7:0
15:8
7:0
7:0
15:8
23:16
31:24
7:0
7:0
PEREN
6
5
4
RUNSTDBY
SWAP
PINVEN2
PINVEN1
MAXCMP[3:0]
CMD[2:0]
CMD[2:0]
EVEI[2:0]
MCEO1
MC1
MC1
MC1
3
PINVEN0
MCEO0
MC0
MC0
MC0
DIR
STOP
HERR
CCBUFV1
WINERR
CCBUFV0
CC0
COUNT
FILTER
PRESC
2
1
MODE[1:0]
ALOCK
PINEN2
EVINV[2:0]
VLCEO
VLC
VLC
VLC
DIREO
DIR
DIR
DIR
MPERR
STATUS
CTRLB
0
ENABLE
SWRST
CONF[2:0]
PINEN1
PINEN0
ANGULAR[2:0]
LUPD
LUPD
EVACT[1:0]
ERREO
OVFEO
ERR
OVF
ERR
OVF
ERR
OVF
IDXERR
QERR
FILTERBUFV PRESCBUFV
ENABLE
DBGRUN
SWRST
CC1
PRESC[3:0]
FILTER[7:0]
7:0
7:0
PRESCBUF[3:0]
FILTERBUF[7:0]
Reserved
COUNT
CC0
CC1
0x28
...
0x2F
Reserved
0x34
7:0
15:8
23:16
31:24
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7
Reserved
0x24
0x30
Bit Pos.
CCBUF0
CCBUF1
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
COUNT[7:0]
COUNT[15:8]
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
CCBUF[7:0]
CCBUF[15:8]
© 2021 Microchip Technology Inc.
and its subsidiaries
CC[7:0]
CC[15:8]
CC[7:0]
CC[15:8]
CCBUF[7:0]
CCBUF[15:8]
Datasheet
DS60001638D-page 863
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.1
Control A
Name:
Offset:
Reset:
Property:
CTRLA
0x00
0x00000000
PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits
Bit
31
30
29
MAXCMP[3:0]
RW
RW
0
0
Access
Reset
RW
0
Bit
23
22
PINVEN2
RW
0
21
PINVEN1
RW
0
20
PINVEN0
RW
0
15
PEREN
RW
0
14
SWAP
RW
0
13
12
7
6
RUNSTDBY
RW
0
5
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
28
27
26
RW
0
25
ANGULAR[2:0]
RW
0
RW
0
19
18
PINEN2
RW
0
17
PINEN1
RW
0
16
PINEN0
RW
0
11
ALOCK
RW
0
10
8
RW
0
9
CONF[2:0]
RW
0
RW
0
3
2
1
ENABLE
RW
0
0
SWRST
W
0
RW
0
4
MODE[1:0]
RW
0
RW
0
24
Bits 31:28 – MAXCMP[3:0] Maximum Consecutive Missing Pulses
These bits define the threshold for the maximum consecutive missing pulses in AUTOC configuration of the QDEC
mode.
Outside of AUTOC configuration of QDEC mode, these bits have no effect.
Note: This bit field is enable-protected. This bit field is not synchronized.
Bits 26:24 – ANGULAR[2:0] Angular Counter Length
In QDEC mode, these bits define the size of the Angular counter within COUNT. Angular counter size is equal to
CTRLA.ANGULAR+9. The remaining MSB of the COUNTER register are used for counting revolutions.
For example, CTRLA.ANGULAR=0 defines the 9 LSB of COUNT as Angular counter and the residual 7 MSB of
COUNT as Revolution counter. CTRLA.ANGULAR=7 will define a 16-bit Angular counter and no Revolution counter.
Outside of QDEC mode, these bits have no effect.
Note: This bit field is enable-protected. This bit field is not synchronized.
Table 42-1. Angular and Revolution Counters in COUNTER Register
ANGULAR[2:0]
Angular counter
Revolution counter
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
COUNTER[0:8]
COUNTER[0:9]
COUNTER[0:10]
COUNTER[0:11]
COUNTER[0:12]
COUNTER[0:13]
COUNTER[0:14]
COUNTER[0:15]
COUNTER[9:15]
COUNTER[10:15]
COUNTER[11:15]
COUNTER[12:15]
COUNTER[13:15]
COUNTER[14:15]
COUNTER[15]
no revolution counter
Bits 20, 21, 22 – PINVENx IO Pin x Invert Enable [x = 2..0]
When this bit is written to '1', the corresponding input pin active level is inverted. This bit has no effect if PINENx bit is
zero.
© 2021 Microchip Technology Inc.
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Datasheet
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PIC32CM MC00 Family
Position Decoder (PDEC)
In COUNTER mode only PINVEN[0] is significant.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
Pin active level is not inverted.
Pin active level is inverted.
Bits 16, 17, 18 – PINENx PDEC Input From Pin x Enable [x = 2..0]
This bit enables the IO pin x as signal input.
In COUNTER mode, only PINEN[0] is significant.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
Event line is the signal input.
I/O pin is the signal input.
Bit 15 – PEREN Period Enable
This bit is used to enable the CC0 register as counter period.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
Period register function is disabled.
CC0 is acting as counter period register.
Bit 14 – SWAP PDEC Phase A and B Swap
This bit is used to swap input source of signal 0 and 1.
In COUNTER mode this bit has no effect.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
The input sources of signal 0 and 1 are not swapped.
The input sources of signal 0 and 1 are swapped.
Bit 11 – ALOCK Auto Lock
When this bit is set, the Lock Update bit in Control B register (CTRLB.LUPD) is set by hardware when an UPDATE
condition is detected.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
Auto Lock is disabled.
Auto Lock is enabled.
Bits 10:8 – CONF[2:0] PDEC Configuration
These bits define the PDEC configuration.
Outside of QDEC mode, these bits have no effect.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0
1
2
3
4
Name
X4
X4S
X2
X2S
AUTOC
Description
Quadrature decoder direction
Secure Quadrature decoder direction
Decoder direction
Secure decoder direction
Auto correction mode
Bit 6 – RUNSTDBY Run in Standby
This bit is used to keep the PDEC running in standby mode.
Note: This bit is enable-protected. This bit is not synchronized.
Value
0
1
Description
The PDEC is halted in standby.
The PDEC continues to run in standby.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
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PIC32CM MC00 Family
Position Decoder (PDEC)
Bits 3:2 – MODE[1:0] Operation Mode
These bits select one of the QDEC, HALL, COUNTER modes.
Note: This bit field is enable-protected. This bit field is not synchronized.
Value
0x0
0x1
0x2
Name
QDEC
HALL
COUNTER
Description
QDEC operating mode
HALL operating mode
COUNTER operating mode
Bit 1 – ENABLE Enable
Notes:
1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
2. This bit is not enable-protected.
Value
0
1
Description
The peripheral is disabled.
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the PDEC (except DBGCTRL) to their initial state, and the PDEC will be
disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be
discarded.
Notes:
1. This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST
synchronization is complete.
2. This bit is not enable-protected.
Value
0
1
Description
There is no Reset operation ongoing.
A Reset operation is ongoing.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 866
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.2
Control B Clear
Name:
Offset:
Reset:
Property:
CTRLBCLR
0x04
0x00
PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Control B Set (CTRLBSET) register.
Note: This register is write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the CTRLBCLR register
synchronization is complete.
Bit
Access
Reset
7
RW
0
6
CMD[2:0]
RW
0
5
4
3
RW
0
2
1
LUPD
RW
0
0
Bits 7:5 – CMD[2:0] Command
These bits can be used for software control of the PDEC. When a command has been executed, the CMD bit group
will read back zero. The commands are executed on the next prescaled GCLK_PDEC clock cycle.
Writing a zero to this bit group has no effect.
Writing a valid value to these bits will clear the corresponding pending command.
Writing a '0' to these bits has no effect.
Writing a '1' to an individual bit will clear the corresponding bit.
Value
Name
Description
0
NONE
No action
1
RETRIGGER
Force a counter restart or re-trigger
2
UPDATE
Force update of double buffered registers
3
READSYNC
Force a read synchronization of COUNT
4
START
Start QDEC/HALL
5
STOP
Stop QDEC/HALL
Bit 1 – LUPD Lock Update
This bit controls the update operation of the PDEC buffered registers.
When CTRLB.LUPD is set, no any update of the registers with value of its buffered register is performed on hardware
UPDATE condition. Locking the update ensures that all buffer registers are valid before an hardware update is
performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked.
Writing a '0' to this bit has no effect.
Writing a '1' to this will disable the lock update.
Value
Description
0
The PRESCBUF, FILTERBUF and CCBUFx buffer registers value are copied into CCx and PER
registers on hardware update condition.
1
The PRESCBUF, FILTERBUF and CCBUFx buffer registers value are not copied into CCx and PER
registers on hardware update condition.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 867
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.3
Control B Set
Name:
Offset:
Reset:
Property:
CTRLBSET
0x05
0x00
PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Control B Clear (CTRLBCLR) register.
Note: This register is write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the CTRLBSET register
synchronization is complete.
Bit
Access
Reset
7
RW
0
6
CMD[2:0]
RW
0
5
4
3
RW
0
2
1
LUPD
RW
0
0
Bits 7:5 – CMD[2:0] Command
These bits can be used for software control of the PDEC. When a command has been executed, the CMD bit group
will read back zero. The commands are executed on the next prescaled GCLK_PDEC clock cycle.
Writing a zero to this bit group has no effect.
Writing a valid value to these bits will set the associated command.
Value
Name
Description
0
NONE
No action
1
RETRIGGER
Force a counter restart or retrigger
2
UPDATE
Force update of double buffered registers
3
READSYNC
Force a read synchronization of COUNT
4
START
Start QDEC/HALL
5
STOP
Stop QDEC/HALL
Bit 1 – LUPD Lock Update
This bit controls the update operation of the PDEC buffered registers.
When CTRLB.LUPD is set, no any update of the registers with value of its buffered register is performed on hardware
UPDATE condition. Locking the update ensures that all buffer registers are valid before an hardware update is
performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked.
Writing a '1' to this will enable the Lock Update.
Value
Description
0
The PRESCBUF, FILTERBUF and CCBUFx buffer registers value are copied into CCx and PER
registers on hardware update condition.
1
The PRESCBUF, FILTERBUF and CCBUFx buffer registers value are not copied into CCx and PER
registers on hardware update condition.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 868
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.4
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x06
0x0000
Enable-Protected, PAC Write-Protection
15
14
13
MCEO1
RW
0
12
MCEO0
RW
0
11
VLCEO
RW
0
10
DIREO
RW
0
9
ERREO
RW
0
8
OVFEO
RW
0
7
6
EVEI[2:0]
RW
0
5
4
3
EVINV[2:0]
RW
0
2
1
0
Access
Reset
Bit
Access
Reset
RW
0
RW
0
RW
0
EVACT[1:0]
RW
0
RW
0
RW
0
Bits 12, 13 – MCEOx Match Channel x Event Output Enable [x = 1..0]
These bits control whether event match on channel x is enabled or not and generated for every match.
Value
Description
0
Match event on channel x is disabled and will not be generated.
1
Match event on channel x is enabled and will be generated for every compare.
Bit 11 – VLCEO Velocity Output Event Enable
This bit is used to enable the velocity event. When enabled, an event level will be generated for each change on the
qualified PDEC phases.
This bit has no effect when COUNTER operation mode is selected.
Value
Description
0
VLC output event is disabled and will not be generated.
1
VLC output is enabled and will be generated for every valid velocity condition.
Bit 10 – DIREO Direction Output Event Enable
This bit is used to enable the Direction event. When enabled, an event level output is generated to report the rotation
direction.
Value
Description
0
DIR output event is disabled and will not be generated.
1
DIR output is enabled and changes the level when the rotation direction changes.
Bit 9 – ERREO Error Output Event Enable
This bit enables the output of the Error event (ERR).
Value
Description
0
ERR Event output is disabled.
1
ERR Event output is enabled.
Bit 8 – OVFEO Overflow/Underflow Output Event Enable
This bit is used to enable the Overflow/Underflow event. When enabled, an event will be generated when the Counter
overflows/underflows.
Value
Description
0
Overflow/Underflow event is disabled and will not be generated.
1
Overflow/Underflow event is enabled and will be generated for every counter overflow/underflow.
Bits 7:5 – EVEI[2:0] Event Input Enable
This bit is used to enable asynchronous input event for the Retrigger action. The bit position of the EVEI[2:0] bitfield
corresponds with the PDEC channel number.
Value
Description
0
Incoming events are disabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 869
PIC32CM MC00 Family
Position Decoder (PDEC)
Value
1
Description
Incoming events are enabled.
Bits 4:2 – EVINV[2:0] Inverted Event Input Enable
This bit inverts the asynchronous input event for the Retrigger action. The bit position of the EVINV[2:0] bitfield
corresponds with the PDEC channel number.
Value
Description
0
Input event source is not inverted.
1
Input event source is inverted.
Bits 1:0 – EVACT[1:0] Event Action
These bits have an effect only when COUNTER operation mode is selected, and ignored in all other operation
modes.
These bits define the event action the counter will perform on an event.
Value
Name
Description
0
OFF
Event action disabled
1
RETRIGGER
Start, restart or retrigger on event
2
Reserved
-
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 870
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.5
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x08
0x00
PAC Write-Protection
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
7
6
Access
Reset
5
MC1
RW
0
4
MC0
RW
0
3
VLC
RW
0
2
DIR
RW
0
1
ERR
RW
0
0
OVF
RW
0
Bits 4, 5 – MCx Channel x Compare Match Disable [x = 1..0]
Writing a '0' to MCx has no effect.
Writing a '1' to MCx will clear the corresponding Match Channel x Interrupt Disable/Enable bit, which disables the
Match Channel x interrupt.
Value
Description
0
The Match Channel x interrupt is disabled.
1
The Match Channel x interrupt is enabled.
Bit 3 – VLC Velocity Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Velocity Interrupt Disable/Enable bit, which disables the Velocity interrupt.
This bit has no effect when COUNTER operation mode is selected.
Value
Description
0
The Velocity interrupt is disabled.
1
The Velocity interrupt is enabled.
Bit 2 – DIR Direction Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Direction Change Interrupt Disable/Enable bit, which disables the Direction
Change interrupt.
This bit has no effect when COUNTER operation mode is selected.
Value
Description
0
The Direction Change interrupt is disabled.
1
The Direction Change interrupt is enabled.
Bit 1 – ERR Error Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Error Interrupt Disable/Enable bit, which disables the Error interrupt.
Value
Description
0
The Error interrupt is disabled.
1
The Error interrupt is enabled.
Bit 0 – OVF Overflow/Underflow Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overflow Interrupt Disable/Enable bit, which disables the Overflow interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 871
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.6
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x09
0x00
PAC Write-Protection
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
7
6
Access
Reset
5
MC1
RW
0
4
MC0
RW
0
3
VLC
RW
0
2
DIR
RW
0
1
ERR
RW
0
0
OVF
RW
0
Bits 4, 5 – MCx Channel x Compare Match Enable [x = 1..0]
Writing a '0' to MCx has no effect.
Writing a '1' to MCx will set the corresponding Match Channel x Interrupt Disable/Enable bit, which enables the Match
Channel x interrupt.
Value
Description
0
The Match Channel x interrupt is disabled.
1
The Match Channel x interrupt is enabled.
Bit 3 – VLC Velocity Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Velocity Interrupt Disable/Enable bit, which enables the Velocity interrupt.
This bit has no effect when COUNTER operation mode is selected.
Value
Description
0
The Velocity interrupt is disabled.
1
The Velocity interrupt is enabled.
Bit 2 – DIR Direction Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Direction Change Interrupt Disable/Enable bit, which enables the Direction Change
interrupt.
This bit has no effect when COUNTER operation mode is selected.
Value
Description
0
The Direction Change interrupt is disabled.
1
The Direction Change interrupt is enabled.
Bit 1 – ERR Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Error Interrupt Disable/Enable bit, which enables the Error interrupt.
Value
Description
0
The Error interrupt is disabled.
1
The Error interrupt is enabled.
Bit 0 – OVF Overflow/Underflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Overflow Interrupt Disable/Enable bit, which enable the Overflow interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 872
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.7
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAG
0x0A
0x00
-
6
Access
Reset
5
MC1
RW
0
4
MC0
RW
0
3
VLC
RW
0
2
DIR
RW
0
1
ERR
RW
0
0
OVF
RW
0
Bits 4, 5 – MCx Channel x Compare Match [x = 1..0]
This flag is set on the next CLK_PDEC_CNT cycle after a match with the compare condition, and will generate
an interrupt request if the corresponding Match Channel x Interrupt Enable bit in the Interrupt Enable Set register
(INTENSET.MCx) is '1'.
Writing a '0' to one of these bits has no effect.
Writing a '1' to one of these bits will clear the corresponding Match Channel x interrupt flag.
Bit 3 – VLC Velocity
This flag is set if a velocity transition occurs, and will generate an interrupt request if the Velocity Interrupt Enable bit
in Interrupt Enable Set register (INTENSET.VLC) is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Velocity transition interrupt flag.
This flag is never set when COUNTER operation mode is selected.
Bit 2 – DIR Direction Change
This flag is set if a direction change occurs, and will generate an interrupt request if the Direction Change Interrupt
Enable bit in Interrupt Enable Set register (INTENSET.DIR) is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Velocity transition interrupt flag.
This flag is never set when COUNTER operation mode is selected.
Bit 1 – ERR Error
This flag is set when an error condition is detected, and will generate an interrupt request if the Error Interrupt Enable
bit in the Interrupt Enable Set register (INTENSET.ERR) is '1'. The error source can be identified by reading the
Status (STATUS) register.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Error interrupt flag.
Bit 0 – OVF Overflow/Underflow
This flag is set on the next CLK_TC_CNT cycle after an overflow condition occurs, and will generate an interrupt
request if the Overflow Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.OVF) is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 873
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.8
Status
Name:
Offset:
Reset:
Property:
STATUS
0x0C
0x0040
Read-Synchronized, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.STATUS must be checked to ensure the STATUS register
synchronization is complete.
Bit
15
14
13
CCBUFV1
R
0
12
CCBUFV0
R
0
11
10
9
FILTERBUFV
R
0
8
PRESCBUFV
R
0
7
DIR
R
0
6
STOP
R
1
5
HERR
RW
0
4
WINERR
RW
0
3
2
MPERR
RW
0
1
IDXERR
RW
0
0
QERR
RW
0
Access
Reset
Bit
Access
Reset
Bits 12, 13 – CCBUFVx Compare Channel x Buffer Valid [x = 1..0]
The bit is set when a new value is written to the corresponding CCBUF register.
The bit is cleared by writing a '1' to the corresponding location or automatically cleared on an UPDATE condition.
Bit 9 – FILTERBUFV Filter Buffer Valid
This bit is set when a new value is written to the PRESCALERBUF register.
The bit is cleared by writing a '1' to the corresponding location or automatically cleared on an UPDATE condition.
This bit is always read '0' when COUNTER operation mode is selected.
Bit 8 – PRESCBUFV Prescaler Buffer Valid
This bit is set when a new value is written to the PRESC register.
The bit is cleared by writing a '1' to the corresponding location or automatically cleared on an UPDATE condition.
Bit 7 – DIR Direction Status Flag
This bit reflects the HALL/QDEC direction.
in COUNTER mode, this bits is always read '0'.
Value
Description
0
Clockwise direction.
1
Counter-clockwise direction.
Bit 6 – STOP Stop
This bit reflects the HALL/QDEC decoding status.
In COUNTER mode, this bits is always read '0'.
Value
Description
0
PDEC/HALL decoding is running.
1
PDEC/HALL decoding is stopped.
Bit 5 – HERR Hall Error Flag
This flag is set when an invalid HALL code is detected.
The flag is cleared by writing a '1' to this bit location. After write to the STATUS register, ensure the
SYNCBUSY.STATUS is '0' before reading.
Outside of HALL mode, this bits is always read '0'.
Bit 4 – WINERR Window Error Flag
This flag is set when the counter is outside the window monitor.
The flag is cleared by writing a '1' to this bit location. After write to the STATUS register, ensure the
SYNCBUSY.STATUS is '0' before reading.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 874
PIC32CM MC00 Family
Position Decoder (PDEC)
Outside of HALL mode, this bits is always read '0'.
Bit 2 – MPERR Missing Pulse Error flag
This flag is set when a missing pulse error condition is detected.
The flag is cleared by writing a '1' to this bit location. After write to the STATUS register, ensure the
SYNCBUSY.STATUS is '0' before reading.
Outside of QDEC mode, this bits is always read '0'.
Bit 1 – IDXERR Index Error Flag
This flag is set when an index error condition is detected.
The flag is cleared by writing a '1' to this bit location. After write to the STATUS register, ensure the
SYNCBUSY.STATUS is '0' before reading.
Outside of QDEC mode, this bits is always read '0'.
Bit 0 – QERR Quadrature Error Flag
This flag is set when an invalid QDEC transition is detected.
The flag is cleared by writing a '1' to this bit location. After write to the STATUS register, ensure the
SYNCBUSY.STATUS is '0' before reading.
Outside of QDEC mode, this bits is always read '0'.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 875
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.9
Debug Control
Name:
Offset:
Reset:
Property:
Bit
DBGCTRL
0x0F
0x00
PAC Write-Protection
7
6
5
4
3
Access
Reset
2
1
0
DBGRUN
RW
0
Bit 0 – DBGRUN Debug Run Mode
This bit is not affected by software reset and should not be changed by software while the PDEC module is enabled.
Value
Description
0
The PDEC module is halted when the device is halted in debug mode.
1
The PDEC module continues normal operation when the device is halted in debug mode.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 876
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.10 Synchronization Status
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x10
0x00000000
Read-Only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
CC1
R
0
7
CC0
R
0
6
COUNT
R
0
5
FILTER
R
0
4
PRESC
R
0
3
STATUS
R
0
2
CTRLB
R
0
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 7, 8 – CC Compare Channel x Synchronization Busy
This bit is cleared when the synchronization of Compare Channel x (CCx) register between the clock domains is
complete.
This bit is set when the synchronization of Compare Channel x (CCx) register between clock domains is started.
Bit 6 – COUNT Count Synchronization Busy
This bit is cleared when the synchronization of Count register between the clock domains is complete.
This bit is set when the synchronization of Count register between clock domains is started.
Bit 5 – FILTER Filter Synchronization Busy
This bit is cleared when the synchronization of Filter register between the clock domains is complete.
This bit is set when the synchronization of Filter register between clock domains is started.
This bit is always read '0' when COUNTER operation mode is selected.
Bit 4 – PRESC Prescaler Synchronization Busy
This bit is cleared when the synchronization of Prescaler register between the clock domains is complete.
This bit is set when the synchronization of Prescaler register between clock domains is started.
Bit 3 – STATUS Status Synchronization Busy
This bit is cleared when the synchronization of Status register between the clock domains is complete.
This bit is set when the synchronization of Status register between clock domains is started.
Bit 2 – CTRLB Control B Synchronization Busy
This bit is cleared when the synchronization of Control B register between the clock domains is complete.
This bit is set when the synchronization of Control B register between clock domains is started.
Bit 1 – ENABLE Enable Synchronization Busy
This bit is cleared when the synchronization of Enable register bit between the clock domains is complete.
This bit is set when the synchronization of Enable register bit between clock domains is started.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 877
PIC32CM MC00 Family
Position Decoder (PDEC)
Bit 0 – SWRST Software Reset Synchronization Busy
This bit is cleared when the synchronization of Software Reset register bit between the clock domains is complete.
This bit is set when the synchronization of Software Reset register bit between clock domains is started.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 878
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.11 Prescaler Value
Name:
Offset:
Reset:
Property:
PRESC
0x14
0x00
Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.PRESC must be checked to ensure the PRESC register
synchronization is complete.
Bit
7
6
5
4
3
2
1
0
RW
0
RW
0
PRESC[3:0]
Access
Reset
RW
0
Bits 3:0 – PRESC[3:0] Prescaler Value
These bits select the GCLK prescaler factor.
Value
Name
0
DIV1
1
DIV2
2
DIV4
3
DIV8
4
DIV16
5
DIV32
6
DIV64
7
DIV128
8
DIV256
9
DIV512
10
DIV1024
© 2021 Microchip Technology Inc.
and its subsidiaries
RW
0
Description
No division
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 128
Divide by 256
Divide by 512
Divide by 1024
Datasheet
DS60001638D-page 879
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.12 Filter Value
Name:
Offset:
Reset:
Property:
FILTER
0x15
0x00
Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.FILTER must be checked to ensure the FILTER register
synchronization is complete.
Bit
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
FILTER[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
Bits 7:0 – FILTER[7:0] Filter Value
These bits select the PDEC inputs filter length.
These bits have no effect when COUNTER operation mode is selected.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 880
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.13 Prescaler Buffer Value
Name:
Offset:
Reset:
Property:
PRESCBUF
0x18
0x00
Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.PRESC must be checked to ensure the PRESC register
synchronization is complete.
Bit
7
6
Access
Reset
5
4
3
RW
0
2
1
PRESCBUF[3:0]
RW
RW
0
0
0
RW
0
Bits 3:0 – PRESCBUF[3:0] Prescaler Buffer Value
These bits hold the value of the prescaler buffer register. The value is copied in the corresponding PRESC register on
UPDATE condition.
Value
Name
Description
0
DIV1
No division
1
DIV2
Divide by 2
2
DIV4
Divide by 4
3
DIV8
Divide by 8
4
DIV16
Divide by 16
5
DIV32
Divide by 32
6
DIV64
Divide by 64
7
DIV128
Divide by 128
8
DIV256
Divide by 256
9
DIV512
Divide by 512
10
DIV1024
Divide by 1024
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 881
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.14 Filter Buffer Value
Name:
Offset:
Reset:
Property:
FILTERBUF
0x19
0x00
Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.FILTER must be checked to ensure the FILTERBUF register
synchronization is complete.
Bit
Access
Reset
7
6
5
RW
0
RW
0
RW
0
4
3
FILTERBUF[7:0]
RW
RW
0
0
2
1
0
RW
0
RW
0
RW
0
Bits 7:0 – FILTERBUF[7:0] Filter Buffer Value
These bits hold the value of the filter buffer register. The value is copied in the corresponding FILTER register on
UPDATE condition.
These bits have no effect when COUNTER operation mode is selected.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 882
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.15 Counter Value
Name:
Offset:
Reset:
Property:
COUNT
0x1C
0x00000000
PAC Write-Protection, Read-Synchronized, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.COUNT must be checked to ensure the COUNT register
synchronization is complete.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Bit
15
14
13
12
10
9
8
Access
Reset
RW
0
RW
0
RW
0
11
COUNT[15:8]
RW
RW
0
0
RW
0
RW
0
RW
0
7
6
5
3
2
1
0
RW
0
RW
0
RW
0
RW
0
Access
Reset
Bit
Access
Reset
Bit
4
COUNT[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
Bits 15:0 – COUNT[15:0] Counter Value
These bits contain the counter value. To read the most updated counter value, the READSYNC software command
must be applied first (CTRLBSET.CMD = READSYNC).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 883
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.16 Channel x Compare Value
Name:
Offset:
Reset:
Property:
CCx
0x20 + x*0x04 [x=0..1]
0x00000000
Read-Synchronized, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCx register
synchronization is complete.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
RW
0
RW
0
RW
0
RW
0
3
2
1
0
RW
0
RW
0
RW
0
RW
0
Access
Reset
Bit
Access
Reset
Bit
CC[15:8]
Access
Reset
Bit
RW
0
RW
0
RW
0
RW
0
7
6
5
4
CC[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
Bits 15:0 – CC[15:0] Channel Compare Value
These bits hold value of the channel x compare register.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 884
PIC32CM MC00 Family
Position Decoder (PDEC)
42.7.17 Channel x Compare Buffer Value
Name:
Offset:
Reset:
Property:
CCBUFx
0x30 + x*0x04 [x=0..1]
0x00000000
Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCBUFx register
synchronization is complete.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Bit
15
14
13
12
10
9
8
Access
Reset
RW
0
RW
0
RW
0
11
CCBUF[15:8]
RW
RW
0
0
RW
0
RW
0
RW
0
7
6
5
3
2
1
0
RW
0
RW
0
RW
0
RW
0
Access
Reset
Bit
Access
Reset
Bit
4
CCBUF[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
Bits 15:0 – CCBUF[15:0] Channel Compare Buffer Value
These bits hold the value of the channel x compare buffer register. The register is used as buffer for the associated
compare register (CCx). Accessing this register using the CPU will affect the corresponding CCBVx status bit
(STATUS.CCBUFVx).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 885
PIC32CM MC00 Family
Electrical Characteristics 85℃
43.
Electrical Characteristics 85℃
Absolute maximum ratings are listed below. Exposure to these maximum rating conditions for extended periods may
affect device reliability. Functional operation of the device at these or any other conditions, above the parameters
indicated in the operation listings of this specification, is not implied.
Table 43-1. Absolute Maximum Ratings (1)
Ambient temperature under bias
-40°C to +85°C
Storage temperature
-60°C to +150°C
Voltage on VDD with respect to GND
-0.3V to +5.8V
Voltage on VDDIO with respect to GND
-0.3V to +5.8V
Voltage on any pin with respect to GND
-0.3V to (VDD/VDDIO+0.3V)
Voltage on VREFA with respect to VDDANA
VDDANA-0.6V
Voltage on VREFB with respect to VDDANA
VDDANA-0.6V
Maximum total current out of all GND pins
129 mA
Maximum total current into all VDDIN, VDDANA, and VDDIOx pins (Note2)
129 mA
Maximum output current sourced/sunk by any Low-Current Mode I/O pin
10 mA
Maximum output current sourced/sunk by any High- Current Mode I/O pin
20 mA
Maximum current sunk by all ports
129 mA
Maximum current sourced by all ports (Note 2)
129 mA
Maximum Junction Temperature
+105°C
Human Body Model (HBM) per JESD22-A114
2000 V
Charged Device Model (CDM) (ANSI/ESD STM 5.3.1) (All pins/Corner pins)
500 V/750 V
Notes:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions, above those
indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
2. Maximum allowable current is a function of device maximum power dissipation.
43.1
Operating Frequencies and Thermal Limitations
Table 43-2. Operating Frequency vs. Voltage
Param. No.
DC_5
VDDIO, VDDIN, VDDANA Range
2.7 to
5.5V(1,2,3)
Temp. Range (in °C)
-40°C to +85°C
Max CPU Frequency
48 Mhz
Comments
Industrial
Notes:
1. With BODVDD disabled.
2. The same voltage must be applied to VDDIN and VDDANA. This common voltage is referred to as VDD in the
data sheet. VDDIO should be lower or equal to VDD = VDDIN = VDDANA.
3. Some I/Os are in the VDDIO cluster, but can be multiplexed as analog functions (inputs or outputs). In such
a case, VDDANA is used to power the I/O. Using this configuration may result in an electrical conflict if the
VDDIO voltage is lower than VDD = VDDIN = VDDANA.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS60001638D-page 886
PIC32CM MC00 Family
Electrical Characteristics 85℃
Table 43-3. Thermal Operating Conditions
Rating
Symbol Min. Typ. Max. Unit
Operating Ambient Temperature Range
TA
-40
—
85
°C
Operating Junction Temperature Range
TJ
—
—
(1)
°C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = (VDDIOx x (IDD - Σ IOH)) + (VDDCORE x IDDCORE) + (VUSB3V3 x
IDDUSB) + (VDDANA * VDDANA_IDD) + (VDDREG x IDDREG)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/θJA
W
I/O Pin Power Dissipation:
PI/O = Σ(({VDD -VOH} x IOH) + Σ (VOL x IOL))
Maximum Allowed Power Dissipation
Note:
1. See Absolute Maximum Ratings.
Table 43-4. Thermal Packaging Characteristics
Characteristics
Symbol
Typ.
Max.
Unit
Thermal Resistance, 32-pin TQFP (7x7x1 mm) Package
θJA
63.1
—
°C/W
Thermal Resistance, 48-pin TQFP (7x7x1 mm) Package
θJA
62.7
—
°C/W
Thermal Resistance, 32-pin VQFN (5x5x0.9 mm) Package
θJA
40.5
—
°C/W
Thermal Resistance, 48-pin VQFN (7x7x0.9 mm) Package
θJA
30.9
—
°C/W
Comments
Note (1)
Note:
1. Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.
43.2
Power Supply
Table 43-5. Power Supply Electrical Specifications
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise
stated)
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
DC CHARACTERISTICS
Param. No.
Symbol
Characteristics
Min.
Typical
Max.
Units
Conditions
0.8
1
1.2
µF
Bulk Ceramic or solid
Tantalum with ESR
