PIC32MK GENERAL PURPOSE AND
MOTOR CONTROL (GPG/MCJ)
WITH CAN FD FAMILY
32-bit General Purpose and Motor Control Application MCUs with
CAN FD, FPU, ECC Flash, and up to 512 KB Flash, 64 KB SRAM, and
Op amps
Operating Conditions: 2.3V to 3.6V
Security Features
• -40ºC to +85ºC, DC to 120 MHz
• -40ºC to +125ºC, DC to 80 MHz
• Advanced Memory Protection:
- Peripheral and memory region access control
Core: 120 MHz (up to 198 DMIPS)
Advanced Analog Features
• MIPS32® microAptiv™ MCU core with Floating Point Unit
• microMIPS™ mode for up to 40% smaller code size
• DSP-enhanced core:
- Four 64-bit accumulators
- Single-cycle MAC, saturating and fractional math
• Code-efficient (C and Assembly) architecture
• Two 32-bit core register files to reduce interrupt latency
• 12-bit ADC module:
- Sum of all individual ADCs combined, 25.45 Msps 12-bit
mode or 33.79 Msps 8-bit mode
- 7 individual ADC modules
- 3.75 Msps per S&H with dedicated DMA
- Up to 30 analog inputs
• Flexible and independent ADC trigger sources
• Four high bandwidth op-amps and five comparators
• Up to two 12-bit CDACs
• Internal temperature sensor ±2ºC accuracy
• Capacitive Touch Divider (CVD)
Clock Management
• 8 MHz ±4% (FRC) internal oscillator -40ºC to +85ºC
• Programmable PLLs and oscillator clock sources:
- HS and EC clock modes
• 32 kHz Internal Low-power RC oscillator (LPRC)
• Independent external low-power 32 kHz crystal oscillator
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timers (WDT) and Deadman Timer
(DMT)
• Fast wake-up and start-up
• Four Fractional clock out (REFCLKO) modules
Power Management
• Low-power management modes (Sleep, and Idle)
• Integrated:
- Power-on Reset (POR) and Brown-out Reset (BOR)
- Programmable High/Low Voltage Detect (HLVD)
• On-board capacitorless regulator
Motor Control PWM
•
•
•
•
•
•
•
Up to nine PWM pairs
Leading-edge and Trailing-edge blanking
Dead Time for rising and falling edges
Dead Time Compensation
8.33 ns PWM Resolution
Clock Chopping for High-Frequency Operation
PWM Support for:
- DC/DC, AC/DC, inverters, PFC, lighting
- BLDC, PMSM, ACIM, SRM motors
• Choice of 10 Fault and 9 Current Limit Inputs
• Flexible Trigger Configuration for ADC Triggering
Motor Encoder Interface
• Three Quadrature Encoder Interface (QEI) modules:
- Four inputs: Phase A, Phase B, Home, and Index
Audio/Graphics/Touch Interfaces
• Up to two I2S audio data communication interfaces
• Up to two SPI control interfaces
• Programmable master clock:
- Generation of fractional clock frequencies
- Can be tuned in run-time
Unique Features
• Permanent non-volatile 4-word unique device serial number
• Flash Error Code Correction (ECC)
Direct Memory Access (DMA)
• Up to eight channels with automatic data size detection
• Programmable Cyclic Redundancy Check (CRC)
• Up to 64 KB transfers
2019-2020 Microchip Technology Inc.
Communication Interfaces
• CAN Flexible Data-Rate (CAN FD) module (with dedicated DMA
channels):
- 2.0B Active with DeviceNet™ addressing support
- ISO 11898-1:2015 compliant
• Up to two UART modules (up to 25 Mbps):
- Supports LIN 2.1 and IrDA® protocols
• Two SPI/I2S modules (SPI 50 Mbps)
• Two I2C modules (up to 1 Mbaud) with SMBus support
• Peripheral Pin Select (PPS) to enable remappable pin functions
Timers/Output Compare/Input Capture/RTCC
• Up to nine 16-bit or one 16-bit and eight 32-bit timers/counters
for GP and MC devices and two additional QEI 32-bit timers for
MC devices
• 9 Output Compare (OC) modules
• 9 Input Capture (IC) modules
• PPS to enable function remap
• Real-Time Clock and Calendar (RTCC) module
Input/Output
•
•
•
•
5V-tolerant pins with up to 22 mA source/sink
Selectable internal open drain, pull-ups, and pull-downs
External interrupts on all I/O pins
Five programmable edge/level-triggered interrupt pins
Qualification and Class B Support
•
•
•
•
Class B Safety Library, IEC 60730 (planned)
Back-up internal oscillator
Clock monitor with back-up internal oscillator
Global register locking
Debugger Development Support
•
•
•
•
•
In-circuit and in-application programming
2-wire or 4-wire MIPS® Enhanced JTAG interface
Unlimited software and 12 complex breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Non-intrusive hardware-based instruction trace
Software and Tools Support
•
•
•
•
•
C/C++ compiler with native DSP/fractional support
MPLAB® Harmony Integrated Software Framework
TCP/IP, Graphics, and mTouch™ middleware
MFi, Android™ and Bluetooth® audio frameworks
RTOS Kernels: Express Logic ThreadX, FreeRTOS™,
OPENRTOS®, Micriµm® µC/OS™, and SEGGER embOS®
DS60001570C -page 1
PIC32MK GPG/MCJ with CAN FD Family
Packages
Type
VQFN
QFN
TQFP
Pin Count
48
64
48
64
I/O Pins (up to)
37
53
37
53
Contact/Lead Pitch
0.4 mm
0.50 mm
0.5 mm
0.50 mm
Dimensions
6 x 6 x 0.9 mm
9 x 9 x 1 mm
7 x 7 x 0.9 mm
10 x 10 x 1 mm
DS60001570C-page 2
2019-2020 Microchip Technology Inc.
Program Memory
Data Memory
Floating Point Unit (FPU)
Pins
Packages
Boot Flash Memory
Timers/Capture/Compare(1)
UART
SPI/I2S
External Interrupts(2)
Motor Control PWM Pairs
QEI (Quadrature Encoder)
CAN FD 2.0B
DMA Channels w/CRC Programmable/Dedicated
(Programmable/Dedicated)
Independent ADC Modules
ADC Channels
Op Amp/Comparator
I2C
RTCC
REFCLK
CDAC (Control DAC)
CTMU
CLC (Configurable Logic Cell)
HLVD
I/O Pins
JTAG/ICSP
Trace
PIC32MK MOTOR CONTROL AND GENERAL PURPOSE (MC AND GP) FAMILY FEATURES
PIC32MK0512MCJ064
512K
64K
Y
64
64
TQFP
UQFN
16
9/9/9
2
2/2
5
9
3
1
8/2
7
30
4/5
2
Y
4
2
1
4
1
53
Y
Y
PIC32MK0512MCJ048
512K
64K
Y
48
48
TQFP
VQFN
16
9/9/9
2
2/2
5
6
3
1
8/2
7
18
4/5
2
Y
4
2
1
4
1
37
Y
N
PIC32MK0256MCJ064
256K
64K
Y
64
64
TQFP
UQFN
16
9/9/9
2
2/2
5
9
3
1
8/2
7
30
4/5
2
Y
4
2
1
4
1
53
Y
Y
PIC32MK0256MCJ048
256K
64K
Y
48
48
TQFP
VQFN
16
9/9/9
2
2/2
5
6
3
1
8/2
7
18
4/5
2
Y
4
2
1
4
1
37
Y
N
PIC32MK0512GPG064
512K
64K
Y
64
64
TQFP
UQFN
16
9/9/9
2
2/2
5
0
0
0
8/1
7
30
4/5
2
Y
4
2
1
4
1
53
Y
Y
PIC32MK0512GPG048
512K
64K
Y
48
48
TQFP
VQFN
16
9/9/9
2
2/2
5
0
0
0
8/1
7
18
4/5
2
Y
4
2
1
4
1
37
Y
N
PIC32MK0256GPG064
256K
64K
Y
64
64
TQFP
UQFN
16
9/9/9
2
2/2
5
0
0
0
8/1
7
30
4/5
2
Y
4
2
1
4
1
53
Y
Y
PIC32MK0256GPG048
256K
64K
Y
48
48
TQFP
VQFN
16
9/9/9
2
2/2
5
0
0
0
8/1
7
18
4/5
2
Y
4
2
1
4
1
37
Y
N
Device
Remappable Pin Functions
Note
1:
2:
Eight out of nine timers are remappable.
Four out of five external interrupts are remappable.
DS60001570C-page 3
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 1:
PIC32MK GPG/MCJ with CAN FD Family
Device Pin Tables
TABLE 2:
PIN NAMES FOR 64-PIN GENERAL PURPOSE (GPG) DEVICES
64-PIN QFN(4) AND TQFP (TOP VIEW)
PIC32MK0512GPG064
PIC32MK0256GPG064
64
QFN
Pin #
Full Pin Name
(4)
64
1
TQFP
Pin #
1
Full Pin Name
1
TCK/RPA7/RA7
33
2
RPB14/RB14
34
AN40/CVD40/RPE0/RE0
3
RPB15/RB15
35
AN41/CVD41/RPE1/RE1
4
AN19/CVD19/RPG6/RG6
36
AN46/CVD46/RPA14/RA14
5
AN18/CVD18/RPG7/RG7
37
AN47/CVD47/RPA15/RA15
6
AN17/CVD17/RPG8/RG8
38
VDD
7
MCLR#
39
OSCI/CLKI/AN49/CVD49/RPC12/RC12
8
AN16/CVD16/RPG9/RG9
40
OSCO/CLKO/RPC15/RC15
9
VSS
41
VSS
10
VDD
42
RD8
11
AN10/CVD10/RPA12/RA12
43
PGD2/RPB5/SDA1/RB5
12
AN9/CVD9/RPA11/RA11
44
PGC2/RPB6/SCL1/RB6
13
OA2OUT/AN0/C2IN4-/C4IN3-/RPA0/RA0
45
DAC1/AN48/CVD48/RPC10/RC10
14
OA2IN+/AN1/C2IN1+/RPA1/RA1
46
OA5OUT/AN25/CVD25/C5IN4-/RPB7/SCK1/INT0/RB7
15
PGD3/VREF-/OA2IN-/AN2/C2IN1-/RPB0/CTED2/RB0
47
SOSCI/RPC13(5)/RC13(5)
16
PGC3/OA1OUT/VREF+/AN3/C1IN4-/C4IN2-/RPB1/CTED1/RB1
48
SOSCO/RPB8(5)/T1CK(5)/RB8(5)
17
PGC1/OA1IN+/AN4/C1IN1+/C1IN3-/C2IN3-/RPB2/RB2
49
TMS/OA5IN-/AN27/CVD27/LVDIN/C5IN1-/RPB9/RB9
18
PGD1/OA1IN-/AN5/CTCMP/C1IN1-/RTCC/RPB3/RB3
50
TRCLK/RPC6/RC6
19
AVDD
51
TRD0/RPC7/RC7
20
AVSS
52
TRD1/RPC8/RC8
21
OA3OUT/AN6/CVD6/C3IN4-/C4IN1+/C4IN4-/RPC0/RC0
53
TRD2/RPD5/RD5
22
OA3IN-/AN7/CVD7/C3IN1-/C4IN1-/RPC1/RC1
54
TRD3/RPD6/RD6
23
OA3IN+/AN8/CVD8/C3IN1+/C3IN3-/RPC2/RC2
55
RPC9/RC9
24
AN11/CVD11/C1IN2-/RC11
56
VSS
25
VSS
57
VDD
26
VDD
58
RPF0/RF0
27
AN12/CVD12/C2IN2-/C5IN2-/RE12
59
RPF1/RF1
28
AN13/CVD13/C3IN2-/RE13
60
RPB10/RB10
29
AN14/CVD14/RPE14/RE14
61
RPB11/RB11
30
AN15/CVD15/RPE15/RE15
62
RPB12/RB12
31
TDI/DAC2/AN26/CVD26/RPA8/SDA2/RA8
63
RPB13/CTPLS/RB13
32
RPB4/SCL2/RB4
64
TDO/RA10
Note
1:
2:
3:
4:
5:
OA5IN+/AN24/CVD24/C5IN1+/C5IN3-/RPA4/RA4
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and 10.3 “Peripheral Pin Select
(PPS)” for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See 10.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
The metal heat sink pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS
externally.
Functions are restricted to input functions only and inputs will be slower than the standard inputs. Change notification interrupt is
not available on this pin.
DS60001570C-page 4
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 3:
PIN NAMES FOR 64-PIN MOTOR CONTROL (MCJ) DEVICES
64-PIN QFN(4) AND TQFP (TOP VIEW)
PIC32MK0512MCJ064
PIC32MK0256MCJ064
64
QFN
Pin #
Full Pin Name
(4)
64
1
Pin #
TQFP
1
Full Pin Name
1
TCK/RPA7/PWM4L/RA7
33
OA5IN+/AN24/CVD24/C5IN1+/C5IN3-/RPA4/RA4
2
RPB14/PWM1H/RB14
34
AN40/CVD40/RPE0/RE0
3
RPB15/PWM1L/RB15
35
AN41/CVD41/RPE1/RE1
4
AN19/CVD19/RPG6/PWM7L/RG6
36
AN46/CVD46/RPA14/RA14
5
AN18/CVD18/RPG7/PWM7H/RG7
37
AN47/CVD47/RPA15/RA15
6
AN17/CVD17/RPG8/RG8
38
VDD
7
MCLR#
39
OSCI/CLKI/AN49/CVD49/RPC12/RC12
8
AN16/CVD16/RPG9/FLT12/RG9
40
OSCO/CLKO/RPC15/RC15
9
VSS
41
VSS
10
VDD
42
RD8
11
AN10/CVD10/RPA12/FLT13/RA12
43
PGD2/RPB5/SDA1/RB5
12
AN9/CVD9/RPA11/FLT14/RA11
44
PGC2/RPB6/SCL1/RB6
13
OA2OUT/AN0/C2IN4-/C4IN3-/RPA0/RA0
45
DAC1/AN48/CVD48/RPC10/RC10
14
OA2IN+/AN1/C2IN1+/RPA1/RA1
46
OA5OUT/AN25/CVD25/C5IN4-/RPB7/SCK1/INT0/RB7
15
PGD3/VREF-/OA2IN-/AN2/C2IN1-/RPB0/CTED2/RB0
47
SOSCI/RPC13(5)/RC13(5)
16
PGC3/OA1OUT/VREF+/AN3/C1IN4-/C4IN2-/RPB1/CTED1/RB1
48
SOSCO/RPB8(5)/T1CK(5)/RB8(5)
17
PGC1/OA1IN+/AN4/C1IN1+/C1IN3-/C2IN3-/RPB2/RB2
49
TMS/OA5IN-/AN27/CVD27/LVDIN/C5IN1-/RPB9/RB9
18
PGD1/OA1IN-/AN5/CTCMP/C1IN1-/RTCC/RPB3/RB3
50
TRCLK/RPC6/PWM6H/RC6
19
AVDD
51
TRD0/RPC7/PWM6L/RC7
20
AVSS
52
TRD1/RPC8/PWM5H/RC8
21
OA3OUT/AN6/CVD6/C3IN4-/C4IN1+/C4IN4-/RPC0/RC0
53
TRD2/RPD5/PWM9H/RD5
22
OA3IN-/AN7/CVD7/C3IN1-/C4IN1-/RPC1/RC1
54
TRD3/RPD6/PWM9L/RD6
23
OA3IN+/AN8/CVD8/C3IN1+/C3IN3-/RPC2/FLT3/RC2
55
RPC9/PWM5L/RC9
24
AN11/CVD11/C1IN2-/FLT4/RC11
56
VSS
25
VSS
57
VDD
26
VDD
58
RPF0/PWM8H/RF0
27
AN12/CVD12/C2IN2-/C5IN2-/FLT5/RE12
59
RPF1/PWM8L/RF1
28
AN13/CVD13/C3IN2-/FLT6/RE13
60
RPB10/PWM3H/RB10
29
AN14/CVD14/RPE14/FLT7/RE14
61
RPB11/PWM3L/RB11
30
AN15/CVD15/RPE15/FLT8/RE15
62
RPB12/PWM2H/RB12
31
TDI/DAC2/AN26/CVD26/RPA8/SDA2/RA8
63
RPB13/PWM2L/CTPLS/RB13
32
FLT15/RPB4/SCL2/RB4
64
TDO/PWM4H/RA10
Note
1:
2:
3:
4:
5:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and 10.3 “Peripheral Pin Select (PPS)”
for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin. See 10.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
The metal heat sink pad on the bottom of the QFN device is not connected to any pins and is recommended to be connected to VSS
externally.
Functions are restricted to input functions only and inputs will be slower than standard inputs. Change notification interrupt is not available on this pin.
2019-2020 Microchip Technology Inc.
DS60001570C-page 5
PIC32MK GPG/MCJ with CAN FD Family
TABLE 4:
PIN NAMES FOR 48-PIN GENERAL PURPOSE (GPG) DEVICES
48-PIN VQFN(4) AND TQFP (TOP VIEW)
M
PIC32MK0512GPG048
PIC32MK0256GPG048
48
48
1
TQFP
1
VQFN (4)
Pin #
Full Pin Name
Pin #
TCK / RPA7 / RA7
2
RPB14 / RB14
26
VDD
3
RPB15 / RB15
27
OSCI/CLKI / AN49 / CVD49 / RPC12 / RC12
4
MCLR#
28
OSCO / CLKO / RPC15 / RC15
5
VSS
29
VSS
6
VDD
30
RD8
7
AN10 / CVD10 / RPA12 / RA12
31
PGD2 / RPB5 / SDA1 / RB5
8
AN9 / CVD9 / RPA11 / RA11
32
PGC2 / RPB6 / SCL1 / RB6
9
OA2OUT / AN0 / C2IN4- / C4IN3- / RPA0 / RA0
33
DAC1 / AN48 / CVD48 / RPC10 / RC10
10
OA2IN+ / AN1 / C2IN1+ / RPA1 / RA1
34
OA5OUT / AN25 / CVD25 / C5IN4- / RPB7 / SCK1 / INT0 / RB7
11
PGD3 / VREF- / OA2IN- / AN2 / C2IN1- / RPB0 / CTED2 / RB0
35
SOSCI/RPC13(5)/RC13(5)
12
PGC3 / OA1OUT / VREF+ / AN3 / C1IN4- / C4IN2- / RPB1 /
CTED1 / RB1
36
SOSCO/RPB8(5)/T1CK(5)/RB8(5)
13
PGC1 / OA1IN+ / AN4 / C1IN1+ / C1IN3- / C2IN3- / RPB2 / RB2
37
TMS / OA5IN- / AN27 / CVD27 / LVDIN / C5IN1- / RPB9 / RB9
14
PGD1 / OA1IN- / AN5 / CTCMP / C1IN1- / RTCC / RPB3 / RB3
38
RPC6 / RC6
15
AVDD
39
RPC7 / RC7
16
AVSS
40
RPC8 / RC8
17
OA3OUT / AN6 / CVD6 / C3IN4- / C4IN1+ / C4IN4- / RPC0 / RC0
41
RPC9 / RC9
18
OA3IN- / AN7 / CVD7 / C3IN1- / C4IN1- / RPC1 / RC1
42
VSS
19
OA3IN+ / AN8 / CVD8 / C3IN1+ / C3IN3- / RPC2 / RC2
43
VDD
20
AN11 / CVD11 / C1IN2- / RC11
44
RPB10 / RB10
21
VSS
45
RPB11 / RB11
22
VDD
46
RPB12 / RB12
23
TDI / DAC2 / AN26 / CVD26 / RPA8 / SDA2 / RA8
47
RPB13 / CTPLS / RB13
24
RPB4 / SCL2 / RB4
48
TDO / RA10
Note
1:
2:
3:
4:
5:
25
Full Pin Name
1
OA5IN+ / AN24 / CVD24 / C5IN1+ / C5IN3- / RPA4 / RA4
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and 10.3 “Peripheral Pin Select (PPS)”
for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification interrupt pin. See 10.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
The metal heat sink pad on the bottom of the QFN device is not connected to any pins and is recommended to be connected to VSS
externally.
Functions are restricted to input functions only and inputs will be slower than standard inputs. Change notification interrupt is not available
on this pin.
DS60001570C-page 6
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 5:
PIN NAMES FOR 48-PIN MOTOR CONTROL (MCJ) DEVICES
48-PIN VQFN(4) AND TQFP (TOP VIEW)
M
PIC32MK0512MCJ048
PIC32MK0256MCJ048
48
48
VQFN (4)
Pin #
Full Pin Name
TQFP
1
Pin #
1
Full Pin Name
1
TCK / RPA7 / PWM4L / RA7
25
OA5IN+ / AN24 / CVD24 / C5IN1+ / C5IN3- / RPA4 / RA4
2
RPB14 / PWM1H / RB14
26
VDD
3
RPB15 / PWM1L / RB15
27
OSCI / CLKI / AN49 / CVD49 / RPC12 / RC12'
4
MCLR#
28
OSCO / CLKO / RPC15 / RC15
5
VSS
29
VSS
6
VDD
30
RD8
7
AN10 / CVD10 / RPA12 / FLT13 / RA12
31
PGD2 / RPB5 / SDA1 / RB5
8
AN9 / CVD9 / RPA11 / FLT14 / RA11
32
PGC2 / RPB6 / SCL1 / RB6
9
OA2OUT / AN0 / C2IN4- / C4IN3- / RPA0 / RA0
33
DAC1 / AN48 / CVD48 / RPC10 / RC10
10
OA2IN+ / AN1 / C2IN1+ / RPA1 / RA1
34
OA5OUT / AN25 / CVD25 / C5IN4- / RPB7 / SCK1 / INT0 / RB7
11
PGD3 / VREF- / OA2IN- / AN2 / C2IN1- / RPB0 / CTED2 / RB0
35
SOSCI / RPC13(5) / RC13(5)
12
PGC3 / OA1OUT / VREF+ / AN3 / C1IN4- / C4IN2- / RPB1 /
CTED1 / RB1
36
SOSCO / RPB8(5) /T1CK(5) / RB8(5)
13
PGC1 / OA1IN+ / AN4 / C1IN1+ / C1IN3- / C2IN3- / RPB2 / RB2
37
TMS / OA5IN- / AN27 / CVD27 / LVDIN / C5IN1- / RPB9 / RB9
14
PGD1 / OA1IN- / AN5 / CTCMP / C1IN1- / RTCC / RPB3 / RB3
38
RPC6 / PWM6H / RC6
15
AVDD
39
RPC7 / PWM6L / RC7
16
AVSS
40
RPC8 / PWM5H / RC8
17
OA3OUT / AN6 / CVD6 / C3IN4- / C4IN1+ / C4IN4- / RPC0 / RC0
41
RPC9 / PWM5L / RC9
18
OA3IN- / AN7 / CVD7 / C3IN1- / C4IN1- / RPC1 / RC1
42
VSS
19
OA3IN+ / AN8 / CVD8 / C3IN1+ / C3IN3- / RPC2 / FLT3 / RC2
43
VDD
20
AN11 / CVD11 / C1IN2- / FLT4 / RC11
44
RPB10 / PWM3H / RB10
21
VSS
45
RPB11 / PWM3L / RB11
22
VDD
46
RPB12 / PWM2H / RB12
23
TDI / DAC2 / AN26 / CVD26 / RPA8 / SDA2 / RA8
47
RPB13 / PWM2L / CTPLS / RB13
24
FLT15 / RPB4 / SCL2 / RB4
48
TDO / PWM4H / RA10
Note
1:
2:
3:
4:
5:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and 10.3 “Peripheral Pin Select (PPS)”
for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification interrupt pin. See 10.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
The metal heat sink pad on the bottom of the QFN device is not connected to any pins and is recommended to be connected to VSS
externally.
Functions are restricted to input functions only and inputs will be slower than standard inputs. Change notification interrupt is not available
on this pin.
2019-2020 Microchip Technology Inc.
DS60001570C-page 7
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 8
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 8
2.0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................ 26
3.0 CPU............................................................................................................................................................................................ 37
4.0 Memory Organization ................................................................................................................................................................. 59
5.0 Flash Program Memory.............................................................................................................................................................. 81
6.0 Resets ........................................................................................................................................................................................ 92
7.0 CPU Exceptions and Interrupt Controller ................................................................................................................................. 100
8.0 Oscillator Configuration ............................................................................................................................................................ 140
9.0 Prefetch Module ....................................................................................................................................................................... 158
10.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 164
11.0 I/O Ports ................................................................................................................................................................................... 192
12.0 Timer1 ...................................................................................................................................................................................... 224
13.0 Timer2 Through Timer9............................................................................................................................................................ 230
14.0 Deadman Timer (DMT) ............................................................................................................................................................ 236
15.0 Watchdog Timer (WDT) ........................................................................................................................................................... 244
16.0 Input Capture............................................................................................................................................................................ 248
17.0 Output Compare....................................................................................................................................................................... 253
18.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I2S)....................................................................................................... 257
19.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 267
20.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 275
21.0 Configurable Logic Cell (CLC).................................................................................................................................................. 287
22.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 301
23.0 12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC)......................................... 311
24.0 Controller Area Network with Flexible Data-rate (CAN FD) ..................................................................................................... 388
25.0 Op Amp/Comparator Module ................................................................................................................................................... 451
26.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 480
27.0 Control Digital-to-Analog Converter (CDAC)............................................................................................................................ 486
28.0 Quadrature Encoder Interface (QEI) ........................................................................................................................................ 489
29.0 Motor Control PWM Module ..................................................................................................................................................... 505
30.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 554
31.0 Power-Saving Features ........................................................................................................................................................... 558
32.0 Special Features ...................................................................................................................................................................... 565
33.0 Instruction Set .......................................................................................................................................................................... 588
34.0 Migration Guide ........................................................................................................................................................................ 586
35.0 Development Support............................................................................................................................................................... 591
36.0 Electrical Characteristics .......................................................................................................................................................... 595
37.0 AC and DC Characteristics Graphs.......................................................................................................................................... 652
38.0 Packaging Information.............................................................................................................................................................. 654
Product Identification System ............................................................................................................................................................ 667
The Microchip Web Site ..................................................................................................................................................................... 674
Customer Change Notification Service .............................................................................................................................................. 674
Customer Support .............................................................................................................................................................................. 674
2019-2020 Microchip Technology Inc.
DS60001570C-page 9
PIC32MK GPG/MCJ with CAN FD Family
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS60001570C-page 10
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
1.0
Note:
DEVICE OVERVIEW
This data sheet summarizes the
features of the PIC32MK GPG/MCJ with
CAN FD Family of devices. It is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
the
documents
listed
in
the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
This data sheet contains device-specific information for
PIC32MK GPG/MCJ with CAN FD Family of devices.
Figure 1-1 illustrates a general block diagram of the
core and peripheral modules in the PIC32MK GPG/
MCJ with CAN FD Family of devices.
Table 1-21 through Table 1-22 list the pinout I/O
descriptions for the pins shown in the device pin tables
(see Table 2 and Table 4).
2019-2020 Microchip Technology Inc.
DS60001570C-page 11
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 1-1:
PIC32MK GPG/MCJ WITH CAN FD FAMILY BLOCK DIAGRAM
VDD
OSC2/CLKO
OSC1/CLKI
VDD
DIVIDERS
RTCC
CRU
SYSCLK
FSCM
PBCLK
PORTG
PORTF
Watchdog
Timer
Timing
Generation
JTAG
BSCAN
MCLR
Power-on
Reset
Precision
Band Gap
Reference
PLL
LPRC
Oscillator
VDD,VSS
Oscillator
Start-up Timer
Voltage
Regulator
FRC
Oscillators
Secondary
Oscillator
SOSOC
Power-up
Timer
OSC
Oscillators
PORTE
PORTD
Brown-out
Reset
PORTC
Dead Man
Timer
PORTA
PORTB
INT
MIPS32®
microAptiv™ MCU
Core with FPU
CAN1
EJTAG
ADC0-5, 7 SAR
EVIC
DMAC
8-ch.
PB5
DS
IS
I10
I2
I1
I3
T7
I7
Sonics - Shared Link
Sonics Dedicated Link
T1 T2 T3
I5
T10
T11
I4
Tn = Target Interface Number
I6
PB4
T4
In = Initiator Interface Number
T5
T8
T14
ICD
PB1
CFG
PPS
WDT
Flash
Controller
Flash
Prefetch
Cache
128
PB2
SRAM1
128
PB6
SRAM2
DSCON
9-Channel
Motor Control
PWM
RTCC
PFM Flash Wrapper
OC1-OC9
128-bit Wide
Panel
Flash Memory
Timer1TImer9
IC1-IC9
SPI1-SPI2
DMT
DFM Flash Wrapper
CRU
16K
33-bit Wide
Flash Memory
I2C1- I2C2
CTMU plus
Temperature
Sensor
Comparator
1-5
UART1-2
12-bit CDAC1
12-bit CDAC2
QEI1-QEI3
Op amp 1-4
CLC1-4
.
DS60001570C-page 12
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 1-1:
PORTA THROUGH PORTG REMAPPABLE PERIPHERAL DESCRIPTIONS
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
I/O
ST
Description
PORT A
RPA0
13
9
RPA1
14
10
I/O
ST
25
I/O
ST
RPA4
33
RPA7
1
1
I/O
ST
RPA8
31
23
I/O
ST
ST
ST
RPA11
12
8
I/O
RPA12
11
7
I/O
RPA14
36
—
I/O
ST
RPA15
37
—
I/O
ST
ST
ST
Remappable PORTA Peripheral Functions
PORT B
RPB0
15
11
I/O
RPB1
16
12
I/O
RPB2
17
13
I/O
ST
RPB3
18
14
I/O
ST
RPB4
32
24
I/O
ST
I/O
ST
RPB5
43
31
RPB6
44
32
I/O
ST
RPB7
46
34
I/O
ST
RPB8
48
36
I/O
ST
RPB9
49
37
I/O
ST
I/O
ST
RPB10
60
44
RPB11
61
45
I/O
ST
RPB12
62
46
I/O
ST
RPB13
63
47
I/O
ST
ST
RPB14
2
2
I/O
RPB15
3
3
I/O
ST
RPC0
21
17
I/O
ST
RPC1
22
18
I/O
ST
19
I/O
ST
Remappable PORTB Peripheral Functions
PORT C
RPC2
23
RPC6
50
38
I/O
ST
RPC7
51
39
I/O
ST
RPC8
52
40
I/O
ST
ST
ST
RPC9
55
41
I/O
RPC10
45
33
I/O
RPC12
39
27
I/O
ST
RPC13
47
35
I/O
ST
RPC15
40
28
I/O
ST
Remappable PORTC Peripheral Functions
PORT D
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
Note 1: Only Available on “MC” variants.
2019-2020 Microchip Technology Inc.
DS60001570C-page 13
PIC32MK GPG/MCJ with CAN FD Family
TABLE 1-1:
PORTA THROUGH PORTG REMAPPABLE PERIPHERAL DESCRIPTIONS
(CONTINUED) (CONTINUED)
Pin Number
Pin Name
RPD5
Pin
Type
Buffer
Type
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
53
—
I/O
ST
ST
ST
RPD6
54
—
I/O
RPE0
34
—
I/O
RPE1
35
—
I/O
ST
ST
Description
Remappable PORTD Peripheral Functions
PORT E
RPE14
29
—
I/O
RPE15
30
—
I/O
ST
RPF0
58
—
I/O
ST
RPF1
59
—
I/O
ST
ST
Remappable PORTE Peripheral Functions
PORT F
Remappable PORTF Peripheral Functions
PORT G
RPG6
4
—
I/O
RPG7
5
—
I/O
ST
RPG8
6
—
I/O
ST
RPG9
Legend:
I/O
ST
8
—
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
Remappable PORTG Peripheral Functions
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
Note 1: Only Available on “MC” variants.
DS60001570C-page 14
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 1-2:
PORTA THROUGH PORT G PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
64-pin
TQFP/QFN
48-Pin
TQFP/
VQFN
Pin Buffer
Type Type
Description
PORT A
RA0
13
9
I/O
ST
RA1
14
10
I/O
ST
RA4
33
25
I/O
ST
RA7
1
1
I/O
ST
RA8
31
23
I/O
ST
RA10
64
48
I/O
ST
RA11
12
8
I/O
ST
RA12
11
7
I/O
ST
RA14
36
---
I/O
ST
RA15
37
---
I/O
ST
RB0
15
11
I/O
ST
RB1
16
12
I/O
ST
RB2
17
13
I/O
ST
RB3
18
14
I/O
ST
RB4
32
24
I/O
ST
RB5
43
31
I/O
ST
RB6
44
32
I/O
ST
RB7
46
34
I/O
ST
RB8
48
36
I/O
ST
PORTA is a bidirectional I/O port
PORT B
RB9
49
37
I/O
ST
RB10
60
44
I/O
ST
RB11
61
45
I/O
ST
RB12
62
46
I/O
ST
RB13
63
47
I/O
ST
RB14
2
2
I/O
ST
RB15
3
3
I/O
ST
PORTB is a bidirectional I/O port
PORT C
2019-2020 Microchip Technology Inc.
DS60001570C-page 15
PIC32MK GPG/MCJ with CAN FD Family
TABLE 1-2:
PORTA THROUGH PORT G PINOUT I/O DESCRIPTIONS (CONTINUED)
RC0
21
17
I/O
ST
RC1
22
18
I/O
ST
RC2
23
19
I/O
ST
RC6
50
38
I/O
ST
RC7
51
39
I/O
ST
RC8
52
40
I/O
ST
RC9
55
41
I/O
ST
RC10
45
33
I/O
ST
RC11
24
20
I/O
ST
RC12
39
27
I/O
ST
RC13
47
35
I/O
ST
RC15
40
28
I/O
ST
PORTC is a bidirectional I/O port
PORT D
RD5
53
---
I/O
ST
RD6
54
---
I/O
ST
RD8
42
30
I/O
PORTD is a bidirectional I/O port
ST
PORT E
RE0
34
---
I/O
ST
RE1
35
---
I/O
ST
RE12
27
---
I/O
ST
RE13
28
---
I/O
ST
RE14
29
---
I/O
ST
RE15
30
---
I/O
ST
RF0
58
---
I/O
ST
RF1
59
---
I/O
ST
PORTE is a bidirectional I/O port
PORT F
PORTF is a bidirectional I/O port
PORT G
RG6
4
---
I/O
ST
RG7
5
---
I/O
ST
RG8
6
---
I/O
ST
8
---
I/O
RG9
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
PORTG is a bidirectional I/O port
ST
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
Note 1: Only Available on “MC” variants.
DS60001570C-page 16
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 1-3:
OSCILLATOR AND CLOCK PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
CLKI
39
27
CLKO
40
28
OSCI
39
27
OSCO
40
28
SOSCI
47
35
Pin
Type
Buffer
Type
Description
I
ST
External clock source input. Always associated with OSC1 pin function.
O
CMOS
Oscillator crystal output. Connects to crystal in Crystal Oscillator mode.
Optionally functions as CLKO in FRC and EC modes. Always associated
with OSC2 pin function.
I
ST/
CMOS
Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise
O
CMOS
Oscillator crystal output. Connects to crystal in Crystal Oscillator mode.
Optionally functions as CLKO in FRC and EC modes.
I
CMOS
32.768 kHz low-power crystal input
O/I
ST/
CMOS
32.768 low-power crystal output or 32.768 clock oscillator input when
SOSCEN is disabled.
One of several alternate REFCLKOx user-selectable input clock sources.
SOSCO
48
36
REFCLKI
PPS
PPS
I
CMOS
REFCLKO1
PPS
PPS
O
CMOS
REFCLKO2
PPS
PPS
O
CMOS
PPS
O
CMOS
REFCLKO3
PPS
O
CMOS
PPS
PPS
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
Reference Clock Generator Outputs 1-4
REFCLKO4
Legend:
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
Note 1: Only Available on “MC” variants.
TABLE 1-4:
INPUT CAPTURE PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
IC1
PPS
PPS
I
ST
ST
IC2
PPS
PPS
I
IC3
PPS
PPS
I
ST
IC4
PPS
PPS
I
ST
PPS
I
ST
ST
IC5
PPS
IC6
PPS
PPS
I
IC7
PPS
PPS
I
ST
IC8
PPS
PPS
I
ST
IC9
Legend:
I
ST
PPS
PPS
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2019-2020 Microchip Technology Inc.
Description
Input Capture Inputs 1 - 9
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001570C-page 17
PIC32MK GPG/MCJ with CAN FD Family
TABLE 1-5:
OUTPUT COMPARE PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
OC1
PPS
PPS
O
CMOS
OC2
PPS
PPS
O
CMOS
OC3
PPS
PPS
O
CMOS
OC4
PPS
PPS
O
CMOS
CMOS
OC5
PPS
PPS
O
OC6
PPS
PPS
O
CMOS
OC7
PPS
PPS
O
CMOS
OC8
PPS
PPS
O
CMOS
PPS
O
CMOS
PPS
I
ST
OC9
PPS
OCFA
OCFB
Legend:
PPS
I
ST
PPS
PPS
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-6:
Description
Output Compare 1 - 9
Output Compare Fault A Input
Output Compare Fault B Input
Analog = Analog input
P = Power
O = Output
I = Input
PPS = Peripheral Pin Select
EXTERNAL INTERRUPTS PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
Description
INT0
46
34
I
ST
External Interrupt 0
INT1
PPS
PPS
I
ST
External Interrupt 1
PPS
I
ST
External Interrupt 2
INT2
INT3
INT4
Legend:
PPS
I
ST
PPS
I
ST
PPS
PPS
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
PPS
DS60001570C-page 18
External Interrupt 3
External Interrupt 4
Analog = Analog input
P = Power
O = Output
I = Input
PPS = Peripheral Pin Select
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 1-7:
UART1 THROUGH UART2 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
U1RX
PPS
PPS
I
St
UART1 Receive
PPS
O
CMOS
UART1 Transmit
ST
Description
Universal Asynchronous Receiver Transmitter 1
U1TX
PPS
U1CTS
PPS
PPS
I
U1RTS
PPS
PPS
O
U2RX
PPS
PPS
I
ST
UART2 Receive
CMOS
UART2 Transmit
ST
CMOS UART1 Request to Send
Universal Asynchronous Receiver Transmitter 2
U2TX
PPS
PPS
O
U2CTS
PPS
PPS
I
U2RTS
Legend:
UART1 Clear to Send
UART2 Clear to Send
O
CMOS UART2 Request to Send
PPS
PPS
CMOS = CMOS-compatible input or output
Analog = Analog input
ST = Schmitt Trigger input with CMOS levels
O = Output
TTL = Transistor-transistor Logic input buffer
PPS = Peripheral Pin Select
TABLE 1-8:
P = Power
I = Input
SPI1 THROUGH SPI2 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
SCK1
46
34
I/O
ST/CMOS
SDI1
PPS
PPS
I
ST
SPI1 Data In
CMOS
SPI1 Data Out
Description
Serial Peripheral Interface 1
SPI1 Synchronous Serial Clock Input/Output
SDO1
PPS
PPS
O
SS1
PPS
PPS
I/O
ST/CMOS
SCK2
PPS
PPS
I/O
ST/CMOS
SPI2 Synchronous Serial Clock Input/Output
SDI2
PPS
PPS
I
ST
SPI2 Data In
O
CMOS
SDO2
SS2
Legend:
PPS
SPI1 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 2
PPS
I/O
ST/CMOS
PPS
PPS
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-9:
SPI2 Data Out
SPI2 Slave Synchronization Or Frame Pulse I/O
Analog = Analog input
P = Power
O = Output
I = Input
PPS = Peripheral Pin Select
I2C1 THROUGH I2C2 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
SCL1
44
32
I/O
ST
I2C1 Synchronous Serial Clock Input/Output
SDA1
43
31
I/O
ST
I2C1 Synchronous Serial Data Input/Output
Description
Inter-Integrated Circuit 1
Inter-Integrated Circuit 2
SCL2
SDA2
Legend:
32
24
I/O
ST
I/O
ST
31
23
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2019-2020 Microchip Technology Inc.
I2C2 Synchronous Serial Clock Input/Output
I2C2 Synchronous Serial Data Input/Output
Analog = Analog input
P = Power
O = Output
I = Input
PPS = Peripheral Pin Select
DS60001570C-page 19
PIC32MK GPG/MCJ with CAN FD Family
TABLE 1-10:
TIMER1 THROUGH TIMER9 AND RTCC PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
T1CK
48
36
I
ST
Timer1 External Clock Input
T2CK
PPS
PPS
I
ST
Timer2 External Clock Input
ST
Timer3 External Clock Input
Description
Timer1 through Timer9
T3CK
PPS
PPS
I
T4CK
PPS
PPS
I
ST
Timer4 External Clock Input
T5CK
PPS
PPS
I
ST
Timer5 External Clock Input
T6CK
PPS
PPS
I
ST
Timer6 External Clock Input
ST
Timer7 External Clock Input
Timer8 External Clock Input
T7CK
PPS
PPS
I
T8CK
PPS
PPS
I
ST
T9CK
PPS
PPS
I
ST
RTCC
Legend:
O
CMOS
18
14
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001570C-page 20
Timer9 External Clock Input
Real-Time Clock Alarm/Seconds Output
Analog = Analog input
P = Power
O = Output
I = Input
PPS = Peripheral Pin Select
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 1-11:
COMPARATOR 1 THROUGH COMPARATOR 5 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
C1IN1-
18
14
I
Analog
Comparator #1 Negative Input 1
Analog
Comparator #1 Positive Input 1
Description
Comparator 1
C1IN1+
17
13
I
C1IN2-
24
20
I
Analog
Comparator #1 Negative Input 2
C1IN3-
17
13
I
Analog
Comparator #1 Negative Input 3
C1IN4-
16
12
I
Analog
Comparator #1 Negative Input 4
Comparator 2
C2IN1-
15
11
I
Analog
C2IN1+
14
10
I
Analog
Comparator #2 Negative Input 1
Comparator #2 Positive Input 1
C2IN2-
27
-
I
Analog
Comparator #2 Negative Input 2
C2IN3-
17
13
I
Analog
Comparator #2 Negative Input 3
9
I
Analog
C2IN4-
13
Comparator #2 Negative Input 4
Comparator 3
C3IN1-
22
18
I
Analog
C3IN1+
23
19
I
Analog
Comparator #3 Negative Input 1
Comparator #3 Positive Input 1
C3IN2-
28
-
I
Analog
Comparator #3 Negative Input 2
Analog
Comparator #3 Negative Input 3
Analog
C3IN3-
23
19
I
C3IN4-
21
17
I
Comparator #3 Negative Input 4
Comparator 4
C4IN1-
22
18
I
Analog
C4IN1+
21
17
I
Analog
Comparator #4 Positive Input 1
C4IN2-
16
12
I
Analog
Comparator #4 Negative Input 2
C4IN3-
13
9
I
Analog
Comparator #4 Negative Input 3
C4IN4-
21
17
I
Analog
Comparator #4 Negative Input 1
Comparator #4 Negative Input 4
Comparator 5
C5IN1-
49
37
I
Analog
Comparator #5 Negative Input 1
C5IN1+
33
25
I
Analog
Comparator #5 Positive Input 1
Analog
Comparator #5 Negative Input 2
Analog
Comparator #5 Negative Input 3
C5IN2-
27
-
I
C5IN3-
33
25
I
C5IN4Legend:
I
Analog
46
34
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2019-2020 Microchip Technology Inc.
Comparator #5 Negative Input 4
Analog = Analog input
P = Power
O = Output
I = Input
PPS = Peripheral Pin Select
DS60001570C-page 21
PIC32MK GPG/MCJ with CAN FD Family
TABLE 1-12:
OP AMP 1 THROUGH OP-AMP 5 PINOUT I/O DESCRIPTIONS
Pin Number
64-Pin
TQFP/
QFN
Pin Name
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
I
Analog
Description
Op amp 1
OA1IN-
18
14
Op amp 1 Input
OA1IN+
17
13
I
Analog
Op amp 1 Input
OA1OUT
16
12
O
Analog
Op amp 1 Output
OA2IN-
15
11
I
Analog
Analog
Op amp 2 Input
Op amp 2 Output
Op amp 2
Op amp 2 Input
OA2IN+
14
10
I
OA2OUT
13
9
O
Analog
OA3IN-
22
18
I
Analog
Op amp 3 Input
OA3IN+
23
19
I
Analog
Op amp 3 Input
17
O
Analog
Op amp 3
OA3OUT
21
Op amp 3 Output
Op amp 5
OA5IN-
49
37
I
Analog
OA5IN+
33
25
I
Analog
OA5OUT
Legend:
O
Analog
46
34
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-13:
Op amp 5 Input
Op amp 5 Input
Op amp 5 Output
Analog = Analog input
P = Power
O = Output
I = Input
PPS = Peripheral Pin Select
CAN_FD PINOUT I/O DESCRIPTIONS
Pin Number
64-Pin
TQFP/
QFN
Pin Name
C1TX (1)
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
Legend:
O
CMOS
PPS
I
ST
PPS
PPS
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
Note 1:
Not available on “GPG” variants.
C1RX (1)
PPS
TABLE 1-14:
Description
CANFD1 Bus Transmit Pin
CANFD1 Bus Receive Pin
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
CTMU PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
Description
CTCMP
18
14
I
Analog
CTMU external capacitor input for pulse generation
CTED1
16
12
I
ST
CTMU External Edge/Level Input 1
CTED2
15
11
I
ST
CTMU External Edge/Level Input 2
O
CMOS
CTPLS
Legend:
63
47
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001570C-page 22
CTMU Pulse Generator Output
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 1-15:
DAC1 AND DAC2 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
Description
DAC1
45
33
O
Analog
Control 12bit DAC1 Output
O
Analog
DAC2
Legend:
31
23
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-16:
Control 12bit DAC2 Output
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
MCPWM1 THROUGH MCPWM9 PINOUT I/O DESCRIPTIONS (MOTOR CONTROL
DEVICES ONLY)
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
Description
PWM1H
2
2
O
CMOS
MCPWM1 High Side Output
PWM1L
3
3
O
CMOS
MCPWM1 Low Side Output
PWM2H
62
46
O
CMOS
MCPWM2 High Side Output
PWM2L
63
47
O
CMOS
MCPWM2 Low Side Output
PWM3H
60
44
O
CMOS
MCPWM3 High Side Output
PWM3L
61
45
O
CMOS
MCPWM3 Low Side Output
PWM4H
64
48
O
CMOS
MCPWM4 High Side Output
PWM4L
1
1
O
CMOS
MCPWM4 Low Side Output
CMOS
MCPWM5 High Side Output
PWM5H
52
40
O
PWM5L
55
41
O
CMOS
MCPWM5 Low Side Output
PWM6H
50
38
O
CMOS
MCPWM6 High Side Output
PWM6L
51
39
O
CMOS
MCPWM6 Low Side Output
CMOS
MCPWM7 High Side Output
PWM7H
5
-
O
PWM7L
4
-
O
CMOS
MCPWM7 Low Side Output
PWM8H
58
-
O
CMOS
MCPWM8 High Side Output
PWM8L
59
-
O
CMOS
MCPWM8 Low Side Output
O
CMOS
MCPWM9 High Side Output
PWM9H
PWM9L
Legend:
Note:
53
O
CMOS
54
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
MCPWM9 Low Side Output
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
PWM features are only supported on “MC” variants.
2019-2020 Microchip Technology Inc.
DS60001570C-page 23
PIC32MK GPG/MCJ with CAN FD Family
TABLE 1-17:
MCPWM FAULT, CURRENT-LIMIT, AND DEAD TIME COMPENSATION PINOUT I/O
DESCRIPTIONS (MOTOR CONTROL DEVICES ONLY)
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
FLT3
23
19
I
ST
FLT4
24
20
I
ST
FLT5
27
-
I
ST
FLT6
28
-
I
ST
ST
FLT7
29
-
I
FLT8
30
-
I
ST
FLT12
8
-
I
ST
FLT13
11
7
I
ST
8
I
ST
FLT14
FLT15
Legend:
Note:
12
ST
32
24
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
Description
PWM Fault / Dead Time Comp Input Control
I
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
MCPWM fault features are only supported on “MC” variants.
TABLE 1-18:
QEI1 THROUGH QEI3 PINOUT I/O DESCRIPTIONS (MOTOR CONTROL DEVICES
ONLY)
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
ST
QEI1 Phase A Input in QEI mode
Description
Quadrature Encoder Interface 1
QEA1
PPS
PPS
I
QEB1
PPS
PPS
I
ST
QEI1 Phase B Input in QEI Mode. Auxiliary Timer mode.
INDX1
PPS
PPS
I
ST
QEI1 Index Pulse Input
HOME1
PPS
PPS
I
ST
QEI1 Position Counter Input Capture Trigger
PPS
I
ST
QEI1 Capture Compare Match Output
QEICMP1
PPS
Quadrature Encoder Interface 2
QEA2
PPS
PPS
I
ST
QEI2 Phase A Input in QEI mode
QEB2
PPS
PPS
I
ST
QEI2 Phase B Input in QEI Mode. Auxiliary Timer mode.
INDX2
PPS
PPS
I
ST
QEI2 Index Pulse Input
ST
QEI2 Position Counter Input Capture Trigger
ST
QEI2 Capture Compare Match Output
HOME2
PPS
PPS
I
QEICMP2
PPS
PPS
I
Quadrature Encoder Interface 3
QEA3
PPS
PPS
I
ST
QEI3 Phase A Input in QEI mode
QEB3
PPS
PPS
I
ST
QEI3 Phase B Input in QEI Mode. Auxiliary Timer mode.
PPS
I
ST
QEI3 Index Pulse Input
PPS
I
ST
QEI3 Position Counter Input Capture Trigger
INDX3
HOME3
QEICMP3
Legend:
Note:
PPS
PPS
I
ST
QEI3 Capture Compare Match Output
PPS
PPS
CMOS = CMOS-compatible input or output
Analog = Analog input
ST = Schmitt Trigger input with CMOS levels
O = Output
TTL = Transistor-transistor Logic input buffer
PPS = Peripheral Pin Select
P = Power
I = Input
QEI features are only supported on “MC” variants.
DS60001570C-page 24
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 1-19:
POWER, GROUND, HLVD AND VOLTAGE REFERENCE PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
Description
15
P
P
Positive supply for analog modules. This pin must be connected at all times.
20
16
P
P
Ground reference for analog modules. This pin must be
connected at all times
VDD
10, 26, 38, 42(1),
57
6,22,26,30(1),43
P
P
Positive supply for peripheral logic and I/O pins. This pin
must be connected at all times
VSS
9, 25, 41, 56
5, 21, 29, 42
P
P
Ground reference for logic, and I/O pins. This pin must be
connected at all times
VREF+
16
12
I
Analog
Analog Voltage Reference (High) Input
11
I
Analog
Analog Voltage Reference (Low) Input
Pin Name
64-Pin TQFP/
QFN
48-Pin TQFP/
VQFN
AVDD
19
AVSS
Voltage References
VREF-
15
High / Low Voltage Detect
LVDIN
Legend:
I
49
37
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
Analog
High / Low Voltage detect input
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
Note 1: Only available on “GP” variants.
TABLE 1-20:
JTAG, TRACE, MASTER CLEAR AND PROGRAMMING/DEBUGGING PINOUT I/O
DESCRIPTIONS
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
I
ST
JTAG Test Clock Input Pin
JTAG Test Data Input Pin
Description
JTAG Interface
TCK
1
1
TDI
31
23
I
ST
TDO
64
48
O
CMOS
37
I
ST
TMS
49
JTAG Test Data Output Pin
JTAG Test Mode Select Pin
Trace Interface
TRCLK
50
-
O
CMOS
TRD0
51
-
O
CMOS
TRD1
52
-
O
CMOS
TRD2
53
-
O
CMOS
-
O
CMOS
TRD3
54
Trace Clock
Trace Data bits 0-3
Trace support is available through the MPLAB® REAL ICE™ In-circuit
Emulator.
Programming/Debugging
PGED1
18
14
I/O
ST
Data I/O pin for Programming/Debugging Communication Channel 1
PGEC1
17
13
I
ST
Clock input pin for Programming/Debugging Communication Channel 1
PGED2
43
31
I/O
ST
Data I/O pin for Programming/Debugging Communication Channel 2
32
I
ST
Clock input pin for Programming/Debugging Communication Channel 2
PGEC2
44
PGED3
15
11
I/O
ST
Data I/O pin for Programming/Debugging Communication Channel 3
PGEC3
16
12
I
ST
Clock input pin for Programming/Debugging Communication Channel 3
Master Clear
MCLR
Legend:
I
ST
Master Clear (Reset) input. This pin is an active-low Reset to the device.
7
4
CMOS = CMOS-compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = Transistor-transistor Logic input buffer
PPS = Peripheral Pin Select
2019-2020 Microchip Technology Inc.
DS60001570C-page 25
PIC32MK GPG/MCJ with CAN FD Family
TABLE 1-21:
CONFIGURABLE LOGIC CELL PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
Description
Configurable Logic Module 1
CLCINA
PPS
PPS
I
CLC01
O
PPS
PPS
Configurable Logic Module 2
CLCINB
I
PPS
O
PPS
PPS
Configurable Logic Module 3
CLC02
CLCINC
CLC03
CLCIND
CLC04
Legend:
PPS
PPS
PPS
I
O
PPS
PPS
Configurable Logic Module 4
ST
CMOS
ST
CMOS
Configurable Logic Inputs & Outputs 1-4
ST
CMOS
I
ST
PPS
O
CMOS
PPS
PPS
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
PPS
DS60001570C-page 26
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 1-22:
CAPACITIVE VOLTAGE DIVIDER PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
CVD6
21
17
I
Analog
Analog
CVD7
22
18
I
CVD8
23
19
I
Analog
CVD9
12
8
I
Analog
CVD10
11
7
I
Analog
Analog
CVD11
24
20
I
CVD12
27
-
I
Analog
CVD13
28
-
I
Analog
CVD14
29
-
I
Analog
-
I
Analog
Analog
CVD15
30
CVD16
8
-
I
CVD17
6
-
I
Analog
CVD18
5
-
I
Analog
CVD19
4
-
I
Analog
Analog
CVD24
33
25
I
CVD25
46
34
I
Analog
CVD26
31
23
I
Analog
CVD27
49
37
I
Analog
Analog
CVD40
34
-
I
CVD41
35
-
I
Analog
CVD46
36
-
I
Analog
CVD47
37
-
I
Analog
33
I
Analog
CVD48
CVD49
Legend:
45
Analog
39
27
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2019-2020 Microchip Technology Inc.
Description
Capacitive Voltage Divider Inputs
I
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001570C-page 27
PIC32MK GPG/MCJ with CAN FD Family
TABLE 1-23:
ADC0 - ADC5, ADC7 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
64-Pin
TQFP/
QFN
48-Pin
TQFP/
VQFN
Pin
Type
Buffer
Type
Description
AN0
13
9
I
Analog
Dedicated Class_1 ADC0 module
Analog Input Channel
AN1
14
10
I
Analog
Dedicated Class_1 ADC1 module
Analog Input Channel
AN2
15
11
I
Analog
Dedicated Class_1 ADC2 module
Analog Input Channel
AN3
16
12
I
Analog
Dedicated Class_1 ADC3 module
Analog Input Channel
AN4
17
13
I
Analog
Dedicated Class_1 ADC4 module
Analog Input Channel
AN5
18
14
I
Analog
Dedicated Class_1 ADC5 module
Analog Input Channel
AN6
21
17
I
Analog
AN7
22
18
I
Analog
Analog
AN8
23
19
I
AN9
12
8
I
Analog
AN10
11
7
I
Analog
AN11
24
20
I
Analog
-
I
Analog
Analog
AN12
27
AN13
28
-
I
AN14
29
-
I
Analog
AN15
30
-
I
Analog
-
I
Analog
Analog
AN16
8
AN17
6
-
I
AN18
5
-
I
Analog
AN19
4
-
I
Analog
AN24
33
25
I
Analog
Analog
AN25
46
34
I
AN26
31
23
I
Analog
AN27
49
37
I
Analog
AN40
34
-
I
Analog
-
I
Analog
-
I
Analog
AN41
35
AN46
36
AN47
37
-
I
Analog
AN48
45
33
I
Analog
AN49
Legend:
Analog
39
27
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001570C-page 28
Shared ADC7 module
Analog Input Channels
I
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
2.0
Note:
2.1
GUIDELINES FOR GETTING
STARTED WITH 32-BIT MCUS
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the documents listed in the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
Basic Connection Requirements
Getting started with the PIC32MK GPG/MCJ with CAN
FD Family of 32-bit Microcontrollers (MCUs) requires
attention to a minimal set of device pin connections
before proceeding with development. The following is a
list of pin names, which must always be connected:
• All VDD and VSS pins (see 2.2 “Decoupling
Capacitors”)
• All AVDD and AVSS pins, even if the ADC module is
not used (see 2.2 “Decoupling Capacitors”)
• MCLR pin (see 2.3 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins, used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see 2.4 “ICSP Pins”)
• OSC1 and OSC2 pins, when external oscillator
source is used (see 2.7 “External Oscillator Pins”)
The following pins may be required:
VREF+/VREF- pins, used when external voltage
reference for the ADC module is implemented.
Note:
The AVDD and AVSS pins must be
connected, regardless of ADC use and
the ADC voltage reference source.
DS60001570C-page 26
2.2
Decoupling Capacitors
The use of decoupling capacitors on power supply
pins, such as VDD, VSS, AVDD and AVSS is required,
see Figure 2-1.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A value of 0.1 µF
(100 nF), 10-20V is recommended. The capacitor
should be a low Equivalent Series Resistance
(low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is
further recommended that ceramic capacitors be
used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended that
the capacitors be placed on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within onequarter inch (6 mm) in length.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
2.3
Master Clear (MCLR) Pin
The MCLR
functions:
pin
provides
two
specific
device
• Device Reset
• Device programming and debugging
Pulling The MCLR pin low generates a device Reset.
Figure 2-2 illustrates a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
For example, as illustrated in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components illustrated in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
Note 1: As an option, instead of a hard-wired
connection, an inductor (L1) can be substituted between VDD and AVDD to
improve ADC noise rejection. The inductor impedance must be less than 3 and
the inductor capacity is greater than 10
mA.
2.2.1
R
ICSP™
(i.e., ADC conversion rate/2)
2
1
L = ----------------------
2f C
Note
1
5
4
2
3
6
2019-2020 Microchip Technology Inc.
VDD
VSS
NC
10k
C
R1(1)
1 k
MCLR
PIC32
PGECx(3)
PGEDx(3)
1:
470 R1 1 K will limit any current flowing into
MCLR from the external capacitor C, in the event of
MCLR pin breakdown, due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS). Ensure that the
MCLR pin VIH and VIL specifications are met without
interfering with the Debug/Programmer tools.
2:
The capacitor can be sized to prevent unintentional
Resets from brief glitches or to extend the device
Reset period during POR.
3:
No pull-ups or bypass capacitors are allowed on
active debug/program PGECx/PGEDx pins.
BULK CAPACITORS
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
0.1 µF(2)
Where:
F CNV
f = -------------2
1
f = ---------------------- 2 LC
FIGURE 2-2:
DS60001570C-page 27
PIC32MK GPG/MCJ with CAN FD Family
2.4
ICSP Pins
The PGECx and PGEDx pins are used for ICSP and
debugging purposes. It is recommended to keep the
trace length between the ICSP connector and the ICSP
pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a
series resistor is recommended, with the value in the
range of a few tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 3 or MPLAB REAL ICE™.
For additional information on ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web
site.
• “Using MPLAB® ICD 3” (poster) DS50001765
• “MPLAB® ICD 3 Design Advisory” DS50001764
• “MPLAB® REAL ICE™ In-Circuit Debugger
User’s Guide” DS50001616
• “Using MPLAB® REAL ICE™ Emulator” (poster)
DS50001749
2.5
2.6
Trace
When present on select pin counts, the trace pins
can be connected to a hardware trace-enabled programmer to provide a compressed real-time instruction trace. When used for trace, the TRD3, TRD2,
TRD1, TRD0 and TRCLK pins should be dedicated
for this use. The trace hardware requires a 22 Ohm
series resistor between the trace pins and the trace
connector.
2.7
External Oscillator Pins
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 7.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same side
of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The
load capacitors should be placed next to the oscillator
itself, on the same side of the board. Use a grounded
copper pour around the oscillator circuit to isolate them
from surrounding circuits. The grounded copper pour
should be routed directly to the MCU ground. Do not
run any signal traces or power traces inside the ground
pour. Also, if using a two-sided board, avoid any traces
on the other side of the board where the crystal is
placed. A suggested layout is illustrated in Figure 2-3.
FIGURE 2-3:
SUGGESTED OSCILLATOR
CIRCUIT PLACEMENT
JTAG
The TMS, TDO, TDI and TCK pins are used for testing
and debugging according to the Joint Test Action
Group (JTAG) standard. It is recommended to keep the
trace length between the JTAG connector and the
JTAG pins on the device as short as possible. If the
JTAG connector is expected to experience an ESD
event, a series resistor is recommended, with the value
in the range of a few tens of Ohms, not to exceed 100
Ohms.
Oscillator
Secondary
Guard Trace
Guard Ring
Main Oscillator
Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended
as they will interfere with the programmer/debugger
communications to the device. If such discrete components are an application requirement, they should be
removed from the circuit during programming and
debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the
respective device Flash programming specification for
information on capacitive loading limits and pin input
voltage high (VIH) and input low (VIL) requirements.
DS60001570C-page 28
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
CRYSTAL OSCILLATOR DESIGN
CONSIDERATION
The following example assumptions are used to
calculate the Primary Oscillator loading capacitor
values:
•
•
•
•
CIN = PIC32_OSCO_Pin Capacitance = 4 pF
COUT = PIC32_OSCI_Pin Capacitance = 4 pF
PCB stray capacitance (i.e., 12 mm length) = 2.5 pF
C1 and C2 = the loading capacitors to use on
2.7.1.1
Additional Microchip References
• AN588 “PICmicro® Microcontroller Oscillator
Design Guide”
• AN826 “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
• AN849 “Basic PICmicro® Oscillator Design”
FIGURE 2-4:
your crystal circuit design to guarantee that the
effective capacitance as seen by the crystal in
circuit meets the crystal manufacturer
specification
CLOAD = {( [CIN + C1] * [COUT + C2] ) / [CIN + C1 + C2
+ COUT] } + oscillator PCB stray capacitance
EXAMPLE 2-1: CRYSTAL LOAD CAPACITOR
CALCULATION
Crystal manufacturer data sheet spec example: CLOAD = 15 pF
Therefore:
MFG CLOAD = {( [CIN + C1] * [COUT + C2] ) / [CIN + C1 + C2 + COUT] }
+ estimated oscillator PCB stray capacitance
Circuit A
C1
MFG Crystal Data Sheet CLOAD spec:
PRIMARY CRYSTAL
OSCILLATOR CIRCUIT
RECOMMENDATIONS
C2
2.7.1
Rs
OSCO
OSCI
Circuit B
Not Recommended
Assuming C1 = C2 and PIC32 Cin = Cout, the formula can be further
simplified and restated to solve for C1 and C2 by:
C1 = C2 = ((2 * MFG Cload spec) - Cin - (2 * PCB capacitance))
= ((2 * 15) - 4 - (2 * 2.5 pF))
= (30 - 4 - 5)
= 21 pF
RSHUNT
Rs
Therefore:
C1 = C2 = 21 pF is the correct loading capacitors to use on your crystal circuit design to guarantee that the effective capacitance as seen
by the crystal in circuit in this example is 15 pF to meet the crystal
manufacturer specification.
Tips to increase oscillator gain, (that is, to increase
peak-to-peak oscillator signal):
• Select an crystal oscillator with a lower XTAL
manufacturing “ESR” rating.
• C1 and C2 values also affect the gain of the oscillator.
The lower the values, the higher the gain.
• Likewise, C2/C1 ratio also affects gain. To increase
the gain, make C1 slightly smaller than C2, which will
also help start-up performance.
Note:
OSCO
OSCI
Circuit C
Not Recommended
Rs
RSHUNT
OSCO
OSCI
Do not add excessive gain such that the
oscillator signal is clipped, flat on top of
the sine wave. If so, you need to reduce
the gain or add a series resistor, RS, as
shown in circuit “A” in Figure 2-4. Failure
to do so will stress and age the crystal,
which can result in an early failure. When
measuring the oscillator signal you must
use an active-powered scope probe with
1 pF or the scope probe itself will unduly
change the gain and peak-to-peak levels.
2019-2020 Microchip Technology Inc.
DS60001570C-page 29
PIC32MK GPG/MCJ with CAN FD Family
2.8
Unused I/Os
2.9
Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
to a logic-low state.
2.9.1
Note:
NON-5V TOLERANT INPUT PINS
A quick review of the absolute maximum rating section
in 36.0 “Electrical Characteristics” will indicate that
the voltage on any non-5v tolerant pin may not exceed
VDD + 0.3V unless the input current is limited to meet
the respective injection current specifications defined
by parameters DI60a, DI60b, and DI60c in TABLE 3610: “DC Characteristics: I/O Pin Input Injection current Specifications”. Figure 2-5 shows an example of
a remote circuit using an independent power source,
which is powered while connected to a PIC32 non-5V
tolerant circuit that is not powered.
Alternatively, inputs can be reserved by connecting the
pin to VSS through a 1k resistor and configuring the pin
as an input, which they are by default on any Reset.
FIGURE 2-5:
Considerations When Interfacing
to Remotely Powered Circuits
PIC32 NON-5V TOLERANT CIRCUIT EXAMPLE
When VDD power is OFF.
PIC32
Non-5V Tolerant
Pin Architecture
On/Off
VDD
ANSEL
I/O IN
AN2/RB0
I/O OUT
Remote
GND
TRIS
CPU LOGIC
Remote
0.3V dVIH d 3.6V
PIC32
POWER
SUPPLY
Current Flow
VSS
DS60001570C-page 30
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 2-6:
Opto Coupling
Analog/Digital Switch
EXAMPLES OF DIGITAL/
ANALOG ISOLATORS WITH
OPTIONAL LEVEL
TRANSLATION
Capacitive Coupling
TABLE 2-1:
Inductive Coupling
Without proper signal isolation, on non-5V tolerant
pins, the remote signal can power the PIC32 device
through the high side ESD protection diodes.
Besides violating the absolute maximum rating
specification when VDD of the PIC32 device is
restored and ramping up or ramping down, it can
also negatively affect the internal Power-on Reset
(POR) and Brown-out Reset (BOR) circuits, which
can lead to improper initialization of internal PIC32
logic circuits. In these cases, it is recommended to
implement digital or analog signal isolation as
depicted in Figure 2-6, as appropriate. This is
indicative of all industry microcontrollers and not just
Microchip products.
ADuM7241 / 40 ARZ (1 Mbps)
X
—
—
—
ADuM7241 / 40 CRZ (25 Mbps)
X
—
—
—
ISO721
—
X
—
—
LTV-829S (2 Channel)
—
—
X
—
LTV-849S (4 Channel)
—
—
X
—
FSA266 / NC7WB66
—
—
—
X
Example Digital/Analog
Signal Isolation Circuits
EXAMPLE DIGITAL/ANALOG SIGNAL ISOLATION CIRCUITS
Conn
PIC32 VDD
Digital Isolator
External VDD
PIC32 VDD
Digital Isolator
External VDD
REMOTE_IN
IN1
REMOTE_OUT
OUT1
IN
PIC32
REMOTE_IN
PIC32
VSS
VSS
PIC32 VDD
PIC32 VDD
Analog / Digital Isolator
Opto Digital
ISOLATOR
Conn
IN1
External VDD
ENB
Analog_IN2
Analog_OUT2
PIC32
External_VDD1
ENB
REMOTE_IN
PIC32
S
Analog_IN1
Analog Switch
VSS
VSS
2019-2020 Microchip Technology Inc.
DS60001570C-page 31
PIC32MK GPG/MCJ with CAN FD Family
2.9.2
5V TOLERANT INPUT PINS
The internal high side diode on 5v tolerant pins are
bussed to an internal floating node, rather than being
connected to VDD, as shown in Figure 2-7. Voltages
on these pins, if VDD < 2.3V, should not exceed
roughly 3.2V relative to VSS of the PIC32 device.
Voltage of 3.6V or higher will violate the absolute
maximum specification, and will stress the oxide
layer separating the high side floating node, which
impacts device reliability. If a remotely powered
“digital-only” signal can be guaranteed to always be
3.2V relative to Vss on the PIC32 device side, a
5V tolerant pin could be used without the need for a
digital isolator. This is assuming there is not a
ground loop issue, logic ground of the two circuits
not at the same absolute level, and a remote logic
low input is not less than VSS - 0.3V.
FIGURE 2-7:
PIC32 5V TOLERANT PIN ARCHITECTURE EXAMPLE
PIC32
5V Tolerant Pin
Architecture
Floating Bus
Oxide BV = 3.6V
if VDD < 2.3V
OXIDE
On/Off
VDD
ANSEL
I/O IN
RG10
I/O OUT
Remote
GND
TRIS
CPU LOGIC
Remote
VIH = 2.5V
PIC32
POWER
SUPPLY
VSS
DS60001570C-page 32
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
2.10
Designing for High-Speed
Peripherals
The PIC32MK GPG/MCJ with CAN FD Family of
devices have peripherals that operate at frequencies
much higher than typical for an embedded environment. Table 2-2 lists the peripherals that produce highspeed signals on their external pins:
TABLE 2-2:
PERIPHERALS THAT
PRODUCE HS SIGNALS ON
EXTERNAL PINS
Peripheral
High-Speed Signal
Pins
Maximum
Speed on
Signal Pin
SPI/I2S
SCKx, SDOx, SDIx
50 MHz
REFCLKx
REFCLKx
50 MHz
Due to these high-speed signals, it is important to
consider several factors when designing a product that
uses these peripherals, as well as the PCB on which
these components will be placed. Adhering to these
recommendations will help achieve the following goals:
• Minimize the effects of electromagnetic interference
to the proper operation of the product
• Ensure signals arrive at their intended destination at
the same time
• Minimize crosstalk
• Maintain signal integrity
• Reduce system noise
• Minimize ground bounce and power sag
2.10.1
2.10.1.1
SYSTEM DESIGN
Impedance Matching
When selecting parts to place on high-speed buses,
particularly the SPI bus and REFCLKx outputs, if the
impedance of the peripheral device does not match the
impedance of the pins on the PIC32MK GPG/MCJ with
CAN FD Family of devices to which it is connected, signal reflections could result, thereby degrading the quality of the signal.
If it is not possible to select a product that matches
impedance, place a series resistor at the load to create
the matching impedance. See Figure 2-8 for an
example.
FIGURE 2-8:
SERIES RESISTOR
PIC32MK
50
2019-2020 Microchip Technology Inc.
2.10.1.2
PCB Layout Recommendations
The following list contains recommendations that will
help ensure the PCB layout will promote the goals
previously listed.
• Component Placement
- Place bypass capacitors as close to their
component power and ground pins as possible,
and place them on the same side of the PCB.
- Devices on the same bus that have larger setup
times must be placed closer to the PIC32MK
GPG/MCJ with CAN FD Family of devices.
• Power and Ground
- Multi-layer PCBs will allow separate power and
ground planes
- Each ground pin should be connected to the
ground plane individually
- Place bypass capacitor vias as close to the pad
as possible (preferably inside the pad)
- If power and ground planes are not used,
maximize width for power and ground traces
- Use low-ESR, surface-mount bypass capacitors
• Clocks and Oscillators
- Place crystals as close as possible to the
PIC32MK GPG/MCJ with CAN FD Family device
OSC/SOSC pins
- Do not route high-speed signals near the clock or
oscillator
- Avoid via usage and branches in clock lines
(SCK)
- Place termination resistors at the end of clock
lines
• Traces
- Higher-priority signals should have the shortest
traces
- Avoid long run lengths on parallel traces to reduce
coupling
- Make the clock traces as straight as possible
- Use rounded turns rather than right-angle turns
- Have traces on different layers intersect on right
angles to minimize crosstalk
- Maximize the distance between traces, preferably
no less than three times the trace width
- Power traces should be as short and as wide as
possible
- High-speed traces should be placed close to the
ground plane
SPI
Flash
Device
DS60001570C-page 33
PIC32MK GPG/MCJ with CAN FD Family
2.10.1.3
EMI/EMC/EFT (IEC 61000-4-4 and
IEC 61000-4-2) Suppression
Considerations
The use of LDO regulators is preferred to reduce
overall system noise and provide a cleaner power
source. However, when utilizing switching Buck/Boost
regulators as the local power source for PIC32MK GP
devices, as well as in electrically noisy environments or
test conditions required for IEC 61000-4-4 and IEC
61000-4-2, users should evaluate the use of T-Filters
(i.e., L-C-L) on the power pins, as shown in Figure 2-9.
In addition to a more stable power source, use of this
type of T-Filter can greatly reduce susceptibility to EMI
sources and events.
FIGURE 2-9:
EMI/EMC/EFT
SUPPRESSION CIRCUIT
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DS60001570C-page 34
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
2.11
Typical Application Connection
Examples
Examples of typical application connections are shown
in Figure 2-10, Figure , and Figure .
FIGURE 2-10:
CAPACITIVE TOUCH SENSING APPLICATION
PIC32
Current Source
To AN6
CTMU
ADC
AN1
To AN11
R1
R1
R1
R1
R1
C1
C2
C3
C4
C5
R2
R2
R2
R2
R2
C1
C2
C3
C4
C5
To AN1
To AN5
AN11
2019-2020 Microchip Technology Inc.
To AN9
AN9
Process Samples
User
Application
To AN8
To AN0
AN0
Read the Touch Sensors
Microchip
mTouch™
Library
To AN7
R3
R3
R3
R3
R3
C1
C2
C3
C4
C5
DS60001570C-page 35
PIC32MK GPG/MCJ with CAN FD Family
2.0
CPU
Note 1: This data sheet summarizes the features of the PIC32MK GPG/MCJ with
CAN FD Family of devices. It is not
intended to be a comprehensive reference source. To complement the information in this data sheet, refer to
Section 50. “CPU for Devices with
MIPS32® microAptiv™ and M-Class
Cores” (DS60001192) of the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
2: The microAptiv™ CPU core resources
are available at: www.imgtec.com.
The MIPS32® microAptiv™ MCU Core is the heart of
the PIC32MK GPG/MCJ with CAN FD Family of
device’s processor. The CPU fetches instructions,
decodes each instruction, fetches source operands,
executes each instruction and writes the results of
instruction execution to the proper destinations.
The following are key features of the CPU module:
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32 Enhanced Architecture (Release 5):
- Multiply-accumulate and multiply-subtract
instructions
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency for
interrupt handlers
- Bit field manipulation instructions
- Virtual memory support
• microMIPS™ compatible instruction set:
- Improves code size density over MIPS32, while
maintaining MIPS32 performance.
- Supports all MIPS32 instructions (except branchlikely instructions)
- Fifteen additional 32-bit instructions and 39 16-bit
instructions corresponding to commonly-used
MIPS32 instructions
- Stack pointer implicit in instruction
- MIPS32 assembly and ABI compatible
2019-2020 Microchip Technology Inc.
• Autonomous Multiply/Divide Unit (MDU):
- Maximum issue rate of one 32x32 multiply per clock
- Early-in iterative divide. Minimum 12 and
maximum 38 clock latency (dividend (rs) sign
extension-dependent)
• Power Control:
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT instruction)
- Extensive use of local gated clocks
• EJTAG Debug and Instruction Trace:
- Support for single stepping
- Virtual instruction and data address/value
breakpoints
- Hardware breakpoint supports both address
match and address range triggering.
- Eight instruction and four data complex
breakpoints
• iFlowtrace® version 2.0 support:
- Real-time instruction program counter
- Special events trace capability
- Two performance counters with 34 userselectable countable events
- Disabled if the processor enters Debug mode
- Program Counter sampling
• DSP ASE Extension:
- Native fractional format data type operations
- Register Single Instruction Multiple Data (SIMD)
operations (add, subtract, multiply, shift)
- GPR-based shift
- Bit manipulation
- Compare-Pick
- DSP Control Access
- Indexed-Load
- Branch
- Multiplication of complex operands
- Variable bit insertion and extraction
- Virtual circular buffers
- Arithmetic saturation and overflow handling
- Zero-cycle overhead saturation and rounding
operations
• Floating Point Unit (FPU):
- 1985 IEEE-754 compliant Floating Point Unit
- Supports single and double precision datatypes
- 2008 IEEE-754 compatibility control of NaN
handling and Abs/Neg instructions
- Runs at 1:1 core/FPU clock ratio
DS60001570C-page 29
PIC32MK GPG/MCJ with CAN FD Family
A typical block diagram of the PIC32MK GPG/MCJ with
CAN FD Family processor core is shown in Figure 2-1.
FIGURE 2-1:
PIC32MK GPG/MCJ WITH CAN FD FAMILY MICROPROCESSOR CORE BLOCK
DIAGRAM
microAptiv™ MCU Core
PBCLK7
Decode
(MIPS32® microAptiv™
MCU Core)
microMIPS™
GPR
(Two Sets)
Execution Unit
ALU/Shift
Atomic/LdSt
DSP ASE
System
Interface
FMT
(Fixed Map
Table)
BIU
System Bus
FPU
(Single & Double)
Debug/Profiling
System
Coprocessor
Interrupt
Interface
2-wire Debug
DS60001570C-page 30
Enhanced MDU
(with DSP ASE)
Break Points
iFlowtrace®
Fast Debug Channel
Performance Counters
Sampling
Secure Debug
Power
Management
EJTAG
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
2.1
Architecture Overview
The MIPS32 microAptiv MCU core in the PIC32MK
GPG/MCJ with CAN FD Family of devices contains
several logic blocks working together in parallel, providing an efficient high-performance computing engine.
The following blocks are included with the core:
•
•
•
•
•
•
•
•
Execution unit
General Purpose Register (GPR)
Multiply/Divide Unit (MDU)
System control coprocessor (CP0)
Floating Point Unit (FPU)
Power Management
microMIPS support
Enhanced JTAG (EJTAG) controller
2.1.1
2.1.2
MULTIPLY/DIVIDE UNIT (MDU)
The processor core includes a Multiply/Divide Unit
(MDU) that contains a separate pipeline for multiply
and divide operations, and DSP ASE multiply instructions. This pipeline operates in parallel with the Integer
Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially
masked by system stalls and/or other integer unit
instructions.
EXECUTION UNIT
The processor core execution unit implements a load/
store architecture with single-cycle ALU operations
(logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer
operations and address calculation. Seven additional
register file shadow sets (containing thirty-two registers) are added to minimize context switching overhead
during interrupt/exception processing. The register file
consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline.
The execution unit includes:
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
address
• Logic for branch determination and branch target
address calculation
• Load aligner
• Trap condition comparator
• Bypass multiplexers used to avoid stalls when
executing instruction streams where data
producing instructions are followed closely by
consumers of their results
TABLE 2-1:
• Leading Zero/One detect unit for implementing
the CLZ and CLO instructions
• Arithmetic Logic Unit (ALU) for performing arithmetic
and bitwise logical operations
• Shifter and store aligner
• DSP ALU and logic block for performing DSP
instructions, such as arithmetic/shift/compare
operations
The high-performance MDU consists of a 32x16 Booth
recoded multiplier, a pair of result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number
shown (‘32’ of 32x16) represents the rs operand. The
second number ‘16’ of 32x16) represents the rt
operand.
The MDU supports execution of one multiply or
multiply-accumulate operation every clock cycle.
Divide operations are implemented with a simple 1-bitper-clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For
a 16-bit wide rs, 15 iterations are skipped and for a
24-bit wide rs, 7 iterations are skipped. Any attempt to
issue a subsequent MDU instruction while a divide is
still active causes an IU pipeline stall until the divide
operation has completed.
Table 2-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency (number of cycles until a result is available) for the processor
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
MIPS32® microAptiv™ MCU CORE HIGH-PERFORMANCE INTEGER MULTIPLY/
DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU (HI/LO destination)
MUL (GPR destination)
DIV/DIVU
2019-2020 Microchip Technology Inc.
Operand Size (mul rt) (div rs)
Latency
Repeat Rate
16 bits
32 bits
16 bits
32 bits
8 bits
16 bits
24 bits
32 bits
5
5
5
5
12/14
20/22
28/30
36/38
1
1
1
1
12/14
20/22
28/30
36/38
DS60001570C-page 31
PIC32MK GPG/MCJ with CAN FD Family
The MIPS architecture defines that the result of a
multiply or divide operation be placed in one of four
pairs of HI and LO registers. Using the Move-From-HI
(MFHI) and Move-From-LO (MFLO) instructions, these
values can be transferred to the General Purpose
Register file.
Table 2-2 lists the latencies and repeat rates for the
DSP multiply and dot-product operations. The approximate latencies and repeat rates are listed in terms of
pipeline clocks.
TABLE 2-2:
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in
the primary register file instead of the HI/LO register
pair. By avoiding the explicit MFLO instruction
required when using the LO register, and by supporting multiple destination registers, the throughput of
multiply-intensive operations is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
The MDU also implements various shift instructions
operating on the HI/LO register and multiply instructions as defined in the DSP ASE. The MDU supports all
of the data types required for this purpose and includes
three extra HI/LO registers as defined by the ASE.
TABLE 2-3:
Register
Number
DSP-RELATED LATENCIES
AND REPEAT RATES
Op code
Latency
Repeat
Rate
Multiply and dot-product without
saturation after accumulation
5
1
Multiply and dot-product with
saturation after accumulation
5
1
Multiply without accumulation
5
1
2.1.3
SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (Kernel, User and Debug) and
whether interrupts are enabled or disabled. Configuration information, such as the presence of options like
microMIPS is also available by accessing the CP0
registers, listed in Table 2-3.
COPROCESSOR 0 REGISTERS
Register
Name
Function
0-6
Reserved
Reserved in the PIC32MK GP Family core.
7
HWREna
Enables access via the RDHWR instruction to selected hardware registers in
Non-privileged mode.
8
BadVAddr
Reports the address for the most recent address-related exception.
BadInstr
Reports the instruction that caused the most recent exception.
9
BadInstrP
Reports the branch instruction if a delay slot caused the most recent exception.
Count
Processor cycle count.
10
Reserved
Reserved in the PIC32MK GP Family core.
11
Compare
Core timer interrupt control.
12
Status
Processor status and control.
IntCtl
Interrupt control of vector spacing.
13
SRSCtl
Shadow register set control.
SRSMap
Shadow register mapping control.
View_IPL
Allows the Priority Level to be read/written without
extracting or inserting that bit from/to the Status register.
SRSMAP2
Contains two 4-bit fields that provide the mapping from a vector number to the shadow
set number to use when servicing such an interrupt.
Cause
Describes the cause of the last exception.
NestedExc
Contains the error and exception level status bit values that existed prior to the current
exception.
View_RIPL
Enables read access to the RIPL bit that is available in the Cause register.
DS60001570C-page 32
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 2-3:
Register
Number
14
15
COPROCESSOR 0 REGISTERS (CONTINUED)
Register
Name
Function
EPC
Program counter at last exception.
NestedEPC
Contains the exception program counter that existed prior to the current exception.
PRID
Processor identification and revision
Ebase
Exception base address of exception vectors.
CDMMBase
Common device memory map base.
Config
Configuration register.
Config1
Configuration register 1.
Config2
Configuration register 2.
Config3
Configuration register 3.
Config4
Configuration register 4.
Config5
Configuration register 5.
Config7
Configuration register 7.
17
Reserved
Reserved in the PIC32MK GP Family core.
18
Reserved
Reserved in the PIC32MK GP Family core.
19
Reserved
Reserved in the PIC32MK GP Family core.
20-22
Reserved
Reserved in the PIC32MK GP Family core.
16
23
Debug
EJTAG debug register.
TraceControl
EJTAG trace control.
TraceControl2
EJTAG trace control 2.
UserTraceData1 EJTAG user trace data 1 register.
24
TraceBPC
EJTAG trace breakpoint register.
Debug2
Debug control/exception status 1.
DEPC
Program counter at last debug exception.
UserTraceData2 EJTAG user trace data 2 register.
25
PerfCtl0
Performance counter 0 control.
PerfCnt0
Performance counter 0.
PerfCtl1
Performance counter 1 control.
PerfCnt1
Performance counter 1.
26
Reserved
Reserved in the PIC32MK GP Family core.
27
Reserved
Reserved in the PIC32MK GP Family core.
28
Reserved
Reserved in the PIC32MK GP Family core.
29
Reserved
Reserved in the PIC32MK GP Family core.
30
ErrorEPC
Program counter at last error exception.
31
DeSave
Debug exception save.
2019-2020 Microchip Technology Inc.
DS60001570C-page 33
PIC32MK GPG/MCJ with CAN FD Family
2.1.4
FLOATING POINT UNIT (FPU)
The Floating Point Unit (FPU), Coprocessor (CP1),
implements the MIPS Instruction Set Architecture for
floating point computation. The implementation supports the ANSI/IEEE Standard 754 (IEEE for Binary
Floating Point Arithmetic) for single- and double-precision data formats. The FPU can be programmed to
have thirty-two 32-bit or 64-bit floating point registers
used for floating point operations.
The performance is optimized for single precision formats. Most instructions have one FPU cycle throughput
and four FPU cycle latency. The FPU implements the
multiply-add (MADD) and multiply-sub (MSUB) instructions with intermediate rounding after the multiply function. The result is guaranteed to be the same as
executing a MUL and an ADD instruction separately,
but the instruction latency, instruction fetch, dispatch
bandwidth, and the total number of register accesses
are improved.
IEEE denormalized input operands and results are
supported by hardware for some instructions. IEEE
denormalized results are not supported by hardware in
general, but a fast flush-to-zero mode is provided to
optimize performance. The fast flush-to-zero mode is
enabled through the FCCR register, and use of this
mode is recommended for best performance when
denormalized results are generated.
The FPU has a separate pipeline for floating point
instruction execution. This pipeline operates in parallel
with the integer core pipeline and does not stall when
the integer pipeline stalls. This allows long-running
FPU operations, such as divide or square root, to be
partially masked by system stalls and/or other integer
unit instructions. Arithmetic instructions are always
dispatched and completed in order, but loads and
stores can complete out of order. The exception model
is “precise” at all times.
Table 2-4 contains the floating point instruction latencies and repeat rates for the processor core. In this
table, 'Latency' refers to the number of FPU cycles necessary for the first instruction to produce the result
needed by the second instruction. The “Repeat Rate”
refers to the maximum rate at which an instruction can
be executed per FPU cycle.
DS60001570C-page 34
TABLE 2-4:
FPU INSTRUCTION
LATENCIES AND REPEAT
RATES
Latency
(FPU
Cycles)
Repeat
Rate
(FPU
Cycles)
ABS.[S,D], NEG.[S,D],
ADD.[S,D], SUB.[S,D],
C.cond.[S,D], MUL.S
4
1
MADD.S, MSUB.S,
NMADD.S, NMSUB.S,
CABS.cond.[S,D]
4
1
CVT.D.S, CVT.PS.PW,
CVT.[S,D].[W,L]
4
1
CVT.S.D,
CVT.[W,L].[S,D],
CEIL.[W,L].[S,D],
FLOOR.[W,L].[S,D],
ROUND.[W,L].[S,D],
TRUNC.[W,L].[S,D]
4
1
MOV.[S,D], MOVF.[S,D],
MOVN.[S,D],
MOVT.[S,D], MOVZ.[S,D]
4
1
MUL.D
5
2
MADD.D, MSUB.D,
NMADD.D, NMSUB.D
5
2
RECIP.S
13
10
RECIP.D
26
21
RSQRT.S
17
14
RSQRT.D
36
31
DIV.S, SQRT.S
17
14
DIV.D, SQRT.D
32
29
MTC1, DMTC1, LWC1,
LDC1, LDXC1, LUXC1,
LWXC1
4
1
MFC1, DMFC1, SWC1,
SDC1, SDXC1, SUXC1,
SWXC1
1
1
Op code
Legend: S = Single D = Double
W = Word L = Long word
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
The FPU implements a high-performance 7-stage
pipeline:
• Decode, register read and unpack (FR stage)
• Multiply tree - double pumped for double (M1
stage)
• Multiply complete (M2 stage)
• Addition first step (A1 stage)
• Addition second and final step (A2 stage)
• Packing to IEEE format (FP stage)
• Register writeback (FW stage)
The FPU implements a bypass mechanism that allows
the result of an operation to be forwarded directly to the
instruction that needs it without having to write the
result to the FPU register and then read it back.
Table 2-5 lists the Coprocessor 1 Registers for the
FPU.
TABLE 2-5:
FPU (CP1) REGISTERS
Register Register
Number
Name
Function
0
FIR
Floating Point implementation
register. Contains information
that identifies the FPU.
25
FCCR
Floating Point condition codes
register.
26
FEXR
Floating Point exceptions
register.
28
FENR
Floating Point enables register.
31
FCSR
Floating Point Control and
Status register.
2019-2020 Microchip Technology Inc.
2.2
Power Management
The processor core offers a number of power management features, including low-power design, active power
management and power-down modes of operation. The
core is a static design that supports slowing or halting
the clocks, which reduces system power consumption
during Idle periods.
2.2.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see 31.0 “PowerSaving Features”.
2.2.2
LOCAL CLOCK GATING
The majority of the power consumed by the processor
core is in the clock tree and clocking registers. The
PIC32MK family makes extensive use of local gatedclocks to reduce this dynamic power consumption.
2.3
EJTAG Debug Support
The processor core provides for an Enhanced JTAG
(EJTAG) interface for use in the software debug of
application and kernel code. In addition to standard
User mode and Kernel modes of operation, the processor core provides a Debug mode that is entered after a
debug exception (derived from a hardware breakpoint,
single-step exception, etc.) is taken and continues until
a Debug Exception Return (DERET) instruction is
executed. During this time, the processor executes the
debug exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for transferring test data in and out of the core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification specify which
registers are selected and how they are used.
DS60001570C-page 35
PIC32MK GPG/MCJ with CAN FD Family
2.4
MIPS DSP ASE Extension
The MIPS DSP Application-Specific Extension
Revision 2 is an extension to the MIPS32 architecture.
This extension comprises new integer instructions and
states that include new HI/LO accumulator register
pairs and a DSP control register. This extension is
crucial in a wide range of DSP, multimedia, and DSPlike algorithms covering Audio and Video processing
applications. The extension supports native fractional
format data type operations, register Single Instruction
Multiple Data (SIMD) operations, such as add,
subtract, multiply, and shift. In addition, the extension
includes the following features that are essential in
making DSP algorithms computationally efficient:
•
•
•
•
Support for multiplication of complex operands
Variable bit insertion and extraction
Implementation and use of virtual circular buffers
Arithmetic saturation and overflow handling
support
• Zero cycle overhead saturation and rounding
operations
DS60001570C-page 36
2.5
microMIPS ISA
The processor core supports the microMIPS ISA,
which contains all MIPS32 ISA instructions (except for
branch-likely instructions) in a new 32-bit encoding
scheme, with some of the commonly used instructions
also available in 16-bit encoded format. This ISA
improves code density through the additional 16-bit
instructions while maintaining a performance similar to
MIPS32 mode. In microMIPS mode, 16-bit or 32-bit
instructions will be fetched and recoded to legacy
MIPS32 instruction opcodes in the pipeline’s I stage, so
that the processor core can have the same microAptiv
MPU microarchitecture. Because the microMIPS
instruction stream can be intermixed with 16-bit halfword or 32-bit word size instructions on halfword or
word boundaries, additional logic is in place to address
the word misalignment issues, thus minimizing
performance loss.
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
2.6
MIPS32® microAptiv™ MCU Core
Configuration
Register 2-1 through Register 2-5 show the default
configuration of the MIPS32 microAptiv MCU core,
which is included on the PIC32MK GPG/MCJ with CAN
FD Family of devices.
REGISTER 2-1:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG: CONFIGURATION REGISTER; CP0 REGISTER 16, SELECT 0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
r-1
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
ISP
R-0
R-0
R-1
R-0
U-0
R-1
R-0
R-0
DSP
UDI
SB
MDU
—
R-0
R-0
R-0
R-0
R-0
BE
AT
MM
R-1
AR
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
BM
R-0
R-1
U-0
U-0
—
—
K0
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
Bit
24/16/8/0
x = Bit is unknown
Reserved: This bit is hardwired to ‘1’ to indicate the presence of the Config1 register.
bit 30-25 Unimplemented: Read as ‘0’
bit 24
ISP: Instruction Scratch Pad RAM bit
0 = Instruction Scratch Pad RAM is not implemented
bit 23
DSP: Data Scratch Pad RAM bit
0 = Data Scratch Pad RAM is not implemented
bit 22
UDI: User-defined bit
0 = CorExtend User-Defined Instructions are not implemented
bit 21
SB: SimpleBE bit
1 = Only Simple Byte Enables are allowed on the internal bus interface
bit 20
MDU: Multiply/Divide Unit bit
0 = Fast, high-performance MDU
bit 19
Unimplemented: Read as ‘0’
bit 18-17 MM: Merge Mode bits
10 = Merging is allowed
bit 16
BM: Burst Mode bit
0 = Burst order is sequential
bit 15
BE: Endian Mode bit
0 = Little-endian
bit 14-13 AT: Architecture Type bits
00 = MIPS32
bit 12-10 AR: Architecture Revision Level bits
001 = MIPS32 Release 2
bit 9-3
Unimplemented: Read as ‘0’
2019-2020 Microchip Technology Inc.
DS60001570C-page 37
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 2-1:
bit 2-0
CONFIG: CONFIGURATION REGISTER; CP0 REGISTER 16, SELECT 0
(CONTINUED)
K0: Kseg0 Coherency Algorithm bits
000 = Reserved
001 = Reserved
010 = Instruction Prefetch Uncached (Default)
011 = Instruction Prefetch cached (Recommended)
100 = Reserved
•
•
•
111 = Reserved
DS60001570C-page 38
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 2-2:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG1: CONFIGURATION REGISTER 1; CP0 REGISTER 16, SELECT 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
r-1
R-0
R-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
U-0
—
MMUSIZE
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R-1
R-1
R-0
R-1
R-1
—
—
—
PC
WR
CA
EP
FP
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
U-0
x = Bit is unknown
Reserved: This bit is hardwired to a ‘1’ to indicate the presence of the Config2 register.
bit 30-25 MMUSIZE: MMU Size bits
Note:
This bit field is read as ‘0’ decimal in the fixed table-based MMU core, as no TLB is present.
bit 24-5
Unimplemented: Read as ‘0’
bit 4
PC: Performance Counter bit
1 = The processor core contains Performance Counters
bit 3
WR: Watch Register Presence bit
1 = No Watch registers are present
bit 2
CA: Code Compression Implemented bit
0 = No MIPS16e® present
bit 1
EP: EJTAG Present bit
1 = Core implements EJTAG
bit 0
FP: Floating Point Unit bit
1 = Floating Point Unit is present
2019-2020 Microchip Technology Inc.
DS60001570C-page 39
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 2-3:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG3: CONFIGURATION REGISTER 3; CP0 REGISTER 16, SELECT 3
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
R-1
R-0
R-0
R-0
R-1
R/W-y
MCU
ISAONEXC(1)
U-0
R-1
—
R-y
ISA
IPLW
R-y
(1)
MMAR
R-1
R-1
R-1
R-1
ULRI
RXI
DSP2P
DSPP
—
ITL
U-0
R-1
R-1
R-0
R-1
U-0
U-0
R-0
—
VEIC
VINT
SP
CDMM
—
—
TL
Legend:
r = Reserved bit
y = Value set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
Reserved: This bit is hardwired as ‘1’ to indicate the presence of the Config4 register
bit 30-23 Unimplemented: Read as ‘0’
bit 22-21 IPLW: Width of the Status IPL and Cause RIPL bits
01 = IPL and RIPL bits are 8-bits in width
bit 20-18 MMAR: microMIPS Architecture Revision Level bits
000 = Release 1
bit 17
MCU: MIPS® MCU™ ASE Implemented bit
1 = MCU ASE is implemented
bit 16
ISAONEXC: ISA on Exception bit(1)
1 = microMIPS is used on entrance to an exception vector
0 = MIPS32 ISA is used on entrance to an exception vector
bit 15-14 ISA: Instruction Set Availability bits(1)
11 = Both MIPS32 and microMIPS are implemented; microMIPS is used when coming out of reset
10 = Both MIPS32 and microMIPS are implemented; MIPS32 ISA used when coming out of reset
bit 13
ULRI: UserLocal Register Implemented bit
1 = UserLocal Coprocessor 0 register is implemented
bit 12
RXI: RIE and XIE Implemented in PageGrain bit
1 = RIE and XIE bits are implemented
bit 11
DSP2P: MIPS DSP ASE Revision 2 Presence bit
1 = DSP Revision 2 is present
bit 10
DSPP: MIPS DSP ASE Presence bit
1 = DSP is present
bit 9
Unimplemented: Read as ‘0’
bit 8
ITL: Indicates that iFlowtrace® hardware is present
1 = The iFlowtrace® 2.0 hardware is implemented in the core
bit 7
Unimplemented: Read as ‘0’
bit 6
VEIC: External Vector Interrupt Controller bit
1 = Support for an external interrupt controller is implemented.
bit 5
VINT: Vector Interrupt bit
1 = Vector interrupts are implemented
bit 4
SP: Small Page bit
0 = 4 KB page size
Note 1:
These bits are set based on the value of the BOOTISA Configuration bit (DEVCFG0).
DS60001570C-page 40
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 2-3:
CONFIG3: CONFIGURATION REGISTER 3; CP0 REGISTER 16, SELECT 3
(CONTINUED)
bit 3
CDMM: Common Device Memory Map bit
1 = CDMM is implemented
bit 2-1
Unimplemented: Read as ‘0’
bit 0
TL: Trace Logic bit
0 = Trace logic is not implemented
Note 1:
These bits are set based on the value of the BOOTISA Configuration bit (DEVCFG0).
2019-2020 Microchip Technology Inc.
DS60001570C-page 41
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 2-4:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG4: CONFIGURATION REGISTER 4; CP0 REGISTER 16, SELECT 4
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
M
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
KScr Exist
R/W-0
R/W-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
—
—
—
Legend:
r = Reserved
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
M: Config5 Register Present bit
1 = Config5 register is present
0 = Config5 register is not present
bit 30-24 Unimplemented: Read as ‘0’
bit 23-16 KScr Exist: Number of Scratch Registers Available to Kernel Mode bits
Indicates how many scratch registers are available to Kernel mode software within CP0 Register 31.
Each bit represents a select for Coprocessor0 Register 31. Bit 16 represents Select 0. Bit 23 represents
Select 7. If the bit is set, the associated scratch register is implemented and is available for Kernel mode
software.
Note:
bit 15-0
These bits are read-only, and this field is all zeros on these products, as is read as ‘0’.
Reserved: Read/write as ‘0’
DS60001570C-page 42
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 2-5:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG5: CONFIGURATION REGISTER 5; CP0 REGISTER 16, SELECT 5
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-1
—
—
—
—
—
—
—
NF
Legend:
r = Reserved
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-1
Unimplemented: Read as ‘0’
bit 0
NF: Nested Fault bit
1 = Nested Fault feature is implemented
REGISTER 2-6:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
CONFIG7: CONFIGURATION REGISTER 7; CP0 REGISTER 16, SELECT 7
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
WII
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
WII: Wait IE Ignore bit
1 = Indicates that this processor will allow an interrupt to unblock a WAIT instruction
bit 30-0
Unimplemented: Read as ‘0’
2019-2020 Microchip Technology Inc.
DS60001570C-page 43
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 2-7:
Bit
Range
31:24
23:16
15:8
7:0
FIR: FLOATING POINT IMPLEMENTATION REGISTER; CP1 REGISTER 0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
U-0
U-0
—
—
Bit
24/16/8/0
U-0
R-1
U-0
U-0
U-0
R-1
—
UFRP
—
—
—
FC
R-1
R-1
R-1
R-1
R-1
R-0
R-0
R-1
HAS2008
F64
L
W
MIPS3D
PS
D
S
R-1
R-0
R-1
R-0
R-0
R-1
R-1
R-1
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
PRID
Legend:
R = Readable bit
-n = Value at POR
REVISION
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28
UFRP: User Mode FR Switching Instruction bit
1 = User mode FR switching instructions are supported
0 = User mode FR switching instructions are not supported
bit 27-25 Unimplemented: Read as ‘0’
bit 24
FC: Full Convert Ranges bit
1 = Full convert ranges are implemented (all numbers can be converted to another type by the FPU)
0 = Full convert ranges are not implemented
bit 23
HAS008: IEEE-754-2008 bit
1 = MAC2008, ABS2008, NAN2008 bits exist within the FCSR register
0 = MAC2009, ABS2008, and NAN2008 bits do not exist within the FCSR register
bit 22
F64: 64-bit FPU bit
1 = This is a 64-bit FPU
0 = This is not a 64-bit FPU
bit 21
L: Long Fixed Point Data Type bit
1 = Long fixed point data types are implemented
0 = Long fixed point data types are not implemented
bit 20
W: Word Fixed Point data type bit
1 = Word fixed point data types are implemented
0 = Word fixed point data types are not implemented
bit 19
MIPS3D: MIPS-3D ASE bit
1 = MIPS-3D is implemented
0 = MIPS-3D is not implemented
bit 18
PS: Paired Single Floating Point data bit
1 = PS floating point is implemented
0 = PS floating point is not implemented
bit 17
D: Double-precision floating point data bit
1 = Double-precision floating point data types are implemented
0 = Double-precision floating point data types are not implemented
bit 16
S: Single-precision Floating Point Data bit
1 = Single-precision floating point data types are implemented
0 = Single-precision floating point data types are not implemented
bit 15-8 PRID: Processor Identification bits
These bits allow software to distinguish between the various types of MIPS processors. For
PIC32 devices with the MIPS32 microAptiv MCU core, this value is 0x9D.
bit 7-0
REVISION: Processor Revision Identification bits
These bits allow software to distinguish between one revision and another of the same processor type. This
number is increased on major revisions of the processor core
DS60001570C-page 44
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 2-8:
Bit
Range
31:24
23:16
15:8
7:0
FCCR: FLOATING POINT CONDITION CODES REGISTER; CP1 REGISTER 25
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
FCC
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8
Unimplemented: Read as ‘0’
bit 7-0
FCC: Floating Point Condition Code bits
These bits record the results of floating point compares and are tested for floating point conditional branches
and conditional moves.
2019-2020 Microchip Technology Inc.
DS60001570C-page 45
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 2-9: FEXR: FLOATING POINT EXCEPTIONS STATUS REGISTER; CP1 REGISTER 26
Bit
Range
31:24
23:16
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-x
R/W-x
—
—
—
—
—
—
E
V
R/W-x
R/W-x
R/W-x
U-0
U-0
U-0
U-0
U-0
—
—
—
—
R/W-x
R/W-x
U-0
U-0
U
I
—
—
CAUSE
15:8
7:0
Z
O
U
U-0
R/W-x
R/W-x
—
I
R/W-x
FLAGS
V
Z
O
CAUSE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-18 Unimplemented: Read as ‘0’
bit 17-12 CAUSE: FPU Exception Cause bits
These bits indicated the exception conditions that arise during execution of an FPU arithmetic instruction.
bit 17
E: Unimplemented Operation bit
bit 16
V: Invalid Operation bit
bit 15
Z: Divide-by-Zero bit
bit 14
O: Overflow bit
bit 13
U: Underflow bit
bit 12
I: Inexact bit
bit 11-7
Unimplemented: Read as ‘0’
bit 6-2
FLAGS: FPU Flags bits
These bits show any exception conditions that have occurred for completed instructions since the flag was
last reset by software.
bit 6
V: Invalid Operation bit
bit 4
Z: Divide-by-Zero bit
bit 4
O: Overflow bit
bit 3
U: Underflow bit
bit 2
I: Inexact bit
bit 1-0
Unimplemented: Read as ‘0’
DS60001570C-page 46
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 2-10: FENR: FLOATING POINT EXCEPTIONS AND MODES ENABLE REGISTER;
CP1 REGISTER 28
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
—
V
Z
O
U
R/W-x
U-0
U-0
U-0
U-0
R-x
R/W-x
R/W-x
—
—
—
—
FS
ENABLES
I
ENABLES
RM
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-12 Unimplemented: Read as ‘0’
bit 11-7
ENABLES: FPU Exception Enable bits
These bits control whether or not a trap is taken when an IEEE exception condition occurs for any of the five
conditions. The trap occurs when both an enable bit and its corresponding cause bit are set either during an
FPU arithmetic operation or by moving a value to the FCSR or one of its alternative representations.
bit 11
V: Invalid Operation bit
bit 10
Z: Divide-by-Zero bit
bit 9
O: Overflow bit
bit 8
U: Underflow bit
bit 7
I: Inexact bit
bit 6-3
Unimplemented: Read as ‘0’
bit 2
FS: Flush to Zero control bit
1 = Denormal input operands are flushed to zero. Tiny results are flushed to either zero or the applied format's
smallest normalized number (MinNorm) depending on the rounding mode settings.
0 = Denormal input operands result in an Unimplemented Operation exception.
bit 1-0
RM: Rounding Mode control bits
11 = Round towards Minus Infinity (– )
10 = Round towards Plus Infinity (+ )
01 = Round toward Zero (0)
00 = Round to Nearest
2019-2020 Microchip Technology Inc.
DS60001570C-page 47
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 2-11: FCSR: FLOATING POINT CONTROL AND STATUS REGISTER; CP1 REGISTER 31
Bit
Range
31:24
23:16
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R-0
R-1
R-1
R/W-x
R/W-x
FCC
FCC
FO
FN
MAC2008
ABS2008
NAN2008
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
15:8
R/W-x
R/W-x
V
Z
ENABLES
I
CAUSE
R/W-x
R/W-x
ENABLES
CAUSE
R/W-x
7:0
FS
R/W-x
V
Z
O
U
R/W-x
R/W-x
R/W-x
R/W-x
U
I
FLAGS
O
RM
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-25 FCC: Floating Point Condition Code bits
These bits record the results of floating point compares and are tested for floating point conditional
branches and conditional moves.
bit 24
FS: Flush to Zero control bit
1 = Denormal input operands are flushed to zero. Tiny results are flushed to either zero or the applied
format's smallest normalized number (MinNorm) depending on the rounding mode settings.
0 = Denormal input operands result in an Unimplemented Operation exception.
bit 23
FCC: Floating Point Condition Code bits
These bits record the results of floating point compares and are tested for floating point conditional branches
and conditional moves.
bit 22
FO: Flush Override Control bit
1 = The intermediate result is kept in an internal format, which can be perceived as having the usual
mantissa precision but with unlimited exponent precision and without forcing to a specific value or
taking an exception.
0 = Handling of Tiny Result values depends on setting of the FS bit.
bit 21
FN: Flush to Nearest Control bit
1 = Final result is rounded to either zero or 2E_min (MinNorm), whichever is closest when in Round to
Nearest (RN) rounding mode. For other rounding modes, a final result is given as if FS was set to 1.
0 = Handling of Tiny Result values depends on setting of the FS bit.
bit 20
MAC2008: Fused Multiply Add mode control bit
0 = Unfused multiply-add. Intermediary multiplication results are rounded to the destination format.
bit 19
ABS2008: Absolute value format control bit
1 = ABS.fmt and NEG.fmt instructions compliant with IEEE Standard 754-2008. The ABS and NEG functions
accept QNAN inputs without trapping.
bit 18
NAN2008: NaN Encoding control bit
1 = Quiet and signaling NaN encodings recommended by the IEEE Standard 754-2008. A quiet NaN is
encoded with the first bit of the fraction being 1 and a signaling NaN is encoded with the first bit of the
fraction being 0.
bit 17-12 CAUSE: FPU Exception Cause bits
These bits indicated the exception conditions that arise during execution of an FPU arithmetic instruction.
bit 17
E: Unimplemented Operation bit
bit 16
V: Invalid Operation bit
bit 15
Z: Divide-by-Zero bit
DS60001570C-page 48
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 2-11: FCSR: FLOATING POINT CONTROL AND STATUS REGISTER; CP1 REGISTER 31
bit 14
O: Overflow bit
bit 13
U: Underflow bit
bit 12
I: Inexact bit
bit 11-7
ENABLES: FPU Exception Enable bits
These bits control whether or not a trap is taken when an IEEE exception condition occurs for any of the
five conditions. The trap occurs when both an enable bit and its corresponding cause bit are set either
during an FPU arithmetic operation or by moving a value to the FCSR or one of its alternative
representations.
bit 11
V: Invalid Operation bit
bit 10
Z: Divide-by-Zero bit
bit 9
O: Overflow bit
bit 8
U: Underflow bit
bit 7
I: Inexact bit
bit 6-2
FLAGS: FPU Flags bits
These bits show any exception conditions that have occurred for completed instructions since the flag was
last reset by software.
bit 6
V: Invalid Operation bit
bit 5
Z: Divide-by-Zero bit
bit 4
O: Overflow bit
bit 3
U: Underflow bit
bit 2
I: Inexact bit
bit 1-0
RM: Rounding Mode control bits
11 = Round towards Minus Infinity (– )
10 = Round towards Plus Infinity (+ )
01 = Round toward Zero (0)
00 = Round to Nearest
2019-2020 Microchip Technology Inc.
DS60001570C-page 49
PIC32MK GPG/MCJ with CAN FD Family
NOTES:
DS60001570C-page 50
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
3.0
Note:
MEMORY ORGANIZATION
This data sheet summarizes the
features of the PIC32MK GPG/MCJ with
CAN FD Family of devices. It is not
intended to be a comprehensive
reference
source.
For
detailed
information, refer to Section 48.
“Memory
Organization
and
Permissions” (DS60001214), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
PIC32MK GPG/MCJ with CAN FD Family
microcontrollers provide 4 GB of unified virtual memory
address space. All memory regions, including program,
data memory, Special Function Registers (SFRs) and
Configuration registers, reside in this address space at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, PIC32MK GPG/MCJ
with CAN FD Family of devices allow execution from
data memory.
3.1
Memory Layout
PIC32MK GPG/MCJ with CAN FD Family microcontrollers implement two address schemes: virtual and physical. All hardware resources, such as program memory,
data memory and peripherals, are located at their
respective physical addresses. Virtual addresses are
exclusively used by the CPU to fetch and execute
instructions as well as access peripherals. Physical
addresses are used by bus master peripherals, such as
DMA and the Flash controller, that access memory
independently of the CPU.
The main memory maps for the PIC32MK GPG/MCJ
with CAN FD Family of devices are illustrated in
Figure 3-1 through Figure 3-2. Figure 3-3 provides
memory map information for boot Flash and boot alias.
Table 3-3 provides memory map information for SFRs.
The following are key features of this module:
• 32-bit native data width
• Separate User (KUSEG) and Kernel (KSEG0/
KSEG1) mode address space
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
runaway code
• Read/write permission access to predefined
memory regions
2019-2020 Microchip Technology Inc.
DS60001570C-page 51
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 3-1:
Note
1:
MEMORY MAP FOR DEVICES WITH 256 KB PROGRAM MEMORY AND 64 KB RAM
Memory areas are not shown to scale.
DS60001570C-page 52
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 3-2:
Note
1:
MEMORY MAP FOR DEVICES WITH 512 KB PROGRAM MEMORY AND 64 KB RAM
Memory areas are not shown to scale.
2019-2020 Microchip Technology Inc.
DS60001570C-page 53
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 3-3:
BOOT AND ALIAS
MEMORY MAP
TABLE 3-1:
Virtual Address
Peripheral
Physical Memory Map(1)
Base
0xFFFF_FFFF
CFG-PMD
CACHE
0x0800
FC-NVM
0x0A00
0x0C00
0xBF800000
DMT
0x1000
CRU
0x1200
0x1FC45800
PPS
0x1400
0x1FC457FF
HLVD
0x1800
0xBF810000
0x0000
0x1FC4_502F
DMA
0x1FC4_502C
Timer1-Timer9
0x0000
IC1-IC9
0x2000
0x1FC4_5020
0x1000
0x1FC4_501C
OC1-OC9
0x4000
DEVADC7
0x1FC4_5018
I2C1-I2C2
0x6000
DEVADC5
0x1FC4_5014
DEVADC4
0x1FC4_5010
SPI1-SPI2
DEVADC3
0x1FC4_500C
DEVADC2
0x1FC4_5008
PWM1 - PWM9
0xA000
DEVADC1
0x1FC4_5004
QEI1-QEI3
0xB200
DEVADC0
0x1FC4_5000
CMP
0xC000
CTMU
0xD000
0x1FC4_3FDF
CLC1-CLC4
0xD200
0x1FC4_3F3C
CDAC1-CDAC2
Public Test Flash
0x1FC4_4FFF
0x1FC4_4000
Configuration
Word Space
0x1FC4_3F3B
0x1FC4_0000
0x1FC3_FFFF
0x1FC0_5000
0x1FC0_4FFF
0x1FC0_4000
Configuration
Word Space
0x1FC0_3FDF
0x7000
UART1-UART2
PORTA-PORTG
CANFD1
ADC
Reserved
Boot Alias
0x0E00
ICD
EVIC
Device Serial Number
DEVSNx, x=0-3
Offset Start
0x0000
WDT
Reserved
Boot Flash 1
SFR MEMORY MAP
RTCC
SSX CTL
Note 1:
0xBF820000
0xBF840000
0xBF860000
0xBF880000
0x8000
0xC400
0x0000
0x0000
0x7000
0xBF8C0000
0x0000
0xBF8F0000
0x0000
Refer to 3.2 “System Bus Arbitration”
for important legal information.
0x1FC0_3F3C
0x1FC0_3F3B
0x1FC0_0000
Note
1:
2:
3:
4:
5:
Memory areas are not shown to scale.
Memory locations 0x1FC0_3FB0 through
0x1FC0_3FFC are used to initialize Configuration registers (Refer to 32.0 Special Features).
Refer to 3.1.1 Boot Flash Sequence and Configuration Spaces for more information.
Memory locations 0x1FC4_5020 and
0x1FC4_502C contain a unique device serial
number (Refer to 32.0 Special Features).
This configuration space cannot be used for
executing code in the upper Boot Alias.
DS60001570C-page 54
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
3.1.1
BOOT FLASH SEQUENCE AND
CONFIGURATION SPACES
Sequence space is used to identify which boot Flash is
aliased by aliased regions. If the value programmed
into the TSEQ bits of the BF1SEQ word is equal
to or greater than the value programmed into the
TSEQ bits of the BF2SEQ word, Boot Flash 1 is
aliased by the lower boot alias region, and Boot Flash
2 is aliased by the upper boot alias region. If the
TSEQ bits of the BF2SEQ word is greater than
the TSEQ bits of the BF1SEQ word, the
opposite is true (see Table 3-2 and Table 4-3 for
BFxSEQ word memory locations).
Once boot Flash memories are aliased, configuration
space located in the lower boot alias region is used as
the basis for the Configuration words, DEVSIGN0,
DEVCP0, and DEVCFGx. This means that the boot
Flash region to be aliased by lower boot alias region
memory must contain configuration values in the
appropriate memory locations.
Note:
3.1.2
Use only Quad Word program operation
(NVMOP = 0010) when programming data into the sequence and
configuration spaces.
ALTERNATE SEQUENCE AND
CONFIGURATION WORDS
Every word in the configuration space and sequence
space has an associated alternate word (designated by
the letter A as the first letter in the name of the word).
During device start-up, primary words are read, and if
uncorrectable ECC errors are found, the BCFGERR
(RCON) flag is set and alternate words are used.
If uncorrectable ECC errors are found in primary and
alternate words, the BCFGFAIL (RCON) flag is
set and the default configuration is used.
2019-2020 Microchip Technology Inc.
DS60001570C-page 55
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
3F40 ABF1DEVCFG3 31:16
xxxx
3F4C ABF1DEVCFG0 31:16
3FC8 BF1DEVCFG1
2019-2020 Microchip Technology Inc.
3FCC BF1DEVCFG0
3FD0 BF1DEVCP3
3FD4 BF1DEVCP2
3FD8 BF1DEVCP1
3FDC BF1DEVCP0
Legend:
xxxx
15:0
xxxx
31:16
xxxx
15:0
xxxx
31:16
xxxx
15:0
xxxx
31:16
xxxx
15:0
xxxx
31:16
xxxx
15:0
3FC4 BF1DEVCFG2
16/0
xxxx
15:0
3FC0 BF1DEVCFG3
17/1
xxxx
3F48 ABF1DEVCFG1 31:16
3F5C ABF1DEVCP0
18/2
xxxx
15:0
3F58 ABF1DEVCP1
19/3
xxxx
3F44 ABF1DEVCFG2 31:16
3F54 ABF1DEVCP2
20/4
xxxx
15:0
3F50 ABF1DEVCP3
21/5
All Reset
Bit Range
Bits
Register
Name
Virtual Address
(BFC4_#)
BOOT FLASH 1 SEQUENCE AND CONFIGURATION WORDS SUMMARY
31:16
Note:See Table 32-1 for the bit descriptions.
xxxx
xxxx
15:0
xxxx
31:16
xxxx
15:0
xxxx
31:16
xxxx
15:0
xxxx
31:16
xxxx
15:0
xxxx
31:16
xxxx
15:0
xxxx
31:16
xxxx
15:0
xxxx
31:16
xxxx
15:0
xxxx
31:16
xxxx
15:0
xxxx
x = unknown value on Reset; — = Reserved, read as ‘1’. Reset values are shown in hexadecimal.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 56
TABLE 3-2:
PIC32MK GPG/MCJ with CAN FD Family
3.2
System Bus Arbitration
Note:
As shown in the PIC32MK GPG/MCJ with CAN FD
Family Block Diagram (see Figure 1-1), there are multiple initiator modules (I1 through I13) in the system that
can access various target modules (T1 through T14).
Table 3-3 illustrates which initiator can access which
target. The System Bus supports simultaneous access
to targets by initiators, so long as the initiators are
accessing different targets. The System Bus will perform arbitration, if multiple initiators attempt to access
the same target.
The
System
Bus
interconnect
implements one or more instantiations of
the SonicsSX® interconnect from Sonics,
Inc. This document contains materials
that are (c) 2003-2015 Sonics, Inc., and
that constitute proprietary information of
Sonics, Inc. SonicsSX is a registered
trademark of Sonics, Inc. All such
materials and trademarks are used under
license from Sonics, Inc.
TABLE 3-3:
INITIATORS TO TARGETS ACCESS ASSOCIATION
Target
#
Initiator ID:
1
2
3
4
5
6
7
10
Name:
CPU IS
CPU ID
DMA
Read
DMA
Write
Flash
ICD
JTAG
ADC
Mem.
CAN1
1
Program Flash
2
Data
X
X
3
Peripheral Module
4
RAM Bank 1
X
X
X
X
X
X
X
X
5
RAM Bank 2
X
X
X
X
X
X
X
X
7
Peripheral Bus 1:
DMT, CVR,
PPS Input,
PPS Output,
WDT
X
X
X
X
Peripheral Bus 2:
Timer1-Timer9,
I2C1-I2C2,
SPI1-SPI2,
UART1-UART2,
OC1-OC9,
IC1-IC9,
PMP,
Comparator 1-
Comparator 5,
Op amp 1-3,5
PWM1-PWM9
QEI1-QEI2
X
X
X
X
9
Peripheral Bus 3:
CDAC1-CDAC2
X
X
X
X
10
Peripheral Bus 4:
PORTA-PORTG
X
X
X
X
11
Peripheral Bus 5:
CAN1
ADC 0-5, 7
X
X
Peripheral Bus 6:
RTCC
X
X
8
14
2019-2020 Microchip Technology Inc.
X
DS60001570C-page 57
PIC32MK GPG/MCJ with CAN FD Family
The System Bus arbitration scheme implements a nonprogrammable, Least Recently Serviced (LRS) priority,
which provides Quality Of Service (QOS) for most
initiators. However, some initiators can use Fixed High
Priority (HIGH) arbitration to guarantee their access to
data.
3.3
The arbitration scheme for the available initiators is
shown in Table 3-4.
The System Bus divides the entire memory space into
fourteen target regions and permits access to each
target by initiators through permission groups. Four
Permission Groups (0 through 3) can be assigned to
each initiator. Each permission group is independent
of the others and can have exclusive or shared
access to a region.
TABLE 3-4:
INITIATOR ID AND QOS
Name
ID
QOS
CPU-IS
1
LRS
CPU-DS
2
LRS
DMA Read
3
LRS
DMA Write
4
LRS
Flash Controller
5
HIGH
ICD-JTAG
6
LRS
ADC
7
LRS
CAN1
10
LRS
Permission Access and System
Bus Registers
The System Bus on PIC32MK GPG/MCJ with CAN
FD Family of devices provides access control capabilities for the transaction initiators on the System Bus.
Using the CFGPG register (see Register 32-8 in
32.0 “Special Features”), Boot firmware can assign a
permission group to each initiator, which can make
requests on the System Bus.
The available targets and their regions, as well as the
associated control registers to assign protection, are
described and listed in Table 3-5.
Register 3-1 through Register 3-9 are used for setting
and controlling access permission groups and regions.
To change these registers, they must be unlocked in
hardware. The register lock is controlled by the
PGLOCK Configuration bit (CFGCON). Setting
the PGLOCK bit prevents writes to the control registers and clearing the PGLOCK bit allows writes.
To set or clear the PGLOCK bit, an unlock sequence
must be executed. Refer to Section 42. “Oscillators
with Enhanced PLL” (DS60001250) in the “PIC32
Family Reference Manual” for details.
DS60001570C-page 58
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 3-5:
SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS
SBTxREGy Register
Target
Number
0
Target Description
Name
Region
Physical
Start
Address
SBT0REG1 Region 1 1F8F8000
32 KB
SBT1REG0 Region 0 1D000000
1
Legend:
Name
0
SBT0RD0
1,1,1,1
SBT0WR0
1,1,1,1
3
SBT0RD1
0,0,0,1
SBT0WR1
0,0,0,1
0
SBT1RD0
1,1,1,1
SBT1WR0
0,0,0,0
4 KB
2
SBT1RD2
0,0,0,1
SBT1WR2
0,0,0,0
4 KB
2
SBT1RD3
0,0,0,1
SBT1WR3
0,0,0,0
4 KB
2
SBT1RD4
0,0,0,1
SBT1WR4
0,0,0,0
SBT1REG5 Region 5 1FC64000
4 KB
2
SBT1RD5
0,0,0,1
SBT1WR5
0,0,0,0
0
SBT2RD0
1,1,1,1
SBT2WR0
0,0,0,0
Flash Memory (CPU data)
Program Flash
SBT2REG2 Region 2 1FC04000
4 KB
2
SBT2RD2
0,0,0,1
SBT2WR2
0,0,0,0
SBT2REG3 Region 3 1FC24000
4 KB
2
SBT2RD3
0,0,0,1
SBT2WR3
0,0,0,0
SBT2REG4 Region 4 1FC44000
4 KB
2
SBT2RD4
0,0,0,1
SBT2WR4
0,0,0,0
SBT2REG5 Region 5 1FC64000
4 KB
2
SBT2RD5
0,0,0,1
SBT2WR5
0,0,0,0
0
SBT3RD0
1,1,1,1
SBT3WR0
0,0,0,0
SBT3REG0 Region 0 1D000000
3
Name
Write
Permission
(Group3,
Group2,
Group1,
Group0)
Flash Memory (CPU Instruction) SBT1REG2 Region 2 1FC04000
Program Flash
SBT1REG3 Region 3 1FC24000
Boot Flash Prefetch
SBT1REG4 Region 4 1FC44000
SBT2REG0 Region 0 1D000000
2
SBTxWRy Register
Read
Permission
(Group3,
Group2,
Group1,
Group0)
Region Priority
Size
Level
SBT0REG0 Region 0 1F8F0000
System Bus
SBTxRDy Register
Flash Memory (peripheral)
Program Flash
R = Read;
SBT3REG2 Region 2 1FC04000
4 KB
2
SBT3RD2
0,0,0,1
SBT3WR2
0,0,0,0
SBT3REG3 Region 3 1FC24000
4 KB
2
SBT3RD3
0,0,0,1
SBT3WR3
0,0,0,0
SBT3REG4 Region 4 1FC44000
4 KB
2
SBT3RD4
0,0,0,1
SBT3WR4
0,0,0,0
SBT3REG5 Region 5 1FC64000
4 KB
2
SBT3RD5
0,0,0,1
SBT3WR5
0,0,0,0
R/W = Read/Write; ‘x’ in a register name = 0-13; ‘y’ in a register name = 0-8.
2019-2020 Microchip Technology Inc.
DS60001570C-page 59
Virtual Address
(BF8F_#)
Register
Name
Bit Range
SYSTEM BUS REGISTER MAP
0510
SBFLAG
31:16
15:0
Virtual Address
(BF8F_#)
Register
Name
8020
SBT0ELOG1
8028
8030
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T3PGV
—
T2PGV
—
T1PGV
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
0000
—
0000
T0PGV 0000
SYSTEM BUS TARGET 0 REGISTER MAP
SBT0ELOG2
SBT0ECON
SBT0ECLRS
SBT0REG0
8050
SBT0RD0
8058
SBT0WR0
8060
SBT0REG1
DS60001570C-page 60
8070
SBT0RD1
8078
SBT0WR1
Legend:
Note:
Bit Range
Bits
8038 SBT0ECLRM
8040
30/14
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-7:
8024
31/15
All
Resets
Legend:
16/0
All
Resets
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
REGION
—
CMD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
0000
31:16
—
GROUP
BASE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
15:0
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 3-5 for the actual reset values.
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
0000
CLEAR 0000
xxxx
SIZE
31:16
31:16
0000
CLEAR 0000
BASE
15:0
0000
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 3-6:
Virtual Address
(BF8F_#)
Register
Name
8420
SBT1ELOG1
8424
8428
8430
SBT1ELOG2
SBT1ECON
SBT1ECLRS
SBT1REG0
8450
SBT1RD0
8458
SBT1WR0
8480
SBT1REG2
8490
SBT1RD2
8498
SBT1WR2
84A0
SBT1REG3
2019-2020 Microchip Technology Inc.
84B0
SBT1RD3
84B8
SBT1WR3
84C0
SBT1REG4
84D0
SBT1RD4
84D8
SBT1WR4
Legend:
Note:
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
All
Resets
Bit Range
Bits
8438 SBT1ECLRM
8440
SYSTEM BUS TARGET 1 REGISTER MAP
—
—
0000
CMD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
0000
31:16
—
GROUP
BASE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 3-5 for the actual reset values.
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
0000
CLEAR 0000
xxxx
SIZE
31:16
31:16
0000
CLEAR 0000
BASE
15:0
0000
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 61
TABLE 3-8:
Virtual Address
(BF8F_#)
Register
Name
84E0
SBT1REG5
SYSTEM BUS TARGET 1 REGISTER MAP (CONTINUED)
84F0
SBT1RD5
84F8
SBT1WR5
Legend:
Note:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
PRI
—
31:16
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
xxxx
—
—
—
xxxx
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 3-5 for the actual reset values.
All
Resets
Bit Range
Bits
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
DS60001570C-page 62
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 3-8:
8824
8828
8830
SBT2ELOG2
SBT2ECON
SBT2ECLRS
8838 SBT2ECLRM
8840
SBT2REG0
8850
SBT2RD0
8858
SBT2WR0
8860
SBT2REG1
2019-2020 Microchip Technology Inc.
8870
SBT2RD1
8878
SBT2WR1
8880
SBT2REG2
8890
SBT2RD2
8898
SBT2WR2
Legend:
Note:
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
All
Resets
Register
Name
SBT2ELOG1
Bit Range
Virtual Address
(BF8F_#)
8820
SYSTEM BUS TARGET 2 REGISTER MAP
—
—
0000
CMD
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
—
GROUP
BASE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 3-5 for the actual reset values.
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
0000
CLEAR 0000
xxxx
SIZE
31:16
31:16
0000
CLEAR 0000
BASE
15:0
0000
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 63
TABLE 3-9:
8C24 SBT3ELOG2
8C28
SBT3ECON
8C30 SBT3ECLRS
8C38 SBT3ECLRM
8C40
SBT3REG0
8C50
SBT3RD0
8C58
SBT3WR0
8C60
SBT3REG1
2019-2020 Microchip Technology Inc.
8C70
SBT3RD1
8C78
SBT3WR1
8C80
SBT3REG2
8C90
SBT3RD2
8C98
SBT3WR2
Legend:
Note:
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
All
Resets
Bit Range
Register
Name
Virtual Address
(BF8F_#)
8C20 SBT3ELOG1
SYSTEM BUS TARGET 3 REGISTER MAP
—
—
0000
CMD
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
—
—
GROUP
BASE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
PRI
—
31:16
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 3-5 for the actual reset values.
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
0000
CLEAR 0000
xxxx
SIZE
31:16
31:16
0000
CLEAR 0000
BASE
15:0
0000
—
—
—
xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
—
—
—
xxxx
GROUP2 GROUP1 GROUP0 xxxx
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 64
TABLE 3-10:
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 3-1:
Bit
Range
31:24
23:16
15:8
7:0
SBFLAG: SYSTEM BUS STATUS FLAG REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
—
—
—
—
T3PGV
T2PGV
T1PGV
T0PGV
Legend:
R = Readable bit
-n = Value at POR
bit 31-4
bit 3-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Unimplemented: Read as ‘0’
T3PGV:T0PGV: Target Permission Group Violation Status bits
Refer to Table 3-5 for the list of available targets and their descriptions.
1 = Target is reporting a Permission Group (PG) violation
0 = Target is not reporting a PG violation
Note:
All errors are cleared at the source (i.e., SBTxELOG1, SBTxELOG2, SBTxECLRS, or SBTxECLRM
registers).
2019-2020 Microchip Technology Inc.
DS60001570C-page 65
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 3-2:
Bit
Range
SBTxELOG1: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 1
(‘x’ = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0, C
U-0
U-0
U-0
R/W-0, C
R/W-0, C
R/W-0, C
R/W-0, C
MULTI
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
31:24
23:16
15:8
CODE
U-0
INITID
7:0
REGION
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U-0
R-0
—
CMD
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
bit 31
MULTI: Multiple Permission Violations Status bit
This bit is cleared by writing a ‘1’.
1 = Multiple errors have been detected
0 = No multiple errors have been detected
bit 30-28 Unimplemented: Read as ‘0’
bit 27-24 CODE: Error Code bits
Indicates the type of error that was detected. These bits are cleared by writing a ‘1’.
1111 = Reserved
1101 = Reserved
•
•
•
0011 = Permission violation
0010 = Reserved
0001 = Reserved
0000 = No error
bit 23-16 Unimplemented: Read as ‘0’
bit 15-8 INITID: Initiator ID of Requester bits
11111111 = Reserved
•
•
•
00001111 = Reserved
00001110 = Reserved
00001101 = Reserved
00001100 = Reserved
00001011 = Reserved
00001010 = CAN1
00001001 = Reserved
00001000 = Reserved
00000111 = ADC0-ADC5, ADC7
00000110 = Reserved
00000101 = Flash Controller
00000100 = DMA Read
00000011 = DMA Read
00000010 = CPU (CPUPRI (CFGCON) = 1)
00000001 = CPU (CPUPRI (CFGCON) = 0)
00000000 = Reserved
Note:
Refer to Table 3-5 for the list of available targets and their descriptions.
DS60001570C-page 66
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 3-2:
bit 7-4
bit 3
bit 2-0
Note:
SBTxELOG1: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 1
(‘x’ = 0-3) (CONTINUED)
REGION: Requested Region Number bits
1111 - 0000 = Target’s region that reported a permission group violation
Unimplemented: Read as ‘0’
CMD: Transaction Command of the Requester bits
111 = Reserved
110 = Reserved
101 = Write (a non-posted write)
100 = Reserved
011 = Read (a locked read caused by a Read-Modify-Write transaction)
010 = Read
001 = Write
000 = Idle
Refer to Table 3-5 for the list of available targets and their descriptions.
2019-2020 Microchip Technology Inc.
DS60001570C-page 67
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 3-3:
Bit
Range
31:24
23:16
15:8
7:0
SBTxELOG2: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 2 (‘x’ = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R-0
R-0
—
—
—
—
—
—
GROUP
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-3
Unimplemented: Read as ‘0’
bit 1-0
GROUP: Requested Permissions Group bits
11 = Reserved
10 = Reserved
01 = Group 1
00 = Group 0 (default group of CPU at Reset)
Note:
Refer to Table 3-5 for the list of available targets and their descriptions.
REGISTER 3-4:
Bit
Range
31:24
23:16
15:8
7:0
SBTxECON: SYSTEM BUS TARGET ‘x’ ERROR CONTROL REGISTER
(‘x’ = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
ERRP
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-25 Unimplemented: Read as ‘0’
bit 24
ERRP: Error Control bit
1 = Report protection group violation errors
0 = Do not report protection group violation errors
bit 23-0
Unimplemented: Read as ‘0’
Note:
Refer to Table 3-5 for the list of available targets and their descriptions.
DS60001570C-page 68
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 3-5:
Bit
Range
31:24
23:16
15:8
7:0
SBTxECLRS: SYSTEM BUS TARGET ‘x’ SINGLE ERROR CLEAR REGISTER
(‘x’ = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
CLEAR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-1
Unimplemented: Read as ‘0’
bit 0
CLEAR: Clear Single Error on Read bit
A single error as reported through SBTxELOG1 and SBTxELOG2 is cleared by a read of this register.
Note:
Refer to Table 3-5 for the list of available targets and their descriptions.
REGISTER 3-6:
Bit
Range
31:24
23:16
15:8
7:0
SBTxECLRM: SYSTEM BUS TARGET ‘x’ MULTIPLE ERROR CLEAR REGISTER
(‘x’ = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
CLEAR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-1
Unimplemented: Read as ‘0’
bit 0
CLEAR: Clear Multiple Errors on Read bit
Multiple errors as reported through SBTxELOG1 and SBTxELOG2 is cleared by a read of this register.
Note:
Refer to Table 3-5 for the list of available targets and their descriptions.
2019-2020 Microchip Technology Inc.
DS60001570C-page 69
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 3-7:
Bit
Range
31:24
23:16
15:8
7:0
SBTxREGy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ REGISTER
(‘x’ = 0-3; ‘y’ = 0-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W0
R/W-0
R/W0
R/W-0
R/W0
R/W-0
R/W0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
U-0
PRI
—
R/W-0
U-0
U-0
U-0
—
—
—
BASE
R/W-0
BASE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BASE
R/W-0
SIZE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-10 BASE: Region Base Address bits
bit 9
PRI: Region Priority Level bit
1 = Level 2
0 = Level 1
bit 8
Unimplemented: Read as ‘0’
bit 7-3
SIZE: Region Size bits
Permissions for a region are only active is the SIZE is non-zero.
11111 = Region size = 2(SIZE – 1) x 1024 (bytes)
•
•
•
00001 = Region size = 2(SIZE – 1) x 1024 (bytes)
00000 = Region is not present
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
2:
Refer to Table 3-5 for the list of available targets and their descriptions.
For some target regions, certain bits in this register are read-only with preset values. See Table 3-5 for
more information.
DS60001570C-page 70
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 3-8:
Bit
Range
31:24
23:16
15:8
7:0
SBTxRDy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ READ PERMISSIONS
REGISTER (‘x’ = 0-3; ‘y’ = 0-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R-1
R-1
R-1
R-1
—
—
—
—
GROUP3
GROUP2
GROUP1
GROUP0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-4
Unimplemented: Read as ‘0’
bit 3
GROUP3: Group 3 Read Permissions bits
1 = Privilege Group 3 has read permission
0 = Privilege Group 3 does not have read permission
bit 2
GROUP2: Group 2 Read Permissions bits
1 = Privilege Group 2 has read permission
0 = Privilege Group 2 does not have read permission
bit 1
GROUP1: Group 1 Read Permissions bits
1 = Privilege Group 1 has read permission
0 = Privilege Group 1 does not have read permission
bit 0
GROUP0: Group 0 Read Permissions bits
1 = Privilege Group 0 has read permission
0 = Privilege Group 0 does not have read permission
Note 1:
2:
Refer to Table 3-5 for the list of available targets and their descriptions.
For some target regions, certain bits in this register are read-only with preset values. See Table 3-5 for
more information.
2019-2020 Microchip Technology Inc.
DS60001570C-page 71
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 3-9:
Bit
Range
31:24
23:16
15:8
7:0
SBTxWRy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ WRITE PERMISSIONS
REGISTER (‘x’ = 0-3; ‘y’ = 0-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
—
GROUP3
GROUP2
GROUP1
GROUP0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-4
Unimplemented: Read as ‘0’
bit 3
GROUP3: Group 3 Write Permissions bits
1 = Privilege Group 3 has write permission
0 = Privilege Group 3 does not have write permission
bit 2
GROUP2: Group 2 Write Permissions bits
1 = Privilege Group 2 has write permission
0 = Privilege Group 2 does not have write permission
bit 1
GROUP1: Group 1 Write Permissions bits
1 = Privilege Group 1 has write permission
0 = Privilege Group 1 does not have write permission
bit 0
GROUP0: Group 0 Write Permissions bits
1 = Privilege Group 0 has write permission
0 = Privilege Group 0 does not have write permission
Note 1:
2:
Refer to Table 3-5 for the list of available targets and their descriptions.
For some target regions, certain bits in this register are read-only with preset values. See Table 3-5 for
more information.
DS60001570C-page 72
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
4.0
Note:
FLASH PROGRAM MEMORY
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 52. “Flash
Program Memory” (DS60001193), which
is available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
PIC32MK GPG/MCJ with CAN FD Family of devices
contain an internal Flash program memory for
executing user code, which includes the following features:
• Write protection for program and boot Flash
• ECC support
RTSP is performed by software executing from either
Flash or RAM memory. For information about RTSP
techniques, refer to Section 52. “Flash Program
Memory” (DS60001193) in the “PIC32 Family
Reference Manual”.
EJTAG is performed using the EJTAG port of the
device and an EJTAG capable programmer.
ICSP is performed using a serial data connection to the
device and allows much faster programming times than
RTSP.
The EJTAG and ICSP methods are described in the
“PIC32
Flash
Programming
Specification”
(DS60001145), which is available for download from
the Microchip website.
Note:
In PIC32MK GPG/MCJ with CAN FD
Family of devices, the Flash page size is
1024 Instruction Words and the row size is
128 Instruction Words.
There are three methods by which the user can
program this memory:
• Run-Time Self-Programming (RTSP)
• EJTAG Programming
• In-Circuit Serial Programming (ICSP)
2019-2020 Microchip Technology Inc.
DS60001570C-page 73
Flash Control Registers
Register
Name
FLASH CONTROLLER REGISTER MAP
Virtual Address
(BF80_#)
TABLE 4-1:
0A00
NVMCON(1)
0A10
NVMKEY
(1)
0A20 NVMADDR
0A30
0A40
0A50
NVMDATA0
NVMDATA1
NVMDATA2
0A60
NVMDATA3
0A70
NVMSRC
ADDR
(1)
0A80
NVMPWP
0A90
NVMBWP(1)
0AA0 NVMCON2(1)
Legend:
Note
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
WR
WREN
WRERR
LVDERR
—
—
—
—
—
—
—
—
31:16
31:16
31:16
0000
0000
0000
0000
NVMDATA0
15:0
31:16
0000
0000
NVMDATA1
15:0
31:16
0000
0000
NVMDATA2
15:0
31:16
0000
0000
NVMDATA3
15:0
31:16
0000
0000
NVMSRCADDR
15:0
31:16 PWPULOCK
—
—
—
—
—
—
0000
—
15:0
PWP
8000
PWP
—
15:0 LBWPULOCK
31:16
15:0
0000
NVMADDR
15:0
—
—
—
—
—
—
—
—
LBWP4
LBWP3
LBWP2
LBWP1
—
—
—
—
—
ERETRY
ERSCNT
—
—
CREAD1 VREAD1
—
—
0000
—
—
—
—
—
—
—
0000
—
—
UBWP4
UBWP3
UBWP2
UBWP1
UBWP0
9FDF
—
—
—
—
—
—
—
001F
SWAPLOCK
—
—
—
—
—
—
0000
LBWP0 UBWPULOCK
—
0000
0000
NVMKEY
15:0
31:16
NVMOP
All Resets
Bit Range
Bits
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:This register has corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more information.
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 74
4.1
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 4-1:
Bit
Range
31:24
23:16
15:8
7:0
NVMCON: PROGRAMMING CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
R/W-0, HC
(1)
WR
Bit
Bit
29/21/13/5 28/20/12/4
—
R/W-0
(1)
WREN
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R-0, HS, HC
(1)
R-0, HS, HC
(1)
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
WRERR
LVDERR
U-0
U-0
U-0
U-0
—
—
—
—
NVMOP
Legend:
HS = Hardware Set
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
WR: Write Control bit(1)
This bit cannot be cleared and can be set only when WREN = 1 and the unlock sequence has been
performed.
1 = Initiate a Flash operation
0 = Flash operation is complete or inactive
bit 14
WREN: Write Enable bit(1)
1 = Enable writes to the WR bit and disables writes to the NVMOP bits
0 = Disable writes to WR bit and enables writes to the NVMOP bits
bit 13
WRERR: Write Error bit(1)
This bit can be cleared only by setting the NVMOP bits = 0000 and initiating a Flash operation.
1 = Program or erase sequence did not complete successfully
0 = Program or erase sequence completed normally
bit 12
LVDERR: Low-Voltage Detect Error bit(1)
This bit can be cleared only by setting the NVMOP bits = 0000 and initiating a Flash operation.
1 = Low-voltage detected (possible data corruption, if WRERR is set)
0 = Voltage level is acceptable for programming
bit 11-4
Unimplemented: Read as ‘0’
Note 1:
2:
These bits are only reset by a Power-on Reset (POR) and are not affected by other reset sources.
This bit can only be modified when the WREN bit = 0, the NVMKEY unlock sequence is satisfied, and the
SWAPLOCK bits (NVMCON2) are cleared to ‘0’.
This operation results in a “No Operation” (NOP) when the Dynamic Flash ECC Configuration bits = 00
(FECCCON (DVCFG0)), which enables ECC at all times. For all other FECCCON bit
settings, this command will execute, but will not write the ECC bits for the word and can cause DED errors
if dynamic Flash ECC is enabled (FECCCON = 01). Refer to Section 52. “Flash Program Memory” (DS60001193) for information regarding ECC and Flash programming.
3:
2019-2020 Microchip Technology Inc.
DS60001570C-page 75
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 4-1:
bit 3-0
NVMCON: PROGRAMMING CONTROL REGISTER (CONTINUED)
NVMOP: NVM Operation bits
These bits are only writable when WREN = 0.
1111 = Reserved
•
•
•
1000 = Reserved
0111 = Program erase operation: erase all of program Flash memory (all pages must be unprotected,
PWP = 0x000000)
0110 = Reserved
0101 = Program Flash memory erase operation: erases all of Program Flash (all pages in that region must
be unprotected)
0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected
0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected
0010 = Quad Word (128-bit) program operation: programs the 128-bit Flash word selected by NVMADDR,
if it is not write-protected
0001 = Word program operation: programs word selected by NVMADDR, if it is not write-protected(4)
0000 = No operation
Note 1:
2:
3:
These bits are only reset by a Power-on Reset (POR) and are not affected by other reset sources.
This bit can only be modified when the WREN bit = 0, the NVMKEY unlock sequence is satisfied, and the
SWAPLOCK bits (NVMCON2) are cleared to ‘0’.
This operation results in a “No Operation” (NOP) when the Dynamic Flash ECC Configuration bits = 00
(FECCCON (DVCFG0)), which enables ECC at all times. For all other FECCCON bit
settings, this command will execute, but will not write the ECC bits for the word and can cause DED errors
if dynamic Flash ECC is enabled (FECCCON = 01). Refer to Section 52. “Flash Program Memory” (DS60001193) for information regarding ECC and Flash programming.
DS60001570C-page 76
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 4-2:
Bit
Range
31:24
23:16
15:8
7:0
NVMKEY: PROGRAMMING UNLOCK REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
W-0
W-0
W-0
Note:
W-0
31:24
23:16
15:8
7:0
W-0
W-0
W-0
Bit
24/16/8/0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY
W-0
W-0
W-0
W-0
W-0
NVMKEY
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
NVMKEY: Unlock Register bits
These bits are write-only, and read as ‘0’ on any read
This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.
NVMADDR: FLASH ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR(1)
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
W-0
Bit
25/17/9/1
NVMKEY
REGISTER 4-3:
Bit
Range
W-0
Bit
26/18/10/2
NVMKEY
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
Bit
Bit
28/20/12/4 27/19/11/3
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
NVMADDR: Flash Address bits(1)
NVMOP
Selection
Flash Address Bits (NVMADDR)
Page Erase
Row Program
Word Program
Quad Word Program
Note 1:
Note:
Address identifies the page to erase (NVMADDR are ignored).
Address identifies the row to program (NVMADDR are ignored).
Address identifies the word to program (NVMADDR are ignored).
Address identifies the quad word (128-bit) to program (NVMADDR bits are
ignored).
For all other NVMOP bit settings, the Flash address is ignored. See the NVMCON
register (Register 4-1) for additional information on these bits.
The bits in this register are only reset by a POR and are not affected by other reset sources.
2019-2020 Microchip Technology Inc.
DS60001570C-page 77
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 4-4:
Bit
Range
31:24
23:16
15:8
7:0
NVMDATAx: FLASH DATA REGISTER (x = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
NVMDATA: Flash Data bits
Word Program: Writes NVMDATA0 to the target Flash address defined in NVMADDR
Quad Word Program: Writes NVMDATA3:NVMDATA2:NVMDATA1:NVMDATA0 to the target Flash address
defined in NVMADDR. NVMDATA0 contains the Least Significant Instruction Word.
The bits in this register are only reset by a POR and are not affected by other reset sources.
REGISTER 4-5:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
NVMSRCADDR: SOURCE DATA ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR
R/W-0
R/W-0
NVMSRCADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
x = Bit is unknown
NVMSRCADDR: Source Data Address bits
The system physical address of the data to be programmed into the Flash when the NVMOP bits
(NVMCON) are set to perform row programming.
The bits in this register are only reset by a POR and are not affected by other reset sources.
DS60001570C-page 78
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 4-6:
Bit
Range
31:24
23:16
15:8
7:0
NVMPWP: PROGRAM FLASH WRITE-PROTECT REGISTER
Bit
31/23/15/7
R/W-1
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
PWPULOCK
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
PWP
R-0
PWP
R-0
PWP
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
PWPULOCK: Program Flash Memory Page Write-protect Unlock bit
1 = Register is not locked and can be modified
0 = Register is locked and cannot be modified
This bit is only clearable and cannot be set except by any reset.
bit 30-24 Unimplemented: Read as ‘0’
bit 23-0
Note:
PWP: Flash Program Write-protect (Page) Address bits
Physical memory below address 0x1Dxxxxxx is write protected, where ‘xxxxxx’ is specified by PWP.
When PWP has a value of ‘0’, write protection is disabled for the entire program Flash. If the specified
address falls within the page, the entire page and all pages below the current page will be protected.
The bits in this register are only writable when the NVMKEY unlock sequence is followed.
2019-2020 Microchip Technology Inc.
DS60001570C-page 79
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 4-7:
Bit
Range
31:24
23:16
15:8
7:0
NVMBWP: FLASH BOOT (PAGE) WRITE-PROTECT REGISTER
Bit
31/23/15/7
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
BWPULOCK
—
—
BWP4(1)
BWP3(1)
BWP2(1)
BWP1(1)
BWP0(1)
r-1
r-1
U-0
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
Legend:
r = Reserved
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
BWPULOCK: Lower Boot Alias Write-protect Unlock bit
1 = LBWPx bits are not locked and can be modified
0 = LBWPx bits are locked and cannot be modified
This bit is only clearable and cannot be set except by any reset.
bit 14-13 Unimplemented: Read as ‘0’
bit 12
BWP4: Boot Alias Page 4 Write-protect bit(1)
1 = Write protection for physical address 0x01FC10000 through 0x1FC13FFF enabled
0 = Write protection for physical address 0x01FC10000 through 0x1FC13FFF disabled
bit 11
BWP3: Boot Alias Page 3 Write-protect bit(1)
1 = Write protection for physical address 0x01FC0C000 through 0x1FC0FFFF enabled
0 = Write protection for physical address 0x01FC0C000 through 0x1FC0FFFF disabled
bit 10
BWP2: Boot Alias Page 2 Write-protect bit(1)
1 = Write protection for physical address 0x01FC08000 through 0x1FC0BFFF enabled
0 = Write protection for physical address 0x01FC08000 through 0x1FC0BFFF disabled
bit 9
BWP1: Boot Alias Page 1 Write-protect bit(1)
1 = Write protection for physical address 0x01FC04000 through 0x1FC07FFF enabled
0 = Write protection for physical address 0x01FC04000 through 0x1FC07FFF disabled
bit 8
BWP0: Boot Alias Page 0 Write-protect bit(1)
1 = Write protection for physical address 0x01FC00000 through 0x1FC03FFF enabled
0 = Write protection for physical address 0x01FC00000 through 0x1FC03FFF disabled
bit 7
Reserved
bit 6
Reserved: This bit is reserved for use by development tools
bit 5
Unimplemented: Read as ‘0’
bit 4-0
Unimplemented: Read as ‘0’
Note:
The bits in this register are only writable when the NVMKEY unlock sequence is followed.
DS60001570C-page 80
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 4-8:
Bit
Range
31:24
23:16
15:8
7:0
NVMCON2: FLASH PROGRAMMING CONTROL REGISTER 2
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
r-1
r-1
r-1
r-1
—
—
—
r-0
U-0
R/W-0
R/W-0
VREAD1(1)
ERSCNT
r-1
(Reserved, users must always write ‘1’ to these locations)
U-0
U-0
R/W-0
R/W-0
—
—
CREAD1(1)
—
—
ERETRY
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend: r = Reserved
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 ERSCNT: Erase Retry State Count bits
These bits can be used by software to track the erase retry state count in the event of a Master Clear or
BOR. These bits are purely for software tracking purpose and are not used by hardware in any way.
bit 27-21 Unimplemented: Read as ‘0’
bit 20-16 Reserved: Users must always write ‘1’ to these bits
bit 15-14 Unimplemented: Read as ‘0’
bit 13
CREAD1: Compare Read of Logic 1 bit(1)
1 = Compare Read is enabled (only if VERIFYREAD1 = 1)
0 = Compare Read is disabled
Compare Read ‘1’ causes all bits in a Flash Word to be evaluated during the read. If all bits are ‘1’, the lowest
Word in the Flash Word evaluates to 0x00000001, all other words are 0x00010000. If any bit is ‘0’, the read
evaluates to 0x00000000 for all Words in the Flash Word.
bit 12
VREAD1: Verify Read of Logic 1 Control bit(1)
1 = Selects Erase Retry Procedure with Verify Read
0 = Selects Single Erase w/o Verify Read
bit 11-10 Unimplemented: Read as ‘0’
bit 9-8
ERETRY: Erase Retry Control bits
11 = Erase strength for last retry cycle
10 = Erase strength for third retry cycle
01 = Erase strength for second retry cycle
00 = Erase strength for first retry cycle
The user application must start with '00' (first retry cycle) and move on to higher strength if the programming
does not complete.
This bit is used only when VREAD1 = 1 and when VREAD1 = 1.
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
This bit can only be modified when the WREN bit = 0, and the NVMKEY unlock sequence is satisfied.
2019-2020 Microchip Technology Inc.
DS60001570C-page 81
PIC32MK GPG/MCJ with CAN FD Family
5.0
Note:
RESETS
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 7. “Resets”
(DS60001118), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
FIGURE 5-1:
DS60001570C-page 82
The Reset module combines all Reset sources and
controls the device Master Reset signal, SYSRST. The
device Reset sources are as follows:
•
•
•
•
•
•
•
Power-on Reset (POR)
Master Clear Reset pin (MCLR)
Software Reset (SWR)
Watchdog Timer Reset (WDTR)
Brown-out Reset (BOR)
Configuration Mismatch Reset (CMR)
Deadman Timer Reset (DMTR)
A simplified block diagram of the Reset module is
illustrated in Figure 5-1.
SYSTEM RESET BLOCK DIAGRAM
2019-2020 Microchip Technology Inc.
Reset Control Registers
TABLE 5-1:
1260
1270
RSWRST
RNMICON
PWRCON
Legend:
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
—
—
—
15:0
—
—
—
—
25/9
24/8
—
—
—
—
—
—
—
—
—
—
—
—
C000
CMR
—
EXTR
SWR
DMTO
WDTO
SLEEP
IDLE
BOR
POR
31:16
—
—
—
—
—
—
0003
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
SWRST
31:16
—
—
—
—
—
0000
—
DMTO
WDTO
SWNMI
—
—
—
GNMI
HLVD
CF
—
0000
—
—
—
—
—
—
—
0000
—
—
—
VREGS
0000
BCFGERR BCFGFAIL
15:0
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Register
Name
RCON
Bit Range
Virtual Address
(BF80_#)
Bits
1240
1250
RESETS REGISTER MAP
NMICNT
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
0000
VREGRUN
VREGSLP
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 83
5.1
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 5-1:
Bit
Range
31:24
23:16
15:8
7:0
RCON: RESET CONTROL REGISTER
Bit
Bit
31/23/15/7 30/22/14/6
U-1, HS
U-1, HS
Bit
Bit
29/21/13/5 28/20/12/4
U-0
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-0, HC
R/W-0, HC
U-0
U-0
—
—
—
—
BCFGERR
BCFGFAIL
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-1
U-x
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0, HS
U-0
—
—
—
—
—
—
CMR
—
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
EXTR
SWR
DMTO
WDTO
SLEEP
IDLE
R/W-1, HS
(2)
R/W-1, HS
(2)
BOR
Legend:
HS = Hardware Set
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
POR
x = Bit is unknown
bit 31:30 Reserved: Read as ‘1’ on power up.
bit 29-28 Unimplemented: Read as ‘0’
bit 27
BCFGERR: Primary Configuration Registers Error Flag bit
1 = An error occurred during a read of the primary configuration registers
0 = No error occurred during a read of the primary configuration registers
bit 26
BCFGFAIL: Primary/Secondary Configuration Registers Error Flag bit
1 = An error occurred during a read of the primary and alternate configuration registers
0 = No error occurred during a read of the primary and alternate configuration registers
bit 25-10 Unimplemented: Read as ‘0’
bit 9
CMR: Configuration Mismatch Reset Flag bit
1 = A Configuration Mismatch Reset has occurred
0 = A Configuration Mismatch Reset has not occurred
bit 8
Unimplemented: Read as ‘0’
bit 7
EXTR: External Reset (MCLR) Pin Flag bit
1 = Master Clear (pin) Reset has occurred
0 = Master Clear (pin) Reset has not occurred
bit 6
SWR: Software Reset Flag bit
1 = Software Reset was executed
0 = Software Reset was not executed
bit 5
DMTO: Deadman Timer Time-out Flag bit
1 = A DMT time-out has occurred
0 = A DMT time-out has not occurred
bit 4
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT Time-out has occurred
0 = WDT Time-out has not occurred
bit 3
SLEEP: Wake From Sleep Flag bit
1 = Device was in Sleep mode
0 = Device was not in Sleep mode
bit 2
IDLE: Wake From Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
Note 1:
User software must clear this bit to view the next detection.
DS60001570C-page 84
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 5-1:
RCON: RESET CONTROL REGISTER
bit 1
BOR: Brown-out Reset Flag bit(1)
1 = Brown-out Reset has occurred
0 = Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit(1)
1 = Power-on Reset has occurred
0 = Power-on Reset has not occurred
Note 1:
User software must clear this bit to view the next detection.
2019-2020 Microchip Technology Inc.
DS60001570C-page 85
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 5-2:
Bit
Range
31:24
23:16
15:8
7:0
RSWRST: SOFTWARE RESET REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
Legend:
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
—
W-0, HC
(1,2)
SWRST
x = Bit is unknown
bit 31-1
Unimplemented: Read as ‘0’
bit 0
SWRST: Software Reset Trigger bit(1,2)
1 = Enable software Reset event
0 = No effect
Note 1:
The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section
42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for
details.
Once this bit is set, any read of the RSWRST register will cause a Reset to occur.
2:
DS60001570C-page 86
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 5-3:
Bit
Range
31:24
23:16
15:8
7:0
RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
DMTO
WDTO
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0, HS
R/W-0, HS, HC
R/W-0
SWNMI
—
—
—
GNMI
HLVD
CF
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NMICNT
R/W-0
NMICNT
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clear
W = Writable bit
‘1’ = Bit is set
HS = Hardware Set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25
DMTO: Deadman Timer Time-out Flag bit
1 = DMT time-out has occurred and caused a NMI
0 = DMT time-out has not occurred
Setting this bit will cause a DMT NMI event, and NMICNT will begin counting. Clearing this bit before the
NMICNT SYSCLK" cycle counter has expired will negate a normal DMT CPU reset.
bit 24
WDTO: Watchdog Timer Time-Out Flag bit
1 = WDT time-out has occurred and caused a NMI
0 = WDT time-out has not occurred
Setting this bit will cause a WDT NMI event, and MNICNT will begin counting. Clearing this bit before the
NMICNT SYSCLK" cycle counter has expired will negate a normal WDT CPU reset.
bit 23
SWNMI: Software NMI Trigger.
1 = An NMI will be generated
0 = An NMI will not be generated
bit 22-20 Unimplemented: Read as ‘0’
bit 19
GNMI: General NMI bit
1 = A general NMI event has been detected or a user-initiated NMI event has occurred
0 = A general NMI event has not been detected
Setting GNMI to a ‘1’ causes a user-initiated NMI event. This bit is also set by writing 0x4E to the
NMIKEY (INTCON) bits.
bit 18
HLVD: High/Low-Voltage Detect Status
1 = Indicates HLVD Event interrupt is active.
0 = Indicates HLVD Event interrupt is not active.
Note 1: When a Watchdog Timer NMI event (when not in Sleep mode) or a Deadman Timer NMI event is triggered
the NMICNT will start decrementing. When NMICNT reaches zero, the device is Reset if the corresponding WDT or DMT flag is not cleared in SW. This NMI reset counter is only applicable to these two specific
NMI events. The NMICNT cannot be updated or changed once in the NMI interrupt service routine by SW.
Note:
The system unlock sequence must be performed before the SWRST bit is written. Refer to the Section 42.
“Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
2019-2020 Microchip Technology Inc.
DS60001570C-page 87
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 5-3:
bit 17
RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER
CF: Clock Fail Detect bit
1 = FSCM has detected clock failure and caused an NMI
0 = FSCM has not detected clock failure
Note:
On a clock fail event if enabled by the FCKSM bits (DEVCFG1) = ‘0b11, this bit
and the OSCCON bit will be set. The user software must clear both the bits inside the CF
NMI before attempting to exit the ISR. Software or hardware settings of the CF bit
(OSCCON) will cause a CF NMI event and an automatic clock switch to the Backup FRC
(BFRC) provided the FCKSM = ‘0b11. Unlike the CF bit (OSCCON), software or
hardware settings of the CF bit (RNMICON) will cause a CF NMI event but will not cause
a clock switch to the BFRC. After a Clock Fail event, a successful user software clock switch if
implemented, hardware will automatically clear the CF bit (RNMICON), but not the CF bit
(OSCCON). The CF bit (OSCCON) must be cleared by software using the OSCCON
register unlock procedure.
bit 16
bit 15-0
Unimplemented: Read as ‘0’
NMICNT: NMI Reset Counter Value bits
These bits specify the reload value used by the NMI reset counter.
11111111-00000001 = Number of SYSCLK cycles before a device Reset occurs(1)
00000000 = No delay between NMI assertion and device Reset event
Note 1:
When a Watchdog Timer NMI event (when not in Sleep mode) or a Deadman Timer NMI event is triggered
the NMICNT will start decrementing. When NMICNT reaches zero, the device is Reset if the corresponding WDT or DMT flag is not cleared in SW. This NMI reset counter is only applicable to these two specific
NMI events. The NMICNT cannot be updated or changed once in the NMI interrupt service routine by SW.
Note:
The system unlock sequence must be performed before the SWRST bit is written. Refer to the Section 42.
“Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
DS60001570C-page 88
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 5-4:
Bit
Range
31:24
23:16
15:8
7:0
PWRCON: POWER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
VREGS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-1
Unimplemented: Read as ‘0’
bit 0
VREGS: Internal Voltage Regulator Stand-by Enable bit
1 = Voltage regulator will remain active during Sleep
0 = Voltage regulator will go to Stand-by mode during Sleep
2019-2020 Microchip Technology Inc.
x = Bit is unknown
DS60001570C-page 89
PIC32MK GPG/MCJ with CAN FD Family
6.0
Note:
CPU EXCEPTIONS AND
INTERRUPT CONTROLLER
This data sheet summarizes the
features of the PIC32MK GPG/MCJ with
CAN FD Family of devices. It is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 8. “Interrupt Controller”
(DS60001108) and Section 50. “CPU
for
Devices
with
MIPS32®
microAptiv™ and M-Class Cores”
(DS60001192), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
PIC32MK GPG/MCJ with CAN FD Family of devices
generate interrupt requests in response to interrupt
events from peripheral modules. The Interrupt Controller
module exists outside of the CPU and prioritizes the
interrupt events before presenting them to the CPU.
DS60001570C-page 90
The CPU handles interrupt events as part of the
exception handling mechanism, which is described in
6.1 “CPU Exceptions”.
The Interrupt Controller module includes the following
features:
• Up to 216 interrupt sources and vectors with
dedicated programmable offsets, eliminating the
need for redirection
• Single and multi-vector mode operations
• Five external interrupts with edge polarity control
• Interrupt proximity timer
• Seven user-selectable priority levels for each
vector
• Four user-selectable subpriority levels within each
priority
• Seven shadow register sets that can be used for any
priority level, eliminating software context switch and
reducing interrupt latency
• Software can generate any interrupt
Table 6-1 provides Interrupt Service routine (ISR)
latency information.
2019-2020 Microchip Technology Inc.
ISR LATENCY INFORMATION
Recommended Settings for Optimal Interrupt
Performance
Optimal Performance Configuration
CP0 REGISTER 16, PERCHEEN bit DCHEEN bit
SELECT 0
(CHECON) (CHECON)
Condition
ICHEEN bit
PREFEN bits PFMWS bits User source file ISR declaration/invocation.
(CHECON) (CHECON)
CHECON)
Note:
The user is responsible for the ISR declaration for the fastest ISR latency
response.
Note
1:
2:
3:
Interrupt Latency
(SYSCLK Cycles)
(Time from interrupt event to first
user source code
instruction execution inside ISR).
3’b010
1’b1
1’b1
1’b1
2’b00
3’b111
void __ISR(,
ipl7auto)ISR(void)
{
// “n” = Vector Number, see data sheet
// User ISR code
}
257 Instr Cycles
3’b011
1’b1
1’b1
1’b1
2’b01
3’b010
(Refer to note 3)
void __attribute__((interrupt(iplXsrs),
at_vector(n), aligned(16))) isr ()
{
// ”n”=Vector Number, see data sheet
// “X”=IPL 1-7
// User ISR code
}
30 + (7 – IPL)
(Instr Cycles per
interrupt (3))
Reset Values
Recommended
user optimized
CPU and ISR
Latency Settings (see Note
2)
Comment
The CPU ISR latency can cause unexpected behavior in high data rate peripherals when a high repetitive rate of CPU interrupts. For example, it is possible that if multiple interrupt sources occur simultaneously, or if a high-speed peripheral like ADC occurs faster than the CPU can read the results from the first original interrupt, then that data may be overwritten by the second interrupt. If the possibility exists in user application that the CPU servicing requirements are less than the combined sum of all possible overlapping interrupt rate specified above, then to avoid buffer overflows or data
overwrites it is recommended to use the DMA to service the data and buffer instead of the CPU.
For the best optimized CPU and ISR performance, to complete the optimization, the user application should define ISRs that use the “at vector” attribute as shown in Table 6-1 In addition, if the ADC
combined sum throughput rate of all the ADC modules in use is greater than (SYSCLK/43) = 2.8 Msps, it is recommended to use the ADC CPU early interrupt generation defined in the ADCxTIME and
ADCEIENx registers. This will reduce the probability of the ADC results being overwritten by the next conversion before the CPU can read the previous ADC result if not using the DMA for ADC. Do not
use the early interrupts if using the ADC in DMA mode.
For optimal interrupt performance, (i.e. latency), the user should assign a unique shadow register set for each interrupt priority level by setting PRISS = IPL.
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 91
TABLE 6-1:
PIC32MK GPG/MCJ with CAN FD Family
Figure 6-1 shows the block diagram for the Interrupt
Controller and CPU exceptions.
CPU EXCEPTIONS AND INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM
Interrupt Requests
FIGURE 6-1:
Vector Number and Offset
Interrupt Controller
Priority Level
CPU Core
(Exception Handling)
Shadow Set Number
SYSCLK
DS60001570C-page 92
2019-2020 Microchip Technology Inc.
CPU Exceptions
CPU coprocessor 0 contains the logic for identifying and managing exceptions.
Exceptions can be caused by a variety of sources, including boundary cases in
data, external events or program errors. Table 6-2 lists the exception types in
order of priority.
TABLE 6-2:
Exception Type
(In Order of
Priority)
MIPS32® microAptiv™ MCU CORE EXCEPTION TYPES
Description
Branches to
Status
Bits Set
Debug Bits
Set
EXCCODE
BEV, ERL
BEV, SR,
ERL
—
—
—
—
—
—
DSS
DINT
—
—
BEV, NMI,
ERL
IPL
—
—
—
0x00
See Table 6-3.
WP, EXL
—
0x17
_general_exception_handler
—
EXL
DIB
—
—
0x17
—
_general_exception_handler
EXL
—
0x04
_general_exception_handler
EXL
EXL
—
—
0x06
0x0A or
0x0B
_general_exception_handler
_general_exception_handler
XC32 Function Name
Highest Priority
Reset
Soft Reset
Assertion MCLR or a Power-on Reset (POR).
Assertion of a software Reset.
0xBFC0_0000
0xBFC0_0000
DSS
DINT
EJTAG debug single step.
EJTAG debug interrupt. Caused by the assertion of
the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
Assertion of NMI signal.
0xBFC0_0480
0xBFC0_0480
NMI
Interrupt
Deferred Watch
DIB
WATCH
2019-2020 Microchip Technology Inc.
AdEL
IBE
Instruction
Validity
Exceptions
0xBFC0_0000
Assertion of unmasked hardware or software inter- See Table 6-3.
rupt signal.
Deferred watch (unmasked by K|DM=>!(K|DM)
EBASE+0x180
transition).
EJTAG debug hardware instruction break matched.
0xBFC0_0480
A reference to an address that is in one of the
EBASE+0x180
Watch registers (fetch).
Fetch address alignment error. Fetch reference to
EBASE+0x180
protected address.
Instruction fetch bus error.
EBASE+0x180
An instruction could not be completed because it
EBASE+0x180
was not allowed to access the required resources
(Coprocessor Unusable) or was illegal (Reserved
Instruction). If both exceptions occur on the same
instruction, the Coprocessor Unusable Exception
takes priority over the Reserved Instruction
Exception.
_on_reset
_on_reset
—
—
_nmi_handler
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 93
6.1
Exception Type
(In Order of
Priority)
Execute
Exception
Tr
DDBL/DDBS
WATCH
AdEL
AdES
DBE
DDBL
CBrk
MIPS32® microAptiv™ MCU CORE EXCEPTION TYPES (CONTINUED)
Description
Branches to
Status
Bits Set
Debug Bits
Set
An instruction-based exception occurred: Integer
overflow, trap, system call, breakpoint, floating
point, or DSP ASE state disabled exception.
Execution of a trap (when trap condition is true).
EJTAG Data Address Break (address only) or
EJTAG data value break on store (address +
value).
A reference to an address that is in one of the
Watch registers (data).
Load address alignment error. User mode load
reference to kernel address.
Store address alignment error. User mode store to
kernel address.
Load or store bus error.
EJTAG data hardware breakpoint matched in load
data compare.
EJTAG complex breakpoint.
EBASE+0x180
EXL
—
EBASE+0x180
0xBFC0_0480
EXL
—
—
DDBL or
DDBS
0x0D
—
_general_exception_handler
—
EBASE+0x180
EXL
—
0x17
_general_exception_handler
EBASE+0x180
EXL
—
0x04
_general_exception_handler
EBASE+0x180
EXL
—
0x05
_general_exception_handler
EBASE+0x180
0xBFC0_0480
EXL
—
—
DDBL
0x07
—
_general_exception_handler
—
0xBFC0_0480
—
DIBIMPR,
DDBLIMPR,
and/or
DDBSIMPR
—
—
Lowest Priority
EXCCODE
XC32 Function Name
0x08-0x0C _general_exception_handler
DS60001570C-page 94
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 6-2:
PIC32MK GPG/MCJ with CAN FD Family
6.2
Interrupts
The PIC32MK GPG/MCJ with CAN FD Family of
devices uses variable offsets for vector spacing. This
allows the interrupt vector spacing to be configured
according to application needs. A unique interrupt vector offset can be set for each vector using its associated
OFFx register.
For additional information on the variable offset features, refer to 8.5.2 “Variable Offset” in Section 8.
“Interrupt Controller” (DS60001108) of the “PIC32
Family Reference Manual”.
Table 6-3 provides the Interrupt IRQ, vector and bit
location information.
2019-2020 Microchip Technology Inc.
DS60001570C-page 95
INTERRUPT IRQ, VECTOR AND BIT LOCATION
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
DS60001570C-page 96
Highest Natural Order Priority
Core Timer Interrupt
_CORE_TIMER_VECTOR
0
OFF000 IFS0 IEC0
IPC0
IPC0
No
Core Software Interrupt 0
_CORE_SOFTWARE_0_VECTOR
1
OFF001 IFS0 IEC0 IPC0
IPC0
No
Core Software Interrupt 1
_CORE_SOFTWARE_1_VECTOR
2
OFF002 IFS0 IEC0 IPC0 IPC0
No
External Interrupt 0
_EXTERNAL_0_VECTOR
3
OFF003 IFS0 IEC0 IPC0 IPC0
No
Timer1
_TIMER_1_VECTOR
4
OFF004 IFS0 IEC0
IPC1
IPC1
No
Input Capture 1 Error
_INPUT_CAPTURE_1_ERROR_VECTOR
5
OFF005 IFS0 IEC0 IPC1
IPC1
Yes
Input Capture 1
_INPUT_CAPTURE_1_VECTOR
6
OFF006 IFS0 IEC0 IPC1 IPC1
Yes
Output Compare 1
_OUTPUT_COMPARE_1_VECTOR
7
OFF007 IFS0 IEC0 IPC1 IPC1
No
External Interrupt 1
_EXTERNAL_1_VECTOR
8
OFF008 IFS0 IEC0
IPC2
IPC2
No
Timer2
_TIMER_2_VECTOR
9
OFF009 IFS0 IEC0 IPC2
IPC2
No
Input Capture 2 Error
_INPUT_CAPTURE_2_ERROR_VECTOR
10
OFF010 IFS0 IEC0 IPC2 IPC2
Yes
Input Capture 2
_INPUT_CAPTURE_2_VECTOR
11
OFF011 IFS0 IEC0 IPC2 IPC2
Yes
Output Compare 2
_OUTPUT_COMPARE_2_VECTOR
12
OFF012 IFS0 IEC0
IPC3
IPC3
No
External Interrupt 2
_EXTERNAL_2_VECTOR
13
OFF013 IFS0 IEC0 IPC3
IPC3
No
Timer3
_TIMER_3_VECTOR
14
OFF014 IFS0 IEC0 IPC3 IPC3
No
Input Capture 3 Error
_INPUT_CAPTURE_3_ERROR_VECTOR
15
OFF015 IFS0 IEC0 IPC3 IPC3
Yes
Input Capture 3
_INPUT_CAPTURE_3_VECTOR
16
OFF016 IFS0 IEC0
IPC4
IPC4
Yes
Output Compare 3
_OUTPUT_COMPARE_3_VECTOR
17
OFF017 IFS0 IEC0 IPC4
IPC4
No
External Interrupt 3
_EXTERNAL_3_VECTOR
18
OFF018 IFS0 IEC0 IPC4 IPC4
No
Timer4
_TIMER_4_VECTOR
19
OFF019 IFS0 IEC0 IPC4 IPC4
No
Input Capture 4 Error
_INPUT_CAPTURE_4_ERROR_VECTOR
20
OFF020 IFS0 IEC0
IPC5
IPC5
Yes
Input Capture 4
_INPUT_CAPTURE_4_VECTOR
21
OFF021 IFS0 IEC0 IPC5
IPC5
Yes
Output Compare 4
_OUTPUT_COMPARE_4_VECTOR
22
OFF022 IFS0 IEC0 IPC5 IPC5
No
External Interrupt 4
_EXTERNAL_4_VECTOR
23
OFF023 IFS0 IEC0 IPC5 IPC5
No
Timer5
_TIMER_5_VECTOR
24
OFF024 IFS0 IEC0
IPC6
IPC6
No
Input Capture 5 Error
_INPUT_CAPTURE_5_ERROR_VECTOR
25
OFF025 IFS0 IEC0 IPC6
IPC6
Yes
Input Capture 5
_INPUT_CAPTURE_5_VECTOR
26
OFF026 IFS0 IEC0 IPC6 IPC6
Yes
Output Compare 5
_OUTPUT_COMPARE_5_VECTOR
27
OFF027 IFS0 IEC0 IPC6 IPC6
No
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK Motor Control and General Purpose (MC and GP) Family Features” for the list of
available peripherals.
2: This interrupt source is not available on 48-pin devices.
3: This interrupt source is ONLY available on “MC” variants of the device.
4: Only available on “MC” variants.
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 6-3:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
XC32 Vector Name
IRQ
#
Vector #
Reserved
—
28
—
Reserved
Real Time Clock
Flash Control Event
Comparator 1 Interrupt
Comparator 2 Interrupt
—
29
30
31
32
33
—
OFF030
OFF031
OFF032
OFF033
Interrupt Source(1)
_RTCC_VECTOR
_FLASH_CONTROL_VECTOR
_COMPARATOR_1_VECTOR
_COMPARATOR_2_VECTOR
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
—
—
—
—
—
—
IPC7
IPC7
IPC8
IPC8
—
IPC7
IPC7
IPC8
IPC8
—
Yes
No
No
No
—
—
IFS0 IEC0
IFS0 IEC0
IFS1 IEC1
IFS1 IEC1
2019-2020 Microchip Technology Inc.
Reserved
—
34
—
—
—
—
—
—
SPI1 Fault
_SPI1_FAULT_VECTOR
35
OFF035 IFS1 IEC1 IPC8 IPC8
Yes
SPI1 Receive Done
_SPI1_RX_VECTOR
36
OFF036 IFS1 IEC1
IPC9
IPC9
Yes
SPI1 Transfer Done
_SPI1_TX_VECTOR
37
OFF037 IFS1 IEC1 IPC9
IPC9
Yes
UART1 Fault
_UART1_FAULT_VECTOR
38
OFF038 IFS1 IEC1 IPC9 IPC9
Yes
UART1 Receive Done
_UART1_RX_VECTOR
39
OFF039 IFS1 IEC1 IPC9 IPC9
Yes
UART1 Transfer Done
_UART1_TX_VECTOR
40
OFF040 IFS1 IEC1
IPC10
IPC10
Yes
I2C1 Bus Collision Event
_I2C1_BUS_VECTOR
41
OFF041 IFS1 IEC1 IPC9
IPC9
Yes
I2C1 Slave Event
_I2C1_SLAVE_VECTOR
42
OFF042 IFS1 IEC1 IPC9 IPC9
Yes
I2C1 Master Event
_I2C1_MASTER_VECTOR
43
OFF043 IFS1 IEC1 IPC10 IPC10
No
PORTA Input Change Interrupt
_CHANGE_NOTICE_A_VECTOR
44
OFF044 IFS1 IEC1 IPC11
IPC11
Yes
PORTB Input Change Interrupt
_CHANGE_NOTICE_B_VECTOR
45
OFF045 IFS1 IEC1 IPC11
IPC11
Yes
PORTC Input Change Interrupt
_CHANGE_NOTICE_C_VECTOR
46
OFF046 IFS1 IEC1 IPC11 IPC11
Yes
PORTD Input Change Interrupt
_CHANGE_NOTICE_D_VECTOR
47
OFF047 IFS1 IEC1 IPC11 IPC11
Yes
PORTE Input Change Interrupt
_CHANGE_NOTICE_E_VECTOR
48
OFF048 IFS1 IEC1 IPC12
IPC12
Yes
PORTF Input Change Interrupt
_CHANGE_NOTICE_F_VECTOR
49
OFF049 IFS1 IEC1 IPC12 IPC12
Yes
PORTG Input Change Interrupt
_CHANGE_NOTICE_G_VECTOR
50
OFF050 IFS1 IEC1 IPC12 IPC12
Yes
Reserved
—
51
—
—
—
—
—
—
Reserved
—
52
—
—
—
—
—
—
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK Motor Control and General Purpose (MC and GP) Family Features” for the list of
available peripherals.
2: This interrupt source is not available on 48-pin devices.
3: This interrupt source is ONLY available on “MC” variants of the device.
4: Only available on “MC” variants.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 97
TABLE 6-3:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
SPI2 Fault
SPI2 Receive Done
SPI2 Transfer Done
UART2 Fault
UART2 Receive Done
UART2 Transfer Done
XC32 Vector Name
_SPI2_FAULT_VECTOR
_SPI2_RX_VECTOR
_SPI2_TX_VECTOR
_UART2_FAULT_VECTOR
_UART2_RX_VECTOR
_UART2_TX_VECTOR
IRQ
#
Vector #
53
54
55
56
57
58
OFF053
OFF054
OFF055
OFF056
OFF057
OFF058
Interrupt Bit Location
Flag
Enable
IFS1
IFS1
IFS1
IFS1
IFS1
IFS1
IEC1
IEC1
IEC1
IEC1
IEC1
IEC1
Priority
Sub-priority
IPC13 IPC13
IPC13 IPC13
IPC13 IPC13
IPC14
IPC14
IPC14 IPC14
IPC14 IPC14
Persistent
Interrupt
Yes
Yes
Yes
Yes
Yes
Yes
DS60001570C-page 98
I2C2 Bus Collision Event
_I2C2_BUS_VECTOR
59
OFF059 IFS1 IEC1 IPC14 IPC14
Yes
I2C2 Slave Event
_I2C2_SLAVE_VECTOR
60
OFF060 IFS1 IEC1 IPC15
IPC15
Yes
I2C2 Master Event
_I2C2_MASTER_VECTOR
61
OFF061 IFS1 IEC1 IPC15 IPC15
Yes
Reserved
—
62
—
—
—
—
—
—
Reserved
—
63
—
—
—
—
—
—
Reserved
—
64
—
—
—
—
—
—
Reserved
—
65
—
—
—
—
—
—
Reserved
—
66
—
—
—
—
—
—
Reserved
—
67
—
—
—
—
—
—
Reserved
—
68
—
—
—
—
—
—
Reserved
—
69
—
—
—
—
—
—
Reserved
—
70
—
—
—
—
—
—
CTMU Interrupt
_CTMU_VECTOR
71
OFF071 IFS2 IEC2 IPC17 IPC17
Yes
DMA Channel 0
_DMA0_VECTOR
72
OFF072 IFS2 IEC2
IPC18
IPC18
Yes
DMA Channel 1
_DMA1_VECTOR
73
OFF073 IFS2 IEC2 IPC18 IPC18
Yes
DMA Channel 2
_DMA2_VECTOR
74
OFF074 IFS2 IEC2 IPC18 IPC18
Yes
DMA Channel 3
_DMA3_VECTOR
75
OFF075 IFS2 IEC2 IPC18 IPC18
Yes
Timer6
_TIMER_6_VECTOR
76
OFF076 IFS2 IEC2 IPC19
IPC19
Yes
Input Capture 6 Error
_INPUT_CAPTURE_6_ERROR_VECTOR
77
OFF077 IFS2 IEC2 IPC19 IPC19
Yes
Input Capture 6
_INPUT_CAPTURE_6_VECTOR
78
OFF078 IFS2 IEC2 IPC19 IPC19
Yes
Output Compare 6
_OUTPUT_COMPARE_6_VECTOR
79
OFF079 IFS2 IEC2 IPC19 IPC19
Yes
Timer7
_TIMER_7_VECTOR
80
OFF080 IFS2 IEC2 IPC20
IPC20
Yes
Input Capture 7 Error
_INPUT_CAPTURE_7_ERROR_VECTOR
81
OFF081 IFS2 IEC2 IPC20 IPC20
Yes
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK Motor Control and General Purpose (MC and GP) Family Features” for the list of
available peripherals.
2: This interrupt source is not available on 48-pin devices.
3: This interrupt source is ONLY available on “MC” variants of the device.
4: Only available on “MC” variants.
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 6-3:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
Input Capture 7
Output Compare 7
Timer8
Input Capture 8 Error
Input Capture 8
Output Compare 8
XC32 Vector Name
_INPUT_CAPTURE_7_VECTOR
_OUTPUT_COMPARE_7_VECTOR
_TIMER_8_VECTOR
_INPUT_CAPTURE_8_ERROR_VECTOR
_INPUT_CAPTURE_8_VECTOR
_OUTPUT_COMPARE_8_VECTOR
IRQ
#
Vector #
82
83
84
85
86
87
OFF082
OFF083
OFF084
OFF085
OFF086
OFF087
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
IFS2
IFS2
IFS2
IFS2
IFS2
IFS2
IEC2
IEC2
IEC2
IEC2
IEC2
IEC2
IPC20
IPC20
IPC21
IPC21
IPC21
IPC21
IPC20
IPC20
IPC21
IPC21
IPC21
IPC21
Yes
Yes
Yes
Yes
Yes
Yes
2019-2020 Microchip Technology Inc.
Timer9
_TIMER_9_VECTOR
88
OFF088 IFS2 IEC2 IPC22
IPC22
Yes
Input Capture 9 Error
_INPUT_CAPTURE_9_ERROR_VECTOR
89
OFF089 IFS2 IEC2 IPC22 IPC22
Yes
Input Capture 9
_INPUT_CAPTURE_9_VECTOR
90
OFF090 IFS2 IEC2 IPC22 IPC22
Yes
Output Compare 9
_OUTPUT_COMPARE_9_VECTOR
91
OFF091 IFS2 IEC2 IPC22 IPC22
Yes
ADC Global Interrupt
_ADC_VECTOR
92
OFF092 IFS2 IEC2 IPC23
IPC23
Yes
Reserved
—
93
—
—
—
—
—
—
ADC Digital Comparator 1
_ADC_DC1_VECTOR
94
OFF094 IFS2 IEC2 IPC23 IPC23
Yes
ADC Digital Comparator 2
_ADC_DC2_VECTOR
95
OFF095 IFS2 IEC2 IPC23 IPC23
Yes
ADC Digital Filter 1
_ADC_DF1_VECTOR
96
OFF096 IFS3 IEC3
IPC24
IPC24
Yes
ADC Digital Filter 2
_ADC_DF2_VECTOR
97
OFF097 IFS3 IEC3 IPC24 IPC24
Yes
ADC Digital Filter 3
_ADC_DF3_VECTOR
98
OFF098 IFS3 IEC3 IPC24 IPC24
Yes
ADC Digital Filter 4
_ADC_DF4_VECTOR
99
OFF099 IFS3 IEC3 IPC24 IPC24
Yes
ADC Fault
_ADC_FAULT_VECTOR
100 OFF100 IFS3 IEC3
IPC25
IPC25
Yes
ADC End of Scan
_ADC_EOS_VECTOR
101 OFF101 IFS3 IEC3 IPC25 IPC25
Yes
ADC Ready
_ADC_ARDY_VECTOR
102 OFF102 IFS3 IEC3 IPC25 IPC25
Yes
ADC Update Ready After Suspend _ADC_URDY_VECTOR
103 OFF103 IFS3 IEC3 IPC25 IPC25
Yes
ADC First Class Channels DMA
_ADC_DMA_VECTOR
104 OFF104 IFS3 IEC3
IPC26
IPC26
No
ADC Early Group Interrupt
_ADC_EARLY_VECTOR
105 OFF105 IFS3 IEC3 IPC26 IPC26
Yes
ADC Data 0
_ADC_DATA0_VECTOR
106 OFF106 IFS3 IEC3 IPC26 IPC26
Yes
ADC Data 1
_ADC_DATA1_VECTOR
107 OFF107 IFS3 IEC3 IPC26 IPC26
Yes
ADC Data 2
_ADC_DATA2_VECTOR
108 OFF108 IFS3 IEC3 IPC26
IPC27
Yes
ADC Data 3
_ADC_DATA3_VECTOR
109 OFF109 IFS3 IEC3 IPC27 IPC27
Yes
ADC Data 4
_ADC_DATA4_VECTOR
110 OFF110 IFS3 IEC3 IPC27 IPC27
Yes
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK Motor Control and General Purpose (MC and GP) Family Features” for the list of
available peripherals.
2: This interrupt source is not available on 48-pin devices.
3: This interrupt source is ONLY available on “MC” variants of the device.
4: Only available on “MC” variants.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 99
TABLE 6-3:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
ADC Data 5
ADC Data 6
ADC Data 7
ADC Data 8
ADC Data 9
ADC Data 10
ADC Data 11
ADC Data 12(2)
ADC Data 13(2)
ADC Data 14(2)
ADC Data 15(2)
ADC Data 16(2)
XC32 Vector Name
_ADC_DATA5_VECTOR
_ADC_DATA6_VECTOR
_ADC_DATA7_VECTOR
_ADC_DATA8_VECTOR
_ADC_DATA9_VECTOR
_ADC_DATA10_VECTOR
IRQ
#
Vector #
111
112
113
114
115
116
OFF111
OFF112
OFF113
OFF114
OFF115
OFF116
Interrupt Bit Location
Flag
Enable
IFS3
IFS3
IFS3
IFS3
IFS3
IFS3
IEC3
IEC3
IEC3
IEC3
IEC3
IEC3
Priority
Sub-priority
IPC27 IPC27
IPC28
IPC28
IPC28 IPC28
IPC28 IPC28
IPC28 IPC28
IPC29
IPC29
Persistent
Interrupt
Yes
Yes
Yes
Yes
Yes
Yes
DS60001570C-page 100
_ADC_DATA11_VECTOR
117 OFF117 IFS3 IEC3 IPC29 IPC29
Yes
_ADC_DATA12_VECTOR
118 OFF118 IFS3 IEC3 IPC29 IPC29
Yes
_ADC_DATA13_VECTOR
119 OFF119 IFS3 IEC3 IPC29 IPC29
Yes
_ADC_DATA14_VECTOR
120 OFF120 IFS3 IEC3 IPC30
IPC30
Yes
_ADC_DATA15_VECTOR
121 OFF121 IFS3 IEC3 IPC30 IPC30
Yes
_ADC_DATA16_VECTOR
122 OFF122 IFS3 IEC3 IPC30 IPC30
Yes
_ADC_DATA17_VECTOR
123 OFF123 IFS3 IEC3 IPC30 IPC30
Yes
ADC Data 17(2)
ADC Data 18(2)
_ADC_DATA18_VECTOR
124 OFF124 IFS3 IEC3 IPC31
IPC31
Yes
ADC Data 19(2)
_ADC_DATA19_VECTOR
125 OFF125 IFS3 IEC3 IPC31 IPC31
Yes
Reserved
—
126
—
—
—
—
—
—
Reserved
—
127
—
—
—
—
—
—
Reserved
—
128
—
—
—
—
—
—
Reserved
—
129
—
—
—
—
—
—
ADC Data 24
_ADC_DATA24_VECTOR
130 OFF130 IFS4 IEC4 IPC32 IPC32
Yes
ADC Data 25
_ADC_DATA25_VECTOR
131 OFF131 IFS4 IEC4 IPC32 IPC32
Yes
ADC Data 26
_ADC_DATA26_VECTOR
132 OFF132 IFS4 IEC4
IPC33
IPC33
Yes
ADC Data 27
_ADC_DATA27_VECTOR
133 OFF133 IFS4 IEC4 IPC33 IPC33
Yes
Reserved
—
134
—
—
—
—
—
—
Reserved
—
135
—
—
—
—
—
—
Reserved
—
136
—
—
—
—
—
—
Reserved
—
137
—
—
—
—
—
—
Reserved
—
138
—
—
—
—
—
—
Reserved
—
139
—
—
—
—
—
—
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK Motor Control and General Purpose (MC and GP) Family Features” for the list of
available peripherals.
2: This interrupt source is not available on 48-pin devices.
3: This interrupt source is ONLY available on “MC” variants of the device.
4: Only available on “MC” variants.
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 6-3:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
Reserved
XC32 Vector Name
IRQ
#
Vector #
—
140
—
Interrupt Bit Location
Flag
Enable
Priority
—
—
—
Sub-priority
Persistent
Interrupt
2019-2020 Microchip Technology Inc.
—
—
Reserved
—
141
—
—
—
—
—
—
Reserved
—
142
—
—
—
—
—
—
Reserved
—
143
—
—
—
—
—
—
Reserved
—
144
—
—
—
—
—
—
Reserved
—
145
—
—
—
—
—
—
ADC Data 40(2)
_ADC_DATA40_VECTOR
146 OFF146 IFS4 IEC4 IPC36 IPC36
Yes
ADC Data 41(2)
_ADC_DATA41_VECTOR
147 OFF147 IFS4 IEC4 IPC36 IPC36
Yes
Reserved
—
148
—
—
—
—
—
—
Reserved
—
149
—
—
—
—
—
—
Reserved
—
150
—
—
—
—
—
—
Reserved
—
151
—
—
—
—
—
—
_ADC_DATA46_VECTOR
152 OFF152 IFS4 IEC4 IPC38
IPC38
Yes
ADC Data 46(2)
ADC Data 47(2)
_ADC_DATA47_VECTOR
153 OFF153 IFS4 IEC4 IPC38 IPC38
Yes
ADC Data 48
_ADC_DATA48_VECTOR
154 OFF154 IFS4 IEC4 IPC38 IPC38
Yes
ADC Data 49
_ADC_DATA49_VECTOR
155 OFF155 IFS4 IEC4 IPC38 IPC38
Yes
ADC Data 50
_ADC_DATA50_VECTOR
156 OFF156 IFS4 IEC4 IPC39
IPC39
Yes
Reserved
—
157
—
—
—
—
—
—
Reserved
—
158
—
—
—
—
—
—
ADC Data 53
_ADC_DATA53_VECTOR
159 OFF159 IFS4 IEC4 IPC39 IPC39
Yes
Comparator 3 Interrupt
_COMPARATOR_3_VECTOR
160 OFF160 IFS5 IEC5
IPC40
IPC40
No
Comparator 4 Interrupt
_COMPARATOR_4_VECTOR
161 OFF161 IFS5 IEC5 IPC40 IPC40
No
Comparator 5 Interrupt
_COMPARATOR_5_VECTOR
162 OFF162 IFS5 IEC5 IPC40 IPC40
No
Reserved
—
163
—
—
—
—
—
—
Reserved
—
164
—
—
—
—
—
—
Reserved
—
165
—
—
—
—
—
—
Reserved
—
166
—
—
—
—
—
—
(4)
CAN1 Global Interrupt
_CAN1_VECTOR
167 OFF167 IFS5 IEC5 IPC41 IPC41
Yes
Reserved
—
168
—
—
—
—
—
—
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK Motor Control and General Purpose (MC and GP) Family Features” for the list of
available peripherals.
2: This interrupt source is not available on 48-pin devices.
3: This interrupt source is ONLY available on “MC” variants of the device.
4: Only available on “MC” variants.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 101
TABLE 6-3:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
DS60001570C-page 102
QEI1 Interrupt(3)
_QEI1_VECTOR
169 OFF169 IFS5 IEC5 IPC42 IPC42
Yes
QEI2 Interrupt(3)
_QEI2_VECTOR
170 OFF170 IFS5 IEC5 IPC42 IPC42
Yes
PWM Primary Event(3)
_PWM_PRI_VECTOR
171 OFF171 IFS5 IEC5 IPC42 IPC42
No
PWM Sec Event(3)
_PWM_SEC_VECTOR
172 OFF172 IFS5 IEC5 IPC43
IPC43
No
PWM1 Combined Interrupt (Period,
_PWM1_VECTOR
173 OFF173 IFS5 IEC5 IPC43 IPC43
No
Fault, Trigger, Current-Limit)(3)
PWM2 Combined Interrupt (Period,
_PWM2_VECTOR
174 OFF174 IFS5 IEC5 IPC43 IPC43
No
Fault, Trigger, Current-Limit)(3)
PWM3 Combined Interrupt (Period,
_PWM3_VECTOR
175 OFF175 IFS5 IEC5 IPC43 IPC43
No
Fault, Trigger, Current-Limit)(3)
PWM4 Combined Interrupt (Period,
_PWM4_VECTOR
176 OFF176 IFS5 IEC5 IPC44
IPC44
No
Fault, Trigger, Current-Limit)(3)
PWM5 Interrupt (Period, Fault,
_PWM5_VECTOR
177 OFF177 IFS5 IEC5 IPC44 IPC44
No
Trigger, Current-Limit)(3)
PWM6 Interrupt (Period, Fault,
_PWM6_VECTOR
178 OFF178 IFS5 IEC5 IPC44 IPC44
No
Trigger, Current-Limit)(3)
Reserved
—
179
—
—
—
—
—
—
Reserved
—
180
—
—
—
—
—
—
Reserved
—
181
—
—
—
—
—
—
DMA Channel 4
_DMA4_VECTOR
182 OFF182 IFS5 IEC5 IPC45 IPC45
Yes
DMA Channel 5
_DMA5_VECTOR
183 OFF183 IFS5 IEC5 IPC45 IPC45
Yes
DMA Channel 6
_DMA6_VECTOR
184 OFF184 IFS5 IEC5 IPC46
IPC46
Yes
DMA Channel 7
_DMA7_VECTOR
185 OFF185 IFS5 IEC5 IPC46 IPC46
Yes
Reserved
—
186
—
—
—
—
—
—
Reserved
—
187
—
—
—
—
—
—
Reserved
—
188
—
—
—
—
—
—
QEI3 Interrupt(3)
_QEI3_VECTOR
189 OFF189 IFS5 IEC5 IPC47 IPC47
Yes
Reserved
—
190
—
—
—
—
—
—
Reserved
—
191
—
—
—
—
—
—
Reserved
—
192
—
—
—
—
—
—
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK Motor Control and General Purpose (MC and GP) Family Features” for the list of
available peripherals.
2: This interrupt source is not available on 48-pin devices.
3: This interrupt source is ONLY available on “MC” variants of the device.
4: Only available on “MC” variants.
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 6-3:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
Reserved
XC32 Vector Name
IRQ
#
Vector #
—
193
—
Interrupt Bit Location
Flag
Enable
Priority
—
—
—
Sub-priority
Persistent
Interrupt
2019-2020 Microchip Technology Inc.
—
—
Reserved
—
194
—
—
—
—
—
—
Reserved
—
195
—
—
—
—
—
—
Reserved
—
196
—
—
—
—
—
—
Reserved
—
197
—
—
—
—
—
—
Reserved
—
198
—
—
—
—
—
—
Reserved
—
199
—
—
—
—
—
—
Reserved
—
200
—
—
—
—
—
—
Reserved
—
201
—
—
—
—
—
—
Reserved
—
202
—
—
—
—
—
—
Reserved
—
203
—
—
—
—
—
—
Reserved
—
204
—
—
—
—
—
—
Reserved
—
205
—
—
—
—
—
—
Reserved
—
206
—
—
—
—
—
—
Reserved
—
207
—
—
—
—
—
—
Reserved
—
208
—
—
—
—
—
—
Reserved
—
209
—
—
—
—
—
—
Reserved
—
210
—
—
—
—
—
—
Reserved
—
211
—
—
—
—
—
—
Reserved
—
212
—
—
—
—
—
—
Reserved
—
213
—
—
—
—
—
—
Reserved
—
214
—
—
—
—
—
—
Reserved
—
215
—
—
—
—
—
—
Reserved
—
216
—
—
—
—
—
—
Reserved
—
217
—
—
—
—
—
—
Reserved
—
218
—
—
—
—
—
—
Reserved
—
219
—
—
—
—
—
—
Reserved
—
220
—
—
—
—
—
—
Reserved
—
221
—
—
—
—
—
—
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK Motor Control and General Purpose (MC and GP) Family Features” for the list of
available peripherals.
2: This interrupt source is not available on 48-pin devices.
3: This interrupt source is ONLY available on “MC” variants of the device.
4: Only available on “MC” variants.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 103
TABLE 6-3:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
DS60001570C-page 104
Reserved
—
222
—
—
—
—
—
—
Reserved
—
223
—
—
—
—
—
—
Reserved
—
224
—
—
—
—
—
—
Reserved
—
225
—
—
—
—
—
—
Reserved
—
226
—
—
—
—
—
—
Reserved
—
227
—
—
—
—
—
—
Reserved
—
228
—
—
—
—
—
—
Reserved
—
229
—
—
—
—
—
—
System Bus Protection Violation
_SYSTEM_BUS_PROTECTION_VECTOR 230 OFF230 IFS7 IEC7 IPC57 IPC57
Yes
Reserved
—
231
—
—
—
—
—
—
Reserved
—
232
—
—
—
—
—
—
Reserved
—
233
—
—
—
—
—
—
Reserved
—
234
—
—
—
—
—
—
Reserved
—
235
—
—
—
—
—
—
Reserved
—
236
—
—
—
—
—
—
Reserved
—
237
—
—
—
—
—
—
PWM7 Interrupt (Period, Fault,
_PWM7_VECTOR
238 OFF238 IFS7 IEC7 IPC59 IPC59
No
Trigger, Current-Limit)(3)
PWM8 Interrupt (Period, Fault,
_PWM8_VECTOR
239 OFF239 IFS7 IEC7 IPC59 IPC59
No
Trigger, Current-Limit)(3)
PWM9 Interrupt (Period, Fault,
_PWM9_VECTOR
240 OFF240 IFS7 IEC7 IPC60
IPC60
No
Trigger, Current-Limit)(3)
Reserved
—
241
—
—
—
—
—
—
Reserved
—
242
—
—
—
—
—
—
Reserved
—
243
—
—
—
—
—
—
Reserved
—
244
—
—
—
—
—
—
ADC Digital Comparator 3
_ADC_DC3_VECTOR
245 OFF245 IFS7 IEC7 IPC61 IPC61
Yes
ADC Digital Comparator 4
_ADC_DC4_VECTOR
246 OFF246 IFS7 IEC7 IPC61 IPC61
Yes
Prefetch Cache Event
_PCACHE_VECTOR
247 OFF247 IFS7 IEC7 IPC61 IPC61
Yes
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK Motor Control and General Purpose (MC and GP) Family Features” for the list of
available peripherals.
2: This interrupt source is not available on 48-pin devices.
3: This interrupt source is ONLY available on “MC” variants of the device.
4: Only available on “MC” variants.
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 6-3:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
Reserved
2:
3:
4:
IRQ
#
Vector #
—
248
—
Interrupt Bit Location
Flag
Enable
Priority
—
—
—
Sub-priority
Persistent
Interrupt
—
—
249 OFF249 IFS7 IEC7 IPC62
IPC62
Yes
250 OFF250 IFS7 IEC7 IPC62 IPC62
Yes
251 OFF251 IFS7 IEC7 IPC62 IPC62
Yes
252 OFF252 IFS7 IEC7
IPC63
IPC62
Yes
—
253
—
—
—
—
—
—
_CORE_PERF_COUNT_VECTOR
254 OFF254 IFS7 IEC7 IPC63 IPC63
—
_CORE_FAST_DEBUG_CHAN_VECTOR
255 OFF255 IFS7 IEC7 IPC63 IPC63
—
Lowest Natural Order Priority
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK Motor Control and General Purpose (MC and GP) Family Features” for the list of
available peripherals.
This interrupt source is not available on 48-pin devices.
This interrupt source is ONLY available on “MC” variants of the device.
Only available on “MC” variants.
CLC1
CLC2
CLC3
CLC4
Reserved
Core Performance Counter Interrupt
Fast Debug Channel Interrupt
Note 1:
XC32 Vector Name
_CLC1_VECTOR
_CLC2_VECTOR
_CLC3_VECTOR
_CLC4_VECTOR
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 105
TABLE 6-3:
Interrupt Control Registers
0000 INTCON
0010
PRISS
0020 INTSTAT
Bits
31/15
30/14
29/13
28/12
—
—
—
MVEC
31:16
15:0
27/11
26/10
25/9
24/8
SWNMIKEY
—
TPC
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
—
—
—
SS0
0000
—
—
—
—
0000
31:16
PRI7SS
PRI6SS
PRI5SS
15:0
PRI3SS
PRI2SS
PRI1SS
31:16
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
SRIPL
31:16
20/4
19/3
18/2
17/1
16/0
All Resets
INTERRUPT REGISTER MAP
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
TABLE 6-4:
—
PRI4SS
—
0000
INT0EP 0000
0000
SIRQ
0000
0000
0030
IPTMR
0040
IFS0(4) 31:16
FCEIF
RTCCIF
—
—
OC5IF
IC5IF
IC5EIF
T5IF
INT4IF
OC4IF
IC4IF
IC4EIF
T4IF
INT3IF
OC3IF
IC3IF
0000
15:0
IC3EIF
T3IF
INT2IF
OC2IF
IC2IF
IC2EIF
T2IF
INT1IF
OC1IF
IC1IF
IC1EIF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
—
—
—
—
—
U2TXIF
U2RXIF
U2EIF
SPI2TXIF
SPI2RXIF
SPI2EIF
—
—
CNGIF
CNFIF
CNEIF
0000
CNDIF
CNCIF
CNBIF
CNAIF
—
—
—
U1TXIF
U1RXIF
U1EIF
SPI1TXIF
SPI1RXIF
SPI1EIF
—
CMP2IF
—
AD1IF
OC9IF
IC9IF
IC9EIF
T9IF
OC8IF
IC8IF
IC8EIF
T8IF
OC7IF
IC7IF
IC7EIF
T7IF
0000
IC6EIF
T6IF
DMA3IF
DMA2IF
DMA1IF
DMA0IF
CTMUIF
—
—
—
—
—
—
—
0000
AD1D16IF
AD1D15IF
AD1D14IF
AD1D8IF
AD1D7IF
0050
IFS1(4) 31:16
15:0
0060
IPTMR
15:0
IFS2(4) 31:16 AD1DC2IF AD1DC1IF
15:0
OC6IF
IC6IF
—
—
0070
IFS3(4) 31:16
0080
IFS4(4) 31:16 AD1D53IF AD1D52IF
15:0 AD1D5IF
0090
00A0
00B0
AD1D4IF
AD1D19IF AD1D18IF AD1D17IF
AD1D3IF
—
AD1D2IF
0000
AD1D13IF AD1D12IF
AD1D11IF
AD1D1IF
AD1D0IF
AD1G1IF AD1FCBTIF AD1RSIF
AD1ARIF
AD1EOSIF
AD1D50IF AD1D49IF
AD1D48IF
AD1D47IF
AD1D46IF
—
—
—
AD1D10IF AD1D9IF
CMP1IF 0000
AD1D6IF 0000
AD1F1IF AD1DF4IF AD1DF3IF AD1DF2IF AD1DF1IF 0000
AD1D41IF AD1D40IF
—
—
0000
AD1D26IF AD1D25IF AD1D24IF
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
AD1D27IF
IFS5(4) 31:16
—
—
QEI3IF
—
—
—
DMA7IF
DMA6IF
DMA5IF
DMA4IF
—
—
—
PWM6IF
PWM5IF
PWM4IF 0000
15:0
PWM3IF
PWM2IF
PWM1IF
PWM
SEVTIF
PWM
PEVTIF
QEI2IF
QEI1IF
—
CAN1IF(3)
—
—
—
—
CMP5IF
CMP4IF
CMP3IF 0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IFS7(4) 31:16
—
CPCIF
—
CLC4
CLC3
CLC2
CLC1
—
—
—
—
—
—
IFS6(4)
00C0
IEC0
00D0
IEC1
AD1DC4IF AD1DC3IF
PWM9IF 0000
DS60001570C-page 106
15:0
PWM8IF
PWM7IF
—
—
—
—
—
—
—
SBIF
—
—
—
—
—
—
0000
31:16
FCEIE
RTCCIE
—
—
OC5IE
IC5IE
IC5EIE
T5IE
INT4IE
OC4IE
IC4IE
IC4EIE
T4IE
INT3IE
OC3IE
IC3IE
0000
15:0
IC3EIE
T3IE
INT2IE
OC2IE
IC2IE
IC2EIE
T2IE
INT1IE
OC1IE
IC1IE
IC1EIE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
0000
31:16
—
—
—
—
—
U2TXIE
U2RXIE
U2EIE
SPI2TXIE
SPI2RXIE
SPI2EIE
—
—
CNGIE
CNFIE
CNEIE
0000
15:0
CNDIE
CNCIE
CNBIE
CNAIE
—
—
—
U1TXIE
U1RXIE
U1EIE
SPI1TXIE
SPI1RXIE
SPI1EIE
—
CMP2IE
CMP1IE 0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition is occurred. The IFSx bits are persistent, hence they must be cleared if they are set
by user software after an IFSx user bit interrogation.
1:
2:
3:
4:
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
6.3
Bits
31/15
30/14
31:16 AD1DC2IE AD1DC1IE
15:0
OC6IE
IC6IE
—
—
29/13
28/12
27/11
26/10
25/9
24/8
-
AD1IE
OC9IE
IC9IE
IC9EIE
IC6EIE
T6IE
DMA3IE
DMA2IE
DMA1IE
AD1D19IE AD1D18IE AD1D17IE
AD1D16IE
AD1D15IE
AD1D14IE
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
T9IE
OC8IE
IC8IE
IC8EIE
T8IE
OC7IE
IC7IE
IC7EIE
T7IE
0000
DMA0IE
CTMUIE
—
—
—
—
—
—
—
0000
00F0
IEC3
31:16
15:0 AD1D05IE AD1D04IE AD1D03IE AD1D02IE AD1D01IE
AD1D00IE
AD1G1IE AD1FCBTIE AD1RSIE
0100
IEC4
31:16 AD1D53IE AD1D52IE
—
AD1D48IE
AD1D47IE
AD1D46IE
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
DMA7IE
15:0
PWM3IE
PWM2IE
PWM1IE
PWM
SEVTIE
PWM
PEVTIE
QEI2IE
31:16
—
—
—
—
—
15:0
—
—
—
—
31:16
—
CPCIE
—
CLC4IE
—
0110
IEC5
0120
IEC6
0130
IEC7
0140
IPC0
0150
IPC1
0160
IPC2
0170
IPC3
0180
IPC4
0190
IPC5
2019-2020 Microchip Technology Inc.
01A0
IPC6
01B0
IPC7
01C0
IPC8
All Resets
Register
Name(1)
IEC2
Bit Range
Virtual Address
(BF81_#)
00E0
INTERRUPT REGISTER MAP (CONTINUED)
AD1D11IE
AD1D10IE AD1D09IE AD1D08IE AD1D07IE AD1D06IE 0000
AD1ARIE
AD1EOSIE
AD1F1IE AD1DF4IE AD1DF3IE AD1DF2IE AD1DF1IE 0000
—
—
—
—
AD1D27IE
DMA6IE
DMA5IE
DMA4IE
—
—
—
PWM6IE
PWM5IE
PWM4IE 0000
QEI1IE
—
CAN1IE(3)
—
—
—
—
CMP5IE
CMP4IE
CMP3IE 0000
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
0000
CLC3IE
CLC2IE
CLC1IE
—
—
—
—
—
—
AD1D50IE AD1D49IE
AD1D13IE AD1D12IE
AD1DC4IE AD1DC3IE
—
AD1D41IE AD1D40IE AD1D39IE AD1D38IE 0000
AD1D26IE AD1D25IE AD1D24IE
—
PWM9IE 0000
—
—
—
—
SBIE
—
—
—
—
INT0IP
INT0IS
—
—
—
CS1IP
CS1IS
0000
15:0
—
—
—
CS0IP
CS0IS
—
—
—
CTIP
CTIS
0000
31:16
—
—
—
OC1IP
OC1IS
—
—
—
IC1IP
IC1IS
0000
15:0
—
—
—
IC1EIP
IC1EIS
—
—
—
T1IP
T1IS
0000
31:16
—
—
—
IC2IP
IC2IS
—
—
—
IC2EIP
IC2EIS
0000
15:0
—
—
—
T2IP
T2IS
—
—
—
INT1IP
INT1IS
0000
31:16
—
—
—
IC3EIP
IC3EIS
—
—
—
T3IP
T3IS
0000
15:0
—
—
—
INT2IP
INT2IS
—
—
—
OC2IP
OC2IS
0000
31:16
—
—
—
T4IP
T4IS
—
—
—
INT3IP
INT3IS
0000
15:0
—
—
—
OC3IP
OC3IS
—
—
—
IC3IP
IC3IS
0000
31:16
—
—
—
INT4IP
INT4IS
—
—
—
OC4IP
OC4IS
0000
15:0
—
—
—
IC4IP
IC4IS
—
—
—
IC4EIP
IC4EIS
0000
31:16
—
—
—
OC5IP
OC5IS
—
—
—
IC5IP
IC5IS
0000
15:0
—
—
—
IC5EIP
IC5EIS
—
—
—
T5IP
T5IS
0000
31:16
—
—
—
FCEIP
FCEIS
—
—
—
RTCCIP
RTCCIS
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
SPI1EIP
SPI1EIS
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
CMP2IP
CMP2IS
—
—
—
CMP1IS
0000
—
—
CMP1IP
—
0000
15:0
—
—
PWM10IE
—
31:16
—
—
PWM12IE PWM11IE
—
—
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition is occurred. The IFSx bits are persistent, hence they must be cleared if they are set
by user software after an IFSx user bit interrogation.
1:
2:
3:
4:
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 107
TABLE 6-4:
01E0
IPC10
01F0
IPC11
0200
IPC12
0210
IPC13
0220
IPC14
0230
IPC15
0240
IPC16
0250
IPC17
0260
IPC18
0270
IPC19
0280
IPC20
0290
IPC21
02A0
IPC22
DS60001570C-page 108
02B0
IPC23
Bits
31/15
30/14
29/13
28/12
23/7
22/6
21/5
31:16
—
—
—
U1RXIP
15:0
—
—
—
SPI1TXIP
U1RXIS
—
—
—
U1EIP
U1EIS
0000
SPI1TXIS
—
—
—
SPI1RXIP
SPI1RXIS
31:16
—
—
—
—
—
—
—
0000
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
U1TXIP
U1TXIS
31:16
—
—
—
CNDIP
0000
CNDIS
—
—
—
CNCIP
CNCIS
15:0
—
—
—
CNBIP
0000
CNBIS
—
—
—
CNAIP
CNAIS
31:16
—
—
—
0000
—
—
—
CNGIP
CNGIS
15:0
—
—
—
CNFIP
0000
CNFIS
—
—
—
CNEIP
CNEIS
31:16
—
—
—
0000
SPI2TXIP
SPI2TXIS
—
—
—
SPI2RXIP
SPI2RXIS
15:0
—
—
—
0000
SPI2EIP
SPI2EIS
—
—
—
31:16
—
—
—
—
—
—
—
U2TXIP
U2TXIS
15:0
—
—
—
0000
U2RXIS
—
—
—
U2EIP
U2EIS
31:16
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
0000
CTMUIS
—
—
—
—
—
—
—
—
15:0
—
—
—
0000
—
—
—
—
—
—
—
31:16
—
—
—
DMA3IP
—
0000
DMA3IS
—
—
—
DMA2IP
DMA2IS
15:0
—
—
—
0000
DMA1IP
DMA1IS
—
—
—
DMA0IP
DMA0IS
31:16
—
—
0000
—
OC6IP
OC6IS
—
—
—
IC6IP
IC6IS
15:0
—
0000
—
—
IC6EIP
IC6EIS
—
—
—
T6IP
T6IS
31:16
0000
—
—
—
OC7IP
OC7IS
—
—
—
IC7IP
IC7IS
0000
15:0
—
—
—
IC7EIP
IC7EIS
—
—
—
T7IP
T7IS
0000
31:16
—
—
—
OC8IP
OC8IS
—
—
—
IC8IP
IC8IS
0000
15:0
—
—
—
IC8EIP
IC8EIS
—
—
—
T8IP
T8IS
0000
31:16
—
—
—
OC9IP
OC9IS
—
—
—
IC9IP
IC9IS
0000
15:0
—
—
—
IC9EIP
IC9EIS
—
—
—
T9IP
T9IS
0000
31:16
—
—
—
AD1DC2IP
AD1DC2IS
—
—
—
AD1DC1IP
AD1DC1IS
0000
15:0
—
—
—
—
—
—
AD1IP
AD1IS
0000
—
—
27/11
—
—
26/10
—
—
U2RXIP
CTMUIP
—
—
—
—
—
—
25/9
—
—
24/8
—
—
—
—
20/4
—
—
19/3
—
—
—
18/2
—
—
17/1
16/0
All Resets
Register
Name(1)
IPC9
Bit Range
Virtual Address
(BF81_#)
01D0
INTERRUPT REGISTER MAP (CONTINUED)
—
—
—
—
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition is occurred. The IFSx bits are persistent, hence they must be cleared if they are set
by user software after an IFSx user bit interrogation.
1:
2:
3:
4:
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 6-4:
02D0
IPC25
02E0
IPC26
02F0
IPC27
0300
IPC28
0310
IPC29
0320
IPC30
0330
IPC31
0340
IPC32
0350
IPC33
0360
IPC34
0370
IPC35
2019-2020 Microchip Technology Inc.
0380
IPC36
0390
IPC37
03A0
IPC38
Bits
31/15
30/14
29/13
28/12
23/7
22/6
21/5
31:16
—
—
—
AD1DF4IP
15:0
—
—
—
AD1DF2IP
AD1DF4IS
—
—
—
AD1DF3IP
AD1DF3IS
0000
AD1DF2IS
—
—
—
AD1DF1IP
AD1DF1IS
31:16
—
—
—
0000
AD1RSIP
AD1RSIS
—
—
—
AD1ARIP
AD1ARIS
15:0
—
—
0000
—
AD1EOSIP
AD1EOSIS
—
—
—
AD1F1IP
AD1F1IS
31:16
—
0000
—
—
AD1D01IP
AD1D01IS
—
—
—
AD1D00IP
AD1D00IS
15:0
0000
—
—
—
AD1G1IP
AD1G1IS
—
—
—
AD1FCBTIP
AD1FCBTIS
0000
31:16
—
—
—
—
—
—
—
—
AD1D04IP
AD1D04IS
0000
15:0
—
—
—
AD1D03IP
AD1D03IS
—
—
—
AD1D02IP
AD1D02IS
0000
31:16
—
—
—
AD1D09IP
AD1D09IS
—
—
—
AD1D08IP
AD1D08IS
0000
15:0
—
—
—
AD1D07IP
AD1D07IS
—
—
—
AD1D06IP
AD1D06IS
0000
31:16
—
—
—
AD1D13IP
AD1D13IS
—
—
—
AD1D12IP
AD1D12IS
0000
15:0
—
—
—
AD1D11IP
AD1D11IS
—
—
—
AD1D10IP
AD1D10IS
0000
31:16
—
—
—
AD1D17IP
AD1D17IS
—
—
—
AD1D16IP
AD1D16IS
0000
15:0
—
—
—
AD1D15IP
AD1D15IS
—
—
—
AD1D14IP
AD1D14IS
0000
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
AD1D19IP
AD1D19IS
—
—
—
31:16
—
—
—
AD1D25IP
AD1D25IS
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
AD1D27IS
—
—
—
AD1D26IS
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
AD1D41IS
—
—
—
AD1D40IS
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
AD1D49IP
AD1D49IS
—
—
—
AD1D48IP
AD1D48IS
0000
15:0
—
—
—
AD1D47IP
AD1D47IS
—
—
—
AD1D46IP
AD1D46IS
0000
—
—
27/11
—
—
26/10
—
—
AD1D27IP
AD1D41IP
25/9
24/8
20/4
—
19/3
18/2
17/1
—
16/0
All Resets
Register
Name(1)
IPC24
Bit Range
Virtual Address
(BF81_#)
02C0
INTERRUPT REGISTER MAP (CONTINUED)
—
0000
AD1D18IP
AD1D18IS
0000
AD1D24IP
AD1D24IS
0000
—
—
AD1D26IP
AD1D40IP
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition is occurred. The IFSx bits are persistent, hence they must be cleared if they are set
by user software after an IFSx user bit interrogation.
1:
2:
3:
4:
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 109
TABLE 6-4:
03C0
IPC40
03D0
IPC41
03E0
IPC42
03F0
IPC43
0400
IPC44
0410
IPC45
0420
IPC46
0430
IPC47
0440
IPC48
0450
IPC49
0460
IPC50
0470
IPC51
0480
IPC52
DS60001570C-page 110
0490
IPC53
Bits
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
—
—
15:0
—
—
—
—
23/7
22/6
21/5
—
—
AD1D53IS
—
—
—
AD1D52IP
AD1D52IS
0000
—
—
—
—
—
AD1D50IP
AD1D50IS
31:16
—
—
—
—
—
—
0000
—
—
—
—
—
CMP5IP
CMP5IS
15:0
—
—
—
CMP4IP
0000
CMP4IS
—
—
—
CMP3IP
CMP3IS
31:16
—
—
—
CAN1IP(3)
0000
CAN1IS(3)
—
—
—
—
—
—
—
15:0
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
31:16
—
—
—
PWMPEVTIP
0000
PWMSEVTIP
—
—
—
QEI2SIP
15:0
—
—
—
0000
QEI1IP
QEI1SIP
—
—
—
—
—
31:16
—
—
0000
—
PWM3IP
PWM3SIP
—
—
—
PWM2IP
PWM2SIP
15:0
—
0000
—
—
PWM1IP
PWM1SIP
—
—
—
PWMSEVTIP
31:16
15:0
—
—
—
—
—
—
—
—
PWM6IP
PWM6SIP
0000
—
—
—
PWM5IP
PWM5SIP
—
—
—
PWM4IP
PWM4SIP
0000
31:16
—
—
—
DMA5IP
DMA5IS
—
—
—
DMA4IP
DMA4IS
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
DMA7IS
—
—
—
DMA6IS
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
QEI3SIP
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
AD1D53IP
—
—
—
—
—
—
DMA7IP
—
—
—
QEI3IP
25/9
24/8
—
20/4
19/3
18/2
QEI2IP
—
—
—
17/1
16/0
All Resets
Register
Name(1)
IPC39
Bit Range
Virtual Address
(BF81_#)
03B0
INTERRUPT REGISTER MAP (CONTINUED)
PWMSEVTSIP 0000
DMA6IP
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition is occurred. The IFSx bits are persistent, hence they must be cleared if they are set
by user software after an IFSx user bit interrogation.
1:
2:
3:
4:
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 6-4:
04B0
IPC55
04C0
IPC56
04D0
IPC57
04F0
IPC59
0500
IPC60
0510
IPC61
0530
IPC63
0540 OFF000
0544 OFF001
0548 OFF002
054C OFF003
2019-2020 Microchip Technology Inc.
0550 OFF004
0554 OFF005
0558 OFF006
Bits
All Resets
Register
Name(1)
IPC54
Bit Range
Virtual Address
(BF81_#)
04A0
INTERRUPT REGISTER MAP (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
PWM8SIP
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
PWM9IP
31:16
—
—
—
—
—
—
—
—
—
—
—
AD1DC4IP
AD1DC4IS
0000
15:0
—
—
—
AD1DC3IS
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
PWM8IP
—
—
AD1DC3IP
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
0000
PWM7SIP
0000
—
0000
—
—
—
0000
PWM9SIP
0000
—
—
—
0000
CPCIS
0000
—
—
—
0000
—
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
—
—
—
—
—
VOFF
—
0000
—
—
CPCIP
—
—
—
VOFF
15:0
31:16
PWM7IP
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
SBIS
VOFF
15:0
31:16
—
SBIP
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition is occurred. The IFSx bits are persistent, hence they must be cleared if they are set
by user software after an IFSx user bit interrogation.
1:
2:
3:
4:
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 111
TABLE 6-4:
055C OFF007
0560 OFF008
0564 OFF009
0568 OFF010
056C OFF011
0570 OFF012
0574 OFF013
0578 OFF014
057C OFF015
0580 OFF016
0584 OFF017
0588 OFF018
058C OFF019
0590 OFF020
0594 OFF021
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS60001570C-page 112
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
VOFF
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
VOFF
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
INTERRUPT REGISTER MAP (CONTINUED)
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition is occurred. The IFSx bits are persistent, hence they must be cleared if they are set
by user software after an IFSx user bit interrogation.
1:
2:
3:
4:
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 6-4:
0598 OFF022
059C OFF023
05A0 OFF024
05A4 OFF025
05A8 OFF026
05AC OFF027
05B8 OFF030
05BC OFF031
05C0 OFF032
05C4 OFF033
05CC OFF035
05D0 OFF036
2019-2020 Microchip Technology Inc.
05D4 OFF037
05D8 OFF038
05DC OFF039
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
VOFF
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
VOFF
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
INTERRUPT REGISTER MAP (CONTINUED)
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition is occurred. The IFSx bits are persistent, hence they must be cleared if they are set
by user software after an IFSx user bit interrogation.
1:
2:
3:
4:
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 113
TABLE 6-4:
05E0 OFF040
05E4 OFF041
05E8 OFF042
05EC OFF043
05F0 OFF044
05F4 OFF045
05F8 OFF046
05FC OFF047
0600 OFF048
0604 OFF049
0608 OFF050
0614 OFF053
0618 OFF054
061C OFF055
0620 OFF056
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS60001570C-page 114
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
VOFF
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
VOFF
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
INTERRUPT REGISTER MAP (CONTINUED)
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition is occurred. The IFSx bits are persistent, hence they must be cleared if they are set
by user software after an IFSx user bit interrogation.
1:
2:
3:
4:
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 6-4:
0624 OFF057
0628 OFF058
062C OFF059
0630 OFF060
0634 OFF061
065C OFF071
0660 OFF072
0664 OFF073
0668 OFF074
066C OFF075
0670 OFF076
0674 OFF077
2019-2020 Microchip Technology Inc.
0678 OFF078
067C OFF079
0680 OFF080
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
VOFF
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
VOFF
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
INTERRUPT REGISTER MAP (CONTINUED)
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition is occurred. The IFSx bits are persistent, hence they must be cleared if they are set
by user software after an IFSx user bit interrogation.
1:
2:
3:
4:
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 115
TABLE 6-4:
0684 OFF081
0688 OFF082
068C OFF083
0690 OFF084
0694 OFF085
0698 OFF086
069C OFF087
06A0 OFF088
06A4 OFF089
06A8 OFF090
06AC OFF091
06B0 OFF092
06B8 OFF094
06BC OFF095
06C0 OFF096
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS60001570C-page 116
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
VOFF
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
VOFF
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
INTERRUPT REGISTER MAP (CONTINUED)
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition is occurred. The IFSx bits are persistent, hence they must be cleared if they are set
by user software after an IFSx user bit interrogation.
1:
2:
3:
4:
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 6-4:
06C4 OFF097
06C8 OFF098
06CC OFF099
06D0 OFF100
06D4 OFF101
06D8 OFF102
06DC OFF103
06E0 OFF104
06E4 OFF105
06E8 OFF106
06EC OFF107
06F0 OFF108
06F4 OFF109
06F8 OFF110
06FC OFF111
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS60001570C-page 117
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
VOFF
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
VOFF
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
INTERRUPT REGISTER MAP (CONTINUED)
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition is occurred. The IFSx bits are persistent, hence they must be cleared if they are set
by user software after an IFSx user bit interrogation.
1:
2:
3:
4:
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 6-4:
0700 OFF112
0704 OFF113
0708 OFF114
070C OFF115
0710 OFF116
0714 OFF117
0718 OFF118
071C OFF119
0720 OFF120
0724 OFF121
0728 OFF122
072C OFF123
0730 OFF124
0734 OFF125
0748 OFF130
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS60001570C-page 118
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
VOFF
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
VOFF
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
INTERRUPT REGISTER MAP (CONTINUED)
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition is occurred. The IFSx bits are persistent, hence they must be cleared if they are set
by user software after an IFSx user bit interrogation.
1:
2:
3:
4:
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 6-4:
074C OFF131
0750 OFF132
0754 OFF133
0788 OFF146
078C OFF147
07A0 OFF152
07A4 OFF153
07A8 OFF154
07AC OFF155
07B0 OFF156
07B8 OFF158
07BC OFF159
2019-2020 Microchip Technology Inc.
07C0 OFF160
07C4 OFF161
07C8 OFF162
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
VOFF
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
VOFF
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
INTERRUPT REGISTER MAP (CONTINUED)
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition is occurred. The IFSx bits are persistent, hence they must be cleared if they are set
by user software after an IFSx user bit interrogation.
1:
2:
3:
4:
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 119
TABLE 6-4:
07DC OFF167
07E4 OFF169
07E8 OFF170
07EC OFF171
07F0 OFF172
07F4 OFF173
07F8 OFF174
07FC OFF175
0800 OFF176
0804 OFF177
0808 OFF178
0818 OFF182
081C OFF183
0820 OFF184
0824 OFF185
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS60001570C-page 120
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
VOFF
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
VOFF
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
INTERRUPT REGISTER MAP (CONTINUED)
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition is occurred. The IFSx bits are persistent, hence they must be cleared if they are set
by user software after an IFSx user bit interrogation.
1:
2:
3:
4:
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 6-4:
0834 OFF189
08D8 OFF230
08F8 OFF238
08FC OFF239
0900 OFF240
0914 OFF245
0918 OFF246
091C OFF247
0924 OFF249
0928 OFF250
0938 OFF254
0938C OFF255
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
VOFF
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
VOFF
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
INTERRUPT REGISTER MAP (CONTINUED)
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
2019-2020 Microchip Technology Inc.
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition is occurred. The IFSx bits are persistent, hence they must be cleared if they are set
by user software after an IFSx user bit interrogation.
1:
2:
3:
4:
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 121
TABLE 6-4:
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 6-1:
Bit
Range
31:24
23:16
15:8
7:0
INTCON: INTERRUPT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
U-0
NMIKEY
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
MVEC
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
TPC
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 NMIKEY: Software Generated NMI Key Register bits
Software NMI event when the correct key (4Eh) is written.
Software NMI event not generated when any other value (not the key) is written.
bit 23-13 Unimplemented: Read as ‘0’
bit 12
MVEC: Multi Vector Configuration bit
1 = Interrupt controller configured for multi vectored mode
0 = Interrupt controller configured for single vectored mode
bit 11
Unimplemented: Read as ‘0’
bit 10-8 TPC: Interrupt Proximity Timer Control bits
111 =Interrupts of group priority 7 or lower start the Interrupt Proximity timer
110 =Interrupts of group priority 6 or lower start the Interrupt Proximity timer
101 =Interrupts of group priority 5 or lower start the Interrupt Proximity timer
100 =Interrupts of group priority 4 or lower start the Interrupt Proximity timer
011 =Interrupts of group priority 3 or lower start the Interrupt Proximity timer
010 =Interrupts of group priority 2 or lower start the Interrupt Proximity timer
001 =Interrupts of group priority 1 start the Interrupt Proximity timer
000 =Disables Interrupt Proximity timer
bit 7-5
Unimplemented: Read as ‘0’
bit 4
INT4EP: External Interrupt 4 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 3
INT3EP: External Interrupt 3 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 2
INT2EP: External Interrupt 2 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 1
INT1EP: External Interrupt 1 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 0
INT0EP: External Interrupt 0 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
DS60001570C-page 122
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 6-2:
Bit
Range
PRISS: PRIORITY SHADOW SELECT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
31:24
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
PRI7SS(1)
R/W-0
23:16
R/W-0
R/W-0
PRI6SS(1)
R/W-0
R/W-0
PRI5SS(1)
R/W-0
15:8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRI1SS(1)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
PRI4SS(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRI2SS(1)
PRI3SS
7:0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
—
—
—
SS0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 PRI7SS: Interrupt with Priority Level 7 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 7 uses Shadow Set 0)
•
•
•
0111 = Interrupt with a priority level of 7 uses Shadow Set 7
0110 = Interrupt with a priority level of 7 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 7 uses Shadow Set 1
0000 = Interrupt with a priority level of 7 uses Shadow Set 0 (default)
bit 27-24 PRI6SS: Interrupt with Priority Level 6 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 6 uses Shadow Set 0)
•
•
•
0111 = Interrupt with a priority level of 6 uses Shadow Set 7
0110 = Interrupt with a priority level of 6 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 6 uses Shadow Set 1
0000 = Interrupt with a priority level of 6 uses Shadow Set 0 (default)
bit 23-20 PRI5SS: Interrupt with Priority Level 5 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 5 uses Shadow Set 0)
•
•
•
0111 = Interrupt with a priority level of 5 uses Shadow Set 7
0110 = Interrupt with a priority level of 5 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 5 uses Shadow Set 1
0000 = Interrupt with a priority level of 5 uses Shadow Set 0 (default)
Note 1:
These bits are ignored if the MVEC bit (INTCON) = 0.
2019-2020 Microchip Technology Inc.
DS60001570C-page 123
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 6-2:
PRISS: PRIORITY SHADOW SELECT REGISTER (CONTINUED)
bit 19-16 PRI4SS: Interrupt with Priority Level 4 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 4 uses Shadow Set 0)
•
•
•
0111 = Interrupt with a priority level of 4 uses Shadow Set 7
0110 = Interrupt with a priority level of 4 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 4 uses Shadow Set 1
0000 = Interrupt with a priority level of 4 uses Shadow Set 0 (default)
bit 15-12 PRI3SS: Interrupt with Priority Level 3 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 3 uses Shadow Set 0)
•
•
•
0111 = Interrupt with a priority level of 3 uses Shadow Set 7
0110 = Interrupt with a priority level of 3 uses Shadow Set 6
•
•
•
bit 11-8
0001 = Interrupt with a priority level of 3 uses Shadow Set 1
0000 = Interrupt with a priority level of 3 uses Shadow Set 0 (default)
PRI2SS: Interrupt with Priority Level 2 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 2 uses Shadow Set 0)
•
•
•
0111 = Interrupt with a priority level of 2 uses Shadow Set 7
0110 = Interrupt with a priority level of 2 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 2 uses Shadow Set 1
0000 = Interrupt with a priority level of 2 uses Shadow Set 0 (default)
bit 7-4
PRI1SS: Interrupt with Priority Level 1 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 1 uses Shadow Set 0)
•
•
•
0111 = Interrupt with a priority level of 1 uses Shadow Set 7
0110 = Interrupt with a priority level of 1 uses Shadow Set 6
•
•
•
bit 3-1
bit 0
0001 = Interrupt with a priority level of 1 uses Shadow Set 1
0000 = Interrupt with a priority level of 1 uses Shadow Set 0 (default)
Unimplemented: Read as ‘0’
SS0: Single Vector Shadow Register Set bit
1 = Single vector is presented with a shadow set
0 = Single vector is not presented with a shadow set
Note 1:
These bits are ignored if the MVEC bit (INTCON) = 0.
DS60001570C-page 124
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 6-3:
Bit
Range
31:24
23:16
15:8
7:0
INTSTAT: INTERRUPT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
SRIPL
R-0
R-0
R-0
SIRQ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10-8
SRIPL: Requested Priority Level bits for Single Vector Mode bits
111-000 = The priority level of the latest interrupt presented to the CPU
bit 7-6
bit 7-0
Unimplemented: Read as ‘0’
SIRQ: Last Interrupt Request Serviced Status bits
11111111-00000000 = The last interrupt request number serviced by the CPU
REGISTER 6-4:
Bit
Range
31:24
23:16
15:8
7:0
IPTMR: INTERRUPT PROXIMITY TIMER REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR
R/W-0
IPTMR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
IPTMR: Interrupt Proximity Timer Reload bits
Used by the Interrupt Proximity Timer as a reload value when the Interrupt Proximity timer is triggered by
an interrupt event.
2019-2020 Microchip Technology Inc.
DS60001570C-page 125
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 6-5:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
IFSx: INTERRUPT FLAG STATUS REGISTER ‘x’ (‘x’ = 0-7)
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS31
IFS30
IFS29
IFS28
IFS27
IFS26
IFS25
IFS24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS23
IFS22
IFS21
IFS20
IFS19
IFS18
IFS17
IFS16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS15
IFS14
IFS13
IFS12
IFS11
IFS10
IFS9
IFS8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS7
IFS6
IFS5
IFS4
IFS3
IFS2
IFS1
IFS0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
31:24
23:16
15:8
7:0
x = Bit is unknown
IFS31-IFS0: Interrupt Flag Status bits
1 = Interrupt request has occurred
0 = No interrupt request has occurred
This register represents a generic definition of the IFSx register. Refer to Table 6-3 for the exact bit
definitions.
REGISTER 6-6:
Bit
Range
Bit
24/16/8/0
Bit
31/23/15/7
IECx: INTERRUPT ENABLE CONTROL REGISTER ‘x’ (‘x’ = 0-7)
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC31
IEC30
IEC29
IEC28
IEC27
IEC26
IEC25
IEC24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC23
IEC22
IEC21
IEC20
IEC19
IEC18
IEC17
IEC16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC15
IEC14
IEC13
IEC12
IEC11
IEC10
IEC9
IEC8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC7
IEC6
IEC5
IEC4
IEC3
IEC2
IEC1
IEC0
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
Note:
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
IEC31-IEC0: Interrupt Enable bits
1 = Interrupt is enabled
0 = Interrupt is disabled
This register represents a generic definition of the IECx register. Refer to Table 6-3 for the exact bit
definitions.
DS60001570C-page 126
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 6-7:
Bit
Range
IPCx: INTERRUPT PRIORITY CONTROL REGISTER ‘x’ (‘x’ = 0-63)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
31:24
23:16
15:8
7:0
Legend:
R = Readable bit
-n = Value at POR
Bit
Bit
28/20/12/4 27/19/11/3
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
IP3
R/W-0
R/W-0
IS3
R/W-0
IP2
R/W-0
R/W-0
R/W-0
IP0
R/W-0
IS2
R/W-0
IP1
R/W-0
R/W-0
R/W-0
R/W-0
IS1
R/W-0
R/W-0
R/W-0
IS0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-26 IP3: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 25-24 IS3: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
bit 23-21 Unimplemented: Read as ‘0’
bit 20-18 IP2: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 17-16 IS2: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
bit 15-13 Unimplemented: Read as ‘0’
Note:
This register represents a generic definition of the IPCx register. Refer to Table 6-3 for the exact bit
definitions.
2019-2020 Microchip Technology Inc.
DS60001570C-page 127
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 6-7:
IPCx: INTERRUPT PRIORITY CONTROL REGISTER ‘x’ (‘x’ = 0-63) (CONTINUED)
bit 12-10 IP1: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
bit 9-8
bit 7-5
bit 4-2
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
IS1: Interrupt Subpriority bits
11 =Interrupt subpriority is 3
10 =Interrupt subpriority is 2
01 =Interrupt subpriority is 1
00 =Interrupt subpriority is 0
Unimplemented: Read as ‘0’
IP0: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
bit 1-0
Note:
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
IS0: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
This register represents a generic definition of the IPCx register. Refer to Table 6-3 for the exact bit
definitions.
DS60001570C-page 128
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 6-8:
Bit
Range
31:24
23:16
15:8
7:0
OFFx: INTERRUPT VECTOR ADDRESS OFFSET REGISTER (x = 0-190)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VOFF
R/W-0
R/W-0
R/W-0
U-0
VOFF
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
R/W-0
R/W-0
R/W-0
VOFF
W = Writable bit
‘1’ = Bit is set
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 17-1 VOFF: Interrupt Vector ‘x’ Address Offset bits
bit 0
Unimplemented: Read as ‘0’
2019-2020 Microchip Technology Inc.
DS60001570C-page 129
PIC32MK GPG/MCJ with CAN FD Family
7.0
Note:
OSCILLATOR
CONFIGURATION
This data sheet summarizes the
features of the PIC32MK GPG/MCJ with
CAN FD Family of devices. It is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section
42.
“Oscillators
with
Enhanced PLL” (DS60001250) in the
“PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
The PIC32MK GPG/MCJ with CAN FD Family
oscillator system has the following modules and
features:
• Five external and internal oscillator options as clock
sources
• On-Chip PLL with user-selectable input divider,
multiplier and output divider to boost operating
frequency on select internal and external oscillator
sources
• On-Chip user-selectable divisor postscaler on select
oscillator sources
• Software-controllable switching between
various clock sources
• A Fail-Safe Clock Monitor (FSCM) that detects clock
failure and permits safe application recovery or shutdown with dedicated Backup FRC (BFRC)
• Flexible reference clock output
• Multiple clock branches for peripherals for better
performance flexibility
A block diagram of the oscillator system is provided
in Figure 7-1. The clock distribution is shown in
Table 7-1.
DS60001570C-page 130
2019-2020 Microchip Technology Inc.
2019-2020 Microchip Technology Inc.
Note
1:
2:
3:
4:
5:
PIC32MK GPG/MCJ WITH CAN FD FAMILY OSCILLATOR DIAGRAM
Refer to 2.0 “Guidelines for Getting Started with 32-bit MCUs” for recommended external crystal component values and restrictions.
The internal POSC feedback resistor, RF, is typically in the range of 2 to 10 M.
The maximum PBCLK6 clock rate to the peripherals in the Low power domain is 30 MHz. This is not the power-up default and must be configured by the user before attempting any access to
those peripherals.
Refer to Table 36-16 in 36.0 “Electrical Characteristics” for PBCLK6 frequency limitations.
CLKO on OSCO pin, if enabled in configuration word, available in EC & FRC mode is PBCLK1 / 2.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 131
FIGURE 7-1:
PIC32MK GPG/MCJ with CAN FD Family
SYSTEM AND PERIPHERAL CLOCK DISTRIBUTION
Peripheral
ADC1-ADC7
X
CAN1
X
REFCLKO4
REFCLKO3
REFCLKO2
REFCLKO1
PBCLK6
X
X
CLKO(5)
X
Comparator 1-5
X
X
X
X
X
X
CRU
X
X
CTMU
X
CDAC1-CDAC2
X
DMA
X
DMT
X
EVIC
X
Flash
X
X
X
Input Capture 1-9
X
ICD
X
Output Compare 1-9
X
Op amp 1-3, 5
X
PORTA-PORTG
X
PPS
X
RTCC
X
X
X
X
SSX Control
X
X
X
X
X
Timer2-Timer9
WDT
X
X
Timer1
UART1-UART2
X
X
SPI1-SPI2
X
X
X
X
X
X
X
CLC1-4
X
HLVD
Note 1:
2:
3:
4:
5:
PBCLK4
X
CFG PMD
CPU
PBCLK2
SPLL
SYSCLK
POSC
SOSC
LPRC
FRC
Clock Source
PBCLK1(1)
TABLE 7-1:
X
PBCLK1 is used by system modules and cannot be turned off.
SYSCLK is used to fetch data from/to the Flash Controller, while the FRC clock is used for programming.
Special Function Register (SFR) access only.
Timer1 only.
PBCLK1 divided by 2 is available on CLKO function pin on oscillator in EC or FRC mode.
DS60001570C-page 132
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
7.1
Fail-Safe Clock Monitor (FSCM)
The PIC32MK GPG/MCJ with CAN FD Family oscillator system includes a Fail-safe Clock Monitor (FSCM).
The FSCM monitors the SYSCLK for continuous operation. If it detects that the SYSCLK has failed, it
switches the SYSCLK over to the BFRC oscillator and
triggers a NMI. When the NMI is executed, software
can attempt to restart the main oscillator or shut down
the system.
In Sleep mode both the SYSCLK and the FSCM halt,
which prevents FSCM detection.
2019-2020 Microchip Technology Inc.
DS60001570C-page 133
Oscillator Control Registers
Register
Name
1200
OSCCON
1210
OSCTUN
1220
SPLLCON
1290 REFO1TRIM
12A0 REFO2CON
12B0 REFO2TRIM
12C0 REFO3CON
12D0 REFO3TRIM
12E0 REFO4CON
12F0 REFO4TRIM
1300
PB1DIV
1310
PB2DIV
DS60001570C-page 134
1330
PB4DIV
1350
PB6DIV(2)
PB7DIV(3)
Bit Range
Bits
1280 REFO1CON
1360
OSCILLATOR CONFIGURATION REGISTER MAP
31/15
30/14
31:16
—
—
15:0
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
—
—
—
—
—
PLLODIV
—
—
—
—
PLLIDIV
15:0
—
31:16
—
15:0
ON
29/13
28/12
27/11
—
—
—
—
COSC
26/10
25/9
24/8
23/7
22/6
21/5
FRCDIV
DRMEN
—
SLP2SPD
NOSC
CLKLOCK
—
—
—
—
—
—
—
—
—
—
—
31:16
—
15:0
ON
—
SIDL
OE
—
—
—
PLLICLK
RSLP
—
DIVSWEN
ACTIVE
—
—
—
—
—
SIDL
OE
RSLP
—
DIVSWEN
ACTIVE
31:16
—
15:0
ON
—
—
—
—
—
—
—
—
SIDL
OE
31:16
—
—
—
RSLP
—
DIVSWEN
ACTIVE
—
ROTRIM
15:0
—
31:16
—
15:0
ON
—
—
—
—
SLPEN
CF
—
SOSCEN
—
—
16/0
—
—
—
—
—
—
—
—
—
—
TUN
SIDL
OE
31:16
RSLP
—
DIVSWEN
ACTIVE
—
ROTRIM
0000
0020
PLLMULT
0xxx
—
—
—
—
PLLRANGE
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
0xxx
0000
ROSEL
0000
0000
ROSEL
0000
0000
ROSEL
0000
RODIV
—
0xx0
OSWEN xxxx
RODIV
0000
ROSEL
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
Refer to Table 36-16 in 36.0 “Electrical Characteristics” for PBCLK6 frequency limitations.
The PB7DIV register is read-only.
1:
2:
3:
—
ROTRIM
—
17/1
RODIV
31:16
15:0
18/2
—
ROTRIM
—
19/3
RODIV
31:16
15:0
20/4
All Resets(1)
Virtual Address
(BF80_#)
TABLE 7-2:
PBDIV
—
—
—
—
8801
PBDIV
—
—
—
—
8801
PBDIV
—
—
—
—
—
—
—
PBDIV
0000
8801
PBDIV
—
0000
0000
8803
0000
8800
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
7.2
Register
Name
SLEWCON
1390
CLKSTAT
Bit Range
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
SPLLRDY
—
SLWDIV
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
Refer to Table 36-16 in 36.0 “Electrical Characteristics” for PBCLK6 frequency limitations.
The PB7DIV register is read-only.
1:
2:
3:
19/3
18/2
—
—
UPEN
DNEN
BUSY
0000
—
—
—
—
—
0000
—
POSCRDY
—
LPRCRDY SOSCRDY
17/1
16/0
All Resets(1)
Virtual Address
(BF80_#)
1380
OSCILLATOR CONFIGURATION REGISTER MAP (CONTINUED)
SYSDIV
0000
FRCRDY 0000
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 135
TABLE 7-2:
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 7-1:
Bit
Range
31:24
23:16
15:8
7:0
OSCCON: OSCILLATOR CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
U-0
—
—
—
—
—
R/W-0
U-0
R/W-y
U-0
U-0
U-0
U-0
DRMEN
—
SLP2SPD
—
—
—
—
—
U-0
R-0
R-0
R-0
U-0
R/W-y
R/W-y
R/W-y
—
COSC
FRCDIV
—
U-0
NOSC
R/W-0
U-0
U-0
R/W-0
R/W-0, HS
U-0
R/W-y
R/W-y
CLKLOCK
—
—
SLPEN
CF
—
SOSCEN
OSWEN(1)
Legend:
R = Readable bit
y = Value set from Configuration bits on POR
HS = Hardware Set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-24 FRCDIV: Internal Fast RC (FRC) Oscillator Clock Divider bits
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2
000 = FRC divided by 1 (default setting)
bit 23
DRMEN: Dream Mode Enable bit
1 = Dream mode is enabled
0 = Dream mode is disabled
bit 22
bit 21
Unimplemented: Read as ‘0’
SLP2SPD: Sleep Two-speed Start-up Control bit
1 = Use FRC as SYSCLK until the selected clock is ready
0 = Use the selected clock directly
bit 20-15 Unimplemented: Read as ‘0’
bit 14-12 COSC: Current Oscillator Selection bits
111 = Reserved
110 = Backup Fast RC (BFRC) Oscillator
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Reserved
010 = Primary Oscillator (POSC) (HS or EC)
001 = System PLL (SPLL) input clock and divider set by SPLLCON
000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (FRCDIV) supports FRN / N, where
‘N’ is 1, 2, 4, 8, 16, 32, 64, and 256
bit 11
Unimplemented: Read as ‘0’
Note 1:
The reset value for this bit depends on the setting of the IESO bit (DEVCFG1). When IESO = 1, the
reset value is ‘1’. When IESO = 0, the reset value is ‘0’.
Note:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL”
(DS60001250) in the “PIC32 Family Reference Manual” for details.
DS60001570C-page 136
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 7-1:
bit 10-8
bit 7
OSCCON: OSCILLATOR CONTROL REGISTER
NOSC: New Oscillator Selection bits
111 = Reserved
110 = Backup Fast RC (BFRC) Oscillator
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Reserved
010 = Primary Oscillator (POSC) (HS or EC)
001 = System PLL (SPLL) input clock and divider set by SPLLCON
000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (FRCDIV) supports FRN/N, where
N is 1, 2, 4, 8, 16, 32, 64, and 256
On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1).
CLKLOCK: Clock Selection Lock Enable bit
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified
bit 6-5
bit 4
Unimplemented: Read as ‘0’
SLPEN: Sleep Mode Enable bit
1 = Device will enter Sleep mode when a WAIT instruction is executed
0 = Device will enter Idle mode when a WAIT instruction is executed
bit 3
CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
Note:
On a clock fail event if enabled by the FCKSM bits (DEVCFG1) = ‘0b11, this bit
and the RNMICON bit will be set. The user software must clear both the bits inside the CF
NMI before attempting to exit the ISR. Software or hardware settings of the CF bit
(OSCCON) will cause a CF NMI event and an automatic clock switch to the FRC provided
the FCKSM = ‘0b11. Unlike the CF bit (OSCCON), software or hardware settings of
the CF bit (RNMICON) will cause a CF NMI event but will not cause a clock switch to the
FRC. After a Clock Fail event, a successful user software clock switch if implemented, hardware
will automatically clear the CF bit (RNMICON), but not the CF bit (OSCCON). The CF
bit (OSCCON) must be cleared by software using the OSCCON register unlock procedure.
bit 2
bit 1
Reserved
SOSCEN: Secondary Oscillator (SOSC) Enable bit
1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator
bit 0
OSWEN: Oscillator Switch Enable bit(1)
1 = Initiate an oscillator switch to selection specified by NOSC bits
0 = Oscillator switch is complete
Note 1:
The reset value for this bit depends on the setting of the IESO bit (DEVCFG1). When IESO = 1, the
reset value is ‘1’. When IESO = 0, the reset value is ‘0’.
Note:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL”
(DS60001250) in the “PIC32 Family Reference Manual” for details.
2019-2020 Microchip Technology Inc.
DS60001570C-page 137
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 7-2:
Bit
Range
31:24
23:16
15:8
7:0
OSCTUN: FRC TUNING REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
R/W-0
(1)
TUN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-6
Unimplemented: Read as ‘0’
bit 5-0
TUN: FRC Oscillator Tuning bits(1)
111111 = +1.453%
•
•
•
100000 = 0.000% (Nominal Center Frequency, default)
•
•
•
000000 =-1.500%
x = Bit is unknown
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither
characterized nor tested.
Note:
Writes to this register require an unlock sequence. Refer to the Section 42. “Oscillators with Enhanced
PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
DS60001570C-page 138
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 7-3:
Bit
Range
31:24
23:16
15:8
7:0
SPLLCON: SYSTEM PLL CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
U-0
U-0
U-0
U-0
U-0
R/W-y
—
—
—
—
—
U-0
R/W-y
R/W-y
R/W-y
—
U-0
R/W-y
Bit
25/17/9/1
Bit
24/16/8/0
R/W-y
R/W-y
PLLODIV
R/W-y
R/W-y
R/W-y
R/W-y
R/W-y
PLLMULT
U-0
U-0
U-0
U-0
R/W-y
—
PLLIDIV
R/W-y
U-0
U-0
U-0
U-0
PLLICLK
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
R/W-y
R/W-y
R/W-y
PLLRANGE
y = Value set from Configuration bits on POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-24 PLLODIV: System PLL Output Clock Divider bits
111 = Reserved
110 = Reserved
101 = PLL Divide by 32
100 = PLL Divide by 16
011 = PLL Divide by 8
010 = PLL Divide by 4
001 = PLL Divide by 2
000 = Reserved
The default setting is specified by the FPLLODIV Configuration bits in the DEVCFG2 register. Refer
to Register 32-5 in 32.0 “Special Features” for information.
bit 23
Unimplemented: Read as ‘0’
bit 22-16 PLLMULT: System PLL Multiplier bits
1111111 = Multiply by 128
1111110 = Multiply by 127
1111101 = Multiply by 126
1111100 = Multiply by 125
•
•
•
0000000 = Multiply by 1
The default setting is specified by the FPLLMULT Configuration bits in the DEVCFG2 register. Refer
to Register 32-5 in 32.0 “Special Features” for information.
bit 15-11 Unimplemented: Read as ‘0’
Note 1:
2:
3:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced
PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
Writes to this register are not allowed if the SPLL is selected as a clock source (COSC = 001).
While the PLL is active, and if updating the PLL bits in the OSCCON register at run-time, the user application must remain within the following limits at all times for all nodes in the PLL clock tree. Therefore, the
order in which the PLL values may be modified, (i.e., PLLODIV, PLLMULT, PLLODIV) becomes important.
Failure to maintain PLL nodes within min/max ranges may result in unstable PLL and system behavior.
• Output and input to PLLIDIV block (i.e., FPLLI) 5 MHz to 64 MHz (min/max at all times)
• VCO output, (i.e., FVCO) 350 MHz to 700 MHz (min/max at all times)
• Output of PLLODIV, (i.e., FPLL) 10 MHz to 120 MHz (min/max at all times)
2019-2020 Microchip Technology Inc.
DS60001570C-page 139
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 7-3:
bit 10-8
SPLLCON: SYSTEM PLL CONTROL REGISTER
PLLIDIV: System PLL Input Clock Divider bits
111 = Divide by 8
110 = Divide by 7
101 = Divide by 6
100 = Divide by 5
011 = Divide by 4
010 = Divide by 3
001 = Divide by 2
000 = Divide by 1
The default setting is specified by the FPLLIDIV Configuration bits in the DEVCFG2 register. Refer to
Register 32-5 in 32.0 “Special Features” for information. If the PLLICLK is set for FRC, this setting is
ignored by the PLL and the divider is set to Divide-by-1.
PLLICLK: System PLL Input Clock Source bit
1 = FRC is selected as the input to the System PLL
0 = POSC is selected as the input to the System PLL
The POR default is specified by the FPLLICLK Configuration bit in the DEVCFG2 register. Refer to
Register 32-5 in 32.0 “Special Features” for information.
Unimplemented: Read as ‘0’
PLLRANGE: System PLL Frequency Range Selection bits
111 = Reserved
110 = 54-64 MHz
101 = 34-64 MHz
100 = 21-42 MHz
011 = 13-26 MHz
010 = 8-16 MHz
001 = 5-10 MHz
000 = Bypass
Use the highest filter range that covers the input freq to the VCO multiplier block that corresponds to the
PLLIDIV output freq to minimize PLL system jitter (see Figure 7-1). For example, Crystal = 20 MHz,
PLLIDIV = 0b1; therefore, the filter input frequency is equal to 10 MHz, and therefore,
PLLRANGE = 0b010. The default setting is specified by the FPLLRNG Configuration bits in the
DEVCFG2 register. Refer to Register 32-5 in 32.0 “Special Features” for information.
bit 7
bit 6-3
bit 2-0
Note 1:
2:
3:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced
PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
Writes to this register are not allowed if the SPLL is selected as a clock source (COSC = 001).
While the PLL is active, and if updating the PLL bits in the OSCCON register at run-time, the user application must remain within the following limits at all times for all nodes in the PLL clock tree. Therefore, the
order in which the PLL values may be modified, (i.e., PLLODIV, PLLMULT, PLLODIV) becomes important.
Failure to maintain PLL nodes within min/max ranges may result in unstable PLL and system behavior.
• Output and input to PLLIDIV block (i.e., FPLLI) 5 MHz to 64 MHz (min/max at all times)
• VCO output, (i.e., FVCO) 350 MHz to 700 MHz (min/max at all times)
• Output of PLLODIV, (i.e., FPLL) 10 MHz to 120 MHz (min/max at all times)
DS60001570C-page 140
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 7-4:
Bit
Range
31:24
23:16
15:8
7:0
REFOxCON: REFERENCE OSCILLATOR CONTROL REGISTER (‘x’ = 1-4)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
R/W-0
R/W-0
R/W-0
—
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RODIV
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0, HC
R-0, HS, HC
(1)
—
SIDL
OE
RSLP(2)
—
DIVSWEN
ACTIVE(1)
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
RODIV
ON
ROSEL
(3)
Legend:
HC = Hardware Cleared
HS = Hardware Set
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
Unimplemented: Read as ‘0’
bit 30-16 RODIV Reference Clock Divider bits
The value selects the reference clock divider bits (see Figure 7-1 for details). A value of ‘0’ selects no
divider.
bit 15
ON: Output Enable bit(1)
1 = Reference Oscillator Module enabled
0 = Reference Oscillator Module disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Peripheral Stop in Idle Mode bit
1 = Discontinue module operation when the device enters Idle mode
0 = Continue module operation in Idle mode
bit 12
OE: Reference Clock Output Enable bit
1 = Reference clock is driven out on REFCLKOx pin
0 = Reference clock is not driven out on REFCLKOx pin
bit 11
RSLP: Reference Oscillator Module Run in Sleep bit(2)
1 = Reference Oscillator Module output continues to run in Sleep
0 = Reference Oscillator Module output is disabled in Sleep
bit 10
Unimplemented: Read as ‘0’
bit 9
DIVSWEN: Divider Switch Enable bit
1 = Divider switch is in progress
0 = Divider switch is complete
bit 8
ACTIVE: Reference Clock Request Status bit(1)
1 = Reference clock request is active
0 = Reference clock request is not active
bit 7-4
Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
5:
Do not write to this register when the ON bit is not equal to the ACTIVE bit.
This bit is ignored when the ROSEL bits = 0000 or 0001.
The ROSEL bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result.
REFOx pin output freq = (ROSEL, Reference Clock Source Freq / (2 * (RODIV + (ROTRIM / 512))
For REFOx resulting frequencies that constitute a fractional result, the circuit will produce an average
clock rate, meaning that the circuit will steal cycles from the input clock source such that the REFOx clock
output over a period of cycles will average out to the desired frequency. For this reason, unless the resulting clock output is a whole integer value, it is not recommend for use as a clock source for ADC or asynchronous peripherals like CAN or UART do to the resulting jitter and clock rate uncertainty.
2019-2020 Microchip Technology Inc.
DS60001570C-page 141
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 7-4:
REFOxCON: REFERENCE OSCILLATOR CONTROL REGISTER (‘x’ = 1-4)
bit 3-0
ROSEL: Reference Clock Source Select bits(3)
1111 = Reserved
•
•
•
1001 = Reserved
1000 = REFCLKI
0111 = SPLL
0110 = Reserved
0101 = SOSC
0100 = LPRC
0011 = FRC
0010 = POSC
0001 = PBCLK1
0000 = SYSCLK
Note 1:
2:
3:
4:
5:
Do not write to this register when the ON bit is not equal to the ACTIVE bit.
This bit is ignored when the ROSEL bits = 0000 or 0001.
The ROSEL bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result.
REFOx pin output freq = (ROSEL, Reference Clock Source Freq / (2 * (RODIV + (ROTRIM / 512))
For REFOx resulting frequencies that constitute a fractional result, the circuit will produce an average
clock rate, meaning that the circuit will steal cycles from the input clock source such that the REFOx clock
output over a period of cycles will average out to the desired frequency. For this reason, unless the resulting clock output is a whole integer value, it is not recommend for use as a clock source for ADC or asynchronous peripherals like CAN or UART do to the resulting jitter and clock rate uncertainty.
DS60001570C-page 142
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 7-5:
Bit
Range
31:24
23:16
15:8
7:0
REFOxTRIM: REFERENCE OSCILLATOR TRIM REGISTER (‘x’ = 1-4)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
ROTRIM
R/W-0
R-0
U-0
U-0
U-0
U-0
U-0
ROTRIM
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-23 ROTRIM: Reference Oscillator Trim bits
111111111 = 511/512 divisor added to RODIV value
111111110 = 510/512 divisor added to RODIV value
•
•
•
100000000 = 256/512 divisor added to RODIV value
•
•
•
000000010 = 2/512 divisor added to RODIV value
000000001 = 1/512 divisor added to RODIV value
000000000 = 0 divisor added to RODIV value
bit 22-0
Note 1:
2:
3:
4:
5:
6:
Unimplemented: Read as ‘0’
While the ON bit (REFOxCON) is ‘1’, writes to this register do not take effect until the DIVSWEN bit is
also set to ‘1’.
Do not write to this register when the ON bit (REFOxCON) is not equal to the ACTIVE bit
(REFOxCON).
Specified values in this register do not take effect if RODIV (REFOxCON) = 0.
REFCLKOx Frequency = ((Selected Source Clock / 2) * (N + (M / 512)))
where, Selected source clock = ROSEL, N = RODIV, and M = ROTRIM.
If the value of REFCLKOx Frequency is not a whole integer value, the output clock will have jitter as it will
cause the REFCLKOx circuit to clock cycle steal to produce an average frequency equivalent to the user
application’s desired frequency. The amount of jitter, (i.e., clock cycle steals), become less as the
fractional remainder value becomes closer to a whole number and is greatest at any value plus 0.5.
REFOx pin output freq = (ROSEL, Reference Clock Source Freq / (2 * (RODIV + (ROTRIM / 512))
For REFOx resulting frequencies that constitute a fractional result, the circuit will produce an
average clock rate, meaning that the circuit will steal cycles from the input clock source such
that the REFOx clock output over a period of cycles will average out to the desired frequency.
For this reason, unless the resulting clock output is a whole integer value, it is not recommend
for use as a clock source for ADC or asynchronous peripherals like CAN or UART do to the
resulting jitter and clock rate uncertainty.
2019-2020 Microchip Technology Inc.
DS60001570C-page 143
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 7-6:
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
(1)
U-0
U-0
U-0
R-1
U-0
U-0
U-0
—
—
—
PBDIVRDY
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1(2)
ON
7:0
PBxDIV: PERIPHERAL BUS ‘x’ CLOCK DIVISOR CONTROL REGISTER
(‘x’ = 1-4, 6)
—
PBDIV
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Peripheral Bus ‘x’ Output Clock Enable bit(1)
1 = Output clock is enabled
0 = Output clock is disabled
bit 14-12 Unimplemented: Read as ‘0’
bit 11
PBDIVRDY: Peripheral Bus ‘x’ Clock Divisor Ready bit
1 = Clock divisor logic is not switching divisors and the PBxDIV bits may be written
0 = Clock divisor logic is currently switching values and the PBxDIV bits cannot be written
bit 10-7
Unimplemented: Read as ‘0’
bit 6-0
PBDIV: Peripheral Bus ‘x’ Clock Divisor Control bits
1111111 = PBCLKx is SYSCLK divided by 128
1111110 = PBCLKx is SYSCLK divided by 127
•
•
•
0000011 = PBCLKx is SYSCLK divided by 4 (default value for x = 6)
0000010 = PBCLKx is SYSCLK divided by 3
0000001 = PBCLKx is SYSCLK divided by 2 (default value for x < 6)
0000000 = PBCLKx is SYSCLK divided by 1 (default value for x = 7)
Note 1: The clock for Peripheral Bus 1 and Peripheral Bus 7 cannot be turned off. Therefore, the ON bit in the
PB1DIV register and the PB7DIV register cannot be written as a ‘0’.
2: The default value for CPU clock PB7DIV Lsb = 0, where PB7CLK = SYSCLK (PB7DIV is read-only).
REFOx pin output freq = (ROSEL, Reference Clock Source Freq / (2 * (RODIV + (ROTRIM / 512))
Note:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL”
(DS60001250) in the “PIC32 Family Reference Manual” for details.
Note:
For REFOx resulting frequencies that constitute a fractional result, the circuit will produce an average clock
rate, meaning that the circuit will steal cycles from the input clock source such that the REFOx clock output
over a period of cycles will average out to the desired frequency. For this reason, unless the resulting clock
output is a whole integer value, it is not recommend for use as a clock source for ADC or asynchronous
peripherals like CAN or UART do to the resulting jitter and clock rate uncertainty.
DS60001570C-page 144
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 7-7:
Bit
Range
31:24
23:16
15:8
7:0
SLEWCON: OSCILLATOR SLEW CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R-0, HS, HC
—
—
—
—
—
UPEN
DNEN
BUSY
SYSDIV(1)
R/W-0
R/W-0
R/W-0
SLWDIV
Legend:
HC = Hardware Cleared HS = Hardware Set
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-20 Unimplemented: Read as ‘0’
bit 19-16 SYSDIV: System Clock Divide Control bits(1)
1111 = SYSCLK is divided by 16
1110 = SYSCLK is divided by 15
•
•
•
0010 = SYSCLK is divided by 3
0001 = SYSCLK is divided by 2
0000 = SYSCLK is not divided
bit 15-11 Unimplemented: Read as ‘0’
bit 10-8
SLWDIV: Slew Divisor Steps Control bits
These bits control the maximum division steps used when slewing during a frequency change.
111 = Steps are divide by 128, 64, 32, 16, 8, 4, 2, and then no divisor
110 = Steps are divide by 64, 32, 16, 8, 4, 2, and then no divisor
101 = Steps are divide by 32, 16, 8, 4, 2, and then no divisor
100 = Steps are divide by 16, 8, 4, 2, and then no divisor
011 = Steps are divide by 8, 4, 2, and then no divisor
010 = Steps are divide by 4, 2, and then no divisor
001 = Steps are divide by 2, and then no divisor
000 = No divisor is used during slewing
The steps apply in reverse order (i.e., 2, 4, 8, etc.) during a downward frequency change.
bit 7-3
Unimplemented: Read as ‘0’
bit 2
UPEN: Upward Slew Enable bit
1 = Slewing enabled for switching to a higher frequency
0 = Slewing disabled for switching to a higher frequency
bit 1
DNEN: Downward Slew Enable bit
1 = Slewing enabled for switching to a lower frequency
0 = Slewing disabled for switching to a lower frequency
bit 0
BUSY: Clock Switching Slewing Active Status bit
1 = Clock frequency is being actively slewed to the new frequency
0 = Clock switch has reached its final value
Note 1:
The SYSDIV bit settings are ignored if both UPEN and DNEN = 0, and SYSCLK will be divided by 1.
2019-2020 Microchip Technology Inc.
DS60001570C-page 145
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 7-8:
Bit
Range
31:24
23:16
15:8
7:0
CLKSTAT: OSCILLATOR CLOCK STATUS REGISTER
Bit
31/23/15/7
U-0
Bit
Bit
30/22/14/6 29/21/13/5
U-0
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
U-0
R-0
R-0
U-0
R-0
U-0
R-0
SPLLRDY
—
—
POSCRDY
—
FRCRDY
LPRCRDY SOSCRDY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-8
Unimplemented: Read as ‘0’
bit 7
SPLLRDY: System PLL (SPLL) Ready Status bit
1 = SPLL is ready
0 = SPLL is not ready
bit 5
LPRCRDY: Low-Power RC (LPRC) Oscillator Ready Status bit
1 = LPRC is stable and ready
0 = LPRC is disabled or not operating
bit 4
SOSCRDY: Secondary Oscillator (SOSC) Ready Status bit
1 = SOSC is stable and ready
0 = SOSC is disabled or not operating
bit 3
Unimplemented: Read as ‘0’
bit 2
POSCRDY: Primary Oscillator (POSC) Ready Status bit
1 = POSC is stable and ready
0 = POSC is disabled or not operating
bit 1
Unimplemented: Read as ‘0’
bit 0
FRCRDY: Fast RC (FRC) Oscillator Ready Status bit
1 = FRC is stable and ready
0 = FRC is disabled for not operating
DS60001570C-page 146
x = Bit is unknown
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
NOTES:
2019-2020 Microchip Technology Inc.
DS60001570C-page 147
PIC32MK GPG/MCJ with CAN FD Family
8.0
PREFETCH MODULE
Note:
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
Cache Module” (DS60001119), which is
available from the Documentation > Reference Manual section of the Microchip
PIC32 web site (www.microchip.com/
pic32).
The Prefetch module is a performance enhancing
module that is included in the PIC32MK GPG/MCJ with
CAN FD Family of devices. When running at high-clock
rates, Wait states must be inserted into Program Flash
Memory (PFM) read transactions to meet the access
time of the PFM. Wait states can be hidden to the core
by prefetching and storing instructions in a temporary
holding area that the CPU can access quickly. Although
the data path to the CPU is 32 bits wide, the data path
to the PFM is 128 bits wide. This wide data path
provides the same bandwidth to the CPU as a 32-bit
path running at four times the frequency.
FIGURE 8-1:
The Prefetch module holds a subset of PFM in
temporary holding spaces known as lines. Each line
contains a tag and data field. Normally, the lines hold a
copy of what is currently in memory to make
instructions or data available to the CPU without Flash
Wait states.
8.1
•
•
•
•
•
•
Prefetch Cache Features
36x16 byte fully-associative lines
16 lines for CPU instructions
Four lines for CPU data
Four lines for peripheral data
16-byte parallel memory fetch
Configurable predictive prefetch
A simplified block diagram of the Prefetch module is
shown in Figure 8-1.
PREFETCH MODULE BLOCK DIAGRAM
SYSCLK
CPU
Prefetch Buffer
Data
CPU
Tag
Bus Control
Line Control
Program Flash Memory (PFM)
DS60001570C-page 148
2019-2020 Microchip Technology Inc.
Prefetch Control Registers
PREFETCH REGISTER MAP
31/15
30/14
29/13
28/12
27/11
31:16
—
—
—
—
—
15:0
—
—
—
CHE
PERFEN
—
0800 CHECON
0820 CHEHIT
0830 CHEMIS
Legend:
26/10
25/9
24/8
23/7
PERCHEEN DCHEEN ICHEEN
—
PFM
AWSEN
—
—
—
22/6
21/5
20/4
PER
DCHEINV ICHEINV
CHEINV
—
PREFEN
19/3
—
—
18/2
17/1
16/0
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF80_#)
TABLE 8-1:
PER
DCHECOH ICHECOH 0700
CHECOH
PFMWS
0107
31:16
CHEHIT
0000
15:0
CHEHIT
0000
31:16
CHEMIS
0000
15:0
CHEMIS
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 149
8.2
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 8-1:
Bit
Range
31:24
23:16
15:8
7:0
CHECON: CACHE MODULE CONTROL REGISTER
Bit
Bit
31/23/15/7 30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
—
—
—
—
—
PERCHEEN
DCHEEN
ICHEEN
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
—
PER
DCHEINV(1) ICHEINV(1)
CHEINV(1)
—
PER
DCHECOH(2) ICHECOH(2)
CHECOH(2)
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
R/W-1
—
—
—
CHE
PERFEN
—
—
—
PFM
AWSEN
U-0
U-0
R/W-0
R/W-0
U-0
R/W-1
R/W-1
R/W-1
—
—
PREFEN
PFMWS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26
PERCHEEN: Peripheral Cache Enable bit
1 = Peripheral cache is enabled
0 = Peripheral cache is disabled
bit 25
DCHEEN: Data Cache Enable bit
1 = Data cache is enabled
0 = Data cache is disabled
bit 24
ICHEEN: Instruction Cache Enable bit
1 = Instruction cache is enabled
0 = Instruction cache is disabled
bit 23
Unimplemented: Read as ‘0’
bit 22
PERCHEINV: Peripheral Cache Invalidate bit(1)
1 = Force invalidate cache/invalidate busy
0 = Cache Invalidation follows CHECOH/invalid complete
bit 21
DCHEINV: Data Cache Invalidate bit(1)
1 = Force invalidate cache/invalidate busy
0 = Cache Invalidation follows CHECOH/invalid complete
bit 20
ICHEINV: Instruction Cache Invalidate bit(1)
1 = Force invalidate cache/invalidate busy
0 = Cache Invalidation follows CHECOH/invalid complete
bit 19
Unimplemented: Read as ‘0’
bit 18
PERCHECOH: Peripheral Auto-cache Coherency Control bit(2)
1 = Automatically invalidate cache on a programming event
0 = Do not automatically invalidate cache on a programming event
bit 17
DCHECOH: Data Auto-cache Coherency Control bit(2)
1 = Automatically invalidate cache on a programming event
0 = Do not automatically invalidate cache on a programming event
Note 1:
2:
Hardware automatically clears this bit when cache invalidate completes. Bits may clear at different times.
The PERCHECOH, DCHECOH, and ICHECOH bits must be stable before initiation of programming.
DS60001570C-page 150
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 8-1:
bit 16
CHECON: CACHE MODULE CONTROL REGISTER (CONTINUED)
ICHECOH: Instruction Auto-cache Coherency Control bit(2)
1 = Automatically invalidate cache on a programming event
0 = Do not automatically invalidate cache on a programming event
bit 15-13 Unimplemented: Read as ‘0’
bit 12
CHEPERFEN: Cache Performance Counters Enable bit
1 = Performance counters are enabled
0 = Performance counters are disabled
bit 11-9
Unimplemented: Read as ‘0’
bit 8
PFMAWSEN: PFM Address Wait State Enable bit
1 = Add one more Wait State to flash address setup (suggested for higher system clock frequencies)
0 = Add no Wait States to the flash address setup (suggested for lower system clock frequencies to achieve
higher performance)
When this bit is set to ‘1’, total Flash wait states are PFMWS plus PFMAWSEN.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
PREFEN: Predictive Prefetch Enable bits
11 = Disable predictive prefetch
10 = Disable predictive prefetch
01 = Enable predictive prefetch for CPU instructions only
00 = Disable predictive prefetch
bit 3-0
PFMWS: PFM Access Time Defined in Terms of SYSCLK Wait States bits
0111 =Seven Wait states
•
•
•
010 = Two Wait states
001 = One Wait state
000 = Zero Wait states
DEVCFG0
FECCCON bits
(DEVCFG0) = 0x1x
with ECC disabled
FECCCON bits
(DEVCFG0) = 0x0x
with ECC enabled
Note 1:
2:
Required Flash Wait States
PFMWS bits
1 - Wait State
2 - Wait State
1 - Wait State
2 - Wait State
SYSCLK (MHz)
0 < SYSCLK 116 MHz
116 MHz < SYSCLK 120
MHz
0 < SYSCLK 96 MHz
96 MHz < SYSCLK 120 MHz
Hardware automatically clears this bit when cache invalidate completes. Bits may clear at different times.
The PERCHECOH, DCHECOH, and ICHECOH bits must be stable before initiation of programming.
2019-2020 Microchip Technology Inc.
DS60001570C-page 151
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 8-2:
Bit
Range
31:24
23:16
15:8
7:0
CHEHIT: CACHE HIT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHEHIT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHEHIT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHEHIT
R/W-0
CHEHIT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
CHEHIT: Instruction Cache Hit Count bits
When the CHEPERFEN bit (CHECON) = 1, the CHEHIT bits increment each time the processor issues an instruction fetch or load that hits the prefetch cache from a cacheable region. Non-cacheable
accesses do not modify this value.
The CHEHIT bits are reset on a ‘0’ to ‘1’ transition of the CHEPERFEN bit.
DS60001570C-page 152
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 8-3:
Bit
Range
31:24
23:16
15:8
7:0
CHEMIS: CACHE MISS STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHEMIS
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHEMIS
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHEMIS
R/W-0
CHEMIS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
CHEMIS: Instruction Cache Miss Count bits
When the CHEPERFEN bit (CHECON) = 1, the CHEMIS bits increment each time the processor issues an instruction fetch or load that hits the prefetch cache from a cacheable region. Non-cacheable
accesses do not modify this value.
The CHEMIS bits are reset on a ‘0’ to ‘1’ transition of the CHEPERFEN bit.
2019-2020 Microchip Technology Inc.
DS60001570C-page 153
PIC32MK GPG/MCJ with CAN FD Family
9.0
DIRECT MEMORY ACCESS
(DMA) CONTROLLER
Note:
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 31. “Direct Memory
Access
(DMA)
Controller”
(DS60001117), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The Direct Memory Access (DMA) Controller is a bus
master module useful for data transfers between
different devices without CPU intervention. The source
and destination of a DMA transfer can be any of the
memory mapped modules existent in the device, such
as SPI, UART, PMP, etc., or memory itself.
The following are some of the key features of the DMA
Controller module:
• Eight identical channels, each featuring:
- Auto-increment source and destination
address registers
- Source and destination pointers
- Memory-to-memory and memory-toperipheral transfers
• Automatic word-size detection:
- Transfer granularity, down to byte level
- Bytes need not be word-aligned at source and
destination
FIGURE 9-1:
DMA BLOCK DIAGRAM
INT Controller
Peripheral Bus
• Fixed priority channel arbitration
• Flexible DMA channel operating modes:
- Manual (software) or automatic (interrupt) DMA
requests
- One-Shot or Auto-Repeat Block Transfer modes
- Channel-to-channel chaining
• Flexible DMA requests:
- A DMA request can be selected from any of the
peripheral interrupt sources
- Each channel can select any (appropriate)
observable interrupt as its DMA request source
- A DMA transfer abort can be selected from any
of the peripheral interrupt sources
- Up to 2-byte Pattern (data) match transfer
termination
• Multiple DMA channel status interrupts:
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half full
- DMA transfer aborted due to an external event
- Invalid DMA address generated
• DMA debug support features:
- Most recent error address accessed by a DMA
channel
- Most recent DMA channel to transfer data
• CRC Generation module:
- CRC module can be assigned to any of the
available channels
- CRC module is highly configurable
System IRQ
Address Decoder
Channel 0 Control
I0
Channel 1 Control
I1
SE
L
Y
DMA
Bus
Interface
SYSCLK
System Bus + Bus Arbitration
I2
Global Control
(DMACON)
Channel n Control
In
L
SE
Channel Priority
Arbitration
DS60001570C-page 154
2019-2020 Microchip Technology Inc.
DMA Control Registers
Register
Name(1)
Bit Range
DMA GLOBAL REGISTER MAP
Virtual Address
(BF81_#)
TABLE 9-1:
1000
DMACON
31:16
15:0
—
ON
—
—
—
—
1010
DMASTAT
31:16
15:0
RDWR
—
—
—
—
—
1020 DMAADDR
31:16
15:0
Legend:
Note 1:
30/14
29/13
28/12
27/11
—
—
SUSPEND DMABUSY
—
—
—
—
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMACH
—
0000
0000
0000
0000
DMAADDR
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more information.
TABLE 9-2:
Virtual Address
(BF81_#)
31/15
All Resets
Bits
DMA CRC REGISTER MAP
1030 DCRCCON
1040 DCRCDATA
2019-2020 Microchip Technology Inc.
1050 DCRCXOR
31/15
30/14
31:16
—
—
15:0
—
—
31:16
15:0
31:16
15:0
29/13
28/12
BYTO
—
27/11
WBO
26/10
25/9
24/8
—
—
BITO
PLEN
23/7
—
CRCEN
DCRCDATA
DCRCXOR
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
—
—
CRCAPP CRCTYP
17/1
16/0
—
—
CRCCH
All Resets
Bit Range
Register
Name(1)
Bits
0000
0000
0000
0000
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
1:
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 155
9.1
Virtual Address
(BF81_#)
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP
1060 DCH0CON
1070 DCH0ECON
31/15
30/14
29/13
31:16
15:0 CHBUSY
—
CHPIGNEN
31:16
—
—
—
15:0
—
—
—
—
—
—
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
—
—
CHCHNS
—
CHEN
—
CHAED
—
CHCHN
—
CHAEN
—
—
—
CHEDET
—
—
CHSIRQ
—
—
—
PATEN
CHAIRQ
SIRQEN AIRQEN
—
—
—
—
CHPIGN
—
CHPATLEN
—
—
CFORCE CABORT
—
—
—
—
CHSDIE
CHSDIF
CHSHIE
CHSHIF
CHDDIE
CHDDIF
CHDHIE
CHDHIF
CHBCIE
CHBCIF
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Bits
—
—
CHPRI
0000
0000
—
—
00FF
FF00
CHCCIE
CHCCIF
CHTAIE
CHTAIF
—
CHERIE 0000
CHERIF 0000
DCH0INT
31:16
15:0
1090 DCH0SSA
31:16
15:0
CHSSA
0000
0000
10A0 DCH0DSA
31:16
15:0
CHDSA
0000
0000
10B0 DCH0SSIZ
31:16
15:0
—
—
—
—
—
—
—
—
—
CHSSIZ
—
—
—
—
—
—
—
0000
0000
10C0 DCH0DSIZ
31:16
15:0
—
—
—
—
—
—
—
—
—
CHDSIZ
—
—
—
—
—
—
—
0000
0000
10D0 DCH0SPTR
31:16
15:0
—
—
—
—
—
—
—
—
—
CHSPTR
—
—
—
—
—
—
—
0000
0000
10E0 DCH0DPTR
31:16
15:0
—
—
—
—
—
—
—
—
—
CHDPTR
—
—
—
—
—
—
—
0000
0000
10F0 DCH0CSIZ
31:16
15:0
—
—
—
—
—
—
—
—
—
CHCSIZ
—
—
—
—
—
—
—
0000
0000
1100 DCH0CPTR
31:16
15:0
—
—
—
—
—
—
—
—
—
CHCPTR
—
—
—
—
—
—
—
0000
0000
1110
31:16
15:0
—
—
—
—
—
—
—
—
—
CHPDAT
—
—
—
—
—
—
—
0000
0000
—
—
0000
—
CHPIGNEN
—
CHPATLEN
—
—
CHCHNS
CHPRI
0000
—
—
—
—
—
—
—
1080
DCH0DAT
1120 DCH1CON
1130 DCH1ECON
DS60001570C-page 156
1140
DCH1INT
1150 DCH1SSA
1160 DCH1DSA
Legend:
Note
1:
31:16
CHPIGN
15:0 CHBUSY
31:16
—
15:0
CHSIRQ
—
—
—
—
—
—
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHAIRQ
CFORCE CABORT
00FF
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
31:16
15:0
31:16
CHSSA
CHDSA
15:0
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
0000
0000
0000
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 9-3:
Virtual Address
(BF81_#)
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
1170 DCH1SSIZ
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
CHSSIZ
All Resets
Bit Range
Register
Name(1)
Bits
0000
0000
31:16
1180 DCH1DSIZ
15:0
—
—
—
—
—
—
—
—
—
CHDSIZ
—
—
—
—
—
—
—
0000
0000
31:16
—
—
—
—
—
—
—
—
—
CHSPTR
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHDPTR
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHCSIZ
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
CHCPTR
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
0000
PATEN
CHAIRQ
SIRQEN AIRQEN
—
—
00FF
FF00
CHCCIE
CHCCIF
CHTAIE
CHTAIF
1190 DCH1SPTR
11A0 DCH1DPTR
11B0 DCH1CSIZ
11C0 DCH1CPTR
11D0 DCH1DAT
11E0 DCH2CON
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
—
—
CHPDAT
31:16
15:0 CHBUSY
—
CHPIGNEN
—
—
CHPIGN
—
CHPATLEN
—
—
CHCHNS
—
—
CHSIRQ
—
—
—
—
—
—
—
0000
31:16
11F0 DCH2ECON
15:0
—
DCH2INT
31:16
15:0
—
—
1210 DCH2SSA
31:16
15:0
CHSSA
0000
0000
1220 DCH2DSA
31:16
15:0
CHDSA
0000
0000
1230 DCH2SSIZ
31:16
15:0
—
—
—
—
—
—
—
—
—
CHSSIZ
—
—
—
—
—
—
—
0000
0000
1240 DCH2DSIZ
31:16
15:0
—
—
—
—
—
—
—
—
—
CHDSIZ
—
—
—
—
—
—
—
0000
0000
1250 DCH2SPTR
31:16
15:0
—
—
—
—
—
—
—
—
—
CHSPTR
—
—
—
—
—
—
—
0000
0000
1260 DCH2DPTR
31:16
15:0
—
—
—
—
—
—
—
—
—
CHDPTR
—
—
—
—
—
—
—
0000
0000
1270 DCH2CSIZ
31:16
15:0
—
—
—
—
—
—
—
—
—
CHCSIZ
—
—
—
—
—
—
—
0000
0000
1200
2019-2020 Microchip Technology Inc.
Legend:
Note
1:
—
—
—
—
—
—
CFORCE CABORT
—
—
—
—
CHSDIE
CHSDIF
CHSHIE
CHSHIF
CHDDIE
CHDDIF
CHDHIE
CHDHIF
CHBCIE
CHBCIF
—
CHERIE 0000
CHERIF 0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 157
TABLE 9-3:
Virtual Address
(BF81_#)
1290 DCH2DAT
12A0 DCH3CON
12B0 DCH3ECON
DCH3INT
12D0 DCH3SSA
12E0 DCH3DSA
12F0 DCH3SSIZ
1300 DCH3DSIZ
1310 DCH3SPTR
1320 DCH3DPTR
1330 DCH3CSIZ
1340 DCH3CPTR
1350 DCH3DAT
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
DS60001570C-page 158
1380
DCH4INT
Legend:
Note
1:
—
—
CHPIGNEN
31:16
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
CHPATLEN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHAED
—
CHCHN
—
CHAEN
—
—
—
CHEDET
PATEN
CHAIRQ
SIRQEN AIRQEN
—
—
—
—
—
—
—
—
—
CHEN
—
—
—
—
CHSDIE
CHSDIF
0000
CHSHIE
CHSHIF
CHDDIE
CHDDIF
CHDHIE
CHDHIF
CHBCIE
CHBCIF
0000
0000
—
—
00FF
FF00
CHCCIE
CHCCIF
CHTAIE
CHTAIF
—
CHERIE 0000
CHERIF 0000
0000
0000
0000
CHDSA
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHAED
—
CHCHN
—
CHAEN
—
—
—
CHEDET
PATEN
CHAIRQ
SIRQEN AIRQEN
CHSSIZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
15:0
—
—
—
—
CHPIGNEN
—
—
15:0
—
—
—
—
—
—
—
—
CHCHNS
—
—
CHSIRQ
—
—
—
—
—
—
—
—
—
—
CHEN
—
—
CHSDIE
CHSDIF
0000
0000
CFORCE CABORT
—
—
0000
0000
CHPDAT
CHPIGN
—
CHPATLEN
0000
0000
CHCPTR
—
0000
0000
CHCSIZ
—
0000
0000
CHDPTR
—
0000
0000
CHSPTR
—
0000
0000
CHDSIZ
—
0000
—
—
CHPRI
CHSSA
—
0000
0000
CFORCE CABORT
15:0
31:16
15:0
—
—
15:0
31:16
—
—
15:0
31:16
16/0
—
15:0
31:16
17/1
—
—
CHSIRQ
15:0
31:16
18/2
CHCHNS
31:16
31:16
19/3
—
15:0
31:16
20/4
—
31:16
31:16
21/5
CHPIGN
15:0 CHBUSY
31:16
22/6
CHPDAT
31:16
1360 DCH4CON
15:0 CHBUSY
1370 DCH4ECON
—
31:16
15:0
23/7
CHCPTR
15:0
31:16
24/8
All Resets
Bit Range
Register
Name(1)
Bits
1280 DCH2CPTR
12C0
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
CHSHIE
CHSHIF
CHDDIE
CHDDIF
CHDHIE
CHDHIF
CHBCIE
CHBCIF
—
—
CHPRI
0000
0000
—
—
00FF
FF00
CHCCIE
CHCCIF
CHTAIE
CHTAIF
—
CHERIE 0000
CHERIF 0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 9-3:
Virtual Address
(BF81_#)
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
1390 DCH4SSA
13A0 DCH4DSA
13B0 DCH4SSIZ
13C0 DCH4DSIZ
13D0 DCH4SPTR
13E0 DCH4DPTR
13F0 DCH4CSIZ
1400 DCH4CPTR
1410 DCH4DAT
31/15
1440
DCH5INT
2019-2020 Microchip Technology Inc.
1450 DCH5SSA
1460 DCH5DSA
1470 DCH5SSIZ
1480 DCH5DSIZ
1490 DCH5SPTR
29/13
28/12
27/11
26/10
25/9
31:16
31:16
—
CHSSIZ
—
—
—
—
—
—
—
—
—
0000
0000
—
—
CHDSIZ
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
CHSPTR
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CHCSIZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPIGNEN
—
—
—
—
CHCHNS
—
—
—
—
—
CHSIRQ
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
CHAIRQ
00FF
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
0000
0000
0000
CHDSA
15:0
—
—
—
—
—
—
—
15:0
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSSIZ
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
CHSPTR
0000
0000
CHDSIZ
—
FF00
—
CHSSA
15:0
0000
0000
CFORCE CABORT
—
0000
0000
CHPDAT
CHPIGN
—
CHPATLEN
0000
0000
CHCPTR
—
15:0
—
CHDPTR
—
31:16
0000
0000
0000
0000
31:16
31:16
0000
—
—
15:0
31:16
16/0
—
—
15:0
31:16
17/1
—
—
15:0
31:16
18/2
—
—
15:0
31:16
19/3
—
—
15:0
31:16
20/4
—
—
15:0
31:16
21/5
—
—
15:0
31:16
22/6
—
—
15:0
31:16
23/7
CHDSA
15:0
31:16
24/8
CHSSA
15:0
31:16
1420 DCH5CON
15:0 CHBUSY
1430 DCH5ECON
30/14
All Resets
Bit Range
Register
Name(1)
Bits
0000
0000
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
1:
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 159
TABLE 9-3:
Virtual Address
(BF81_#)
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
14A0 DCH5DPTR
14B0 DCH5CSIZ
14C0 DCH5CPTR
14D0 DCH5DAT
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
1500
DCH6INT
1510 DCH6SSA
1520 DCH6DSA
1530 DCH6SSIZ
1540 DCH6DSIZ
1550 DCH6SPTR
1560 DCH6DPTR
1570 DCH6CSIZ
1580 DCH6CPTR
DS60001570C-page 160
1590 DCH6DAT
Note
1:
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
CHCSIZ
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
CHCPTR
—
—
—
—
—
—
—
—
—
0000
0000
—
CHAED
—
CHCHN
—
CHAEN
—
—
—
CHEDET
PATEN
SIRQEN
AIRQEN
—
—
CHPDAT
—
—
CHPIGNEN
—
—
15:0
CHPIGN
—
CHPATLEN
—
—
CHCHNS
—
—
—
—
—
CHSIRQ
—
CHEN
0000
—
—
CHPRI
CHAIRQ
CFORCE CABORT
0000
0000
00FF
—
FF00
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
31:16
31:16
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
CHPIGNEN
—
—
CHCHNS
—
CHEN
—
CHAED
—
CHCHN
—
CHAEN
—
—
—
CHEDET
0000
0000
0000
0000
0000
0000
0000
0000
CHPDAT
CHPIGN
—
CHPATLEN
0000
0000
CHCPTR
—
0000
0000
CHCSIZ
15:0
31:16
0000
—
CHDPTR
15:0
31:16
—
CHSPTR
15:0
31:16
—
CHDSIZ
15:0
31:16
0000
CHSSIZ
15:0
31:16
0000
CHDSA
15:0
31:16
0000
CHSSA
15:0
31:16
15A0 DCH7CON
15:0 CHBUSY
Legend:
20/4
—
15:0
31:16
21/5
—
31:16
14E0 DCH6CON
15:0 CHBUSY
14F0 DCH6ECON
22/6
—
15:0
31:16
23/7
CHDPTR
—
—
15:0
31:16
24/8
All Resets
Bit Range
Register
Name(1)
Bits
0000
0000
—
—
CHPRI
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 9-3:
Virtual Address
(BF81_#)
DCH7INT
15D0 DCH7SSA
15E0 DCH7DSA
15F0 DCH7SSIZ
1600 DCH7DSIZ
1610 DCH7SPTR
1620 DCH7DPTR
1630 DCH7CSIZ
1640 DCH7CPTR
1650 DCH7DAT
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
CHSIRQ
—
—
15:0
—
—
—
—
—
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
17/1
16/0
CHAIRQ
00FF
—
CFORCE CABORT PATEN
CHSDIE CHSHIE CHDDIE
SIRQEN
CHDHIE
AIRQEN
CHBCIE
—
CHCCIE
—
CHTAIE
—
FF00
CHERIE 0000
—
CHSDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
0000
CHSHIF
CHDDIF
0000
0000
—
—
—
—
—
—
—
—
0000
0000
CHSSIZ
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPDAT
0000
0000
0000
0000
CHCPTR
—
0000
0000
CHCSIZ
15:0
31:16
18/2
CHDPTR
15:0
31:16
19/3
CHSPTR
15:0
31:16
20/4
CHDSIZ
15:0
31:16
21/5
CHDSA
15:0
31:16
22/6
CHSSA
15:0
31:16
23/7
All Resets
Bit Range
Register
Name(1)
Bits
15B0 DCH7ECON
15C0
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
0000
0000
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
1:
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 161
TABLE 9-3:
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-1:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
U-0
DMACON: DMA CONTROLLER CONTROL REGISTER
Bit
Bit
30/22/14/6 29/21/13/5
U-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
ON
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
SUSPEND(1) DMABUSY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: DMA On bit
1 = DMA module is enabled
0 = DMA module is disabled
bit 14-13 Unimplemented: Read as ‘0’
bit 12
SUSPEND: DMA Suspend bit(1)
1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus
0 = DMA operates normally
bit 11
DMABUSY: DMA Module Busy bit
1 = DMA module is active and is transferring data
0 = DMA module is disabled and not actively transferring data
bit 10-0
Unimplemented: Read as ‘0’
Note 1:
If the user application clears this bit, it may take a number of cycles before the DMA module completes
the current transaction and responds to this request. The user application should poll the BUSY bit to
verify that the request has been honored.
DS60001570C-page 162
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-2:
Bit
Range
31:24
23:16
15:8
7:0
DMASTAT: DMA STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
RDWR
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
—
—
—
—
—
DMACH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
RDWR: Read/Write Status bit
1 = Last DMA bus access when an error was detected was a read
0 = Last DMA bus access when an error was detected was a write
bit 30-3 Unimplemented: Read as ‘0’
bit 2-0
Note:
DMACH: DMA Channel bits
These bits contain the value of the most recent active DMA channel when an error was detected.
The DMASTAT register will be cleared when its contents are read. If more than one errors at the same time,
the read transaction will be recorded. Additional transfers that occur later with an error will not update this
register until it has been read or cleared.
2019-2020 Microchip Technology Inc.
DS60001570C-page 163
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-3:
Bit
Range
31:24
23:16
15:8
7:0
DMAADDR: DMA ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R-0
R-0
R-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DMAADDR
R-0
R-0
R-0
R-0
R-0
DMAADDR
R-0
R-0
R-0
R-0
R-0
DMAADDR
R-0
R-0
R-0
R-0
R-0
DMAADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DMAADDR: DMA Module Address bits
These bits contain the address of the most recent DMA access when an error was detected.
Note:
The DMAADDR register will be cleared when its contents are read. If more than one errors at the same
time, the read transaction will be recorded. Additional transfers that occur later with an error will not update
this register until it has been read or cleared.
DS60001570C-page 164
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-4:
Bit
Range
31:24
23:16
15:8
7:0
DCRCCON: DMA CRC CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
R/W-0
R/W-0
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
U-0
U-0
R/W-0
WBO(1)
—
—
BITO
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BYTO
PLEN(1,2,3)
R/W-0
R/W-0
R/W-0
U-0
U-0
CRCEN
CRCAPP(1)
CRCTYP
—
—
R/W-0
CRCCH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 BYTO: CRC Byte Order Selection bits
11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order
per half-word)
10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per
half-word)
01 = Endian byte swap on word boundaries (i.e., reverse source byte order)
00 = No swapping (i.e., source byte order)
bit 27
WBO: CRC Write Byte Order Selection bit(1)
1 = Source data is written to the destination re-ordered as defined by BYTO
0 = Source data is written to the destination unaltered
bit 26-25 Unimplemented: Read as ‘0’
bit 24
BITO: CRC Bit Order Selection bit
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected)
0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected)
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected)
0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected)
bit 23-13 Unimplemented: Read as ‘0’
bit 12-8
PLEN: Polynomial Length bits(1,2,3)
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
These bits are unused.
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
Denotes the length of the polynomial – 1.
bit 7
CRCEN: CRC Enable bit
1 = CRC module is enabled and channel transfers are routed through the CRC module
0 = CRC module is disabled and channel transfers proceed normally
Note 1:
2:
3:
When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
The maximum CRC length supported by the DMA module is 32.
This bit is unused when CRCTYP is equal to ‘1’.
2019-2020 Microchip Technology Inc.
DS60001570C-page 165
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-4:
DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED)
bit 6
CRCAPP: CRC Append Mode bit(1)
1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer
completes the DMA writes the calculated CRC value to the location given by CHxDSA
0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the
destination
bit 5
CRCTYP: CRC Type Selection bit
1 = The CRC module will calculate an IP header checksum
0 = The CRC module will calculate a LFSR CRC
bit 4-3
Unimplemented: Read as ‘0’
bit 2-0
CRCCH: CRC Channel Select bits
111 = CRC is assigned to Channel 7
110 = CRC is assigned to Channel 6
101 = CRC is assigned to Channel 5
100 = CRC is assigned to Channel 4
011 = CRC is assigned to Channel 3
010 = CRC is assigned to Channel 2
001 = CRC is assigned to Channel 1
000 = CRC is assigned to Channel 0
Note 1:
2:
3:
When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
The maximum CRC length supported by the DMA module is 32.
This bit is unused when CRCTYP is equal to ‘1’.
DS60001570C-page 166
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-5:
Bit
Range
31:24
23:16
15:8
7:0
DCRCDATA: DMA CRC DATA REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA
R/W-0
R/W-0
DCRCDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DCRCDATA: CRC Data Register bits
Writing to this register will seed the CRC generator. Reading from this register will return the current value of
the CRC. Bits greater than PLEN will return ‘0’ on any read.
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written
to this register is converted and read back in 1’s complement form (i.e., current IP header checksum value).
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
Bits greater than PLEN will return ‘0’ on any read.
2019-2020 Microchip Technology Inc.
DS60001570C-page 167
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-6:
Bit
Range
31:24
23:16
15:8
7:0
DCRCXOR: DMA CRCXOR ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DCRCXOR: CRC XOR Register bits
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
This register is unused.
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
1 = Enable the XOR input to the Shift register
0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in
the register
DS60001570C-page 168
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-7:
Bit
Range
31:24
23:16
15:8
7:0
DCHxCON: DMA CHANNEL ‘x’ CONTROL REGISTER (‘x’ = 0-7)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
CHPIGN
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
CHBUSY
—
CHIPGNEN
—
CHPATLEN
—
—
CHCHNS(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R-0
CHEN(2)
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 CHPIGN: Channel Register Data bits
Pattern Terminate mode:
Any byte matching these bits during a pattern match may be ignored during the pattern match determination when the CHPIGNEN bit is set. If a byte is read that is identical to this data byte, the pattern match
logic will treat it as a “don’t care” when the pattern matching logic is enabled and the CHPIGEN bit is set.
bit 23-16 Unimplemented: Read as ‘0’
bit 15
CHBUSY: Channel Busy bit
1 = Channel is active or has been enabled
0 = Channel is inactive or has been disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
CHPIGNEN: Enable Pattern Ignore Byte bit
1 = Treat any byte that matches the CHPIGN bits as a “don’t care” when pattern matching is enabled
0 = Disable this feature
bit 12
Unimplemented: Read as ‘0’
bit 11
CHPATLEN: Pattern Length bit
1 = 2 byte length
0 = 1 byte length
bit 10-9
Unimplemented: Read as ‘0’
bit 8
CHCHNS: Chain Channel Selection bit(1)
1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
bit 7
CHEN: Channel Enable bit(2)
1 = Channel is enabled
0 = Channel is disabled
bit 6
CHAED: Channel Allow Events If Disabled bit
1 = Channel start/abort events will be registered, even if the channel is disabled
0 = Channel start/abort events will be ignored if the channel is disabled
bit 5
CHCHN: Channel Chain Enable bit
1 = Allow channel to be chained
0 = Do not allow channel to be chained
Note 1:
2:
The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).
When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.
2019-2020 Microchip Technology Inc.
DS60001570C-page 169
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-7:
bit 4
DCHxCON: DMA CHANNEL ‘x’ CONTROL REGISTER (‘x’ = 0-7) (CONTINUED)
CHAEN: Channel Automatic Enable bit
1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete
0 = Channel is disabled on block transfer complete
bit 3
Unimplemented: Read as ‘0’
bit 2
CHEDET: Channel Event Detected bit
1 = An event has been detected
0 = No events have been detected
bit 1-0
CHPRI: Channel Priority bits
11 = Channel has priority 3 (highest)
10 = Channel has priority 2
01 = Channel has priority 1
00 = Channel has priority 0
Note 1:
2:
The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).
When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.
DS60001570C-page 170
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-8:
Bit
Range
31:24
23:16
DCHxECON: DMA CHANNEL x EVENT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
(1)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CHAIRQ
15:8
R/W-1
CHSIRQ(1)
7:0
S-0
S-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
Legend:
R = Readable bit
-n = Value at POR
S = Settable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 CHAIRQ: Channel Transfer Abort IRQ bits(1)
11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag
•
•
•
bit 15-8
00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag
00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag
CHSIRQ: Channel Transfer Start IRQ bits(1)
11111111 = Interrupt 255 will initiate a DMA transfer
•
•
•
00000001 = Interrupt 1 will initiate a DMA transfer
00000000 = Interrupt 0 will initiate a DMA transfer
bit 2-0
The DMA does not support I2C, Change Notification, Input Capture, CTMU, QEI, and Motor
Control PWMs. Use of any of these DMA trigger transfer events could lead to unexpected
behavior.
CFORCE: DMA Forced Transfer bit
1 = A DMA transfer is forced to begin when this bit is written to a ‘1’
0 = This bit always reads ‘0’
CABORT: DMA Abort Transfer bit
1 = A DMA transfer is aborted when this bit is written to a ‘1’
0 = This bit always reads ‘0’
PATEN: Channel Pattern Match Abort Enable bit
1 = Abort transfer and clear CHEN on pattern match
0 = Pattern match is disabled
SIRQEN: Channel Start IRQ Enable bit
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer
AIRQEN: Channel Abort IRQ Enable bit
1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs
0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer
Unimplemented: Read as ‘0’
Note 1:
See Table 6-3: “Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources.
Note:
bit 7
bit 6
bit 5
bit 4
bit 3
2019-2020 Microchip Technology Inc.
DS60001570C-page 171
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-9:
Bit
Range
31:24
23:16
15:8
7:0
DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23
CHSDIE: Channel Source Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 22
CHSHIE: Channel Source Half Empty Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 21
CHDDIE: Channel Destination Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 20
CHDHIE: Channel Destination Half Full Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 19
CHBCIE: Channel Block Transfer Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 18
CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 17
CHTAIE: Channel Transfer Abort Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 16
CHERIE: Channel Address Error Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 15-8
Unimplemented: Read as ‘0’
bit 7
CHSDIF: Channel Source Done Interrupt Flag bit
1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
0 = No interrupt is pending
bit 6
CHSHIF: Channel Source Half Empty Interrupt Flag bit
1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
0 = No interrupt is pending
DS60001570C-page 172
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-9:
DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER (CONTINUED)
bit 5
CHDDIF: Channel Destination Done Interrupt Flag bit
1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
0 = No interrupt is pending
bit 4
CHDHIF: Channel Destination Half Full Interrupt Flag bit
1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
0 = No interrupt is pending
bit 3
CHBCIF: Channel Block Transfer Complete Interrupt Flag bit
1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a
pattern match event occurs
0 = No interrupt is pending
bit 2
CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit
1 = A cell transfer has been completed (CHCSIZ bytes have been transferred)
0 = No interrupt is pending
bit 1
CHTAIF: Channel Transfer Abort Interrupt Flag bit
1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
0 = No interrupt is pending
bit 0
CHERIF: Channel Address Error Interrupt Flag bit
1 = A channel address error has been detected
Either the source or the destination address is invalid.
0 = No interrupt is pending
2019-2020 Microchip Technology Inc.
DS60001570C-page 173
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-10:
Bit Range
DCHxSSA: DMA CHANNEL x SOURCE START ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
R/W-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA
23:16
R/W-0
R/W-0
CHSSA
15:8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA
7:0
R/W-0
CHSSA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
CHSSA Channel Source Start Address bits
Channel source start address.
Note: This must be the physical address of the source.
REGISTER 9-11:
Bit
Range
31:24
23:16
15:8
7:0
DCHxDSA: DMA CHANNEL x DESTINATION START ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 CHDSA: Channel Destination Start Address bits
Channel destination start address.
Note: This must be the physical address of the destination.
DS60001570C-page 174
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-12:
Bit
Range
31:24
23:16
15:8
DCHxSSIZ: DMA CHANNEL x SOURCE SIZE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSIZ
7:0
R/W-0
CHSSIZ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CHSSIZ: Channel Source Size bits
1111111111111111 = 65,535 byte source size
•
•
•
0000000000000010 = 2 byte source size
0000000000000001 = 1 byte source size
0000000000000000 = 65,536 byte source size
2019-2020 Microchip Technology Inc.
DS60001570C-page 175
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-13:
Bit
Range
31:24
23:16
15:8
DCHxDSIZ: DMA CHANNEL x DESTINATION SIZE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSIZ
7:0
R/W-0
CHDSIZ
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHDSIZ: Channel Destination Size bits
1111111111111111 = 65,535 byte destination size
•
•
•
0000000000000010 = 2 byte destination size
0000000000000001 = 1 byte destination size
0000000000000000 = 65,536 byte destination size
DS60001570C-page 176
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-14:
Bit
Range
31:24
23:16
15:8
DCHxSPTR: DMA CHANNEL x SOURCE POINTER REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHSPTR
7:0
R-0
R-0
CHSPTR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CHSPTR: Channel Source Pointer bits
1111111111111111 = Points to byte 65,535 of the source
•
•
•
0000000000000001 = Points to byte 1 of the source
0000000000000000 = Points to byte 0 of the source
Note:
When in Pattern Detect mode, this register is reset on a pattern detect.
2019-2020 Microchip Technology Inc.
DS60001570C-page 177
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-15:
Bit
Range
31:24
23:16
15:8
DCHxDPTR: DMA CHANNEL x DESTINATION POINTER REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHDPTR
7:0
R-0
R-0
CHDPTR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHDPTR: Channel Destination Pointer bits
1111111111111111 = Points to byte 65,535 of the destination
•
•
•
0000000000000001 = Points to byte 1 of the destination
0000000000000000 = Points to byte 0 of the destination
DS60001570C-page 178
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-16:
Bit
Range
31:24
23:16
15:8
DCHxCSIZ: DMA CHANNEL x CELL-SIZE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHCSIZ
7:0
R/W-0
CHCSIZ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CHCSIZ: Channel Cell-Size bits
1111111111111111 = 65,535 bytes transferred on an event
•
•
•
0000000000000010 = 2 bytes transferred on an event
0000000000000001= 1 byte transferred on an event
0000000000000000 = 65,536 bytes transferred on an event
2019-2020 Microchip Technology Inc.
DS60001570C-page 179
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-17:
Bit
Range
31:24
23:16
15:8
DCHxCPTR: DMA CHANNEL x CELL POINTER REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHCPTR
7:0
R-0
R-0
CHCPTR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCPTR: Channel Cell Progress Pointer bits
1111111111111111 = 65,535 bytes have been transferred since the last event
•
•
•
0000000000000001 = 1 byte has been transferred since the last event
0000000000000000 = 0 bytes have been transferred since the last event
Note:
When in Pattern Detect mode, this register is reset on a pattern detect.
DS60001570C-page 180
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 9-18:
Bit
Range
31:24
23:16
15:8
7:0
DCHxDAT: DMA CHANNEL x PATTERN DATA REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHPDAT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHPDAT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CHPDAT: Channel Data Register bits
Pattern Terminate mode:
Data to be matched must be stored in this register to allow terminate on match.
All other modes:
Unused.
2019-2020 Microchip Technology Inc.
DS60001570C-page 181
PIC32MK GPG/MCJ with CAN FD Family
10.0
I/O PORTS
Note:
are multiplexed with alternate function(s). These functions depend on which peripheral features are on the
device. In general, when a peripheral is functioning,
that pin may not be used as a general purpose I/O pin.
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS60001120), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The following are key features of the I/O ports:
• Individual output pin open-drain enable/disable
• Individual input pin weak pull-up and pull-down
• Monitor selective inputs and generate interrupt
when change in pin state is detected
• Operation during Sleep and Idle modes
• Fast bit manipulation using CLR, SET, and INV
registers
Figure 10-1 illustrates a block diagram of a typical
multiplexed I/O port.
General purpose I/O pins are the simplest of
peripherals. They allow the PIC32MK GPG/MCJ with
CAN FD Family of devices to monitor and control other
devices. To add flexibility and functionality, some pins
FIGURE 10-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Peripheral Module
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
Port Control
PIO Module
RD ODC
PBCLK4
Data Bus
PBCLK4
D
Q
ODC
CK
EN Q
WR ODC
1
RD TRIS
0
0
I/O Cell
1
D
Q
1
TRIS
CK
EN Q
WR TRIS
Output Multiplexers
D
WR LAT
WR PORT
0
Q
I/O Pin
LAT
CK
EN Q
RD LAT
1
RD PORT
0
Sleep
Q
Q
D
CK
Q
Q
D
CK
PBCLK4
Synchronization
R
Peripheral Input
Peripheral Input Buffer
Legend:
Note:
R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure
for any specific port/peripheral combination may be different than it is shown here.
DS60001570C-page 182
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
10.1
Parallel I/O (PIO) Ports
All port pins have ten registers directly associated with
their operation as digital I/O. The data direction register
(TRISx) determines whether the pin is an input or an
output. If the data direction bit is a ‘1’, then the pin is an
input. All port pins are defined as inputs after a Reset.
Reads from the latch (LATx) read the latch. Writes to
the latch write the latch. Reads from the port (PORTx)
read the port pins, while writes to the port pins write the
latch.
10.1.1
OPEN-DRAIN CONFIGURATION
In addition to the PORTx, LATx, and TRISx registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of outputs
higher than VDD (e.g., 5V) on any desired 5V-tolerant
pins by using external pull-up resistors. The maximum
open-drain voltage allowed is the same as the
maximum VIH specification.
Refer to the pin name tables (Table 2 and Table 4) for
the available pins and their functionality.
10.1.2
CONFIGURING ANALOG AND
DIGITAL PORT PINS
The ANSELx register controls the operation of the
analog port pins. The port pins that are to function as
analog inputs must have their corresponding ANSEL
and TRIS bits set. In order to use port pins for I/O
functionality with digital modules, such as Timers,
UARTs, etc., the corresponding ANSELx bit must be
cleared.
The ANSELx register has a default value of 0xFFFF;
therefore, all pins that share analog functions are
analog (not digital) by default.
If the TRIS bit is cleared (output) while the ANSELx bit
is set, the digital output level (VOH or VOL) is converted
by an analog peripheral, such as the ADC module or
Comparator module.
When the PORT register is read, all pins configured as
analog input channels are read as cleared (a low level).
Pins configured as digital inputs do not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
2019-2020 Microchip Technology Inc.
10.1.3
I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be an NOP.
10.1.4
INPUT CHANGE NOTIFICATION
The input change notification function of the I/O ports
allows the PIC32MK GPG/MCJ with CAN FD Family
devices to generate interrupt requests to the processor
in response to a change-of-state on selected input pins.
This feature can detect input change-of-states even in
Sleep mode, when the clocks are disabled. Every I/O
port pin can be selected (enabled) for generating an
interrupt request on a change-of-state.
Five control registers are associated with the CN functionality of each I/O port. The CNENx and CNNEx registers contain the CN interrupt enable control bits for
each of the input pins. Setting these bits enables a CN
interrupt for the corresponding pins. The CNENx register enables a mismatch CN interrupt condition when
the EDGEDETECT bit (CNCONx) is not set.
When the EDGEDETECT bit is set, the CNNEx register
controls the negative edge while the CNENx register
controls the positive edge.
The CNSTATx and CNFx registers indicate the status
of change notice based on the setting of the
EDGEDETECT bit. If the EDGEDETECT bit is set to
‘0’, the CNSTATx register indicates whether a change
occurred on the corresponding pin since the last read
of the PORTx bit. If the EDGEDETECT bit is set to ‘1’,
the CNFx register indicates whether a change has
occurred and through the CNNEx and CNENx registers
the edge type of the change that occurred is also
indicated.
Each I/O pin also has a weak pull-up and a weak
pull-down connected to it. The pull-ups act as a
current source or sink source connected to the pin,
and eliminate the need for external resistors when
push-button or keypad devices are connected. The
pull-ups and pull-downs are enabled separately using
the CNPUx and the CNPDx registers, which contain
the control bits for each of the pins. Setting any of
the control bits enables the weak pull-ups and/or
pull-downs for the corresponding pins.
Note:
Pull-ups and pull-downs on change
notification pins should always be
disabled when the port pin is configured as
a digital output.
An additional control register (CNCONx) is shown in
Register 10-3.
DS60001570C-page 183
PIC32MK GPG/MCJ with CAN FD Family
10.2
CLR, SET, and INV Registers
Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
10.3
Peripheral Pin Select (PPS)
In comparison, some digital-only peripheral modules
are never included in the PPS feature. This is because
the peripheral’s function requires special I/O circuitry
on a specific port and cannot be easily connected to
multiple pins. A similar requirement excludes all
modules with analog inputs, such as the Analog-toDigital Converter (ADC).
A key difference between remappable and non-remappable peripherals is that remappable peripherals are
not associated with a default I/O pin. The peripheral
must always be assigned to a specific I/O pin before it
can be used. In contrast, non-remappable peripherals
are always available on a default pin, assuming that the
peripheral is active and not conflicting with another
peripheral.
A major challenge in general purpose devices is providing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. The challenge is even greater on low pin-count devices. In an
application where more than one peripheral needs to
be assigned to a single pin, inconvenient workarounds
in application code or a complete redesign may be the
only option.
When a remappable peripheral is active on a given I/O
pin, it takes priority over all other digital I/O and digital
communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
is mapped. Remappable peripherals never take priority
over any analog functions associated with the pin.
PPS configuration provides an alternative to these
choices by enabling peripheral set selection and their
placement on a wide range of I/O pins. By increasing
the pinout options available on a particular device,
users can better tailor the device to their entire
application, rather than trimming the application to fit
the device.
PPS features are controlled through two sets of SFRs:
one to map peripheral inputs, and one to map outputs.
Because they are separately controlled, a particular
peripheral’s input and output (if the peripheral has both)
can be placed on any selectable function pin without
constraint.
The PPS configuration feature operates over a fixed
subset of digital I/O pins. Users may independently
map the input and/or output of most digital peripherals
to these I/O pins. PPS is performed in software and
generally does not require the device to be
reprogrammed. Hardware safeguards are included that
prevent accidental or spurious changes to the peripheral mapping once it has been established.
10.3.3
CONTROLLING PPS
The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on
whether an input or output is being mapped.
10.3.4
INPUT MAPPING
The number of available pins is dependent on the
particular device and its pin count. Pins that support the
PPS feature include the designation “RPn” in their full
pin designation, where “RP” designates a remappable
peripheral and “n” is the remappable port number.
The inputs of the PPS options are mapped on the basis
of the peripheral. That is, a control register associated
with a peripheral dictates the pin it will be mapped to.
The [pin name]R registers, where [pin name] refers to the
peripheral pins listed in Table 10-1, are used to configure peripheral input mapping (see Register 10-1). Each
register contains sets of 4 bit fields. Programming these
bit fields with an appropriate value maps the RPn pin
with the corresponding value to that peripheral. For any
given device, the valid range of values for any bit field is
shown in Table 10-1.
10.3.2
Figure 10-2 illustrates the remappable pin selection for
the U1RX input.
10.3.1
AVAILABLE PINS
AVAILABLE PERIPHERALS
The peripherals managed by the PPS are all digitalonly peripherals. These include general serial
communications (UART, SPI, and CAN), general purpose timer clock inputs, timer-related peripherals (input
capture and output compare), interrupt-on-change
inputs, and reference clocks (input and output).
DS60001570C-page 184
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 10-2:
REMAPPABLE INPUT
EXAMPLE FOR U1RX
U1RXR
0
RPD2
1
RPG8
2
RPF4
U1RX input
to peripheral
n
RPn
Note:
For input only, PPS functionality does not
have priority over TRISx settings. Therefore,
when configuring RPn pin for input, the
corresponding bit in the TRISx register must
also be configured for input (set to ‘1’).
2019-2020 Microchip Technology Inc.
DS60001570C-page 185
PIC32MK GPG/MCJ with CAN FD Family
TABLE 10-1:
INPUT PIN SELECTION
Peripheral Pin
[pin name]R SFR
[pin name]R bits
INT4
INT4R
INT4R
T2CK
T2CKR
T2CKR
T6CK
T6CKR
T6CKR
IC4
IC4R
IC4R
IC7
IC7R
IC7R
SDI1
SDI1R
QEA1(3)
SDI1R
QEA1R (3)
1000 = RPA11 (2)
1001 = RPD5 (1)
HOME2R (3)
HOME2R (3)
QAEA3(3)
QAEA3R (3)
QEA3R (3)
FLT1R
(3)
0000 = RPA0
0001 = RPB3
0010 = RPB4
0011 = RPB15
0100 = RPB7
0101 = RPC7 (2)
0110 = RPC0
0111 = Reserved
HOME2(3)
FLT1(3)
Note 1:
2:
3:
4:
QEA1R
(3)
[pin name]R Value to
RPn Pin Selection
FLT1R
(3)
REFCLKI
REFIR
REFIR
FLT2(3)
FLT2R (3)
FLT2R (3)
CLCINC
CLCINCR
CLCINCR
1010 = RPG6 (1)
1011 = RPF1 (1)
1100 = RPE0 (1)
1101 = RPA15 (1)
1110 = Reserved
1111 = Reserved
64-Pin devices only.
Register is write only.
Only available on “MCJ” variant.
Not available on “GPG” variant.
DS60001570C-page 186
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 10-1:
INPUT PIN SELECTION (CONTINUED)
Peripheral Pin
[pin name]R SFR
[pin name]R bits
INT3
INT3R
INT3R
T3CK
T3CKR
T3CKR
T7CK
T7CKR
T7CKR
IC3
IC3R
IC3R
IC8
IC8R
IC8R
U1CTS
U1CTSR
U1CTSR
U2RX
U2RXR
U2RXR
Note 1:
2:
3:
4:
SDI2
SDI2R
SDI2R
QEB1(3)
QEB1R (3)
QEB1R (3)
INDX2(3)
INDX2R (3)
INDX2R (3)
QEB3(3)
QEB3R (3)
QEB3R (3)
FLT2(3)
FLT2R
(3)
FLT2R (3)
CLCINA
CLCINAR
CLCINAR
[pin name]R Value to
RPn Pin Selection
0000 = RPA1
0001 = RPB5
0010 = RPB1
0011 = RPB11
0100 = RPB8
0101 = RPA8
0110 = RPC8 (2)
0111 = RPB12
1000 = RPA12 (2)
1001 = RPD6 (1)
1010 = RPG7 (1)
1011 = Reserved
1100 = RPE1(1)
1101 = RPA14(1)
1110 = Reserved
1111 = Reserved
64-Pin devices only.
Register is write only.
Only available on “MCJ” variant.
Not available on “GPG” variant.
2019-2020 Microchip Technology Inc.
DS60001570C-page 187
PIC32MK GPG/MCJ with CAN FD Family
TABLE 10-1:
INPUT PIN SELECTION (CONTINUED)
Peripheral Pin
[pin name]R bits
[pin name]R Value to
RPn Pin Selection
INT2
INT2R
INT2R
0000 = RPB6
T4CK
T4CKR
T4CKR
0001 = RPC15
T8CK
T8CKR
T8CKR
0010 = RPA4
IC1
IC1R
IC1R
0011 = RPB13
IC5
IC5R
IC5R
0100 = RPB2
IC9
IC9R
IC9R
0101 = RPC6(2)
U1RX
U1RXR
U1RXR
0110 = RPC1
U2CTS
U2CTSR
U2CTSR
0111 = RPA7
SS1
SS1R
SS1R
SCK2
Note 1:
2:
3:
4:
[pin name]R SFR
SCK2R[3:0]
1000 = RPE14 (1)
SCK2R
INDX1
(3)
INDX1R
(3)
QEB2
(3)
QEB2R
(3)
INDX3
(3)
INDX3R
(3)
C1RX
(4)
C1RXR (4)
1001 = RPC13
INDX1R
(3)
1010 = RPG8 (1)
QEB2R
(3)
1011 = Reserved
INDX3R
(3)
1100 = RPF0 (1)
C1RXR
(4)
1101 = Reserved
OCFB
OCFBR
OCFBR
1110 = Reserved
CLCIND
CLCINDR
CLCINDR
1111 = Reserved
64-Pin devices only.
Register is write only.
Only available on “MCJ” variant.
Not available on “GPG” variant.
DS60001570C-page 188
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 10-1:
INPUT PIN SELECTION (CONTINUED)
Peripheral Pin
[pin name]R SFR
[pin name]R bits
INT1
INT1R
INT1R
T5CK
T5CKR
T5CKR
T9CK
T9CKR
T9CKR
IC2
IC2R
IC2R
IC6
IC6R
IC6R
SS2
SS2R(2)
SS2R
HOME1 (3)
HOME1R (3)
HOME1R (3)
QEA2 (3)
QEA2R (3)
QEA2R (3)
HOME3 (3)
HOME3R (3)
HOME3R (3)
OCFA
OCFAR
OCFAR
CLCINB
CLCINBR
CLCINBR
Note 1:
2:
3:
4:
[pin name]R Value to
RPn Pin Selection
0000 = RPB14
0001 = RPC12
0010 = RPB0
0011 = RPB10
0100 = RPB9
0101 = RPC9 (2)
0110 = RPC2 (2)
0111 = Reserved
1000 = RPE15 (1)
1001 = RPC10
1010 = RPG9 (1)
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
64-Pin devices only.
Register is write only.
Only available on “MCJ” variant.
Not available on “GPG” variant.
2019-2020 Microchip Technology Inc.
DS60001570C-page 189
PIC32MK GPG/MCJ with CAN FD Family
10.3.5
OUTPUT MAPPING
10.3.6.1
In contrast to inputs, the outputs of the PPS options
are mapped on the basis of the pin. In this case, a
control register associated with a particular pin
dictates the peripheral output to be mapped. The
RPnR registers (Register 10-2) are used to control
output mapping. Like the [pin name]R registers, each
register contains sets of 4 bit fields. The value of the
bit field corresponds to one of the peripherals, and
that peripheral’s output is mapped to the pin (see
Table 10-2 and Figure 10-3).
A null output is associated with the output register reset
value of ‘0’. This is done to ensure that remappable
outputs remain disconnected from all output pins by
default.
FIGURE 10-3:
EXAMPLE OF
MULTIPLEXING OF
REMAPPABLE OUTPUT
FOR RPF0
RPF0R
Default
U1TX Output
U2RTS Output
0
1
2
RPF0
Output Data
Control Register Lock
Under normal operation, writes to the RPnR and [pin
name]R registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these
registers, they must be unlocked in hardware. The
register lock is controlled by the IOLOCK
Configuration bit (CFGCON). Setting the
IOLOCK bit prevents writes to the control registers
and clearing the IOLOCK bit allows writes.
To set or clear the IOLOCK bit, an unlock sequence
must be executed. Refer to the Section 42. “Oscillators with Enhanced PLL” (DS60001250) in the
“PIC32 Family Reference Manual” for details.
10.3.6.2
Configuration Bit Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPnR and [pin name]R registers. The IOL1WAY
Configuration bit (DEVCFG3) blocks the IOLOCK
bit from being cleared after it has been set once. If the
IOLOCK bit remains set, the register unlock procedure
does not execute, and the PPS control registers cannot
be written to. The only way to clear the bit and reenable peripheral remapping is to perform a device
Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session.
14
REFCLKO1
10.3.6
15
CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. The PIC32MK GPG/MCJ with CAN FD Family devices include two features to prevent alterations to
the peripheral map:
• Control register lock sequence
• Configuration bit select lock
DS60001570C-page 190
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 10-2:
OUTPUT PIN SELECTION
RPn Port Pin
RPnR SFR
RPnR bits
RPA0
RPA0R
RPA0R
RPB3
RPB3R
RPB3R
RPB4
RPB4R
RPB4R
RPB15
RPB15R
RPB15R
RPB7
RPB7R
RPB7R
RPC7
RPC7R
RPC7R
RPC0
RPC0R
RPC0R
RPA11
RPA11R
RPA11R
RPD5 (1)
RPD5R
RPD5R
RPG6 (1)
RPG6R
RPG6R
RPF1 (1)
RPF1R
RPF1R
RPE0 (1)
RPE0R
RPE0R
RPA15 (1)
RPA15R
RPA15R
Note 1:
2:
3:
4:
5:
RPnR Value to Peripheral
Selection
00000 = Off
00001 = U1TX
00010 = U2RTS
00011 = SDO1
00100 = SDO2
00101 = OCI
00110 = OC7
00111 = C2OUT
01000 = C4OUT
01001 = Reserved
01010 = Reserved
01011 = Reserved
01100 = C1TX (4)
01101 = Reserved
01110 = Reserved
•••
10001 = Reserved
10010 = REFCLKO4
10011 = Reserved
10100 = QEICMP1 (3)
10101 = Reserved
10110 = Reserved
10111 = Reserved
11000 = CLCO2
•••
11111 = Reserved
64 pin devices only.
Register is write only.
Only available on “MCJ” variant.
Not available on “GPG” variant.
SPI Frame Sync Output in Frame Master mode
2019-2020 Microchip Technology Inc.
DS60001570C-page 191
PIC32MK GPG/MCJ with CAN FD Family
TABLE 10-2:
OUTPUT PIN SELECTION (CONTINUED)
RPn Port Pin
RPnR SFR
RPnR bits
RPA1
RPA1R
RPA1R
RPB5
RPB5R
RPB5R
RPB1
RPB1R
RPB1R
RPB11
RPB11R
RPB11R
RPA8
RPA8R
RPA8R
RPC8
RPC8R
RPC8R
RPB12
RPB12R
RPB12R
RPA12
RPA12R
RPA12R
RPD6 (1)
RPD6R
RPD6R
RPG7 (1)
RPG7R
RPG7R
RPE1 (1)
RPE1R
RPE1R
RPA14 (1)
RPA14R
RPA14R
Note 1:
2:
3:
4:
5:
RPnR Value to Peripheral
Selection
00000 = Off
00001 = Reserved
00010 = Reserved
00011 = SDO1
00100 = SDO2
00101 = OC2
00110 = OC8
00111 = C3OUT
01000 = OC9
01001 = Reserved
***
10001 = Reserved
10010 = REFOUT3
10011 = Reserved
10100 = QEICMP2 (3)
10101 = Reserved
10110 = Reserved
10111 = Reserved
11000 = CLCO1
11001 = Reserved
***
11111 = Reserved
64 pin devices only.
Register is write only.
Only available on “MCJ” variant.
Not available on “GPG” variant.
SPI Frame Sync Output in Frame Master mode
DS60001570C-page 192
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 10-2:
OUTPUT PIN SELECTION (CONTINUED)
RPn Port Pin
RPnR SFR
RPnR bits
RPB6
RPB6R
RPB6R
RPC15
RPC15R
RPC15R
RPA4
RPA4R
RPA4R
RPB13
RPB13R
RPB13R
RPB2
RPB2R
RPB2R
RPC6
RPC6R
RPC6R
RPC1
RPC1R
RPC1R
RPA7
RPA7R
RPA7R
RPE14 (1)
RPE14R
RPE14R
RPG8 (1)
RPG8R
RPG8R
RPF0 (1)
RPF0R
RPF0R
Note 1:
2:
3:
4:
5:
RPnR Value to Peripheral
Selection
00000 = Off
00001 = Reserved
00010 = Reserved
00011 = SS1 (5)
00100 = SCK2
00101 = OC4
00110 = OC5
00111 = REFOUT1
01000 = C5OUT
01001 = Reserved
***
10001 = Reserved
10010 = REFOUT2
10011 = Reserved
10100 = QEICMP3 (3)
10101 = Reserved
10110 = Reserved
10111 = Reserved
11000 = CLCO4
11001 = Reserved
***
11111 = Reserved
64 pin devices only.
Register is write only.
Only available on “MCJ” variant.
Not available on “GPG” variant.
SPI Frame Sync Output in Frame Master mode
2019-2020 Microchip Technology Inc.
DS60001570C-page 193
PIC32MK GPG/MCJ with CAN FD Family
TABLE 10-2:
OUTPUT PIN SELECTION (CONTINUED)
RPnR Value to Peripheral
Selection
RPn Port Pin
RPnR SFR
RPnR bits
RPB14
RPB14R
RPB14R
RPC12
RPC12R
RPC12R
RPB0
RPB0R
RPB0R
RPB10
RPB10R
RPB10R
00101 = OC3
RPB9
RPB9R
RPB9R
00111 = C1OUT
RPC9
RPC9R
RPC9R
RPC2
RPC2R
RPC2R
RPE15 (1)
RPE15R
RPE15R
RPC10
RPC10R
RPC10R
00000 = Off
00001 = U1RTS
00010 = U2TX
00011 = Reserved
00100 = SS2 (5)
00110 = OC6
01000 = Reserved
01001 = Reserved
***
10111 = Reserved
11000 = CLCO3
11001 = Reserved
***
11110 = Reserved
RPG9
Note 1:
2:
3:
4:
5:
(1)
RPG9R
RPG9R
11111 = Reserved
64 pin devices only.
Register is write only.
Only available on “MCJ” variant.
Not available on “GPG” variant.
SPI Frame Sync Output in Frame Master mode
DS60001570C-page 194
2019-2020 Microchip Technology Inc.
I/O Ports Control Registers
Virtual Address
(BF86_#)
Register
Name(1)
TABLE 10-3:
0000
ANSELA
PORTA REGISTER MAP
31:16
15:0
31:16
0010
0020
0030
TRISA
PORTA
LATA
15:0
ODCA
0060
CNPUA
CNPDA
0070 CNCONA
2019-2020 Microchip Technology Inc.
0080
CNENA
0090 CNSTATA
CNNEA
Legend:
Note 1:
2:
3:
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
ANSA10
ANSA9
—
—
ANSA26
—
—
—
ANSA24
—
—
ANSA1
ANSA0
D913
—
—
—
—
ANSA47
ANSA46
(1)
—
—
—
—
(1)
TRISA15 TRISA14
(1)
(1)
—
TRISA12 TRISA11
—
—
—
—
—
—
—
—
—
—
—
0000
TRISA10
—
TRISA8
TRISA7
—
—
TRISA4
—
—
TRISA1
TRISA0
DD93
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
RA15 (1)
RA14 (1)
—
RA12
RA11
RA10
—
RA8
RA7
—
—
RA4
—
—
RA1
RA0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
LATA15
LATA14
(1)
—
LATA12
LATA11
LATA10
—
LATA8
LATA7
—
—
LATA4
—
—
LATA1
LATA0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
ODCA10
—
ODCA8
ODCA7
—
—
ODCA4
—
—
ODCA1
ODCA0
0000
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
CNPUA4
—
—
—
—
—
—
—
—
—
CNPDA4
—
—
15:0
15:0
15:0
(1)
ODCA15 ODCA14
(1)
(1)
—
—
—
—
CNPUA15 CNPUA14
(1)
(1)
—
ODCA12 ODCA11
—
—
CNPUA12 CNPUA11 CNPUA10
—
—
15:0
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
SIDL
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
CNENA4
—
—
—
—
15:0
CNENA14 (1)
—
CNPDA12 CNPDA11 CNPDA10
CNENA12 CNENA11 CNENA10
—
—
—
—
—
CNPDA8 CNPDA7
CNENA8 CNENA7
—
CNPDA1 CNPDA0
CNENA1 CNENA0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CNSTATA15 (1)
CNSTATA14 (1)
—
CNSTATA12
CNSTATA11
CNSTATA10
—
CNSTATA8
CNSTATA7
—
—
CNSTATA4
—
—
CNSTATA1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNNEA12
CN
NEA11
—
—
—
—
15:0
CNNEA15 CNNEA14
(1)
(1)
—
CNNEA10
—
CNNEA8 CNNEA7
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Does not exist on 48-pin variants.
Not available on “GPG” variants.
Only available on “MC” variants.
CNNEA4
—
0000
CNPDA14 (1)
—
—
CNPUA1 CNPUA0
—
CNENA15 (1)
—
CNPUA8 CNPUA7
CNPDA15 (1)
31:16
—
—
31:16
31:16
00A0
29/13
15:0
31:16
0050
30/14
31:16
31:16
0040
31/15
All
Resets
Bit Range
Bits
—
0000
0000
0000
0000
CNSTA0000
TA0
—
0000
CNNEA1 CNNEA0 0000
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 195
10.4
Virtual Address
(BF86_#)
Register
Name(1)
CNFA
30/14
29/13
—
—
—
CNFA15
CNFA14
—
00C0 SRCON0A 31:16
—
—
15:0
—
—
31:16
—
—
00D0 SRCON1A
Legend:
Note 1:
2:
3:
15:0
(1)
(1)
28/12
27/11
26/10
25/9
—
24/8
23/7
22/6
21/5
—
—
—
—
CNFA8
CNFA7
—
—
20/4
19/3
18/2
—
—
—
—
—
—
—
—
CNFA12
CNFA11
CNFA10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SR0A10
—
SR0A8
SR0A7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
SR1A10
—
SR1A8
SR1A7
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Does not exist on 48-pin variants.
Not available on “GPG” variants.
Only available on “MC” variants.
CNFA4
17/1
16/0
All
Resets
Bit Range
31:16
31/15
—
—
0000
CNFA1
CNFA0
0000
—
—
—
0000
—
SR0A1
—
0000
—
—
—
—
0000
—
—
SR1A1
—
0000
DS60001570C-page 196
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
00B0
Bits
0110
0120
0130
0140
TRISB
PORTB
LATB
ODCB
0150
CNPUB
0160
CNPDB
0170 CNCONB
0180
CNENB
0190 CNSTATB
2019-2020 Microchip Technology Inc.
01A0
CNNEB
01B0
CNFB
01C0 SRCON0B
01D0 SRCON1B
Legend:
Note 1:
2:
3:
Bits
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
—
—
—
—
15:0
—
—
—
—
—
31:16
—
—
—
—
—
15:0
TRISB15 TRISB14 TRISB13 TRISB12 TRISB11
25/9
24/8
—
—
—
ANSA27
—
19/3
16/0
All
Resets
Register
Name(1)
ANSELB
Bit Range
Virtual Address
(BF86_#)
0100
PORTB REGISTER MAP
—
—
0000
ANSA3
ANSA2
028F
—
—
0000
TRISB2
TRISB1
TRISB0
FFFF
23/7
22/6
21/5
20/4
18/2
—
—
—
—
—
—
—
—
ANSA25
—
—
—
ANSA5
ANSA4
—
—
—
—
—
—
—
—
TRISB10
TRISB9
—
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
17/1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATB15
LATB14
LATB13
LATB12
LATB11
LATB10
LATB9
—
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
ODCB10
ODCB9
—
ODCB7
ODCB6
ODCB5
ODCB4
ODCB3
ODCB2
ODCB1
ODCB0
0000
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
31:16
ODCB15 ODCB14 ODCB13 ODCB12 ODCB11
—
—
—
—
—
15:0 CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9
—
31:16
—
—
—
—
—
—
—
—
15:0 CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9
—
31:16
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
0000
—
31:16
—
—
—
—
—
15:0 CNENB15 CNENB14 CNENB13 CNENB12 CNENB11 CNENB10 CNENB9
—
31:16
—
—
—
—
—
CNSTATB CNSTATB CNSTATB CNSTATB CNSTATB CNSTATB CNSTATB
15:0
15
14
13
12
11
10
9
—
31:16
—
—
—
—
SIDL
—
—
—
—
—
—
—
ON
—
—
—
15:0
—
—
CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000
—
EDGE
DETECT
—
CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000
—
—
—
—
CNENB7 CNENB6 CNENB5 CNENB4 CNENB3 CNENB2 CNENB1 CNENB0 0000
—
—
—
—
—
—
—
—
0000
CNSTATB CNSTATB CNSTATB CNSTATB CNSTATB CNSTATB CNSTATB CNSTATB 0000
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
0000
15:0 CNNEB15 CNNEB14 CNNEB13 CNNEB12 CNNEB11 CNNEB10 CNNEB9
—
CNNEB7 CNNEB6 CNNEB5 CNNEB4 CNNEB3 CNNEB2 CNNEB1 CNNEB0 0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNFB15
CNFB14
CNFB13
CNFB12
CNFB11
CNFB10
CNFB9
—
CNFB7
CNFB6
CNFB5
CNFB4
CNFB3
CNFB2
CNFB1
CNFB0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
SR0B15
SR0B14
SR0B13
SR0B12
SR0B11
SR0B10
—
—
SR0B7
SR0B6
SR0B5
SR0B4
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
SR1B15
SR1B14
SR1B13
SR1B12
SR1B11
SR1B10
—
—
SR1B7
SR1B6
SR1B5
SR1B4
—
—
—
—
0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Does not exist on 48 pin variants.
Not available on “GPG” variants.
Only available on “MC” variants.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 197
TABLE 10-4:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSA8
ANSA7
ANSA6
—
—
—
—
—
—
—
—
—
TRISC2
TRISC1
TRISC0
—
—
—
—
—
—
—
—
—
RC2
RC1
RC0
—
—
—
—
—
—
—
—
—
LATC2
LATC1
LATC0
—
—
—
—
—
—
—
—
—
ODCC2
ODCC1
ODCC0
—
—
—
—
—
—
—
—
—
CNPUC2
CNPUC1
CNPUC0
All
Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF86_#)
PORTC REGISTER MAP
0200 ANSELC
31:16
15:0
—
—
—
—
—
—
—
—
—
ANSA49
ANSA11
ANSA48
0210
TRISC
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
TRISC15
TRISC12
TRISC11
TRISC10
TRISC9
TRISC8
TRISC7
TRISC6
0220
PORTC
31:16
15:0
—
—
—
—
—
—
—
—
—
—
RC15
RC13
RC12
RC11
RC10
RC9
RC8
RC7
RC6
0230
LATC
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
LATC15
LATC12
LATC11
LATC10
LATC9
LATC8
LATC7
LATC6
0240
ODCC
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
ODCC15
ODCC12
ODCC11
ODCC10
ODCC9
ODCC8
ODCC7
ODCC6
0250 CNPUC
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
CNPUC15
CNPUC12
CNPUC11
CNPUC10
CNPUC9
CNPUC8
CNPUC7
CNPUC6
0260 CNPDC
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
CNPDC10
CNPDC9
CNPDC8
CNPDC7
CNPDC6
—
—
—
CNPDC11
—
—
—
CNPDC12
—
—
—
CNPDC15
CNPDC2
CNPDC1
CNPDC0
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
SIDL
—
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNENC15
—
—
CNENC12
CNENC11
CNENC10
CNENC9
CNENC8
CNENC7
CNENC6
—
—
—
CNENC2
CNENC1
CNENC0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNSTATC15
—
—
CNSTATC12
CNSTATC11
CNSTATC10
CNSTATC9
CNSTATC8
CNSTATC7
CNSTATC6
—
—
—
CNSTATC2
CNSTATC1
CNSTATC0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNNEC15
—
—
CNNEC12
CNNEC11
CNNEC10
CNNEC9
CNNEC8
CNNEC7
CNNEC6
—
—
—
CNNEC2
CNNEC1
CNNEC0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNFC15
—
—
CNFC12
CNFC11
CNFC10
CNFC9
CNFC8
CNFC7
CNFC6
—
—
—
CNFC2
CN—FC1
CNFC0
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
SR0C15
—
—
—
SR0C11
—
SR0C9
SR0C8
SR0C7
SR0C6
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
SR1C7
SR1C6
—
—
—
—
—
—
0000
0270 CNCONC
0280 CNENC
0290 CNSTATC
02A0 CNNEC
02B0
CNFC
2019-2020 Microchip Technology Inc.
SRCON0 31:16
02C0
C
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
SRCON1 31:16
02D0
C
15:0
SR1C15
—
—
—
—
SR1C11
SR1C9
SR1C8
Legend:
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Note 1:
Does not exist on 48 pin variants.
2:
Not available on “GPG” variants.
3:
Only Available on “MC” variants.
0000
1C07
0000
BFC7
0000
xxxx
0000
xxxx
0000
0000
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 198
TABLE 10-5:
TRISD
0320
PORTD
0330
LATD
ODCD
0350
CNPUD
0360
CNPDD
0370 CNCOND
0380
CNEND
0390 CNSTATD
03A0
DS60001570C-page 199
03B0
CNNED
CNFD
03C0 SRCON0D
Legend:
Note 1:
2:
3:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
0310
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
0300 ANSELD
0340
PORTD REGISTER MAP
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0160
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RD8
—
—
—
RD6 (1)
—
RD5 (1)
—
—
—
—
—
—
—
—
—
—
—
xxxx
0000
15:0
—
—
—
—
—
—
—
LATD8
—
LATD6 (1)
LATD5
(1)
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
ODCD8
—
—
ODCD5
—
15:0
—
ODCD6
(1)
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
CNPUD8
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
(1)
CNPUD6 CNPUD5
(1)
(1)
—
—
—
—
—
—
—
—
0000
CNPDD6 CNPDD5
15:0
—
—
—
—
—
—
—
CNPDD8
—
(1)
(1)
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
SIDL
—
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
CNEND6 CNEND5
CNEND8
—
(1)
(1)
—
—
—
—
—
0000
—
—
—
—
CNSTAT
D8
—
—
—
—
—
—
—
—
—
—
CNNED8
—
(1)
(1)
—
—
—
—
—
—
—
—
—
—
—
0000
CNSTAT CNSTAT
D6 (1)
D5 (1)
—
—
—
—
—
0000
—
—
CNNED6 CNNED5
—
—
—
—
—
—
—
0000
—
—
—
0000
—
—
—
—
—
—
0000
CNFD5
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
CNFD8
—
CNFD6 (1)
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
SR0D6 (1)
SR0D5 (1
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
SR0D8
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Does not exist on 48 pin variants.
Not available on “GPG” variants.
Only available on “MC” variants.
(1)
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 10-6:
Legend:
Note 1:
2:
3:
31:16
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
03D0 SRCON1D
31/15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
SR1D6 (1)
SR1D5 (1
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
SR1D8
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Does not exist on 48 pin variants.
Not available on “GPG” variants.
Only available on “MC” variants.
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 200
Bits
TRISE
0420
PORTE
0430
LATE
CNPUE
CNPDE
0470 CNCONE
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ANSA15(1)
ANSA14(1)
ANSA13(1)
ANSA12(1)
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
TRISE13(1 TRISE12(1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISE1 (1)
—
0000
TRISE0(
F003
1)
15:0 TRISE15(1) TRISE14(1)
31:16
15:0
15:0
15:0
CNENE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RE1 (1)
—
0000
RE0(1) xxxx
—
—
—
—
—
—
—
—
—
—
—
—
0000
LATE0(1
xxxx
)
LATE15(1)
LATE14(1)
LATE13(1)
LATE12(1)
ODCE13(1 ODCE12(1
)
)
CNPUE15( CNPUE14( CNPUE13( CNPUE12(
CNNEE
DS60001570C-page 201
CNFE
04C0 SRCON0E
Legend:
Note 1:
2:
3:
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
ODCE0(
0000
—
—
—
—
—
—
—
—
—
—
ODCE1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CNPUE1( CNPUE
0000
1)
0(1)
—
—
—
—
—
—
—
—
—
—
—
1)
0000
1)
1)
15:0
CNPDE15(1)
CNPDE14(1)
CNPDE13(1)
CNPDE12(1)
—
—
—
—
—
—
—
—
—
—
CNPDE1(1)
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
15:0
15:0
ON
—
SIDL
—
—
—
—
CNENE15( CNENE14( CNENE13( CNENE12(
1)
1)
1)
1)
15:0
CNSTATE CNSTATE CNSTATE CNSTATE
15(1)
14(1)
13(1)
12(1)
15:0
CNNEE15( CNNEE14( CNNEE13( CNNEE12(
1)
1)
1)
1)
31:16
04B0
—
—
1)
31:16
04A0
—
LATE1(1)
1)
31:16
0490 CNSTATE
F003
—
—
RE12(1)
ODCE14
(1
)
RE13(1)
15:0 ODCE15
(1)
)
RE14(1)
(1)
ANSA41 ANSA40
—
RE15(1)
(1)
31:16
0480
0000
28/12
31:16
0460
—
29/13
31:16
0450
—
30/14
31:16
ODCE
16/0
31/15
31:16
0440
17/1
All
Resets
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
0400 ANSELE
0410
PORTE REGISTER MAP
15:0 CNFE15
31:16
(1)
(1)
CNFE14
(1)
CNFE13
(1)
CNFE12
—
—
—
—
SR0E15(1)
SR0E14(1)
SR0E13(1)
SR0E12(1)
—
—
15:0
—
—
—
—
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Does not exist on 48 pin variants.
Not available on “GPG” variants.
Only available on “MC” variants.
—
—
0000
CNP0000
DE0(1)
—
—
0000
CNENE1( CNENE
0000
1)
0(1)
—
—
0000
CNSTATE CNSTA
0000
1(1)
TE0(1)
—
—
0000
CNNEE1( CNNEE
0000
1)
0(1)
—
CNFE1
(1)
—
0000
CNFE0(
0000
1)
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 10-7:
Legend:
Note 1:
2:
3:
31:16
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
04D0 SRCON1E
31/15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
15:0 SR1E15(1) SR1E14(1) SR1E13(1) SR1E12(1)
—
—
—
—
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Does not exist on 48 pin variants.
Not available on “GPG” variants.
Only available on “MC” variants.
DS60001570C-page 202
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
Bits
TRISF
0520
PORTF
0530
LATF
0540
ODCF
0550
CNPUF
CNPDF
0570 CNCONF
0580
CNENF
0590 CNSTATF
2019-2020 Microchip Technology Inc.
05A0
CNNEF
05B0
CNFF
05C0 SRCON0F
05D0 SRCON1F
Legend:
Note 1:
2:
3:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
0510
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
0500 ANSELF
0560
PORTF REGISTER MAP
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LATF1(1) LATF0(1) xxxx
—
—
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ODCF1(1) ODCF0(1) 0000
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
EDGE
DETECT
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
15:0
—
—
TRISF1(1) TRISF0(1) 0003
—
—
0000
RF1(1)
—
RF0(1)
—
CNPUF1( CNPUF0(
1)
1)
xxxx
0000
0000
—
—
0000
CNPDF1( CNPDF0(
0000
1)
1)
CNENF1( CNENF0(
1)
1)
0000
—
—
0000
CNSTATF CNSTATF
0000
1(1)
0(1)
—
—
CNNEF1( CNNEF0(
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNFF1(1) CNFF0(1) 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
SR0F1(1) SR0F0(1) 0000
0000
—
—
—
—
—
—
—
—
SR1F1(1) SR1F0(1) 0000
15:0
—
—
—
—
—
—
—
—
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Does not exist on 48 pin variants.
Not available on “GPG” variants.
Only available on “MC” variants.
1)
1)
0000
—
—
0000
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 203
TABLE 10-8:
Virtual Address
(BF86_#)
Register
Name(1)
0600
ANSELG
0610
TRISG
0630
0640
0650
0660
PORTG
LATG
ODCG
CNPUG
CNPDG
0670 CNCONG
0680
CNENG
0690 CNSTATG
Bit Range
Bits
25/9
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
0620
PORTG REGISTER MAP
—
—
—
—
—
—
—
—
0000
ANSA18(1)
ANSA19(1)
—
—
—
—
—
—
—
—
—
—
—
—
03C0
0000
—
—
—
—
—
—
—
—
—
—
—
—
03C0
0000
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
0000
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
31/15
30/14
29/13
28/12
27/11
26/10
24/8
23/7
31:16
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
ANSA16(1)
ANSA17(1)
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
TRISG9(1)
TRISG8(1)
TRISG7(1)
TRISG6(1)
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
RG9(1)
RG8(1)
RG7(1)
RG6(1)
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
LATG9(1)
LATG8(1)
LATG7(1)
LATG6(1)
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
ODCG9(1)
ODCG8(1)
ODCG7(1)
ODCG6(1)
—
—
—
15:0
—
—
—
—
—
—
CNPUG9(1)
CNPUG8(1)
CNPUG7(1)
CNPUG6(1)
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
CNPDG9(1)
CNPDG8(1)
CNPDG7(1)
CNPDG6(1)
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
SIDL
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNENG9(1)
CNENG8(1)
CNENG7(1)
CNENG6(1)
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CNSTATG9(1 CNSTATG8(1
(1)
(1)
15:0
—
—
—
—
—
—
)
)
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
CNNEG9(1)
CNNEG8(1)
CNNEG7(1)
CNNEG6(1)
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
CNFG9(1)
CNFG8(1)
CNFG7(1)
CNFG6(1)
—
—
—
—
—
—
0000
SRCON0 31:16
06C0
G
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
SR0G7(1)
SR0G6(1)
—
—
—
—
—
—
0000
SRCON1 31:16
G
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
SR1G7(1)
SR1G6(1)
—
—
—
—
—
—
0000
06A0
2019-2020 Microchip Technology Inc.
06B0
06D0
CNNEG
CNFG
Legend:
Note 1:
2:
3:
CNSTATG7
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Does not exist on 48 variants.
Not available on “GPG” variants.
Only available on “MC” variants.
CNSTATG6
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 204
TABLE 10-9:
1408
140C
1410
1418
141C
1420
1424
1428
142C
1430
1434
1438
DS60001570C-page 205
143C
1440
Legend:
Note 1:
2:
3:
INT1R
INT2R
INT3R
INT4R
T2CKR
T3CKR
T4CKR
T5CKR
T6CKR
T7CKR
T8CKR
T9CKR
IC1R
IC2R
IC3R
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Does not exist on 48 pin variants.
Not available on “GPG” variants.
Only available on “MC” variants.
INT1R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IC3R
0000
0000
—
IC2R
—
0000
0000
—
IC1R
—
0000
0000
—
T9CKR
—
0000
0000
—
T8CKR
—
0000
0000
—
T7CKR
—
0000
0000
—
T6CKR
—
0000
0000
—
T5CKR
—
0000
0000
—
T4CKR
—
0000
0000
—
T3CKR
—
0000
0000
—
T2CKR
—
0000
0000
—
INT4R
—
0000
0000
—
INT3R
—
0000
0000
—
INT2R
—
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
1404
Bits
0000
0000
—
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 10-10: PERIPHERAL PIN SELECT INPUT REGISTER MAP
1444
IC4R
1448
IC5R
144C
IC6R
1450
IC7R
1454
IC8R
1458
IC9R
145C
1460
OCFAR
OCFBR
1464
1468
U1RXR
U1CTSR
146C
2019-2020 Microchip Technology Inc.
1470
U2RXR
U2CTSR
1498
SDI1R
149C
SS1R
14A0
SCK2R
Legend:
Note 1:
2:
3:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Does not exist on 48 pin variants.
Not available on “GPG” variants.
Only available on “MC” variants.
IC4R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCK2R
0000
0000
—
SS1R
—
0000
0000
—
SDI1R
—
0000
0000
—
U2CTSR
—
0000
0000
—
U2RXR
—
0000
0000
—
U1CTSR
—
0000
0000
—
U1RXR
—
0000
0000
—
OCFBR
—
0000
0000
—
OCFAR
—
0000
0000
—
IC9R
—
0000
0000
—
IC8R
—
0000
0000
—
IC7R
—
0000
0000
—
IC6R
—
0000
0000
—
IC5R
—
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000
0000
—
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 206
TABLE 10-10: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
14A4
SDI2R
14A8
14C4
14C8
SS2R
C1RXR
(3)
C2RXR(3)
14CC
REFIR
14D0
QEA1R(3)
14D4
QEB1R(3)
14D8
14DC
INDX1R(3)
HOME1R(3)
14E0
QEA2R(3)
14E4
QEB2R(3)
14E8
14EC
INDX2R(3)
HOME2R(3)
DS60001570C-page 207
14F0
FLT1R(3)
14F4
(3)
FLT2R
Legend:
Note 1:
2:
3:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Does not exist on 48 pin variants.
Not available on “GPG” variants.
Only available on “MC” variants.
SDI2R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FLT2R
0000
0000
—
FLT1R
—
0000
0000
—
HOME2R
—
0000
0000
—
INDX2R
—
0000
0000
—
QEB2R
—
0000
0000
—
QEA2R
—
0000
0000
—
HOME1R
—
0000
0000
—
INDX1R
—
0000
0000
—
QEB1R
—
0000
0000
—
QEA1R
—
0000
0000
—
REFIR
—
0000
0000
—
C2RXR
—
0000
0000
—
C1RXR
—
0000
0000
—
SS2R
—
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000
0000
—
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 10-10: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
152C
1530
1534
C3RXR(3)
C4RXR(3)
QEA3R(3)
1538
QEB3R(3)
153C
(3)
1540
1574
1578
157C
1580
INDX3R
HOME3R(3)
CLCIN1
CLCIN2
CLCIN3
CLCIN4
2019-2020 Microchip Technology Inc.
Legend:
Note 1:
2:
3:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Does not exist on 48 pin variants.
Not available on “GPG” variants.
Only available on “MC” variants.
C3RXR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLCIN4R
0000
0000
—
CLCIN3R
—
0000
0000
—
CLCIN2R
—
0000
0000
—
CLCIN1R
—
0000
0000
—
HOME3R
—
0000
0000
—
INDX3R
—
0000
0000
—
QEB3R
—
0000
0000
—
QEA3R
—
0000
0000
—
C4RXR
—
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000
0000
—
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 208
TABLE 10-10: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
DS60001570C-page 209
—
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1604 RPA1R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1608 RPA2R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
160C RPA3R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1610 RPA4R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
161C RPA7R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1620 RPA8R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
162C RPA11R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1630 RPA12R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1638 RPA14R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
163C RPA15R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1640 RPB0R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1644 RPB1R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1648 RPB2R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
164C RPB3R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1650 RPB4R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1654 RPB5R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1658 RPB6R
15:0
—
—
—
—
—
—
—
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1600
Note
RPA0R
1:
Does not exist on 48 pin variants.
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RPA0R
—
RPA1R
—
RPA2R
—
RPA3R
—
RPA4R
—
RPA7R
—
RPA8R
—
RPA11R
—
RPA12R
—
RPA14R
—
RPA15R
—
RPB0R
—
RPB1R
—
RPB2R
—
RPB3R
—
RPB4R
—
RPB5R
—
RPB6R
—
—
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 10-11: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
2019-2020 Microchip Technology Inc.
—
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1664 RPB9R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1668 RPB10R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
166C RPB11R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1670 RPB12R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1674 RPB13R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1678 RPB14R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
167C RPB15R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1680 RPC0R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1684 RPC1R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1688 RPC2R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1690 RPC4R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1698 RPC6R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
169C RPC7R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
16A0 RPC8R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
16A4 RPC9R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
16A8 RPC10R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
16B0 RPC12R
15:0
—
—
—
—
—
—
—
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
165C
Note
RPB7R
1:
Does not exist on 48 pin variants.
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RPB7R
—
RPB9R
—
RPB10R
—
RPB11R
—
RPB12R
—
RPB13R
—
RPB14R
—
RPB15R
—
RPC0R
—
RPC1R
—
RPC2R
—
RPC4R
—
RPC6R
—
RPC7R
—
RPC8R
—
RPC9R
—
RPC10R
—
RPC12R
—
—
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 210
TABLE 10-11: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
DS60001570C-page 211
—
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
16CC RPD3R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
16D0 RPD4R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
16D4 RPD5R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
16D8 RPD6R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1700 RPE0R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1704 RPE1R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1738 RPE14R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
173C RPE15R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1740 RPF0R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1744 RPF1R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1780 RPG0R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1784 RPG1R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1798 RPG6R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
179C RPG7R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
17A0 RPG8R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
17A4 RPG9R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
17B0 RPG12R
15:0
—
—
—
—
—
—
—
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
16BC
Note
RPC15R
1:
Does not exist on 48 pin variants.
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RPC15R
—
RPD3R
—
RPD4R
—
RPD5R
—
RPD6R
—
RPE0R
—
RPE1R
—
RPF14R
—
RPE15R
—
RPF0R
—
RPF1R
—
RPG0R
—
RPG1R
—
RPG6R
—
RPG7R
—
RPG8R
—
RPG9R
—
RPG12R
—
—
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 10-11: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 10-1:
Bit
Range
31:24
23:16
15:8
7:0
[pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
[pin name]R
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4
Unimplemented: Read as ‘0’
bit 3-0
[pin name]R: Peripheral Pin Select Input bits
Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Table 10-1 for
input pin selection values.
Note:
Register values can only be changed if the IOLOCK Configuration bit (CFGCON) = 0.
REGISTER 10-2:
Bit
Range
31:24
23:16
15:8
7:0
RPnR: PERIPHERAL PIN SELECT OUTPUT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RPnR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-5
Unimplemented: Read as ‘0’
bit 4-0
RPnR: Peripheral Pin Select Output bits
See Table 10-2 for output pin selection values.
Note:
x = Bit is unknown
Register values can only be changed if the IOLOCK Configuration bit (CFGCON) = 0.
DS60001570C-page 212
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 10-3:
Bit
Range
31:24
23:16
15:8
7:0
CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (x = A – G)
Bit
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4
U-0
U-0
U-0
U-0
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
R/W-0
r-0
U-0
U-0
ON
—
SIDL
—
EDGEDETECT
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Change Notice (CN) Control ON bit
1 = CN is enabled
0 = CN is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Control bit
1 = CPU Idle mode halts CN operation
0 = CPU Idle mode does not affect CN operation
bit 12
Unimplemented: Read as ‘0’
bit 11
EDGEDETECT: Edge Detection Type Control bit
1 = Detects any edge on the pin (CNx is used for the CN event)
0 = Detects any edge on the pin (CNSTATx is used for the CN event)
bit 10
Reserved: Always write ‘0’
bit 9-0
Unimplemented: Read as ‘0’
2019-2020 Microchip Technology Inc.
DS60001570C-page 213
PIC32MK GPG/MCJ with CAN FD Family
11.0
Note:
TIMER1
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS60001105), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
PIC32MK GPG/MCJ with CAN FD Family of devices feature one synchronous/asynchronous 16-bit timer that can
operate as a free-running interval timer for various timing
applications and counting external events. This timer can
also be used with the low-power Secondary Oscillator
(SOSC) for real-time clock applications.
The following modes are supported by Timer1:
•
•
•
•
Synchronous Internal Timer
Synchronous Internal Gated Timer
Synchronous External Timer
Asynchronous External Timer
11.1
Additional Supported Features
• Selectable clock prescaler
• Timer operation during Sleep and Idle modes
• Fast bit manipulation using CLR, SET, and INV
registers
• Asynchronous mode can be used with the SOSC
to function as a real-time clock
• ADC event trigger
11.2
11.2.1
TImer1 Usage Model Guidelines
EXTERNAL CLOCK MODE
OPERATION
11.2.2
ASYNCHRONOUS MODE
OPERATION
When writing the ON bit when the Timer is configured
in Asynchronous mode or in an external clock mode
with the prescaler enabled, the act of setting the ON bit
does not take effect until two rising edges of the
external clock input have occurred.
11.2.3
ASYNCHRONOUS MODE
OPERATION WITH A PENDING
TMRx REGISTER WRITE
When the Timer is configured in Asynchronous mode
and the Timer is attempting to write to the TMRx
register while a previous write is awaiting
synchronization, the value written to the timer can
become corrupted.
To ensure that writes will not cause the TMRx value to
become corrupted, the TWDIS bit (TxCON), when
set, will ignore a write to the TMRx register when a
previous write to the TMRx register is awaiting synchronization into the Asynchronous Timer Clock domain.
The TWIP bit (TxCON) indicates when write
synchronization is complete, and it is safe to write
another value to the timer.
11.2.4
PRx REGISTER WRITES
Writing to the PRx register while the Timer is active,
may cause erratic operation.
11.2.5
TIMER1 FORMULA
PR1 = ((Desired Time * FPBCLK2) - Prescaler Count)
• Prescaler Count = 1, 8, 64, 256
• FPBCLK2 = (FSYSCLK / PB2DIV)
Note:
Timer1 interrupt occurs one additional
prescaler cycle count after the timer and
period match (TMR1 = PR1).
When the Timer is operating with an external clock
mode with the TCS bit (TxCON) = 1, the mode bits
of the TxCON register must be initialized using a separate Write operation from that used to enable the Timer.
Specifically, the TCS, TSYNC, etc. bits must be written
first, and then the ON bit (TxCON) must be set in
a subsequent write.
Once the ON bit is set, any writes to the TxCON
register may cause erroneous counter operation.
Note:
The ON bit should be clear when updates
are made to any other bits in the TxCON
register.
DS60001570C-page 214
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 11-1:
TIMER1 BLOCK DIAGRAM
PR1
Q
D
16-bit Comparator
TSYNC
Q
1
Sync
TMR1
Reset
T1IF(1)
Event Flag
0
0
1
Q
TGATE
D
Q
TGATE
TCS
ON
SOSC
00
T1CK
01
LPRC
10
TECS
x1
Gate
Sync
PBCLK2
10
00
Prescaler
1, 8, 64, 256
2
TCKPS
Note:
Timer1
trigger
and interrupt
occurs
onplus
match
1 count, TMR1
therefore
set the
period
to PR1 - 1 to compensate
Note
1: ADC
Timer1
Trigger/T1IF
is on PR1
match
one+additional
prescaler
count
value.
irregardless of the pre-scaler.
2019-2020 Microchip Technology Inc.
DS60001570C-page 215
Timer1 Control Register
Virtual Address
(BF82_#)
TABLE 11-1:
TMR1
0020
Legend:
PR1
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
15:0
31:16
ON
—
—
—
SIDL
—
—
—
—
—
—
TWDIS
—
TWIP
—
—
—
TECS
—
—
15:0
31:16
—
—
—
—
—
—
—
23/7
22/6
21/5
20/4
19/3
—
—
—
—
—
TGATE
—
—
—
TCKPS
—
—
—
—
—
—
—
—
TMR1
—
—
15:0
PR1
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
18/2
All Resets
Bit Range
Register
Name(1)
Bits
0000 T1CON
0010
TIMER1 REGISTER MAP
17/1
16/0
—
—
—
0000
TSYNC
—
TCS
—
—
—
0000
0000
—
—
0000
0000
FFFF
Note 1:All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
DS60001570C-page 216
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
11.3
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 11-1:
Bit
Range
31:24
23:16
15:8
7:0
T1CON: TYPE A TIMER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
R/W-0
R-0
U-0
R/W-0
R/W-0
ON
—
SIDL
TWDIS
TWIP
—
R/W-0
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
TGATE
—
—
TSYNC
TCS
—
TCKPS
TECS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Timer On bit
1 = Timer is enabled
0 = Timer is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation even in Idle mode
bit 12
TWDIS: Asynchronous Timer Write Disable bit
1 = Writes to TMR1 are ignored until pending write operation completes
0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
bit 11
TWIP: Asynchronous Timer Write in Progress bit
In Asynchronous Timer mode:
1 = Asynchronous write to TMR1 register in progress
0 = Asynchronous write to TMR1 register complete
In Synchronous Timer mode:
This bit is read as ‘0’.
bit 10
Unimplemented: Read as ‘0’
bit 9-8
TECS: Timer1 External Clock Selection bits
11 =Reserved
10 =External clock comes from the LPRC
01 =External clock comes from the T1CK pin
00 = External clock comes from the SOSC
bit 7
TGATE: Timer Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5-4
TCKPS: Timer Input Clock Prescale Select bits
11 =1:256 prescale value
10 =1:64 prescale value
01 =1:8 prescale value
00 =1:1 prescale value
2019-2020 Microchip Technology Inc.
DS60001570C-page 217
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 11-1:
T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED)
bit 3
Unimplemented: Read as ‘0’
bit 2
TSYNC: Timer External Clock Input Synchronization Selection bit
When TCS = 1:
1 = External clock input is synchronized
0 = External clock input is not synchronized
When TCS = 0:
This bit is ignored.
bit 1
TCS: Timer Clock Source Select bit
1 = External clock is defined by the TECS bits
0 = Internal peripheral clock
bit 0
Unimplemented: Read as ‘0’
DS60001570C-page 218
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
NOTES:
2019-2020 Microchip Technology Inc.
DS60001570C-page 219
PIC32MK GPG/MCJ with CAN FD Family
12.0
Note:
TIMER2 THROUGH TIMER9
12.1
Features
The following are key features of the timers:
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS60001105), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
• External 16/32-bit Counter Input mode
• Asynchronous external clock with/without
selectable prescaler
• Synchronous internal clock with/without
selectable prescaler
• External gate control (External pulse width
measurement)
• Automatic timer synchronization control
• Operation in Idle mode
• Interrupt on a period register match or falling edge
of external gate signal
• Time base for Input Capture and/or Output
Compare modules
The PIC32MK GPG/MCJ with CAN FD Family of
devices
features
eight
native
synchronous/
asynchronous 16/32-bit timers (default 16-bit mode)
that can operate as free-running interval timers for
various timing applications and counting external
events.
12.2
Timer2-Timer9 Formula
PRx = ((Desired Time * FPBCLK2) - Prescaler Count)
• Prescaler Count = 1, 2, 4, 8, 16, 32, 64, 256
• FPBCLK2 = (FSYSCLK / PB2DIV)
Note:
FIGURE 12-1:
Timer interrupts and triggers occur one
additional prescaler cycle count after the
timer and period match (TMRx = PRx).
TIMER2 THROUGH TIMER9 BLOCK DIAGRAM (16/32-BIT)
Reset
Sync
TMRx (16/32)
Trigger to
ADC(1,2)
Q
Q
D
Equal
Comparator x 16/32
PRx (16/32)
0
TxIF
Event
Flag(2)
1
TGATE
Q
TGATE
D
Q
TCS
ON
TxCK
x1
Gate
Sync
PBCLK2
Note
1:
2:
10
00
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
3
TCKPS
ADC event trigger is only available on Timer, Timer3, and Timer5.
Timer_x ADC trigger and interrupts occurs on match + 1 count, therefore set the period to PRx- 1 to compensate irregardless of the pre-scaler.
DS60001570C-page 220
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 12-2:
TIMER SYNCHRONIZATION BLOCK DIAGRAM
Timer2
(1)
0
Timer3
Timerx
(1)
1
TCON2
Sync
TON
0
1
TON (to Timer2)
2019-2020 Microchip Technology Inc.
0
1
TCONx
Sync
TON
0
1
TON (to Timerx)
DS60001570C-page 221
Timer2-Timer9 Control Registers
TIMER2 THROUGH TIMER9 REGISTER MAP
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
SYNC
—
TGATE
—
—
TCKPS
—
—
T32
—
—
—
TCS
—
—
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF82_#)
TABLE 12-1:
0200 T2CON
31:16
15:0
0210
TMR2
31:16
15:0
TMR2
TMR2
0000
0000
0220
PR2
31:16
15:0
PR2
PR2
FFFF
FFFF
—
ON
0400 T3CON
31:16
15:0
0410
TMR3
31:16
15:0
TMR3
TMR3
0000
0000
0420
PR3
31:16
15:0
PR3
PR3
FFFF
FFFF
—
ON
—
—
TMR5
31:16
15:0
TMR5
TMR5
0000
0000
0820
PR5
31:16
15:0
PR5
PR5
FFFF
FFFF
DS60001570C-page 222
31:16
15:0
0A10 TMR6
31:16
15:0
TMR6
TMR6
0000
0000
0A20
31:16
15:0
PR6
PR6
FFFF
FFFF
0C00 T7CON
Legend:
Note 1:
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SYNC
—
SYNC
—
TGATE
—
TGATE
—
—
—
TCKPS
—
TCKPS
—
—
—
T32
—
T32
—
—
—
—
—
TCS
—
TCS
—
—
0000
0000
0A00 T6CON
PR6
—
—
—
—
0000
0000
0810
—
SIDL
—
TCS
—
—
0000
0000
31:16
15:0
—
—
—
—
—
TCS
—
—
0800 T5CON
—
ON
—
T32
—
—
—
TCS
FFFF
FFFF
—
—
T32
—
—
PR4
PR4
—
TCKPS
—
—
T32
31:16
15:0
—
—
TCKPS
—
PR4
—
TGATE
—
—
TCKPS
0620
—
SYNC
—
TGATE
—
0000
0000
—
—
—
SYNC
—
TGATE
TMR4
TMR4
—
—
—
—
—
SYNC
31:16
15:0
—
—
—
—
—
—
TMR4
—
—
—
—
—
—
0610
—
SIDL
—
—
—
—
31:16
15:0
—
—
—
SIDL
—
—
0600 T4CON
—
ON
—
—
—
SIDL
0000
0000
—
—
0000
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
12.3
Virtual Address
(BF82_#)
0C20
PR7
0E00 T8CON
0E10 TMR8
0E20
PR8
1000 T9CON
TMR9
1020
PR9
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Bits
0C10 TMR7
1010
TIMER2 THROUGH TIMER9 REGISTER MAP (CONTINUED)
31:16
TMR7
0000
15:0
31:16
TMR7
PR7
0000
FFFF
15:0
31:16
15:0
31:16
—
—
—
—
—
—
—
ON
—
SIDL
—
—
—
—
15:0
31:16
PR7
—
—
—
SYNC
TGATE
TMR8
—
—
TCKPS
—
—
—
—
T32
—
TCS
—
TMR8
PR8
15:0
31:16
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
PR8
—
—
SYNC
TGATE
FFFF
0000
0000
0000
0000
FFFF
—
—
TCKPS
—
—
—
—
—
FFFF
0000
T32
—
TCS
—
0000
31:16
TMR9
0000
15:0
TMR9
0000
31:16
PR9
FFFF
15:0
PR9
FFFF
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
1:
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 223
TABLE 12-1:
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 12-1:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
R/W-0
ON
—
SIDL
—
—
—
—
SYNC
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
T32
—
TCS
—
TGATE
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15
bit 14
bit 13
bit 12-9
bit 8
TxCON: TYPE B TIMER CONTROL REGISTER (‘x’ = 2-9)
TCKPS
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
ON: Timer On bit
1 = Module is enabled
0 = Module is disabled
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation even in Idle mode
Unimplemented: Read as ‘0’
SYNC: TMRx Synchronized Timer Start/Stop Enable bit
1 = TMRx synchronized timer start/stop is enabled
0 = TMRx synchronized timer start/stop is disabled
Note:
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Setting this bit chains all timers whose corresponding SYNC bit is also set such that when the
TON bit of all corresponding timers is set, the timers are enabled simultaneously. If any timers
in the group are disabled, they are all disabled simultaneously. See Figure 12-2 for additional
information.
TGATE: Timer Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored and is read as ‘0’.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
TCKPS: Timer Input Clock Prescale Select bits
111 = 1:256 prescale value
110 = 1:64 prescale value
101 = 1:32 prescale value
100 = 1:16 prescale value
011 = 1:8 prescale value
010 = 1:4 prescale value
001 = 1:2 prescale value
000 = 1:1 prescale value
T32: 32-Bit Timer Mode Select bit
1 = 32-bit Timer mode
0 = 16-bit Timer mode
Unimplemented: Read as ‘0’
TCS: Timer Clock Source Select bit
1 = External clock from TxCK pin
0 = Internal peripheral clock
Unimplemented: Read as ‘0’
DS60001570C-page 224
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
NOTES:
2019-2020 Microchip Technology Inc.
DS60001570C-page 225
PIC32MK GPG/MCJ with CAN FD Family
13.0
DEADMAN TIMER (DMT)
Note:
The primary function of the Deadman Timer (DMT) is
to reset the processor in the event of a software malfunction. The DMT is a free-running instruction fetch
timer, which is clocked whenever an instruction fetch
occurs until a count match occurs. Instructions are not
fetched when the processor is in Sleep mode.
This data sheet summarizes the
features of the PIC32MK GPG/MCJ with
CAN FD Family of devices. It is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 9. “Watchdog, Deadman, and
Power-up
Timers”
(DS60001114),
which
is
available
from
the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The DMT consists of a 32-bit counter with a time-out
count match value as specified by the DMTCNT
bits in the DEVCFG1 Configuration register.
A Deadman Timer is typically used in mission critical
and safety critical applications, where any single
failure of the software functionality and sequencing
must be detected.
Figure 13-1 shows a block diagram of the Deadman
Timer module.
FIGURE 13-1:
DEADMAN TIMER BLOCK DIAGRAM
“improper sequence” flag
ON
Instruction Fetched Strobe
Force DMT Event
System Reset
Counter Initialization Value
SYSCLK
Clock
“Proper Clear Sequence” Flag
ON
32-bit counter
ON
32
DMT event
to NMI(3)
DMT Count Reset Load
System Reset
(COUNTER) = DMT Max Count(1)
(COUNTER) DMT Window Interval(2)
Window Interval Open
Note
1:
2:
3:
DMT Max Count is controlled by the DMTCNT bits in the DEVCFG1 Configuration register.
DMT Window Interval is controlled by the DMTINTV bits in the DEVCFG1 Configuration register.
Refer to 5.0 “Resets” for more information.
DS60001570C-page 226
2019-2020 Microchip Technology Inc.
Deadman Timer Control Registers
Register
Name
Bit Range
DEADMAN TIMER REGISTER MAP
Virtual Address
(BF80_#)
TABLE 13-1:
0E00
DMTCON
31:16
15:0
All Resets
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0E10 DMTPRECLR
31:16
15:0
—
—
—
—
—
STEP1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0E20
DMCLR
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STEP2
—
—
—
0000
0000
0E30
DMTSTAT
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BAD1
—
BAD2
—
DMTEVENT
—
—
—
—
—
—
0E40
DMTCNT
31:16
15:0
0E60
DMTPSCNT
0E70
DMTPSINTV
Legend:
31:16
15:0
31:16
15:0
COUNTER
PSCNT
PSINTV
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
0000
WINOPN 0000
0000
0000
0000
0000
0000
0000
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 227
13.1
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 13-1:
Bit Range
DMTCON: DEADMAN TIMER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
31:24
23:16
15:8
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
ON
7:0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-16
Unimplemented: Read as ‘0’
bit 15
ON: Deadman Timer Module Enable bit(1)
1 = Deadman Timer module is enabled
0 = Deadman Timer module is disabled
bit 13-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
This bit only has control when FDMTEN (DEVCFG1) = 0.
REGISTER 13-2:
Bit Range
DMTPRECLR: DEADMAN TIMER PRECLEAR REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
STEP1
7:0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15-8
STEP1: Preclear Enable bits
01000000 = Enables the Deadman Timer Preclear (Step 1)
All other write patterns = Set BAD1 flag.
These bits are cleared when a DMT reset event occurs. STEP1 is also cleared if the
STEP2 bits are loaded with the correct value in the correct sequence.
bit 7-0
Unimplemented: Read as ‘0’
DS60001570C-page 228
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 13-3:
Bit Range
Bit
30/22/14/6
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
DMTCLR: DEADMAN TIMER CLEAR REGISTER
Bit
31/23/15/7
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STEP2
Legend:
R = Readable bit
-n = Value at POR
bit 31-8
bit 7-0
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
STEP2: Clear Timer bits
00001000 = Clears STEP1, STEP2 and the Deadman Timer if, and only if, preceded by
correct loading of STEP1 bits in the correct sequence. The write to these bits may
be verified by reading DMTCNT and observing the counter being reset.
All other write patterns = Set BAD2 bit, the value of STEP1 will remain unchanged, and the new
value being written STEP2 will be captured. These bits are also cleared when a DMT reset event
occurs.
2019-2020 Microchip Technology Inc.
DS60001570C-page 229
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 13-4:
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
DMTSTAT: DEADMAN TIMER STATUS REGISTER
bit 6
bit 5
bit 4-1
bit 0
Bit
Bit
25/17/9/1 24/16/8/0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0, HC
R-0, HC
R-0, HC
R/W-0
R/W-0
R/W-0
R/W-0
R-0
BAD1
BAD2
DMTEVENT
Legend:
R = Readable bit
-n = Value at POR
bit 31-8
bit 7
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
HC = Hardware Cleared
W = Writable bit
‘1’ = Bit is set
WINOPN
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
BAD1: Bad STEP1 Value Detect bit
1 = Incorrect STEP1 value or out of sequence write to STEP2 was detected
0 = Incorrect STEP1 value was not detected
BAD2: Bad STEP2 Value Detect bit
1 = Incorrect STEP2 value was detected
0 = Incorrect STEP2 value was not detected
DMTEVENT: Deadman Timer Event bit
1 = Deadman timer event was detected (counter expired or bad STEP1 or STEP2 value was
entered prior to counter increment)
0 = Deadman timer even was not detected
Note:
This bit is cleared only on a Reset.
Unimplemented: Read as ‘0’
WINOPN: Deadman Timer Clear Window bit
1 = Deadman timer clear window is open
0 = Deadman timer clear window is not open
DS60001570C-page 230
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 13-5:
Bit Range
DMTCNT: DEADMAN TIMER COUNT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
R-0
R-0
31:24
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
COUNTER
R-0
7:0
R-0
R-0
R-0
R-0
COUNTER
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
COUNTER: Read current contents of DMT counter
REGISTER 13-6:
DMTPSCNT: POST STATUS CONFIGURE DMT COUNT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
R-0
R-0
31:24
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
R-0
R-0
R-0
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-y
R-y
R-y
PSCNT
R-0
23:16
R-0
R-0
R-0
R-0
PSCNT
R-0
15:8
R-0
R-0
R-0
R-0
PSCNT
R-0
7:0
R-0
R-0
R-y
R-y
PSCNT
Legend:
R = Readable bit
-n = Value at POR
bit 31-8
R-0
Bit
24/16/8/0
COUNTER
15:8
Bit Range
R-0
Bit
25/17/9/1
COUNTER
23:16
bit 31-8
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
W = Writable bit
‘1’ = Bit is set
y= Value set from Configuration bits on POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
PSCNT: DMT Instruction Count Value Configuration Status bits
This is always the value of the DMTCNT bits in the DEVCFG1 Configuration register.
2019-2020 Microchip Technology Inc.
DS60001570C-page 231
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 13-7:
Bit Range
DMTPSINTV: POST STATUS CONFIGURE DMT INTERVAL STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
R-0
R-0
31:24
R-0
R-0
R-0
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-y
R-y
R-y
PSINTV
R-0
23:16
R-0
R-0
R-0
R-0
PSINTV
R-0
15:8
R-0
R-0
R-0
R-0
PSINTV
R-0
7:0
R-0
R-0
R-0
R-0
PSINTV
Legend:
R = Readable bit
-n = Value at POR
bit 31-8
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
W = Writable bit
‘1’ = Bit is set
y= Value set from Configuration bits on POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
PSINTV: DMT Window Interval Configuration Status bits
This is always the value of the DMTINTV bits in the DEVCFG1 Configuration register.
DS60001570C-page 232
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
NOTES:
2019-2020 Microchip Technology Inc.
DS60001570C-page 233
PIC32MK GPG/MCJ WITH CAN FD FAMILY
14.0
WATCHDOG TIMER (WDT)
Note:
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 9. “Watchdog,
Deadman, and Power-up Timers”
(DS60001114), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
FIGURE 14-1:
When enabled, the Watchdog Timer (WDT) operates
from the internal Low-Power Oscillator (LPRC) clock
source and can be used to detect system software malfunctions by resetting the device if the WDT is not
cleared periodically in software. Various WDT time-out
periods can be selected using the WDT postscaler. The
WDT can also be used to wake the device from Sleep
or Idle mode.
Some of the key features of the WDT module are:
• Configuration or software controlled
• User-configurable time-out period
• Can wake the device from Sleep or Idle
WATCHDOG TIMER BLOCK DIAGRAM
LPRC
WDTCLR = 1
ON
Wake
ON
Reset Event
ON
Clock
25-bit Counter
25
0
WDT Counter Reset
1
WDT Event
to NMI(1)
Power Save
Decoder
FWDTPS (DEVCFG1)
Note 1:
Refer to 5.0 “Resets” for more information.
DS60001570C-page 234
2019-2020 Microchip Technology Inc.
Watchdog Timer Control Registers
Register
Name
Bit Range
WATCHDOG TIMER REGISTER MAP
Virtual Address
(BF80_#)
TABLE 14-1:
0C00
WDTCON(1)
31:16
15:0
Legend:
Note 1:
31/15
30/14
29/13
ON
—
—
28/12
27/11
26/10
RUNDIV
25/9
24/8
23/7
22/6
WDTCLRKEY
—
—
21/5
20/4
19/3
SLPDIV
18/2
17/1
16/0
All Resets
Bits
0000
WDTWINEN 0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more information.
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ WITH CAN FD FAMILY
DS60001570C-page 235
14.1
PIC32MK GPG/MCJ WITH CAN FD FAMILY
REGISTER 14-1:
Bit
Range
31:24
23:16
15:8
7:0
WDTCON: WATCHDOG TIMER CONTROL REGISTER
Bit
31/23/15/7
W-0
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4
W-0
W-0
W-0
Bit
Bit
27/19/11/3 26/18/10/2
W-0
Bit
25/17/9/1
Bit
24/16/8/0
W-0
W-0
W-0
W-0
W-0
W-0
R-y
R-y
R-y
WDTCLRKEY
W-0
W-0
W-0
W-0
W-0
WDTCLRKEY
R/W-0
U-0
U-0
ON(1)
—
—
U-0
U-0
R-y
—
—
R-y
R-y
RUNDIV
R-y
R-y
R-y
R-y
SLPDIV
R/W-0
WDTWINEN
Legend:
y = Values set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 WDTCLRKEY: Watchdog Timer Clear Key bits
To clear the Watchdog Timer to prevent a time-out, software must write the value 0x5743 to these bits using
a single 16-bit write.
bit 15
ON: Watchdog Timer Enable bit(1)
1 = The Watchdog Timer module is enabled
0 = The Watchdog Timer module is disabled
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8
RUNDIV: Watchdog Timer Postscaler Value in Run Mode bits
In Run mode, these bits are set to the values of the WDTPS Configuration bits in the DEVCFG1
register.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-1
SLPDIV: Watchdog Timer Postscaler Value in Sleep Mode bits
In Sleep mode, these bits are set to the values of the WDTPS Configuration bits in the DEVCFG1
register.
bit 0
WDTWINEN: Watchdog Timer Window Enable bit
1 = Enable windowed Watchdog Timer
0 = Disable windowed Watchdog Timer
Note 1:
This bit only has control when FWDTEN (DEVCFG1) = 0.
DS60001570C-page 236
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ WITH CAN FD FAMILY
NOTES:
2019-2020 Microchip Technology Inc.
DS60001570C-page 237
PIC32MK GPG/MCJ with CAN FD Family
15.0
INPUT CAPTURE
Note:
- Capture every 4th rising edge of input at ICx
pin
- Capture every 16th rising edge of input at ICx
pin
- Capture every rising and falling edge of input
at ICx pin
- Capture timer values based on internal or
external clocks
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 15. “Input
Capture” (DS60001122), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
Each input capture channel can select between either
seven 16-bit time bases or three 32-bit time base. The
selected timer can use either an internal or external
clock.
Other operational features include:
The Input Capture module is useful in applications
requiring frequency (period) and pulse measurement.
• Device wake-up from capture pin during Sleep and
Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values; Interrupt
optionally generated after 1, 2, 3, or 4 buffer
locations are filled
• Input capture can also be used to provide additional
sources of external interrupts
• sources of external interrupts
The Input Capture module captures the 16-bit or 32-bit
value of the selected Time Base registers when an
event occurs at the ICx pin.
Capture events are caused by the following factors:
• Capture timer value on every edge (rising and falling),
specified edge first
• Prescaler capture event modes:
- Capture every falling edge of input at ICx pin
- Capture every rising edge of input at ICx pin
FIGURE 15-1:
INPUT CAPTURE BLOCK DIAGRAM
FEDGE
Specified/Every
Edge Mode
ICM
110
See Table 15-1
Timerx(2)
Prescaler Mode
(16th Rising Edge)
101
Prescaler Mode
(4th Rising Edge)
100
Rising Edge Mode
011
Falling Edge Mode
010
ICx(1)
C32
(ICxCON
ICACLK
(CFGCON
CaptureEvent
PBCLKx (‘x’ = 2, 3)(3)
Timery(2)
To CPU
FIFO Control
ICxBUF(1)
FIFO
ICI
Edge Detection
Mode
001
ICM
Set Flag ICxIF(1)
(In IFSx Register)
/N
Sleep/Idle
Wake-up Mode
111
Note
1:
An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
2:
See Table 15-1 for Timerx and Timery selections.
3:
PBCLK2 = Input Capture 1 through Input Capture 9..
DS60001570C-page 238
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
The timer source for each Input Capture module
depends on the setting of the ICACLK bit in the
CFGCON register and the C32 bit in the ICxCON
register. The available configurations are shown in
Table 15-1.
TABLE 15-1:
ICx
IC1-IC3
IC4-IC6,
IC7-IC9
TIMER SOURCE CONFIGURATIONS
ICACLK
C32
ICTMR
(CFGCON ICxCON ICxCON
Timerx
Timery
ICxBUF Contents
0
—
TMR3
TMR3
0
0
1
TMR2
—
TMR2
0
1
x
TMR2
TMR2
TMR2
1
0
0
—
TMR5
TMR5
1
TMR4
—
TMR4
1
1
x
TMR4
TMR4
TMR4
0
0
0
—
TMR3
TMR3
1
TMR2
—
TMR2
0
1
x
TMR2
TMR2
TMR2
1
0
0
—
TMR3
TMR3
1
TMR2
—
TMR2
1
1
x
TMR2
TMR2
TMR2
0
0
0
—
TMR3
TMR3
1
TMR2
—
TMR2
0
1
x
TMR2
TMR2
TMR2
1
0
0
—
TMR7
TMR7
1
TMR6
—
TMR6
x
TMR6
TMR6
TMR6
1
2019-2020 Microchip Technology Inc.
1
DS60001570C-page 239
Input Capture Control Registers
INPUT CAPTURE 1 THROUGH INPUT CAPTURE 9 REGISTER MAP
2000 IC1CON(1)
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS60001570C-page 240
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
IC1BUF
IC1BUF
2010
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2200 IC2CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
IC2BUF
2210 IC2BUF
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2400 IC3CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
IC3BUF
2410 IC3BUF
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2600 IC4CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
IC4BUF
2610 IC4BUF
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2800 IC5CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
IC5BUF
2810 IC5BUF
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2A00 IC6CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
IC6BUF
2A10 IC6BUF
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2C00 IC7CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
IC7BUF
2C10 IC7BUF
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2E00 IC8CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
IC8BUF
2E10 IC8BUF
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3000 IC9CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
IC9BUF
3010 IC9BUF
15:0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more information.
All Resets
Bit Range
Bits
Register
Name
Virtual Address
BF82_#
TABLE 15-2:
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
15.1
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 15-1:
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
U-0
R/W-0
ON
—
SIDL
R/W-0
R/W-0
31:24
23:16
15:8
7:0
ICXCON: INPUT CAPTURE ‘x’ CONTROL REGISTER (‘x’ = 1-9)
ICTMR(1)
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
FEDGE
C32
R-0
R-0
R/W-0
R/W-0
R/W-0
ICOV
ICBNE
R/W-0
ICI
ICM
Legend:
R = Readable bit
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = unknown)
U = Unimplemented bit
P = Programmable bit
r = Reserved bit
bit 31-16
Unimplemented: Read as ‘0’
bit 15
ON: Input Capture Module Enable bit
1 = Module enabled
0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Control bit
1 = Halt in CPU Idle mode
0 = Continue to operate in CPU Idle mode
bit 12-10
Unimplemented: Read as ‘0’
bit 9
FEDGE: First Capture Edge Select bit (only used in mode 6, ICM = 110)
1 = Capture rising edge first
0 = Capture falling edge first
bit 8
C32: 32-bit Capture Select bit
1 = 32-bit timer resource capture
0 = 16-bit timer resource capture
bit 7
ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON) is ‘1’)(1)
0 = Timery is the counter source for capture
1 = Timerx is the counter source for capture
bit 6-5
ICI: Interrupt Control bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4
ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
bit 3
ICBNE: Input Capture Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty; at least one more capture value can be read
0 = Input capture buffer is empty
Note 1:
Refer to Table 15-1 for Timerx and Timery selections.
2019-2020 Microchip Technology Inc.
DS60001570C-page 241
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 15-1:
bit 2-0
Note 1:
ICXCON: INPUT CAPTURE ‘x’ CONTROL REGISTER (‘x’ = 1-9) (CONTINUED)
ICM: Input Capture Mode Select bits
111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter
101 = Prescaled Capture Event mode – every sixteenth rising edge
100 = Prescaled Capture Event mode – every fourth rising edge
011 = Simple Capture Event mode – every rising edge
010 = Simple Capture Event mode – every falling edge
001 = Edge Detect mode – every edge (rising and falling)
000 = Input Capture module is disabled
Refer to Table 15-1 for Timerx and Timery selections.
DS60001570C-page 242
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
16.0
OUTPUT COMPARE
Note:
When a match occurs, the Output Compare module
generates an event based on the selected mode of
operation.
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 16. “Output
Compare” (DS60001111), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The following are some of the key features of the
Output Compare:
• Multiple Output Compare modules in a device
• Programmable interrupt generation on compare
event
• Single and Dual Compare modes
• Single and continuous output pulse generation
• Pulse-Width Modulation (PWM) mode
• Hardware-based PWM Fault detection and
automatic output disable
• Programmable selection of 16-bit or 32-bit time
bases
• Can operate from either of two available 16-bit
time bases or a single 32-bit time base
• ADC event trigger for OC1 through OC4
The Output Compare module is used to generate a
single pulse or a train of pulses in response to selected
time base events.
For all modes of operation, the Output Compare module compares the values stored in the OCxR and/or the
OCxRS registers to the value in the selected timer.
FIGURE 16-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit OCxIF(1)
OCxRS(1)
Trigger to ADC(4)
Output
Logic
OCxR(1)
3
OCM
Mode Select
Comparator
0
16/32
PBCLKx
(‘x’ = 2, 3)(5)
Timerx(3)
OCTSEL
1
0
S
R
Output
Enable
Q
OCx(1)
Output Enable
Logic
OCFA or
OCFB(2)
1
16/32
Timery(3)
Timerx(3)
Rollover
Timery(3)
Rollover
Note 1:Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels, 1
through 9.
2: The OCFA pin controls the OCMP1-OCMP3, and OCMP7-OCMP9 channels. The OCFB pin controls the OCMP4OCMP6 channels.
3: Refer to Table 16-1 for Timerx and Timery selections.
4: The ADC event trigger is only available on OC1 through OC4.
5:
PBCLK2 = Output Compare 1 through Output Compare 9.
2019-2020 Microchip Technology Inc.
DS60001570C-page 243
PIC32MK GPG/MCJ with CAN FD Family
The timer source for each Output Compare module
depends on the setting of the OCACLK bit in the
CFGCON register, the OC32 bit in the OCxCON
register, and the OCTSEL bit in the OCxCON register.
The available configurations are shown in Table 16-1.
OC Module
Fault Input
OCMP1-3
OCFA
OCMP4-6
OCFB
OCMP7-9
OCFA
TABLE 16-1:
TIMER SOURCE CONFIGURATIONS
OCx
OCACLK
OC32
OCTSEL
CFGCON (OCxCON OCxCON
OC1-OC3
0
0
1
1
OC4-OC6,
0
0
1
1
OC7-OC9
0
0
1
1
DS60001570C-page 244
0
1
0
1
0
1
0
1
0
1
0
1
Timerx
Timery
Output
Compare
Timer Source
TMR2
—
TMR2
1
—
TMR3
TMR3
0
TMR2
—
TMR2
1
—
TMR2
TMR2
0
TMR4
—
TMR4
1
—
TMR5
TMR5
0
TMR4
—
TMR4
1
—
TMR4
TMR4
0
TMR2
—
TMR2
1
—
TMR3
TMR3
0
TMR2
—
TMR2
1
—
TMR2
TMR2
0
TMR2
—
TMR2
1
—
TMR3
TMR3
0
TMR2
—
TMR2
1
—
TMR2
TMR2
0
TMR2
—
TMR2
1
—
TMR3
TMR3
0
TMR2
—
TMR2
1
—
TMR2
TMR2
0
TMR6
—
TMR6
1
—
TMR7
TMR7
0
TMR6
—
TMR6
1
—
TMR6
TMR6
0
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
16.1
Output Compare Control
Registers
REGISTER 16-1:
Bit
Range
31:24
23:16
15:8
7:0
OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER (‘x’ = 1-16)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ON
—
SIDL
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
OC32
R-0, HS, HC
(1)
R/W-0
—
OCFLT
OCTSEL(2)
OCM
Legend:
HS = Set in hardware
HC = Cleared by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Output Compare Peripheral On bit
1 = Output Compare peripheral is enabled
0 = Output Compare peripheral is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters Idle mode
0 = Continue operation in Idle mode
bit 12-6
Unimplemented: Read as ‘0’
bit 5
OC32: 32-bit Compare Mode bit
1 = OCxR and/or OCxRS are used for comparisons to the 32-bit timer source
0 = OCxR and OCxRS are used for comparisons to the 16-bit timer source
bit 4
OCFLT: PWM Fault Condition Status bit(1)
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred
bit 3
OCTSEL: Output Compare Timer Select bit(2)
1 = Timery is the clock source for this Output Compare module
0 = Timerx is the clock source for this Output Compare module
bit 2-0
OCM: Output Compare Mode Select bits
111 = PWM mode on OCx; Fault pin enabled
110 = PWM mode on OCx; Fault pin disabled
101 = Initialize OCx pin low; generate continuous output pulses on OCx pin
100 = Initialize OCx pin low; generate single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initialize OCx pin high; compare event forces OCx pin low
001 = Initialize OCx pin low; compare event forces OCx pin high
000 = Output compare peripheral is disabled but continues to draw current
Note 1:
2:
This bit is only used when OCM = ‘111’. It is read as ‘0’ in all other modes.
Refer to Table 16-1 for Timerx and Timery selections.
2019-2020 Microchip Technology Inc.
DS60001570C-page 245
PIC32MK GPG/MCJ with CAN FD Family
NOTES:
DS60001570C-page 246
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
The SPI/I2S module is compatible with Motorola® SPI
and SIOP interfaces.
17.0 SERIAL PERIPHERAL
INTERFACE (SPI) AND
INTER-IC SOUND (I2S)
Note:
The following are some of the key features of the SPI
module:
This data sheet summarizes the
features of the PIC32MK GPG/MCJ with
CAN FD Family of devices. It is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 23. “Serial Peripheral Interface
(SPI)” (DS60001106), which is available
from the Documentation > Reference
Manual section of the Microchip PIC32
web site (www.microchip.com/pic32).
•
•
•
•
•
Master and Slave modes support
Four different clock formats
Enhanced Framed SPI protocol support
User-configurable 32/24/16/8-bit data width
Separate SPI FIFO buffers for receive and transmit
- FIFO buffers act as 4/8/16-level deep FIFOs
based on 32/24/16/8-bit data width
• Programmable interrupt event on every 8-bit,
16-bit and 32-bit data transfer
• Operation during Sleep and Idle modes
• Audio codec support:
- I2S protocol
- Left-justified
- Right-justified
- PCM
The SPI/I2S module is a synchronous serial interface
that is useful for communicating with external
peripherals and other microcontroller devices, as well
as digital audio devices. These peripheral devices may
be Serial EEPROMs, Shift registers, display drivers,
analog-to-digital converters (ADC), and so on.
FIGURE 17-1:
SPI/I2S MODULE BLOCK DIAGRAM
Internal
Data Bus
SPIxBUF
Read
Write
SPIxRXB FIFO
FIFOs Share Address SPIxBUF
SPIxTXB FIFO
Transmit
Receive
SPIxSR
SDIx
bit 0
SDOx
SSx/FSYNC
Slave Select
and Frame
Sync Control
Shift
Control
Clock
Control
MCLKSEL
Edge
Select
SCKx
REFCLKO1
Baud Rate
Generator
PBCLK2 (SPI1-SPI2)
MSTEN
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.
2019-2020 Microchip Technology Inc.
DS60001570C-page 247
SPI Control Registers
SPI1 AND SPI2 REGISTER MAP
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
7000 SPI1CON
31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW
FRMCNT
15:0
ON
—
SIDL
DISSDO MODE32 MODE16
SMP
CKE
7010 SPI1STAT
31:16
15:0
7020 SPI1BUF
31:16
15:0
7030 SPI1BRG
31:16
15:0
—
—
7200 SPI2CON
7210 SPI2STAT
7220 SPI2BUF
7230 SPI2BRG
7240 SPI2CON2
Legend:
—
—
FRMERR
RXBUFELM
SPIBUSY
—
—
SPITUR
22/6
21/5
20/4
MCLKSEL
SSEN
—
CKP
—
MSTEN
—
DISSDI
—
SRMT
—
SPIROV
—
SPIRBE
—
19/3
18/2
—
—
STXISEL
17/1
16/0
SPIFE ENHBUF 0000
SRXISEL
0000
TXBUFELM
SPITBE
—
SPITBF
0000
SPIRBF 0028
0000
0000
DATA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SPI
TUREN
—
—
—
—
SPI
ROVEN
—
—
—
FRM
ERREN
IGNROV
IGNTUR
31:16 FRMEN FRMSYNC FRMPOL
MSSEN
FRMSYPW
DISSDO
MODE32
31:16
7040 SPI1CON2
—
—
23/7
—
SPI
15:0
SGNEXT
15:0
ON
—
SIDL
31:16
—
—
—
15:0
—
—
—
FRMCNT
MODE16
SMP
CKE
RXBUFELM
FRMERR
SPIBUSY
—
—
31:16
SPITUR
—
BRG
—
—
—
—
—
—
0000
0000
—
—
—
—
AUD
MONO
—
—
—
0000
—
—
AUDEN
—
—
—
MCLKSEL
—
—
—
SSEN
CKP
MSTEN
DISSDI
—
—
—
SRMT
SPIROV
SPIRBE
—
AUDMOD
SPIFE
STXISEL
SRXISEL
TXBUFELM
—
SPITBE
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SPI
FRM
SPI
SPI
15:0
—
—
IGNROV IGNTUR AUDEN
SGNEXT
ERREN
ROVEN
TUREN
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
0000
SPITBF
SPIRBF 0028
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AUD
MONO
—
BRG
—
0C00
ENHBUF 0000
DATA
15:0
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF82_#)
TABLE 17-1:
—
—
0000
0000
—
AUDMOD
2019-2020 Microchip Technology Inc.
Note 1:All registers in this table except SPIxBUF have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV
Registers” for more information.
0000
0C00
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 248
17.1
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 17-1:
Bit
Range
31:24
23:16
15:8
7:0
SPIxCON: SPI CONTROL REGISTER (X=1-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMEN
FRMSYNC
FRMPOL
MSSEN
FRMSYPW
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
FRMCNT
R/W-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
MCLKSEL(1)
—
—
—
—
—
SPIFE
ENHBUF(1)
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ON
—
SIDL
DISSDO(4)
MODE32
MODE16
SMP
CKE(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEN
CKP(3)
MSTEN
DISSDI(4)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
STXISEL
SRXISEL
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
FRMEN: Framed SPI Support bit
1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)
0 = Framed SPI support is disabled
bit 30
FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only)
1 = Frame sync pulse input (Slave mode)
0 = Frame sync pulse output (Master mode)
bit 29
FRMPOL: Frame Sync Polarity bit (Framed SPI mode only)
1 = Frame pulse is active-high
0 = Frame pulse is active-low
bit 28
MSSEN: Master Mode Slave Select Enable bit
1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in
Master mode. Polarity is determined by the FRMPOL bit.
0 = Slave select SPI support is disabled.
bit 27
FRMSYPW: Frame Sync Pulse Width bit
1 = Frame sync pulse is one character wide
0 = Frame sync pulse is one clock wide
bit 26-24 FRMCNT: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per
pulse. This bit is only valid in Framed mode.
111 = Reserved
110 = Reserved
101 = Generate a frame sync pulse on every 32 data characters
100 = Generate a frame sync pulse on every 16 data characters
011 = Generate a frame sync pulse on every 8 data characters
010 = Generate a frame sync pulse on every 4 data characters
001 = Generate a frame sync pulse on every 2 data characters
000 = Generate a frame sync pulse on every data character
bit 23
MCLKSEL: Master Clock Enable bit(1)
1 = REFCLKO1 is used by the Baud Rate Generator
0 = PBCLK2 is used by the Baud Rate Generator for SPI1 and SPI2
bit 22-18 Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
This bit can only be written when the ON bit = 0. Refer to 36.0 “Electrical Characteristics” for maximum
clock frequency requirements.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual
value of the CKP bit.
This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see
10.3 “Peripheral Pin Select (PPS)” for more information).
2019-2020 Microchip Technology Inc.
DS60001570C-page 249
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 17-1:
SPIxCON: SPI CONTROL REGISTER (CONTINUED)(X=1-2)
bit 17
SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only)
1 = Frame synchronization pulse coincides with the first bit clock
0 = Frame synchronization pulse precedes the first bit clock
ENHBUF: Enhanced Buffer Enable bit(1)
bit 16
1 = Enhanced Buffer mode is enabled
0 = Enhanced Buffer mode is disabled
bit 15
ON: SPI/I2S Module On bit
1 = SPI/I2S module is enabled
0 = SPI/I2S module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters in Idle mode
0 = Continue operation in Idle mode
bit 12
DISSDO: Disable SDOx pin bit(4)
1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register
0 = SDOx pin is controlled by the module
bit 11-10 MODE: 32/16-Bit Communication Select bits
When AUDEN = 1:
MODE32 MODE16 Communication
11 24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
10 32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
01 16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame
00 16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame
When AUDEN = 0:
MODE32 MODE16 Communication
1x 32-bit
01 16-bit
00 8-bit
SMP: SPI Data Input Sample Phase bit
Master mode (MSTEN = 1):
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode (MSTEN = 0):
SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.
CKE: SPI Clock Edge Select bit(2)
1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
SSEN: Slave Select Enable (Slave mode) bit
1 = SSx pin used for Slave mode
0 = SSx pin not used for Slave mode, pin controlled by port function.
CKP: Clock Polarity Select bit(3)
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 9
bit 8
bit 7
bit 6
Note 1:
2:
3:
4:
This bit can only be written when the ON bit = 0. Refer to 36.0 “Electrical Characteristics” for maximum
clock frequency requirements.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual
value of the CKP bit.
This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see
10.3 “Peripheral Pin Select (PPS)” for more information).
2019-2020 Microchip Technology Inc.
DS60001570C-page 250
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 17-1:
bit 5
SPIxCON: SPI CONTROL REGISTER (CONTINUED)(X=1-2)
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
DISSDI: Disable SDI bit(4)
1 = SDI pin is not used by the SPI module (pin is controlled by PORT function)
0 = SDI pin is controlled by the SPI module
STXISEL: SPI Transmit Buffer Empty Interrupt Mode bits
11 = Interrupt is generated when the buffer is not full (has one or more empty elements)
10 = Interrupt is generated when the buffer is empty by one-half or more
01 = Interrupt is generated when the buffer is completely empty
00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are
complete
SRXISEL: SPI Receive Buffer Full Interrupt Mode bits
11 = Interrupt is generated when the buffer is full
10 = Interrupt is generated when the buffer is full by one-half or more
01 = Interrupt is generated when the buffer is not empty
00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)
bit 4
bit 3-2
bit 1-0
Note 1:
2:
3:
4:
This bit can only be written when the ON bit = 0. Refer to 36.0 “Electrical Characteristics” for maximum
clock frequency requirements.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual
value of the CKP bit.
This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see
10.3 “Peripheral Pin Select (PPS)” for more information).
2019-2020 Microchip Technology Inc.
DS60001570C-page 251
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 17-2:
Bit
Range
31:24
23:16
15:8
7:0
SPIxCON2: SPI CONTROL REGISTER 2 (X=1-2)
Bit
31/23/15/7
Bit
Bit
30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
Bit
Bit
26/18/10/2 25/17/9/1 24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
SPISGNEXT
—
—
FRMERREN
SPIROVEN
R/W-0
U-0
U-0
U-0
R/W-0
U-0
AUDEN(1)
—
—
—
AUDMONO(1,2)
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
SPITUREN IGNROV
R/W-0
IGNTUR
R/W-0
AUDMOD(1,2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
SPISGNEXT: Sign Extend Read Data from the RX FIFO bit
1 = Data from RX FIFO is sign extended
0 = Data from RX FIFO is not sign extended
bit 14-13 Unimplemented: Read as ‘0’
bit 12
FRMERREN: Enable Interrupt Events via FRMERR bit
1 = Frame Error overflow generates error events
0 = Frame Error does not generate error events
bit 11
SPIROVEN: Enable Interrupt Events via SPIROV bit
1 = Receive overflow generates error events
0 = Receive overflow does not generate error events
bit 10
SPITUREN: Enable Interrupt Events via SPITUR bit
1 = Transmit Underrun Generates Error Events
0 = Transmit Underrun Does Not Generates Error Events
bit 9
IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions)
1 = A ROV is not a critical error; during ROV data in the FIFO is not overwritten by receive data
0 = A ROV is a critical error which stop SPI operation
bit 8
IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions)
1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty
0 = A TUR is a critical error which stop SPI operation
bit 7
AUDEN: Enable Audio CODEC Support bit(1)
1 = Audio protocol is enabled
0 = Audio protocol is disabled
bit 6-5
Unimplemented: Read as ‘0’
bit 3
AUDMONO: Transmit Audio Data Format bit(1,2)
1 = Audio data is mono (Each data word is transmitted on both left and right channels)
0 = Audio data is stereo
bit 2
Unimplemented: Read as ‘0’
bit 1-0
AUDMOD: Audio Protocol Mode bit(1,2)
11 = PCM/DSP mode
10 = Right Justified mode
01 = Left Justified mode
00 = I2S mode
Note 1:
2:
This bit can only be written when the ON bit = 0.
This bit is only valid for AUDEN = 1.
2019-2020 Microchip Technology Inc.
DS60001570C-page 252
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 17-3:
Bit
Range
31:24
23:16
15:8
7:0
SPIxSTAT: SPI STATUS REGISTER (X=1-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
R/C-0, HS
R-0, HS, HC
U-0
U-0
R-0
—
—
—
FRMERR
SPIBUSY
—
—
SPITUR
R-0, HS, HC
R/C-0, HS
R-1, HS, HC
U-0
R-1, HS, HC
U-0
R-0, HS, HC
R-0, HS, HC
SRMT
SPIROV
SPIRBE
—
SPITBE
—
SPITBF
SPIRBF
RXBUFELM
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
TXBUFELM
Legend:
HC = Cleared in hardware HS = Set in hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
C = Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 RXBUFELM: Receive Buffer Element Count bits (valid only when ENHBUF = 1)
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFELM: Transmit Buffer Element Count bits (valid only when ENHBUF = 1)
bit 15-13 Unimplemented: Read as ‘0’
bit 12
FRMERR: SPI Frame Error status bit
1 = Frame error is detected
0 = No Frame error is detected
This bit is only valid when FRMEN = 1.
bit 11
SPIBUSY: SPI Activity Status bit
1 = SPI peripheral is currently busy with some transactions
0 = SPI peripheral is currently idle
bit 10-9
Unimplemented: Read as ‘0’
bit 8
SPITUR: Transmit Under Run bit
1 = Transmit buffer has encountered an underrun condition
0 = Transmit buffer has no underrun condition
This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling
the module.
bit 7
SRMT: Shift Register Empty bit (valid only when ENHBUF = 1)
1 = When SPI module shift register is empty
0 = When SPI module shift register is not empty
bit 6
SPIROV: Receive Overflow Flag bit
1 = A new data is completely received and discarded. The user software has not read the previous data in
the SPIxBUF register.
0 = No overflow has occurred
This bit is set in hardware; can only be cleared (= 0) in software.
bit 5
SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1)
1 = RX FIFO is empty (CRPTR = SWPTR)
0 = RX FIFO is not empty (CRPTR SWPTR)
bit 4
Unimplemented: Read as ‘0’
2019-2020 Microchip Technology Inc.
DS60001570C-page 253
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 17-3:
SPIxSTAT: SPI STATUS REGISTER (X=1-2)
bit 3
SPITBE: SPI Transmit Buffer Empty Status bit
1 = Transmit buffer, SPIxTXB is empty
0 = Transmit buffer, SPIxTXB is not empty
Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR.
Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.
bit 2
Unimplemented: Read as ‘0’
bit 1
SPITBF: SPI Transmit Buffer Full Status bit
1 = Transmit not yet started, SPITXB is full
0 = Transmit buffer is not full
Standard Buffer Mode:
Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB.
Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR.
Enhanced Buffer Mode:
Set when CWPTR + 1 = SRPTR; cleared otherwise
bit 0
SPIRBF: SPI Receive Buffer Full Status bit
1 = Receive buffer, SPIxRXB is full
0 = Receive buffer, SPIxRXB is not full
Standard Buffer Mode:
Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer Mode:
Set when SWPTR + 1 = CRPTR; cleared otherwise
2019-2020 Microchip Technology Inc.
DS60001570C-page 254
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 17-4:
Bit Range
SPIxBUF: SPIx BUFFER REGISTER (x = 1-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
31:24
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
R/W-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATA
R/W-0
23:16
R/W-0
R/W-0
R/W-0
R/W-0
DATA
R/W-0
15:8
R/W-0
R/W-0
R/W-0
R/W-0
DATA
R/W-0
7:0
R/W-0
R/W-0
R/W-0
R/W-0
DATA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
DATA FIFO Data bits
When MODE32 or MODE16 selects 32-bit data, the SPI uses DATA.
When MODE32 or MODE16 selects 24-bit data, the SPI only uses DATA.
When MODE32 or MODE16 selects 16-bit data, the SPI only uses DATA.
When MODE32 or MODE16 selects 8-bit data, the SPI only uses DATA.
REGISTER 17-5:
Bit Range
x = Bit is unknown
SPIxBRG: SPIx BAUD RATE GENERATOR REGISTER (x= 1-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
R/W-0
—
—
—
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BRG
R/W-0
R/W-0
R/W-0
BRG
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13
Unimplemented: Read as ‘0’
bit 12-0
BRG Baud Rate Generator Divisor bits
Baud Rate = FPBCLKx / (2 * (SPIxBRG + 1)), where ‘x’ = 1, 2. Therefore, the maximum baud rate possible is FPBCLKx / 2 (SPIXBRG = 0) and the minimum baud rate possible is FPBCLKx / 16384.
Note:
Changing the BRG value when the ON bit is equal to ‘1’ causes undefined behavior.
2019-2020 Microchip Technology Inc.
DS60001570C-page 255
PIC32MK GPG/MCJ with CAN FD Family
NOTES:
2019-2020 Microchip Technology Inc.
DS60001570C-page 256
PIC32MK GPG/MCJ with CAN FD Family
18.0
Note:
INTER-INTEGRATED CIRCUIT
(I2C)
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 24. “InterIntegrated Circuit (I2C)” (DS60001116),
which is available from the Documentation
> Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The I2C module provides complete hardware support
for both Slave and Multi-Master modes of the I2C serial
communication standard.
Each I2C module offers the following key features:
• I2C interface supporting both master and slave
operation
• I2C Slave mode supports 7-bit and 10-bit addressing
• I2C Master mode supports 7-bit and 10-bit addressing
• I2C port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for the I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
• I2C supports multi-master operation; detects bus
collision and arbitrates accordingly
• Provides support for address bit masking
• SMBus support
Figure 18-1 illustrates the I2C module block diagram.
Each I2C module has a 2-pin interface:
• SCLx pin is clock
• SDAx pin is data
2019-2020 Microchip Technology Inc.
DS60001570C-page 257
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 18-1:
I2C BLOCK DIAGRAM
Internal
Data Bus
I2CxRCV
Read
SCLx
Shift
Clock
I2CxRSR
LSB
SDAx
Address Match
Match Detect
Write
I2CxMSK
Write
Read
I2CxADD
Read
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
Control Logic
I2CxSTAT
Collision
Detect
Read
Write
I2CxCON
Acknowledge
Generation
Read
Clock
Stretching
Write
I2CxTRN
LSB
Read
Shift Clock
Reload
Control
BRG Down Counter
Write
I2CxBRG
Read
I2C1-I2C2 = PBCLK2
DS60001570C-page 258
2019-2020 Microchip Technology Inc.
I2C Control Registers
Virtual Address
BF82_#
Register
Name(1)
TABLE 18-1:
6000
I2C1CON
6010
I2C1STAT
6020
I2C1ADD
6030
I2C1MSK
6040
I2C1BRG
6050
I2C1TRN
6060
I2C1RCV
I2C1 AND I2C2 REGISTER MAP
31/15
30/14
31:16
—
—
15:0
ON
—
31:16
—
—
15:0 ACKSTAT TRSTAT
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
31:16
—
—
15:0
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
28/12
27/11
26/10
25/9
24/8
23/7
22/6
—
SIDL
—
ACKTIM
—
—
—
—
—
—
SCLREL
—
—
—
—
—
—
—
—
STRICT
—
—
—
—
—
—
—
—
—
—
BCL
—
—
—
—
—
—
DISSLW
—
GCSTAT
—
—
SMEN
—
ADD10
—
—
GCEN
—
IWCOL
—
PCIE
STREN
—
I2COV
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Baud Rate Generator Register
—
—
—
—
—
—
—
—
—
—
—
—
21/5
20/4
19/3
SCIE
BOEN
SDAHT
ACKDT
ACKEN
RCEN
—
—
—
D/A
P
S
—
—
—
Address Register
—
—
—
Address Mask Register
—
—
—
—
—
—
—
Transmit Register
—
—
Receive Register
18/2
17/1
16/0
SBCDE
PEN
—
R/W
—
AHEN
RSEN
—
RBF
—
DHEN
SEN
—
TBF
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
—
—
—
—
—
—
—
—
—
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN 0000
15:0
ON
—
SIDL
SCLREL STRICT
—
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
6210 I2C2STAT
15:0 ACKSTAT TRSTAT ACKTIM
—
—
BCL
GCSTAT ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
6220 I2C2ADD
15:0
—
—
—
—
—
—
Address Register
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
6230 I2C2MSK
15:0
—
—
—
—
—
—
Address Mask Register
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
6240 I2C2BRG
15:0
Baud Rate Generator Register
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
6250 I2C2TRN
15:0
—
—
—
—
—
—
—
—
Transmit Register
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
6260 I2C2RCV
15:0
—
—
—
—
—
—
—
—
Receive Register
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:All registers in this table except I2CxRCV have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers”
for more information.
6200
I2C2CON
31:16
29/13
All Resets
Bit Range
Bits
DS60001570C-page 259
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
18.1
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 18-1:
Bit
Range
31:24
23:16
15:8
7:0
I2CXCON: I2C CONTROL REGISTER (X=1-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DHEN
—
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
R/W-0
U-0
R/W-0
R/W-1, HC
R/W-0
r-0
R/W-0
R/W-0
ON
—
SIDL
SCKREL
STRICT
—
DISSLW
SMEN
R/W-0
R/W-0
R/W-0
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
Legend:
R = Readable bit
-n = Value at POR
HC = Cleared in Hardware
r = Reserved bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-23 Unimplemented: Read as ‘0’
bit 22
PCIE: Stop Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
bit 21
SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
bit 20
BOEN: Buffer Overwrite Enable bit (I2C Slave mode only)
1 = I2CxRCV is updated and ACK is generated for a received address/data byte, ignoring the state of the
I2COV bit (I2CxSTAT)only if the RBF bit (I2CxSTAT) = 0
0 = I2CxRCV is only updated when the I2COV bit (I2CxSTAT) is clear
bit 19
SDAHT: SDA Hold Time Selection bit
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 18
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 17
AHEN: Address Hold Enable bit (Slave mode only)
1 = Following the 8th falling edge of SCL for a matching received address byte; SCKREL bit will be cleared
and the SCL will be held low.
0 = Address holding is disabled
bit 16
DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the SCKREL bit
and SCL is held low
0 = Data holding is disabled
bit 15
ON: I2C Enable bit
1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins
0 = Disables the I2C module; all I2C pins are controlled by PORT functions
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
DS60001570C-page 260
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 18-1:
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
I2CXCON: I2C CONTROL REGISTER (CONTINUED) (X=1-2)
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1 = Release SCLx clock
0 = Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at
beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
STRICT: Strict I2C Reserved Address Rule Enable bit
1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate
addresses in reserved address space.
0 = Strict I2C Reserved Address Rule not enabled
Reserved
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
SMEN: SMBus Input Levels bit
1 = Enable I/O pin thresholds compliant with SMBus specification
0 = Disable SMBus input thresholds
GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enable interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0 = General call address disabled
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1 = Send NACK during Acknowledge
0 = Send ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Hardware clear at end of master Acknowledge sequence.
0 = Acknowledge sequence not in progress
RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.
0 = Receive sequence not in progress
PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0 = Stop condition not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
master Repeated Start sequence.
0 = Repeated Start condition not in progress
SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0 = Start condition not in progress
2019-2020 Microchip Technology Inc.
DS60001570C-page 261
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 18-2:
Bit
Range
31:24
23:16
15:8
7:0
I2CXSTAT: I2C STATUS REGISTER (X=1-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0, HS, HC
R-0, HS, HC
R/C-0, HS, HC
U-0
U-0
R/C-0, HS
R-0, HS,HC
R-0, HS, HC
ACKSTAT
TRSTAT
ACKTIM
—
—
BCL
GCSTAT
ADD10
R/C-0, HS, SC
R/C-0, HS, SC
R-0, HS, HC
R/C-0, HS, HC
R/C-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
Legend:
HS = Hardware Set
HC = Hardware Cleared
SC = Software Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
C = Clearable bit
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ACKSTAT: Acknowledge Status bit
(when operating as I2C master, applicable to master transmit operation)
1 = NACK received from slave
0 = ACK received from slave
Hardware set or clear at end of slave Acknowledge.
bit 14
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.
bit 13
ACKTIM: Acknowledge Time Status bit (Valid in I2C Slave mode only)
1 = I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCL clock
0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCL clock
bit 12-11 Unimplemented: Read as ‘0’
bit 10
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware set at detection of bus collision.
bit 9
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware set when address matches general call address. Hardware clear at Stop detection.
bit 8
ADD10: 10-bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
bit 7
IWCOL: Write Collision Detect bit
1 = An attempt to write the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
bit 6
I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
DS60001570C-page 262
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 18-2:
I2CXSTAT: I2C STATUS REGISTER (CONTINUED)(X=1-2)
bit 5
D_A: Data/Address bit (when operating as I2C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of slave byte.
bit 4
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
bit 3
S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
bit 2
R_W: Read/Write Information bit (when operating as I2C slave)
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
Hardware set or clear after reception of I 2C device address byte.
bit 1
RBF: Receive Buffer Full Status bit
1 = Receive complete, I2CxRCV is full
0 = Receive not complete, I2CxRCV is empty
Hardware set when I2CxRCV is written with received byte. Hardware clear when software
reads I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.
2019-2020 Microchip Technology Inc.
DS60001570C-page 263
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 18-3:
Bit
Range
31:24
23:16
I2CXBRG: – I2C MODULE BAUDRATE REGISTER (X=1-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
15:8
I2CxBRG(1,2)
R/W-0
7:0
I2CxBRG(1,2)
Legend:
HS = Hardware Set
HC = Hardware Cleared
SC = Software Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
C = Clearable bit
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
I2CxBRG: I2C Baud Rate Generator Value bits(1,2)
These bits control the divider function of the Peripheral Clock.
EQUATION 18-1:
PBCLK
120 MHz
120 MHz
120 MHz
60MHz
60MHz
60MHz
EQUATION 18-2:
BAUD RATE GENERATOR RELOAD VALUE CALCULATION
FSCK
(Two Rollovers of I2CxBRG)
1000 kHz
400 kHz
100 kHz
1000 kHz
400 kHz
100 kHz
Calculated
I2CxBRG
0x0034
0x008E
0x0250
0x001A
0x0047
0x0128
SCK FREQUENCY
Note1: The value of these bits must not be changed when the I2C module is active. It is safe to change
the value when ON = 0, when idle or waiting in Master mode.
2: I2CxBRG values of 0x0 through 0x3 are expressly prohibited. Do not program the I2CxBRG register to any of these values, as indeterminate results may occur.
DS60001570C-page 264
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
19.0
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Note:
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 21. “Universal
Asynchronous Receiver Transmitter
(UART)” (DS60001107), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The UART module is one of the serial I/O modules
available in PIC32MK GPG/MCJ with CAN FD Family of devices. The UART is a full-duplex, asynchronous communication channel that communicates with
peripheral devices and personal computers through
protocols, such as RS-232, RS-485, LIN, and IrDA®.
The module also supports the hardware flow control
option, with UxCTS and UxRTS pins, and also
includes an IrDA encoder and decoder.
The following are key features of the UART module:
• Ability to receive data during Sleep mode
• Full-duplex, 8-bit or 9-bit data transmission
• Even, Odd, or No Parity options (for 8-bit data)
• One or two Stop bits
• Auto-baud support
• Four clock source inputs for asynchronous clocking
• Transmit and Receive (TX/RX) polarity control
• Hardware flow control option
• Fully integrated Baud Rate Generator (BRG) with
16-bit prescaler
• Baud rates up to 30 Mbps
• 8-level deep First-In-First-Out (FIFO) transmit data
buffer
• 8-level deep FIFO receive data buffer
• Parity, framing and buffer overrun error detection
• Support for interrupt-only on address detect
(ninth bit = 1)
• Separate transmit and receive interrupts
• Loopback mode for diagnostic support
• LIN Protocol support
• IrDA encoder and decoder with 16x baud clock
output for external IrDA encoder/decoder support
Figure 19-1 illustrates a simplified block diagram of the
UART module.
FIGURE 19-1:
UART SIMPLIFIED BLOCK DIAGRAM
REFCLK1
11
FRC
SYSCLK
10
01
PBCLKx(1)
00
Baud Rate Generator
IrDA®
CLKSEL
(UxMODE)
Hardware Flow Control
UxRTS/BCLKx
UxCTS
UxRX
UARTx Receiver
UARTx Transmitter
Note 1:
UxTX
‘x’ = 2 for UART1 and UART2.
2019-2020 Microchip Technology Inc.
DS60001570C-page 265
UART Control Registers
Virtual Address
BF82_#
TABLE 19-1:
8010
U1STA(1)
8020
U1TXREG
8030 U1RXREG
8040
U1BRG(1)
8200
U2MODE(1)
8210
U2STA(1)
8220
U2TXREG
8230 U2RXREG
(1)
U2BRG
Legend:
31/15
30/14
29/13
31:16
—
—
—
15:0
ON
—
SIDL
31:16
15:0
28/12
27/11
26/10
25/9
24/8
23/7
—
—
—
—
—
SLPEN
CKRDY
—
—
—
CLKSEL
RUNOV 0000
IREN
RTSMD
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL
STSEL
UEN
UTXISEL
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
19/3
18/2
17/1
16/0
URXISEL
—
—
ADDEN
—
PERR
FERR
OERR
URXDA 0110
—
—
—
—
—
—
—
—
Transmit Register
—
—
—
—
—
—
—
—
ON
—
SIDL
—
—
—
IREN
RTSMD
—
—
—
UEN
0000
—
—
U1BRG
SLPEN
CKRDY
—
—
—
CLKSEL
RUNOV 0000
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL
STSEL
0000
0000
ADDR
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
0000
—
ADDRMSK
UTXISEL
0000
0000
Receive Register
—
0000
0000
RIDLE
U1BRG
31:16
15:0
20/4
ADDR
15:0
15:0
21/5
ADDRMSK
31:16
31:16
15:0
22/6
All Resets
Register
Name
Bit Range
Bits
8000 U1MODE(1)
8240
UART1 AND UART2 REGISTER MAP
URXISEL
—
—
ADDEN
—
0000
RIDLE
PERR
FERR
OERR
URXDA 0110
—
—
—
—
—
—
—
—
Transmit Register
—
—
—
—
—
—
—
—
0000
0000
Receive Register
—
0000
0000
0000
BRG
BRG
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2019-2020 Microchip Technology Inc.
Note 1:This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more information.
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 266
19.1
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 19-1:
Bit
Range
31:24
23:16
15:8
7:0
UxMODE: UARTx MODE REGISTER (“X” = 1-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R-0, HS, HC
U-0
U-0
U-0
SLPEN
CLKRDY
—
—
—
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
ON
—
SIDL
IREN
RTSMD
—
R-0, HC
R/W-0
R/W-0, HC
R/W-0
R/W-0
R/W-0
WAKE
LPBACK
ABAUD
RXINV
BRGH
CLKSEL(1)
R/W-0
R/W-0
RUNOV
R/W-0
UEN(2)
R/W-0
PDSEL
Legend:
HS = Set by hardware
HC = cleared by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
R/W-0
STSEL
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23
SLPEN: Run During Sleep Enable bit
1 = BRG clock runs during Sleep mode
0 = BRG clock is turned off during Sleep mode
Note:
bit 22
SLPEN = 1 only applies if CLKSEL = FRC, or in some cases REFCLK depending on the
selected REFCLK input source if running while in Sleep mode.
CLKRDY: USART Clock Status bit
1 = UART clock is ready (User should not update the UxMODE register)
0 = UART clock is not ready (User can update the UxMODE register)
bit 21-19 Unimplemented: Read as ‘0’
bit 18-17 CLKSEL: UART Baud Rate Generator Clock Selection bits(1)
11 = BRG clock is REFCLK1
10 = BRG clock is FRC
01 = BRG clock is SYSCLK (off in Sleep mode)
00 = BRG clock is PBCLKx (off in Sleep mode)
bit 16
RUNOV: Run During Overflow Mode bit
1 = Shift register continues to run when Overflow (OERR) condition is detected
0 = Shift register stops accepting new data when Overflow (OERR) condition is detected
bit 15
ON: UARTx Enable bit
1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN and UTXEN
control bits
0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx
registers; UARTx power consumption is minimal
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation in Idle mode
bit 12
IREN: IrDA Encoder and Decoder Enable bit
1 = IrDA is enabled
0 = IrDA is disabled
Note 1:
2:
These bits can be changed only when the ON bit (UxMODE) is set to ‘0’.
These bits are present for legacy compatibility, and are superseded by PPS functionality on these devices
(see 10.3 “Peripheral Pin Select (PPS)” for more information).
2019-2020 Microchip Technology Inc.
DS60001570C-page 267
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 19-1:
UxMODE: UARTx MODE REGISTER (CONTINUED)(“X” = 1-2)
bit 11
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
bit 9-8
UEN: UARTx Enable bits(2)
11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by
corresponding bits in the PORTx register
bit 7
WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit
1 = Wake-up is enabled
0 = Wake-up is disabled
bit 6
LPBACK: UARTx Loopback Mode Select bit
1 = Loopback mode is enabled
0 = Loopback mode is disabled
bit 5
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next reception of Sync character (0x55); cleared by hardware
upon completion
0 = Baud rate measurement disabled or completed
bit 4
RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1 = High-Speed mode – 4x baud clock enabled
0 = Standard Speed mode – 16x baud clock enabled
bit 2-1
PDSEL: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0
STSEL: Stop Selection bit
1 = 2 Stop bits
0 = 1 Stop bit
Note 1:
2:
These bits can be changed only when the ON bit (UxMODE) is set to ‘0’.
These bits are present for legacy compatibility, and are superseded by PPS functionality on these devices
(see 10.3 “Peripheral Pin Select (PPS)” for more information).
Note:
DS60001570C-page 268
Only use BRGH = 1 for Baud rates ≥ 7.5MBPS.
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 19-2:
Bit
Range
31:24
23:16
15:8
7:0
UxSTA: UARTx STATUS AND CONTROL REGISTER (“X” = 1-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MASK
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR
R/W-0
R/W-0
UTXISEL
R/W-0
R/W-0
URXISEL
R/W-0
R/W-0
R/W-0, HC
R/W-0
R-0
R-1
UTXINV
URXEN
UTXBRK
UTXEN(1)
UTXBF
TRMT
R/W-0
R-1
R-0
R-0
R/W-0, HS
R-0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
Legend:
HS = Set by hardware
HC = cleared by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 MASK: Address Match Mask bits
These bits are used to mask the ADDR bits.
11111111 = Corresponding matching ADDR bits are used to detect the address match
Note:
This setting allows the user to assign individual address as well as a group broadcast address
to a UART.
00000000 = Corresponding ADDRx bits are not used to detect the address match.
See 19.2 “UART Broadcast Mode Example” for additional information.
bit 23-16 ADDR: Automatic Address Mask bits
1 = Corresponding MASKx bits are used to detect the address match.
Note:
This setting allows the user to assign individual address as well as a group broadcast address
to a UART.
0 = Corresponding MASKx bits are not used to detect the address match.
See 19.2 “UART Broadcast Mode Example” for additional information.
bit 15-14 UTXISEL: TX Interrupt Mode Selection bits
11 = Reserved, do not use
10 = Interrupt is generated and asserted while the transmit buffer is empty
01 = Interrupt is generated and asserted when all characters have been transmitted
00 =Interrupt is generated and asserted while the transmit buffer contains at least one empty space
bit 13
UTXINV: Transmit Polarity Inversion bit
If IrDA mode is disabled (i.e., IREN (UxMODE) is ‘0’):
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IrDA mode is enabled (i.e., IREN (UxMODE) is ‘1’):
1 = IrDA encoded UxTX Idle state is ‘1’
0 = IrDA encoded UxTX Idle state is ‘0’
bit 12
URXEN: Receiver Enable bit
1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON bit (UxMODE) = 1)
0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module and released to the PORT
Note:
Note 1:
The event of disabling an enabled receiver will release the RX pin to the PORT function;
however, the receive buffers will not be reset. Disabling the receiver has no effect on the receive
status flags.
This bit should not be enabled until after the ON bit (UxMODE) = 1. If TX interrupts are enabled, setting this bit will immediately cause a TX interrupt based on the value of the UTXISEL bit.
2019-2020 Microchip Technology Inc.
DS60001570C-page 269
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 19-2:
UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)(“X” = 1-2)
bit 11
UTXBRK: Transmit Break bit
1 = Send Break on next transmission. Start bit followed by twelve ‘0’ bits, followed by Stop bit; cleared by
hardware upon completion
0 = Break transmission is disabled or completed
bit 10
UTXEN: Transmit Enable bit(1)
1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON bit (UxMODE) = 1)
0 = UARTx transmitter is disabled
The event of disabling an enabled transmitter will release the TX pin to the PORT function and reset the
transmit buffers to empty. Any pending transmission is aborted and data characters in the transmit buffers
are lost. All transmit status flags are cleared and the TRMT bit is set.
bit 9
UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register is Empty bit (read-only)
1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
bit 7-6
URXISEL: Receive Interrupt Mode Selection bit
11 = Reserved
10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full
01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full
00 =Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character)
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect
0 = Address Detect mode is disabled
bit 4
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Data is being received
bit 3
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character
0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character
0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit.
When RUNOV = 0, clearing a previously set OERR bit will clear and reset the receive buffer and shift
register.
When RUNOV = 1, Clearing a previously set OERR bit will NOT reset the receive buffer and shift register
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed
bit 0
URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
Note 1:
This bit should not be enabled until after the ON bit (UxMODE) = 1. If TX interrupts are enabled, setting this bit will immediately cause a TX interrupt based on the value of the UTXISEL bit.
DS60001570C-page 270
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 19-3:
Bit
Range
31:24
23:16
15:8
7:0
UxRXREG: UARTx RECEIVE REGISTER (“X” = 1-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
RX
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
RX
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-9
Unimplemented: Read as ‘0’
bit 8
RX: Data bit 8 of the received character (in 9-bit mode)
bit 7-0
RX: Data bits 7-0 of the received character
REGISTER 19-4:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
UxTXREG: UARTx TRANSMIT REGISTER (“X” = 1-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-x
U-x
U-x
U-x
U-x
U-x
U-x
U-x
—
—
—
—
—
—
—
—
U-x
U-x
U-x
U-x
U-x
U-x
U-x
U-x
—
—
—
—
—
—
—
—
U-x
U-x
U-x
U-x
U-x
U-x
U-x
W-x
—
—
—
—
—
—
—
TX
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
TX
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-9
Unimplemented: Read as initialized data
bit 8
TX: Data bit 8 of the transmitted character (in 9-bit mode)
bit 7-0
TX: Data bits 7-0 of the transmitted character
2019-2020 Microchip Technology Inc.
x = Bit is unknown
DS60001570C-page 271
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 19-5:
Bit
Range
UxBRG: UARTx BAUD RATE GENERATOR REGISTER (“X” = 1-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BRG
BRG
7:0
R/W-0
BRG
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-20 Unimplemented: Read as ‘0’
bit 19-0
BRG: Baud Rate Generator Divisor bits
Note:
TABLE 19-2:
The UxBRG register cannot be changed while UARTx is enabled (ON bit (UxMODE) = 1)).
UART BAUD RATE CALCULATIONS
UART Baud Rate With
UxBRG Equals
BRGH = 0
UxBRG = ((CLKSEL Frequency / (16 * Desired Baud Rate)) – 1)
BRGH = 1
UxBRG = ((CLKSEL Frequency / (4 * Desired Baud Rate)) – 1)
Note:
UART1 and UART2 on PBCLK2.
DS60001570C-page 272
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
19.2
UART Broadcast Mode Example
To send a broadcast message to all UARTs in the group
identified by bit 7 = 1, send UxTXREG = (0x190),
address bit 9 set. All the UARTs in that group, bit 7 = 1,
would generate an interrupt for an address match
because of the bit , match, Logic AND of
MASK and ADDR registers equal “true”. User software
would check if bit 4 = 1, and if true, the RX bits
register value is valid for all UARTS.
As shown in Table 19-3, the group hardware address
identifier bit was arbitrarily chosen as bit 7 with bit 4
chosen as the software group or individual UART target
ID. Therefore, the collective group address assigned
for all UARTs (i.e, [w, x, y, z]) is ‘0b100100xx, while
the individual addresses are ‘0b10000000 through
‘0b10000011, respectively.
To send a specific message to UARTy within the group,
the user would send UxTXREG = (0x182), address bit
9 set. All of the UARTs in that group identified with bit 7
= 1 would still generate an interrupt for an address
match because of the bit , address match,
Logic AND of MASK and ADDR registers equal True. In
this case, user software would check if bit 4 = 0, and if
true, the RX bits register value would be intended
only for UARTy, with all others ignored.
Any MASK register bit = 0 means the corresponding
ADDR bit is a “don't care” from a hardware
address matching point of view. Using this scheme,
multiple UART subnet groups could be created within a
network. If not using address match with a broadcast
mode, set the ADDRMSK bits (UxSTAT Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The RTCC module is intended for applications in which
accurate time must be maintained for extended periods
of time with minimal or no CPU intervention. Lowpower optimization provides extended battery lifetime
while keeping track of time.
The following are key features of the RTCC module:
• Time: hours, minutes and seconds
FIGURE 22-1:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
24-hour format (military time)
Visibility of one-half second period
Provides calendar: Weekday, date, month and year
Alarm intervals are configurable for half of a second,
one second, 10 seconds, one minute, 10 minutes,
one hour, one day, one week, one month, and one
year
Alarm repeat with decrementing counter
Alarm with indefinite repeat: Chime
Year range: 2000 to 2099
Leap year correction
BCD format for smaller firmware overhead
Optimized for long-term battery operation
Fractional second synchronization
User calibration of the clock crystal frequency with
auto-adjust
Calibration range: 0.66 seconds error per month
Calibrates up to 260 ppm of crystal error
Uses external 32.768 kHz crystal or 32 kHz
internal oscillator
Alarm pulse, seconds clock, or internal clock output
on RTCC pin
RTCC BLOCK DIAGRAM
RTCCLKSEL
32.768 kHz Input from
Secondary Oscillator (SOSC)
32 kHz Input from
Internal Oscillator (LPRC)
TRTC
RTCC Prescalers
0.5 seconds
RTCC Timer
Alarm
Event
YEAR, MTH, DAY
RTCVAL
WKDAY
HR, MIN, SEC
Comparator
MTH, DAY
Compare Registers
with Masks
ALRMVAL
WKDAY
HR, MIN, SEC
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
Seconds Pulse
TRTC
RTCC Pin
RTCOE
RTCOUTSEL
2019-2020 Microchip Technology Inc.
DS60001570C-page 291
RTCC Control Registers
Register
Name(1)
Bit Range
RTCC REGISTER MAP
Virtual Address
(BF8C_#)
TABLE 22-1:
0000
RTCCON
31:16
15:0
31/15
30/14
29/13
28/12
27/11
—
ON
—
—
—
SIDL
—
—
—
—
—
CHIME
—
PIV
—
ALRMSYNC
—
0010 RTCALRM
31:16
—
15:0 ALRMEN
0020 RTCTIME
31:16
15:0
HR10
SEC10
0030 RTCDATE
31:16
15:0
0040 ALRMTIME
31:16
15:0
0050 ALRMDATE
31:16
15:0
Legend:
Note 1:
—
26/10
25/9
24/8
23/7
22/6
—
RTCCLKSEL RTCOUTSEL RTCCLKON
CAL
—
—
—
HR01
SEC01
—
MIN10
—
—
—
YEAR10
DAY10
YEAR01
DAY01
—
MONTH10
—
—
—
HR10
SEC10
HR01
SEC01
—
MIN10
—
—
—
—
MONTH10
—
—
—
—
—
—
—
DAY01
—
20/4
—
—
—
DAY10
—
—
AMASK
21/5
—
—
19/3
18/2
17/1
16/0
RTCWREN RTCSYNC HALFSEC RTCOE
—
—
ARPT
—
—
—
—
MIN01
—
—
—
MONTH01
WDAY01
—
MIN01
—
—
MONTH01
WDAY01
All Resets
Bits
0000
0000
0000
0000
xxxx
xx00
xxxx
xx00
—
xxxx
xx00
00xx
xx0x
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 292
22.1
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 22-1:
Bit
Range
Bit
31/23/15/7
23:16
Bit
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
CAL
CAL
15:8
7:0
RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
ON(1)
—
SIDL
—
—
RTCCLKSEL
R/W-0
R-0
U-0
U-0
R/W-0
R-0
R-0
R/W-0
—
—
RTC
WREN(3)
RTC
SYNC
HALFSEC(4)
RTCOE
RTC
RTC
OUTSEL(2) CLKON(5)
RTC
OUTSEL(2)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25-16 CAL: Real-Time Clock Drift Calibration bits, which contain a signed 10-bit integer value
0111111111 = Maximum positive adjustment, adds 511 real-time clock pulses every one minute
•
•
•
0000000001 = Minimum positive adjustment, adds 1 real-time clock pulse every one minute
0000000000 = No adjustment
1111111111 = Minimum negative adjustment, subtracts 1 real-time clock pulse every one minute
•
•
•
1000000000 = Maximum negative adjustment, subtracts 512 real-time clock pulses every one minute
bit 15
ON: RTCC On bit(1)
1 = RTCC module is enabled
0 = RTCC module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Disables RTCC operation when CPU enters Idle mode
0 = Continue normal operation when CPU enters Idle mode
bit 12-11 Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
5:
Note:
The ON bit is only writable after RTCWREN = 1.
Requires RTCOE = 1 (RTCCON) for the output to be active.
The RTCWREN bit can be set only when the write sequence is enabled.
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME).
This bit is undefined when RTCCLKSEL = 00 (LPRC is the clock source).
This register is reset only on a POR.
2019-2020 Microchip Technology Inc.
DS60001570C-page 293
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 22-1:
RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER
(CONTINUED)
bit 10-9
RTCCLKSEL: RTCC Clock Select bits
When a new value is written to these bits, the Seconds Value register should also be written to properly
reset the clock prescalers in the RTCC.
11 = Reserved
10 = Reserved
01 = RTCC uses the external 32.768 kHz Secondary Oscillator (SOSC)
00 = RTCC uses the internal 32 kHz oscillator (LPRC)
bit 8-7
RTCOUTSEL: RTCC Output Data Select bits(2)
11 = Reserved
10 = RTCC Clock is presented on the RTCC pin
01 = Seconds Clock is presented on the RTCC pin
00 = Alarm Pulse is presented on the RTCC pin when the alarm interrupt is triggered
bit 6
RTCCLKON: RTCC Clock Enable Status bit(5)
1 = RTCC Clock is actively running
0 = RTCC Clock is not running
bit 5-4
Unimplemented: Read as ‘0’
bit 3
RTCWREN: Real-Time Clock Value Registers Write Enable bit(3)
1 = Real-Time Clock Value registers can be written to by the user
0 = Real-Time Clock Value registers are locked out from being written to by the user
bit 2
RTCSYNC: Real-Time Clock Value Registers Read Synchronization bit
1 = Real-time clock value registers can change while reading (due to a rollover ripple that results in an invalid
data read). If the register is read twice and results in the same data, the data can be assumed to be valid.
0 = Real-time clock value registers can be read without concern about a rollover ripple
bit 1
HALFSEC: Half-Second Status bit(4)
1 = Second half period of a second
0 = First half period of a second
bit 0
RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is not enabled
Note 1:
2:
3:
4:
5:
The ON bit is only writable after RTCWREN = 1.
Requires RTCOE = 1 (RTCCON) for the output to be active.
The RTCWREN bit can be set only when the write sequence is enabled.
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME).
This bit is undefined when RTCCLKSEL = 00 (LPRC is the clock source).
Note:
This register is reset only on a POR.
DS60001570C-page 294
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 22-2:
Bit
Range
31:24
23:16
15:8
7:0
RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R-0
ALRMEN(1,2)
CHIME(2)
R/W-0
(2)
R/W-0
R/W-0
PIV
Bit
Bit
27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
(2)
R/W-0
R/W-0
R/W-0
ALRMSYNC
R/W-0
AMASK
R/W-0
R/W-0
R/W-0
ARPT(2)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ALRMEN: Alarm Enable bit(1,2)
1 = Alarm is enabled
0 = Alarm is disabled
bit 14
CHIME: Chime Enable bit(2)
1 = Chime is enabled – ARPT is allowed to rollover from 0x00 to 0xFF
0 = Chime is disabled – ARPT stops once it reaches 0x00
bit 13
PIV: Alarm Pulse Initial Value bit(2)
When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse.
When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.
bit 12
ALRMSYNC: Alarm Sync bit
1 = ARPT and ALRMEN may change as a result of a half second rollover during a read.
The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple
bits may be changing.
0 = ARPT and ALRMEN can be read without concerns of rollover because the prescaler is more than
32 real-time clocks away from a half-second rollover
bit 11-8
AMASK: Alarm Mask Configuration bits(2)
0000 = Every half-second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29, once every four years)
1010 = Reserved
1011 = Reserved
11xx = Reserved
Note 1:
Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT = 00 and
CHIME = 0.
This field should not be written when the RTCC ON bit = ‘1’ (RTCCON) and ALRMSYNC = 1.
2:
Note:
The RTCALRM register is reset on a MCLR or Power-on Reset (POR).
2019-2020 Microchip Technology Inc.
DS60001570C-page 295
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 22-2:
RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER (CONTINUED)
ARPT: Alarm Repeat Counter Value bits(2)
11111111 =Alarm will trigger 256 times
bit 7-0
•
•
•
00000000 =Alarm will trigger one time
The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.
Note 1:
2:
Note:
Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT = 00 and
CHIME = 0.
This field should not be written when the RTCC ON bit = ‘1’ (RTCCON) and ALRMSYNC = 1.
The RTCALRM register is reset on a MCLR or Power-on Reset (POR).
DS60001570C-page 296
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 22-3:
Bit
Range
31:24
23:16
15:8
7:0
RTCTIME: REAL-TIME CLOCK TIME VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
HR10
R/W-x
R/W-x
HR01
R/W-x
R/W-x
R/W-x
R/W-x
MIN10
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MIN01
R/W-x
R/W-x
R/W-x
SEC10
R/W-x
R/W-x
SEC01
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 HR10: Binary-Coded Decimal Value of Hours bits, 10 digits; contains a value from 0 to 2
bit 27-24 HR01: Binary-Coded Decimal Value of Hours bits, 1 digit; contains a value from 0 to 9
bit 23-20 MIN10: Binary-Coded Decimal Value of Minutes bits, 10 digits; contains a value from 0 to 5
bit 19-16 MIN01: Binary-Coded Decimal Value of Minutes bits, 1 digit; contains a value from 0 to 9
bit 15-12 SEC10: Binary-Coded Decimal Value of Seconds bits, 10 digits; contains a value from 0 to 5
bit 11-8
SEC01: Binary-Coded Decimal Value of Seconds bits, 1 digit; contains a value from 0 to 9
bit 7-0
Unimplemented: Read as ‘0’
Note:
This register is only writable when RTCWREN = 1 (RTCCON).
2019-2020 Microchip Technology Inc.
DS60001570C-page 297
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 22-4:
Bit
Range
31:24
23:16
15:8
7:0
RTCDATE: REAL-TIME CLOCK DATE VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
YEAR10
R/W-x
YEAR01
MONTH10
R/W-x
R/W-x
U-0
U-0
—
—
R/W-x
R/W-x
R/W-x
MONTH01
R/W-x
R/W-x
R/W-x
U-0
U-0
R/W-x
R/W-x
—
—
DAY10
R/W-x
R/W-x
DAY01
R/W-x
R/W-x
WDAY01
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 YEAR10: Binary-Coded Decimal Value of Years bits, 10 digits
bit 27-24 YEAR01: Binary-Coded Decimal Value of Years bits, 1 digit
bit 23-20 MONTH10: Binary-Coded Decimal Value of Months bits, 10 digits; contains a value from 0 to 1
bit 19-16 MONTH01: Binary-Coded Decimal Value of Months bits, 1 digit; contains a value from 0 to 9
bit 15-12 DAY10: Binary-Coded Decimal Value of Days bits, 10 digits; contains a value from 0 to 3
bit 11-8
DAY01: Binary-Coded Decimal Value of Days bits, 1 digit; contains a value from 0 to 9
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
WDAY01: Binary-Coded Decimal Value of Weekdays bits,1 digit; contains a value from 0 to 6
Note:
This register is only writable when RTCWREN = 1 (RTCCON).
DS60001570C-page 298
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 22-5:
Bit
Range
31:24
23:16
15:8
7:0
ALRMTIME: ALARM TIME VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
HR10
R/W-x
R/W-x
HR01
R/W-x
R/W-x
R/W-x
R/W-x
MIN10
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MIN01
R/W-x
R/W-x
R/W-x
SEC10
R/W-x
R/W-x
SEC01
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 HR10: Binary Coded Decimal value of hours bits, 10 digits; contains a value from 0 to 2
bit 27-24 HR01: Binary Coded Decimal value of hours bits, 1 digit; contains a value from 0 to 9
bit 23-20 MIN10: Binary Coded Decimal value of minutes bits, 10 digits; contains a value from 0 to 5
bit 19-16 MIN01: Binary Coded Decimal value of minutes bits, 1 digit; contains a value from 0 to 9
bit 15-12 SEC10: Binary Coded Decimal value of seconds bits, 10 digits; contains a value from 0 to 5
bit 11-8
SEC01: Binary Coded Decimal value of seconds bits, 1 digit; contains a value from 0 to 9
bit 7-0
Unimplemented: Read as ‘0’
2019-2020 Microchip Technology Inc.
DS60001570C-page 299
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 22-6:
Bit
Range
31:24
23:16
15:8
7:0
ALRMDATE: ALARM DATE VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
U-0
U-0
Bit
Bit
27/19/11/3 26/18/10/2
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
U-0
U-0
U-0
U-0
R/W-x
R/W-x
—
—
—
—
MONTH10
R/W-x
MONTH01
DAY10
R/W-x
R/W-x
DAY01
R/W-x
R/W-x
WDAY01
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-20 MONTH10: Binary Coded Decimal value of months bits, 10 digits; contains a value from 0 to 1
bit 19-16 MONTH01: Binary Coded Decimal value of months bits, 1 digit; contains a value from 0 to 9
bit 15-12 DAY10: Binary Coded Decimal value of days bits, 10 digits; contains a value from 0 to 3
bit 11-8
DAY01: Binary Coded Decimal value of days bits, 1 digit; contains a value from 0 to 9
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
WDAY01: Binary Coded Decimal value of weekdays bits, 1 digit; contains a value from 0 to 6
DS60001570C-page 300
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
23.0
Note:
12-BIT HIGH-SPEED
SUCCESSIVE APPROXIMATION
REGISTER (SAR) ANALOG-TODIGITAL CONVERTER (ADC)
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 22. “12-bit HighSpeed
Successive Approximation
Register
(SAR)
Analog-to-Digital
Converter (ADC)” (DS60001344) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
The 12-bit High-Speed Successive Approximation
Register (SAR) analog-to-digital converter (ADC)
includes the following features:
• 12-bit resolution
• Seven ADC modules with dedicated Sample and
Hold (S&H) circuits
• Up to 6 dedicated class1 ADC modules can be
combined using an interleave technique to provide conversion rates up to 20 msps, refer to
Application Note: "AN2785_World's Fastest
Embedded Interleaved 12- bit ADC Using
PIC32MZ and PIC32MK Families".
• Up to 45 analog input sources, in addition to the
internal CTMU, internal voltage reference and
internal temperature sensor
• Single-ended and/or differential inputs
• Supports touch sense applications
• Four digital comparators
• Four digital filters supporting two modes:
- Oversampling mode
- Averaging mode
• Early interrupt generation resulting in faster
processing of converted data
• Designed for power conversion and general
purpose applications
• Operation during Sleep and Idle modes
A simplified block diagram of the ADC module is
illustrated in Figure 23-1.
The 12-bit HS SAR ADC has up to six dedicated
ADC modules (ADC0-ADC5) and one shared ADC
module (ADC7). The dedicated ADC modules use a
single input (or its alternate) and are intended for
high-speed and precise sampling of time-sensitive or
transient inputs. The shared ADC module
incorporates a multiplexer on the input to facilitate a
larger group of inputs, with slower sampling, and
provides flexible automated scanning option through
the input scan logic.
2019-2020 Microchip Technology Inc.
For each ADC module, the analog inputs are
connected to the S&H capacitor. The clock, sampling
time, and output data resolution for each ADC
module can be set independently. The ADC module
performs the conversion of the input analog signal
based on the configurations set in the registers.
When conversion is complete, the final result is
stored in the result buffer for the specific analog
input and is passed to the digital filter and digital
comparator if configured to use data from this
particular sample. Input to ADCx mapping is
illustrated in Figure 23-2.
23.1
Activation Sequence
The following ADCx activation sequence is to be
followed at all times:
Step 1: Initialize the ADC calibration values by
copying them from the factory programmed
DEVADCx Flash locations starting at 0xBFC45000
into the ADCxCFG registers starting at 0xBF887D00,
respectively.
Then, configure the AICPMPEN bit (ADCCON1
and the IOANCPEN bit (CFGCON) = 1 if and
only if VDD is less than 2.5V. The default is ‘0’, which
assumes VDD is greater than or equal to 2.5V.
Step 2: The user writes all the essential ADC
configuration SFRs including the ADC control clock
and all ADC core clocks setup:
• ADCCON1, keeping the ON bit = 0
• ADCCON2, especially paying attention to
ADCDIV and SAMC
• ADCANCON, keeping all analog enables ANENx
bit = 0, WKUPCLKCNT bit = 0xA
• ADCCON3, keeping all DIGEN5x = 0, especially
paying attention to ADCSEL, CONCLKDIV
, and VREFSEL
• ADCxTIME, ADCDIVx, and SAMCx
• ADCTRGMODE, ADCIMCONx, ADCTRGSNS,
ADCCSSx, ADCGIRQENx, ADCTRGx, ADCBASE
• Comparators, Filters, etc.
Step 3: The user sets the ANENx bit to ‘1’ for the ADC
SAR Cores needed (which internally in the ADC module enables the control clock to generate by division the
core clocks for the desired ADC SAR Cores, which in
turn enables the bias circuitry for these ADC SAR
Cores).
Step 4: The user sets the ON bit to ‘1’, which enables
the ADC control clock.
Step 5: The user waits for the interrupt/polls the
BGVRRDY bit (ADCCON2) and the WKRDYx
bit (ADCANCON) = 1, which signals that
the device analog environment (band gap and VREF)
is ready.
DS60001570C-page 301
PIC32MK GPG/MCJ with CAN FD Family
Step 6: Set the DIGENx bit (ADCCON3) to
‘1’, which enables the digital circuitry to immediately
begin processing incoming triggers to perform data
conversions.
Note:
Do not activate ADC trigger sources until ADC has
been completely initialized, enabled, and warm up
time complete.
Note:
For the best optimized CPU and ISR performance the user should refer to Table 61. The CPU interrupt latency is ~43
SYSCLK cycles if no other interrupts are
pending. If not using ADC DMA and the
ADC combined sum throughput rate of all
the ADC modules in use is greater than
(SYSCLK / 43) = 2.8 Msps, it is recommended to use the ADC CPU early interrupt generation, defined in the ADCxTIME
and ADCEIENx registers. This will reduce
the probability of the ADC results being
overwritten by the next conversion before
the CPU can read the previous ADC
result(s).
Do not use the early interrupts if using the
ADC in the DMA module.
TABLE 23-1:
If using ADC DMA, ADC source clock must
be SYSCLK only.
Non-interleaved Dedicated Class_1 ADCx Throughput
rate
= 1/((Sample time + Conversion time)(TAD))
= 1 / ((SAMC+# bit resolution+1)(TAD))
For example:
SAMC = 3 TAD, 12-bit mode, TAD = 16.667 ns = 60
MHz
Throughput rate:
= 1 /((3+12+1)(16.667 ns))
= 1/(16 * 16.667 ns)
= 3.75 msps
PIC32MKXXX BASED ON 60 MHZ TAD CLOCK (16.667 ns)
Number of
Interleaved ADCs
Used
12-bit (Max) Msps
10-bit (Max) Msps
8-bit (Max) Msps
6-bit (Max) Msps
1
3.75
4.286
5.0
6.0
2
7.50
8.571
10.00
12.00
3
10.00
12.00
15.00
15.00
4
15.00
17.1429
20.00
24.00
5
15.00
20.00
20.00
30.00
(2)
20.00
24.00
30.00
30.00
6
Note 1:
2:
Interleaved ADCs in this context means connecting the same analog source signal to multiple dedicated
Class_1 ADCs (that is, ADC0-ADC5), and using independent staggered trigger sources accordingly for
each interleaved ADC.
Only available in the Motor Control Variant, that is, PIC32MKXXMCXX.
DS60001570C-page 302
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 23-1:
ADC BLOCK DIAGRAM
AN0
AN3
AN5
AN24
00
01
10
11
VREF+
VREF-
11
ADCSEL
01
00
CONCLKDIV
VREFSEL
1
0
VREFH
DIFF0
(ADCIMCON1)
VREFL
TAD0-TAD5
ADCDIV
(ADCxTIME)
TQ
ADC0
TAD7
AN5
AN2
AN6
AN25
10
TCLK
SH0ALT
(ADCTRGMODE)
AN6
VREFL
AVSS
AVDD
ADCDIV
(ADCCON2)
00
01
10
11
SH4ALT
(ADCTRGMODE)
AN11
VREFL
1
0
ADC5
DIFF4
(ADCIMCON1)
AN6
CTMU
AN38
IVREF (1.2V)
AN 9
ADC7
AN1
VREFL
1
0
DIFFx
x = 6 to 4
ADCDATA0
…...
ADCDATA
Digital Comparator
Data
Interrupt/Event
Triggers,
Scan Control
Logic
Trigger
Capacitive Voltage
Divider (CVD)
Status and Control
Registers
2019-2020 Microchip Technology Inc.
Interrupt/Event
System Bus
Digital Filter
Interrupt
DS60001570C-page 303
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 23-2:
S&H BLOCK DIAGRAM
AN0
AN3
AN0
AN3
AN8
AN5
AN26
AN24
SH0ALT
SH3ALT
AN6
AN27
DIFF
DIFF
Dedicated ADC3
AN4
AN1
AN1
AN4
AN9
AN7
AN0
AN0
SH4ALT
Dedicated ADC0
SH1ALT
AN10
AN7
DIFF
DIFF
Dedicated ADC4
Dedicated ADC1
AN5
AN2
AN2
AN5
AN6
AN6
AN25
AN25
SH2ALT
SH5ALT
AN8
AN11
DIFF
DIFF
Dedicated ADC5
Dedicated ADC2
AN53(1)
AN50 (1)
CTMU_IOUT
ADC Party Line
AN1
,VREF
(1.2V)
CTMU
Temperature
Sensor
DIFF
Shared ADC7
Note 1: AN50 and AN53 are internal analog input sources.
DS60001570C-page 304
2019-2020 Microchip Technology Inc.
ADC Control Registers
7000 ADCCON1
7010 ADCCON2
Bits
31/15
30/14
31:16
—
—
15:0
ON
—
SIDL
REFFLT
EOSRDY
31:16 BGVRRDY
29/13
31:16
EOSIEN
—
26/10
25/9
24/8
—
CVDEN
FSSCLKEN FSPBCLKEN
FRACT
—
22/6
ADCEIOVR
TRGSUSP
—
UPDIEN
21/5
20/4
19/3
SELRES
—
18/2
17/1
16/0
—
—
STRGSRC
IRQVS
STRGLVL
—
0600
SAMC
ADCEIS
UPDRDY
SAMP
ADCDIV
—
DIGEN5
DIGEN4
RQCNVRT GLSWTRG GSWTRG
DIGEN1
DIGEN0
ADINSEL
—
15:0
—
—
STRGEN5
STRGEN4
STRGEN3
STRGEN2
STRGEN1
STRGEN0
—
—
31:16
DIFF15
SIGN15
DIFF14
SIGN14
DIFF13
SIGN13
DIFF12
SIGN12
DIFF11
SIGN11
DIFF10
SIGN10
DIFF9
SIGN9
DIFF8
SIGN8
0000
15:0
DIFF7
SIGN7
DIFF6
SIGN6
DIFF5
SIGN5
DIFF4
SIGN4
DIFF3
SIGN3
DIFF2
SIGN2
DIFF1
SIGN1
DIFF0
SIGN0
0000
31:16
—
—
—
—
—
—
—
—
DIFF27
SIGN27
DIFF26
SIGN26
DIFF25
SIGN25
DIFF24
SIGN24
0000
15:0
DIFF23(1)
SIGN23(1)
DIFF22(1)
SIGN22(1)
DIFF21(1)
SIGN21(1)
DIFF20(1)
SIGN20(1)
DIFF19
SIGN19
DIFF18
SIGN18
DIFF17
SIGN17
DIFF16
SIGN16
0000
7060 ADCIMCON3
31:16 DIFF47(1)
SIGN47(1)
DIFF46(1)
SIGN46(1)
DIFF45(1)
SIGN45(1)
—
—
—
—
—
—
DIFF41(1)
SIGN41(1)
DIFF40(1)
15:0
DIFF39(1)
SIGN39(1)
DIFF38(1)
SIGN38(1)
DIFF37(1)
SIGN37(1)
DIFF36(1)
SIGN36(1)
DIFF35(1)
SIGN35(1)
DIFF34(1)
SIGN34(1)
DIFF33(1)
SIGN33(1)
—
—
0000
7070 ADCIMCON4
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
DIFF49
SIGN49
DIFF48
SIGN48
0000
7080 ADCGIRQEN1
31:16
—
—
—
—
AGIEN27
AGIEN26
AGIEN25
AGIEN24
AGIEN19
AGIEN18
AGIEN17
15:0
AGIEN15
AGIEN14
AGIEN13
AGIEN12
AGIEN11
AGIEN10
AGIEN9
AGIEN8
AGIEN7
AGIEN6
AGIEN5
AGIEN4
AGIEN3
AGIEN2
AGIEN1
7090 ADCGIRQEN2
31:16
—
—
—
—
—
—
—
—
—
—
AGIEN53(2)
—
—
15:0 AGIEN47(1) AGIEN46(1) AGIEN45(1)
—
—
—
70A0 ADCCSS1
31:16
—
—
—
—
CSS27
CSS26
CSS25
CSS24
CSS23(1)
CSS22(1)
CSS21(1)
CSS20(1)
CSS19
CSS18
CSS17
CSS16
0000
15:0
CSS15
CSS14
CSS13
CSS12
CSS11
CSS10
CSS9
CSS8
CSS7
CSS6
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
0000
31:16
—
—
—
—
—
—
—
—
—
—
CSS53
—
—
CSS50
CSS49
CSS48
0000
15:0
CSS47(1)
CSS46(1)
CSS45(1)
—
—
—
CSS41(1)
CSS40(1)
CSS39(1)
CSS38(1)
CSS37(1)
CSS36(1)
CSS35(1)
CSS34(1)
CSS33(1)
—
0000
31:16
—
—
—
—
ARDY27
ARDY26
ARDY25
ARDY24
ARDY21(1)
ARDY20(1)
ARDY19
ARDY18
ARDY17
ARDY16
0000
15:0
ARDY15
ARDY14
ARDY13
ARDY12
ARDY11
ARDY10
ARDY9
ARDY8
ARDY7
ARDY6
ARDY5
ARDY4
ARDY3
ARDY2
ARDY1
ARDY0
0000
31:16
—
—
—
—
—
—
—
—
—
—
ARDY53
ARDY52
—
ARDY50
ARDY49
ARDY48
0000
ARDY45(1)
—
—
—
ARDY41(1)
ARDY40(1) ARDY39(1) ARDY38(1)
ARDY37(1)
ARDY36(1)
—
0000
CMPE23(1) CMPE22(1)
CMPE21(1)
CMPE20(1)
CMPE19
CMPE18
CMPE17
CMPE16 0000
CMPE5
CMPE4
CMPE3
CMPE2
CMPE1
CMPE0
70D0 ADCDSTAT2
DS60001570C-page 305
15:0 ARDY47(1) ARDY46(1)
SH1ALT
0000
—
70C0 ADCDSTAT1
SH2ALT
0000
—
70B0 ADCCSS2
SH3ALT
0000
DIGEN2
—
7050 ADCIMCON2
SH4ALT
DIGEN3
7030 ADCTRGMODE 31:16
7040 ADCIMCON1
SH5ALT
DIGEN7
0000
0000
—
CONCLKDIV
VREFSEL
23/7
CVDCPL
ADCSEL
15:0
27/11
—
15:0 BGVRIEN REFFLTIEN
7020 ADCCON3
28/12
All Resets
Register
Name
ADC REGISTER MAP
Bit Range
Virtual
Address
TABLE 23-2:
SH0ALT
0000
SSAMPEN5 SSAMPEN4 SSAMPEN3 SSAMPEN2 SSAMPEN1 SSAMPEN0 0000
AGIEN23(1) AGIEN22(1) AGIEN21(1) AGIEN20(1)
AGIEN50(2) AGIEN49
SIGN40(1) 0000
AGIEN16 0000
AGIEN0
0000
AGIEN48 0000
AGIEN41(1) AGIEN40(1) AGIEN39(1) AGIEN38(1) AGIEN37(1) AGIEN36(1) AGIEN35(1) AGIEN34(1) AGIEN33(1) AGIEN32(1) 0000
ARDY23(1) ARDY22(1)
ARDY35(1) ARDY34(1) ARDY33(1)
70E0 ADCCMPEN1
31:16
—
—
—
—
CMPE27
CMPE26
CMPE25
CMPE24
15:0
CMPE15
CMPE14
CMPE13
CMPE12
CMPE11
CMPE10
CMPE9
CMPE8
70F0 ADCCMP1
31:16
DCMPHI
0000
15:0
DCMPLO
0000
Note
1:
2:
3:
CMPE7
CMPE6
This bit or register is not available on 64-pin devices.
These register bits are for internal ADC input sources (i.e., IVREF, and CTMU Temperature Sensor.
Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory programmed DEVADCx Flash locations starting at 0xBFC45000 into the ADCxCFG registers starting at
0xBF887D00, respectively.
0000
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
23.2
7100 ADCCMPEN2
7110 ADCCMP2
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
CMPE27
CMPE26
CMPE25
CMPE24
15:0
CMPE15
CMPE14
CMPE13
CMPE12
CMPE11
CMPE10
CMPE9
CMPE8
23/7
CMPE23(1) CMPE22(1)
CMPE7
31:16
DCMPHI
15:0
DCMPLO
31:16
—
—
—
—
CMPE27
CMPE26
CMPE25
CMPE24
15:0
CMPE15
CMPE14
CMPE13
CMPE12
CMPE11
CMPE10
CMPE9
CMPE8
7130 ADCCMP3
31:16
DCMPHI
15:0
DCMPLO
CMPE7
31:16
—
—
—
—
CMPE27
CMPE26
CMPE25
CMPE24
15:0
CMPE15
CMPE14
CMPE13
CMPE12
CMPE11
CMPE10
CMPE9
CMPE8
7150 ADCCMP4
31:16
DCMPHI
15:0
DCMPLO
AFEN
DATA16EN
DFMODE
OVRSAM
AFGIEN
15:0
71B0 ADCFLTR2
31:16
31:16
AFEN
DATA16EN
DFMODE
OVRSAM
AFGIEN
31:16
AFEN
DATA16EN
DFMODE
OVRSAM
AFGIEN
7210 ADCTRG2
2019-2020 Microchip Technology Inc.
7220 ADCTRG3
7230 ADCTRG4
7240 ADCTRG5
7250 ADCTRG6(1)
7260 ADCTRG7
Note
1:
2:
3:
18/2
17/1
16/0
CMPE21(1)
CMPE20(1)
CMPE19
CMPE18
CMPE17
CMPE16 0000
CMPE5
CMPE4
CMPE3
CMPE2
CMPE1
CMPE0
AFRDY
—
AFRDY
—
AFEN
DATA16EN
DFMODE
OVRSAM
AFGIEN
AFRDY
—
0000
0000
CMPE6
CMPE21(1)
CMPE20(1)
CMPE19
CMPE18
CMPE17
CMPE16 0000
CMPE5
CMPE4
CMPE3
CMPE2
CMPE1
CMPE0
0000
0000
0000
CMPE6
CMPE21(1)
CMPE20(1)
CMPE19
CMPE18
CMPE17
CMPE16 0000
CMPE5
CMPE4
CMPE3
CMPE2
CMPE1
CMPE0
0000
0000
0000
—
—
CHNLID
—
—
CHNLID
—
—
CHNLID
—
—
CHNLID
0000
0000
0000
0000
FLTRDATA
15:0
7200 ADCTRG1
19/3
FLTRDATA
15:0
71D0 ADCFLTR4
—
20/4
FLTRDATA
15:0
71C0 ADCFLTR3
AFRDY
CMPE7
21/5
0000
CMPE23(1) CMPE22(1)
7140 ADCCMPEN4
31:16
CMPE6
CMPE23(1) CMPE22(1)
7120 ADCCMPEN3
71A0 ADCFLTR1
22/6
All Resets
Bit Range
Virtual
Address
Register
Name
ADC REGISTER MAP (CONTINUED)
0000
0000
FLTRDATA
0000
0000
31:16
—
—
—
TRGSRC3
—
—
—
TRGSRC2
0000
15:0
—
—
—
TRGSRC1
—
—
—
TRGSRC0
0000
31:16
—
—
—
TRGSRC7
—
—
—
TRGSRC6
0000
15:0
—
—
—
TRGSRC5
—
—
—
TRGSRC4
0000
31:16
—
—
—
TRGSRC11
—
—
—
TRGSRC10
0000
15:0
—
—
—
TRGSRC9
—
—
—
TRGSRC8
0000
31:16
—
—
—
TRGSRC15
—
—
—
TRGSRC14
0000
15:0
—
—
—
TRGSRC13
—
—
—
TRGSRC12
0000
31:16
—
—
—
TRGSRC19(1)
—
—
—
TRGSRC18
0000
15:0
—
—
—
TRGSRC17
—
—
—
TRGSRC16
0000
31:16
—
—
—
TRGSRC23
—
—
—
TRGSRC22
0000
15:0
—
—
—
TRGSRC21
—
—
—
TRGSRC20
0000
31:16
—
—
—
TRGSRC27
—
—
—
TRGSRC26
0000
15:0
—
—
—
TRGSRC25
—
—
—
TRGSRC24
0000
This bit or register is not available on 64-pin devices.
These register bits are for internal ADC input sources (i.e., IVREF, and CTMU Temperature Sensor.
Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory programmed DEVADCx Flash locations starting at 0xBFC45000 into the ADCxCFG registers starting at
0xBF887D00, respectively.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 306
TABLE 23-2:
Bits
31/15
30/14
29/13
15:0
—
—
7290 ADCCMPCON2 31:16
—
—
—
15:0
—
—
—
72A0 ADCCMPCON3 31:16
—
—
—
15:0
—
—
—
72B0 ADCCMPCON4 31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
28/12
27/11
26/10
25/9
7280 ADCCMPCON1 31:16
7300 ADCBASE
7320 ADCCNTB
7330 ADCDMAB
7340 ADCTRGSNS
7350 ADC0TIME
7360 ADC1TIME
7370 ADC2TIME
7380 ADC3TIME
7390 ADC4TIME
73A0 ADC5TIME
DS60001570C-page 307
73C0 ADCEIEN1
73D0 ADCEIEN2
1:
2:
3:
22/6
21/5
20/4
19/3
18/2
17/1
16/0
DCMPED
IEBTWN
IEHIHI
IEHILO
IELOHI
IELOLO
—
—
—
0000
—
—
—
—
—
—
0000
DCMPED
IEBTWN
IEHIHI
IEHILO
IELOHI
IELOLO
—
—
AINID
—
—
—
0000
—
—
—
—
—
—
0000
DCMPED
IEBTWN
IEHIHI
IEHILO
IELOHI
IELOLO
—
—
—
—
0000
—
—
—
—
—
—
0000
DCMPED
IEBTWN
IEHIHI
IEHILO
IELOHI
IELOLO
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
ENDCMP DCMPGIEN
—
—
AINID
—
—
ENDCMP DCMPGIEN
AINID
—
0000
ENDCMP DCMPGIEN
—
—
ENDCMP DCMPGIEN
—
—
—
ADCBASE
0000
31:16
DMAEN
—
RBFIEN5
RBFIEN4
RBFIEN3
RBFIEN2
RBFIEN1
RBFIEN0
WOVERR
—
RBF5
RBF4
RBF3
RBF2
RBF1
RBF0
0000
15:0
DMACEN
—
RAFIEN5
RAFIEN4
RAFIEN3
RAFIEN2
RAFIEN1
RAFIEN0
—
—
RAF5
RAF4
RAF3
RAF2
RAF1
RAF0
0000
31:16
ADCCNTB
0000
15:0
ADCCNTB
0000
31:16
ADCDMAB
0000
15:0
ADCDMAB
0000
31:16
—
—
—
—
LVL27
LVL26
LVL25
LVL24
LVL23(1)
LVL22(1)
LVL21(1)
LVL20(1)
LVL19
LVL18
LVL17
LVL16
0000
15:0
LVL15
LVL14
LVL13
LVL12
LVL11
LVL10
LVL9
LVL8
LVL7
LVL6
LVL5
LVL4
LVL3
LVL2
LVL1
LVL0
0000
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
EIEN27
EIEN26
EIEN25
EIEN24
EIEN23(1)
EIEN22(1)
EIEN21(1)
EIEN20(1)
EIEN19
EIEN18
EIEN17
EIEN16
0000
15:0
EIEN15
EIEN14
EIEN13
EIEN12
EIEN11
EIEN10
EIEN9
EIEN8
EIEN7
EIEN6
EIEN5
EIEN4
EIEN3
EIEN2
EIEN1
EIEN0
0000
31:16
—
—
—
—
—
—
—
—
—
—
EIRDY53
EIRDY52
—
EIRDY50
EIRDY49
—
—
—
EIEN41(1)
EIEN40(1)
EIEN39(1)
EIEN38(1)
EIEN37(1)
EIEN36(1)
EIEN35(1)
EIEN34(1)
EIEN33(1)
15:0 EIRDY47(1) EIRDY46(1) EIRDY45(1)
Note
23/7
CVDDATA
AINID
15:0
7310 ADCDSTAT
24/8
All Resets
Bit Range
Virtual
Address
Register
Name
ADC REGISTER MAP (CONTINUED)
ADCEIS
—
—
SELRES
—
—
—
—
—
BCHEN
0300
0000
ADCDIV
—
0300
SAMC
SELRES
BCHEN
0000
ADCDIV
—
0300
SAMC
SELRES
BCHEN
0000
ADCDIV
—
ADCEIS
0000
ADCDIV
SAMC
SELRES
ADCEIS
—
BCHEN
—
ADCEIS
0300
SAMC
SELRES
ADCEIS
—
ADCDIV
—
ADCEIS
—
BCHEN
0300
SAMC
SELRES
BCHEN
0000
ADCDIV
0300
SAMC
0000
EIRDY48 0000
—
This bit or register is not available on 64-pin devices.
These register bits are for internal ADC input sources (i.e., IVREF, and CTMU Temperature Sensor.
Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory programmed DEVADCx Flash locations starting at 0xBFC45000 into the ADCxCFG registers starting at
0xBF887D00, respectively.
0000
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 23-2:
73E0 ADCEISTAT1
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
EIRDY23(1) EIRDY22(1) EIRDY21(1) EIRDY20(1)
19/3
18/2
17/1
16/0
All Resets
Bit Range
Virtual
Address
Register
Name
ADC REGISTER MAP (CONTINUED)
31:16
—
—
—
—
EIRDY27
EIRDY26
EIRDY25
EIRDY24
EIRDY19
EIRDY18
EIRDY17
15:0
EIRDY15
EIRDY14
EIRDY13
EIRDY12
EIRDY11
EIRDY10
EIRDY9
EIRDY8
EIRDY7
EIRDY6
EIRDY5
EIRDY4
EIRDY3
EIRDY2
EIRDY1
EIRDY0
73F0 ADCEISTAT2
31:16
—
—
—
—
—
—
—
—
—
—
EIRDY53
EIRDY52
—
EIRDY50
EIRDY49
EIRDY48 0000
15:0 EIRDY47(1) EIRDY46(1) EIRDY45(1)
—
—
7400 ADCANCON
31:16
—
—
—
—
15:0
WKRDY7
—
WKRDY5
WKRDY4
7600 ADCDATA0
7610 ADCDATA1
7620 ADCDATA2
7630 ADCDATA3
7640 ADCDATA4
7650 ADCDATA5
7660 ADCDATA6
7670 ADCDATA7
7680 ADCDATA8
2019-2020 Microchip Technology Inc.
7690 ADCDATA9
76A0 ADCDATA10
76B0 ADCDATA11
76C0 ADCDATA12
76D0 ADCDATA13
Note
1:
2:
3:
—
EIRDY41(1) EIRDY40(1) EIRDY39(1) EIRDY38(1) EIRDY37(1) EIRDY36(1) EIRDY35(1) EIRDY34(1) EIRDY33(1)
WKUPCLKCNT
WKRDY3
WKRDY2
WKRDY1
WKRDY0
EIRDY16 0000
0000
—
0000
WKIEN7
—
WKIEN5
WKIEN4
WKIEN3
WKIEN2
WKIEN1
WKIEN0
0000
ANEN7
—
ANEN5
ANEN4
ANEN3
ANEN2
ANEN1
ANEN0
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
This bit or register is not available on 64-pin devices.
These register bits are for internal ADC input sources (i.e., IVREF, and CTMU Temperature Sensor.
Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory programmed DEVADCx Flash locations starting at 0xBFC45000 into the ADCxCFG registers starting at
0xBF887D00, respectively.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 308
TABLE 23-2:
76E0 ADCDATA14
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Virtual
Address
Register
Name
ADC REGISTER MAP (CONTINUED)
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
7740 ADCDATA20(1) 31:16
DATA
0000
15:0
DATA
0000
7750 ADCDATA21(1) 31:16
DATA
0000
15:0
DATA
0000
7760 ADCDATA22(1) 31:16
DATA
0000
15:0
DATA
0000
7770 ADCDATA23(1) 31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
7810 ADCDATA33(1) 31:16
DATA
0000
15:0
DATA
0000
7820 ADCDATA34(1) 31:16
DATA
0000
15:0
DATA
0000
7830 ADCDATA35(1) 31:16
DATA
0000
15:0
DATA
0000
76F0 ADCDATA15
7700 ADCDATA16
7710 ADCDATA17
7720 ADCDATA18
7730 ADCDATA19
7780 ADCDATA24
7790 ADCDATA25
77A0 ADCDATA26
77B0 ADCDATA27
DS60001570C-page 309
Note
1:
2:
3:
This bit or register is not available on 64-pin devices.
These register bits are for internal ADC input sources (i.e., IVREF, and CTMU Temperature Sensor.
Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory programmed DEVADCx Flash locations starting at 0xBFC45000 into the ADCxCFG registers starting at
0xBF887D00, respectively.
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 23-2:
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Virtual
Address
Register
Name
ADC REGISTER MAP (CONTINUED)
7840 ADCDATA36(1) 31:16
DATA
0000
15:0
DATA
0000
7850 ADCDATA37(1) 31:16
DATA
0000
15:0
DATA
0000
7860 ADCDATA38(1) 31:16
DATA
0000
15:0
DATA
0000
7870 ADCDATA39(1) 31:16
DATA
0000
15:0
DATA
0000
7880 ADCDATA40(1) 31:16
DATA
0000
15:0
DATA
0000
7890 ADCDATA41(1) 31:16
DATA
0000
15:0
DATA
0000
78D0 ADCDATA45(1) 31:16
DATA
0000
15:0
DATA
0000
78E0 ADCDATA46(1) 31:16
DATA
0000
15:0
DATA
0000
78F0 ADCDATA47(1) 31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
7920 ADCDATA50(2) 31:16
DATA
0000
15:0
DATA
0000
7950 ADCDATA53(2) 31:16
DATA
0000
15:0
DATA
7900 ADCDATA48
7910 ADCDATA49
2019-2020 Microchip Technology Inc.
7E00 ADCSYSCFG0 31:16
15:0
7E10 ADCSYSCFG1 31:16
15:0
7D00 ADC0CFG(3)
7D10 ADC1CFG(3)
Note
1:
2:
3:
0000
—
—
—
—
AN27
AN26
AN25
AN24
AN23(1)
AN22(1)
AN21(1)
AN20(1)
AN19
AN18
AN17
AN16
0FxF
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
FFFF
—
—
—
—
—
—
—
—
—
—
AN53(1)
AN52(1)
—
AN50(1)
AN49
AN48
00xx
AN47(1)
AN46(1)
AN45(1)
—
—
—
AN41(1)
AN40(1)
AN39(1)
AN38(1)
AN37(1)
AN36(1)
AN35(1)
AN34(1)
AN33(1)
—
xxxx
31:16
ADCCFG
0000
15:0
ADCCFG
0000
31:16
ADCCFG
0000
15:0
ADCCFG
0000
This bit or register is not available on 64-pin devices.
These register bits are for internal ADC input sources (i.e., IVREF, and CTMU Temperature Sensor.
Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory programmed DEVADCx Flash locations starting at 0xBFC45000 into the ADCxCFG registers starting at
0xBF887D00, respectively.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 310
TABLE 23-2:
7D20 ADC2CFG(3)
7D30 ADC3CFG(3)
7D40 ADC4CFG(3)
7D50 ADC5CFG(3)
7D70 ADC7CFG(3)
Note
1:
2:
3:
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Virtual
Address
Register
Name
ADC REGISTER MAP (CONTINUED)
31:16
ADCCFG
0000
15:0
ADCCFG
0000
31:16
ADCCFG
0000
15:0
ADCCFG
0000
31:16
ADCCFG
0000
15:0
ADCCFG
0000
31:16
ADCCFG
0000
15:0
ADCCFG
0000
31:16
ADCCFG
0000
15:0
ADCCFG
0000
This bit or register is not available on 64-pin devices.
These register bits are for internal ADC input sources (i.e., IVREF, and CTMU Temperature Sensor.
Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory programmed DEVADCx Flash locations starting at 0xBFC45000 into the ADCxCFG registers starting at
0xBF887D00, respectively.
DS60001570C-page 311
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 23-2:
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-1:
Bit
Range
31:24
23:16
15:8
7:0
ADCCON1: ADC CONTROL REGISTER 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
—
—
R/W-0
R/W-1
FRACT
R/W-0
—
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
R/W-1
R/W-0
—
R/W-0
SELRES
U-0
R/W-0
R/W-0
ON
U-0
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
R/W-0
R/W-0
R/W-0
R/W-0
U-0
STRGSRC
U-0
R/W-0
SIDL
—
CVDEN
R/W-0
R/W-0
R/W-0
IRQVS
R/W-0
FSSCLKEN FSPBCLKEN
R/W-0
STRGLVL
R/W-0
—
R/W-0
DMABL
Legend:
HC = Hardware Set
HS = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read/Write as ‘0’
bit 23
FRACT: Fractional Data Output Format bit
1 = Fractional
0 = Integer
bit 22-21 SELRES: Shared ADC7 (i.e., AN6-AN53) Resolution bits
11 = 12 bits (default)
10 = 10 bits
01 = 8 bits
00 = 6 bits
Note 1:
The PWM bit definitions are only applicable to the PIC32MKXXXMCJXX Motor Control devices otherwise
these bits are reserved.
DS60001570C-page 312
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-1:
ADCCON1: ADC CONTROL REGISTER 1 (CONTINUED)
bit 20-16 STRGSRC: Scan Trigger Source Select bits
11111 = Reserved
11110 = PWM Generator 12 trigger(1)
11101 = PWM Generator 11 trigger(1)
11100 = PWM Generator 10 trigger(1)
11011 = PWM Generator 4 Current-Limit(1)
11010 = PWM Generator 3 Current-Limit((1)1)
11001 = PWM Generator 2 Current-Limit
11000 = PWM Generator 1 Current-Limit(1)
10111 = PWM Generator 9 trigger(1)
10110 = PWM Generator 8 trigger(1)
10101 = PWM Generator 7 trigger(1)
10100 = CTMU trip
10011 = Output Compare 4 period end
10010 = Output Compare 3 period end
10001 = Output Compare 2 period end
10000 = Output Compare 1 period end
01111 = PWM Generator 6 trigger(1)
01110 = PWM Generator 5 trigger(1)
01101 = PWM Generator 4 trigger(1)
01100 = PWM Generator 3 trigger(1)
01011 = PWM Generator 2 trigger(1)
01010 = PWM Generator 1 trigger(1)
01001 = Secondary PWM time base(1)
01000 = Primary PWM time base(1)
00111 = General Purpose Timer5
00110 = General Purpose Timer3
00101 = General Purpose Timer1
00100 = INT0
00011 = Scan trigger
00010 = Software level trigger
00001 = Software edge trigger
00000 = No Trigger
Note:
bit 15
These triggers only apply to implemented analog inputs AN32-AN53. For AN0-AN27 refer to
ADCTRG1-ADCTRG7.
ON: ADC Module Enable bit
1 = ADC module is enabled
0 = ADC module is disabled
Note:
The ON bit should be set only after the ADC module has been configured.
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12
Reserved: (Read/Write as 0)
bit 11
CVDEN: Capacitive Voltage Division Enable bit
1 = CVD operation is enabled
0 = CVD operation is disabled
bit 10
FSSCLKEN: Bypass Fast Synchronous DMA System Clock to ADC Control Clock
1 = Bypass synchronizer logic for DMA system clock to ADC control clocks
0 = Enable clock synchronizers for non-synchronized DMA to ADC clock sources
NOTE: Synchronizers required if ADCCON3 = REFCLK3, or ADCCON3 = FRC and
FRC is not SYSCLK source otherwise this bit is n/a.
Note 1:
The PWM bit definitions are only applicable to the PIC32MKXXXMCJXX Motor Control devices otherwise
these bits are reserved.
2019-2020 Microchip Technology Inc.
DS60001570C-page 313
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-1:
ADCCON1: ADC CONTROL REGISTER 1 (CONTINUED)
bit 9
FSPBCLKEN: Bypass Fast Synchronous Peripheral Bus Clock to ADC Control Clock
1 = Bypass synchronizer logic for peripheral clock to ADC control clocks
0 = Enable clock synchronizers for non-synchronized peripheral clock to ADC control clocks
NOTE: Synchronizers required if ADCCON3 = REFCLK3, or ADCCON3 = FRC and
FRC is not SYSCLK source otherwise this bit is n/a.
bit 8-7
Unimplemented: Read as ‘0’
bit 6-4
IRQVS: Interrupt Vector Shift bits
To determine interrupt vector address, this bit specifies the amount of left shift done to the AIRDYx status
bits in the ADCDSTAT1 and ADCDSTAT2 registers, prior to adding with the ADCBASE register.
Interrupt Vector Address = Read Value of ADCBASE and Read Value of ADCBASE = Value written to
ADCBASE + x 000), the internal capacitors are internally connected to all ADC7 inputs. To
determine user ADC sampling time requirements (SAMC bits (ADCCON2)) with
CVDCPL selection, refer to TABLE 36-41: “ADC Sample Times with CVD Enabled”.
2019-2020 Microchip Technology Inc.
DS60001570C-page 315
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-2:
bit 25-16
ADCCON2: ADC CONTROL REGISTER 2 (CONTINUED)
SAMC: Sample Time for the Shared ADC (ADC7) bits
1111111111 = 1025 TAD
•
•
•
0000000001 = 3 TAD
0000000000 = 2 TAD
Where TAD = period of the ADC conversion clock for the Shared ADC (ADC7) controlled by the
ADCDIV bits.
Shared ADC7 Throughput rate:
= ((1/((Sample time + Conversion time)(TAD))) / #of ADC inputs used in scan list)
= ((1 / ((SAMC + # bit resolution+1)(TAD))) / #of ADC inputs used in scan list)
Example:
SCAN mode enabled with (2) ANx inputs in scan list, (i.e. ADCCSSx), SAMC = 4 TAD, 12-bit
mode, TAD = 16.667ns = 60 MHz:
Throughput rate = ((1/((4+12+1)(16.667 ns))) /2)
= ((1/(17 * 16.667 ns)) /2)
= 1.764706 msps
Note:
Unlike the High-Speed Class 1 ADC modules, the trigger event for the shared Class 3 ADC7
module initiates the SAMC sampling sequence, rather than the convert sequence.
bit 15
BGVRIEN: Band Gap/VREF Voltage Ready Interrupt Enable bit
1 = Interrupt will be generated when the BGVRDDY bit is set
0 = No interrupt is generated when the BGVRRDY bit is set
bit 14
REFFLTIEN: Band Gap/VREF Voltage Fault Interrupt Enable bit
1 = Interrupt will be generated when the REFFLT bit is set
0 = No interrupt is generated when the REFFLT bit is set
bit 13
EOSIEN: End of Scan Interrupt Enable bit
1 = Interrupt will be generated when EOSRDY bit is set
0 = No interrupt is generated when the EOSRDY bit is set
bit 12
ADCEIOVR: Early Interrupt Request Override bit
1 = Early interrupt generation is overridden and interrupt generation is controlled by the ADCGIRQEN1
and ADCGIRQEN2 registers
0 = Early interrupt generation is not overridden and interrupt generation is controlled by the ADCEIEN1
and ADCEIEN2 registers
bit 11
Unimplemented: Read as ‘0’
bit 10-8
ADCEIS: Shared ADC (ADC7) Early Interrupt Select bits
These bits select the number of clocks (TAD7) prior to the arrival of valid data that the associated interrupt
is generated.
111 = The data ready interrupt is generated 8 ADC clocks prior to end of conversion
110 = The data ready interrupt is generated 7 ADC clocks prior to end of conversion
•
•
•
001 = The data ready interrupt is generated 2 ADC module clocks prior to end of conversion
000 = The data ready interrupt is generated 1 ADC module clock prior to end of conversion
Note:
bit 7
All options are available when the selected resolution, set by the SELRES bits
(ADCCON1), is 12-bit or 10-bit. For a selected resolution of 8-bit, options from ‘000’ to
‘101’ are valid. For a selected resolution of 6-bit, options from ‘000’ to ‘011’ are valid.
Unimplemented: Read as ‘0’
DS60001570C-page 316
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-2:
bit 6-0
ADCCON2: ADC CONTROL REGISTER 2 (CONTINUED)
ADCDIV: Shared ADC (ADC7) Clock Divider bits
1111111 = 254 * TQ = TAD
•
•
•
0000011 = 6 * TQ = TAD
0000010 = 4 * TQ = TAD
0000001 = 2 * TQ = TAD
0000000 = Reserved
The ADCDIV bits divide the ADC control clock (TQ) to generate the clock for the Shared ADC, ADC7
(TAD7).
2019-2020 Microchip Technology Inc.
DS60001570C-page 317
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-3:
Bit
Range
ADCCON3: ADC CONTROL REGISTER 3
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
ADCSEL
23:16
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIGEN7
—
DIGEN5
DIGEN4
DIGEN3
DIGEN2
DIGEN1
DIGEN0
R/W-0
R/W-0
R/W-0
15:8
VREFSEL
R/W-0
7:0
CONCLKDIV
R-0, HS, HC
R/W-0
R/W-0
R/W-0
R-0, HS, HC
R/W-0
R-0, HS, HC
TRGSUSP
UPDIEN
UPDRDY
SAMP(1,2,3,4)
RQCNVRT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GLSWTRG GSWTRG
ADINSEL
Legend:
R = Readable bit
HC = Hardware Set
W = Writable bit
HS = Hardware Cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 ADCSEL: Analog-to-Digital Clock Source (TCLK) bits
11 = SYSCLK (Required if using DMA for ADC)
10 = REFCLK3
01 = FRC
00 = SYSCLK
bit 29-24 CONCLKDIV: Analog-to-Digital Control Clock (TQ) Divider bits
111111 = 126 * TCLK = TQ
•
•
•
000011 = 6 * TCLK = TQ
000010 = 4 * TCLK = TQ
000001 = 2 * TCLK = TQ
000000 = TCLK = TQ
DIGEN7: Shared ADC (ADC7) Digital Enable bit
1 = ADC7 is digital enabled
0 = ADC7 is digital disabled
Unimplemented: Read as ‘0’
bit 23
bit 22
bit 21
DIGEN5: ADC5 Digital Enable bit
1 = ADC5 is digital enabled (required for active operation)
0 = ADC5 is digital disabled (power-saving mode)
bit 20
DIGEN4: ADC4 Digital Enable bit
1 = ADC4 is digital enabled (required for active operation)
0 = ADC4 is digital disabled (power-saving mode)
Note 1:
The SAMP bit has the highest priority and setting this bit will keep the S&H circuit in Sample mode until the
bit is cleared. Also, usage of the SAMP bit will cause settings of SAMC bits (ADCCON2) to
be ignored.
The SAMP bit only connects analog inputs to the shared ADC, ADC7. All Class 1 analog inputs are not
affected by the SAMP bit.
The SAMP bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit
and only after setting the RQCNVRT bit to start the analog-to-digital conversion.
Normally, when the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx bits and
STRGSRC bits should be set to ‘00000’ to disable all external hardware triggers and prevent them
from interfering with the software-controlled sampling command signal SAMP and with the softwarecontrolled trigger RQCNVRT.
2:
3:
4:
DS60001570C-page 318
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-3:
ADCCON3: ADC CONTROL REGISTER 3 (CONTINUED)
bit 19
DIGEN3: ADC3 Digital Enable bit
1 = ADC3 is digital enabled (required for active operation)
0 = ADC3 is digital disabled (power-saving mode)
bit 18
DIGEN2: ADC2 Digital Enable bit
1 = ADC2 is digital enabled (required for active operation)
0 = ADC2 is digital disabled (power-saving mode)
bit 17
DIGEN1: ADC1 Digital Enable bit
1 = ADC1 is digital enabled (required for active operation)
0 = ADC1 is digital disabled (power-saving mode)
DIGEN0: ADC0 Digital Enable bit
1 = ADC0 is digital enabled (required for active operation)
0 = ADC0 is digital disabled (power-saving mode)
bit 15-13 VREFSEL: Voltage Reference (VREF) Input Selection bits
bit 16
VREFSEL
ADC VREFH
ADC VREFL
1xx
011
010
001
000
Reserved
VREF+
AVDD
VREF+
AVDD
Reserved
VREFVREFAVSS
AVSS
bit 12
TRGSUSP: Trigger Suspend bit
1 = Triggers are blocked from starting a new analog-to-digital conversion, but the ADC module is not disabled
0 = Triggers are not blocked
bit 11
UPDIEN: Update Ready Interrupt Enable bit
1 = Interrupt will be generated when the UPDRDY bit is set by hardware
0 = No interrupt is generated
bit 10
UPDRDY: ADC Update Ready Status bit
1 = ADC SFRs can be updated
0 = ADC SFRs cannot be updated
Note: This bit is only active while the TRGSUSP bit is set and there are no more running conversions of
any ADC modules.
bit 9
SAMP: Shared ADC7 Analog Input Sampling Enable bit(1,2,3,4)
1 = The ADC S&H amplifier is sampling
0 = The ADC S&H amplifier is holding
bit 8
RQCNVRT: Individual ADC Input Conversion Request bit
This bit and its associated ADINSEL bits enable the user to individually request an analog-to-digital
conversion of an analog input through software.
1 = Trigger the conversion of the selected ADC input as specified by the ADINSEL bits
0 = Do not trigger the conversion
Note: This bit is automatically cleared in the next ADC clock cycle.
Note 1:
The SAMP bit has the highest priority and setting this bit will keep the S&H circuit in Sample mode until the
bit is cleared. Also, usage of the SAMP bit will cause settings of SAMC bits (ADCCON2) to
be ignored.
The SAMP bit only connects analog inputs to the shared ADC, ADC7. All Class 1 analog inputs are not
affected by the SAMP bit.
The SAMP bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit
and only after setting the RQCNVRT bit to start the analog-to-digital conversion.
Normally, when the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx bits and
STRGSRC bits should be set to ‘00000’ to disable all external hardware triggers and prevent them
from interfering with the software-controlled sampling command signal SAMP and with the softwarecontrolled trigger RQCNVRT.
2:
3:
4:
2019-2020 Microchip Technology Inc.
DS60001570C-page 319
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-3:
ADCCON3: ADC CONTROL REGISTER 3 (CONTINUED)
bit 7
GLSWTRG: Global Level Software Trigger bit
1 = Trigger conversion for ADC inputs that have selected the GLSWTRG bit as the trigger signal, either
through the associated TRGSRC bits in the ADCTRGx registers or through the STRGSRC
bits in the ADCCON1 register
0 = Do not trigger an analog-to-digital conversion
bit 6
GSWTRG: Global Software Trigger bit
1 = Trigger conversion for ADC inputs that have selected the GSWTRG bit as the trigger signal, either
through the associated TRGSRC bits in the ADCTRGx registers or through the STRGSRC
bits in the ADCCON1 register
0 = Do not trigger an analog-to-digital conversion
Note: This bit is automatically cleared in the next ADC clock cycle.
Note 1:
The SAMP bit has the highest priority and setting this bit will keep the S&H circuit in Sample mode until the
bit is cleared. Also, usage of the SAMP bit will cause settings of SAMC bits (ADCCON2) to
be ignored.
The SAMP bit only connects analog inputs to the shared ADC, ADC7. All Class 1 analog inputs are not
affected by the SAMP bit.
The SAMP bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit
and only after setting the RQCNVRT bit to start the analog-to-digital conversion.
Normally, when the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx bits and
STRGSRC bits should be set to ‘00000’ to disable all external hardware triggers and prevent them
from interfering with the software-controlled sampling command signal SAMP and with the softwarecontrolled trigger RQCNVRT.
2:
3:
4:
DS60001570C-page 320
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-3:
bit 5-0
ADCCON3: ADC CONTROL REGISTER 3 (CONTINUED)
ADINSEL: Analog Input Select bits
These bits select the analog input to be converted when the RQCNVRT bit is set.
111111 = Reserved
•
•
•
110110 = Reserved
110101 = CTMU Temperature Sensor (internal AN53)
110100 = Reserved
110011 = Reserved
110010 = IVREF 1.2V (internal AN50)
110001 = AN49
•
•
•
101101 = AN45
101100 = Reserved
•
•
•
101010 = Reserved
101001 = AN41
•
•
•
100001 = AN33
100000 = Reserved
•
•
•
011100 = Reserved
011011 = AN27
•
•
•
000000 = AN0
Note:
Note 1:
2:
3:
4:
AN20-AN23, AN33-AN41, and AN45-AN47 are not available on 64-pin devices. Refer to
TABLE 1-1: “PORTA THrough PORTG REMAPPABLE PERIPHERAL DescriptionS” for
details.
The SAMP bit has the highest priority and setting this bit will keep the S&H circuit in Sample mode until the
bit is cleared. Also, usage of the SAMP bit will cause settings of SAMC bits (ADCCON2) to
be ignored.
The SAMP bit only connects analog inputs to the shared ADC, ADC7. All Class 1 analog inputs are not
affected by the SAMP bit.
The SAMP bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit
and only after setting the RQCNVRT bit to start the analog-to-digital conversion.
Normally, when the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx bits and
STRGSRC bits should be set to ‘00000’ to disable all external hardware triggers and prevent them
from interfering with the software-controlled sampling command signal SAMP and with the softwarecontrolled trigger RQCNVRT.
2019-2020 Microchip Technology Inc.
DS60001570C-page 321
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-4:
ADCTRGMODE: ADC TRIGGERING MODE FOR DEDICATED ADC REGISTER
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6
31:24
23:16
15:8
7:0
U-0
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
SH3ALT
SH5ALT
R/W-0
SH2ALT
R/W-0
SH4ALT
R/W-0
SH1ALT
R/W-0
SH0ALT
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
STRGEN5
STRGEN4
STRGEN3
STRGEN2
STRGEN1
STRGEN0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
SSAMPEN5 SSAMPEN4 SSAMPEN3 SSAMPEN2 SSAMPEN1 SSAMPEN0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 Unimplemented: Read as ‘0’
bit 27-26 SH5ALT: ADC5 Analog Input Select bit
11 = AN25(1)
10 = AN6(1)
01 = AN2(1)
00 = AN5
bit 25-24 SH4ALT: ADC4 Analog Input Select bit
11 = AN0(1)
10 = AN9(1)
01 = AN1(1)
00 = AN4
bit 23-22 SH3ALT: ADC3 Analog Input Select bit
11 = AN26(1)
10 = AN8(1)
01 = AN0(1)
00 = AN3
bit 21-20 SH2ALT: ADC2 Analog Input Select bit
11 = AN25(1)
10 = AN6(1)
01 = AN5(1)
00 = AN2
bit 19-18 SH1ALT: ADC1 Analog Input Select bit
11 = AN0(1)
10 = AN7(1)
01 = AN4(1)
00 = AN1
bit 17-16 SH0ALT: ADC0 Analog Input Select bit
11 = AN24(1)
10 = AN5(1)
01 = AN3(1)
00 = AN0
Note 1:
Regardless of what alternate input is selected by SHxALT, only for ADC0-ADC5, all control and results are
handled by the native SHxALT = ‘0b00 input. For example, SH0ALT = ‘0b11 = AN24. However, from a
software and silicon hardware control and results register perspective, the user application must initialize
the ADC0 module as if AN24 were actually AN0.
DS60001570C-page 322
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-4:
ADCTRGMODE: ADC TRIGGERING MODE FOR DEDICATED ADC REGISTER
(CONTINUED)
bit 15-14 Unimplemented: Read as ‘0’
bit 13
bit 12
STRGEN5: ADC5 Presynchronized Triggers bit
1 = ADC5 uses presynchronized triggers
0 = ADC5 does not use presynchronized triggers
STRGEN4: ADC4 Presynchronized Triggers bit
1 = ADC4 uses presynchronized triggers
0 = ADC4 does not use presynchronized triggers
bit 11
STRGEN3: ADC3 Presynchronized Triggers bit
1 = ADC3 uses presynchronized triggers
0 = ADC3 does not use presynchronized triggers
bit 10
STRGEN2: ADC2 Presynchronized Triggers bit
1 = ADC2 uses presynchronized triggers
0 = ADC2 does not use presynchronized triggers
bit 9
STRGEN1: ADC1 Presynchronized Triggers bit
1 = ADC1 uses presynchronized triggers
0 = ADC1 does not use presynchronized triggers
STRGEN0: ADC0 Presynchronized Triggers bit
1 = ADC0 uses presynchronized triggers
0 = ADC0 does not use presynchronized triggers
Unimplemented: Read as ‘0’
bit 8
bit 7-6
bit 5
SSAMPEN5: ADC5 Synchronous Sampling bit
1 = ADC5 uses synchronous sampling for the first sample after being idle or disabled
0 = ADC5 does not use synchronous sampling
bit 4
SSAMPEN4: ADC4 Synchronous Sampling bit
1 = ADC4 uses synchronous sampling for the first sample after being idle or disabled
0 = ADC4 does not use synchronous sampling
SSAMPEN3: ADC3 Synchronous Sampling bit
1 = ADC3 uses synchronous sampling for the first sample after being idle or disabled
0 = ADC3 does not use synchronous sampling
SSAMPEN2: ADC2Synchronous Sampling bit
1 = ADC2 uses synchronous sampling for the first sample after being idle or disabled
0 = ADC2 does not use synchronous sampling
SSAMPEN1: ADC1 Synchronous Sampling bit
1 = ADC1 uses synchronous sampling for the first sample after being idle or disabled
0 = ADC1 does not use synchronous sampling
bit 3
bit 2
bit 1
bit 0
Note 1:
SSAMPEN0: ADC0 Synchronous Sampling bit
1 = ADC0 uses synchronous sampling for the first sample after being idle or disabled
0 = ADC0 does not use synchronous sampling
Regardless of what alternate input is selected by SHxALT, only for ADC0-ADC5, all control and results are
handled by the native SHxALT = ‘0b00 input. For example, SH0ALT = ‘0b11 = AN24. However, from a
software and silicon hardware control and results register perspective, the user application must initialize
the ADC0 module as if AN24 were actually AN0.
2019-2020 Microchip Technology Inc.
DS60001570C-page 323
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-5:
Bit Range
31:24
23:16
15:8
7:0
ADCIMCON1: ADC INPUT MODE CONTROL REGISTER 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIFF15
SIGN15
DIFF14
SIGN14
DIFF13
SIGN13
DIFF12
SIGN12
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIFF11
SIGN11
DIFF10
SIGN10
DIFF9
SIGN9
DIFF8
SIGN8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIFF7
SIGN7
DIFF6
SIGN6
DIFF5
SIGN5
DIFF4
SIGN4
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIFF3
SIGN3
DIFF2
SIGN2
DIFF1
SIGN1
DIFF0
SIGN0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
DIFF15: AN15 Mode bit
1 = Selects AN15 differential input pair as AN15+ and AN10 = AN15 is using Single-ended mode
bit 30
SIGN:15 AN15 Signed Data Mode bit
1 = AN15 is using Signed Data mode
0 = AN15 is using Unsigned Data mode
bit 29
DIFF14: AN14 Mode bit
1 = Selects AN14 differential input pair as AN14+ and AN10 = AN14 is using Single-ended mode
bit 28
SIGN14: AN14 Signed Data Mode bit
1 = AN14 is using Signed Data mode
0 = AN14 is using Unsigned Data mode
bit 27
DIFF13: AN13 Mode bit
1 = Selects AN13 differential input pair as AN13+ and AN10 = AN13 is using Single-ended mode
bit 26
SIGN13: AN13 Signed Data Mode bit
1 = AN13 is using Signed Data mode
0 = AN13 is using Unsigned Data mode
bit 25
DIFF12: AN12 Mode bit
1 = Selects AN12 differential input pair as AN12+ and AN10 = AN12 is using Single-ended mode
bit 24
SIGN12: AN12 Signed Data Mode bit
1 = AN12 is using Signed Data mode
0 = AN12 is using Unsigned Data mode
bit 23
DIFF11: AN11 Mode bit
1 = Selects AN11 differential input pair as AN11+ and AN10 = AN11 is using Single-ended mode
bit 22
SIGN11: AN11 Signed Data Mode bit
1 = AN11 is using Signed Data mode
0 = AN11 is using Unsigned Data mode
bit 21
DIFF10: AN10 Mode bit
1 = Selects AN10 differential input pair as AN10+ and AN10 = AN10 is using Single-ended mode
DS60001570C-page 324
x = Bit is unknown
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-5:
ADCIMCON1: ADC INPUT MODE CONTROL REGISTER 1 (CONTINUED)
bit 20
SIGN10: AN10 Signed Data Mode bit
1 = AN10 is using Signed Data mode
0 = AN10 is using Unsigned Data mode
bit 19
DIFF9: AN9 Mode bit
1 = Selects AN9 differential input pair as AN9+ and AN10 = AN9 is using Single-ended mode
bit 18
SIGN9: AN9 Signed Data Mode bit
1 = AN9 is using Signed Data mode
0 = AN9 is using Unsigned Data mode
bit 17
DIFF8: AN 8 Mode bit
1 = Selects AN8 differential input pair as AN8+ and AN10 = AN8 is using Single-ended mode
bit 16
SIGN8: AN8 Signed Data Mode bit
1 = AN8 is using Signed Data mode
0 = AN8 is using Unsigned Data mode
bit 15
DIFF7: AN7 Mode bit
1 = Selects AN7 differential input pair as AN7+ and AN10 = AN7 is using Single-ended mode
bit 14
SIGN7: AN7 Signed Data Mode bit
1 = AN7 is using Signed Data mode
0 = AN7 is using Unsigned Data mode
bit 13
DIFF6: AN6 Mode bit
1 = Selects AN6 differential input pair as AN6+ and AN10 = AN6 is using Single-ended mode
bit 12
SIGN6: AN6 Signed Data Mode bit
1 = AN6 is using Signed Data mode
0 = AN6 is using Unsigned Data mode
bit 11
DIFF5: AN5 Mode bit
1 = Selects AN5 differential input pair as AN5+ and AN110 = AN5 is using Single-ended mode
bit 10
SIGN5: AN5 Signed Data Mode bit
1 = AN5 is using Signed Data mode
0 = AN5 is using Unsigned Data mode
bit 9
DIFF4: AN4 Mode bit
1 = Selects AN4 differential input pair as AN4+ and AN100 = AN4 is using Single-ended mode
bit 8
SIGN4: AN4 Signed Data Mode bit
1 = AN4 is using Signed Data mode
0 = AN4 is using Unsigned Data mode
bit 7
DIFF3: AN3 Mode bit
1 = Selects AN3 differential input pair as AN3+ and AN270 = AN3 is using Single-ended mode
bit 6
SIGN3: AN3 Signed Data Mode bit
1 = AN3 is using Signed Data mode
0 = AN3 is using Unsigned Data mode
bit 5
DIFF2: AN2 Mode bit
1 = Selects AN2 differential input pair as AN2+ and AN80 = AN2 is using Single-ended mode
bit 4
SIGN2: AN2 Signed Data Mode bit
1 = AN2 is using Signed Data mode
0 = AN2 is using Unsigned Data mode
2019-2020 Microchip Technology Inc.
DS60001570C-page 325
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-5:
ADCIMCON1: ADC INPUT MODE CONTROL REGISTER 1 (CONTINUED)
bit 3
DIFF1: AN1 Mode bit
1 = Selects AN1 differential input pair as AN1+ and AN70 = AN1 is using Single-ended mode
bit 2
SIGN1: AN1 Signed Data Mode bit
1 = AN1 is using Signed Data mode
0 = AN1 is using Unsigned Data mode
bit 1
DIFF0: AN0 Mode bit
1 = Selects AN0 differential input pair as AN0+ and AN60 = AN0 is using Single-ended mode
bit 0
SIGN0: AN0 Signed Data Mode bit
1 = AN0 is using Signed Data mode
0 = AN0 is using Unsigned Data mode
DS60001570C-page 326
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-6:
Bit Range
31:24
23:16
15:8
7:0
ADCIMCON2: ADC INPUT MODE CONTROL REGISTER 2
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIFF27
SIGN27
DIFF26
SIGN26
DIFF25
SIGN25
DIFF24
SIGN24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIFF23(1)
SIGN23(1)
DIFF22(1)
SIGN22(1)
DIFF21(1)
SIGN21(1)
DIFF20(1)
SIGN20(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIFF19
SIGN19
DIFF18
SIGN18
DIFF17
SIGN17
DIFF16
SIGN16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-24
Unimplemented: Read as ‘0’
bit 23
DIFF27: AN27 Mode bit
1 = Selects AN27 differential pair input as AN27+ and AN10 = AN27 is using Single-ended mode
bit 22
SIGN27: AN27 Signed Data Mode bit
1 = AN27 is using Signed Data mode
0 = AN27 is using Unsigned Data mode
bit 21
DIFF26: AN26 Mode bit
1 = Selects AN26 differential pair input as AN26+ and AN10 = AN26 is using Single-ended mode
bit 20
SIGN26: AN26 Signed Data Mode bit
1 = AN26 is using Signed Data mode
0 = AN26 is using Unsigned Data mode
bit 19
DIFF25: AN25 Mode bit
1 = Selects AN25 differential pair input as AN25+ and AN10 = AN25 is using Single-ended mode
bit 18
SIGN25: AN25 Signed Data Mode bit
1 = AN25 is using Signed Data mode
0 = AN25 is using Unsigned Data mode
bit 17
DIFF24: AN24 Mode bit
1 = Selects AN24 differential pair input as AN24+ and AN10 = AN24 is using Single-ended mode
bit 16
SIGN24: AN24 Signed Data Mode bit
1 = AN24 is using Signed Data mode
0 = AN24 is using Unsigned Data mode
bit 15
DIFF23: AN23 Mode bit(1)
1 = Selects AN23 differential pair input as AN23+ and AN10 = AN23 is using Single-ended mode
bit 14
SIGN23: AN23 Signed Data Mode bit(1)
1 = AN23 is using Signed Data mode
0 = AN23 is using Unsigned Data mode
Note 1:
x = Bit is unknown
This bit is not available on 64-pin devices.
2019-2020 Microchip Technology Inc.
DS60001570C-page 327
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-6:
ADCIMCON2: ADC INPUT MODE CONTROL REGISTER 2 (CONTINUED)
bit 13
DIFF22: AN22 Mode bit(1)
1 = Selects AN22 differential pair input as AN22+ and AN10 = AN22 is using Single-ended mode
bit 12
SIGN22: AN22 Signed Data Mode bit(1)
1 = AN22 is using Signed Data mode
0 = AN22 is using Unsigned Data mode
bit 11
DIFF21: AN21 Mode bit(1)
1 = Selects AN21 differential pair input as AN21+ and AN10 = AN21 is using Single-ended mode
bit 10
SIGN21: AN21 Signed Data Mode bit(1)
1 = AN21 is using Signed Data mode
0 = AN21 is using Unsigned Data mode
bit 9
DIFF20: AN20 Mode bit(1)
1 = Selects AN20 differential pair input as AN20+ and AN10 = AN20 is using Single-ended mode
bit 8
SIGN20: AN20 Signed Data Mode bit(1)
1 = AN20 is using Signed Data mode
0 = AN20 is using Unsigned Data mode
bit 7
DIFF19: AN19 Mode bit
1 = Selects AN19 differential pair input as AN19+ and AN10 = AN19 is using Single-ended mode
bit 6
SIGN19: AN19 Signed Data Mode bit
1 = AN19 is using Signed Data mode
0 = AN19 is using Unsigned Data mode
bit 5
DIFF18: AN18 Mode bit
1 = Selects AN18 differential pair input as AN18+ and AN10 = AN18 is using Single-ended mode
bit 4
SIGN18: AN18 Signed Data Mode bit
1 = AN18 is using Signed Data mode
0 = AN18 is using Unsigned Data mode
bit 3
DIFF17: AN17 Mode bit
1 = Selects AN17 differential pair input as AN17+ and AN10 = AN17 is using Single-ended mode
bit 2
SIGN17: AN17 Signed Data Mode bit
1 = AN17 is using Signed Data mode
0 = AN17 is using Unsigned Data mode
bit 1
DIFF16: AN16 Mode bit
1 = Selects AN16 differential pair input as AN16+ and AN10 = AN16 is using Single-ended mode
bit 0
SIGN16: AN16 Signed Data Mode bit
1 = AN16 is using Signed Data mode
0 = AN16 is using Unsigned Data mode
Note 1:
This bit is not available on 64-pin devices.
DS60001570C-page 328
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-7:
Bit Range
31:24
23:16
15:8
7:0
ADCIMCON3: ADC INPUT MODE CONTROL REGISTER 3
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
DIFF47(1)
SIGN47(1)
DIFF46(1)
SIGN46(1)
DIFF45(1)
SIGN45(1)
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
DIFF41(1)
SIGN41(1)
DIFF40(1)
SIGN40(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIFF39(1)
SIGN39(1)
DIFF38(1)
SIGN38(1)
DIFF37(1)
SIGN37(1)
DIFF36(1)
SIGN36(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
DIFF35(1)
SIGN35(1)
DIFF34(1)
SIGN34(1)
DIFF33(1)
SIGN33(1)
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
DIFF47: AN47 Mode bit(1)
1 = Selects AN47 differential input pair as AN47+ and AN10 = AN47 is using Single-ended mode
bit 30
SIGN47: AN47 Signed Data Mode bit(1)
1 = AN41 is using Signed Data mode
0 = AN41 is using Unsigned Data mode
bit 29
DIFF46: AN46 Mode bit(1)
1 = Selects AN46 differential input pair as AN46+ and AN10 = AN41 is using Single-ended mode
bit 28
SIGN46: AN46 Signed Data Mode bit(1)
1 = AN46 is using Signed Data mode
0 = AN46 is using Unsigned Data mode
bit 27
DIFF45: AN45 Mode bit(1)
1 = Selects AN45 differential input pair as AN45+ and AN10 = AN45 is using Single-ended mode
bit 26
SIGN46: AN45 Signed Data Mode bit(1)
1 = AN45 is using Signed Data mode
0 = AN45 is using Unsigned Data mode
bit 25-20
Unimplemented: Read as ‘0’
bit 19
DIFF41: AN41 Mode bit(1)
1 = Selects AN41 differential input pair as AN41+ and AN10 = AN41 is using Single-ended mode
bit 18
SIGN41: AN41 Signed Data Mode bit(1)
1 = AN41 is using Signed Data mode
0 = AN41 is using Unsigned Data mode
bit 17
DIFF40: AN40 Mode bit(1)
1 = Selects AN40 differential input pair as AN40+ and AN10 = AN40 is using Single-ended mode
bit 16
SIGN40: AN40 Signed Data Mode bit(1)
1 = AN40 is using Signed Data mode
0 = AN40 is using Unsigned Data mode
Note 1:
x = Bit is unknown
This bit is not available on 64-pin devices.
2019-2020 Microchip Technology Inc.
DS60001570C-page 329
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-7:
ADCIMCON3: ADC INPUT MODE CONTROL REGISTER 3 (CONTINUED)
bit 15
DIFF39: AN39 Mode bit(1)
1 = Selects AN39 differential input pair as AN39+ and AN10 = AN39 is using Single-ended mode
bit 14
SIGN39: AN39 Signed Data Mode bit(1)
1 = AN39 is using Signed Data mode
0 = AN39 is using Unsigned Data mode
bit 13
DIFF38: AN38 Mode bit(1)
1 = Selects AN38 differential input pair as AN38+ and AN10 = AN38 is using Single-ended mode
bit 12
SIGN38: AN38 Signed Data Mode bit(1)
1 = AN38 is using Signed Data mode
0 = AN38 is using Unsigned Data mode
bit 11
DIFF37: AN37 Mode bit(1)
1 = Selects AN37 differential input pair as AN37+ and AN10 = AN37 is using Single-ended mode
bit 10
SIGN37: AN37 Signed Data Mode bit(1)
1 = AN37 is using Signed Data mode
0 = AN37 is using Unsigned Data mode
bit 9
DIFF36: AN36 Mode bit(1)
1 = Selects AN36 differential input pair as AN36+ and AN10 = AN36 is using Single-ended mode
bit 8
SIGN36: AN36 Signed Data Mode bit(1)
1 = AN36 is using Signed Data mode
0 = AN36 is using Unsigned Data mode
bit 7
DIFF35: AN35 Mode bit(1)
1 = Selects AN35 differential input pair as AN35+ and AN10 = AN35 is using Single-ended mode
bit 6
SIGN35: AN35 Signed Data Mode bit(1)
1 = AN35 is using Signed Data mode
0 = AN35 is using Unsigned Data mode
bit 5
DIFF34: AN34 Mode bit(1)
1 = Selects AN34 differential input pair as AN34+ and AN10 = AN34 is using Single-ended mode
bit 4
SIGN34: AN34 Signed Data Mode bit(1)
1 = AN34 is using Signed Data mode
0 = AN34 is using Unsigned Data mode
bit 3
DIFF33: AN33 Mode bit(1)
1 = Selects AN33 differential input pair as AN33+ and AN10 = AN33 is using Single-ended mode
bit 2
SIGN33: AN33 Signed Data Mode bit(1)
1 = AN33 is using Signed Data mode
0 = AN33 is using Unsigned Data mode
bit 1-0
Unimplemented: Read as ‘0’
Note 1:
This bit is not available on 64-pin devices.
DS60001570C-page 330
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-8:
Bit Range
31:24
23:16
15:8
7:0
ADCIMCON4: ADC INPUT MODE CONTROL REGISTER 4
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
DIFF49
SIGN49
DIFF48
SIGN48
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-4
Unimplemented: Read as ‘0’
bit 3
DIFF49: AN49 Mode bit
1 = Selects AN49 differential input pair as AN49+ and AN10 = AN49 is using Single-ended mode
bit 2
SIGN49: AN41 Signed Data Mode bit
1 = AN49 is using Signed Data mode
0 = AN49 is using Unsigned Data mode
bit 1
DIFF48: AN48 Mode bit
1 = Selects AN40 differential input pair as AN48+ and AN10 = AN48 is using Single-ended mode
bit 0
SIGN48: AN48 Signed Data Mode bit
1 = AN48 is using Signed Data mode
0 = AN48 is using Unsigned Data mode
2019-2020 Microchip Technology Inc.
x = Bit is unknown
DS60001570C-page 331
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-9:
Bit
Range
31:24
23:16
15:8
7:0
ADCGIRQEN1: ADC GLOBAL INTERRUPT ENABLE REGISTER 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
AGIEN27
AGIEN26
AGIEN25
AGIEN24
R/W-0
R/W-0
R/W-0
R/W-0
AGIEN23(1) AGIEN22(1) AGIEN21(1) AGIEN20(1)
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
AGIEN19
AGIEN18
AGIEN17
AGIEN16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AGIEN15
AGIEN14
AGIEN13
AGIEN12
AGIEN11
AGIEN10
AGIEN9
AGIEN8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AGIEN7
AGIEN6
AGIEN5
AGIEN4
AGIEN3
AGIEN2
AGIEN1
AGIEN0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 Unimplemented: Read as ‘0’
bit 27-0
AGIEN27:AGIEN0: ADC Global Interrupt Enable bits
1 = Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data
is ready (indicated by the AIRDYx bit of the ADCDSTAT1 register)
0 = Interrupts are disabled
Note 1:
This bit is not available on 64-pin devices.
DS60001570C-page 332
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-10: ADCGIRQEN2: ADC GLOBAL INTERRUPT ENABLE REGISTER 2
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
AGIEN53
—
—
AGIEN50
AGIEN49
AGIEN48
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
AGIEN47(1)
AGIEN46(1)
AGIEN45(1)
—
—
—
AGIEN41(1)
AGIEN40(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
AGIEN39(1) AGIEN38(1) AGIEN37(1) AGIEN36(1) AGIEN35(1) AGIEN34(1) AGIEN33(1)
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-22 Unimplemented: Read as ‘0’
bit 21
AGIEN53: ADC Global Interrupt Enable bit
1 = Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data
is ready (indicated by the AIRDYx bit of the ADCDSTAT2 register)
0 = Interrupts are disabled
bit 20-19 Unimplemented: Read as `0’
bit 18-13 AGIEN50: AGIEN45: ADC Global Interrupt Enable bits
1 = Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data
is ready (indicated by the AIRDYx bit of the ADCDSTAT2 register)
0 = Interrupts are disabled
bit 12-10 Unimplemented: Read as ‘0’
bit 9-1
AGIEN41:AGIEN33 ADC Global Interrupt Enable bits
1 = Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data
is ready (indicated by the AIRDYx bit of the ADCDSTAT2 register)
0 = Interrupts are disabled
bit 0
Unimplemented: Read as ‘0’
Note 1:
This bit is not available on 64-pin devices.
2019-2020 Microchip Technology Inc.
DS60001570C-page 333
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-11: ADCCSS1: ADC COMMON SCAN SELECT REGISTER 1
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
CSS27
CSS26
CSS25
CSS24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS23(1)
CSS22(1)
CSS21(1)
CSS20(1)
CSS19
CSS18
CSS17
CSS16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS15
CSS14
CSS13
CSS12
CSS11
CSS10
CSS9
CSS8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS7
CSS6
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-28
Unimplemented: Read as ‘0’
bit 27-0
CSS27:CSS0: Analog Common Scan Select bits
x = Bit is unknown
Analog inputs AN27-AN6 are always Class 3 shared ADC7.
1 = Select ANx for input scan (i.e., ANx = CSSx and scan is sequential starting with the lowest to highest
enabled CSSx analog input pin)
0 = Skip ANx for input scan
Note 1:
This bit is not available on 64-pin devices.
Note 1:
In addition to setting the appropriate bits in this register, Class 1 and Class 2 analog inputs must select the
STRIG input as the trigger source if they are to be scanned through the CSSx bits. Refer to the bit
descriptions in the ADCTRGx registers for selecting the STRIG option.
If a Class 1 or Class 2 input is included in the scan by setting the CSSx bit to ‘1’ and by setting the
TRGSRCx bits to STRIG mode (‘0b11), the user application must ensure that no other triggers are
generated for that input using the RQCNVRT bit in the ADCCON3 register or the hardware input or any
digital filter. Otherwise, the scan behavior is unpredictable.
2:
DS60001570C-page 334
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-12: ADCCSS2: ADC COMMON SCAN SELECT REGISTER 2
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
CSS53(2)
—
—
CSS50(2)
CSS49
CSS48
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
CSS47(1)
CSS46(1)
CSS45(1)
—
CSS41(1)
CSS40(1)
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
CSS39(1)
CSS38(1)
CSS37(1)
CSS36(1)
CSS35(1)
CSS34(1)
CSS33(1)
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-22
Unimplemented: Read as ‘0’
bit 21
CSS53: Analog Common Scan Select bits
1 = Select ANx for input scan
0 = Skip ANx for input scan
bit 20-19
Unimplemented: Read as ‘0’
bit 18-13
CSS50:CSS45: Analog Common Scan Select bits
bit 12-10
Unimplemented: Read as ‘0’
bit 9-1
CSS41:CSS33: Analog Common Scan Select bits
1 = Select ANx for input scan
0 = Skip ANx for input scan
bit 0
Unimplemented: Read as ‘0’
Note 1:
2:
x = Bit is unknown
This bit is not available on 64-pin devices.
CSS50-CSS53 are internal analog inputs with respect to internal (IVREF, and CTMU) Temperature Sensor.
2019-2020 Microchip Technology Inc.
DS60001570C-page 335
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-13: ADCDSTAT1: ADC DATA READY STATUS REGISTER 1
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
—
—
—
—
AIRDY27
AIRDY26
AIRDY25
AIRDY24
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
AIRDY23(1) AIRDY22(1) AIRDY21(1) AIRDY20(1)
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
AIRDY19
AIRDY18
AIRDY17
AIRDY16
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
AIRDY15
AIRDY14
AIRDY13
AIRDY12
AIRDY11
AIRDY10
AIRDY9
AIRDY8
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
AIRDY7
AIRDY6
AIRDY5
AIRDY4
AIRDY3
AIRDY2
AIRDY1
AIRDY0
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Set
W = Writable bit
‘1’ = Bit is set
HC = Hardware Cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 Unimplemented: Read as ‘0’
bit 27-0 AIRDY27:AIRDY0: Conversion Data Ready for Corresponding Analog Input Ready bits
1 = This bit is set when converted data is ready in the data register
0 = This bit is cleared when the associated data register is read
Note 1:
This bit is not available on 64-pin devices.
REGISTER 23-14: ADCDSTAT2: ADC DATA READY STATUS REGISTER 2
Bit
Range
31:24
23:16
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
—
—
AIRDY53
AIRDY52
AIRDY51
AIRDY50
AIRDY49
AIRDY48
15:8
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
U-0
U-0
U-0
R-0, HS, HC
R-0, HS, HC
AIRDY47(1) AIRDY46(1) AIRDY45(1)
—
—
—
AIRDY41(1) AIRDY40(1)
7:0
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
U-0
AIRDY39(1) AIRDY38(1) AIRDY37(1) AIRDY36(1) AIRDY35(1) AIRDY34(1) AIRDY33(1)
—
R-0, HS, HC
Legend:
R = Readable bit
-n = Value at POR
R-0, HS, HC
R-0, HS, HC
HS = Hardware Set
W = Writable bit
‘1’ = Bit is set
HC = Hardware Cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-22 Unimplemented: Read as ‘0’
bit 23-13 AIRDY53:AIRDY45: Conversion Data Ready for Corresponding Analog Input Ready bits
1 = This bit is set when converted data is ready in the data register
0 = This bit is cleared when the associated data register is read
bit 12-10 Unimplemented: Read as ‘0’
bit 23-13 AIRDY41:AIRDY33: Conversion Data Ready for Corresponding Analog Input Ready bits
1 = This bit is set when converted data is ready in the data register
0 = This bit is cleared when the associated data register is read
Note 1:
This bit is not available on 64-pin devices.
DS60001570C-page 336
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-15: ADCCMPENx: ADC DIGITAL COMPARATOR ‘x’ ENABLE REGISTER
(‘x’ = 1 THROUGH 4)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
CMPE27
CMPE26
CMPE25
CMPE24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPE23(1)
CMPE22(1)
CMPE21(1)
CMPE20(1)
CMPE19
CMPE18
CMPE17
CMPE16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPE15
CMPE14
CMPE13
CMPE12
CMPE11
CMPE10
CMPE9
CMPE8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPE7
CMPE6
CMPE5
CMPE4
CMPE3
CMPE2
CMPE1
CMPE0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 Unimplemented: Read as ‘0’
bit 27-0 CMPE27:CMPE0: ADC Digital Comparator ’x’ Enable bits
These bits enable conversion results corresponding to the Analog Input to be processed by the Digital
Comparator. CMPE0 enables AN0, CMPE1 enables AN1, and so on.
Note 1:
This bit is not available on 64-pin devices.
Note 1:
2:
CMPEx = ANx, where ’x’ = 0-31 (Digital Comparator inputs are limited to AN0 through AN31).
Changing the bits in this register while the Digital Comparator is enabled (ENDCMP = 1) can result in
unpredictable behavior.
2019-2020 Microchip Technology Inc.
DS60001570C-page 337
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-16: ADCCMPx: ADC DIGITAL COMPARATOR ‘x’ LIMIT VALUE REGISTER
(‘x’ = 1 THROUGH 4)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
bit 15-0
Note 1:
2:
3:
R/W-0
Bit
Bit
27/19/11/3 26/18/10/2
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCMPHI(1,2,3)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCMPHI
R/W-0
R/W-0
R/W-0
R/W-0
(1,2,3)
R/W-0
DCMPLO(1,2,3)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCMPLO(1,2,3)
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
Bit
28/20/12/4
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DCMPHI: Digital Comparator ’x’ High Limit Value bits(1,2,3)
These bits store the high limit value, which is used by digital comparator for comparisons with ADC
converted data.
DCMPLO: Digital Comparator ’x’ Low Limit Value bits(1,2,3)
These bits store the low limit value, which is used by digital comparator for comparisons with ADC
converted data.
Changing theses bits while the Digital Comparator is enabled (ENDCMP = 1) can result in unpredictable
behavior.
The format of the limit values should match the format of the ADC converted value in terms of sign and
fractional settings.
For Digital Comparator 0 used in CVD mode, the DCMPHI and DCMPLO bits must always
be specified in signed format, as the CVD output data is differential and is always signed.
DS60001570C-page 338
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-17: ADCFLTRx: ADC DIGITAL FILTER ‘x’ REGISTER
(‘x’ = 1 THROUGH 6)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
R/W-0
Bit
Bit
27/19/11/3 26/18/10/2
R/W-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
AFEN
DATA16EN
DFMODE
U-0
U-0
U-0
—
—
—
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
OVRSAM
R/W-0
R/W-0
R/W-0
R/W-0
R-0, HS, HC
AFGIEN
AFRDY
R/W-0
R/W-0
CHNLID
R-0, HS, HC
FLTRDATA
R-0, HS, HC
FLTRDATA
Legend:
HS = Hardware Set
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
AFEN: Digital Filter ’x’ Enable bit
1 = Digital filter is enabled
0 = Digital filter is disabled and the AFRDY status bit is cleared
NOTE: If ADCFLTRx = 1 then ADCxTIME minimum must be ≥ to 0x004 or equivalent to
≥ 6 TAD. This will correspondingly reduce the maximum sampling rate.
bit 30
DATA16EN: Filter Significant Data Length bit
1 = All 16 bits of the filter output data are significant
0 = Only the first 12 bits are significant, followed by four zeros
Note: This bit is significant only if DFMODE = 1 (Averaging Mode) and FRACT (ADCCON1) = 1
(Fractional Output Mode).
bit 29
DFMODE: ADC Filter Mode bit
1 = Filter ’x’ works in Averaging mode
0 = Filter ’x’ works in Oversampling Filter mode (default)
bit 28-26 OVRSAM: Oversampling Filter Ratio bits
If DFMODE is ‘0’:
111 = 128 samples (shift sum 3 bits to right, output data is in 15.1 format)
110 = 32 samples (shift sum 2 bits to right, output data is in 14.1 format)
101 = 8 samples (shift sum 1 bit to right, output data is in 13.1 format)
100 = 2 samples (shift sum 0 bits to right, output data is in 12.1 format)
011 = 256 samples (shift sum 4 bits to right, output data is 16 bits)
010 = 64 samples (shift sum 3 bits to right, output data is 15 bits)
001 = 16 samples (shift sum 2 bits to right, output data is 14 bits)
000 = 4 samples (shift sum 1 bit to right, output data is 13 bits)
If DFMODE is ‘1’:
111 = 256 samples (256 samples to be averaged)
110 = 128 samples (128 samples to be averaged)
101 = 64 samples (64 samples to be averaged)
100 = 32 samples (32 samples to be averaged)
011 = 16 samples (16 samples to be averaged)
010 = 8 samples (8 samples to be averaged)
001 = 4 samples (4 samples to be averaged)
000 = 2 samples (2 samples to be averaged)
Note 1:
This selection is not available on 64-pin devices.
2019-2020 Microchip Technology Inc.
DS60001570C-page 339
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-17: ADCFLTRx: ADC DIGITAL FILTER ‘x’ REGISTER
(‘x’ = 1 THROUGH 6) (CONTINUED)
bit 25
AFGIEN: Digital Filter ’x’ Interrupt Enable bit
1 = Digital filter interrupt is enabled and is generated by the AFRDY status bit
0 = Digital filter is disabled
bit 24
AFRDY: Digital Filter ’x’ Data Ready Status bit
1 = Data is ready in the FLTRDATA bits
0 = Data is not ready
Note:
This bit is cleared by reading the FLTRDATA bits or by disabling the Digital Filter module
(by setting AFEN to ‘0’).
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 CHNLID: Digital Filter Analog Input Selection bits
These bits specify the analog input to be used as the oversampling filter data source.
11111 = Reserved
•
•
•
11100 = Reserved
11011 = AN27 input
11010 = AN26 input
11001 = AN25 input
11000 = AN24 input
10111 = AN23(1) input
10110 = AN22(1) input
10101 = AN21(1) input
10100 = AN20(1) input
10011 = AN19 input
•
•
•
10110 = AN6 input
00101 = ADC5 Module
00100 = ADC4 Module
00011 = ADC3 Module
00010 = ADC2 Module
00001 = ADC1 Module
00000 = ADC0 Module
Note:
Only the first 32 analog inputs (Class 1 and Class 2) can use a digital filter.
bit 15-0
FLTRDATA: Digital Filter ’x’ Data Output Value bits
The filter output data is as per the fractional format set in the FRACT (ADCCON1) bit. The FRACT bit
should not be changed while the filter is enabled. Changing the state of the FRACT bit after the operation
of the filter ended will not update the value of FLTRDATA to reflect the new format.
Note 1:
This selection is not available on 64-pin devices.
DS60001570C-page 340
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-18: ADCTRG1: ADC TRIGGER SOURCE 1 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
TRGSRC3
R/W-0
R/W-0
R/W-0
TRGSRC2
R/W-0
R/W-0
R/W-0
TRGSRC1
R/W-0
R/W-0
R/W-0
TRGSRC0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC3: Trigger Source for Conversion of ADC3 Module Select bits
11111 = Reserved
11110 = PWM Generator 7 Current-Limit(1)
11101 = PWM Generator 6 Current-Limit(1)
11100 = PWM Generator 5 Current-Limit(1)
11011 = PWM Generator 4 Current-Limit(1)
11010 = PWM Generator 3 Current-Limit(1)
11001 = PWM Generator 2 Current-Limit(1)
11000 = PWM Generator 1 Current-Limit(1)
10111 = PWM Generator 9 trigger(1)
10110 = PWM Generator 8 trigger(1)
10101 = PWM Generator 7 trigger(1)
10100 = Reserved
10011 = Output Compare 4 rising edge
10010 = Output Compare 3 rising edge
10001 = Output Compare 2 rising edge
10000 = Output Compare 1 rising edge
01111 = PWM Generator 6 trigger(1)
01110 = PWM Generator 5 trigger(1)
01101 = PWM Generator 4 trigger(1)
01100 = PWM Generator 3 trigger(1)
01011 = PWM Generator 2 trigger(1)
01010 = PWM Generator 1 trigger(1)
01001 = Secondary Special Event Trigger(1)
01000 = Primary Special Event Trigger(1)
00111 = General Purpose Timer5
00110 = General Purpose Timer3
00101 = General Purpose Timer1
00100 = INT0
00011 = Scan trigger(2)
00010 = Software level trigger (must also configure the ADCTRGNS register)
00001 = Software edge trigger
00000 = No Trigger
Note 1:
2:
The PWM bit definitions are only applicable to PIC32MKXXXMCXX Motor Control devices.
For Scan Trigger, in addition to setting the trigger, it also requires programming of the STRGSRC
bits (ADCCON1) to select the trigger source, and requires the appropriate CSS bits to be set in
the ADCCSSx registers.
2019-2020 Microchip Technology Inc.
DS60001570C-page 341
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-18: ADCTRG1: ADC TRIGGER SOURCE 1 REGISTER
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC2: Trigger Source for Conversion of ADC2 Module Select bits
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TRGSRC1: Trigger Source for Conversion of ADC1 Module Select bits
See bits 28-24 for bit value definitions.
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
TRGSRC0: Trigger Source for Conversion of ADC0 Module Select bits
See bits 28-24 for bit value definitions.
Note 1:
2:
The PWM bit definitions are only applicable to PIC32MKXXXMCXX Motor Control devices.
For Scan Trigger, in addition to setting the trigger, it also requires programming of the STRGSRC
bits (ADCCON1) to select the trigger source, and requires the appropriate CSS bits to be set in
the ADCCSSx registers.
DS60001570C-page 342
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-19: ADCTRG2: ADC TRIGGER SOURCE 2 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC6
R/W-0
TRGSRC5
R/W-0
R/W-0
R/W-0
TRGSRC4
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC7: Trigger Source for Conversion of Analog Input AN7 Select bits
11111 = Reserved
11110 = PWM Generator 12 trigger(1)
11101 = PWM Generator 11 trigger(1)
11100 = PWM Generator 10 trigger(1)
11011 = PWM Generator 4 Current-Limit(1)
11010 = PWM Generator 3 Current-Limit(1)
11001 = PWM Generator 2 Current-Limit(1)
11000 = PWM Generator 1 Current-Limit(1)
10111 = PWM Generator 9 trigger(1)
10110 = PWM Generator 8 trigger(1)
10101 = PWM Generator 7 trigger(1)
10100 = CTMU trip
10011 = Output Compare 4 rising edge
10010 = Output Compare 3 rising edge
10001 = Output Compare 2 rising edge
10000 = Output Compare 1 rising edge
01111 = PWM Generator 6 trigger(1)
01110 = PWM Generator 5 trigger(1)
01101 = PWM Generator 4 trigger(1)
01100 = PWM Generator 3 trigger(1)
01011 = PWM Generator 2 trigger(1)
01010 = PWM Generator 1 trigger(1)
01001 = Secondary Special Event Trigger(1)
01000 = Primary Special Event Trigger(1)
00111 = General Purpose Timer5
00110 = General Purpose Timer3
00101 = General Purpose Timer1
00100 = INT0
00011 = Scan trigger(2)
00010 = Software level trigger (must also configure the ADCTRGNS register)
00001 = Software edge trigger
00000 = No trigger
Note 1:
2:
The PWM bit definitions are only applicable to PIC32MKXXMCXX Motor Control devices.
For Scan Trigger, in addition to setting the trigger, it also requires programming of the STRGSRC
bits (ADCCON1) to select the trigger source, and requires the appropriate CSS bits to be set in
the ADCCSSx registers.
2019-2020 Microchip Technology Inc.
DS60001570C-page 343
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-19: ADCTRG2: ADC TRIGGER SOURCE 2 REGISTER
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC6: Trigger Source for Conversion of Analog Input AN6 Select bits
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8
TRGSRC5: Trigger Source for Conversion of ADC5 Module Select bits
See bits 28-24 for bit value definitions.
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
TRGSRC4: Trigger Source for Conversion of ADC4 Module Select bits
See bits 28-24 for bit value definitions.
Note 1:
2:
The PWM bit definitions are only applicable to PIC32MKXXMCXX Motor Control devices.
For Scan Trigger, in addition to setting the trigger, it also requires programming of the STRGSRC
bits (ADCCON1) to select the trigger source, and requires the appropriate CSS bits to be set in
the ADCCSSx registers.
DS60001570C-page 344
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-20: ADCTRG3: ADC TRIGGER SOURCE 3 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
TRGSRC11
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC10
R/W-0
TRGSRC9
R/W-0
R/W-0
R/W-0
TRGSRC8
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC11: Trigger Source for Conversion of Analog Input AN11 Select bits
11111 = Reserved
11110 = PWM Generator 12 trigger(1)
11101 = PWM Generator 11 trigger(1)
11100 = PWM Generator 10 trigger(1)
11011 = PWM Generator 4 Current-Limit(1)
11010 = PWM Generator 3 Current-Limit(1)
11001 = PWM Generator 2 Current-Limit(1)
11000 = PWM Generator 1 Current-Limit(1)
10111 = PWM Generator 9 trigger(1)
10110 = PWM Generator 8 trigger(1)
10101 = PWM Generator 7 trigger(1)
10100 = CTMU trip
10011 = Output Compare 4 rising edge
10010 = Output Compare 3 rising edge
10001 = Output Compare 2 rising edge
10000 = Output Compare 1 rising edge
01111 = PWM Generator 6 trigger(1)
01110 = PWM Generator 5 trigger(1)
01101 = PWM Generator 4 trigger(1)
01100 = PWM Generator 3 trigger(1)
01011 = PWM Generator 2 trigger(1)
01010 = PWM Generator 1 trigger(1)
01001 = Secondary Special Event Trigger(1)
01000 = Primary Special Event Trigger(1)
00111 = General Purpose Timer5
00110 = General Purpose Timer3
00101 = General Purpose Timer1
00100 = INT0
00011 = Scan trigger(2)
00010 = Software level trigger (must also configure the ADCTRGNS register)
00001 = Software edge trigger
00000 = No trigger
Note 1:
2:
The PWM bit definitions are only applicable to PIC32MKXXMCXX Motor Control devices.
For Scan Trigger, in addition to setting the trigger, it also requires programming of the STRGSRC
bits (ADCCON1) to select the trigger source, and requires the appropriate CSS bits to be set in
the ADCCSSx registers.
2019-2020 Microchip Technology Inc.
DS60001570C-page 345
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-20: ADCTRG3: ADC TRIGGER SOURCE 3 REGISTER
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC10: Trigger Source for Conversion of Analog Input AN10 Select bits
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8
TRGSRC9: Trigger Source for Conversion of Analog Input AN9 Select bits
See bits 28-24 for bit value definitions.
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
TRGSRC8: Trigger Source for Conversion of Analog Input AN8 Select bits
See bits 28-24 for bit value definitions.
Note 1:
2:
The PWM bit definitions are only applicable to PIC32MKXXMCXX Motor Control devices.
For Scan Trigger, in addition to setting the trigger, it also requires programming of the STRGSRC
bits (ADCCON1) to select the trigger source, and requires the appropriate CSS bits to be set in
the ADCCSSx registers.
DS60001570C-page 346
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-21: ADCTRG4: ADC TRIGGER SOURCE 4 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
TRGSRC15
R/W-0
R/W-0
R/W-0
TRGSRC14
R/W-0
R/W-0
R/W-0
TRGSRC13
R/W-0
R/W-0
R/W-0
TRGSRC12
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC15: Trigger Source for Conversion of Analog Input AN15 Select bits
11111 = Reserved
11110 = PWM Generator 12 trigger(1)
11101 = PWM Generator 11 trigger(1)
11100 = PWM Generator 10 trigger(1)
11011 = PWM Generator 4 Current-Limit(1)
11010 = PWM Generator 3 Current-Limit(1)
11001 = PWM Generator 2 Current-Limit(1)
11000 = PWM Generator 1 Current-Limit(1)
10111 = PWM Generator 9 trigger(1)
10110 = PWM Generator 8 trigger(1)
10101 = PWM Generator 7 trigger(1)
10100 = CTMU trip
10011 = Output Compare 4 rising edge
10010 = Output Compare 3 rising edge
10001 = Output Compare 2 rising edge
10000 = Output Compare 1 rising edge
01111 = PWM Generator 6 trigger(1)
01110 = PWM Generator 5 trigger(1)
01101 = PWM Generator 4 trigger(1)
01100 = PWM Generator 3 trigger(1)
01011 = PWM Generator 2 trigger(1)
01010 = PWM Generator 1 trigger(1)
01001 = Secondary Special Event Trigger(1)
01000 = Primary Special Event Trigger(1)
00111 = General Purpose Timer5
00110 = General Purpose Timer3
00101 = General Purpose Timer1
00100 = INT0
00011 = Scan trigger(2)
00010 = Software level trigger (must also configure the ADCTRGNS register)
00001 = Software edge trigger
00000 = No trigger
Note 1:
2:
The PWM bit definitions are only applicable to PIC32MKXXMCXX Motor Control devices.
For Scan Trigger, in addition to setting the trigger, it also requires programming of the STRGSRC
bits (ADCCON1) to select the trigger source, and requires the appropriate CSS bits to be set in
the ADCCSSx registers.
2019-2020 Microchip Technology Inc.
DS60001570C-page 347
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-21: ADCTRG4: ADC TRIGGER SOURCE 4 REGISTER
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC14: Trigger Source for Conversion of Analog Input AN14 Select bits
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8
TRGSRC13: Trigger Source for Conversion of Analog Input AN13 Select bits
See bits 28-24 for bit value definitions.
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
TRGSRC12: Trigger Source for Conversion of Analog Input AN12 Select bits
See bits 28-24 for bit value definitions.
Note 1:
2:
The PWM bit definitions are only applicable to PIC32MKXXMCXX Motor Control devices.
For Scan Trigger, in addition to setting the trigger, it also requires programming of the STRGSRC
bits (ADCCON1) to select the trigger source, and requires the appropriate CSS bits to be set in
the ADCCSSx registers.
DS60001570C-page 348
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-22: ADCTRG5: ADC TRIGGER SOURCE 5 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
TRGSRC19(3)
R/W-0
R/W-0
R/W-0
TRGSRC18
R/W-0
R/W-0
R/W-0
TRGSRC17
R/W-0
R/W-0
R/W-0
TRGSRC16
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC19: Trigger Source for Conversion of Analog Input AN19 Select bits(3)
11111 = Reserved
11110 = PWM Generator 12 trigger(1)
11101 = PWM Generator 11 trigger(1)
11100 = PWM Generator 10 trigger(1)
11011 = PWM Generator 4 Current-Limit(1)
11010 = PWM Generator 3 Current-Limit(1)
11001 = PWM Generator 2 Current-Limit(1)
11000 = PWM Generator 1 Current-Limit(1)
10111 = PWM Generator 9 trigger(1)
10110 = PWM Generator 8 trigger(1)
10101 = PWM Generator 7 trigger(1)
10100 = CTMU trip
10011 = Output Compare 4 rising edge
10010 = Output Compare 3 rising edge
10001 = Output Compare 2 rising edge
10000 = Output Compare 1 rising edge
01111 = PWM Generator 6 trigger(1)
01110 = PWM Generator 5 trigger(1)
01101 = PWM Generator 4 trigger(1)
01100 = PWM Generator 3 trigger(1)
01011 = PWM Generator 2 trigger(1)
01010 = PWM Generator 1 trigger(1)
01001 = Secondary Special Event Trigger(1)
01000 = Primary Special Event Trigger(1)
00111 = General Purpose Timer5
00110 = General Purpose Timer3
00101 = General Purpose Timer1
00100 = INT0
00011 = Scan trigger(2)
00010 = Software level trigger (must also configure the ADCTRGNS register)
00001 = Software edge trigger
00000 = No trigger
Note 1:
2:
3:
The PWM bit definitions are only applicable to PIC32MKXXMCXX Motor Control devices.
For Scan Trigger, in addition to setting the trigger, it also requires programming of the STRGSRC
bits (ADCCON1) to select the trigger source, and requires the appropriate CSS bits to be set in
the ADCCSSx registers.
These bits are not available on 64-pin devices.
2019-2020 Microchip Technology Inc.
DS60001570C-page 349
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-22: ADCTRG5: ADC TRIGGER SOURCE 5 REGISTER
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC18: Trigger Source for Conversion of Analog Input AN18 Select bits
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TRGSRC17: Trigger Source for Conversion of Analog Input AN17 Select bits
See bits 28-24 for bit value definitions.
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
TRGSRC16: Trigger Source for Conversion of Analog Input AN16 Select bits
See bits 28-24 for bit value definitions.
Note 1:
2:
3:
The PWM bit definitions are only applicable to PIC32MKXXMCXX Motor Control devices.
For Scan Trigger, in addition to setting the trigger, it also requires programming of the STRGSRC
bits (ADCCON1) to select the trigger source, and requires the appropriate CSS bits to be set in
the ADCCSSx registers.
These bits are not available on 64-pin devices.
DS60001570C-page 350
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-23: ADCTRG6: ADC TRIGGER SOURCE 6 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
TRGSRC23
R/W-0
R/W-0
R/W-0
TRGSRC22
R/W-0
R/W-0
R/W-0
TRGSRC21
R/W-0
R/W-0
R/W-0
TRGSRC20
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC23: Trigger Source for Conversion of Analog Input AN23 Select bits
11111 = Reserved
11110 = PWM Generator 12 trigger(1)
11101 = PWM Generator 11 trigger(1)
11100 = PWM Generator 10 trigger(1)
11011 = PWM Generator 4 Current-Limit(1)
11010 = PWM Generator 3 Current-Limit(1)
11001 = PWM Generator 2 Current-Limit(1)
11000 = PWM Generator 1 Current-Limit(1)
10111 = PWM Generator 9 trigger(1)
10110 = PWM Generator 8 trigger(1)
10101 = PWM Generator 7 trigger(1)
10100 = CTMU trip
10011 = Output Compare 4 rising edge
10010 = Output Compare 3 rising edge
10001 = Output Compare 2 rising edge
10000 = Output Compare 1 rising edge
01111 = PWM Generator 6 trigger(1)
01110 = PWM Generator 5 trigger(1)
01101 = PWM Generator 4 trigger(1)
01100 = PWM Generator 3 trigger(1)
01011 = PWM Generator 2 trigger(1)
01010 = PWM Generator 1 trigger(1)
01001 = Secondary Special Event Trigger(1)
01000 = Primary Special Event Trigger(1)
00111 = General Purpose Timer5
00110 = General Purpose Timer3
00101 = General Purpose Timer1
00100 = INT0
00011 = Scan trigger(2)
00010 = Software level trigger (must also configure the ADCTRGNS register)
00001 = Software edge trigger
00000 = No trigger
Note 1:
2:
Note:
The PWM bit definitions are only applicable to PIC32MKXXMCXX Motor Control devices.
For Scan Trigger, in addition to setting the trigger, it also requires programming of the STRGSRC
bits (ADCCON1) to select the trigger source, and requires the appropriate CSS bits to be set in
the ADCCSSx registers.
This register is not available on 64-pin devices.
2019-2020 Microchip Technology Inc.
DS60001570C-page 351
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-23: ADCTRG6: ADC TRIGGER SOURCE 6 REGISTER
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC22: Trigger Source for Conversion of Analog Input AN22 Select bits
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TRGSRC21: Trigger Source for Conversion of Analog Input AN21 Select bits
See bits 28-24 for bit value definitions.
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
TRGSRC20: Trigger Source for Conversion of Analog Input AN20 Select bits
See bits 28-24 for bit value definitions.
Note 1:
2:
Note:
The PWM bit definitions are only applicable to PIC32MKXXMCXX Motor Control devices.
For Scan Trigger, in addition to setting the trigger, it also requires programming of the STRGSRC
bits (ADCCON1) to select the trigger source, and requires the appropriate CSS bits to be set in
the ADCCSSx registers.
This register is not available on 64-pin devices.
DS60001570C-page 352
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-24: ADCTRG7: ADC TRIGGER SOURCE 7 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
TRGSRC27
R/W-0
R/W-0
R/W-0
TRGSRC26
R/W-0
R/W-0
R/W-0
TRGSRC25
R/W-0
R/W-0
R/W-0
TRGSRC24
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC27: Trigger Source for Conversion of Analog Input AN27 Select bits
11111 = Reserved
11110 = PWM Generator 12 trigger(1)
11101 = PWM Generator 11 trigger(1)
11100 = PWM Generator 10 trigger(1)
11011 = PWM Generator 4 Current-Limit(1)
11010 = PWM Generator 3 Current-Limit(1)
11001 = PWM Generator 2 Current-Limit(1)
11000 = PWM Generator 1 Current-Limit(1)
10111 = PWM Generator 9 trigger(1)
10110 = PWM Generator 8 trigger(1)
10101 = PWM Generator 7 trigger(1)
10100 = CTMU trip
10011 = Output Compare 4 rising edge
10010 = Output Compare 3 rising edge
10001 = Output Compare 2 rising edge
10000 = Output Compare 1 rising edge
01111 = PWM Generator 6 trigger(1)
01110 = PWM Generator 5 trigger(1)
01101 = PWM Generator 4 trigger(1)
01100 = PWM Generator 3 trigger(1)
01011 = PWM Generator 2 trigger(1)
01010 = PWM Generator 1 trigger(1)
01001 = Secondary Special Event Trigger(1)
01000 = Primary Special Event Trigger(1)
00111 = General Purpose Timer5
00110 = General Purpose Timer3
00101 = General Purpose Timer1
00100 = INT0
00011 = Scan trigger(2)
00010 = Software level trigger (must also configure the ADCTRGNS register)
00001 = Software edge trigger
00000 = No trigger
Note 1:
2:
Note:
The PWM bit definitions are only applicable to PIC32MKXXMCXX Motor Control devices.
For Scan Trigger, in addition to setting the trigger, it also requires programming of the STRGSRC
bits (ADCCON1) to select the trigger source, and requires the appropriate CSS bits to be set in
the ADCCSSx registers.
This register is not available on 64-pin devices.
2019-2020 Microchip Technology Inc.
DS60001570C-page 353
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-24: ADCTRG7: ADC TRIGGER SOURCE 7 REGISTER
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC26: Trigger Source for Conversion of Analog Input AN26 Select bits
See bits 28-24 for bit value definitions.
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TRGSRC25: Trigger Source for Conversion of Analog Input AN25 Select bits
See bits 28-24 for bit value definitions.
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
TRGSRC24: Trigger Source for Conversion of Analog Input AN24 Select bits
See bits 28-24 for bit value definitions.
Note 1:
2:
Note:
The PWM bit definitions are only applicable to PIC32MKXXMCXX Motor Control devices.
For Scan Trigger, in addition to setting the trigger, it also requires programming of the STRGSRC
bits (ADCCON1) to select the trigger source, and requires the appropriate CSS bits to be set in
the ADCCSSx registers.
This register is not available on 64-pin devices.
DS60001570C-page 354
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-25: ADCCMPCON1: ADC DIGITAL COMPARATOR 1 CONTROL
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
CVDDATA
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
CVDDATA
U-0
U-0
—
—
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
AINID
R/W-0
R/W-0
R-0, HS, HC
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ENDCMP
DCMPGIEN
DCMPED
IEBTWN
IEHIHI
IEHILO
IELOHI
IELOLO
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Set
W = Writable bit
‘1’ = Bit is set
HC = Hardware Cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 CVDDATA: CVD Data Status bits
In CVD mode, these bits obtain the CVD differential output data (subtraction of CVD positive and negative
measurement), whenever a Digital Comparator interrupt is generated. The value in these bits is compliant
with the FRACT bit (ADCCON1) and is always signed.
bit 15-14 Unimplemented: Read as ‘0’
2019-2020 Microchip Technology Inc.
DS60001570C-page 355
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-25: ADCCMPCON1: ADC DIGITAL COMPARATOR 1 CONTROL
REGISTER (CONTINUED)
bit 13-8
AINID: Digital Comparator 1 Analog Input Identification (ID) bits
When a digital comparator event occurs (DCMPED = 1), these bits identify the analog input being
monitored by Digital Comparator 1.
Note:
In normal ADC mode, only analog inputs can be processed by the Digital Comparator 1.
The Digital Comparator 1 also supports the CVD mode, in which all Class 2 and Class 3 analog
inputs may be stored in the AINID bits.
111111 = Reserved
•
•
•
110110 = Reserved
110101 = Internal AN53 (CTMU temperature sensor)
110101 = Reserved
110101 = Reserved
110010 = Internal AN50 (IVREF 1.2V)
110001 = AN49 is being monitored
•
•
•
101101 = AN45 is being monitored
101100 = Reserved
•
•
•
101010 = Reserved
101001 = AN41 is being monitored
•
•
•
100001 = AN33 is being monitored
111100 = Reserved
•
•
•
111000 = Reserved
111011 = AN27 is being monitored
•
•
•
000000 = AN0 is being monitored
bit 7
bit 6
bit 5
Note:
For 64 pin devices AN20-AN23 and AN33-AN47 inputs above are not implemented.
ENDCMP: Digital Comparator 1 Enable bit
1 = Digital Comparator 1 is enabled
0 = Digital Comparator 1 is not enabled, and the DCMPED status bit (ADCCMP0CON) is cleared
DCMPGIEN: Digital Comparator 1 Global Interrupt Enable bit
1 = A Digital Comparator 1 interrupt is generated when the DCMPED status bit (ADCCMP0CON) is set
0 = A Digital Comparator 1 interrupt is disabled
DCMPED: Digital Comparator 1 “Output True” Event Status bit
The logical conditions under which the digital comparator gets “True” are defined by the IEBTWN, IEHIHI,
IEHILO, IELOHI, and IELOLO bits.
Note:
bit 4
This bit is cleared by reading the AINID bits or by disabling the Digital Comparator module
(by setting ENDCMP to ‘0’).
1 = Digital Comparator 1 output true event has occurred (output of Comparator is ‘1’)
0 = Digital Comparator 1 output is false (output of comparator is ‘0’)
IEBTWN: Between Low/High Digital Comparator 1 Event bit
1 = Generate a digital comparator event when DCMPLO DATA < DCMPHI
0 = Do not generate a digital comparator event
DS60001570C-page 356
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-25: ADCCMPCON1: ADC DIGITAL COMPARATOR 1 CONTROL
REGISTER (CONTINUED)
bit 3
bit 2
bit 1
bit 0
IEHIHI: High/High Digital Comparator 0 Event bit
1 = Generate a Digital Comparator 0 Event when DCMPHI DATA
0 = Do not generate an event
IEHILO: High/Low Digital Comparator 0 Event bit
1 = Generate a Digital Comparator 0 Event when DATA < DCMPHI
0 = Do not generate an event
IELOHI: Low/High Digital Comparator 0 Event bit
1 = Generate a Digital Comparator 0 Event when DCMPLO DATA
0 = Do not generate an event
IELOLO: Low/Low Digital Comparator 0 Event bit
1 = Generate a Digital Comparator 0 Event when DATA < DCMPLO
0 = Do not generate an event
2019-2020 Microchip Technology Inc.
DS60001570C-page 357
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-26: ADCCMPCONx: ADC DIGITAL COMPARATOR ‘x’ CONTROL REGISTER
(‘x’ = 2 THROUGH 4)
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
—
—
—
R/W-0
R/W-0
R-0, HS, HC
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ENDCMP
DCMPGIEN
DCMPED
IEBTWN
IEHIHI
IEHILO
IELOHI
IELOLO
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Set
W = Writable bit
‘1’ = Bit is set
AINID
HC = Hardware Cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12-8 AINID: Digital Comparator ’x’ Analog Input Identification (ID) bits
When a digital comparator event occurs (DCMPED = 1), these bits identify the analog input being
monitored by the Digital Comparator.
Note:
Only analog inputs can be processed by the Digital Comparator module ’x’ (’x’ = 2-4).
11111 = Reserved
•
•
•
11100 = Reserved
11011 = AN27
11010 = AN26
11001 = AN25
11000 = AN24
10111 = AN23(1)
10110 = AN22(1)
10101 = AN21(1)
10100 = AN20(1)
10011 = AN19
•
•
•
bit 7
bit 6
Note 1:
00001 = AN1
00000 = AN0
ENDCMP: Digital Comparator ’x’ Enable bit
1 = Digital Comparator ’x’ is enabled
0 = Digital Comparator ’x’ is not enabled, and the DCMPED status bit (ADCCMPxCON) is cleared
DCMPGIEN: Digital Comparator ’x’ Global Interrupt Enable bit
1 = A Digital Comparator ’x’ interrupt is generated when the DCMPED status bit (ADCCMPxCON) is set
0 = A Digital Comparator ’x’ interrupt is disabled
This setting is not available on 64-pin devices.
DS60001570C-page 358
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-26: ADCCMPCONx: ADC DIGITAL COMPARATOR ‘x’ CONTROL REGISTER
(‘x’ = 2 THROUGH 4) (CONTINUED)
bit 5
DCMPED: Digital Comparator ’x’ “Output True” Event Status bit
The logical conditions under which the digital comparator gets “True” are defined by the IEBTWN, IEHIHI,
IEHILO, IELOHI and IELOLO bits.
This bit is cleared by reading the AINID bits (ADCCMPCONx) or by disabling the Digital Comparator module (by setting ENDCMP to ‘0’).
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
1 = Digital Comparator ’x’ output true event has occurred (output of Comparator is ‘1’)
0 = Digital Comparator ’x’ output is false (output of Comparator is ‘0’)
IEBTWN: Between Low/High Digital Comparator ’x’ Event bit
1 = Generate a digital comparator event when the DCMPLO bits DATA bits
< DCMPHI bits
0 = Do not generate a digital comparator event
IEHIHI: High/High Digital Comparator ’x’ Event bit
1 = Generate a Digital Comparator ’x’ Event when the DCMPHI bits DATA bits
0 = Do not generate an event
IEHILO: High/Low Digital Comparator ’x’ Event bit
1 = Generate a Digital Comparator ’x’ Event when the DATA bits < DCMPHI bits
0 = Do not generate an event
IELOHI: Low/High Digital Comparator ’x’ Event bit
1 = Generate a Digital Comparator ’x’ Event when the DCMPLO bits DATA bits
0 = Do not generate an event
IELOLO: Low/Low Digital Comparator ’x’ Event bit
1 = Generate a Digital Comparator ’x’ Event when the DATA bits < DCMPLO bits
0 = Do not generate an event
This setting is not available on 64-pin devices.
2019-2020 Microchip Technology Inc.
DS60001570C-page 359
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 23-27: ADCBASE: ADC BASE REGISTER
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
Bit
27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCBASE
R/W-0
ADCBASE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Unimplemented: Read as ‘0’
bit 15-0
ADCBASE: ADC ISR Base Address bits
x = Bit is unknown
This register, when read, contains the base address of the user's ADC ISR jump table. The interrupt vector
address is determined by the IRQVS bits of the ADCCON1 register specifying the amount of left
shift done to the AIRDYx status bits in the ADCDSTAT1 and ADCDSTAT2 registers, prior to adding with
ADCBASE register.
Interrupt Vector Address = Read Value of ADCBASE and Read Value of ADCBASE = Value written to
ADCBASE + x VIN-.
The Comparator and the relationship between the
analog input levels and the digital output are illustrated
in Figure 25-19. Each Comparator can be individually
configured to compare against an external voltage
reference or internal voltage reference. For more
information on the internal op amp/comparator voltage
reference, refer to Section 45. “Control Digital-toAnalog converter” (DS60001327) of the “PIC32
Family Reference Manual”.
FIGURE 25-19:
COMPARATOR CONFIGURATION FOR DEFAULT BUILT-IN HYSTERESIS
AVDD
CxINy-
CDAC2, CxINy+
X
VIN-
X
VIN+
-
X
CMPx
CxOUT
+
AVSS
CPOL = 0 (non-inverted polarity)
HYSPOL = 0 (Hysteresis on Rising Edge)
CxOUT(L) -> CxOUT(H) = VIN+ > VIN- + VHYST
CxOUT(H) -> CxOUT(L) = VIN+ < VIN-
CPOL = 0 (non-inverted polarity)
HYSPOL = 1 (Hysteresis on Falling Edge)
CxOUT(L) -> CxOUT(H) = VIN+ > VINCxOUT(H) -> CxOUT(L) = VIN+ < VIN- - VHYST
VIN+
VIN-
VIN+
VHYST
VIN-
VHYST
CxOUT (H)
CxOUT (H)
CxOUT (L)
CxOUT (L)
CPOL = 1 (inverted polarity)
HYSPOL = 1 (Hysteresis on Falling Edge)
CxOUT(H) -> COUTL= VIN+ > VINCxOUT(L) -> CxOUT(H) = VIN+ < VIN- - VHYST
CPOL = 1 (inverted polarity)
HYSPOL = 0 (Hysteresis on Rising Edge)
CxOUT(H) -> CxOUT(L) = VIN+ > VIN- + VHYST
CxOUT(L) -> CxOUT(H) = VIN+ < VIN-
VIN+
VIN-
VINVHYST
VHYST
CxOUT (H)
CxOUT (H)
CxOUT (L)
CxOUT (L)
2019-2020 Microchip Technology Inc.
VIN+
DS60001570C-page 461
PIC32MK GPG/MCJ with CAN FD Family
TABLE 25-2:
CPOL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Note:
COMPARATOR CMPX OUTPUT AND EVENT POLARITY SELECTION (X=1-5)
EVPOL Comparator Input Change Comparator
[1:0]
(comparator_status_in)
Output
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
+In > -In
+In < -In
+In > -In
+In < -In
+In > -In
+In < -In
+In > -In
+In < -In
+In > -In
+In < -In
+In > -In
+In < -In
+In > -In
+In < -In
+In > -In
+In < -In
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
CxOUT
High
Low
High
Low
High
Low
High
Low
Low
High
Low
High
Low
High
Low
High
Trigger/Interrupt Generated?
No
No
Yes (only while CEVT = 0)
No
No
Yes (only while CEVT = 0)
Yes (only while CEVT = 0)
Yes (only while CEVT = 0)
No
No
No
Yes (only while CEVT = 0)
Yes (only while CEVT = 0)
No
Yes (only while CEVT = 0)
Yes (only while CEVT = 0)
Each comparator has its dedicated Polarity and Event selection. There is no interaction between the settings
of the multiple comparators.
DS60001570C-page 462
2019-2020 Microchip Technology Inc.
Virtual Address
(BF82)
Register
Name(1)
TABLE 25-3:
C000
CMSTAT
C010
CM1CON
CM2CON
C040 CM2MSKCON
C050
CM3CON
C060 CM3MSKCON
C070
CM4CON
C080 CM4MSKCON
C090
CM5CON
C0A0 CM5MSKCON
2019-2020 Microchip Technology Inc.
Legend:
Note 1:
31/15
30/14
31:16
—
15:0
—
31:16 OPAON
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
—
C5EVT
C4EVT
C3EVT
—
SIDL
—
—
—
—
—
—
—
—
C5OUT
C4OUT
C3OUT
HYSSEL
—
ENPGA
—
HYSPOL
—
—
15:0
ON
COE
CPOL
CLPWR
—
—
31:16
—
—
—
—
—
ENPGA
OCEN
—
OCNEN
HYSPOL
OBEN
—
OBNEN
—
—
15:0 HLMS
31:16 OPAON
15:0
ON
COE
CPOL
CLPWR
—
—
—
—
15:0
HLMS
—
OCEN
OCNEN
OBEN
OBNEN
—
ENPGA
—
HYSPOL
—
—
ON
COE
CPOL
CLPWR
—
—
31:16
—
—
—
—
15:0
HLMS
—
OCEN
OCNEN
OBEN
OBNEN
OAEN
COUT
NAGS
—
EVPOL
COUT
NAGS
31:16
—
—
—
HYSPOL
—
—
15:0
ON
COE
CPOL
—
—
—
31:16
—
—
—
—
15:0
HLMS
—
OCEN
OCNEN
OBEN
OBNEN
OANEN
COUT
NAGS
ENPGA
—
HYSPOL
—
—
15:0
ON
COE
CPOL
CLPWR
—
—
—
31:16
—
—
—
—
15:0
HLMS
—
OCEN
OCNEN
COUT
NAGS
OBNEN
OAEN
PAGS
—
—
ABEN
NAGS
PAGS
CFDIV
—
CCH
ACEN
—
ACEN
—
ACEN
ABNEN
CFLTREN
CREF
—
0000
0000
0000
0000
AAEN AANEN 0000
CFDIV
—
CCH
SELSRCA
ACNEN
ABEN
ABNEN
CFLTREN
CREF
—
ACNEN
ABEN
CFDIV
—
CCH
ABNEN
CFLTREN
CREF
—
0000
0000
0000
0000
0000
AAEN AANEN 0000
CFDIV
—
0000
AAEN AANEN 0000
SELSRCA
SELSRCB
OANEN
C2EVT C1EVT 0000
C2OUT C1OUT 0000
SELSRCA
ACNEN
CFSEL
EVPOL
SELSRCC
OBEN
ACEN
CFSEL
EVPOL
16/0
SELSRCA
SELSRCB
OANEN
HYSSEL
CEVT
PAGS
17/1
ACEN ACNEN
ABEN
ABNEN AAEN AANEN 0000
CFSEL
CFLTREN
CFDIV
0000
—
CREF
—
—
CCH
0000
CFSEL
EVPOL
SELSRCC
OAEN
—
SELSRCB
HYSSEL
CEVT
PAGS
—
SELSRCC
OAEN
PAGS
18/2
CFLTREN
CREF
SELSRCB
OANEN
HYSSEL
CEVT
—
19/3
SELSRCB
OAEN
OANEN
HYSSEL
CEVT
CFSEL
EVPOL
SELSRCC
15:0
31:16 OPAON
COUT
SELSRCC
31:16
31:16 OPAON
CEVT
20/4
All Resets
Bit Range
Bits
C020 CM1MSKCON
C030
OP AMP/COMPARATOR REGISTER MAP
CCH
0000
0000
SELSRCA
ACNEN
ABEN
ABNEN
0000
AAEN AANEN 0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 463
25.10 Op amp/Comparator Control Registers
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 25-1:
Bit Range
31:24
23:16
15:8
7:0
CMSTAT: OP AMP/COMPARATOR STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
HS, R-0
HS, R-0
HS, R-0
HS, R-0
HS, R-0
—
—
—
C5EVT
C4EVT
C3EVT
C2EVT
C1EVT
U-0
U-x
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
SIDL
—
—
—
—
—
U-0
U-0
U-0
R-0
R-0
R-0
R-0
R-0
—
—
—
C5OUT
C4OUT
C3OUT
C2OUT
C1OUT
Legend:
HS = Set by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-21
Unimplemented: Read as ‘0’
bit 20
C5EVT: Comparator 5 Event Status bit
1 = Comparator event according to EVPOL settings occurred. Future events/triggers and interrupts
are disabled until the CEVT bit (CMxCON) is cleared by user software.
0 = Comparator event did not occur
bit 19
C4EVT: Comparator 4 Event Status bit
1 = Comparator event according to EVPOL settings occurred. Future events/triggers and interrupts
are disabled until the CEVT bit (CMxCON) is cleared by user software.
0 = Comparator event did not occur
bit 18
C3EVT: Comparator 3 Event Status bit
1 = Comparator event according to EVPOL settings occurred. Future events/triggers and interrupts
are disabled until the CEVT bit (CMxCON) is cleared by user software.
0 = Comparator event did not occur
bit 17
C2EVT: Comparator 2 Event Status bit
1 = Comparator event according to EVPOL settings occurred. Future events/triggers and interrupts
are disabled until the CEVT bit (CMxCON) is cleared by user software.
0 = Comparator event did not occur
bit 16
C1EVT: Comparator 1 Event Status bit
1 = Comparator event according to EVPOL settings occurred. Future events/triggers and interrupts
are disabled until the CEVT bit (CMxCON) is cleared by user software.
0 = Comparator event did not occur
bit 15-14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation of all Op amp/Comparators when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-5
Unimplemented: Read as ‘0’
bit 4-0
C5OUT:C1OUT: Op amp/Comparator 5 through Comparator 1 Output Status bit
When CPOL = 0:
1 = VIN+ > VTH+
0 = VIN+ < VTHWhen CPOL = 1:
1 = VIN+ < VTH0 = VIN+ > VTH+
DS60001570C-page 464
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 25-2:
CMxCON: OP AMP/COMPARATOR ‘x’ CONTROL REGISTER
(‘x’ = 1-5)
Bit
Range
Bit
31/23/15/7
31:24
U-0
R/W-0
23:16
15:8
7:0
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
OPAON(2)
ENPGA(2)
—
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
—
HYSPOL
—
—
R/W-0
R/W-0
R/W-0
R/W-0
CFSEL
CFLTREN
HYSSEL
R/W-0
R/W-0
CFDIV
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
HS, R/W-0
R-0
ON
COE
CPOL
OPLPWR
—
—
CVET(1)
COUT
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
—
CREF
—
—
EVPOL
Legend:
R = Readable bit
-n = Value at POR
bit 31
Bit
28/20/12/4
HS = Set by hardware
W = Writable bit
‘1’ = Bit is set
CCH
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
OPAON: Op amp Enable bit(2)
1 = Op amp enabled and connected to pin
0 = Op amp disabled and pin is released to other functions
Note:
Initialize ENPGA & OPLPWR prior to enabling the op-amp, CMxCON=1.
ENPGA: Op amp Fixed Gain Enable bit(2)
1 = Op amp is operating in Fixed Gain 1X mode
0 = Op amp is operating in Open Loop mode (default)
Unimplemented: Read as ‘0’
bit 29
bit 28
HYSPOL: Comparator Hysteresis Polarity Selection
1 = Hysteresis on falling edge, rising edge is accurate
0 = Hysteresis on rising edge, falling edge is accurate
bit 27-26 Unimplemented: Read as ‘0’
bit 25-24 HYSSEL: Hysteresis Selection bits
11 = Set highest hysteresis level (Typical 45 mV)
10 = Set medium hysteresis level (Typical 30 mV)
01 = Set lowest hysteresis level (Typical 15 mV)
00 = No hysteresis selected.
bit 30
Note:
These bits select the hysteresis of the analog comparator.
Unimplemented: Read as ‘0’
bit 23
bit 22-20 CFSEL: Comparator Output Filter Clock Source Select bits
111 = PBCLK2/Timer5 Period Value (PR5)
110 = PBCLK2/Timer4 Period Value (PR4)
101 = PBCLK2/Timer3 Period Value (PR3)
100 = PBCLK2/Timer2 Period Value (PR2)
011 = REFCLK3 Clock
010 = PWM Secondary Special Event
001 = PPBCLK2 Clock
000 = SYSCLK Clock
Note 1: Before attempting to initialize or enable any of the op amp bits, the user application must clear the
corresponding OPA5MD, OPA3MD, OPA2MD, OPA1MD bits in the PMD register.
2: These bits are not available in the CM4CON register.
Note:
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and
an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the
user application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see
whether an interrupt condition has occurred. The IFSx bits are persistent, so they must be cleared by user
software.
2019-2020 Microchip Technology Inc.
DS60001570C-page 465
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 25-2:
bit 19
CMxCON: OP AMP/COMPARATOR ‘x’ CONTROL REGISTER
(‘x’ = 1-5) (CONTINUED)
CFLTREN: Comparator Output Digital Filter Enable bit
1 = Digital Filters enabled
0 = Digital Filters disabled
bit 18-16 CFDIV: Comparator Output Filter Clock Divide Select bits
These bits are based on the CFSEL clock source selection.
111 = 1:128 Clock Divide
110 = 1:64 Clock Divide
101 = 1:32 Clock Divide
100 = 1:16 Clock Divide
011 = 1:8 Clock Divide
010 = 1:4 Clock Divide
001 = 1:2 Clock Divide
000 = 1:1 Clock Divide
ON: Comparator Enable bit
bit 15
1 = Comparator is enabled
0 = Comparator is disabled
COE: Comparator Output Enable bit
bit 14
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
bit 13
CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
OPLPWR: Op Amp Power mode
bit 12
1 = Op amp operating in low-power mode (1/10 power, slower response, Bandwidth ≤ 10 MHz)
0 = Op amp operating in normal power mode, (10 MHz ≥ Bandwidth ≤ 100 MHz)
Note:
This bit does not exist for in CM4CON as there is no Op-Amp #4.
bit 11-10 Unimplemented: Read as ‘0’
CEVT: Comparator Event bit(1)
bit 9
1 = Comparator event according to EVPOL bit settings occurred
Note:
CEVT = 1 disables future events/triggers and interrupts until the bit is cleared by user software.
0 = Comparator event did not occur
COUT: Comparator Output bit
When CPOL = 0 (non-inverted polarity):
1 = VIN+ > VTH+
0 = VIN+ < VTH-
bit 8
When CPOL = 1 (inverted polarity):
1 = VIN+ < VTH0 = VIN+ > VTH+
Note 1:
2:
Note:
Before attempting to initialize or enable any of the op amp bits, the user application must clear the
corresponding OPA5MD, OPA3MD, OPA2MD, OPA1MD bits in the PMD register.
These bits are not available in the CM4CON register.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and
an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the
user application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see
whether an interrupt condition has occurred. The IFSx bits are persistent, so they must be cleared by user
software.
DS60001570C-page 466
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 25-2:
bit 7-6
CMxCON: OP AMP/COMPARATOR ‘x’ CONTROL REGISTER
(‘x’ = 1-5) (CONTINUED)
EVPOL: Trigger/Event Polarity Select bits
11 = Trigger/Event generated on any change of the comparator output
10 = Trigger/Event generated only on high-to-low transition of the polarity-selected comparator output
If CPOL = 0 (non-inverted polarity):
High-to-low transition of the comparator output
If CPOL = 1 (inverted polarity):
Low-to-high transition of the comparator output
01 = Trigger/Event generated only on low-to-high transition of the polarity-selected comparator output
If CPOL = 0 (non-inverted polarity):
Low-to-high transition of the comparator output
If CPOL = 1 (inverted polarity):
High-to-low transition of the comparator output
00 = Trigger/Event generation is disabled
Unimplemented: Read as ‘0’
CREF: Op amp/Comparator Reference Select bit
1 = VIN+ input connects to internal CDAC2 output voltage
0 = VIN+ input connects to CxIN1+ pin
Unimplemented: Read as ‘0’
CCH: Comparator Channel Select bits
11 = CxIN410 = CxIN301 = CxIN200 = CxIN1-
bit 5
bit 4
bit 3-2
bit 1-0
Note 1:
2:
Note:
Before attempting to initialize or enable any of the op amp bits, the user application must clear the
corresponding OPA5MD, OPA3MD, OPA2MD, OPA1MD bits in the PMD register.
These bits are not available in the CM4CON register.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and
an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the
user application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see
whether an interrupt condition has occurred. The IFSx bits are persistent, so they must be cleared by user
software.
2019-2020 Microchip Technology Inc.
DS60001570C-page 467
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 25-3:
Bit Range
31:24
23:16
15:8
7:0
CMxMSKCON: COMPARATOR ‘x’ MASK CONTROL REGISTER
(‘x’ = 1-5)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
SELSRCC
R/W-0
SELSRCB
R/W-0
R/W-0
R/W-0
SELSRCA
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HLMS
—
OCEN
OCNEN
OBEN
OBNEN
OAEN
OANEN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NAGS
PAGS
ACEN
ACNEN
ABEN
ABNEN
AAEN
AANEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28
Unimplemented: Read as ‘0’
bit 27-24
SELSRCC: Mask C Input Select bits
See the definitions for the SELSRCA bits.
bit 23-20
SELSRCB: Mask B Input Select bits
See the definitions for the SELSRCA bits.
bit 19-16
SELSRCA: Mask A Input Select bits
1111 = FLT4 pin
1110 = FLT2 pin
1101 = PWM5L
1100 = PWM4L
1011 = PWM3L
1010 = PWM2L
1001 = PWM1L
1000 = PWM9H (Not available on 48-pin devices)
0111 = PWM8H (Not available on 48-pin devices)
0110 = PWM7H (Not available on 48-pin devices)
0101 = PWM6H
0100 = PWM5H
0011 = PWM4H
0010 = PWM3H
0001 = PWM2H
0000 = PWM1H
bit 15
HLMS: High or Low Level Masking Select bit
1 = The comparator deasserted state is 1, and the masking (blanking) function will prevent any
asserted (‘0’) comparator signal from propagating
0 = The comparator deasserted state is 0, and the masking (blanking) function will prevent any
asserted (‘1’) comparator signal from propagating
bit 14
Unimplemented: Read as ‘0’
bit 13
OCEN: OR Gate “C” Input Enable bit
1 = “C” input enabled as input to OR gate
0 = “C” input disabled as input to OR gate
Note:
This register is only available on PIC32MKXXMCXXX devices.
DS60001570C-page 468
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 25-3:
CMxMSKCON: COMPARATOR ‘x’ MASK CONTROL REGISTER
(‘x’ = 1-5) (CONTINUED)
bit 12
OCNEN: OR Gate “C” Input Inverted Enable bit
1 = “C” input (inverted) enabled as input to OR gate
0 = “C” input (inverted) disabled as input to OR gate
bit 11
OBEN: OR Gate “B” Input Enable bit
1 = “B” input enabled as input to OR gate
0 = “B” input disabled as input to OR gate
bit 10
OBNEN: OR Gate “B” Input Inverted Enable bit
1 = “B” input (inverted) enabled as input to OR gate
0 = “B” input (inverted) disabled as input to OR gate
bit 9
OAEN: OR Gate “A” Input Enable bit
1 = “A” input enabled as input to OR gate
0 = “A” input disabled as input to OR gate
bit 8
OANEN: OR Gate “A” Input Inverted Enable bit
1 = “A” input (inverted) enabled as input to OR gate
0 = “A” input (inverted) disabled as input to OR gate
bit 7
NAGS: Negative AND Gate Output Select bit
1 = The negative (inverted) output of the AND gate to the OR gate is enabled
0 = The negative (inverted) output of the AND gate to the OR gate is disabled
bit 6
PAGS: Positive AND Gate Output Select bit
1 = The positive output of the AND gate to the OR gate is enabled
0 = The positive output of the AND gate to the OR gate is disabled
bit 5
ACEN: AND Gate “C” Input Enable bit
1 = “C” input enabled as input to AND gate
0 = “C” input disabled as input to AND gate
bit 4
ACNEN: AND Gate “C” Inverted Input Enable bit
1 = “C” input (inverted) enabled as input to AND gate
0 = “C” input (inverted) disabled as input to AND gate
bit 3
ABEN: AND Gate “B” Input Enable bit
1 = “B” input enabled as input to AND gate
0 = “B” input disabled as input to AND gate
bit 2
ABNEN: AND Gate “B” Inverted Input Enable bit
1 = “B” input (inverted) enabled as input to AND gate
0 = “B” input (inverted) disabled as input to AND gate
bit 1
AAEN: AND Gate “A” Input Enable bit
1 = “A” input enabled as input to AND gate
0 = “A” input disabled as input to AND gate
bit 0
AANEN: AND Gate “A” Inverted Input Enable bit
1 = “A” input (inverted) enabled as input to AND gate
0 = “A” input (inverted) disabled as input to AND gate
Note:
This register is only available on PIC32MKXXMCXXX devices.
2019-2020 Microchip Technology Inc.
DS60001570C-page 469
PIC32MK GPG/MCJ with CAN FD Family
26.0
Note:
CHARGE TIME
MEASUREMENT UNIT (CTMU)
or generate output pulses with a specific time delay.
The CTMU is ideal for interfacing with capacitive-based
sensors.
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 37. “Charge
Time Measurement Unit (CTMU)”
(DS60001167), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The CTMU module includes the following key features:
• Two channels are available for capacitive or time
measurement input
• On-chip precision current source
• 16-edge input trigger sources
• Selection of edge or level-sensitive inputs
• Polarity control for each edge source
• Control of edge sequence
• Control of response to edges
• High precision time measurement
• Time delay of external or internal signal
asynchronous to system clock
• Integrated temperature sensing diode
• Control of current source during auto-sampling
• Four current source ranges
• Time measurement resolution of one nanosecond
• Up to 39 inputs for capacitive measurement
The Charge Time Measurement Unit (CTMU) is a
flexible analog module that has a configurable current
source with a digital configuration circuit built around it.
The CTMU can be used for differential time
measurement between pulse sources and can be used
for generating an asynchronous pulse. By working with
other on-chip analog modules, the CTMU can be used
for high resolution time measurement, measure
capacitance, measure relative changes in capacitance
FIGURE 26-1:
A block diagram of the CTMU is shown in Figure 26-1.
CTMU BLOCK DIAGRAM
CTMUCON1
CTMUICON
ITRIM
IRNG
Current Source
CTED1
Edge
Control
Logic
CTED2
Timer1
OC1-OC4
IC1-IC6
CMP1/4/5
PBCLK2
EDG1STAT
EDG2STAT
TGEN
Current
Control
CTMUP
CTMUT
(To ADC)
Temperature
Sensor
CTMU
Control
Logic
ADC
Trigger
Pulse
Generator
CTPLS
CTMUI
(To ADC S&H capacitor)
C1IN1CDelay
Comparator 1
External capacitor
for pulse generation
Current Control Selection
DS60001570C-page 470
TGEN
EDG1STAT, EDG2STAT
CTMUT
0
EDG1STAT = EDG2STAT
CTMUI
0
EDG1STAT EDG2STAT
CTMUP
1
EDG1STAT EDG2STAT
No Connect
1
EDG1STAT = EDG2STAT
2019-2020 Microchip Technology Inc.
Control Registers
D000 CTMUCON
Legend:
Note 1:
CTMU REGISTER MAP
31/15
30/14
31:16 EDG1MOD EDG1POL
29/13
28/12
27/11
EDG1SEL
26/10
25/9
24/8
23/7
22/6
EDG2STAT EDG1STAT EDG2MOD EDG2POL
21/5
20/4
19/3
EDG2SEL
18/2
17/1
16/0
—
—
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF82_#)
TABLE 26-1:
0000
15:0
ON
—
SIDLE
TGEN
EDGEN EDGSEQEN IDISSEN
CTTRIG
ITRIM
IRNG
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 471
26.1
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 26-1:
Bit
Range
31:24
23:16
15:8
7:0
CTMUCON: CTMU CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
EDG1MOD EDG1POL
R/W-0
R/W-0
R/W-0
Bit
26/18/10/2
R/W-0
EDG1SEL
R/W-0
R/W-0
EDG2MOD EDG2POL
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
EDG2STAT EDG1STAT
R/W-0
EDG2SEL
U-0
U-0
—
—
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ON
—
SIDLE
TGEN(1)
EDGEN
EDGSEQEN
IDISSEN(2)
CTTRIG
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ITRIM
IRNG
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
EDG1MOD: Edge 1 Edge Sampling Select bit
1 = Reserved
0 = Input is level-sensitive
bit 30
EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 programmed for a logic high level response
0 = Edge 1 programmed for a logic low level response
x = Bit is unknown
bit 29-26 EDG1SEL: Edge 1 Source Select bits
1111 = C5OUT Capture Event is selected
1110 = C4OUT pin is selected
1101 = C1OUT pin is selected
1100 = PBCLK2 is selected
1011 = IC5 Capture Event is selected
1010 = IC4 Capture Event is selected
1001 = IC3 pin is selected
1000 = IC2 pin is selected
0111 = IC1 pin is selected
0110 = OC4 pin is selected
0101 = OC3 pin is selected
0100 = OC2 pin is selected
0011 = CTED1 pin is selected
0010 = CTED2 pin is selected
0001 = OC1 Compare Event is selected
0000 = Timer1 Event is selected
Note 1:
2:
3:
4:
5:
6:
When this bit is set for Pulse Delay Generation, the EDG2SEL bits must be set to ‘1101’ to select
C1OUT.
The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
Refer to the CTMU Current Source Specifications (Table 36-43) in 36.0 “Electrical Characteristics” for
current values.
This bit setting is not available for the CTMU temperature diode.
For CTMU temperature measurements on this range, ADC sampling time 1.6 µs.
For CTMU temperature measurements on this range, ADC sampling time 300 ns.
DS60001570C-page 472
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 26-1:
CTMUCON: CTMU CONTROL REGISTER (CONTINUED)
bit 25
EDG2STAT: Edge 2 Status bit
Indicates the status of Edge 2 and can be written to control edge source
1 = Edge 2 event has occurred
0 = Edge 2 event has not occurred
bit 24
EDG1STAT: Edge 1 Status bit
Indicates the status of Edge 1 and can be written to control edge source
1 = Edge 1 event has occurred
0 = Edge 1 event has not occurred
bit 23
EDG2MOD: Edge 2 Edge Sampling Select bit
1 = Reserved
0 = Input is level-sensitive
bit 22
EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 programmed for a high level response
0 = Edge 2 programmed for a low level response
bit 21-18 EDG2SEL: Edge 2 Source Select bits
1111 = C5OUT Capture Event is selected
1110 = C4OUT pin is selected
1101 = C1OUT pin is selected
1100 = IC6 Capture Event is selected
1011 = IC5 Capture Event is selected
1010 = IC4 Capture Event is selected
1001 = IC3 pin is selected
1000 = IC2 pin is selected
0111 = IC1 pin is selected
0110 = OC4 pin is selected
0101 = OC3 pin is selected
0100 = OC2 pin is selected
0011 = CTED1 pin is selected
0010 = CTED2 pin is selected
0001 = OC1 Compare Event is selected
0000 = Timer1 Event is selected
bit 17-16 Unimplemented: Read as ‘0’
bit 15
ON: ON Enable bit
1 = Module is enabled
0 = Module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDLE: Stop-in-Idle-Mode
1 = Discontinue Module Operation when device enters idle mode.
0 = Continue module operation in idle mode.
Note 1:
When this bit is set for Pulse Delay Generation, the EDG2SEL bits must be set to ‘1101’ to select
C1OUT.
The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
Refer to the CTMU Current Source Specifications (Table 36-43) in 36.0 “Electrical Characteristics” for
current values.
This bit setting is not available for the CTMU temperature diode.
For CTMU temperature measurements on this range, ADC sampling time 1.6 µs.
For CTMU temperature measurements on this range, ADC sampling time 300 ns.
2:
3:
4:
5:
6:
2019-2020 Microchip Technology Inc.
DS60001570C-page 473
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 26-1:
CTMUCON: CTMU CONTROL REGISTER (CONTINUED)
bit 12
TGEN: Time Generation Enable bit(1)
1 = Enables edge delay generation
0 = Disables edge delay generation
bit 11
EDGEN: Edge Enable bit
1 = Edges are not blocked
0 = Edges are blocked
bit 10
EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 must occur before Edge 2 can occur
0 = No edge sequence is needed
bit 9
IDISSEN: Analog Current Source Control bit(2)
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
bit 8
CTTRIG: Trigger Control bit
1 = Trigger output is enabled
0 = Trigger output is disabled
bit 7-2
ITRIM: Current Source Trim bits
011111 = Maximum positive change from nominal current
011110
•
•
•
000001 = Minimum positive change from nominal current
000000 = Nominal current output specified by IRNG
111111 = Minimum negative change from nominal current
•
•
•
100010
100001 = Maximum negative change from nominal current
bit 1-0
IRNG: Current Range Select bits(3)
11 = 100 times base current (i.e., 0.55 µA Typical)(6)
10 = 10 times base current (i.e., 5.5 µA Typical)(5)
01 = Base current level (i.e., 0.55 µA Typical)(4)
00 = 1000 times base current (i.e., 550 µA Typical)(4)
Note 1:
When this bit is set for Pulse Delay Generation, the EDG2SEL bits must be set to ‘1101’ to select
C1OUT.
The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
Refer to the CTMU Current Source Specifications (Table 36-43) in 36.0 “Electrical Characteristics” for
current values.
This bit setting is not available for the CTMU temperature diode.
For CTMU temperature measurements on this range, ADC sampling time 1.6 µs.
For CTMU temperature measurements on this range, ADC sampling time 300 ns.
2:
3:
4:
5:
6:
DS60001570C-page 474
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
NOTES:
2019-2020 Microchip Technology Inc.
DS60001570C-page 475
PIC32MK GPG/MCJ with CAN FD Family
27.0
CONTROL DIGITAL-TOANALOG CONVERTER (CDAC)
Note:
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 45.
“Control Digital-to-Analog Converter
(CDAC)” (DS60001327), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The PIC32MK GPG/MCJ with CAN FD Family Control
Digital-to-Analog Converter (CDAC) generates analog
voltage corresponding to the digital inputs. The voltage
can be used as a reference source for comparators or
can be used as an offset to an op amp. This module is
targeted for control applications, as opposed to other
DAC modules, which are used for audio applications.
The following are key features of the CDAC module:
•
•
•
•
Wide voltage range (1.8V to 3.6V)
12-bit resolution
Fast conversion times, 1 Msps
Buffered output for comparator use
Note:
For additional information on conversion
time, sampling rate, module turn-on time
and glitch reduction circuit characteristics,
36.0 “Electrical
refer
to
Characteristics”.
Figure 27-1 illustrates the functional block diagram of
the CDAC module.
FIGURE 27-1:
CDAC BLOCK DIAGRAM
AVDD
MUX
No Connect
No Connect
No Connect
REFSEL
Resistor Network
ON
(DACxCON)
Buffer
DACxCON
DACDATA
CDAC1-CDAC2
Only CDAC2
to Comparator
AVSS
DACOE
(DACxCON)
ON (DACxCON)
DS60001570C-page 476
2019-2020 Microchip Technology Inc.
31/15
30/14
29/13
28/12
31:16
BF84_
DAC1CON
C400
15:0
—
—
—
—
ON
—
—
—
31:16
BF84_
DAC2CON
C600
15:0
—
—
—
—
ON
—
—
—
Legend:
Note 1:
27/11
26/10
25/9
24/8
23/7
—
—
—
DACOE
—
—
—
—
DACOE
—
22/6
21/5
20/4
19/3
18/2
—
—
—
—
REFSEL 0000
—
—
—
—
0000
REFSEL 0000
DACDAT
—
16/0
0000
DACDAT
—
17/1
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
CDAC REGISTER MAP
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 477
TABLE 27-1:
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 27-1:
Bit
Range
31:24
23:16
15:8
7:0
DACxCON: CDAC CONTROL REGISTER ‘x’ (‘x’ = 2 THROUGH 3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
(1)
R/W-0
R/W-0
(1)
R/W-0
R/W-0
R/W-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
DACDAT
DACDAT
R/W-0
(1)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
DACOE(1)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
REFSEL(1,2)
ON
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 Unimplemented: Read as ‘0’
bit 27-16 DACDAT: CDAC Data Port bits(1)
Data input register bits for the CDAC.
bit 15
ON: CDAC Enable bit
1 = The CDAC is enabled
0 = The CDAC is disabled
bit 14-9
Unimplemented: Read as ‘0’
bit 8
DACOE: CDAC Output Buffer Enable bit
1 = Output is enabled; CDAC voltage is connected to the pin
0 = Output is disabled; drive to pin is floating
bit 7-2
Unimplemented: Read as ‘0’
bit 1-0
REFSEL: Reference Source Select bits(1,2)
11 = Positive reference voltage = AVDD
10 = No reference selected (no reference current consumption)
01 = No reference selected (no reference current consumption)
00 = No reference selected (no reference current consumption)
Note 1:
2:
To minimize CDAC start-up output transients, configure the DACDATA, DACOE, and
REFSEL bits prior to enabling the CDAC (prior to making DACON = 1). Also, remember to wait TON
time, after enabling the CDAC. This time is required to allow the CDAC output to stabilize. Refer to
36.0 “Electrical Characteristics” for the TON specification.
If the ON bit is ‘0’, the reference source is disconnected from the internal resistor network.
DS60001570C-page 478
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
28.0
Note:
QUADRATURE ENCODER
INTERFACE (QEI)
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 43. “Quadrature
Encoder
Interface
(QEI)”
(DS60001346), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
This chapter describes the Quadrature Encoder Interface (QEI) module and associated operational modes.
The QEI module provides the interface to incremental
encoders for obtaining mechanical position data.
The QEI module consists of the following major
features:
• Four input pins: two phase signals, an index pulse
and a home pulse
• Programmable digital noise filters on inputs
• Quadrature decoder providing counter pulses and
count direction
• Count direction status
• 4x count resolution
• Index (INDX) pulse to reset the position counter
• General purpose 32-bit Timer/Counter mode
• Interrupts generated by QEI or counter events
• 32-bit velocity counter
• 32-bit position counter
• 32-bit index pulse counter
• 32-bit interval timer
• 32-bit position Initialization/Capture register
• 32-bit Compare Less Than and Greater Than
registers
• External Up/Down Count mode
• External Gated Count mode
• External Gated Timer mode
• Interval Timer mode
Figure 28-1 illustrates the QEI block diagram.
2019-2020 Microchip Technology Inc.
DS60001570C-page 479
QEI BLOCK DIAGRAM
FLTREN
GATEN
HOMEx
FHOMEx
DIR_GATE
COUNT
QFDIV
1
EXTCNT
PBCLK2
COUNT_EN
0
DIVCLK
INDXx
FINDXx
CCM
Digital
Filter
DIR
Quadrature
Decoder
Logic
QEBx
DIR_GATE
COUNT
CNT_DIR
1’B0
DIR
CNTPOL
EXTCNT
QEAx
DIR_GATE
PCHGE
PCLLE
CCMPx
PCHEQ
PCLLE
PCLEQ
32-bit Comparator
PCHGE
32-bit Comparator
PCLLE
PCHGE
OUTFNC
INTDIV
PBCLK2
DIVCLK
COUNT_EN CNT_DIR COUNT_EN
2019-2020 Microchip Technology Inc.
FINDXx
32-bit Index Counter
Register (INDXxCNT)
CNT_DIR
32-bit Index Counter
Hold Register
(INDXxHLD)
32-bit Interval
Timer Register
(INTxTMR)
32-bit Interval Timer
Hold Register
(INTxHLD)
32-bit Velocity
Counter Register
(VELxCNT)
32-bit Velocity
Hold Register
(VELxHLD)
Data Bus
Note 1:
32-bit Greater Than or Equal
Compare Register
(QEIxICC)
32-bit Less Than or Equal
Compare Register
(QEIxCMPL)
(POSxCNT)
32-bit Position Counter Register
COUNT_EN
POSxCNT
CNT_DIR
32-bit Position Counter
Hold Register
(POSxHLD)
QCAPEN
32-bit Initialization and
Capture Register
(QEIxICC)
Data Bus
These registers map to the same memory location.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 480
FIGURE 28-1:
QEI Control Registers
TABLE 28-1:
QEI1IOC
B220
QEI1STAT
B230
POS1CNT
B240
B250
B260
B270
B280
POS1HLD
VEL1CNT
VEL1HLD
INT1TMR
INT1HLD
B290 INDX1CNT
B2A0 INDX1HLD
B2B0
QEI1ICC
DS60001570C-page 481
B2C0 QEI1CMPL
B400
B410
QEI2CON
QEI2IOC
Legend:
Note 1:
31/15
30/14
29/13
28/12
31:16
—
15:0
QEIEN
—
—
—
—
QEISIDL
31:16
—
—
—
15:0 QCAPEN FLTREN
31:16
—
—
15:0
—
—
27/11
26/10
25/9
24/8
23/7
22/6
—
—
—
—
—
—
PIMOD
—
—
QFDIV
—
—
IMV
—
—
—
OUTFNC
—
—
—
SWPAB
—
—
21/5
20/4
—
—
INTDIV
—
—
HOMPOL IDXPOL QEBPOL
—
—
—
All Resets
Register
Name(1)
QEI1CON
Bit Range
Virtual Address
(BF82_#)
Bits
B200
B210
QEI1 THROUGH QEI6 REGISTER MAP
19/3
18/2
17/1
16/0
—
—
—
—
0000
CCM
0000
CNTPOL GATEN
—
—
—
—
QEAPOL
HOME
INDEX
QEB
QEA
0000
—
—
—
—
—
0000
—
PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN PCIIRQ PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ
HCAPEN 0000
IDXIEN 0000
31:16
POSCNT
0000
15:0
POSCNT
0000
31:16
POSHLD
0000
15:0
POSHLD
0000
31:16
VELCNT
0000
15:0
VELCNT
0000
31:16
VELHLD
0000
15:0
VELHLD
0000
31:16
INTTMR
0000
15:0
INTTMR
0000
31:16
INTHLD
0000
15:0
INTHLD
0000
31:16
INDXCNT
0000
15:0
INDXCNT
0000
31:16
INDXHLD
0000
15:0
INDXHLD
0000
31:16
QEIICC
0000
15:0
QEIICC
0000
31:16
QEICMPL
0000
15:0
QEICMPL
31:16
—
—
—
15:0
QEIEN
—
QEISIDL
31:16
—
—
—
15:0 QCAPEN FLTREN
—
—
—
—
PIMOD
—
QFDIV
—
—
IMV
—
—
OUTFNC
0000
—
—
—
—
SWPAB
—
—
—
INTDIV
—
—
HOMPOL IDXPOL QEBPOL
—
—
CNTPOL GATEN
—
—
0000
CCM
0000
—
—
—
—
QEAPOL
HOME
INDEX
QEB
HCAPEN 0000
QEA
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
28.1
B430
POS2CNT
B450
B460
B470
B480
POS2HLD
VEL2CNT
VEL2HLD
INT2TMR
INT2HLD
B490 INDX2CNT
B4A0 INDX2HLD
B4B0
QEI2ICC
B4C0 QEI2CMPL
2019-2020 Microchip Technology Inc.
B600
B610
QEI3CON
QEI3IOC
B620
QEI3STAT
B630
POS3CNT
B640
POS3HLD
Legend:
Note 1:
31/15
30/14
31:16
—
—
15:0
—
—
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
—
—
—
—
—
—
—
—
—
—
—
—
—
PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN PCIIRQ PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ
All Resets
Register
Name(1)
QEI2STAT
Bit Range
Virtual Address
(BF82_#)
Bits
B420
B440
QEI1 THROUGH QEI6 REGISTER MAP (CONTINUED)
16/0
—
0000
IDXIEN 0000
31:16
POSCNT
0000
15:0
POSCNT
0000
31:16
POSHLD
0000
15:0
POSHLD
0000
31:16
VELCNT
0000
15:0
VELCNT
0000
31:16
VELHLD
0000
15:0
VELHLD
0000
31:16
INTTMR
0000
15:0
INTTMR
0000
31:16
INTHLD
0000
15:0
INTHLD
0000
31:16
INDXCNT
0000
15:0
INDXCNT
0000
31:16
INDXHLD
0000
15:0
INDXHLD
0000
31:16
QEIICC
0000
15:0
QEIICC
0000
31:16
QEICMPL
0000
15:0
QEICMPL
31:16
—
—
—
15:0
QEIEN
—
QEISIDL
31:16
—
—
—
15:0 QCAPEN FLTREN
31:16
—
—
15:0
—
—
—
—
—
PIMOD
—
—
QFDIV
—
—
—
—
IMV
—
—
OUTFNC
—
—
—
0000
—
—
—
—
SWPAB
—
—
INTDIV
—
—
HOMPOL IDXPOL QEBPOL
—
—
—
—
—
—
—
CNTPOL GATEN
—
—
0000
CCM
0000
—
—
—
—
QEAPOL
HOME
INDEX
QEB
QEA
0000
—
—
—
—
—
0000
PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN PCIIRQ PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ
HCAPEN 0000
IDXIEN 0000
31:16
POSCNT
0000
15:0
POSCNT
0000
31:16
POSHLD
0000
15:0
POSHLD
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 482
TABLE 28-1:
B670
B680
VEL3HLD
INT3TMR
INT3HLD
B690 INDX3CNT
B6A0 INDX3HLD
B6B0
QEI3ICC
B6C0 QEI3CMPL
Legend:
Note 1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
All Resets
Register
Name(1)
VEL3CNT
Bit Range
Virtual Address
(BF82_#)
Bits
B650
B660
QEI1 THROUGH QEI6 REGISTER MAP (CONTINUED)
16/0
31:16
VELCNT
0000
15:0
VELCNT
0000
31:16
VELHLD
0000
15:0
VELHLD
0000
31:16
INTTMR
0000
15:0
INTTMR
0000
31:16
INTHLD
0000
15:0
INTHLD
0000
31:16
INDXCNT
0000
15:0
INDXCNT
0000
31:16
INDXHLD
0000
15:0
INDXHLD
0000
31:16
QEIICC
0000
15:0
QEIICC
0000
31:16
QEICMPL
0000
15:0
QEICMPL
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
DS60001570C-page 483
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 28-1:
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 28-1:
Bit
Range
31:24
23:16
15:8
7:0
QEIxCON: QEIx CONTROL REGISTER (‘X’ = 1-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEIEN
—
QEISIDL
U-0
U-0
U-0
—
INTDIV
PIMOD(1)
U-0
(3)
IMV(2)
R/W-0
R/W-0
CNTPOL
GATEN
R/W-0
R/W-0
CCM
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
QEIEN: Quadrature Encoder Interface Module Counter Enable bit
1 = Module counters are enabled
0 = Module counters are disabled, but SFRs can be read or written
bit 14
Unimplemented: Read as ‘0’
bit 13
QEISIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-10 PIMOD: Position Counter Initialization Mode Select bits(1)
111 = Modulo Count mode for position counter and every index event resets the position counter
110 = Modulo Count mode for position counter
101 = Resets the position counter when the position counter equals QEIxICCH register
100 = Second index event after home event initializes position counter with contents of QEIxICCH
register
011 = First index event after home event initializes position counter with contents of QEIxICCH register
010 = Next index input event initializes the position counter with contents of QEIxICCH register
001 = Every Index input event resets the position counter
000 = Index input event does not affect position counter
bit 9-8
IMV: Index Match Value bits(2)
11 =Index match occurs when QEB = 1 and QEA = 1
10 =Index match occurs when QEB = 1 and QEA = 0
01 =Index match occurs when QEB = 0 and QEA = 1
00 = Index match occurs when QEB = 0 and QEA = 0
bit 7
Unimplemented: Read as ‘0’
Note 1:
When CCM equals modes ‘01’, ‘10’, and ‘11’, all of the QEI counters operate as timers and the
PIMOD bits are ignored.
When CCM = 00 and QEA and QEB values match Index Match Value (IMV), the POSxCNTH and
POSxCNTL registers are reset.
The selected clock rate should be at least twice the expected maximum quadrature count rate.
2:
3:
DS60001570C-page 484
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 28-1:
QEIxCON: QEIx CONTROL REGISTER (‘X’ = 1-3) (CONTINUED)
bit 6-4
INTDIV: Timer Input Clock Prescale Select bits (Interval timer, Main timer (position counter), velocity
counter and index counter internal clock divider select)(3)
111 = 1:128 prescale value
110 = 1:64 prescale value
101 = 1:32 prescale value
100 = 1:16 prescale value
011 = 1:8 prescale value
010 = 1:4 prescale value
001 = 1:2 prescale value
000 = 1:1 prescale value
bit
CNTPOL: Position and Index Counter/Timer Direction Select bit
1 = Counter direction is negative unless modified by external Up/Down signal
0 = Counter direction is positive unless modified by external Up/Down signal
bit
GATEN: External Count Gate Enable bit
1 = External gate signal controls position counter operation
0 = External gate signal does not affect position counter/timer operation
bit
CCM: Counter Control Mode Selection bits
11 = Internal Timer mode with optional QEB external clock gating input control based on GATEN. QEB High
= Timer Run, QEB Low = Timer Stop.
10 = QEA is the external clock input, QEB is optional clock gating input control based on GATEN. QEB High
= Clock Run, QEB Low = Clock Stop.
01 = QEA is the external clock input, QEB is external UP/DN direction input. (QEB High = Count Up, QEB
Low = Count Down)
00 = Quadrature Encoder Interface Count mode (x4 mode)
Note 1:
When CCM equals modes ‘01’, ‘10’, and ‘11’, all of the QEI counters operate as timers and the
PIMOD bits are ignored.
When CCM = 00 and QEA and QEB values match Index Match Value (IMV), the POSxCNTH and
POSxCNTL registers are reset.
The selected clock rate should be at least twice the expected maximum quadrature count rate.
2:
3:
2019-2020 Microchip Technology Inc.
DS60001570C-page 485
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 28-2:
Bit
Range
31:24
23:16
15:8
7:0
QEIxIOC: QEIx I/O CONTROL REGISTER (‘X’ = 1-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
HCAPEN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QCAPEN
FLTREN
R/W-0
R/W-0
R/W-0
R/W-0
R-x
R-x
R-x
R-x
HOMPOL
IDXPOL
QEBPOL
QEAPOL
HOME
INDEX
QEB
QEA
QFDIV
OUTFNC
SWPAB
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-17 Unimplemented: Read as ‘0’
bit 16
HCAPEN: Position Counter Input Capture by Home Event Enable bit
1 = HOMEx input event (positive edge) triggers a position capture event
0 = HOMEx input event (positive edge) does not trigger a position capture event
bit 15
QCAPEN: Position Counter Input Capture Enable bit
1 = Positive edge detect of Home input triggers position capture function
0 = Home input event (positive edge) does not trigger a capture even
bit 14
FLTREN: QEA/QEB/INDX/HOMEx Digital Filter Enable bit
1 = Input Pin Digital filter is enabled
0 = Input Pin Digital filter is disabled (bypassed)
bit 13-11 QFDIV: QEA/QEB/INDX/HOMEx Digital Input Filter Clock
111 = 1:128 clock divide
110 = 1:64 clock divide
101 = 1:32 clock divide
100 = 1:16 clock divide
011 = 1:8 clock divide
010 = 1:4 clock divide
001 = 1:2 clock divide
000 = 1:1 clock divide
Select bits
bit 10-9
OUTFNC: QEI Module Output Function Mode Select bits
11 = The CNTCMPx pin goes high when POSxCNT QEIxCMPL or POSxCNT QEIxICCH
10 = The CNTCMPx pin goes high when POSxCNT QEIxCMPL
01 = The CNTCMPx pin goes high when POSxCNT QEIxICCH
00 = Output is disabled
bit 8
SWPAB: Swap QEA and QEB Inputs bit
1 = QEAx and QEBx are swapped prior to quadrature decoder logic
0 = QEAx and QEBx are not swapped
bit 7
HOMPOL: HOMEx Input Polarity Select bit
1 = Input is inverted
0 = Input is not inverted
bit 6
IDXPOL: INDXx Input Polarity Select bit
1 = Input is inverted
0 = Input is not inverted
bit 5
QEBPOL: QEBx Input Polarity Select bit
1 = Input is inverted
0 = Input is not inverted
DS60001570C-page 486
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 28-2:
QEIxIOC: QEIx I/O CONTROL REGISTER (‘X’ = 1-3) (CONTINUED)
bit 4
QEAPOL: QEAx Input Polarity Select bit
1 = Input is inverted
0 = Input is not inverted
bit 3
HOME: Status of HOMEx Input Pin after Polarity Control bit (read-only)
1 = Pin is at logic ‘1’, if HOMPOL bit is set to ‘0’
Pin is at logic ‘0’, if HOMPOL bit is set to ‘1’
0 = Pin is at logic ‘0’, if HOMPOL bit is set to ‘0’
Pin is at logic ‘1’, if HOMPOL bit is set to ‘1’
bit 2
INDEX: Status of INDXx Input Pin after Polarity Control bit (Read-Only)
1 = Pin is at logic ‘1’, if IDXPOL bit is set to ‘0’
Pin is at logic ‘0’, if IDXPOL bit is set to ‘1’
0 = Pin is at logic ‘0’, if IDXPOL bit is set to ‘0’
Pin is at logic ‘1’, if IDXPOL bit is set to ‘1’
bit 1
QEB: Status of QEBx Input Pin after Polarity Control and SWPAB Pin Swapping bit (read-only)
1 = Physical pin QEB is at logic ‘1’, if QEBPOL bit is set to ‘0’ and SWPAB bit is set to ‘0’
Physical pin QEB is at logic ‘0’, if QEBPOL bit is set to ‘1’ and SWPAB bit is set to ‘0’
Physical pin QEA is at logic ‘1’, if QEBPOL bit is set to ‘0’ and SWPAB bit is set to ‘1’
Physical pin QEA is at logic ‘0’, if QEBPOL bit is set to ‘1’ and SWPAB bit is set to ‘1’
0 = Physical pin QEB is at logic ‘0’, if QEBPOL bit is set to ‘0’ and SWPAB bit is set to ‘0’
Physical pin QEB is at logic ‘1’, if QEBPOL bit is set to ‘1’ and SWPAB bit is set to ‘0’
Physical pin QEA is at logic ‘0’, if QEBPOL bit is set to ‘0’ and SWPAB bit is set to ‘1’
Physical pin QEA is at logic ‘1’, if QEBPOL bit is set to ‘1’ and SWPAB bit is set to ‘1’
bit 0
QEA: Status of QEAx Input Pin after Polarity Control and SWPAB Pin Swapping bit (read-only)
1 = Physical pin QEA is at logic ‘1’, if QEAPOL bit is set to ‘0’ and SWPAB bit is set to ‘0’
Physical pin QEA is at logic ‘0’, if QEAPOL bit is set to ‘1’ and SWPAB bit is set to ‘0’
Physical pin QEB is at logic ‘1’, if QEAPOL bit is set to ‘0’ and SWPAB bit is set to ‘1’
Physical pin QEB is at logic ‘0’, if QEAPOL bit is set to ‘1’ and SWPAB bit is set to ‘1’
0 = Physical pin QEA is at logic ‘0’, if QEAPOL bit is set to ‘0’ and SWPAB bit is set to ‘0’
Physical pin QEA is at logic ‘1’, if QEAPOL bit is set to ‘1’ and SWPAB bit is set to ‘0’
Physical pin QEB is at logic ‘0’, if QEAPOL bit is set to ‘0’ and SWPAB bit is set to ‘1’
Physical pin QEB is at logic ‘1’, if QEAPOL bit is set to ‘1’ and SWPAB bit is set to ‘1’
2019-2020 Microchip Technology Inc.
DS60001570C-page 487
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 28-3:
Bit
Range
31:24
23:16
15:8
7:0
QEIxSTAT: QEIx STATUS REGISTER (‘X’ = 1-3)
Bit
Bit
31/23/15/7 30/22/14/6
U-0
U-0
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
RC-0, HS
R/W-0
RC-0, HS
R/W-0
RC-0, HS
R/W-0
—
RC-0, HS
(1)
PCIIRQ
—
R/W-0
PCIIEN
PCHEQIRQ PCHEQIEN
RC-0, HS
R/W-0
VELOVIRQ VELOVIEN
PCLEQIRQ
PCLEQIEN POSOVIRQ POSOVIEN
RC-0, HS
R/W-0
RC-0, HS
R/W-0
HOMIRQ
HOMIEN
IDXIRQ
IDXIEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13
PCHEQIRQ: Position Counter Greater Than or Equal Compare Status bit
1 = POSxCNT QEIxICCH
0 = POSxCNT < QEIxICCH
bit 12
PCHEQIEN: Position Counter Greater Than or Equal Compare Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 11
PCLEQIRQ: Position Counter Less Than or Equal Compare Status bit
1 = POSxCNT QEIxCMPL
0 = POSxCNT > QEIxCMPL
bit 10
PCLEQIEN: Position Counter Less Than or Equal Compare Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 9
POSOVIRQ: Position Counter Overflow Status bit
1 = Overflow has occurred
0 = No overflow has occurred
bit 8
POSOVIEN: Position Counter Overflow Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 7
PCIIRQ: Position Counter (Homing) Initialization Process Complete Status bit(1)
1 = POSxCNT was reinitialized
0 = POSxCNT was not reinitialized
bit 6
PCIIEN: Position Counter (Homing) Initialization Process Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 5
VELOVIRQ: Velocity Counter Overflow Status bit
1 = Overflow has occurred
0 = No overflow has not occurred
bit 4
VELOVIEN: Velocity Counter Overflow Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
Note 1:
This status bit in only applies to PIMOD modes ‘011’ and ‘100’.
DS60001570C-page 488
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 28-3:
QEIxSTAT: QEIx STATUS REGISTER (‘X’ = 1-3) (CONTINUED)
bit 3
HOMIRQ: Status Flag for Home Event Status bit
1 = Home event has occurred
0 = No Home event has occurred
bit 2
HOMIEN: Home Input Event Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 1
IDXIRQ: Status Flag for Index Event Status bit
1 = Index event has occurred
0 = No Index event has occurred
bit 0
IDXIEN: Index Input Event Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
Note 1:
This status bit in only applies to PIMOD modes ‘011’ and ‘100’.
2019-2020 Microchip Technology Inc.
DS60001570C-page 489
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 28-4:
Bit
Range
31:24
23:16
15:8
7:0
POSxCNT: POSITION COUNTER REGISTER (‘X’ = 1-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POSCNT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POSCNT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POSCNT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POSCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
POSCNT: 32-bit Position Counter Register bits
The Operating mode of the position counter is controlled by the CCM bit in the QEIxCON register.
Quadrature Count mode: The QEA and QEB inputs are decoded to generate count pulses and direction
information for controlling the position counter operation.
External Count with External Up/Down mode: The QEA/EXTCNT input is treated as an external count
signal, and the QEB/DIR/GATE input provides the count direction information.
External Count with External Gate mode: The QEA/EXTCNT input is treated as an external count signal.
If the GATEN bit in the QEIxCON register is equal to ‘1’, the QEB/DIR/GATE input will gate the counter
signal.
Internal Timer mode: The position counter uses PBCLK2 divided by the clock divider INTDIV as the count
source.
DS60001570C-page 490
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 28-5:
Bit
Range
31:24
23:16
15:8
7:0
VELxCNT: VELOCITY COUNTER REGISTER (‘X’ = 1-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VELCNT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VELCNT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VELCNT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VELCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
VELCNT: 32-bit Velocity Counter bits
The velocity counter is automatically cleared after every processor read of the velocity counter. It is not reset
by the index input or otherwise affected by any of the PIMOD specified modes. The contents of the
counter represents the distance traveled during the time between samples. Velocity equals the distance
traveled per unit of time. The velocity counter can save the application software the trouble of performing
32-bit math operations between current and previous position counter values to calculate velocity. If the
velocity counter rolls over from 0x7FFFFFFF to 0x80000000, or from 0x80000000 to 0x7FFFFFFF, an
overflow/underflow condition is detected. If the VELOVIEN bit is set in the QEISTAT register, an interrupt will
be generated.
2019-2020 Microchip Technology Inc.
DS60001570C-page 491
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 28-6:
Bit
Range
31:24
23:16
15:8
7:0
VELxHLD: VELOCITY HOLD REGISTER (‘X’ = 1-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VELHLD
R/W-0
VELHLD
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VELHLD
R/W-0
VELHLD
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
VELHLD: 32-bit Velocity Hold bits
When VELxCNT is read, the contents are captured at the same time into the VELxHLD register.
REGISTER 28-7:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
INTxHLD: INTERVAL TIMER HOLD REGISTER (‘X’ = 1-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTHLD
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTHLD
R/W-0
INTHLD
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTHLD
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
INTHLD: 32-bit Index Counter Hold bits
When the next count pulse is detected, the current contents of the interval timer (INTxTMR) are transferred
to the Interval Hold register (INTxHLD) and the interval timer is cleared and the process repeats.
DS60001570C-page 492
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 28-8:
Bit
Range
31:24
23:16
15:8
7:0
INDxCNT: INDEX COUNTER REGISTER (‘X’ = 1-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INDxCNT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INDxCNT
R/W-0
INDxCNT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INDxCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
IDXCNT: 32-bit Position Counter bits
REGISTER 28-9:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
INTxTMR: INTERVAL TIMER REGISTER (‘X’ = 1-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTTMR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTTMR
R/W-0
INTTMR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTTMR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
INTTMR: 32-bit Interval Timer Counter bits
The INTxTMR register provides a means to measure the time between each decoded quadrature count
pulse to yield improved velocity information. The interval timer should be set to run at a frequency chosen
such that the counter does not overflow at the expected minimum operating speed of the motor. The interval
timer is automatically cleared when a count pulse is detected. The timer then counts at the specified rate
based on the setting of the INTDIV bit in the QEIxCON register.
2019-2020 Microchip Technology Inc.
DS60001570C-page 493
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 28-10: QEIxICC: QEIx INITIALIZE/CAPTURE/COMPARE REGISTER (‘X’ = 1-3)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ICCH
R/W-0
ICCH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ICCH
R/W-0
ICCH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
ICCH: 32-bit Initialize/Capture/Compare High bits
REGISTER 28-11: QEIxCMPL: CAPTURE LOW REGISTER (‘X’ = 1-3)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPL
R/W-0
CMPL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPL
R/W-0
CMPL
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
CMPL: 32-bit Compare Low Value bits
DS60001570C-page 494
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
29.0
Note:
MOTOR CONTROL PWM
MODULE
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 44. “Motor
Control
PWM
(MCPWM)”
(DS60001393), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The PIC32MK GPG/MCJ with CAN FD Family of
devices support a dedicated Motor Control PulseWidth Modulation (PWM) module with up to 24
outputs.
The Motor Control PWM module consists of the
following major features:
• Two master time base modules with special event
triggers
• PWM module input clock prescaler
• Two synchronization inputs
• Two synchronization outputs
• 9 PWM generators with complimentary output
pairs
• Period, duty cycle, phase shift and dead time
minimum resolution of 1/FSYSCLK in EdgeAligned mode and 2/FSYSCLK minimum
resolution in Center-Aligned mode
• Cycle by cycle fault recovery and latched fault
modes
• PWM time-base capture upon current limit
• 10 fault input pins are available for faults and current limits
• Programmable analog-to-digital trigger with
interrupt for each PWM pair
• Complementary PWM outputs
• Push-Pull PWM outputs
• Edge-Aligned PWM mode
• Center-Aligned PWM mode
• Variable Phase PWM mode
• Multi-Phase PWM mode
2019-2020 Microchip Technology Inc.
•
•
•
•
•
•
•
•
•
•
Fixed-Off Time PWM mode
Current Limit PWM mode
Current Reset PWM mode
PWMxH and PWMxL output override control
PWMxH and PWMxL output pin swapping
Chopping mode (also known as Gated mode)
Dead time insertion
Dead time compensation
Enhanced Leading-Edge Blanking (LEB)
15 mA PWM pin output drive
The Motor Control PWM module contains up to twelve
PWM generators. Two master time base generators
provide a synchronous signal as a common time base
to synchronize the various PWM outputs. Each generator can operate independently or in synchronization
with either of the two master time bases. The individual
PWM outputs are available on the output pins of the
device. The input Fault signals and current-limit signals, when enabled, can monitor and protect the system by placing the PWM outputs into a known “safe”
state.
Each PWM can generate a trigger to the ADC module
to sample the analog signal at a specific instance
during the PWM period. In addition, the Motor Control
PWM module also generates two Special Event
Triggers to the ADC module based on the two master
time bases.
PWM generators 1 through 9 have two outputs,
PWMxH and PWMxL, brought out to the dedicated
pins.
Figure 29-1 illustrates an architectural overview of the
Motor Control PWM module and its interconnection
with the CPU and other peripherals.
DS60001570C-page 495
MOTOR CONTROL PWM MODULE ARCHITECTURAL OVERVIEW
PBCLK2
Primary and Secondary
Master Time Bases
Synchronization
PWMxH
Triggers
GENERATORS
PWM 1-9
PWMxL
DATA BUS
PWM Interrupt
CPU
FLTx / Current Limit / DTCMPy
2019-2020 Microchip Technology Inc.
ADC
PWM
PIN
Function
(DTC Enb)
PWM1
FLT3
DTCCMP1
PWM2
FLT4
DTCCMP2
PWM3
FLT5
DTCCMP3
PWM4
FLT6
DTCCMP4
PWM5
FLT7
DTCCMP5
PWM6
FLT8
DTCCMP6
PWM7
FLT12
DTCCMP7
PWM8
FLT13
DTCCMP8
PWM9
FLT14
DTCCMP9
Generator and Master
Time Base Triggers
NOTE: Since DTCOMPx, (i.e. dead time compensation) , FLTx and Current Limit share the same digital input pins, their
availability is mutually exclusive with fault function as the highest priority.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 496
FIGURE 29-1:
3 PHASE AC MOTOR CONTROL EXAMPLE
Max Differential Op-Amp Gain = 3.1v / (RSHUNT * ISHUNT)
R2 = Max Gain * (2 * R1)
Differential Mode ƒ-3dB = 1 / (2ʌ(2*R1)(470pf/2+1nf))
Common Mode ƒ-3dB = 1 / (2ʌ*R1*470pf)
R1, R2 = 0.1%, R1=1K
From AC
Full-Wave Rectifier
VDC
470pf
PWM2H
PWM1H
PWM1L
PWM2L
3ͲPhase
AC
Motor
R1
R1
R1
1nf
R1
PWM3H
PWM3L
470pf
Isense_1
PIC32MKxxMCxx
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
R2
Ͳ
Op-Amp
+
R2
1.65v
Simultaneous
3 channel
Sampling
470pf
0.1
Isense_2
ADCn
R1
R1
R1
1nf
R1
R2
Ͳ
0.1
470pf
Op-Amp
ADCn+1
+
R2
1.65v
470pf
Isense_Sum
+1.6v
0.0v
-1.6v
Rshunt=0.1
470pf
Optional VSENSE
R1
R1
R1
1nf
R1
470pf
R2
Ͳ
Op-Amp
ADCn+2
+
R2
DACx
1.65v
V3_Sense
Vref
Comp
DS60001570C-page 497
ANx
ANy
ANz
V2_Sense
V1_Sense
1.65v
DAC
1
PWM
Fault
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
FIGURE 29-2:
PIC32MK GPG/MCJ with CAN FD Family
29.1
PWM Faults
The PWM module incorporates multiple external Fault
inputs to include FLT1 and FLT2, which are remappable using the PPS feature, and FLT15, which has been
implemented with Class B safety features, and is available on a fixed pin at reset for Fault detection.
Fault pins are selectable for active level (active high or
low). FLT pins provide a safe and reliable way to shut
down the PWM outputs, tri-state, when the Fault input
is asserted. Therefore, the user should provide the necessary external pull-up or pull-down to disable the high
or low side FETs in motor control applications.
29.1.1
PWM FAULTS AT RESET
During any reset event, the PWM module maintains
ownership of the Class B fault FLT15. At reset, this fault
is enabled in latched mode to guarantee the fail-safe
power-up of the application. The application software
must clear the PWM fault before enabling the HighSpeed Motor Control PWM module. To clear the fault
condition, the FLT15 pin must first be pulled low externally or the internal pull down resistor in the CNPDx
register can be enabled.
Note:
29.1.2
WRITE-PROTECTED REGISTERS
Write protection is implemented for the IOCONx register. The write protection feature prevents any inadvertent writes. This protection feature can be controlled by
the PWMLOCK Configuration bit (DEVCFG3).
The default state of the write protection feature is disabled (PWMLOCK = 1). The write protection feature
can be enabled by configuring the PWMLOCK = 0.
To gain write access, the application software must
write two consecutive values of (0xABCD and 0x4321)
to the PWMKEY register to perform the unlock operation. The write access to the IOCONx register must be
the next SFR access following the unlock process.
There can be no other SFR accesses during the unlock
process and subsequent write access. Every write to
the IOCONx register requires a prior unlock operation.
The unlocking sequence is described in Example 29-1.
Figure 29-3 shows the register interconnection
diagram for the Motor Control PWM module.
The Fault mode may be changed using
the FLTMOD bits (IOCONx)
regardless of the state of FLT15.
EXAMPLE 29-1:
PWM WRITE-PROTECTED REGISTER UNLOCK SEQUENCE
Untested Code – For Information Purposes Only
; In the default Reset state, the FLT15 pin must be pulled low externally to clear and disable
; the fault.
; Writing to IOCONx register requires unlock sequence
di
v1
ehb
;Disable interrupts
mov
#0xXXXX,r3
;Move desired IOCON4 register data to r3 register
mov
#0xabcd,r1
;Load first unlock key to r1 register
mov
#0x4321,r2
;Load second unlock key to r2 register
mov
r1, PWMKEY
;Write first unlock key to PWMKEY register
mov
r2, PWMKEY
;Write second unlock key to PWMKEY register
mov
r3,IOCON4
;Write desired value to IOCON SFR for channel 4
mfc0
v0,c0_status
ori
v0,v0,0x1
mtc0
v0,c0_status
ehb
;Re-enable Interrupts
DS60001570C-page 498
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 29-3:
MOTOR CONTROL PWM MODULE REGISTER INTERCONNECTION DIAGRAM
PTCON
Module Control and Timing
Special Event
Postscaler
Comparator
Comparator
Synchronization
Special Event Compare Trigger
SEVTCMP
PTPER
Special Event Trigger
Master Time Base Counter
Primary Master Time Base
(PMTMR)
Clock
Prescaler
PMTMR
SSEV TCMP
STPER
Special Event Compare Trigger
Special Event
Postscaler
Comparator
Comparator
Special Event Trigger
Secondary Master Time Base
(SMTMR)
Clock
Prescaler
SMTMR
PWM Generator 1
PDCx/SDCx
Master Period
32-bit Data Bus
Synchronization
Master Time Base Counter
PWM Output Mode
Control Logic
MUX
ADC Trigger
User Override Logic
Comparator
Comparator
Current-Limit
Override Logic
TRIGx/STRIGx
Dead
Time
and
Compensation
Logic
Pin
Control
Logic
PWM1H
PWM1L
Fault Override Logic
PTMRx
CAPx
I nterrupt
Logic
PWMCONx
TRGCONx
DTCMP1
Fault and
Current-Limit
Logic
FLTx/DTCMPy
ALTDTRx
LEBCONx
Master Period
Synchronization
PHASEx
IOCONx
DTRx
PWMxH
PWM Generator ‘x’
PWMxL
FLTy/DTCMPz
Legend:
‘x’ = 1 through 12.
‘y’ = 1 through 8 and 15.
‘z’ = 3 through 8.
Note: Since DTCMPx and FLTx share the same digital input pins, their availability is mutually exclusive.
2019-2020 Microchip Technology Inc.
DS60001570C-page 499
Motor Control PWM Control Registers
MCPWM REGISTER MAP
Register
Name
A000 PTCON
A010 PTPER
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
—
—
—
15:0
PTEN
—
PTSIDL
SESTAT
—
—
—
—
—
—
SEIEN
PWMRDY
—
—
—
31:16
—
—
—
—
—
—
—
—
—
15:0
A020 SEVTCMP
31:16
31:16
—
—
—
—
—
—
—
A050 STPER
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
SSESTAT
SSEIEN
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
A0E0 PDC1
—
—
—
—
—
—
—
—
—
—
—
—
15:0 CHPCLKEN
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
CLIF
TRGIF
PWMLIF
15:0
FLTSTAT
CLTSTAT
—
—
31:16
—
—
15:0
PENH
PENL
POLH
POLL
31:16
—
—
—
—
DS60001570C-page 500
31:16
—
PWMHIF
—
31:16
—
—
—
—
—
—
—
ECAM
CLSRC
PMOD
—
—
—
ITB
—
CLPOL
CLMOD
OVRENH OVRENL
—
FLTIEN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCLKDIV
SEVTPS
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
XPRES
—
0000
FLTMOD
0078
—
‘—’ = unimplemented; read as ‘0’.
—
—
—
—
—
—
DTR
0000
0020
0000
0000
0000
0000
—
—
—
0000
0000
0000
0000
CLIEN
TRGIEN PWMLIEN PWMHIEN
DTCP
PTDIR
MTBS
FLTSRC
FLTPOL
FLTDAT
CLDAT
SWAP
OSYNC 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
PHASE
—
0000
—
OVRDAT
—
0000
0000
SDC
—
0000
0000
—
—
0000
0020
DTC
—
0000
0000
—
PDC
15:0
Legend:
—
—
15:0
A110 DTR1
—
CHOPCLK
15:0
A100 PHASE1
—
PWMKEY
FLTIF
31:16
—
SEVTPS
SMTMR
15:0
A0F0 SDC1
—
16/0
SSEVTCMP
—
A0C0 PWMCON1 31:16
—
17/1
STPER
15:0
A0D0 IOCON1
—
—
15:0
A090 PWMKEY
—
—
15:0
A080 CHOP
—
—
31:16
—
PCLKDIV
18/2
PMTMR
15:0
A070 SMTMR
—
31:16
A060 SSEVTCMP 31:16
19/3
SEVTCMP
15:0
A040 STCON
20/4
PTPER
15:0
A030 PMTMR
21/5
All Resets
Bits
Bit Range
Virtual Address
(BF82_#)
TABLE 29-1:
—
0000
0000
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
29.2
Register
Name
A120 ALTDTR1
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
A130 DTCOMP1
A140 TRIG1
—
—
15:0
—
—
31:16
—
—
—
—
—
—
—
31:16
31:16
—
—
—
—
—
—
—
—
—
TRGDIV
—
—
—
—
—
TRGSEL
—
—
—
—
31:16
—
A190 LEBDLY1
A1A0 AUXCON1
A1B0 PTMR1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
DTM
STRGIS
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
PLR
PLF
31:16
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
FLTIEN
CLIEN
—
2019-2020 Microchip Technology Inc.
CLIF
TRGIF
PWMLIF
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
LEB
15:0
FLTSTAT
CLTSTAT
—
—
31:16
—
—
15:0
PENH
PENL
POLH
POLL
31:16
—
—
—
—
PWMHIF
—
ECAM
CLSRC
PMOD
—
—
31:16
31:16
—
0000
CHOPSEL
—
—
—
—
—
ITB
—
CLPOL
CLMOD
OVRENH OVRENL
—
—
—
—
—
—
—
0000
—
XPRES
—
0000
FLTMOD
0078
—
—
—
—
—
—
—
TRGIEN PWMLIEN PWMHIEN
DTCP
PTDIR
MTBS
FLTSRC
OVRDAT
—
FLTPOL
FLTDAT
CLDAT
SWAP
OSYNC 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
‘—’ = unimplemented; read as ‘0’.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
DTR
—
0000
0000
PHASE
—
0000
0000
SDC
—
0000
0000
DTC
—
0000
CHOPHEN CHOPLEN 0000
PDC
—
0000
—
TMR
FLTIF
0000
0000
PHF
31:16
0000
0000
PHR
—
0000
0000
15:0
FLTLEBEN CLLEBEN
0000
—
15:0
Legend:
—
—
15:0
A220 ALTDTR2
—
—
15:0
A210 DTR2
16/0
—
31:16
A200 PHASE2
17/1
—
15:0
A1F0 SDC2
18/2
31:16
A1C0 PWMCON2 31:16
A1E0 PDC2
19/3
CAP
15:0
A1D0 IOCON2
20/4
STRGCMP
15:0
A180 LEBCON1
21/5
STRGSEL
15:0
A170 CAP1
22/6
TRGCMP
15:0
A160 STRIG1
23/7
COMP
15:0
A150 TRGCON1
24/8
ALTDTR
31:16
All Resets
Bits
Bit Range
Virtual Address
(BF82_#)
MCPWM REGISTER MAP (CONTINUED)
0000
0000
ALTDTR
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 501
TABLE 29-1:
Register
Name
A230 DTCOMP2
A240 TRIG2
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
31:16
—
—
—
—
—
—
15:0
A250 TRGCON2
31:16
31:16
—
—
—
—
TRGDIV
—
—
—
—
—
TRGSEL
—
—
—
—
31:16
—
A290 LEBDLY2
A2A0 AUXCON2
A2B0 PTMR2
—
—
—
—
—
—
—
—
—
DS60001570C-page 502
Legend:
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
DTM
STRGIS
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
PLR
PLF
31:16
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
FLTIEN
CLIEN
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
LEB
—
0000
CHOPSEL
—
—
—
CLIF
TRGIF
PWMLIF
15:0
FLTSTAT
CLTSTAT
—
—
31:16
—
—
15:0
PENH
PENL
POLH
POLL
31:16
—
—
—
—
PWMHIF
—
ECAM
CLSRC
PMOD
—
—
—
—
ITB
—
CLPOL
CLMOD
OVRENH OVRENL
—
—
—
—
—
—
—
0000
—
XPRES
—
0000
FLTMOD
0078
—
TRGIEN PWMLIEN PWMHIEN
DTCP
PTDIR
MTBS
FLTSRC
OVRDAT
FLTPOL
FLTDAT
CLDAT
SWAP
OSYNC 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PDC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
‘—’ = unimplemented; read as ‘0’.
—
—
—
—
—
—
—
0000
0000
ALTDTR
31:16
0000
0000
DTR
—
0000
0000
PHASE
31:16
0000
0000
SDC
—
0000
0000
DTC
—
0000
CHOPHEN CHOPLEN 0000
TMR
FLTIF
0000
0000
PHF
—
0000
0000
PHR
31:16
0000
0000
15:0
FLTLEBEN CLLEBEN
0000
—
15:0
A330 DTCOMP3
—
—
15:0
A320 ALTDTR3
—
—
15:0
A310 DTR3
16/0
—
31:16
A300 PHASE3
17/1
—
15:0
A2F0 SDC3
18/2
31:16
A2C0 PWMCON3 31:16
A2E0 PDC3
19/3
CAP
15:0
A2D0 IOCON3
20/4
STRGCMP
15:0
A280 LEBCON2
21/5
—
STRGSEL
15:0
A270 CAP2
22/6
TRGCMP
15:0
A260 STRIG2
23/7
COMP
—
All Resets
Bits
Bit Range
Virtual Address
(BF82_#)
MCPWM REGISTER MAP (CONTINUED)
0000
0000
COMP
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 29-1:
Register
Name
A340 TRIG3
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
A350 TRGCON3
31:16
15:0
A360 STRIG3
31:16
—
—
—
TRGDIV
—
—
—
—
—
TRGSEL
—
—
—
—
31:16
—
A390 LEBDLY3
A3A0 AUXCON3
A3B0 PTMR3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
DTM
STRGIS
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
0000
0000
PHF
PLR
PLF
31:16
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
FLTIEN
CLIEN
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
LEB
CLIF
TRGIF
PWMLIF
15:0
FLTSTAT
CLTSTAT
—
—
31:16
—
—
15:0
PENH
PENL
POLH
POLL
31:16
—
—
—
—
2019-2020 Microchip Technology Inc.
31:16
31:16
—
0000
CHOPSEL
—
—
—
PWMHIF
—
ECAM
CLSRC
PMOD
—
—
—
—
ITB
—
CLPOL
CLMOD
OVRENH OVRENL
—
—
—
—
—
—
—
0000
—
XPRES
—
0000
FLTMOD
0078
—
TRGIEN PWMLIEN PWMHIEN
DTCP
PTDIR
MTBS
FLTSRC
OVRDAT
FLTPOL
FLTDAT
CLDAT
SWAP
OSYNC 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PDC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
31:16
—
—
15:0
‘—’ = unimplemented; read as ‘0’.
—
—
—
—
—
—
—
—
—
—
—
—
—
TRGCMP
0000
0000
COMP
—
0000
0000
ALTDTR
31:16
0000
0000
DTR
—
0000
0000
PHASE
—
0000
0000
SDC
—
0000
0000
DTC
—
0000
CHOPHEN CHOPLEN 0000
TMR
FLTIF
0000
0000
PHR
FLTLEBEN CLLEBEN
0000
—
15:0
Legend:
—
—
15:0
A440 TRIG4
—
15:0
31:16
A430 DTCOMP4
16/0
—
15:0
A420 ALTDTR4
17/1
—
15:0
A410 DTR4
18/2
—
31:16
A400 PHASE4
19/3
—
15:0
A3F0 SDC4
20/4
31:16
A3C0 PWMCON4 31:16
A3E0 PDC4
21/5
CAP
15:0
A3D0 IOCON4
22/6
STRGCMP
15:0
A380 LEBCON3
23/7
STRGSEL
15:0
A370 CAP3
24/8
TRGCMP
—
All Resets
Bits
Bit Range
Virtual Address
(BF82_#)
MCPWM REGISTER MAP (CONTINUED)
—
0000
0000
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 503
TABLE 29-1:
Register
Name
A450 TRGCON4
31:16
31/15
—
15:0
A460 STRIG4
31:16
30/14
29/13
28/12
—
—
—
TRGDIV
—
—
—
27/11
26/10
—
—
TRGSEL
—
—
—
25/9
24/8
—
—
STRGSEL
—
15:0
A470 CAP4
31:16
A490 LEBDLY4
A4A0 AUXCON4
A4B0 PTMR4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
0000
PHR
PHF
PLR
PLF
31:16
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
FLTIEN
CLIEN
FLTLEBEN CLLEBEN
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
LEB
CLIF
TRGIF
PWMLIF
15:0
FLTSTAT
CLTSTAT
—
—
31:16
—
—
15:0
PENH
PENL
POLH
POLL
31:16
—
—
—
—
31:16
31:16
—
—
CHOPSEL
—
—
—
PWMHIF
—
ECAM
CLSRC
PMOD
—
—
—
—
ITB
—
CLPOL
CLMOD
OVRENH OVRENL
—
—
—
—
—
—
—
0000
—
XPRES
—
0000
FLTMOD
0078
—
—
—
—
—
—
—
—
—
—
—
—
—
TRGIEN PWMLIEN PWMHIEN
DTCP
PTDIR
MTBS
FLTSRC
OVRDAT
FLTPOL
FLTDAT
CLDAT
SWAP
OSYNC 0000
DS60001570C-page 504
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
DTM
STRGIS
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRGDIV
‘—’ = unimplemented; read as ‘0’.
—
—
—
TRGSEL
—
—
STRGSEL
0000
0000
0000
0000
TRGCMP
—
0000
0000
COMP
—
0000
0000
ALTDTR
—
0000
0000
DTR
—
0000
0000
PHASE
—
0000
0000
DTC
—
0000
CHOPHEN CHOPLEN 0000
SDC
—
15:0
0000
PDC
31:16
31:16
—
TMR
FLTIF
0000
—
15:0
Legend:
—
—
15:0
A550 TRGCON5
—
STRGIS
—
15:0
A540 TRIG5
—
DTM
15:0
31:16
A530 DTCOMP5
16/0
—
15:0
A520 ALTDTR5
17/1
—
15:0
A510 DTR5
18/2
—
31:16
A500 PHASE5
19/3
—
15:0
A4F0 SDC5
20/4
31:16
A4C0 PWMCON5 31:16
A4E0 PDC5
21/5
CAP
15:0
A4D0 IOCON5
22/6
STRGCMP
15:0
A480 LEBCON4
23/7
All Resets
Bits
Bit Range
Virtual Address
(BF82_#)
MCPWM REGISTER MAP (CONTINUED)
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 29-1:
Register
Name
A560 STRIG5
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
A570 CAP5
31:16
A590 LEBDLY5
A5A0 AUXCON5
A5B0 PTMR5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PLR
PLF
31:16
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
FLTIEN
CLIEN
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
LEB
CLIF
TRGIF
PWMLIF
15:0
FLTSTAT
CLTSTAT
—
—
31:16
—
—
15:0
PENH
PENL
POLH
POLL
31:16
—
—
—
—
31:16
2019-2020 Microchip Technology Inc.
31:16
—
—
CHOPSEL
—
—
—
PWMHIF
—
ECAM
CLSRC
PMOD
—
—
—
—
ITB
—
CLPOL
CLMOD
OVRENH OVRENL
—
—
—
—
—
—
—
0000
—
XPRES
—
0000
FLTMOD
0078
—
—
—
—
—
—
—
—
—
—
—
—
—
TRGIEN PWMLIEN PWMHIEN
DTCP
PTDIR
MTBS
FLTSRC
OVRDAT
FLTPOL
FLTDAT
CLDAT
SWAP
OSYNC 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
DTM
STRGIS
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRGDIV
—
—
15:0
‘—’ = unimplemented; read as ‘0’.
—
—
—
TRGSEL
—
—
—
—
—
STRGSEL
—
—
STRGCMP
0000
0000
0000
0000
TRGCMP
—
0000
0000
COMP
—
0000
0000
ALTDTR
—
0000
0000
DTR
—
0000
0000
PHASE
—
0000
0000
DTC
—
0000
CHOPHEN CHOPLEN 0000
SDC
—
31:16
0000
PDC
31:16
31:16
—
TMR
FLTIF
0000
0000
PHF
FLTLEBEN CLLEBEN
0000
0000
PHR
15:0
Legend:
—
—
15:0
A660 STRIG6
—
—
15:0
A650 TRGCON6
—
—
15:0
A640 TRIG6
16/0
15:0
31:16
A630 DTCOMP6
17/1
—
15:0
A620 ALTDTR6
18/2
—
15:0
A610 DTR6
19/3
—
31:16
A600 PHASE6
20/4
—
15:0
A5F0 SDC6
21/5
31:16
A5C0 PWMCON6 31:16
A5E0 PDC6
22/6
CAP
15:0
A5D0 IOCON6
23/7
STRGCMP
15:0
A580 LEBCON5
24/8
All Resets
Bits
Bit Range
Virtual Address
(BF82_#)
MCPWM REGISTER MAP (CONTINUED)
0000
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 505
TABLE 29-1:
Register
Name
A670 CAP6
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
A680 LEBCON6
A690 LEBDLY6
A6A0 AUXCON6
A6B0 PTMR6
—
—
—
—
—
—
—
—
0000
PHF
PLR
PLF
31:16
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
FLTIEN
CLIEN
FLTLEBEN CLLEBEN
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
LEB
CLIF
TRGIF
PWMLIF
15:0
FLTSTAT
CLTSTAT
—
—
31:16
—
—
15:0
PENH
PENL
POLH
POLL
31:16
—
—
—
—
31:16
31:16
—
—
—
—
—
—
—
PWMHIF
—
ECAM
CLSRC
PMOD
—
—
—
—
ITB
—
CLPOL
CLMOD
OVRENH OVRENL
—
—
—
—
—
—
—
0000
—
XPRES
—
0000
FLTMOD
0078
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRGIEN PWMLIEN PWMHIEN
DTCP
PTDIR
MTBS
FLTSRC
OVRDAT
FLTPOL
FLTDAT
CLDAT
SWAP
OSYNC 0000
DS60001570C-page 506
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
DTM
STRGIS
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRGDIV
—
—
—
—
—
TRGSEL
—
—
—
—
—
STRGSEL
—
—
—
15:0
‘—’ = unimplemented; read as ‘0’.
—
—
—
—
—
—
CAP
—
0000
0000
0000
0000
STRGCMP
—
0000
0000
TRGCMP
—
0000
0000
—
—
0000
0000
COMP
—
0000
0000
ALTDTR
—
0000
0000
DTR
—
0000
0000
DTC
—
0000
CHOPHEN CHOPLEN 0000
PHASE
—
31:16
CHOPSEL
SDC
—
31:16
0000
PDC
31:16
31:16
—
TMR
FLTIF
0000
—
15:0
Legend:
—
PHR
15:0
A770 CAP7
—
—
15:0
A760 STRIG7
—
—
15:0
A750 TRGCON7
16/0
—
15:0
A740 TRIG7
17/1
15:0
31:16
A730 DTCOMP7
18/2
—
15:0
A720 ALTDTR7
19/3
—
15:0
A710 DTR7
20/4
—
31:16
A700 PHASE7
21/5
—
15:0
A6F0 SDC7
22/6
31:16
A6C0 PWMCON7 31:16
A6E0 PDC7
23/7
CAP
15:0
A6D0 IOCON7
24/8
All Resets
Bits
Bit Range
Virtual Address
(BF82_#)
MCPWM REGISTER MAP (CONTINUED)
0000
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 29-1:
Register
Name
A780 LEBCON7
A790 LEBDLY7
A7A0 AUXCON7
A7B0 PTMR7
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
31:16
—
—
—
—
15:0
PHR
PHF
PLR
PLF
31:16
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
FLTIEN
CLIEN
FLTLEBEN CLLEBEN
—
—
LEB
15:0
A7C0 PWMCON8 31:16
A7D0 IOCON8
A7E0 PDC8
CLIF
TRGIF
PWMLIF
15:0
FLTSTAT
CLTSTAT
—
—
31:16
—
—
15:0
PENH
PENL
POLH
POLL
31:16
—
—
—
—
PWMHIF
—
ECAM
CLSRC
PMOD
—
—
—
—
ITB
—
CLPOL
CLMOD
OVRENH OVRENL
—
15:0
A7F0 SDC8
31:16
31:16
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
2019-2020 Microchip Technology Inc.
A840 TRIG8
—
—
—
—
—
—
—
31:16
—
—
15:0
—
—
31:16
—
—
31:16
31:16
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
TRGDIV
—
—
—
—
—
TRGSEL
—
—
—
—
Legend:
—
—
—
—
0000
—
XPRES
—
0000
FLTMOD
0078
—
—
TRGIEN PWMLIEN PWMHIEN
DTCP
PTDIR
MTBS
FLTSRC
OVRDAT
FLTPOL
FLTDAT
CLDAT
SWAP
OSYNC 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
DTM
STRGIS
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
15:0
PHR
PHF
PLR
PLF
‘—’ = unimplemented; read as ‘0’.
—
—
FLTLEBEN CLLEBEN
0000
0000
0000
0000
0000
0000
0000
0000
CAP
31:16
0000
0000
—
—
0000
0000
—
—
0000
0000
STRGCMP
—
0000
0000
DTC
—
STRGSEL
15:0
A880 LEBCON8
—
COMP
15:0
A870 CAP8
—
TRGCMP
15:0
A860 STRIG8
—
ALTDTR
15:0
A850 TRGCON8
—
DTR
15:0
A830 DTCOMP8
—
0000
CHOPHEN CHOPLEN 0000
PHASE
15:0
A820 ALTDTR8
CHOPSEL
SDC
15:0
A810 DTR8
0000
PDC
15:0
A800 PHASE8
—
TMR
FLTIF
All Resets
Bits
Bit Range
Virtual Address
(BF82_#)
MCPWM REGISTER MAP (CONTINUED)
0000
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 507
TABLE 29-1:
Register
Name
A890 LEBDLY8
A8A0 AUXCON8
A8B0 PTMR8
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
FLTIEN
CLIEN
LEB
15:0
A8C0 PWMCON9 31:16
A8D0 IOCON9
A8E0 PDC9
FLTIF
CLIF
TRGIF
PWMLIF
15:0
FLTSTAT
CLTSTAT
—
—
31:16
—
—
15:0
PENH
PENL
POLH
POLL
31:16
—
—
—
—
31:16
PWMHIF
—
ECAM
CLSRC
PMOD
—
—
—
—
ITB
—
CLPOL
CLMOD
OVRENH OVRENL
—
31:16
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
A940 TRIG9
—
—
—
—
—
—
—
31:16
—
—
15:0
—
—
31:16
—
—
31:16
31:16
—
—
—
—
—
—
DTC
—
PTDIR
MTBS
FLTSRC
OVRDAT
—
DTCP
0000
—
XPRES
—
0000
FLTMOD
0078
FLTPOL
FLTDAT
CLDAT
SWAP
OSYNC 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
DTM
STRGIS
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS60001570C-page 508
‘—’ = unimplemented; read as ‘0’.
—
—
—
TRGSEL
—
—
—
—
—
STRGSEL
—
—
0000
0000
0000
0000
0000
0000
0000
0000
—
—
STRGCMP
0000
0000
COMP
TRGDIV
15:0
Legend:
—
0000
0000
TRGIEN PWMLIEN PWMHIEN
0000
0000
TRGCMP
15:0
A960 STRIG9
—
ALTDTR
15:0
A950 TRGCON9
—
DTR
15:0
A930 DTCOMP9
—
PHASE
15:0
A920 ALTDTR9
—
SDC
15:0
A910 DTR9
—
0000
CHOPHEN CHOPLEN 0000
PDC
15:0
A900 PHASE9
CHOPSEL
—
0000
0000
TMR
15:0
A8F0 SDC9
—
All Resets
Bits
Bit Range
Virtual Address
(BF82_#)
MCPWM REGISTER MAP (CONTINUED)
0000
0000
0000
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 29-1:
Register
Name
A970 CAP9
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
A980 LEBCON9
A990 LEBDLY9
A9A0 AUXCON9
A9B0 PTMR9
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
CAP
—
—
—
—
15:0
PHR
PHF
PLR
PLF
31:16
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
‘—’ = unimplemented; read as ‘0’.
—
—
FLTLEBEN CLLEBEN
—
—
0000
0000
31:16
15:0
Legend:
24/8
All Resets
Bits
Bit Range
Virtual Address
(BF82_#)
MCPWM REGISTER MAP (CONTINUED)
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
LEB
TMR
—
0000
CHOPSEL
—
—
—
0000
CHOPHEN CHOPLEN 0000
—
—
—
0000
0000
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 509
TABLE 29-1:
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-1:
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
HS/HC-0
R/W-0
HS/HC-0
U-0
U-0
PTEN
—
PTSIDL
SESTAT(1)
SEIEN(3)
PWMRDY
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15
PTCON: PWM PRIMARY TIME BASE CONTROL REGISTER
PCLKDIV(2)
W = Writable bit
‘1’ = Bit is set
SEVTPS(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
PTEN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
Note:
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-7
bit 6-4
Note 1:
2:
3:
Many of the PWM registers and/or bits as designated, do not allow updates once a PWM
module is enabled. Therefore, it is recommended that the user application initialize all
required PWM registers before setting the PTEN bit equal to ‘1’.
Unimplemented: Read as ‘0’
PTSIDL: PWM Time Base Stop in Idle Mode bit
1 = PWM time base halts in CPU Idle mode
0 = PWM time base runs in CPU Idle mode
SESTAT: Special Event Interrupt Status bit(1)
1 = Special Event Interrupt is pending
0 = Special Event Interrupt is not pending
SEIEN: Special Event Interrupt Enable bit
1 = Special Event Interrupt is enabled
0 = Special Event Interrupt is disabled
PWMRDY: PWM Module Status bit
1 = PWM module is ready and operation has begun
0 = PWM module is not ready
Unimplemented: Read as ‘0’
PCLKDIV: Primary PWM Input Clock Prescaler bits(2)
111 = Divide by 128, PWM resolution = 128/FSYSCLK
110 = Divide by 64, PWM resolution = 64/FSYSCLK
•
•
•
000 = Divide by 1, PWM resolution = 1/FSYSCLK (power-on default)
The SESTAT bit is cleared by clearing the SEIEN bit and the corresponding bit in the IFSx register.
The SEVTPS bits should be changed only when the PTEN bit (PTCON) = 0.
To clear the Primary Special Event Interrupt the user application must do the following:
1) Clear the SEIEN bit by setting it to ‘0’.
2) Clear the Primary Special Event Interrupt flag by setting IFS5 = 0.
3) Re-enabling the PTCON register by setting the SEIEN equal to ‘1’ if desired.
The user application will not be able to clear the Primary Special Event Interrupt flag as long as the SEIEN
bit is equal to ‘1’.
DS60001570C-page 510
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-1:
bit 3-0
Note 1:
2:
3:
PTCON: PWM PRIMARY TIME BASE CONTROL REGISTER (CONTINUED)
SEVTPS: PWM Special Event Trigger Output Postscaler Select bits(2)
1111 = 1:16 postscaler generates Special Event trigger at every 16th compare match event
•
•
•
0001 = 1:2 postscaler generates Special Event trigger at every second compare match event
0000 = 1:1 postscaler generates Special Event trigger at every compare match event
The SESTAT bit is cleared by clearing the SEIEN bit and the corresponding bit in the IFSx register.
The SEVTPS bits should be changed only when the PTEN bit (PTCON) = 0.
To clear the Primary Special Event Interrupt the user application must do the following:
1) Clear the SEIEN bit by setting it to ‘0’.
2) Clear the Primary Special Event Interrupt flag by setting IFS5 = 0.
3) Re-enabling the PTCON register by setting the SEIEN equal to ‘1’ if desired.
The user application will not be able to clear the Primary Special Event Interrupt flag as long as the SEIEN
bit is equal to ‘1’.
2019-2020 Microchip Technology Inc.
DS60001570C-page 511
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-2:
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0(3)
R/W-0(3)
R/W-0(3)
PTPER(1,2)
R/W-0
Note 1:
2:
3:
4:
R/W-0
R/W-1
R/W-0
R/W-0
PTPER
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
PTPER: PRIMARY MASTER TIME BASE PERIOD REGISTER
W = Writable bit
‘1’ = Bit is set
(1,2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
PTPER: Primary Master Time Base Period Value bits(1,2,4)
Minimum LSb = 1/FSYSCLK.
Minimum value is 0x0008.
If a period value is lesser than 0x0008 is chosen, the internal hardware forcefully sets the period to a
minimum value of 0x0008.
PTPER = (FSYSCLK/ (FPWM * PTCON))
FPWM = User Desired PWM Frequency
DS60001570C-page 512
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-3:
Bit Range
31:24
23:16
15:8
7:0
SEVTCMP: PWM PRIMARY SPECIAL EVENT COMPARE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP(1,2)
R/W-0
R/W-0
Note 1:
2:
31:24
23:16
15:8
7:0
W = Writable bit
‘1’ = Bit is set
Note 1:
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Minimum LSb = 1/FSYSCLK.
To trigger at the period boundary, set the SEVTCMP bit to 0x0 and not the PTPER period value.
PMTMR: PRIMARY MASTER TIME BASE TIMER REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
PMTMR(1)
R-0
R-0
R-0
R-0
R-0
PMTMR(1)
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
R/W-0
Unimplemented: Read as ‘0’
SEVTCMP: Special Event Compare Count Value bits(1,2)
The special event trigger allows analog-to-digital conversions to be synchronized to the master PWM time
base. The analog-to-digital sampling and conversion time may be programmed to occur at any point
within the PWM period.
REGISTER 29-4:
Bit Range
R/W-0
SEVTCMP(1,2)
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
R/W-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
PMTMR: Primary Master Time Base Timer Value bits(1)
This timer increments with each PWM clock until the PTPER value is reached.
LSb = 1/FSYSCLK.
2019-2020 Microchip Technology Inc.
DS60001570C-page 513
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-5:
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
HS/HC-0
R/W-0
U-0
U-0
U-0
—
—
—
U-0
R/W-0
R/W-0
—
Legend:
R = Readable bit
-n = Value at POR
bit 31-13
bit 12
bit 11
bit 10-7
bit 6-4
bit 3-0
Note 1:
2:
3:
STCON: SECONDARY MASTER TIME BASE CONTROL REGISTER
SSESTAT(1) SSEIEN(3)
SCLKDIV(2)
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
R/W-0
SEVTPS(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
SSESTAT: Secondary Special Event Interrupt Status bit(1)
1 = Secondary Special Event Interrupt is pending
0 = Secondary Special Event Interrupt is not pending
SSEIEN: Secondary Special Event Interrupt Enable bit(3)
1 = Secondary Special Event Interrupt is enabled
0 = Secondary Special Event Interrupt is disabled
Unimplemented: Read as ‘0’
SCLKDIV: Secondary PWM Input Clock Prescaler(2)
111 = Divide by 128, PWM resolution = (128/FSYSCLK)
110 = Divide by 64, PWM resolution = (64/FSYSCLK)
•
•
•
000 = Divide by 1, PWM resolution = 1/FSYSCLK (power-on default)
SEVTPS: PWM Secondary Special Event Trigger Output Postscaler Select bits(2)
1111 = 1:16 Postscale
•
•
•
0001 = 1:2 Postscale
0000 = 1:1 Postscale
The SSESTAT bit is cleared by clearing the SSEIEN bit and corresponding bit in the IFSx register.
These bits should be changed only when the PTEN bit (PTCON) = 0.
To clear the Secondary Special Event Interrupt, the user application must do the following:
1) First, clear the SSEIEN bit by setting it to ‘0’.
2) Next, clear the Secondary Special Event Interrupt flag, IFS5, by setting it to ‘0’.
3) Finally, re-enable the STCON register by setting the SSEIEN bit equal to ‘1’, if desired.
The user application will not be able to clear the Secondary Special Event Interrupt flag as long as the
SSEIEN bit is equal to ‘1’.
DS60001570C-page 514
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-6:
Bit Range
31:24
23:16
15:8
7:0
STPER: SECONDARY MASTER TIME BASE PERIOD REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0(3)
R/W-0(3)
R/W-0(3)
STPER(1,2,4)
R/W-0
R/W-0
Note 1:
2:
3:
4:
31:24
23:16
15:8
7:0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Minimum LSb = 1/FSYSCLK.
Minimum value is 0x0008.
If a period value lesser than 0x0008 is chosen, the internal hardware forcefully sets the period to a
minimum value of 0x0008.
STPER = (FSYSCLK/ (FPWM * PTCON))
FPWM = User Desired PWM Frequency
SSEVTCMP: PWM SECONDARY SPECIAL EVENT COMPARE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEVTCMP(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEVTCMP(1)
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
R/W-0
Unimplemented: Read as ‘0’
STPER: Secondary Master Time Base Period Value bits(1,2,4)
REGISTER 29-7:
Bit Range
R/W-0
STPER(1,2,4)
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
R/W-1
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
SSEVTCMP: Secondary Special Event Compare Value bits(1)
The secondary special event trigger allows analog-to-digital conversions to be synchronized to the
secondary master PWM time base. The analog-to-digital sampling and conversion time may be
programmed to occur at any point within the PWM period.
Note 1:
To trigger at the period boundary, set SSEVTCMP to 0x0 and not the PTPER period value.
2019-2020 Microchip Technology Inc.
DS60001570C-page 515
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-8:
Bit Range
31:24
23:16
15:8
7:0
SMTMR: SECONDARY MASTER TIME BASE TIMER REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
SMTMR(1)
R-0
R-0
Note 1:
R-0
R-0
SMTMR(1)
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
R-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
SMTMR: Secondary Master Time Base Timer Value bits(1)
This timer increments with each PWM FSYSCLK until the STPER value is reached.
Min LSb = 1/FSYSCLK.
DS60001570C-page 516
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-9:
Bit Range
31:24
23:16
15:8
7:0
CHOP: PWM CHOP CLOCK GENERATOR REGISTER
Bit
31/2 /15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
CHPCLKEN
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 14-10
bit 9-0
Note 1:
2:
3:
Note:
R/W-0
R/W-0
CHOPCLK(2,3)
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15
CHOPCLK(2,3)
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
CHPCLKEN: Enable Chop Clock Generator bit
1 = Chop clock generator is enabled(1)
0 = Chop clock generator is disabled
Unimplemented: Read as ‘0’
CHOPCLK: Chop Clock Divider bits(2,3)
Chop Frequency = (FSYSCLK/PCLKDIV) / (CHOPCLK)
The chop clock generator operates with the PCLKDIV bits (PTCON).
Minimum values is 0x0002. A value of 0x0000 or 0x0001 will produce no chop clock.
These bits should only be changed when the PTEN bit (PTCON) is clear.
The Chop Clock is a continuous high frequency signal (relative to PWM cycles) that is optionally gated with
the PWM output signals to allow the PWM signals to pass through an external isolation barrier such as a
pulse transformer or capacitor. The value of [CHOP * PWM clock duration] defines the high, and the
low times of the Chop Clock. A value of ‘8’ in the CHOP register yields a Chop Clock signal with a period
of 16 PWM clock cycles as defined by the primary PWM clock prescaler PCLKDIV A Value of 0x0000
or 0x0001 will produce no Chop Clock
2019-2020 Microchip Technology Inc.
DS60001570C-page 517
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-10: PWMKEY: PWM UNLOCK REGISTER
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
PWMKEY
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
W-0
PWMKEY
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
PWMKEY: PWM Unlock bits
If the PWMLOCK Configuration bit is asserted (PWMLOCK = 0), the IOCONx registers are writable only
after the proper sequence is written to the PWMKEY register. If the PWMLOCK Configuration bit is
deasserted (PWMLOCK = 1), the IOCONx registers are writable at all times. For more information on the
unlock sequence, refer to the 44.9 “Write Protection” in Section 44. Motor Control PWM (MCPWM)
(DS60001393) of the “PIC32 Family Reference Manual” for more information.
This register is implemented only in devices where the PWMLOCK Configuration bit is present in the
DEVCFG3 Configuration register.
Note:
The user must write two consecutive values of 0xABCD and 0x4321 to the PWMKEY register to perform
an unlock operation if PWMLOCK = 0. Write access to any subsequent secure register must be the very
next access following the unlock process. This is not an atomic operation and any CPU interrupts that occur
during or immediately after an unlock sequence may cause writes to any PWM secure register to fail.
DS60001570C-page 518
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-11: PWMCONx: PWM CONTROL REGISTER ‘x’ (‘x’ = 1 THROUGH 12)
Bit Range
Bit
31/23/15/7
R/W-0
R/W-0
R/W-0
31:24
FLTIF(1)
CLIF(1)
TRGIF(1)
23:16
15:8
7:0
Bit
30/22/14/6
bit 30
bit 29
bit 28
bit 27
bit 26-24
bit 23
bit 22
Note 1:
2:
3:
4:
5:
6:
7:
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
U-0
U-0
U-0
PWMLIF(1)
PWMHIF(1)
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
FLTIEN
CLIEN
TRGIEN
PWMLIEN
PWMHIEN
—
—
—
HS/HC-0
HS/HC-0
U-0
U-0
R/W-0
R/W-0
R/W-0
U-0
FLTSTAT
CLTSTAT
—
—
ITB(2)
—
R/W-0
R/W-0
R/W-0
HS/HC/R-0
R/W-0
U-0
R/W-0
U-0
DTCP(4)
PTDIR(6)
MTBS(7)
—
XPRES(3)
—
DTC
Legend:
R = Readable bit
-n = Value at POR
bit 31
Bit
29/21/13/5
W = Writable bit
‘1’ = Bit is set
ECAM(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
FLTIF: Fault Interrupt Flag bit(1)
1 = Fault interrupt has occurred
0 = Fault interrupt has not occurred
CLIF: Current-Limit Status bit(1)
1 = Current limit has occurred
0 = Current limit has not occurred
TRGIF: Trigger Interrupt Status bit(1)
1 = Trigger interrupt is pending
0 = Trigger interrupt is not pending
PWMLIF: PWML Interrupt Status bit(1)
1 = PWM Timer equal to 0x4 interrupt has occurred
0 = PWM Interrupt has not occurred
PWMHIF: PWMH Interrupt Status bit
1 = PWM period match interrupt has occurred
0 = PWM period match interrupt has not occurred
Unimplemented: Read as ‘0’
FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled. If FLTIF = 1, an interrupt event will be generated.
0 = Fault interrupt is disabled
CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt is enabled. If CLIF = 1, an interrupt event will be generated.
0 = Current-limit interrupt is disabled
If PWM interrupts are enabled, software must clear the PWMCONx interrupt flags here first, followed
second by the corresponding IFSx bit in the Interrupt controller. The corresponding PWM IFSx interrupt
flag cannot be cleared if any of these local PWMCON interrupt bits are not cleared first. Failure to do so
will result in an infinite interrupt loop.
This bit should not be changed after the PWM is enabled (PTEN bit (PTCON) = 1).
To operate in External Period Reset mode, the ITB bit must be set to ‘1’ and the CLMOD bit in the IOCONx
register must be set to ‘0’.
For Dead Time Compensation (DTCP) to be effective, DTC must be set to ‘11’; otherwise, DTCP is
ignored.
Negative dead time is only implemented for Edge-Aligned mode.
XPRES mode should only be used in Edge-Aligned mode with or without complimentary outputs. It does
not support dead time compensation (i.e., duty cycle adjustment), which is selected when DTC = 11.
The clock source is one of the master time bases even if ITB = 1 is selected.
2019-2020 Microchip Technology Inc.
DS60001570C-page 519
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-11: PWMCONx: PWM CONTROL REGISTER ‘x’ (‘x’ = 1 THROUGH 12) (CONTINUED)
bit 21
bit 20
bit 19
bit 18-16
bit 15
bit 14
bit 13-12
bit 11-10
bit 9
bit 8
bit 7-6
bit 5
TRIGIEN: Primary Trigger Interrupt Enable bit
1 = A primary trigger event generates an interrupt request
0 = A primary trigger event interrupts request is disabled
PWMLIEN: PWM Low Phase Interrupt Enable bit
1 = When the PWM Timer is equal to 0x4, the PWMLIF flag = 1 and generates an interrupt request
0 = PWM Period event interrupt request is disabled
PWMHIEN: PWM High Phase Interrupt Enable bit
1 = When the PWM Period matches the value in the PWM timer, an interrupt request is generated
0 = PWM Period event interrupt request is disabled, and the PWMHIF bit is cleared
Unimplemented: Read as ‘0’
FLTSTAT: Fault Interrupt Status bit(1)
1 = Fault interrupt is pending
0 = No fault interrupt is pending
This bit is cleared by setting FLTIEN = 0.
CLTSTAT: Current-Limit Interrupt Status bit(1)
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending
This bit is cleared by setting CLIEN = 0.
Unimplemented: Read as ‘0’
ECAM: Edge/Center-Aligned Mode Enable bits(1)
11 = Asymmetric Center-Aligned mode with simultaneous update (PWM(min) Duty Cycle Resolution = (1/
FSYSCLK))
10 = Asymmetric Center-Aligned mode double update (PWM(min) Duty Cycle Resolution = (1/FSYSCLK))
01 = Symmetric Center-Aligned mode (PWM(min) Duty Cycle Resolution = (2/FSYSCLK))
00 = Edge-Aligned mode (PWM(min) Duty Cycle Resolution = (1/FSYSCLK))
ITB: Independent Time Base Mode bit(2)
1 = PHASEx registers provide time base period for this PWM generator
0 = PTPER/STPER register provides timing for this PWM generator based on the MTBS bit
Unimplemented: Read as ‘0’
DTC: Dead Time Control bits
11 = Dead Time Compensation mode enabled
10 = Dead time function is disabled
01 = Negative dead time actively applied for Complementary Output mode(5)
00 = Positive dead time actively applied for all output modes
DTCP: Dead Time Compensation Polarity bit(5)
1 = If the DTCMPx pin = 0, PWMxL is shortened, and PWMxH is lengthened
If the DTCMPx pin = 1, PWMxH is shortened, and PWMxL is lengthened
0 = If the DTCMPx pin = 0, PWMxH is shortened, and PWMxL is lengthened
If the DTCMPx pin = 1, PWMxL is shortened, and PWMxH is lengthened
Note 1:
2:
3:
4:
5:
6:
7:
If PWM interrupts are enabled, software must clear the PWMCONx interrupt flags here first, followed
second by the corresponding IFSx bit in the Interrupt controller. The corresponding PWM IFSx interrupt
flag cannot be cleared if any of these local PWMCON interrupt bits are not cleared first. Failure to do so
will result in an infinite interrupt loop.
This bit should not be changed after the PWM is enabled (PTEN bit (PTCON) = 1).
To operate in External Period Reset mode, the ITB bit must be set to ‘1’ and the CLMOD bit in the IOCONx
register must be set to ‘0’.
For Dead Time Compensation (DTCP) to be effective, DTC must be set to ‘11’; otherwise, DTCP is
ignored.
Negative dead time is only implemented for Edge-Aligned mode.
XPRES mode should only be used in Edge-Aligned mode with or without complimentary outputs. It does
not support dead time compensation (i.e., duty cycle adjustment), which is selected when DTC = 11.
The clock source is one of the master time bases even if ITB = 1 is selected.
DS60001570C-page 520
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-11: PWMCONx: PWM CONTROL REGISTER ‘x’ (‘x’ = 1 THROUGH 12) (CONTINUED)
PTDIR: PWM Timer Direction bit(6)
1 = PWM timer is decrementing
0 = PWM timer is incrementing
MTBS: Master Time Base Select bit(7)
1 = Secondary master time base is the clock source for the MCPWM module
0 = Primary master time base is the clock source for the MCPWM module
Unimplemented: Read as ‘0’
XPRES: External PWM Reset Control bit(3)
1 = Current-limit source resets primary local time base for this PWM generator if it is in Independent Time
Base mode and the PWM module enters the deassertion portion of the duty cycle
0 = External pins do not affect PWM time base
bit 4
bit 3
bit 2
bit 1
Note:
If the Current-Limit Reset signal is asserted during the active assertion time of the duty cycle,
the time base will not Reset until two PWM clock cycles after the duty cycle transition from
assertion to deassertion phase of the duty cycle.
Unimplemented: Read as ‘0’
bit 0
Note 1:
2:
3:
4:
5:
6:
7:
If PWM interrupts are enabled, software must clear the PWMCONx interrupt flags here first, followed
second by the corresponding IFSx bit in the Interrupt controller. The corresponding PWM IFSx interrupt
flag cannot be cleared if any of these local PWMCON interrupt bits are not cleared first. Failure to do so
will result in an infinite interrupt loop.
This bit should not be changed after the PWM is enabled (PTEN bit (PTCON) = 1).
To operate in External Period Reset mode, the ITB bit must be set to ‘1’ and the CLMOD bit in the IOCONx
register must be set to ‘0’.
For Dead Time Compensation (DTCP) to be effective, DTC must be set to ‘11’; otherwise, DTCP is
ignored.
Negative dead time is only implemented for Edge-Aligned mode.
XPRES mode should only be used in Edge-Aligned mode with or without complimentary outputs. It does
not support dead time compensation (i.e., duty cycle adjustment), which is selected when DTC = 11.
The clock source is one of the master time bases even if ITB = 1 is selected.
2019-2020 Microchip Technology Inc.
DS60001570C-page 521
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-12: IOCONx: PWMX I/O CONTROL REGISTER ‘x’ (‘x’ = 1 THROUGH 9)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
U-0
R/W-1
—
Note 1:
2:
3:
4:
Note:
R/W-1
R/W-1
FLTSRC
R/W-0
R/W-0
R/W-0
R/W-0
PENL(1)
POLH(2)
POLL(2)
R/W-0
R/W-0
R/W-0
R/W-0
OVRDAT(3)
R/W-1
(2,4)
PENH(1)
Legend:
R = Readable bit
-n = Value at POR
bit 31-30
CLSRC(2,4)
FLTDAT(2,3)
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
R/W-0
R/W-0
FLTPOL
R/W-0
PMOD(2)
R/W-0
Bit
24/16/8/0
CLPOL(2,4) CLMOD(2,4)
(2)
R/W-0
Bit
25/17/9/1
R/W-0
CLDAT
R/W-0
FLTMOD(4)
R/W-0
R/W-0
OVRENH
OVRENL
R/W-0
R/W-0
SWAP
OSYNC
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
During PWM initialization, if the PWMLOCK fuse bit is ‘enabled’ (logic ‘0’), the control on the state of the
PWMxL/PWMxH output pins rests solely with the PENH and PENL bits. However, these bits are at ‘0’,
which leaves the pin control with the I/O module. Care must be taken to not inadvertently set the TRIS bits
to output, which could impose an incorrect output on the PWMxH/PWMxL pins even if there are external
pull-up and pull-down resistors. The data direction for the pins must be set to input if tri-state behavior is
desired or be driven to the appropriate logic states. The PENH and PENL bits must always be initialized
prior to enabling the MCPWM module (PTEN bit = 1).
These bits must not be changed after the MCPWM module is enabled (PTEN bit = 1).
State represents Active/Inactive state of the PWM, depending on the POLH and POLL bits. For example,
if FLTDAT is set to ‘1’ and POLH is set to ‘1’, the PWMxH pin will be at logic level 0 (active level) when
a Fault occurs.
If (PWMLOCK = 0), these bits are writable only after the proper sequence is written to the PWMKEY register. If (PWMLOCK = 1), these bits are writable at all times. The user application must write two consecutive values of (0xABCD and 0x4321) to the PWMKEY register to perform the unlock operation for the
IOCONx register if PWMLOCK = 1. Write access to a IOCONx register must be the next SFR access following the unlock process. There can be no other SFR accesses during the unlock process and subsequent write access. This is not an atomic operation, and therefore, any CPU interrupts that occur during or
immediately after an unlock sequence may cause the IOCONx SFR write access to fail.
Dead Time Compensation, Current-Limit, and Faults share common inputs on the FLTx inputs (‘x’ = 1-8,
and 15). Therefore, it is not recommended that a user application assign these multiple functions on the
same Fault FLTx pin. In addition, DTCMP functions are fixed to specific FLTx inputs, where Current-Limit,
(CLSRC bits) and Faults (FLTSRC bits) can be assigned to any one of 15 unique and separate
inputs. For example, if a user application was required to assign multiple simultaneous Fault, Current-Limit,
DTCMP to a single PWM1. Refer to the following examples for both desirable and undesirable practices.
Desirable Example PWM1: (DTCMP1 = FLT3 pin, Current Limit = FLT7 pin, Fault = FLT8 pin)
PWMCON1bits.DTC = 0b11;
IOCON1bits.CLMOD = 1;
IOCON1bits.CLSRC = 0b0110;
IOCON1bits.FLTMOD = 1;
IOCON1bits.FLTSRC = 0b0111;
//Enable
//Enable
//Enable
//Enable
//Enable
DTCMP1 input on FLT3 function pin
PWM1 Current-Limit mode
current limit for PWM1 on FLT7 pin
PWM1 Fault mode
Fault for PWM1 on FLT8 pin
Undesirable Example: PWM1: (DTCMP1 = Current Limit = Fault = FLT3 pin)
PWMCON1bits.DTC = 0b11;
IOCON1bits.CLMOD = 1;
IOCON1bits.CLSRC = 0b0010;
IOCON1bits.FLTMOD = 1;
IOCON1bits.FLTSRC = 0b0010;
DS60001570C-page 522
//Enable
//Enable
//Enable
//Enable
//Enable
DTCMP1 input on FLT3 function pin
PWM1 Current-Limit mode
current limit for PWM1 on FLT3 pin
PWM1 Fault mode
Fault for PWM1 on FLT3 pin
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-12: IOCONx: PWMX I/O CONTROL REGISTER ‘x’ (‘x’ = 1 THROUGH 9) (CONTINUED)
bit 29-26
bit 25
Note 1:
2:
3:
4:
Note:
CLSRC: Current-Limit Control Signal Source select bit for PWM Generator ‘x’(2,4)
These bits specify the current-limit control signal source.
1111 = FLT15
1110 = Reserved
1101 = Reserved
1100 = Comparator 5
1011 = Comparator 4
1010 = Comparator 3
1001 = Comparator 2
1000 = Comparator 1
0111 = FLT8
0110 = FLT7
0101 = FLT6
0100 = FLT5
0011 = FLT4
0010 = FLT3
0001 = FLT2
0000 = FLT1
CLPOL: Current-Limit Polarity bits for PWM Generator ‘x’(2,4)
1 = The selected current-limit source is active-low
0 = The selected current-limit source is active-high
During PWM initialization, if the PWMLOCK fuse bit is ‘enabled’ (logic ‘0’), the control on the state of the
PWMxL/PWMxH output pins rests solely with the PENH and PENL bits. However, these bits are at ‘0’,
which leaves the pin control with the I/O module. Care must be taken to not inadvertently set the TRIS bits
to output, which could impose an incorrect output on the PWMxH/PWMxL pins even if there are external
pull-up and pull-down resistors. The data direction for the pins must be set to input if tri-state behavior is
desired or be driven to the appropriate logic states. The PENH and PENL bits must always be initialized
prior to enabling the MCPWM module (PTEN bit = 1).
These bits must not be changed after the MCPWM module is enabled (PTEN bit = 1).
State represents Active/Inactive state of the PWM, depending on the POLH and POLL bits. For example,
if FLTDAT is set to ‘1’ and POLH is set to ‘1’, the PWMxH pin will be at logic level 0 (active level) when
a Fault occurs.
If (PWMLOCK = 0), these bits are writable only after the proper sequence is written to the PWMKEY register. If (PWMLOCK = 1), these bits are writable at all times. The user application must write two consecutive values of (0xABCD and 0x4321) to the PWMKEY register to perform the unlock operation for the
IOCONx register if PWMLOCK = 1. Write access to a IOCONx register must be the next SFR access following the unlock process. There can be no other SFR accesses during the unlock process and subsequent write access. This is not an atomic operation, and therefore, any CPU interrupts that occur during or
immediately after an unlock sequence may cause the IOCONx SFR write access to fail.
Dead Time Compensation, Current-Limit, and Faults share common inputs on the FLTx inputs (‘x’ = 1-8,
and 15). Therefore, it is not recommended that a user application assign these multiple functions on the
same Fault FLTx pin. In addition, DTCMP functions are fixed to specific FLTx inputs, where Current-Limit,
(CLSRC bits) and Faults (FLTSRC bits) can be assigned to any one of 15 unique and separate
inputs. For example, if a user application was required to assign multiple simultaneous Fault, Current-Limit,
DTCMP to a single PWM1. Refer to the following examples for both desirable and undesirable practices.
Desirable Example PWM1: (DTCMP1 = FLT3 pin, Current Limit = FLT7 pin, Fault = FLT8 pin)
PWMCON1bits.DTC = 0b11;
IOCON1bits.CLMOD = 1;
IOCON1bits.CLSRC = 0b0110;
IOCON1bits.FLTMOD = 1;
IOCON1bits.FLTSRC = 0b0111;
//Enable
//Enable
//Enable
//Enable
//Enable
DTCMP1 input on FLT3 function pin
PWM1 Current-Limit mode
current limit for PWM1 on FLT7 pin
PWM1 Fault mode
Fault for PWM1 on FLT8 pin
Undesirable Example: PWM1: (DTCMP1 = Current Limit = Fault = FLT3 pin)
PWMCON1bits.DTC = 0b11;
IOCON1bits.CLMOD = 1;
IOCON1bits.CLSRC = 0b0010;
IOCON1bits.FLTMOD = 1;
IOCON1bits.FLTSRC = 0b0010;
2019-2020 Microchip Technology Inc.
//Enable
//Enable
//Enable
//Enable
//Enable
DTCMP1 input on FLT3 function pin
PWM1 Current-Limit mode
current limit for PWM1 on FLT3 pin
PWM1 Fault mode
Fault for PWM1 on FLT3 pin
DS60001570C-page 523
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-12: IOCONx: PWMX I/O CONTROL REGISTER ‘x’ (‘x’ = 1 THROUGH 9) (CONTINUED)
CLMOD: Current-Limit Mode Enable bit for PWM Generator ‘x’(2,4)
1 = Current-limit function is enabled
0 = Current-limit function is disabled, current-limit overrides disabled (current-limit interrupts can still be
generated). If Faults are enabled, FLTMOD will override the CLMOD bit.
Changes take effect on the next PWM cycle boundary following PWM being enabled, and subsequently
on each PWM cycle boundary. When updating CLMOD from ‘1’ to ‘0’, if the current-limit input is still active,
the current-limit override condition will not be removed.
Unimplemented: Read as ‘0’
bit 24
bit 23
Note 1:
2:
3:
4:
Note:
During PWM initialization, if the PWMLOCK fuse bit is ‘enabled’ (logic ‘0’), the control on the state of the
PWMxL/PWMxH output pins rests solely with the PENH and PENL bits. However, these bits are at ‘0’,
which leaves the pin control with the I/O module. Care must be taken to not inadvertently set the TRIS bits
to output, which could impose an incorrect output on the PWMxH/PWMxL pins even if there are external
pull-up and pull-down resistors. The data direction for the pins must be set to input if tri-state behavior is
desired or be driven to the appropriate logic states. The PENH and PENL bits must always be initialized
prior to enabling the MCPWM module (PTEN bit = 1).
These bits must not be changed after the MCPWM module is enabled (PTEN bit = 1).
State represents Active/Inactive state of the PWM, depending on the POLH and POLL bits. For example,
if FLTDAT is set to ‘1’ and POLH is set to ‘1’, the PWMxH pin will be at logic level 0 (active level) when
a Fault occurs.
If (PWMLOCK = 0), these bits are writable only after the proper sequence is written to the PWMKEY register. If (PWMLOCK = 1), these bits are writable at all times. The user application must write two consecutive values of (0xABCD and 0x4321) to the PWMKEY register to perform the unlock operation for the
IOCONx register if PWMLOCK = 1. Write access to a IOCONx register must be the next SFR access following the unlock process. There can be no other SFR accesses during the unlock process and subsequent write access. This is not an atomic operation, and therefore, any CPU interrupts that occur during or
immediately after an unlock sequence may cause the IOCONx SFR write access to fail.
Dead Time Compensation, Current-Limit, and Faults share common inputs on the FLTx inputs (‘x’ = 1-8,
and 15). Therefore, it is not recommended that a user application assign these multiple functions on the
same Fault FLTx pin. In addition, DTCMP functions are fixed to specific FLTx inputs, where Current-Limit,
(CLSRC bits) and Faults (FLTSRC bits) can be assigned to any one of 15 unique and separate
inputs. For example, if a user application was required to assign multiple simultaneous Fault, Current-Limit,
DTCMP to a single PWM1. Refer to the following examples for both desirable and undesirable practices.
Desirable Example PWM1: (DTCMP1 = FLT3 pin, Current Limit = FLT7 pin, Fault = FLT8 pin)
PWMCON1bits.DTC = 0b11;
IOCON1bits.CLMOD = 1;
IOCON1bits.CLSRC = 0b0110;
IOCON1bits.FLTMOD = 1;
IOCON1bits.FLTSRC = 0b0111;
//Enable
//Enable
//Enable
//Enable
//Enable
DTCMP1 input on FLT3 function pin
PWM1 Current-Limit mode
current limit for PWM1 on FLT7 pin
PWM1 Fault mode
Fault for PWM1 on FLT8 pin
Undesirable Example: PWM1: (DTCMP1 = Current Limit = Fault = FLT3 pin)
PWMCON1bits.DTC = 0b11;
IOCON1bits.CLMOD = 1;
IOCON1bits.CLSRC = 0b0010;
IOCON1bits.FLTMOD = 1;
IOCON1bits.FLTSRC = 0b0010;
DS60001570C-page 524
//Enable
//Enable
//Enable
//Enable
//Enable
DTCMP1 input on FLT3 function pin
PWM1 Current-Limit mode
current limit for PWM1 on FLT3 pin
PWM1 Fault mode
Fault for PWM1 on FLT3 pin
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-12: IOCONx: PWMX I/O CONTROL REGISTER ‘x’ (‘x’ = 1 THROUGH 9) (CONTINUED)
bit 22-19
bit 18
Note 1:
2:
3:
4:
Note:
FLTSRC: Fault Control Signal Source Select bits for PWM Generator ‘x’(2,4)
These bits specify the Fault control source.
1111 = FLT15
1110 = Reserved
1101 = Reserved
1100 = Comparator 5
1011 = Comparator 4
1010 = Comparator 3
1001 = Comparator 2
1000 = Comparator 1
0111 = FLT8
0110 = FLT7
0101 = FLT6
0100 = FLT5
0011 = FLT4
0010 = FLT3
0001 = FLT2
0000 = FLT1
FLTPOL: Fault Polarity bits for PWM Generator ‘x’(2)
1 = The selected fault source is active-low
0 = The selected fault source is active-high
During PWM initialization, if the PWMLOCK fuse bit is ‘enabled’ (logic ‘0’), the control on the state of the
PWMxL/PWMxH output pins rests solely with the PENH and PENL bits. However, these bits are at ‘0’,
which leaves the pin control with the I/O module. Care must be taken to not inadvertently set the TRIS bits
to output, which could impose an incorrect output on the PWMxH/PWMxL pins even if there are external
pull-up and pull-down resistors. The data direction for the pins must be set to input if tri-state behavior is
desired or be driven to the appropriate logic states. The PENH and PENL bits must always be initialized
prior to enabling the MCPWM module (PTEN bit = 1).
These bits must not be changed after the MCPWM module is enabled (PTEN bit = 1).
State represents Active/Inactive state of the PWM, depending on the POLH and POLL bits. For example,
if FLTDAT is set to ‘1’ and POLH is set to ‘1’, the PWMxH pin will be at logic level 0 (active level) when
a Fault occurs.
If (PWMLOCK = 0), these bits are writable only after the proper sequence is written to the PWMKEY register. If (PWMLOCK = 1), these bits are writable at all times. The user application must write two consecutive values of (0xABCD and 0x4321) to the PWMKEY register to perform the unlock operation for the
IOCONx register if PWMLOCK = 1. Write access to a IOCONx register must be the next SFR access following the unlock process. There can be no other SFR accesses during the unlock process and subsequent write access. This is not an atomic operation, and therefore, any CPU interrupts that occur during or
immediately after an unlock sequence may cause the IOCONx SFR write access to fail.
Dead Time Compensation, Current-Limit, and Faults share common inputs on the FLTx inputs (‘x’ = 1-8,
and 15). Therefore, it is not recommended that a user application assign these multiple functions on the
same Fault FLTx pin. In addition, DTCMP functions are fixed to specific FLTx inputs, where Current-Limit,
(CLSRC bits) and Faults (FLTSRC bits) can be assigned to any one of 15 unique and separate
inputs. For example, if a user application was required to assign multiple simultaneous Fault, Current-Limit,
DTCMP to a single PWM1. Refer to the following examples for both desirable and undesirable practices.
Desirable Example PWM1: (DTCMP1 = FLT3 pin, Current Limit = FLT7 pin, Fault = FLT8 pin)
PWMCON1bits.DTC = 0b11;
IOCON1bits.CLMOD = 1;
IOCON1bits.CLSRC = 0b0110;
IOCON1bits.FLTMOD = 1;
IOCON1bits.FLTSRC = 0b0111;
//Enable
//Enable
//Enable
//Enable
//Enable
DTCMP1 input on FLT3 function pin
PWM1 Current-Limit mode
current limit for PWM1 on FLT7 pin
PWM1 Fault mode
Fault for PWM1 on FLT8 pin
Undesirable Example: PWM1: (DTCMP1 = Current Limit = Fault = FLT3 pin)
PWMCON1bits.DTC = 0b11;
IOCON1bits.CLMOD = 1;
IOCON1bits.CLSRC = 0b0010;
IOCON1bits.FLTMOD = 1;
IOCON1bits.FLTSRC = 0b0010;
2019-2020 Microchip Technology Inc.
//Enable
//Enable
//Enable
//Enable
//Enable
DTCMP1 input on FLT3 function pin
PWM1 Current-Limit mode
current limit for PWM1 on FLT3 pin
PWM1 Fault mode
Fault for PWM1 on FLT3 pin
DS60001570C-page 525
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-12: IOCONx: PWMX I/O CONTROL REGISTER ‘x’ (‘x’ = 1 THROUGH 9) (CONTINUED)
bit 17-16
bit 15
bit 14
bit 13
Note 1:
2:
3:
4:
Note:
FLTMOD: Fault Mode bits for PWM Generator ‘x’(4)
11 = Fault input is disabled, no fault overrides possible. (fault interrupts can still be generated)
10 = Reserved
01 = Selected fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle by cycle)
00 = Selected fault source forces PWMxH, PWMxL pins to FLTDAT values (Latched condition)
Changes take effect on the next PWM cycle boundary following PWM being enabled, and subsequently
on each PWM cycle boundary. When updating FLTMOD from ‘00’ or ‘01’ to ‘11’ (disabled), if the
fault input is still active the fault override condition will not be removed. If enabled, Faults will override the
CLMOD bit setting.
PENH: PWMxH Output Pin Ownership bit(1)
1 = PWM module controls PWMxH pin
0 = GPIO module controls PWMxH pin
PENL: PWMxL Output Pin Ownership bit(1)
1 = PWM module controls PWMxL pin
0 = GPIO module controls PWMxL pin
POLH: PWMxH Output Pin Polarity bit(2)
1 = PWMxH pin is active-low
0 = PWMxH pin is active-high
During PWM initialization, if the PWMLOCK fuse bit is ‘enabled’ (logic ‘0’), the control on the state of the
PWMxL/PWMxH output pins rests solely with the PENH and PENL bits. However, these bits are at ‘0’,
which leaves the pin control with the I/O module. Care must be taken to not inadvertently set the TRIS bits
to output, which could impose an incorrect output on the PWMxH/PWMxL pins even if there are external
pull-up and pull-down resistors. The data direction for the pins must be set to input if tri-state behavior is
desired or be driven to the appropriate logic states. The PENH and PENL bits must always be initialized
prior to enabling the MCPWM module (PTEN bit = 1).
These bits must not be changed after the MCPWM module is enabled (PTEN bit = 1).
State represents Active/Inactive state of the PWM, depending on the POLH and POLL bits. For example,
if FLTDAT is set to ‘1’ and POLH is set to ‘1’, the PWMxH pin will be at logic level 0 (active level) when
a Fault occurs.
If (PWMLOCK = 0), these bits are writable only after the proper sequence is written to the PWMKEY register. If (PWMLOCK = 1), these bits are writable at all times. The user application must write two consecutive values of (0xABCD and 0x4321) to the PWMKEY register to perform the unlock operation for the
IOCONx register if PWMLOCK = 1. Write access to a IOCONx register must be the next SFR access following the unlock process. There can be no other SFR accesses during the unlock process and subsequent write access. This is not an atomic operation, and therefore, any CPU interrupts that occur during or
immediately after an unlock sequence may cause the IOCONx SFR write access to fail.
Dead Time Compensation, Current-Limit, and Faults share common inputs on the FLTx inputs (‘x’ = 1-8,
and 15). Therefore, it is not recommended that a user application assign these multiple functions on the
same Fault FLTx pin. In addition, DTCMP functions are fixed to specific FLTx inputs, where Current-Limit,
(CLSRC bits) and Faults (FLTSRC bits) can be assigned to any one of 15 unique and separate
inputs. For example, if a user application was required to assign multiple simultaneous Fault, Current-Limit,
DTCMP to a single PWM1. Refer to the following examples for both desirable and undesirable practices.
Desirable Example PWM1: (DTCMP1 = FLT3 pin, Current Limit = FLT7 pin, Fault = FLT8 pin)
PWMCON1bits.DTC = 0b11;
IOCON1bits.CLMOD = 1;
IOCON1bits.CLSRC = 0b0110;
IOCON1bits.FLTMOD = 1;
IOCON1bits.FLTSRC = 0b0111;
//Enable
//Enable
//Enable
//Enable
//Enable
DTCMP1 input on FLT3 function pin
PWM1 Current-Limit mode
current limit for PWM1 on FLT7 pin
PWM1 Fault mode
Fault for PWM1 on FLT8 pin
Undesirable Example: PWM1: (DTCMP1 = Current Limit = Fault = FLT3 pin)
PWMCON1bits.DTC = 0b11;
IOCON1bits.CLMOD = 1;
IOCON1bits.CLSRC = 0b0010;
IOCON1bits.FLTMOD = 1;
IOCON1bits.FLTSRC = 0b0010;
DS60001570C-page 526
//Enable
//Enable
//Enable
//Enable
//Enable
DTCMP1 input on FLT3 function pin
PWM1 Current-Limit mode
current limit for PWM1 on FLT3 pin
PWM1 Fault mode
Fault for PWM1 on FLT3 pin
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-12: IOCONx: PWMX I/O CONTROL REGISTER ‘x’ (‘x’ = 1 THROUGH 9) (CONTINUED)
bit 12
bit 11-10
bit 9
bit 8
bit 7-6
Note 1:
2:
3:
4:
Note:
POLL: PWMxL Output Pin Polarity bit(2)
1 = PWMxL pin is active-low
0 = PWMxL pin is active-high
PMOD: PWM ‘x’ I/O Pin Mode bits(2)
11 = PWMxL output is held at logic ‘0’ (adjusted by the POLL bit)
10 = PWM I/O pin pair is in Push-Pull Output mode
01 = PWM I/O pin pair is in Redundant Output mode
00 = PWM I/O pin pair is in Complementary Output mode
OVRENH: Override Enable for PWMxH Pin bit
1 = OVRDAT provides data for output on PWMxH pin
0 = PWM generator provides data for PWMxH pin
OVRENL: Override Enable for PWMxL Pin bit
1 = OVRDAT provides data for output on PWMxL pin
0 = PWM generator provides data for PWMxL pin
OVRDAT: State(3) for PWMxH, PWMxL Pins if Override is Enabled bits
If OVRENH = 1, OVRDAT provides data for PWMxH
If OVRENL = 1, OVRDAT provides data for PWMxL
During PWM initialization, if the PWMLOCK fuse bit is ‘enabled’ (logic ‘0’), the control on the state of the
PWMxL/PWMxH output pins rests solely with the PENH and PENL bits. However, these bits are at ‘0’,
which leaves the pin control with the I/O module. Care must be taken to not inadvertently set the TRIS bits
to output, which could impose an incorrect output on the PWMxH/PWMxL pins even if there are external
pull-up and pull-down resistors. The data direction for the pins must be set to input if tri-state behavior is
desired or be driven to the appropriate logic states. The PENH and PENL bits must always be initialized
prior to enabling the MCPWM module (PTEN bit = 1).
These bits must not be changed after the MCPWM module is enabled (PTEN bit = 1).
State represents Active/Inactive state of the PWM, depending on the POLH and POLL bits. For example,
if FLTDAT is set to ‘1’ and POLH is set to ‘1’, the PWMxH pin will be at logic level 0 (active level) when
a Fault occurs.
If (PWMLOCK = 0), these bits are writable only after the proper sequence is written to the PWMKEY register. If (PWMLOCK = 1), these bits are writable at all times. The user application must write two consecutive values of (0xABCD and 0x4321) to the PWMKEY register to perform the unlock operation for the
IOCONx register if PWMLOCK = 1. Write access to a IOCONx register must be the next SFR access following the unlock process. There can be no other SFR accesses during the unlock process and subsequent write access. This is not an atomic operation, and therefore, any CPU interrupts that occur during or
immediately after an unlock sequence may cause the IOCONx SFR write access to fail.
Dead Time Compensation, Current-Limit, and Faults share common inputs on the FLTx inputs (‘x’ = 1-8,
and 15). Therefore, it is not recommended that a user application assign these multiple functions on the
same Fault FLTx pin. In addition, DTCMP functions are fixed to specific FLTx inputs, where Current-Limit,
(CLSRC bits) and Faults (FLTSRC bits) can be assigned to any one of 15 unique and separate
inputs. For example, if a user application was required to assign multiple simultaneous Fault, Current-Limit,
DTCMP to a single PWM1. Refer to the following examples for both desirable and undesirable practices.
Desirable Example PWM1: (DTCMP1 = FLT3 pin, Current Limit = FLT7 pin, Fault = FLT8 pin)
PWMCON1bits.DTC = 0b11;
IOCON1bits.CLMOD = 1;
IOCON1bits.CLSRC = 0b0110;
IOCON1bits.FLTMOD = 1;
IOCON1bits.FLTSRC = 0b0111;
//Enable
//Enable
//Enable
//Enable
//Enable
DTCMP1 input on FLT3 function pin
PWM1 Current-Limit mode
current limit for PWM1 on FLT7 pin
PWM1 Fault mode
Fault for PWM1 on FLT8 pin
Undesirable Example: PWM1: (DTCMP1 = Current Limit = Fault = FLT3 pin)
PWMCON1bits.DTC = 0b11;
IOCON1bits.CLMOD = 1;
IOCON1bits.CLSRC = 0b0010;
IOCON1bits.FLTMOD = 1;
IOCON1bits.FLTSRC = 0b0010;
2019-2020 Microchip Technology Inc.
//Enable
//Enable
//Enable
//Enable
//Enable
DTCMP1 input on FLT3 function pin
PWM1 Current-Limit mode
current limit for PWM1 on FLT3 pin
PWM1 Fault mode
Fault for PWM1 on FLT3 pin
DS60001570C-page 527
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-12: IOCONx: PWMX I/O CONTROL REGISTER ‘x’ (‘x’ = 1 THROUGH 9) (CONTINUED)
FLTDAT: State(3) for PWMxH and PWMxL Pins if FLTMOD is Enabled bits(2)
If FLTMOD (IOCONx) = 00 or 01, one of the following Fault modes is enabled:
If fault is active, FLTDAT provides the state for PWMxH
If fault is active, FLTDAT provides the state for PWMxL
If fault is inactive, FLTDAT bits are ignored
CLDAT: State for PWMxH and PWMxL Pins if CLMOD is Enabled bits(3)
If CLMOD (IOCONx) = 1, Current-Limit mode is enabled, as follows:
If current limit is active, CLTDAT provides the state for PWMxH
If current limit is active, CLTDAT provides the state for PWMxL
If current limit is inactive, CLTDAT bits are ignored
SWAP: SWAP PWMxH and PWMxL Pins bit
1 = PWMxH output signal is connected to PWMxL pin; PWMxL output signal is connected to PWMxH pin
0 = PWMxH and PWMxL output signals pins are mapped to their respective pins
OSYNC: Output Override Synchronization bit
1 = Output overrides through the OVRDAT bits are synchronized to the PWM time base
0 = Output overrides through the OVRDAT bits occur on next CPU clock boundary
bit 5-4
bit 3-2
bit 1
bit 0
Note 1:
2:
3:
4:
Note:
During PWM initialization, if the PWMLOCK fuse bit is ‘enabled’ (logic ‘0’), the control on the state of the
PWMxL/PWMxH output pins rests solely with the PENH and PENL bits. However, these bits are at ‘0’,
which leaves the pin control with the I/O module. Care must be taken to not inadvertently set the TRIS bits
to output, which could impose an incorrect output on the PWMxH/PWMxL pins even if there are external
pull-up and pull-down resistors. The data direction for the pins must be set to input if tri-state behavior is
desired or be driven to the appropriate logic states. The PENH and PENL bits must always be initialized
prior to enabling the MCPWM module (PTEN bit = 1).
These bits must not be changed after the MCPWM module is enabled (PTEN bit = 1).
State represents Active/Inactive state of the PWM, depending on the POLH and POLL bits. For example,
if FLTDAT is set to ‘1’ and POLH is set to ‘1’, the PWMxH pin will be at logic level 0 (active level) when
a Fault occurs.
If (PWMLOCK = 0), these bits are writable only after the proper sequence is written to the PWMKEY register. If (PWMLOCK = 1), these bits are writable at all times. The user application must write two consecutive values of (0xABCD and 0x4321) to the PWMKEY register to perform the unlock operation for the
IOCONx register if PWMLOCK = 1. Write access to a IOCONx register must be the next SFR access following the unlock process. There can be no other SFR accesses during the unlock process and subsequent write access. This is not an atomic operation, and therefore, any CPU interrupts that occur during or
immediately after an unlock sequence may cause the IOCONx SFR write access to fail.
Dead Time Compensation, Current-Limit, and Faults share common inputs on the FLTx inputs (‘x’ = 1-8,
and 15). Therefore, it is not recommended that a user application assign these multiple functions on the
same Fault FLTx pin. In addition, DTCMP functions are fixed to specific FLTx inputs, where Current-Limit,
(CLSRC bits) and Faults (FLTSRC bits) can be assigned to any one of 15 unique and separate
inputs. For example, if a user application was required to assign multiple simultaneous Fault, Current-Limit,
DTCMP to a single PWM1. Refer to the following examples for both desirable and undesirable practices.
Desirable Example PWM1: (DTCMP1 = FLT3 pin, Current Limit = FLT7 pin, Fault = FLT8 pin)
PWMCON1bits.DTC = 0b11;
IOCON1bits.CLMOD = 1;
IOCON1bits.CLSRC = 0b0110;
IOCON1bits.FLTMOD = 1;
IOCON1bits.FLTSRC = 0b0111;
//Enable
//Enable
//Enable
//Enable
//Enable
DTCMP1 input on FLT3 function pin
PWM1 Current-Limit mode
current limit for PWM1 on FLT7 pin
PWM1 Fault mode
Fault for PWM1 on FLT8 pin
Undesirable Example: PWM1: (DTCMP1 = Current Limit = Fault = FLT3 pin)
PWMCON1bits.DTC = 0b11;
IOCON1bits.CLMOD = 1;
IOCON1bits.CLSRC = 0b0010;
IOCON1bits.FLTMOD = 1;
IOCON1bits.FLTSRC = 0b0010;
DS60001570C-page 528
//Enable
//Enable
//Enable
//Enable
//Enable
DTCMP1 input on FLT3 function pin
PWM1 Current-Limit mode
current limit for PWM1 on FLT3 pin
PWM1 Fault mode
Fault for PWM1 on FLT3 pin
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-13: PDCx: PWM GENERATOR DUTY CYCLE REGISTER ‘x’ (‘x’ = 1 THROUGH 12)
Bit Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PDC
R/W-0
7:0
R/W-0
R/W-0
R/W-0
R/W-0
PDC
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
PDC: Primary PWM Generator ‘x’ Duty Cycle Value bits(2)
If Edge-Aligned mode is enabled (ECAM bits (PWMCONx) = 00), these bits specify the
trailing edge instance of the ON time and controls the duty cycle directly (PWM Resolution = (1/FSYCLK)).
If one of the Center-Aligned mode is enabled (ECAM (PWMCONx) = 01, 10, or 11), these
bits specify the compare instance for ‘leading edge’ level transition (PWM Resolution = (2/FSYCLK)).
Note 1: In Independent PWM mode, PMOD (IOCONx) = 11, the PDCx register controls the PWMxH
duty cycle only. In Complementary, Redundant and Push-Pull PWM modes (PMOD = 00, 01, or 10),
the PDCx register controls the duty cycle of both the PWMxH and PWMxL.
2: PDCx = ((FSYSCLK / (FPWM * PTCON)) * Desired Duty Cycle)
FPWM = User Desired PWM Frequency
2019-2020 Microchip Technology Inc.
DS60001570C-page 529
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-14: SDCx: PWM SECONDARY DUTY CYCLE REGISTER ‘x’ (‘x’ = 1 THROUGH 12)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDC
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
R/W-0
SDC
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
SDC: Secondary Duty Cycle bits for PWMx output pin
If Edge-Aligned mode is enabled (ECAM (PWMCONx) = 00) these bits are unused.
If Symmetric Center-Aligned mode is enabled (ECAM (PWMCONx) = 01), these bits are
updated transparently to the user. Loads to the PDCx register automatically copy over to the SDCx
register.
If Asymmetric Center-Aligned mode is enabled (ECAM (PWMCONx) = 10 or 11), these
bits specify the compare instance for ‘trailing edge’ level transition (PWM Resolution = (2/FSYCLK)).
DS60001570C-page 530
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-15: PHASEx: PWM PRIMARY PHASE SHIFT REGISTER ‘x’ (‘x’ = 1 THROUGH 12)
Bit Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PHASE
R/W-0
7:0
R/W-0
R/W-0
R/W-0
R/W-0
PHASE
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
PHASE: PWM Phase Shift Value or Independent Time Base Period bits for the PWM Generator bits(6)
Phase shifting is used to offset the start of a PWM Generator’s time base period, relative to a master time
base, as well as the generated duty cycle. Also, the effects on the operation of the PWM signals through
any external control signals, such as current-limit, Fault, and dead time compensation, are also shifted in
time.
Note 1: If the ITB bit (PWMCONx) = 0, the following applies based on the mode of operation:
Complementary, Redundant and Push-Pull Output modes (PMOD (IOCONx) = 00, 01, or
10) PHASE = Phase shift value for PWMxH and PWMxL outputs
2: If the ITB bit = 1, the following applies based on the mode of operation:
Complementary, Redundant, and Push-Pull Output modes (PMOD = 00, 01, or 10)
PHASE = local time base period value for TMRx
3: A Phase offset that exceeds the PWM period will lead to unpredictable results.
4: The minimum period value is 0x0008.
5: The SDCx register is used in Independent PWM mode only (PMOD = 11). When used in Independent PWM mode, the SDCx register controls the PWMxL duty cycle.
6: PHASEx = (FSYSCLK / (FPWM * PTCON))
FPWM = User Desired PWM Frequency
2019-2020 Microchip Technology Inc.
DS60001570C-page 531
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-16: DTRx: PWM DEAD TIME REGISTER ‘x’ (‘x’ = 1 THROUGH 12)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
R/W-0
R/W-0
Note:
R/W-0
DTR
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
DTR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
DTR: Unsigned 14-bit Dead Time Value for PWMxH Dead Time Unit bits
These bits specify the leading edge dead time count between the PWMxH and PWMxL. The time base
for the count is the same as for the PWM generator.
The dead time period is typically set equal to the switching times of the power transistors in the application
circuits. It is specifically intended for use in Complementary Output mode. The use of dead time in any
other mode may generate unexpected or unpredictable results. If the duty cycle value in the DC register
equals ‘0’, or is greater than or equal to the Period, dead time compensation is ignored. The values for
Duty Cycle + Dead Time + Dead Time Compensation must not exceed the value for the Period register
minus 1. If the sum exceeds the Period Register minus 1, unexpected results may occur. The values for
Duty Cycle + Dead Time - Dead Time Compensation must be greater than ‘0’, or unexpected results may
occur.
DTR and ALTDTR must be ≥ 6 while using Leading Edge Blanking.
DS60001570C-page 532
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-17: ALTDTRx: PWM ALTERNATE DEAD TIME REGISTER ‘x’ (‘x’ = 1 THROUGH 12)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
Note:
R/W-0
R/W-0
R/W-0
R/W-0
ALTDTR
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
ALTDTR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
ALTDTR: Unsigned 14-bit Dead Time Value for PWMxL Dead Time Unit bits
These bits specify the trailing edge dead time count between the PWMxH and PWMxL. The time base
for the count is the same as for the PWM generator.
The alternate dead time period is typically set equal to the switching times of the power transistors in the
application circuits. It is specifically intended for use in Complementary Output mode. The use of dead
time in any other mode may generate unexpected or unpredictable results. If the duty cycle value in the
DC register equals ‘0’, or is greater than or equal to the Period, alternate dead time compensation is
ignored. The values for Duty Cycle + Dead Time + ALT Dead Time Compensation must not exceed the
value for the Period Register minus 1. If the sum exceeds the Period Register -minus1, unexpected
results may occur. The values for Duty Cycle + Dead Time minus Alternate Dead Time Compensation
must be greater than ‘0’, or unexpected results may occur.
DTR and ALTDTR must be ≥ 6 while using Leading Edge Blanking.
2019-2020 Microchip Technology Inc.
DS60001570C-page 533
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-18: DTCOMPx: DEAD TIME COMPENSATION REGISTER ‘x’ (‘x’ = 1 THROUGH 12)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
R-0
R-0
R-0
R-0
Note 1:
2:
R-0
R-0
R-0
R-0
COMP(1,2)
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
COMP(1,2)
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
COMP: Dead Time Compensation Value bits(1,2)
Dead time compensation value if Dead Time compensation mode is enabled.
COMP Min LSb = 1 / FSYSCLK for ECAM bits (PWMCONx) = ‘0b00 Edge-Aligned
mode; COMP Min LSb = 2 / FSYSCLK for ECAM bits (PWMCONx)> ‘0b00 CenterAligned mode.
When Dead Time compensation mode is selected through the DTC bits in the PWMCONx register,
an external pin, CMPx (i.e., FLTx) connected to the Dead Time Compensation module input signals,
cause the value in the COMPx register to be added to or subtracted from the PWMx duty cycle. The dead
time compensation input signals are sampled at the end of a PWM cycle for use in the next PWM cycle.
The modification of the duty cycle duration through the CMPx registers occurs during the end (trailing
edge) of the duty cycle. Dead time compensation is available only for Positive Dead Time mode. The
CMPx value must be less than one-half the value of the duty cycle register, PDCx; otherwise, unpredictable behavior will result. Dead time compensation will not apply for a duty cycle of zero. In this case, the
PWM output will remain zero regardless of the state of the CMPx input pin.
DS60001570C-page 534
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-19: TRIGx: PWM PRIMARY TRIGGER COMPARE VALUE REGISTER ‘x’ (‘x’ = 1
THROUGH 12)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGCMP
R/W-0
R/W-0
Note:
R/W-0
R/W-0
TRGCMP
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
R/W-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
TRGCMP: Trigger Compare Value bits
These bits specify the value to match against the local time base register PTMR to generate a trigger to
the ADC module and an interrupt if the TRGIEN bit (PWMCONx) is set.
To trigger at the period boundary, set TRIGx to 0x0 and not the PTPER period value.
2019-2020 Microchip Technology Inc.
DS60001570C-page 535
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-20: TRGCONx: PWM TRIGGER CONTROL REGISTER ‘x’ (‘x’ = 1 THROUGH 12)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 11-10
Note 1:
2:
STRGSEL(1)
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
DTM(1,2)
STRGIS(1)
—
—
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-12
TRGSEL(1)
TRGDIV
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
TRGDIV: Trigger ‘x’ Output Divider bits
1111 = Trigger output for every sixteenth trigger event
•
•
•
0010 = Trigger output for every third trigger event
0001 = Trigger output for every second trigger event
0000 = Trigger output for every trigger event
TRGSEL: Trigger Cycle Selection for Dual Cycle PWM Cycles (Center-Aligned and Push-Pull)(1)
This bit field has no effect on the raw trigger generation for single cycle PWM modes such as edgealigned PWM. Each time a raw comparison event occurs, the raw event is processed by the trigger
divider.
11 = Reserved, default to same behavior as TRGSEL = 00.
10 = When a trigger comparison match event occurs in the incrementing phase in the dual cycle PWM
mode (PTDIR = 0), a trigger event output is generated if the trigger divider has counted the
appropriate number of trigger events.
01 = When a trigger comparison match event occurs in the decrementing phase in the dual cycle PWM
mode (PTDIR = 1), a trigger event output is generated if the trigger divider has counted the
appropriate number of trigger events.
00 = When a trigger comparison match event occurs, generate a trigger event output if the trigger divider
has counted the appropriate number of raw trigger events. For dual cycle PWM modes such as
Center-Aligned mode and Push-Pull mode, the raw trigger event is generated twice every cycle.
However, TRIGx/STRIGx compare values of ‘0’ or equal to the PERIOD match register will only
generate one interrupt even in the dual cycle modes.
These bits must not be changed after the MCPWM module is enabled (PTEN bit (PTCON) = 1).
The secondary trigger event is generated regardless of the setting of the DTM bit.
DS60001570C-page 536
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-20: TRGCONx: PWM TRIGGER CONTROL REGISTER ‘x’ (‘x’ = 1 THROUGH 12)
(CONTINUED)
bit 9-8
bit 7
bit 6
bit 5-0
Note 1:
2:
STRGSEL: Secondary Trigger Cycle Selection bits for Dual Cycle PWM Cycles
(Center-Aligned and Push-Pull)(1)
These bits have no effect on the raw secondary PWM trigger generation for single cycle PWM modes
such as edge aligned PWM. Each time a raw comparison event occurs, the raw event is processed by
the secondary PWM trigger divider.
11 = Reserved, default to same behavior as STRGSEL = 00
10 = When a secondary PWM trigger comparison match event occurs in the second half of a dual cycle
PWM mode (PTDIR = 0), generate a secondary PWM trigger event output if the secondary PWM
trigger divider has counted the appropriate number of secondary PWM trigger events.
01 = When a secondary PWM trigger comparison match event occurs in the first half of a dual cycle PWM
mode (PTDIR = 1), generate a trigger event output if the secondary PWM trigger divider has
counted the appropriate number of secondary PWM trigger events.
00 = When a secondary PWM trigger comparison match event occurs, generate a secondary PWM
trigger event output if the trigger divider has counted the appropriate number of raw secondary PWM
trigger events. For two cycle PWM modes such as Center-Aligned mode and Push-Pull mode, the
raw secondary PWM trigger event is generated twice.
DTM: Dual ADC Trigger Mode(1, 2)
1 = Secondary trigger event is combined with the primary trigger event for purposes of creating a
combined ADC trigger
0 = Secondary trigger event is not combined with the primary trigger event for purposes of creating a
combined ADC trigger
STRGIS: Secondary Trigger Interrupt Select(1)
This bit should be changed by the user only when PTEN = 0.
1 = Selects the Secondary Trigger Register (STRIGx) based events for interrupts
0 = When the DTM bit (TRGCONx) is clear (= 0), TRIGx-based events for interrupts are selected.
When the DTM bit is set (= 1), the logical OR of both STRIGx and TRIGx based triggers for interrupts
are selected.
Unimplemented: Read as ‘0’
These bits must not be changed after the MCPWM module is enabled (PTEN bit (PTCON) = 1).
The secondary trigger event is generated regardless of the setting of the DTM bit.
2019-2020 Microchip Technology Inc.
DS60001570C-page 537
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-21: STRIGx: SECONDARY PWM TRIGGER COMPARE REGISTER ‘x’
(‘x’ = 1 THROUGH 12)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STRGCMP
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
Note 1:
2:
R/W-0
STRGCMP
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
STRGCMP: Secondary Trigger Value Bits
These bits store the 16-bit value to compare against the SMTMR to generate a trigger to the ADC module to initiate conversion, and an interrupt if the TRGIEN bit (PWMCONx) and the DTM bit (TRIGCONx) are enabled.
Min LSb = 1/FSYSCLK.
To trigger at the period boundary, set STRIGx to 0x0 and not the PTPER period value.
REGISTER 29-22: CAPx: PWM TIMER CAPTURE REGISTER ‘x’ (‘x’ = 1 THROUGH 12)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
CAP(1)
R/W-0
Note 1:
R/W-0
R/W-0
R/W-0
CAP(1)
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
R/W-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
CAP: Captured Local PWM Timer Value bits(1)
The value in this register represents the captured local PWM timer (PTMRx) value when a leading edge
is detected on the current-limit input.
The feature is only active after LEB processing on the current-limit input signals complete.
DS60001570C-page 538
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-23: LEBCONx: LEADING-EDGE BLANKING CONTROL REGISTER ‘x’
(‘x’ = 1 THROUGH 12)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
PHR
PHF
PLR
PLF
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
FLTLEBEN CLLEBEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15
PHR: PWMxH Rising Edge Trigger Enable bit
1 = Rising edge of PWMxH will trigger/retrigger the Leading-Edge Blanking counter
0 = Rising edge of PWMxH will not trigger/retrigger the Leading-Edge Blanking counter
bit 14
PHF: PWMxH Falling Edge Trigger Enable bit
1 = Falling edge of PWMxH will trigger/retrigger the Leading-Edge Blanking counter
0 = Falling edge of PWMxH will not trigger/retrigger the Leading-Edge Blanking counter
bit 13
PLR: PWMxL Rising Edge Trigger Enable bit
1 = Rising edge of PWMxL will trigger/retrigger the Leading-Edge Blanking counter
0 = Rising edge of PWMxL will not trigger/retrigger the Leading-Edge Blanking counter
bit 12
PLF: PWMxL Falling Edge Trigger Enable bit
1 = Falling edge of PWMxL will trigger/retrigger the Leading-Edge Blanking counter
0 = Falling edge of PWMxL will not trigger/retrigger the Leading-Edge Blanking counter
bit 11
FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to selected fault input
0 = Leading-Edge Blanking is not applied to selected fault input
bit 10
CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to selected current-limit input
0 = Leading-Edge Blanking is not applied to selected current-limit input
bit 9-0
Note:
Unimplemented: Read as ‘0’
DTR and ALTDTR must be ≥ 6 while using Leading Edge Blanking.
2019-2020 Microchip Technology Inc.
DS60001570C-page 539
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-24: LEBDLYx: LEADING-EDGE BLANKING DELAY REGISTER ‘x’
(‘x’ = 1 THROUGH 12)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEB
Legend:
R = Readable bit
-n = Value at POR
bit 31-12
bit 11-0
LEB
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
LEB: Leading-Edge Blanking Delay bits for Current-Limit and Fault Inputs bits
These bits specify the time period for which the selected current limit and fault signals are blanked or
delayed following the selected edge transition of the PWM signals. This retriggerable counter has the
PWM module clock source (SYSCLK) as the time base.
DS60001570C-page 540
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-25: AUXCONx: PWM AUXILIARY CONTROL REGISTER ‘x’ (‘x’ = 1 THROUGH 9)
Bit Range
Bit
Bit
31/23/15/7 30/22/14/6
31:24
23:16
15:8
7:0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CHOPHEN
CHOPLEN
Legend:
R = Readable bit
-n = Value at POR
bit 31-6
bit 5-2
Bit
29/21/13/5
CHOPSEL(1)
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
CHOPSEL: PWM Chop Clock Source Select bits(1)
The selected signal will enable and disable (CHOP) the selected PWM outputs.
1111 = Reserved.
•
•
1010 = Reserved.
1001 = PWM9H selected as CHOP clock source (68-pin variant only)
1000 = PWM8H selected as CHOP clock source (68-pin variant only)
0111 = PWM7H selected as CHOP clock source (68-pin variant only)
0110 = PWM6H selected as CHOP clock source
•
•
bit 1
bit 0
Note 1:
0001 = PWM1H selected as CHOP clock source
0000 = Chop clock generator selected as CHOP clock source
CHOPHEN: PWMxH Output Chopping Enable bit
1 = PWMxH chopping function is enabled
0 = PWMxH chopping function is disabled
CHOPLEN: PWMxL Output Chopping Enable bit
1 = PWMxL chopping function is enabled
0 = PWMxL chopping function is disabled
This bit should be changed only when the PTEN bit (PTCON) = 0.
2019-2020 Microchip Technology Inc.
DS60001570C-page 541
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 29-26: PTMRx: PWM TIMER REGISTER ‘x’ (‘x’ = 1 THROUGH 12)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
TMR
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
R/W-0
TMR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
TMR: PWM Timer bits
When the ECAM bits (PWMCONx) = 00, the counter counts upwards until a period match
forces rollover.
When the ECAM bits (PWMCONx) 00, the counter counts downwards starting with a
master time base synchronization signal to 0 and then counts upwards until the next synchronization.
DS60001570C-page 542
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
NOTES:
2019-2020 Microchip Technology Inc.
DS60001570C-page 543
PIC32MK GPG/MCJ with CAN FD Family
30.0
HIGH/LOW-VOLTAGE DETECT
(HLVD)
Note:
This data sheet summarizes the
features of the PIC32MK GPG/MCJ with
CAN FD Family of devices. It is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 38. “High/Low-Voltage Detect
(DS60001408), which is
(HLVD)”
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
FIGURE 30-1:
VDD
The High/Low-Voltage Detect (HLVD) module is a
programmable circuit that can be used to specify both
the device voltage trip point and the direction of
change. When enabled, a HLVD event will act to disable the Flash controller from executing a programming
sequence. This module is used to ensure the supply
voltage is sufficient for programming.
The HLVD module is an interrupt-driven supply-level
detection. The voltage detection monitors the internal
power supply.
The HLVD module provides the following key features:
• Detection hysteresis
• Detection of low-to-high or high-to-low voltage
changes
• Generation of Non-Maskable Interrupts (NMI)
• LVDIN pin to provide external voltage trip point
PROGRAMMABLE HLVD MODULE BLOCK DIAGRAM
Externally Generated
Trip Point
VDD
LVDIN
HLVDL
16-to-1 MUX
ON
VDIR
HLVD
Event
Band Gap
Reference
ON
DS60001570C-page 544
2019-2020 Microchip Technology Inc.
Control Registers
HLVD REGISTER MAP
1800 HLVDCON
Legend:
Note 1:
31:16
15:0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
—
ON
—
—
—
—
—
—
—
VDIR
—
BGVST
—
—
—
HLVDET
—
DISOUT
—
—
—
—
—
—
—
18/2
17/1
—
—
HLVDL
16/0
—
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF80_#)
TABLE 30-1:
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The register in this table has corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more
information.
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 545
30.1
PIC32MK GPG/MCJ with CAN FD Family
H
REGISTER 30-1:
Bit
Range
31:24
23:16
15:8
7:0
HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
U-1
HS/HC, R/W-0
ON
—
—
—
VDIR(1)
BGVST
—
HLVDET
R/S-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
DISOUT
—
—
—
R/W-0
(1)
HLVDL
Legend:
HS = Hardware Set
HC = Hardware Clear
S = Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: HLVD Module Enable bit
1 = HLVD module is enabled
0 = HLVD module is disabled
bit 14-12 Unimplemented: Read as ‘0’
bit 11
VDIR: Voltage Change Direction Select bit(1)
1 = Event occurs when voltage equals or exceeds trip point (HLVDL)
0 = Event occurs when voltage equals or falls below trip point (HLVDL)
bit 10
BGVST: Band Gap Reference Voltages Stable Status bit
1 = Indicates internal band gap voltage references is stable
0 = Indicates internal band gap voltage reference is not stable
bit 9
Unimplemented: Read as ‘1’
bit 8
HLVDET: High/Low-Voltage Detection Event Status bit
1 = Indicates HLVD Event interrupt is active
0 = Indicates HLVD Event interrupt is not active
bit 7
DISOUT: Disable HLVD Output bit
1 = Enable output of HLVD Comparator. Once set, can only be cleared by setting the ON bit to ‘0’.
0 = Disable output of HLVD Comparator (default Reset value). Will be forced to ‘0’ whenever the ON bit is
equal to ‘0’.
bit 6-4
Unimplemented: Read as ‘0’
Note:
Note 1:
This bit is readable when the HLVD module is disabled (ON bit is equal to ‘0’).
To avoid false HLVD events, all HLVD module setting changes should occur only when the module is
disabled (ON bit is equal to ‘0’).
DS60001570C-page 546
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 30-1:
bit 3-0
Note 1:
HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
HLVDL: High/Low-Voltage Detection Limit Select bits(1)
1111 = 1.2V (Selects external LVDIN pin)
1110 = Reserved, Do not use
1101 = Reserved, Do not use
1100 = Reserved, Do not use
1011 = Reserved, Do not use
1010 = 2.4V
1001 = 2.5V
1000 = 2.697V
0111 = 2.791V
0110 = 3.0V
0101 = 3.288V
0100 = 3.529V
0011 = Reserved; do not use
0010 = Reserved; do not use
0001 = Reserved; do not use
0000 = Reserved; do not use
To avoid false HLVD events, all HLVD module setting changes should occur only when the module is
disabled (ON bit is equal to ‘0’).
2019-2020 Microchip Technology Inc.
DS60001570C-page 547
PIC32MK GPG/MCJ with CAN FD Family
31.0
Note:
POWER-SAVING FEATURES
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 10. “PowerSaving Features” (DS60001130), which
is available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
This section describes the power-saving features on
the PIC32MK GPG/MCJ CAN FD family of devices.
These devices have multiple power domains and offer
various methods and modes that allow the user to balance the power consumption with device performance.
31.1
Power Saving with CPU Running
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency or
selecting a lower power clock source (i.e., LPRC or
SOSC).
In addition, the Peripheral Bus Scaling mode is available
for each peripheral bus where peripherals are clocked at
reduced speed by selecting a higher divider for the
associated PBCLKx, or by disabling the clock
completely.
31.2
Power-Saving with CPU Halted
Peripherals and the CPU can be Halted or disabled to
further reduce power consumption.
31.2.1
SLEEP MODE
Sleep mode has the lowest power consumption of the
device power-saving operating modes. The CPU and
most peripherals are Halted and the associated clocks
are disabled. Select peripherals can continue to
operate in Sleep mode and can be used to wake the
device from Sleep. See the individual peripheral
module sections for descriptions of behavior in Sleep
mode.
Sleep mode includes the following characteristics:
• There can be a wake-up delay based on the
oscillator selection
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode
• The BOR circuit remains operative during Sleep
mode
• The WDT, if enabled, is not automatically cleared
prior to entering Sleep mode
DS60001570C-page 548
• Some peripherals can continue to operate at limited
functionality in Sleep mode. These peripherals
include I/O pins that detect a change in the input
signal, WDT, ADC, UART and peripherals that use
an external clock input or the internal LPRC
oscillator (e.g., RTCC, Timer1 and Input Capture).
• I/O pins continue to sink or source current in the
same manner as they do when the device is not in
Sleep
The processor will exit, or ‘wake-up’, from Sleep on one
of the following events:
• On any interrupt from an enabled source that is
operating in Sleep. The interrupt priority must be
greater than the current CPU priority.
• On any form of device Reset
• On a WDT time-out
If the interrupt priority is lower than or equal to the
current priority, the CPU will remain Halted, but the
peripheral bus clocks will start running and the device
will enter into Idle mode.
31.2.2
IDLE MODE
In Idle mode, the CPU is Halted; however, all clocks are
still enabled. This allows peripherals to continue to
operate. Peripherals can be individually configured to
Halt when entering Idle by setting their respective SIDL
bit. Latency, when exiting Idle mode, is very low due to
the CPU oscillator source remaining active.
The device enters Idle mode when the SLPEN bit
(OSCCON) is clear and a WAIT instruction is
executed.
The processor will wake or exit from Idle mode on the
following events:
• On any interrupt event for which the interrupt source
is enabled. The priority of the interrupt event must
be greater than the current priority of the CPU. If the
priority of the interrupt event is lower than or equal
to current priority of the CPU, the CPU will remain
Halted and the device will remain in Idle mode.
• On any form of device Reset
• On a WDT time-out interrupt
31.2.3
POWER-SAVING MODES
Figure 31-1 shows a block diagram and the related
power-saving features. The various blocks are
controlled by the following Configuration bit settings
and SFRs:
• RTCCLKSEL (RTCCON )
• SLPEN (OSCCON)
• VREGS (PWRCON)
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 31-1:
LOW-POWER DEVICE BLOCK DIAGRAM
RTCDIS
Low-Power
VREG
RTCCLKSEL
Timers
LPRC
SOSCI
RTCC
SOSC
VDD
SOSCO
VBPOR
POR
BOR
MCLR
MCLR
Monitors
Regulators
Main VREG
CPU
SRAM
Peripherals
Flash VREG
Idle/Sleep (SLPEN)
VREGS
Program Flash
Memory
RELEASE
I/O Lock Logic
Peripheral I/O
2019-2020 Microchip Technology Inc.
DS60001570C-page 549
PIC32MK GPG/MCJ with CAN FD Family
31.3
Peripheral Module Disable
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum
power consumption state. The control and status
registers associated with the peripheral are also
disabled, so writes to those registers do not have
effect and read values are invalid. If the associated
peripheral PMD bit was previously = 1, subsequently
clearing the bit will require the user to reinitialize the
peripheral.The only exception to this is the DMA
module.
To disable a peripheral, the associated PMDx bit must
be set to ‘1’. To enable a peripheral, the associated
PMDx bit must be cleared (default). See Table 31-1 for
more information.
Note:
Disabling a peripheral module while it's
ON bit is set, may result in undefined
behavior. The ON bit for the associated
peripheral module must be cleared prior to
disable a module via the PMDx bits.
DS60001570C-page 550
2019-2020 Microchip Technology Inc.
Register
Name
0040
PMD1(2)
0050
(2)
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
(2)
31:16
—
—
—
—
—
—
—
OC9MD
OC8MD
OC7MD
OC6MD
OC5MD
OC4MD
OC3MD
OC2MD
OC1MD
0000
15:0
—
—
—
—
—
—
—
IC9MD
IC8MD
IC7MD
IC6MD
IC5MD
IC4MD
IC3MD
IC2MD
IC1MD
0000
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
CAN1MD(3)
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
0060
0070
0080
PMD2
PMD3
PMD4(2)
(1,2)
PMD5
0090
PMD6(2)
00A0
(2)
PMD7
Legend:
Note 1:
2:
3:
4:
Bit Range
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
31:16
—
—
—
—
CLC4MD
CLC3MD
15:0
—
—
—
—
—
—
31:16
24/8
23/7
22/6
CLC2MD
CLC1MD
—
—
CTMUMD
—
—
—
—
16/0
All Resets(1)
Virtual Address
(BF80_#)
PERIPHERAL MODULE DISABLE REGISTER SUMMARY
21/5
20/4
19/3
18/2
17/1
—
—
HLVDMD
—
—
—
—
0000
DAC2MD
DAC1MD
—
—
—
—
ADCMD
0000
—
OPA5MD
—
OPA3MD
OPA2MD
CMP5MD C4MPMD C3MPMD CMP2MD CMP1MD 0000
OPA1MD 0000
PWM9MD( PWM8MD( PWM7MD( PWM6MD( PWM5MD( PWM4MD( PWM3MD( PWM2MD( PWM1MD(
4)
4)
4)
4)
4)
4)
4)
4)
4)
0000
T9MD
T8MD
T7MD
T6MD
T5MD
T4MD
T3MD
T2MD
T1MD
0000
—
—
—
—
—
—
—
—
I2C2MD
I2C1MD
0000
SPI2MD
SPI1MD
—
—
—
—
—
—
U2MD
U1MD
0000
QEI3MD(4) QEI2MD(4) QEI1MD(4)
—
—
—
—
—
—
—
—
0000
REFO4MD REFO3MD REFO2MD REFO1MD
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
DMAMD
—
—
—
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset values are dependent on the device variant.
For any associated PMDx bit, ‘0’ = clocks enabled to the peripheral; ‘1’ = For associated peripheral, clocks are disabled, SFRs are reset, and CPU read/write is invalid.
Not available in “GPG” variants.
Only available in “MC” variants.
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 551
TABLE 31-1:
PIC32MK GPG/MCJ with CAN FD Family
TABLE 31-2:
PERIPHERAL MODULE DISABLE BITS AND LOCATIONS
PMDx Bit Name(1)
Register Name and Bit Location
ADC1-ADC7
ADC1MD
PMD1
CDAC1
DAC1MD
PMD1
CDAC2
DAC2MD
PMD1
CTMU
CTMU1MD
PMD1
HLVD
HLVDMD
PMD1
CLC1
CLC1MD
PMD1
CLC2
CLC2MD
PMD1
CLC3
CLC3MD
PMD1
CLC4
CLC4MD
PMD1
Comparator 1
C1MD
PMD2
Comparator 2
C2MD
PMD2
Comparator 3
C3MD
PMD2
Comparator 4
C4MD
PMD2
Peripheral
Comparator 5
C5MD
PMD2
Op amp 1
OPA1MD
PMD2
Op amp 2
OPA2MD
PMD2
Op amp 3
OPA3MD
PMD2
Op amp 5
OPA5MD
PMD2
Input Capture 1
IC1MD
PMD3
Input Capture 2
IC2MD
PMD3
Input Capture 3
IC3MD
PMD3
Input Capture 4
IC4MD
PMD3
Input Capture 5
IC5MD
PMD3
Input Capture 6
IC6MD
PMD3
Input Capture 7
IC7MD
PMD3
Input Capture 8
IC8MD
PMD3
Input Capture 9
IC9MD
PMD3
Output Compare 1
OC1MD
PMD3
Output Compare 2
OC2MD
PMD3
Output Compare 3
OC3MD
PMD3
Output Compare 4
OC4MD
PMD3
Output Compare 5
OC5MD
PMD3
Output Compare 6
OC6MD
PMD3
Output Compare 7
OC7MD
PMD3
Output Compare 8
OC8MD
PMD3
Output Compare 9
OC9MD
PMD3
Timer1
T1MD
PMD4
Timer2
T2MD
PMD4
Timer3
T3MD
PMD4
Note 1:
2:
3:
For any associated PMDx bit, 0 = clocks enabled to the peripheral; 1 = For associated peripheral, clocks
are disabled, SFRs are reset, and CPU read/write is invalid. If the associated peripheral PMD bit was previously = 1, subsequently clearing the bit will require the user to reinitialize the peripheral. The only exception to this is the DMA module.
Not available in “GPG” variants.
Only available in “MC” variants.
DS60001570C-page 552
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 31-2:
PERIPHERAL MODULE DISABLE BITS AND LOCATIONS (CONTINUED)
PMDx Bit Name(1)
Register Name and Bit Location
Timer4
T4MD
PMD4
Timer5
T5MD
PMD4
Timer6
T6MD
PMD4
Timer7
T7MD
PMD4
Timer8
T8MD
PMD4
Timer9
T9MD
PMD4
(3)
PWM1MD
PMD4
PWM2(3)
PWM2MD
PMD4
PWM3(3)
PWM3MD
PMD4
PWM4(3)
PWM4MD
PMD4
PWM5(3)
PWM5MD
PMD4
PWM6(3)
PWM6MD
PMD4
(3)
PWM7MD
PMD4
PWM8(3)
PWM8MD
PMD4
PWM9(3)
PWM9MD
PMD4
U1MD
PMD5
Uart2
U2MD
PMD5
SPI1
SPI1MD
PMD5
SPI2
SPI2MD
PMD5
I2C1
I2C1MD
PMD
Peripheral
PWM1
PWM7
Uart1
I2C2
I2C2MD
PMD
CAN1(2)
CAN1MD
PMD5
Reference Clock 1
REFO1MD
PMD6
Reference Clock 2
REFO2MD
PMD6
Reference Clock 3
REFO3MD
PMD6
Reference Clock 4
REFO4MD
PMD6
(3)
QEI1MD
PMD6
QEI2(3)
QEI2MD
PMD6
(3)
QEI3MD
PMD6
DMAMD
PMD7
QEI1
QEI3
DMA
Note 1:
2:
3:
For any associated PMDx bit, 0 = clocks enabled to the peripheral; 1 = For associated peripheral, clocks
are disabled, SFRs are reset, and CPU read/write is invalid. If the associated peripheral PMD bit was previously = 1, subsequently clearing the bit will require the user to reinitialize the peripheral. The only exception to this is the DMA module.
Not available in “GPG” variants.
Only available in “MC” variants.
2019-2020 Microchip Technology Inc.
DS60001570C-page 553
PIC32MK GPG/MCJ with CAN FD Family
31.3.1
CONTROLLING CONFIGURATION
CHANGES
Because peripherals can be disabled during run time,
some restrictions on disabling peripherals are needed
to prevent accidental configuration changes. PIC32MK
GPG/MCJ with CAN FD Family of devices include two
features to prevent alterations to enabled or disabled
peripherals:
• Control Register Lock Sequence
• Configuration Bit Select Lock
31.3.1.1
Control Register Lock
Under normal operation, writes to the PMDx registers
are not allowed. Attempted writes appear to execute
normally, but the contents of the registers remain
unchanged. To change these registers, they must be
unlocked in hardware. The register lock is controlled by
the PMDLOCK Configuration bit (CFGCON).
Setting the PMDLOCK bit prevents writes to the control
registers and clearing the PMDLOCK bit allows writes.
To set or clear the PMDLOCK bit, an unlock sequence
must be executed. Refer to Section 42. “Oscillators
with Enhanced PLL” (DS60001250) in the “PIC32
Family Reference Manual” for details.
31.3.1.2
Configuration Bit Select Lock
As an additional level of safety, the device can be configured to prevent more than one write session to the
PMDx registers. The PMDL1WAY Configuration bit
(DEVCFG3) blocks the PMDLOCK bit from being
cleared after it has been set once. If the PMDLOCK bit
remains set, the register unlock procedure does not
execute, and the PPS control registers cannot be written to. The only way to clear the bit and re-enable PMD
functionality is to perform a device Reset.
DS60001570C-page 554
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
32.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features
of the PIC32MK GPG/MCJ with CAN FD
Family of devices. However, it is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section
32.
“Configuration”
(DS60001124)
and
Section
33.
“Programming
and
Diagnostics”
(DS60001129), which are available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
PIC32MK GPG/MCJ with CAN FD Family of devices
include several features intended to maximize application flexibility and reliability and minimize cost through
elimination of external components. These are:
•
•
•
•
The following run-time programmable Configuration
registers provide additional configuration control:
• CFGCON: Configuration Control Register
• CFGPG: Permission Group Configuration
Register
In addition, the DEVID register (Register 32-9)
provides device and revision information, the
DEVADC1 through DEVADC5 registers (Register 3210) provide ADC module calibration data, and the
DEVSN0 and DEVSN3 registers contain a unique
serial number of the device (Register 32-11).
Note:
Do not use Word program operation
(NVMOP = 0001) when programming the device Words that are described
in this section.
Flexible device configuration
Joint Test Action Group (JTAG) interface
In-Circuit Serial Programming™ (ICSP™)
Internal temperature sensor
32.1
Configuration Bits
PIC32MK GPG/MCJ with CAN FD Family of devices
contain two Boot Flash memories (Boot Flash 1 and
Boot Flash 2), each with an associated configuration
space. These configuration spaces can be programmed to contain various device configurations.
Configuration space that is aliased by the Lower Boot
Alias memory region is used to provide values for Configuration registers listed below. See 3.1.1 “Boot
Flash Sequence and Configuration Spaces” for
more information.
• DEVSIGN0: Device Signature Word 0 Register
• DEVCP0: Device Code-Protect 0 Register
• DEVCFG0/ADEVCFG0: Device/Alternate Device
Configuration Word 0
• DEVCFG1/ADEVCFG1: Device/Alternate Device
Configuration Word 1
• DEVCFG2/ADEVCFG2: Device/Alternate Device
Configuration Word 2
• DEVCFG3/ADEVCFG3: Device/Alternate Device
Configuration Word 3
2019-2020 Microchip Technology Inc.
DS60001570C-page 555
Registers
TABLE 32-1:
DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
3FC0 DEVCFG3 31:16
31/15
30/14
29/13
—
—
IOL1WAY
28/12
27/11
PMDL1WAY PGL1WAY
26/10
25/9
—
—
15:0
—
15:0
—
3FC8 DEVCFG1 31:16
15:0
3FCC DEVCFG0 31:16
3FD0
3FD4
3FD8
3FDC
DEVCP3
DEVCP2
DEVCP1
DEVCP0
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
PWMLOCK
—
—
—
—
—
—
—
—
FPLLODIV
xxxx
—
FPLLIDIV
xxxx
USERID
3FC4 DEVCFG2 31:16
—
BORSEL
—
—
—
—
FPLLMULT
FDMTEN
EJTAGBEN
—
FWDTEN
WINDIS
IES0
LPOSCEN
—
—
OSCIOFNC
POSCMOD
—
—
POSCAGC
---
POSCAGCDLY
—
FSLEEP
FECCCON
—
DBGPER
FPLLRNG
FWDTWINSZ
—
xxxx
xxxx
FPLLICLK
DMTCNT
FCKSM
—
FDSEN
All Resets
Bit Range
Register
Name
Virtual Address
(BFC0_#)
Bits
POSCFGAIN
WDTSPGM
WDTPSR
DMTINTV
POSCBOOST
POSCGAIN
BOOTISA
TRCEN
ICESEL
15:0
SMCLR
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
CP
—
—
—
15:0
—
—
—
—
—
—
—
xxxx
FNOSC
xxxx
SOSCGAIN
xxxx
DEBUG
xxxx
—
—
—
xxxx
—
—
—
—
xxxx
—
—
—
—
—
xxxx
—
—
—
—
—
—
xxxx
—
—
—
—
—
—
—
xxxx
—
—
—
—
—
—
—
—
xxxx
—
—
—
—
—
—
—
—
—
xxxx
—
—
—
—
—
—
—
—
—
xxxx
3FF0 DEVSEQ 3 31:16
CSEQ
15:0
TSEQ
JTAGEN
xxxx
xxxx
2019-2020 Microchip Technology Inc.
3FF4 DEVSEQ 2 31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
3FF8 DEVSEQ 1 31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
3FFC DEVSEQ0 31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
Legend:
x = unknown value on Reset; See register description detail for more information. Reset values are shown in hexadecimal.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 556
32.2
3F40 ADEVCFG3 31:16
31/15
30/14
—
—
29/13
28/12
27/11
IOL1WAY PMDL1WAY PGL1WAY
26/10
25/9
—
—
15:0
—
15:0
—
15:0
3F4C ADEVCFG0 31:16
15:0
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
PWMLOCK
—
—
—
—
—
—
—
—
FPLLODIV
—
FPLLIDIV
USERID
3F44 ADEVCFG2 31:16
3F48 ADEVCFG1 31:16
24/8
—
BORSEL
—
—
—
—
FPLLMULT
FDMTEN
EJTAGBEN
SMCLR
FPLLRNG
FWDTEN
WINDIS
IES0
LPOSCEN
—
—
OSCIOFNC
POSCMOD
—
—
POSCAGC
---
POSCAGCDLY
—
FSLEEP
FECCCON
xxxx
xxxx
FWDTWINSZ
—
DBGPER
—
FPLLICLK
DMTCNT
FCKSM
—
FDSEN
All Resets
Bit Range
Bits
Register
Name
Virtual Address
(BFC0_#)
ADEVCFG: ALTERNATE DEVICE CONFIGURATION WORD SUMMARY
POSCFGAIN
WDTSPGM
DMTINTV
ICESEL
TRCEN
xxxx
FNOSC
POSCGAIN
BOOTISA
xxxx
WDTPSR
POSCBOOST
—
xxxx
xxxx
SOSCGAIN
JTAGEN
xxxx
DEBUG
xxxx
3F50 ADEVCP3 31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
3F54 ADEVCP2 31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
3F58 ADEVCP1 31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
3F5C ADEVCP0 31:16
—
—
—
CP
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
3F70 ADEVSEQ 3 31:16
CSEQ
15:0
TSEQ
xxxx
xxxx
3F74 ADEVSEQ 2 31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
3F78 ADEVSEQ 1 31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
3F7C ADEVSEQ0 31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
Legend:
x = unknown value on Reset; See register description detail for more information. Reset values are shown in hexadecimal.
DS60001570C-page 557
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 32-2:
Register
Name
CFGCON
0020
0030
00E0
DEVID
SYSKEY
CFGPG
Legend:
Note
1:
2:
3:
Bit Range
Bits
31/15
30/14
31:16
—
—
15:0
—
—
31:16
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
—
—
—
ADCPRI
—
—
—
—
—
—
—
IOLOCK PMDLOCK PGLOCK
21/5
20/4
—
—
—
—
ECCCON
VER
19/3
18/2
17/1
—
—
ICACLK
JTAGEN
TROEN
—
16/0
OCACLK 0000
TDOEN
DEVID
15:0
xxxx
0000
SYSKEY
15:0
31:16
—
—
JTAGPG
—
—
ADCPG
15:0
—
—
CAN1PG
—
—
—
—
0000
FCPG
—
00xx
xxxx
DEVID
31:16
All Resets(2)
Virtual Address
(BF80_#)
0000
DEVICE ID, REVISION, AND CONFIGURATION SUMMARY
—
—
—
DMAPG
—
—
CPUDSPG
—
—
0000
CPUPG
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 10.2 “CLR, SET, and INV Registers” for more information.
Reset values are dependent on the device variant.
This register is not available on 64-pin devices.
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 558
TABLE 32-3:
DEVADC2(2)
500C DEVADC3(2)
(2)
5010 DEVADC4
5014 DEVADC5(2)
(2)
5018 DEVADC7
Legend:
Note
1:
2:
Virtual Address
(BFC4_#)
Register
Name
5030
DEVEE0
DS60001570C-page 559
5038
503C
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
ADC Calibration Data
xxxx
15:0
ADC Calibration Data
xxxx
31:16
ADC Calibration Data
xxxx
15:0
ADC Calibration Data
xxxx
31:16
ADC Calibration Data
xxxx
15:0
ADC Calibration Data
xxxx
31:16
ADC Calibration Data
xxxx
15:0
ADC Calibration Data
xxxx
31:16
ADC Calibration Data
xxxx
15:0
ADC Calibration Data
xxxx
31:16
ADC Calibration Data
xxxx
15:0
ADC Calibration Data
xxxx
31:16
ADC Calibration Data
xxxx
15:0
ADC Calibration Data
xxxx
x = unknown value on Reset.
Reset values are dependent on the device variant.
Before enabling the ADC, the user application must initialize the ADC calibration codes by copying them from the factory programmed DEVADCx Flash locations into the ADCxCFG special function registers, respectively.
TABLE 32-5:
5034
30/14
DEVICE EE DATA CALIBRATION SUMMARY
DEVEE1
DEVEE2
DEVEE3
Bit Range
Bits
Legend:
Note
1:
All Resets(1)
Bit Range
Register
Name
5004 DEVADC1(2)
31/15
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets(1)
Virtual Address
(BFC4_#)
Bits
5000 DEVADC0(2)
5008
DEVICE ADC CALIBRATION SUMMARY
31:16
EE Data Calibration Data
xxxx
15:0
EE Data Calibration Data
xxxx
31:16
EE Data Calibration Data
xxxx
15:0
EE Data Calibration Data
xxxx
31:16
EE Data Calibration Data
xxxx
15:0
EE Data Calibration Data
xxxx
31:16
EE Data Calibration Data
xxxx
15:0
EE Data Calibration Data
xxxx
x = unknown value on Reset.
Reset values are device dependent. This is a device by device unique permanent number programmed into the device by the factory before shipment.
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 32-4:
Register
Name
DEVSN0
5024
5028
502C
DEVSN1
DEVSN2
DEVSN3
Legend:
Note
1:
Bit Range
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets(1)
Virtual Address
(BFC4_#)
5020
DEVICE SERIAL NUMBER SUMMARY
31:16
Device Serial Number
xxxx
15:0
Device Serial Number
xxxx
31:16
Device Serial Number
xxxx
15:0
Device Serial Number
xxxx
31:16
Device Serial Number
xxxx
15:0
Device Serial Number
xxxx
31:16
Device Serial Number
xxxx
15:0
Device Serial Number
xxxx
x = unknown value on Reset.
Reset values are dependent on the device variant.
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 560
TABLE 32-6:
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 32-1:
Bit
Range
31:24
23:16
15:8
7:0
DEVSIGN0: DEVICE SIGNATURE WORD 0 REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
r-0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
Reserved: Write as ‘0’
bit 30-0
Reserved: Write as ‘1’
REGISTER 32-2:
Bit
Range
31:24
23:16
15:8
7:0
Bit
24/16/8/0
x = Bit is unknown
DEVCP0: DEVICE CODE-PROTECT 0 REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
r-1
r-1
R/P
r-1
r-1
r-1
r-1
—
—
—
CP
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
Legend:
r = Reserved bit
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Reserved: Write as ‘1’
bit 28
CP: Code-Protect bit
Prevents boot and program Flash memory from being read or modified by an external programming device.
1 = Protection is disabled
0 = Protection is enabled
bit 27-0
Reserved: Write as ‘1’
2019-2020 Microchip Technology Inc.
DS60001570C-page 561
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 32-3:
Bit
Range
31:24
23:16
15:8
7:0
DEVCFG0/ADEVCFG0: DEVICE/ALTERNATE DEVICE
CONFIGURATION WORD 0
Bit
Bit
31/23/15/7 30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
r-x
R/P
r-1
r-1
R/P
r
—
EJTAGBEN
—
—
POSCAGC
---
R/P
R/P
R/P
R/P
R/P
POSCFGAIN
R/P
R/P
SMCLR
POSCBOOST
R/P
R/P
DBGPER
r-1
R/P
R/P
—
BOOTISA
TRCEN
Legend:
R = Readable bit
-n = Value at POR
POSCGAIN
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R/P
R/P
SOSCBOOST
r-y
R/P
—
FSLEEP
R/P
ICESEL
R/P
JTAGEN
Bit
Bit
25/17/9/1 24/16/8/0
R/P
R/P
POSCAGCDLY
R/P
R/P
SOSCGAIN
R/P
R/P
FECCCON
R/P
R/P
DEBUG
P = Programmable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Reserved: The reset value of this bit is the same as DEVSIGN0.
EJTAGBEN: EJTAG Boot Enable bit
1 = Normal EJTAG functionality
0 = Reduced EJTAG functionality
bit 29-28 Reserved: Write as ‘1’
bit 27
POSCAGC: Primary Oscillator Automatic Gain Control bit
1 = Automatic gain control is enabled (default)
0 = Manual oscillator gain control
bit 31
bit 30
When the POSCAGC bit is enabled and POSC HS mode is selected, DEVCFG1 = ‘0b10 (i.e., POSCMOD), the Primary Oscillator will automatically do a linear search to find the lowest power/gain setting to
guarantee oscillation with the users crystal.
Note:
If the POSCMOD bits (DEVCFG1/ADEVCFG1_ = ‘0b00 (i.e., POSCMOD = EC
mode), the POSCAGC bit must be set to ‘0’. POSCMOD = EC mode with POSCAGC = 1 is not
permitted and will result in no oscillation.
Reserved: Do not write a logic “0” to this bit.
bit 26
bit 25-24 POSCAGCDLY: Primary Crystal AGC Gain Search Step Settling Time Control bits
11 = Approximately (25 ms) (default)
10 = Approximately (6.25 ms)
01 = Approximately (400 ms)
00 = Approximately (100 ms)
Note 1: When the POSCAGC bit (DEVCFG0) = 0 (i.e., manual oscillator gain control), these bits are
not used. They are only used when AGC is enabled.
2: For POSC HS mode (DEVCFG1 = ‘0b10), the default setting should meet the user crystal
requirements. Internally, there are a maximum of 16 and a minimum of one AGC linear gain
search steps the logic may utilize before locking. A lock will occur when the crystal is oscillating
and the amplitude of the crystal signal is between a max and min fixed internal threshold. The
POSCAGCDLY is the time for each of the possible AGC search steps settling time to allow the
crystal to startup and amplitude stabilize before determining if a lock is true or to continue to
search for the required gain. The POSCAGCDLY bits represent a balance between startup time and crystal power optimization. The lower the POSCAGCDLY delay time the faster the
crystal start-up time but potentially at a higher crystal power level. The higher the POSCAGCDLY
delay time the slower the crystal start-up time but with a better crystal power optimization level
(i.e., less power).
3: Use of resonators with this product have not been confirmed -- use at your own discretion. When
using a resonator, due to their long start-up times, it may be necessary to use a longer AGC gain
step settling time.
DS60001570C-page 562
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 32-3:
DEVCFG0/ADEVCFG0: DEVICE/ALTERNATE DEVICE
CONFIGURATION WORD 0 (CONTINUED)
bit 23-22 POSCFGAIN: Primary Crystal Oscillator Fine Gain Control bits
11 = Gain level 3 (highest, default)
10 = Gain is G2
01 = Gain is G1
00 = Gain is G0(lowest)
Note 1: G3 > G2 > G1 > G0.
2: When the POSCAGC bit (DEVCFG0) = 1 (i.e., automatic gain control), or the
POSCMOD bits (DEVCFG1/ADEVCFG1) ‘0b10 (i.e., HS crystal mode), the POSCGAIN bits are not used.
3: These bits are used in conjunction with DEVCFG0/ADEVCFG0. In almost all cases, the
crystal fine gain default setting of ‘0b11 will work with the users course gain setting selection.
bit 21
POSCBOOST: Primary Oscillator Boost bit
1 = Uses internal XTAL feedback gain resistor (Default, in which case the user application should not use
any external XTAL feedback resistor in the crystal circuit)
0 = Disconnects the internal XTAL feedback resistor
bit 20-19 POSCGAIN: Primary Crystal Oscillator Coarse Gain Control bits
11 = Gain Level 3 (highest, default)
10 = Gain Level 2
01 = Gain Level 1
00 = Gain Level 0 (lowest)
Note 1: G3 > G2 > G1 > G0.
2: When the POSCAGC bit (DEVCFG0) = 1 (i.e., automatic gain control), or the
POSCMOD bits (DEVCFG1/ADEVCFG1) ‘0b10 (i.e., HS crystal mode), the POSCGAIN bits are not used.
SOSCBOOST: Secondary Oscillator Kick Start Programmability bit
bit 18
1 = Start up and operate with high-power SOSC internal buffer only.
0 = Start up with internal SOSC high-power buffer, and then switch to low-power buffer when the SOSC is
stable.
bit 17-16 SOSCGAIN: Secondary Oscillator Gain Control bits
If SOSCGAIN = 0:
11 = Gain is G3 (default)
10 = Gain is G2
01 = Gain is G1
00 = Gain is G0
Note:
G3 > G2 > G1 > G0.
bit 15
SMCLR: Soft Master Clear Enable bit
1 = MCLR pin generates a normal system Reset
0 = MCLR pin generates a POR Reset
bit 14-12 DBGPER: Debug Mode CPU Access Permission bits
1xx = Allow CPU access to Permission Group 2 permission regions
x1x = Allow CPU access to Permission Group 1 permission regions
xx1 = Allow CPU access to Permission Group 0 permission regions
0xx = Deny CPU access to Permission Group 2 permission regions
x0x = Deny CPU access to Permission Group 1 permission regions
xx0 = Deny CPU access to Permission Group 0 permission regions
Note:
bit 11
When the CPU is in Debug mode and the CPU1PG bits (CFGPG) are set to a denied
permission group as defined by DBGPER, the transaction request is assigned Group 3 permissions.
Reserved: This bit is controlled by debugger/emulator development tools and should not be modified by the
user.
2019-2020 Microchip Technology Inc.
DS60001570C-page 563
PIC32MK GPG/MCJ with CAN FD Family
DEVCFG0/ADEVCFG0: DEVICE/ALTERNATE DEVICE
CONFIGURATION WORD 0 (CONTINUED)
REGISTER 32-3:
bit 10
bit 9-8
FSLEEP: Flash Sleep Mode bit
1 = Flash is powered down when the device is in Sleep mode
0 = Flash power down is controlled by the VREGS bit (PWRCON)
FECCCON: Dynamic Flash ECC Configuration bits
11 = ECC and dynamic ECC are disabled (ECCCON bits are writable)
10 = ECC and dynamic ECC are disabled (ECCCON bits are locked)
01 = Dynamic Flash ECC is enabled (ECCCON bits are locked)
00 = Flash ECC is enabled (ECCCON bits are locked; disables word Flash writes)
Note:
bit 7
bit 6
bit 5
bit 4-3
bit 2
Upon a device POR, the value of these bits are copied by hardware into CFGCON bits, (i.e.
ECCCON.
Reserved: Write as ‘1’
BOOTISA: Boot ISA Selection bit
1 = Boot code and Exception code is MIPS32
(ISAONEXC bit is set to ‘0’ and the ISA bits are set to ‘10’ in the CP0 Config3 register)
0 = Boot code and Exception code is microMIPS
(ISAONEXC bit is set to ‘1’ and the ISA bits are set to ‘11’ in the CP0 Config3 register)
TRCEN: Trace Enable bit
1 = Trace features in the CPU are enabled
0 = Trace features in the CPU are disabled
ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bits
11 = PGEC1/PGED1 pair is used
10 = PGEC2/PGED2 pair is used
01 = PGEC3/PGED3 pair is used
00 = Reserved
JTAGEN: JTAG Enable bit
1 = JTAG is enabled
0 = JTAG is disabled
Note 1: On Reset, this Configuration bit is copied into JTAGEN (CFGCON). If JTAGEN
(DEVCFG0) = 0, the JTAGEN bit cannot be set to ‘1’ by the user application at
run-time, as JTAG is always disabled. However, if JTAGEN (DEVCFG0) = 1, the
user application may enable/disable JTAG at run-time by simply writing JTAGEN
(CFGCON as required.
bit 1-0
2: This bit sets the value of the JTAGEN bit in the CFGCON register.
DEBUG: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)
11 = 4-wire JTAG Enabled - PGECx/PGEDx Disabled - ICD module Disabled
10 = 4-wire JTAG Enabled - PGECx/PGEDx Disabled - ICD module Enabled
01 = PGECx/PGEDx Enabled - 4-wire JTAG I/F Disabled - ICD module Disabled
00 = PGECx/PGEDx Enabled - 4-wire JTAG I/F Disabled - ICD module Enabled
Note:
When the FJTAGEN or JTAGEN bits are equal to ‘0’, this prevents 4-wire JTAG debugging, but
not PGECx/PGEDx debugging.
DS60001570C-page 564
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 32-4:
Bit
Range
31:24
DEVCFG1/ADEVCFG1: DEVICE/ALTERNATE DEVICE
CONFIGURATION WORD 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
R/P
R/P
R/P
R/P
R/P
R/P
FDMTEN
23:16
15:8
DMTCNT
R/P
R/P
R/P
FWDTEN
WINDIS
WDTSPGM
R/P
R/P
FCKSM
7:0
R/P
R/P
IESO
FSOSCEN(1)
R/P
Bit
24/16/8/0
R/P
R/P
FWDTWINSZ
R/P
R/P
R/P
R/P
R/P
R/P
WDTPS
r-1
r-1
r-1
R/P
—
—
—
OSCIOFNC
R/P
R/P
R/P
R/P
Bit
25/17/9/1
DMTINV
POSCMOD
R/P
Legend:
r = Reserved bit
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
R/P
FNOSC
x = Bit is unknown
FDMTEN: Deadman Timer enable bit
1 = Deadman Timer is enabled and cannot be disabled by software
0 = Deadman Timer is disabled and can be enabled by software
bit 30-26 DMTCNT: Deadman Timer Count Select bits
11111 = Reserved
•
•
•
11000 = Reserved
10111 = 231 (2147483648)
10110 = 230 (1073741824)
10101 = 229 (536870912)
10100 = 228 (268435456)
•
•
•
00001 = 29 (512)
00000 = 28 (256)
bit 25-24 FWDTWINSZ: Watchdog Timer Window Size bits
11 = Window size is 25%
10 = Window size is 37.5%
01 = Window size is 50%
00 = Window size is 75%
bit 23
FWDTEN: Watchdog Timer Enable bit
1 = Watchdog Timer is enabled and cannot be disabled by software
0 = Watchdog Timer is not enabled; it can be enabled in software
bit 22
WINDIS: Watchdog Timer Window Enable bit
1 = Watchdog Timer is in non-Window mode
0 = Watchdog Timer is in Window mode
bit 21
WDTSPGM: Watchdog Timer Stop During Flash Programming bit
1 = Watchdog Timer stops during Flash programming
0 = Watchdog Timer runs during Flash programming (for read/execute while programming Flash
applications)
Note 1:
If using external clock oscillator for SOSC instead of crystal, the FSOSCEN bit must be set to ‘0’ with clock
oscillator input connected to SOSCO; SOSC output pin not the SOSCI input pin. This will free up the
SOSCI pin for use as an extra I/O pin.
2019-2020 Microchip Technology Inc.
DS60001570C-page 565
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 32-4:
DEVCFG1/ADEVCFG1: DEVICE/ALTERNATE DEVICE
CONFIGURATION WORD 1 (CONTINUED)
bit 20-16 WDTPS: Watchdog Timer Postscale Select bits
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
All other combinations not shown result in operation = 10100
bit 15-14 FCKSM: Clock Switching and Monitoring Selection Configuration bits
11 = Software run-time clock switching is enabled and clock monitoring is enabled
10 = Software run-time clock switching is disabled and clock monitoring is enabled
01 = Software run-time clock switching is enabled and clock monitoring is disabled
00 = Software run-time clock switching is disabled and clock monitoring is disabled
bit 13-11 Reserved: Write as ‘1’
bit 10
OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output is disabled
0 = CLKO output signal is active on the OSC2 pin; Primary Oscillator must be disabled or configured for the
External Clock mode (EC) for the CLKO to be active (POSCMOD = 11 or 00)
bit 9-8
POSCMOD: Primary Oscillator Configuration Mode bits
11 = POSC is disabled
10 = HS Oscillator mode is selected
01 = Reserved
00 = EC mode is selected. This mode must not be selected if the POSCAGC bit (DEVCFG0/
ADEVCFG0) = 1.
bit 7
IESO: Internal External Switchover bit
1 = Internal to External HDW Clock Switchover mode is enabled (Two-Speed Start-up is enabled)
0 = Internal to External HDW Clock Switchover mode is disabled (Two-Speed Start-up is disabled)
When IES0 is set, CPU hardware will start up executing code on FRC and automatically switch to the clock
source defined by FNOSC when that oscillator source is ready and stable, regardless of whether or not
FCKSM clock switching is enabled.
bit 6
FSOSCEN: Secondary Oscillator Enable bit
1 = Enable SOSC
0 = Disable SOSC
Note 1:
If using external clock oscillator for SOSC instead of crystal, FSOSCEN bit must be set to ‘0’ with clock
oscillator input connected to SOSCO, SOSC output pin not the SOSCI input pin. This will free up the
SOSCI pin for use as an extra I/O pin.
DS60001570C-page 566
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 32-4:
DEVCFG1/ADEVCFG1: DEVICE/ALTERNATE DEVICE
CONFIGURATION WORD 1 (CONTINUED)
bit 5-3
DMTINV: Deadman Timer Count Window Interval bits
111 = Window/Interval value is 127/128 counter value
110 = Window/Interval value is 63/64 counter value
101 = Window/Interval value is 31/32 counter value
100 = Window/Interval value is 15/16 counter value
011 = Window/Interval value is 7/8 counter value
010 = Window/Interval value is 3/4 counter value
001 = Window/Interval value is 1/2 counter value
000 = Window/Interval value is zero
bit 2-0
FNOSC: Oscillator Selection bits
111 = Reserved
110 = Backup Fast RC (BFRC) Oscillator
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Reserved
010 = Primary Oscillator (POSC) (HS, EC)
001 = System PLL (SPLL Module) (input clock and divider set by SPLLCON)
000 = Fast RC Oscillator (FRC) divided by the FRCDIV bits (OSCCON)
(supports FRC / n, where n = 1, 2, 4, 8, 16, 32, 64, 256
Note 1:
If using external clock oscillator for SOSC instead of crystal, FSOSCEN bit must be set to ‘0’ with clock
oscillator input connected to SOSCO, SOSC output pin not the SOSCI input pin. This will free up the
SOSCI pin for use as an extra I/O pin.
2019-2020 Microchip Technology Inc.
DS60001570C-page 567
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 32-5:
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
R/P-0
R/P-0
R/P-0
R/P-0
R/P-0
31:24
23:16
15:8
7:0
DEVCFG2/ADEVCFG2: DEVICE/ALTERNATE DEVICE
CONFIGURATION WORD 2
r-1
R/P
—
—
BORSEL
—
—
—
—
—
R/P-0
R/P-0
R/P-0
R/P-0
r-1
R/P
R/P
R/P
—
—
—
—
—
r-1
R/P
R/P
R/P
R/P
R/P
R/P
R/P
—
R/P
FPLLODIV
R/P
R/P
R/P
R/P
R/P
FPLLMULT
FPLLICLK
r-1
FPLLRNG
R/P
—
FPLLIDIV
Legend:
r = Reserved bit
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Reserved: Write as ‘1’
bit 29
BORSEL: Brown-out Reset (BOR) Select Trip Voltage bit
1 = BOR trip voltage 2.168V (non-op amp device operation)
0 = BOR trip voltage 2.932V (op amp device operation)
Note:
The user application must select the greatest BORSEL voltage to enable the highest trip voltage
possible that is still less than VDD application operating voltage.
bit 28-20 Reserved: Write as ‘0’
bit 19
RESERVED: Write as “1”
bit 18-16 FPLLODIV: Default System PLL Output Divisor bits
111 = PLL output divided by 32
110 = PLL output divided by 32
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 2
bit 15
Reserved: Write as ‘1’
bit 14-8
FPLLMULT: System PLL Feedback Divider bits
1111111 = Multiply by 128
1111110 = Multiply by 127
1111101 = Multiply by 126
1111100 = Multiply by 125
•
•
•
0000000 = Multiply by 1
bit 7
FPLLICLK: System PLL Input Clock Select bit
1 = FRC is selected as input to the System PLL
0 = POSC is selected as input to the System PLL
DS60001570C-page 568
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 32-5:
bit 6-4
DEVCFG2/ADEVCFG2: DEVICE/ALTERNATE DEVICE
CONFIGURATION WORD 2 (CONTINUED)
FPLLRNG: System PLL Divided Input Clock Frequency Range bits
111 = Reserved
110 = Reserved
101 = 34-64 MHz
100 = 21-42 MHz
011 = 13-26 MHz
010 = 8-16 MHz
001 = 5-10 MHz
000 = Bypass
Note:
Use the highest filter range that covers the input frequency to the VCO multiplier block that
corresponds to the PLLIDIV output freq to minimize PLL system jitter (see FIGURE 71: “PIC32MK GPG/MCJ with CAN FD Family Oscillator Diagram”). For example, Crystal =
20 MHz, PLLIDIV = ‘0b1; therefore, the filter input frequency is equal to 10 MHz and
SPLLRANGE FPLLRNG = ‘0b010.
bit 3
Reserved: Write as ‘1’
bit 2-0
FPLLIDIV: PLL Input Divider bits
111 = Divide by 8
110 = Divide by 7
101 = Divide by 6
100 = Divide by 5
011 = Divide by 4
010 = Divide by 3
001 = Divide by 2
000 = Divide by 1
2019-2020 Microchip Technology Inc.
DS60001570C-page 569
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 32-6:
Bit
Range
31:24
23:16
15:8
7:0
DEVCFG3/ADEVCFG3: DEVICE/ALTERNATE DEVICE
CONFIGURATION WORD 3
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
r-1
r-1
R/P
—
—
IOL1WAY
R/P
R/P
r-1
r-1
r-1
R/P
r-1
r-1
r-1
r-1
—
—
—
PWMLOCK
—
—
—
—
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
PMDL1WAY PGL1WAY
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
r-1
r-1
—
—
—
USERID
R/P
Legend:
R = Readable bit
-n = Value at POR
R/P
R/P
R/P
R/P
USERID
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
P = Programmable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 RESERVED:Write as “1”
bit 29
IOL1WAY: Peripheral Pin Select Configuration bit
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
bit 28
PMDL1WAY: Peripheral Module Disable Configuration bit
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
bit 27
PGL1WAY: Permission Group Lock One Way Configuration bit
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
bit 26-22 Reserved: Write as ‘1’
bit 21
Reserved: Write as ‘1’
bit 20
PWMLOCK: PWM Write Access Select bit
1 = Write accesses to the PWM IOCONx register are not locked or protected
0 = Write accesses to the PWM IOCONx register must use the PWMKEY unlock procedure
bit 19-16 Reserved: Write as ‘1’
bit 15-0 USERID: This is a 16-bit value that is user-defined and is readable via ICSP™ and JTAG
DS60001570C-page 570
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 32-7:
Bit
Range
31:24
23:16
15:8
7:0
CFGCON: CONFIGURATION CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
r-0
PMDLOCK(1)
PGLOCK(1)
—
—
—
R/W-y
R/W-y
R/W-0
U-0
R/W-1
JTAGEN
TROEN
—
TDOEN
—
—
IOLOCK(1)
U-0
U-0
R/W-y
—
—
ECCCON
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
r-0
U-0
ADCPRI(1)
—
—
R/W-0
R/W-0
ICACLK(1) OCACLK(1)
r-0
U-0
Legend:
r = Reserved bit
y = Value set from Configuration bits on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26
bit 25
ADCPRI: ADC Arbitration Priority to SRAM bit(1)
1 = ADC gets High Priority access to SRAM
0 = ADC uses Least Recently Serviced Arbitration (same as other initiators)
Reserved: Write as ‘0’
bit 24-18 Unimplemented: Read as ‘0’
bit 17
ICACLK: Input Capture Alternate Clock Selection bit(1)
1 = Input Capture modules use an alternative Timer pair as their timebase clock
0 = All Input Capture modules use Timer2/3 as their timebase clock
OCACLK: Output Compare Alternate Clock Selection bit(1)
1 = Output Compare modules use an alternative Timer pair as their timebase clock
0 = All Output Compare modules use Timer2/3 as their timebase clock
bit 15-14 Unimplemented: Read as ‘0’
bit 16
bit 13
bit 12
IOLOCK: Peripheral Pin Select Lock bit(1)
1 = Peripheral Pin Select is locked. Writes to PPS registers are not allowed
0 = Peripheral Pin Select is not locked. Writes to PPS registers are allowed
PMDLOCK: Peripheral Module Disable bit(1)
1 = Peripheral module is locked. Writes to PMD registers are not allowed
0 = Peripheral module is not locked. Writes to PMD registers are allowed
PGLOCK: Permission Group Lock bit(1)
1 = Permission Group registers are locked. Writes to PG registers are not allowed
0 = Permission Group registers are not locked. Writes to PG registers are allowed
bit 10-9 Reserved: Write as ‘0’
bit 11
bit 8
bit 7-6
Unimplemented: Read as ‘0’
Unimplemented: Read/write as ‘0’
bit 5-4
ECCCON: Flash ECC Configuration bits
11 = ECC and dynamic ECC are disabled (ECCCON bits are writable)
10 = ECC and dynamic ECC are disabled (ECCCON bits are locked)
01 = Dynamic Flash ECC is enabled (ECCCON bits are locked)
00 = Flash ECC is enabled (ECCCON bits are locked; disables word Flash writes)
Note:
Note 1:
These bits are loaded from DEVCFG0, (i.e. FECCCON), configuration word fuse bits
on POR power on reset
To change this bit, the unlock sequence must be performed. Refer to Section 42. “Oscillators with
Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
2019-2020 Microchip Technology Inc.
DS60001570C-page 571
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 32-7:
bit 3
CFGCON: CONFIGURATION CONTROL REGISTER (CONTINUED)
JTAGEN: JTAG Port Enable bit
1 = Enable the JTAG port
0 = Disable the JTAG port
Note:
bit 2
The reset value of this bit is the value of the JTAGEN Configuration Word setting in the DEVCFG0
register. If JTAGEN (DEVCFG0) = 0, this bit cannot be set to ‘1’ by the user application at runtime. If JTAGEN (DEVCFG0) = 1, the user application may enable/disable JTAG at run-time
by writing this bit to the desired value.
TROEN: Trace Output Enable bit
1 = Enable trace outputs and start trace clock (trace probe must be present)
0 = Disable trace outputs and stop trace clock
Note:
When the user Configuration Word, TRCEN in the DEVCFG0 register is equal to ‘0’, the value of
this bit is ignored, but has the effect of being ‘0’.
bit 1
Unimplemented: Read as ‘0’
bit 0
TDOEN: TDO Enable for 2-Wire JTAG
1 = 2-wire JTAG protocol uses TDO
0 = 2-wire JTAG protocol does not use TDO
Note:
Note 1:
Implementing the JTAG protocol over the 2-wire interface requires four 2-wire clocks for each TCK
if TDO is required. However, if the values shifted out TDO are predetermined, TDO can be
disabled.
To change this bit, the unlock sequence must be performed. Refer to Section 42. “Oscillators with
Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
DS60001570C-page 572
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 32-8:
Bit
Range
31:24
23:16
15:8
7:0
CFGPG: PERMISSION GROUP CONFIGURATION REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
R/W-0
R/W-0
FCPG
U-0
U-0
—
—
U-0
U-0
—
—
Legend:
R = Readable bit
-n = Value at POR
JTAGPG
ADCPG
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R/W-0
R/W-0
U-0
U-0
U-0
U-0
CAN1PG
R/W-0
R/W-0
DMAPG
W = Writable bit
‘1’ = Bit is set
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
CPUDSPG
CPUPG
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 JTAGPG: JTAG Permission Group bits
Same definition as bits 25-24.
bit 27-26 Unimplemented: Read as ‘0’
bit 25-24 ADCPG: ADC Permission bits
The Bus Initiator has access to access controlled memory regions as defined by the bus structure’s
permission group SFRs for RDPER and WRPER.
11 = Read access if RDPER = 1; write access if WRPER = 1
10 = Read access if RDPER = 1; write access if WRPER = 1
01 = Read access if RDPER = 1; write access if WRPER = 1
00 = Read access if RDPER = 1; write access if WRPER = 1
bit 23-22 FCPG: Flash Control Permission Group bits
Same definition as bits 25-24.
bit 21-14 Unimplemented: Read as ‘0’
bit 13-12 CAN1PG: CAN1 Module Permission Group bits
Same definition as bits 25-24.
bit 11-6 Unimplemented: Read as ‘0’
bit 5-4
DMAPG: DMA Module Permission Group bits
Same definition as bits 25-24.
bit 3-2
CPUDSPG: CPU Data Space Permission Group bits
Same definition as bits 25-24.
bit 1-0
CPUPG: CPU Instruction Space Permission Group bits
Same definition as bits 25-24.
Note:
CPUPG automatically reverts to ‘0b00 when the CPU acknowledges entry into a NMI
exception as indicated by the GNMI bit (RNMICON). The effective value of CPUPG
when the CPU is in Debug Mode is controlled by the DBGPER bit in the DEVCFG0/ADEVCFG0
register. If DBGPER denies access to the Group CPUPG selects, the effective value selects
Group3.
2019-2020 Microchip Technology Inc.
DS60001570C-page 573
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 32-9:
Bit
Range
31:24
DEVID: DEVICE AND REVISION ID REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
R
R
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
R
R
R
R
R
R
R
(1)
VER
R
23:16
R
Bit
25/17/9/1
Bit
24/16/8/0
R
(1)
R
R
R
R
R
(1)
R
R
R
R
R
R
R
(1)
DEVID
DEVID
15:8
R
R
R
R
R
R
R
DEVID
7:0
R
DEVID(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 VER: Revision Identifier bits(1)
bit 27-0
DEVID: Device ID(1)
Note 1:
See the “PIC32 Flash Programming Specification” (DS60001145) for a list of Revision and Device ID values.
REGISTER 32-10: DEVADCx: DEVICE ADC CALIBRATION REGISTER ‘x’ (‘x’ = 0-5, 7)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R
R
R
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
ADCAL
R
R
R
R
R
ADCAL
R
R
R
R
R
ADCAL
R
R
R
R
R
ADCAL
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
Bit
28/20/12/4
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
ADCAL: Calibration Data for the ADC Module bits
Before enabling the ADC, the user application must initialize the ADC calibration values by copying them
from the factory programmed DEVADCx Flash locations starting at 0xBFC45000 into the ADCxCFG
registers starting at 0xBF887D00, respectively. Refer to 23.0 “12-bit High-Speed Successive
Approximation Register (SAR) Analog-to-Digital Converter (ADC)” for more information.
DS60001570C-page 574
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
REGISTER 32-11: DEVSNx: DEVICE SERIAL NUMBER REGISTER ‘x’ (‘x’ = 0-3)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
SN
R
R
R
R
SN
R
R
R
R
SN
R
R
R
R
SN
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
R
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
SN: Device Unique Serial Number bits
These registers contain a value, programmed during factory production test, that is unique to each unit
and are user read only. These values are persistent and not erased even when a new application code is
programmed into the device. These values can be used if desired as an encryption key in combination
with the Microchip encryption library.
2019-2020 Microchip Technology Inc.
DS60001570C-page 575
PIC32MK GPG/MCJ with CAN FD Family
32.3
On-Chip Voltage Regulator
The core and digital logic for all PIC32MK GPG/MCJ
with CAN FD Family of devices are designed to operate
at a nominal 1.2V. To simplify system designs, devices
in the PIC32MK GPG/MCJ with CAN FD Family incorporate an on-chip regulator providing the required core
logic voltage from VDD.
32.3.1
ON-CHIP REGULATOR AND BOR
PIC32MK GPG/MCJ with CAN FD Family of devices
also have a simple brown-out capability. If the voltage
supplied to the regulator is inadequate to maintain a
regulated level, the regulator Reset circuitry will
generate a Brown-out Reset. This event is captured by
the BOR flag bit (RCON). The brown-out voltage
levels are specific in 36.1 “DC Characteristics”.
32.4
On-chip Temperature Sensor
PIC32MK GPG/MCJ with CAN FD Family of devices
include a temperature sensor that provides accurate
measurement of a device’s junction temperature (see
36.2 “AC Characteristics and Timing Parameters”
for more information).
The temperature sensor is connected to the ADC
module and can be measured using the shared S&H
circuit (see 23.0 “12-bit High-Speed Successive
Approximation Register (SAR) Analog-to-Digital
Converter (ADC)” for more information).
32.5
BLOCK DIAGRAM OF
PROGRAMMING,
DEBUGGING AND TRACE
PORTS
PGEC1
PGED1
ICSP™
Controller
ON-CHIP REGULATOR AND POR
It takes a fixed delay for the on-chip regulator to generate
an output. During this time, designated as TPU, code
execution is disabled. TPU is applied every time the
device resumes operation after any power-down,
including Sleep mode.
32.3.2
FIGURE 32-1:
PGEC2
PGED2
ICESEL
TDI
TDO
TCK
JTAG
Controller
Core
TMS
JTAGEN
DEBUG
TRCLK
TRD0
TRD1
Instruction Trace
Controller
TRD2
TRD3
DEBUG
Programming and Diagnostics
PIC32MK GPG/MCJ with CAN FD Family of devices
provide a complete range of programming and diagnostic features that can increase the flexibility of any
application using them. These features allow system
designers to include:
• Simplified field programmability using two-wire
In-Circuit Serial Programming™ (ICSP™)
interfaces
• Debugging using ICSP
• Programming and debugging capabilities using
the EJTAG extension of JTAG
• JTAG boundary scan testing for device and board
diagnostics
PIC32MK devices incorporate two programming and
diagnostic modules, and a trace controller, that provide
a range of functions to the application developer.
DS60001570C-page 576
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
NOTES:
2019-2020 Microchip Technology Inc.
DS60001570C-page 577
PIC32MK GPG/MCJ with CAN FD Family
33.0
INSTRUCTION SET
The PIC32MK GPG/MCJ with CAN FD Family instruction set complies with the MIPS32® Release 5 instruction set architecture. The PIC32MK GPG/MCJ with
CAN FD Family device family does not support the following features:
• Core extend instructions
• Coprocessor 1 instructions
• Coprocessor 2 instructions
Note:
Refer to “MIPS32® Architecture for
Programmers Volume II: The MIPS32®
Instruction Set” at www.imgtec.com for
more information.
DS60001570C-page 578
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
NOTES:
2019-2020 Microchip Technology Inc.
DS60001570C-page 579
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 580
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
34.0
MIGRATION GUIDE
TABLE 34-1:
PIC32MKXXGPD/GPEXX TO PIC32MKXXGPGXX MIGRATION REFERENCE
PIC32MKxxGPD/GPExx
FEATURE
PIC32MKxxGPGxx
64-pin PIC32MKxxGPD/E
to
64-pin PIC32MKxxGPG
Migration Impact
PCB HDW
SW
100/64
#PIN
64/44
X
X
77 (100-pin), 48 (64-pin)
# I/O
53 (64-pin), 37 (48-pin)
X
X
MIPS arch @ 120 MHz
CPU
MIPS arch @ 120 MHz
---
---
4
Configuration Word
Registers
5
---
X
1024 / 512 Mb
No ECC
Live Update
Dual Boot
FLASH
524,288,262,144 Mb
ECC
No Live Update
No Dual Boot
---
X(2)
256, 128 Kb
SRAM
64-Kb Only
---
X(1)
POSC
SOSC
UPLL (USB PLL)
Oscillator
POSC w/AGC & Fine gain
SOSC
No UPLL (No USB)
X(2)
X(2)
4-Kb
EE Data Flash Module
(None)
---
X
(None)
CLC
(Configurable Logic Cell)
4
---
---
8/13
DMA
8/2
---
X
(2) Full-Speed (100 pin)
(1) Full-Speed (64 pin)
USB
(None)
X
X
1
TIMER1
1 (Identical)
---
---
8
32 bit TIMERS 2-9 type B
8 (Identical)
---
---
1
Watch Dog Timer
1 (identical)
---
---
1
Dead Man Timer
1
---
---
16
Input Capture
8
X(1)
X(1)
16
Output Compare
8
X(1)
X(1)
6
SPI
2
X(1)
X(1)
(None)
I2 C
2
---
---
6
UART
2
X(1)
X(1)
1
PMP
(None)
X
X
1
RTCC
1 (Identical)
---
---
CAN (Lite)
CAN
CAN FD
(New HDW/SW)
---
X
7
ADC Modules
7 (Identical)
---
--X(1)
X
42 (100-pin), 26 (64 pin-
ADC Channels
30 (64-pin), 18 (48-pin)
X(1)
4
OPAMP
4 (New features
and configurations)
---
2019-2020 Microchip Technology Inc.
DS60001570C-page 586
PIC32MK GPG/MCJ with CAN FD Family
TABLE 34-1:
PIC32MKXXGPD/GPEXX TO PIC32MKXXGPGXX MIGRATION REFERENCE
(CONTINUED)
PIC32MKxxGPD/GPExx
FEATURE
PIC32MKxxGPGxx
64-pin PIC32MKxxGPD/E
to
64-pin PIC32MKxxGPG
Migration Impact
PCB HDW
SW
5
COMPARATORS
5 (New features
and configurations)
---
X
3
DAC
2
X(1)
X(1)
(None)
Low Voltage Detect
1
---
X
1
CTMU
1 (Identical)
---
---
Yes (20)
CVD Module
(Touch Enhancement)
Yes (24)
X(1)
X(1)
Yes
PMD
(Peripheral Module
Disable)
Yes (Fewer Peripherals)
---
X(1)
Yes
JTAG
Yes
---
---
Yes (100-pin and 64-pin)
TRACE
Yes (64-pin), No (48-pin)
---
---
Note 1:
2:
3
PGCx/PGDx (Debug)
3
---
---
Yes
VBAT
No
X
X
Yes
Deep Sleep
No
---
X
This is only affected if the user application is using any additional modules, peripheral functions, peripheral
pin function, or features on the PIC32MKxxGPD/GPExx that the PIC32MKxxGPGxx does not posses (see
Table 34-2 for more information).
POSC Legacy code on PIC32MKxxGPD/GPExx will default in silicon on to PIC32MKxxGPGxx POSC w/
AGC and ignore POSC gain setting. If using an external shunt gain resistor across POSC XTAL on
PIC32MKxxGPD/GPExx users must ensure that the DEVCFG0=0 on PIC32MKxxGPGxx
or remove the resistor for operation. Either internal or external gain boost but not both.
DS60001570C-page 587
2019-2020 Microchip Technology Inc.
64 PIN PIC32MKXXGPD/E TO PIC32MKXXGPG FUNCTION MIGRATION MISMATCHES
PIC32MKxxGPD/GPExx 64 pin
PIC32MKxxGPGxx 64 Pin
Pin
Function
Match
1
TCK/RPA7/PMD5/RA7
TCK/RPA7/RA7
NO
PMD5
PMP
2
RPB14/VBUSON1/PMD6/RB14
RPB14/RB14
NO
VBUSON1/PMD6
USB / PMP
3
RPB15/PMD7/RB15
RPB15/RB15
NO
PMD7
PMP
4
AN19/CVD19/RPG6/PMA5/RG6
AN19/CVD19/RPG6/RG6
NO
PMA5
PMP
5
AN18/CVD18/RPG7/PMA4/RG7(6)
AN18/CVD18/RPG7/RG7
NO
PMA4
PMP
6
AN17/CVD17/RPG8/PMA3/RG8(7)
AN17/CVD17/RPG8/RG8
NO
PMA3
PMP
7
MCLR#
MCLR#
MATCH
---
---
8
AN16/CVD16/RPG9/PMA2/RG9
AN16/CVD16/RPG9/RG9
NO
PMA2
PMP
Pin #
Mismatch
Function
Peripheral
DS60001570C-page 588
9
VSS
VSS
MATCH
---
---
10
VDD
VDD
MATCH
---
---
11
AN10/CVD10/RPA12/RA12
AN10/CVD10/RPA12/RA12
MATCH
---
---
12
AN9/CVD9/RPA11/RA11
AN9/CVD9/RPA11/RA11
MATCH
---
---
13
OA2OUT/AN0/C2IN4-/C4IN3-/RPA0/RA0
OA2OUT/AN0/C2IN4-/C4IN3-/RPA0/RA0
MATCH
---
---
14
OA2IN+/AN1/C2IN1+/RPA1/RA1
OA2IN+/AN1/C2IN1+/RPA1/RA1
MATCH
---
---
15
PGD3/VREF-/OA2IN-/AN2/C2IN1-/RPB0/
CTED2/RB0
PGD3/VREF-/OA2IN-/AN2/C2IN1-/RPB0/CTED2/
RB0
MATCH
---
---
16
PGC3/OA1OUT/VREF+/AN3/C1IN4-/C4IN2-/
RPB1/CTED1/PMA6/RB1
PGC3/OA1OUT/VREF+/AN3/C1IN4-/C4IN2-/
RPB1/CTED1/RB1
NO
PMA6
PMP
17
PGC1/OA1IN+/AN4/C1IN1+/C1IN3-/C2IN3-/
RPB2/RB2
PGC1/OA1IN+/AN4/C1IN1+/C1IN3-/C2IN3-/RPB2/
RB2
MATCH
---
---
18
PGD1/OA1IN-/AN5/CTCMP/C1IN1-/RTCC/
RPB3/RB3
PGD1/OA1IN-/AN5/CTCMP/C1IN1-/RTCC/RPB3/
RB3
MATCH
---
---
19
AVDD
AVDD
MATCH
---
---
20
AVSS
AVSS
MATCH
---
---
21
OA3OUT/AN6/CVD6/C3IN4-/C4IN1+/C4IN4-/
RPC0/RC0
OA3OUT/AN6/CVD6/C3IN4-/C4IN1+/C4IN4-/
RPC0/RC0
MATCH
---
---
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 34-2:
64 PIN PIC32MKXXGPD/E TO PIC32MKXXGPG FUNCTION MIGRATION MISMATCHES (CONTINUED)
Pin #
PIC32MKxxGPD/GPExx 64 pin
PIC32MKxxGPGxx 64 Pin
Pin
Function
Match
Mismatch
Function
Peripheral
22
OA3IN-/AN7/CVD7/C3IN1-/C4IN1-/RPC1/
PMA7/RC1
OA3IN-/AN7/CVD7/C3IN1-/C4IN1-/RPC1/RC1
NO
PMA7
PMP
23
OA3IN+/AN8/CVD8/C3IN1+/C3IN3-/RPC2/
PMA13/RC2
OA3IN+/AN8/CVD8/C3IN1+/C3IN3-/RPC2/RC2
NO
PMA13
PMP
24
AN11/CVD11/C1IN2-/PMA12/RC11
AN11/CVD11/C1IN2-/RC11
NO
PMA12
PMP
2019-2020 Microchip Technology Inc.
25
VSS
VSS
MATCH
---
---
26
VDD
VDD
MATCH
---
---
27
AN12/CVD12/C2IN2-/C5IN2-/PMA11/RE12
AN12/CVD12/C2IN2-/C5IN2-/RE12
NO
PMA11
PMP
28
AN13/CVD13/C3IN2-/PMA10/RE13
AN13/CVD13/C3IN2-/RE13
NO
PMA10
PMP
29
AN14/CVD14/RPE14/PMA1/RE14
AN14/CVD14/RPE14/RE14
NO
PMA1
PMP
30
AN15/CVD15/RPE15/PMA0/RE15
AN15/CVD15/RPE15/RE15
NO
PMA0
PMP
31
TDI/DAC3/AN26/CVD26/RPA8/PMA9/RA8
TDI/DAC2/AN26/CVD26/RPA8/SDA2/RA8
NO
PMA9/DAC3
PMP/DAC
32
RPB4/PMA8/RB4
RPB4/SCL2/RB4
NO
PMA8/SCL2
PMP/I2C
33
OA5IN+/DAC1/AN24/CVD24/C5IN1+/C5IN3-/
RPA4/T1CK/RA4
OA5IN+/AN24/CVD24/C5IN1+/C5IN3-/RPA4/RA4
NO
T1CLK
Timer1
34
VBUS
AN40/CVD40/RPE0/RE0
NO
ALL Functions:
USB /' ANx / CVD /
RPxx / IO
---
35
VUSB3V3
AN41/CVD41/RPE1/RE1
NO
---
---
36
D-
AN46/CVD46/RPA14/RA14
NO
---
---
37
D+
AN47/CVD47/RPA15/RA15
NO
---
---
38
VDD
VDD
MATCH
---
---
39
OSCI/CLKI/AN49/CVD49/RPC12/RC12
OSCI/CLKI/AN49/CVD49/RPC12/RC12
MATCH
---
---
40
OSCO/CLKO/RPC15/RC15
OSCO/CLKO/RPC15/RC15
MATCH
---
---
41
VSS
VSS
MATCH
---
---
42
VBAT
RD8
NO
VBAT /RD8
VBAT & I/O
43
PGD2/RPB5/USBID1/RB5
PGD2/RPB5/SDA1/RB5
NO
SDA1 / USBID
I2C / USB
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 589
TABLE 34-2:
64 PIN PIC32MKXXGPD/E TO PIC32MKXXGPG FUNCTION MIGRATION MISMATCHES (CONTINUED)
Pin #
PIC32MKxxGPD/GPExx 64 pin
PIC32MKxxGPGxx 64 Pin
Pin
Function
Match
Mismatch
Function
Peripheral
44
PGC2/RPB6/SCK2/PMA15/RB6
PGC2/RPB6/SCL1/RB6
NO
SCLK2/PMA15/
SCL1
SPI/PMP/I2C
45
DAC2/AN48/CVD48/RPC10/PMA14/RC10
DAC1/AN48/CVD48/RPC10/RC10
NO
PMA14/DAC2
PMP/DAC
46
OA5OUT/AN25/CVD25/C5IN4-/RPB7/SCK1/
INT0/RB7
OA5OUT/AN25/CVD25/C5IN4-/RPB7/SCK1/INT0/
RB7
MATCH
---
---
47
SOSCI/RPC13/RC13
SOSCI/RPC13/RC13
NO
---
---
48
SOSCO/RPB8/RB8
SOSCO/RPB8/T1CK/RB8
NO
T1CLK
Timer1
49
TMS/OA5IN-/AN27/CVD27/C5IN1-/RPB9/RB9
TMS/OA5IN-/AN27/CVD27/LVDIN/C5IN1-/RPB9/
RB9
NO
LVDIN
HLVD
50
TRCLK/RPC6/RC6
TRCLK/RPC6/RC6
MATCH
---
---
51
TRD0/RPC7/RC7
TRD0/RPC7/RC7
MATCH
---
---
52
TRD1/RPC8/PMWR/RC8
TRD1/RPC8/RC8
NO
PMWR
PMP
53
TRD2/RPD5/PMRD/RD5
TRD2/RPD5/RD5
NO
PMRD
PMP
54
TRD3/RPD6/RD6
TRD3/RPD6/RD6
MATCH
---
---
55
RPC9/RC9
RPC9/RC9
MATCH
---
---
56
VSS
VSS
MATCH
---
---
57
VDD
VDD
MATCH
---
---
58
RPF0/RF0
RPF0/RF0
MATCH
---
---
59
RPF1/RF1
RPF1/RF1
MATCH
---
---
60
RPB10/PMD0/RB10
RPB10/RB10
NO
PMD0
PMP
61
RPB11/PMD1/RB11
RPB11/RB11
NO
PMD1
PMP
DS60001570C-page 590
62
RPB12/PMD2/RB12
RPB12/RB12
NO
PMD2
PMP
63
RPB13/CTPLS/PMD3/RB13
RPB13/CTPLS/RB13
NO
PMD3
PMP
64
TDO/PMD4/RA10
TDO/RA10
NO
PMD4
PMP
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
TABLE 34-2:
PIC32MK GPG/MCJ with CAN FD Family
35.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
35.1
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
DS60001570C-page 591
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
35.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other
relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler
to produce its object file. Notable features of the
assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
35.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
35.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
35.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
2019-2020 Microchip Technology Inc.
DS60001570C-page 592
PIC32MK GPG/MCJ with CAN FD Family
35.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
35.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
DS60001570C-page 593
35.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
35.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the
target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
35.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
35.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
35.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
2019-2020 Microchip Technology Inc.
DS60001570C-page 594
PIC32MK GPG/MCJ with CAN FD Family
36.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC32MK GPG/MCJ with CAN FD Family electrical characteristics. Additional
information will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC32MK GPG/MCJ with CAN FD Family devices are listed below. Exposure to these
maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these
or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings
(See Note 1)
Ambient temperature under bias ........................................................................................................... (VDD + 0.3) for non-5V tolerant pins only.
Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any
“positive” input injection current.
Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD
+ 0.3) or VIL source < (VSS - 0.3)).
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the “absolute instantaneous” sum of the input injection currents from all pins do not exceed the
specified limit. If Note 2, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 3, IICH = ((IICH source - (VDD + 0.3))
/ RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3) VSOURCE (VDD +
0.3), injection current = 0.
2019-2020 Microchip Technology Inc.
DS60001570C-page 602
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param. Sym.
Characteristic
Min.
Typ.
Max. Units
Conditions
—
—
0.4
V
IOL 10 mA, VDD = 3.3V
—
—
0.4
V
IOL 15 mA, VDD = 3.3V
2.4
—
—
V
IOH -10 mA, VDD = 3.3V
2.4
—
—
V
IOH -15 mA, VDD = 3.3V
Output Low Voltage
I/O Pins
4x Sink Driver Pins RA0, RA4, RA11, RA12, RA14, RA15
RB0-RB3, RB8, RB9
RC0-RC2, RC10, RC12, RC13
RD8
RE0, RE1
RG8, RG9
DO10
VOL
Output Low Voltage
I/O Pins:
8x Sink Driver Pins RA1, RA7, RA8, RA10
RB4-RB7, RB10-RB15
RC6-RC9, RC11, RC15
RD5, RD6
RE12-RE15
RF0, RF1
RG6, RG7
Output High Voltage
I/O Pins:
4x Source Driver Pins RA0, RA4, RA11, RA12, RA14, RA15
RB0-RB3, RB8, RB9
RC0-RC2, RC10, RC12, RC13
RD8
RE0, RE1
RG8, RG9
DO20
VOH
Output High Voltage
I/O Pins:
8x Source Driver Pins RA1, RA7, RA8, RA10
RB4-RB7, RB10-RB15
RC6-RC9, RC11, RC15
RD5, RD6
RE12-RE15
RF0, RF1
RG6, RG7
DS60001570C-page 603
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param. Sym.
Characteristic
Output High Voltage
I/O Pins:
4x Source Driver Pins RA0, RA4, RA11, RA12, RA14, RA15
RB0-RB3, RB8, RB9
RC0-RC2, RC10, RC12, RC13
RD8
RE0, RE1
RG8, RG9
DO20a VOH1 Output High Voltage
I/O Pins:
8x Source Driver Pins 8x Source Driver Pins RA1, RA7, RA8, RA10
RB4-RB7, RB10-RB15
RC6-RC9, RC11, RC15
RD5, RD6
RE12-RE15
RF0, RF1
RG6, RG7
2019-2020 Microchip Technology Inc.
Min.
Typ.
Max. Units
Conditions
1.5
—
—
V
IOH -14 mA, VDD = 3.3V
2.0
—
—
V
IOH -12 mA, VDD = 3.3V
3.0
—
—
V
IOH -7 mA, VDD = 3.3V
1.5
—
—
V
IOH -22 mA, VDD = 3.3V
2.0
—
—
V
IOH -18 mA, VDD = 3.3V
3.0
—
—
V
IOH -10 mA, VDD = 3.3V
DS60001570C-page 604
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-12: DC CHARACTERISTICS: PROGRAM MEMORY(3)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param.
Sym.
No.
D130
Characteristics
—
E/W
—
VDD for Read
VDDMIN
—
VDDMAX
V
—
VDDMIN
—
VDDMAX
V
—
D134
TRETD Characteristic Retention
D135
IDDP
Supply Current during
Programming
Row Write Cycle Time (Notes 2)
—
Year
—
—
30
mA
—
—
—
265
—
384000
—
Combined Upper Plus Lower Flash
Panels Erase Cycle Time (both Boot 256000
Flash excluded)
—
320000 FRC Cycles
—
Single Panel Flash Erase Cycle
Time (either Upper or Lower Panel, 128000
excluding both Boot Flash)
—
160000 FRC Cycles
—
128000
—
160000 FRC Cycles
Erase Retry Disabled VREAD1
(NVMCON2) = 0
32000
—
160000 FRC Cycles
Erase Retry enabled VREAD1
(NVMCON2) = 1
—
—
D138
TWW
Word Write Cycle Time
D139
TCE
Chip Erase Cycle Time (Note 4)
D140
TPFE
TPGE
—
—
650
TRW
TQWW Quad Word Write Cycle Time
TPBE
20
16000
D136
D137
20800 FRC Cycles
—
777
FRC Cycles
—
297
FRC Cycles
—
480000 FRC Cycles
—
Page Erase Cycle Time
TFLPU NVM Power-up Delay
4:
Conditions
—
VPR
D143
Units
20,000
VPEW VDD for Erase or Write
Note 1:
2:
3:
Max.
Cell Endurance
D131
D142
Typ.(1)
EP
D132
D141
Min.
10
µs
—
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated.
The minimum SYSCLK for row programming is 4 MHz.
Refer to the “PIC32 Flash Programming Specification” (DS60001145) for operating conditions during
programming and erase cycles.
This parameter depends on FRC accuracy (see Table 36-17) and FRC tuning values (see the OSCTUN
register: Register 7-2).
TABLE 36-13: DC CHARACTERISTICS: PROGRAM FLASH MEMORY WAIT STATES FOR ACTIVE
HIGH POWER MODE
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
DEVCFG0
FECCCON bits
(DEVCFG0) = 0x1x
with ECC disabled
DS60001570C-page 605
Required Flash Wait
States
PFMWS bits
SYSCLK (MHz)
1 - Wait State
0 < SYSCLK 116 MHz
2 - Wait State
116 MHz < SYSCLK 120 MHz
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-13: DC CHARACTERISTICS: PROGRAM FLASH MEMORY WAIT STATES FOR ACTIVE
HIGH POWER MODE (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
DEVCFG0
Required Flash Wait
States
PFMWS bits
SYSCLK (MHz)
1 - Wait State
0 < SYSCLK 96 MHz
FECCCON bits
(DEVCFG0) = 0x0x
with ECC enabled
2019-2020 Microchip Technology Inc.
2 - Wait State
96 MHz < SYSCLK 120 MHz
DS60001570C-page 606
PIC32MK GPG/MCJ with CAN FD Family
36.2
AC Characteristics and Timing
Parameters
The information contained in this section defines
PIC32MK GPG/MCJ with CAN FD Family device AC
characteristics and timing parameters.
FIGURE 36-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2 (in EC mode)
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
VSS
TABLE 36-14: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
Symbol
No.
Min.
Typ.(1)
Max.
Units
Conditions
—
—
50
pF
—
DO56
Note 1:
CL
Characteristics
All I/O pins
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
DS60001570C-page 607
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-2:
EXTERNAL CLOCK TIMING
OS30
OS20
OS31
OSC1
OS31
OS30
TABLE 36-15: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
No.
OS10
FOSC
OS13
Minimum
Typical(1)
Maximum
Units
Conditions
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
—
64
MHz
EC (Note 2,3)
Oscillator Crystal Frequency
4
—
32
MHz
HS (Note 2,3)
32
32.768
100
kHz
SOSC crystal
ESR must be ≤
80K ohms (Note
2)
—
—
—
—
See parameter
OS10 for FOSC
value
Characteristics
OS15
OS20
TOSC
TOSC = 1/FOSC
OS30
TOSL,
TOSH
External Clock In (OSC1)
High or Low Time
0.375 x TOSC
—
0.675 x TOSC
ns
EC (Note 2)
OS31
TOSR,
TOSF
External Clock In (OSC1)
Rise or Fall Time
—
—
7.5
ns
EC (Note 2)
OS40
TOST
Oscillator Start-up Timer Period
(Only applies to HS, HSPLL,
and SOSC Clock Oscillator
modes)
—
1024
—
OS41
TFSCM
Primary Clock Fail Safe
Time-out Period
—
2
—
OS42
GM
External Oscillator
Transconductance
—
16
—
Note 1:
2:
3:
TOSC (Note 2)
ms
(Note 2)
mA/V VDD = 3.3V,
TA = +25°C, HS
(Note 2)
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are characterized but
are not tested.
This parameter is characterized, but not tested in manufacturing.
See parameter OS50 for PLL input frequency limitations.
2019-2020 Microchip Technology Inc.
DS60001570C-page 608
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-16: SYSTEM PLL TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
OS50
FIN
PLL Input Frequency Range
OS51
FSYS
System Frequency
OS52
TLOCK
PLL Start-up Time (Lock Time)
OS53
DCLK
CLKO Stability(2)
(Period Jitter or Cumulative)
OS54
FVCO
PLL VCO Frequency Range
OS54a
FPLL
OS54b
OS55a
Typ.
Max.
Units
Conditions
5
—
64
MHz
—
DC
—
120
MHz
—
—
—
100
µs
-0.25
—
+0.25
%
350
—
700
MHz FVco output frequency to
PLLODIV output
PLL Output Frequency Range
10
—
120
MHz PLLODIV output frequency
range
FPLLI
VCO Input Frequency Range
5
—
64
MHz PLLIDIV output frequency
range to FVCO input
FPB
Peripheral Bus Frequency
DC
—
120
MHz For PBCLKx, ‘x’ 6
DC
—
30
MHz For PBCLK6
OS55b
Note 1:
2:
Min.
—
Measured over 100 ms
period
These parameters are characterized, but not tested in manufacturing.
This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for
individual time-bases on communication clocks, use the following formula:
D CLK
EffectiveJitter = -------------------------------------------------------------PBCLKx
---------------------------------------------------------CommunicationClock
For example, if PBCLKx = 100 MHz and SPI bit rate = 50 MHz, the effective jitter is as follows:
D CLK
D CLK
EffectiveJitter = -------------- = -------------1.41
100
--------50
DS60001570C-page 609
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-17:
INTERNAL FRC ACCURACY
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
No.
Characteristics
Min.
Typ.
Max.
Units
Conditions
-4
—
+4
%
0°C TA +85°C
-5
—
+5
%
-40°C TA +125°C
Internal FRC Accuracy @ 8.00 MHz(1)
F20
FRC
Note 1:
Frequency calibrated at 25°C and 3.3V. The TUN bits can be used to compensate for temperature drift.
TABLE 36-18: INTERNAL LPRC ACCURACY
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
No.
Characteristics
Min.
Typ.
Max.
Units
-8
-25
Conditions
—
+8
%
0°C TA +85°C
—
+25
%
-40°C TA +125°C
Internal LPRC @ 32.768 kHz(1)
F21
LPRC
Note 1:
Change of LPRC frequency as VDD changes.
TABLE 36-19: INTERNAL BFRC ACCURACY
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param. No.
Characteristics(1)
Min.
Typ.
Max.
Units
Comments
BF1
BFRC
-20
-
20
%
-40°C ≤ TA ≤ +125°C
Note 1: These parameters are characterized but not tested.
2019-2020 Microchip Technology Inc.
DS60001570C-page 610
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-20:
COMPARATOR SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (Note 2)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
No.
Min.
Typ.
Characteristics(1)
Symbol
Max. Units
Comments
CM30
VIOFF
Input Offset Voltage
-15
—
+15
mV
—
CM31
VICM
Input Common Mode
Voltage
AVSS
—
AVDD
V
—
CM36a VHYST_01 Input Hysteresis Voltage
10
15
30
mV
HYSSEL (CMxCON) =
‘0b01 (Lowest)
CM36b VHYST_10 Input Hysteresis Voltage
15
30
45
mV
HYSSEL (CMxCON) =
‘0b10
CM36c VHYST_11 Input Hysteresis Voltage
25
45
65
mV
HYSSEL (CMxCON) =
‘0b11 (Highest)
CM37
TRESP
Large Signal Response
Time
—
—
50
ns
—
CM38
TSRESP
Small Signal Response
Time
—
—
70
ns
CM41
VIN
Input Voltage Range
AVSS
—
AVDD
V
—
CM43
TON
Comparator Enabled to
Output Valid
—
10
—
µs
Comparator module is configured
before setting the Comparator ON bit
CM44
TOFF
Disable to outputs disabled
—
100
—
ns
—
CM47
CMRR
Common Mode Rejection
39
Note 1:
VCM = VDD/2; 100 mV step
These parameters are characterized but not tested.
DS60001570C-page 611
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
DO31
DO32
Note: Refer to Figure 36-1 for load conditions.
TABLE 36-21: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
No.
DO31
Note 1:
2:
Symbol
TIOR
Characteristics(2)
Port Output Rise Time
I/O Pins:
4x Source Driver Pins RA0, RA4, RA11, RA12, RA14, RA15,
RB0-RB3, RB8, RB9
RC0, RC1, RC2, RC10, RC12, RC13
RD8, RD12-RD15
RE0, RE1, RE8, RE9
RF5-RF7, RF9, RF10, RF12, RF13
RG0, RG1, RG6-RG15
Min.
Typ.(1)
Max.
Units
—
—
9.5
ns
CLOAD = 50 pF
—
—
6
ns
CLOAD = 20 pF
8
ns
CLOAD = 50 pF
6
ns
CLOAD = 20 pF
Port Output Rise Time
I/O Pins:
—
—
8x Source Driver Pins Replace 8x Source Driver pins with:
RA1, RA7, RA8, RA10
RB4-RB7, RB10-RB15
RC6-RC9, RC11, RC15
—
—
RD1-RD6
RE12-RE15
RF0, RF1
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated.
This parameter is characterized, but not tested in manufacturing.
2019-2020 Microchip Technology Inc.
Conditions
DS60001570C-page 612
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-21: I/O TIMING REQUIREMENTS (CONTINUED)
AC CHARACTERISTICS
Param.
No.
DO32
Characteristics(2)
Symbol
TIOF
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Port Output Fall Time
I/O Pins:
4x Source Driver Pins RA0, RA4, RA11, RA12, RA14, RA15,
RB0-RB3, RB8, RB9
RC0, RC1, RC2, RC10, RC12, RC13
RD8, RD12-RD15
RE0, RE1, RE8, RE9
RF5-RF7, RF9, RF10, RF12, RF13
RG0, RG1, RG6-RG15
Min.
Typ.(1)
Max.
Units
—
—
9.5
ns
CLOAD = 50 pF
—
—
6
ns
CLOAD = 20 pF
8
ns
CLOAD = 50 pF
6
ns
CLOAD = 20 pF
—
—
ns
ns
Port Output Fall Time
I/O Pins:
—
—
8x Source Driver Pins RA1, RA7, RA8, RA10
RB4-RB7, RB10-RB15
RC6-RC9, RC11, RC15
RD1-RD6
—
—
RE12-RE15
RF0, RF1
DI35
TINP
INTx Pin High or Low Time
5
—
DI40
TRBP
CNx High or Low Time (input)
5
—
Note 1: Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated.
2: This parameter is characterized, but not tested in manufacturing.
DS60001570C-page 613
Conditions
—
—
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-4:
POWER-ON RESET TIMING CHARACTERISTICS
Internal Voltage Regulator Enabled
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
CPU Starts Fetching Code
SY00
(TPU)
(Note 1)
Internal Voltage Regulator Enabled
Clock Sources = (HS, HSPLL, and SOSC)
VDD
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
SY00
(TPU)
(Note 1)
Note 1:
2:
OS40
(TOST)
CPU Starts Fetching Code
The power-up period will be extended if the power-up sequence completes before the device exits from BOR
(VDD < VDDMIN).
Includes interval voltage regulator stabilization delay.
2019-2020 Microchip Technology Inc.
DS60001570C-page 614
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-5:
EXTERNAL RESET TIMING CHARACTERISTICS
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
MCLR
TMCLR
(SY20)
BOR
TBOR
(SY30)
(TSYSDLY)
SY02
Reset Sequence
CPU Starts Fetching Code
Clock Sources = (HS, HSPLL, and SOSC)
(TSYSDLY)
SY02
Reset Sequence
CPU Starts Fetching Code
TOST
(OS40)
TABLE 36-22: RESETS TIMING
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typ.(2)
Max.
Units
Conditions
SY00
TPU
Power-up Period
Internal Voltage Regulator Enabled
—
400
R
s
—
SY02
TSYSDLY System Delay Period:
Time Required to Reload Device
Configuration Fuses plus SYSCLK
Delay before First instruction is
Fetched.
—
s +
8 SYSCLK
cycles
—
—
—
SY20
TMCLR
MCLR Pulse Width (low)
2
—
—
s
—
SY30
TBOR
BOR Pulse Width (low)
—
1
—
s
—
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.
DS60001570C-page 615
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-6:
TIMER1-TIMER9 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRx
Note: Refer to Figure 36-1 for load conditions.
TABLE 36-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
No.
TA10
TA11
TA15
Symbol
TTXH
TTXL
TTXP
Characteristics(2)
TxCK
High Time
TxCK
Low Time
Typ. Max.
Units
Conditions
Synchronous, [(12.5 ns or 1 TPBCLK3)
with prescaler
/N] + 20 ns
—
—
ns
Must also meet
parameter TA15
(Note 3)
Asynchronous,
with prescaler
—
—
ns
—
Synchronous, [(12.5 ns or 1 TPBCLK3)
/N] + 20 ns
with prescaler
—
—
ns
Must also meet
parameter TA15
(Note 3)
Asynchronous,
with prescaler
10
—
—
ns
—
[(Greater of 20 ns or
2 TPBCLK3)/N] + 30 ns
—
—
ns
VDD > 2.7V
(Note 3)
[(Greater of 20 ns or
2 TPBCLK3)/N] + 50 ns
—
—
ns
VDD < 2.7V
(Note 3)
20
—
—
ns
VDD > 2.7V
50
—
—
ns
VDD < 2.7V
32
—
50
kHz
—
1
TPBCLK3
—
TxCK
Synchronous,
Input Period with prescaler
Asynchronous,
with prescaler
OS60
FT1
TA20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
Note 1:
2:
3:
Min.
SOSCO/T1CK Oscillator
Input Frequency Range
(oscillator enabled by setting
TCS bit (T1CON))
10
—
Timer1 is a Type A.
This parameter is characterized, but not tested in manufacturing.
N = Prescale Value (1, 8, 64, 256).
2019-2020 Microchip Technology Inc.
DS60001570C-page 616
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-24: TIMER2-TIMER9 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Max.
Units
Conditions
TB10
TTXH
TxCK
Synchronous, with
High Time prescaler
[(12.5 ns or 1 TPBCLK3)
/N] + 25 ns
—
ns
TB11
TTXL
TxCK
Synchronous, with
Low Time prescaler
[(12.5 ns or 1 TPBCLK3)
/N] + 25 ns
—
ns
TB15
TTXP
TxCK
Input
Period
[(Greater of [(25 ns or
2 TPBCLK3)/N] + 30 ns
[(Greater of [(25 ns or
2 TPBCLK3)/N] + 50 ns
—
—
ns
Must also
meet
parameter
TB15
Must also
meet
parameter
TB15
VDD > 2.7V
—
ns
VDD < 2.7V
Synchronous, with
prescaler
1
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer Increment
Note 1: These parameters are characterized, but not tested in manufacturing.
TB20
FIGURE 36-7:
TPBCLK3
N = prescale
value
(1, 2, 4, 8,
16, 32, 64,
256)
—
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 36-1 for load conditions.
TABLE 36-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
Symbol Characteristics(1)
No.
Min.
Max. Units
Conditions
IC10
TCCL
ICx Input Low
Time
((TPBCLKx/N) + 25 ns)
—
ns
IC11
TCCH
ICx Input High
Time
((TPBCLKx/N) + 25 ns)
—
ns
IC15
TCCP
ICx Input Period
((TPBCLKx/N) + 50 ns)
—
ns
Note 1:
These parameters are characterized, but not tested in manufacturing.
DS60001570C-page 617
Must also meet
parameter
IC15.
Must also meet
parameter
IC15.
—
x = 2 for IC1-IC9
x = 3 for IC10-IC16
N = prescale value
(1, 4, 16)
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-8:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM mode)
OC10
OC11
Note: Refer to Figure 36-1 for load conditions.
TABLE 36-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typ.(2)
Max.
Units
Conditions
OC10
TCCF
OCx Output Fall Time
—
—
—
ns
See parameter DO32
OC11
TCCR
OCx Output Rise Time
—
—
—
ns
See parameter DO31
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
FIGURE 36-9:
OCx/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCx
OCx is tri-stated
Note: Refer to Figure 36-1 for load conditions.
TABLE 36-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristics(1)
Min
Typ.(2)
Max
Units
Conditions
OC15
TFD
Fault Input to PWM I/O Change
—
—
50
ns
—
OC20
TFLT
Fault Input Pulse Width
50
—
—
ns
—
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2019-2020 Microchip Technology Inc.
DS60001570C-page 618
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-28:
OP AMP SPECIFICATIONS
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Standard Operating Conditions: 2.3V to 3.6V (Note 2)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.(1)
Max.
Units
Comments
AVSS
—
AVDD
V
—
—
45
—
dB
+5
mV
Non-Unity Gain
Mode
nA
—
dB
dB
dB
@ 10 kHz
@ 100 kHz
@ 1 MHz
OA1
VCMR
Common Mode Input
Voltage Range
OA2
CMRR
Common Mode
Rejection Ratio
OA3
VOFFSET Op amp Offset Voltage
-5
—
OA5
ILKG
Input leakage current
—
—
OA6
PSRR
Power Supply Rejection
Ratio
40
38
30
52
49
42
OA7
TDRIFT
Amplifier Input Offset
Drift
-15
—
+15
µV/ºC
With temperature
—
—
V
VOH
Amplifier Output
Voltage High
AVSS - 0.300
OA8
AVSS - 0.1
AVSS - 0.05
—
—
—
—
V
V
ISOURCE 10 mA
ISOURCE 500 μA
—
—
—
—
AVDD + 0.300
AVDD + 0.1
V
V
—
—
—
10
AVDD -+0.05
—
V
μs
—
100
—
ns
—
—
—
—
—
—
—
OA9
VOL
Amplifier Output
Voltage Low
Enable to Valid Output
Disable to Outputs
Disabled
See IIL in
Table 36-9
—
—
—
OA10
TON
OA11
TOFF
OA12
IOS
Input Offset Current
—
OA13
IB
Input Bias Current
—
OA14
SR
Slew Rate (Non-Lowpower mode)
40.0
—
—
OA14a SR
Slew Rate (Low-power
mode)
3.7
—
—
OA15
Gain Bandwidth
48.4
—
—
OA15A GBWLP
Gain Bandwidth Lowpower
7.97
—
—
OA16
AV
Gain
2
—
—
OA17
PM
Phase Margin
34
—
—
Note 1:
2:
GBW
See IIL in
Table 36-9
See IIL in
Table 36-9
VCM = AVDD/2
ISOURCE 200 μA
ISINK 10 mA
ISINK 500 μA
ISINK 200 μA
—
@ VOUT = 1.0 VPP,
VCM = AVDD/2, AVDD
= 3.3V
@ VOUT = 1.0 VPP,
V/μs VCM = AVDD/2, AVDD
= 3.3V
@ VCM = AVDD/2 and
MHz
AVDD > 2.7V, GAIN
>= 2
@ VCM = AVDD/2 and
MHz
AVDD > 2.7V, GAIN
>= 2
Minimum op amp
V/V stable gain in nonunity gain mode.
Degree
—
s
V/μs
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated.
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules: ADC, op amp/Comparator, and Comparator voltage reference, will have degraded performance. Refer to parameter BO10 in Table 36-5 for the minimum and maximum BOR values.
DS60001570C-page 619
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-29: UNITY GAIN OP AMP TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristics (2)
Min. Typ.(1) Max.
Units
Conditions
UG10
SR
Slew Rate
50
—
—
V/μs
UG20
PM
Phase Margin
65
—
—
Degree
From 0.5V to 2.5V
UG30
GM
Gain Margin
5.3
—
—
dB
UG40
GBW
Gain Bandwidth
29
—
—
MHz
UG50
VOFFSET
Opamp Offset Voltage
-8
—
8
mV
UG60
PSRR
Power Supply Rejection Ratio
—
59
—
dB
Specified at 0 Hz
UG70
PEAK
Peak Gain
—
—
1.1
dB
Gain in excess of 1 (@ 6 MHz)
—
Note 1: Data in "Typical" column is at 3.3V, +25°C unless otherwise stated.
2: All other specifications are identical to the regular op amp mode operation.
3: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules: ADC, op amp/Comparator, and Comparator voltage reference, will have degraded performance. Refer to parameter BO10 in Table 36-5 for the mini-mum
and maximum BOR values.
2019-2020 Microchip Technology Inc.
DS60001570C-page 620
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-10:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
SP31
SDIx
MSb In
LSb
SP30
Bit 14 - - - -1
LSb In
SP40 SP41
Note: Refer to Figure 36-1 for load conditions.
DS60001570C-page 621
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-30:
SPIx MASTER MODE (CKE = 0, SMP = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
No.
SP9a
Symbol
TSCK
Note 1:
2:
3:
Characteristics(1)
Min. Typ.(2) Max. Units
SCK1 Period (SPI1 only)
22.7
—
—
ns
—
35
—
ns
—
41
—
ns
—
47
—
ns
Conditions
(VDD 3.3V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 0, SRCON1x.y = 0.
Dedicated SCK1 and SCK2 on
RB7 and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 1, SRCON1x.y = 0.
Dedicated SCK1 and SCK2 on
RB7 and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 0, SRCON1x.y = 1.
Dedicated SCK1 and SCK2 on
RB7 and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 1, SRCON1x.y = 1.
Dedicated SCK1 and SCK2 on
RB7 and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
These parameters are characterized, but not tested in manufacturing.
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
Assumes 30 pF load on all SPIx pins.
2019-2020 Microchip Technology Inc.
DS60001570C-page 622
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-30:
SPIx MASTER MODE (CKE = 0, SMP = 1) TIMING REQUIREMENTS (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
No.
SP9b
Characteristics(1)
Symbol
TSCK
Min. Typ.(2) Max. Units
SCK2 Period (SPI2 only)
35.7
—
—
ns
—
64
—
ns
—
82
—
ns
—
SP10
SP11
SP20
SP21
SP30
SP31
SP35
SCKx Output Low Time
TSCK/2
SCKx Output High Time
TSCK/2
SCKx Output Fall Time
—
(Note 3)
TSCR
SCKx Output Rise Time
—
(Note 3)
SDOx Data Output Fall Time —
TDOF
(Note 3)
SDOx Data Output Rise Time —
TDOR
(Note 3)
—
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
TSCL
TSCH
TSCF
Conditions
(VDD 3.3V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 0, SRCON1x.y = 0.
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 1, SRCON1x.y = 0.
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 0, SRCON1x.y = 1.
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 1, SRCON1x.y = 1
97
—
ns
—
—
—
—
—
—
ns
ns
ns
See parameter DO32
—
—
ns
See parameter DO31
—
—
ns
See parameter DO32
—
—
ns
See parameter DO31
—
—
7
ns
ns
VDD > 3.0V
VDD < 3.0V
—
—
10
—
—
ns
—
TDIV2SCH, Setup Time of SDIx Data
5
TDIV2SCL Input to SCKx Edge
SP41 TSCH2DIL, Hold Time of SDIx Data Input 5
—
—
ns
—
TSCL2DIL to SCKx Edge
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
3: Assumes 30 pF load on all SPIx pins.
SP40
DS60001570C-page 623
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-11:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11
SCKX
(CKP = 1)
SP10
SP21
SP20
SP20
SP21
SP35
Bit 14 - - - - - -1
MSb
SDOX
LSb
SP30,SP31
SDIX
MSb In
SP40
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 36-1 for load conditions.
2019-2020 Microchip Technology Inc.
DS60001570C-page 624
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-31: SPIx MODULE MASTER MODE (CKE = 1, SMP = 1) TIMING
REQUIREMENTS
AC CHARACTERISTICS
Param.
No.
SP9a
Characteristics(1)
Symbol
TSCK
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
3:
Units
SCK1 Period
22.7
Note 1:
2:
Typ.(2) Max.
—
—
ns
Conditions
(VDD 3.3V and the SMP bit (SPIxCON = 1), I/O Pin Slew Rate
Control (x = A-F, y = port pin),
SRCON0x.y = 0, SRCON1x.y = 0.
Dedicated SCK1 and SCK2 on RB7
and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
(VDD 3.0V and the SMP bit (SPIxCON = 1), I/O Pin Slew Rate
Control (x = A-F, y = port pin),
SRCON0x.y = 1, SRCON1x.y = 0.
—
27
—
ns
Dedicated SCK1 and SCK2 on RB7
and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
(VDD 3.0V and the SMP bit (SPIxCON = 1), I/O Pin Slew Rate
Control (x = A-F, y = port pin),
SRCON0x.y = 0, SRCON1x.y = 1.
—
33
—
ns
Dedicated SCK1 and SCK2 on RB7
and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
(VDD 3.0V and the SMP bit (SPIxCON = 1), I/O Pin Slew Rate
Control (x = A-F, y = port pin),
SRCON0x.y = 1, SRCON1x.y = 1.
—
39
—
ns
Dedicated SCK1 and SCK2 on RB7
and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
These parameters are characterized, but not tested in manufacturing.
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
Assumes 10 pF load on all SPIx pins.
DS60001570C-page 625
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-31: SPIx MODULE MASTER MODE (CKE = 1, SMP = 1) TIMING
REQUIREMENTS (CONTINUED)
AC CHARACTERISTICS
Param.
No.
SP9b
Symbol
TSCK
Characteristics(1)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
TSCL
TSCH
TSCF
SP21
TSCR
SP30
TDOF
Note 1:
2:
3:
Conditions
ns
(VDD 3.3V and the SMP bit (SPIxCON = 1), I/O Pin Slew Rate
Control (x = A-F, y = port pin),
SRCON0x.y = 0, SRCON1x.y = 0.
—
—
All other remappable SPI pins not
contained in conditions for
parameter SP9a.
(VDD 3.0V and the SMP bit (SPIxCON = 1), I/O Pin Slew Rate
Control (x = A-F, y = port pin),
SRCON0x.y = 1, SRCON1x.y = 0.
All other remappable SPI pins not
contained in conditions for
parameter SP9a.
(VDD 3.0V and the SMP bit (SPIxCON = 1), I/O Pin Slew Rate
Control (x = A-F, y = port pin),
SRCON0x.y = 0, SRCON1x.y = 1.
All other remappable SPI pins not
contained in conditions for
parameter SP9a.
(VDD 3.0V and the SMP bit (SPIxCON = 1), I/O Pin Slew Rate
Control (x = A-F, y = port pin),
SRCON0x.y = 1, SRCON1x.y = 1.
All other remappable SPI pins not
contained in conditions for
parameter SP9a.
—
41
—
ns
—
59
—
ns
—
74
—
ns
—
—
—
—
—
—
ns
ns
ns
—
—
See parameter DO32
—
—
ns
See parameter DO31
—
—
ns
See parameter DO32
SCKx Output Low Time TSCK/2
SCKx Output High Time TSCK/2
SCKx Output Fall Time
—
(Note 3)
SCKx Output Rise Time —
(Note 3)
SDOx Data Output Fall
—
Time (Note 3)
SCKx Period
20
Dedicated SCK1 and SCK2 on RB7
and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
40
—
—
ns All other remappable SPI pins not
contained in conditions for parameter SP9a.
These parameters are characterized, but not tested in manufacturing.
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
Assumes 10 pF load on all SPIx pins.
SP30a TSCK
SP30b
Units
SCK2 Period
35.7
SP10
SP11
SP20
Typ.(2) Max.
2019-2020 Microchip Technology Inc.
—
—
ns
DS60001570C-page 626
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-31: SPIx MODULE MASTER MODE (CKE = 1, SMP = 1) TIMING
REQUIREMENTS (CONTINUED)
AC CHARACTERISTICS
Param.
No.
SP31
SP35
SP36
Symbol
Characteristics(1)
TDOR
SDOx Data Output Rise
Time (Note 3)
TSCH2DOV, SDOx Data Output Valid
TSCL2DOV after SCKx Edge
TDOV2SC, SDOx Data Output
TDOV2SCL Setup to First SCKx
Edge
TDIV2SCH, Setup Time of SDIx Data
TDIV2SCL Input to SCKx Edge
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.(2) Max.
Units
Conditions
—
—
—
ns
See parameter DO31
—
—
—
7
10
ns
VDD > 2.7V
VDD < 2.7V
7
—
—
ns
—
7
—
—
ns VDD > 2.7V
10
VDD < 2.7V
7
—
—
ns VDD > 2.7V
SP41
TSCH2DIL, Hold Time of SDIx Data
TSCL2DIL Input to SCKx Edge
10
—
—
ns VDD < 2.7V
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
3: Assumes 10 pF load on all SPIx pins.
SP40
DS60001570C-page 627
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-12:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
Bit 14 - - - - - -1
LSb
SP51
SP30,SP31
SDIX
MSb In
SP40
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 36-1 for load conditions.
2019-2020 Microchip Technology Inc.
DS60001570C-page 628
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-32: SPIx MODULE SLAVE MODE (CKE = 0, SMP = 1) TIMING
REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
No.
SP9a
TSCK
Note 1:
2:
3:
Characteristics(1)
Symbol
Min. Typ.(2) Max.
Units
SCKx Period
20
—
—
ns
27
—
—
ns
33
—
—
ns
39
—
—
ns
Conditions
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 0, SRCON1x.y = 0
Dedicated SCK1 and SCK2 on
RB7 and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 1, SRCON1x.y = 0
Dedicated SCK1 and SCK2 on
RB7 and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 0, SRCON1x.y = 1
Dedicated SCK1 and SCK2 on
RB7 and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 1, SRCON1x.y = 1
Dedicated SCK1 and SCK2 on
RB7 and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
These parameters are characterized, but not tested in manufacturing.
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
Assumes 10 pF load on all SPIx pins.
DS60001570C-page 629
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-32: SPIx MODULE SLAVE MODE (CKE = 0, SMP = 1) TIMING
REQUIREMENTS (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
No.
SP9b
Symbol
TSCK
Characteristics(1)
Min. Typ.(2) Max.
SP31
SP35
Conditions
ns
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 0, SRCON1x.y = 0
SCKx Period
22
SP70
SP71
SP72
SP73
SP30
Units
TSCL
TSCH
TSCF
TSCR
TDOF
SCKx Input Low Time
SCKx Input High Time
SCKx Input Fall Time
SCKx Input Rise Time
SDOx Data Output Fall
Time
(Note 3)
SDOx Data Output Rise
TDOR
Time (Note 3)
TSCH2DOV, SDOx Data Output Valid
TSCL2DOV after SCKx Edge
—
—
41
—
—
ns
59
—
—
ns
74
—
—
ns
TSCK/2
TSCK/2
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
All other remappable SPI pins not
contained in conditions for
parameter SP9a.
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 1, SRCON1x.y = 0
All other remappable SPI pins not
contained in conditions for
parameter SP9a.
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 0, SRCON1x.y = 1
All other remappable SPI pins not
contained in conditions for
parameter SP9a.
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 1, SRCON1x.y = 1
All other remappable SPI pins not
contained in conditions for
parameter SP9a.
—
—
See parameter DO32
See parameter DO31
See parameter DO32
—
—
—
ns
See parameter DO31
—
—
5
—
—
—
7
10
—
ns
ns
ns
VDD > 2.7V
VDD < 2.7V
—
TDIV2SCH, Setup Time of SDIx Data
TDIV2SCL Input to SCKx Edge
SP41 TSCH2DIL, Hold Time of SDIx Data
5
—
—
ns
—
TSCL2DIL Input to SCKx Edge
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
3: Assumes 10 pF load on all SPIx pins.
SP40
2019-2020 Microchip Technology Inc.
DS60001570C-page 630
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-32: SPIx MODULE SLAVE MODE (CKE = 0, SMP = 1) TIMING
REQUIREMENTS (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
No.
SP50
SP51
Symbol
Characteristics(1)
TSSL2SCH, SSx to SCKx or SCKx
TSSL2SCL Input
TSSH2DOZ SSx to SDOx Output
High-Impedance
Min. Typ.(2) Max.
Units
Conditions
88
—
—
ns
—
2.5
—
12
ns
—
SP52
TSCH2SSH SSx after SCKx Edge
10
—
—
ns
—
TSCL2SSH
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
3: Assumes 10 pF load on all SPIx pins.
DS60001570C-page 631
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-13:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30,SP31
SDIx
SDI
MSb In
SP40
Bit 14 - - - -1
SP51
LSb In
SP41
Note: Refer to Figure 36-1 for load conditions.
2019-2020 Microchip Technology Inc.
DS60001570C-page 632
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-33: SPIx MODULE SLAVE MODE (CKE = 1, SMP = 1) TIMING
REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
No.
SP9a
Characteristics(1)
Symbol
TSCK
Min. Typ.(2) Max.
27
33
39
3:
Conditions
ns
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 0, SRCON1x.y = 0.
Dedicated SCK1 and SCK2 on RB7
and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
ns
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 1, SRCON1x.y = 0.
Dedicated SCK1 and SCK2 on RB7
and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
ns
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 0, SRCON1x.y = 1.
Dedicated SCK1 and SCK2 on RB7
and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
ns
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 1, SRCON1x.y = 1.
Dedicated SCK1 and SCK2 on RB7
and RB6, respectively or PPS
remappable SPI onto pins RB5,
RA1, and RB15.
SCKx Period
20
Note 1:
2:
Units
—
—
—
—
—
—
—
—
These parameters are characterized, but not tested in manufacturing.
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
Assumes 10 pF load on all SPIx pins.
DS60001570C-page 633
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-33: SPIx MODULE SLAVE MODE (CKE = 1, SMP = 1) TIMING
REQUIREMENTS (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
No.
SP9b
Symbol
TSCK
Characteristics(1)
Min. Typ.(2) Max.
Units
Conditions
ns
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 0, SRCON1x.y = 0.
All other remappable SPI pins not
contained in conditions for
parameter SP9a.
ns
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 1, SRCON1x.y = 0.
All other remappable SPI pins not
contained in conditions for
parameter SP9a.
ns
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 0, SRCON1x.y = 1.
All other remappable SPI pins not
contained in conditions for
parameter SP9a.
SCKx Period
22
41
59
—
—
—
—
—
—
74
—
—
ns
(VDD 3.0V and the SMP bit
(SPIxCON = 1), I/O Pin Slew
Rate Control (x = A-F, y = port pin),
SRCON0x.y = 1, SRCON1x.y = 1.
All other remappable SPI pins not
contained in conditions for
parameter SP9a.
SP70
TSCL
SCKx Input Low Time
TSCK/2
—
—
ns
—
SP71
TSCH
SCKx Input High Time
TSCK/2
—
—
ns
—
SP72
TSCF
SCKx Input Fall Time
—
—
10
ns
—
SP73
TSCR
SCKx Input Rise Time
—
—
10
ns
—
SP30
TDOF
SDOx Data Output Fall
Time (Note 3)
—
—
—
ns
See parameter DO32
SP31
TDOR
SDOx Data Output Rise
Time (Note 3)
—
—
—
ns
See parameter DO31
SP35
TSCH2DOV, SDOx Data Output Valid
TSCL2DOV after SCKx Edge
—
—
10
ns
VDD > 2.7V
—
—
15
ns
VDD < 2.7V
SP40
TDIV2SCH, Setup Time of SDIx Data
TDIV2SCL Input to SCKx Edge
0
—
—
ns
—
SP41
TSCH2DIL, Hold Time of SDIx Data
TSCL2DIL Input to SCKx Edge
7
—
—
ns
—
Note 1:
2:
3:
These parameters are characterized, but not tested in manufacturing.
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
Assumes 10 pF load on all SPIx pins.
2019-2020 Microchip Technology Inc.
DS60001570C-page 634
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-33: SPIx MODULE SLAVE MODE (CKE = 1, SMP = 1) TIMING
REQUIREMENTS (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min. Typ.(2) Max.
Units
Conditions
SP50
TSSL2SCH, SSx to SCKx or SCKx
TSSL2SCL Input
88
—
—
ns
—
SP51
TSSH2DOZ SSx to SDOX Output
High-Impedance (Note 3)
2.5
—
12
ns
—
SP52
TSCH2SSH SSx after SCKx Edge
TSCL2SSH
10
—
—
ns
—
SP60
TSSL2DOV SDOx Data Output Valid
after
SSx Edge
—
—
12.5
ns
—
Note 1:
2:
3:
These parameters are characterized, but not tested in manufacturing.
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
Assumes 10 pF load on all SPIx pins.
DS60001570C-page 635
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-14:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 36-1 for load conditions.
FIGURE 36-15:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM33
IM25
SDAx
In
IM45
IM40
IM40
SDAx
Out
Note: Refer to Figure 36-1 for load conditions.
TABLE 36-34: I2CX BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature 0°C TA +70°C for Commercial
-40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
IM10
IM11
Note 1:
2:
3:
Min.(1)
Max.
Units
Conditions
TLO:SCL Clock Low Time 100 kHz mode
TPB * (BRG + 2)
—
s
—
400 kHz mode
TPB * (BRG + 2)
—
s
—
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
s
—
Clock High Time 100 kHz mode
TPB * (BRG + 2)
—
s
—
400 kHz mode
TPB * (BRG + 2)
—
s
—
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
s
—
THI:SCL
Characteristics
BRG is the value of the I2C Baud Rate Generator.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
The typical value for this parameter is 104 ns.
2019-2020 Microchip Technology Inc.
DS60001570C-page 636
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-34: I2CX BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature 0°C TA +70°C for Commercial
-40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
IM20
TF:SCL
Characteristics
Min.(1)
Max.
Units
SDAx and SCLx 100 kHz mode
Fall Time
400 kHz mode
—
300
ns
20 + 0.1 CB
300
ns
—
100
ns
1 MHz mode
(Note 2)
IM21
IM25
IM26
IM30
IM31
IM33
IM34
TR:SCL
SDAx and SCLx 100 kHz mode
Rise Time
400 kHz mode
TSU:DAT Data Input
Setup Time
THD:DAT Data Input
Hold Time
TSU:STA Start Condition
Setup Time
THD:STA Start Condition
Hold Time
TSU:STO Stop Condition
Setup Time
THD:STO Stop Condition
Hold Time
IM40
Note 1:
2:
3:
TAA:SCL Output Valid
from Clock
Conditions
CB is specified to be
from 10 to 200 pF
—
1000
ns
20 + 0.1 CB
300
ns
CB is specified to be
from 10 to 200 pF
1 MHz mode
(Note 2)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode
(Note 2)
100
—
ns
100 kHz mode
0
—
s
400 kHz mode
0
0.9
s
1 MHz mode
(Note 2)
0
0.3
s
100 kHz mode
TPB * (BRG + 2)
—
s
400 kHz mode
TPB * (BRG + 2)
—
s
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
s
100 kHz mode
TPB * (BRG + 2)
—
s
400 kHz mode
TPB * (BRG + 2)
—
s
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
s
100 kHz mode
TPB * (BRG + 2)
—
s
400 kHz mode
TPB * (BRG + 2)
—
s
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
s
100 kHz mode
TPB * (BRG + 2)
—
ns
400 kHz mode
TPB * (BRG + 2)
—
ns
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
ns
100 kHz mode
—
3500
ns
—
400 kHz mode
—
1000
ns
—
1 MHz mode
(Note 2)
—
350
ns
—
—
—
Only relevant for
Repeated Start
condition
After this period, the
first clock pulse is
generated
—
—
BRG is the value of the I2C Baud Rate Generator.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
The typical value for this parameter is 104 ns.
DS60001570C-page 637
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-34: I2CX BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature 0°C TA +70°C for Commercial
-40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
IM45
Min.(1)
Max.
Units
Conditions
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode
(Note 2)
0.5
—
s
The amount of time the
bus must be free
before a new
transmission can start
Characteristics
TBF:SDA Bus Free Time
IM50
CB
Bus Capacitive Loading
—
200
pF
—
IM51
TPGD
Pulse Gobbler Delay
52
312
ns
See Note 3
Note 1:
2:
3:
BRG is the value of the I2C Baud Rate Generator.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
The typical value for this parameter is 104 ns.
2019-2020 Microchip Technology Inc.
DS60001570C-page 638
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-16:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 36-1 for load conditions.
FIGURE 36-17:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS33
IS25
SDAx
In
IS45
IS40
IS40
SDAx
Out
Note: Refer to Figure 36-1 for load conditions.
TABLE 36-35: I2CX BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature 0°C TA +70°C for Commercial
-40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
No.
IS10
IS11
Note 1:
Symbol
TLO:SCL
THI:SCL
Characteristics
Clock Low Time
Clock High Time
Min.
Max.
Units
Conditions
100 kHz mode
4.7
—
s
PBCLK must operate at a
minimum of 800 kHz
400 kHz mode
1.3
—
s
PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode
(Note 1)
0.5
—
s
100 kHz mode
4.0
—
s
PBCLK must operate at a
minimum of 800 kHz
400 kHz mode
0.6
—
s
PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode
(Note 1)
0.5
—
s
—
—
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS60001570C-page 639
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-35: I2CX BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature 0°C TA +70°C for Commercial
-40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
No.
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
Note 1:
Symbol
TF:SCL
TR:SCL
TSU:DAT
THD:DAT
TSU:STA
THD:STA
TSU:STO
THD:STO
TAA:SCL
TBF:SDA
CB
Characteristics
SDAx and SCLx
Fall Time
SDAx and SCLx
Rise Time
Data Input
Setup Time
Data Input
Hold Time
Start Condition
Setup Time
Start Condition
Hold Time
Stop Condition
Setup Time
Stop Condition
Hold Time
Min.
Max.
Units
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode
(Note 1)
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode
(Note 1)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode
(Note 1)
100
—
ns
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
1 MHz mode
(Note 1)
0
0.3
s
100 kHz mode
4700
—
ns
400 kHz mode
600
—
ns
1 MHz mode
(Note 1)
250
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode
(Note 1)
250
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode
(Note 1)
600
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode
(Note 1)
250
0
3500
ns
0
1000
ns
1 MHz mode
(Note 1)
0
350
ns
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode
(Note 1)
0.5
—
s
—
400
pF
Bus Capacitive Loading
CB is specified to be from
10 to 200 pF
CB is specified to be from
10 to 200 pF
—
—
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
—
—
ns
Output Valid from 100 kHz mode
Clock
400 kHz mode
Bus Free Time
Conditions
—
The amount of time the bus
must be free before a new
transmission can start
—
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2019-2020 Microchip Technology Inc.
DS60001570C-page 640
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-18:
QEI MODULE EXTERNAL CLOCK TIMING CHARACTERISTICS
QEB
TQ11
TQ10
TQ15
TQ20
POSCNT
TABLE 36-36: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
TQ10
TQ11
TQ15
Symbol
TtQH
TtQL
TtQP
TQ20
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
TQCK High Time Synchronous,
with prescaler
[(12.5 or
0.5 TCY) / N]
+ 25
—
—
ns
Must also meet
parameter TQ15.
TQCK Low Time
TQCP Input
Period
Synchronous,
with prescaler
Synchronous,
with prescaler
[(12.5 or
0.5 TCY) / N]
+ 25
[(25 or TCY)
/ N] + 50
—
—
TCKEXTMRL Delay from External TxCK Clock
—
1
Edge to Timer Increment
Note 1: These parameters are characterized but not tested in manufacturing.
2: N = Index Channel Digital Filter Clock Divide Select bits.
DS60001570C-page 641
—
ns
—
ns
TCY
—
N = 1, 2, 4, 16,
32, 64, 128 and
256 (Note 2)
Must also meet
parameter TQ15.
N = 1, 2, 4, 16,
32, 64, 128 and
256 (Note 2)
N = 1, 2, 4, 16,
32, 64, 128 and
256 (Note 2)
—
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-19:
QEA/QEB INPUT CHARACTERISTICS
TQ36
QEA
(input)
TQ30
TQ31
TQ35
QEB
(input)
TQ41
TQ40
TQ30
TQ31
TQ35
QEB
Internal
TABLE 36-37: QUADRATURE DECODER TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
TQ30
Symbol
TQUL
TQ31
TQ35
TQ36
TQ40
Characteristic(1)
Typ.(2)
Max.
Units
Conditions
Quadrature Input Low Time
6 TCY
—
ns
—
Quadrature Input High Time
6 TCY
—
ns
—
Quadrature Input Period
12 TCY
—
ns
—
Quadrature Phase Period
3 TCY
—
ns
—
Filter Time to Recognize Low,
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
with Digital Filter
128 and 256 (Note 3)
TQUFH
Filter Time to Recognize High,
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
with Digital Filter
128 and 256 (Note 3)
These parameters are characterized but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
N = Index Channel Digital Filter Clock Divide Select bits.
TQUH
TQUIN
TQUP
TQUFL
TQ41
Note 1:
2:
3:
2019-2020 Microchip Technology Inc.
DS60001570C-page 642
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-20:
CiTx Pin
(output)
CANFDx MODULE I/O TIMING CHARACTERISTICS
New Value
Old Value
CA10 CA11
CiRx Pin
(input)
CA20
TABLE 36-38: CANFDx MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
CA10
TioF
Port Output Fall Time
—
—
—
ns
See parameter DO32
CA11
TioR
Port Output Rise Time
—
—
—
ns
See parameter DO31
CA20
Tcwf
Pulse Width to Trigger
CAN Wake-up Filter
700
—
—
ns
Note 1:
2:
3:
4:
—
These parameters are characterized but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
CAN module wake from sleep could take up to 300us worst case. Multiple CAN messages could therefore
be missed depending on the USER CAN baud rate.
Recommended CAN-FD clock frequency is 20MHz/40MHz/80MHz. Implementing following steps to set
Module Clock frequency of 40MHz while maintaining CPU clock frequency of 120MHz:
• Select module clock source as REFCLK4 by configuring CLKSEL0 bit (CFDxCON) = 1
• Select SYSCLK as the input clock fro REFCLK4 by configure ROSEL bits (REFO4CON) = 0
• Set REF4CLK prescaler to 3 by configuring RODIV bits (REFO4CON) = 1 and ROTRIM bits
(REFO4TRIM = 256.
DS60001570C-page 643
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-39: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param.
Symbol
No.
Device Supply
AD01 AVDD
AD02 AVSS
Reference Inputs
AD05 VREFH
AD06 VREFL
AD07 VREF
AD08
IREF
Characteristics
Module VDD Supply
Module VSS Supply
Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Greater of
VDD – 0.3
or 2.3
VSS
—
—
Lesser of
VDD + 0.3
or 3.6
VSS + 0.3
—
—
—
AVDD
VREFH – 1.8
AVDD
V
V
V
(Note 1)
(Note 1)
(Note 2)
102
—
µA
ADC is operating or is in
Stand-by.
1.255
V
VREFH
VREFL
V
V
—
—
VREFH
V
—
Reference Voltage High VREFL + 1.8
Reference Voltage Low
AVSS
1.8
Absolute Reference
Voltage (VREFH – VREFL)
Current Drain
—
Bandgap Reference
1.145
1.2
IVREF
Analog Input
AD12 VINH-VINL Full-Scale Input Span
VREFL
—
Absolute VINL Input
AVSS
—
AD13 VINL
Voltage
AD14 VINH
Absolute VINH Input
AVSS
—
Voltage
ADC Accuracy – Measurements with External VREF+/VREFAD20c Nr
Resolution
6
—
AD21c INL
Integral Nonlinearity
AD22c DNL
12
-3.5
±1.5
+3.5
Differential Nonlinearity
-1
1.2
3
AD23c GERR
Gain Error
-8
1
8
AD24c EOFF
Offset Error
-5
-0.5
5
AD25c
—
Monotonicity
—
—
—
Dynamic Performance
—
67
—
AD31b SINAD
Signal to Noise and
Distortion
AD34b ENOB
Effective Number of bits
—
10.8
—
Note 1: These parameters are not characterized or tested in manufacturing.
2: These parameters are characterized, but not tested in manufacturing.
3: Characterized with a 1 kHz sine wave.
4: Tested on single ADC core, operating in Single-ended mode.
2019-2020 Microchip Technology Inc.
Units
Conditions
V
—
V
—
bits Selectable 6, 8, 10, 12
Resolution Ranges
LSb AVSS = VREFL = 0V, AVDD =
VREFH = 3.3V (Note 4)
LSb AVSS = VREFL = 0V, AVDD =
VREFH = 3.3V (Note 4)
LSb AVSS = VREFL = 0V, AVDD =
VREFH = 3.3V, Gain error
includes offset error.
(Note 4)
LSb AVSS = 0V,
AVDD = 3.3V (Note 4)
— Guaranteed (Note 2)
dB
Single-ended (Notes 2,3)
bits (Notes 2,3)
DS60001570C-page 644
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-40: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS
AC
CHARACTERISTICS(2)
Param.
Symbol
No.
Characteristics
Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min. Typ.(1) Max.
Units
Conditions
—
Clock Parameters
AD50
TAD
ADC Clock Period 16.667
—
6250
ns
Sample Rate for
ADC0-ADC5
(Class 1 Inputs)
—
—
—
—
—
—
—
—
3.75
4.284
4.992
6
Msps
Msps
Msps
Msps
12-bit resolution Source Impedance 200
10-bit resolution Source Impedance 200
8-bit resolution Source Impedance 200
6-bit resolution Source Impedance 200
Sample Rate for
ADC7
(Class 2 and Class
3 Inputs)
—
—
—
—
—
—
—
—
3.53
4.00
4.615
5.45
Msps
Msps
Msps
Msps
12-bit resolution Source Impedance 200
10-bit resolution Source Impedance 200
8-bit resolution Source Impedance 200
6-bit resolution Source Impedance 200
TAD
Source Impedance 200, Max ADC clock
Source Impedance 500, Max ADC clock
Source Impedance 1 K, Max ADC clock
Source Impedance 5 K, Max ADC clock
Throughput Rate
AD51
FTP
Timing Parameters
AD60
TSAMP
Sample Time for
ADC0-ADC5
(Class 1 Inputs)
3
4
5
13
Sample Time for
ADC7
(Class 2 and Class
3 Inputs)
4
5
6
14
AD65
Note 1:
2:
TCONV
TWAKE
Conversion Time
(after sample time is
complete)
Wake-up time from
Low-Power Mode
—
—
—
TAD
Source Impedance 200, Max ADC clock
Source Impedance 500, Max ADC clock
Source Impedance 1 K, Max ADC clock
Source Impedance 5 K, Max ADC clock
—
—
TAD
CVDEN (ADCCON1) = 1
—
—
—
—
—
—
—
—
13
11
9
7
TAD
12-bit resolution
10-bit resolution
8-bit resolution
6-bit resolution
—
500
—
TAD
—
20
—
µs
Sample Time for
See
ADC7
Table
(Class 2 and Class
36-41
3 Inputs)
AD62
—
Lesser of 500 TAD or 20 µs
These parameters are characterized, but not tested in manufacturing.
The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is guaranteed, but not characterized.
DS60001570C-page 645
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-41: ADC SAMPLE TIMES WITH CVD ENABLED
(2)
AC CHARACTERISTICS
Param.
Symbol
No.
AD60a TSAMP
Characteristics
Sample Time for
ADC7 (Class 2 and
Class 3 Inputs) with
the CVDEN bit
(ADCCON1) = 1
Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
8
9
11
12
14
16
17
10
12
14
16
18
19
21
13
16
18
21
23
26
28
41
48
56
63
70
78
85
Note 1:
2:
Typ.(1) Max.
—
—
—
—
—
—
—
—
Units
Conditions
TAD
Source Impedance 200
CVDCPL (ADCCON2) = 001
CVDCPL (ADCCON2) = 010
CVDCPL (ADCCON2) = 011
CVDCPL (ADCCON2) = 100
CVDCPL (ADCCON2) = 101
CVDCPL (ADCCON2) = 110
CVDCPL (ADCCON2) = 111
TAD
Source Impedance 500
CVDCPL (ADCCON2) = 001
CVDCPL (ADCCON2) = 010
CVDCPL (ADCCON2) = 011
CVDCPL (ADCCON2) = 100
CVDCPL (ADCCON2) = 101
CVDCPL (ADCCON2) = 110
CVDCPL (ADCCON2) = 111
TAD
Source Impedance 1 K
CVDCPL (ADCCON2) = 001
CVDCPL (ADCCON2) = 010
CVDCPL (ADCCON2) = 011
CVDCPL (ADCCON2) = 100
CVDCPL (ADCCON2) = 101
CVDCPL (ADCCON2) = 110
CVDCPL (ADCCON2) = 111
TAD
Source Impedance 5 K
CVDCPL (ADCCON2) = 001
CVDCPL (ADCCON2) = 010
CVDCPL (ADCCON2) = 011
CVDCPL (ADCCON2) = 100
CVDCPL (ADCCON2) = 101
CVDCPL (ADCCON2) = 110
CVDCPL (ADCCON2) = 111
These parameters are characterized, but not tested in manufacturing.
The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is guaranteed, but not characterized.
2019-2020 Microchip Technology Inc.
DS60001570C-page 646
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-42: CONTROL DAC (CDAC) SPECIFICATIONS
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
0.1 *
CDACVREF
—
0.9 *
CDACVREF
V
Conditions
CDAC
CD10
VOUT
CDAC Output Voltage
Range for Guaranteed
Settling Time
Specifications
CD11
N
CDAC Resolution
12
—
—
Bits
Guaranteed Monotonic by
architecture
CD12
INL
CDAC Integral
Nonlinearity
-4
1.03
+4
LSB
Guaranteed Monotonic by
architecture with CDACVREF
= AVDD = 3.3V
CD13
DNL
CDAC Differential
Nonlinearity
-1
-0.2
+2
LSB
Guaranteed Monotonic by
architecture with CDACVREF
= AVDD = 3.3V
CD14
OERR
CDAC Offset Error
-13
—
13
mV
CDACVREF = AVDD = 3.3V
CD15
GERR
CDAC Gain Error
-1
-0.088
+1
CD16
CDACVREF CDAC VREF Input
Range
0.5
—
AVDD
V
CD17
TON
CDAC Module Turn On
Time
—
1.0
2
µs
From write of DACON bit
CD18
TOFF
CDAC Module Turn Off
Time
—
1.0
2
µs
From write of DACON bit
CD19
TST
Settling Time
—
3
6
µs
Output is within ±4 LSb of
desired output step voltage
with a 10% to 90% step or
90% to 10% step. With load
capacitance of 30 pF.
PBCLK2 > 15 MHz
CD20
FS
Sampling Frequency
—
—
1
Msps
Maximum frequency for a
correct CDAC output change
for small variations of input
codes (from code to code
plus 1 LSb).
CD21
CLOAD
Output Load
Capacitance
---
—
30
pF
User application loads
DC22
IOUT
Output Current Drive
Strength
—
—
1
mA
Sink and source
DS60001570C-page 647
@ ILOAD = IOUT (max)
% of FS CDACVREF = AVDD = 3.3V
—
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-43: CTMU CURRENT SOURCE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V (Note 1)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
CTMU CURRENT SOURCE
CTMU0
RES
Resolution
-2
—
+2
ºC
3.3V @ -40ºC to 125ºC
CTMUI1
IOUT1
Base Range(1)
—
0.55
—
µA
CTMUCON = 01
—
5.5
—
µA
CTMUCON = 10
—
55
—
µA
CTMUCON = 11
—
550
—
µA
CTMUCON = 00
—
0.598
—
V
TA = +25ºC,
CTMUCON = 01
—
0.658
—
V
TA = +25ºC,
CTMUCON = 10
—
0.721
—
V
TA = +25ºC,
CTMUCON = 11
—
-1.74
—
mV/ºC CTMUCON = 01
—
-1.58
—
mV/ºC CTMUCON = 10
—
-1.42
—
mV/ºC CTMUCON = 11
Range(1)
CTMUI2
IOUT2
10x
CTMUI3
IOUT3
100x Range(1)
CTMUI4
IOUT4
CTMUFV1 VF
CTMUFV2 VFVR
Note 1:
2:
1000x
Range(1)
Temperature Diode Forward
Voltage(1,2)
Temperature Diode Rate of
Change(1,2)
Nominal value at center point of current trim range (CTMUCON = 000000).
Parameters are characterized but not tested in manufacturing. Measurements taken with the following
conditions:
• VREF+ = AVDD = 3.3V
• ADC module configured for conversion speed of 500 ksps
• All PMD bits are cleared (PMDx = 0)
• Executing a while(1) statement
• Device operating from the FRC with no PLL
2019-2020 Microchip Technology Inc.
DS60001570C-page 648
PIC32MK GPG/MCJ with CAN FD Family
TABLE 36-44: UART TIMING CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature 0°C TA +70°C for Commercial
-40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
UT10
FB
Characteristics(1)
Min.
Typ.
Max.
Baud Rate BRGH = 0
—
—
7.5
Mbps Baud rate = (FPBy / (16 * (UxBRG + 1))
where:
‘x’ = 1-6
‘y’ = FPBCLK2 for UART1 and UART2
‘y’ = FPBLKC3 for UART3-UART6
BRGH = 1
7.5
—
30
Mbps Baud rate = (FPBy / (4 * (UxBRG + 1))
where:
‘x’ = 1-6
‘y’ = FPBCLK2 for UART1 and UART2
‘y’ = FPBLKC3 for UART3-UART6
UT20
Note 1:
Units
Conditions
These parameters are characterized, but not tested in manufacturing.
FIGURE 36-21:
MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS
MP30
Fault Input
(active-low)
MP20
PWMx
TABLE 36-45: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature 0°C TA +70°C for Commercial
-40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
No.
MP10
MP11
Symbol
TFPWM
TRPWM
TFD
Characteristic(1)
Min.
Typ.
Max.
PWM Output Fall Time
—
—
—
PWM Output Rise Time
—
—
—
Fault Input to PWM
—
—
50
MP20
I/O Change
MP30
TFH
Fault Input Pulse Width
50
—
—
Note 1:These parameters are characterized, but not tested in manufacturing.
DS60001570C-page 649
Units
ns
ns
ns
ns
Conditions
See parameter DO32
See parameter DO31
—
—
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-22:
LOW VOLTAGE DETECT CHARACTERISTICS
MP30
Fault Input
(active-low)
MP20
PWMx
TABLE 36-46: ELECTRICAL CHARACTERISTICS LVD
Standard Operating Conditions: 2.3V to 3.6V
(Unless otherwise stated)
Operating temperature -40°c ≤ TA ≤ +125°C
DC Specifications
Symbol
VLVD
Min
Typƚ
Max
Units
Conditions
LVDL = 0000
—
—
—
V
Reserved
LVDL = 0001
—
—
—
V
Reserved
LVDL = 0010
—
—
—
V
Reserved
LVDL = 0011
—
—
—
V
Reserved
LVD = 0100
3.38
3.52
3.66
V
LVD = 0101
3.14
3.27
3.4
V
LVD = 0110
2.87
2.99
3.11
V
LVD = 0111
2.67
2.78
2.89
V
LVD = 1000
2.57
2.68
2.79
V
LVD = 1001
2.39
2.49
2.59
V
Characteristic
LVD Voltage
on VDD
transition
high to low
LVD = 1010
2.29
2.39
2.48
V
LVDL = 1011
—
—
—
V
Reserved
LVDL = 1100
—
—
—
V
Reserved
LVDL = 1101
—
—
—
V
Reserved
Reserved
LVDL = 1110
—
—
—
V
LVDL = 1111
External
External
External
V
VLVERR
LVD Total Error
-10
-
10
mV
VLHYS
Low-Voltage Detect Hysteresis
-
6.8
24
mV
2019-2020 Microchip Technology Inc.
offset, regulation drift and
temperature drift
DS60001570C-page 650
PIC32MK GPG/MCJ with CAN FD Family
FIGURE 36-23:
EJTAG TIMING CHARACTERISTICS
TTCKcyc
TTCKhigh
TTCKlow
Trf
TCK
Trf
TMS
TDI
TTsetup TThold
Trf
Trf
TDO
TRST*
TTRST*low
TTDOout
TTDOzstate
Defined
Trf
Undefined
TABLE 36-47: EJTAG TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
No.
Symbol
Description(1)
Min.
Max.
Units
Conditions
EJ1
TTCKCYC
TCK Cycle Time
25
—
ns
—
EJ2
TTCKHIGH
TCK High Time
10
—
ns
—
EJ3
TTCKLOW
TCK Low Time
10
—
ns
—
EJ4
TTSETUP
TAP Signals Setup Time Before
Rising TCK
5
—
ns
—
EJ5
TTHOLD
TAP Signals Hold Time After
Rising TCK
3
—
ns
—
EJ6
TTDOOUT
TDO Output Delay Time from
Falling TCK
—
5
ns
—
EJ7
TTDOZSTATE TDO 3-State Delay Time from
Falling TCK
—
5
ns
—
EJ8
TTRSTLOW
TRST Low Time
25
—
ns
—
EJ9
TRF
TAP Signals Rise/Fall Time, All
Input and Output
—
—
ns
—
Note 1:
These parameters are characterized, but not tested in manufacturing.
DS60001570C-page 651
2019-2020 Microchip Technology Inc.
AC AND DC CHARACTERISTICS GRAPHS
Note:
The graphs provided are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested
or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FIGURE 37-1:
VOH – 4x DRIVER PINS
FIGURE 37-3:
VOH – 8x DRIVER PINS
VOH(V)
VOH(V)
Ͳ0.050
Ͳ0.090
Ͳ0.045
Ͳ0.080
Ͳ0.040
Ͳ0.070
Ͳ0.060
Ͳ0.030
IOH(A)
IOH(A)
Ͳ0.035
Ͳ0.025
Ͳ0.050
Ͳ0.040
Ͳ0.020
0 020
Ͳ0.030
Ͳ0.015
Ͳ0.020
AbsoluteMaximum
Ͳ0.010
AbsoluteMaximum
Ͳ0.010
Ͳ0.005
0.000
0.000
0.00
0.50
FIGURE 37-2:
1.00
1.50
2.00
2.50
3.00
0.00
3.50
0.50
FIGURE 37-4:
VOL – 4x DRIVER PINS
1.00
2.00
2.50
3.00
3.50
VOL – 8x DRIVER PINS
VOL(V)
VOL(V)
0.050
0.090
0.045
0.080
0.040
0.070
0.035
0.060
DS60001570C-page 652
IOL(A)
0.030
IOL(A)
1.50
0.025
0.050
0.040
0 020
0.020
0.030
0.015
AbsoluteMaximum
AbsoluteMaximum
0.020
0.010
0.010
0.005
0.000
0.000
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
37.0
PIC32MK GPG/MCJ with CAN FD Family
NOTES:
DS60001570C-page 653
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
38.0
PACKAGING INFORMATION
38.1
Package Marking Information
64-Lead QFN (9x9x0.9 mm)
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
MK0512
MCJ064
e3
0510017
64-Lead TQFP (10x10x1 mm)
e3
0510017
48-Lead TQFP (7x7x1 mm)
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
48-Lead VQFN (6x6x0.9 mm)
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
*
Note:
Example
MK0512
MCJ064
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
Example
Example
MK0512
MCJ048
0510017
Example
MK0512
MCJ048
e3
0510017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e)3
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2019-2020 Microchip Technology Inc.
DS60001570C-page 654
PIC32MK GPG/MCJ with CAN FD Family
38.2
Package Details
DS60001570C-page 655
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
2019-2020 Microchip Technology Inc.
DS60001570C-page 656
PIC32MK GPG/MCJ with CAN FD Family
DS60001570C-page 657
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1/2
D
NOTE 2
A
B
E1/2
E1
A
E
A
SEE DETAIL 1
N
4X N/4 TIPS
0.20 C A-B D
1 3
2
4X
NOTE 1
0.20 H A-B D
TOP VIEW
A2
A
0.05
C
SEATING
PLANE
0.08 C
64 X b
0.08
e
A1
C A-B D
SIDE VIEW
Microchip Technology Drawing C04-085C Sheet 1 of 2
2019-2020 Microchip Technology Inc.
DS60001570C-page 658
PIC32MK GPG/MCJ with CAN FD Family
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
H
c
E
L
(L1)
T
X=A—B OR D
X
SECTION A-A
e/2
DETAIL 1
Notes:
Units
Dimension Limits
Number of Leads
N
e
Lead Pitch
Overall Height
A
Molded Package Thickness
A2
Standoff
A1
Foot Length
L
Footprint
L1
I
Foot Angle
Overall Width
E
Overall Length
D
Molded Package Width
E1
Molded Package Length
D1
c
Lead Thickness
b
Lead Width
D
Mold Draft Angle Top
E
Mold Draft Angle Bottom
MIN
0.95
0.05
0.45
0°
0.09
0.17
11°
11°
MILLIMETERS
NOM
64
0.50 BSC
1.00
0.60
1.00 REF
3.5°
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
0.22
12°
12°
MAX
1.20
1.05
0.15
0.75
7°
0.20
0.27
13°
13°
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085C Sheet 2 of 2
DS60001570C-page 659
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
E
C2
G
Y1
X1
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X28)
X1
Contact Pad Length (X28)
Y1
Distance Between Pads
G
MIN
MILLIMETERS
NOM
0.50 BSC
11.40
11.40
MAX
0.30
1.50
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2085B Sheet 1 of 1
2019-2020 Microchip Technology Inc.
DS60001570C-page 660
PIC32MK GPG/MCJ with CAN FD Family
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