PIC32MK GENERAL PURPOSE AND
MOTOR CONTROL (GP/MC) FAMILY
32-bit General Purpose and Motor Control Application MCUs with FPU and
up to 1 MB Live-Update Flash, 256 KB SRAM, 4 KB EEPROM, and Op amps
Operating Conditions: 2.2V to 3.6V
Security Features
• -40ºC to +85ºC, DC to 120 MHz
• -40ºC to +125ºC, DC to 80 MHz
• Advanced Memory Protection:
- Peripheral and memory region access control
Core: 120 MHz (up to 198 DMIPS)
Advanced Analog Features
• MIPS32® microAptiv™ MCU core with Floating Point Unit
• microMIPS™ mode for up to 40% smaller code size
• DSP-enhanced core:
- Four 64-bit accumulators
- Single-cycle MAC, saturating and fractional math
• Code-efficient (C and Assembly) architecture
• Two 32-bit core register files to reduce interrupt latency
• 12-bit ADC module:
- Sum of all individual ADC's combined, 25.45 Msps 12-bit mode
or 33.79 Msps 8-bit mode
- 7 individual ADC modules
- 3.75 Msps per S&H with dedicated DMA
- Up to 42 analog inputs
• Flexible and independent ADC trigger sources
• Four Op amps and five Comparators
• Up to three 12-bit CDACs
• Internal temperature sensor ±2ºC accuracy
• Capacitive Touch Divider (CVD)
Clock Management
• 8 MHz ±5% (FRC) internal oscillator 0ºC to +70ºC
• Programmable PLLs and oscillator clock sources:
- HS and EC clock modes
• Secondary USB PLL
• 32 kHz Internal Low-power RC oscillator (LPRC)
• Independent external low-power 32 kHz crystal oscillator
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timers (WDT) and Deadman Timer (DMT)
• Fast wake-up and start-up
• Four Fractional clock out (REFCLKO) modules
Power Management
• Low-power management modes (Deep Sleep, Sleep, and Idle)
• Integrated:
- Power-on Reset (POR) and Brown-out Reset (BOR)
• On-board capacitorless regulator
Motor Control PWM
•
•
•
•
•
•
•
Eight PWM pairs
Six additional Single-Ended PWM modules
Dead Time for rising and falling edges
Dead-Time Compensation
8.33 ns PWM Resolution
Clock Chopping for High-Frequency Operation
PWM Support for:
- DC/DC, AC/DC, inverters, PFC, lighting
- BLDC, PMSM, ACIM, SRM motors
• Choice of six Fault and Current Limit Inputs
• Flexible Trigger Configuration for ADC Triggering
Motor Encoder Interface
• Six Quadrature Encoder Interface (QEI) modules:
- Four inputs: Phase A, Phase B, Home, and Index
Audio/Graphics/Touch Interfaces
•
•
•
•
External Graphics interfaces through PMP
Up to six I2S audio data communication interfaces
Up to six SPI audio control interfaces
Programmable audio Host clock:
- Generation of fractional clock frequencies
- Can be synchronized with USB clock
- Can be tuned in run-time
Unique Features
• Permanent non-volatile 4-word unique device serial number
Direct Memory Access (DMA)
• Up to eight channels with automatic data size detection
• Programmable Cyclic Redundancy Check (CRC)
• Up to 64 KB transfers
2016-2021 Microchip Technology Inc.
Communication Interfaces
• Up to four CAN modules (with dedicated DMA channels):
- 2.0B Active with DeviceNet™ addressing support
• Up to six UART modules (up to 25 Mbps):
- Supports LIN 1.2 and IrDA® protocols
• Six SPI/I2S modules (SPI 50 Mbps)
• Parallel Host Port (PMP)
• Up to two FS USB 2.0-compliant On-The-Go (OTG) controllers
• Peripheral Pin Select (PPS) to enable remappable pin functions
Timers/Output Compare/Input Capture/RTCC
• Up to 14 16-bit or one 16-bit and eight 32-bit timers/counters for GP
and MC devices and six additional QEI 32-bit timers for MC devices
• 16 Output Compare (OC) modules
• 16 Input Capture (IC) modules
• PPS to enable function remap
• Real-Time Clock and Calendar (RTCC) module
Input/Output
•
•
•
•
5V-tolerant pins with up to 22 mA source/sink
Selectable internal open drain, pull-ups, and pull-downs
External interrupts on all I/O pins
Five programmable edge/level-triggered interrupt pins
Qualification and Class B Support
•
•
•
•
Class B Safety Library
Back-up internal oscillator
Clock monitor with back-up internal oscillator
Global register locking
Debugger Development Support
•
•
•
•
•
In-circuit and in-application programming
2-wire or 4-wire MIPS® Enhanced JTAG interface
Unlimited software and 12 complex breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Non-intrusive hardware-based instruction trace
Software and Tools Support
•
•
•
•
•
C/C++ compiler with native DSP/fractional support
MPLAB® Harmony Integrated Software Framework
TCP/IP, USB, Graphics, and mTouch™ middleware
MFi, Android™ and Bluetooth® audio frameworks
RTOS Kernels: Express Logic ThreadX, FreeRTOS™,
OPENRTOS®, Micriµm® µC/OS™, and SEGGER embOS®
DS60001402H-page 1
PIC32MK GP/MC Family
Packages
Type
VQFN
Pin Count
I/O Pins (up to)
Contact/Lead Pitch
Dimensions
TABLE 1:
TQFP
64
48 (GP devices)
49 (MC devices)
0.50 mm
9x9x0.9 mm
64
48 (GP devices)
49 (MC devices)
0.50 mm
10x10x1 mm
PIC32MK GENERAL PURPOSE (GP) FAMILY FEATURES
1:
2:
Legend:
CAN 2.0B
ADC (Channels)
Op amp/Comparator
USB 2.0 FS OTG
PMP
RTCC
REFCLK
CDAC
CTMU
I/O Pins
JTAG/ICSP
Trace
Y
64
TQFP,
16
VQFN
Y
9/16/16
6
6
5
—
8/13
26 4/5
1
Y
1
4
3
1
48
Y
Y
4
Y 100 TQFP 16
Y
9/16/16
6
6
5
—
8/13
42 4/5
2
Y
1
4
3
1
77
Y
Y
4
Y
TQFP,
16
VQFN
Y
9/16/16
6
6
5
4
8/13
26 4/5
1
Y
1
4
3
1
48
Y
Y
4
Y 100 TQFP 16
Y
9/16/16
6
6
5
4
8/13
42 4/5
2
Y
1
4
3
1
77
Y
Y
64
Boot Flash Memory (KB)
4
Packages
DMA Channels
(Programmable/Dedicated)
PIC32MK1024GPE100 1024 256
External Interrupts(2)
PIC32MK0512GPE100 512 128
UART
PIC32MK1024GPE064 1024 256
SPI/I2S
PIC32MK0512GPE064 512 128
Timers/Capture/Compare(1)
PIC32MK1024GPD100 1024 256
Remappable Pins
PIC32MK0512GPD100 512 128
Pins
PIC32MK1024GPD064 1024 256
Floating Point Unit (FPU)
PIC32MK0512GPD064 512 128
EE Memory (KB)
Data Memory (KB)
Device
Program Memory (KB)
Remappable Peripherals
Note
100
77 (GP devices)
78 (MC devices)
0.40 mm
12x12x1 mm
Eight out of nine timers are remappable.
Four out of five external interrupts are remappable.
An ‘—’ indicates this feature is not available for the listed device.
TABLE 2:
PIC32MK MOTOR CONTROL (MC) FAMILY FEATURES
Note
1:
2:
PMP
QEI
MCPWM
RTCC
REFCLK
CDAC
CTMU
I/O Pins
JTAG/ICSP
Trace
5
4
8/13 26 4/5 1
Y
6
12
1
4
3
1
49
Y
Y
4
Y 100 TQFP 16
Y 9/16/16 6
6
5
4
8/13 42 4/5 2
Y
6
12
1
4
3
1
78
Y
Y
Op amp/Comparator
6
ADC (Channels)
USB 2.0 FS OTG
DMA Channels
(Programmable/Dedicated)
CAN 2.0B
Y 9/16/16 6
UART
TQFP,
16
VQFN
Timers/Capture/Compare(1)
64
Remappable Pins
Y
Boot Flash Memory (KB)
4
Packages
External Interrupts(2)
PIC32MK1024MCF100 1024 256
SPI/I2S
PIC32MK0512MCF100 512 128
Pins
PIC32MK1024MCF064 1024 256
Floating Point Unit (FPU)
PIC32MK0512MCF064 512 128
EE Memory (KB)
Data Memory (KB)
Device
Program Memory (KB)
Remappable Peripherals
Eight out of nine timers are remappable.
Four out of five external interrupts are remappable.
DS60001402H-page 2
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
Device Pin Tables
TABLE 3:
PIN NAMES FOR 64-PIN GENERAL PURPOSE (GPD/GPE) DEVICES
64-PIN VQFN(4) AND TQFP (TOP VIEW)
PIC32MK0512GPD064
PIC32MK0512GPE064
PIC32MK1024GPD064
PIC32MK1024GPE064
64
Pin #
Full Pin Name
VQFN(4)
1
64
TQFP
1
Pin #
Full Pin Name
33
OA5IN+/DAC1/AN24/CVD24/C5IN1+/C5IN3-/RPA4/T1CK/
RA4
1
TCK/RPA7/PMD5/RA7
2
RPB14/VBUSON1/PMD6/RB14
34
VBUS
3
RPB15/PMD7/RB15
35
VUSB3V3
4
AN19/CVD19/RPG6/PMA5/RG6
36
D-
5
AN18/CVD18/RPG7/PMA4/RG7(6)
37
D+
6
AN17/CVD17/RPG8/PMA3/RG8(7)
38
VDD
7
MCLR
39
OSCI/CLKI/AN49/CVD49/RPC12/RC12
8
AN16/CVD16/RPG9/PMA2/RG9
40
OSCO/CLKO/RPC15/RC15
9
VSS
41
VSS
10
VDD
42
VBAT
11
AN10/CVD10/RPA12/RA12
43
PGD2/RPB5/USBID1/RB5(7)
12
AN9/CVD9/RPA11/RA11
44
PGC2/RPB6/SCK2/PMA15/RB6(6)
13
OA2OUT/ANO/C2IN4-/C4IN3-/RPA0/RA0
45
DAC2/AN48/CVD48/RPC10/PMA14/PMCS/RC10
14
OA2IN+/AN1/C2IN1+/RPA1/RA1
46
OA5OUT/AN25/CVD25/C5IN4-/RPB7/SCK1/INT0/RB7
15
PGD3/VREF-/OA2IN-/AN2/C2IN1-/RPB0/CTED2/RB0
47
SOSCI/RPC13(5)/RC13(5)
16
PGC3/OA1OUT/VREF+/AN3/C1IN4-/C4IN2-/RPB1/CTED1/PMA6/
RB1
48
SOSCO/RPB8(5)/RB8(5)
17
PGC1/OA1IN+/AN4/C1IN1+/C1IN3-/C2IN3-/RPB2/RB2
49
TMS/OA5IN-/AN27/CVD27/C5IN1-/RPB9/RB9
TRCLK/RPC6/RC6
18
PGD1/OA1IN-/AN5/CTCMP/C1IN1-/RTCC/RPB3/RB3
50
19
AVDD
51
TRD0/RPC7/RC7
20
AVSS
52
TRD1/RPC8/PMWR/RC8
21
OA3OUT/AN6/CVD6/C3IN4-/C4IN1+/C4IN4-/RPC0/RC0
53
TRD2/RPD5/PMRD/RD5
22
OA3IN-/AN7/CVD7/C3IN1-/C4IN1-/RPC1/PMA7/RC1
54
TRD3/RPD6/RD6
23
OA3IN+/AN8/CVD8/C3IN1+/C3IN3-/RPC2/PMA13/RC2
55
RPC9/RC9
24
AN11/CVD11/C1IN2-/PMA12/RC11
56
VSS
25
VSS
57
VDD
26
VDD
58
RPF0/RF0
27
AN12/CVD12/C2IN2-/C5IN2-/PMA11/RE12(7)
59
RPF1/RF1
28
AN13/CVD13/C3IN2-/PMA10/RE13(6)
60
RPB10/PMD0/RB10
29
AN14/CVD14/RPE14/PMA1/RE14
61
RPB11/PMD1/RB11
30
AN15/CVD15/RPE15/PMA0/RE15
62
RPB12/PMD2/RB12
31
TDI/DAC3/AN26/CVD26/RPA8/PMA9/RA8(7)
63
RPB13/CTPLS/PMD3/RB13
32
RPB4/PMA8/RB4(6)
64
TDO/PMD4/RA10
Note
1:
2:
3:
4:
5:
6:
7:
8:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and 13.3 “Peripheral Pin Select (PPS)”
for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See 13.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
Functions are restricted to input functions only and inputs will be slower than the standard inputs.
The I2C library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I2C Host/Client clock, that is SCL.
The I2C library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I2C data I/O, that is, SDA.
VBAT functionality is compromised. For additional information, refer to specific errata documents. This pin must be connected to VDD.
2016-2021 Microchip Technology Inc.
DS60001402H-page 3
PIC32MK GP/MC Family
TABLE 4:
PIN NAMES FOR 64-PIN MOTOR CONTROL (MCF) DEVICES
64-PIN VQFN(4) AND TQFP (TOP VIEW)
PIC32MK0512MCF064
PIC32MK1024MCF064
64
Pin
#
Full Pin Name
VQFN(4)
64
1
TQFP
Pin
#
1
Full Pin Name
1
TCK/RPA7/PWM10H/PWM4L/PMD5/RA7
33 OA5IN+/DAC1/AN24/CVD24/C5IN1+/C5IN3-/RPA4/T1CK/RA4
2
RPB14/PWM1H/VBUSON1/PMD6/RB14
34 VBUS
3
RPB15/PWM7H/PWM1L/PMD7/RB15
35 VUSB3V3
4
AN19/CVD19/RPG6/PMA5/RG6
36 D-
5
AN18/CVD18/RPG7/PMA4/RG7(6)
37 D+
6
AN17/CVD17/RPG8/PMA3/RG8(7)
38 VDD
7
MCLR
39 OSCI/CLKI/AN49/CVD49/RPC12/RC12
8
AN16/CVD16/RPG9/PMA2/RG9
40 OSCO/CLKO/RPC15/RC15
9
VSS
41 VSS
10 VDD
42 RD8
11 AN10/CVD10/RPA12/RA12
43 PGD2/RPB5/USBID1/RB5(7)
12 AN9/CVD9/RPA11/USBOEN1/RA11
44 PGC2/RPB6/SCK2/PMA15/RB6(6)
13 OA2OUT/AN0/C2IN4-/C4IN3-/RPA0/RA0
45 DAC2/AN48/CVD48/RPC10/PMA14/PMCS/RC10
14 OA2IN+/AN1/C2IN1+/RPA1/RA1
46 OA5OUT/AN25/CVD25/C5IN4-/RPB7/SCK1/INT0/RB7
15 PGD3/VREF-/OA2IN-/AN2/C2IN1-/RPB0/CTED2/RB0
47 SOSCI/RPC13(5)/RC13(5)
16 PGC3/OA1OUT/VREF+/AN3/C1IN4-/C4IN2-/RPB1/CTED1/PMA6/RB1
48 SOSCO/RPB8(5)/RB8(5)
17 PGC1/OA1IN+/AN4/C1IN1+/C1IN3-/C2IN3-/RPB2/RB2
49 TMS/OA5IN-/AN27/CVD27/C5IN1-/RPB9/RB9
18 PGD1/OA1IN-/AN5/CTCMP/C1IN1-/RTCC/RPB3/RB3
50 TRCLK/RPC6/PWM6H/RC6
19 AVDD
51 TRD0/RPC7/PWM12H/PWM6L/RC7
20 AVSS
52 TRD1/RPC8/PWM5H/PMWR/RC8
21 OA3OUT/AN6/CVD6/C3IN4-/C4IN1+/C4IN4-/RPC0/RC0
53 TRD2/RPD5/PWM12H/PMRD/RD5
22 OA3IN-/AN7/CVD7/C3IN1-/C4IN1-/RPC1/PMA7/RC1
54 TRD3/RPD6/PWM12L/RD6
23 OA3IN+/AN8/CVD8/C3IN1+/C3IN3-/RPC2/FLT3/PMA13/RC2
55 RPC9/PWM11H/PWM5L/RC9
24 AN11/CVD11/C1IN2-/FLT4/PMA12/RC11
56 VSS
25 VSS
57 VDD
26 VDD
58 RPF0/PWM11H/RF0
27 AN12/CVD12/C2IN2-/C5IN2-/FLT5/PMA11/RE12(7)
59 RPF1/PWM11L/RF1
28 AN13/CVD13/C3IN2-/FLT6/PMA10/RE13(6)
60 RPB10/PWM3H/PMD0/RB10
29 AN14/CVD14/RPE14/FLT7/PMA1/RE14
61 RPB11/PWM9H/PWM3L/PMD1/RB11
30 AN15/CVD15/RPE15/FLT8/PMA0/RE15
62 RPB12/PWM2H/PMD2/RB12
31 TDI/DAC3/AN26/CVD26/RPA8/PMA9/RA8(7)
63 RPB13/PWM8H/PWM2L/CTPLS/PMD3/RB13
32 FLT15/RPB4/PMA8/RB4(6)
64 TDO/PWM4H/PMD4/RA10
Note
1:
2:
3:
4:
5:
6:
7:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and 13.3 “Peripheral Pin Select (PPS)”
for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See 13.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
Functions are restricted to input functions only and inputs will be slower than standard inputs.Change notification interrupt is not available
on this pin.
The I2C Library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I2C Host/Client clock, that is, SCL.
The I2C Library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I2C data I/O, that is, SDA.
DS60001402H-page 4
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 5:
PIN NAMES FOR 100-PIN GENERAL PURPOSE (GPD/GPE) DEVICES
100-PIN TQFP (TOP VIEW)
M
PIC32MK0512GPD100
PIC32MK0512GPE100
PIC32MK1024GPD100
PIC32MK1024GPE100
100
1
Pin #
Full Pin Name
Pin #
Full Pin Name
1
AN23/CVD23/PMA23/RG15
36
VSS
2
VDD
37
VDD
3
TCK/RPA7/PMD5/RA7
38
AN35/CVD35/RG11
4
RPB14/VBUSON1/PMD6/RB14
39
AN36/CVD36/RF13
5
RPB15/PMD7/RB15
40
AN37/CVD37/RF12
6
RD1
41
AN12/CVD12/C2IN2-/C5IN2-/SDA4/PMA11/RE12(6)
7
RD2
42
AN13/CVD13/C3IN2-/SCL4/PMA10/RE13(5)
8
RPD3/RD3
43
AN14/CVD14/RPE14/PMA1/RE14
AN15/CVD15/RPE15/PMA0/RE15
9
RPD4/RD4
44
10
AN19/CVD19/RPG6/VBUSON2/PMA5/RG6
45
VSS
11
AN18/CVD18/RPG7/SCL1/PMA4/RG7(5)
46
VDD
AN38/CVD38/RD14
12
AN17/CVD17/RPG8/SDA1/PMA3/RG8(6)
47
13
MCLR
48
AN39/CVD39/RD15
14
AN16/CVD16/RPG9/PMA2/RG9
49
TDI/DAC3/AN26/CVD26/RPA8/SDA2/PMA9/RA8(6)
15
VSS
50
RPB4/SCL2/PMA8/RB4(5)
16
VDD
51
OA5IN+/DAC1/AN24/CVD24/C5IN1+/C5IN3-/RPA4/T1CK/RA4
17
AN22/CVD22/RG10
52
AN40/CVD40/RPE0/RE0
18
AN21/CVD21/RE8
53
AN41/CVD41/RPE1/RE1
19
AN20/CVD20/RE9
54
VBUS1
20
AN10/CVD10/RPA12/RA12
55
VUSB3V3
21
AN9/CVD9/RPA11/RA11
56
D1-
22
OA2OUT/AN0/C2IN4-/C4IN3-/RPA0/RA0
57
D1+
23
OA2IN+/AN1/C2IN1+/RPA1/RA1
58
VBUS2
24
PGD3/OA2IN-/AN2/C2IN1-/RPB0/CTED2/RB0
59
D2-
25
PGC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPB1/CTED1/RB1
60
D2+
26
PGC1/OA1IN+/AN4/C1IN1+/C1IN3-/C2IN3-/RPB2/RB2
61
AN45/CVD45/RF5
27
PGD1/OA1IN-/AN5/CTCMP/C1IN1-/RTCC/RPB3/RB3
62
VDD
28
VREF-/AN33/CVD33/PMA7/RF9
63
OSCI/CLKI/AN49/CVD49/RPC12/RC12
29
VREF+/AN34/CVD34/PMA6/RF10
64
OSCO/CLKO/RPC15/RC15
30
AVDD
65
VSS
31
AVSS
66
AN46/CVD46/RPA14/RA14
32
OA3OUT/AN6/CVD6/C3IN4-/C4IN1+/C4IN4-/RPC0/RC0
67
AN47/CVD47/RPA15/RA15
33
OA3IN-/AN7/CVD7/C3IN1-/C4IN1-/RPC1/RC1
68
VBAT
34
OA3IN+/AN8/CVD8/C3IN1+/C3IN3-/RPC2/PMA13/RC2
69
PGD2/RPB5/SDA3/USBID1/RB5(6)
35
AN11/CVD11/C1IN2-/PMA12/RC11
70
PGC2/RPB6/SCL3/SCK2/PMA15/RB6(5)
Note
1:
2:
3:
4:
5:
6:
7:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and 13.3 “Peripheral Pin Select (PPS)”
for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See 13.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
Functions are restricted to input functions only and inputs will be slower than standard inputs. Change notification interrupt is not available
on this pin.
The I2C library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I2C Host/Client clock, that is, SCL.
The I2C library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I2C data I/O, that is, SDA.
VBAT functionality is compromised. For additional information, refer to specific errata documents. This pin must be connected to VDD.
2016-2021 Microchip Technology Inc.
DS60001402H-page 5
PIC32MK GP/MC Family
TABLE 5:
PIN NAMES FOR 100-PIN GENERAL PURPOSE (GPD/GPE) DEVICES (CONTINUED)
100-PIN TQFP (TOP VIEW)
M
PIC32MK0512GPD100
PIC32MK0512GPE100
PIC32MK1024GPD100
PIC32MK1024GPE100
100
1
Pin #
Full Pin Name
Pin #
Full Pin Name
71
DAC2/AN48/CVD48/RPC10/PMA14/PMCS/RC10
86
72
OA5OUT/AN25/CVD25/C5IN4-/RPB7/SCK1/INT0/RB7
87
RPF0/PMD11/RF0
73
SOSCI/RPC13(4)/RC13(4)
88
RPF1/PMD10/RF1
74
SOSCO/RPB8(4)/RB8(4)
89
RPG1/PMD9/RG1
75
VSS
90
RPG0/PMD8/RG0
76
TMS/OA5IN-/AN27/CVD27/LVDIN/C5IN1-/RPB9/RB9
91
TRCLK/PMA18/RF6
77
RPC6/USBID2/PMA16/RC6
92
TRD3/PMA19/RF7
78
RPC7/PMA17/RC7
93
RPB10/PMD0/RB10
79
PMD12/RD12
94
RPB11/PMD1/RB11
80
PMD13/RD13
95
TRD2/PMA20/RG14
81
RPC8/PMWR/RC8
96
TRD1/RPG12/PMA21/RG12
82
RPD5/PMRD/RD5
97
TRD0/PMA22/RG13
83
RPD6/PMD14/RD6
98
RPB12/PMD2/RB12
84
RPC9/PMD15/RC9
99
RPB13/CTPLS/PMD3/RB13
85
VSS
100
TDO/PMD4/RA10
Note
1:
2:
3:
4:
5:
6:
7:
VDD
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and 13.3 “Peripheral Pin Select (PPS)”
for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See 13.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
Functions are restricted to input functions only and inputs will be slower than standard inputs. Change notification interrupt is not available
on this pin.
The I2C library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I2C Host/Client clock, that is, SCL.
The I2C library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I2C data I/O, that is, SDA.
VBAT functionality is compromised. For additional information, refer to specific errata documents. This pin must be connected to VDD.
DS60001402H-page 6
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 6:
PIN NAMES FOR 100-PIN MOTOR CONTROL (MCF) DEVICES
100-PIN TQFP (TOP VIEW)
M
PIC32MK0512MCF100
PIC32MK1024MCF100
100
1
Pin #
Full Pin Name
Pin #
Full Pin Name
1
AN23/CVD23/PMA23/RG15
36
VSS
2
VDD
37
VDD
3
TCK/RPA7/PWMH10/PWML4/PMD5/RA7
38
AN35/CVD35/RG11
4
RPB14/PWMH1/VBUSON1/PMD6/RB14
39
AN36/CVD36/RF13
5
RPB15/PWMH7/PWML1/PMD7/RB15
40
AN37/CVD37/RF12
6
PWMH11/PWML5/RD1
41
AN12/CVD12/C2IN2-/C5IN2-/SDA4/FLT5/PMA11/RE12(6)
7
PWMH5/RD2
42
AN13/CVD13/C3IN2-/SCL4/FLT6/PMA10/RE13(5)
8
RPD3/PWMH12/PWML6/RD3
43
AN14/CVD14/RPE14/FLT7/PMA1/RE14
9
RPD4/PWMH6/RD4
44
AN15/CVD15/RPE15/FLT8/PMA0/RE15
10
AN19/CVD19/RPG6/VBUSON2/PMA5/RG6
45
VSS
11
AN18/CVD18/RPG7/SCL1/PMA4/RG7(5)
46
VDD
12
AN17/CVD17/RPG8/SDA1/PMA3/RG8(6)
47
AN38/CVD38/RD14
13
MCLR
48
AN39/CVD39/RD15
14
AN16/CVD16/RPG9/PMA2/RG9
49
TDI/DAC3/AN26/CVD26/RPA8/SDA2/PMA9/RA8(6)
15
VSS
50
FLT15/RPB4/SCL2/PMA8/RB4(5)
16
VDD
51
OA5IN+/DAC1/AN24/CVD24/C5IN1+/C5IN3-/RPA4/T1CK/RA4
17
AN22/CVD22/RG10
52
AN40/CVD40/RPE0/RE0
18
AN21/CVD21/RE8
53
AN41/CVD41/RPE1/RE1
19
AN20/CVD20/RE9
54
VBUS1
20
AN10/CVD10/RPA12/RA12
55
VUSB3V3
21
AN9/CVD9/RPA11/RA11
56
D1-
22
OA2OUT/AN0/C2IN4-/C4IN3-/RPA0/RA0
57
D1+
23
OA2IN+/AN1/C2IN1+/RPA1/RA1
58
VBUS2
24
PGD3/OA2IN-/AN2/C2IN1-/RPB0/CTED2/RB0
59
D2-
25
PGC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPB1/CTED1/RB1
60
D2+
26
PGC1/OA1IN+/AN4/C1IN1+/C1IN3-/C2IN3-/RPB2/RB2
61
AN45/CVD45/RF5
27
PGD1/OA1IN-/AN5/CTCMP/C1IN1-/RTCC/RPB3/RB3
62
VDD
28
VREF-/AN33/CVD33/PMA7/RF9
63
OSCI/CLKI/AN49/CVD49/RPC12/RC12
29
VREF+/AN34/CVD34/PMA6/RF10
64
OSCO/CLKO/RPC15/RC15
30
AVDD
65
VSS
31
AVSS
66
AN46/CVD46/RPA14/RA14
32
OA3OUT/AN6/CVD6/C3IN4-/C4IN1+/C4IN4-/RPC0/RC0
67
AN47/CVD47/RPA15/RA15
33
OA3IN-/AN7/CVD7/C3IN1-/C4IN1-/RPC1/RC1
68
RD8
34
OA3IN+/AN8/CVD8/C3IN1+/C3IN3-/RPC2/FLT3/PMA13/RC2
69
PGD2/RPB5/SDA3/USBID1/RB5(6)
35
AN11/CVD11/C1IN2-/FLT4/PMA12/RC11
70
PGC2/RPB6/SCL3/SCK2/PMA15/RB6(5)
Note
1:
2:
3:
4:
5:
6:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and 13.3 “Peripheral Pin Select (PPS)”
for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See 13.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
Functions are restricted to input functions only and inputs will be slower than standard inputs. Change notification interrupt is not available on this pin.
The I2C library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I2C Host/Client clock (i.e., SCL).
The I2C library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I2C data I/O (i.e., SDA).
2016-2021 Microchip Technology Inc.
DS60001402H-page 7
PIC32MK GP/MC Family
TABLE 6:
PIN NAMES FOR 100-PIN MOTOR CONTROL (MCF) DEVICES (CONTINUED)
100-PIN TQFP (TOP VIEW)
M
PIC32MK0512MCF100
PIC32MK1024MCF100
100
1
Pin #
71
Full Pin Name
Pin #
Full Pin Name
DAC2/AN48/CVD48/RPC10/PMA14/PMCS/RC10
86
VDD
72
OA5OUT/AN25/CVD25/C5IN4-/RPB7/SCK1/INT0/RB7
87
RPF0/PWMH11/PMD11/RF0
73
SOSCI/RPC13(4)/RC13(4)
88
RPF1/PWML11/PMD10/RF1
74
SOSCO/RPB8(4)/RB8(4)
89
RPG1/PMD9/RG1
75
VSS
90
RPG0/PMD8/RG0
76
TMS/OA5IN-/AN27/CVD27/LVDIN/C5IN1-/RPB9/RB9
91
TRCLK/PMA18/RF6
77
RPC6/USBID2/PMA16/RC6
92
TRD3/PMA19/RF7
78
RPC7/PMA17/RC7
93
RPB10/PWMH3/PMD0/RB10
79
PMD12/RD12
94
RPB11/PWMH9/PWML3/PMD1/RB11
80
PMD13/RD13
95
TRD2/PMA20/RG14
81
RPC8/PMWR/RC8
96
TRD1/RPG12/PMA21/RG12
82
RPD5/PWMH12/PMRD/RD5
97
TRD0/PMA22/RG13
83
RPD6/PWML12/PMD14/RD6
98
RPB12/PWMH2/PMD2/RB12
84
RPC9/PMD15/RC9
99
RPB13/PWMH8/PWML2/CTPLS/PMD3/RB13
85
VSS
100
TDO/PWMH4/PMD4/RA10
Note
1:
2:
3:
4:
5:
6:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and 13.3 “Peripheral Pin Select (PPS)”
for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See 13.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
Functions are restricted to input functions only and inputs will be slower than standard inputs. Change notification interrupt is not available on this pin.
The I2C library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I2C Host/Client clock (i.e., SCL).
The I2C library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I2C data I/O (i.e., SDA).
DS60001402H-page 8
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
1
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip Worldwide Web site: http://www.microchip.com
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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2016-2021 Microchip Technology Inc.
DS60001402H-page 9
PIC32MK GP/MC Family
Referenced Sources
This device data sheet is based on the following
individual sections of the “PIC32 Family Reference
Manual”. These documents should be considered as
the general reference for the operation of a particular
module or device feature.
Note:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
To access the following documents, refer
to the Documentation > Reference
Manuals section of the Microchip PIC32
web site: http://www.microchip.com/pic32.
Section 1. “Introduction” (DS60001127)
Section 4. “Prefetch Cache Module” (DS60001119)
Section 7. “Resets” (DS60001118)
Section 8. “Interrupt Controller” (DS60001108)
Section 9. “Watchdog, Deadman, and Power-up Timers” (DS60001114)
Section 10. “Power-Saving Features” (DS60001130)
Section 12. “I/O Ports” (DS60001120)
Section 13. “Parallel Host Port (PMP)” (DS60001128)
Section 14. “Timers” (DS60001105)
Section 15. “Input Capture” (DS60001122)
Section 16. “Output Compare” (DS60001111)
Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107)
Section 22. “12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter
(ADC)” (DS60001344)
Section 23. “Serial Peripheral Interface (SPI)” (DS60001106)
Section 27. “USB On-The-Go (OTG)” (DS60001126)
Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125)
Section 31. “Direct Memory Access (DMA) Controller” (DS60001117)
Section 32. “Configuration” (DS60001124)
Section 33. “Programming and Diagnostics” (DS60001129)
Section 34. “Controller Area Network (CAN)” (DS60001154)
Section 37. “Charge Time Measurement Unit (CTMU)” (DS60001167)
Section 39. “Op amp/Comparator” (DS60001178)
Section 42. “Oscillators with Enhanced PLL” (DS60001250)
Section 43. “Quadrature Encoder Interface (QEI)” (DS60001346)
Section 44. “Motor Control PWM (MCPWM) (DS60001393)
Section 45. “Control Digital-to-Analog Converter (CDAC)” (DS60001327)
Section 48. “Memory Organization and Permissions” (DS60001214)
Section 50. “CPU for Devices with MIPS32® microAptiv™ and M-Class Cores” (DS60001192)
Section 52. “Flash Program Memory with Support for Live Update” (DS60001193)
Section 58. “Data EEPROM” (DS60001341)
DS60001402H-page 10
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
NOTES:
2016-2021 Microchip Technology Inc.
DS60001402H-page 11
PIC32MK GP/MC Family
1.0
Note:
DEVICE OVERVIEW
This data sheet summarizes the
features of the PIC32MK GP/MC Family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the documents listed in
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
This data sheet contains device-specific information for
PIC32MK GP/MC devices.
Figure 1-1 illustrates a general block diagram of the
core and peripheral modules in the PIC32MK GP/MC
family of devices.
Table 1-21 through Table 1-22 list the pinout I/O
descriptions for the pins shown in the device pin tables
(see Table 3 and Table 5).
DS60001402H-page 12
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
FIGURE 1-1:
PIC32MK GP/MC FAMILY BLOCK DIAGRAM
VDD
OSC2/CLKO
OSC1/CLKI
VBAT
VDD
JTAG
BSCAN
Precision
Band Gap
Reference
PLL
Power
Switch
DIVIDERS
LPRC
Oscillator
PLL USB
RTCC
CRU
DSWDT
FSCM
Deep Sleep
SIB
Timing
Generation
VDD,VSS
MCLR
Oscillator
Start-up Timer
Voltage
Regulator
FRC
Oscillators
Secondary
Oscillator
SOSOC
Power-up
Timer
OSC
Oscillators
USBCLK
SYSCLK
PBCLK
Power-on
Reset
PORTG
Watchdog
Timer
PORTE
PORTF
PORTD
Brown-out
Reset
PORTC
Dead Man
Timer
PORTA
PORTB
ADC0-5, 7 SAR
CAN4
CAN3
PB5
DS
IS
I8
I2
I1
I3
I9
T7
I11
I10
I13
I12
T10
T11
Sonics - Shared Link
Sonics Dedicated Link
T1 T2 T3
I5
PB4
I7
I4
Tn = Target Interface Number
I6
CAN2
DMAC
8-ch.
CAN1
INT
MIPS32®
microAptiv™ MCU
Core with FPU
FS USB2
EJTAG
FS USB1
EVIC
T4
In = Initiator Interface Number
T8
T5
T14
T9
ICD
PB1
CFG
PPS
WDT
Flash
Controller
Flash
Prefetch
Cache
128
SRAM1
PB6
PB3
SRAM2
128
12-Channel
Motor Control
PWM
DSCON
IC10-IC16
RTCC
OC10-OC16
PFM Flash Wrapper
OC1-OC9
128-bit Wide
Panel
Flash Memory
128-bit Wide
Panel
Flash Memory
DMT
DFM Flash Wrapper
CRU
PB2
Timer1TImer9
IC1-IC9
SPI1-SPI2
SPI3-SPI6
UART3UART6
PMP
16K
33-bit Wide
Data EE
Control
Flash Memory
CTMU plus
Temperature
Sensor
UART1-2
12-bit CDAC1
12-bit CDAC2
12-bit CDAC3
QEI1-QEI6
Comparator
1-5
Op amp 1-4
Note:
Not all features are available on all devices. Refer to the family feature tables (Table 1 and Table 2) for the list of available features by device.
2016-2021 Microchip Technology Inc.
DS60001402H-page 13
PIC32MK GP/MC Family
TABLE 1-1:
ADC ANALOG PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
AN0
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
Buffer
Type
22
13
I
Analog
AN1
23
14
I
Analog
AN2
24
15
I
Analog
AN3
25
16
I
Analog
Analog
AN4
26
17
I
AN5
27
18
I
Analog
Analog
AN6
32
21
I
AN7
33
22
I
Analog
Analog
AN8
34
23
I
AN9
21
12
I
Analog
Analog
AN10
20
11
I
AN11
35
24
I
Analog
Analog
AN12
41
27
I
AN13
42
28
I
Analog
Analog
AN14
43
29
I
AN15
44
30
I
Analog
Analog
AN16
14
8
I
AN17
12
6
I
Analog
Analog
AN18
11
5
I
AN19
10
4
I
Analog
AN20
19
—
I
Analog
AN21
18
—
I
Analog
AN22
17
—
I
Analog
AN23
1
—
I
Analog
AN24
51
33
I
Analog
AN25
72
46
I
Analog
I
Analog
AN26
49
31
AN27
76
49
I
Analog
AN33
28
—
I
Analog
AN34
29
—
I
Analog
I
Analog
AN35
38
—
AN36
39
—
I
Analog
AN37
40
—
I
Analog
AN38
47
—
I
Analog
Analog
AN39
48
—
I
AN40
52
—
I
Analog
Analog
AN41
53
—
I
AN45
61
—
I
Analog
Analog
Analog
AN46
66
—
I
AN47
67
—
I
AN48
AN49
Legend:
I
Analog
71
45
I
Analog
63
39
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001402H-page 14
Description
Analog Input Channels
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 1-2:
OSCILLATOR PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
100-pin
TQFP
64-pin
QFN/
TQFP
CLKI
63
39
I
ST
CLKO
64
40
O
CMOS
OSC1
63
39
I
OSC2
64
40
O
SOSCI
73
47
I
SOSCO
74
48
O
CMOS
REFCLKI
PPS
PPS
I
—
One of several alternate REFCLKOx user-selectable input clock sources.
REFCLKO1
PPS
PPS
O
—
Reference Clock Generator Outputs 1-4
REFCLKO2
PPS
PPS
O
—
REFCLKO3
PPS
PPS
O
—
REFCLKO4
PPS
PPS
O
—
Pin Name
Legend:
Description
External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
32.768 low-power oscillator crystal output.
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2016-2021 Microchip Technology Inc.
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001402H-page 15
PIC32MK GP/MC Family
TABLE 1-3:
CVD, CAPACITIVE TOUCH ASSIST PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
21
Input
Analog
33
22
Input
Analog
CVD8
34
23
Input
Analog
CVD9
21
12
Input
Analog
CVD10
20
11
Input
Analog
CVD11
35
24
Input
Analog
CVD12
41
27
Input
Analog
CVD13
42
28
Input
Analog
CVD14
43
29
Input
Analog
CVD15
44
30
Input
Analog
CVD16
14
8
Input
Analog
CVD17
12
6
Input
Analog
CVD18
11
5
Input
Analog
CVD19
10
4
Input
Analog
CVD20
19
—
Input
Analog
CVD21
18
—
Input
Analog
CVD22
17
—
Input
Analog
CVD23
1
—
Input
Analog
CVD24
51
33
Input
Analog
CVD25
72
46
Input
Analog
CVD26
49
31
Input
Analog
CVD27
76
49
Input
Analog
CVD33
28
—
Input
Analog
CVD34
29
—
Input
Analog
CVD35
38
—
Input
Analog
CVD36
39
—
Input
Analog
CVD37
40
—
Input
Analog
CVD38
47
—
Input
Analog
CVD39
48
—
Input
Analog
CVD40
52
—
Input
Analog
CVD41
53
—
Input
Analog
CVD45
61
—
Input
Analog
CVD46
66
—
Input
Analog
CVD47
67
—
Input
Analog
CVD48
71
45
Input
Analog
63
39
Input
Analog
Pin Name
100-pin
TQFP
64-pin
QFN/TQFP
CVD6
32
CVD7
CVD49
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001402H-page 16
Description
Capacitive Touch Assist
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 1-4:
IC1 THROUGH IC16 PINOUT I/O DESCRIPTIONS
Pin Number
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
Buffer
Type
IC1
PPS
PPS
I
ST
IC2
PPS
PPS
I
ST
IC3
PPS
PPS
I
ST
IC4
PPS
PPS
I
ST
IC5
PPS
PPS
I
ST
IC6
PPS
PPS
I
ST
IC7
PPS
PPS
I
ST
IC8
PPS
PPS
I
ST
IC9
PPS
PPS
I
ST
IC10
PPS
PPS
I
ST
IC11
PPS
PPS
I
ST
IC12
PPS
PPS
I
ST
IC13
PPS
PPS
I
ST
IC14
PPS
PPS
I
ST
IC15
PPS
PPS
I
ST
IC16
PPS
PPS
I
ST
Pin Name
Description
Input Capture
Legend:
Input Capture Inputs 1-6
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2016-2021 Microchip Technology Inc.
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001402H-page 17
PIC32MK GP/MC Family
TABLE 1-5:
OC1 THROUGH OC16 PINOUT I/O DESCRIPTIONS
Pin Number
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
Buffer
Type
OC1
PPS
PPS
O
—
OC2
PPS
PPS
O
—
OC3
PPS
PPS
O
—
OC4
PPS
PPS
O
—
OC5
PPS
PPS
O
—
OC6
PPS
PPS
O
—
OC7
PPS
PPS
O
—
OC8
PPS
PPS
O
—
OC9
PPS
PPS
O
—
OC10
PPS
PPS
O
—
Pin Name
Description
Output Compare
Output Compare Outputs 1-16
OC11
PPS
PPS
O
—
OC12
PPS
PPS
O
—
OC13
PPS
PPS
O
—
OC14
PPS
PPS
O
—
OC15
PPS
PPS
O
—
OC16
PPS
PPS
O
—
OCFA
PPS
PPS
I
ST
Output Compare Fault A Input
OCFB
PPS
PPS
I
ST
Output Compare Fault B Input
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-6:
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
EXTERNAL INTERRUPTS PINOUT I/O DESCRIPTIONS
Pin Number
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
Buffer
Type
INT0
72
46
I
ST
External Interrupt 0
INT1
PPS
PPS
I
ST
External Interrupt 1
INT2
PPS
PPS
I
ST
External Interrupt 2
INT3
PPS
PPS
I
ST
External Interrupt 3
INT4
PPS
PPS
I
ST
External Interrupt 4
Pin Name
Description
External Interrupts
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001402H-page 18
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 1-7:
PORTA THROUGH PORTG PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
RA0
RA1
RA4
RA7
RA8
RA10
RA11
RA12
RA14
RA15
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
Buffer
Type
22
23
51
3
49
100
21
20
66
67
13
14
33
1
31
64
12
11
—
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
RB0
24
15
I/O
RB1
25
16
I/O
ST
ST
RB2
26
17
I/O
RB3
27
18
I/O
ST
RB4
50
32
I/O
ST
RB5
69
43
I/O
ST
RB6
70
44
I/O
ST
RB7
72
46
I/O
ST
ST
RB8
74
48
I
RB9
76
49
I/O
ST
60
I/O
ST
61
I/O
ST
ST
RB10
RB11
93
94
RB12
98
62
I/O
RB13
99
63
I/O
ST
RB14
4
2
I/O
ST
RB15
5
3
I/O
ST
RC0
RC1
RC2
RC6
RC7
RC8
RC9
RC10
RC11
RC12
RC13
RC15
Legend:
Note 1:
2:
3:
Description
PORTA
PORTA is a bidirectional I/O port
PORTB
PORTB is a bidirectional I/O port
PORTC
32
21
I/O
ST
PORTC is a bidirectional I/O port
33
22
I/O
ST
34
23
I/O
ST
77
50
I/O
ST
78
51
I/O
ST
81
52
I/O
ST
84
55
I/O
ST
71
45
I/O
ST
35
24
I/O
ST
63
39
I/O
ST
73
47
I
ST
64
40
I/O
ST
CMOS = CMOS-compatible input or output
Analog = Analog input
ST = Schmitt Trigger input with CMOS levels
O = Output
TTL = Transistor-transistor Logic input buffer
PPS = Peripheral Pin Select
This function does not exist on 100-pin general purpose devices.
This function does not exist on 64-pin general purpose devices.
This function does not exist on any general purpose devices.
2016-2021 Microchip Technology Inc.
P = Power
I = Input
DS60001402H-page 19
PIC32MK GP/MC Family
TABLE 1-7:
PORTA THROUGH PORTG PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
Buffer
Type
RD1
RD2
RD3
RD4
RD5
RD6
RD8(3)
RD12
RD13
RD14
RD15
6
7
8
9
82
83
68
79
80
47
48
—
—
—
—
53
54
42
—
—
—
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
RE0
RE1
RE8
RE9
RE12
RE13
RE14
RE15
52
53
18
19
41
42
43
44
—
—
—
—
27
28
29
30
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
Pin Name
RF0
RF1
RF5
RF6
RF7
RF9
RF10
RF12
RF13
Legend:
Note 1:
2:
3:
Description
PORTD
PORTD is a bidirectional I/O port
PORTE
PORTE is a bidirectional I/O port
PORTF
87
58
I/O
ST
PORTF is a bidirectional I/O port
88
59
I/O
ST
61
—
I/O
ST
91
—
I/O
ST
92
—
I/O
ST
28
—
I/O
ST
29
—
I/O
ST
40
—
I/O
ST
39
—
I/O
ST
CMOS = CMOS-compatible input or output
Analog = Analog input
ST = Schmitt Trigger input with CMOS levels
O = Output
TTL = Transistor-transistor Logic input buffer
PPS = Peripheral Pin Select
This function does not exist on 100-pin general purpose devices.
This function does not exist on 64-pin general purpose devices.
This function does not exist on any general purpose devices.
DS60001402H-page 20
P = Power
I = Input
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 1-7:
PORTA THROUGH PORTG PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
RG0
RG1
RG6
RG7
RG8
RG9
RG10
RG11
RG12
RG13
RG14
RG15
Legend:
Note 1:
2:
3:
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
Buffer
Type
Description
PORTG
90
—
I/O
ST
PORTG is a bidirectional I/O port
89
—
I/O
ST
10
4
I/O
ST
11
5
I/O
ST
12
6
I/O
ST
14
8
I/O
ST
17
—
I/O
ST
38
—
I/O
ST
96
—
I/O
ST
97
—
I/O
ST
95
—
I/O
ST
1
—
I/O
ST
CMOS = CMOS-compatible input or output
Analog = Analog input
ST = Schmitt Trigger input with CMOS levels
O = Output
TTL = Transistor-transistor Logic input buffer
PPS = Peripheral Pin Select
This function does not exist on 100-pin general purpose devices.
This function does not exist on 64-pin general purpose devices.
This function does not exist on any general purpose devices.
2016-2021 Microchip Technology Inc.
P = Power
I = Input
DS60001402H-page 21
PIC32MK GP/MC Family
TABLE 1-8:
UART1 THROUGH UART6 PINOUT I/O DESCRIPTIONS
Pin Number
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
U1RX
PPS
PPS
I
ST
U1TX
PPS
PPS
O
—
UART1 Transmit
U1CTS
PPS
PPS
I
ST
UART1 Clear to Send
U1RTS
PPS
PPS
O
—
UART1 Ready to Send
Pin Name
Buffer
Type
Description
Universal Asynchronous Receiver Transmitter 1
UART1 Receive
Universal Asynchronous Receiver Transmitter 2
U2RX
PPS
PPS
I
ST
U2TX
PPS
PPS
O
—
UART2 Receive
UART2 Transmit
U2CTS
PPS
PPS
I
ST
UART2 Clear To Send
U2RTS
PPS
PPS
O
—
UART2 Ready To Send
Universal Asynchronous Receiver Transmitter 3
U3RX
PPS
PPS
I
ST
U3TX
PPS
PPS
O
—
UART3 Receive
UART3 Transmit
U3CTS
PPS
PPS
I
ST
UART3 Clear to Send
U3RTS
PPS
PPS
O
—
UART3 Ready to Send
Universal Asynchronous Receiver Transmitter 4
U4RX
PPS
PPS
I
ST
U4TX
PPS
PPS
O
—
UART4 Receive
UART4 Transmit
U4CTS
PPS
PPS
I
ST
UART4 Clear to Send
U4RTS
PPS
PPS
O
—
UART4 Ready to Send
Universal Asynchronous Receiver Transmitter 5
U5RX
PPS
PPS
I
ST
U5TX
PPS
PPS
O
—
UART5 Receive
UART5 Transmit
U5CTS
PPS
PPS
I
ST
UART5 Clear to Send
U5RTS
PPS
PPS
O
—
UART5 Ready to Send
Universal Asynchronous Receiver Transmitter 6
U6RX
PPS
PPS
I
ST
U6TX
PPS
PPS
O
—
UART6 Transmit
U6CTS
PPS
PPS
I
ST
UART6 Clear to Send
PPS
PPS
O
—
UART6 Ready to Send
U6RTS
Legend:
UART6 Receive
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001402H-page 22
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 1-9:
SPI1 THROUGH SPI 6 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
72
46
I/O
Buffer
Type
Description
Serial Peripheral Interface 1
SCK1
ST/CMOS SPI1 Synchronous Serial Clock Input/Output
SDI1
PPS
PPS
I
ST
SDO1
PPS
PPS
O
CMOS
SPI1 Data In
SS1
PPS
PPS
I/O
ST/CMOS SPI1 Client Synchronization Or Frame Pulse I/O
70
44
I/O
ST/CMOS SPI2 Synchronous Serial Clock Input/output
SPI1 Data Out
Serial Peripheral Interface 2
SCK2
SDI2
PPS
PPS
I
ST
SDO2
PPS
PPS
O
CMOS
SPI2 Data In
SS2
PPS
PPS
I/O
ST/CMOS SPI2 Client Synchronization Or Frame Pulse I/O
SCK3
PPS
PPS
I/O
ST/CMOS SPI3 Synchronous Serial Clock Input/Output
SPI2 Data Out
Serial Peripheral Interface 3
SDI3
PPS
PPS
I
ST
SDO3
PPS
PPS
O
CMOS
SPI3 Data In
SS3
PPS
PPS
I/O
ST/CMOS SPI3 Client Synchronization Or Frame Pulse I/O
SCK4
PPS
PPS
I/O
ST/CMOS SPI4 Synchronous Serial Clock Input/Output
SPI3 Data Out
Serial Peripheral Interface 4
SDI4
PPS
PPS
I
ST
SDO4
PPS
PPS
O
CMOS
SPI4 Data In
SS4
PPS
PPS
I/O
ST/CMOS SPI4 Client Synchronization Or Frame Pulse I/O
SCK5
PPS
PPS
I/O
ST/CMOS SPI5 Synchronous Serial Clock Input/Output
SPI4 Data Out
Serial Peripheral Interface 5
SDI5
PPS
PPS
I
ST
SDO5
PPS
PPS
O
CMOS
SPI5 Data In
SS5
PPS
PPS
I/O
ST/CMOS SPI5 Client Synchronization Or Frame Pulse I/O
SCK6
PPS
PPS
I/O
ST/CMOS SPI6 Synchronous Serial Clock Input/Output
SPI5 Data Out
Serial Peripheral Interface 6
SDI6
PPS
PPS
I
ST
SDO6
PPS
PPS
O
CMOS
PPS
PPS
I/O
SS6
Legend:
SPI6 Data In
SPI6 Data Out
ST/CMOS SPI6 Client Synchronization Or Frame Pulse I/O
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2016-2021 Microchip Technology Inc.
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001402H-page 23
PIC32MK GP/MC Family
TABLE 1-10:
TIMER1 THROUGH TIMER9 AND RTCC PINOUT I/O DESCRIPTIONS
Pin Number
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
Buffer
Type
T1CK
51
33
I
ST
Timer1 External Clock Input
T2CK
PPS
PPS
I
ST
Timer2 External Clock Input
T3CK
PPS
PPS
I
ST
Timer3 External Clock Input
T4CK
PPS
PPS
I
ST
Timer4 External Clock Input
T5CK
PPS
PPS
I
ST
Timer5 External Clock Input
T6CK
PPS
PPS
I
ST
Timer6 External Clock Input
T7CK
PPS
PPS
I
ST
Timer7 External Clock Input
T8CK
PPS
PPS
I
ST
Timer8 External Clock Input
T9CK
PPS
PPS
I
ST
Timer9 External Clock Input
Pin Name
Description
Timer1 through Timer9
Real-Time Clock and Calendar
RTCC
Legend:
27
18
O
—
Real-Time Clock Alarm/Seconds Output (not in VBAT power domain,
requires VDD
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001402H-page 24
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 1-11:
Pin Name
PMP PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
Description
100-pin
TQFP
64-pin
QFN/
TQFP
PMA0
44
30
O
PMA1
43
29
O
TTL/CMOS Parallel Host Port Address (Demultiplexed Host mode) or Address/Data
(Multiplexed Host modes)
TTL/CMOS
PMA2
14
8
O
TTL/CMOS
PMA3
12
6
O
TTL/CMOS
PMA4
11
5
O
TTL/CMOS
PMA5
10
4
O
TTL/CMOS
PMA6
29
16
O
TTL/CMOS
PMA7
28
22
O
TTL/CMOS
PMA8
50
32
O
TTL/CMOS
PMA9
49
31
O
TTL/CMOS
PMA10
42
28
O
TTL/CMOS
PMA11
41
27
O
TTL/CMOS
PMA12
35
24
O
TTL/CMOS
PMA13
34
23
O
TTL/CMOS
PMA14
71
45
O
TTL/CMOS
PMA15
70
44
O
TTL/CMOS
PMA16
77
—
O
TTL/CMOS
PMA17
78
—
O
TTL/CMOS
PMA18
91
—
O
TTL/CMOS
PMA19
92
—
O
TTL/CMOS
PMA20
95
—
O
TTL/CMOS
PMA21
96
—
O
TTL/CMOS
PMA22
97
—
O
TTL/CMOS
PMA23
1
—
O
TTL/CMOS
PMCS1
71
45
O
TTL/CMOS Parallel Host Port Chip Select 1 for PMA(13:0)
PMCS2
70
44
O
TTL/CMOS Parallel Host Port Chip Select 2 for PMA(14:0)
PMPRD
82
53
O
TTL/CMOS Parallel Host Port Read Strobe
PMWR
81
52
O
TTL/CMOS Parallel Host Port Write Strobe
PMCS1A
97
—
O
TTL/CMOS Parallel Host Port Chip Select 1 for PMA(21:0)
PMCS2A
Legend:
1
—
O
TTL/CMOS Parallel Host Port Chip Select 2 for PMA(22:0)
CMOS = CMOS-compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = Transistor-transistor Logic input buffer
PPS = Peripheral Pin Select
2016-2021 Microchip Technology Inc.
DS60001402H-page 25
PIC32MK GP/MC Family
TABLE 1-11:
Pin Name
PMD0
PMP PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Description
Parallel Host Port Data (Demultiplexed Host mode) or Address/Data (Multiplexed Host modes)
100-pin
TQFP
64-pin
QFN/
TQFP
93
60
I/O
TTL/ST
TTL/ST
PMD1
94
61
I/O
PMD2
98
62
I/O
TTL/ST
PMD3
99
63
I/O
TTL/ST
PMD4
100
64
I/O
TTL/ST
1
I/O
TTL/ST
2
I/O
TTL/ST
PMD5
PMD6
3
4
PMD7
5
3
I/O
TTL/ST
PMD8
90
—
I/O
TTL/ST
—
I/O
TTL/ST
TTL/ST
PMD9
89
PMD10
88
—
I/O
PMD11
87
—
I/O
TTL/ST
PMD12
79
—
I/O
TTL/ST
—
I/O
TTL/ST
TTL/ST
PMD13
80
PMD14
83
—
I/O
PMD15
84
43
—
29
I/O
PMALH
PMALL
44
30
O
Legend:
O
TTL/ST
TTL/CMOS Parallel Host Port Address Latch Enable High Byte (Multiplexed Host
modes)
—
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001402H-page 26
Parallel Host Port Address Latch Enable Low Byte (Multiplexed Host
modes)
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 1-12:
COMPARATOR 1 THROUGH COMPARATOR 5 PINOUT I/O DESCRIPTIONS
Pin Number
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
Buffer
Type
C1IN1+
26
17
I
Analog
Comparator 1 Positive Input
C1IN1-
27
18
I
Analog
Comparator 1 Negative Input 1-4
C1IN2-
35
24
I
Analog
C1IN3-
26
17
I
Analog
C1IN4-
25
16
I
Analog
C1OUT
PPS
PPS
O
—
C2IN1+
23
14
I
Analog
Comparator 2 Positive Input
C2IN1-
24
15
I
Analog
Comparator 2 Negative Input 1-4
C2IN2-
41
27
I
Analog
C2IN3-
26
17
I
Analog
C2IN4-
22
13
I
Analog
C2OUT
PPS
PPS
O
—
C3IN1+
34
23
I
Analog
Comparator 3 Positive Input
C3IN1-
33
22
I
Analog
Comparator 3 Negative Input 1-4
C3IN2-
42
28
I
Analog
C3IN3-
34
23
I
Analog
C3IN4-
32
21
I
Analog
C3OUT
PPS
PPS
O
—
C4IN1+
32
21
I
Analog
Comparator 4 Positive Input
C4IN1-
33
22
I
Analog
Comparator 4 Negative Input 1-4
C4IN2-
25
16
I
Analog
C4IN3-
22
13
I
Analog
C4IN4-
32
21
I
Analog
C4OUT
PPS
PPS
O
—
C5IN1+
51
33
I
Analog
Comparator 5 Positive Input
C5IN1-
76
49
I
Analog
Comparator 5 Negative Input 1-4
C5IN2-
41
27
I
Analog
C5IN3-
51
33
I
Analog
C5IN4-
72
46
I
Analog
C1OUT
PPS
PPS
O
—
Pin Name
Description
Comparator 1
Comparator 1 Output
Comparator 2
Comparator 2 Output
Comparator 3
Comparator 3 Output
Comparator 4
Comparator 4 Output
Comparator 5
Legend:
Comparator 5 Output
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2016-2021 Microchip Technology Inc.
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001402H-page 27
PIC32MK GP/MC Family
TABLE 1-13:
OP AMP 1 THROUGH OP AMP 3, AND OP AMP 5 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
Buffer
Type
Description
Op amp 1
OA1OUT
25
16
O
Analog
Op amp 1 Output
OA1IN+
26
17
I
Analog
Op amp 1 Positive Input
OA1IN-
27
18
I
Analog
Op amp 1 Negative Input
OA2OUT
22
13
O
Analog
Op amp 2 Output
OA2IN+
23
14
I
Analog
Op amp 2 Positive Input
OA2IN-
24
15
I
Analog
Op amp 2 Negative Input
OA3OUT
32
21
O
Analog
Op amp 3 Output
OA3IN+
34
23
I
Analog
Op amp 3 Positive Input
OA3IN-
33
22
I
Analog
Op amp 3 Negative Input
OA5OUT
72
46
O
Analog
Op amp 5 Output
OA5IN+
51
33
I
Analog
Op amp 5 Positive Input
Op amp 2
Op amp 3
Op amp 5
OA5INLegend:
76
49
I
Analog Op amp 5 Negative Input
CMOS = CMOS-compatible input or output
Analog = Analog input
ST = Schmitt Trigger input with CMOS levels
O = Output
TTL = Transistor-transistor Logic input buffer
PPS = Peripheral Pin Select
TABLE 1-14:
P = Power
I = Input
CAN1 THROUGH CAN4 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
(see Note 1) 100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
Buffer
Type
Description
C1TX
PPS
PPS
O
—
CAN1 Bus Transmit Pin
C1RX
PPS
PPS
I
ST
CAN1 Bus Receive Pin
C2TX
PPS
PPS
O
—
CAN2 Bus Transmit Pin
C2RX
PPS
PPS
I
ST
CAN2 Bus Receive Pin
C3TX
PPS
PPS
O
—
CAN3 Bus Transmit Pin
C3RX
PPS
PPS
I
ST
CAN3 Bus Receive Pin
C4TX
PPS
PPS
O
—
CAN4 Bus Transmit Pin
C4RX
PPS
PPS
I
ST
CAN4 Bus Receive Pin
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
Note 1:
This function does not exist on PIC32MKXXXGPDXXX devices.
DS60001402H-page 28
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 1-15:
USB1 AND USB2 PINOUT I/O DESCRIPTIONS
Pin Number
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
VUSB3V3
55
35
P
—
VBUS1
54
34
I
Analog
USB1 Bus Power Monitor (Tied to VSS if USB1 not used.)
VBUSON1
4
2
O
CMOS
USB1 VBUS Power Control Output
VBUSON2
10
—
O
CMOS
USB2 VBUS Power Control Output
D1+
57
37
I/O
Analog
USB1 D+ (Connect through 10K to VSS if USB1 not used.)
USB1 D-(Connect through 10K to VSS if USB1 not used.)
Pin Name
Buffer
Type
Description
USB internal transceiver supply. This pin should be connected to VDD.
D1-
56
36
I/O
Analog
USBID1
69
43
I
ST
VBUS2
58
—
I
Analog
USB2 Bus Power Monitor (Tied to VSS if USB2 not used.)
D2+
60
—
I/O
Analog
USB2 D+ (Connect through 10K to VSS if USB2 not used.)
D2-
59
—
I/O
Analog
USB2 D- (Connect through 10K to VSS if USB2 not used.)
USBID2
77
—
I
ST
Legend:
USB1 OTG ID Detect
USB2 OTG ID detect
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-16:
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
CTMU PINOUT I/O DESCRIPTIONS
Pin Number
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
Buffer
Type
CTED1
25
16
I
ST
CTMU External Edge Input 1
CTED2
24
15
I
ST
CTMU External Edge Input 2
CTCMP
27
18
I
Analog
CTMU external capacitor input for pulse generation
CTPLS
PPS
PPS
O
CMOS
CTMU Pulse Generator Output
Pin Name
Legend:
Description
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-17:
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
CDAC1 THROUGH CDAC3 PINOUT I/O DESCRIPTIONS
Pin Number
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
Buffer
Type
CDAC1
51
33
O
Analog
12-bit CDAC1 output
CDAC2
71
45
O
Analog
12-bit CDAC2 output
CDAC3
49
31
O
Analog
12-bit CDAC3 output
Pin Name
Legend:
Description
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2016-2021 Microchip Technology Inc.
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001402H-page 29
PIC32MK GP/MC Family
TABLE 1-18:
MCPWM1 THROUGH MCPWM12 PINOUT I/O DESCRIPTIONS (MOTOR CONTROL
DEVICES ONLY)
Pin Number
Pin Name
PWM1H
100- 64-Pin Pin Buffer
QFN/ Type Type
Pin
TQFP TQFP
4
2
O
Description
CMOS MCPWM1 High Side Output
PWM1L
5
3
O
CMOS MCPWM1 Low Side Output (Only if PWMAPIN1 (CFGCON) = 0, default)
PWM2H
98
62
O
CMOS MCPWM2 High Side Output
PWM2L
99
63
O
CMOS MCPWM2 Low Side Output (Only if PWMAPIN2 (CFGCON) = 0, default)
PWM3H
93
60
O
CMOS MCPWM3 High Side Output
PWM3L
94
61
O
CMOS MCPWM3 Low Side Output (Only if PWMAPIN3 (CFGCON) = 0, default)
PWM4H
100
64
O
CMOS MCPWM4 High Side Output
PWM4L
3
1
O
CMOS MCPWM4 Low Side Output (Only if PWMAPIN4 (CFGCON) = 0, default)
PWM5H
7
52
O
CMOS MCPWM5 High Side Output
PWM5L
6
55
O
CMOS MCPWM5 Low Side Output (Only if PWMAPIN5 (CFGCON) = 0, default)
PWM6H
9
50
O
CMOS MCPWM6 High Side Output
PWM6L
8
51
O
CMOS MCPWM6 Low Side Output (Only if PWMAPIN6 (CFGCON) = 0, default)
PWM7H
5
3
O
CMOS If PWMAPIN1 (CFGCON) = 1), PWM1L is replaced by PWM7H.
PWM8H
99
63
O
CMOS If PWMAPIN2 (CFGCON) = 1), PWM2L is replaced by PWM8H.
PWM9H
94
61
O
CMOS If PWMAPIN3 (CFGCON) = 1), PWM3L is replaced by PWM9H.
PWM10H
3
1
O
CMOS If PWMAPIN4 (CFGCON) = 1), PWM4L is replaced by PWM10H.
PWM11H
87
55
O
CMOS MCPWM11 High Side Output
6
58
O
CMOS If PWMAPIN5 (CFGCON) = 1), PWM5L is replaced by PWM11H.
PWM11L
88
59
O
CMOS MCPWM11 Low Side Output
PWM12H
82
51
O
CMOS MCPWM12 High Side Output
8
55
O
CMOS If PWMAPIN6 (CFGCON) = 1), PWM6L is replaced by PWM12H.
83
54
O
CMOS MCPWM12 Low Side Output
PWM12L
Legend:
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-Transistor Logic input buffer
DS60001402H-page 30
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 1-19:
MCPWM FAULT, CURRENT-LIMIT, AND DEAD TIME COMPENSATION PINOUT I/O
DESCRIPTIONS (MOTOR CONTROL DEVICES ONLY)
Pin Number
Pin Name
100-Pin
TQFP
64-Pin
QFN/
TQFP
Pin
Type
Buffer
Type
FLT1
PPS
PPS
I
ST
FLT2
PPS
PPS
I
ST
FLT3
34
23
I
ST
FLT4
35
24
I
ST
FLT5
41
27
I
ST
FLT6
42
28
I
ST
FLT7
43
29
I
ST
FLT8
44
30
I
ST
FLT15
50
32
I
ST
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-Transistor Logic input buffer
2016-2021 Microchip Technology Inc.
Description
PWM Fault Input Control
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001402H-page 31
PIC32MK GP/MC Family
TABLE 1-20:
QEI1 THROUGH QEI6 PINOUT I/O DESCRIPTIONS (MOTOR CONTROL DEVICES
ONLY)
Pin Number
Pin Name
QEA1
QEB1
INDX1
HOME1
QEICMP1
QEA2
QEB2
INDX2
HOME2
QEICMP2
QEA3
QEB3
INDX3
HOME3
QEICMP3
QEA4
QEB4
INDX4
HOME4
QEICMP4
QEA5
QEB5
INDX5
HOME5
QEICMP5
QEA6
QEB6
INDX6
HOME6
QEICMP6
Legend:
100-Pin
TQFP
64-Pin
QFN/
TQFP
Pin
Type
Buffer
Type
Description
Quadrature Encoder Interface 1
QEI1 Phase A Input in QEI mode
QEI1 Phase B Input in QEI Mode. Auxiliary timer external clock/gate input in
Timer mode.
PPS
PPS
I
ST
QEI1 Index Pulse Input
PPS
PPS
I
ST
QEI1 Position Counter Input Capture Trigger Control
PPS
PPS
O
CMOS QEI1 Capture Compare Match Output
Quadrature Encoder Interface 2
PPS
PPS
I
ST
QEI2 Phase A Input in QEI mode
PPS
PPS
I
ST
QEI2 Phase B Input in QEI Mode. Auxiliary timer external clock/gate input in
Timer mode.
PPS
PPS
I
ST
QEI2 Index Pulse Input
PPS
PPS
I
ST
QEI2 Position Counter Input Capture Trigger Control
PPS
PPS
O
CMOS QEI2 Capture Compare Match Output
Quadrature Encoder Interface 3
PPS
PPS
I
ST
QEI3 Phase A Input in QEI mode
PPS
PPS
I
ST
QEI3 Phase B Input in QEI Mode. Auxiliary timer external clock/gate input in
Timer mode.
PPS
PPS
I
ST
QEI3 Index Pulse Input
PPS
PPS
I
ST
QEI3 Position Counter Input Capture Trigger Control
PPS
PPS
O
CMOS QEI3 Capture Compare Match Output
Quadrature Encoder Interface 4
PPS
PPS
I
ST
QEI4 Phase A Input in QEI mode
PPS
PPS
I
ST
QEI4 Phase B Input in QEI Mode. Auxiliary timer external clock/gate input in
Timer mode.
PPS
PPS
I
ST
QEI4 Index Pulse Input
PPS
PPS
I
ST
QEI4 Position Counter Input Capture Trigger Control
PPS
PPS
O
CMOS QEI4 Capture Compare Match Output
Quadrature Encoder Interface 5
PPS
PPS
I
ST
QAI5 Phase A Input in QEI mode
PPS
PPS
I
ST
QAI5 Phase B Input in QEI Mode. Auxiliary timer external clock/gate input in
Timer mode.
PPS
PPS
I
ST
QAI5 Index Pulse Input
PPS
PPS
I
ST
QAI5 Position Counter Input Capture Trigger Control
PPS
PPS
O
CMOS QAI5 Capture Compare Match Output
Quadrature Encoder Interface 6
PPS
PPS
I
ST
QEI6 Phase A Input in QEI mode
PPS
PPS
I
ST
QEI6 Phase B Input in QEI Mode. Auxiliary timer external clock/gate input in
Timer mode.
PPS
PPS
I
ST
QEI6 Index Pulse Input
PPS
PPS
I
ST
QEI6 Position Counter Input Capture Trigger Control
PPS
PPS
O
CMOS QEI6 Capture Compare Match Output
CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = Transistor-Transistor Logic input buffer
PPS = Peripheral Pin Select
PPS
PPS
DS60001402H-page 32
PPS
PPS
I
I
ST
ST
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 1-21:
POWER, GROUND, AND VOLTAGE REFERENCE PINOUT I/O DESCRIPTIONS
Pin Number
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
Buffer
Type
AVDD
30
19
P
P
AVSS
31
20
P
P
P
—
P
—
P
P
Pin Name
VDD
VSS
VBAT(1)
2, 16, 37, 10, 26,
46, 62, 86 38, 57
15, 36, 9, 25, 41,
56
45, 65,
75, 85
68
42
Description
Power and Ground
Positive supply for analog modules. This pin must be connected at all
times.
Ground reference for analog modules. This pin must be connected at all
times.
Positive supply for peripheral logic and I/O pins. This pin must be connected at all times.
Ground reference for logic, I/O pins, and USB. This pin must be connected
at all times.
VREF+
VREFLegend:
Battery backup for selected peripherals; otherwise connect to VDD.
Voltage Reference
29
16
I
Analog Analog Voltage Reference (High) Input
28
15
I
Analog Analog Voltage Reference (Low) Input
CMOS = CMOS-compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = Transistor-transistor Logic input buffer
PPS = Peripheral Pin Select
Note
VBAT functionality is compromised, see errata for additional information. This pin should be connected to VDD.
1:
2016-2021 Microchip Technology Inc.
DS60001402H-page 33
PIC32MK GP/MC Family
TABLE 1-22:
JTAG, TRACE, AND PROGRAMMING/DEBUGGING PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
100-pin
TQFP
64-pin
QFN/
TQFP
Pin
Type
Buffer
Type
3
1
I
ST
Description
JTAG
TCK
JTAG Test Clock Input Pin
TDI
49
31
I
ST
JTAG Test Data Input Pin
TDO
100
64
O
—
JTAG Test Data Output Pin
TMS
76
49
I
ST
JTAG Test Mode Select Pin
CMOS
Trace Clock
Trace Data bits 0-3
Trace support is available through the MPLAB® REAL ICE™ In-circuit
Emulator.
Trace
TRCLK
91
50
O
TRD0
97
54
O
CMOS
TRD1
96
53
O
CMOS
TRD2
95
52
O
CMOS
TRD3
92
51
O
CMOS
18
I/O
ST
Data I/O pin for Programming/Debugging Communication Channel 1
ST
Clock input pin for Programming/Debugging Communication Channel 1
Programming/Debugging
PGED1
27
PGEC1
26
17
I
PGED2
69
43
I/O
ST
Data I/O pin for Programming/Debugging Communication Channel 2
PGEC2
70
44
I
ST
Clock input pin for Programming/Debugging Communication Channel 2
PGED3
24
15
I/O
ST
Data I/O pin for Programming/Debugging Communication Channel 3
16
7
I
ST
Clock input pin for Programming/Debugging Communication Channel 3
I
ST
Host Clear (Reset) input. This pin is an active-low Reset to the device.
PGEC3
MCLR
Legend:
25
13
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001402H-page 34
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
NOTES:
2016-2021 Microchip Technology Inc.
DS60001402H-page 35
PIC32MK GP/MC Family
2.0
Note:
2.1
GUIDELINES FOR GETTING
STARTED WITH 32-BIT MCUS
This data sheet summarizes the features
of the PIC32MK GP/MC family of devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
documents listed in the Documentation >
Reference Manual section of the Microchip PIC32 web site (www.microchip.com/
pic32).
Basic Connection Requirements
Getting started with the PIC32MK GP/MC family of 32bit Microcontrollers (MCUs) requires attention to a
minimal set of device pin connections before
proceeding with development. The following is a list of
pin names, which must always be connected:
• All VDD and VSS pins (see 2.2 “Decoupling
Capacitors”)
• All AVDD and AVSS pins, even if the ADC module is
not used (see 2.2 “Decoupling Capacitors”)
• MCLR pin (see 2.3 “Host Clear (MCLR) Pin”)
• PGECx/PGEDx pins, used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see 2.4 “ICSP Pins”)
• OSC1 and OSC2 pins, when external oscillator
source is used (see 2.7 “External Oscillator Pins”)
The following pins may be required:
VREF+/VREF- pins, used when external voltage
reference for the ADC module is implemented.
Note:
The AVDD and AVSS pins must be
connected, regardless of ADC use and
the ADC voltage reference source.
DS60001402H-page 36
2.2
Decoupling Capacitors
The use of decoupling capacitors on power supply
pins, such as VDD, VSS, AVDD and AVSS is required.
See Figure 2-1.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A value of 0.1 µF
(100 nF), 10-20V is recommended. The capacitor
should be a low Equivalent Series Resistance
(low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is
further recommended that ceramic capacitors be
used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended that
the capacitors be placed on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within onequarter inch (6 mm) in length.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
VDD
10K
R1
MCLR
C
0.1 µF
VUSB3V3(1)
PIC32MK
VDD
VSS
Connect(2)
Note
VDD
AVSS
AVDD
VDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
VSS
1K
0.1 µF
Ceramic
VSS
VDD
0.1 µF
Ceramic
2.3
Host Clear (MCLR) Pin
The MCLR
functions:
pin
provides
specific
device
• Device Reset
• Device programming and debugging
Pulling The MCLR pin low generates a device Reset.
Figure 2-2 illustrates a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
For example, as illustrated in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
L1(2)
Place the components illustrated in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
1:
This pin must be connected to VDD, regardless of
whether the USB module is or is not used.
FIGURE 2-2:
2:
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 3 and the inductor
capacity greater than 10 mA.
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R
10k
R1(1)
Where:
(i.e., ADC conversion rate/2)
2
1
L = ----------------------
2f C
3:
Aluminum or electrolytic capacitors should not be
used. ESR 3 from -40ºC to 125ºC @ SYSCLK
frequency (i.e., MIPS).
0.1 µF(2)
ICSP™
F CNV
f = -------------2
1
f = ---------------------- 2 LC
2.2.1
two
Note
1
5
4
2
3
6
2016-2021 Microchip Technology Inc.
1 k
MCLR
PIC32
PGECx(3)
PGEDx(3)
1:
470 R1 1 K will limit any current flowing into
MCLR from the external capacitor C, in the event of
MCLR pin breakdown, due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS). Ensure that the
MCLR pin VIH and VIL specifications are met without
interfering with the Debug/Programmer tools.
2:
The capacitor can be sized to prevent unintentional
Resets from brief glitches or to extend the device
Reset period during POR.
3:
No pull-ups or bypass capacitors are allowed on
active debug/program PGECx/PGEDx pins.
BULK CAPACITORS
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.
VDD
VSS
NC
C
DS60001402H-page 37
PIC32MK GP/MC Family
2.4
ICSP Pins
The PGECx and PGEDx pins are used for ICSP and
debugging purposes. It is recommended to keep the
trace length between the ICSP connector and the ICSP
pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a
series resistor is recommended, with the value in the
range of a few tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 3 or MPLAB REAL ICE™.
For additional information on ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web
site.
• “Using MPLAB® ICD 3” (poster) DS50001765
• “MPLAB® ICD 3 Design Advisory” DS50001764
• “MPLAB® REAL ICE™ In-Circuit Debugger
User’s Guide” DS50001616
• “Using MPLAB® REAL ICE™ Emulator” (poster)
DS50001749
2.5
2.6
Trace
When present on select pin counts, the trace pins
can be connected to a hardware trace-enabled programmer to provide a compressed real-time instruction trace. When used for trace, the TRD3, TRD2,
TRD1, TRD0 and TRCLK pins should be dedicated
for this use. The trace hardware requires a 22 Ohm
series resistor between the trace pins and the trace
connector.
2.7
External Oscillator Pins
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 9.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same side
of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The
load capacitors should be placed next to the oscillator
itself, on the same side of the board. Use a grounded
copper pour around the oscillator circuit to isolate them
from surrounding circuits. The grounded copper pour
should be routed directly to the MCU ground. Do not
run any signal traces or power traces inside the ground
pour. Also, if using a two-sided board, avoid any traces
on the other side of the board where the crystal is
placed. A suggested layout is illustrated in Figure 2-3.
FIGURE 2-3:
SUGGESTED OSCILLATOR
CIRCUIT PLACEMENT
JTAG
The TMS, TDO, TDI and TCK pins are used for testing
and debugging according to the Joint Test Action
Group (JTAG) standard. It is recommended to keep the
trace length between the JTAG connector and the
JTAG pins on the device as short as possible. If the
JTAG connector is expected to experience an ESD
event, a series resistor is recommended, with the value
in the range of a few tens of Ohms, not to exceed 100
Ohms.
Oscillator
Secondary
Guard Trace
Guard Ring
Main Oscillator
Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended
as they will interfere with the programmer/debugger
communications to the device. If such discrete components are an application requirement, they should be
removed from the circuit during programming and
debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the
respective device Flash programming specification for
information on capacitive loading limits and pin input
voltage high (VIH) and input low (VIL) requirements.
DS60001402H-page 38
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
CRYSTAL OSCILLATOR DESIGN
CONSIDERATION
The following example assumptions are used to
calculate the Primary Oscillator loading capacitor
values:
•
•
•
•
CIN = PIC32_OSC2_Pin Capacitance = 4 pF
COUT = PIC32_OSC1_Pin Capacitance = 4 pF
PCB stray capacitance (i.e., 12 mm length) = 2.5 pF
C1 and C2 = the loading capacitors to use on
2.7.1.1
Additional Microchip References
• AN588 “PICmicro® Microcontroller Oscillator
Design Guide”
• AN826 “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
• AN849 “Basic PICmicro® Oscillator Design”
FIGURE 2-4:
your crystal circuit design to guarantee that the
effective capacitance as seen by the crystal in
circuit meets the crystal manufacturer
specification
PRIMARY CRYSTAL
OSCILLATOR CIRCUIT
RECOMMENDATIONS
Circuit A
C1
MFG Crystal Data Sheet CLOAD spec:
CLOAD = {( [Cin + C1] * [COUT + C2] ) / [Cin + C1 + C2
+ COUT] } + oscillator PCB stray capacitance
EXAMPLE 2-1: CRYSTAL LOAD CAPACITOR
CALCULATION
Rs
OSC2
Crystal manufacturer data sheet spec example: CLOAD = 15 pF
C2
2.7.1
OSC1
Circuit B
Not Recommended
Therefore:
MFG CLOAD = {( [CIN + C1] * [COUT + C2] ) / [CIN + C1 + C2 + COUT] }
+ estimated oscillator PCB stray capacitance
Assuming C1 = C2 and PIC32 Cin = Cout, the formula can be further
simplified and restated to solve for C1 and C2 by:
C1 = C2 = ((2 * MFG Cload spec) - Cin - (2 * PCB capacitance))
= ((2 * 15) - 4 - (2 * 2.5 pF))
RSHUNT
Rs
= (30 - 4 - 5)
= 21 pF
Therefore:
C1 = C2 = 21 pF is the correct loading capacitors to use on your crystal circuit design to guarantee that the effective capacitance as seen
by the crystal in circuit in this example is 15 pF to meet the crystal
manufacturer specification.
OSC2
Circuit C
Not Recommended
Tips to increase oscillator gain, (i.e., to increase peakto-peak oscillator signal):
• Select an crystal oscillator with a lower XTAL
manufacturing “ESR” rating.
• Add a parallel resistor across the crystal. The greater
the resistor value the greater the gain.
• C1 and C2 values also affect the gain of the oscillator.
The lower the values, the higher the gain.
• Likewise, C2/C1 ratio also affects gain. To increase
the gain, make C1 slightly smaller than C2, which will
also help start-up performance.
Note:
Do not add excessive gain such that the
oscillator signal is clipped, flat on top of
the sine wave. If so, you need to reduce
the gain or add a series resistor, RS, as
shown in circuit “A” in Figure 2-4. Failure
to do so will stress and age the crystal,
which can result in an early failure. When
measuring the oscillator signal you must
use an active-powered scope probe with
1 pF or the scope probe itself will unduly
change the gain and peak-to-peak levels.
2016-2021 Microchip Technology Inc.
OSC1
Rs
RSHUNT
OSC2
Note:
OSC1
Refer to the “PIC32MK GP/MC Family Silicon Errata and Data Sheet Clarification”
(DS80000737B), which is available for
download from the Microchip web site
(www.microchip.com)
for
the
recommended Rs values versus crystal/
frequency.
DS60001402H-page 39
PIC32MK GP/MC Family
2.8
Unused I/Os
2.9
Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
to a logic-low state.
2.9.1
Note:
NON-5V TOLERANT INPUT PINS
A quick review of the absolute maximum rating section
in 36.0 “Electrical Characteristics” will indicate that
the voltage on any non-5v tolerant pin may not exceed
VDD + 0.3V unless the input current is limited to meet
the respective injection current specifications defined
by parameters DI60a, DI60b, and DI60c in Table 3610: “DC Characteristics: I/O Pin Input Injection current Specifications”. Figure 2-5 shows an example of
a remote circuit using an independent power source,
which is powered while connected to a PIC32 non-5V
tolerant circuit that is not powered.
Alternatively, inputs can be reserved by connecting the
pin to VSS through a 1k resistor and configuring the pin
as an input.
FIGURE 2-5:
Considerations When Interfacing
to Remotely Powered Circuits
PIC32 NON-5V TOLERANT CIRCUIT EXAMPLE
When VDD power is OFF.
PIC32
Non-5V Tolerant
Pin Architecture
On/Off
VDD
ANSEL
I/O IN
AN2/RB0
I/O OUT
Remote
GND
TRIS
CPU LOGIC
Remote
0.3V dVIH d 3.6V
PIC32
POWER
SUPPLY
Current Flow
VSS
DS60001402H-page 40
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
FIGURE 2-6:
Opto Coupling
Analog/Digital Switch
EXAMPLES OF DIGITAL/
ANALOG ISOLATORS WITH
OPTIONAL LEVEL
TRANSLATION
Capacitive Coupling
TABLE 2-1:
Inductive Coupling
Without proper signal isolation, on non-5V tolerant
pins, the remote signal can actually power the PIC32
device through the high side ESD protection diodes.
Besides violating the absolute maximum rating
specification when VDD of the PIC32 device is
restored and ramping up or ramping down, it can
also negatively affect the internal Power-on Reset
(POR) and Brown-out Reset (BOR) circuits, which
can lead to improper initialization of internal PIC32
logic circuits. In these cases, it is recommended to
implement digital or analog signal isolation as
depicted in Figure 2-6, as appropriate. This is
indicative of all industry microcontrollers and not just
Microchip products.
ADuM7241 / 40 ARZ (1 Mbps)
X
—
—
—
ADuM7241 / 40 CRZ (25 Mbps)
X
—
—
—
ISO721
—
X
—
—
LTV-829S (2 Channel)
—
—
X
—
LTV-849S (4 Channel)
—
—
X
—
FSA266 / NC7WB66
—
—
—
X
Example Digital/Analog
Signal Isolation Circuits
EXAMPLE DIGITAL/ANALOG SIGNAL ISOLATION CIRCUITS
Conn
PIC32 VDD
Digital Isolator
External VDD
IN
REMOTE_IN
PIC32
PIC32 VDD
Digital Isolator
External VDD
REMOTE_IN
IN1
REMOTE_OUT
OUT1
PIC32
VSS
VSS
PIC32 VDD
Opto Digital
ISOLATOR
External VDD
PIC32 VDD
Analog / Digital Isolator
Conn
IN1
ENB
Analog_OUT2
PIC32
External_VDD1
ENB
PIC32
S
Analog_IN1
REMOTE_IN
Analog_IN2
Analog Switch
VSS
VSS
2016-2021 Microchip Technology Inc.
DS60001402H-page 41
PIC32MK GP/MC Family
2.9.2
5V TOLERANT INPUT PINS
The internal high side diode on 5v tolerant pins are
bussed to an internal floating node, rather than being
connected to VDD, as shown in Figure 2-7. Voltages
on these pins, if VDD < 2.3V, should not exceed
roughly 3.2V relative to VSS of the PIC32 device.
Voltage of 3.6V or higher will violate the absolute
maximum specification, and will stress the oxide
layer separating the high side floating node, which
impacts device reliability. If a remotely powered
“digital-only” signal can be guaranteed to always be
£ 3.2V relative to Vss on the PIC32 device side, a
5V tolerant pin could be used without the need for a
digital isolator. This is assuming there is not a
ground loop issue, logic ground of the two circuits
not at the same absolute level, and a remote logic
low input is not less than VSS - 0.3V.
FIGURE 2-7:
PIC32 5V TOLERANT PIN ARCHITECTURE EXAMPLE
PIC32
5V Tolerant Pin
Architecture
Floating Bus
Oxide BV = 3.6V
if VDD < 2.3V
OXIDE
On/Off
VDD
ANSEL
I/O IN
RG10
I/O OUT
Remote
GND
TRIS
CPU LOGIC
Remote
VIH = 2.5V
PIC32
POWER
SUPPLY
VSS
DS60001402H-page 42
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
2.10
Designing for High-Speed
Peripherals
The PIC32MK GP/MC family devices have peripherals
that operate at frequencies much higher than typical for
an embedded environment. Table 2-2 lists the peripherals that produce high-speed signals on their external
pins:
TABLE 2-2:
PERIPHERALS THAT
PRODUCE HS SIGNALS ON
EXTERNAL PINS
Peripheral
High-Speed Signal
Pins
Maximum
Speed on
Signal Pin
SPI/I2S
SCKx, SDOx, SDIx
50 MHz
REFCLKx
REFCLKx
50 MHz
Due to these high-speed signals, it is important to
consider several factors when designing a product that
uses these peripherals, as well as the PCB on which
these components will be placed. Adhering to these
recommendations will help achieve the following goals:
• Minimize the effects of electromagnetic interference
to the proper operation of the product
• Ensure signals arrive at their intended destination at
the same time
• Minimize crosstalk
• Maintain signal integrity
• Reduce system noise
• Minimize ground bounce and power sag
2.10.1
2.10.1.1
SYSTEM DESIGN
Impedance Matching
When selecting parts to place on high-speed buses,
particularly the SPI bus and/or REFCLKx output(s), if
the impedance of the peripheral device does not match
the impedance of the pins on the PIC32MK GP/MC
device to which it is connected, signal reflections could
result, thereby degrading the quality of the signal.
If it is not possible to select a product that matches
impedance, place a series resistor at the load to create
the matching impedance. See Figure 2-8 for an
example.
FIGURE 2-8:
SERIES RESISTOR
PIC32MK
50
2.10.1.2
• Component Placement
- Place bypass capacitors as close to their
component power and ground pins as possible,
and place them on the same side of the PCB
- Devices on the same bus that have larger setup
times should be placed closer to the PIC32MK
GP/MC device
• Power and Ground
- Multi-layer PCBs will allow separate power and
ground planes
- Each ground pin should be connected to the
ground plane individually
- Place bypass capacitor vias as close to the pad
as possible (preferably inside the pad)
- If power and ground planes are not used,
maximize width for power and ground traces
- Use low-ESR, surface-mount bypass capacitors
• Clocks and Oscillators
- Place crystals as close as possible to the
PIC32MK GP/MC device OSC/SOSC pins
- Do not route high-speed signals near the clock or
oscillator
- Avoid via usage and branches in clock lines
(SCK)
- Place termination resistors at the end of clock
lines
• Traces
- Higher-priority signals should have the shortest
traces
- Avoid long run lengths on parallel traces to reduce
coupling
- Make the clock traces as straight as possible
- Use rounded turns rather than right-angle turns
- Have traces on different layers intersect on right
angles to minimize crosstalk
- Maximize the distance between traces, preferably
no less than three times the trace width
- Power traces should be as short and as wide as
possible
- High-speed traces should be placed close to the
ground plane
SPI
Flash
Device
PCB Layout Recommendations
The following list contains recommendations that will
help ensure the PCB layout will promote the goals
previously listed.
2016-2021 Microchip Technology Inc.
DS60001402H-page 43
PIC32MK GP/MC Family
2.10.1.3
EMI/EMC/EFT (IEC 61000-4-4 and
IEC 61000-4-2) Suppression
Considerations
The use of LDO regulators is preferred to reduce
overall system noise and provide a cleaner power
source. However, when utilizing switching Buck/Boost
regulators as the local power source for PIC32MK GP
devices, as well as in electrically noisy environments or
test conditions required for IEC 61000-4-4 and IEC
61000-4-2, users should evaluate the use of T-Filters
(i.e., L-C-L) on the power pins, as shown in Figure 2-9.
In addition to a more stable power source, use of this
type of T-Filter can greatly reduce susceptibility to EMI
sources and events.
FIGURE 2-9:
EMI/EMC/EFT
SUPPRESSION CIRCUIT
Ferrite Chip SMD
DCR = 0.15ȍ(max)
600 ma ISAT
300ȍ@ 100 MHz
PN#:
VDD
0.01 µF
Ferrite
Chips
0.1 µF
VSS
VDD
VDD
VSS
0.1 µF
VSS
VDD
VSS
0.1 µF
PIC32M.
VSS
0.1 µF
0.1 µF
VDD
VSS
VDD
VSS
VUSB3V3
VDD
AVDD
AVSS
0.1 µF
VSS
VDD
0.1 µF
0.1 µF
0.1 µF
Ferrite
Chips
VDD
0.01 µF
DS60001402H-page 44
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
2.11
Typical Application Connection
Examples
Examples of typical application connections are shown
in Figure 2-10, Figure 2-11, and Figure 2-12.
FIGURE 2-10:
CAPACITIVE TOUCH SENSING WITH GRAPHICS APPLICATION
PIC32
Current Source
To AN6
To AN7
To AN8
To AN9
To AN11
To AN0
CTMU
AN0
AN1
ADC
R1
R1
R1
R1
C1
C2
C3
C4
C5
To AN1
Read the Touch Sensors
Microchip
mTouch™
Library
R1
R2
R2
R2
R2
R2
C1
C2
C3
C4
C5
R3
R3
R3
R3
R3
C1
C2
C3
C4
C5
AN9
To AN5
Process Samples
AN11
User
Application
Display Data
Microchip
Graphics
Library
FIGURE 2-11:
USB
Host
Parallel
Host
Port
LCD Controller
PMD
Display
Controller
Frame
Buffer
PMWR
LCD
Panel
AUDIO PLAYBACK APPLICATION
PMD
PMP
USB
Display
PMWR
PIC32
I2S
SPI
Stereo Headphones
3
REFCLKO
3
Audio
Codec
Speaker
3
MMC SD
SDI
2016-2021 Microchip Technology Inc.
DS60001402H-page 45
PIC32MK GP/MC Family
FIGURE 2-12:
LOW-COST CONTROLLERLESS (LCC) GRAPHICS APPLICATION WITH
PROJECTED CAPACITIVE TOUCH
PIC32
CTMU
ADC
ANx
Microchip mTouch™
GFX Libraries
DMA
LCD Display
Projected Capacitive
Touch Overlay
PMP
SRAM
DS60001402H-page 46
External Frame Buffer
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
NOTES:
2016-2021 Microchip Technology Inc.
DS60001402H-page 47
PIC32MK GP/MC Family
3.0
CPU
Note 1: This data sheet summarizes the features of the PIC32MK GP/MC family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 50. “CPU for
Devices with MIPS32® microAptiv™
and M-Class Cores” (DS60001192) of
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
2: The microAptiv™ CPU core resources
are available at: www.imgtec.com.
The MIPS32® microAptiv™ MCU Core is the heart of
the PIC32MK GP/MC family device processor. The
CPU fetches instructions, decodes each instruction,
fetches source operands, executes each instruction
and writes the results of instruction execution to the
proper destinations.
Key features include:
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32 Enhanced Architecture (Release 5):
- Multiply-accumulate and multiply-subtract
instructions
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow register to minimize latency for
interrupt handlers
- Bit field manipulation instructions
- Virtual memory support
• microMIPS™ compatible instruction set:
- Improves code size density over MIPS32, while
maintaining MIPS32 performance.
- Supports all MIPS32 instructions (except branchlikely instructions)
- Fifteen additional 32-bit instructions and 39 16-bit
instructions corresponding to commonly-used
MIPS32 instructions
- Stack pointer implicit in instruction
- MIPS32 assembly and ABI compatible
DS60001402H-page 48
• Autonomous Multiply/Divide Unit (MDU):
- Maximum issue rate of one 32x32 multiply per clock
- Early-in iterative divide. Minimum 12 and
maximum 38 clock latency (dividend (rs) sign
extension-dependent)
• Power Control:
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT instruction)
- Extensive use of local gated clocks
• EJTAG Debug and Instruction Trace:
- Support for single stepping
- Virtual instruction and data address/value
breakpoints
- Hardware breakpoint supports both address
match and address range triggering.
- Eight instruction and four data complex
breakpoints
• iFlowtrace® version 2.0 support:
- Real-time instruction program counter
- Special events trace capability
- Two performance counters with 34 userselectable countable events
- Disabled if the processor enters Debug mode
- Program Counter sampling
• DSP ASE Extension:
- Native fractional format data type operations
- Register Single Instruction Multiple Data (SIMD)
operations (add, subtract, multiply, shift)
- GPR-based shift
- Bit manipulation
- Compare-Pick
- DSP Control Access
- Indexed-Load
- Branch
- Multiplication of complex operands
- Variable bit insertion and extraction
- Virtual circular buffers
- Arithmetic saturation and overflow handling
- Zero-cycle overhead saturation and rounding
operations
• Floating Point Unit (FPU):
- 1985 IEEE-754 compliant Floating Point Unit
- Supports single and double precision datatypes
- 2008 IEEE-754 compatibility control of NaN
handling and Abs/Neg instructions
- Runs at 1:1 core/FPU clock ratio
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
A block diagram of the PIC32MK GP/MC family
processor core is shown in Figure 3-1.
FIGURE 3-1:
PIC32MK GP/MC FAMILY MICROPROCESSOR CORE BLOCK DIAGRAM
microAptiv™ MCU Core
PBCLK7
Decode
(MIPS32® microAptiv™
MCU Core)
microMIPS™
GPR
(Two Sets)
Execution Unit
ALU/Shift
Atomic/LdSt
DSP ASE
System
Interface
Enhanced MDU
(with DSP ASE)
FMT
(Fixed Map
Table)
BIU
System Bus
FPU
(Single & Double)
Debug/Profiling
System
Coprocessor
Interrupt
Interface
2-wire Debug
2016-2021 Microchip Technology Inc.
Break Points
iFlowtrace®
Fast Debug Channel
Performance Counters
Sampling
Secure Debug
Power
Management
EJTAG
DS60001402H-page 49
PIC32MK GP/MC Family
3.1
Architecture Overview
The MIPS32 microAptiv MCU core in the PIC32MK GP/
MC family devices contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are
included with the core:
•
•
•
•
•
•
•
•
Execution unit
General Purpose Register (GPR)
Multiply/Divide Unit (MDU)
System control coprocessor (CP0)
Floating Point Unit (FPU)
Power Management
microMIPS support
Enhanced JTAG (EJTAG) controller
3.1.1
3.1.2
MULTIPLY/DIVIDE UNIT (MDU)
The processor core includes a Multiply/Divide Unit
(MDU) that contains a separate pipeline for multiply
and divide operations, and DSP ASE multiply instructions. This pipeline operates in parallel with the Integer
Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially
masked by system stalls and/or other integer unit
instructions.
EXECUTION UNIT
The processor core execution unit implements a load/
store architecture with single-cycle ALU operations
(logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer
operations and address calculation. One additional
register file shadow sets (containing thirty-two registers) are added to minimize context switching overhead
during interrupt/exception processing. The register file
consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline.
The execution unit includes:
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
address
• Logic for branch determination and branch target
address calculation
• Load aligner
• Trap condition comparator
• Bypass multiplexers used to avoid stalls when
executing instruction streams where data
producing instructions are followed closely by
consumers of their results
TABLE 3-1:
• Leading Zero/One detect unit for implementing
the CLZ and CLO instructions
• Arithmetic Logic Unit (ALU) for performing arithmetic
and bitwise logical operations
• Shifter and store aligner
• DSP ALU and logic block for performing DSP
instructions, such as arithmetic/shift/compare
operations
The high-performance MDU consists of a 32x16 Booth
recoded multiplier, a pair of result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number
shown (‘32’ of 32x16) represents the rs operand. The
second number ‘16’ of 32x16) represents the rt
operand.
The MDU supports execution of one multiply or
multiply-accumulate operation every clock cycle.
Divide operations are implemented with a simple 1-bitper-clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For
a 16-bit wide rs, 15 iterations are skipped and for a
24-bit wide rs, 7 iterations are skipped. Any attempt to
issue a subsequent MDU instruction while a divide is
still active causes an IU pipeline stall until the divide
operation has completed.
Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency (number of cycles until a result is available) for the processor
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
MIPS32® microAptiv™ MCU CORE HIGH-PERFORMANCE INTEGER MULTIPLY/
DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU (HI/LO destination)
MUL (GPR destination)
DIV/DIVU
DS60001402H-page 50
Operand Size (mul rt) (div rs)
Latency
Repeat Rate
16 bits
32 bits
16 bits
32 bits
8 bits
16 bits
24 bits
32 bits
5
5
5
5
12/14
20/22
28/30
36/38
1
1
1
1
12/14
20/22
28/30
36/38
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
The MIPS architecture defines that the result of a
multiply or divide operation be placed in one of four
pairs of HI and LO registers. Using the Move-From-HI
(MFHI) and Move-From-LO (MFLO) instructions, these
values can be transferred to the General Purpose
Register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results
in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction
required when using the LO register, and by supporting multiple destination registers, the throughput of
multiply-intensive operations is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
The MDU also implements various shift instructions
operating on the HI/LO register and multiply instructions as defined in the DSP ASE. The MDU supports all
of the data types required for this purpose and includes
three extra HI/LO registers as defined by the ASE.
TABLE 3-3:
Register
Number
Register
Name
Reserved
HWREna
8
BadVAddr
BadInstr
BadInstrP
Count
Reserved
Compare
Status
IntCtl
SRSCtl
SRSMap
View_IPL
SRSMAP2
13
14
TABLE 3-2:
DSP-RELATED LATENCIES
AND REPEAT RATES
Op code
Latency
Repeat
Rate
Multiply and dot-product without
saturation after accumulation
5
1
Multiply and dot-product with
saturation after accumulation
5
1
Multiply without accumulation
5
1
3.1.3
SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (Kernel, User and Debug) and
whether interrupts are enabled or disabled. Configuration information, such as the presence of options like
microMIPS is also available by accessing the CP0
registers, listed in Table 3-3.
COPROCESSOR 0 REGISTERS
0-6
7
9
10
11
12
Table 3-2 lists the latencies and repeat rates for the
DSP multiply and dot-product operations. The approximate latencies and repeat rates are listed in terms of
pipeline clocks.
Cause
NestedExc
View_RIPL
EPC
NestedEPC
Function
Reserved in the PIC32MK GP Family core.
Enables access via the RDHWR instruction to selected hardware registers in
Non-privileged mode.
Reports the address for the most recent address-related exception.
Reports the instruction that caused the most recent exception.
Reports the branch instruction if a delay slot caused the most recent exception.
Processor cycle count.
Reserved in the PIC32MK GP Family core.
Core timer interrupt control.
Processor status and control.
Interrupt control of vector spacing.
Shadow register set control.
Shadow register mapping control.
Allows the Priority Level to be read/written without
extracting or inserting that bit from/to the Status register.
Contains two 4-bit fields that provide the mapping from a vector number to the shadow
set number to use when servicing such an interrupt.
Describes the cause of the last exception.
Contains the error and exception level status bit values that existed prior to the current
exception.
Enables read access to the RIPL bit that is available in the Cause register.
Program counter at last exception.
Contains the exception program counter that existed prior to the current exception.
2016-2021 Microchip Technology Inc.
DS60001402H-page 51
PIC32MK GP/MC Family
TABLE 3-3:
COPROCESSOR 0 REGISTERS (CONTINUED)
Register
Number
Register
Name
15
PRID
Ebase
CDMMBase
Config
Config1
Config2
Config3
Config4
Config5
Config7
Reserved
Reserved
Reserved
Reserved
Debug
TraceControl
TraceControl2
UserTraceData1
TraceBPC
Debug2
DEPC
UserTraceData2
PerfCtl0
PerfCnt0
PerfCtl1
PerfCnt1
Reserved
Reserved
Reserved
Reserved
ErrorEPC
DeSave
16
17
18
19
20-22
23
24
25
26
27
28
29
30
31
DS60001402H-page 52
Function
Processor identification and revision
Exception base address of exception vectors.
Common device memory map base.
Configuration register.
Configuration register 1.
Configuration register 2.
Configuration register 3.
Configuration register 4.
Configuration register 5.
Configuration register 7.
Reserved in the PIC32MK GP Family core.
Reserved in the PIC32MK GP Family core.
Reserved in the PIC32MK GP Family core.
Reserved in the PIC32MK GP Family core.
EJTAG debug register.
EJTAG trace control.
EJTAG trace control 2.
EJTAG user trace data 1 register.
EJTAG trace breakpoint register.
Debug control/exception status 1.
Program counter at last debug exception.
EJTAG user trace data 2 register.
Performance counter 0 control.
Performance counter 0.
Performance counter 1 control.
Performance counter 1.
Reserved in the PIC32MK GP Family core.
Reserved in the PIC32MK GP Family core.
Reserved in the PIC32MK GP Family core.
Reserved in the PIC32MK GP Family core.
Program counter at last error exception.
Debug exception save.
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
3.1.4
FLOATING POINT UNIT (FPU)
The Floating Point Unit (FPU), Coprocessor (CP1),
implements the MIPS Instruction Set Architecture for
floating point computation. The implementation supports the ANSI/IEEE Standard 754 (IEEE for Binary
Floating Point Arithmetic) for single- and double-precision data formats. The FPU can be programmed to
have thirty-two 32-bit or 64-bit floating point registers
used for floating point operations.
The performance is optimized for single precision formats. Most instructions have one FPU cycle throughput
and four FPU cycle latency. The FPU implements the
multiply-add (MADD) and multiply-sub (MSUB) instructions with intermediate rounding after the multiply function. The result is guaranteed to be the same as
executing a MUL and an ADD instruction separately,
but the instruction latency, instruction fetch, dispatch
bandwidth, and the total number of register accesses
are improved.
IEEE denormalized input operands and results are
supported by hardware for some instructions. IEEE
denormalized results are not supported by hardware in
general, but a fast flush-to-zero mode is provided to
optimize performance. The fast flush-to-zero mode is
enabled through the FCCR register, and use of this
mode is recommended for best performance when
denormalized results are generated.
The FPU has a separate pipeline for floating point
instruction execution. This pipeline operates in parallel
with the integer core pipeline and does not stall when
the integer pipeline stalls. This allows long-running
FPU operations, such as divide or square root, to be
partially masked by system stalls and/or other integer
unit instructions. Arithmetic instructions are always
dispatched and completed in order, but loads and
stores can complete out of order. The exception model
is “precise” at all times.
Table 3-4 contains the floating point instruction latencies and repeat rates for the processor core. In this
table, 'Latency' refers to the number of FPU cycles necessary for the first instruction to produce the result
needed by the second instruction. The “Repeat Rate”
refers to the maximum rate at which an instruction can
be executed per FPU cycle.
2016-2021 Microchip Technology Inc.
TABLE 3-4:
FPU INSTRUCTION
LATENCIES AND REPEAT
RATES
Latency
(FPU
Cycles)
Repeat
Rate
(FPU
Cycles)
ABS.[S,D], NEG.[S,D],
ADD.[S,D], SUB.[S,D],
C.cond.[S,D], MUL.S
4
1
MADD.S, MSUB.S,
NMADD.S, NMSUB.S,
CABS.cond.[S,D]
4
1
CVT.D.S, CVT.PS.PW,
CVT.[S,D].[W,L]
4
1
CVT.S.D,
CVT.[W,L].[S,D],
CEIL.[W,L].[S,D],
FLOOR.[W,L].[S,D],
ROUND.[W,L].[S,D],
TRUNC.[W,L].[S,D]
4
1
MOV.[S,D], MOVF.[S,D],
MOVN.[S,D],
MOVT.[S,D], MOVZ.[S,D]
4
1
MUL.D
5
2
MADD.D, MSUB.D,
NMADD.D, NMSUB.D
5
2
RECIP.S
13
10
RECIP.D
26
21
RSQRT.S
17
14
RSQRT.D
36
31
DIV.S, SQRT.S
17
14
DIV.D, SQRT.D
32
29
MTC1, DMTC1, LWC1,
LDC1, LDXC1, LUXC1,
LWXC1
4
1
MFC1, DMFC1, SWC1,
SDC1, SDXC1, SUXC1,
SWXC1
1
1
Op code
Legend: S = Single D = Double
W = Word L = Long word
DS60001402H-page 53
PIC32MK GP/MC Family
The FPU implements a high-performance 7-stage
pipeline:
• Decode, register read and unpack (FR stage)
• Multiply tree - double pumped for double (M1
stage)
• Multiply complete (M2 stage)
• Addition first step (A1 stage)
• Addition second and final step (A2 stage)
• Packing to IEEE format (FP stage)
• Register writeback (FW stage)
The FPU implements a bypass mechanism that allows
the result of an operation to be forwarded directly to the
instruction that needs it without having to write the
result to the FPU register and then read it back.
Table 3-5 lists the Coprocessor 1 Registers for the
FPU.
TABLE 3-5:
FPU (CP1) REGISTERS
Register Register
Number
Name
Function
0
FIR
Floating Point implementation
register. Contains information
that identifies the FPU.
25
FCCR
Floating Point condition codes
register.
26
FEXR
Floating Point exceptions
register.
28
FENR
Floating Point enables register.
31
FCSR
Floating Point Control and
Status register.
DS60001402H-page 54
3.2
Power Management
The processor core offers a number of power management features, including low-power design, active power
management and power-down modes of operation. The
core is a static design that supports slowing or halting
the clocks, which reduces system power consumption
during Idle periods.
3.2.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see 32.0 “PowerSaving Features”.
3.2.2
LOCAL CLOCK GATING
The majority of the power consumed by the processor
core is in the clock tree and clocking registers. The
PIC32MK family makes extensive use of local gatedclocks to reduce this dynamic power consumption.
3.3
EJTAG Debug Support
The processor core provides for an Enhanced JTAG
(EJTAG) interface for use in the software debug of
application and kernel code. In addition to standard
User mode and Kernel modes of operation, the processor core provides a Debug mode that is entered after a
debug exception (derived from a hardware breakpoint,
single-step exception, etc.) is taken and continues until
a Debug Exception Return (DERET) instruction is
executed. During this time, the processor executes the
debug exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for transferring test data in and out of the core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification specify which
registers are selected and how they are used.
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
3.4
MIPS DSP ASE Extension
The MIPS DSP Application-Specific Extension
Revision 2 is an extension to the MIPS32 architecture.
This extension comprises new integer instructions and
states that include new HI/LO accumulator register
pairs and a DSP control register. This extension is
crucial in a wide range of DSP, multimedia, and DSPlike algorithms covering Audio and Video processing
applications. The extension supports native fractional
format data type operations, register Single Instruction
Multiple Data (SIMD) operations, such as add,
subtract, multiply, and shift. In addition, the extension
includes the following features that are essential in
making DSP algorithms computationally efficient:
•
•
•
•
Support for multiplication of complex operands
Variable bit insertion and extraction
Implementation and use of virtual circular buffers
Arithmetic saturation and overflow handling
support
• Zero cycle overhead saturation and rounding
operations
2016-2021 Microchip Technology Inc.
3.5
microMIPS ISA
The processor core supports the microMIPS ISA,
which contains all MIPS32 ISA instructions (except for
branch-likely instructions) in a new 32-bit encoding
scheme, with some of the commonly used instructions
also available in 16-bit encoded format. This ISA
improves code density through the additional 16-bit
instructions while maintaining a performance similar to
MIPS32 mode. In microMIPS mode, 16-bit or 32-bit
instructions will be fetched and recoded to legacy
MIPS32 instruction opcodes in the pipeline’s I stage, so
that the processor core can have the same microAptiv
MPU microarchitecture. Because the microMIPS
instruction stream can be intermixed with 16-bit halfword or 32-bit word size instructions on halfword or
word boundaries, additional logic is in place to address
the word misalignment issues, thus minimizing
performance loss.
DS60001402H-page 55
PIC32MK GP/MC Family
3.6
MIPS32® microAptiv™ MCU Core
Configuration
Register 3-1 through Register 3-5 show the default
configuration of the MIPS32 microAptiv MCU core,
which is included on the PIC32MK GP/MC family of
devices.
REGISTER 3-1:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG: CONFIGURATION REGISTER; CP0 REGISTER 16, SELECT 0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
r-1
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
ISP
R-1
R-0
R-0
R-1
R-0
U-0
DSP
UDI
SB
MDU
—
R-0
R-0
R-0
R-0
BE
AT
R-0
R-1
U-0
U-0
U-0
U-0
—
—
—
—
—
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R/W-0
R-0
BM
R-0
R-1
U-0
U-0
—
K0
—
AR
U-0
Legend:
R = Readable bit
-n = Value at POR
R-0
MM
Bit
24/16/8/0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Reserved: This bit is hardwired to ‘1’ to indicate the presence of the Config1 register.
bit 30-25 Unimplemented: Read as ‘0’
bit 24
ISP: Instruction Scratch Pad RAM bit
0 = Instruction Scratch Pad RAM is not implemented
bit 23
DSP: Data Scratch Pad RAM bit
0 = Data Scratch Pad RAM is not implemented
bit 22
UDI: User-defined bit
0 = CorExtend User-Defined Instructions are not implemented
bit 21
SB: SimpleBE bit
1 = Only Simple Byte Enables are allowed on the internal bus interface
bit 20
MDU: Multiply/Divide Unit bit
0 = Fast, high-performance MDU
bit 19
Unimplemented: Read as ‘0’
bit 18-17 MM: Merge Mode bits
10 = Merging is allowed
bit 16
BM: Burst Mode bit
0 = Burst order is sequential
bit 15
BE: Endian Mode bit
0 = Little-endian
bit 14-13 AT: Architecture Type bits
00 = MIPS32
bit 12-10 AR: Architecture Revision Level bits
001 = MIPS32 Release 2
bit 9-3
Unimplemented: Read as ‘0’
DS60001402H-page 56
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 3-1:
bit 2-0
CONFIG: CONFIGURATION REGISTER; CP0 REGISTER 16, SELECT 0
K0: Kseg0 Coherency Algorithm bits
000 = Reserved
001 = Reserved
010 = Instruction Prefetch uncached (Default)
011 = Instruction Prefetch cached (Recommended)
100 = Reserved
•
•
•
111 = Reserved
2016-2021 Microchip Technology Inc.
DS60001402H-page 57
PIC32MK GP/MC Family
REGISTER 3-2:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG1: CONFIGURATION REGISTER 1; CP0 REGISTER 16, SELECT 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
r-1
R-0
R-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
U-0
U-0
U-0
U-0
—
U-0
MMUSIZE
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R-1
R-1
R-0
R-1
R-1
—
—
—
PC
WR
CA
EP
FP
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Reserved: This bit is hardwired to a ‘1’ to indicate the presence of the Config2 register.
bit 30-25 MMUSIZE: MMU Size bits
bit 24-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note:
This bit field is read as ‘0’ decimal in the fixed table-based MMU core, as no TLB is present.
Unimplemented: Read as ‘0’
PC: Performance Counter bit
1 = The processor core contains Performance Counters
WR: Watch Register Presence bit
1 = No Watch registers are present
CA: Code Compression Implemented bit
0 = No MIPS16e® present
EP: EJTAG Present bit
1 = Core implements EJTAG
FP: Floating Point Unit bit
1 = Floating Point Unit is present
DS60001402H-page 58
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 3-3:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG3: CONFIGURATION REGISTER 3; CP0 REGISTER 16, SELECT 3
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
r-1
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
R-1
R-0
R-0
R-0
R-1
R/W-y
MCU
ISAONEXC(1)
—
R-y
IPLW
R-y
ISA(1)
MMAR
R-1
R-1
R-1
R-1
U-0
R-1
ULRI
RXI
DSP2P
DSPP
—
ITL
U-0
R-1
R-1
R-0
R-1
U-0
U-0
R-0
—
VEIC
VINT
SP
CDMM
—
—
TL
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
y = Value set from Configuration bits on POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Reserved: This bit is hardwired as ‘1’ to indicate the presence of the Config4 register
bit 30-23 Unimplemented: Read as ‘0’
bit 22-21 IPLW: Width of the Status IPL and Cause RIPL bits
01 = IPL and RIPL bits are 8-bits in width
bit 20-18 MMAR: microMIPS Architecture Revision Level bits
000 = Release 1
bit 17
MCU: MIPS® MCU™ ASE Implemented bit
1 = MCU ASE is implemented
bit 16
ISAONEXC: ISA on Exception bit(1)
1 = microMIPS is used on entrance to an exception vector
0 = MIPS32 ISA is used on entrance to an exception vector
bit 15-14 ISA: Instruction Set Availability bits(1)
11 = Both MIPS32 and microMIPS are implemented; microMIPS is used when coming out of reset
10 = Both MIPS32 and microMIPS are implemented; MIPS32 ISA used when coming out of reset
bit 13
ULRI: UserLocal Register Implemented bit
1 = UserLocal Coprocessor 0 register is implemented
bit 12
RXI: RIE and XIE Implemented in PageGrain bit
1 = RIE and XIE bits are implemented
bit 11
DSP2P: MIPS DSP ASE Revision 2 Presence bit
1 = DSP Revision 2 is present
bit 10
DSPP: MIPS DSP ASE Presence bit
1 = DSP is present
bit 9
Unimplemented: Read as ‘0’
bit 8
ITL: Indicates that iFlowtrace® hardware is present
1 = The iFlowtrace® 2.0 hardware is implemented in the core
bit 7
Unimplemented: Read as ‘0’
bit 6
VEIC: External Vector Interrupt Controller bit
1 = Support for an external interrupt controller is implemented.
bit 5
VINT: Vector Interrupt bit
1 = Vector interrupts are implemented
bit 4
SP: Small Page bit
0 = 4 KB page size
bit 3
CDMM: Common Device Memory Map bit
1 = CDMM is implemented
bit 2-1
Unimplemented: Read as ‘0’
bit 0
TL: Trace Logic bit
0 = Trace logic is not implemented
Note 1:
These bits are set based on the value of the BOOTISA Configuration bit (DEVCFG0).
2016-2021 Microchip Technology Inc.
DS60001402H-page 59
PIC32MK GP/MC Family
REGISTER 3-4:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG4: CONFIGURATION REGISTER 4; CP0 REGISTER 16, SELECT 4
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
M
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
KScr Exist
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
—
—
—
Legend:
r = Reserved
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
M: Config5 Register Present bit
1 = Config5 register is present
0 = Config5 register is not present
bit 30-24 Unimplemented: Read as ‘0’
bit 23-16 KScr Exist: Number of Scratch Registers Available to Kernel Mode bits
Indicates how many scratch registers are available to Kernel mode software within CP0 Register 31.
Each bit represents a select for Coprocessor0 Register 31. Bit 16 represents Select 0. Bit 23 represents
Select 7. If the bit is set, the associated scratch register is implemented and is available for Kernel mode
software.
Note:
bit 15-0
These bits are read-only, and this field is all zeros on these products, as is read as ‘0’.
Reserved: Read/write as ‘0’
DS60001402H-page 60
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 3-5:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG5: CONFIGURATION REGISTER 5; CP0 REGISTER 16, SELECT 5
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-1
—
—
—
—
—
—
—
NF
Legend:
r = Reserved
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-1
Unimplemented: Read as ‘0’
bit 0
NF: Nested Fault bit
1 = Nested Fault feature is implemented
REGISTER 3-6:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
CONFIG7: CONFIGURATION REGISTER 7; CP0 REGISTER 16, SELECT 7
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
WII
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
WII: Wait IE Ignore bit
1 = Indicates that this processor will allow an interrupt to unblock a WAIT instruction
bit 30-0
Unimplemented: Read as ‘0’
2016-2021 Microchip Technology Inc.
DS60001402H-page 61
PIC32MK GP/MC Family
REGISTER 3-7:
Bit
Range
31:24
23:16
15:8
7:0
FIR: FLOATING POINT IMPLEMENTATION REGISTER; CP1 REGISTER 0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
U-0
U-0
—
—
Bit
24/16/8/0
U-0
R-1
U-0
U-0
U-0
R-1
—
UFRP
—
—
—
FC
R-1
R-1
R-1
R-1
R-1
R-0
R-0
R-1
HAS2008
F64
L
W
MIPS3D
PS
D
S
R-1
R-0
R-1
R-0
R-0
R-1
R-1
R-1
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
PRID
Legend:
R = Readable bit
-n = Value at POR
REVISION
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28
UFRP: User Mode FR Switching Instruction bit
1 = User mode FR switching instructions are supported
0 = User mode FR switching instructions are not supported
bit 27-25 Unimplemented: Read as ‘0’
bit 24
FC: Full Convert Ranges bit
1 = Full convert ranges are implemented (all numbers can be converted to another type by the FPU)
0 = Full convert ranges are not implemented
bit 23
HAS008: IEEE-754-2008 bit
1 = MAC2008, ABS2008, NAN2008 bits exist within the FCSR register
0 = MAC2009, ABS2008, and NAN2008 bits do not exist within the FCSR register
bit 22
F64: 64-bit FPU bit
1 = This is a 64-bit FPU
0 = This is not a 64-bit FPU
bit 21
L: Long Fixed Point Data Type bit
1 = Long fixed point data types are implemented
0 = Long fixed point data types are not implemented
bit 20
W: Word Fixed Point data type bit
1 = Word fixed point data types are implemented
0 = Word fixed point data types are not implemented
bit 19
MIPS3D: MIPS-3D ASE bit
1 = MIPS-3D is implemented
0 = MIPS-3D is not implemented
bit 18
PS: Paired Single Floating Point data bit
1 = PS floating point is implemented
0 = PS floating point is not implemented
bit 17
D: Double-precision floating point data bit
1 = Double-precision floating point data types are implemented
0 = Double-precision floating point data types are not implemented
bit 16
S: Single-precision Floating Point Data bit
1 = Single-precision floating point data types are implemented
0 = Single-precision floating point data types are not implemented
bit 15-8 PRID: Processor Identification bits
These bits allow software to distinguish between the various types of MIPS processors. For PIC32 devices
with the MIPS32 microAptiv MCU core, this value is 0x9D.
bit 7-0
REVISION: Processor Revision Identification bits
These bits allow software to distinguish between one revision and another of the same processor type. This
number is increased on major revisions of the processor core
DS60001402H-page 62
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 3-8:
Bit
Range
31:24
23:16
15:8
7:0
FCCR: FLOATING POINT CONDITION CODES REGISTER; CP1 REGISTER 25
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
FCC
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8
Unimplemented: Read as ‘0’
bit 7-0
FCC: Floating Point Condition Code bits
These bits record the results of floating point compares and are tested for floating point conditional branches
and conditional moves.
2016-2021 Microchip Technology Inc.
DS60001402H-page 63
PIC32MK GP/MC Family
REGISTER 3-9: FEXR: FLOATING POINT EXCEPTIONS STATUS REGISTER; CP1 REGISTER 26
Bit
Range
31:24
23:16
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-x
R/W-x
—
—
—
—
—
—
E
V
R/W-x
R/W-x
R/W-x
U-0
U-0
U-0
U-0
U-0
—
—
—
—
R/W-x
R/W-x
U-0
U-0
U
I
—
—
CAUSE
15:8
7:0
CAUSE
Z
O
U
I
U-0
R/W-x
R/W-x
R/W-x
—
FLAGS
V
Z
O
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-18 Unimplemented: Read as ‘0’
bit 17-12 CAUSE: FPU Exception Cause bits
These bits indicated the exception conditions that arise during execution of an FPU arithmetic instruction.
bit 17
E: Unimplemented Operation bit
bit 16
V: Invalid Operation bit
bit 15
Z: Divide-by-Zero bit
bit 14
O: Overflow bit
bit 13
U: Underflow bit
bit 12
I: Inexact bit
bit 11-7
Unimplemented: Read as ‘0’
bit 6-2
FLAGS: FPU Flags bits
These bits show any exception conditions that have occurred for completed instructions since the flag was
last reset by software.
bit 6
V: Invalid Operation bit
bit 4
Z: Divide-by-Zero bit
bit 4
O: Overflow bit
bit 3
U: Underflow bit
bit 2
I: Inexact bit
bit 1-0
Unimplemented: Read as ‘0’
DS60001402H-page 64
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 3-10: FENR: FLOATING POINT EXCEPTIONS AND MODES ENABLE REGISTER;
CP1 REGISTER 28
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
ENABLES
—
—
—
—
V
Z
O
U
R/W-x
U-0
U-0
U-0
U-0
R-x
R/W-x
R/W-x
—
—
—
—
FS
ENABLES
I
RM
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-12 Unimplemented: Read as ‘0’
bit 11-7
ENABLES: FPU Exception Enable bits
These bits control whether or not a trap is taken when an IEEE exception condition occurs for any of the five
conditions. The trap occurs when both an enable bit and its corresponding cause bit are set either during an
FPU arithmetic operation or by moving a value to the FCSR or one of its alternative representations.
bit 11
V: Invalid Operation bit
bit 10
Z: Divide-by-Zero bit
bit 9
O: Overflow bit
bit 8
U: Underflow bit
bit 7
I: Inexact bit
bit 6-3
Unimplemented: Read as ‘0’
bit 2
FS: Flush to Zero control bit
1 = Denormal input operands are flushed to zero. Tiny results are flushed to either zero or the applied format's
smallest normalized number (MinNorm) depending on the rounding mode settings.
0 = Denormal input operands result in an Unimplemented Operation exception.
bit 1-0
RM: Rounding Mode control bits
11 = Round towards Minus Infinity (– )
10 = Round towards Plus Infinity (+ )
01 = Round toward Zero (0)
00 = Round to Nearest
2016-2021 Microchip Technology Inc.
DS60001402H-page 65
PIC32MK GP/MC Family
REGISTER 3-11: FCSR: FLOATING POINT CONTROL AND STATUS REGISTER; CP1 REGISTER 31
Bit
Range
31:24
23:16
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-x
R/W-x
R/W-x
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
FCC
FS
R/W-x
R/W-x
R/W-x
R-0
R-1
R-1
FCC
FO
FN
MAC2008
ABS2008
NAN2008
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
15:8
R/W-x
R/W-x
ENABLES
I
R/W-x
R/W-x
CAUSE
R/W-x
R/W-x
V
Z
O
U
R/W-x
R/W-x
R/W-x
R/W-x
U
I
FLAGS
V
R/W-x
ENABLES
CAUSE
R/W-x
7:0
Bit
28/20/12/4
Z
O
RM
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-25 FCC: Floating Point Condition Code bits
These bits record the results of floating point compares and are tested for floating point conditional
branches and conditional moves.
bit 24
FS: Flush to Zero control bit
1 = Denormal input operands are flushed to zero. Tiny results are flushed to either zero or the applied
format's smallest normalized number (MinNorm) depending on the rounding mode settings.
0 = Denormal input operands result in an Unimplemented Operation exception.
bit 23
FCC: Floating Point Condition Code bits
These bits record the results of floating point compares and are tested for floating point conditional branches
and conditional moves.
bit 22
FO: Flush Override Control bit
1 = The intermediate result is kept in an internal format, which can be perceived as having the usual
mantissa precision but with unlimited exponent precision and without forcing to a specific value or
taking an exception.
0 = Handling of Tiny Result values depends on setting of the FS bit.
bit 21
FN: Flush to Nearest Control bit
1 = Final result is rounded to either zero or 2E_min (MinNorm), whichever is closest when in Round to
Nearest (RN) rounding mode. For other rounding modes, a final result is given as if FS was set to 1.
0 = Handling of Tiny Result values depends on setting of the FS bit.
bit 20
MAC2008: Fused Multiply Add mode control bit
0 = Unfused multiply-add. Intermediary multiplication results are rounded to the destination format.
bit 19
ABS2008: Absolute value format control bit
1 = ABS.fmt and NEG.fmt instructions compliant with IEEE Standard 754-2008. The ABS and NEG functions
accept QNAN inputs without trapping.
bit 18
NAN2008: NaN Encoding control bit
1 = Quiet and signaling NaN encodings recommended by the IEEE Standard 754-2008. A quiet NaN is
encoded with the first bit of the fraction being 1 and a signaling NaN is encoded with the first bit of the
fraction being 0.
bit 17-12 CAUSE: FPU Exception Cause bits
These bits indicated the exception conditions that arise during execution of an FPU arithmetic instruction.
DS60001402H-page 66
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 3-11: FCSR: FLOATING POINT CONTROL AND STATUS REGISTER; CP1 REGISTER 31
bit 17
E: Unimplemented Operation bit
bit 16
V: Invalid Operation bit
bit 15
Z: Divide-by-Zero bit
bit 14
O: Overflow bit
bit 13
U: Underflow bit
bit 12
I: Inexact bit
bit 11-7
ENABLES: FPU Exception Enable bits
These bits control whether or not a trap is taken when an IEEE exception condition occurs for any of the
five conditions. The trap occurs when both an enable bit and its corresponding cause bit are set either
during an FPU arithmetic operation or by moving a value to the FCSR or one of its alternative
representations.
bit 11
V: Invalid Operation bit
bit 10
Z: Divide-by-Zero bit
bit 9
O: Overflow bit
bit 8
U: Underflow bit
bit 7
I: Inexact bit
bit 6-2
FLAGS: FPU Flags bits
These bits show any exception conditions that have occurred for completed instructions since the flag was
last reset by software.
bit 6
V: Invalid Operation bit
bit 5
Z: Divide-by-Zero bit
bit 4
O: Overflow bit
bit 3
U: Underflow bit
bit 2
I: Inexact bit
bit 1-0
RM: Rounding Mode control bits
11 = Round towards Minus Infinity (– )
10 = Round towards Plus Infinity (+ )
01 = Round toward Zero (0)
00 = Round to Nearest
2016-2021 Microchip Technology Inc.
DS60001402H-page 67
PIC32MK GP/MC Family
4.0
Note:
MEMORY ORGANIZATION
This data sheet summarizes the
features of the PIC32MK GP/MC Family
of devices. It is not intended to be a
comprehensive reference source. For
detailed information, refer to Section 48.
“Memory
Organization
and
Permissions” (DS60001214), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
PIC32MK GP/MC microcontrollers provide 4 GB of
unified virtual memory address space. All memory
regions, including program, data memory, Special
Function Registers (SFRs) and Configuration registers,
reside in this address space at their respective unique
addresses. The program and data memories can be
optionally partitioned into user and kernel memories. In
addition, PIC32MK GP/MC devices allow execution
from data memory.
4.1
Memory Layout
PIC32MK GP/MC microcontrollers implement two address schemes: virtual and physical. All hardware resources, such as program memory, data memory and
peripherals, are located at their respective physical addresses. Virtual addresses are exclusively used by the
CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by bus
Host peripherals, such as DMA and the Flash controller, that access memory independently of the CPU.
The main memory maps for the PIC32MK GP/MC devices are illustrated in Figure 4-1 through Figure 4-2.
Figure 4-3 provides memory map information for boot
Flash and boot alias. Table 4-3 provides memory map
information for SFRs.
Key features of this module include:
• 32-bit native data width
• Separate User (KUSEG) and Kernel (KSEG0/
KSEG1) mode address space
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
runaway code
• Read/write permission access to predefined
memory regions
DS60001402H-page 68
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
MEMORY MAP FOR DEVICES WITH 512 KB PROGRAM MEMORY AND 128 KB RAM
0xFFFFFFFF
0xBFC65000
0xBFC64FFF
0xBFC60000
0xBFC5FFFF
0xBFC45000
0xBFC44FFF
0xBFC40000
0xBF900000
0xBF8FFFFF
0xBF800000
0xBD080000
0xBD07FFFF
Virtual
Memory Map
Physical
Memory Map
Reserved
Reserved
Boot Flash 2
(see Figure 4-3)
Boot Flash 2
(see Figure 4-3)
Reserved
Reserved
Boot Flash 1
(see Figure 4-3)
Boot Flash 1
(see Figure 4-3)
Reserved
Reserved
SFRs
(see Table 4-3)
SFRs
(see Table 4-3)
Reserved
KSEG1
FIGURE 4-1:
Program Flash
0xA0020000
0xA001FFFF
Program Flash
Panel 1
Reserved
Reserved
RAM(2)
0xA0000000
0x9FC60000
0x9FC45000
0x9FC44FFF
0x9FC40000
0x9D080000
0x9D07FFFF
RAM(2)
Reserved
0x1FC45000
0x1FC44FFF
0x1FC40000
0x1F900000
0x1F8FFFFF
0x1F800000
0x1D080000
0x1D07FFFF
0x1D040000
0x1D03FFFF
0x1D000000
0x00020000
0x0001FFFF
0x00000000
Boot Flash 2
(see Figure 4-3)
Reserved
Boot Flash 1
(see Figure 4-3)
Reserved
KSEG0
0x9FC65000
0x9FC64FFF
0x1FC60000
Reserved
Program Flash
Panel 2
0xBD000000
0xFFFFFFFF
0x1FC65000
0x1FC64FFF
Program Flash
0x9D000000
0x80020000
0x8001FFFF
Reserved
RAM(2)
0x80000000
0x00000000
Note
1:
2:
Reserved
Memory areas are not shown to scale.
RAM memory is divided into two equal banks: RAM Bank 1 and RAM Bank 2 on a half boundary.
2016-2021 Microchip Technology Inc.
DS60001402H-page 69
PIC32MK GP/MC Family
0xFFFFFFFF
0xBFC65000
0xBFC64FFF
0xBFC60000
0xBFC45000
0xBFC44FFF
0xBFC40000
0xBF900000
0xBF8FFFFF
0xBF800000
MEMORY MAP FOR DEVICES WITH 1024 KB PROGRAM MEMORY AND 256 KB RAM
Virtual
Memory Map
Physical
Memory Map
Reserved
Reserved
Boot Flash 2
(see Figure 4-3)
Boot Flash 2
(see Figure 4-3)
Reserved
Reserved
Boot Flash 1
(see Figure 4-3)
Reserved
SFRs
(see Table 4-3)
Boot Flash 1
(see Figure 4-3)
KSEG1
FIGURE 4-2:
Reserved
SFRs
(see Table 4-3)
Reserved
0xBD100000
0xBD0FFFFF
0xBD000000
Program Flash
Panel 2
Reserved
0xA0040000
0xA003FFFF
Program Flash
Panel 1
RAM(2)
Reserved
0xA0000000
0x9FC45000
0x9FC44FFF
0x9FC40000
0x1FC45000
0x1FC44FFF
0x1FC40000
0x1F900000
0x1F8FFFFF
0x1F800000
Reserved
(2)
RAM
0x1D100000
0x1D0FFFFF
0x1D080000
0x1D07FFFF
0x1D000000
0x00040000
0x0003FFFF
0x00000000
Boot Flash 2
(see Figure 4-3)
Reserved
Boot Flash 1
(see Figure 4-3)
Reserved
0x9D100000
0x9D0FFFFF
KSEG0
0x9FC60000
0x1FC60000
Reserved
Program Flash
0x9FC65000
0x9FC64FFF
0xFFFFFFFF
0x1FC65000
0x1FC64FFF
Program Flash
0x9D000000
0x80040000
0x8003FFFF
Reserved
RAM(2)
0x80000000
0x00000000
Note
1:
2:
Reserved
Memory areas are not shown to scale.
RAM memory is divided into two equal banks: RAM Bank 1 and RAM Bank 2 on a half boundary.
DS60001402H-page 70
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
FIGURE 4-3:
BOOT AND ALIAS
MEMORY MAP
TABLE 4-1:
Virtual Address
Peripheral
(1)
Physical Memory Map
0x1FC64FFF
0x1FC64000
Seq/Configuration
Word Space
Boot Flash 2
0x1FC63FFF
0x0800
0x0A00
0x1FC60000
WDT
0x1FC5FFFF
DMT
0x1FC45800
CRU
0x1200
0x1FC457FF
PPS
0x1400
PLVD
0x1800
0x1FC4503C
0x1FC45030
EVIC
0x1FC4502F
DMA
0x1FC4501C
0x0000
IC1-IC9
0x2000
0x4000
0x6000
DEVADC5
0x1FC45014
Reserved
DEVADC4
0x1FC45010
DEVADC3
0x1FC4500C
SPI1-SPI2
0x7000
DEVADC2
0x1FC45008
UART1-UART2
0x8000
DEVADC1
0x1FC45004
DATAEE
DEVADC0
0x1FC45000
PWM1-PWM12
0xA000
QEI1-QEI6
0xB200
0x1FC43FFF
CMP
0xC000
0x1FC43FB0
CDAC1
0xC200
0x1FC43FAC
CTMU
0xD000
PMP
0xE000
Seq/Configuration
Word Space
Reserved
0x1FC3FFFF
IC10-IC16
0x3200
OC10-OC16
0x5200
Reserved
0xBF840000
0x6400
0x1FC20000
SPI3-SPI6
0x1FC1FFFF
UART3-UART6
0x8400
0x1FC05000
CDAC2-CDAC3
0xC400
PORTA-PORTG
0xBF860000
0x7400
0x0000
0x1FC03FFF
CAN1-CAN4
0x1FC03FB0
ADC
0x1FC03FAC
USB1-USB2
0x9000
RTCC
0x0000
0x1FC00000
Memory areas are not shown to scale.
Memory locations 0x1FC03FB0 through
0x1FC03FFC are used to initialize
Configuration registers (see 33.0 “Special
Features”).
Refer to 4.1.1 “Boot Flash Sequence and
Configuration Spaces” for more information.
Memory locations 0x1FC5020 and 0x1FC502C
contain a unique device serial number (see
33.0 “Special Features”).
This configuration space cannot be used for
executing code in the upper Boot Alias.
2016-2021 Microchip Technology Inc.
0x9000
0x1FC24FFF
0x1FC04000
Seq/Configuration
Word Space
0xBF820000
0x1FC25000
0x1FC04FFF
5:
Timer1-Timer9
0x1FC45018
Upper Boot Alias
4:
0x0000
0x1000
DEVADC7
Reserved
3:
0xBF810000
OC1-OC9
0x1FC40000
1:
2:
0x0E00
0x1000
0x1FC44000
Note
0x0C00
0xBF800000
ICD
0x1FC44FFF
Lower Boot Alias
0x0000
FC-NVM
Device Serial Number(4) 0x1FC4502C
DEVSNx, x=0-3
0x1FC45020
Boot Flash 1
CFG-PMD
Offset
Start
CACHE
0x1FC45040
Public Test Flash
Base
0x1FC63FAC
0x1FC63FB0
Reserved
DATA EE CAL
(DEVEE0-DEVEE3)
SFR MEMORY MAP
0xBF880000
Deep Sleep
SSX CTL
Note 1:
0x0000
0xBF8C0000
0xBF8F0000
0x7000
0x0200
0x0000
Refer to 4.2 “System Bus Arbitration”
for important legal information.
DS60001402H-page 71
PIC32MK GP/MC Family
4.1.1
BOOT FLASH SEQUENCE AND
CONFIGURATION SPACES
Sequence space is used to identify which boot Flash is
aliased by aliased regions. If the value programmed
into the TSEQ bits of the BF1SEQ word is equal
to or greater than the value programmed into the
TSEQ bits of the BF2SEQ word, Boot Flash 1 is
aliased by the lower boot alias region, and Boot Flash
2 is aliased by the upper boot alias region. If the
TSEQ bits of the BF2SEQ word is greater than
the TSEQ bits of the BF1SEQ word, the
opposite is true (see Table 4-2 and Table 4-3 for
BFxSEQ word memory locations).
Once boot Flash memories are aliased, configuration
space located in the lower boot alias region is used as
the basis for the Configuration words, DEVSIGN0,
DEVCP0, and DEVCFGx. This means that the boot
Flash region to be aliased by lower boot alias region
memory must contain configuration values in the appropriate memory locations.
Note:
Use only Quad Word program operation
(NVMOP = 0010) when programming data into the sequence and
configuration spaces.
DS60001402H-page 72
2016-2021 Microchip Technology Inc.
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:0
31:0
31:0
Note: See Table 33-1 for the bit descriptions.
31:0
31:0
31:0
CSEQ
31:16
3FF0 BF1SEQ
15:0
TSEQ
Legend:
x = unknown value on Reset; — = Reserved, read as ‘1’. Reset values are shown in hexadecimal.
BF1DEVCFG3
BF1DEVCFG2
BF1DEVCFG1
BF1DEVCFG0
BF1DEVCP
BF1DEVSIGN
BOOT FLASH 2 SEQUENCE AND CONFIGURATION WORDS SUMMARY
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
BF2DEVCFG3
BF2DEVCFG2
BF2DEVCFG1
BF2DEVCFG0
BF2DEVCP
BF2DEVSIGN
20/4
19/3
18/2
17/1
16/0
All Resets
31/15
31:0
31:0
31:0
Note: See Table 33-1 for the bit descriptions.
31:0
31:0
31:0
CSEQ
31:16
3FF0 BF2SEQ
15:0
TSEQ
Legend:
x = unknown value on Reset; — = Reserved, read as ‘1’. Reset values are shown in hexadecimal.
3FC0
3FC4
3FC8
3FCC
3FDC
3FEC
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
Bits
Register
Name
Virtual Address
(BFC6_#)
TABLE 4-3:
Bit Range
3FC0
3FC4
3FC8
3FCC
3FDC
3FEC
All Reset
Bit Range
Bits
Register
Name
Virtual Address
(BFC4_#)
BOOT FLASH 1 SEQUENCE AND CONFIGURATION WORDS SUMMARY
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
PIC32MK GP/MC Family
DS60001402H-page 73
TABLE 4-2:
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 4-1:
Bit
Range
31:24
23:16
15:8
7:0
BFxSEQ: BOOT FLASH ‘x’ SEQUENCE REGISTER (‘x’ = 1 AND 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
CSEQ
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
CSEQ
TSEQ
R/P
R/P
R/P
R/P
R/P
TSEQ
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 CSEQ: Boot Flash Complement Sequence Number bits
bit 15-0
TSEQ: Boot Flash True Sequence Number bits
DS60001402H-page 74
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
4.2
System Bus Arbitration
Note:
The
System
Bus
interconnect
implements one or more instantiations of
the SonicsSX® interconnect from Sonics,
Inc. This document contains materials
that are (c) 2003-2015 Sonics, Inc., and
that constitute proprietary information of
Sonics, Inc. SonicsSX is a registered
trademark of Sonics, Inc. All such
materials and trademarks are used under
license from Sonics, Inc.
TABLE 4-4:
Target
#
As shown in the PIC32MK GP/MC Family Block Diagram (see Figure 1-1), there are multiple initiator modules (I1 through I13) in the system that can access
various target modules (T1 through T14). Table 4-4 illustrates which initiator can access which target. The
System Bus supports simultaneous access to targets
by initiators, so long as the initiators are accessing different targets. The System Bus will perform arbitration,
if multiple initiators attempt to access the same target.
INITIATORS TO TARGETS ACCESS ASSOCIATION
Initiator ID:
1
2
3
4
5
6
7
8
9
10
11
12
13
Name:
CPU
IS
CPU
ID
DMA
Read
DMA
Write
Flash
ICD
JTAG
ADC
Mem.
USB1
USB2
CAN1
CAN2
CAN3
CAN4
1
Program Flash
2
Data
X
X
3
Peripheral Module
X
X
X
X
X
X
4
RAM Bank 1
X
X
X
X
X
X
X
X
X
X
X
X
X
5
RAM Bank 2
X
X
X
X
X
X
X
X
X
X
X
X
X
7
Peripheral Bus 1:
DMT, CVR,
PPS Input,
PPS Output,
WDT
X
X
X
X
Peripheral Bus 2:
Timer1-Timer9,
I2C1-I2C2,
SPI1-SPI2,
UART1-UART2,
CDAC1,
OC1-OC9,
IC1-IC9,
PMP,
Comparator 1-
Comparator 5,
Op amp 1-Op amp 4
PWM1-PWM12
QEI1-QEI6
X
X
X
X
Peripheral Bus 3:
IC10-IC16,
OC10-OC16,
SPI3-SPI6,
I2C3-I2C4,
UART3-UART6,
CDAC2-CDAC3
X
X
X
X
10
Peripheral Bus 4:
PORTA-PORTG
X
X
X
X
11
Peripheral Bus 5:
USB1-USB2,
CAN1-CAN4
ADC
X
X
Peripheral Bus 6:
DSCON,
RTCC
X
X
8
9
14
2016-2021 Microchip Technology Inc.
DS60001402H-page 75
PIC32MK GP/MC Family
The System Bus arbitration scheme implements a nonprogrammable, Least Recently Serviced (LRS) priority,
which provides Quality Of Service (QOS) for most
initiators. However, some initiators can use Fixed High
Priority (HIGH) arbitration to guarantee their access to
data.
4.3
The arbitration scheme for the available initiators is
shown in Table 4-5.
The System Bus divides the entire memory space into
fourteen target regions and permits access to each
target by initiators through permission groups. Four
Permission Groups (0 through 3) can be assigned to
each initiator. Each permission group is independent
of the others and can have exclusive or shared
access to a region.
TABLE 4-5:
INITIATOR ID AND QOS
Name
ID
QOS
CPU-IS
1
LRS
CPU-DS
2
LRS
DMA Read
3
LRS
DMA Write
4
LRS
Flash Controller
5
HIGH
ICD-JTAG
6
LRS
ADC
7
LRS
USB1
8
LRS
USB2
9
LRS
CAN1
10
LRS
CAN2
11
LRS
CAN3
12
LRS
CAN4
13
LRS
Permission Access and System
Bus Registers
The System Bus on PIC32MK GP/MC family of
microcontrollers provides access control capabilities
for the transaction initiators on the System Bus.
Using the CFGPG register (see Register 33-8 in
33.0 “Special Features”), Boot firmware can assign a
permission group to each initiator, which can make
requests on the System Bus.
The available targets and their regions, as well as the
associated control registers to assign protection, are
described and listed in Table 4-6.
Register 4-2 through Register 4-10 are used for setting
and controlling access permission groups and regions.
To change these registers, they must be unlocked in
hardware. The register lock is controlled by the
PGLOCK Configuration bit (CFGCON). Setting
the PGLOCK bit prevents writes to the control registers and clearing the PGLOCK bit allows writes.
To set or clear the PGLOCK bit, an unlock sequence
must be executed. Refer to Section 42. “Oscillators
with Enhanced PLL” (DS60001250) in the “PIC32
Family Reference Manual” for details.
DS60001402H-page 76
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 4-6:
SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS
SBTxREGy Register
Target
Number
Target Description
Name
Region
Physical
Start
Address
Region Priority
Size
Level
SBT0REG0 Region 0 1F8F0000
1,1,1,1
SBT0WR0
1,1,1,1
0,0,0,1
SBT0WR1
0,0,0,1
0
SBT1RD0
1,1,1,1
SBT1WR0
0,0,0,0
2
SBT1RD2
0,0,0,1
SBT1WR2
0,0,0,0
4 KB
2
SBT1RD3
0,0,0,1
SBT1WR3
0,0,0,0
4 KB
2
SBT1RD4
0,0,0,1
SBT1WR4
0,0,0,0
4 KB
2
SBT1RD5
0,0,0,1
SBT1WR5
0,0,0,0
0
SBT2RD0
1,1,1,1
SBT2WR0
0,0,0,0
4 KB
1
SBT1REG5 Region 5 1FC64000
SBT2REG0 Region 0 1D000000
SBT2REG2 Region 2 1FC04000
4 KB
2
SBT2RD2
0,0,0,1
SBT2WR2
0,0,0,0
SBT2REG3 Region 3 1FC24000
4 KB
2
SBT2RD3
0,0,0,1
SBT2WR3
0,0,0,0
SBT2REG4 Region 4 1FC44000
4 KB
2
SBT2RD4
0,0,0,1
SBT2WR4
0,0,0,0
SBT2REG5 Region 5 1FC64000
4 KB
2
SBT2RD5
0,0,0,1
SBT2WR5
0,0,0,0
0
SBT3RD0
1,1,1,1
SBT3WR0
0,0,0,0
SBT3REG0 Region 0 1D000000
Legend:
Flash Memory (peripheral)
Program Flash
R = Read;
Name
SBT0RD0
32 KB
SBT1REG0 Region 0 1D000000
3
Name
Write
Permission
(Group3,
Group2,
Group1,
Group0)
SBT0RD1
Flash Memory (CPU Instruction) SBT1REG2 Region 2 1FC04000
Program Flash
SBT1REG3 Region 3 1FC24000
Boot Flash Prefetch
SBT1REG4 Region 4 1FC44000
Flash Memory (CPU data)
Program Flash
Read
Permission
(Group3,
Group2,
Group1,
Group0)
0
System Bus
2
SBTxWRy Register
3
0
SBT0REG1 Region 1 1F8F8000
SBTxRDy Register
SBT3REG2 Region 2 1FC04000
4 KB
2
SBT3RD2
0,0,0,1
SBT3WR2
0,0,0,0
SBT3REG3 Region 3 1FC24000
4 KB
2
SBT3RD3
0,0,0,1
SBT3WR3
0,0,0,0
SBT3REG4 Region 4 1FC44000
4 KB
2
SBT3RD4
0,0,0,1
SBT3WR4
0,0,0,0
SBT3REG5 Region 5 1FC64000
4 KB
2
SBT3RD5
0,0,0,1
SBT3WR5
0,0,0,0
R/W = Read/Write;
2016-2021 Microchip Technology Inc.
‘x’ in a register name = 0-13;
‘y’ in a register name = 0-8.
DS60001402H-page 77
Virtual Address
(BF8F_#)
Register
Name
0510
SBFLAG
Register
Name
8020
SBT0ELOG1
All
Resets
Bit Range
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
T3PGV
T2PGV
T1PGV
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
0000
T0PGV 0000
SYSTEM BUS TARGET 0 REGISTER MAP
SBT0ELOG2
SBT0ECON
SBT0ECLRS
SBT0REG0
8050
SBT0RD0
8058
SBT0WR0
8060
SBT0REG1
DS60001402H-page 78
8070
SBT0RD1
8078
SBT0WR1
Legend:
Note:
Bit Range
Bits
8038 SBT0ECLRM
8040
17/1
0000
29/13
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
REGION
—
CMD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
xxxx
31:16
—
0000
31:16
—
GROUP
BASE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
PRI
—
GROUP1 GROUP0 xxxx
—
—
BASE
xxxx
SIZE
—
—
—
xxxx
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
xxxx
GROUP1 GROUP0 xxxx
BASE
15:0
0000
CLEAR 0000
xxxx
SIZE
31:16
31:16
0000
CLEAR 0000
BASE
15:0
0000
GROUP1 GROUP0 xxxx
—
—
xxxx
GROUP1 GROUP0 xxxx
PIC32MK GP/MC Family
8030
18/2
—
30/14
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-8:
8028
19/3
16/0
31/15
All
Resets
Legend:
8024
SYSTEM BUS REGISTER MAP
Bits
Virtual Address
(BF8F_#)
2016-2021 Microchip Technology Inc.
TABLE 4-7:
Virtual Address
(BF8F_#)
Register
Name
8420
SBT1ELOG1
8424
SBT1ELOG2
8428
SBT1ECON
8430
SBT1ECLRS
SBT1REG0
8450
SBT1RD0
8458
SBT1WR0
8480
SBT1REG2
8490
SBT1RD2
8498
SBT1WR2
84A0
SBT1REG3
2016-2021 Microchip Technology Inc.
84B0
SBT1RD3
84B8
SBT1WR3
84C0
SBT1REG4
84D0
SBT1RD4
84D8
SBT1WR4
Legend:
Note:
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
xxxx
31:16
—
All
Resets
Bit Range
Bits
8438 SBT1ECLRM
8440
SYSTEM BUS TARGET 1 REGISTER MAP
—
GROUP
CLEAR 0000
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
PRI
—
31:16
GROUP1 GROUP0 xxxx
—
—
BASE
xxxx
SIZE
—
—
—
xxxx
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
PRI
—
31:16
GROUP1 GROUP0 xxxx
—
—
BASE
xxxx
SIZE
—
—
—
xxxx
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
PRI
—
31:16
GROUP1 GROUP0 xxxx
—
—
BASE
xxxx
SIZE
—
—
—
xxxx
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
xxxx
GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP1 GROUP0 xxxx
BASE
15:0
0000
CLEAR 0000
BASE
15:0
0000
0000
GROUP1 GROUP0 xxxx
—
—
xxxx
GROUP1 GROUP0 xxxx
PIC32MK GP/MC Family
DS60001402H-page 79
TABLE 4-9:
Virtual Address
(BF8F_#)
Register
Name
84E0
SBT1REG5
SYSTEM BUS TARGET 1 REGISTER MAP (CONTINUED)
84F0
SBT1RD5
84F8
SBT1WR5
Legend:
Note:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
PRI
—
31:16
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
xxxx
—
—
xxxx
BASE
15:0
BASE
All
Resets
Bits
Bit Range
2016-2021 Microchip Technology Inc.
TABLE 4-9:
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
GROUP1 GROUP0 xxxx
—
—
xxxx
GROUP1 GROUP0 xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
PIC32MK GP/MC Family
DS60001402H-page 80
8824
SBT2ELOG2
8828
SBT2ECON
8830
SBT2ECLRS
8838 SBT2ECLRM
8840
SBT2REG0
8850
SBT2RD0
8858
SBT2WR0
8860
SBT2REG1
2016-2021 Microchip Technology Inc.
8870
SBT2RD1
8878
SBT2WR1
8880
SBT2REG2
8890
SBT2RD2
8898
SBT2WR2
Legend:
Note:
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
All
Resets
Register
Name
SBT2ELOG1
Bit Range
Virtual Address
(BF8F_#)
8820
SYSTEM BUS TARGET 2 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
xxxx
31:16
—
—
GROUP
CLEAR 0000
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
PRI
—
31:16
GROUP1 GROUP0 xxxx
—
—
BASE
xxxx
SIZE
—
—
—
xxxx
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
PRI
—
31:16
GROUP1 GROUP0 xxxx
—
—
BASE
xxxx
SIZE
—
—
—
xxxx
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
xxxx
GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP1 GROUP0 xxxx
BASE
15:0
0000
CLEAR 0000
BASE
15:0
0000
0000
GROUP1 GROUP0 xxxx
—
—
xxxx
GROUP1 GROUP0 xxxx
PIC32MK GP/MC Family
DS60001402H-page 81
TABLE 4-10:
8C20 SBT3ELOG1
8C24 SBT3ELOG2
8C28
SBT3ECON
8C30 SBT3ECLRS
8C38 SBT3ECLRM
8C40
SBT3REG0
SBT3RD0
8C58
SBT3WR0
8C60
SBT3REG1
8C70
SBT3RD1
8C78
SBT3WR1
8C80
SBT3REG2
DS60001402H-page 82
8C90
SBT3RD2
8C98
SBT3WR2
Legend:
Note:
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
All
Resets
Bits
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
xxxx
31:16
—
—
GROUP
CLEAR 0000
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
PRI
—
31:16
GROUP1 GROUP0 xxxx
—
—
BASE
xxxx
SIZE
—
—
—
xxxx
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
PRI
—
31:16
GROUP1 GROUP0 xxxx
—
—
BASE
xxxx
SIZE
—
—
—
xxxx
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-6 for the actual reset values.
xxxx
GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP1 GROUP0 xxxx
BASE
15:0
0000
CLEAR 0000
BASE
15:0
0000
0000
GROUP1 GROUP0 xxxx
—
—
xxxx
GROUP1 GROUP0 xxxx
PIC32MK GP/MC Family
8C50
SYSTEM BUS TARGET 3 REGISTER MAP
Bit Range
Register
Name
Virtual Address
(BF8F_#)
2016-2021 Microchip Technology Inc.
TABLE 4-11:
PIC32MK GP/MC Family
REGISTER 4-2:
Bit
Range
31:24
23:16
15:8
7:0
SBFLAG: SYSTEM BUS STATUS FLAG REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
—
—
—
—
T3PGV
T2PGV
T1PGV
T0PGV
Legend:
R = Readable bit
-n = Value at POR
bit 31-4
bit 3-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Unimplemented: Read as ‘0’
T3PGV:T0PGV: Target Permission Group Violation Status bits
Refer to Table 4-6 for the list of available targets and their descriptions.
1 = Target is reporting a Permission Group (PG) violation
0 = Target is not reporting a PG violation
Note:
All errors are cleared at the source, that is, SBTxELOG1, SBTxELOG2, SBTxECLRS, or SBTxECLRM
registers.
2016-2021 Microchip Technology Inc.
DS60001402H-page 83
PIC32MK GP/MC Family
REGISTER 4-3:
Bit
Range
SBTxELOG1: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 1
(‘x’ = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0, C
U-0
U-0
U-0
R/W-0, C
R/W-0, C
R/W-0, C
R/W-0, C
U-0
U-0
31:24
23:16
15:8
MULTI
—
—
—
U-0
U-0
U-0
U-0
CODE
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
INITID
7:0
REGION
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U-0
—
CMD
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
bit 31
MULTI: Multiple Permission Violations Status bit
This bit is cleared by writing a ‘1’.
1 = Multiple errors have been detected
0 = No multiple errors have been detected
bit 30-28 Unimplemented: Read as ‘0’
bit 27-24 CODE: Error Code bits
Indicates the type of error that was detected. These bits are cleared by writing a ‘1’.
1111 = Reserved
1101 = Reserved
•
•
•
0011 = Permission violation
0010 = Reserved
0001 = Reserved
0000 = No error
bit 23-16 Unimplemented: Read as ‘0’
bit 15-8 INITID: Initiator ID of Requester bits
11111111 = Reserved
•
•
•
00001111 = Reserved
00001110 = Reserved
00001101 = CAN4
00001100 = CAN3
00001011 = CAN2
00001010 = CAN1
00001001 = USB2
00001000 = USB1
00000111 = ADC0-ADC5, ADC7
00000110 = Reserved
00000101 = Flash Controller
00000100 = DMA Read
00000011 = DMA Read
00000010 = CPU (CPUPRI (CFGCON) = 1)
00000001 = CPU (CPUPRI (CFGCON) = 0)
00000000 = Reserved
Note:
Refer to Table 4-6 for the list of available targets and their descriptions.
DS60001402H-page 84
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 4-3:
bit 7-4
bit 3
bit 2-0
Note:
SBTxELOG1: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 1
(‘x’ = 0-3) (CONTINUED)
REGION: Requested Region Number bits
1111 - 0000 = Target’s region that reported a permission group violation
Unimplemented: Read as ‘0’
CMD: Transaction Command of the Requester bits
111 = Reserved
110 = Reserved
101 = Write (a non-posted write)
100 = Reserved
011 = Read (a locked read caused by a Read-Modify-Write transaction)
010 = Read
001 = Write
000 = Idle
Refer to Table 4-6 for the list of available targets and their descriptions.
2016-2021 Microchip Technology Inc.
DS60001402H-page 85
PIC32MK GP/MC Family
REGISTER 4-4:
Bit
Range
31:24
23:16
15:8
7:0
SBTxELOG2: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 2 (‘x’ = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R-0
R-0
—
—
—
—
—
—
GROUP
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-3
Unimplemented: Read as ‘0’
bit 1-0
GROUP: Requested Permissions Group bits
11 = Reserved
10 = Reserved
01 = Group 1
00 = Group 0 (default group of CPU at Reset)
Note:
Refer to Table 4-6 for the list of available targets and their descriptions.
REGISTER 4-5:
Bit
Range
31:24
23:16
15:8
7:0
SBTxECON: SYSTEM BUS TARGET ‘x’ ERROR CONTROL REGISTER
(‘x’ = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
ERRP
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-25 Unimplemented: Read as ‘0’
bit 24
ERRP: Error Control bit
1 = Report protection group violation errors
0 = Do not report protection group violation errors
bit 23-0
Unimplemented: Read as ‘0’
Note:
Refer to Table 4-6 for the list of available targets and their descriptions.
DS60001402H-page 86
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 4-6:
Bit
Range
31:24
23:16
15:8
7:0
SBTxECLRS: SYSTEM BUS TARGET ‘x’ SINGLE ERROR CLEAR REGISTER
(‘x’ = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
CLEAR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-1
Unimplemented: Read as ‘0’
bit 0
CLEAR: Clear Single Error on Read bit
A single error as reported through SBTxELOG1 and SBTxELOG2 is cleared by a read of this register.
Note:
Refer to Table 4-6 for the list of available targets and their descriptions.
REGISTER 4-7:
Bit
Range
31:24
23:16
15:8
7:0
SBTxECLRM: SYSTEM BUS TARGET ‘x’ MULTIPLE ERROR CLEAR REGISTER
(‘x’ = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
CLEAR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-1
Unimplemented: Read as ‘0’
bit 0
CLEAR: Clear Multiple Errors on Read bit
Multiple errors as reported through SBTxELOG1 and SBTxELOG2 is cleared by a read of this register.
Note:
Refer to Table 4-6 for the list of available targets and their descriptions.
2016-2021 Microchip Technology Inc.
DS60001402H-page 87
PIC32MK GP/MC Family
REGISTER 4-8:
Bit
Range
31:24
23:16
15:8
7:0
SBTxREGy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ REGISTER
(‘x’ = 0-3; ‘y’ = 0-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W0
R/W-0
R/W0
R/W-0
R/W0
R/W-0
R/W0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
U-0
BASE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BASE
R/W-0
R/W-0
BASE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SIZE
PRI
—
U-0
U-0
U-0
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-10 BASE: Region Base Address bits
bit 9
PRI: Region Priority Level bit
1 = Level 2
0 = Level 1
bit 8
Unimplemented: Read as ‘0’
bit 7-3
SIZE: Region Size bits
Permissions for a region are only active is the SIZE is non-zero.
11111 = Region size = 2(SIZE – 1) x 1024 (bytes)
•
•
•
00001 = Region size = 2(SIZE – 1) x 1024 (bytes)
00000 = Region is not present
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
2:
Refer to Table 4-6 for the list of available targets and their descriptions.
For some target regions, certain bits in this register are read-only with preset values. See Table 4-6 for
more information.
DS60001402H-page 88
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 4-9:
Bit
Range
31:24
23:16
15:8
7:0
SBTxRDy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ READ PERMISSIONS
REGISTER (‘x’ = 0-3; ‘y’ = 0-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R-1
R-1
R-1
R-1
—
—
—
—
GROUP3
GROUP2
GROUP1
GROUP0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-4
Unimplemented: Read as ‘0’
bit 3
GROUP3: Group 3 Read Permissions bits
1 = Privilege Group 3 has read permission
0 = Privilege Group 3 does not have read permission
bit 2
GROUP2: Group 2 Read Permissions bits
1 = Privilege Group 2 has read permission
0 = Privilege Group 2 does not have read permission
bit 1
GROUP1: Group 1 Read Permissions bits
1 = Privilege Group 1 has read permission
0 = Privilege Group 1 does not have read permission
bit 0
GROUP0: Group 0 Read Permissions bits
1 = Privilege Group 0 has read permission
0 = Privilege Group 0 does not have read permission
Note 1:
2:
Refer to Table 4-6 for the list of available targets and their descriptions.
For some target regions, certain bits in this register are read-only with preset values. See Table 4-6 for
more information.
2016-2021 Microchip Technology Inc.
DS60001402H-page 89
PIC32MK GP/MC Family
REGISTER 4-10:
Bit
Range
31:24
23:16
15:8
7:0
SBTxWRy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ WRITE PERMISSIONS
REGISTER (‘x’ = 0-3; ‘y’ = 0-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
—
GROUP3
GROUP2
GROUP1
GROUP0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-4
Unimplemented: Read as ‘0’
bit 3
GROUP3: Group 3 Write Permissions bits
1 = Privilege Group 3 has write permission
0 = Privilege Group 3 does not have write permission
bit 2
GROUP2: Group 2 Write Permissions bits
1 = Privilege Group 2 has write permission
0 = Privilege Group 2 does not have write permission
bit 1
GROUP1: Group 1 Write Permissions bits
1 = Privilege Group 1 has write permission
0 = Privilege Group 1 does not have write permission
bit 0
GROUP0: Group 0 Write Permissions bits
1 = Privilege Group 0 has write permission
0 = Privilege Group 0 does not have write permission
Note 1:
2:
Refer to Table 4-6 for the list of available targets and their descriptions.
For some target regions, certain bits in this register are read-only with preset values. See Table 4-6 for
more information.
DS60001402H-page 90
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
NOTES:
2016-2021 Microchip Technology Inc.
DS60001402H-page 91
PIC32MK GP/MC Family
5.0
Note:
FLASH PROGRAM MEMORY
This data sheet summarizes the features
of the PIC32MK GP/MC family of devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 52. “Flash Program Memory
with Support for Live Update”
(DS60001193), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
PIC32MK GP/MC devices contain an internal Flash
program memory for executing user code, which
includes the following features:
• Two Flash banks for live update support
• Dual boot support
• Write protection for program and boot Flash
RTSP is performed by software executing from either
Flash or RAM memory. For information about RTSP
techniques, refer to Section 52. “Flash Program
Memory with Support for Live Update”
(DS60001193) in the “PIC32 Family Reference
Manual”.
EJTAG is performed using the EJTAG port of the
device and an EJTAG capable programmer.
ICSP is performed using a serial data connection to the
device and allows much faster programming times than
RTSP.
The EJTAG and ICSP methods are described in the
“PIC32
Flash
Programming
Specification”
(DS60001145), which is available for download from
the Microchip web site (www.microchip.com).
Note:
In PIC32MK GP/MC devices, the Flash
page size is 1024 Instruction Words and
the row size is 128 Instruction Words.
There are three methods by which the user can
program this memory:
• Run-Time Self-Programming (RTSP)
• EJTAG Programming
• In-Circuit Serial Programming (ICSP)
DS60001402H-page 92
2016-2021 Microchip Technology Inc.
Flash Control Registers
Virtual Address
(BF80_#)
Register
Name
TABLE 5-1:
0A00
NVMCON(1)
0A10
NVMKEY
0A20
NVMADDR(1)
FLASH CONTROLLER REGISTER MAP
0A30
NVMDATA0
0A40
NVMDATA1
0A50
NVMDATA2
0A60
NVMDATA3
0A70
NVMSRC
ADDR
0A80
NVMPWP(1)
0A90
NVMBWP(1)
0AA0
NVMCON2(1)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
WR
WREN
WRERR
LVDERR
—
—
—
—
PFSWAP
BFSWAP
—
—
31:16
31:16
0000
0000
0000
NVMADDR
15:0
31:16
0000
0000
NVMDATA0
15:0
31:16
0000
0000
NVMDATA1
15:0
31:16
0000
0000
NVMDATA2
15:0
31:16
0000
0000
NVMDATA3
15:0
31:16
0000
0000
NVMSRCADDR
15:0
PWPULOCK
—
—
—
—
—
—
0000
—
15:0
PWP
8000
PWP
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LBWPULOCK
—
—
LBWP4
LBWP3
LBWP2
LBWP1
LBWP0
UBWPULOCK
—
—
UBWP4
UBWP3
UBWP2
UBWP1
UBWP0
9FDF
—
—
—
—
—
—
—
—
—
ERETRY
SWAPLOCK
—
—
—
31:16
15:0
ERSCNT
LPRD
—
CREAD1
VREAD1
LPRDWS
—
—
—
001F
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more information.
1:
0000
0000
NVMKEY
15:0
31:16
NVMOP
All Resets
Bit Range
Bits
0000
PIC32MK GP/MC Family
DS60001402H-page 93
5.1
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 5-1:
NVMCON: PROGRAMMING CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
31:24
U-0
U-0
U-0
—
—
—
U-0
U-0
—
—
23:16
15:8
7:0
Bit
Bit
29/21/13/5 28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
U-0
R/W-0, HC
R/W-0
R-0, HS, HC R-0, HS, HC
U-0
U-0
U-0
WR(1)
WREN(1)
WRERR(1) LVDERR(1)
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PFSWAP(2) BFSWAP(2,3)
Legend:
U-0
U-0
—
—
NVMOP
HS = Hardware Set
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
WR: Write Control bit(1)
This bit cannot be cleared and can be set only when WREN = 1 and the unlock sequence has been
performed.
1 = Initiate a Flash operation
0 = Flash operation is complete or inactive
bit 14
WREN: Write Enable bit(1)
1 = Enable writes to the WR bit and disables writes to the NVMOP bits
0 = Disable writes to WR bit and enables writes to the NVMOP bits
bit 13
WRERR: Write Error bit(1)
This bit can be cleared only by setting the NVMOP bits = 0000 and initiating a Flash operation.
1 = Program or erase sequence did not complete successfully
0 = Program or erase sequence completed normally
bit 12
LVDERR: Low-Voltage Detect Error bit(1)
This bit can be cleared only by setting the NVMOP bits = 0000 and initiating a Flash operation.
1 = Low-voltage detected (possible data corruption, if WRERR is set)
0 = Voltage level is acceptable for programming
bit 11-8
Unimplemented: Read as ‘0’
bit 7
PFSWAP: Program Flash Bank Swap Control bit(2)
1 = Program Flash Bank 2 is mapped to the lower mapped region and Program Flash Bank 1 is mapped to
the upper mapped region
0 = Program Flash Bank 1 is mapped to the lower mapped region and Program Flash Bank 2 is mapped to
the upper mapped region
bit 6
BFSWAP: Boot Flash Bank Swap Control bit(2,3)
1 = Boot Flash Bank 2 is mapped to the lower boot region and program Boot Flash Bank 1 is mapped to the
upper boot region
0 = Boot Flash Bank 1 is mapped to the lower boot region and program Boot Flash Bank 2 is mapped to the
upper boot region
bit 5-4
Unimplemented: Read as ‘0’
Note 1:
2:
These bits are only reset by a Power-on Reset (POR) and are not affected by other reset sources.
This bit can only be modified when the WREN bit = 0, the NVMKEY unlock sequence is satisfied, and the
SWAPLOCK bits (NVMCON2) are cleared to ‘0’.
The BFSWAP value is determined by the values of the user-programmed Sequence Numbers in each
boot panel.
3:
DS60001402H-page 94
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 5-1:
bit 3-0
NVMCON: PROGRAMMING CONTROL REGISTER (CONTINUED)
NVMOP: NVM Operation bits
These bits are only writable when WREN = 0.
1111 = Reserved
•
•
•
1000 = Reserved
0111 = Program erase operation: erase all of program Flash memory (all pages must be unprotected,
PWP = 0x000000)
0110 = Upper program Flash memory erase operation: erases only the upper mapped region of program
Flash (all pages in that region must be unprotected)
0101 = Lower program Flash memory erase operation: erases only the lower mapped region of program
Flash (all pages in that region must be unprotected)
0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected
0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected
0010 = Quad Word (128-bit) program operation: programs the 128-bit Flash word selected by NVMADDR,
if it is not write-protected
0001 = Word program operation: programs word selected by NVMADDR, if it is not write-protected
0000 = No operation
Note 1:
2:
3:
These bits are only reset by a Power-on Reset (POR) and are not affected by other reset sources.
This bit can only be modified when the WREN bit = 0, the NVMKEY unlock sequence is satisfied, and the
SWAPLOCK bits (NVMCON2) are cleared to ‘0’.
The BFSWAP value is determined by the values of the user-programmed Sequence Numbers in each
boot panel.
2016-2021 Microchip Technology Inc.
DS60001402H-page 95
PIC32MK GP/MC Family
REGISTER 5-2:
NVMKEY: PROGRAMMING UNLOCK REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
31:24
W-0
W-0
W-0
Bit
Bit
28/20/12/4 27/19/11/3
W-0
W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY
23:16
W-0
W-0
W-0
W-0
W-0
NVMKEY
15:8
W-0
W-0
W-0
W-0
W-0
NVMKEY
7:0
W-0
W-0
W-0
W-0
W-0
NVMKEY
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
Note:
W = Writable bit
‘1’ = Bit is set
NVMKEY: Unlock Register bits
These bits are write-only, and read as ‘0’ on any read
This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.
REGISTER 5-3:
NVMADDR: FLASH ADDRESS REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
31:24
R/W-0
R/W-0
R/W-0
23:16
R/W-0
15:8
R/W-0
7:0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR(1)
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR(1)
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR(1)
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR(1)
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
NVMADDR: Flash Address bits(1)
NVMOP
Selection
Flash Address Bits (NVMADDR)
Page Erase
Row Program
Word Program
Quad Word Program
Note 1:
Note:
Address identifies the page to erase (NVMADDR are ignored).
Address identifies the row to program (NVMADDR are ignored).
Address identifies the word to program (NVMADDR are ignored).
Address identifies the quad word (128-bit) to program (NVMADDR bits are
ignored).
For all other NVMOP bit settings, the Flash address is ignored. See the NVMCON
register (Register 5-1) for additional information on these bits.
The bits in this register are only reset by a POR and are not affected by other reset sources.
DS60001402H-page 96
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 5-4:
NVMDATAx: FLASH DATA REGISTER (x = 0-3)
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
31:24
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
23:16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
15:8
R/W-0
R/W-0
R/W-0
R/W-0
7:0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
R/W-0
NVMDATA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
x = Bit is unknown
NVMDATA: Flash Data bits
Word Program: Writes NVMDATA0 to the target Flash address defined in NVMADDR
Quad Word Program: Writes NVMDATA3:NVMDATA2:NVMDATA1:NVMDATA0 to the target Flash address
defined in NVMADDR. NVMDATA0 contains the Least Significant Instruction Word.
The bits in this register are only reset by a POR and are not affected by other reset sources.
REGISTER 5-5:
NVMSRCADDR: SOURCE DATA ADDRESS REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
31:24
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR
23:16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR
15:8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR
7:0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
x = Bit is unknown
NVMSRCADDR: Source Data Address bits
The system physical address of the data to be programmed into the Flash when the NVMOP bits
(NVMCON) are set to perform row programming.
The bits in this register are only reset by a POR and are not affected by other reset sources.
2016-2021 Microchip Technology Inc.
DS60001402H-page 97
PIC32MK GP/MC Family
REGISTER 5-6:
Bit
Range
31:24
23:16
NVMPWP: PROGRAM FLASH WRITE-PROTECT REGISTER
Bit
31/23/15/7
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
PWPULOCK
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
PWP
15:8
R/W-0
R/W-0
R-0
R-0
7:0
R-0
R-0
R-0
R-0
R-0
PWP
R-0
PWP
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
PWPULOCK: Program Flash Memory Page Write-protect Unlock bit
1 = Register is not locked and can be modified
0 = Register is locked and cannot be modified
This bit is only clearable and cannot be set except by any reset.
bit 30-24 Unimplemented: Read as ‘0’
bit 23-0
Note:
PWP: Flash Program Write-protect (Page) Address bits
Physical memory below address 0x1Dxxxxxx is write protected, where ‘xxxxxx’ is specified by PWP.
When PWP has a value of ‘0’, write protection is disabled for the entire program Flash. If the specified
address falls within the page, the entire page and all pages below the current page will be protected.
The bits in this register are only writable when the NVMKEY unlock sequence is followed.
DS60001402H-page 98
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 5-7:
NVMBWP: FLASH BOOT (PAGE) WRITE-PROTECT REGISTER
Bit
Range
Bit
31/23/15/7
31:24
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
R/W-1
U-0
LBWPULOCK
23:16
15:8
7:0
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
LBWP4(1)
LBWP3(1)
LBWP2(1)
LBWP1(1)
LBWP0(1)
R/W-1
r-1
U-0
R/W-1
R/W-1
UBWPULOCK
—
—
UBWP4(1) UBWP3(1)
Legend:
R/W-1
R/W-1
R/W-1
UBWP2(1)
UBWP1(1)
UBWP0(1)
r = Reserved
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
LBWPULOCK: Lower Boot Alias Write-protect Unlock bit
1 = LBWPx bits are not locked and can be modified
0 = LBWPx bits are locked and cannot be modified
This bit is only clearable and cannot be set except by any reset.
bit 14-13 Unimplemented: Read as ‘0’
bit 12
LBWP4: Lower Boot Alias Page 4 Write-protect bit(1)
1 = Write protection for physical address 0x01FC10000 through 0x1FC13FFF enabled
0 = Write protection for physical address 0x01FC10000 through 0x1FC13FFF disabled
bit 11
LBWP3: Lower Boot Alias Page 3 Write-protect bit(1)
1 = Write protection for physical address 0x01FC0C000 through 0x1FC0FFFF enabled
0 = Write protection for physical address 0x01FC0C000 through 0x1FC0FFFF disabled
bit 10
LBWP2: Lower Boot Alias Page 2 Write-protect bit(1)
1 = Write protection for physical address 0x01FC08000 through 0x1FC0BFFF enabled
0 = Write protection for physical address 0x01FC08000 through 0x1FC0BFFF disabled
bit 9
LBWP1: Lower Boot Alias Page 1 Write-protect bit(1)
1 = Write protection for physical address 0x01FC04000 through 0x1FC07FFF enabled
0 = Write protection for physical address 0x01FC04000 through 0x1FC07FFF disabled
bit 8
LBWP0: Lower Boot Alias Page 0 Write-protect bit(1)
1 = Write protection for physical address 0x01FC00000 through 0x1FC03FFF enabled
0 = Write protection for physical address 0x01FC00000 through 0x1FC03FFF disabled
bit 7
UBWPULOCK: Upper Boot Alias Write-protect Unlock bit
1 = UBWPx bits are not locked and can be modified
0 = UBWPx bits are locked and cannot be modified
This bit is only user-clearable and cannot be set except by any reset.
bit 6
Reserved: This bit is reserved for use by development tools
bit 5
Unimplemented: Read as ‘0’
Note 1:
These bits are only available when the NVMKEY unlock sequence is performed and the associated Lock
bit (LBWPULOCK or UBWPULOCK) is set.
Note:
The bits in this register are only writable when the NVMKEY unlock sequence is followed.
2016-2021 Microchip Technology Inc.
DS60001402H-page 99
PIC32MK GP/MC Family
REGISTER 5-7:
NVMBWP: FLASH BOOT (PAGE) WRITE-PROTECT REGISTER
bit 4
UBWP4: Upper Boot Alias Page 4 Write-protect bit(1)
1 = Write protection for physical address 0x01FC30000 through 0x1FC33FFF enabled
0 = Write protection for physical address 0x01FC30000 through 0x1FC33FFF disabled
bit 3
UBWP3: Upper Boot Alias Page 3 Write-protect bit(1)
1 = Write protection for physical address 0x01FC2C000 through 0x1FC2FFFF enabled
0 = Write protection for physical address 0x01FC2C000 through 0x1FC2FFFF disabled
bit 2
UBWP2: Upper Boot Alias Page 2 Write-protect bit(1)
1 = Write protection for physical address 0x01FC28000 through 0x1FC2BFFF enabled
0 = Write protection for physical address 0x01FC28000 through 0x1FC2BFFF disabled
bit 1
UBWP1: Upper Boot Alias Page 1 Write-protect bit(1)
1 = Write protection for physical address 0x01FC24000 through 0x1FC27FFF enabled
0 = Write protection for physical address 0x01FC24000 through 0x1FC27FFF disabled
bit 0
UBWP0: Upper Boot Alias Page 0 Write-protect bit(1)
1 = Write protection for physical address 0x01FC20000 through 0x1FC23FFF enabled
0 = Write protection for physical address 0x01FC20000 through 0x1FC23FFF disabled
Note 1:
These bits are only available when the NVMKEY unlock sequence is performed and the associated Lock
bit (LBWPULOCK or UBWPULOCK) is set.
Note:
The bits in this register are only writable when the NVMKEY unlock sequence is followed.
DS60001402H-page 100
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 5-8:
NVMCON2: FLASH PROGRAMMING CONTROL REGISTER 2
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ERSCNT
23:16
15:8
U-0
U-0
U-0
—
—
—
U-0
R/W-0
R/W-0
(1)
LPRD
7:0
R/W-0
LPRDWS(1)
R/W-0
(1)
CREAD1
VREAD1
U-0
(1)
U-0
—
—
ERETRY
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
SWAPLOCK
—
—
—
—
—
—
R/W-0
—
R/W-0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit
28
31- ERSCNT: Erase Retry State Count bits
bit
21
27- Unimplemented: Read as ‘0’
x = Bit is unknown
These bits can be used by software to track the erase retry state count in the event of a Host Clear
or BOR. These bits are purely for software tracking purpose and are not used by hardware in any
way.
bit 2016
LPRDWS: Wait State bits(1)
11111 = 31 Wait States (32 total System Clocks)
11110 = 30 Wait States (31 total System Clocks)
•
•
•
00010 = 2 Wait States (3 total System Clocks)
00001 = 1 Wait State (2 total System Clocks)
00000 = 0 Wait State (1 total System Clock)
Note:
When VREAD1 = 1, NVMWS only affects the panel containing NVMADDR. When LPRD =
1, LPRDWS affects all reads to all panels.
Required Flash Wait States
LPRDWS
Note 1:
2:
bit 15
SYSCLK (MHz)
3 - Wait State
0 < SYSCLK < 60 MHz
4 - Wait State
60 MHz < SYSCLK < 80 MHz
5 - Wait State
80 MHz < SYSCLK 120 MHz
When the LPRD bit = 0, Flash read access wait states are governed by the PFMWS bits
(CHECON).
When the LPRD bit = 1, Flash read access wait states are governed by the LPRDWS
bits.
LPRD: Low-Power Read Control bit(1)
1 = Configures Flash for Low Power reads (increases access time).
0 = Configures Flash for Low Latency reads
When LPRD = 1, the LPRDWS bits control the Flash wait states; otherwise, the PFMWS bits
control the Flash wait states.
Note 1:
This bit can only be modified when the WREN bit = 0, and the NVMKEY unlock sequence is satisfied.
2016-2021 Microchip Technology Inc.
DS60001402H-page 101
PIC32MK GP/MC Family
REGISTER 5-8:
NVMCON2: FLASH PROGRAMMING CONTROL REGISTER 2 (CONTINUED)
bit 14
Unimplemented: Read as ‘0’
bit 13
CREAD1: Compare Read of Logic 1 bit(1)
1 = Compare Read is enabled (only if VERIFYREAD1 = 1)
0 = Compare Read is disabled
Compare Read 1 causes all bits in a Flash Word to be evaluated during the read. If all bits are ‘1’, the lowest
Word in the Flash Word evaluates to 0x00000001, all other words are 0x00010000. If any bit is ‘0’, the read
evaluates to 0x00000000 for all Words in the Flash Word.
bit 12
VREAD1: Verify Read of Logic 1 Control bit(1)
1 = Selects Erase Retry Procedure with Verify Read
0 = Selects Single Erase w/o Verify Read
When VREAD1 = 1, Flash wait state control is from the LPRDWS bits for the panel containing
NVMADDR.
bit 11-10 Unimplemented: Read as ‘0’
bit 9-8
ERETRY: Erase Retry Control bits
11 = Erase strength for last retry cycle
10 = Erase strength for third retry cycle
01 = Erase strength for second retry cycle
00 = Erase strength for first retry cycle
The user application should start with '00' (first retry cycle) and move on to higher strength if the
programming does not complete.
This bit is used only when VREAD1 = 1 and when VREAD1 = 1.
bit 7-6
SWAPLOCK: Flash Memory Swap Lock Control bits
11 = PFSWAP and BFSWAP are not writable and SWAPLOCK is not writable
10 = PFSWAP and BFSWAP are not writable and SWAPLOCK is writable
01 = PFSWAP and BFSWAP are not writable and SWAPLOCK is writable
00 = PFSWAP and BFSWAP are writable and SWAPLOCK is writable
bit 5-0
Unimplemented: Read as ‘0’
Note 1:
This bit can only be modified when the WREN bit = 0, and the NVMKEY unlock sequence is satisfied.
DS60001402H-page 102
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
NOTES:
2016-2021 Microchip Technology Inc.
DS60001402H-page 103
PIC32MK GP/MC Family
6.0
Note:
DATA EEPROM
This data sheet summarizes the
features of the PIC32MK GP/MC family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 58. “Data
EEPROM” (DS60001341), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
6.1
Data EEPROM Flash
Table 6-1 provides the status of the Data EEPROM
Flash.
TABLE 6-1:
Data EE Wait Status
EEWS bits
(CFGCON2) =
The Data EEPROM module provides the following
features:
• 1K x 32-bit Emulated Data EEPROM using the 1K
x 16 x 33-bit (66 KB)
• Register-based indirect access
• Register-based, non-memory mapped, SFR
Program/Erase/Read interface
• Read:
- Word read
- Read start Control bit and read complete status
flag
- Read complete interrupt
• Program/Erase:
- No user erase required prior to program
- Hardware Word program verify
- Automatic page erase as part of wear-leveling
scheme
- Hardware page erase verify
- Bulk and page erase
- Write complete and error interrupts
• Brown-out protection for all commands
• Concurrent Data EEPROM read with Program
Flash read/write
• Endurance:
- 160K program cycles per address location
- Transparent wear-leveling scheme
- No software overhead
- Automatic page erase (once every 17
program write operations)
- “Worn out” page detection and error flag
- “Imminent Page Erase” prediction status flag
to allow user to schedule wear leveling page
erasure
• Low-power features:
- Always in stand-by unless accessed
- Power down in Sleep and/or Idle mode
- Independent Data EEPROM Flash power
down in Idle Control bit
DS60001402H-page 104
DATA EEPROM FLASH
Note 1:
2:
PBCLK (FSYSCLK /
PBDIV bits
(PB2DIV))
0
0-39 MHz
1
40-59 MHz
2
60-79 MHz
3
80-97 MHz
4
98-117 MHz
5
118-120 MHz
The Data EEPROM Flash must have its
calibration trim bits reinitialized after each
cold power-up before any attempted
accesses. Refer to Section 58. “Data
EEPROM” (DS60001341) of the “PIC32
Family Reference Manual” for additional
information.
Before any attempts to access the Data
EEPROM module, the user application
must configure the appropriate number of
Wait states by configuring the EEWS
bits (CFGCON2< 7:0>) according to the
details provided in Table 6-1.
2016-2021 Microchip Technology Inc.
Control Registers
DATA EEPROM SFR SUMMARY
9000 EECON(1)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
—
—
19/3
18/2
—
—
17/1
16/0
—
—
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
15:0
ON
RDY
SIDL
ABORT
—
—
—
—
RW
WREN
9010 EEKEY(2)
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9020 EEADDR(3)
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
15:0
9030 EEDATA
Legend:
Note 1:
2:
3:
ERR
ILW
CMD
0000
EEKEY
—
All Resets
Bit Range
Bits
Register
Name
Virtual Address
(BF82_#)
TABLE 6-2:
0000
EEADDR
0000
0000
31:16
EEDATA
0000
15:0
EEDATA
0000
— = unimplemented, read as ‘0’.
This register has corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more information.
This register is a write-only register. Reads always result in ‘0’.
Because the EEPROM word size is 32 bits, for reads and writes the last two bits (EEADDR) must always be ‘0’.
PIC32MK GP/MC Family
DS60001402H-page 105
6.2
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 6-1:
Bit
Range
31:24
23:16
15:8
7:0
EECON(2): EEPROM CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0, HC
R-0
R/W-0
R/W-0, HC
U-0
U-0
U-0
U-0
SIDL
ABORT
ON
R/W-0, HC
RW
RDY
R/W-0
(1)
WREN
Legend:
R = Readable bit
-n = Value at POR
—
—
—
—
R/W-0, HS, HC R/W-0, HS, HC
R/W-0, HS
R/W-0
R/W-0
R/W-0
ERR
ILW
HS = Hardware settable
W = Writable bit
‘1’ = Bit is set
CMD(1)
HC = Hardware clearable
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Data EEPROM Power Control bit
1 = Data EEPROM is enabled
0 = Data EEPROM is disabled
bit 14
bit 13
bit 12
bit 11-8
bit 7
Attempting to clear this bit will have no effect if the RW bit is set. In addition, this bit is not cleared during
Sleep if the FSLEEP bit in the DEVCFG register is set.
RDY: Data EEPROM Ready bit
1 = Data EEPROM is ready for access
0 = Data EEPROM is not ready for access
RDY is cleared by hardware whenever a POR or BOR event occurs. It is set by hardware when the
ON bit = 1 and the power-up timer has expired.
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters in Idle mode
0 = Continue operation in Idle mode
ABORT: Data EEPROM Abort Operation Control bit
1 = Set by software to abort the on-going write command as soon as possible
0 = Data EEPROM panel is ready/Normal operation
Unimplemented: Read as ‘0’
RW: Start Command Execution Control bit
When WREN = 1:
1 = Start memory word program or erase command
0 = Cleared by hardware to indicate program or erase operation has completed
When WREN = 0:
1 = Start memory word read command
0 = Cleared by hardware to indicate read operation has completed
bit 6
Note 1:
2:
This bit cannot be set if the ON bit = 0, or if the ON bit = 1 and the power-up timer has not yet expired (i.e.,
The RDY bit = 0). A BOR reset will indirectly clear this bit by forcing any executing command to terminate
and to clear the RW bit afterwards.
WREN: Data EEPROM Write Enable Control bit(1)
1 = Enables program or erase operations
0 = Disables program or erase of memory elements, and enables read operations
This bit cannot be modified when the RW bit = 1.
The Configuration Write command (CMD = 100) must be executed after any power-up before the
Data EEPROM is ready for use. For additional information, refer to Example 58-1 “Data EEPROM Initialization Code” in Section 58. “Data EEPROM” (DS60001341).
DS60001402H-page 106
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 6-1:
bit 5-4
bit 3
bit 2-0
EECON(2): EEPROM CONTROL REGISTER (CONTINUED)
ERR: Data EEPROM Sequence Error Status bits
11 = A BOR event has occurred
10 = An attempted execution of a read or write operation with an invalid write OR command with a
misaligned address (EEADDR 00)
01 = A Bulk or Page Erase or a Word Program verify error has occurred
00 = No error condition
These bits can be cleared by software, or as the result of the successful execution of the next operation, or
when the ON bit = 0. These bits may also be set by software (when the RW bit = 0) without affecting the
operation of the module.
ILW: Data EEPROM Imminent Long Write Status bit
1 = The next write to the EEPROM address (held in the EEADDR register) will require more time (~ 20 ms)
than usual
0 = The next write to the EEPROM address (held in the EEADDR register) will be a normal write cycle
This bit can be cleared by software, or as the result of a write to the EEADDR register. This bit is set by
hardware after a write command.
CMD: Data EEPROM Command Selection bits(1)
These bits are cleared only on a POR event.
111 = Reserved
•
•
•
100 = Configuration register Write command (WREN bit must be set)(2)
011 = Data EEPROM memory Bulk Erase command (WREN bit must be set)
010 = Data EEPROM memory Page Erase command (WREN bit must be set)
001 = Word Write command (WREN bit must be set)
000 = Word Read command (WREN bit must be clear)
Note 1:
2:
This bit cannot be modified when the RW bit = 1.
The Configuration Write command (CMD = 100) must be executed after any power-up before the
Data EEPROM is ready for use. For additional information, refer to Example 58-1 “Data EEPROM Initialization Code” in Section 58. “Data EEPROM” (DS60001341).
2016-2021 Microchip Technology Inc.
DS60001402H-page 107
PIC32MK GP/MC Family
REGISTER 6-2:
Bit
Range
31:24
23:16
15:8
7:0
EEKEY: EEPROM KEY REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
EEKEY
W-0
EEKEY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
EEKEY: Data EEPROM Key bits
Writing the value 0xEDB7 followed by writing the value 0x1248 to this register will unlock the EECON
register for write/erase operations. Reads have no effect on this register and return ‘0’.
Writing any other value will lock the EECON register.
REGISTER 6-3:
Bit
Range
31:24
23:16
15:8
7:0
EEADDR(3): EEPROM ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
(1,2)
R/W-0
R/W-0
R/W-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
EEADDR
R/W-0
(1)
R/W-0
EEADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-12 Unimplemented: Read as ‘0’
bit 11-0
Note
1:
2:
3:
EEADR: Data EEPROM Address bits(1)
This register holds the address in the EEPROM memory upon which to operate. EEADDR must
always be ‘00’ when the RW bit (EECON) is set or an error will occur.
The bits in this register cannot be modified when the RW bit (EECON) = 1.
EEDATA is organized in 32-bit words, not by byte, therefore the EEADDR bit must always be 32-bit word address aligned. Check that the
EEADDR bits are = 0’b00 at the beginning of any command when the user sets EEGO to ‘1’. If the EEADDR bits are not
0’b00, it will forcefully clear the EEGO bit to ‘0’ and will also set the ERR bits (EECON) to 0’b10.
This register cannot be "watched" in debug mode. In order to read the most recent contents of this register, we recommend storing contents of the SFR in a 32-bit variable just before halting the CPU in debug mode.
DS60001402H-page 108
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 6-4:
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEDATA(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEDATA(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEDATA(1)
R/W-0
7:0
EEDATA(2): EEPROM DATA REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
EEDATA(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
EEDATA: Data EEPROM Data bits(1)
This register holds the data in the EEPROM memory to store during write operations, or the data from
memory after a read operation.
Note 1:
2:
These bits cannot be modified when the RW bit (EECON) = 1. In addition, reading this register, when
the RW bit = 1 may not return valid data, as the read operation may not have completed.
This register cannot be "watched" in debug mode. In order to read the most recent contents of this register,
we recommend storing contents of the SFR in a 32-bit variable just before halting the CPU in debug mode.
2016-2021 Microchip Technology Inc.
DS60001402H-page 109
PIC32MK GP/MC Family
7.0
RESETS
Note:
This data sheet summarizes the features
of the PIC32MK GP/MC family of devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 7. “Resets” (DS60001118),
which is available from the Documentation
> Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
FIGURE 7-1:
The Reset module combines all Reset sources and
controls the device Host Reset signal, SYSRST. The
device Reset sources are as follows:
•
•
•
•
•
•
•
Power-on Reset (POR)
Host Clear Reset pin (MCLR)
Software Reset (SWR)
Watchdog Timer Reset (WDTR)
Brown-out Reset (BOR)
Configuration Mismatch Reset (CMR)
Deadman Timer Reset (DMTR)
A simplified block diagram of the Reset module is
illustrated in Figure 7-1.
SYSTEM RESET BLOCK DIAGRAM
MCLR
Glitch Filter
Sleep or Idle
MCLR
DMTR/WDTR
NMI
Time-out
WDT
Time-out
DMT
Time-out
Voltage Regulator Enabled
POR
SYSRST
VDD Rise
Detect
VDD
Configuration
Mismatch
Reset
Brown-out
Reset
BOR
CMR
SWR
Software Reset
VBAT Monitor
VBAT POR
VBAT
VBATRST (RTCC, SOSC, LPRC)
VBAT BOR
DS60001402H-page 110
2016-2021 Microchip Technology Inc.
Reset Control Registers
Virtual Address
(BF80_#)
Register
Name
TABLE 7-1:
1240
RCON
1250
1260
1270
RESETS REGISTER MAP
RSWRST
RNMICON
PWRCON
Legend:
31:16
31/15
30/14
PORIO PORCORE
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Bits
—
—
—
—
—
—
—
—
—
—
—
—
VBPOR
VBAT
0003
15:0
—
—
—
—
—
DPSLP
CMR
—
EXTR
SWR
DMTO
WDTO
SLEEP
IDLE
BOR
POR
0003
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SWRST
0000
31:16
—
—
—
—
—
—
DMTO
WDTO
SWNMI
—
—
—
GNMI
---
CF
WDTS
0000
—
—
—
—
—
—
—
0000
—
—
—
VREGS
0000
15:0
NMICNT
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
0000
VREGRUN
VREGSLP
PIC32MK GP/MC Family
DS60001402H-page 111
7.1
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 7-1:
Bit
Range
31:24
23:16
15:8
7:0
RCON: RESET CONTROL REGISTER
Bit
Bit
31/23/15/7 30/22/14/6
Bit
Bit
29/21/13/5 28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0, HS
R/W-0, HS
U-0
U-0
U-0
U-0
U-0
U-0
PORIO
PORCORE
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-1, HS
R/W-1, HS
—
—
—
—
—
—
VBPOR
VBAT
U-0
U-0
U-0
U-0
U-0
R/W-0, HS
R/W-0, HS
U-0
—
—
—
—
—
DPSLP(1)
CMR
—
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
EXTR
SWR
DMTO
WDTO
SLEEP
IDLE
R/W-1, HS
(2)
R/W-1, HS
(2)
Legend:
HS = Hardware Set
BOR
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
PORIO: I/O Voltage POR Flag bit
1 = A Power-up Reset has occurred due to I/O Voltage
0 = A Power-up Reset has not occurred due to I/O Voltage
Note:
bit 30
POR
Set by hardware at detection of an I/O POR event. User software must clear this bit to
view the next detection; however, writing a ‘1’ to this bit does not cause a PORIO.
PORCORE: Core Voltage POR Flag bit
1 = A Power-up Reset has occurred due to Core Voltage
0 = A Power-up Reset has not occurred due to Core Voltage
Note:
Set by hardware at detection of a Core POR event. User software must clear this bit to
view the next detection; however, writing a ‘1’ to this bit does not cause a PORCORE.
bit 29-18 Unimplemented: Read as ‘0’
bit 17
VBPOR: VBPOR Mode Flag bit
1 = A VBAT domain POR has occurred
0 = A VBAT domain POR has not occurred
bit 16
VBAT: VBAT Mode Flag bit
1 = A POR exit from VBAT has occurred (a true POR must be established with the valid VBAT voltage on the
VBAT pin)
0 = A POR exit from VBAT has not occurred
bit 15-11 Unimplemented: Read as ‘0’
bit 10
DPSLP: Deep Sleep Mode Flag bit(1)
1 = Deep Sleep mode has occurred
0 = Deep Sleep mode has not occurred
bit 9
CMR: Configuration Mismatch Reset Flag bit
1 = A Configuration Mismatch Reset has occurred
0 = A Configuration Mismatch Reset has not occurred
bit 8
Unimplemented: Read as ‘0’
bit 7
EXTR: External Reset (MCLR) Pin Flag bit
1 = Host Clear (pin) Reset has occurred
0 = Host Clear (pin) Reset has not occurred
bit 6
SWR: Software Reset Flag bit
1 = Software Reset was executed
0 = Software Reset was not executed
Note 1:
User software must clear this bit to view the next detection.
DS60001402H-page 112
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 7-1:
RCON: RESET CONTROL REGISTER
bit 5
DMTO: Deadman Timer Time-out Flag bit
1 = A DMT time-out has occurred
0 = A DMT time-out has not occurred
bit 4
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT Time-out has occurred
0 = WDT Time-out has not occurred
bit 3
SLEEP: Wake From Sleep Flag bit
1 = Device was in Sleep mode
0 = Device was not in Sleep mode
bit 2
IDLE: Wake From Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
bit 1
BOR: Brown-out Reset Flag bit(1)
1 = Brown-out Reset has occurred
0 = Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit(1)
1 = Power-on Reset has occurred
0 = Power-on Reset has not occurred
Note 1:
User software must clear this bit to view the next detection.
2016-2021 Microchip Technology Inc.
DS60001402H-page 113
PIC32MK GP/MC Family
REGISTER 7-2:
Bit
Range
31:24
23:16
15:8
7:0
RSWRST: SOFTWARE RESET REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
—
—
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
W-0, HC
—
—
—
—
—
—
—
SWRST(1,2)
Legend:
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-1
Unimplemented: Read as ‘0’
bit 0
SWRST: Software Reset Trigger bit(1,2)
1 = Enable software Reset event
0 = No effect
Note 1:
The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section
42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for
details.
Once this bit is set, any read of the RSWRST register will cause a Reset to occur.
2:
DS60001402H-page 114
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 7-3:
Bit
Range
31:24
23:16
15:8
7:0
RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
DMTO
WDTO
R/W-0
U-0
U-0
U-0
R/W-0
U-0
R/W-0, HS, HC
R/W-0
SWNMI
—
—
—
GNMI
—
CF
WDTS
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NMICNT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NMICNT
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clear
W = Writable bit
‘1’ = Bit is set
HS = Hardware Set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25
DMTO: Deadman Timer Time-out Flag bit
1 = DMT time-out has occurred and caused a NMI
0 = DMT time-out has not occurred
Setting this bit will cause a DMT NMI event, and NMICNT will begin counting.
bit 24
WDTO: Watchdog Timer Time-Out Flag bit
1 = WDT time-out has occurred and caused a NMI
0 = WDT time-out has not occurred
Setting this bit will cause a WDT NMI event, and MNICNT will begin counting.
bit 23
SWNMI: Software NMI Trigger.
1 = An NMI will be generated
0 = An NMI will not be generated
bit 22-20 Unimplemented: Read as ‘0’
bit 19
GNMI: General NMI bit
1 = A general NMI event has been detected or a user-initiated NMI event has occurred
0 = A general NMI event has not been detected
bit 18
bit 17
Setting GNMI to a ‘1’ causes a user-initiated NMI event. This bit is also set by writing 0x4E to the
NMIKEY (INTCON) bits.
Unimplemented: Read as ‘0’
CF: Clock Fail Detect bit
1 = FSCM has detected clock failure and caused an NMI
0 = FSCM has not detected clock failure
Note:
On a clock fail event if enabled by the FCKSM bits (DEVCFG1) = ‘0b11, this bit
and the OSCCON bit will be set. The user software must clear both the bits inside the CF
NMI before attempting to exit the ISR. Software or hardware settings of the CF bit
(OSCCON) will cause a CF NMI event and an automatic clock switch to the FRC provided
the FCKSM = ‘0b11. Unlike the CF bit (OSCCON), software or hardware settings of
the CF bit (RNMICON) will cause a CF NMI event but will not cause a clock switch to the
FRC. After a Clock Fail event, a successful user software clock switch if implemented, hardware
will automatically clear the CF bit (RNMICON), but not the CF bit (OSCCON). The CF
bit (OSCCON) must be cleared by software using the OSCCON register unlock procedure.
Note 1:
When a Watchdog Timer NMI event (when not in Sleep mode) or a Deadman Timer NMI event is triggered
the NMICNT will start decrementing. When NMICNT reaches zero, the device is Reset. This NMI reset
counter is only applicable to these two specific NMI events.
Note:
The system unlock sequence must be performed before the SWRST bit is written. Refer to the Section 42.
“Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
2016-2021 Microchip Technology Inc.
DS60001402H-page 115
PIC32MK GP/MC Family
REGISTER 7-3:
bit 16
bit 15-0
RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER
WDTS: Watchdog Timer Time-out in Sleep Mode Flag bit
1 = WDT time-out has occurred during Sleep mode and caused a wake-up from sleep
0 = WDT time-out has not occurred during Sleep mode
Setting this bit will cause a WDT NMI.
NMICNT: NMI Reset Counter Value bits
These bits specify the reload value used by the NMI reset counter.
11111111-00000001 = Number of SYSCLK cycles before a device Reset occurs(1)
00000000 = No delay between NMI assertion and device Reset event
Note 1:
When a Watchdog Timer NMI event (when not in Sleep mode) or a Deadman Timer NMI event is triggered
the NMICNT will start decrementing. When NMICNT reaches zero, the device is Reset. This NMI reset
counter is only applicable to these two specific NMI events.
Note:
The system unlock sequence must be performed before the SWRST bit is written. Refer to the Section 42.
“Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
DS60001402H-page 116
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 7-4:
Bit
Range
31:24
23:16
15:8
7:0
PWRCON: POWER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
—
—
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
VREGS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-1
Unimplemented: Read as ‘0’
bit 0
VREGS: Internal Voltage Regulator Stand-by Enable bit
1 = Voltage regulator will remain active during Sleep
0 = Voltage regulator will go to Stand-by mode during Sleep
2016-2021 Microchip Technology Inc.
x = Bit is unknown
DS60001402H-page 117
PIC32MK GP/MC Family
8.0
Note:
CPU EXCEPTIONS AND
INTERRUPT CONTROLLER
This data sheet summarizes the
features of the PIC32MK GP/MC family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Interrupt
Controller” (DS60001108) and Section
50. “CPU for Devices with MIPS32®
microAptiv™ and M-Class Cores”
(DS60001192), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
PIC32MK GP/MC devices generate interrupt requests
in response to interrupt events from peripheral modules.
The Interrupt Controller module exists outside of the
CPU and prioritizes the interrupt events before
presenting them to the CPU.
The CPU handles interrupt events as part of the
exception handling mechanism, which is described in
8.1 “CPU Exceptions”.
The Interrupt Controller module includes the following
features:
• Up to 216 interrupt sources and vectors with
dedicated programmable offsets, eliminating the
need for redirection.
• Single and multi-vector mode operations.
• Five external interrupts with edge polarity control.
• Interrupt proximity timer.
• Seven user-selectable priority levels for each
vector.
• Four user-selectable subpriority levels within each
priority.
• One shadow register set that can be used for any
priority level, eliminating software context switch and
reducing interrupt latency.
• Software can generate any interrupt.
Table 8-1 provides Interrupt Service routine (ISR)
latency information.
DS60001402H-page 118
2016-2021 Microchip Technology Inc.
ISR LATENCY INFORMATION
User/MPLAB® Harmony Responsibility
Compiler Automatic Run-time
CP0 REGISTER 16, PERCHEEN bit DCHEEN bit
SELECT 0
(CHECON) (CHECON)
Condition
0’b010
0’b1
0’b1
0’b1
0’b00
0’b111
void __ISR(,
ipl7auto)ISR(void)
{
// “n” = Vector Number, see data sheet
// User ISR code
}
257
0’b011
0’b1
0’b1
0’b1
0’b01
0’b011
void __attribute__((interrupt(iplXauto),
at_vector(n), aligned(16))) isr ()
{
// “n”=Vector Number, see data sheet
// “X”=IPL 1-7
// User ISR code
}
43 + (7 – IPL)
(Latency per
interrupt)
Reset Values
Recommended user
optimized CPU and
ISR Latency Settings
(2)
Note
1:
2:
Comment
Interrupt Latency
ICHEEN bit
PREFEN bits PFMWS bits User source file ISR declaration/invocation.
(SYSCLK Cycles)
(CHECON) (CHECON)
CHECON)
Note:
The user is responsible for the ISR declara- (Time from intertion for the fastest ISR latency response.
rupt event to first
user source code
instruction execution inside ISR).
The CPU ISR latency can cause unexpected behavior in high data rate peripherals when a high repetitive rate of CPU interrupts. For example, it is possible that if multiple interrupt sources occur simultaneously, or if a high-speed peripheral like ADC occurs faster than the CPU can read the results from the first original interrupt, then that data may be overwritten by the second interrupt. If the possibility exists in user application that the CPU servicing requirements are less than the combined sum of all possible overlapping interrupt rate specified above, to avoid buffer overflows or data
overwrites, it is recommended to use the DMA to service the data and buffer instead of the CPU.
For the best optimized CPU and ISR performance, to complete the optimization, the user application should define ISRs that use the “at vector” attribute as shown in Table 8-1. In addition, if the ADC
combined sum throughput rate of all the ADC modules in use is greater than (SYSCLK/43) = 2.8 Msps, it is recommended to use the ADC CPU early interrupt generation defined in the ADCxTIME and
ADCEIENx registers. This will reduce the probability of the ADC results being overwritten by the next conversion before the CPU can read the previous ADC result if not using the DMA for ADC. Do not
use the early interrupts if using the ADC in DMA mode.
PIC32MK GP/MC Family
DS60001402H-page 119
TABLE 8-1:
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
Figure 8-1 illustrates the block diagram of the Interrupt
Controller and CPU exceptions.
FIGURE 8-1:
CPU EXCEPTIONS AND INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM
Vector Number and Offset
Interrupt
Requests
Interrupt Controller
Priority Level
CPU Core
(Exception Handling)
Shadow Set Number
SYSCLK
8.1
CPU Exceptions
CPU co-processor 0 contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including boundary cases in
data, external events or program errors. Table 8-2 lists
the exception types in order of priority.
DS60001402H-page 120
2016-2021 Microchip Technology Inc.
Exception Type
(In Order of
Priority)
MIPS32® microAptiv™ MCU CORE EXCEPTION TYPES
Description
Branches to
Status
Bits Set
Debug Bits
EXCCODE
Set
XC32 Function Name
Highest Priority
Reset
Soft Reset
Assertion MCLR or a Power-on Reset (POR).
Assertion of a software Reset.
0xBFC0_0000
0xBFC0_0000
DSS
DINT
EJTAG debug single step.
EJTAG debug interrupt. Caused by the assertion of
the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
Assertion of NMI signal.
0xBFC0_0480
0xBFC0_0480
NMI
Interrupt
Deferred Watch
DIB
WATCH
AdEL
IBE
Instruction
Validity
Exceptions
2016-2021 Microchip Technology Inc.
Execute
Exception
Tr
DDBL/DDBS
WATCH
0xBFC0_0000
Assertion of unmasked hardware or software inter- See Table 8-3.
rupt signal.
Deferred watch (unmasked by K|DM=>!(K|DM)
EBASE+0x180
transition).
EJTAG debug hardware instruction break matched.
0xBFC0_0480
A reference to an address that is in one of the
EBASE+0x180
Watch registers (fetch).
Fetch address alignment error. Fetch reference to
EBASE+0x180
protected address.
Instruction fetch bus error.
EBASE+0x180
EBASE+0x180
An instruction could not be completed because it
was not allowed to access the required resources
(Coprocessor Unusable) or was illegal (Reserved
Instruction). If both exceptions occur on the same
instruction, the Coprocessor Unusable Exception
takes priority over the Reserved Instruction
Exception.
EBASE+0x180
An instruction-based exception occurred: Integer
overflow, trap, system call, breakpoint, floating
point, or DSP ASE state disabled exception.
Execution of a trap (when trap condition is true).
EBASE+0x180
0xBFC0_0480
EJTAG Data Address Break (address only) or
EJTAG data value break on store (address +
value).
A reference to an address that is in one of the
EBASE+0x180
Watch registers (data).
BEV, ERL
BEV, SR,
ERL
—
—
—
—
—
—
DSS
DINT
—
—
BEV, NMI,
ERL
IPL
—
—
—
0x00
See Table 8-3.
WP, EXL
—
0x17
_general_exception_handler
—
EXL
DIB
—
—
0x17
—
_general_exception_handler
EXL
—
0x04
_general_exception_handler
EXL
EXL
—
—
0x06
0x0A or
0x0B
_general_exception_handler
_general_exception_handler
EXL
—
EXL
—
—
DDBL or
DDBS
0x0D
—
_general_exception_handler
—
EXL
—
0x17
_general_exception_handler
_on_reset
_on_reset
—
—
_nmi_handler
0x08-0x0C _general_exception_handler
PIC32MK GP/MC Family
DS60001402H-page 121
TABLE 8-2:
2016-2021 Microchip Technology Inc.
TABLE 8-2:
Exception Type
(In Order of
Priority)
AdEL
AdES
DBE
DDBL
CBrk
MIPS32® microAptiv™ MCU CORE EXCEPTION TYPES (CONTINUED)
Description
Branches to
Status
Bits Set
Debug Bits
EXCCODE
Set
Load address alignment error. User mode load
reference to kernel address.
Store address alignment error. User mode store to
kernel address.
Load or store bus error.
EJTAG data hardware breakpoint matched in load
data compare.
EJTAG complex breakpoint.
EBASE+0x180
EXL
—
0x04
_general_exception_handler
EBASE+0x180
EXL
—
0x05
_general_exception_handler
EBASE+0x180
0xBFC0_0480
EXL
—
—
DDBL
0x07
—
_general_exception_handler
—
0xBFC0_0480
—
DIBIMPR,
DDBLIMPR,
and/or
DDBSIMPR
—
—
XC32 Function Name
Lowest Priority
PIC32MK GP/MC Family
DS60001402H-page 122
PIC32MK GP/MC Family
8.2
Interrupts
The PIC32MK GP/MC family uses variable offsets for
vector spacing. This allows the interrupt vector spacing
to be configured according to application needs. A
unique interrupt vector offset can be set for each vector
using its associated OFFx register.
For details on the Variable Offset feature, refer to
8.5.2 “Variable Offset” in Section 8. “Interrupt
Controller” (DS60001108) of the “PIC32 Family
Reference Manual”.
Table 8-3 provides the Interrupt IRQ, vector and bit
location information.
2016-2021 Microchip Technology Inc.
DS60001402H-page 123
2016-2021 Microchip Technology Inc.
TABLE 8-3:
INTERRUPT IRQ, VECTOR AND BIT LOCATION
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
PIC32MK GP/MC Family
DS60001402H-page 124
Highest Natural Order Priority
Core Timer Interrupt
_CORE_TIMER_VECTOR
0 OFF000
IFS0 IEC0 IPC0
IPC0
No
Core Software Interrupt 0
_CORE_SOFTWARE_0_VECTOR
1 OFF001
IFS0 IEC0 IPC0 IPC0
No
Core Software Interrupt 1
_CORE_SOFTWARE_1_VECTOR
2 OFF002
IFS0 IEC0 IPC0 IPC0
No
External Interrupt 0
_EXTERNAL_0_VECTOR
3 OFF003
IFS0 IEC0 IPC0 IPC0
No
Timer1
_TIMER_1_VECTOR
4 OFF004
IFS0 IEC0 IPC1
IPC1
No
Input Capture 1 Error
_INPUT_CAPTURE_1_ERROR_VECTOR
5 OFF005
IFS0 IEC0 IPC1 IPC1
Yes
Input Capture 1
_INPUT_CAPTURE_1_VECTOR
6 OFF006
IFS0 IEC0 IPC1 IPC1
Yes
Output Compare 1
_OUTPUT_COMPARE_1_VECTOR
7 OFF007
IFS0 IEC0 IPC1 IPC1
No
External Interrupt 1
_EXTERNAL_1_VECTOR
8 OFF008
IFS0 IEC0 IPC2
IPC2
No
Timer2
_TIMER_2_VECTOR
9 OFF009
IFS0 IEC0 IPC2 IPC2
No
Input Capture 2 Error
_INPUT_CAPTURE_2_ERROR_VECTOR
10 OFF010
IFS0 IEC0 IPC2 IPC2
Yes
Input Capture 2
_INPUT_CAPTURE_2_VECTOR
11 OFF011
IFS0 IEC0 IPC2 IPC2
Yes
Output Compare 2
_OUTPUT_COMPARE_2_VECTOR
12 OFF012
IFS0 IEC0 IPC3
IPC3
No
External Interrupt 2
_EXTERNAL_2_VECTOR
13 OFF013
IFS0 IEC0 IPC3 IPC3
No
Timer3
_TIMER_3_VECTOR
14 OFF014
IFS0 IEC0 IPC3 IPC3
No
Input Capture 3 Error
_INPUT_CAPTURE_3_ERROR_VECTOR
15 OFF015
IFS0 IEC0 IPC3 IPC3
Yes
Input Capture 3
_INPUT_CAPTURE_3_VECTOR
16 OFF016
IFS0 IEC0 IPC4
IPC4
Yes
Output Compare 3
_OUTPUT_COMPARE_3_VECTOR
17 OFF017
IFS0 IEC0 IPC4 IPC4
No
External Interrupt 3
_EXTERNAL_3_VECTOR
18 OFF018
IFS0 IEC0 IPC4 IPC4
No
Timer4
_TIMER_4_VECTOR
19 OFF019
IFS0 IEC0 IPC4 IPC4
No
Input Capture 4 Error
_INPUT_CAPTURE_4_ERROR_VECTOR
20 OFF020
IFS0 IEC0 IPC5
IPC5
Yes
Input Capture 4
_INPUT_CAPTURE_4_VECTOR
21 OFF021
IFS0 IEC0 IPC5 IPC5
Yes
Output Compare 4
_OUTPUT_COMPARE_4_VECTOR
22 OFF022
IFS0 IEC0 IPC5 IPC5
No
External Interrupt 4
_EXTERNAL_4_VECTOR
23 OFF023
IFS0 IEC0 IPC5 IPC5
No
Timer5
_TIMER_5_VECTOR
24 OFF024
IFS0 IEC0 IPC6
IPC6
No
Input Capture 5 Error
_INPUT_CAPTURE_5_ERROR_VECTOR
25 OFF025
IFS0 IEC0 IPC6 IPC6
Yes
Input Capture 5
_INPUT_CAPTURE_5_VECTOR
26 OFF026
IFS0 IEC0 IPC6 IPC6
Yes
Output Compare 5
_OUTPUT_COMPARE_5_VECTOR
27 OFF027
IFS0 IEC0 IPC6 IPC6
No
Reserved
—
28
—
—
—
—
—
—
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK General Purpose (GP) Family Features” for the list of available peripherals.
2: This interrupt source is not available on 64-pin devices.
3: This interrupt source is not available on 100-pin devices.
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
2016-2021 Microchip Technology Inc.
Reserved
—
29
—
—
—
—
—
—
Real Time Clock
_RTCC_VECTOR
30 OFF030
IFS0 IEC0 IPC7 IPC7
Yes
Flash Control Event
_FLASH_CONTROL_VECTOR
31 OFF031
IFS0 IEC0 IPC7 IPC7
No
Comparator 1 Interrupt
_COMPARATOR_1_VECTOR
32 OFF032
IFS1 IEC1 IPC8
IPC8
No
Comparator 2 Interrupt
_COMPARATOR_2_VECTOR
33 OFF033
IFS1 IEC1 IPC8 IPC8
Yes
USB1 Interrupts
_USB_1_VECTOR
34 OFF034
IFS1 IEC1 IPC8 IPC8
Yes
SPI1 Fault
_SPI1_FAULT_VECTOR
35 OFF035
IFS1 IEC1 IPC8 IPC8
No
SPI1 Receive Done
_SPI1_RX_VECTOR
36 OFF036
IFS1 IEC1 IPC9
IPC9
No
SPI1 Transfer Done
_SPI1_TX_VECTOR
37 OFF037
IFS1 IEC1 IPC9 IPC9
Yes
UART1 Fault
_UART1_FAULT_VECTOR
38 OFF038
IFS1 IEC1 IPC9 IPC9
Yes
UART1 Receive Done
_UART1_RX_VECTOR
39 OFF039
IFS1 IEC1 IPC9 IPC9
No
UART1 Transfer Done
_UART1_TX_VECTOR
40 OFF040
IFS1 IEC1 IPC10
IPC10
No
Reserved
—
41
—
—
—
—
—
—
Reserved
—
42
—
—
—
—
—
—
Reserved
—
43
—
—
—
—
—
—
PORTA Input Change Interrupt
_CHANGE_NOTICE_A_VECTOR
44 OFF044
IFS1 IEC1 IPC11
IPC11
Yes
PORTB Input Change Interrupt
_CHANGE_NOTICE_B_VECTOR
45 OFF045
IFS1 IEC1 IPC11 IPC11
Yes
PORTC Input Change Interrupt
_CHANGE_NOTICE_C_VECTOR
46 OFF046
IFS1 IEC1 IPC11 IPC11
Yes
PORTD Input Change Interrupt
_CHANGE_NOTICE_D_VECTOR
47 OFF047
IFS1 IEC1 IPC11 IPC11
Yes
PORTE Input Change Interrupt
_CHANGE_NOTICE_E_VECTOR
48 OFF048
IFS1 IEC1 IPC12
IPC12
Yes
PORTF Input Change Interrupt
_CHANGE_NOTICE_F_VECTOR
49 OFF049
IFS1 IEC1 IPC12 IPC12
Yes
PORTG Input Change Interrupt
_CHANGE_NOTICE_G_VECTOR
50 OFF050
IFS1 IEC1 IPC12 IPC12
Yes
Parallel Host Port
_PMP_VECTOR
51 OFF051
IFS1 IEC1 IPC12 IPC12
Yes
Parallel Host Port Error
_PMP_ERROR_VECTOR
52 OFF052
IFS1 IEC1 IPC13
IPC13
Yes
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK General Purpose (GP) Family Features” for the list of available peripherals.
2: This interrupt source is not available on 64-pin devices.
3: This interrupt source is not available on 100-pin devices.
PIC32MK GP/MC Family
DS60001402H-page 125
TABLE 8-3:
2016-2021 Microchip Technology Inc.
TABLE 8-3:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
PIC32MK GP/MC Family
DS60001402H-page 126
SPI2 Fault
_SPI2_FAULT_VECTOR
53 OFF053
IFS1 IEC1 IPC13 IPC13
Yes
SPI2 Receive Done
_SPI2_RX_VECTOR
54 OFF054
IFS1 IEC1 IPC13 IPC13
Yes
SPI2 Transfer Done
_SPI2_TX_VECTOR
55 OFF055
IFS1 IEC1 IPC13 IPC13
Yes
UART2 Fault
_UART2_FAULT_VECTOR
56 OFF056
IFS1 IEC1 IPC14
IPC14
Yes
UART2 Receive Done
_UART2_RX_VECTOR
57 OFF057
IFS1 IEC1 IPC14 IPC14
Yes
UART2 Transfer Done
_UART2_TX_VECTOR
58 OFF058
IFS1 IEC1 IPC14 IPC14
Yes
Reserved
—
59
—
—
—
—
—
—
Reserved
—
60
—
—
—
—
—
—
Reserved
—
61
—
—
—
—
—
—
UART3 Fault
_UART3_FAULT_VECTOR
62 OFF062
IFS1 IEC1 IPC15 IPC15
Yes
UART3 Receive Done
_UART3_RX_VECTOR
63 OFF063
IFS1 IEC1 IPC15 IPC15
Yes
UART3 Transfer Done
_UART3_TX_VECTOR
64 OFF064
IFS2 IEC2 IPC16
IPC16
Yes
UART4 Fault
_UART4_FAULT_VECTOR
65 OFF065
IFS2 IEC2 IPC16 IPC16
Yes
UART4 Receive Done
_UART4_RX_VECTOR
66 OFF066
IFS2 IEC2 IPC16 IPC16
Yes
UART4 Transfer Done
_UART4_TX_VECTOR
67 OFF067
IFS2 IEC2 IPC16 IPC16
Yes
UART5 Fault
_UART5_FAULT_VECTOR
68 OFF068
IFS2 IEC2 IPC17
IPC17
Yes
UART5 Receive Done
_UART5_RX_VECTOR
69 OFF069
IFS2 IEC2 IPC17 IPC17
Yes
UART5 Transfer Done
_UART5_TX_VECTOR
70 OFF070
IFS2 IEC2 IPC17 IPC17
Yes
CTMU Interrupt
_CTMU_VECTOR
71 OFF071
IFS2 IEC2 IPC17 IPC17
Yes
DMA Channel 0
_DMA0_VECTOR
72 OFF072
IFS2 IEC2 IPC18
IPC18
Yes
DMA Channel 1
_DMA1_VECTOR
73 OFF073
IFS2 IEC2 IPC18 IPC18
Yes
DMA Channel 2
_DMA2_VECTOR
74 OFF074
IFS2 IEC2 IPC18 IPC18
Yes
DMA Channel 3
_DMA3_VECTOR
75 OFF075
IFS2 IEC2 IPC18 IPC18
Yes
Timer6
_TIMER_6_VECTOR
76 OFF076
IFS2 IEC2 IPC19
IPC19
Yes
Input Capture 6 Error
_INPUT_CAPTURE_6_ERROR_VECTOR
77 OFF077
IFS2 IEC2 IPC19 IPC19
Yes
Input Capture 6
_INPUT_CAPTURE_6_VECTOR
78 OFF078
IFS2 IEC2 IPC19 IPC19
Yes
Output Compare 6
_OUTPUT_COMPARE_6_VECTOR
79 OFF079
IFS2 IEC2 IPC19 IPC19
Yes
Timer7
_TIMER_7_VECTOR
80 OFF080
IFS2 IEC2 IPC20
IPC20
Yes
Input Capture 7 Error
_INPUT_CAPTURE_7_ERROR_VECTOR
81 OFF081
IFS2 IEC2 IPC20 IPC20
Yes
Input Capture 7
_INPUT_CAPTURE_7_VECTOR
82 OFF082
IFS2 IEC2 IPC20 IPC20
Yes
Output Compare 7
_OUTPUT_COMPARE_7_VECTOR
83 OFF083
IFS2 IEC2 IPC20 IPC20
Yes
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK General Purpose (GP) Family Features” for the list of available peripherals.
2: This interrupt source is not available on 64-pin devices.
3: This interrupt source is not available on 100-pin devices.
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
2016-2021 Microchip Technology Inc.
Timer8
_TIMER_8_VECTOR
84 OFF084
IFS2 IEC2 IPC21
IPC21
Yes
Input Capture 8 Error
_INPUT_CAPTURE_8_ERROR_VECTOR
85 OFF085
IFS2 IEC2 IPC21 IPC21
Yes
Input Capture 8
_INPUT_CAPTURE_8_VECTOR
86 OFF086
IFS2 IEC2 IPC21 IPC21
Yes
Output Compare 8
_OUTPUT_COMPARE_8_VECTOR
87 OFF087
IFS2 IEC2 IPC21 IPC21
Yes
Timer9
_TIMER_9_VECTOR
88 OFF088
IFS2 IEC2 IPC22
IPC22
Yes
Input Capture 9 Error
_INPUT_CAPTURE_9_ERROR_VECTOR
89 OFF089
IFS2 IEC2 IPC22 IPC22
Yes
Input Capture 9
_INPUT_CAPTURE_9_VECTOR
90 OFF090
IFS2 IEC2 IPC22 IPC22
Yes
Output Compare 9
_OUTPUT_COMPARE_9_VECTOR
91 OFF091
IFS2 IEC2 IPC22 IPC22
Yes
ADC Global Interrupt
_ADC_VECTOR
92 OFF092
IFS2 IEC2 IPC23
IPC23
Yes
Reserved
—
93
—
—
—
—
—
—
ADC Digital Comparator 1
_ADC_DC1_VECTOR
94 OFF094
IFS2 IEC2 IPC23 IPC23
Yes
ADC Digital Comparator 2
_ADC_DC2_VECTOR
95 OFF095
IFS2 IEC2 IPC23 IPC23
Yes
ADC Digital Filter 1
_ADC_DF1_VECTOR
96 OFF096
IFS3 IEC3 IPC24
IPC24
Yes
ADC Digital Filter 2
_ADC_DF2_VECTOR
97 OFF097
IFS3 IEC3 IPC24 IPC24
Yes
ADC Digital Filter 3
_ADC_DF3_VECTOR
98 OFF098
IFS3 IEC3 IPC24 IPC24
Yes
ADC Digital Filter 4
_ADC_DF4_VECTOR
99 OFF099
IFS3 IEC3 IPC24 IPC24
Yes
ADC Fault
_ADC_FAULT_VECTOR
100 OFF100
IFS3 IEC3 IPC25
IPC25
Yes
ADC End of Scan
_ADC_EOS_VECTOR
101 OFF101
IFS3 IEC3 IPC25 IPC25
Yes
ADC Ready
_ADC_ARDY_VECTOR
102 OFF102
IFS3 IEC3 IPC25 IPC25
Yes
ADC Update Ready After Suspend _ADC_URDY_VECTOR
103 OFF103
IFS3 IEC3 IPC25 IPC25
Yes
ADC First Class Channels DMA
_ADC_DMA_VECTOR
104 OFF104
IFS3 IEC3 IPC26
IPC26
No
ADC Early Group Interrupt
_ADC_EARLY_VECTOR
105 OFF105
IFS3 IEC3 IPC26 IPC26
Yes
ADC Data 0
_ADC_DATA0_VECTOR
106 OFF106
IFS3 IEC3 IPC26 IPC26
Yes
ADC Data 1
_ADC_DATA1_VECTOR
107 OFF107
IFS3 IEC3 IPC26 IPC26
Yes
ADC Data 2
_ADC_DATA2_VECTOR
108 OFF108
IFS3 IEC3 IPC26
IPC27
Yes
ADC Data 3
_ADC_DATA3_VECTOR
109 OFF109
IFS3 IEC3 IPC27 IPC27
Yes
ADC Data 4
_ADC_DATA4_VECTOR
110 OFF110
IFS3 IEC3 IPC27 IPC27
Yes
ADC Data 5
_ADC_DATA5_VECTOR
111 OFF111
IFS3 IEC3 IPC27 IPC27
Yes
ADC Data 6
_ADC_DATA6_VECTOR
112 OFF112
IFS3 IEC3 IPC28
IPC28
Yes
ADC Data 7
_ADC_DATA7_VECTOR
113 OFF113
IFS3 IEC3 IPC28 IPC28
Yes
ADC Data 8
_ADC_DATA8_VECTOR
114 OFF114
IFS3 IEC3 IPC28 IPC28
Yes
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK General Purpose (GP) Family Features” for the list of available peripherals.
2: This interrupt source is not available on 64-pin devices.
3: This interrupt source is not available on 100-pin devices.
PIC32MK GP/MC Family
DS60001402H-page 127
TABLE 8-3:
2016-2021 Microchip Technology Inc.
TABLE 8-3:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
PIC32MK GP/MC Family
DS60001402H-page 128
ADC Data 9
_ADC_DATA9_VECTOR
115 OFF115
IFS3 IEC3 IPC28 IPC28
Yes
ADC Data 10
_ADC_DATA10_VECTOR
116 OFF116
IFS3 IEC3 IPC29
IPC29
Yes
ADC Data 11
_ADC_DATA11_VECTOR
117 OFF117
IFS3 IEC3 IPC29 IPC29
Yes
ADC Data 12
_ADC_DATA12_VECTOR
118 OFF118
IFS3 IEC3 IPC29 IPC29
Yes
ADC Data 13
_ADC_DATA13_VECTOR
119 OFF119
IFS3 IEC3 IPC29 IPC29
Yes
ADC Data 14
_ADC_DATA14_VECTOR
120 OFF120
IFS3 IEC3 IPC30
IPC30
Yes
ADC Data 15
_ADC_DATA15_VECTOR
121 OFF121
IFS3 IEC3 IPC30 IPC30
Yes
ADC Data 16
_ADC_DATA16_VECTOR
122 OFF122
IFS3 IEC3 IPC30 IPC30
Yes
ADC Data 17
_ADC_DATA17_VECTOR
123 OFF123
IFS3 IEC3 IPC30 IPC30
Yes
ADC Data 18
_ADC_DATA18_VECTOR
124 OFF124
IFS3 IEC3 IPC31
IPC31
Yes
ADC Data 19
_ADC_DATA19_VECTOR
125 OFF125
IFS3 IEC3 IPC31 IPC31
Yes
ADC Data 20
_ADC_DATA20_VECTOR
126 OFF126
IFS3 IEC3 IPC31 IPC31
Yes
ADC Data 21
_ADC_DATA21_VECTOR
127 OFF127
IFS3 IEC3 IPC31 IPC31
Yes
ADC Data 22
_ADC_DATA22_VECTOR
128 OFF128
IFS4 IEC4 IPC32
IPC32
Yes
ADC Data 23
_ADC_DATA23_VECTOR
129 OFF129
IFS4 IEC4 IPC32 IPC32
Yes
ADC Data 24
_ADC_DATA24_VECTOR
130 OFF130
IFS4 IEC4 IPC32 IPC32
Yes
ADC Data 25
_ADC_DATA25_VECTOR
131 OFF131
IFS4 IEC4 IPC32 IPC32
Yes
ADC Data 26
_ADC_DATA26_VECTOR
132 OFF132
IFS4 IEC4 IPC33
IPC33
Yes
ADC Data 27
_ADC_DATA27_VECTOR
133 OFF133
IFS4 IEC4 IPC33 IPC33
Yes
Reserved
—
134
—
—
—
—
—
—
Reserved
—
135
—
—
—
—
—
—
Reserved
—
136
—
—
—
—
—
—
Reserved
—
137
—
—
—
—
—
—
Reserved
—
138
—
—
—
—
—
—
ADC Data 33
_ADC_DATA33_VECTOR
139 OFF139
IFS4 IEC4 IPC34 IPC34
Yes
ADC Data 34
_ADC_DATA34_VECTOR
140 OFF140
IFS4 IEC4 IPC35
IPC35
Yes
ADC Data 35
_ADC_DATA35_VECTOR
141 OFF141
IFS4 IEC4 IPC35 IPC35
Yes
ADC Data 36
_ADC_DATA36_VECTOR
142 OFF142
IFS4 IEC4 IPC35 IPC35
Yes
ADC Data 37
_ADC_DATA37_VECTOR
143 OFF143
IFS4 IEC4 IPC35 IPC35
Yes
ADC Data 38
_ADC_DATA38_VECTOR
144 OFF144
IFS4 IEC4 IPC36
IPC36
Yes
ADC Data 39
_ADC_DATA39_VECTOR
145 OFF145
IFS4 IEC4 IPC36 IPC36
Yes
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK General Purpose (GP) Family Features” for the list of available peripherals.
2: This interrupt source is not available on 64-pin devices.
3: This interrupt source is not available on 100-pin devices.
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
2016-2021 Microchip Technology Inc.
ADC Data 40
_ADC_DATA40_VECTOR
146 OFF146
IFS4 IEC4 IPC36 IPC36
Yes
ADC Data 41
_ADC_DATA41_VECTOR
147 OFF147
IFS4 IEC4 IPC36 IPC36
Yes
Reserved
—
148
—
—
—
—
—
—
Reserved
—
149
—
—
—
—
—
—
Reserved
—
150
—
—
—
—
—
—
ADC Data 45
_ADC_DATA45_VECTOR
151 OFF151
IFS4 IEC4 IPC37 IPC37
Yes
ADC Data 46
_ADC_DATA46_VECTOR
152 OFF152
IFS4 IEC4 IPC38
IPC38
Yes
ADC Data 47
_ADC_DATA47_VECTOR
153 OFF153
IFS4 IEC4 IPC38 IPC38
Yes
ADC Data 48
_ADC_DATA48_VECTOR
154 OFF154
IFS4 IEC4 IPC38 IPC38
Yes
ADC Data 49
_ADC_DATA49_VECTOR
155 OFF155
IFS4 IEC4 IPC38 IPC38
Yes
ADC Data 50
_ADC_DATA50_VECTOR
156 OFF156
IFS4 IEC4 IPC39
IPC39
Yes
ADC Data 51
_ADC_DATA51_VECTOR
157 OFF157
IFS4 IEC4 IPC39 IPC39
Yes
ADC Data 52
_ADC_DATA52_VECTOR
158 OFF158
IFS4 IEC4 IPC39 IPC39
Yes
ADC Data 53
_ADC_DATA53_VECTOR
159 OFF159
IFS4 IEC4 IPC39 IPC39
Yes
Comparator 3 Interrupt
_COMPARATOR_3_VECTOR
160 OFF160
IFS5 IEC5 IPC40
IPC40
Yes
Comparator 4 Interrupt
_COMPARATOR_4_VECTOR
161 OFF161
IFS5 IEC5 IPC40 IPC40
Yes
Comparator 5 Interrupt
_COMPARATOR_5_VECTOR
162 OFF162
IFS5 IEC5 IPC40 IPC40
Yes
Reserved
—
163
—
—
—
—
—
—
UART6 Fault
_UART6_FAULT_VECTOR
164 OFF164
IFS5 IEC5 IPC41
IPC41
Yes
UART6 Receive Done
_UART6_RX_VECTOR
165 OFF165
IFS5 IEC5 IPC41 IPC41
Yes
UART6 Transfer Done
_UART6_TX_VECTOR
166 OFF166
IFS5 IEC5 IPC41 IPC41
Yes
CAN1 Global Interrupt
_CAN1_VECTOR
167 OFF167
IFS5 IEC5 IPC41 IPC41
Yes
CAN2 Global Interrupt
_CAN2_VECTOR
168 OFF168
IFS5 IEC5 IPC42
IPC42
Yes
QEI1 Interrupt
_QEI1_VECTOR
169 OFF169
IFS5 IEC5 IPC42 IPC42
Yes
QEI2 Interrupt
_QEI2_VECTOR
170 OFF170
IFS5 IEC5 IPC42 IPC42
Yes
PWM Primary Event
_PWM_PRI_VECTOR
171 OFF171
IFS5 IEC5 IPC42 IPC42
Yes
PWM Sec Event
_PWM_SEC_VECTOR
172 OFF172
IFS5 IEC5 IPC43
IPC43
Yes
PWM1 Combined Interrupt (Period,
_PWM1_VECTOR
173 OFF173
IFS5 IEC5 IPC43 IPC43
Yes
Fault, Trigger, Current-Limit)
PWM2 Combined Interrupt (Period,
_PWM2_VECTOR
174 OFF174
IFS5 IEC5 IPC43 IPC43
Yes
Fault, Trigger, Current-Limit)
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK General Purpose (GP) Family Features” for the list of available peripherals.
2: This interrupt source is not available on 64-pin devices.
3: This interrupt source is not available on 100-pin devices.
PIC32MK GP/MC Family
DS60001402H-page 129
TABLE 8-3:
2016-2021 Microchip Technology Inc.
TABLE 8-3:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
PIC32MK GP/MC Family
DS60001402H-page 130
PWM3 Combined Interrupt (Period,
_PWM3_VECTOR
175 OFF175
IFS5 IEC5 IPC43 IPC43
Yes
Fault, Trigger, Current-Limit)
PWM4 Combined Interrupt (Period,
_PWM4_VECTOR
176 OFF176
IFS5 IEC5 IPC44
IPC44
Yes
Fault, Trigger, Current-Limit)
PWM5 Interrupt (Period, Fault,
_PWM5_VECTOR
177 OFF177
IFS5 IEC5 IPC44 IPC44
Yes
Trigger, Current-Limit)
PWM6 Interrupt (Period, Fault,
_PWM6_VECTOR
178 OFF178
IFS5 IEC5 IPC44 IPC44
Yes
Trigger, Current-Limit)
Reserved
—
179
—
—
—
—
—
—
Reserved
—
180
—
—
—
—
—
—
Reserved
—
181
—
—
—
—
—
—
DMA Channel 4
_DMA4_VECTOR
182 OFF182
IFS5 IEC5 IPC45 IPC45
Yes
DMA Channel 5
_DMA5_VECTOR
183 OFF183
IFS5 IEC5 IPC45 IPC45
Yes
DMA Channel 6
_DMA6_VECTOR
184 OFF184
IFS5 IEC5 IPC46
IPC46
Yes
DMA Channel 7
_DMA7_VECTOR
185 OFF185
IFS5 IEC5 IPC46 IPC46
Yes
Data EEPROM Global Interrupt
_DATA_EE_VECTOR
186 OFF186
IFS5 IEC5 IPC46 IPC46
Yes
CAN3 Global Interrupt
_CAN3_VECTOR
187 OFF187
IFS5 IEC5 IPC46 IPC46
Yes
CAN4 Global Interrupt
_CAN4_VECTOR
188 OFF188
IFS5 IEC5 IPC47
IPC47
Yes
QEI3 Interrupt
_QEI2_VECTOR
189 OFF189
IFS5 IEC5 IPC47 IPC47
Yes
QEI4 Interrupt
_QEI3_VECTOR
190 OFF190
IFS5 IEC5 IPC47 IPC47
Yes
QEI5 Interrupt
_QEI5_VECTOR
191 OFF191
IFS5 IEC5 IPC47 IPC47
Yes
QEI6 Interrupt
_QEI6_VECTOR
192 OFF192
IFS6 IEC6 IPC48
IPC48
Yes
Reserved
—
193
—
—
—
—
—
—
Reserved
—
194
—
—
—
—
—
—
Reserved
—
195
—
—
—
—
—
—
Reserved
—
196
—
—
—
—
—
—
Input Capture 10 Error
_INPUT_CAPTURE_10_ERROR_VECTOR 197 OFF197
IFS6 IEC6 IPC49 IPC49
Yes
Input Capture 10
_INPUT_CAPTURE_10_VECTOR
198 OFF198
IFS6 IE6
IPC49 IPC49
Yes
Output Compare 10
_OUTPUT_COMPARE_10_VECTOR
199 OFF199
IFS6 IEC6 IPC49 IPC49
Yes
Input Capture 11 Error
_INPUT_CAPTURE_11_ERROR_VECTOR 200 OFF200
IFS6 IEC6 IPC50
IPC50
Yes
Input Capture 11
_INPUT_CAPTURE_11_VECTOR
201 OFF201
IFS6 IEC6 IPC50 IPC50
Yes
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK General Purpose (GP) Family Features” for the list of available peripherals.
2: This interrupt source is not available on 64-pin devices.
3: This interrupt source is not available on 100-pin devices.
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
2016-2021 Microchip Technology Inc.
Output Compare 11
_OUTPUT_COMPARE_11_VECTOR
202 OFF202
IFS6 IEC6 IPC50 IPC50
Yes
Input Capture 12 Error
_INPUT_CAPTURE_12_ERROR_VECTOR 203 OFF203
IFS6 IEC6 IPC50 IPC50
Yes
Input Capture 12
_INPUT_CAPTURE_12_VECTOR
204 OFF204
IFS6 IEC6 IPC51
IPC51
Yes
Output Compare 12
_OUTPUT_COMPARE_12_VECTOR
205 OFF205
IFS6 IEC6 IPC51 IPC51
Yes
Input Capture 13 Error
_INPUT_CAPTURE_13_ERROR_VECTOR 206 OFF206
IFS6 IEC6 IPC51 IPC51
Yes
Input Capture 13
_INPUT_CAPTURE_13_VECTOR
207 OFF207
IFS6 IEC6 IPC51 IPC51
Yes
Output Compare 13
_OUTPUT_COMPARE_13_VECTOR
208 OFF208
IFS6 IEC6 IPC52
IPC52
Yes
Input Capture 14 Error
_INPUT_CAPTURE_14_ERROR_VECTOR 209 OFF209
IFS6 IEC6 IPC52 IPC52
Yes
Input Capture 14
_INPUT_CAPTURE_14_VECTOR
210 OFF210
IFS6 IEC6 IPC52 IPC52
Yes
Output Compare 14
_OUTPUT_COMPARE_14_VECTOR
211 OFF211
IFS6 IEC6 IPC52 IPC52
Yes
Input Capture 15 Error
_INPUT_CAPTURE_15_ERROR_VECTOR 212 OFF212
IFS6 IEC6 IPC53
IPC53
Yes
Input Capture 15
_INPUT_CAPTURE_15_VECTOR
213 OFF213
IFS6 IEC6 IPC53 IPC53
Yes
Output Compare 15
_OUTPUT_COMPARE_15_VECTOR
214 OFF214
IFS6 IEC6 IPC53 IPC53
Yes
Input Capture 16 Error
_INPUT_CAPTURE_16_ERROR_VECTOR 215 OFF215
IFS6 IEC6 IPC53 IPC53
Yes
Input Capture 16
_INPUT_CAPTURE_16_VECTOR
216 OFF216
IFS6 IEC6 IPC54
IPC54
Yes
Output Compare 16
_OUTPUT_COMPARE_16_VECTOR
217 OFF217
IFS6 IEC6 IPC54 IPC54
Yes
SPI3 Fault
_SPI3_FAULT_VECTOR
218 OFF218
IFS6 IEC6 IPC54 IPC54
Yes
SPI3 Receive Done
_SPI3_RX_VECTOR
219 OFF219
IFS6 IEC6 IPC54 IPC54
Yes
SPI3 Transfer Done
_SPI3_TX_VECTOR
220 OFF220
IFS6 IEC6 IPC55
IPC55
Yes
SPI4 Fault
_SPI4_FAULT_VECTOR
221 OFF221
IFS6 IEC6 IPC55 IPC55
Yes
SPI4 Receive Done
_SPI4_RX_VECTOR
222 OFF222
IFS6 IEC6 IPC55 IPC55
Yes
SPI4 Transfer Done
_SPI4_TX_VECTOR
223 OFF223
IFS6 IEC6 IPC55 IPC55
Yes
SPI5 Fault
_SPI5_FAULT_VECTOR
224 OFF224
IFS7 IEC7 IPC56
IPC56
Yes
SPI5 Receive Done
_SPI5_RX_VECTOR
225 OFF225
IFS7 IEC7 IPC56 IPC56
Yes
SPI5 Transfer Done
_SPI5_TX_VECTOR
226 OFF226
IFS7 IEC7 IPC56 IPC56
Yes
SPI6 Fault
_SPI6_FAULT_VECTOR
227 OFF227
IFS7 IEC7 IPC56 IPC56
Yes
SPI6 Receive Done
_SPI6_RX_VECTOR
228 OFF228
IFS7 IEC7 IPC57
IPC57
Yes
SPI6 Transfer Done
_SPI6_TX_VECTOR
229 OFF229
IFS7 IEC7 IPC57 IPC57
Yes
System Bus Protection Violation
_SYSTEM_BUS_PROTECTION_VECTOR 230 OFF230
IFS7 IEC7 IPC57 IPC57
Yes
Reserved
—
231
—
—
—
—
—
—
Reserved
—
232
—
—
—
—
—
—
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK General Purpose (GP) Family Features” for the list of available peripherals.
2: This interrupt source is not available on 64-pin devices.
3: This interrupt source is not available on 100-pin devices.
PIC32MK GP/MC Family
DS60001402H-page 131
TABLE 8-3:
2016-2021 Microchip Technology Inc.
TABLE 8-3:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
XC32 Vector Name
IRQ
#
Vector #
Reserved
Reserved
Reserved
Reserved
Reserved
PWM7 Interrupt (Period, Fault,
Trigger, Current-Limit)
PWM8 Interrupt (Period, Fault,
Trigger, Current-Limit)
PWM9 Interrupt (Period, Fault,
Trigger, Current-Limit)
PWM10 Interrupt (Period, Fault,
Trigger, Current-Limit)
PWM11 Interrupt (Period, Fault,
Trigger, Current-Limit)
PWM12 Interrupt (Period, Fault,
Trigger, Current-Limit)
USB2 Combined Interrupt(2)
ADC Digital Comparator 3
ADC Digital Comparator 4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Core Performance Counter Interrupt
Fast Debug Channel Interrupt
—
—
—
—
—
233
234
235
236
237
—
—
—
—
—
Note 1:
2:
3:
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
_PWM7_VECTOR
238 OFF238
IFS7 IEC7 IPC59 IPC59
Yes
_PWM8_VECTOR
239 OFF239
IFS7 IEC7 IPC59 IPC59
Yes
_PWM9_VECTOR
240 OFF240
IFS7 IEC7 IPC60
IPC60
Yes
_PWM10_VECTOR
241 OFF241
IFS7 IEC7 IPC60 IPC60
Yes
_PWM11_VECTOR
242 OFF242
IFS7 IEC7 IPC60 IPC60
Yes
_PWM12_VECTOR
243 OFF243
IFS7 IEC7 IPC60 IPC60
Yes
_USB_2_VECTOR
244 OFF244
IFS7 IEC7 IPC61
IPC61
Yes
_ADC_DC3_VECTOR
245 OFF245
IFS7 IEC7 IPC61 IPC61
Yes
_ADC_DC4_VECTOR
246 OFF246
IFS7 IEC7 IPC61 IPC61
Yes
—
247
—
—
—
—
—
—
—
248
—
—
—
—
—
—
—
249
—
—
—
—
—
—
—
250
—
—
—
—
—
—
—
251
—
—
—
—
—
—
—
252
—
—
—
—
—
—
—
253
—
—
—
—
—
—
_CORE_PERF_COUNT_VECTOR
254 OFF254
IFS7 IEC7 IPC63 IPC63
—
_CORE_FAST_DEBUG_CHAN_VECTOR
255 OFF255
IFS7 IEC7 IPC63 IPC63
—
Lowest Natural Order Priority
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MK General Purpose (GP) Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
PIC32MK GP/MC Family
DS60001402H-page 132
Interrupt Source(1)
Interrupt Control Registers
0000 INTCON
0010
PRISS
0020 INTSTAT
Bits
31/15
30/14
29/13
28/12
—
—
—
MVEC
31:16
15:0
27/11
26/10
25/9
24/8
SWNMIKEY
—
TPC
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
—
—
—
SS0
0000
—
—
—
—
0000
31:16
PRI7SS
PRI6SS
PRI5SS
15:0
PRI3SS
PRI2SS
PRI1SS
31:16
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
SRIPL
31:16
20/4
19/3
18/2
17/1
16/0
All Resets
INTERRUPT REGISTER MAP
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
TABLE 8-4:
—
PRI4SS
—
0000
INT0EP 0000
0000
SIRQ
0000
0000
0030
IPTMR
0040
IFS0(7) 31:16
FCEIF
RTCCIF
—
—
OC5IF
IC5IF
IC5EIF
T5IF
INT4IF
OC4IF
IC4IF
IC4EIF
T4IF
INT3IF
OC3IF
IC3IF
0000
15:0
IC3EIF
T3IF
INT2IF
OC2IF
IC2IF
IC2EIF
T2IF
INT1IF
OC1IF
IC1IF
IC1EIF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
U3EIF
—
—
—
U2TXIF
U2RXIF
U2EIF
SPI2TXIF
SPI2RXIF
SPI2EIF
PMPEIF
PMPIF
CNGIF
CNFIF
CNEIF
0000
CNCIF
CNBIF
CNAIF
—
—
—
U1TXIF
U1RXIF
U1EIF
SPI1TXIF
SPI1RXIF
SPI1EIF
USB1IF
CMP2IF
-
AD1IF
OC9IF
IC9IF
IC9EIF
T9IF
OC8IF
IC8IF
IC8EIF
T8IF
OC7IF
IC7IF
IC7EIF
T7IF
0000
IC6EIF
T6IF
DMA3IF
DMA2IF
DMA1IF
DMA0IF
CTMUIF
U5TXIF
U5RXIF
U5EIF
U4TXIF
U4RXIF
U4EIF
U3TXIF
0000
AD1D16IF
AD1D15IF
AD1D14IF
AD1D13IF
AD1D12IF
AD1D11IF
AD1D8IF
AD1D7IF
0050
IFS1(7) 31:16 U3RXIF
15:0
0060
IPTMR
15:0
CNDIF
IFS2(7) 31:16 AD1DC2IF AD1DC1IF
15:0
OC6IF
IC6IF
0000
CMP1IF 0000
0070
IFS3(7) 31:16 AD1D21IF AD1D20IF AD1D19IF AD1D18IF AD1D17IF
AD1D1IF
AD1D0IF
AD1G1IF AD1FCBTIF AD1RSIF
AD1ARIF
AD1EOSIF
AD1F1IF
AD1DF4IF AD1DF3IF AD1DF2IF AD1DF1IF 0000
0080
IFS4(7) 31:16 AD1D53IF AD1D52IF AD1D51IF AD1D50IF AD1D49IF
AD1D48IF
AD1D47IF
AD1D46IF
AD1D45IF
—
—
—
AD1D41IF AD1D40IF AD1D39IF AD1D38IF 0000
—
—
—
—
—
AD1D27IF
DATAEEIF
DMA7IF
DMA6IF
DMA4IF
—
15:0 AD1D5IF
AD1D4IF
AD1D3IF
AD1D2IF
15:0 AD1D37IF AD1D36IF AD1D35IF AD1D34IF AD1D33IF
0090
IFS5(7) 31:16
QEI3IF
CAN4IF(3) CAN3IF(3)
DMA5IF
—
—
PWM6IF
PWM5IF
PWM4IF 0000
PWM2IF
PWM1IF
QEI2IF
QEI1IF
CAN2IF
U6TXIF
U6RXIF
U6EIF
—
CMP5IF
CMP4IF
CMP3IF 0000
SPI4EIF
SPI3TXIF
SPI3RXIF
SPI3EIF
OC16IF
IC16IF
IC16EIF
OC15IF
IC15IF
IC15EIF
OC14IF
C14IF
IC14EIF
OC13IF 0000
—
—
—
—
2016-2021 Microchip Technology Inc.
IFS7(7) 31:16
00C0
IEC0
PWM3IF
PWM
PEVTIF
AD1D26IF AD1D25IF AD1D24IF AD1D23IF AD1D22IF 0000
IFS6(7) 31:16 SPI4TXIF SPI4RXIF
15:0
00B0
QEI4IF
AD1D6IF 0000
PWM
SEVTIF
15:0
00A0
QEI5IF
AD1D10IF AD1D9IF
(3)
CAN1IF
(3)
IC13IF
IC13EIF
OC12IF
IC12IF
IC12EIF
OC11IF
IC11IF
IC11EIF
OC10IF
IC10IF
IC10EIF
—
CPCIF
—
—
—
—
—
—
—
AD1DC4IF
AD1DC3IF
USB2IF(2) PWM12IF
PWM11IF
PWM10IF
PWM9IF 0000
QEI6IF
SPI5EIF 0000
0000
15:0
PWM8IF
PWM7IF
—
—
—
—
—
—
—
SBIF
SPI6TXIF
SPI6RXIF
SPI6EIF
SPI5TXIF
SPI5RXIF
31:16
FCEIE
RTCCIE
-
-
OC5IE
IC5IE
IC5EIE
T5IE
INT4IE
OC4IE
IC4IE
IC4EIE
T4IE
INT3IE
OC3IE
IC3IE
0000
15:0
IC3EIE
T3IE
INT2IE
OC2IE
IC2IE
IC2EIE
T2IE
INT1IE
OC1IE
IC1IE
IC1EIE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
This bit is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 22 is not available on 64-pin devices.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition has occurred. The IFSx bits are persistent, they must be cleared if they are set by
user software after an IFSx user bit interrogation.
1:
2:
3:
4:
5:
6:
7:
PIC32MK GP/MC Family
DS60001402H-page 133
8.3
IEC1
00E0
IEC2
IEC3
0100
IEC4
0110
IEC5
31/15
IEC6
0130
IEC7
0140
IPC0
IPC1
0160
IPC2
0170
IPC3
0180
IPC4
0190
IPC5
01A0
IPC6
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
U3EIE
—
—
—
U2TXIE
U2RXIE
U2EIE
SPI2TXIE
SPI2RXIE
SPI2EIE
PMPEIE
PMPIE
CNGIE
CNFIE
CNCIE
CNBIE
CNAIE
—
—
—
U1TXIE
U1RXIE
U1EIE
SPI1TXIE
SPI1RXIE
SPI1EIE
USB1IE
CMP2IE
-
AD1IE
OC9IE
IC9IE
IC9EIE
T9IE
OC8IE
IC8IE
IC8EIE
T8IE
OC7IE
IC7IE
IC7EIE
IC6EIE
T6IE
DMA3IE
DMA2IE
DMA1IE
DMA0IE
CTMUIE
U5TXIE
U5RXIE
U5EIE
U4TXIE
U4RXIE
U4EIE
31:16 AD1D21IE AD1D20IE AD1D19IE AD1D18IE AD1D17IE
AD1D16IE
AD1D15IE
AD1D14IE
15:0 AD1D05IE AD1D04IE AD1D03IE AD1D02IE AD1D01IE
AD1D00IE
AD1G1IE AD1FCBTIE AD1RSIE
31:16 AD1D53IE AD1D52IE AD1D51IE AD1D50IE AD1D49IE
AD1D48IE
AD1D47IE
AD1D46IE
15:0 AD1D37IE AD1D36IE AD1D35IE AD1D34IE AD1D33IE
—
—
—
DATAEEIE
DMA7IE
DMA6IE
CNDIE
31:16 AD1DC2IE AD1DC1IE
31:16
OC6IE
QEI5IE
IC6IE
QEI4IE
QEI3IE
CAN4IE(3) CAN3IE(3)
PWM
PEVTIE
AD1D13IE AD1D12IE
16/0
CNEIE
0000
CMP1IE 0000
T7IE
0000
U3TXIE 0000
AD1D11IE
AD1D10IE AD1D09IE AD1D08IE AD1D07IE AD1D06IE 0000
AD1ARIE
AD1EOSIE
AD1F1IE AD1DF4IE AD1DF3IE AD1DF2IE AD1DF1IE 0000
AD1D45IE
—
—
—
—
AD1D27IE
DMA4IE
—
DMA5IE
—
AD1D41IE AD1D40IE AD1D39IE AD1D38IE 0000
AD1D26IE AD1D25IE AD1D24IE AD1D23IE AD1D22IE 0000
—
—
PWM6IE
PWM5IE
PWM4IE 0000
PWM2IE
PWM1IE
PWM
SEVTIE
QEI2IE
QEI1IE
CAN2IE
U6TXIE
U6RXIE
U6EIE
—
CMP5IE
CMP4IE
CMP3IE 0000
31:16 SPI4TXIE SPI4RXIE
SPI4EIE
SPI3TXIE
SPI3RXIE
SPI3EIE
OC16IE
IC16IE
IC16EIE
OC15IE
IC15IE
IC15EIE
OC14IE
C14IE
IC14EIE
OC13IE 0000
15:0
IC13IE
IC13EIE
OC12IE
IC12IE
IC12EIE
OC11IE
IC11IE
IC11EIE
OC10IE
IC10IE
IC10EIE
—
—
—
—
31:16
—
CPCIE
—
—
—
—
—
—
—
—
—
—
—
—
(3)
CAN1IE
(3)
AD1DC4IE AD1DC3IE
QEI6IE
0000
USB2IE(2) PWM12IE PWM11IE
PWM10IE
PWM9IE 0000
SPI6RXIE
SPI5RXIE
SPI5EIE 0000
15:0
—
—
—
—
SBIE
SPI6TXIE
31:16
—
—
—
INT0IP
INT0IS
—
—
—
CS1IP
SPI6EIE
SPI5TXIE
CS1IS
0000
15:0
—
—
—
CS0IP
CS0IS
—
—
—
CTIP
CTIS
0000
31:16
—
—
—
OC1IP
OC1IS
—
—
—
IC1IP
IC1IS
0000
15:0
—
—
—
IC1EIP
IC1EIS
—
—
—
T1IP
T1IS
0000
31:16
—
—
—
IC2IP
IC2IS
—
—
—
IC2EIP
IC2EIS
0000
15:0
—
—
—
T2IP
T2IS
—
—
—
INT1IP
INT1IS
0000
31:16
—
—
—
IC3EIP
IC3EIS
—
—
—
T3IP
T3IS
0000
15:0
—
—
—
INT2IP
INT2IS
—
—
—
OC2IP
OC2IS
0000
31:16
—
—
—
T4IP
T4IS
—
—
—
INT3IP
INT3IS
0000
15:0
—
—
—
OC3IP
OC3IS
—
—
—
IC3IP
IC3IS
0000
31:16
—
—
—
INT4IP
INT4IS
—
—
—
OC4IP
OC4IS
0000
15:0
—
—
—
IC4IP
IC4IS
—
—
—
IC4EIP
IC4EIS
0000
31:16
—
—
—
OC5IP
OC5IS
—
—
—
IC5IP
IC5IS
0000
15:0
—
—
—
IC5EIP
IC5EIS
—
—
—
T5IP
T5IS
0000
DS60001402H-page 134
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
This bit is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 22 is not available on 64-pin devices.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition has occurred. The IFSx bits are persistent, they must be cleared if they are set by
user software after an IFSx user bit interrogation.
1:
2:
3:
4:
5:
6:
7:
PIC32MK GP/MC Family
0150
29/13
15:0
15:0 PWM3IE
0120
30/14
31:16 U3RXIE
15:0
00F0
Bits
All Resets
Register
Name(1)
00D0
INTERRUPT REGISTER MAP (CONTINUED)
Bit Range
Virtual Address
(BF81_#)
2016-2021 Microchip Technology Inc.
TABLE 8-4:
01C0
IPC8
01D0
IPC9
01E0
IPC10
01F0
IPC11
0200
IPC12
0210
IPC13
0220
IPC14
0230
IPC15
0240
IPC16
0250
IPC17
0260
IPC18
2016-2021 Microchip Technology Inc.
0270
IPC19
0280
IPC20
Bits
31/15
30/14
29/13
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
31:16
—
15:0
28/12
27/11
26/10
25/9
—
—
FCEIP
24/8
22/6
21/5
—
—
—
—
—
—
—
SPI1EIP
SPI1EIS
—
—
—
—
CMP2IP
CMP2IS
—
—
—
—
U1RXIP
U1RXIS
—
—
—
—
SPI1TXIP
SPI1TXIS
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
—
—
—
CNDIP
15:0
—
—
—
31:16
—
—
15:0
—
31:16
20/4
19/3
18/2
16/0
0000
—
—
0000
USB1IP
USB1IS
0000
—
CMP1IP
CMP1IS
0000
—
—
U1EIP
U1EIS
0000
—
—
—
SPI1RXIP
SPI1RXIS
0000
—
—
—
—
—
—
—
—
U1TXIP
U1TXIS
0000
CNDIS
—
—
—
CNCIP
CNCIS
0000
CNBIP
CNBIS
—
—
—
CNAIP
CNAIS
0000
—
PMPIP
PMPIS
—
—
—
CNGIP
CNGIS
0000
—
—
CNFIP
CNFIS
—
—
—
CNEIP
CNEIS
0000
—
—
—
SPI2TXIP
SPI2TXIS
—
—
—
SPI2RXIP
SPI2RXIS
0000
15:0
—
—
—
SPI2EIP
SPI2EIS
—
—
—
PMPEIP
PMPEIS
0000
31:16
—
—
—
—
—
—
—
U2TXIP
U2TXIS
0000
15:0
—
—
—
U2RXIP
U2RXIS
—
—
—
U2EIP
U2EIS
0000
31:16
—
—
—
U3RXIP
U3RXIS
—
—
—
U3EIP
U3EIS
0000
15:0
—
—
—
—
—
—
—
31:16
—
—
—
U4TXIP
U4TXIS
—
—
—
15:0
—
—
—
U4EIP
U4EIS
—
—
31:16
—
—
—
CTMUIP
CTMUIS
—
15:0
—
—
—
U5RXIP
U5RXIS
31:16
—
—
—
DMA3IP
15:0
—
—
—
31:16
—
—
15:0
—
31:16
15:0
—
—
—
—
—
—
—
—
—
RTCCIP
17/1
RTCCIS
—
FCEIS
23/7
All Resets
Register
Name(1)
IPC7
Bit Range
Virtual Address
(BF81_#)
01B0
INTERRUPT REGISTER MAP (CONTINUED)
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
0000
U4RXIP
U4RXIS
0000
—
U3TXIP
U3TXIS
0000
—
—
U5TXIP
U5TXIS
0000
—
—
—
U5EIP
U5EIS
0000
DMA3IS
—
—
—
DMA2IP
DMA2IS
0000
DMA1IP
DMA1IS
—
—
—
DMA0IP
DMA0IS
0000
—
OC6IP
OC6IS
—
—
—
IC6IP
IC6IS
0000
—
—
IC6EIP
IC6EIS
—
—
—
T6IP
T6IS
0000
—
—
—
OC7IP
OC7IS
—
—
—
IC7IP
IC7IS
0000
—
—
—
IC7EIP
IC7EIS
—
—
—
T7IP
T7IS
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
This bit is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 22 is not available on 64-pin devices.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition has occurred. The IFSx bits are persistent, they must be cleared if they are set by
user software after an IFSx user bit interrogation.
1:
2:
3:
4:
5:
6:
7:
PIC32MK GP/MC Family
DS60001402H-page 135
TABLE 8-4:
IPC21
02A0
IPC22
02B0
IPC23
02C0
IPC24
02D0
IPC25
02E0
IPC26
02F0
IPC27
0300
IPC28
IPC29
0320
IPC30
0330
IPC31
0340
IPC32
0350
IPC33
0360
IPC34
31/15
30/14
29/13
28/12
23/7
22/6
21/5
31:16
—
—
—
OC8IP
15:0
—
—
—
IC8EIP
OC8IS
—
—
—
IC8IP
IC8IS
0000
IC8EIS
—
—
—
T8IP
T8IS
31:16
—
—
—
OC9IP
0000
OC9IS
—
—
—
IC9IP
IC9IS
15:0
—
—
—
0000
IC9EIP
IC9EIS
—
—
—
T9IP
T9IS
31:16
—
—
—
0000
AD1DC2IP
AD1DC2IS
—
—
—
AD1DC1IP
AD1DC1IS
15:0
—
—
—
0000
—
—
—
—
AD1IP
AD1IS
31:16
—
—
—
0000
AD1DF4IP
AD1DF4IS
—
—
—
AD1DF3IP
AD1DF3IS
15:0
—
—
0000
—
AD1DF2IP
AD1DF2IS
—
—
—
AD1DF1IP
AD1DF1IS
31:16
—
0000
—
—
AD1RSIP
AD1RSIS
—
—
—
AD1ARIP
AD1ARIS
15:0
0000
—
—
—
AD1EOSIP
AD1EOSIS
—
—
—
AD1F1IP
AD1F1IS
0000
31:16
—
—
—
AD1D01IP
AD1D01IS
—
—
—
AD1D00IP
AD1D00IS
0000
15:0
—
—
—
AD1G1IP
AD1G1IS
—
—
—
AD1FCBTIP
AD1FCBTIS
0000
31:16
—
—
—
AD1D05IP
AD1D05IS
—
—
—
AD1D04IP
AD1D04IS
0000
15:0
—
—
—
AD1D03IP
AD1D03IS
—
—
—
AD1D02IP
AD1D02IS
0000
31:16
—
—
—
AD1D09IP
AD1D09IS
—
—
—
AD1D08IP
AD1D08IS
0000
15:0
—
—
—
AD1D07IP
AD1D07IS
—
—
—
AD1D06IP
AD1D06IS
0000
31:16
—
—
—
AD1D13IP
AD1D13IS
—
—
—
AD1D12IP
AD1D12IS
0000
15:0
—
—
—
AD1D11IP
AD1D11IS
—
—
—
AD1D10IP
AD1D10IS
0000
31:16
—
—
—
AD1D17IP
AD1D17IS
—
—
—
AD1D16IP
AD1D16IS
0000
15:0
—
—
—
AD1D15IP
AD1D15IS
—
—
—
AD1D14IP
AD1D14IS
0000
31:16
—
—
—
AD1D21IP
AD1D21IS
—
—
—
AD1D20IP
AD1D20IS
0000
15:0
—
—
—
AD1D19IP
AD1D19IS
—
—
—
AD1D18IP
AD1D18IS
0000
31:16
—
—
—
AD1D25IP
AD1D25IS
—
—
—
AD1D24IP
AD1D24IS
0000
15:0
—
—
—
AD1D23IP
AD1D23IS
—
—
—
AD1D22IP
AD1D22IS
0000
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
AD1D27IP
AD1D27IS
—
—
—
31:16
—
—
—
AD1D33IP
AD1D33IS
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
27/11
—
—
—
26/10
—
—
—
25/9
—
24/8
—
20/4
—
19/3
—
18/2
—
AD1D26IP
17/1
—
16/0
—
0000
AD1D26IS
0000
DS60001402H-page 136
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
This bit is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 22 is not available on 64-pin devices.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition has occurred. The IFSx bits are persistent, they must be cleared if they are set by
user software after an IFSx user bit interrogation.
1:
2:
3:
4:
5:
6:
7:
PIC32MK GP/MC Family
0310
Bits
All Resets
Register
Name(1)
0290
INTERRUPT REGISTER MAP (CONTINUED)
Bit Range
Virtual Address
(BF81_#)
2016-2021 Microchip Technology Inc.
TABLE 8-4:
0380
IPC36
0390
IPC37
03A0
IPC38
03B0
IPC39
03C0
IPC40
03D0
IPC41
03E0
IPC42
03F0
IPC43
0400
IPC44
0410
IPC45
0420
IPC46
2016-2021 Microchip Technology Inc.
0430
IPC47
0440
IPC48
Bits
31/15
30/14
29/13
28/12
23/7
22/6
21/5
31:16
—
—
—
AD1D37IP
15:0
—
—
—
AD1D35IP
AD1D37IS
—
—
—
AD1D36IP
AD1D36IS
0000
AD1D35IS
—
—
—
AD1D34IP
AD1D34IS
31:16
—
—
—
0000
AD1D41IP
AD1D41IS
—
—
—
AD1D40IP
AD1D40IS
15:0
—
—
0000
—
AD1D39IP
AD1D39IS
—
—
—
AD1D38IP
AD1D38IS
31:16
—
0000
—
—
AD1D45IP
AD1D45IS
—
—
—
—
—
—
—
—
15:0
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
AD1D49IP
AD1D49IS
—
—
—
AD1D48IP
AD1D48IS
0000
15:0
—
—
—
AD1D47IP
AD1D47IS
—
—
—
AD1D46IP
AD1D46IS
0000
31:16
—
—
—
AD1D53IP
AD1D53IS
—
—
—
AD1D52IP
AD1D52IS
0000
15:0
—
—
—
AD1D51IP
AD1D51IS
—
—
—
AD1D50IP
AD1D50IS
0000
31:16
—
—
—
—
—
—
—
CMP5IP
CMP5IS
0000
15:0
—
—
—
CMP4IP
CMP4IS
—
—
—
CMP3IP
CMP3IS
0000
31:16
—
—
—
CAN1IP(3)
CAN1IS(3)
—
—
—
U6TXIP
U6TXIS
0000
15:0
—
—
—
U6RXIP
U6RXIS
—
—
—
U6EIP
U6EIS
0000
31:16
—
—
—
PWMPEVTIP
PWMSEVTIP
—
—
—
QEI2IP
QEI2SIP
0000
15:0
—
—
—
QEI1IP
QEI1SIP
—
—
—
CAN2IP(3)
CAN2IS(3)
0000
31:16
—
—
—
PWM3IP
PWM3SIP
—
—
—
PWM2IP
PWM2SIP
0000
15:0
—
—
—
PWM1IP
PWM1SIP
—
—
—
PWMSEVTIP
31:16
—
—
—
—
—
—
—
—
PWM6IP
PWM6SIP
0000
15:0
—
—
—
PWM5IP
PWM5SIP
—
—
—
PWM4IP
PWM4SIP
0000
31:16
—
—
—
DMA5IP
DMA5IS
—
—
—
DMA4IP
DMA4IS
0000
15:0
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
CAN3IP(3)
CAN3IS(3)
—
—
—
DATAEEIP
DATAEEIS
0000
15:0
—
—
—
DMA7IP
DMA7IS
—
—
—
DMA6IP
DMA6IS
0000
31:16
—
—
—
QEI5IP
QEI5SIP
—
—
—
QEI4IP
QEI4SIP
0000
15:0
—
—
—
QEI3IP
QEI3SIP
—
—
—
CAN4IP(3)
CAN4IS(3)
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
27/11
—
—
—
—
26/10
—
—
—
—
25/9
24/8
—
20/4
—
—
19/3
—
—
QEI6IP
18/2
17/1
16/0
All Resets
Register
Name(1)
IPC35
Bit Range
Virtual Address
(BF81_#)
0370
INTERRUPT REGISTER MAP (CONTINUED)
PWMSEVTSIP 0000
—
—
—
—
—
0000
QEI6SIP
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and
INV Registers” for more information.
This bit is not available on 64-pin devices.
This bit is not available on devices without a CAN module.
This bit is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 22 is not available on 64-pin devices.
The IFSx bits, as with all interrupt flag status register bits, are set as long as the peripheral is enabled and an interrupt condition event occurs. Interrupts do not have to be enabled for the IFSx bits to be set. If the user
application does not want to use an interrupt, it can poll the corresponding peripheral IFSx bit to see whether an interrupt condition has occurred. The IFSx bits are persistent, they must be cleared if they are set by
user software after an IFSx user bit interrogation.
1:
2:
3:
4:
5:
6:
7:
PIC32MK GP/MC Family
DS60001402H-page 137
TABLE 8-4:
IPC49
0460
IPC50
0470
IPC51
0480
IPC52
0490
IPC53
04A0
IPC54
04B0
IPC55
04C0
IPC56
IPC57
04F0
IPC59
0500
IPC60
0510
IPC61
0530
IPC63
0540 OFF000
31/15
30/14
29/13
23/7
22/6
21/5
31:16
—
—
—
OC10IP
15:0
—
—
—
IC10EIP
OC10IS
—
—
—
IC10EIS
—
—
—
31:16
—
—
—
IC12EIP
IC12EIS
—
—
—
OC11IP
OC11IS
15:0
—
—
—
0000
IC11IP
IC11IS
—
—
—
IC11EIP
IC11EIS
31:16
—
—
0000
—
IC13IP
IC13IS
—
—
—
IC13EIP
IC13EIS
15:0
—
0000
—
—
OC12IP
OC12IS
—
—
—
IC12IP
IC12IS
31:16
0000
—
—
—
OC14IP
OC14IS
—
—
—
C14IP
C14IS
0000
15:0
—
—
—
IC14EIP
IC14EIS
—
—
—
OC13IP
OC13IS
0000
31:16
—
—
—
IC16EIP
IC16EIS
—
—
—
OC15IP
OC15IS
0000
15:0
—
—
—
IC15IP
IC15IS
—
—
—
IC15EIP
IC15EIS
0000
31:16
—
—
—
SPI3RXIP
SPI3RXIS
—
—
—
SPI3EIP
SPI3EIS
0000
15:0
—
—
—
OC16IP
OC16IS
—
—
—
IC16IP SPI / UART
REFCLK3 > ADC > and
Comparator
TIMER1
RTCC
SOSCBOOST
2016-2021 Microchip Technology Inc.
SOSCGAIN
LPRC Oscillator
32.768 kHz Typical
USB Clock (48 MHz)
TIMER1
RTCC
WDT
VBAT DOMAIN(3,4)
Note
1:
2:
3:
4:
5:
6:
Refer to 2.0 “Guidelines for Getting Started with 32-bit MCUs” for recommended external crystal component values and restrictions.
The internal POSC feedback resistor, RF, is typically in the range of 2 to 10 M.
The maximum PBCLK6 clock rate to the peripherals in the VBAT power domain is 30 MHz. This is not the power-up default and must be configured by the user before attempting any access to
those peripherals.
The shaded region indicates peripherals contained and powered from VBAT on devices that support battery operation from the VBAT pin.
Refer to Table 36-16 in 36.0 “Electrical Characteristics” for PBCLK6 frequency limitations.
CLKO on OSC2 pin, if enabled in configuration word, available in EC & FRC mode is PBCLK1 / 2.
PIC32MK GP/MC Family
DS60001402H-page 165
FIGURE 9-1:
PIC32MK GP/MC Family
TABLE 9-1:
SYSTEM AND PERIPHERAL CLOCK DISTRIBUTION
Peripheral
ADC1-ADC7
X
CAN1-CAN4
X
CFG PMD
X
CLKO(6)
X
Comparator 1-5
CPU
REFCLKO4
REFCLKO3
REFCLKO2
REFCLKO1
PBCLK7
X
X
X
X
X
X
X
X
CRU
X
X
CTMU
X
CDAC1
X
CDAC2-CDAC3
DATAEE
X
X
X
DMA
X
DMT
X
DSCTRL(5)
X
X
EVIC
X
Flash
X
X
X
Input Capture 10-16
X
Input Capture 1-9
X
ICD
X
Output Compare 10-16
X
Output Compare 1-9
X
Op amp 1-3, 5
X
PMP
X
PORTA-PORTG
X
PPS
X
RTCC
X
X
X
X
SPI3-SPI6
SSX Control
X
X
X
Timer1
X
X
X
Timer2-Timer9
X
UART1-UART2
X
X
UART3-UART6
X
X
USB1-USB2
X
X
X
1:
2:
3:
4:
5:
6:
X
X
X
WDT
X
X
SPI1-SPI2
Note
PBCLK6
PBCLK5
PBCLK4
PBCLK3
PBCLK2
PBCLK1(1)
UPLL
SPLL
SYSCLK
POSC
SOSC
LPRC
FRC
Clock Source
X
X
X
X
X
X
X
PBCLK1 is used by system modules and cannot be turned off.
SYSCLK/PBCLK5 is used to fetch data from/to the Flash Controller, while the FRC clock is used for programming.
Special Function Register (SFR) access only.
Timer1 only.
DSCTRL is the Deep Sleep Control Block.
PBCLK1 divided by 2 is available on CLKO function pin on oscillator in EC or FRC mode.
DS60001402H-page 166
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
9.1
Fail-Safe Clock Monitor (FSCM)
The PIC32MK GP/MC oscillator system includes a Failsafe Clock Monitor (FSCM). The FSCM monitors the
SYSCLK for continuous operation. If it detects that the
SYSCLK has failed, it switches the SYSCLK over to the
FRC oscillator and triggers a NMI. When the NMI is
executed, software can attempt to restart the main
oscillator or shut down the system.
In Sleep mode, both the SYSCLK and the FSCM halt,
which prevents FSCM detection.
2016-2021 Microchip Technology Inc.
DS60001402H-page 167
Oscillator Control Registers
1200
OSCCON
1210
OSCTUN
1220
1230
OSCILLATOR CONFIGURATION REGISTER MAP
SPLLCON
UPLLCON
1280 REFO1CON
1290 REFO1TRIM
12A0 REFO2CON
12C0 REFO3CON
12D0 REFO3TRIM
12E0 REFO4CON
12F0 REFO4TRIM
1300
PB1DIV
1310
PB2DIV
DS60001402H-page 168
1320
PB3DIV
1330
PB4DIV
31/15
30/14
29/13
28/12
27/11
31:16
—
—
15:0
—
—
—
—
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
—
—
—
—
—
COSC
26/10
25/9
24/8
23/7
22/6
21/5
FRCDIV
DRMEN
—
SLP2SPD
—
—
—
—
NOSC
CLKLOCK
—
—
SLPEN
CF
UFRCEN
SOSCEN
—
—
—
—
—
—
—
—
—
—
—
PLLODIV
—
15:0
—
—
—
—
—
PLLIDIV
PLLICLK
31:16
—
—
UPOSCEN
—
—
PLLODIV
—
15:0
—
—
—
—
—
PLLIDIV
—
31:16
—
15:0
ON
—
SIDL
OE
RSLP
—
DIVSWEN
ACTIVE
31:16
—
15:0
ON
—
—
—
—
—
—
—
—
SIDL
OE
31:16
—
RSLP
—
DIVSWEN
ACTIVE
—
ROTRIM
15:0
—
31:16
—
15:0
ON
—
—
—
—
—
—
—
—
—
SIDL
OE
RSLP
—
DIVSWEN
ACTIVE
—
ROTRIM
—
31:16
—
15:0
ON
17/1
16/0
—
—
TUN
—
—
—
—
—
—
—
—
—
—
0xxx
—
PLLRANGE
0xxx
PLLMULT
0xxx
—
—
—
—
PLLRANGE
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
0x0x
0000
ROSEL
0000
0000
ROSEL
0000
0000
ROSEL
0000
RODIV
—
SIDL
OE
31:16
RSLP
—
DIVSWEN
ACTIVE
—
ROTRIM
0000
0020
PLLMULT
—
0xx0
OSWEN xxxx
RODIV
31:16
15:0
18/2
RODIV
0000
ROSEL
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
Refer to Table 36-16 in 36.0 “Electrical Characteristics” for PBCLK6 frequency limitations.
The PB7DIV register is read-only.
1:
2:
3:
—
ROTRIM
—
19/3
RODIV
31:16
15:0
20/4
PBDIV
—
—
—
—
8801
PBDIV
—
—
—
—
8801
PBDIV
—
—
—
—
PBDIV
0000
0000
8801
0000
8801
PIC32MK GP/MC Family
12B0 REFO2TRIM
Bit Range
Bits
All Resets(1)
Register
Name
TABLE 9-2:
Virtual Address
(BF80_#)
2016-2021 Microchip Technology Inc.
9.2
Register
Name
PB5DIV
Bit Range
Bits
1350
PB6DIV(2)
1360
(3)
1380
1390
PB7DIV
SLEWCON
CLKSTAT
31/15
30/14
29/13
28/12
31:16
—
—
—
15:0
ON
—
—
31:16
—
—
15:0
ON
31:16
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
—
—
—
—
—
—
—
—
—
—
PBDIVRDY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PBDIVRDY
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
UPEN
DNEN
BUSY
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
POSCRDY
—
SLWDIV
—
UPLLRDY SPLLRDY
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
Refer to Table 36-16 in 36.0 “Electrical Characteristics” for PBCLK6 frequency limitations.
The PB7DIV register is read-only.
1:
2:
3:
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
All Resets(1)
Virtual Address
(BF80_#)
1340
OSCILLATOR CONFIGURATION REGISTER MAP (CONTINUED)
PBDIV
—
—
—
—
8801
PBDIV
—
—
—
—
LPRCRDY SOSCRDY
0000
8801
PBDIV
—
0000
0000
8800
SYSDIV
0000
FRCRDY 0000
PIC32MK GP/MC Family
DS60001402H-page 169
TABLE 9-2:
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 9-1:
Bit
Range
31:24
23:16
15:8
7:0
OSCCON: OSCILLATOR CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
Bit
26/18/10/2
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
FRCDIV
R/W-0
U-0
R/W-y
U-0
U-0
U-0
U-0
DRMEN
—
SLP2SPD
—
—
—
—
—
U-0
R-0
R-0
R-0
U-0
R/W-y
R/W-y
R/W-y
—
COSC
—
U-0
NOSC
R/W-0
U-0
U-0
R/W-0
R/W-0, HS
R/W-0
R/W-y
R/W-y
CLKLOCK
—
—
SLPEN
CF
UFRCEN
SOSCEN
OSWEN(1)
Legend:
R = Readable bit
-n = Value at POR
y = Value set from Configuration bits on POR
HS = Hardware Set
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-24 FRCDIV: Internal Fast RC (FRC) Oscillator Clock Divider bits
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2
000 = FRC divided by 1 (default setting)
bit 23
DRMEN: Dream Mode Enable bit
1 = Dream mode is enabled
0 = Dream mode is disabled
bit 22
Unimplemented: Read as ‘0’
bit 21
SLP2SPD: Sleep Two-speed Start-up Control bit
1 = Use FRC as SYSCLK until the selected clock is ready
0 = Use the selected clock directly
bit 20-15 Unimplemented: Read as ‘0’
bit 14-12 COSC: Current Oscillator Selection bits
111 = Reserved
110 = Reserved
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = USB PLL (UPLL) input clock and divider are set by UPLLCON
010 = Primary Oscillator (POSC) (HS or EC)
001 = System PLL (SPLL) input clock and divider set by SPLLCON
000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (FRCDIV) supports FRN divided
by N, where ‘N’ is 1, 2, 4, 8, 16, 32, 64, and 256
bit 11
Unimplemented: Read as ‘0’
Note 1:
Note:
The reset value for this bit depends on the setting of the IESO bit (DEVCFG1). When IESO = 1, the
reset value is ‘1’. When IESO = 0, the reset value is ‘0’.
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL”
(DS60001250) in the “PIC32 Family Reference Manual” for details.
DS60001402H-page 170
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 9-1:
bit 10-8
bit 7
bit 6-5
bit 4
bit 3
OSCCON: OSCILLATOR CONTROL REGISTER
NOSC: New Oscillator Selection bits
111 = Reserved
110 = Reserved
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = USB PLL (UPLL) input clock and divider are set by UPLLCON
010 = Primary Oscillator (POSC) (HS or EC)
001 = System PLL (SPLL) input clock and divider set by SPLLCON
000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (FRCDIV) supports FRN divided
by N, where ‘N’ is 1, 2, 4, 8, 16, 32, 64, and 256
On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1).
CLKLOCK: Clock Selection Lock Enable bit
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified
Unimplemented: Read as ‘0’
SLPEN: Sleep Mode Enable bit
1 = Device will enter Sleep mode when a WAIT instruction is executed
0 = Device will enter Idle mode when a WAIT instruction is executed
CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
Note:
bit 2
bit 1
bit 0
Note 1:
Note:
On a clock fail event if enabled by the FCKSM bits (DEVCFG1) = ‘0b11, this bit
and the RNMICON bit will be set. The user software must clear both the bits inside the CF
NMI before attempting to exit the ISR. Software or hardware settings of the CF bit
(OSCCON) will cause a CF NMI event and an automatic clock switch to the FRC provided
the FCKSM = ‘0b11. Unlike the CF bit (OSCCON), software or hardware settings of
the CF bit (RNMICON) will cause a CF NMI event but will not cause a clock switch to the
FRC. After a Clock Fail event, a successful user software clock switch if implemented, hardware
will automatically clear the CF bit (RNMICON), but not the CF bit (OSCCON). The CF
bit (OSCCON) must be cleared by software using the OSCCON register unlock procedure.
UFRCEN: USB FRC Sleep Clock Enable bit
1 = FRC is the USB input clock for wake from Sleep mode
0 = USB input clock is determined by the UPOSCEN bit (UPLLCON)
SOSCEN: Secondary Oscillator (SOSC) Enable bit
1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator
OSWEN: Oscillator Switch Enable bit(1)
1 = Initiate an oscillator switch to selection specified by NOSC bits
0 = Oscillator switch is complete
The reset value for this bit depends on the setting of the IESO bit (DEVCFG1). When IESO = 1, the
reset value is ‘1’. When IESO = 0, the reset value is ‘0’.
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL”
(DS60001250) in the “PIC32 Family Reference Manual” for details.
2016-2021 Microchip Technology Inc.
DS60001402H-page 171
PIC32MK GP/MC Family
REGISTER 9-2:
Bit
Range
31:24
23:16
15:8
7:0
OSCTUN: FRC TUNING REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
TUN(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-6
Unimplemented: Read as ‘0’
bit 5-0
TUN: FRC Oscillator Tuning bits(1)
111111 = +1.453%
•
•
•
100000 = 0.000% (Nominal Center Frequency, default)
•
•
•
000000 =-1.500%
x = Bit is unknown
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither
characterized nor tested.
Note:
Writes to this register require an unlock sequence. Refer to the Section 42. “Oscillators with Enhanced
PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
DS60001402H-page 172
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 9-3:
Bit
Range
31:24
23:16
15:8
7:0
SPLLCON: SYSTEM PLL CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
U-0
U-0
U-0
U-0
U-0
R/W-y
—
—
—
—
—
U-0
R/W-y
R/W-y
R/W-y
—
U-0
R/W-y
Bit
25/17/9/1
Bit
24/16/8/0
R/W-y
R/W-y
PLLODIV
R/W-y
R/W-y
R/W-y
R/W-y
R/W-y
PLLMULT
U-0
U-0
U-0
U-0
R/W-y
—
PLLIDIV
R/W-y
U-0
U-0
U-0
U-0
PLLICLK
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
R/W-y
R/W-y
R/W-y
PLLRANGE
y = Value set from Configuration bits on POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-24 PLLODIV: System PLL Output Clock Divider bits
111 = Reserved
110 = Reserved
101 = PLL Divide by 32
100 = PLL Divide by 16
011 = PLL Divide by 8
010 = PLL Divide by 4
001 = PLL Divide by 2
000 = Reserved
The default setting is specified by the FPLLODIV Configuration bits in the DEVCFG2 register. Refer
to Register 33-5 in 33.0 “Special Features” for information.
bit 23
Unimplemented: Read as ‘0’
bit 22-16 PLLMULT: System PLL Multiplier bits
1111111 = Multiply by 128
1111110 = Multiply by 127
1111101 = Multiply by 126
1111100 = Multiply by 125
•
•
•
0000000 = Multiply by 1
The default setting is specified by the FPLLMULT Configuration bits in the DEVCFG2 register. Refer
to Register 33-5 in 33.0 “Special Features” for information.
bit 15-11 Unimplemented: Read as ‘0’
Note 1:
2:
3:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced
PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
Writes to this register are not allowed if the SPLL is selected as a clock source (COSC = 001).
While the PLL is active, and if updating the PLL bits in the OSCCON register at run-time, the user application must remain within the following limits at all times for all nodes in the PLL clock tree. Therefore, the
order in which the PLL values may be modified, (i.e., PLLODIV, PLLMULT, PLLODIV) becomes important.
Failure to maintain PLL nodes within min/max ranges may result in unstable PLL and system behavior.
• Output and input to PLLIDIV block (i.e., FPLLI) 5 MHz to 64 MHz (min/max at all times)
• VCO output, (i.e., FVCO) 350 MHz to 700 MHz (min/max at all times)
• Output of PLLODIV, (i.e., FPLL) 10 MHz to 120 MHz (min/max at all times)
2016-2021 Microchip Technology Inc.
DS60001402H-page 173
PIC32MK GP/MC Family
REGISTER 9-3:
bit 10-8
SPLLCON: SYSTEM PLL CONTROL REGISTER
PLLIDIV: System PLL Input Clock Divider bits
111 = Divide by 8
110 = Divide by 7
101 = Divide by 6
100 = Divide by 5
011 = Divide by 4
010 = Divide by 3
001 = Divide by 2
000 = Divide by 1
The default setting is specified by the FPLLIDIV Configuration bits in the DEVCFG2 register. Refer to
Register 33-5 in 33.0 “Special Features” for information. If the PLLICLK is set for FRC, this setting is
ignored by the PLL and the divider is set to Divide-by-1.
PLLICLK: System PLL Input Clock Source bit
1 = FRC is selected as the input to the System PLL
0 = POSC is selected as the input to the System PLL
The POR default is specified by the FPLLICLK Configuration bit in the DEVCFG2 register. Refer to
Register 33-5 in 33.0 “Special Features” for information.
Unimplemented: Read as ‘0’
PLLRANGE: System PLL Frequency Range Selection bits
111 = Reserved
110 = 54-64 MHz
101 = 34-64 MHz
100 = 21-42 MHz
011 = 13-26 MHz
010 = 8-16 MHz
001 = 5-10 MHz
000 = Bypass
Use the highest filter range that covers the input freq to the VCO multiplier block that corresponds to the
PLLIDIV output freq to minimize PLL system jitter (see Figure 9-1). For example, Crystal = 20 MHz,
PLLIDIV = 0b1; therefore, the filter input frequency is equal to 10 MHz and UPLLRANGE =
‘0b010. The default setting is specified by the FPLLRNG Configuration bits in the DEVCFG2 register.
Refer to Register 33-5 in 33.0 “Special Features” for information.
bit 7
bit 6-3
bit 2-0
Note 1:
2:
3:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced
PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
Writes to this register are not allowed if the SPLL is selected as a clock source (COSC = 001).
While the PLL is active, and if updating the PLL bits in the OSCCON register at run-time, the user application must remain within the following limits at all times for all nodes in the PLL clock tree. Therefore, the
order in which the PLL values may be modified, (i.e., PLLODIV, PLLMULT, PLLODIV) becomes important.
Failure to maintain PLL nodes within min/max ranges may result in unstable PLL and system behavior.
• Output and input to PLLIDIV block (i.e., FPLLI) 5 MHz to 64 MHz (min/max at all times)
• VCO output, (i.e., FVCO) 350 MHz to 700 MHz (min/max at all times)
• Output of PLLODIV, (i.e., FPLL) 10 MHz to 120 MHz (min/max at all times)
DS60001402H-page 174
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 9-4:
Bit
Range
31:24
23:16
15:8
7:0
UPLLCON: USB PLL CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
U-0
—
U-0
R/W-0
U-0
U-0
R/W-0
—
UPOSCEN
—
—
U-0
R/W-0
R/W-0
R/W-0
—
U-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
PLLODIV
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PLLMULT
U-0
U-0
U-0
U-0
R/W-0
—
PLLIDIV
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
R/W-0
PLLRANGE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29
UPOSCEN: Output Enable bit
1 = USB input clock is POSC
0 = USB input clock is UPLL
bit 28-27 Unimplemented: Read as ‘0’
bit 26-24 PLLODIV: System PLL Output Clock Divider bits
111 = Reserved
110 = Reserved
101 = PLL Divide by 32
100 = PLL Divide by 16
011 = PLL Divide by 8
010 = PLL Divide by 4
001 = PLL Divide by 2
000 = Reserved
The default setting is specified by the FPLLODIV Configuration bits in the DEVCFG2 register. Refer
to Register 33-5 in 33.0 “Special Features” for information.
Unimplemented: Read as ‘0’
bit 23
Note 1:
2:
3:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced
PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
Writes to this register are not allowed if the UPLL is selected as a clock source (COSC = 011).
While the PLL is active, and if updating the PLL bits in the OSCCON register at run-time, the user
application must remain within the following limits at all times for all nodes in the PLL clock tree. Therefore,
the order in which the PLL values may be modified, (i.e., PLLODIV, PLLMULT, PLLODIV) becomes
important. Failure to maintain PLL nodes within min/max ranges may result in unstable PLL and system
behavior.
• Output and input to PLLIDIV block (i.e., FPLLI) 5 MHz to 64 MHz (minimum/maximum at all times)
• VCO output, (i.e., FVCO) 350 MHz to 700 MHz (minimum/maximum at all times)
• Output of PLLODIV, (i.e., FPLL) 10 MHz to 120 MHz (minimum/maximum at all times)
2016-2021 Microchip Technology Inc.
DS60001402H-page 175
PIC32MK GP/MC Family
REGISTER 9-4:
UPLLCON: USB PLL CONTROL REGISTER
bit 22-16 PLLMULT: System PLL Multiplier Output Clock Divider bits
1111111 = Multiply by 128
1111110 = Multiply by 127
1111101 = Multiply by 126
•
•
•
0000010 = Multiply by 3
0000001 = Multiply by 2
0000000 = Multiply by 1
The default setting is specified by the FPLLMULT Configuration bits in the DEVCFG2 register. Refer
to Register 33-5 in 33.0 “Special Features” for information.
bit 15-11 Unimplemented: Read as ‘0’
bit 10-8 PLLIDIV: System PLL Input Clock Divider bits
111 = Divide by 8
110 = Divide by 7
101 = Divide by 6
100 = Divide by 5
011 = Divide by 4
010 = Divide by 3
001 = Divide by 2
000 = Divide by 1
The default setting is specified by the FPLLIDIV Configuration bits in the DEVCFG2 register. Refer to
Register 33-5 in 33.0 “Special Features” for information. If the PLLICLK is set for FRC, this setting is
ignored by the PLL and the divider is set to Divide-by-1.
Unimplemented: Read as ‘0’
PLLRANGE: System PLL Frequency Range Selection bits
111 = Reserved
110 = 54-90 MHz
101 = 34-68 MHz
100 = 21-42 MHz
011 = 13-26 MHz
010 = 8-16 MHz
001 = 5-10 MHz
000 = Bypass
Use the highest filter range that covers the input freq to the VCO multiplier block that corresponds to the
PLLIDIV output freq to minimize PLL system jitter (see Figure 9-1). For example, Crystal = 20 MHz,
PLLIDIV = 0b1; therefore, the filter input frequency is equal to 10 MHz and UPLLRANGE =
0b010. The default setting is specified by the FPLLRNG Configuration bits in the DEVCFG2 register.
Refer to Register 33-5 in 33.0 “Special Features” for information.
bit 7-3
bit 2-0
Note 1:
2:
3:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced
PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
Writes to this register are not allowed if the UPLL is selected as a clock source (COSC = 011).
While the PLL is active, and if updating the PLL bits in the OSCCON register at run-time, the user
application must remain within the following limits at all times for all nodes in the PLL clock tree. Therefore,
the order in which the PLL values may be modified, (i.e., PLLODIV, PLLMULT, PLLODIV) becomes
important. Failure to maintain PLL nodes within min/max ranges may result in unstable PLL and system
behavior.
• Output and input to PLLIDIV block (i.e., FPLLI) 5 MHz to 64 MHz (minimum/maximum at all times)
• VCO output, (i.e., FVCO) 350 MHz to 700 MHz (minimum/maximum at all times)
• Output of PLLODIV, (i.e., FPLL) 10 MHz to 120 MHz (minimum/maximum at all times)
DS60001402H-page 176
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 9-5:
Bit
Range
31:24
23:16
15:8
7:0
REFOxCON: REFERENCE OSCILLATOR CONTROL REGISTER (‘x’ = 1-4)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RODIV
R/W-0
R/W-0
R/W-0
R/W-0
RODIV
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0, HC
R-0, HS, HC
—
DIVSWEN
ACTIVE(1)
R/W-0
R/W-0
R/W-0
—
SIDL
OE
RSLP(2)
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
ON
(1)
ROSEL
(3)
Legend:
HC = Hardware Cleared
HS = Hardware Set
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
Unimplemented: Read as ‘0’
bit 30-16 RODIV Reference Clock Divider bits
The value selects the reference clock divider bits (see Figure 9-1 for details). A value of ‘0’ selects no divider.
bit 15
ON: Output Enable bit(1)
1 = Reference Oscillator Module enabled
0 = Reference Oscillator Module disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Peripheral Stop in Idle Mode bit
1 = Discontinue module operation when the device enters Idle mode
0 = Continue module operation in Idle mode
bit 12
OE: Reference Clock Output Enable bit
1 = Reference clock is driven out on REFCLKOx pin
0 = Reference clock is not driven out on REFCLKOx pin
bit 11
RSLP: Reference Oscillator Module Run in Sleep bit(2)
1 = Reference Oscillator Module output continues to run in Sleep
0 = Reference Oscillator Module output is disabled in Sleep
bit 10
Unimplemented: Read as ‘0’
bit 9
DIVSWEN: Divider Switch Enable bit
1 = Divider switch is in progress
0 = Divider switch is complete
bit 8
ACTIVE: Reference Clock Request Status bit(1)
1 = Reference clock request is active
0 = Reference clock request is not active
bit 7-4
Unimplemented: Read as ‘0’
Note 1:
2:
3:
Do not write to this register when the ON bit is not equal to the ACTIVE bit.
This bit is ignored when the ROSEL bits = 0000 or 0001.
The ROSEL bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result.
2016-2021 Microchip Technology Inc.
DS60001402H-page 177
PIC32MK GP/MC Family
REGISTER 9-5:
REFOxCON: REFERENCE OSCILLATOR CONTROL REGISTER (‘x’ = 1-4)
bit 3-0
ROSEL: Reference Clock Source Select bits(3)
1111 = Reserved
•
•
•
1001 = Reserved
1000 = REFCLKI
0111 = SPLL
0110 = UPLL
0101 = SOSC
0100 = LPRC
0011 = FRC
0010 = POSC
0001 = PBCLK1
0000 = SYSCLK
Note 1:
2:
3:
Do not write to this register when the ON bit is not equal to the ACTIVE bit.
This bit is ignored when the ROSEL bits = 0000 or 0001.
The ROSEL bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result.
DS60001402H-page 178
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 9-6:
Bit
Range
31:24
23:16
15:8
7:0
REFOxTRIM: REFERENCE OSCILLATOR TRIM REGISTER (‘x’ = 1-4)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
ROTRIM
R/W-0
R-0
U-0
U-0
U-0
ROTRIM
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-23 ROTRIM: Reference Oscillator Trim bits
111111111 = 511/512 divisor added to RODIV value
111111110 = 510/512 divisor added to RODIV value
•
•
•
100000000 = 256/512 divisor added to RODIV value
•
•
•
000000010 = 2/512 divisor added to RODIV value
000000001 = 1/512 divisor added to RODIV value
000000000 = 0 divisor added to RODIV value
bit 22-0
Note 1:
2:
3:
4:
Unimplemented: Read as ‘0’
While the ON bit (REFOxCON) is ‘1’, writes to this register do not take effect until the DIVSWEN bit is
also set to ‘1’.
Do not write to this register when the ON bit (REFOxCON) is not equal to the ACTIVE bit
(REFOxCON).
Specified values in this register do not take effect if RODIV (REFOxCON) = 0.
REFCLKOx Frequency = ((Selected Source Clock / 2) * (N + (M / 512)))
where, Selected source clock = ROSEL, N = RODIV, and M = ROTRIM.
If the value of REFCLKOx Frequency is not a whole integer value, the output clock will have jitter as it will
cause the REFCLKOx circuit to clock cycle steal to produce an average frequency equivalent to the user
application’s desired frequency. The amount of jitter, (i.e., clock cycle steals), become less as the
fractional remainder value becomes closer to a whole number and is greatest at any value plus 0.5.
2016-2021 Microchip Technology Inc.
DS60001402H-page 179
PIC32MK GP/MC Family
REGISTER 9-7:
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
(1)
U-0
U-0
U-0
R-1
U-0
U-0
U-0
—
—
—
PBDIVRDY
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1(2)
ON
7:0
PBxDIV: PERIPHERAL BUS ‘x’ CLOCK DIVISOR CONTROL REGISTER (‘x’ = 1-7)
—
PBDIV
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Peripheral Bus ‘x’ Output Clock Enable bit(1)
1 = Output clock is enabled
0 = Output clock is disabled
bit 14-12 Unimplemented: Read as ‘0’
bit 11
PBDIVRDY: Peripheral Bus ‘x’ Clock Divisor Ready bit
1 = Clock divisor logic is not switching divisors and the PBxDIV bits may be written
0 = Clock divisor logic is currently switching values and the PBxDIV bits cannot be written
bit 10-7
Unimplemented: Read as ‘0’
bit 6-0
PBDIV: Peripheral Bus ‘x’ Clock Divisor Control bits
1111111 = PBCLKx is SYSCLK divided by 128
1111110 = PBCLKx is SYSCLK divided by 127
•
•
•
0000011 = PBCLKx is SYSCLK divided by 4 (default value for x = 6)
0000010 = PBCLKx is SYSCLK divided by 3
0000001 = PBCLKx is SYSCLK divided by 2 (default value for x < 6)
0000000 = PBCLKx is SYSCLK divided by 1 (default value for x = 7)
Note 1: The clock for Peripheral Bus 1 and Peripheral Bus 7 cannot be turned off. Therefore, the ON bit in the
PB1DIV register and the PB7DIV register cannot be written as a ‘0’.
2: The default value for CPU clock PB7DIV Lsb = 0, where PB7CLK = SYSCLK (PB7DIV is read-only).
Note:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL”
(DS60001250) in the “PIC32 Family Reference Manual” for details.
DS60001402H-page 180
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 9-8:
Bit
Range
31:24
23:16
15:8
7:0
SLEWCON: OSCILLATOR SLEW CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
(1)
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
U-0
U-0
U-0
U-0
U-0
SYSDIV
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R-0, HS, HC
—
—
—
—
—
UPEN
DNEN
BUSY
SLWDIV
Legend:
HC = Hardware Cleared HS = Hardware Set
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-20 Unimplemented: Read as ‘0’
bit 19-16 SYSDIV: System Clock Divide Control bits(1)
1111 = SYSCLK is divided by 16
1110 = SYSCLK is divided by 15
•
•
•
0010 = SYSCLK is divided by 3
0001 = SYSCLK is divided by 2
0000 = SYSCLK is not divided
bit 15-11 Unimplemented: Read as ‘0’
bit 10-8
SLWDIV: Slew Divisor Steps Control bits
These bits control the maximum division steps used when slewing during a frequency change.
111 = Steps are divide by 128, 64, 32, 16, 8, 4, 2, and then no divisor
110 = Steps are divide by 64, 32, 16, 8, 4, 2, and then no divisor
101 = Steps are divide by 32, 16, 8, 4, 2, and then no divisor
100 = Steps are divide by 16, 8, 4, 2, and then no divisor
011 = Steps are divide by 8, 4, 2, and then no divisor
010 = Steps are divide by 4, 2, and then no divisor
001 = Steps are divide by 2, and then no divisor
000 = No divisor is used during slewing
The steps apply in reverse order (i.e., 2, 4, 8, etc.) during a downward frequency change.
bit 7-3
Unimplemented: Read as ‘0’
bit 2
UPEN: Upward Slew Enable bit
1 = Slewing enabled for switching to a higher frequency
0 = Slewing disabled for switching to a higher frequency
bit 1
DNEN: Downward Slew Enable bit
1 = Slewing enabled for switching to a lower frequency
0 = Slewing disabled for switching to a lower frequency
bit 0
BUSY: Clock Switching Slewing Active Status bit
1 = Clock frequency is being actively slewed to the new frequency
0 = Clock switch has reached its final value
Note 1:
The SYSDIV bit settings are ignored if both UPEN and DNEN = 0, and SYSCLK will be divided by 1.
2016-2021 Microchip Technology Inc.
DS60001402H-page 181
PIC32MK GP/MC Family
REGISTER 9-9:
Bit
Range
31:24
23:16
15:8
7:0
CLKSTAT: OSCILLATOR CLOCK STATUS REGISTER
Bit
31/23/15/7
Bit
Bit
30/22/14/6 29/21/13/5
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
UPLLRDY
R-0
U-0
R-0
R-0
U-0
R-0
U-0
R-0
SPLLRDY
—
—
POSCRDY
—
FRCRDY
LPRCRDY SOSCRDY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-9
Unimplemented: Read as ‘0’
bit 8
UPLLRDY: USB PLL (UPLL) Ready Status bit
1 = UPLL is ready
0 = UPLL is not ready
bit 7
SPLLRDY: System PLL (SPLL) Ready Status bit
1 = SPLL is ready
0 = SPLL is not ready
bit 5
LPRCRDY: Low-Power RC (LPRC) Oscillator Ready Status bit
1 = LPRC is stable and ready
0 = LPRC is disabled or not operating
bit 4
SOSCRDY: Secondary Oscillator (SOSC) Ready Status bit
1 = SOSC is stable and ready
0 = SOSC is disabled or not operating
bit 3
Unimplemented: Read as ‘0’
bit 2
POSCRDY: Primary Oscillator (POSC) Ready Status bit
1 = POSC is stable and ready
0 = POSC is disabled or not operating
bit 1
Unimplemented: Read as ‘0’
bit 0
FRCRDY: Fast RC (FRC) Oscillator Ready Status bit
1 = FRC is stable and ready
0 = FRC is disabled for not operating
DS60001402H-page 182
x = Bit is unknown
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
NOTES:
2016-2021 Microchip Technology Inc.
DS60001402H-page 183
PIC32MK GP/MC Family
10.0
PREFETCH MODULE
Note:
This data sheet summarizes the features
of the PIC32MK GP/MC family of devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 4. “Prefetch Cache Module”
(DS60001119), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The Prefetch module is a performance enhancing
module that is included in the PIC32MK GP/MC family
of devices. When running at high-clock rates, Wait
states must be inserted into Program Flash Memory
(PFM) read transactions to meet the access time of the
PFM. Wait states can be hidden to the core by
prefetching and storing instructions in a temporary
holding area that the CPU can access quickly. Although
the data path to the CPU is 32 bits wide, the data path
to the PFM is 128 bits wide. This wide data path
provides the same bandwidth to the CPU as a 32-bit
path running at four times the frequency.
FIGURE 10-1:
The Prefetch module holds a subset of PFM in
temporary holding spaces known as lines. Each line
contains a tag and data field. Normally, the lines hold a
copy of what is currently in memory to make
instructions or data available to the CPU without Flash
Wait states.
10.1
•
•
•
•
•
•
Prefetch Cache Features
36x16 byte fully-associative lines
16 lines for CPU instructions
Four lines for CPU data
Four lines for peripheral data
16-byte parallel memory fetch
Configurable predictive prefetch
A simplified block diagram of the Prefetch module is
shown in Figure 10-1.
PREFETCH MODULE BLOCK DIAGRAM
SYSCLK
CPU
Prefetch Buffer
Data
CPU
Tag
Bus Control
Line Control
Program Flash Memory (PFM)
DS60001402H-page 184
2016-2021 Microchip Technology Inc.
Prefetch Control Registers
PREFETCH REGISTER MAP
0800 CHECON
0820 CHEHIT
0830 CHEMIS
31/15
30/14
29/13
28/12
27/11
31:16
—
—
15:0
—
—
—
—
—
—
CHEPERFEN
—
26/10
25/9
PERCHEEN DCHEEN
—
—
24/8
23/7
ICHEEN
—
PFMAWSEN
—
22/6
21/5
20/4
PERCHEINV DCHEINV ICHEINV
—
PREFEN
19/3
—
—
18/2
17/1
16/0
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF80_#)
TABLE 10-1:
PERCHECOH DCHECOH ICHECOH 0700
PFMWS
0107
31:16
CHEHIT
0000
15:0
CHEHIT
0000
31:16
CHEMIS
0000
15:0
CHEMIS
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section13.2 “CLR, SET, and INV Registers” for
more information.
PIC32MK GP/MC Family
DS60001402H-page 185
10.2
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 10-1:
Bit
Range
31:24
23:16
15:8
7:0
CHECON: CACHE MODULE CONTROL REGISTER
Bit
Bit
31/23/15/7 30/22/14/6
U-0
U-0
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
Bit
26/18/10/2
R/W-1
R/W-1
R/W-1
DCHEEN
ICHEEN
R/W-0
R/W-0
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
PER
DCHEINV(1) ICHEINV(1)
CHEINV(1)
Bit
24/16/8/0
U-0
PERCHEEN
—
Bit
25/17/9/1
—
PER
DCHECOH(2) ICHECOH(2)
CHECOH(2)
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
R/W-1
—
—
—
CHE
PERFEN
—
—
—
PFM
AWSEN
U-0
U-0
R/W-0
R/W-0
U-0
R/W-1
R/W-1
R/W-1
—
—
PREFEN
—
PFMWS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26
PERCHEEN: Peripheral Cache Enable bit
1 = Peripheral cache is enabled
0 = Peripheral cache is disabled
bit 25
DCHEEN: Data Cache Enable bit
1 = Data cache is enabled
0 = Data cache is disabled
bit 24
ICHEEN: Instruction Cache Enable bit
1 = Instruction cache is enabled
0 = Instruction cache is disabled
bit 23
Unimplemented: Read as ‘0’
bit 22
PERCHEINV: Peripheral Cache Invalidate bit(1)
1 = Force invalidate cache/invalidate busy
0 = Cache Invalidation follows CHECOH/invalid complete
bit 21
DCHEINV: Data Cache Invalidate bit(1)
1 = Force invalidate cache/invalidate busy
0 = Cache Invalidation follows CHECOH/invalid complete
bit 20
ICHEINV: Instruction Cache Invalidate bit(1)
1 = Force invalidate cache/invalidate busy
0 = Cache Invalidation follows CHECOH/invalid complete
bit 19
Unimplemented: Read as ‘0’
bit 18
PERCHECOH: Peripheral Auto-cache Coherency Control bit(2)
1 = Automatically invalidate cache on a programming event
0 = Do not automatically invalidate cache on a programming event
Note 1:
2:
Hardware automatically clears this bit when cache invalidate completes. Bits may clear at different times.
The PERCHECOH, DCHECOH, and ICHECOH bits must be stable before initiation of programming to
ensure correct invalidation of data.
DS60001402H-page 186
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 10-1:
CHECON: CACHE MODULE CONTROL REGISTER (CONTINUED)
bit 17
DCHECOH: Data Auto-cache Coherency Control bit(2)
1 = Automatically invalidate cache on a programming event
0 = Do not automatically invalidate cache on a programming event
bit 16
ICHECOH: Instruction Auto-cache Coherency Control bit(2)
1 = Automatically invalidate cache on a programming event
0 = Do not automatically invalidate cache on a programming event
bit 15-13 Unimplemented: Read as ‘0’
bit 12
CHEPERFEN: Cache Performance Counters Enable bit
1 = Performance counters are enabled
0 = Performance counters are disabled
bit 11-9
Unimplemented: Read as ‘0’
bit 8
PFMAWSEN: PFM Address Wait State Enable bit
1 = Add one more Wait State to flash address setup (suggested for higher system clock frequencies)
0 = Add no Wait States to the flash address setup (suggested for lower system clock frequencies to achieve
higher performance)
When this bit is set to ‘1’, total Flash wait states are PFMWS plus PFMAWSEN.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
PREFEN: Predictive Prefetch Enable bits
11 = Disable predictive prefetch
10 = Disable predictive prefetch
01 = Enable predictive prefetch for CPU instructions only
00 = Disable predictive prefetch
bit 3
Unimplemented: Read as ‘0’
bit 2-0
PFMWS: PFM Access Time Defined in Terms of SYSCLK Wait States bits
111 = Seven Wait states
•
•
•
010 = Two Wait states
001 = One Wait state
000 = Zero Wait states
Required Flash Wait States
Note 1:
2:
Note 1:
2:
SYSCLK (MHz)
1 - Wait State
0 < SYSCLK 60 MHz
3 - Wait State
60 MHz < SYSCLK 120 MHz
When the LPRD bit (NVMCON) = 0, Flash read access wait states are governed by the
PFMWS bits.
When the LPRD bit = 1, Flash read access wait states are governed by the LPRDWS
bits (NVMCOM2).
Hardware automatically clears this bit when cache invalidate completes. Bits may clear at different times.
The PERCHECOH, DCHECOH, and ICHECOH bits must be stable before initiation of programming to
ensure correct invalidation of data.
2016-2021 Microchip Technology Inc.
DS60001402H-page 187
PIC32MK GP/MC Family
REGISTER 10-2:
Bit
Range
31:24
23:16
15:8
7:0
CHEHIT: CACHE HIT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHEHIT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHEHIT
R/W-0
CHEHIT
R/W-0
CHEHIT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
CHEHIT: Instruction Cache Hit Count bits
When the CHEPERFEN bit (CHECON) = 1, the CHEHIT bits increment each time the processor issues an instruction fetch or load that hits the prefetch cache from a cacheable region. Non-cacheable
accesses do not modify this value.
The CHEHIT bits are reset on a ‘0’ to ‘1’ transition of the CHEPERFEN bit.
DS60001402H-page 188
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 10-3:
Bit
Range
31:24
23:16
15:8
7:0
CHEMIS: CACHE MISS STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHEMIS
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHEMIS
R/W-0
CHEMIS
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHEMIS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
CHEMIS: Instruction Cache Miss Count bits
When the CHEPERFEN bit (CHECON) = 1, the CHEMIS bits increment each time the processor issues an instruction fetch or load that hits the prefetch cache from a cacheable region. Non-cacheable
accesses do not modify this value.
The CHEMIS bits are reset on a ‘0’ to ‘1’ transition of the CHEPERFEN bit.
2016-2021 Microchip Technology Inc.
DS60001402H-page 189
PIC32MK GP/MC Family
11.0
Note:
DIRECT MEMORY ACCESS
(DMA) CONTROLLER
This data sheet summarizes the features
of the PIC32MK GP/MC family of devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 31. “Direct Memory Access
(DMA) Controller” (DS60001117), which
is available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The Direct Memory Access (DMA) Controller is a bus
Host module useful for data transfers between different
devices without CPU intervention. The source and
destination of a DMA transfer can be any of the
memory mapped modules existent in the device such
as SPI, UART, PMP, etc., or memory itself.
Following are some of the key features of the DMA
Controller module:
• Eight identical channels, each featuring:
- Auto-increment source and destination
address registers
- Source and destination pointers
- Memory-to-memory and memory-toperipheral transfers
• Automatic word-size detection:
- Transfer granularity, down to byte level
- Bytes need not be word-aligned at source and
destination
FIGURE 11-1:
DMA BLOCK DIAGRAM
INT Controller
Peripheral Bus
• Fixed priority channel arbitration
• Flexible DMA channel operating modes:
- Manual (software) or automatic (interrupt) DMA
requests
- One-Shot or Auto-Repeat Block Transfer modes
- Channel-to-channel chaining
• Flexible DMA requests:
- A DMA request can be selected from any of the
peripheral interrupt sources
- Each channel can select any (appropriate)
observable interrupt as its DMA request source
- A DMA transfer abort can be selected from any
of the peripheral interrupt sources
- Up to 2-byte Pattern (data) match transfer
termination
• Multiple DMA channel status interrupts:
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half full
- DMA transfer aborted due to an external event
- Invalid DMA address generated
• DMA debug support features:
- Most recent error address accessed by a DMA
channel
- Most recent DMA channel to transfer data
• CRC Generation module:
- CRC module can be assigned to any of the
available channels
- CRC module is highly configurable
System IRQ
Address Decoder
SE
Channel 0 Control
I0
Channel 1 Control
I1
DMA
SYSCLK
L
Y
Bus
Interface
System Bus + Bus Arbitration
I2
Global Control
(DMACON)
Channel n Control
In
SE
L
Channel Priority
Arbitration
DS60001402H-page 190
2016-2021 Microchip Technology Inc.
DMA Control Registers
Virtual Address
(BF81_#)
Register
Name(1)
TABLE 11-1:
1000
DMACON
1010
DMASTAT
DMA GLOBAL REGISTER MAP
1020 DMAADDR
31/15
30/14
29/13
31:16
—
—
—
15:0
ON
—
—
31:16
RDWR
—
—
—
15:0
—
—
—
—
All Resets
Bit Range
Bits
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
SUSPEND DMABUSY
31:16
DMACH
0000
0000
DMAADDR
15:0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
DMA CRC REGISTER MAP
1030 DCRCCON
1040 DCRCDATA
2016-2021 Microchip Technology Inc.
1050 DCRCXOR
31/15
30/14
31:16
—
—
15:0
—
—
31:16
15:0
31:16
15:0
29/13
28/12
BYTO
—
27/11
WBO
26/10
25/9
24/8
—
—
BITO
PLEN
23/7
—
CRCEN
DCRCDATA
DCRCXOR
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
—
—
CRCAPP CRCTYP
17/1
16/0
—
—
CRCCH
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF81_#)
TABLE 11-2:
0000
0000
0000
0000
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
DS60001402H-page 191
11.1
Virtual Address
(BF81_#)
1060 DCH0CON
1070 DCH0ECON
1080
DCH0INT
1090 DCH0SSA
10A0 DCH0DSA
10B0 DCH0SSIZ
10C0 DCH0DSIZ
10D0 DCH0SPTR
10F0 DCH0CSIZ
1100 DCH0CPTR
DCH0DAT
1120 DCH1CON
1130 DCH1ECON
DS60001402H-page 192
1140
DCH1INT
1150 DCH1SSA
1160 DCH1DSA
30/14
29/13
15:0 CHBUSY
—
CHPIGNEN
—
31:16
—
—
—
31:16
28/12
27/11
26/10
25/9
24/8
23/7
—
—
CHPATLEN
—
—
CHCHNS
CHEN
CHAED
—
—
—
—
CHPIGN
—
15:0
CHSIRQ
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
CHCHN
CHAEN
—
—
—
—
CHEDET
—
0000
CHPRI
0000
FF00
CHAIRQ
CFORCE CABORT
All Resets
Bit Range
31/15
00FF
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
0000
FF00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
CHCPTR
15:0
—
—
0000
CHPDAT
31:16
CHPIGN
15:0 CHBUSY
—
CHPIGNEN
—
CHPATLEN
—
—
CHCHNS
31:16
—
—
—
—
—
—
—
—
15:0
CHSIRQ
0000
0000
CHCSIZ
15:0
31:16
—
CHDPTR
15:0
31:16
0000
—
CHSPTR
15:0
31:16
—
CHDSIZ
15:0
31:16
—
CHSSIZ
15:0
31:16
0000
0000
CHDSA
15:0
31:16
0000
CHSSA
15:0
0000
0000
CHAIRQ
CFORCE CABORT
00FF
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
31:16
15:0
31:16
15:0
CHSSA
CHDSA
0000
0000
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
10E0 DCH0DPTR
1110
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP
Bits
Register
Name(1)
2016-2021 Microchip Technology Inc.
TABLE 11-3:
Virtual Address
(BF81_#)
1180 DCH1DSIZ
1190 DCH1SPTR
11A0 DCH1DPTR
11B0 DCH1CSIZ
11C0 DCH1CPTR
11D0 DCH1DAT
11E0 DCH2CON
11F0 DCH2ECON
DCH2INT
1210 DCH2SSA
1220 DCH2DSA
2016-2021 Microchip Technology Inc.
1230 DCH2SSIZ
1240 DCH2DSIZ
1250 DCH2SPTR
1260 DCH2DPTR
1270 DCH2CSIZ
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
0000
FF00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
CHCPTR
15:0
—
—
0000
CHPDAT
31:16
CHPIGN
15:0 CHBUSY
—
CHPIGNEN
—
CHPATLEN
—
—
CHCHNS
31:16
—
—
—
—
—
—
—
—
15:0
CHSIRQ
0000
0000
CHCSIZ
15:0
31:16
21/5
CHDPTR
15:0
31:16
22/6
CHSPTR
15:0
31:16
23/7
CHDSIZ
15:0
31:16
24/8
CHSSIZ
—
All Resets
Bit Range
Register
Name(1)
Bits
1170 DCH1SSIZ
1200
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
0000
0000
CHAIRQ
CFORCE CABORT
00FF
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
0000
CHDPTR
—
—
CHCSIZ
0000
0000
CHSPTR
15:0
31:16
—
CHDSIZ
15:0
31:16
0000
CHSSIZ
15:0
31:16
0000
CHDSA
15:0
31:16
0000
CHSSA
15:0
0000
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
DS60001402H-page 193
TABLE 11-3:
Virtual Address
(BF81_#)
1280 DCH2CPTR
1290 DCH2DAT
12A0 DCH3CON
12B0 DCH3ECON
12C0
DCH3INT
12D0 DCH3SSA
12E0 DCH3DSA
12F0 DCH3SSIZ
1310 DCH3SPTR
1320 DCH3DPTR
1330 DCH3CSIZ
1340 DCH3CPTR
1350 DCH3DAT
DS60001402H-page 194
1360 DCH4CON
1370 DCH4ECON
DCH4INT
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
0000
FF00
CHCPTR
—
—
—
—
—
—
—
15:0
—
—
CHPIGN
15:0 CHBUSY
—
CHPIGNEN
—
CHPATLEN
—
—
CHCHNS
31:16
—
—
—
—
—
—
—
—
15:0
CHSIRQ
0000
0000
CHPDAT
31:16
All Resets
Bit Range
31:16
31/15
0000
0000
CHAIRQ
CFORCE CABORT
00FF
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
0000
FF00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
CHCPTR
15:0
—
—
0000
CHPDAT
31:16
CHPIGN
15:0 CHBUSY
—
CHPIGNEN
—
CHPATLEN
—
—
CHCHNS
31:16
—
—
—
—
—
—
—
—
15:0
CHSIRQ
0000
0000
CHCSIZ
15:0
31:16
0000
—
CHDPTR
15:0
31:16
—
CHSPTR
15:0
31:16
—
CHDSIZ
15:0
31:16
0000
CHSSIZ
15:0
31:16
0000
CHDSA
15:0
31:16
0000
CHSSA
15:0
0000
0000
CHAIRQ
CFORCE CABORT
00FF
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
1300 DCH3DSIZ
1380
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
Bits
Register
Name(1)
2016-2021 Microchip Technology Inc.
TABLE 11-3:
Virtual Address
(BF81_#)
13A0 DCH4DSA
13B0 DCH4SSIZ
13C0 DCH4DSIZ
13D0 DCH4SPTR
13E0 DCH4DPTR
13F0 DCH4CSIZ
1400 DCH4CPTR
1410 DCH4DAT
1420 DCH5CON
1430 DCH5ECON
DCH5INT
2016-2021 Microchip Technology Inc.
1450 DCH5SSA
1460 DCH5DSA
1470 DCH5SSIZ
1480 DCH5DSIZ
1490 DCH5SPTR
31/15
30/14
29/13
28/12
27/11
26/10
25/9
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
17/1
16/0
0000
0000
0000
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
0000
FF00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
CHCPTR
15:0
—
—
0000
CHPDAT
31:16
CHPIGN
15:0 CHBUSY
—
CHPIGNEN
—
CHPATLEN
—
—
CHCHNS
31:16
—
—
—
—
—
—
—
—
15:0
CHSIRQ
0000
0000
CHCSIZ
15:0
31:16
18/2
CHDPTR
15:0
31:16
19/3
CHSPTR
15:0
31:16
20/4
CHDSIZ
15:0
31:16
21/5
CHSSIZ
15:0
31:16
22/6
CHDSA
15:0
31:16
23/7
CHSSA
15:0
31:16
24/8
All Resets
Bit Range
Register
Name(1)
Bits
1390 DCH4SSA
1440
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
0000
0000
CHAIRQ
CFORCE CABORT
00FF
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
31:16
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
15:0
0000
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
CHSSIZ
15:0
31:16
0000
CHDSA
15:0
31:16
0000
CHSSA
—
—
0000
CHDSIZ
—
—
—
—
—
—
—
—
—
CHSPTR
0000
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
DS60001402H-page 195
TABLE 11-3:
Virtual Address
(BF81_#)
14A0 DCH5DPTR
14B0 DCH5CSIZ
14C0 DCH5CPTR
14D0 DCH5DAT
14E0 DCH6CON
14F0 DCH6ECON
1500
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
DCH6INT
1510 DCH6SSA
1530 DCH6SSIZ
1540 DCH6DSIZ
1550 DCH6SPTR
1560 DCH6DPTR
1570 DCH6CSIZ
1580 DCH6CPTR
DS60001402H-page 196
1590 DCH6DAT
15A0 DCH7CON
31:16
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
15:0
31:16
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
0000
FF00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CHCPTR
15:0
—
—
0000
CHPDAT
31:16
CHPIGN
15:0 CHBUSY
—
CHPIGNEN
—
CHPATLEN
—
—
CHCHNS
31:16
—
—
—
—
—
—
—
—
15:0
CHSIRQ
0000
0000
CHCSIZ
15:0
31:16
24/8
CHDPTR
—
All Resets
31/15
0000
0000
CHAIRQ
CFORCE CABORT
00FF
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
CHCPTR
15:0
—
0000
CHPDAT
31:16
15:0 CHBUSY
—
CHPIGN
—
CHPIGNEN
—
CHPATLEN
—
—
CHCHNS
0000
0000
CHCSIZ
15:0
31:16
0000
—
CHDPTR
15:0
31:16
—
CHSPTR
15:0
31:16
—
CHDSIZ
15:0
31:16
0000
CHSSIZ
15:0
31:16
0000
CHDSA
15:0
31:16
0000
CHSSA
15:0
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
1520 DCH6DSA
Bit Range
Bits
Register
Name(1)
2016-2021 Microchip Technology Inc.
TABLE 11-3:
Virtual Address
(BF81_#)
DCH7INT
15D0 DCH7SSA
15E0 DCH7DSA
15F0 DCH7SSIZ
1600 DCH7DSIZ
1610 DCH7SPTR
1620 DCH7DPTR
1630 DCH7CSIZ
1640 DCH7CPTR
1650 DCH7DAT
31:16
31/15
30/14
29/13
—
—
—
15:0
28/12
27/11
26/10
25/9
24/8
—
—
—
—
—
CHSIRQ
23/7
22/6
21/5
20/4
PATEN
SIRQEN
19/3
18/2
17/1
16/0
AIRQEN
—
—
—
CHAIRQ
CFORCE CABORT
All Resets
Bit Range
Register
Name(1)
Bits
15B0 DCH7ECON
15C0
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
00FF
FF00
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
0000
0000
0000
CHCPTR
—
—
CHPDAT
0000
0000
CHCSIZ
15:0
31:16
0000
—
CHDPTR
15:0
31:16
—
CHSPTR
15:0
31:16
—
CHDSIZ
15:0
31:16
0000
CHSSIZ
15:0
31:16
0000
CHDSA
15:0
31:16
0000
CHSSA
15:0
0000
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
DS60001402H-page 197
TABLE 11-3:
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 11-1:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
DMACON: DMA CONTROLLER CONTROL REGISTER
Bit
Bit
30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
ON
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
SUSPEND(1) DMABUSY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: DMA On bit
1 = DMA module is enabled
0 = DMA module is disabled
bit 14-13 Unimplemented: Read as ‘0’
bit 12
SUSPEND: DMA Suspend bit(1)
1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus
0 = DMA operates normally
bit 11
DMABUSY: DMA Module Busy bit
1 = DMA module is active and is transferring data
0 = DMA module is disabled and not actively transferring data
bit 10-0
Unimplemented: Read as ‘0’
Note 1:
If the user application clears this bit, it may take a number of cycles before the DMA module completes
the current transaction and responds to this request. The user application should poll the BUSY bit to
verify that the request has been honored.
DS60001402H-page 198
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 11-2:
Bit
Range
31:24
23:16
15:8
7:0
DMASTAT: DMA STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
RDWR
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
—
—
—
—
—
DMACH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
RDWR: Read/Write Status bit
1 = Last DMA bus access when an error was detected was a read
0 = Last DMA bus access when an error was detected was a write
bit 30-3 Unimplemented: Read as ‘0’
bit 2-0
Note:
DMACH: DMA Channel bits
These bits contain the value of the most recent active DMA channel when an error was detected.
The DMASTAT register will be cleared when its contents are read. If more than one errors at the same time,
the read transaction will be recorded. Additional transfers that occur later with an error will not update this
register until it has been read or cleared.
2016-2021 Microchip Technology Inc.
DS60001402H-page 199
PIC32MK GP/MC Family
REGISTER 11-3:
Bit
Range
31:24
23:16
15:8
7:0
DMAADDR: DMA ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R-0
R-0
R-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DMAADDR
R-0
R-0
R-0
R-0
R-0
DMAADDR
R-0
R-0
R-0
R-0
R-0
DMAADDR
R-0
R-0
R-0
R-0
R-0
DMAADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DMAADDR: DMA Module Address bits
These bits contain the address of the most recent DMA access when an error was detected.
Note:
The DMAADDR register will be cleared when its contents are read. If more than one errors at the same
time, the read transaction will be recorded. Additional transfers that occur later with an error will not update
this register until it has been read or cleared.
DS60001402H-page 200
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 11-4:
Bit
Range
31:24
23:16
15:8
7:0
DCRCCON: DMA CRC CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
R/W-0
R/W-0
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
U-0
U-0
R/W-0
WBO(1)
—
—
BITO
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BYTO
PLEN(1,2,3)
R/W-0
R/W-0
R/W-0
U-0
U-0
CRCEN
CRCAPP(1)
CRCTYP
—
—
R/W-0
CRCCH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 BYTO: CRC Byte Order Selection bits
11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order
per half-word)
10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per
half-word)
01 = Endian byte swap on word boundaries (i.e., reverse source byte order)
00 = No swapping (i.e., source byte order)
bit 27
WBO: CRC Write Byte Order Selection bit(1)
1 = Source data is written to the destination re-ordered as defined by BYTO
0 = Source data is written to the destination unaltered
bit 26-25 Unimplemented: Read as ‘0’
bit 24
BITO: CRC Bit Order Selection bit
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected)
0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected)
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected)
0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected)
bit 23-13 Unimplemented: Read as ‘0’
bit 12-8
PLEN: Polynomial Length bits(1,2,3)
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
These bits are unused.
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
Denotes the length of the polynomial – 1.
bit 7
CRCEN: CRC Enable bit
1 = CRC module is enabled and channel transfers are routed through the CRC module
0 = CRC module is disabled and channel transfers proceed normally
Note 1:
2:
3:
When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
The maximum CRC length supported by the DMA module is 32.
This bit is unused when CRCTYP is equal to ‘1’.
2016-2021 Microchip Technology Inc.
DS60001402H-page 201
PIC32MK GP/MC Family
REGISTER 11-4:
DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED)
bit 6
CRCAPP: CRC Append Mode bit(1)
1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer
completes the DMA writes the calculated CRC value to the location given by CHxDSA
0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the
destination
bit 5
CRCTYP: CRC Type Selection bit
1 = The CRC module will calculate an IP header checksum
0 = The CRC module will calculate a LFSR CRC
bit 4-3
Unimplemented: Read as ‘0’
bit 2-0
CRCCH: CRC Channel Select bits
111 = CRC is assigned to Channel 7
110 = CRC is assigned to Channel 6
101 = CRC is assigned to Channel 5
100 = CRC is assigned to Channel 4
011 = CRC is assigned to Channel 3
010 = CRC is assigned to Channel 2
001 = CRC is assigned to Channel 1
000 = CRC is assigned to Channel 0
Note 1:
2:
3:
When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
The maximum CRC length supported by the DMA module is 32.
This bit is unused when CRCTYP is equal to ‘1’.
DS60001402H-page 202
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 11-5:
Bit
Range
31:24
23:16
15:8
7:0
DCRCDATA: DMA CRC DATA REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA
R/W-0
R/W-0
DCRCDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DCRCDATA: CRC Data Register bits
Writing to this register will seed the CRC generator. Reading from this register will return the current value of
the CRC. Bits greater than PLEN will return ‘0’ on any read.
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written
to this register is converted and read back in 1’s complement form (i.e., current IP header checksum value).
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
Bits greater than PLEN will return ‘0’ on any read.
REGISTER 11-6:
Bit
Range
31:24
23:16
15:8
7:0
DCRCXOR: DMA CRCXOR ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR
R/W-0
R/W-0
DCRCXOR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DCRCXOR: CRC XOR Register bits
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
This register is unused.
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
1 = Enable the XOR input to the Shift register
0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in
the register
2016-2021 Microchip Technology Inc.
DS60001402H-page 203
PIC32MK GP/MC Family
REGISTER 11-7:
Bit
Range
31:24
23:16
15:8
7:0
DCHxCON: DMA CHANNEL ‘x’ CONTROL REGISTER (‘x’ = 0-7)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
CHPIGN
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
CHBUSY
—
CHIPGNEN
—
CHPATLEN
—
—
CHCHNS(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R-0
CHEN(2)
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 CHPIGN: Channel Register Data bits
Pattern Terminate mode:
Any byte matching these bits during a pattern match may be ignored during the pattern match determination when the CHPIGNEN bit is set. If a byte is read that is identical to this data byte, the pattern match
logic will treat it as a “don’t care” when the pattern matching logic is enabled and the CHPIGEN bit is set.
bit 23-16 Unimplemented: Read as ‘0’
bit 15
CHBUSY: Channel Busy bit
1 = Channel is active or has been enabled
0 = Channel is inactive or has been disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
CHPIGNEN: Enable Pattern Ignore Byte bit
1 = Treat any byte that matches the CHPIGN bits as a “don’t care” when pattern matching is enabled
0 = Disable this feature
bit 12
Unimplemented: Read as ‘0’
bit 11
CHPATLEN: Pattern Length bit
1 = 2 byte length
0 = 1 byte length
bit 10-9
Unimplemented: Read as ‘0’
bit 8
CHCHNS: Chain Channel Selection bit(1)
1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
bit 7
CHEN: Channel Enable bit(2)
1 = Channel is enabled
0 = Channel is disabled
bit 6
CHAED: Channel Allow Events If Disabled bit
1 = Channel start/abort events will be registered, even if the channel is disabled
0 = Channel start/abort events will be ignored if the channel is disabled
bit 5
CHCHN: Channel Chain Enable bit
1 = Allow channel to be chained
0 = Do not allow channel to be chained
Note 1:
2:
The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).
When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.
DS60001402H-page 204
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 11-7:
DCHxCON: DMA CHANNEL ‘x’ CONTROL REGISTER (‘x’ = 0-7) (CONTINUED)
bit 4
CHAEN: Channel Automatic Enable bit
1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete
0 = Channel is disabled on block transfer complete
bit 3
Unimplemented: Read as ‘0’
bit 2
CHEDET: Channel Event Detected bit
1 = An event has been detected
0 = No events have been detected
bit 1-0
CHPRI: Channel Priority bits
11 = Channel has priority 3 (highest)
10 = Channel has priority 2
01 = Channel has priority 1
00 = Channel has priority 0
Note 1:
2:
The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).
When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.
2016-2021 Microchip Technology Inc.
DS60001402H-page 205
PIC32MK GP/MC Family
REGISTER 11-8:
Bit
Range
31:24
23:16
DCHxECON: DMA CHANNEL x EVENT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
(1)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CHAIRQ
15:8
R/W-1
CHSIRQ(1)
7:0
S-0
S-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
Legend:
R = Readable bit
-n = Value at POR
S = Settable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 CHAIRQ: Channel Transfer Abort IRQ bits(1)
11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag
•
•
•
bit 15-8
00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag
00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag
CHSIRQ: Channel Transfer Start IRQ bits(1)
11111111 = Interrupt 255 will initiate a DMA transfer
•
•
•
00000001 = Interrupt 1 will initiate a DMA transfer
00000000 = Interrupt 0 will initiate a DMA transfer
bit 2-0
The DMA does not support I2C, Change Notification, Input Capture, CTMU, QEI, and MC
PWMs. Using any of these DMA trigger transfer events could lead to unexpected behavior.
CFORCE: DMA Forced Transfer bit
1 = A DMA transfer is forced to begin when this bit is written to a ‘1’
0 = This bit always reads ‘0’
CABORT: DMA Abort Transfer bit
1 = A DMA transfer is aborted when this bit is written to a ‘1’
0 = This bit always reads ‘0’
PATEN: Channel Pattern Match Abort Enable bit
1 = Abort transfer and clear CHEN on pattern match
0 = Pattern match is disabled
SIRQEN: Channel Start IRQ Enable bit
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer
AIRQEN: Channel Abort IRQ Enable bit
1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs
0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer
Unimplemented: Read as ‘0’
Note 1:
See Table 8-3: “Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources.
Note:
bit 7
bit 6
bit 5
bit 4
bit 3
DS60001402H-page 206
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 11-9:
Bit
Range
31:24
23:16
15:8
7:0
DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23
CHSDIE: Channel Source Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 22
CHSHIE: Channel Source Half Empty Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 21
CHDDIE: Channel Destination Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 20
CHDHIE: Channel Destination Half Full Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 19
CHBCIE: Channel Block Transfer Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 18
CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 17
CHTAIE: Channel Transfer Abort Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 16
CHERIE: Channel Address Error Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 15-8
Unimplemented: Read as ‘0’
bit 7
CHSDIF: Channel Source Done Interrupt Flag bit
1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
0 = No interrupt is pending
bit 6
CHSHIF: Channel Source Half Empty Interrupt Flag bit
1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
0 = No interrupt is pending
2016-2021 Microchip Technology Inc.
DS60001402H-page 207
PIC32MK GP/MC Family
REGISTER 11-9:
DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER (CONTINUED)
bit 5
CHDDIF: Channel Destination Done Interrupt Flag bit
1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
0 = No interrupt is pending
bit 4
CHDHIF: Channel Destination Half Full Interrupt Flag bit
1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
0 = No interrupt is pending
bit 3
CHBCIF: Channel Block Transfer Complete Interrupt Flag bit
1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a
pattern match event occurs
0 = No interrupt is pending
bit 2
CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit
1 = A cell transfer has been completed (CHCSIZ bytes have been transferred)
0 = No interrupt is pending
bit 1
CHTAIF: Channel Transfer Abort Interrupt Flag bit
1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
0 = No interrupt is pending
bit 0
CHERIF: Channel Address Error Interrupt Flag bit
1 = A channel address error has been detected
Either the source or the destination address is invalid.
0 = No interrupt is pending
DS60001402H-page 208
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 11-10: DCHxSSA: DMA CHANNEL x SOURCE START ADDRESS REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
R/W-0
R/W-0
31:24
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
R/W-0
R/W-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA
R/W-0
23:16
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA
R/W-0
15:8
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA
R/W-0
7:0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
CHSSA Channel Source Start Address bits
Channel source start address.
Note: This must be the physical address of the source.
REGISTER 11-11: DCHxDSA: DMA CHANNEL x DESTINATION START ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSA
R/W-0
R/W-0
CHDSA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSA
R/W-0
CHDSA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 CHDSA: Channel Destination Start Address bits
Channel destination start address.
Note: This must be the physical address of the destination.
2016-2021 Microchip Technology Inc.
DS60001402H-page 209
PIC32MK GP/MC Family
REGISTER 11-12: DCHxSSIZ: DMA CHANNEL x SOURCE SIZE REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSIZ
7:0
R/W-0
CHSSIZ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHSSIZ: Channel Source Size bits
1111111111111111 = 65,535 byte source size
•
•
•
0000000000000010 = 2 byte source size
0000000000000001 = 1 byte source size
0000000000000000 = 65,536 byte source size
REGISTER 11-13: DCHxDSIZ: DMA CHANNEL x DESTINATION SIZE REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSIZ
7:0
R/W-0
CHDSIZ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHDSIZ: Channel Destination Size bits
1111111111111111 = 65,535 byte destination size
•
•
•
0000000000000010 = 2 byte destination size
0000000000000001 = 1 byte destination size
0000000000000000 = 65,536 byte destination size
DS60001402H-page 210
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 11-14: DCHxSPTR: DMA CHANNEL x SOURCE POINTER REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHSPTR
7:0
R-0
R-0
CHSPTR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHSPTR: Channel Source Pointer bits
1111111111111111 = Points to byte 65,535 of the source
•
•
•
0000000000000001 = Points to byte 1 of the source
0000000000000000 = Points to byte 0 of the source
Note:
When in Pattern Detect mode, this register is reset on a pattern detect.
2016-2021 Microchip Technology Inc.
DS60001402H-page 211
PIC32MK GP/MC Family
REGISTER 11-15: DCHxDPTR: DMA CHANNEL x DESTINATION POINTER REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHDPTR
7:0
R-0
R-0
CHDPTR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHDPTR: Channel Destination Pointer bits
1111111111111111 = Points to byte 65,535 of the destination
•
•
•
0000000000000001 = Points to byte 1 of the destination
0000000000000000 = Points to byte 0 of the destination
DS60001402H-page 212
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 11-16: DCHxCSIZ: DMA CHANNEL x CELL-SIZE REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHCSIZ
7:0
R/W-0
CHCSIZ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCSIZ: Channel Cell-Size bits
1111111111111111 = 65,535 bytes transferred on an event
•
•
•
0000000000000010 = 2 bytes transferred on an event
0000000000000001= 1 byte transferred on an event
0000000000000000 = 65,536 bytes transferred on an event
2016-2021 Microchip Technology Inc.
DS60001402H-page 213
PIC32MK GP/MC Family
REGISTER 11-17: DCHxCPTR: DMA CHANNEL x CELL POINTER REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHCPTR
7:0
R-0
R-0
CHCPTR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCPTR: Channel Cell Progress Pointer bits
1111111111111111 = 65,535 bytes have been transferred since the last event
•
•
•
0000000000000001 = 1 byte has been transferred since the last event
0000000000000000 = 0 bytes have been transferred since the last event
Note:
When in Pattern Detect mode, this register is reset on a pattern detect.
DS60001402H-page 214
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 11-18: DCHxDAT: DMA CHANNEL x PATTERN DATA REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHPDAT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHPDAT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CHPDAT: Channel Data Register bits
Pattern Terminate mode:
Data to be matched must be stored in this register to allow terminate on match.
All other modes:
Unused.
2016-2021 Microchip Technology Inc.
DS60001402H-page 215
PIC32MK GP/MC Family
12.0
Note:
USB ON-THE-GO (OTG)
This data sheet summarizes the
features of the PIC32MK GP/MC Family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 27. “USB OnThe-Go (OTG)” (DS60001126), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The Universal Serial Bus (USB) module contains
analog and digital components to provide a USB 2.0
full-speed and low-speed embedded host, full-speed
device or OTG implementation with a minimum of
external components. This module in Host mode is
intended for use as an embedded host and therefore
does not implement a UHCI or OHCI controller.
The USB module consists of the clock generator, the
USB voltage comparators, the transceiver, the Serial
Interface Engine (SIE), a dedicated USB DMA controller, pull-up and pull-down resistors, and the register
interface. A block diagram of the PIC32MK USB OTG
module is presented in Figure 12-1.
The PIC32MK USB module includes the following
features:
•
•
•
•
•
•
•
•
•
USB full-speed support for host and device
Low-speed host support
USB OTG support
Integrated signaling resistors
Integrated analog comparators for VBUS
monitoring
Integrated USB transceiver
Transaction handshaking performed by hardware
Endpoint buffering anywhere in system RAM
Integrated DMA to access system RAM and Flash
Note:
The implementation and use of the USB
specifications, and other third party
specifications or technologies, may
require licensing; including, but not limited
to, USB Implementers Forum, Inc. (also
referred to as USB-IF). The user is fully
responsible
for
investigating
and
satisfying any applicable licensing
obligations.
The clock generator provides the 48 MHz clock
required for USB full-speed and low-speed communication. The voltage comparators monitor the voltage on
the VBUS pin to determine the state of the bus. The
transceiver provides the analog translation between
the USB bus and the digital logic. The SIE is a state
machine that transfers data to and from the endpoint
buffers and generates the hardware protocol for data
transfers. The USB DMA controller transfers data
between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the
need for external signaling components. The register
interface allows the CPU to configure and
communicate with the module.
DS60001402H-page 216
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
FIGURE 12-1:
USB INTERFACE DIAGRAM
UPOSCEN (UPLLCON)
UFRCEN (OSCCON)
USB PLL (UPLL)(1)
5-64 MHz
FIN
/N
Filter
RNG
5-64 MHz
350-700 MHz 10-120 MHz
FPLL
FPLLI
FVCO
/N
PLL * M
0
1
PLLIDIV
(UPLLCON)
OSC1
PLLRANGE
(UPLLCON)
OSC2
PLLMUL
(UPLLCON)
48 MHz USB Clock
0
1
PLLODIV
(UPLLCON)
FOSC (HS or EC)
FRC Oscillator
8 MHz Typical
USB Module
SRP Charge
VBUS
SRP Discharge
USB
Voltage
Comparators
48 MHz USB Clock(2)
Full Speed Pull-up
D+
Registers
and
Control
Interface
Host Pull-down
SIE
Transceiver
Low Speed Pull-up
DDMA
System
RAM
Host Pull-down
ID Pull-up
ID(3)
VBUSON(3)
VUSB3V3
Note 1:
2:
3:
Transceiver Power 3.3V
These bits are contained in the DEVCFG2 register.
A 48 MHz clock is required for proper USB operation.
Pins can be used as GPIO when the USB module is disabled or when the USB module is enabled but the
FVBUSIOx bit (DEVCFG3) = 0 or the FUSBIDIOx bit (DEVCFG3) = 0.
2016-2021 Microchip Technology Inc.
DS60001402H-page 217
Control Registers
Register
Name(1)
TABLE 12-1:
Virtual Address
(BF88_#)
9040
U1OTGIR(2)
9050
U1OTGIE
9080
U1OTGCON
U1PWRC
U1IR(2)
9200
9220
U1IE
U1EIR(2)
9230
9240
U1EIE
U1STAT(3)
9250
DS60001402H-page 218
9260
9270
U1CON
U1ADDR
U1BDTP1
Legend:
Note 1:
2:
3:
4:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
22/6
21/5
—
—
20/4
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
IDIF
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
IDIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
ID
—
LSTATE
—
SESVD
SESEND
—
VBUSVD
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
OTGEN
VBUSCHG
VBUSDIS
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
UACTPND(4)
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
T1MSECIF LSTATEIF
—
—
ACTVIF
—
T1MSECIE LSTATEIE
19/3
18/2
17/1
—
—
—
SESVDIF SESENDIF
—
ACTVIE
DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON
15:0
—
—
—
—
—
—
—
—
STALLIF
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
STALLIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
ATTACHIE RESUMEIE
—
—
USLPGRD USBBUSY
ATTACHIF RESUMEIF
—
—
—
IDLEIF
TRNIF
—
—
UERRIE
—
—
—
—
—
—
—
BTSEF
BMXEF
DMAEF
BTOEF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BTSEE
BMXEE
DMAEE
BTOEE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
ENDPT
—
—
—
—
—
—
—
JSTATE
SE0
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
LSPDEN
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
TOKBUSY
—
DFN8EF CRC16EF
—
15:0
—
UERRIF
SOFIE
—
15:0
—
—
—
PKTDIS
SOFIF
USBRST
—
—
DFN8EE CRC16EE
—
—
CRC5EF
EOFEF
—
CRC5EE
EOFEE
—
—
BDTPTRL
0000
—
0000
URSTIF
0000
DETACHIF 0000
—
0000
URSTIE
0000
DETACHIE 0000
—
PIDEF
—
PIDEE
0000
0000
0000
0000
0000
0000
—
—
—
—
0000
DIR
PPBI
—
—
0000
—
—
—
—
0000
USBEN
0000
SOFEN
0000
0000
HOSTEN RESUME
—
—
0000
VBUSVDIE 0000
PPBRST
—
—
—
—
—
—
0000
—
0000
DEVADDR
—
0000
VBUSVDIF 0000
USUSPEND USBPWR
TRNIE
—
—
—
—
—
—
—
—
—
IDLEIE
15:0
—
—
SESVDIE SESENDIE
—
16/0
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC respectively. See
13.2 “CLR, SET, and INV Registers” for more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET, and INV registers.
Reset value for this bit is undefined.
PIC32MK GP/MC Family
9210
23/7
All Resets
Bits
9060 U1OTGSTAT(3)
9070
USB1 AND USB2 REGISTER MAP
Bit Range
2016-2021 Microchip Technology Inc.
12.1
Virtual Address
(BF88_#)
Register
Name(1)
9280
U1FRML(3)
9290
U1FRMH(3)
U1TOK
92B0
U1SOF
92C0
U1BDTP2
U1BDTP3
92E0
U1CNFG1
9300
U1EP0
9310
U1EP1
9320
U1EP2
9330
U1EP3
2016-2021 Microchip Technology Inc.
9340
U1EP4
9350
U1EP5
9360
U1EP6
9370
U1EP7
9380
U1EP8
Legend:
Note 1:
2:
3:
4:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
UTEYE
UOEMON
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
LSPD
RETRYDIS
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
FRML
—
—
FRMH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
USBSIDL
LSDEV
—
—
—
—
—
—
—
—
—
EPCONDIS EPRXEN
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
0000
0000
BDTPTRU
—
0000
0000
BDTPTRH
—
0000
0000
—
CNT
—
0000
0000
—
EP
—
0000
0000
PID
—
All Resets
Bit Range
Bits
92A0
92D0
USB1 AND USB2 REGISTER MAP (CONTINUED)
0000
0000
0000
UASUSPND 0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC respectively. See
13.2 “CLR, SET, and INV Registers” for more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET, and INV registers.
Reset value for this bit is undefined.
PIC32MK GP/MC Family
DS60001402H-page 219
TABLE 12-1:
Virtual Address
(BF88_#)
Register
Name(1)
9390
U1EP9
U1EP10
93B0
U1EP11
93C0
U1EP12
93D0
U1EP13
U1EP14
93F0
U1EP15
A040
U2OTGIR(2)
A050
U2OTGIE
A060 U2OTGSTAT(3)
A080
U2OTGCON
U2PWRC
U2IR(2)
A200
A210
U2IE
DS60001402H-page 220
Legend:
Note 1:
2:
3:
4:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
IDIF
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
IDIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
ID
—
LSTATE
—
SESVD
SESEND
—
VBUSVD
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
OTGEN
VBUSCHG
VBUSDIS
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
UACTPND(4)
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STALLIF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T1MSECIE LSTATEIE
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
ACTVIF
—
ACTVIE
—
STALLIE
ATTACHIF RESUMEIF
—
—
ATTACHIE RESUMEIE
—
—
—
—
17/1
—
—
—
0000
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
—
—
—
—
—
—
—
TRNIF
SOFIF
UERRIF
—
—
—
—
TRNIE
SOFIE
VBUSVDIF 0000
—
UERRIE
0000
VBUSVDIE 0000
USUSPEND USBPWR
IDLEIF
IDLEIE
16/0
EPTXEN
SESVDIE SESENDIE
USLPGRD USBBUSY
—
18/2
SESVDIF SESENDIF
DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON
15:0
15:0
T1MSECIF LSTATEIF
19/3
0000
—
0000
URSTIF
0000
DETACHIF 0000
—
0000
URSTIE
0000
DETACHIE 0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC respectively. See
13.2 “CLR, SET, and INV Registers” for more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET, and INV registers.
Reset value for this bit is undefined.
PIC32MK GP/MC Family
93E0
20/4
All Resets
Bits
93A0
A070
USB1 AND USB2 REGISTER MAP (CONTINUED)
Bit Range
2016-2021 Microchip Technology Inc.
TABLE 12-1:
Virtual Address
(BF88_#)
Register
Name(1)
A220
U2EIR(2)
USB1 AND USB2 REGISTER MAP (CONTINUED)
31:16
A230
A240
U2EIE
U2STAT
A250
A260
(3)
U2CON
U2ADDR
A270
U2BDTP1
A280
(3)
A290
U2FRML
U2FRMH
A2A0
U2TOK
A2B0
A2C0
2016-2021 Microchip Technology Inc.
A2D0
(3)
U2SOF
U2BDTP2
U2BDTP3
A2E0
U2CNFG1
A300
U2EP0
Legend:
Note 1:
2:
3:
4:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
BTSEF
BMXEF
DMAEF
BTOEF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
DFN8EF CRC16EF
—
15:0
—
—
—
—
—
—
—
—
BTSEE
BMXEE
DMAEE
BTOEE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
JSTATE
SE0
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
LSPDEN
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
UTEYE
UOEMON
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
LSPD
RETRYDIS
—
TOKBUSY
—
USBRST
—
—
CRC5EF
EOFEF
CRC5EE
EOFEE
—
PIDEE
—
—
—
0000
—
—
0000
—
—
—
—
0000
USBEN
0000
SOFEN
0000
0000
HOSTEN RESUME
—
—
—
—
—
PPBRST
—
—
—
—
—
—
0000
—
0000
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
FRMH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
USBSIDL
LSDEV
—
—
—
—
—
—
—
—
0000
0000
BDTPTRH
—
0000
0000
—
CNT
—
0000
0000
—
EP
—
0000
PPBI
—
—
0000
DIR
PID
—
0000
—
FRML
—
0000
—
DEVADDR
—
0000
—
BDTPTRL
—
PIDEF
0000
—
—
PKTDIS
16/0
—
DFN8EE CRC16EE
ENDPT
—
—
17/1
All Resets
Bit Range
Bits
—
0000
BDTPTRU
EPCONDIS EPRXEN
0000
0000
0000
0000
UASUSPND 0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC respectively. See
13.2 “CLR, SET, and INV Registers” for more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET, and INV registers.
Reset value for this bit is undefined.
PIC32MK GP/MC Family
DS60001402H-page 221
TABLE 12-1:
Virtual Address
(BF88_#)
Register
Name(1)
A310
U2EP1
USB1 AND USB2 REGISTER MAP (CONTINUED)
A320
U2EP2
A330
U2EP3
A340
U2EP4
A350
U2EP5
A360
U2EP6
A370
U2EP7
A380
U2EP8
U2EP9
A3A0
U2EP10
A3B0
U2EP11
A3C0
U2EP12
A3D0
U2EP13
A3E0
U2EP14
A3F0
U2EP15
DS60001402H-page 222
Legend:
Note 1:
2:
3:
4:
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
20/4
19/3
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
—
—
EPCONDIS EPRXEN
18/2
17/1
16/0
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
—
—
—
0000
EPTXEN
EPSTALL
EPHSHK
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC respectively. See
13.2 “CLR, SET, and INV Registers” for more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET, and INV registers.
Reset value for this bit is undefined.
PIC32MK GP/MC Family
A390
31/15
All Resets
Bits
Bit Range
2016-2021 Microchip Technology Inc.
TABLE 12-1:
PIC32MK GP/MC Family
REGISTER 12-1:
Bit
Range
31:24
23:16
15:8
7:0
UxOTGIR: USB OTG INTERRUPT STATUS REGISTER (‘x’ = 1 AND 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
U-0
R/WC-0, HS
IDIF
T1MSECIF
LSTATEIF
ACTVIF
SESVDIF
SESENDIF
—
VBUSVDIF
Legend:
WC = Write ‘1’ to clear
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
IDIF: ID State Change Indicator bit
1 = Change in ID state is detected
0 = No change in ID state is detected
bit 6
T1MSECIF: 1 Millisecond Timer bit
1 = 1 millisecond timer has expired
0 = 1 millisecond timer has not expired
bit 5
LSTATEIF: Line State Stable Indicator bit
1 = USB line state has been stable for 1millisecond, but different from last time
0 = USB line state has not been stable for 1 millisecond
bit 4
ACTVIF: Bus Activity Indicator bit
1 = Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up
0 = Activity has not been detected
bit 3
SESVDIF: Session Valid Change Indicator bit
1 = VBUS voltage has dropped below the session end level
0 = VBUS voltage has not dropped below the session end level
bit 2
SESENDIF: B-Device VBUS Change Indicator bit
1 = A change on the session end input was detected
0 = No change on the session end input was detected
bit 1
Unimplemented: Read as ‘0’
bit 0
VBUSVDIF: A-Device VBUS Change Indicator bit
1 = Change on the session valid input is detected
0 = No change on the session valid input is detected
2016-2021 Microchip Technology Inc.
DS60001402H-page 223
PIC32MK GP/MC Family
REGISTER 12-2:
Bit
Range
31:24
23:16
15:8
7:0
UxOTGIE: USB OTG INTERRUPT ENABLE REGISTER (‘x’ = 1 AND 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
IDIE
T1MSECIE
LSTATEIE
ACTVIE
SESVDIE
SESENDIE
—
VBUSVDIE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
IDIE: ID Interrupt Enable bit
1 = ID interrupt is enabled
0 = ID interrupt is disabled
bit 6
T1MSECIE: 1 Millisecond Timer Interrupt Enable bit
1 = 1 millisecond timer interrupt is enabled
0 = 1 millisecond timer interrupt is disabled
bit 5
LSTATEIE: Line State Interrupt Enable bit
1 = Line state interrupt is enabled
0 = Line state interrupt is disabled
bit 4
ACTVIE: Bus Activity Interrupt Enable bit
1 = ACTIVITY interrupt is enabled
0 = ACTIVITY interrupt is disabled
bit 3
SESVDIE: Session Valid Interrupt Enable bit
1 = Session valid interrupt is enabled
0 = Session valid interrupt is disabled
bit 2
SESENDIE: B-Session End Interrupt Enable bit
1 = B-session end interrupt is enabled
0 = B-session end interrupt is disabled
bit 1
Unimplemented: Read as ‘0’
bit 0
VBUSVDIE: A-VBUS Valid Interrupt Enable bit
1 = A-VBUS valid interrupt is enabled
0 = A-VBUS valid interrupt is disabled
DS60001402H-page 224
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 12-3:
Bit
Range
31:24
23:16
15:8
7:0
UxOTGSTAT: USB OTG STATUS REGISTER (‘x’ = 1 AND 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
U-0
R-0
U-0
R-0
R-0
U-0
R-0
ID
—
LSTATE
—
SESVD
SESEND
—
VBUSVD
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
ID: ID Pin State Indicator bit
1 = No cable is attached or a Type-B cable has been plugged into the USB receptacle
0 = A Type-A cable has been plugged into the USB receptacle
bit 6
Unimplemented: Read as ‘0’
bit 5
LSTATE: Line State Stable Indicator bit
1 = USB line state (SE0 (UxCON) and JSTATE (UxCON)) has been stable for the previous 1 ms
0 = USB line state (SE0 and JSTATE) has not been stable for the previous 1 ms
bit 4
Unimplemented: Read as ‘0’
bit 3
SESVD: Session Valid Indicator bit
1 = VBUS voltage is above Session Valid on the A or B device
0 = VBUS voltage is below Session Valid on the A or B device
bit 2
SESEND: B-Device Session End Indicator bit
1 = VBUS voltage is below Session Valid on the B device
0 = VBUS voltage is above Session Valid on the B device
bit 1
Unimplemented: Read as ‘0’
bit 0
VBUSVD: A-Device VBUS Valid Indicator bit
1 = VBUS voltage is above Session Valid on the A device
0 = VBUS voltage is below Session Valid on the A device
2016-2021 Microchip Technology Inc.
DS60001402H-page 225
PIC32MK GP/MC Family
REGISTER 12-4:
Bit
Range
31:24
23:16
15:8
7:0
UxOTGCON: USB OTG CONTROL REGISTER (‘x’ = 1 AND 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VBUSON
OTGEN
VBUSCHG
VBUSDIS
DPPULUP DMPULUP DPPULDWN DMPULDWN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
DPPULUP: D+ Pull-Up Enable bit
1 = D+ data line pull-up resistor is enabled
0 = D+ data line pull-up resistor is disabled
bit 6
DMPULUP: D- Pull-Up Enable bit
1 = D- data line pull-up resistor is enabled
0 = D- data line pull-up resistor is disabled
bit 5
DPPULDWN: D+ Pull-Down Enable bit
1 = D+ data line pull-down resistor is enabled
0 = D+ data line pull-down resistor is disabled
bit 4
DMPULDWN: D- Pull-Down Enable bit
1 = D- data line pull-down resistor is enabled
0 = D- data line pull-down resistor is disabled
bit 3
VBUSON: VBUS Power-on bit
1 = VBUS line is powered
0 = VBUS line is not powered
bit 2
OTGEN: OTG Functionality Enable bit
1 = DPPULUP, DMPULUP, DPPULDWN, and DMPULDWN bits are under software control
0 = DPPULUP, DMPULUP, DPPULDWN, and DMPULDWN bits are under USB hardware control
bit 1
VBUSCHG: VBUS Charge Enable bit
1 = VBUS line is charged through a pull-up resistor
0 = VBUS line is not charged through a resistor
bit 0
VBUSDIS: VBUS Discharge Enable bit
1 = VBUS line is discharged through a pull-down resistor
0 = VBUS line is not discharged through a resistor
DS60001402H-page 226
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 12-5:
Bit
Bit
Range 31/23/15/7
31:24
23:16
15:8
7:0
UxPWRC: USB POWER CONTROL REGISTER (‘x’ = 1 AND 2)
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
U-0
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
UACTPND
—
—
USLPGRD USBBUSY(1)
—
USUSPEND USBPWR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
UACTPND: USB Activity Pending bit
1 = USB hardware has detected a change in link status; however, an interrupt is pending and has not yet
been generated. Software should not put the device into Sleep mode.
0 = An interrupt is not pending
bit 6-5
Unimplemented: Read as ‘0’
bit 4
USLPGRD: USB Sleep Entry Guard bit
1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending
0 = USB module does not block Sleep entry
bit 3
USBBUSY: USB Module Busy bit(1)
1 = USB module is active or disabled, but not ready to be enabled
0 = USB module is not active and is ready to be enabled
Note:
When USBPWR = 0 and USBBUSY = 1, status from all other registers is invalid and writes to all
USB module registers produce undefined results.
bit 2
Unimplemented: Read as ‘0’
bit 1
USUSPEND: USB Suspend Mode bit
1 = USB module is placed in Suspend mode
(The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.)
0 = USB module operates normally
bit 0
USBPWR: USB Operation Enable bit
1 = USB module is turned on
0 = USB module is disabled
(Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power
consumption.)
2016-2021 Microchip Technology Inc.
DS60001402H-page 227
PIC32MK GP/MC Family
REGISTER 12-6:
Bit
Bit
Range 31/23/15/7
31:24
23:16
15:8
7:0
UxIR: USB INTERRUPT REGISTER (‘x’ = 1 AND 2)
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R-0
IDLEIF
TRNIF(3)
SOFIF
UERRIF(4)
R/WC-0, HS
(5)
STALLIF
Legend:
R = Readable bit
-n = Value at POR
ATTACHIF(1) RESUMEIF(2)
WC = Write ‘1’ to clear
W = Writable bit
‘1’ = Bit is set
URSTIF
DETACHIF(6)
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
STALLIF: STALL Handshake Interrupt bit
1 = In Host mode, a STALL handshake was received during the handshake phase of the transaction
In Device mode, a STALL handshake was transmitted during the handshake phase of the transaction
0 = STALL handshake has not been sent
ATTACHIF: Peripheral Attach Interrupt bit(1)
1 = Peripheral attachment was detected by the USB module
0 = Peripheral attachment was not detected
RESUMEIF: Resume Interrupt bit(2)
1 = K-State is observed on the D+ or D- pin for 2.5 µs
0 = K-State is not observed
IDLEIF: Idle Detect Interrupt bit
1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
TRNIF: Token Processing Complete Interrupt bit(3)
1 = Processing of current token is complete; a read of the UxSTAT register will provide endpoint information
0 = Processing of current token not complete
SOFIF: SOF Token Interrupt bit
1 = SOF token received by the peripheral or the SOF threshold reached by the host
0 = SOF token was not received nor threshold reached
UERRIF: USB Error Condition Interrupt bit(4)
1 = Unmasked error condition has occurred
0 = Unmasked error condition has not occurred
URSTIF: USB Reset Interrupt bit (Device mode)(5)
1 = Valid USB Reset has occurred
0 = No USB Reset has occurred
DETACHIF: USB Detach Interrupt bit (Host mode)(6)
1 = Peripheral detachment was detected by the USB module
0 = Peripheral detachment was not detected
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
Note 1:
2:
3:
4:
5:
6:
This bit is valid only if the HOSTEN bit is set (see Register 12-11), there is no activity on the USB for
2.5 µs, and the current bus state is not SE0.
When not in Suspend mode, this interrupt should be disabled.
Clearing this bit will cause the STAT FIFO to advance.
Only error conditions enabled through the UxEIE register will set this bit.
Device mode.
Host mode.
DS60001402H-page 228
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 12-7:
Bit
Range
31:24
23:16
15:8
7:0
UxIE: USB INTERRUPT ENABLE REGISTER (‘x’ = 1 AND 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IDLEIE
TRNIE
SOFIE
UERRIE(1)
STALLIE
ATTACHIE RESUMEIE
URSTIE(2)
DETACHIE(3)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
STALLIE: STALL Handshake Interrupt Enable bit
1 = STALL interrupt is enabled
0 = STALL interrupt is disabled
bit 6
ATTACHIE: ATTACH Interrupt Enable bit
1 = ATTACH interrupt is enabled
0 = ATTACH interrupt is disabled
bit 5
RESUMEIE: RESUME Interrupt Enable bit
1 = RESUME interrupt is enabled
0 = RESUME interrupt is disabled
bit 4
IDLEIE: Idle Detect Interrupt Enable bit
1 = Idle interrupt is enabled
0 = Idle interrupt is disabled
bit 3
TRNIE: Token Processing Complete Interrupt Enable bit
1 = TRNIF interrupt is enabled
0 = TRNIF interrupt is disabled
bit 2
SOFIE: SOF Token Interrupt Enable bit
1 = SOFIF interrupt is enabled
0 = SOFIF interrupt is disabled
bit 1
UERRIE: USB Error Interrupt Enable bit(1)
1 = USB Error interrupt is enabled
0 = USB Error interrupt is disabled
bit 0
URSTIE: USB Reset Interrupt Enable bit(2)
1 = URSTIF interrupt is enabled
0 = URSTIF interrupt is disabled
DETACHIE: USB Detach Interrupt Enable bit(3)
1 = DATTCHIF interrupt is enabled
0 = DATTCHIF interrupt is disabled
Note 1:
2:
3:
For an interrupt to propagate USBIF, the UERRIE bit (UxIE) must be set.
Device mode.
Host mode.
2016-2021 Microchip Technology Inc.
DS60001402H-page 229
PIC32MK GP/MC Family
REGISTER 12-8:
Bit
Range
31:24
23:16
15:8
7:0
UxEIR: USB ERROR INTERRUPT STATUS REGISTER (‘x’ = 1 AND 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
BTSEF
BMXEF
DMAEF(1)
BTOEF(2)
DFN8EF
CRC16EF
CRC5EF(4)
EOFEF(3,5)
Legend:
WC = Write ‘1’ to clear
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
PIDEF
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
BTSEF: Bit Stuff Error Flag bit
1 = Packet rejected due to bit stuff error
0 = Packet accepted
bit 6
BMXEF: Bus Matrix Error Flag bit
1 = The base address, of the BDT, or the address of an individual buffer pointed to by a BDT entry, is invalid.
0 = No address error
bit 5
DMAEF: DMA Error Flag bit(1)
1 = USB DMA error condition detected
0 = No DMA error
bit 4
BTOEF: Bus Turnaround Time-Out Error Flag bit(2)
1 = Bus turnaround time-out has occurred
0 = No bus turnaround time-out
bit 3
DFN8EF: Data Field Size Error Flag bit
1 = Data field received is not an integral number of bytes
0 = Data field received is an integral number of bytes
bit 2
CRC16EF: CRC16 Failure Flag bit
1 = Data packet rejected due to CRC16 error
0 = Data packet accepted
Note 1:
2:
3:
4:
5:
This type of error occurs when the module’s request for the DMA bus is not granted in time to service the
module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer
size is not sufficient to store the received data packet causing it to be truncated.
This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)
has elapsed.
This type of error occurs when the module is transmitting or receiving data and the SOF counter has
reached zero.
Device mode.
Host mode.
DS60001402H-page 230
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 12-8:
UxEIR: USB ERROR INTERRUPT STATUS REGISTER (‘x’ = 1 AND 2)
bit 1
CRC5EF: CRC5 Host Error Flag bit(4)
1 = Token packet rejected due to CRC5 error
0 = Token packet accepted
EOFEF: EOF Error Flag bit(3,5)
1 = EOF error condition detected
0 = No EOF error condition
bit 0
PIDEF: PID Check Failure Flag bit
1 = PID check failed
0 = PID check passed
Note 1:
2:
3:
4:
5:
This type of error occurs when the module’s request for the DMA bus is not granted in time to service the
module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer
size is not sufficient to store the received data packet causing it to be truncated.
This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)
has elapsed.
This type of error occurs when the module is transmitting or receiving data and the SOF counter has
reached zero.
Device mode.
Host mode.
2016-2021 Microchip Technology Inc.
DS60001402H-page 231
PIC32MK GP/MC Family
REGISTER 12-9:
Bit
Range
31:24
23:16
15:8
7:0
UxEIE: USB ERROR INTERRUPT ENABLE REGISTER (‘x’ = 1 AND 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BTSEE
BMXEE
DMAEE
BTOEE
DFN8EE
CRC16EE
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
CRC5EE(1)
EOFEE(2)
PIDEE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
BTSEE: Bit Stuff Error Interrupt Enable bit
1 = BTSEF interrupt is enabled
0 = BTSEF interrupt is disabled
bit 6
BMXEE: Bus Matrix Error Interrupt Enable bit
1 = BMXEF interrupt is enabled
0 = BMXEF interrupt is disabled
bit 5
DMAEE: DMA Error Interrupt Enable bit
1 = DMAEF interrupt is enabled
0 = DMAEF interrupt is disabled
bit 4
BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1 = BTOEF interrupt is enabled
0 = BTOEF interrupt is disabled
bit 3
DFN8EE: Data Field Size Error Interrupt Enable bit
1 = DFN8EF interrupt is enabled
0 = DFN8EF interrupt is disabled
bit 2
CRC16EE: CRC16 Failure Interrupt Enable bit
1 = CRC16EF interrupt is enabled
0 = CRC16EF interrupt is disabled
bit 1
CRC5EE: CRC5 Host Error Interrupt Enable bit(1)
1 = CRC5EF interrupt is enabled
0 = CRC5EF interrupt is disabled
EOFEE: EOF Error Interrupt Enable bit(2)
1 = EOF interrupt is enabled
0 = EOF interrupt is disabled
bit 0
PIDEE: PID Check Failure Interrupt Enable bit
1 = PIDEF interrupt is enabled
0 = PIDEF interrupt is disabled
Note 1:
2:
Note:
Device mode.
Host mode.
For an interrupt to propagate USBIF, the UERRIE bit (UxIE) must be set.
DS60001402H-page 232
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 12-10: UxSTAT: USB STATUS REGISTER (‘x’ = 1 AND 2)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-x
R-x
R-x
R-x
R-x
R-x
U-0
U-0
DIR
PPBI
—
—
ENDPT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-4
ENDPT: Encoded Number of Last Endpoint Activity bits
(Represents the number of the BDT, updated by the last USB transfer.)
1111 = Endpoint 15
1110 = Endpoint 14
•
•
•
0001 = Endpoint 1
0000 = Endpoint 0
bit 3
DIR: Last BD Direction Indicator bit
1 = Last transaction was a transmit transfer (TX)
0 = Last transaction was a receive transfer (RX)
bit 2
PPBI: Ping-Pong BD Pointer Indicator bit
1 = The last transaction was to the ODD BD bank
0 = The last transaction was to the EVEN BD bank
bit 1-0
Unimplemented: Read as ‘0’
Note:
The UxSTAT register is a window into a 4-byte FIFO maintained by the USB module. UxSTAT value is only
valid when the TRNIF bit (UxIR) is active. Clearing the TRNIF bit advances the FIFO. Data in register
is invalid when the TRNIF bit = 0.
2016-2021 Microchip Technology Inc.
DS60001402H-page 233
PIC32MK GP/MC Family
REGISTER 12-11: UxCON: USB CONTROL REGISTER (‘x’ = 1 AND 2)
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6
31:24
23:16
15:8
7:0
U-0
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-x
R-x
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
JSTATE
SE0
PKTDIS(4)
USBRST(5) HOSTEN(2) RESUME(3)
TOKBUSY(1,5)
PPBRST
USBEN(4)
SOFEN(5)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
JSTATE: Live Differential Receiver JSTATE flag bit
1 = JSTATE detected on the USB
0 = No JSTATE detected
bit 6
SE0: Live Single-Ended Zero flag bit
1 = Single Ended Zero detected on the USB
0 = No Single Ended Zero detected
bit 5
PKTDIS: Packet Transfer Disable bit(4)
1 = Token and packet processing disabled (set upon SETUP token received)
0 = Token and packet processing enabled
TOKBUSY: Token Busy Indicator bit(1,5)
1 = Token being executed by the USB module
0 = No token being executed
bit 4
USBRST: Module Reset bit(5)
1 = USB reset is generated
0 = USB reset is terminated
bit 3
HOSTEN: Host Mode Enable bit(2)
1 = USB host capability is enabled
0 = USB host capability is disabled
bit 2
RESUME: RESUME Signaling Enable bit(3)
1 = RESUME signaling is activated
0 = RESUME signaling is disabled
Note 1:
2:
3:
4:
5:
Software is required to check this bit before issuing another token command to the UxTOK register (see
Register 12-15).
All host control logic is reset any time that the value of this bit is toggled.
Software must set the RESUME bit for 10 ms if the part is a function, or for 25 ms if the part is a host, and
then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to
the RESUME signaling when this bit is cleared.
Device mode.
Host mode.
DS60001402H-page 234
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 12-11: UxCON: USB CONTROL REGISTER (‘x’ = 1 AND 2) (CONTINUED)
bit 1
PPBRST: Ping-Pong Buffers Reset bit
1 = Reset all Even/Odd buffer pointers to the EVEN BD banks
0 = Even/Odd buffer pointers not being Reset
bit 0
USBEN: USB Module Enable bit(4)
1 = USB module and supporting circuitry is enabled
0 = USB module and supporting circuitry is disabled
SOFEN: SOF Enable bit(5)
1 = SOF token sent every 1 ms
0 = SOF token disabled
Note 1:
2:
3:
4:
5:
Software is required to check this bit before issuing another token command to the UxTOK register (see
Register 12-15).
All host control logic is reset any time that the value of this bit is toggled.
Software must set the RESUME bit for 10 ms if the part is a function, or for 25 ms if the part is a host, and
then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to
the RESUME signaling when this bit is cleared.
Device mode.
Host mode.
2016-2021 Microchip Technology Inc.
DS60001402H-page 235
PIC32MK GP/MC Family
REGISTER 12-12: UxADDR: USB ADDRESS REGISTER (‘x’ = 1 AND 2)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LSPDEN
DEVADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
LSPDEN: Low Speed Enable Indicator bit
1 = Next token command to be executed at Low Speed
0 = Next token command to be executed at Full Speed
bit 6-0
DEVADDR: 7-bit USB Device Address bits
REGISTER 12-13: UxFRML: USB FRAME NUMBER LOW REGISTER (‘x’ = 1 AND 2)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FRML
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0
FRML: The 11-bit Frame Number Lower bits
The register bits are updated with the current frame number whenever a SOF TOKEN is received.
DS60001402H-page 236
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 12-14: UxFRMH: USB FRAME NUMBER HIGH REGISTER (‘x’ = 1 AND 2)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
—
—
—
—
—
FRMH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-3 Unimplemented: Read as ‘0’
bit 2-0
FRMH: The Upper 3 bits of the Frame Numbers bits
The register bits are updated with the current frame number whenever a SOF TOKEN is received.
REGISTER 12-15: UxTOK: USB TOKEN REGISTER (‘x’ = 1 AND 2)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PID(1)
EP
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-4
PID: Token Type Indicator bits(1)
0001 = OUT (TX) token type transaction
1001 = IN (RX) token type transaction
1101 = SETUP (TX) token type transaction
Note: All other values are reserved and must not be used.
bit 3-0
EP: Token Command Endpoint Address bits
The four bit value must specify a valid endpoint.
Note 1:
All other values are reserved and must not be used.
2016-2021 Microchip Technology Inc.
DS60001402H-page 237
PIC32MK GP/MC Family
REGISTER 12-16: UxSOF: USB SOF THRESHOLD REGISTER (‘x’ = 1 AND 2)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0
CNT: SOF Threshold Value bits
Typical values of the threshold are:
01001010 = 64-byte packet
00101010 = 32-byte packet
00011010 = 16-byte packet
00010010 = 8-byte packet
REGISTER 12-17: UxBDTP1: USB BDT PAGE 1 REGISTER (‘x’ = 1 AND 2)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
BDTPTRL
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-1
BDTPTRL: BDT Base Address bits
This 7-bit value provides address bits 15 through 9 of the BDT base address, which defines the starting
location of the BDT in system memory.
The 32-bit BDT base address is 512-byte aligned.
bit 0
Unimplemented: Read as ‘0’
DS60001402H-page 238
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 12-18: UxBDTP2: USB BDT PAGE 2 REGISTER (‘x’ = 1 AND 2)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BDTPTRH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0
BDTPTRH: BDT Base Address bits
This 8-bit value provides address bits 23 through 16 of the BDT base address, which defines the starting
location of the BDT in system memory.
The 32-bit BDT base address is 512-byte aligned.
REGISTER 12-19: UxBDTP3: USB BDT PAGE 3 REGISTER (‘x’ = 1 AND 2)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BDTPTRU
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8
Unimplemented: Read as ‘0’
bit 7-0
BDTPTRU: BDT Base Address bits
This 8-bit value provides address bits 31 through 24 of the BDT base address, defines the starting location
of the BDT in system memory.
The 32-bit BDT base address is 512-byte aligned.
2016-2021 Microchip Technology Inc.
DS60001402H-page 239
PIC32MK GP/MC Family
REGISTER 12-20: UxCNFG1: USB CONFIGURATION 1 REGISTER (‘x’ = 1 AND 2)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
UTEYE
UOEMON
—
USBSIDL
LSDEV
—
—
UASUSPND
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8
Unimplemented: Read as ‘0’
bit 7
UTEYE: USB Eye-Pattern Test Enable bit
1 = Eye-Pattern Test is enabled
0 = Eye-Pattern Test is disabled
bit 6
UOEMON: USB OE Monitor Enable bit
1 = OE signal is active; it indicates intervals during which the D+/D- lines are driving
0 = OE signal is inactive
bit 5
Unimplemented: Read as ‘0’
bit 4
USBSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 3
LSDEV: Low-Speed Device Enable bit
1 = USB module to operate in Low-Speed Device mode
0 = USB module to operate in OTG, Host, or Full-Speed Device mode
bit 2-1
Unimplemented: Read as ‘0’
bit 0
UASUSPND: Automatic Suspend Enable bit
1 = USB module automatically suspends upon entry to Sleep mode. See the USUSPEND bit
(UxPWRC) in Register 12-5.
0 = USB module does not automatically suspend upon entry to Sleep mode. Software must use the
USUSPEND bit (UxPWRC) to suspend the module, including the USB 48 MHz clock
DS60001402H-page 240
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 12-21: UxEP0-UxEP15: USB ENDPOINT CONTROL REGISTER (‘x’ = 1 AND 2)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LSPD
RETRYDIS
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
LSPD: Low-Speed Direct Connection Enable bit (Host mode and UxEP0 only)
1 = Direct connection to a low-speed device is enabled
0 = Direct connection to a low-speed device is disabled; hub required with PRE_PID
bit 6
RETRYDIS: Retry Disable bit (Host mode and UxEP0 only)
1 = Retry NAKed transactions is disabled
0 = Retry NAKed transactions is enabled; retry done in hardware
bit 5
Unimplemented: Read as ‘0’
bit 4
EPCONDIS: Bidirectional Endpoint Control bit
If EPTXEN = 1 and EPRXEN = 1:
1 = Disable Endpoint n from Control transfers; only TX and RX transfers allowed
0 = Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
Otherwise, this bit is ignored.
bit 3
EPRXEN: Endpoint Receive Enable bit
1 = Endpoint n receive is enabled
0 = Endpoint n receive is disabled
bit 2
EPTXEN: Endpoint Transmit Enable bit
1 = Endpoint n transmit is enabled
0 = Endpoint n transmit is disabled
bit 1
EPSTALL: Endpoint Stall Status bit
1 = Endpoint n was stalled
0 = Endpoint n was not stalled
bit 0
EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint Handshake is enabled
0 = Endpoint Handshake is disabled (typically used for isochronous endpoints)
2016-2021 Microchip Technology Inc.
DS60001402H-page 241
PIC32MK GP/MC Family
13.0
I/O PORTS
Note:
with alternate function(s). These functions depend on
which peripheral features are on the device. In general,
when a peripheral is functioning, that pin may not be
used as a general purpose I/O pin.
This data sheet summarizes the features
of the PIC32MK GP/MC Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS60001120), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The following are key features of the I/O ports:
• Individual output pin open-drain enable/disable
• Individual input pin weak pull-up and pull-down
• Monitor selective inputs and generate interrupt
when change in pin state is detected
• Operation during Sleep mode and Idle mode
• Fast bit manipulation using CLR, SET, and INV
registers
Figure 13-1 illustrates a block diagram of a typical
multiplexed I/O port.
General purpose I/O pins are the simplest of
peripherals. They allow the PIC32MK GP/MC family
device to monitor and control other devices. To add
flexibility and functionality, some pins are multiplexed
FIGURE 13-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Peripheral Module
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
Port Control
PIO Module
RD ODC
PBCLK4
Data Bus
PBCLK4
D
Q
ODC
CK
EN Q
WR ODC
1
RD TRIS
0
0
I/O Cell
1
D
Q
1
TRIS
CK
EN Q
WR TRIS
Output Multiplexers
D
WR LAT
WR PORT
0
Q
I/O Pin
LAT
CK
EN Q
RD LAT
1
RD PORT
0
Sleep
Q
Q
D
CK
Q
Q
D
CK
PBCLK4
Synchronization
Peripheral Input
Legend:
Note:
R
Peripheral Input Buffer
R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure
for any specific port/peripheral combination may be different than it is shown here.
DS60001402H-page 242
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
13.1
Parallel I/O (PIO) Ports
All port pins have ten registers directly associated with
their operation as digital I/O. The data direction register
(TRISx) determines whether the pin is an input or an
output. If the data direction bit is a ‘1’, then the pin is an
input. All port pins are defined as inputs after a Reset.
Reads from the latch (LATx) read the latch. Writes to
the latch write the latch. Reads from the port (PORTx)
read the port pins, while writes to the port pins write the
latch.
13.1.1
OPEN-DRAIN CONFIGURATION
In addition to the PORTx, LATx, and TRISx registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of outputs
higher than VDD (e.g., 5V) on any desired 5V-tolerant
pins by using external pull-up resistors. The maximum
open-drain voltage allowed is the same as the
maximum VIH specification.
Refer to the pin name tables (Table 3 and Table 5) for
the available pins and their functionality.
13.1.2
CONFIGURING ANALOG AND
DIGITAL PORT PINS
The ANSELx register controls the operation of the
analog port pins. The port pins that are to function as
analog inputs must have their corresponding ANSEL
and TRIS bits set. In order to use port pins for I/O
functionality with digital modules, such as Timers,
UARTs, etc., the corresponding ANSELx bit must be
cleared.
The ANSELx register has a default value of 0xFFFF;
therefore, all pins that share analog functions are
analog (not digital) by default.
If the TRIS bit is cleared (output) while the ANSELx bit
is set, the digital output level (VOH or VOL) is converted
by an analog peripheral, such as the ADC module or
Comparator module.
When the PORT register is read, all pins configured as
analog input channels are read as cleared (a low level).
Pins configured as digital inputs do not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
2016-2021 Microchip Technology Inc.
13.1.3
I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be an NOP.
13.1.4
INPUT CHANGE NOTIFICATION
The input change notification function of the I/O ports
allows the PIC32MK GP/MC devices to generate
interrupt requests to the processor in response to a
change-of-state on selected input pins. This feature can
detect input change-of-states even in Sleep mode,
when the clocks are disabled. Every I/O port pin can be
selected (enabled) for generating an interrupt request
on a change-of-state.
Five control registers are associated with the CN functionality of each I/O port. The CNENx and CNNEx registers contain the CN interrupt enable control bits for
each of the input pins. Setting these bits enables a CN
interrupt for the corresponding pins. The CNENx register enables a mismatch CN interrupt condition when
the EDGEDETECT bit (CNCONx) is not set.
When the EDGEDETECT bit is set, the CNNEx register
controls the negative edge while the CNENx register
controls the positive edge.
The CNSTATx and CNFx registers indicate the status
of change notice based on the setting of the
EDGEDETECT bit. If the EDGEDETECT bit is set to
‘0’, the CNSTATx register indicates whether a change
occurred on the corresponding pin since the last read
of the PORTx bit. If the EDGEDETECT bit is set to ‘1’,
the CNFx register indicates whether a change has
occurred and through the CNNEx and CNENx registers
the edge type of the change that occurred is also
indicated.
Each I/O pin also has a weak pull-up and a weak
pull-down connected to it. The pull-ups act as a
current source or sink source connected to the pin,
and eliminate the need for external resistors when
push-button or keypad devices are connected. The
pull-ups and pull-downs are enabled separately using
the CNPUx and the CNPDx registers, which contain
the control bits for each of the pins. Setting any of
the control bits enables the weak pull-ups and/or
pull-downs for the corresponding pins.
Note:
Pull-ups and pull-downs on change
notification pins should always be
disabled when the port pin is configured as
a digital output.
An additional control register (CNCONx) is shown in
Register 13-3.
DS60001402H-page 243
PIC32MK GP/MC Family
13.2
CLR, SET, and INV Registers
Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
13.3
Peripheral Pin Select (PPS)
A major challenge in general purpose devices is providing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. The challenge is even greater on low pin-count devices. In an
application where more than one peripheral needs to
be assigned to a single pin, inconvenient workarounds
in application code or a complete redesign may be the
only option.
PPS configuration provides an alternative to these
choices by enabling peripheral set selection and their
placement on a wide range of I/O pins. By increasing
the pinout options available on a particular device,
users can better tailor the device to their entire
application, rather than trimming the application to fit
the device.
The PPS configuration feature operates over a fixed
subset of digital I/O pins. Users may independently
map the input and/or output of most digital peripherals
to these I/O pins. PPS is performed in software and
generally does not require the device to be
reprogrammed. Hardware safeguards are included that
prevent accidental or spurious changes to the peripheral mapping once it has been established.
13.3.1
AVAILABLE PINS
The number of available pins is dependent on the
particular device and its pin count. Pins that support the
PPS feature include the designation “RPn” in their full
pin designation, where “RP” designates a remappable
peripheral and “n” is the remappable port number.
13.3.2
AVAILABLE PERIPHERALS
The peripherals managed by the PPS are all digitalonly peripherals. These include general serial
communications (UART, SPI, and CAN), general purpose timer clock inputs, timer-related peripherals (input
capture and output compare), interrupt-on-change
inputs, and reference clocks (input and output).
In comparison, some digital-only peripheral modules
are never included in the PPS feature. This is because
the peripheral’s function requires special I/O circuitry
on a specific port and cannot be easily connected to
multiple pins. A similar requirement excludes all
modules with analog inputs, such as the Analog-toDigital Converter (ADC).
A key difference between remappable and non-remappable peripherals is that remappable peripherals are
not associated with a default I/O pin. The peripheral
must always be assigned to a specific I/O pin before it
can be used. In contrast, non-remappable peripherals
are always available on a default pin, assuming that the
peripheral is active and not conflicting with another
peripheral.
When a remappable peripheral is active on a given I/O
pin, it takes priority over all other digital I/O and digital
communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
is mapped. Remappable peripherals never take priority
over any analog functions associated with the pin.
13.3.3
CONTROLLING PPS
PPS features are controlled through two sets of SFRs:
one to map peripheral inputs, and one to map outputs.
Because they are separately controlled, a particular
peripheral’s input and output (if the peripheral has both)
can be placed on any selectable function pin without
constraint.
The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on
whether an input or output is being mapped.
13.3.4
INPUT MAPPING
The inputs of the PPS options are mapped on the basis
of the peripheral. That is, a control register associated
with a peripheral dictates the pin it will be mapped to.
The [pin name]R registers, where [pin name] refers to
the peripheral pins listed in Table 13-1, are used to configure peripheral input mapping (see Register 13-1).
Each register contains sets of 4 bit fields. Programming
these bit fields with an appropriate value maps the RPn
pin with the corresponding value to that peripheral. For
any given device, the valid range of values for any bit
field is shown in Table 13-1.
Figure 13-2 illustrates the remappable pin selection for
the U1RX input.
DS60001402H-page 244
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
FIGURE 13-2:
REMAPPABLE INPUT
EXAMPLE FOR U1RX
U1RXR
0
RPD2
1
RPG8
2
RPF4
U1RX input
to peripheral
n
RPn
Note:
For input only, PPS functionality does not
have priority over TRISx settings. Therefore,
when configuring RPn pin for input, the
corresponding bit in the TRISx register must
also be configured for input (set to ‘1’).
2016-2021 Microchip Technology Inc.
DS60001402H-page 245
PIC32MK GP/MC Family
TABLE 13-1:
INPUT PIN SELECTION
Peripheral Pin
Note 1:
[pin name]R SFR
[pin name]R bits
INT4
INT4R
INT4R
T2CK
T2CKR
T2CKR
T6CK
T6CKR
T6CKR
IC4
IC4R
IC4R
IC7
IC7R
IC7R
IC12
IC12R
IC12R
[pin name]R Value to
RPn Pin Selection
0000 = RPA0
0001 = RPB3
0010 = RPB4
0011 = RPB15
IC15
IC15R
IC15R
U3RX
U3RXR
U3RXR
U4CTS
U4CTSR
U4CTSR
0101 = RPC7
U6RX
U6RXR
U6RXR
0110 = RPC0
SDI1
SDI1R
SDI1R
SDI3
SDI3R
SDI3R
0111 = Reserved
SCK4
SCK4R
SCK4R
SDI5
SDI5R
SDI5R
1000 = RPA11
SS6
SS6R
SS6R
QEA1
QEA1R
QEA1R
HOME2
HOME2R
HOME2R
QAEA3
QAEA3R
QEA3R
HOME4
HOME4R
HOME4R
QEA5
QEA5R
QEA5R
HOME6
HOME6R
HOME6R
FLT1
FLT1R
FLT1R
C3RX
C3RXR
C3RXR
REFCLKI
REFIR
REFIR
0100 = RPB7
1001 = RPD5
1010 = RPG6
1011 = RPF1
1100 = RPE0(1)
1101 = RPA15(1)
1110 = Reserved
1111 = Reserved
This selection is not available on 64-pin devices.
DS60001402H-page 246
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 13-1:
INPUT PIN SELECTION (CONTINUED)
Peripheral Pin
Note 1:
[pin name]R SFR
[pin name]R bits
[pin name]R Value to
RPn Pin Selection
INT3
INT3R
INT3R
0000 = RPA1
T3CK
T3CKR
T3CKR
T7CK
T7CKR
T7CKR
0001 = RPB5
IC3
IC3R
IC3R
IC8
IC8R
IC8R
0011 = RPB11
IC11
IC11R
IC11R
0100 = RPB8
IC16
IC16R
IC16R
U1CTS
U1CTSR
U1CTSR
0101 = RPA8
U2RX
U2RXR
U2RXR
U5CTS
U5CTSR
U5CTSR
0111 = RPB12
SDI2
SDI2R
SDI2R
1000 = RPA12
SDI4
SDI4R
SDI4R
SCK6
SCK6R
SCK6R
1001 = RPD6
QEB1
QEB1R
QEB1R
INDX2
INDX2R
INDX2R
1011 = RPG0(1)
QEB3
QEB3R
QEB3R
1100 = RPE1(1)
INDX4
INDX4R
INDX4R
QEB5
QEB5R
QEB5R
1101 = RPA14(1)
INDX6
INDX6R
INDX6R
C2RX
C2RXR
C2RXR
FLT2
FLT2R
FLT2R
0010 = RPB1
0110 = RPC8
1010 = RPG7
1110 = Reserved
1111 = Reserved
This selection is not available on 64-pin devices.
2016-2021 Microchip Technology Inc.
DS60001402H-page 247
PIC32MK GP/MC Family
TABLE 13-1:
INPUT PIN SELECTION (CONTINUED)
Peripheral Pin
Note 1:
[pin name]R SFR
[pin name]R bits
[pin name]R Value to
RPn Pin Selection
INT2
INT2R
INT2R
T4CK
T4CKR
T4CKR
0000 = RPB6
T8CK
T8CKR
T8CKR
IC1
IC1R
IC1R
0010 = RPA4
IC5
IC5R
IC5R
0011 = RPB13
IC9
IC9R
IC9R
IC13
IC13R
IC13R
U1RX
U1RXR
U1RXR
U2CTS
U2CTSR
U2CTSR
U5RX
U5RXR
U5RXR
SS1
SS1R
SS1R
0111 = RPA7
SS3
SS3R
SS3R
1000 = RPE14
SS4
SS4R
SS4R
SS5
SS5R
SS5R
INDX1
INDX1R
INDX1R
QEB2
QEB2R
QEB2R
INDX3
INDX3R
INDX3R
QEB4
QEB4R
QEB4R
1100 = RPF0
INDX5
INDX5R
INDXR5
1101 = RPD4(1)
QEB6
QEB6R
QEB6R
C1RX
C1RXR
C1RXR
OCFB
OCFBR
OCFBR
0001 = RPC15
0100 = RPB2
0101 = RPC6
0110 = RPC1
1001 = RPC13
1010 = RPG8
1011 = Reserved
1110 = Reserved
1111 = Reserved
This selection is not available on 64-pin devices.
DS60001402H-page 248
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 13-1:
INPUT PIN SELECTION (CONTINUED)
Peripheral Pin
Note 1:
[pin name]R SFR
[pin name]R bits
[pin name]R Value to
RPn Pin Selection
INT1
INT1R
INT1R
T5CK
T5CKR
T5CKR
T9CK
T9CKR
T9CKR
IC2
IC2R
IC2R
0010 = RPB0
0011 = RPB10
IC6
IC6R
IC6R
IC10
IC10R
IC10R
IC14
IC14R
IC14R
U3CTS
U3CTSR
U3CTSR
0000 = RPB14
0001 = RPC12
0100 = RPB9
0101 = RPC9
U4RX
U4RXR
U4RXR
U6CTS
U6CTSR
U6CTSR
SS2
SS2R
SS2R
SCK3
SCK3R
SCK3R
SCK5
SCK5R
SCK5R
SDI6
SDI6R
SDI6R
HOME1
HOME1R
HOME1R
QEA2
QEA2R
QEA2R
HOME3
HOME3R
HOME3R
QEA4
QEA4R
QEA4R
1100 = RPG1(1)
HOME5
HOME5R
HOME5R
1101 = RPD3(1)
QEA6
QEA6R
QEA6R
C4RX
C4RXR
C4RXR
OCFA
OCFAR
OCFAR
0110 = RPC2
0111 = Reserved
1000 = RPE15
1001 = RPC10
1010 = RPG9
1011 = RPG12(1)
1110 = Reserved
1111 = Reserved
This selection is not available on 64-pin devices.
2016-2021 Microchip Technology Inc.
DS60001402H-page 249
PIC32MK GP/MC Family
13.3.5
OUTPUT MAPPING
13.3.6.1
In contrast to inputs, the outputs of the PPS options
are mapped on the basis of the pin. In this case, a
control register associated with a particular pin
dictates the peripheral output to be mapped. The
RPnR registers (Register 13-2) are used to control
output mapping. Like the [pin name]R registers, each
register contains sets of 4 bit fields. The value of the
bit field corresponds to one of the peripherals, and
that peripheral’s output is mapped to the pin (see
Table 13-2 and Figure 13-3).
A null output is associated with the output register reset
value of ‘0’. This is done to ensure that remappable
outputs remain disconnected from all output pins by
default.
FIGURE 13-3:
EXAMPLE OF
MULTIPLEXING OF
REMAPPABLE OUTPUT
FOR RPF0
RPF0R
Default
U1TX Output
U2RTS Output
0
1
2
RPF0
Output Data
Control Register Lock
Under normal operation, writes to the RPnR and [pin
name]R registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these
registers, they must be unlocked in hardware. The
register lock is controlled by the IOLOCK
Configuration bit (CFGCON). Setting the
IOLOCK bit prevents writes to the control registers
and clearing the IOLOCK bit allows writes.
To set or clear the IOLOCK bit, an unlock sequence
must be executed. Refer to the Section 42. “Oscillators with Enhanced PLL” (DS60001250) in the
“PIC32 Family Reference Manual” for details.
13.3.6.2
Configuration Bit Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPnR and [pin name]R registers. The IOL1WAY
Configuration bit (DEVCFG3) blocks the IOLOCK
bit from being cleared after it has been set once. If the
IOLOCK bit remains set, the register unlock procedure
does not execute, and the PPS control registers cannot
be written to. The only way to clear the bit and reenable peripheral remapping is to perform a device
Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session.
14
REFCLKO1
13.3.6
15
CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. The PIC32MK GP/MC devices include two
features to prevent alterations to the peripheral map:
• Control register lock sequence
• Configuration bit select lock
DS60001402H-page 250
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 13-2:
OUTPUT PIN SELECTION
RPn Port Pin
RPnR SFR
RPnR bits
RPA0
RPA0R
RPA0R
RPB3
RPB3R
RPB3R
RPB4
RPB4R
RPB4R
RPB15
RPB15R
RPB15R
RPB7
RPB7R
RPB7R
RPC7
RPC7R
RPC7R
RPC0
RPC0R
RPC0R
RPA11
RPA11R
RPA11R
RPD5
RPD5R
RPD5R
RPG6
RPG6R
RPG6R
RPF1
RPF1R
RPF1R
RPE0(1)
RPE0R(1)
RPE0R (1)
RPA15(1)
RPA15R(1)
RPA15R (1)
RPnR Value to Peripheral
Selection
00000 = Off
00001 = U1TX
00010 = U2RTS
00011 = SDO1
00100 = SDO2
00101 = OCI
00110 = OC7
00111 = C2OUT
01000 = C4OUT
01001 = OC13
01010 = Reserved
01011 = U5RTS
01100 = C1TX
01101 = Reserved
01110 = SDO3
01111 = SCK4
10000 = SDO5
10001 = SS6
10010 = REFCLKO4
10011 = Reserved
10100 = QEICMP1
10101 = QEICMP5
10110 = Reserved
•
•
•
11111 = Reserved
Note 1:
This selection is not available on 64-pin devices.
2016-2021 Microchip Technology Inc.
DS60001402H-page 251
PIC32MK GP/MC Family
TABLE 13-2:
OUTPUT PIN SELECTION (CONTINUED)
RPn Port Pin
RPnR SFR
RPnR bits
RPA1
RPA1R
RPA1R
RPB5
RPB5R
RPB5R
RPB1
RPB1R
RPB1R
RPB11
RPB11R
RPB11R
RPA8
RPA8R
RPA8R
RPC8
RPC8R
RPC8R
RPB12
RPB12R
RPB12R
RPA12
RPA12R
RPA12R
RPD6
RPD6R
RPD6R
RPG7
RPG7R
RPG7R
RPG0(1)
RPG0R(1)
RPG0R (1)
RPE1(1)
RPE1R(1)
RPE1R (1)
RPA14(1)
RPA14R(1)
RPA14R (1)
Note 1:
RPnR Value to Peripheral
Selection
00000 = Off
00001 = U3RTS
00010 = U4TX
00011 = SDO1
00100 = SDO2
00101 = OC2
00110 = OC8
00111 = C3OUT
01000 = OC9
01001 = OC12
01010 = OC16
01011 = U6RTS
01100 = C4TX
01101 = Reserved
01110 = SDO3
01111 = SDO4
10000 = SDO5
10001 = SCK6
10010 = REFCLKO3
10011 = Reserved
10100 = QEICMP2
10101 = QEICMP6
10110 = Reserved
•
•
•
11111 = Reserved
This selection is not available on 64-pin devices.
DS60001402H-page 252
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
TABLE 13-2:
OUTPUT PIN SELECTION (CONTINUED)
RPn Port Pin
RPnR SFR
RPnR bits
RPB6
RPB6R
RPB6R
RPC15
RPC15R
RPC15R
RPA4
RPA4R
RPA4R
RPB13
RPB13R
RPB13R
RPB2
RPB2R
RPB2R
RPC6
RPC6R
RPC6R
RPC1
RPC1R
RPC1R
RPA7
RPA7R
RPA7R
RPE14
RPE14R
RPE14R
RPG8
RPG8R
RPG8R
RPF0
RPF0R
RPF0R
RPnR Value to Peripheral
Selection
00000 = Off
00001 = U3TX
00010 = U4RTS
00011 = SS1
00100 = Reserved
00101 = OC4
00110 = OC5
00111 = REFCLKO1
01000 = C5OUT
01001 = OC10
01010 = OC14
01011 = U6TX
01100 = C3TX
01101 = Reserved
01110 = SS3
01111 = SS4
10000 = SS5
10001 = SDO6
10010 = REFCLKO2
10011 = Reserved
10100 = QEICMP3
10101 = Reserved
•
RPD4(1)
RPD4R(1)
RPD4R (1)
•
•
11111 = Reserved
Note 1:
This selection is not available on 64-pin devices.
2016-2021 Microchip Technology Inc.
DS60001402H-page 253
PIC32MK GP/MC Family
TABLE 13-2:
OUTPUT PIN SELECTION (CONTINUED)
RPnR Value to Peripheral
Selection
RPn Port Pin
RPnR SFR
RPnR bits
RPB14
RPB14R
RPB14R
RPC12
RPC12R
RPC12R
RPB0
RPB0R
RPB0R
RPB10
RPB10R
RPB10R
RPB9
RPB9R
RPB9R
RPC9
RPC9R
RPC9R
RPC2
RPC2R
RPC2R
RPE15
RPE15R
RPE15R
RPC10
RPC10R
RPC10R
RPG9
RPG9R
RPG9R
RPG12(1)
RPG12R(1)
RPG12R
RPG1(1)
RPG1R(1)
RPG1R (1)
RPD3(1)
RPD3R(1)
(1)
00000 = Off
00001 = U1RTS
00010 = U2TX
00011 = Reserved
00100 = SS2
00101 = OC3
00110 = OC6
00111 = C1OUT
01000 = Reserved
01001 = OC11
01010 = OC15
01011 = U5TX
01100 = C2TX
01101 = Reserved
01110 = SCK3
01111 = SDO4
10000 = SCK5
10001 = SDO6
10010 = CTPLS
10011 = Reserved
10100 = QEICMP4
10101 = Reserved
•
•
Note 1:
RPD3R
•
11111 = Reserved
This selection is not available on 64-pin devices.
DS60001402H-page 254
2016-2021 Microchip Technology Inc.
I/O Ports Control Registers
Virtual Address
(BF86_#)
Register
Name(1)
TABLE 13-3:
0000
ANSELA
0010
0020
0030
0040
TRISA
PORTA
LATA
ODCA
CNPUA
0060
CNPDA
0070 CNCONA
CNENA
2016-2021 Microchip Technology Inc.
00A0
CNNEA
00B0
CNFA
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ANSA15
ANSA14
—
ANSA12
ANSA11
—
—
ANSA8
—
—
—
ANSA4
—
—
ANSA1
ANSA0
D813
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
TRISA10
—
TRISA8
TRISA7
—
—
TRISA4
—
—
TRISA1
TRISA0
DD93
15:0
TRISA15 TRISA14
—
TRISA12 TRISA11
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RA15
RA14
—
RA12
RA11
RA10
—
RA8
RA7
—
—
RA4
—
—
RA1
RA0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATA15
LATA14
—
LATA12
LATA11
LATA10
—
LATA8
LATA7
—
—
LATA4
—
—
LATA1
LATA0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
ODCA10
—
ODCA8
ODCA7
—
—
ODCA4
—
—
ODCA1
ODCA0
0000
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
CNPUA4
—
—
—
—
—
—
—
—
—
CNPDA4
—
—
15:0
31:16
ODCA15 ODCA14
—
—
—
—
15:0 CNPUA15 CNPUA14
—
31:16
—
—
—
15:0 CNPDA15 CNPDA14
—
ODCA12 ODCA11
—
—
CNPUA12 CNPUA11 CNPUA10
—
—
—
CNPDA12 CNPDA11 CNPDA10
—
—
—
CNPUA8 CNPUA7
—
—
CNPDA8 CNPDA7
CNPUA1 CNPUA0 0000
—
—
0000
CNPDA1 CNPDA0 0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
SIDL
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
0000
31:16
15:0
31:16
0090 CNSTATA
31/15
All
Resets
Bit Range
Bits
0050
0080
PORTA REGISTER MAP FOR 100-PIN DEVICES ONLY
15:0
31:16
CNIEA15 CNIEA14
—
—
CN
CN
STATA15 STATA14
—
—
—
—
—
—
CNIEA12 CNIEA11
—
—
CN
CN
STATA12 STATA11
—
—
—
—
—
—
—
—
—
—
—
—
CNIEA10
—
CNIEA8
CNIEA7
—
—
CNIEA4
—
—
CNIEA1
—
—
—
—
—
—
—
—
—
—
CN
STATA10
—
CN
STATA8
CN
STATA7
—
—
CN
STATA4
—
—
CN
STATA1
—
—
—
—
—
—
—
—
—
—
—
CNNEA4
—
—
CNNEA8 CNNEA7
—
0000
—
0000
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNFA15
CNFA14
—
CNFA12
CNFA11
CNFA10
—
CNFA8
CNFA7
—
—
CNFA4
—
—
CNFA1
CNFA0
0000
00C0 SRCON0A 31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
SR0A10
—
SR0A8
SR0A7
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
Legend:
Note 1:
—
—
CN
0000
STATA0
15:0 CNNEA15 CNNEA14
00D0 SRCON1A
CNNEA12 CNNEA11 CNNEA10
CNIEA0 0000
CNNEA1 CNNEA0 0000
0000
15:0
—
—
—
—
—
SR1A10
—
SR1A8
SR1A7
—
—
—
—
—
—
—
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
DS60001402H-page 255
13.4
ANSELA
0010
0020
0030
0040
TRISA
PORTA
LATA
ODCA
0050
CNPUA
0060
CNPDA
0080
CNENA
0090 CNSTATA
00A0
CNNEA
00B0
CNFA
DS60001402H-page 256
00C0 SRCON0A
00D0 SRCON1A
Legend:
Note 1:
31/15
30/14
29/13
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
—
15:0
—
—
—
31:16
—
—
—
—
15:0
—
—
—
31:16
—
—
15:0
—
31:16
0623
0000
—
TRISA1
TRISA0
06FF
—
—
—
—
0000
RA4
—
—
RA1
RA0
xxxx
—
—
—
—
—
—
0000
—
—
LATA4
—
—
LATA1
LATA0
xxxx
—
—
—
—
—
—
—
—
0000
ODCA8
ODCA7
—
—
ODCA4
—
—
ODCA1
ODCA0
0000
—
—
—
—
—
—
—
—
—
0000
—
—
CNPUA4
—
—
—
—
—
—
—
—
—
CNPDA4
—
—
—
—
—
—
—
TRISA10
—
TRISA8
—
—
—
RA12
RA11
RA10
—
—
—
—
—
LATA12
—
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
ANSA8
—
—
0000
—
—
15:0
—
ANSA11
—
—
31:16
—
ANSA12
ANSA0
21/5
SIDL
25/9
—
22/6
—
26/10
ANSA1
23/7
ON
27/11
16/0
24/8
15:0
28/12
20/4
19/3
18/2
—
—
—
—
—
ANSA4
—
—
—
—
—
—
—
TRISA7
—
—
TRISA4
—
—
—
—
—
—
—
RA8
RA7
—
—
—
—
—
—
—
LATA11
LATA10
—
LATA8
LATA7
—
—
—
—
ODCA10
—
—
—
TRISA12 TRISA11
ODCA12 ODCA11
—
—
CNPUA12 CNPUA11 CNPUA10
—
—
—
CNPDA12 CNPDA11 CNPDA10
—
—
—
CNPUA8 CNPUA7
—
—
CNPDA8 CNPDA7
17/1
CNPUA1 CNPUA0 0000
—
—
0000
CNPDA1 CNPDA0 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
0000
CNIEA12 CNIEA11
—
—
CN
CN
STATA12 STATA11
—
—
—
—
—
—
—
—
—
—
CNIEA10
—
CNIEA8
CNIEA7
—
—
CNIEA4
—
—
CNIEA1
—
—
—
—
—
—
—
CN
STATA4
—
—
CN
STATA1
—
—
—
CN
STATA10
—
CN
STATA8
CN
STATA7
—
—
—
—
—
—
—
—
—
—
—
—
—
CNNEA4
—
—
CNIEA0 0000
—
0000
CN
0000
STATA0
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
CNFA12
CNFA11
CNFA10
—
CNFA8
CNFA7
—
—
CNFA4
—
—
CNFA1
CNFA0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
SR0A10
—
SR0A8
SR0A7
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
SR1A10
—
SR1A8
SR1A7
—
—
—
—
—
—
—
0000
—
—
CNNEA12 CNNEA11 CNNEA10
—
CNNEA8 CNNEA7
—
—
0000
CNNEA1 CNNEA0 0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
0070 CNCONA
Bits
All
Resets
Register
Name(1)
0000
PORTA REGISTER MAP FOR 64-PIN DEVICES ONLY
Bit Range
Virtual Address
(BF86_#)
2016-2021 Microchip Technology Inc.
TABLE 13-4:
TRISB
0120
PORTB
0140
LATB
ODCB
0150
CNPUB
0160
CNPDB
0170 CNCONB
0180
CNENB
0190 CNSTATB
01A0 CNNEB
2016-2021 Microchip Technology Inc.
01B0
CNFB
01C0 SRCON0B
01D0 SRCON1B
Legend:
Note 1:
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
—
—
—
—
15:0
—
—
—
—
—
31:16
—
—
—
—
15:0
TRISB15
TRISB14
TRISB13
31:16
—
—
15:0
RB15
31:16
16/0
All
Resets
0110
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
0100 ANSELB
0130
PORTB REGISTER MAP FOR 64-PIN AND 100-PIN DEVICES
—
—
0000
ANSB1
ANSB0
008F
—
—
0000
TRISB2
TRISB1
TRISB0
FFFF
—
—
—
—
0000
RB4
RB3
RB2
RB1
RB0
xxxx
—
—
—
—
—
—
0000
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx
—
—
—
—
—
—
—
—
0000
—
ODCB7
ODCB6
ODCB5
ODCB4
ODCB3
ODCB2
ODCB1
ODCB0
0000
—
—
—
—
—
—
—
—
—
0000
25/9
24/8
23/7
22/6
21/5
20/4
—
—
—
ANSB9
—
—
TRISB12
TRISB11
—
—
RB14
RB13
—
—
15:0
LATB15
31:16
—
—
—
—
—
—
—
—
ANSB7
—
—
—
ANSB3
ANSB2
—
—
—
—
—
—
—
—
TRISB10
TRISB9
TRISB8
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
—
—
—
—
—
—
—
—
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
—
—
—
—
—
—
—
—
LATB14
LATB13
LATB12
LATB11
LATB10
LATB9
—
LATB7
—
—
—
—
—
—
—
—
15:0
ODCB15
ODCB14
ODCB13
ODCB12
ODCB11
ODCB10
ODCB9
31:16
—
—
—
—
—
—
—
15:0 CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9
—
31:16
—
—
—
—
—
—
—
—
15:0 CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9
—
31:16
15:0
—
ON
—
—
—
SIDL
CNPUB7 CNPUB6 CNPUB5
—
—
—
CNPDB7 CNPDB6 CNPDB5
CNPUB4
—
CNPDB4
19/3
18/2
17/1
CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000
—
—
—
—
0000
CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CNIEB15
CNIEB14
CNIEB13
CNIEB12
CNIEB11
CNIEB10
CNIEB9
—
CNIEB7
CNIEB6
CNIEB5
CNIEB4
CNIEB3
CNIEB2
CNIEB1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CN
STATB15
CN
STATB14
CN
STATB13
CN
STATB12
CN
STATB11
CN
STATB10
CN
STATB9
—
CN
STATB7
CN
STATB6
CN
STATB5
CN
STATB4
CN
STATB3
CN
STATB2
CN
STATB1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNNEB7 CNNEB6 CNNEB5
—
CNNEB4
CNIEB0 0000
—
0000
CN
0000
STATB0
—
0000
15:0 CNNEB15 CNNEB14 CNNEB13 CNNEB12 CNNEB11 CNNEB10 CNNEB9
—
CNNEB3 CNNEB2 CNNEB1 CNNEB0 0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNFB15
CNFB14
CNFB13
CNFB12
CNFB11
CNFB10
CNFB9
—
CNFB7
CNFB6
CNFB5
CNFB4
CNFB3
CNFB2
CNFB1
CNFB0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
SR0B15
SR0B14
SR0B13
SR0B12
SR0B11
SR0B10
—
—
SR0B7
SR0B6
—
SR0B4
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0 SR1B15
SR1B14
SR1B13
SR1B12
SR1B11
SR1B10
—
—
SR1B7
SR1B6
—
SR1B4
—
—
—
—
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
DS60001402H-page 257
TABLE 13-5:
PORTC REGISTER MAP FOR 64-PIN AND 100-PIN DEVICES
0210
TRISC
0220
PORTC
0230
LATC
0240
ODCC
0250
CNPUC
0260
CNPDC
31/15
30/14
29/13
31:16
—
—
—
—
15:0
—
—
—
ANSC12
31:16
—
—
—
—
15:0
TRISC15
TRISC14
TRISC13
TRISC12
CNENC
0290 CNSTATC
02A0
CNNEC
02B0
CNFC
02C0 SRCON0C
02D0 SRCON1C
DS60001402H-page 258
Legend:
Note 1:
18/2
16/0
—
—
0000
ANSC1
ANSC0
1007
—
0000
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
17/1
—
—
—
—
—
—
—
—
—
—
ANSC11
ANSC10
—
—
—
—
—
—
—
ANSC2
—
—
—
—
—
—
—
—
—
—
—
TRISC11
TRISC10
TRIS92
TRISC8
TRISC7
TRISC6
—
—
—
TRISC2
TRISC1
TRISC0 FFC7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RC15
RC14
RC13
RC12
RC11
RC10
RC9
RC8
RC7
RC6
—
—
—
RC2
RC1
RC0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATC15
LATC14
—
LATC12
LATC11
LATC10
LATC9
LATC8
LATC7
LATC6
—
—
—
LATC2
LATC1
LATC0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCC15
ODCC14
—
ODCC12
ODCC11
ODCC10
ODCC9
ODCC8
ODCC7
ODCC6
—
—
—
ODCC2
ODCC1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
15:0
31:16
15:0
CNPUC15 CNPUC14
—
—
CNPDC15 CNPDC14
—
—
—
—
—
—
15:0
ON
—
31:16
—
—
SIDL
15:0
CNIEC15
CNIEC14
—
CNPUC12 CNPUC11 CNPUC10 CNPUC9 CNPUC8 CNPUC7 CNPUC6
—
—
—
—
—
—
—
CNPDC12 CNPDC11 CNPDC10 CNPDC9 CNPDC8 CNPDC7 CNPDC6
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CNIEC12
CNIEC11
CNIEC10
CNIEC9
CNIEC8
CNIEC7
CNIEC7
—
—
—
CNIEC2
CNIEC1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CN
STATC14
—
CN
STATC12
CN
STATC11
CN
STATC10
CN
STATC9
CN
STATC8
CN
STATC7
CN
STATC6
—
—
—
CN
STATC2
CN
STATC1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CN
STATC15
CNNEC15 CNNEC14
0000
CNPDC2 CNPDC1 CNPDC0 0000
15:0
15:0
—
CNPUC2 CNPUC1 CNPUC0 0000
31:16
31:16
ODCC0 0000
CNNEC12 CNNEC11 CNNEC10 CNNEC9 CNNEC8 CNNEC7 CNNEC6
CNIEC0 0000
—
0000
CN
0000
STATC0
—
0000
CNNEC2 CNNEC1 CNNEC0 0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNFC15
CNFC14
—
CNFC12
CNFC11
CNFC10
CNFC9
CNFC8
CNFC7
CNFC6
—
—
—
CNFC2
CNFC1
CNFC0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
SR0C15
—
—
—
SR0C11
—
SR0C9
SR0C8
SR0C7
SR0C6
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
SR1C15
—
—
—
SR1C11
—
SR1C9
SR1C8
SR1C7
SR1C6
—
—
—
—
—
—
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more information.
PIC32MK GP/MC Family
0280
27/11
31:16
31:16
0270 CNCONC
28/12
All
Resets
0200 ANSELC
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF86_#)
2016-2021 Microchip Technology Inc.
TABLE 13-6:
0320
0330
TRISD
PORTD
LATD
0340
ODCD
0350
CNPUD
0360
CNPDD
0370 CNCOND
0380
CNEND
0390 CNSTATD
03A0
2016-2021 Microchip Technology Inc.
03B0
CNNED
CNFD
03C0 SRCON0D
03D0 SRCON1D
Legend:
Note 1:
2:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
0300 ANSELD
0310
PORTD REGISTER MAP FOR 100-PIN DEVICES ONLY
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ANSD15
ANSD14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
TRISD15
TRISD14
TRISD13
TRISD12
—
—
—
TRISD8(2)
—
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
—
F1FE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RD15
RD14
RD13
RD12
—
—
—
RD8(2)
—
RD6
RD5
RD4
RD3
RD2
RD1
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATD15
LATD14
LATD13
LATD12
—
—
—
LATD8(2)
—
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCD15
ODCD14
ODCD13
ODCD12
—
—
—
ODCD8(2)
—
ODCD6
ODCD5
ODCD4
ODCD3
ODCD2
ODCD1
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0 CNPUD15 CNPUD14 CNPUD13 CNPUD12
—
—
—
CNPUD8(2)
—
—
0000
31:16
—
—
—
—
—
—
0000
15:0 CNPDD15 CNPDD14 CNPDD13 CNPDD12
—
—
—
CNPDD8(2)
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
SIDL
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
CNIED8(2)
—
CNIED6
CNIED5
CNIED4
CNIED3
CNIED2
CNIED1
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
0000
CN
STATD5
CN
STATD4
CN
STATD3
CN
STATD2
CN
STATD1
—
0000
—
—
—
—
—
—
0000
—
0000
—
—
31:16
—
—
15:0
CNIED15
CNIED14
31:16
—
—
15:0
CNS
TATD15
CN
STATD14
31:16
—
—
—
—
CNIED13 CNIED12
—
—
CN
CN
STATD13 STATD12
CNPUD6 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1
—
—
—
—
—
—
CNPDD6 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1
—
—
—
CN
STATD8(2)
—
CN
STATD6
—
—
—
—
—
—
15:0 CNNED15 CNNED14 CNNED13 CNNED12
—
—
—
CNNED8(2)
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNFD15
CNFD14
CNFD13
CNFD12
—
—
—
CNFD8(2)
—
CNFD6
CNFD5
CNFD4
CNFD3
CNFD2
CNFD1
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
SR0D6
SR0D5
SR0D4
SR0D3
SR0D2
SR0D1
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
SR0D8
—
(2)
CNNED6 CNNED5 CNNED4 CNNED3 CNNED2 CNNED1
0000
15:0
—
—
—
—
—
—
—
—
SR1D6
SR1D5
SR1D4
SR1D3
SR1D2
SR1D1
—
SR1D8(2)
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more information.
This bit is not available on general purpose devices.
PIC32MK GP/MC Family
DS60001402H-page 259
TABLE 13-7:
Virtual Address
(BF86_#)
Register
Name(1)
0310
TRISD
Bits
PORTD
0330
LATD
0340
ODCD
0350
0360
CNPUD
CNPDD
0370 CNCOND
0380
CNEND
03A0
03B0
CNNED
CNFD
03C0 SRCON0D
03D0 SRCON1D
DS60001402H-page 260
Legend:
Note 1:
2:
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
0000
TRISD6
TRISD5
—
—
—
—
—
0160
—
—
—
—
—
—
—
0000
—
RD6
RD5
—
—
—
—
—
xxxx
—
—
—
—
—
—
—
—
—
0000
—
LATD8(2)
—
LATD6
LATD5
—
—
—
—
—
xxxx
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
ODCD8(2)
—
ODCD6
ODCD5
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
CNPUD8(2)
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
CNPDD8(2)
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
TRISD8(2)
—
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RD8(2)
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
15:0
—
—
31:16
—
15:0
31:16
22/6
CNPUD6 CNPUD5
—
—
CNPDD6 CNPDD5
15:0
ON
—
SIDL
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
CNIED8(2)
—
CNIED6
CNIED5
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CN
STATD8(2)
—
CN
STATD6
CN
STATD5
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
CNNED8(2)
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
CNFD8(2)
—
CNFD6
CNFD5
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
SR0D5
—
—
—
—
—
0000
—
—
—
—
—
—
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(2)
SR0D8
—
—
—
CNNED6 CNNED5
SR0D6
—
0000
15:0
—
—
—
—
—
—
—
—
SR1D6
SR1D5
—
SR1D8
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
This bit is not available on general purpose devices.
(2)
—
—
—
—
PIC32MK GP/MC Family
0390 CNSTATD
21/5
All
Resets
0320
PORTD REGISTER MAP FOR 64-PIN DEVICES ONLY
Bit Range
2016-2021 Microchip Technology Inc.
TABLE 13-8:
Virtual Address
(BF86_#)
Register
Name(1)
0400
ANSELE
0410
TRISE
0420
0440
PORTE
LATE
ODCE
0450
CNPUE
0460
CNPDE
0470 CNCONE
CNENE
2016-2021 Microchip Technology Inc.
04A0
CNNEE
04B0
CNFE
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ANSE15
ANSE14
ANSE13
ANSE12
—
—
ANSE9
ANSE8
—
—
—
—
—
—
ANSE1
ANSE0
F303
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
TRISE9
TRISE8
—
—
—
—
—
—
TRISE1
TRISE0
F303
15:0
TRISE15 TRISE14 TRISE13 TRISE12
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RE15
RE14
RE13
RE12
—
—
RE9
RE8
—
—
—
—
—
—
RE1
RE0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATE15
LATE14
LATE13
LATE12
—
—
LATE9
LATE8
—
—
—
—
—
—
LATE1
LATE0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
ODCE9
ODCE8
—
—
—
—
—
—
ODCE1
ODCE0
0000
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
ODCE15 ODCE14 ODCE13 ODCE12
—
—
—
—
—
—
—
—
15:0 CNPDE15 CNPDE14 CNPDE13 CNPDE12
CNPUE9 CNPUE8
—
—
CNPDE9 CNPDE8
CNPUE1 CNPUE0 0000
—
—
0000
CNPDE1 CNPDE0 0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
SIDL
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
CNIEE9
CNIEE8
—
—
—
—
—
—
CNIEE1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CN
STATE9
CN
STATE8
—
—
—
—
—
—
CN
STATE1
—
—
—
—
—
—
—
—
—
—
15:0 CNNEE15 CNNEE14 CNNEE13 CNNEE12
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNFE15
CNFE14
CNFE13
CNFE12
—
—
CNFE9
CNFE8
—
—
—
—
—
—
CNFE1
CNFE0
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
SR0E15
SR0E14
SR0E13
SR0E12
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
SR1E15
SR1E14
SR1E13
SR1E12
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
31:16
04C0 SRCON0E 31:16
15:0
04D0 SRCON1E 31:16
15:0
Legend:
Note 1:
30/14
31:16
31:16
0490 CNSTATE
31/15
All
Resets
Bit Range
Bits
0440
0480
PORTE REGISTER MAP FOR 100-PIN DEVICES ONLY
CN
CN
CN
CN
STATE15 STATE14 STATE13 STATE12
—
—
—
—
CNNEE9 CNNEE8
—
CNIEE0 0000
—
0000
CN
0000
STATE0
—
0000
CNNEE1 CNNEE0 0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
DS60001402H-page 261
TABLE 13-9:
Virtual Address
(BF86_#)
Register
Name(1)
0400
ANSELE
0410
TRISE
0420
PORTE
0440
LATE
0440
0450
0460
ODCE
CNPUE
CNPDE
0470 CNCONE
CNENE
0490 CNSTATE
04A0
CNNEE
04B0
CNFE
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ANSE15
ANSE14
ANSE13
ANSE12
—
—
—
—
—
—
—
—
—
—
—
—
F000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
F000
15:0
TRISE15 TRISE14 TRISE13 TRISE12
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RE15
RE14
RE13
RE12
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATE15
LATE14
LATE13
LATE12
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0 CNPDE15 CNPDE14 CNPDE13 CNPDE12
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
31:16
ODCE15 ODCE14 ODCE13 ODCE12
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
31:16
CN
CN
CN
CN
STATE15 STATE14 STATE13 STATE12
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0 CNNEE15 CNNEE14 CNNEE13 CNNEE12
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNFE15
CNFE14
CNFE13
CNFE12
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
SR0E15
SR0E14
SR0E13
SR0E12
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
SR1E15
SR1E14
SR1E13
SR1E12
—
—
—
—
—
—
—
—
—
—
—
—
0000
04C0 SRCON0E 31:16
15:0
04D0 SRCON1E 31:16
15:0
DS60001402H-page 262
Legend:
Note 1:
30/14
—
—
—
—
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
0480
31/15
All
Resets
Bits
Bit Range
2016-2021 Microchip Technology Inc.
TABLE 13-10: PORTE REGISTER MAP FOR 64-PIN DEVICES ONLY
0510
0520
0530
TRISF
PORTF
LATF
0540
ODCF
0550
CNPUF
0560
CNPDF
0570 CNCONF
0580
CNENF
0590 CNSTATF
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
0500 ANSELF
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
—
—
—
—
—
—
—
0000
—
ANSF5
—
—
—
—
—
3620
—
—
—
—
—
—
—
—
0000
—
TRISF7
TRISF6
TRISF5
—
—
—
TRISF1
TRISF0
36E3
—
—
—
—
—
—
—
—
—
—
0000
RF10
RF9
—
RF7
RF6
RF5
—
—
—
RF1
RF0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
0000
LATF12
—
LATF10
LATF9
—
LATF7
LATF6
LATF5
—
—
—
LATF1
LATF0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
ODCF13
ODCF12
—
ODCF10
ODCF9
—
ODCF7
ODCF6
ODCF5
—
—
—
ODCF1
ODCF0
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
CNPUF7
CNPUF6
CNPUF5
—
—
—
CNPUF1
31:16
—
—
15:0
—
—
31:16
—
—
—
—
—
—
15:0
ON
—
SIDL
—
EDGE
DETECT
—
31:16
—
—
—
—
—
15:0
—
—
CNIEF13
CNIEF12
—
31:16
—
—
—
—
—
CN
STATF12
—
31/15
30/14
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
31:16
29/13
28/12
27/11
—
—
—
ANSF13
ANSF12
—
—
—
—
—
TRISF13
TRISF12
—
—
—
15:0
—
—
31:16
—
15:0
25/9
24/8
23/7
22/6
—
—
—
—
ANSF10
ANSF9
—
—
—
—
—
—
TRISF10
TRISF9
—
—
—
RF13
RF12
—
—
—
—
—
—
LATF13
31:16
—
—
15:0
—
31:16
CNPUF13 CNPUF12
—
—
CNPDF13 CNPDF12
—
—
26/10
CNPUF10 CNPUF9
—
—
—
—
—
—
—
—
—
CNPDF7
CNPDF6
CNPDF5
—
—
—
CNPDF1
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
0000
CNIEF10
CNIEF9
—
CNIEF7
CNIEF6
CNIEF5
—
—
—
CNIEF1
CNIEF0
0000
—
—
—
—
—
—
—
—
—
—
—
0000
—
CN
STATF10
CN
STATF9
—
CN
STATF7
CN
STATF6
CN
STATF5
—
—
—
CN
STATF1
CN
STATF0
0000
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
CNNEE7
CNNEF6
CNNEF5
—
—
—
CNNEF1
—
—
—
CNPUF0 0000
CNPDF10 CNPDF9
—
0000
CNPDF0 0000
2016-2021 Microchip Technology Inc.
15:0
—
—
CN
STATF13
31:16
—
—
—
15:0
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
CNFF13
CNFF12
—
CNFF10
CNFF9
—
CNFE7
CNFF6
CNFF5
—
—
—
CNFF1
CNFF0
0000
05C0 SRCON0F 31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SR0F1
SR0F0
0000
05D0 SRCON1F 31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SR1F1
SR1F0
0000
05A0
CNNEF
05B0
CNFF
Legend:
Note 1:
CNNEF13 CNNEF12
—
CNNEF10 CNNEF9
CNNEF0 0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
DS60001402H-page 263
TABLE 13-11: PORTF REGISTER MAP FOR 100-PIN DEVICES ONLY
Virtual Address
(BF86_#)
Register
Name(1)
0510
TRISF
PORTF
0530
LATF
0540
ODCF
0550
CNPUF
0560
CNPDF
0570 CNCONF
0580
CNENF
—
—
0000
TRISF1
TRISF0
0003
—
—
0000
—
RF1
RF0
xxxx
—
—
—
—
0000
—
—
—
LATF1
LATF0
xxxx
—
—
—
—
—
—
0000
—
—
—
—
—
ODCF1
ODCF0
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
CNPUF1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPDF1
—
—
—
—
—
—
—
—
—
—
—
0000
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
17/1
CNPUF0 0000
—
0000
CNPDF0 0000
15:0
ON
—
SIDL
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIEF1
CNIEF0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CN
STATF1
CN
STATF0
0000
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNNEF1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNFF1
CNFF0
0000
05C0 SRCON0F 31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SR0F1
SR0F0
0000
05D0 SRCON1F 31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SR1F1
SR1F0
0000
05A0
CNNEF
05B0
CNFF
Legend:
Note 1:
CNNEF0 0000
DS60001402H-page 264
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
0590 CNSTATF
16/0
All
Resets
0520
Bits
Bit Range
2016-2021 Microchip Technology Inc.
TABLE 13-12: PORTF REGISTER MAP FOR 64-PIN DEVICES ONLY
0610
0620
0630
0640
TRISG
PORTG
LATG
ODCG
0650 CNPUG
0660 CNPDG
0670 CNCONG
0680 CNENG
0690 CNSTATG
06A0 CNNEG
2016-2021 Microchip Technology Inc.
06B0
CNFG
Legend:
Note 1:
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
0600 ANSELG
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
—
—
—
—
—
—
—
—
0000
ANSG7
ANSG6
—
—
—
—
—
—
8FC0
—
—
—
—
—
—
—
—
0000
TRISG8
TRISG7
TRISG6
—
—
—
—
TRISG1
TRISG0
FFC3
—
—
—
—
—
—
—
—
—
—
0000
RG10
RG9
RG8
RG7
RG6
—
—
—
—
RG1
RG0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
0000
LATG12
LATG11
LATG10
LATG9
LATG8
LATG7
LATG6
—
—
—
—
LATG1
LATG0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
ODCG14
ODCG13
ODCG12
ODCG11
ODCG10
ODCG9
ODCG8
ODCG7
ODCG6
—
—
—
—
ODCG1
ODCG0
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CNPUG8
CNPUG7
CNPUG6
—
—
—
—
31/15
30/14
29/13
28/12
27/11
31:16
—
—
—
—
—
—
—
—
15:0
ANSG15
—
—
—
ANSG11
ANSG10
ANSG9
ANSG8
31:16
—
—
—
—
—
—
—
—
15:0
TRISG15
TRISG10
TRISG9
31:16
—
—
—
—
—
—
15:0
RG15
RG14
RG13
RG12
RG11
31:16
—
—
—
—
15:0
LATG15
LATG14
LATG13
31:16
—
—
15:0
ODCG15
31:16
—
TRISG14 TRISG13 TRISG12 TRISG11
26/10
25/9
15:0 CNPUG15 CNPUG14 CNPUG13 CNPUG12 CNPUG11 CNPUG10 CNPUG9
31:16
—
—
—
—
—
—
—
15:0 CNPDG15 CNPDG14 CNPDG13 CNPDG12 CNPDG11 CNPDG10 CNPDG9
24/8
23/7
—
—
—
—
—
—
—
CNPDG8
CNPDG7
CNPDG6
—
—
—
—
CNPUG1 CNPUG0 0000
—
—
0000
CNPDG1 CNPDG0 0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
SIDL
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
0000
31:16
—
15:0
CNIEG15
31:16
—
15:0
CN
STATG15
31:16
—
CNIEG14 CNIEG13 CNIEG12 CNIEG11 CNIEG10
—
—
—
—
—
CN
CN
CN
CN
CN
STATG14 STATG13 STATG12 STATG11 STATG10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIEG9
CNIEG8
CNIEG7
CNIEG6
—
—
—
—
CNIEG1
—
—
—
—
—
CN
STATG1
—
—
—
—
CN
STATG9
CN
STATG8
CN
STATG7
CN
STATG6
—
—
—
—
—
—
—
—
—
—
—
—
CNNEG8
CNNEG7
CNNEG6
—
—
—
—
15:0 CNNEG15 CNNEG14 CNNEG13 CNNEG12 CNNEG11 CNNEG10 CNNEG9
—
CNIEG0 0000
—
0000
CN
0000
STATG0
—
0000
CNNEG1 CNNEG0 0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNFG15
CNFG14
CNFG13
CNFG12
CNFG11
CNFG10
CNFG9
CNFG8
CNFG7
CNFG6
—
—
—
—
CNFG1
CNFG0
0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more information.
PIC32MK GP/MC Family
DS60001402H-page 265
TABLE 13-13: PORTG REGISTER MAP FOR 100-PIN DEVICES ONLY
0610
TRISG
0620
PORTG
0630
LATG
0640
ODCG
0650 CNPUG
0660 CNPDG
0670 CNCONG
0690 CNSTATG
06A0 CNNEG
06B0
CNFG
Legend:
Note 1:
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
0000
ANSG7
ANSG6
—
—
—
—
—
—
03C0
—
—
—
—
—
—
—
—
0000
TRISG8
TRISG7
TRISG6
—
—
—
—
—
—
03C0
—
—
—
—
—
—
—
—
—
—
0000
—
RG9
RG8
RG7
RG6
—
—
—
—
—
—
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
LATG9
LATG8
LATG7
LATG6
—
—
—
—
—
—
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
ODCG9
ODCG8
ODCG7
ODCG6
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
CNPUG9
CNPUG8
CNPUG7
CNPUG6
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
CNPDG9
CNPDG8
CNPDG7
CNPDG6
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
ANSG9
ANSG8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
TRISG9
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
31:16
—
—
—
—
15:0
—
—
—
31:16
—
—
15:0
—
31:16
23/7
15:0
ON
—
SIDL
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
CNIEG9
CNIEG8
CNIEG7
CNIEG6
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
CN
STATG9
CN
STATG8
CN
STATG7
CN
STATG6
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
CNNEG9
CNNEG8
CNNEG7
CNNEG6
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
CNFG9
CNFG8
CNFG7
CNFG6
—
—
—
—
—
—
0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more information.
DS60001402H-page 266
PIC32MK GP/MC Family
0680 CNENG
22/6
All
Resets
0600 ANSELG
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF86_#)
2016-2021 Microchip Technology Inc.
TABLE 13-14: PORTG REGISTER MAP FOR 64-PIN DEVICES ONLY
1408
140C
1410
1418
141C
1420
1424
1428
142C
1430
2016-2021 Microchip Technology Inc.
1434
1438
143C
1440
Legend:
Note 1:
2:
3:
4:
INT1R
INT2R
INT3R
INT4R
T2CKR
T3CKR
T4CKR
T5CKR
T6CKR
T7CKR
T8CKR
T9CKR
IC1R
IC2R
IC3R
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
1404
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register is not available on 64-pin devices.
This register is not available on devices without a CAN module.
This register is only available on PIC32MKXXX*XGPE*/MCF*XXX devices.
This register is only available on motor control variants.
INT1R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
INT2R
—
0000
INT3R
—
0000
INT4R
—
0000
T2CKR
—
0000
T3CKR
—
0000
T4CKR
—
0000
T5CKR
—
0000
T6CKR
—
0000
T7CKR
—
0000
T8CKR
—
0000
T9CKR
—
0000
IC1R
—
0000
IC2R
—
IC3R
0000
0000
PIC32MK GP/MC Family
DS60001402H-page 267
TABLE 13-15: PERIPHERAL PIN SELECT INPUT REGISTER MAP
IC4R
1448
IC5R
144C
IC6R
1450
IC7R
1454
IC8R
1458
IC9R
145C
OCFBR
1464
1468
U1RXR
U1CTSR
146C
1470
U2RXR
U2CTSR
1474
DS60001402H-page 268
1478
U3RXR
U3CTSR
147C
Legend:
Note 1:
2:
3:
4:
U4RXR
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register is not available on 64-pin devices.
This register is not available on devices without a CAN module.
This register is only available on PIC32MKXXX*XGPE*/MCF*XXX devices.
This register is only available on motor control variants.
IC4R
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IC5R
—
0000
IC6R
—
0000
IC7R
—
0000
IC8R
—
0000
IC9R
—
0000
OCFAR
—
—
—
0000
OCFBR
—
—
—
—
—
0000
U1RXR
—
0000
U1CTSR
—
—
—
—
—
0000
U2RXR
—
0000
U2CTSR
—
—
—
—
—
0000
U3RXR
—
0000
U3CTSR
—
—
—
U4RXR
0000
0000
PIC32MK GP/MC Family
1460
OCFAR
All Resets
Register
Name
1444
Bit Range
Bits
Virtual Address
(BF80_#)
2016-2021 Microchip Technology Inc.
TABLE 13-15: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
1480
U4CTSR
1484
1488
U5RXR
U5CTSR
148C
1490
U6RXR
U6CTSR
1498
149C
14A4
14A8
14AC
14B0
2016-2021 Microchip Technology Inc.
14B4
14B8
14BC
14C0
Legend:
Note 1:
2:
3:
4:
SDI1R
SS1R
SDI2R
SS2R
SCK3R
SDI3R
SS3R
SCK4R
SDI4R
SS4R
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register is not available on 64-pin devices.
This register is not available on devices without a CAN module.
This register is only available on PIC32MKXXX*XGPE*/MCF*XXX devices.
This register is only available on motor control variants.
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
18/2
17/1
16/0
—
—
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
U4CTSR
—
—
—
—
—
0000
U5RXR
—
0000
U5CTSR
—
—
—
—
—
0000
U6RXR
—
0000
U6CTSR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
SDI1R
—
0000
SS1R
—
0000
SDI2R
—
0000
SS2R
—
0000
SCK3R
—
0000
SDI3R
—
0000
SS3R
—
0000
SCK4R
—
0000
SDI4R
—
SS4R
0000
0000
PIC32MK GP/MC Family
DS60001402H-page 269
TABLE 13-15: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
14C4
14C8
C2RXR(2)
14D4
14D8
14DC
14E4
14E8
14EC
QEA1R(4)
QEB1R(4)
INDX1R(4)
HOME1R
(4)
QEA2R(4)
QEB2R(4)
INDX2R(4)
HOME2R
14F0
14F4
DS60001402H-page 270
14F8
14FC
Legend:
Note 1:
2:
3:
4:
FLT1R
FLT2R
IC10R
IC11R
(4)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register is not available on 64-pin devices.
This register is not available on devices without a CAN module.
This register is only available on PIC32MKXXX*XGPE*/MCF*XXX devices.
This register is only available on motor control variants.
C1RXR
—
—
—
—
—
—
—
—
—
—
—
0000
C2RXR
—
0000
REFIR
—
0000
QEA1R
—
0000
QEB1R
—
0000
INDX1R
—
—
—
0000
HOME1R
—
—
—
—
—
—
—
0000
QEA2R
—
0000
QEB2R
—
0000
INDX2R
—
—
—
0000
HOME2R
—
—
—
—
—
—
—
—
—
0000
FLT1R
—
0000
FLT2R
—
0000
IC10R
—
IC11R
0000
0000
PIC32MK GP/MC Family
14E0
REFIR
All Resets
Register
Name
C1RXR(2)
14CC
14D0
Bit Range
Bits
Virtual Address
(BF80_#)
2016-2021 Microchip Technology Inc.
TABLE 13-15: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
1500
IC12R
1504
IC13R
1508
IC14R
150C
IC15R
1510
IC16R
1514
SCK5R
1518
SDI5R
151C
SS5R
1520
SCK6R
1524
SDI6R
1528
SS6R
2016-2021 Microchip Technology Inc.
152C
C3RXR(2)
1530
(2)
1534
1538
C4RXR
QEA3R(4)
QEB3R(4)
Legend:
Note 1:
2:
3:
4:
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
0000
—
0000
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register is not available on 64-pin devices.
This register is not available on devices without a CAN module.
This register is only available on PIC32MKXXX*XGPE*/MCF*XXX devices.
This register is only available on motor control variants.
IC12R
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IC13R
—
0000
IC14R
—
0000
IC15R
—
0000
IC16R
—
0000
—
SCK5R
—
—
0000
—
0000
SDI5R
—
—
—
—
—
—
—
0000
SS5R
—
0000
—
SCK6R
—
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
SDI6R
—
—
—
—
—
—
—
—
—
—
—
0000
SS6R
—
0000
C3RXR
—
0000
C4RXR
—
0000
QEA3R
—
QEB3R
0000
0000
PIC32MK GP/MC Family
DS60001402H-page 271
TABLE 13-15: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
153C
INDX3R(4)
1540
HOME3R(4)
1544
QEA4R(4)
1548
154C
1550
1554
155C
1560
1564
1568
156C
DS60001402H-page 272
1570
INDX4R(4)
HOME4R(4)
QEA5R
(4)
QEB5R(4)
INDX5R(4)
HOME5R(4)
QEA6R
(4)
QEB6R(4)
INDX6R(4)
HOME6R(4)
Legend:
Note 1:
2:
3:
4:
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register is not available on 64-pin devices.
This register is not available on devices without a CAN module.
This register is only available on PIC32MKXXX*XGPE*/MCF*XXX devices.
This register is only available on motor control variants.
18/2
17/1
16/0
—
—
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
INDX3R
—
—
—
0000
HOME3R
—
—
—
—
—
—
—
0000
QEA4R
—
0000
QEB4R
—
0000
INDX4R
—
—
—
0000
HOME4R
—
—
—
—
—
—
—
0000
QEA5R
—
0000
QEB5R
—
0000
INDX5R
—
—
—
0000
HOME5R
—
—
—
—
—
—
—
0000
QEA6R
—
0000
QEB6R
—
0000
INDX6R
—
—
—
HOME6R
0000
0000
PIC32MK GP/MC Family
1558
QEB4R(4)
31/15
All Resets
Register
Name
Bit Range
Bits
Virtual Address
(BF80_#)
2016-2021 Microchip Technology Inc.
TABLE 13-15: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
2016-2021 Microchip Technology Inc.
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1604 RPA1R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1608 RPA2R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
160C RPA3R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1610 RPA4R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
161C RPA7R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1620 RPA8R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
162C RPA11R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1630 RPA12R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1638 RPA14R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
163C RPA15R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1640 RPB0R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1644 RPB1R
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
1648 RPB2R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
164C RPB3R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1650 RPB4R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1654 RPB5R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1658 RPB6R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
165C RPB7R
15:0
—
—
—
—
—
—
—
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1600
RPA0R
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RPA0R
—
RPA1R
—
RPA2R
—
RPA3R
—
RPA4R
—
RPA7R
—
RPA8R
—
RPA11R
—
RPA12R
—
RPA14R
—
RPA15R
—
RPB0R
—
RPB1R
—
RPB2R
—
RPB3R
—
RPB4R
—
RPB5R
—
RPB6R
—
RPB7R
—
—
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MK GP/MC Family
DS60001402H-page 273
TABLE 13-16: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
RPB9R
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RPB9R
—
RPB10R
—
RPB11R
—
RPB12R
—
RPB13R
—
RPB14R
—
RPB15R
—
RPC0R
—
RPC1R
—
RPC2R
—
RPC4R
—
RPC6R
—
RPC7R
—
RPC8R
—
RPC9R
—
RPC10R
—
RPC12R
—
RPC15R
—
RPD3R
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MK GP/MC Family
DS60001402H-page 274
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1668 RPB10R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
166C RPB11R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1670 RPB12R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1674 RPB13R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1678 RPB14R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
167C RPB15R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1680 RPC0R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1684 RPC1R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1688 RPC2R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1690 RPC4R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1698 RPC6R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
169C RPC7R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
16A0 RPC8R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
16A4 RPC9R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
16A8 RPC10R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
16B0 RPC12R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
16BC RPC15R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
16CC RPD3R
—
—
—
—
—
—
—
—
15:0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1664
23/7
All Resets
Bit Range
Bits
Register
Name
Virtual Address
(BF80_#)
2016-2021 Microchip Technology Inc.
TABLE 13-16: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
2016-2021 Microchip Technology Inc.
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
16D4 RPD5R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
16D8 RPD6R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1700 RPE0R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1704 RPE1R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1738 RPE14R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
173C RPE15R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1740 RPF0R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1744 RPF1R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1780 RPG0R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1784 RPG1R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1798 RPG6R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
179C RPG7R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
17A0 RPG8R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
17A4 RPG9R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
17B0 RPG12R
—
—
—
—
—
—
—
—
15:0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
16D0
RPD4R
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RPD4R
—
RPD5R
—
RPD6R
—
RPE0R
—
RPE1R
—
RPF14R
—
RPE15R
—
RPF0R
—
RPF1R
—
RPG0R
—
RPG1R
—
RPG6R
—
RPG7R
—
RPG8R
—
RPG9R
—
RPG12R
—
—
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MK GP/MC Family
DS60001402H-page 275
TABLE 13-16: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)
PIC32MK GP/MC Family
REGISTER 13-1:
Bit
Range
31:24
23:16
15:8
7:0
[pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
[pin name]R
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4
Unimplemented: Read as ‘0’
bit 3-0
[pin name]R: Peripheral Pin Select Input bits
Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Table 13-1 for
input pin selection values.
Note:
Register values can only be changed if the IOLOCK Configuration bit (CFGCON) = 0.
REGISTER 13-2:
Bit
Range
31:24
23:16
15:8
7:0
RPnR: PERIPHERAL PIN SELECT OUTPUT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RPnR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-5
Unimplemented: Read as ‘0’
bit 4-0
RPnR: Peripheral Pin Select Output bits
See Table 13-2 for output pin selection values.
Note:
x = Bit is unknown
Register values can only be changed if the IOLOCK Configuration bit (CFGCON) = 0.
DS60001402H-page 276
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 13-3:
Bit
Range
31:24
23:16
15:8
7:0
CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (x = A – G)
Bit
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
R/W-0
r-0
U-0
U-0
ON
—
SIDL
—
EDGEDETECT
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Change Notice (CN) Control ON bit
1 = CN is enabled
0 = CN is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Control bit
1 = CPU Idle mode halts CN operation
0 = CPU Idle mode does not affect CN operation
bit 12
Unimplemented: Read as ‘0’
bit 11
EDGEDETECT: Edge Detection Type Control bit
1 = Detects any edge on the pin (CNx is used for the CN event)
0 = Detects any edge on the pin (CNSTATx is used for the CN event)
bit 10
Reserved: Always write ‘0’
bit 9-0
Unimplemented: Read as ‘0’
2016-2021 Microchip Technology Inc.
DS60001402H-page 277
PIC32MK GP/MC Family
14.0
Note:
TIMER1
This data sheet summarizes the features
of the PIC32MK GP/MC family of devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 14. “Timers” (DS60001105),
which is available from the Documentation
> Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
PIC32MK GP/MC devices feature one synchronous/
asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and
counting external events. This timer can also be used
with the low-power Secondary Oscillator (SOSC) for realtime clock applications.
The following modes are supported by Timer1:
•
•
•
•
Synchronous Internal Timer
Synchronous Internal Gated Timer
Synchronous External Timer
Asynchronous External Timer
14.1
Additional Supported Features
• Selectable clock prescaler
• Timer operation during Sleep and Idle modes
• Fast bit manipulation using CLR, SET, and INV
registers
• Asynchronous mode can be used with the SOSC
to function as a real-time clock
• ADC event trigger
14.2
14.2.1
14.2.2
ASYNCHRONOUS MODE
OPERATION
When writing the ON bit when the Timer is configured
in Asynchronous mode or in an external clock mode
with the prescaler enabled, the act of setting the ON bit
does not take effect until two rising edges of the
external clock input have occurred.
14.2.3
ASYNCHRONOUS MODE
OPERATION WITH A PENDING
TMRx REGISTER WRITE
When the Timer is configured in Asynchronous mode
and the Timer is attempting to write to the TMRx
register while a previous write is awaiting
synchronization, the value written to the timer can
become corrupted.
To ensure that writes will not cause the TMRx value to
become corrupted, the TWDIS bit (TxCON), when
set, will ignore a write to the TMRx register when a
previous write to the TMRx register is awaiting synchronization into the Asynchronous Timer Clock domain.
The TWIP bit (TxCON) indicates when write
synchronization is complete, and it is safe to write
another value to the timer.
14.2.4
PRx REGISTER WRITES
Writing to the PRx register while the Timer is active,
may cause erratic operation.
TImer1 Usage Model Guidelines
EXTERNAL CLOCK MODE
OPERATION
When the Timer is operating with an external clock
mode with the TCS bit (TxCON) = 1, the mode bits
of the TxCON register must be initialized using a separate Write operation from that used to enable the Timer.
Specifically, the TCS, TSYNC, etc. bits must be written
first, and then the ON bit (TxCON) must be set in
a subsequent write.
Once the ON bit is set, any writes to the TxCON
register may cause erroneous counter operation.
Note:
The ON bit should be clear when updates
are made to any other bits in the TxCON
register.
DS60001402H-page 278
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
FIGURE 14-1:
TIMER1 BLOCK DIAGRAM
PR1
Trigger to ADC(1)
Q
D
Equal
16-bit Comparator
TSYNC
Q
1
Sync
TMR1
Reset
0
T1IF Event
Flag(1)
0
1
Q
TGATE
D
Q
TGATE
TCS
ON
SOSC
00
T1CK
01
LPRC
10
TECS
x1
Gate
Sync
PBCLK2
10
00
Prescaler
1, 8, 64, 256
2
TCKPS
Note
1:
Timer1 ADC trigger and interrupt occurs on match plus 1 count; therefore, set the period to PR1 minus 1 to compensate,
regardless of the prescaler.
2016-2021 Microchip Technology Inc.
DS60001402H-page 279
Timer1 Control Register
TABLE 14-1:
Virtual Address
(BF82_#)
TMR1
0020
PR1
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
TWDIS
TWIP
—
31:16
—
—
—
—
—
—
TECS
—
15:0
31:16
15:0
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
0000
TGATE
—
TCKPS
—
TSYNC
TCS
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
TMR1
—
—
—
—
—
—
—
All Resets
Bit Range
0000 T1CON
0010
TIMER1 REGISTER MAP
Bits
Register
Name(1)
2016-2021 Microchip Technology Inc.
14.3
—
—
PR1
0000
0000
FFFF
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
DS60001402H-page 280
PIC32MK GP/MC Family
REGISTER 14-1:
Bit
Range
31:24
23:16
15:8
7:0
T1CON: TYPE A TIMER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
R/W-0
R-0
U-0
R/W-0
R/W-0
ON
—
SIDL
TWDIS
TWIP
—
R/W-0
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
TGATE
—
—
TSYNC
TCS
—
TCKPS
TECS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Timer On bit
1 = Timer is enabled
0 = Timer is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation even in Idle mode
bit 12
TWDIS: Asynchronous Timer Write Disable bit
1 = Writes to TMR1 are ignored until pending write operation completes
0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
bit 11
TWIP: Asynchronous Timer Write in Progress bit
In Asynchronous Timer mode:
1 = Asynchronous write to TMR1 register in progress
0 = Asynchronous write to TMR1 register complete
In Synchronous Timer mode:
This bit is read as ‘0’.
bit 10
Unimplemented: Read as ‘0’
bit 9-8
TECS: Timer1 External Clock Selection bits
11 = Reserved
10 = External clock comes from the LPRC
01 = External clock comes from the T1CK pin
00 = External clock comes from the SOSC
bit 7
TGATE: Timer Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6
Unimplemented: Read as ‘0’
2016-2021 Microchip Technology Inc.
DS60001402H-page 281
PIC32MK GP/MC Family
REGISTER 14-1:
T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED)
bit 5-4
TCKPS: Timer Input Clock Prescale Select bits
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3
Unimplemented: Read as ‘0’
bit 2
TSYNC: Timer External Clock Input Synchronization Selection bit
When TCS = 1:
1 = External clock input is synchronized
0 = External clock input is not synchronized
When TCS = 0:
This bit is ignored.
bit 1
TCS: Timer Clock Source Select bit
1 = External clock is defined by the TECS bits
0 = Internal peripheral clock
bit 0
Unimplemented: Read as ‘0’
DS60001402H-page 282
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
NOTES:
2016-2021 Microchip Technology Inc.
DS60001402H-page 283
PIC32MK GP/MC Family
15.0
TIMER2 THROUGH TIMER9
Note:
15.1
The following are key features of the timers:
This data sheet summarizes the features
of the PIC32MK GP/MC family of devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 14. “Timers” (DS60001105),
which is available from the Documentation
> Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
• External 16-bit/32-bit Counter Input mode
• Asynchronous external clock with/without
selectable prescaler
• Synchronous internal clock with/without
selectable prescaler
• External gate control (External pulse width
measurement)
• Automatic timer synchronization control
• Operation in Idle mode
• Interrupt on a period register match or falling edge
of external gate signal
• Time base for Input Capture and/or Output
Compare modules
The PIC32MK GP/MC family of devices features
eight native synchronous/asynchronous 16/32-bit
timers (default 16-bit mode) that can operate as freerunning interval timers for various timing applications
and counting external events.
FIGURE 15-1:
Features
TIMER2 THROUGH TIMER9 BLOCK DIAGRAM (16/32-BIT)
Reset
Trigger to ADC(1,2)
Q
D
Sync
TMRx (16/32)
Equal
Comparator x 16/32
Q
PRx (16/32)
0
TxIF Event Flag(2)
1
TGATE
Q
TGATE
D
Q
TCS
ON
TxCK
x1
Gate
Sync
PBCLK2
Note
1:
2:
10
00
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
3
TCKPS
The ADC event trigger is available on Timer1, Timer3, and Timer5 only.
Timer2-Timer9 ADC trigger and interrupt occurs on match plus 1 count; therefore, set the period to PRx minus 1 to compensate,
regardless of the prescaler.
DS60001402H-page 284
2016-2021 Microchip Technology Inc.
Timer2-Timer9 Control Registers
Virtual Address
(BF82_#)
TABLE 15-1:
TMR2
0220
PR2
0400 T3CON
0410
TMR3
0420
PR3
0600 T4CON
0610
TMR4
0620
PR4
0800 T5CON
0810
TMR5
2016-2021 Microchip Technology Inc.
0820
PR5
0A00 T6CON
0A10 TMR6
0A20
PR6
0C00 T7CON
31/15
30/14
29/13
28/12
27/11
26/10
25/9
31:16
—
15:0
ON
—
—
—
—
—
—
—
SIDL
—
—
—
—
24/8
23/7
22/6
—
—
—
SYNC
TGATE
21/5
20/4
—
—
TCKPS
19/3
18/2
—
T32
All Resets
Register
Name(1)
Bit Range
Bits
0200 T2CON
0210
TIMER2 THROUGH TIMER9 REGISTER MAP
17/1
16/0
—
—
—
0000
—
TCS
—
0000
31:16
TMR2
0000
15:0
TMR2
0000
31:16
PR2
FFFF
15:0
PR2
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
SYNC
TGATE
FFFF
—
—
—
TCKPS
—
—
—
—
0000
T32
—
TCS
—
0000
31:16
TMR3
0000
15:0
TMR3
0000
31:16
PR3
FFFF
15:0
PR3
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
SYNC
TGATE
FFFF
—
—
—
TCKPS
—
—
—
—
0000
T32
—
TCS
—
0000
31:16
TMR4
0000
15:0
TMR4
0000
31:16
PR4
FFFF
15:0
PR4
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
SYNC
TGATE
FFFF
—
—
—
TCKPS
—
—
—
—
0000
T32
—
TCS
—
0000
31:16
TMR5
0000
15:0
TMR5
0000
31:16
PR5
FFFF
15:0
PR5
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
SYNC
TGATE
FFFF
—
—
—
TCKPS
—
—
—
—
0000
T32
—
TCS
—
0000
31:16
TMR6
0000
15:0
TMR6
0000
31:16
PR6
FFFF
15:0
PR6
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
SYNC
TGATE
FFFF
—
—
TCKPS
—
—
—
—
—
0000
T32
—
TCS
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
DS60001402H-page 285
15.2
Virtual Address
(BF82_#)
TIMER2 THROUGH TIMER9 REGISTER MAP (CONTINUED)
0C10 TMR7
0C20
PR7
0E00 T8CON
0E10 TMR8
0E20
PR8
1000 T9CON
1010
TMR9
1020
PR9
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Bits
Register
Name(1)
2016-2021 Microchip Technology Inc.
TABLE 15-1:
31:16
TMR7
0000
15:0
TMR7
0000
31:16
PR7
FFFF
15:0
PR7
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
SYNC
TGATE
FFFF
—
—
—
TCKPS
—
—
—
—
0000
T32
—
TCS
—
0000
31:16
TMR8
0000
15:0
TMR8
0000
31:16
PR8
FFFF
15:0
PR8
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
SYNC
TGATE
FFFF
—
—
TCKPS
—
—
—
—
—
0000
T32
—
TCS
—
0000
31:16
TMR9
0000
15:0
TMR9
0000
31:16
PR9
FFFF
15:0
PR9
FFFF
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
DS60001402H-page 286
PIC32MK GP/MC Family
Legend:
PIC32MK GP/MC Family
REGISTER 15-1:
Bit
Range
31:24
23:16
15:8
7:0
TxCON: TYPE B TIMER CONTROL REGISTER (‘x’ = 2-9)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
R/W-0
ON
—
SIDL
—
—
—
—
SYNC
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
T32
—
TCS
—
TGATE
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15
bit 14
bit 13
bit 12-9
bit 8
TCKPS
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
ON: Timer On bit
1 = Module is enabled
0 = Module is disabled
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation even in Idle mode
Unimplemented: Read as ‘0’
SYNC: TMRx Synchronized Timer Start/Stop Enable bit
1 = TMRx synchronized timer start/stop is enabled
0 = TMRx synchronized timer start/stop is disabled
Note:
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Setting this bit chains all timers whose corresponding SYNC bit is also set such that when the
TON bit of all corresponding timers is set, the timers are enabled simultaneously. If any timers
in the group are disabled, they are all disabled simultaneously.
TGATE: Timer Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored and is read as ‘0’.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
TCKPS: Timer Input Clock Prescale Select bits
111 = 1:256 prescale value
110 = 1:64 prescale value
101 = 1:32 prescale value
100 = 1:16 prescale value
011 = 1:8 prescale value
010 = 1:4 prescale value
001 = 1:2 prescale value
000 = 1:1 prescale value
T32: 32-Bit Timer Mode Select bit
1 = 32-bit Timer mode
0 = 16-bit Timer mode
Unimplemented: Read as ‘0’
TCS: Timer Clock Source Select bit
1 = External clock from TxCK pin
0 = Internal peripheral clock
Unimplemented: Read as ‘0’
2016-2021 Microchip Technology Inc.
DS60001402H-page 287
PIC32MK GP/MC Family
16.0
DEADMAN TIMER (DMT)
Note:
The primary function of the Deadman Timer (DMT) is
to reset the processor in the event of a software malfunction. The DMT is a free-running instruction fetch
timer, which is clocked whenever an instruction fetch
occurs until a count match occurs. Instructions are not
fetched when the processor is in Sleep mode.
This data sheet summarizes the
features of the PIC32MK GP/MC family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 9. “Watchdog,
Deadman, and Power-up Timers”
(DS60001114), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The DMT consists of a 32-bit counter with a time-out
count match value as specified by the DMTCNT
bits in the DEVCFG1 Configuration register.
A Deadman Timer is typically used in mission critical
and safety critical applications, where any single
failure of the software functionality and sequencing
must be detected.
Figure 16-1 shows a block diagram of the Deadman
Timer module.
FIGURE 16-1:
DEADMAN TIMER BLOCK DIAGRAM
“improper sequence” flag
ON
Instruction Fetched Strobe
Force DMT Event
System Reset
Counter Initialization Value
PBCLK7
Clock
“Proper Clear Sequence” Flag
ON
32-bit counter
ON
32
DMT event
to NMI(3)
DMT Count Reset Load
System Reset
(COUNTER) = DMT Max Count(1)
(COUNTER) DMT Window Interval(2)
Window Interval Open
Note
1:
2:
3:
DMT Max Count is controlled by the DMTCNT bits in the DEVCFG1 Configuration register.
DMT Window Interval is controlled by the DMTINTV bits in the DEVCFG1 Configuration register.
Refer to 7.0 “Resets” for more information.
DS60001402H-page 288
2016-2021 Microchip Technology Inc.
Deadman Timer Control Registers
Virtual Address
(BF80_#)
Register
Name
TABLE 16-1:
0E00
DMTCON
DEADMAN TIMER REGISTER MAP
0E10 DMTPRECLR
0E20
DMCLR
0E30
DMTSTAT
0E40
DMTCNT
0E60
DMTPSCNT
0E70
DMTPSINTV
Legend:
All Resets
Bit Range
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
15:0
STEP1
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
BAD1
BAD2
DMTEVENT
—
—
—
—
31:16
15:0
31:16
15:0
31:16
15:0
STEP2
COUNTER
PSCNT
PSINTV
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
0000
WINOPN 0000
0000
0000
0000
0000
0000
0000
PIC32MK GP/MC Family
DS60001402H-page 289
16.1
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 16-1:
Bit Range
DMTCON: DEADMAN TIMER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
ON
7:0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-16
Unimplemented: Read as ‘0’
bit 15
ON: Deadman Timer Module Enable bit(1,2)
1 = Deadman Timer module is enabled
0 = Deadman Timer module is disabled
bit 13-0
Unimplemented: Read as ‘0’
Note 1:
2:
x = Bit is unknown
This bit only has control when the FDMTEN bit (DEVCFG1) = 0.
Once set, the DMTCON.ON bit cannot be disabled by software.
REGISTER 16-2:
Bit Range
DMTPRECLR: DEADMAN TIMER PRECLEAR REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
STEP1
7:0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15-8
STEP1: Preclear Enable bits
01000000 = Enables the Deadman Timer Preclear (Step 1)
All other write patterns = Set BAD1 flag.
These bits are cleared when a DMT reset event occurs. STEP1 is also cleared if the
STEP2 bits are loaded with the correct value in the correct sequence.
bit 7-0
Unimplemented: Read as ‘0’
DS60001402H-page 290
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 16-3:
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
DMTCLR: DEADMAN TIMER CLEAR REGISTER
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STEP2
Legend:
R = Readable bit
-n = Value at POR
bit 31-8
bit 7-0
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
STEP2: Clear Timer bits
00001000 = Clears STEP1, STEP2 and the Deadman Timer if, and only if, preceded by
correct loading of STEP1 bits in the correct sequence. The write to these bits may
be verified by reading DMTCNT and observing the counter being reset.
All other write patterns = Set BAD2 bit, the value of STEP1 will remain unchanged, and the new
value being written STEP2 will be captured. These bits are also cleared when a DMT reset event
occurs.
2016-2021 Microchip Technology Inc.
DS60001402H-page 291
PIC32MK GP/MC Family
REGISTER 16-4:
Bit Range
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
DMTSTAT: DEADMAN TIMER STATUS REGISTER
Bit
31/23/15/7
bit 6
bit 5
bit 4-1
bit 0
Bit
Bit
25/17/9/1 24/16/8/0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0, HC
R-0, HC
R-0, HC
R/W-0
R/W-0
R/W-0
R/W-0
R-0
BAD1
BAD2
DMTEVENT
Legend:
R = Readable bit
-n = Value at POR
bit 31-8
bit 7
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
HC = Hardware Cleared
W = Writable bit
‘1’ = Bit is set
WINOPN
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
BAD1: Bad STEP1 Value Detect bit
1 = Incorrect STEP1 value or out of sequence write to step2 was detected
0 = Incorrect STEP1 value was not detected
BAD2: Bad STEP2 Value Detect bit
1 = Incorrect STEP2 value was detected
0 = Incorrect STEP2 value was not detected
DMTEVENT: Deadman Timer Event bit
1 = Deadman timer event was detected (counter expired or bad STEP1 or STEP2 value was
entered prior to counter increment)
0 = Deadman timer even was not detected
Note:
This bit is cleared only on a Reset.
Unimplemented: Read as ‘0’
WINOPN: Deadman Timer Clear Window bit
1 = Deadman timer clear window is open
0 = Deadman timer clear window is not open
DS60001402H-page 292
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 16-5:
Bit Range
DMTCNT: DEADMAN TIMER COUNT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
R-0
R-0
31:24
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
COUNTER
R-0
7:0
R-0
R-0
R-0
R-0
COUNTER
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
COUNTER: Read current contents of DMT counter
REGISTER 16-6:
DMTPSCNT: POST STATUS CONFIGURE DMT COUNT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
R-0
R-0
31:24
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
R-0
R-0
R-0
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-y
R-y
R-y
PSCNT
R-0
23:16
R-0
R-0
R-0
R-0
PSCNT
R-0
15:8
R-0
R-0
R-0
R-0
PSCNT
R-0
7:0
R-0
R-0
R-y
R-y
PSCNT
Legend:
R = Readable bit
-n = Value at POR
bit 31-8
R-0
Bit
24/16/8/0
COUNTER
15:8
Bit Range
R-0
Bit
25/17/9/1
COUNTER
23:16
bit 31-8
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
W = Writable bit
‘1’ = Bit is set
y= Value set from Configuration bits on POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
PSCNT: DMT Instruction Count Value Configuration Status bits
This is always the value of the DMTCNT bits in the DEVCFG1 Configuration register.
2016-2021 Microchip Technology Inc.
DS60001402H-page 293
PIC32MK GP/MC Family
REGISTER 16-7:
Bit Range
DMTPSINTV: POST STATUS CONFIGURE DMT INTERVAL STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
R-0
R-0
31:24
R-0
R-0
R-0
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-y
R-y
R-y
PSINTV
R-0
23:16
R-0
R-0
R-0
R-0
PSINTV
R-0
15:8
R-0
R-0
R-0
R-0
PSINTV
R-0
7:0
R-0
R-0
R-0
R-0
PSINTV
Legend:
R = Readable bit
-n = Value at POR
bit 31-8
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
W = Writable bit
‘1’ = Bit is set
y= Value set from Configuration bits on POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
PSINTV: DMT Window Interval Configuration Status bits
This is always the value of the DMTINTV bits in the DEVCFG1 Configuration register.
DS60001402H-page 294
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
NOTES:
2016-2021 Microchip Technology Inc.
DS60001402H-page 295
PIC32MK GP/MC Family
17.0
WATCHDOG TIMER (WDT)
Note:
This data sheet summarizes the features
of the PIC32MK GP/MC Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 9. “Watchdog,
Deadman, and Power-up Timers”
(DS60001114), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
FIGURE 17-1:
When enabled, the Watchdog Timer (WDT) operates
from the internal Low-Power Oscillator (LPRC) clock
source and can be used to detect system software malfunctions by resetting the device if the WDT is not
cleared periodically in software. Various WDT time-out
periods can be selected using the WDT postscaler. The
WDT can also be used to wake the device from Sleep
or Idle mode.
Some of the key features of the WDT module are as
follows:
• Configuration or software controlled
• User-configurable time-out period
• Can wake the device from Sleep mode or Idle
mode
WATCHDOG TIMER BLOCK DIAGRAM
LPRC
WDTCLR = 1
ON
Wake
ON
Reset Event
ON
Clock
25-bit Counter
25
0
1
WDT Counter Reset
WDT Event
to NMI(1)
Power Save
Decoder
FWDTPS (DEVCFG1)
Note 1:
Refer to 7.0 “Resets” for more information.
DS60001402H-page 296
2016-2021 Microchip Technology Inc.
Watchdog Timer Control Registers
Virtual Address
(BF80_#)
Register
Name
TABLE 17-1:
0C00
WDTCON(1)
WATCHDOG TIMER REGISTER MAP
Legend:
Note 1:
31/15
30/14
29/13
ON
—
—
28/12
27/11
26/10
31:16
15:0
25/9
24/8
23/7
22/6
21/5
20/4
19/3
WDTCLRKEY
RUNDIV
—
—
18/2
17/1
All Resets
Bit Range
Bits
16/0
0000
SLPDIV
WDTWINEN 0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more information.
PIC32MK GP/MC Family
DS60001402H-page 297
17.1
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 17-1:
Bit
Range
31:24
23:16
15:8
7:0
WDTCON: WATCHDOG TIMER CONTROL REGISTER
Bit
31/23/15/7
W-0
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4
W-0
W-0
W-0
Bit
Bit
27/19/11/3 26/18/10/2
W-0
Bit
25/17/9/1
Bit
24/16/8/0
W-0
W-0
W-0
W-0
W-0
W-0
R-y
R-y
R-y
WDTCLRKEY
W-0
W-0
W-0
W-0
W-0
WDTCLRKEY
R/W-0
U-0
U-0
ON(1)
—
—
U-0
U-0
R-y
—
—
Legend:
R-y
R-y
RUNDIV
R-y
R-y
R-y
R-y
SLPDIV
R/W-0
WDTWINEN
y = Values set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 WDTCLRKEY: Watchdog Timer Clear Key bits
To clear the Watchdog Timer to prevent a time-out, software must write the value 0x5743 to these bits using
a single 16-bit write.
bit 15
ON: Watchdog Timer Enable bit(1)
1 = The Watchdog Timer module is enabled
0 = The Watchdog Timer module is disabled
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8
RUNDIV: Watchdog Timer Postscaler Value in Run Mode bits
In Run mode, these bits are set to the values of the WDTPS Configuration bits in the DEVCFG1
register.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-1
SLPDIV: Watchdog Timer Postscaler Value in Sleep Mode bits
In Sleep mode, these bits are set to the values of the WDTPS Configuration bits in the DEVCFG1
register.
bit 0
WDTWINEN: Watchdog Timer Window Enable bit
1 = Enable windowed Watchdog Timer
0 = Disable windowed Watchdog Timer
Note 1:
This bit only has control when FWDTEN (DEVCFG1) = 0.
DS60001402H-page 298
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
NOTES:
2016-2021 Microchip Technology Inc.
DS60001402H-page 299
PIC32MK GP/MC Family
18.0
Note:
INPUT CAPTURE
This data sheet summarizes the features
of the PIC32MK GP/MC family of devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section
15.
“Input
Capture”
(DS60001122), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The Input Capture module is useful in applications
requiring frequency (period) and pulse measurement.
The Input Capture module captures the 16-bit or 32-bit
value of the selected Time Base registers when an
event occurs at the ICx pin.
Capture events are caused by the following factors:
• Capture timer value on every edge (rising and falling),
specified edge first
• Prescaler capture event modes:
- Capture timer value on every 4th rising edge of
input at ICx pin
- Capture timer value on every 16th rising edge of
input at ICx pin
- Capture every falling edge of input at ICx pin
- Capture every rising edge of input at ICx pin
- Capture every 4th rising edge of input at ICx
pin
- Capture every 16th rising edge of input at ICx
pin
- Capture every rising and falling edge of input
at ICx pin
- Capture timer values based on internal or
external clocks
Each input capture channel can select between either
eight 16-bit time bases or four 32-bit time base. The
selected timer can use either an internal or external
clock.
Other operational features include:
• Device wake-up from capture pin during Sleep and
Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values; Interrupt
optionally generated after 1, 2, 3, or 4 buffer
locations are filled
• Input capture can also be used to provide additional
sources of external interrupts
DS60001402H-page 300
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
FIGURE 18-1:
INPUT CAPTURE BLOCK DIAGRAM
FEDGE
Specified/Every
Edge Mode
ICM
110
See Table 18-1
Timerx(2)
Prescaler Mode
(16th Rising Edge)
101
Prescaler Mode
(4th Rising Edge)
100
ICx(1)
Rising Edge Mode
011
Falling Edge Mode
010
Edge Detection
Mode
001
C32
(ICxCON
ICACLK
(CFGCON
CaptureEvent
PBCLKx (‘x’ = 2, 3)(3)
Timery(2)
To CPU
FIFO Control
ICxBUF(1)
FIFO
ICI
ICM
Set Flag ICxIF(1)
(In IFSx Register)
/N
Sleep/Idle
Wake-up Mode
111
Note
1:
An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
2:
See Table 18-1 for Timerx and Timery selections.
3:
PBCLK2 = Input Capture 1 through Input Capture 9; PBCLK3 = Input Capture 10 through Input Capture 16.
2016-2021 Microchip Technology Inc.
DS60001402H-page 301
2016-2021 Microchip Technology Inc.
The timer source for each Input Capture module depends on the setting of the
ICACLK bit in the CFGCON register and the C32 bit in the ICxCON register. The
available configurations are shown in Table 18-1.
TABLE 18-1:
ICAPx
TIMER SOURCE CONFIGURATIONS
CFGCON
ICxCON
0
0
0
1
1
0
ICAP[3-1]
ICAP[6-4]
ICAP[16-13]
1
0
0
0
1
1
0
1
1
0
0
0
1
ICAP[9-7]
ICAP[12-10]
DS60001402H-page 302
ICAP[16-13]
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
TIMER_x
—
TIMER_y
0x0000_TMR3 [15:0]
0x0000_TMR2 [15:0]
—
—
TMR2 [31:0]
--0x0000_TMR5 [15:0]
TMR2 [31:0]
—
0x0000_TMR4 [15:0]
—
—
TMR4 [31:0]
TMR4 [31:0]
—
—
0x0000_TMR3 [15:0]
0x0000_TMR2 [15:0]
—
—
TMR2 [31:0]
TMR2 [31:0]
—
—
0x0000_TMR3 [15:0]
0x0000_TMR2 [15:0]
—
—
TMR2 [31:0]
TMR2 [31:0]
—
—
0x0000_TMR3 [15:0]
0x0000_TMR2 [15:0]
—
—
TMR2 [31:0]
TMR2 [31:0]
—
—
0x0000_TMR7 [15:0]
0x0000_TMR6 [15:0]
—
—
TMR6 [31:0]
TMR6 [31:0]
—
—
0x0000_TMR3 [15:0]
0x0000_TMR2 [15:0]
—
—
TMR2 [31:0]
TMR2 [31:0]
—
—
0x0000_TMR9 [15:0]
0x0000_TMR8 [15:0]
—
—
TMR8 [31:0]
TMR8 [31:0]
—
—
0x0000_TMR3 [15:0]
0x0000_TMR2 [15:0]
—
—
TMR2 [31:0]
TMR2 [31:0]
—
—
0x0000_TMR3 [15:0]
0x0000_TMR2 [15:0]
—
—
TMR2 [31:0]
TMR2 [31:0]
—
ICxBUF CONTENT
0x0000_TMR3 [15:0]
0x0000_TMR2 [15:0]
TMR2 [31:0]
TMR2 [31:0]
0x0000_TMR5 [15:0]
0x0000_TMR4 [15:0]
TMR4 [31:0]
TMR4 [31:0]
0x0000_TMR3 [15:0]
0x0000_TMR2 [15:0]
TMR2 [31:0]
TMR2 [31:0]
0x0000_TMR3 [15:0]
0x0000_TMR2 [15:0]
TMR2 [31:0]
TMR2 [31:0]
0x0000_TMR3 [15:0]
0x0000_TMR2 [15:0]
TMR2 [31:0]
TMR2 [31:0]
0x0000_TMR7 [15:0]
0x0000_TMR6 [15:0]
TMR6 [31:0]
TMR6 [31:0]
0x0000_TMR3 [15:0]
0x0000_TMR2 [15:0]
TMR2 [31:0]
TMR2 [31:0]
0x0000_TMR9 [15:0]
0x0000_TMR8 [15:0]
TMR8 [31:0]
TMR8 [31:0]
0x0000_TMR3 [15:0]
0x0000_TMR2 [15:0]
TMR2 [31:0]
TMR2 [31:0]
0x0000_TMR3 [15:0]
0x0000_TMR2 [15:0]
TMR2 [31:0]
TMR2 [31:0]
PIC32MK GP/MC Family
1
ICxCON
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input Capture Control Registers
INPUT CAPTURE 1 THROUGH INPUT CAPTURE 9 REGISTER MAP
2000 IC1CON(1)
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
All Resets
Bit Range
Bits
Register
Name
Virtual Address
BF82_#
TABLE 18-2:
0000
2016-2021 Microchip Technology Inc.
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
0000
31:16
xxxx
IC1BUF
IC1BUF
2010
15:0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
(1) 31:16
2200 IC2CON
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
0000
31:16
xxxx
IC2BUF
IC2BUF
2210
15:0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
2400 IC3CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
0000
31:16
xxxx
IC3BUF
IC3BUF
2410
15:0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
(1)
2600 IC4CON
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
0000
31:16
xxxx
IC4BUF
IC4BUF
2610
15:0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
2800 IC5CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
0000
31:16
xxxx
IC5BUF
IC5BUF
2810
15:0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
(1) 31:16
2A00 IC6CON
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
0000
31:16
xxxx
IC6BUF
IC6BUF
2A10
15:0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
2C00 IC7CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
0000
31:16
xxxx
IC7BUF
2C10 IC7BUF
15:0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
(1) 31:16
2E00 IC8CON
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
0000
31:16
xxxx
IC8BUF
IC8BUF
2E10
15:0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
3000 IC9CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
0000
31:16
xxxx
IC9BUF
IC9BUF
3010
15:0
xxxx
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more information.
PIC32MK GP/MC Family
DS60001402H-page 303
18.1
Virtual Address
BF84_#
3210
IC10BUF
3400
IC11CON(1)
IC11BUF
3600 IC12CON
3610
(1)
IC12BUF
3800 IC13CON
(1)
IC13BUF
3A00
IC14CON(1)
3A10
IC14BUF
3C00 IC15CON
(1)
3C10
IC15BUF
3E00
IC16CON(1)
3E10
IC16BUF
30/14
29/13
28/12
27/11
26/10
31:16
—
15:0
ON
25/9
—
—
—
—
—
—
—
SIDL
—
—
—
FEDGE
31:16
24/8
23/7
22/6
21/5
—
—
—
—
C32
ICTMR
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
31:16
18/2
—
—
—
ICOV
ICBNE
17/1
16/0
—
—
ICM
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
31:16
xxxx
xxxx
—
—
ICI
—
—
ICOV
ICBNE
—
—
—
ICM
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
31:16
xxxx
xxxx
—
—
ICI
—
—
ICOV
ICBNE
—
—
—
ICM
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
31:16
xxxx
xxxx
—
—
ICI
—
—
ICOV
ICBNE
—
—
—
ICM
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
31:16
xxxx
xxxx
—
—
ICI
—
—
ICOV
ICBNE
—
—
—
ICM
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
IC16BUF
0000
0000
xxxx
xxxx
—
—
ICI
—
—
ICOV
ICBNE
—
—
—
ICM
0000
0000
xxxx
IC15BUF
15:0
0000
0000
IC14BUF
15:0
0000
0000
IC13BUF
15:0
0000
0000
IC12BUF
15:0
0000
0000
IC11BUF
15:0
15:0
19/3
IC10BUF
15:0
31:16
ICI
20/4
xxxx
—
—
ICI
—
—
ICOV
ICBNE
—
—
ICM
—
0000
0000
xxxx
xxxx
DS60001402H-page 304
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more information.
PIC32MK GP/MC Family
3810
31/15
All Resets
Bit Range
3200 IC10CON(1)
3410
INPUT CAPTURE 10 THROUGH INPUT CAPTURE 16 REGISTER MAP
Bits
Register
Name
2016-2021 Microchip Technology Inc.
TABLE 18-3:
PIC32MK GP/MC Family
ICXCON: INPUT CAPTURE ‘x’ CONTROL REGISTER (‘x’ = 1-16)
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
—
SIDL
—
—
—
FEDGE
C32
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
ICOV
ICBNE
ON
R/W-0
(1)
ICTMR
ICI
ICM
Legend:
R = Readable bit
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = unknown)
U = Unimplemented bit
P = Programmable bit
r = Reserved bit
bit 31-16
Unimplemented: Read as ‘0’
bit 15
ON: Input Capture Module Enable bit
1 = Module enabled
0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Control bit
1 = Halt in CPU Idle mode
0 = Continue to operate in CPU Idle mode
bit 12-10
Unimplemented: Read as ‘0’
bit 9
FEDGE: First Capture Edge Select bit (only used in mode 6, ICM = 110)
1 = Capture rising edge first
0 = Capture falling edge first
bit 8
C32: 32-bit Capture Select bit
1 = 32-bit timer resource capture
0 = 16-bit timer resource capture
bit 7
ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON) is ‘1’)(1)
0 = Timery is the counter source for capture
1 = Timerx is the counter source for capture
bit 6-5
ICI: Interrupt Control bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4
ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
bit 3
ICBNE: Input Capture Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty; at least one more capture value can be read
0 = Input capture buffer is empty
Note 1:
Refer to Table 18-1 for Timerx and Timery selections.
2016-2021 Microchip Technology Inc.
DS60001402H-page 305
PIC32MK GP/MC Family
ICXCON: INPUT CAPTURE ‘x’ CONTROL REGISTER (‘x’ = 1-16) (CONTINUED)
bit 2-0
Note 1:
ICM: Input Capture Mode Select bits
111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter
101 = Prescaled Capture Event mode – every sixteenth rising edge
100 = Prescaled Capture Event mode – every fourth rising edge
011 = Simple Capture Event mode – every rising edge
010 = Simple Capture Event mode – every falling edge
001 = Edge Detect mode – every edge (rising and falling)
000 = Input Capture module is disabled
Refer to Table 18-1 for Timerx and Timery selections.
DS60001402H-page 306
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
NOTES:
2016-2021 Microchip Technology Inc.
DS60001402H-page 307
PIC32MK GP/MC Family
19.0
Note:
OUTPUT COMPARE
When a match occurs, the Output Compare module
generates an event based on the selected mode of
operation.
This data sheet summarizes the features
of the PIC32MK GP/MC family of devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section
16.
“Output
Compare”
(DS60001111), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The following are some of the key features of the
Output Compare:
• Multiple Output Compare modules in a device
• Programmable interrupt generation on compare
event
• Single and Dual Compare modes
• Single and continuous output pulse generation
• Pulse-Width Modulation (PWM) mode
• Hardware-based PWM Fault detection and
automatic output disable
• Programmable selection of 16-bit or 32-bit time
bases
• Can operate from either of two available 16-bit
time bases or a single 32-bit time base
• ADC event trigger for OC1 through OC4
The Output Compare module is used to generate a
single pulse or a train of pulses in response to selected
time base events.
For all modes of operation, the Output Compare module compares the values stored in the OCxR and/or the
OCxRS registers to the value in the selected timer.
FIGURE 19-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit OCxIF(1)
OCxRS(1)
Trigger to ADC(4)
Output
Logic
OCxR(1)
3
OCM
Mode Select
Comparator
0
16/32
PBCLKx
(‘x’ = 2, 3)(5)
Timerx(3)
1
OCTSEL
0
S
R
Output
Enable
Q
OCx(1)
Output Enable
Logic
OCFA or
OCFB(2)
1
16/32
Timery(3)
Timerx(3)
Rollover
Timery(3)
Rollover
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels, 1
through 9.
2: The OCFA pin controls the OCMP1-OCMP3, OCMP7-OCMP9, and OCMP13-OCMP15 channels. The OCFB pin
controls the OCMP4-OCMP6, OCMP10-OCMP12, and OCMP16 channels.
3: Refer to Table 19-1 for Timerx and Timery selections.
4: The ADC event trigger is only available on OC1 through OC4.
5: PBCLK2 = Output Compare 1 through Output Compare 9; PBCLK3 = Output Compare 10 through Output Compare 16.
DS60001402H-page 308
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
The timer source for each Output Compare module
depends on the setting of the OCACLK bit in the
CFGCON register, the OC32 bit in the OCxCON
register, and the OCTSEL bit in the OCxCON register.
The available configurations are shown in Table 19-1.
TABLE 19-1:
OCx
OC1-OC3
TIMER SOURCE CONFIGURATIONS
OCACLK
OC32
OCTSEL
CFGCON
(OCxCON
OCxCON
0
0
1
1
OC4-OC6,
OC13-OC16
0
0
1
1
OC7-OC9
0
0
1
1
OC10-OC12
0
0
1
1
2016-2021 Microchip Technology Inc.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output Compare
Timerx
Timery
TMR2
—
TMR2
1
—
TMR3
TMR3
0
TMR2
—
TMR2
1
—
TMR2
TMR2
0
TMR4
—
TMR4
1
—
TMR5
TMR5
0
TMR4
—
TMR4
1
—
TMR4
TMR4
0
TMR2
—
TMR2
1
—
TMR3
TMR3
0
TMR2
—
TMR2
1
—
TMR2
TMR2
0
TMR2
—
TMR2
1
—
TMR3
TMR3
0
TMR2
—
TMR2
1
—
TMR2
TMR2
0
TMR2
—
TMR2
1
—
TMR3
TMR3
0
TMR2
—
TMR2
1
—
TMR2
TMR2
0
TMR6
—
TMR6
1
—
TMR7
TMR7
0
TMR6
—
TMR6
1
—
TMR6
TMR6
0
TMR2
—
TMR2
1
—
TMR3
TMR3
0
TMR2
—
TMR2
1
—
TMR2
TMR2
0
TMR8
—
TMR8
1
—
TMR9
TMR9
0
TMR8
—
TMR8
1
—
TMR8
TMR8
0
Timer Source
DS60001402H-page 309
Output Compare Control Registers
TABLE 19-2:
4020
4200
4210
4220
4400
4420
OC3RS
4600
OC4CON
4610
OC4R
4620
OC4RS
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OC32
—
OCFLT
—
OCTSEL
—
—
OCM
—
—
—
—
OC32
—
OCFLT
—
OCTSEL
—
—
OCM
—
—
—
—
OC32
—
OCFLT
—
OCTSEL
—
—
OCM
—
—
—
—
OC32
—
OCFLT
—
OCTSEL
—
—
OCM
—
OC1R
OC1RS
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
31:16
15:0
—
—
OC2R
OC2RS
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
OC3R
31:16
15:0
31:16
15:0
31:16
15:0
—
—
OC3RS
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
OC4R
OC4RS
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT OCTSEL
OCM
31:16
4810
OC5R
OC5R
15:0
31:16
4820 OC5RS
OC5RS
15:0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
4800
DS60001402H-page 310
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
OC5CON
PIC32MK GP/MC Family
4410
31:16
15:0
31:16
OC1R
15:0
31:16
OC1RS
15:0
31:16
OC2CON
15:0
31:16
OC2R
15:0
31:16
OC2RS
15:0
31:16
OC3CON
15:0
31:16
OC3R
15:0
31/15
All Resets
OC1CON
Bit Range
Register
Name(1)
4000
4010
OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 9 REGISTER MAP
Bits
Virtual Address
BF82_#
2016-2021 Microchip Technology Inc.
19.1
31:16
15:0
31:16
4A10
OC6R
15:0
31:16
4A20 OC6RS
15:0
31:16
4C00 OC7CON
15:0
31:16
4C10
OC7R
15:0
31:16
4C20 OC7RS
15:0
31:16
4E00 OC8CON
15:0
31:16
4E10
OC8R
15:0
4A00 OC6CON
4E20
OC8RS
31:16
15:0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OC32
—
OCFLT
—
OCTSEL
—
—
OCM
—
—
—
—
OC32
—
OCFLT
—
OCTSEL
—
—
OCM
—
—
—
—
OC32
—
OCFLT
—
OCTSEL
—
—
OCM
—
OC6R
OC6RS
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
OC7R
OC7RS
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
OC8R
OC8RS
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
BF82_#
OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 9 REGISTER MAP (CONTINUED)
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT OCTSEL
OCM
31:16
5010
OC9R
OC9R
15:0
31:16
5020 OC9RS
OC9RS
xxxx
15:0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
5000
OC9CON
PIC32MK GP/MC Family
DS60001402H-page 311
TABLE 19-2:
2016-2021 Microchip Technology Inc.
5210
OC10R
OC10RS
5400 OC11CON
5410
OC11R
5600 OC12CON
OC12R
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
15:0
ON
—
—
—
—
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
OC32
31:16
5810
OC13R
OC13RS
5A00 OC14CON
DS60001402H-page 312
5A10
OC14R
OC14RS
21/5
20/4
19/3
18/2
—
—
—
OCFLT
OCTSEL
31:16
0000
xxxx
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM
xxxx
xxxx
xxxx
OC11RS
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM
xxxx
xxxx
xxxx
OC12RS
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM
31:16
xxxx
xxxx
xxxx
OC13RS
15:0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
OC14R
OC14RS
0000
0000
OC13R
15:0
0000
0000
OC12R
15:0
0000
0000
OC11R
15:0
0000
xxxx
—
15:0
—
xxxx
31:16
31:16
—
OCM
OC10RS
15:0
15:0
16/0
OC10R
15:0
31:16
17/1
All Resets
29/13
31:16
OC12RS
15:0
5800 OC13CON
5A20
30/14
—
—
OCM
—
0000
0000
xxxx
xxxx
xxxx
xxxx
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
5610
5820
31/15
31:16
OC11RS
15:0
5420
5620
Bit Range
Register
Name(1)
5200 OC10CON
5220
OUTPUT COMPARE 10 THROUGH OUTPUT COMPARE 16 REGISTER MAP
Bits
Virtual Address
BF84_#
2016-2021 Microchip Technology Inc.
TABLE 19-3:
5C10
OC15R
OC15RS
5E00 OC16CON
5E10
5E20
OC16R
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
15:0
ON
—
—
—
—
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
OC32
31:16
21/5
20/4
19/3
18/2
—
—
—
OCFLT
OCTSEL
31:16
—
0000
xxxx
xxxx
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
OC16R
OC16RS
0000
xxxx
31:16
31:16
OC16RS
15:0
—
OCM
OC15RS
15:0
15:0
16/0
OC15R
15:0
31:16
17/1
All Resets
Bit Range
Register
Name(1)
Virtual Address
BF84_#
Bits
5C00 OC15CON
5C20
OUTPUT COMPARE 10 THROUGH OUTPUT COMPARE 16 REGISTER MAP (CONTINUED)
—
—
OCM
—
0000
0000
xxxx
xxxx
xxxx
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
DS60001402H-page 313
TABLE 19-3:
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 19-1:
Bit
Range
31:24
23:16
15:8
7:0
OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER (‘x’ = 1-16)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ON
—
SIDL
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
OC32
R-0, HS, HC
(1)
OCFLT
OCTSEL(2)
OCM
Legend:
HS = Set in hardware
HC = Cleared by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Output Compare Peripheral On bit
1 = Output Compare peripheral is enabled
0 = Output Compare peripheral is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters Idle mode
0 = Continue operation in Idle mode
bit 12-6
Unimplemented: Read as ‘0’
bit 5
OC32: 32-bit Compare Mode bit
1 = OCxR and/or OCxRS are used for comparisons to the 32-bit timer source
0 = OCxR and OCxRS are used for comparisons to the 16-bit timer source
bit 4
OCFLT: PWM Fault Condition Status bit(1)
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred
bit 3
OCTSEL: Output Compare Timer Select bit(2)
1 = Timery is the clock source for this Output Compare module
0 = Timerx is the clock source for this Output Compare module
bit 2-0
OCM: Output Compare Mode Select bits
111 = PWM mode on OCx; Fault pin enabled
110 = PWM mode on OCx; Fault pin disabled
101 = Initialize OCx pin low; generate continuous output pulses on OCx pin
100 = Initialize OCx pin low; generate single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initialize OCx pin high; compare event forces OCx pin low
001 = Initialize OCx pin low; compare event forces OCx pin high
000 = Output compare peripheral is disabled but continues to draw current
Note 1:
2:
This bit is only used when OCM = ‘111’. It is read as ‘0’ in all other modes.
Refer to Table 19-1 for Timerx and Timery selections.
DS60001402H-page 314
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
NOTES:
2016-2021 Microchip Technology Inc.
DS60001402H-page 315
PIC32MK GP/MC Family
The SPI/I2S module is compatible with Motorola® SPI
and SIOP interfaces.
20.0 SERIAL PERIPHERAL
INTERFACE (SPI) AND
INTER-IC SOUND (I2S)
Note:
The following are some of the key features of the SPI
module:
This data sheet summarizes the
features of the PIC32MK GP/MC family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 23. “Serial
Peripheral
Interface
(SPI)”
(DS60001106), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
•
•
•
•
•
Host and Client modes support
Four different clock formats
Enhanced Framed SPI protocol support
User-configurable 32/24/16/8-bit data width
Separate SPI FIFO buffers for receive and transmit
- FIFO buffers act as 4/8/16-level deep FIFOs
based on 32/24/16/8-bit data width
• Programmable interrupt event on every 8-bit,
16-bit and 32-bit data transfer
• Operation during Sleep and Idle modes
• Audio codec support:
- I2S protocol
- Left-justified
- Right-justified
- PCM
The SPI/I2S module is a synchronous serial interface
that is useful for communicating with external
peripherals and other microcontroller devices, as well
as digital audio devices. These peripheral devices may
be Serial EEPROMs, Shift registers, display drivers,
analog-to-digital converters (ADC), etc.
SPI/I2S MODULE BLOCK DIAGRAM
FIGURE 20-1:
Internal
Data Bus
SPIxBUF
Read
Write
SPIxRXB FIFO
FIFOs Share Address SPIxBUF
SPIxTXB FIFO
Transmit
Receive
SPIxSR
SDIx
bit 0
SDOx
SSx/FSYNC
Client Select
and Frame
Sync Control
Shift
Control
Clock
Control
MCLKSEL
Edge
Select
SCKx
REFCLKO1
Baud Rate
Generator
PBCLK2 (SPI1-SPI2)
PBCLK3 (SPI3-SPI6)
MSTEN
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.
DS60001402H-page 316
2016-2021 Microchip Technology Inc.
SPI Control Registers
SPI1 AND SPI2 REGISTER MAP
7000 SPI1CON
7010 SPI1STAT
7020 SPI1BUF
7030 SPI1BRG
7040 SPI1CON2
7200 SPI2CON
7210 SPI2STAT
7220 SPI2BUF
7230 SPI2BRG
7240 SPI2CON2
31/15
30/14
29/13
28/12
27/11
31:16 FRMEN FRMSYNC FRMPOL
MSSEN
FRMSYPW
15:0
ON
—
SIDL
DISSDO
MODE32
31:16
—
—
—
15:0
—
—
—
26/10
25/9
24/8
FRMCNT
MODE16
SMP
23/7
SPIBUSY
—
—
20/4
—
—
—
SSEN
CKP
MSTEN
DISSDI
—
—
—
SRMT
SPIROV
SPIRBE
SPITUR
31:16
21/5
MCLKSEL
CKE
RXBUFELM
FRMERR
22/6
19/3
18/2
17/1
—
—
SPIFE
STXISEL
16/0
ENHBUF 0000
SRXISEL
TXBUFELM
—
SPITBE
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
—
—
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
31:16 FRMEN FRMSYNC FRMPOL
MSSEN
FRMSYPW
DISSDO
MODE32
SPI
15:0
SGNEXT
—
15:0
ON
—
SIDL
31:16
—
—
—
15:0
—
—
—
—
—
—
—
—
SPIRBF 0028
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRG
—
IGNROV
—
MODE16
SMP
—
AUDEN
—
—
—
—
—
—
—
SSEN
CKP
MSTEN
DISSDI
—
—
—
SRMT
SPIROV
SPIRBE
CKE
SPIBUSY
—
—
31:16
SPITUR
AUDMOD
SPIFE
STXISEL
SRXISEL
TXBUFELM
—
SPITBE
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
—
—
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
SPI
15:0
SGNEXT
—
—
—
—
—
—
—
IGNROV
—
IGNTUR
—
AUDEN
0C00
0000
0000
SPITBF
SPIRBF 0028
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AUD
MONO
—
BRG
—
0000
ENHBUF 0000
DATA
15:0
0000
0000
MCLKSEL
RXBUFELM
FRMERR
—
AUD
MONO
IGNTUR
FRMCNT
0000
0000
SPITBF
DATA
15:0
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF82_#)
TABLE 20-1:
—
—
0000
0000
—
AUDMOD
0000
0C00
2016-2021 Microchip Technology Inc.
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table except SPIxBUF have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV
Registers” for more information.
PIC32MK GP/MC Family
DS60001402H-page 317
20.1
SPI3 THROUGH SPI6 REGISTER MAP
7400 SPI3CON
7410 SPI3STAT
7420 SPI3BUF
7430 SPI3BRG
7440 SPI3CON2
7600 SPI4CON
7610 SPI4STAT
7630 SPI4BRG
7640 SPI4CON2
7800 SPI5CON
7810 SPI5STAT
7820 SPI5BUF
DS60001402H-page 318
7830 SPI5BRG
7840 SPI5CON2
30/14
29/13
28/12
27/11
31:16 FRMEN FRMSYNC FRMPOL
MSSEN
FRMSYPW
15:0
ON
—
SIDL
DISSDO
MODE32
31:16
—
—
—
15:0
—
—
—
26/10
25/9
24/8
FRMCNT
MODE16
SMP
23/7
SPIBUSY
—
—
20/4
—
—
—
SSEN
CKP
MSTEN
DISSDI
—
—
—
SRMT
SPIROV
SPIRBE
SPITUR
31:16
21/5
MCLKSEL
CKE
RXBUFELM
FRMERR
22/6
19/3
18/2
17/1
—
—
SPIFE
STXISEL
16/0
ENHBUF 0000
SRXISEL
TXBUFELM
—
SPITBE
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
—
—
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
31:16 FRMEN FRMSYNC FRMPOL
MSSEN
FRMSYPW
DISSDO
MODE32
SPI
15:0
SGNEXT
—
15:0
ON
—
SIDL
31:16
—
—
—
15:0
—
—
—
—
—
—
—
—
SPIRBF 0028
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRG
—
IGNROV
—
MODE16
—
SMP
AUDEN
—
—
—
—
—
—
—
SSEN
CKP
MSTEN
DISSDI
—
—
—
SRMT
SPIROV
SPIRBE
CKE
SPIBUSY
—
—
SPITUR
31:16
AUDMOD
SPIFE
STXISEL
SRXISEL
TXBUFELM
—
SPITBE
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
—
—
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
31:16 FRMEN FRMSYNC FRMPOL
MSSEN
FRMSYPW
15:0
ON
—
SIDL
DISSDO
MODE32
31:16
—
—
—
15:0
—
—
—
SPI
15:0
SGNEXT
—
—
—
—
—
—
IGNROV
SPIRBF 0028
0000
—
FRMCNT
MODE16
SMP
—
IGNTUR
—
—
—
—
—
—
—
—
—
—
—
—
—
AUD
MONO
SPIBUSY
—
—
31:16
—
—
—
—
—
—
—
—
SSEN
CKP
MSTEN
DISSDI
—
—
—
SRMT
SPIROV
SPIRBE
SPITUR
AUDMOD
SPIFE
STXISEL
TXBUFELM
—
SPITBE
—
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
31:16
—
—
—
—
—
—
—
—
—
15:0
SPI
SGNEXT
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
IGNROV
IGNTUR
AUDEN
0000
0C00
ENHBUF 0000
SRXISEL
0000
0000
SPITBF
SPIRBF 0028
0000
DATA
15:0
0000
0000
MCLKSEL
RXBUFELM
FRMERR
—
AUDEN
CKE
0000
0000
—
—
0C00
0000
SPITBF
BRG
—
0000
ENHBUF 0000
DATA
15:0
0000
0000
MCLKSEL
RXBUFELM
FRMERR
—
AUD
MONO
IGNTUR
FRMCNT
0000
0000
SPITBF
DATA
15:0
All Resets
31/15
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AUD
MONO
—
BRG
0000
0000
AUDMOD
0000
0C00
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table except SPIxBUF have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV
Registers” for more information.
PIC32MK GP/MC Family
7620 SPI4BUF
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF84_#)
2016-2021 Microchip Technology Inc.
TABLE 20-2:
7A00 SPI6CON
7A10 SPI6STAT
7A20 SPI6BUF
7A30 SPI6BRG
7A40 SPI6CON2
31/15
30/14
29/13
28/12
27/11
31:16 FRMEN FRMSYNC FRMPOL
MSSEN
FRMSYPW
15:0
ON
—
SIDL
DISSDO
MODE32
31:16
—
—
—
15:0
—
—
—
26/10
25/9
24/8
FRMCNT
MODE16
SMP
23/7
SPIBUSY
—
—
31:16
21/5
20/4
MCLKSEL
—
—
—
SSEN
CKP
MSTEN
DISSDI
—
—
—
SRMT
SPIROV
SPIRBE
CKE
RXBUFELM
FRMERR
22/6
SPITUR
19/3
18/2
17/1
—
—
SPIFE
STXISEL
16/0
ENHBUF 0000
SRXISEL
TXBUFELM
—
SPITBE
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
—
—
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
SPI
15:0
SGNEXT
—
—
—
—
—
—
—
SPIRBF 0028
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AUD
MONO
—
BRG
—
IGNROV
—
IGNTUR
—
AUDEN
0000
0000
SPITBF
DATA
15:0
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF84_#)
SPI3 THROUGH SPI6 REGISTER MAP (CONTINUED)
—
—
0000
0000
—
AUDMOD
0000
0C00
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table except SPIxBUF have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV
Registers” for more information.
PIC32MK GP/MC Family
DS60001402H-page 319
TABLE 20-2:
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 20-1:
Bit
Range
31:24
23:16
15:8
7:0
SPIxCON: SPI CONTROL REGISTER (x=1-6)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMEN
FRMSYNC
FRMPOL
MSSEN
FRMSYPW
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
FRMCNT
R/W-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
MCLKSEL(1)
—
—
—
—
—
SPIFE
ENHBUF(1)
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ON
—
SIDL
DISSDO(4)
MODE32
MODE16
SMP
CKE(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEN
CKP(3)
MSTEN
DISSDI(4)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
STXISEL
SRXISEL
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
FRMEN: Framed SPI Support bit
1 = Framed SPI support is enabled (The SSx pin used as FSYNC input/output)
0 = Framed SPI support is disabled
bit 30
FRMSYNC: Frame Sync Pulse Direction Control on the SSx pin bit (Framed SPI mode only)
1 = Frame sync pulse input (Client mode)
0 = Frame sync pulse output (Host mode)
bit 29
FRMPOL: Frame Sync/Client Select Polarity bit (Framed SPI or Host Transmit modes only)
1 = Frame pulse or the SSx pin is active-high
0 = Frame pulse or the SSx pin is active-low
bit 28
MSSEN: Host Mode Client Select Enable bit
1 = Client select SPI support enabled. The SS pin is automatically driven during transmission in
Host mode. Polarity is determined by the FRMPOL bit.
0 = Client select SPI support is disabled.
bit 27
FRMSYPW: Frame Sync Pulse Width bit
1 = Frame sync pulse is one character wide
0 = Frame sync pulse is one clock wide
bit 26-24 FRMCNT: Frame Sync Pulse Counter bits
Controls the number of data characters transmitted per pulse. This bit is only valid in Framed mode.
111 = Reserved
110 = Reserved
101 = Generate a frame sync pulse on every 32 data characters
100 = Generate a frame sync pulse on every 16 data characters
011 = Generate a frame sync pulse on every 8 data characters
010 = Generate a frame sync pulse on every 4 data characters
001 = Generate a frame sync pulse on every 2 data characters
000 = Generate a frame sync pulse on every data character
bit 23
MCLKSEL: Host Clock Enable bit(1)
1 = REFCLKO1 is used by the Baud Rate Generator
0 = PBCLK2 is used by the Baud Rate Generator for SPI1 and SPI2 or PBCLK3 if SPI3 through SPI6
bit 22-18 Unimplemented: Read as ‘0’
Note 1: This bit can only be written when the ON bit = 0. Refer to 36.0 “Electrical Characteristics” for maximum
clock frequency requirements.
2: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
3: When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual
value of the CKP bit.
4: This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see
13.3 “Peripheral Pin Select (PPS)” for more information).
DS60001402H-page 320
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 20-1:
SPIxCON: SPI CONTROL REGISTER (CONTINUED)(x=1-6)
bit 17
SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only)
1 = Frame synchronization pulse coincides with the first bit clock
0 = Frame synchronization pulse precedes the first bit clock
bit 16
ENHBUF: Enhanced Buffer Enable bit(1)
1 = Enhanced Buffer mode is enabled
0 = Enhanced Buffer mode is disabled
bit 15
ON: SPI/I2S Module On bit
1 = SPI/I2S module is enabled
0 = SPI/I2S module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters in Idle mode
0 = Continue operation in Idle mode
bit 12
DISSDO: Disable SDOx pin bit(4)
1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register
0 = SDOx pin is controlled by the module
bit 11-10 MODE: 32/16-Bit Communication Select bits
When AUDEN = 1:
MODE32
MODE16
Communication
1
1
24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
1
0
32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
0
1
16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame
0
0
16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame
When AUDEN = 0:
MODE32
MODE16
Communication
1
x
32-bit
0
1
16-bit
0
0
8-bit
SMP: SPI Data Input Sample Phase bit
Host mode (MSTEN = 1):
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Client mode (MSTEN = 0):
SMP value is ignored when SPI is used in Client mode. The module always uses SMP = 0.
CKE: SPI Clock Edge Select bit(2)
1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
SSEN: Client Select Enable (Client mode) bit
1 = SSx pin used for Client mode
0 = SSx pin not used for Client mode, pin controlled by port function.
CKP: Clock Polarity Select bit(3)
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 9
bit 8
bit 7
bit 6
Note 1:
2:
3:
4:
This bit can only be written when the ON bit = 0. Refer to 36.0 “Electrical Characteristics” for maximum
clock frequency requirements.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual
value of the CKP bit.
This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see
13.3 “Peripheral Pin Select (PPS)” for more information).
2016-2021 Microchip Technology Inc.
DS60001402H-page 321
PIC32MK GP/MC Family
REGISTER 20-1:
bit 5
SPIxCON: SPI CONTROL REGISTER (CONTINUED)(x=1-6)
MSTEN: Host Mode Enable bit
1 = Host mode
0 = Client mode
DISSDI: Disable SDI bit(4)
1 = SDI pin is not used by the SPI module (pin is controlled by PORT function)
0 = SDI pin is controlled by the SPI module
STXISEL: SPI Transmit Buffer Empty Interrupt Mode bits
11 = Interrupt is generated when the buffer is not full (has one or more empty elements)
10 = Interrupt is generated when the buffer is empty by one-half or more
01 = Interrupt is generated when the buffer is completely empty
00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are
complete
SRXISEL: SPI Receive Buffer Full Interrupt Mode bits
11 = Interrupt is generated when the buffer is full
10 = Interrupt is generated when the buffer is full by one-half or more
01 = Interrupt is generated when the buffer is not empty
00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)
bit 4
bit 3-2
bit 1-0
Note 1:
2:
3:
4:
This bit can only be written when the ON bit = 0. Refer to 36.0 “Electrical Characteristics” for maximum
clock frequency requirements.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual
value of the CKP bit.
This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see
13.3 “Peripheral Pin Select (PPS)” for more information).
DS60001402H-page 322
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 20-2:
Bit
Range
31:24
23:16
15:8
7:0
SPIxCON2: SPI CONTROL REGISTER 2 (x=1-6)
Bit
31/23/15/7
Bit
Bit
30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
Bit
Bit
26/18/10/2 25/17/9/1 24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
SPISGNEXT
—
—
FRMERREN
SPIROVEN
R/W-0
U-0
U-0
U-0
R/W-0
U-0
AUDEN(1)
—
—
—
AUDMONO(1,2)
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
SPITUREN IGNROV
R/W-0
IGNTUR
R/W-0
AUDMOD(1,2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
SPISGNEXT: Sign Extend Read Data from the RX FIFO bit
1 = Data from RX FIFO is sign extended
0 = Data from RX FIFO is not sign extended
bit 14-13 Unimplemented: Read as ‘0’
bit 12
FRMERREN: Enable Interrupt Events via FRMERR bit
1 = Frame Error overflow generates error events
0 = Frame Error does not generate error events
bit 11
SPIROVEN: Enable Interrupt Events via SPIROV bit
1 = Receive overflow generates error events
0 = Receive overflow does not generate error events
bit 10
SPITUREN: Enable Interrupt Events via SPITUR bit
1 = Transmit Underrun Generates Error Events
0 = Transmit Underrun Does Not Generates Error Events
bit 9
IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions)
1 = A ROV is not a critical error; during ROV data in the FIFO is not overwritten by receive data
0 = A ROV is a critical error which stop SPI operation
bit 8
IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions)
1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty
0 = A TUR is a critical error which stop SPI operation
bit 7
AUDEN: Enable Audio CODEC Support bit(1)
1 = Audio protocol enabled
0 = Audio protocol disabled
bit 6-5
Unimplemented: Read as ‘0’
bit 3
AUDMONO: Transmit Audio Data Format bit(1,2)
1 = Audio data is mono (Each data word is transmitted on both left and right channels)
0 = Audio data is stereo
bit 2
Unimplemented: Read as ‘0’
bit 1-0
AUDMOD: Audio Protocol Mode bit(1,2)
11 = PCM/DSP mode
10 = Right Justified mode
01 = Left Justified mode
00 = I2S mode
Note 1:
2:
This bit can only be written when the ON bit = 0.
This bit is only valid for AUDEN = 1.
2016-2021 Microchip Technology Inc.
DS60001402H-page 323
PIC32MK GP/MC Family
REGISTER 20-3:
Bit
Range
31:24
23:16
15:8
7:0
SPIxSTAT: SPI STATUS REGISTER (x=1-6)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
R/C-0, HS
R-0, HS, HC
U-0
U-0
R-0
—
—
—
FRMERR
SPIBUSY
—
—
SPITUR
R-0, HS, HC
R/C-0, HS
R-1, HS, HC
U-0
R-1, HS, HC
U-0
R-0, HS, HC
R-0, HS, HC
SRMT
SPIROV
SPIRBE
—
SPITBE
—
SPITBF
SPIRBF
Legend:
RXBUFELM
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
TXBUFELM
HC = Cleared in hardware HS = Set in hardware
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 RXBUFELM: Receive Buffer Element Count bits (valid only when ENHBUF = 1)
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFELM: Transmit Buffer Element Count bits (valid only when ENHBUF = 1)
bit 15-13 Unimplemented: Read as ‘0’
bit 12
FRMERR: SPI Frame Error status bit
1 = Frame error detected
0 = No Frame error detected
This bit is only valid when FRMEN = 1.
bit 11
SPIBUSY: SPI Activity Status bit
1 = SPI peripheral is currently busy with some transactions
0 = SPI peripheral is currently idle
bit 10-9
Unimplemented: Read as ‘0’
bit 8
SPITUR: Transmit Under Run bit
1 = Transmit buffer has encountered an underrun condition
0 = Transmit buffer has no underrun condition
This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling
the module.
bit 7
SRMT: Shift Register Empty bit (valid only when ENHBUF = 1)
1 = When SPI module shift register is empty
0 = When SPI module shift register is not empty
bit 6
SPIROV: Receive Overflow Flag bit
1 = A new data is completely received and discarded. The user software has not read the previous data in
the SPIxBUF register.
0 = No overflow has occurred
This bit is set in hardware; can only be cleared (= 0) in software.
bit 5
SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1)
1 = RX FIFO is empty (CRPTR = SWPTR)
0 = RX FIFO is not empty (CRPTR SWPTR)
bit 4
Unimplemented: Read as ‘0’
DS60001402H-page 324
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 20-3:
SPIxSTAT: SPI STATUS REGISTER (CONTINUED)(x=1-6)
bit 3
SPITBE: SPI Transmit Buffer Empty Status bit
1 = Transmit buffer, SPIxTXB is empty
0 = Transmit buffer, SPIxTXB is not empty
Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR.
Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.
bit 2
Unimplemented: Read as ‘0’
bit 1
SPITBF: SPI Transmit Buffer Full Status bit
1 = Transmit not yet started, SPITXB is full
0 = Transmit buffer is not full
Standard Buffer Mode:
Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB.
Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR.
Enhanced Buffer Mode:
Set when CWPTR + 1 = SRPTR; cleared otherwise
bit 0
SPIRBF: SPI Receive Buffer Full Status bit
1 = Receive buffer, SPIxRXB is full
0 = Receive buffer, SPIxRXB is not full
Standard Buffer Mode:
Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer Mode:
Set when SWPTR + 1 = CRPTR; cleared otherwise
2016-2021 Microchip Technology Inc.
DS60001402H-page 325
PIC32MK GP/MC Family
REGISTER 20-4:
Bit Range
SPIxBUF: SPIx BUFFER REGISTER (‘x’ = 1-6)
Bit
31/23/15/7
Bit
30/22/14/6
R/W-0
R/W-0
31:24
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
R/W-0
R/W-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATA
R/W-0
23:16
R/W-0
R/W-0
R/W-0
R/W-0
DATA
R/W-0
15:8
R/W-0
R/W-0
R/W-0
R/W-0
DATA
R/W-0
7:0
R/W-0
R/W-0
R/W-0
R/W-0
DATA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
DATA FIFO Data bits
When MODE32 or MODE16 selects 32-bit data, the SPI uses DATA.
When MODE32 or MODE16 selects 24-bit data, the SPI only uses DATA.
When MODE32 or MODE16 selects 16-bit data, the SPI only uses DATA.
When MODE32 or MODE16 selects 8-bit data, the SPI only uses DATA.
REGISTER 20-5:
Bit Range
x = Bit is unknown
SPIxBRG: SPIx BAUD RATE GENERATOR REGISTER (‘x’ = 1-6)
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
31:24
23:16
15:8
7:0
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
R/W-0
BRG
R/W-0
BRG
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13
Unimplemented: Read as ‘0’
bit 12-0
BRG Baud Rate Generator Divisor bits
Baud Rate = FPBCLKx / (2 * (SPIxBRG + 1)), where x = 2 and 3, (FPBCLK2 for SPI1-SPI2, FPBCLK3
for SPI3-SPI6.) Therefore, the maximum baud rate possible is FPBCLKx / 2 (SPIXBRG = 0) and the
minimum baud rate possible is FPBCLKx / 16384.
Note:
DS60001402H-page 326
Changing the BRG value when the ON bit is equal to ‘1’ causes undefined behavior.
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
NOTES:
2016-2021 Microchip Technology Inc.
DS60001402H-page 327
PIC32MK GP/MC Family
21.0
INTER-INTEGRATED CIRCUIT
(I2C)
The I2C software library is available in MPLAB
Harmony. If the user application is to implement I2C, for
future device pin compatibility, it is recommended to
assign software I2C functions according to the details
provided in the device pin tables (Table 3 through
Table 6):
• For 64-pin packages, refer to Notes 6 and 7 in
Table 3 and Table 4.
• For 100-lead packages, refer to Notes 5 and 6 in
Table 5 and Table 6.
21.1
Software I2C Performance
Table 21-1 provides the performance details of the I2C.
TABLE 21-1:
I2C Baud
Rate
I2C PERFORMANCE
I2C Transactions/
Second
I2C CPU
Utilization
22070 (continuous)
50.76%
16841
38.73%
4079
9.38%
400 kHz
429
0.99%
5581 (continuous)
12.84%
4077
9.38%
429
0.99%
100 kHz
DS60001402H-page 328
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
NOTES:
2016-2021 Microchip Technology Inc.
DS60001402H-page 329
PIC32MK GP/MC Family
22.0
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Note:
This data sheet summarizes the features
of the PIC32MK GP/MC family of devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 21. “Universal Asynchronous
Receiver
Transmitter
(UART)”
(DS60001107), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The UART module is one of the serial I/O modules
available in PIC32MK GP/MC family devices. The
UART is a full-duplex, asynchronous communication
channel that communicates with peripheral devices
and personal computers through protocols, such as
RS-232, RS-485, LIN, and IrDA®. The module also
supports the hardware flow control option, with
UxCTS and UxRTS pins, and also includes an IrDA
encoder and decoder.
The following are key features of the UART module:
• Ability to receive data during Sleep mode
• Full-duplex, 8-bit or 9-bit data transmission
• Even, Odd or No Parity options (for 8-bit data)
• One or two Stop bits
• Auto-baud support
• Four clock source inputs for asynchronous clocking
• Transmit and Receive (TX/RX) polarity control
• Hardware flow control option
• Fully integrated Baud Rate Generator (BRG) with
16-bit prescaler
• Baud rates up to 30 Mbps
• 8-level deep First-In-First-Out (FIFO) transmit data
buffer
• 8-level deep FIFO receive data buffer
• Parity, framing and buffer overrun error detection
• Support for interrupt-only on address detect
(9th bit = 1)
• Separate transmit and receive interrupts
• Loopback mode for diagnostic support
• LIN Protocol support
• IrDA encoder and decoder with 16x baud clock
output for external IrDA encoder/decoder support
Figure 22-1 illustrates a simplified block diagram of the
UART module.
FIGURE 22-1:
UART SIMPLIFIED BLOCK DIAGRAM
REFCLK1
11
FRC
SYSCLK
10
01
PBCLKx(1)
00
Baud Rate Generator
IrDA®
CLKSEL
(UxMODE)
Hardware Flow Control
UxRTS/BCLKx
UxCTS
UxRX
UARTx Receiver
UARTx Transmitter
Note 1:
UxTX
‘x’ = 2 for UART1 and UART2; ‘x’ = 3 for UART3 through UART6.
DS60001402H-page 330
2016-2021 Microchip Technology Inc.
UART Control Registers
Virtual Address
BF82_#
TABLE 22-1:
8010
U1STA
(1)
29/13
31:16
—
—
—
15:0
ON
—
SIDL
31:16
28/12
27/11
26/10
25/9
24/8
23/7
—
—
—
—
—
SLPEN
CKRDY
—
—
—
CLKSEL
RUNOV 0000
IREN
RTSMD
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL
STSEL
UEN
UTXISEL
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
U1BRG(1)
15:0
—
—
—
—
—
—
—
—
31:16
15:0
—
—
—
ON
—
SIDL
8210
U2STA(1)
8220
U2TXREG
8230 U2RXREG
U2BRG(1)
Legend:
—
—
—
IREN
RTSMD
—
—
—
URXISEL
—
—
ADDEN
—
19/3
18/2
17/1
16/0
—
—
—
PERR
FERR
OERR
—
—
—
—
—
—
—
—
—
—
URXDA 0110
UEN
UTXISEL
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
0000
0000
—
—
—
U1BRG
SLPEN
CKRDY
—
—
—
CLKSEL
RUNOV 0000
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL
STSEL
0000
0000
ADDR
UTXINV
0000
0000
Receive Register
—
0000
0000
RIDLE
Transmit Register
ADDRMSK
31:16
15:0
20/4
U1BRG
31:16
15:0
21/5
ADDR
15:0
8200 U2MODE
22/6
ADDRMSK
31:16
U1TXREG
(1)
8240
30/14
15:0
8030 U1RXREG
8040
31/15
All Resets
Register
Name
Bit Range
Bits
8000 U1MODE(1)
8020
UART1 AND UART2 REGISTER MAP
URXISEL
—
—
ADDEN
—
0000
RIDLE
PERR
FERR
OERR
URXDA 0110
—
—
—
—
—
—
—
—
Transmit Register
—
—
—
—
—
—
—
—
0000
0000
Receive Register
—
0000
0000
0000
BRG
BRG
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2016-2021 Microchip Technology Inc.
Note 1:This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more information.
0000
0000
PIC32MK GP/MC Family
DS60001402H-page 331
22.1
Virtual Address
BF84_#
8410
U3STA
(1)
—
—
SIDL
26/10
25/9
24/8
23/7
—
—
—
—
—
SLPEN
CKRDY
—
—
—
CLKSEL
RUNOV 0000
IREN
RTSMD
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL
STSEL
UEN
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
U3BRG(1)
15:0
—
—
—
—
—
—
—
—
U4STA(1)
U4TXREG
8810
U5STA
(1)
UTXISEL
—
—
—
—
—
—
ON
—
SIDL
IREN
RTSMD
—
—
—
UEN
UTXISEL
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
ON
—
SIDL
IREN
RTSMD
—
31:16
—
—
UEN
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
U5BRG(1)
15:0
—
—
—
—
—
—
—
—
DS60001402H-page 332
8A10
Legend:
U6STA(1)
31:16
15:0
UTXISEL
—
—
—
—
—
—
—
ON
—
SIDL
IREN
RTSMD
—
—
—
UEN
ADDEN
RIDLE
PERR
FERR
OERR
—
—
—
—
—
URXDA 0110
—
0000
—
—
—
0000
Transmit Register
—
—
—
—
—
—
—
—
0000
Receive Register
—
0000
BRG
0000
0000
SLPEN
CKRDY
—
—
—
CLKSEL
RUNOV 0000
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL
STSEL
URXISEL
—
—
UTXINV
URXEN
UTXBRK
RIDLE
PERR
FERR
OERR
—
—
—
—
—
URXDA 0110
—
0000
—
—
—
0000
Transmit Register
—
—
—
—
—
—
—
—
0000
Receive Register
—
0000
BRG
0000
0000
SLPEN
CKRDY
—
—
—
CLKSEL
RUNOV 0000
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL
STSEL
URXISEL
—
—
UTXBF
TRMT
0000
0000
ADDEN
RIDLE
PERR
FERR
OERR
—
—
—
—
—
URXDA 0110
—
0000
—
—
—
0000
Transmit Register
—
—
—
—
—
—
—
—
0000
Receive Register
—
0000
BRG
0000
0000
SLPEN
CKRDY
—
—
—
CLKSEL
RUNOV 0000
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL
STSEL
ADDR
UTXEN
0000
0000
ADDEN
MASK
UTXISEL
0000
0000
BRG
31:16
15:0
16/0
ADDR
—
8A00 U6MODE(1)
—
MASK
—
8830 U5RXREG
17/1
BRG
31:16
U5TXREG
18/2
ADDR
—
15:0
URXISEL
MASK
31:16
31:16
15:0
19/3
BRG
31:16
15:0
20/4
URXISEL
ADDEN
RIDLE
PERR
0000
0000
FERR
OERR
URXDA 0110
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more information.
PIC32MK GP/MC Family
U4BRG
(1)
31:16
15:0
21/5
ADDR
—
U3TXREG
22/6
ADDRMSK
UTXINV
8800 U5MODE(1)
8840
—
27/11
—
8630 U4RXREG
8820
—
ON
28/12
—
8610
8640
29/13
31:16
15:0
8600 U4MODE(1)
8620
30/14
31:16
8430 U3RXREG
8440
31:16
15:0
31/15
All Resets
Bit Range
8400 U3MODE(1)
8420
UART3 THROUGH UART6 REGISTER MAP
Bits
Register
Name
2016-2021 Microchip Technology Inc.
TABLE 22-2:
Virtual Address
BF84_#
31/15
30/14
29/13
28/12
27/11
26/10
25/9
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
15:0
—
—
—
—
31:16
U6BRG(1)
15:0
—
—
—
—
8A30 U6RXREG
Legend:
24/8
23/7
22/6
21/5
—
—
—
—
—
—
TX8
—
—
—
—
—
—
RX8
—
—
—
—
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
0000
—
—
—
0000
Transmit Register
—
—
—
—
—
—
All Resets
Bit Range
Register
Name
Bits
8A20 U6TXREG
8A40
UART3 THROUGH UART6 REGISTER MAP (CONTINUED)
—
—
0000
Receive Register
—
0000
BRG
BRG
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more information.
0000
0000
PIC32MK GP/MC Family
DS60001402H-page 333
TABLE 22-2:
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 22-1:
Bit
Range
31:24
23:16
15:8
7:0
UxMODE: UARTx MODE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R-0, HS, HC
U-0
U-0
U-0
SLPEN
CLKRDY
—
—
—
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
ON
—
SIDL
IREN
RTSMD
—
R-0, HC
R/W-0
R/W-0, HC
R/W-0
R/W-0
R/W-0
WAKE
LPBACK
ABAUD
RXINV
BRGH
Legend:
CLKSEL(1)
R/W-0
R/W-0
RUNOV
R/W-0
UEN(2)
R/W-0
PDSEL
HS = Set by hardware
HC = cleared by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
R/W-0
STSEL
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23
SLPEN: Run During Sleep Enable bit
1 = BRG clock runs during Sleep mode
0 = BRG clock is turned off during Sleep mode
Note:
bit 22
SLPEN = 1 only applies if CLKSEL = FRC, or in some cases, REFCLK depending on the
selected REFCLK input source if running while in Sleep mode. All clocks, as well as the UART
are disabled in Deep Sleep mode.
CLKRDY: USART Clock Status bit
1 = UART clock is ready (User software should not update the UxMODE register)
0 = UART clock is not ready (User software can update the UxMODE register)
bit 21-19 Unimplemented: Read as ‘0’
bit 18-17 CLKSEL: UART Baud Rate Generator Clock Selection bits(1)
11 = BRG clock is REFCLK1
10 = BRG clock is FRC
01 = BRG clock is SYSCLK (off in Sleep mode)
00 = BRG clock is PBCLKx (off in Sleep mode)
bit 16
RUNOV: Run During Overflow Mode bit
1 = Shift register continues to run when Overflow (OERR) condition is detected
0 = Shift register stops accepting new data when Overflow (OERR) condition is detected
bit 15
ON: UARTx Enable bit
1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN and UTXEN
control bits
0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx
registers; UARTx power consumption is minimal
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation in Idle mode
bit 12
IREN: IrDA Encoder and Decoder Enable bit
1 = IrDA is enabled
0 = IrDA is disabled
Note 1:
2:
These bits can be changed only when the ON bit (UxMODE) is set to ‘0’.
These bits are present for legacy compatibility, and are superseded by PPS functionality on these devices
(see 13.3 “Peripheral Pin Select (PPS)” for more information).
DS60001402H-page 334
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 22-1:
UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 11
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
bit 9-8
UEN: UARTx Enable bits(2)
11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by
corresponding bits in the PORTx register
bit 7
WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit
1 = Wake-up is enabled
0 = Wake-up is disabled
bit 6
LPBACK: UARTx Loopback Mode Select bit
1 = Loopback mode is enabled
0 = Loopback mode is disabled
bit 5
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next reception of Sync character (0x55); cleared by hardware
upon completion
0 = Baud rate measurement disabled or completed
bit 4
RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1 = High-Speed mode – 4x baud clock enabled
0 = Standard Speed mode – 16x baud clock enabled
bit 2-1
PDSEL: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0
STSEL: Stop Selection bit
1 = 2 Stop bits
0 = 1 Stop bit
Note 1:
2:
These bits can be changed only when the ON bit (UxMODE) is set to ‘0’.
These bits are present for legacy compatibility, and are superseded by PPS functionality on these devices
(see 13.3 “Peripheral Pin Select (PPS)” for more information).
2016-2021 Microchip Technology Inc.
DS60001402H-page 335
PIC32MK GP/MC Family
REGISTER 22-2:
Bit
Range
31:24
23:16
15:8
7:0
UxSTA: UARTx STATUS AND CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MASK
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR
R/W-0
R/W-0
UTXISEL
R/W-0
R/W-0
URXISEL
R/W-0
R/W-0
R/W-0, HC
R/W-0
R-0
R-1
UTXINV
URXEN
UTXBRK
UTXEN(1)
UTXBF
TRMT
R/W-0
R-1
R-0
R-0
R/W-0, HS
R-0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
Legend:
HS = Set by hardware
HC = cleared by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 MASK: Address Match Mask bits
These bits are used to mask the ADDR bits.
11111111 = Corresponding matching ADDR bits are used to detect the address match
Note:
This setting allows the user to assign individual address as well as a group broadcast address
to a UART.
00000000 = Corresponding ADDRx bits are not used to detect the address match.
See 22.2 “UART Broadcast Mode Example” for additional information.
bit 23-16 ADDR: Automatic Address Mask bits
1 = Corresponding MASKx bits are used to detect the address match.
Note:
This setting allows the user to assign individual address as well as a group broadcast address
to a UART.
0 = Corresponding MASKx bits are not used to detect the address match.
See 22.2 “UART Broadcast Mode Example” for additional information.
bit 15-14 UTXISEL: TX Interrupt Mode Selection bits
11 = Reserved, do not use
10 = Interrupt is generated and asserted while the transmit buffer is empty
01 = Interrupt is generated and asserted when all characters have been transmitted
00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space
bit 13
UTXINV: Transmit Polarity Inversion bit
If IrDA mode is disabled (i.e., IREN (UxMODE) is ‘0’):
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IrDA mode is enabled (i.e., IREN (UxMODE) is ‘1’):
1 = IrDA encoded UxTX Idle state is ‘1’
0 = IrDA encoded UxTX Idle state is ‘0’
bit 12
URXEN: Receiver Enable bit
1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON bit (UxMODE) = 1)
0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module and released to the PORT
Note:
Note 1:
The event of disabling an enabled receiver will release the RX pin to the PORT function;
however, the receive buffers will not be reset. Disabling the receiver has no effect on the receive
status flags.
This bit should not be enabled until after the ON bit (UxMODE) = 1. If TX interrupts are enabled,
setting this bit will immediately cause a TX interrupt based on the value of the UTXISEL bit.
DS60001402H-page 336
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 22-2:
UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 11
UTXBRK: Transmit Break bit
1 = Send Break on next transmission. Start bit followed by twelve ‘0’ bits, followed by Stop bit; cleared by
hardware upon completion
0 = Break transmission is disabled or completed
bit 10
UTXEN: Transmit Enable bit(1)
1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON bit (UxMODE) = 1)
0 = UARTx transmitter is disabled
The event of disabling an enabled transmitter will release the TX pin to the PORT function and reset the
transmit buffers to empty. Any pending transmission is aborted and data characters in the transmit buffers
are lost. All transmit status flags are cleared and the TRMT bit is set.
bit 9
UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register is Empty bit (read-only)
1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
bit 7-6
URXISEL: Receive Interrupt Mode Selection bit
11 = Reserved
10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full
01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full
00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character)
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect
0 = Address Detect mode is disabled
bit 4
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Data is being received
bit 3
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character
0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character
0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit.
When RUNOV = 0, clearing a previously set OERR bit will clear and reset the receive buffer and shift
register.
When RUNOV = 1, Clearing a previously set OERR bit will not reset the receive buffer and shift register
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed
bit 0
URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
Note 1:
This bit should not be enabled until after the ON bit (UxMODE) = 1. If TX interrupts are enabled,
setting this bit will immediately cause a TX interrupt based on the value of the UTXISEL bit.
2016-2021 Microchip Technology Inc.
DS60001402H-page 337
PIC32MK GP/MC Family
REGISTER 22-3:
Bit
Range
31:24
23:16
15:8
7:0
UxRXREG: UARTx RECEIVE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
RX
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
RX
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-9
Unimplemented: Read as ‘0’
bit 8
RX: Data bit 8 of the received character (in 9-bit mode)
bit 7-0
RX: Data bits 7-0 of the received character
REGISTER 22-4:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
UxTXREG: UARTx TRANSMIT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-x
U-x
U-x
U-x
U-x
U-x
U-x
U-x
—
—
—
—
—
—
—
—
U-x
U-x
U-x
U-x
U-x
U-x
U-x
U-x
—
—
—
—
—
—
—
—
U-x
U-x
U-x
U-x
U-x
U-x
U-x
W-x
—
—
—
—
—
—
—
TX
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
TX
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-9
Unimplemented: Read as initialized data
bit 8
TX: Data bit 8 of the transmitted character (in 9-bit mode)
bit 7-0
TX: Data bits 7-0 of the transmitted character
DS60001402H-page 338
x = Bit is unknown
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 22-5:
Bit
Range
UxBRG: UARTx BAUD RATE GENERATOR REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
BRG
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BRG
R/W-0
7:0
R/W-0
R/W-0
R/W-0
R/W-0
BRG
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-20 Unimplemented: Read as ‘0’
bit 19-0
BRG: Baud Rate Generator Divisor bits
Note:
TABLE 22-3:
The UxBRG register cannot be changed while UARTx is enabled (ON bit (UxMODE) = 1)).
UART BAUD RATE CALCULATIONS
UART Baud Rate With
UxBRG Equals
BRGH = 0
UxBRG = ((CLKSEL Frequency / (16 * Desired Baud Rate)) – 1)
BRGH = 1
UxBRG = ((CLKSEL Frequency / (4 * Desired Baud Rate)) – 1)
Note:
UART1 and UART2 on PBCLK2; UART3 through UART6 on PBCLK3.
2016-2021 Microchip Technology Inc.
DS60001402H-page 339
PIC32MK GP/MC Family
22.2
UART Broadcast Mode Example
To send a broadcast message to all UARTs in the group
identified by bit 7 = 1, send UxTXREG = (0x190),
address bit 9 set. All the UARTs in that group, bit 7 = 1,
would generate an interrupt for an address match
because of the bit , match, Logic AND of
MASK and ADDR registers equal “true”. User software
would check if bit 4 = 1, and if true, the RX bits
register value is valid for all UARTS.
As shown in Table 22-4, the group hardware address
identifier bit was arbitrarily chosen as bit 7 with bit 4
chosen as the software group or individual UART target
ID. Therefore, the collective group address assigned
for all UARTs (i.e, [w, x, y, z]) is ‘0b100100xx, while the
individual addresses are ‘0b10000000 through
‘0b10000011, respectively.
To send a specific message to UARTy within the group,
the user would send UxTXREG = (0x182), address bit
9 set. All of the UARTs in that group identified with bit 7
= 1 would still generate an interrupt for an address
match because of the bit , address match,
Logic AND of MASK and ADDR registers equal True. In
this case, user software would check if bit 4 = 0, and if
true, the RX bits register value would be intended
only for UARTy, with all others ignored.
Any MASK register bit = 0 means the corresponding
ADDR bit is a “don't care” from a hardware
address matching point of view. Using this scheme,
multiple UART subnet groups could be created within a
network. If not using address match with a broadcast
mode, set the ADDRMSK bits (UxSTAT
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The PMP is a parallel 8-bit/16-bit input/output module
specifically designed to communicate with a wide
variety of parallel devices, such as communications
peripherals, LCDs, external memory devices and
microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP module is
highly configurable.
The following are key features of the PMP module:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8-bit or 16-bit data interface
14/22 address lines with two Chip Selects
15/23 address lines with one Chip Select
16/24 address lines without Chip Select
Address auto-increment/auto-decrement
Selectable address bus width for resource limited
I/O
Individual read and write strobes or read/write
strobe with enable strobe
Partially multiplexed address/data mode (eight
bits of address) with an address latch strobe
Fully multiplexed address/data mode (16 bits of
address) with address latch high and low strobes
Programmable wait states
Programmable polarity on selected control signals
Interrupt on cycle end, busy flag for polling
Persistent Interrupt capability for DMA access
Little and Big-Endian Compatible addressing
styles
DS60001402H-page 344
• Extended address mode with addresses up to 24
bits
• Dual (4) word buffer mode with separate read and
write registers.
• Operate during CPU Sleep and Idle modes
• Fast bit manipulation using CLR, SET, and INV
registers
• Freeze option for in-circuit debugging
Note:
On 64-pin devices, data pins PMD
and PMA are not available.
TABLE 23-1:
PMP SUPPORTED
CONFIGURATIONS
Pins
Alternate PMP
Pin Functions
100-pin 64-pin
Devices Devices
PMD
Multiplexed
PMA and
PMA
X
X
PMD
Multiplexed
PMA and
PMA
X
—
PMA
PMALL
X
X
PMA
PMALH
X
X
PMA
—
X
X
PMA
PMCS1 or
PMCS
X
X
PMA
PMCS2
X
X
PMA
—
X
—
PMA
PMCS1A
X
—
PMA
PMCS2A
X
—
PMRD
PMWR
X
X
PMWR
PMENB
X
X
ADRMUX bits:
11 = All 16 bits of address are multiplexed with the
16 bits of data (PMA/PMD) using
two phases.
10 = All 16 bits of address are multiplexed with the
lower 8 bits of data (PMA/PMA/
PMD) using three phases
01 = Lower 8 bits of address are multiplexed with
lower 8 bits of data (PMA/PMD)
00 = Address and data pins are not multiplexed
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
FIGURE 23-1:
PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
Address Bus
Data Bus
Parallel
Host Port
Control Lines
PMA
PMALL
PMA
PMALH
Flash
EEPROM
SRAM
Up to 24-bit Address
PMA
PMA
PMCS1
PMA
PMCS2
PMRD
PMRD/PMWR
PMWR
PMENB
PMD
PMD(1)
Note:
Microcontroller
LCD
FIFO
Buffer
8-bit/16-bit Data (with or without multiplexed addressing)
On 64-pin devices, data pins PMD and PMA are not available.
2016-2021 Microchip Technology Inc.
DS60001402H-page 345
Control Registers
Register
Name(1)
TABLE 23-2:
Virtual Address
(BF82_#)
E000
PMCON
31/15
30/14
31:16
—
—
—
15:0
ON
—
SIDL
31:16
—
—
—
15:0
BUSY
31:16
—
—
—
—
—
—
—
—
PMCS2A
PMCS1A
—
—
—
—
—
—
—
—
ADDR23
ADDR22
CS2
CS1
ADDR15
ADDR14
—
—
PMADDR
15:0
E030
PMDOUT
E040
PMDIN
E050
PMSTAT
31:16
—
—
ADRMUX
—
—
INCM
26/10
25/9
24/8
23/7
22/6
—
—
—
RDSTART
—
PMPTTL PTWREN PTRDEN
—
MODE16
—
31:16
CSF
—
—
MODE
—
21/5
20/4
19/3
18/2
17/1
16/0
DUALBUF EXADR
—
—
—
—
—
—
—
—
CS2P
CS1P
—
WRSP
RDSP
0000
—
—
—
—
—
—
0000
WAITE
0000
WAITB
—
—
WAITM
ADDR
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
0000
0000
—
0000
0000
DATAIN
—
0000
0000
DATAOUT
—
0000
—
ALP
ADDR
15:0
—
PTEN
0000
0000
PTEN
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
008F
31:16
—
—
—
—
—
—
—
—
WCS2A
WCS1A
—
—
—
—
—
—
—
—
WCS2
WCS1
—
—
—
—
—
—
15:0
31:16
E080 PMRADDR
15:0
PMRDIN
27/11
15:0
E070 PMWADDR
E090
IRQM
28/12
WADDR23 WADDR22
—
WADDR15 WADDR14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RCS2
RCS1
—
—
—
—
—
—
RCS2A
15:0
15:0
—
—
—
—
—
—
0000
—
—
—
—
—
—
0000
0000
RCS1A
RADDR
0000
RADDR23 RADDR22
—
RADDR15 RADDR14
31:16
0000
—
WADDR
—
31:16
—
WADDR
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RDATAIN
—
0000
0000
RADDR
0000
0000
DS60001402H-page 346
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
E060
PMAEN
31:16
29/13
All Resets
Bits
E010 PMMODE
E020
PARALLEL HOST PORT REGISTER MAP
Bit Range
2016-2021 Microchip Technology Inc.
23.1
PIC32MK GP/MC Family
REGISTER 23-1:
Bit
Range
31:24
23:16
15:8
7:0
PMCON: PARALLEL PORT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
EXADR
—
—
—
—
—
—
DUALBUF
R/W-0
(1)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SIDL
PMPTTL
PTWREN
PTRDEN
R/W-0
R/W-0
ON
CSF(2)
Legend:
R = Readable bit
-n = Value at POR
ADRMUX
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
ALP(2)
CS2P(2)
CS1P(2)
—
WRSP
RDSP
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23
RDSTART: Start Read Cycle on PMP Bus bit
1 = Start a ready cycle on the PMP bus
0 = No effect
Note:
This bit is cleared by hardware at the end of the read cycle when the BUSY bit (PMMODE)
is equal to ‘0’.
bit 22-18 Unimplemented: Read as ‘0’
bit 17
DUALBUF: Parallel Host Port Dual Read/Write Buffer Enable bit
This bit is only valid in Host mode.
1 = PMP uses separate registers for reads and writes
Reads: PMRADDR and PMRDIN
Writes: PMRWADDR and PMDOUT
0 = PMP uses legacy registers for reads and writes
Reads/Writes: PMADDR and PMRDIN
bit 16
EXADR: Parallel Host Port Extended 24-bit Addressing bit (Host mode only)
1 = PMP 24-bit addressing is enabled
0 = PMP 24-bit addressing is disabled
bit 15
ON: Parallel Host Port Enable bit(1)
1 = PMP is enabled
0 = PMP is disabled, no off-chip access performed
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
2016-2021 Microchip Technology Inc.
DS60001402H-page 347
PIC32MK GP/MC Family
REGISTER 23-1:
PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
bit 12-11 ADRMUX: Address/Data Multiplexing Selection bits
11 = All 16-bit of address are multiplexed with the 16-bits of data (PMA or PMD) using two
phases
10 = All 16-bit of address are multiplexed with the lower 8-bits of data (PMA, PMA, or
PMD) using three phases
01 = Lower 8-bits of address are multiplexed with lower 8-bits of data (PMA or PMD)
00 = Address and data pins are not multiplexed
Note:
bit 10
bit 9
bit 8
bit 7-6
bit 5
The ADRMUX bits are independent of the MODE16 bit. Therefore, if ADDRMUX = 11 and
MODE16 = 0, only the lower 8 bits of the address will be driven out. Additionally, if
ADDRMUX = 10 and MODE16 = 1, the upper 8 bits of the data will be driven out on PMD.
PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffer
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port is enabled
0 = PMRD/PMWR port is disabled
CSF: Chip Select Function bits(2)
11 = Reserved
10 = PMCS2/(a) and PMCS1/(a) used as Chip Select
01 = PMCS2/(a) used as Chip Select, PMCS1/(a) used as address bit 14 or (22 when EXADR = 1)
00 = PMCS2/(a) and PMCS1/(a) used as address bits (15 and 14) or (23 and 22 when EXADR = 1)
Note:
When the CSx bit is used as an address, it is subject to auto-increment/decrement.
ALP: Address Latch Polarity bit(2)
1 = Active-high (PMCS2) / (PMPCS2a)
0 = Active-low (PMCS2) / (PMPCS2a)
Note:
bit 4
When the PMCS2/(a) pin is used as an address pin, the setting of the CS2P bit does not affect
the polarity.
CS2P: Chip Select 1 Polarity bit(2)
1 = Active-high (PMCS2) / (PMPCS2a)
0 = Active-low (PMCS2) / (PMPCS2a)
bit 3
When the PMCS2/PMPCS2a pin is used as an address pin, the setting of the CS2P bit does not affect the
polarity.
CS1P: Chip Select 0 Polarity bit(2)
1 = Active-high (PMCS1) / (PMPCS1a)
0 = Active-low (PMCS1) / (PMPCS1a)
Note:
bit 2
When the PMCS1/PMPCS1a pin is used as an address pin, the setting of the CS1P bit does not
affect the polarity.
Unimplemented: Read as ‘0’
Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
DS60001402H-page 348
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 23-1:
bit 1
bit 0
PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
WRSP: Write Strobe Polarity bit
For Client Modes and Host mode 2 (MODE = 00,01,10):
1 = Write strobe active-high (PMWR)
0 = Write strobe active-low (PMWR)
For Host mode 1 (MODE = 11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB)
RDSP: Read Strobe Polarity bit
For Client modes and Host mode 2 (MODE = 00,01,10):
1 = Read Strobe active-high (PMRD)
0 = Read Strobe active-low (PMRD)
For Host mode 1 (MODE = 11):
1 = Read/write strobe active-high (PMRD/PMWR)
0 = Read/write strobe active-low (PMRD/PMWR)
Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
2016-2021 Microchip Technology Inc.
DS60001402H-page 349
PIC32MK GP/MC Family
REGISTER 23-2:
Bit
Range
31:24
23:16
15:8
PMMODE: PARALLEL PORT MODE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUSY
R/W-0
7:0
IRQM
R/W-0
R/W-0
WAITB(1)
INCM
R/W-0
R/W-0
MODE16
MODE
R/W-0
R/W-0
WAITM(1)
R/W-0
WAITE(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
BUSY: Busy bit (Host mode only)
1 = Port is busy
0 = Port is not busy
bit 14-13 IRQM: Interrupt Request Mode bits
11 = Reserved, do not use
10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA =11 (Addressable Client mode only)
01 = Interrupt generated at the end of the read/write cycle
00 = No Interrupt generated
Note:
This bit only controls the generation of the PMP – Parallel Host Port interrupt. The PMPE – Parallel Host Port Error is ALWAYS generated.
bit 12-11 INCM: Increment Mode bits
11 = Client mode read and write buffers auto-increment (MODE = 00 only)
10 = Decrement ADDR by 1 every read/write cycle(2)
01 = Increment ADDR by 1 every read/write cycle(2)
00 = No increment or decrement of address
bit 10
MODE16: 8-bit/16-bit Data Mode bit
1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer
0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer
bit 9-8
MODE: Parallel Port Mode Select bits
11 = PMP mode, control signals (PMA, PMD, PMCS2(a), PMCS1(a), PMPRD/PMWR,
PMENB)
10 = PMP mode, control signals (PMA, PMD, PMCS2(a), PMCS1(a), PMPRD, PMWR
(byte_enable))
01 = Enhanced PSP mode, control signals (PMPRD, PMWR, PMCS1, PMD, and PMA)
00 = Legacy Parallel Client Port mode, control signals (PMPRD, PMWR, PMCS1, and PMD)
Note 1: Whenever WAITM = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a
write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: Address bits, A15 and A14, are not subject to automatic increment/decrement if configured as Chip Select
CS2 and CS1.
3: These pins are active when MODE16 = 1 (16-bit mode).
DS60001402H-page 350
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 23-2:
PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED)
bit 7-6
WAITB: Data Setup to Read/Write Strobe Wait States bits(1)
11 = Data wait of 4 TPB; multiplexed address phase of 4 TPB
10 = Data wait of 3 TPB; multiplexed address phase of 3 TPB
01 = Data wait of 2 TPB; multiplexed address phase of 2 TPB
00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (default)
bit 5-2
WAITM: Data Read/Write Strobe Wait States bits(1)
1111 = Wait of 16 TPB
•
•
•
0001 = Wait of 2 TPB
0000 = Wait of 1 TPB (default)
bit 1-0
WAITE: Data Hold After Read/Write Strobe Wait States bits(1)
11 = Wait of 4 TPB
10 = Wait of 3 TPB
01 = Wait of 2 TPB
00 = Wait of 1 TPB (default)
For Read operations:
11 = Wait of 3 TPB
10 = Wait of 2 TPB
01 = Wait of 1 TPB
00 = Wait of 0 TPB (default)
Note 1: Whenever WAITM = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a
write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: Address bits, A15 and A14, are not subject to automatic increment/decrement if configured as Chip Select
CS2 and CS1.
3: These pins are active when MODE16 = 1 (16-bit mode).
2016-2021 Microchip Technology Inc.
DS60001402H-page 351
PIC32MK GP/MC Family
REGISTER 23-3:
Bit
Range
31:24
23:16
PMADDR: PARALLEL PORT ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CS2a
WADDR23
CS1a
WADDR22
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15:8
CS2
ADDR15
CS1
ADDR14
7:0
R/W-0
R/W-0
ADDR
R/W-0
R/W-0
R/W-0
R/W-0
ADDR
R/W-0
R/W-0
R/W-0
R/W-0
ADDR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23
CS2a: Chip Select 2a bit
This bit is only valid when the CSF bits = 10 or 01.
1 = Chip Select 2a is enabled
0 = Chip Select 2a is disabled
bit 23
WADDR23: Address bits
This bit is only valid when the CSF bits = 00 and the EXADR bit = 1 and the DUALBUF bit = 0.
bit 22
CS1a: Chip Select 1a bit
This bit is only valid when the CSF bits = 10.
1 = Chip Select 1a is enabled
0 = Chip Select 1a is disabled
bit 22
WADDR22: Address bits
This bit is only valid when the CSF bits = 00 and the EXADR bit = 1 and the DUALBUF bit = 0.
bit 21-16 ADDR: Address bits
These bits are only valid when the EXADR bit = 1 and the DUALBUF bit = 0.
bit 15
CS2: Chip Select 2 bit
This bit is only valid when the CSF bits = 10 or 01 and the EXADR bit = 0.
1 = Chip Select 2 is enabled
0 = Chip Select 2 is disabled
bit 15
ADDR: Target Address bit 15
This bit is only valid when the CSF bits = 10 or 01 and the EXADDR bit = 0.
bit 14
CS1: Chip Select 1 bit
This bit is only valid when the CSF bits = 10 or 01 or EXADR bit = 0.
1 = Chip Select 1 is enabled
0 = Chip Select 1 is disabled
bit 14
ADDR: Target Address bit 14
This bit is only valid when the CSF bits = 01 or 00 or EXADR bit = 1.
bit 13-0 ADDR: Address bits
Note:
If the DUALBUF bit (PMCON) = 0, the bits in this register control both read and write target
addressing. If the DUALBUF bit = 1, the bits in this register are not used. In this instance, use the
PMRADDR register for Read operations and the PMWADDR register for Write operations.
DS60001402H-page 352
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 23-4:
Bit
Range
31:24
23:16
15:8
7:0
PMDOUT: PARALLEL PORT OUTPUT DATA REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATAOUT
R/W-0
R/W-0
DATAOUT
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 DATAOUT: Port Data Output bits
This register is used for Read operations in the Enhanced Parallel Client mode and Write operations for Dual
Buffer Host mode.
In Dual Buffer Host mode, the DUALBUF bit (PMPCON) = 1, a write to the MSB triggers the transaction
on the PMP port. When MODE16 = 1, MSB = DATAOUT. When MODE16 = 0,
MSB = DATAOUT.
Note:
In Host mode, a read will return the last value written to the register. In Client mode, a read will return indeterminate results.
REGISTER 23-5:
Bit
Range
31:24
23:16
15:8
7:0
PMDIN: PARALLEL PORT INPUT DATA REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATAIN
R/W-0
R/W-0
DATAIN
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 DATAIN: Port Data Input bits
This register is used for both Parallel Host Port mode and Enhanced Parallel Client mode.
In Parallel Host mode, a write to the MSB triggers the write transaction on the PMP port. Similarly, a read to
the MSB triggers the read transaction on the PMP port.
When MODE16 = 1, MSB = DATAIN. When MODE16 = 0, MSB = DATAIN.
Note:
This register is not used in Dual Buffer Host mode (i.e., DUALBUF bit (PMPCON) = 1).
2016-2021 Microchip Technology Inc.
DS60001402H-page 353
PIC32MK GP/MC Family
REGISTER 23-6:
Bit
Range
31:24
23:16
15:8
7:0
PMAEN: PARALLEL PORT PIN ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN
R/W-0
R/W-0
PTEN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(1)
R/W-0
PTEN
R/W-0
PTEN(2)
PTEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Write ‘0’; ignore read
bit 23-16 PTEN: Port Enable bits
Valid if the EXADR bit is enabled in Host mode only. PAD enables for PMPCS2a, PMPCS1a, and
ADDR.
bit 15-14 PTEN: PMCSx Address Port Enable bits
1 = PMA15 and PMA14 function as either PMA or PMCS2 and PMCS1(1)
0 = PMA15 and PMA14 function as port I/O
bit 13-2
PTEN: PMP Address Port Enable bits
1 = PMA function as PMP address lines
0 = PMA function as port I/O
bit 1-0
PTEN: PMALH/PMALL Address Port Enable bits
1 = PMA1 and PMA0 function as either PMA or PMALH and PMALL(2)
0 = PMA1 and PMA0 pads function as port I/O
Note 1:
2:
The use of these pins as PMA15/PMA14 or CS2/CS1 is selected by the CSF bits (PMCON).
The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode
selected by the ADRMUX bits in the PMCON register.
DS60001402H-page 354
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 23-7:
Bit
Range
31:24
23:16
15:8
7:0
PMSTAT: PARALLEL PORT STATUS REGISTER (CLIENT MODES ONLY)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R/W-0, HS, SC
U-0
U-0
R-0
R-0
R-0
R-0
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
R-1
R/W-0, HS, SC
U-0
U-0
R-1
R-1
R-1
R-1
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
Legend:
HS = Hardware Set
SC = Software Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
IBF: Input Buffer Full Status bit
1 = All writable input buffer registers are full
0 = Some or all of the writable input buffer registers are empty
bit 14
IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full input byte buffer occurred (must be cleared in software)
Note:
This will generate a PMPE – Parallel Host Port Error interrupt.
0 = No overflow occurred
bit 13-12 Unimplemented: Read as ‘0’
bit 11-8
IBxF: Input Buffer ‘x’ Status Full bits
1 = Input Buffer contains data that has not been read (reading buffer will clear this bit)
0 = Input Buffer does not contain any unread data
bit 7
OBE: Output Buffer Empty Status bit
1 = All readable output buffer registers are empty
0 = Some or all of the readable output buffer registers are full
bit 6
OBUF: Output Buffer Underflow Status bit
1 = A read occurred from an empty output byte buffer (must be cleared in software)
Note:
This will generate a PMPE – Parallel Host Port Error interrupt.
0 = No underflow occurred
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
OBxE: Output Buffer ‘x’ Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains data that has not been transmitted
2016-2021 Microchip Technology Inc.
DS60001402H-page 355
PIC32MK GP/MC Family
REGISTER 23-8:
Bit
Range
31:24
23:16
15:8
7:0
PMWADDR: PARALLEL PORT WRITE ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CS2a
CS1a
WADDR23
WADDR22
R/W-0
R/W-0
WCS2
WCS1
WADDR15
WADDR14
R/W-0
R/W-0
WADDR
R/W-0
R/W-0
R/W-0
R/W-0
WADDR
R/W-0
R/W-0
R/W-0
R/W-0
WADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23
CS2a: Chip Select 2a bit
This bit is only valid when the CSF bits = 10 or 01.
1 = Chip Select 2a is active
0 = Chip Select 2a is inactive
bit 23
WADDR: Target Address bit 23
This bit is only valid when the CSF bits = 00 and the EXADR bit = 1 and the DUALBUF bit = 1.
bit 22
CS1a: Chip Select 1a bit
This bit is only valid when the CSF bits = 10.
1 = Chip Select 1a is active
0 = Chip Select 1a is inactive
bit 22
WADDR: Target Address bit 22
This bit is only valid when the CSF bits = 00 and the EXADR bit = 1 and the DUALBUF bit = 1.
bit 21-16 WADDR: Address bits
This bit is only valid when the EXADR bit = 1 and the DUALBUF bit = 1.
bit 15
WCS2: Chip Select 2 bit
This bit is only valid when the CSF bits = 10 or 01.
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive
bit 15
WADDR: Target Address bit 15
This bit is only valid when the CSF bits = 00.
bit 14
WCS1: Chip Select 1 bit
This bit is only valid when the CSF bits = 10.
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive
bit 14
WADDR: Target Address bit 14
This bit is only valid when the CSF bits = 00 or 01.
bit 13-0
WADDR: Address bits
Note:
This register is only used when the DUALBUF bit (PMCON) is set to ‘1’.
DS60001402H-page 356
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 23-9:
Bit
Range
31:24
23:16
15:8
7:0
PMRADDR: PARALLEL PORT READ ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CS2a
CS1a
RADDR23
RADDR22
R/W-0
R/W-0
RCS2
RCS1
RADDR15
RADDR14
R/W-0
R/W-0
RADDR
R/W-0
R/W-0
R/W-0
R/W-0
RADDR
R/W-0
R/W-0
R/W-0
R/W-0
RADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23
CS2a: Chip Select 2a bit
This bit is only valid when the CSF bits = 10 or 01.
1 = Chip Select 2a is active
0 =Chip Select 2a is inactive
bit 23
RADDR: Target Address bit 23
This bit is only valid when the CSF bits = 00 and the EXADR bit = 1 and the DUALBUF bit = 1.
bit 22
CS1a: Chip Select 1a bit
This bit is only valid when the CSF bits = 10.
1 = Chip Select 1a is active
0 = Chip Select 1a is inactive
bit 22
RADDR: Target Address bit 22
This bit is only valid when the CSF bits = 00 and the EXADR bit = 1 and the DUALBUF bit = 1.
bit 21-16 RADDR: Address bits
This bit is only valid when the EXADR bit = 1 and the DUALBUF bit = 1.
bit 15
RCS2: Chip Select 2 bit
This bit is only valid when the CSF bits = 10 or 01.
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive (RADDR15 function is selected)
bit 15
RADDR: Target Address bit 15
This bit is only valid when the CSF bits = 00.
bit 14
RCS1: Chip Select 1 bit
This bit is only valid when the CSF bits = 10.
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive (RADDR14 function is selected)
bit 14
RADDR: Target Address bit 14
This bit is only valid when the CSF bits = 00 or 01.
bit 13-0
RADDR: Address bits
Note:
This register is only used when the DUALBUF bit (PMCON) is set to ‘1’.
2016-2021 Microchip Technology Inc.
DS60001402H-page 357
PIC32MK GP/MC Family
REGISTER 23-10: PMRDIN: PARALLEL PORT READ INPUT DATA REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RDATAIN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RDATAIN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-8
RDATAIN: Port Data Input bits
Only valid when MODE16 = 1. Used for read operations in Dual Buffer Host mode only.
bit 7-0
RDATAIN: Port Data Input bits
Used for read operations in Dual Buffer Host mode only.
Note:
This register is only used when the DUALBUF bit (PMCON) is set to ‘1’ and exclusively for reads. If the
DUALBUF bit is ‘0’, the PMDIN register (Register 23-5) is used for reads instead of PMRDIN.
DS60001402H-page 358
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
24.0
Note:
REAL-TIME CLOCK AND
CALENDAR (RTCC)
• Provides calendar: Weekday, date, month and year
• Alarm intervals are configurable for half of a second,
one second, 10 seconds, one minute, 10 minutes,
one hour, one day, one week, one month, and one
year
• Alarm repeat with decrementing counter
• Alarm with indefinite repeat: Chime
• Year range: 2000 to 2099
• Leap year correction
• BCD format for smaller firmware overhead
• Optimized for long-term battery operation
• Fractional second synchronization
• User calibration of the clock crystal frequency with
auto-adjust
• Calibration range: ±0.66 seconds error per month
• Calibrates up to 260 ppm of crystal error
• Uses external 32.768 kHz crystal or 32 kHz
internal oscillator
• Alarm pulse, seconds clock, or internal clock output
on RTCC pin (not in VBAT power domain, requires
VDD)
This data sheet summarizes the
features of the PIC32MK GP/MC family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 29. “Real-Time
Clock
and
Calendar
(RTCC)”
(DS60001125), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The RTCC module is intended for applications in which
accurate time must be maintained for extended periods
of time with minimal or no CPU intervention. Lowpower optimization provides extended battery lifetime
while keeping track of time.
The following are key features of the RTCC module:
• Time: hours, minutes and seconds
• 24-hour format (military time)
• Visibility of one-half second period
FIGURE 24-1:
RTCC BLOCK DIAGRAM
RTCCLKSEL
32.768 kHz Input from
Secondary Oscillator (SOSC)
32 kHz Input from
Internal Oscillator (LPRC)
TRTC
RTCC Prescalers
0.5 seconds
YEAR, MTH, DAY
RTCVAL
RTCC Timer
Alarm
Event
WKDAY
HR, MIN, SEC
Comparator
MTH, DAY
Compare Registers
with Masks
ALRMVAL
WKDAY
HR, MIN, SEC
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
Seconds Pulse
TRTC
RTCC Pin
RTCOE
RTCOUTSEL
2016-2021 Microchip Technology Inc.
DS60001402H-page 359
RTCC Control Registers
Virtual Address
(BF8C_#)
Register
Name(1)
TABLE 24-1:
0000
RTCCON
RTCC REGISTER MAP
0010 RTCALRM
0020 RTCTIME
0030 RTCDATE
0040 ALRMTIME
0050 ALRMDATE
Legend:
Note 1:
31/15
30/14
31:16
—
15:0
ON
31:16
—
15:0 ALRMEN
29/13
28/12
27/11
—
—
—
—
—
SIDL
—
—
—
—
—
—
CHIME
PIV
ALRMSYNC
26/10
25/9
—
—
SEC10
SEC01
31:16
YEAR10
YEAR01
15:0
DAY10
DAY01
31:16
HR10
HR01
15:0
SEC10
SEC01
15:0
DAY10
—
—
—
20/4
—
—
—
—
—
—
—
AMASK
15:0
—
21/5
19/3
18/2
17/1
16/0
CAL
HR01
—
22/6
—
HR10
—
23/7
RTCCLKSEL RTCOUTSEL RTCCLKON
31:16
31:16
24/8
—
DAY01
0000
RTCWREN RTCSYNC HALFSEC RTCOE
—
—
—
—
ARPT
MIN10
—
—
—
—
MONTH10
—
—
—
—
MIN10
—
—
—
—
MONTH10
—
—
—
—
—
—
—
0000
xxxx
—
xx00
MONTH01
xxxx
WDAY01
xx00
MIN01
—
0000
0000
MIN01
—
All Resets
Bit Range
Bits
—
—
xxxx
—
xx00
MONTH01
00xx
WDAY01
xx0x
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See 13.2 “CLR, SET, and INV Registers” for more
information.
PIC32MK GP/MC Family
DS60001402H-page 360
24.1
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 24-1:
Bit
Range
Bit
31/23/15/7
31:24
23:16
Bit
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CAL
CAL
15:8
7:0
RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
ON(1)
—
SIDL
—
—
RTCCLKSEL
R/W-0
R-0
U-0
U-0
R/W-0
R-0
R-0
R/W-0
—
—
RTC
WREN(3)
RTC
SYNC
HALFSEC(4)
RTCOE
RTC
RTC
OUTSEL(2) CLKON(5)
RTC
OUTSEL(2)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25-16 CAL: Real-Time Clock Drift Calibration bits, which contain a signed 10-bit integer value
0111111111 = Maximum positive adjustment, adds 511 real-time clock pulses every one minute
•
•
•
0000000001 = Minimum positive adjustment, adds 1 real-time clock pulse every one minute
0000000000 = No adjustment
1111111111 = Minimum negative adjustment, subtracts 1 real-time clock pulse every one minute
•
•
•
1000000000 = Maximum negative adjustment, subtracts 512 real-time clock pulses every one minute
bit 15
ON: RTCC On bit(1)
1 = RTCC module is enabled
0 = RTCC module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Disables RTCC operation when CPU enters Idle mode
0 = Continue normal operation when CPU enters Idle mode
bit 12-11 Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
5:
Note:
The ON bit is only writable when RTCWREN = 1.
Requires RTCOE = 1 (RTCCON) for the output to be active.
The RTCWREN bit can be set only when the write sequence is enabled.
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME).
This bit is undefined when RTCCLKSEL = 00 (LPRC is the clock source).
This register is reset only on a POR.
2016-2021 Microchip Technology Inc.
DS60001402H-page 361
PIC32MK GP/MC Family
REGISTER 24-1:
RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER
bit 10-9
RTCCLKSEL: RTCC Clock Select bits
When a new value is written to these bits, the Seconds Value register should also be written to properly
reset the clock prescalers in the RTCC.
11 = Reserved
10 = Reserved
01 = RTCC uses the external 32.768 kHz Secondary Oscillator (SOSC)
00 = RTCC uses the internal 32 kHz oscillator (LPRC)
bit 8-7
RTCOUTSEL: RTCC Output Data Select bits(2)
11 = Reserved
10 = RTCC Clock is presented on the RTCC pin
01 = Seconds Clock is presented on the RTCC pin
00 = Alarm Pulse is presented on the RTCC pin when the alarm interrupt is triggered
bit 6
RTCCLKON: RTCC Clock Enable Status bit(5)
1 = RTCC Clock is actively running
0 = RTCC Clock is not running
bit 5-4
Unimplemented: Read as ‘0’
bit 3
RTCWREN: Real-Time Clock Value Registers Write Enable bit(3)
1 = Real-Time Clock Value registers can be written to by the user
0 = Real-Time Clock Value registers are locked out from being written to by the user
bit 2
RTCSYNC: Real-Time Clock Value Registers Read Synchronization bit
1 = Real-time clock value registers can change while reading (due to a rollover ripple that results in an invalid
data read). If the register is read twice and results in the same data, the data can be assumed to be valid.
0 = Real-time clock value registers can be read without concern about a rollover ripple
bit 1
HALFSEC: Half-Second Status bit(4)
1 = Second half period of a second
0 = First half period of a second
bit 0
RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is not enabled
Note 1:
2:
3:
4:
5:
The ON bit is only writable when RTCWREN = 1.
Requires RTCOE = 1 (RTCCON) for the output to be active.
The RTCWREN bit can be set only when the write sequence is enabled.
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME).
This bit is undefined when RTCCLKSEL = 00 (LPRC is the clock source).
Note:
This register is reset only on a POR.
DS60001402H-page 362
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 24-2:
Bit
Range
31:24
23:16
15:8
7:0
RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
Bit
27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R-0
R/W-0
R/W-0
CHIME(2)
R/W-0
(2)
R/W-0
ALRMEN(1,2)
R/W-0
(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PIV
ALRMSYNC
R/W-0
AMASK
R/W-0
ARPT(2)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ALRMEN: Alarm Enable bit(1,2)
1 = Alarm is enabled
0 = Alarm is disabled
bit 14
CHIME: Chime Enable bit(2)
1 = Chime is enabled – ARPT is allowed to rollover from 0x00 to 0xFF
0 = Chime is disabled – ARPT stops once it reaches 0x00
bit 13
PIV: Alarm Pulse Initial Value bit(2)
When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse.
When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.
bit 12
ALRMSYNC: Alarm Sync bit
1 = ARPT and ALRMEN may change as a result of a half second rollover during a read.
The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple
bits may be changing.
0 = ARPT and ALRMEN can be read without concerns of rollover because the prescaler is more than
32 real-time clocks away from a half-second rollover
bit 11-8 AMASK: Alarm Mask Configuration bits(2)
0000 = Every half-second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29, once every four years)
1010 = Reserved
1011 = Reserved
11xx = Reserved
Note 1:
2:
Note:
Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT = 00 and
CHIME = 0.
This field should not be written when the RTCC ON bit = ‘1’ (RTCCON) and ALRMSYNC = 1.
The RTCALRM register is reset on a MCLR, Power-on Reset (POR), or any time on an exit from Deep
Sleep or VBAT mode.
2016-2021 Microchip Technology Inc.
DS60001402H-page 363
PIC32MK GP/MC Family
REGISTER 24-2:
RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER (CONTINUED)
ARPT: Alarm Repeat Counter Value bits(2)
11111111 = Alarm will trigger 256 times
bit 7-0
•
•
•
00000000 = Alarm will trigger one time
The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.
Note 1:
2:
Note:
Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT = 00 and
CHIME = 0.
This field should not be written when the RTCC ON bit = ‘1’ (RTCCON) and ALRMSYNC = 1.
The RTCALRM register is reset on a MCLR, Power-on Reset (POR), or any time on an exit from Deep
Sleep or VBAT mode.
DS60001402H-page 364
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 24-3:
Bit
Range
31:24
23:16
15:8
7:0
RTCTIME: REAL-TIME CLOCK TIME VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
HR10
R/W-x
R/W-x
HR01
R/W-x
R/W-x
R/W-x
R/W-x
MIN10
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MIN01
R/W-x
R/W-x
R/W-x
SEC10
R/W-x
R/W-x
SEC01
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 HR10: Binary-Coded Decimal Value of Hours bits, 10 digits; contains a value from 0 to 2
bit 27-24 HR01: Binary-Coded Decimal Value of Hours bits, 1 digit; contains a value from 0 to 9
bit 23-20 MIN10: Binary-Coded Decimal Value of Minutes bits, 10 digits; contains a value from 0 to 5
bit 19-16 MIN01: Binary-Coded Decimal Value of Minutes bits, 1 digit; contains a value from 0 to 9
bit 15-12 SEC10: Binary-Coded Decimal Value of Seconds bits, 10 digits; contains a value from 0 to 5
bit 11-8
SEC01: Binary-Coded Decimal Value of Seconds bits, 1 digit; contains a value from 0 to 9
bit 7-0
Unimplemented: Read as ‘0’
Note:
This register is only writable when RTCWREN = 1 (RTCCON).
2016-2021 Microchip Technology Inc.
DS60001402H-page 365
PIC32MK GP/MC Family
REGISTER 24-4:
Bit
Range
31:24
23:16
15:8
7:0
RTCDATE: REAL-TIME CLOCK DATE VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
YEAR10
R/W-x
R/W-x
R/W-x
YEAR01
R/W-x
R/W-x
MONTH10
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MONTH01
R/W-x
R/W-x
R/W-x
DAY10
R/W-x
R/W-x
DAY01
U-0
U-0
U-0
U-0
—
—
—
—
R/W-x
R/W-x
R/W-x
R/W-x
WDAY01
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 YEAR10: Binary-Coded Decimal Value of Years bits, 10 digits
bit 27-24 YEAR01: Binary-Coded Decimal Value of Years bits, 1 digit
bit 23-20 MONTH10: Binary-Coded Decimal Value of Months bits, 10 digits; contains a value from 0 to 1
bit 19-16 MONTH01: Binary-Coded Decimal Value of Months bits, 1 digit; contains a value from 0 to 9
bit 15-12 DAY10: Binary-Coded Decimal Value of Days bits, 10 digits; contains a value from 0 to 3
bit 11-8
DAY01: Binary-Coded Decimal Value of Days bits, 1 digit; contains a value from 0 to 9
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
WDAY01: Binary-Coded Decimal Value of Weekdays bits,1 digit; contains a value from 0 to 6
Note:
This register is only writable when RTCWREN = 1 (RTCCON).
DS60001402H-page 366
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 24-5:
Bit
Range
31:24
23:16
15:8
7:0
ALRMTIME: ALARM TIME VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
HR10
R/W-x
R/W-x
HR01
R/W-x
R/W-x
R/W-x
R/W-x
MIN10
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MIN01
R/W-x
R/W-x
R/W-x
SEC10
R/W-x
R/W-x
SEC01
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 HR10: Binary Coded Decimal value of hours bits, 10 digits; contains a value from 0 to 2
bit 27-24 HR01: Binary Coded Decimal value of hours bits, 1 digit; contains a value from 0 to 9
bit 23-20 MIN10: Binary Coded Decimal value of minutes bits, 10 digits; contains a value from 0 to 5
bit 19-16 MIN01: Binary Coded Decimal value of minutes bits, 1 digit; contains a value from 0 to 9
bit 15-12 SEC10: Binary Coded Decimal value of seconds bits, 10 digits; contains a value from 0 to 5
bit 11-8
SEC01: Binary Coded Decimal value of seconds bits, 1 digit; contains a value from 0 to 9
bit 7-0
Unimplemented: Read as ‘0’
2016-2021 Microchip Technology Inc.
DS60001402H-page 367
PIC32MK GP/MC Family
REGISTER 24-6:
Bit
Range
31:24
23:16
15:8
7:0
ALRMDATE: ALARM DATE VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
Bit
27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MONTH10
R/W-x
R/W-x
R/W-x
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
R/W-x
R/W-x
R/W-x
MONTH01
R/W-x
R/W-x
R/W-x
DAY10
R/W-x
R/W-x
DAY01
U-0
U-0
U-0
U-0
—
—
—
—
R/W-x
R/W-x
R/W-x
R/W-x
WDAY01
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-20 MONTH10: Binary Coded Decimal value of months bits, 10 digits; contains a value from 0 to 1
bit 19-16 MONTH01: Binary Coded Decimal value of months bits, 1 digit; contains a value from 0 to 9
bit 15-12 DAY10: Binary Coded Decimal value of days bits, 10 digits; contains a value from 0 to 3
bit 11-8
DAY01: Binary Coded Decimal value of days bits, 1 digit; contains a value from 0 to 9
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
WDAY01: Binary Coded Decimal value of weekdays bits, 1 digit; contains a value from 0 to 6
DS60001402H-page 368
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
25.0
Note:
12-BIT HIGH-SPEED
SUCCESSIVE
APPROXIMATION REGISTER
(SAR) ANALOG-TO-DIGITAL
CONVERTER (ADC)
This data sheet summarizes the features
of the PIC32MK GP/MC family of devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section
22.
“12-bit
High-Speed
Successive Approximation Register
(SAR) Analog-to-Digital
Converter
(ADC)” (DS60001344) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
The 12-bit High-Speed Successive Approximation
Register (SAR) analog-to-digital converter (ADC)
includes the following features:
• 12-bit resolution
• Seven ADC modules with dedicated Sample and
Hold (S&H) circuits
• Two dedicated ADC modules can be combined in
Turbo mode to provide double conversion rate
• Up to 45 analog input sources, in addition to the
internal CTMU, VBAT, internal voltage reference
and internal temperature sensor
• Single-ended and/or differential inputs
• Supports touch sense applications
• Four digital comparators
• Four digital filters supporting two modes:
- Oversampling mode
- Averaging mode
• Early interrupt generation resulting in faster
processing of converted data
• Designed for power conversion and general
purpose applications
• Operation during Sleep and Idle modes
A simplified block diagram of the ADC module is
illustrated in Figure 25-1.
The 12-bit HS SAR ADC has up to six dedicated
ADC modules (ADC0-ADC5) and one shared ADC
module (ADC7). The dedicated ADC modules use a
single input (or its alternate) and are intended for
high-speed and precise sampling of time-sensitive or
transient inputs. The shared ADC module
incorporates a multiplexer on the input to facilitate a
larger group of inputs, with slower sampling, and
provides flexible automated scanning option through
the input scan logic.
2016-2021 Microchip Technology Inc.
For each ADC module, the analog inputs are
connected to the S&H capacitor. The clock, sampling
time, and output data resolution for each ADC
module can be set independently. The ADC module
performs the conversion of the input analog signal
based on the configurations set in the registers.
When conversion is complete, the final result is
stored in the result buffer for the specific analog
input and is passed to the digital filter and digital
comparator if configured to use data from this
particular sample. Input to ADCx mapping is
illustrated in Figure 25-2.
25.1
Activation Sequence
The following ADCx activation sequence is to be
followed at all times:
Step 1: Initialize the ADC calibration values by
copying them from the factory programmed
DEVADCx Flash locations starting at 0xBFC45000
into the ADCxCFG registers starting at 0xBF887D00,
respectively.
Then, configure the AICPMPEN bit (ADCCON1
and the IOANCPEN bit (CFGCON) = 1 if and
only if VDD is less than 2.5V. The default is ‘0’, which
assumes VDD is greater than or equal to 2.5V.
Step 2: The user writes all the essential ADC
configuration SFRs including the ADC control clock
and all ADC core clocks setup:
• ADCCON1, keeping the ON bit = 0
• ADCCON2, especially paying attention to
ADCDIV and SAMC
• ADCANCON, keeping all analog enables ANENx
bit = 0
• ADCCON3, keeping all DIGEN5x = 0, especially
paying attention to ADCSEL, CONCLKDIV
, and VREFSEL
• ADCxTIME, especially paying attention to
ADCDIVx and SAMCx
• ADCTRGMODE, ADCIMCONx, ADCTRGSNS,
ADCCSSx, ADCGIRQENx, ADCTRGx, ADCBASE
• Comparators, Filters, etc.
Step 3: The user sets the ON bit to ‘1’, which enables
the ADC control clock.
Step 4: The user waits for the interrupt/polls the
status bit BGVRRDY = 1, which signals that the
device analog environment (band gap and VREF) is
ready.
Step 5: The user sets the ANENx bit to ‘1’ for the
ADC SAR Cores needed (which internally in the
ADC module enables the control clock to generate
by division the core clocks for the desired ADC SAR
Cores, which in turn enables the bias circuitry for
these ADC SAR Cores).
DS60001402H-page 369
PIC32MK GP/MC Family
Step 6: The user waits for the interrupt/polls the
warm-up ready bits WKRDYx = 1, which signals that
the respective ADC SAR Cores are ready to operate.
Step 7: The user sets the DIGENx bit to ‘1’, which
enables the digital circuitry to immediately begin
processing incoming triggers to perform data
conversions.
Note:
For the best optimized CPU and ISR performance, refer to TABLE 8-1: “ISR
Latency Information”. To complete the
optimization, the user application should
define ISRs that use the ‘at vector’ attribute (see Table 8-1). The CPU interrupt
latency is ~43 SYSCLK cycles if no other
interrupts are pending. If not using ADC
DMA, and the ADC combined sum
throughput rate of all the ADC modules in
use is greater than (SYSCLK/ 43) = 2.8
Msps, it is recommended to use the ADC
CPU early interrupt generation, defined in
the ADCxTIME and ADCEIENx registers
(see Register 25-33, Register 25-34, and
Register 25-35). This will reduce the probability of the ADC results being overwritten by the next conversion before the CPU
can read the previous ADC results.
Do not use the early interrupts if using the
ADC in the DMA module.
TABLE 25-1: PIC32MKXXX BASED ON A 60
MHz TAD CLOCK (16.667 ns)
Number of
Class 1
Interleaved
ADC Modules
(12-bit mode)
TAD Trigger
Spacing and
Sampling time
(SAMC)
Max. effective
sampling rate
2
8
7.50 Msps
3
6
10.00 Msps
4
4
15.00 Msps
5
4
15.00 Msps
6
3
20.00 Msps
Note 1:
Interleaved ADCs in this context means
connecting the same analog source signal
to multiple dedicated Class_1 ADCs (that
is, ADC0-ADC5), and using independent
staggered trigger sources accordingly for
each interleaved ADC.
Do not activate ADC triggers sources until after ADC
has been completely initialized, enabled, and warm up
time complete.
NOTE: If using ADC DMA, ADC source clock must
be SYSCLK only.
Dedicated Class 1 ADCx Throughput rate =
1/((Sample time + Conversion time)(TAD))
= 1 / ((SAMC+# bit resolution+1)(TAD))
Example:
SAMC = 3 TAD, 12-bit mode, TAD = 16.667 ns = 60
MHz:
Throughput rate = 1 / ((3+12+1)(16.667 ns))
= 1/(16 * 16.667 ns)
= 3.75 Msps
DS60001402H-page 370
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
FIGURE 25-1:
AN0
AN3
AN5
AN24
ADC BLOCK DIAGRAM
SH0ALT
(ADCTRGMODE)
AN
VREFL
3%
00
01
10
11
AVSS
AVDD
VREF+
VREF-
1
ADCSEL
1
.
TCLK
CONCLKDIV
VREFSEL
VREFH
DIFF0
(ADCIMCON1)
VREFL
TAD0-TAD
ADCDIV
(ADCxTIME)
TQ
ADC0
TAD7
AN
AN
$1
$1
10
&/
ADCDIV
(ADCCON2)
00
01
10
11
SH4ALT
(ADCTRGMODE)
AN
VREFL
ADC
DIFF4
(ADCIMCON1)
AN
CTMUB7HPS
VBAT/2
AN38
IVREF (1.2V)
AN9
ADC7
AN1
VREFL
DIFFx
x = to 4
ADCDATA0
…...
ADCDATA
Digital Comparator
Data
Interrupt/Event
Triggers,
Turbo Channel,
Scan Control Logic
Trigger
Capacitive Voltage
Divider (CVD)
Status and Control
Registers
2016-2021 Microchip Technology Inc.
Interrupt/Event
System Bus
Digital Filter
Interrupt
DS60001402H-page 371
PIC32MK GP/MC Family
FIGURE 25-2:
S&H BLOCK DIAGRAM
AN3
00
AN0
01
AN8
10
AN26
11
SH3ALT
AN0
00
AN3
01
AN5
10
AN24
11
SH0ALT
AN27
1
AN6
1
VREFL
0
VREFL
0
DIFF
DIFF
Dedicated ADC3
AN4
00
AN1
00
AN1
01
AN4
01
AN9
10
AN7
10
AN0
11
AN0
11
SH4ALT
SH1ALT
AN10
1
AN7
1
VREFL
0
VREFL
0
DIFF
DIFF
Dedicated ADC4
AN5
00
AN2
00
AN2
01
AN5
01
AN6
10
AN6
10
AN25
11
AN25
11
SH5ALT
1
AN8
1
VREFL
0
VREFL
0
AN6 AN7 AN8 AN9
Dedicated ADC1
SH2ALT
AN11
DIFF
Dedicated ADC0
DIFF
Dedicated ADC5
Dedicated ADC2
AN46 AN47 AN48 AN49
IVREF
(1.2V)
Note
1:
VBAT/2
AN53(1)
AN52(1)
AN50(1)
CTMU_IOUT
ADC Party Line
CTMU
Temperature
Sensor
AN1
1
VREFL
0
DIFF
Shared ADC7
AN50 through AN53 are internal analog input sources.
DS60001402H-page 372
2016-2021 Microchip Technology Inc.
ADC Control Registers
7000 ADCCON1
7010 ADCCON2
Bits
31/15
30/14
31:16
TRBEN
TRBERR
15:0
ON
—
SIDL
REFFLT
EOSRDY
31:16 BGVRRDY
29/13
31:16
EOSIEN
AICPMPEN
26/10
25/9
24/8
TRBSLV
CVDEN
FSSCLKEN FSPBCLKEN
FRACT
—
22/6
ADCEIOVR
TRGSUSP
—
UPDIEN
21/5
20/4
19/3
SELRES
—
18/2
17/1
16/0
—
—
STRGSRC
IRQVS
STRGLVL
—
0600
SAMC
ADCEIS
UPDRDY
SAMP
ADCDIV
—
DIGEN5
DIGEN4
RQCNVRT GLSWTRG GSWTRG
DIGEN1
DIGEN0
ADINSEL
—
15:0
—
—
STRGEN5
STRGEN4
STRGEN3
STRGEN2
STRGEN1
STRGEN0
—
—
31:16
DIFF15
SIGN15
DIFF14
SIGN14
DIFF13
SIGN13
DIFF12
SIGN12
DIFF11
SIGN11
DIFF10
SIGN10
DIFF9
SIGN9
DIFF8
SIGN8
0000
15:0
DIFF7
SIGN7
DIFF6
SIGN6
DIFF5
SIGN5
DIFF4
SIGN4
DIFF3
SIGN3
DIFF2
SIGN2
DIFF1
SIGN1
DIFF0
SIGN0
0000
31:16
—
—
—
—
—
—
—
—
DIFF27
SIGN27
DIFF26
SIGN26
DIFF25
SIGN25
DIFF24
SIGN24
0000
15:0
DIFF23(1)
SIGN23(1)
DIFF22(1)
SIGN22(1)
DIFF21(1)
SIGN21(1)
DIFF20(1)
SIGN20(1)
DIFF19
SIGN19
DIFF18
SIGN18
DIFF17
SIGN17
DIFF16
SIGN16
0000
7060 ADCIMCON3
31:16 DIFF47(1)
SIGN47(1)
DIFF46(1)
SIGN46(1)
DIFF45(1)
SIGN45(1)
—
—
—
—
—
—
DIFF41(1)
SIGN41(1)
DIFF40(1)
15:0
DIFF39(1)
SIGN39(1)
DIFF38(1)
SIGN38(1)
DIFF37(1)
SIGN37(1)
DIFF36(1)
SIGN36(1)
DIFF35(1)
SIGN35(1)
DIFF34(1)
SIGN34(1)
DIFF33(1)
SIGN33(1)
—
—
0000
7070 ADCIMCON4
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
DIFF49
SIGN49
DIFF48
SIGN48
0000
7080 ADCGIRQEN1
31:16
—
—
—
—
AGIEN27
AGIEN26
AGIEN25
AGIEN24
AGIEN19
AGIEN18
AGIEN17
15:0
AGIEN15
AGIEN14
AGIEN13
AGIEN12
AGIEN11
AGIEN10
AGIEN9
AGIEN8
AGIEN7
AGIEN6
AGIEN3
AGIEN2
AGIEN1
7090 ADCGIRQEN2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
70C0 ADCDSTAT1
70D0 ADCDSTAT2
SH0ALT
0000
SSAMPEN5 SSAMPEN4 SSAMPEN3 SSAMPEN2 SSAMPEN1 SSAMPEN0 0000
AGIEN23(1) AGIEN22(1) AGIEN21(1) AGIEN20(1)
AGIEN5
AGIEN4
AGIEN53(3) AGIEN52(3) AGIEN51(3) AGIEN50(3) AGIEN49
SIGN40(1) 0000
AGIEN16 0000
AGIEN0
0000
AGIEN48 0000
AGIEN41(1) AGIEN40(1) AGIEN39(1) AGIEN38(1) AGIEN37(1) AGIEN36(1) AGIEN35(1) AGIEN34(1) AGIEN33(1) AGIEN32(1) 0000
DS60001402H-page 373
31:16
—
—
—
—
CSS27
CSS26
CSS25
CSS24
CSS23(1)
CSS22(1)
CSS21(1)
CSS20(1)
CSS19
CSS18
CSS17
CSS16
0000
15:0
CSS15
CSS14
CSS13
CSS12
CSS11
CSS10
CSS9
CSS8
CSS7
CSS6
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
0000
31:16
—
—
—
—
—
—
—
—
—
—
CSS53
CSS52
—
CSS50
CSS49
CSS48
0000
15:0
CSS47(1)
CSS46(1)
CSS45(1)
—
—
—
CSS41(1)
CSS40(1)
CSS39(1)
CSS38(1)
CSS37(1)
CSS36(1)
CSS35(1)
CSS34(1)
CSS33(1)
—
0000
31:16
—
—
—
—
ARDY27
ARDY26
ARDY25
ARDY24
ARDY21(1)
ARDY20(1)
ARDY19
ARDY18
ARDY17
ARDY16
0000
15:0
ARDY15
ARDY14
ARDY13
ARDY12
ARDY11
ARDY10
ARDY9
ARDY8
ARDY7
ARDY6
ARDY5
ARDY4
ARDY3
ARDY2
ARDY1
ARDY0
0000
31:16
—
—
—
—
—
—
—
—
—
—
ARDY53
ARDY52
—
ARDY50
ARDY49
ARDY48
0000
ARDY45(1)
—
—
—
ARDY41(1)
ARDY40(1) ARDY39(1) ARDY38(1)
ARDY37(1)
ARDY36(1)
—
0000
CMPE23(1) CMPE22(1)
CMPE21(1)
CMPE20(1)
CMPE19
CMPE18
CMPE17
CMPE16 0000
CMPE5
CMPE4
CMPE3
CMPE2
CMPE1
CMPE0
15:0 ARDY47(1) ARDY46(1)
ARDY23(1) ARDY22(1)
ARDY35(1) ARDY34(1) ARDY33(1)
70E0 ADCCMPEN1
31:16
—
—
—
—
CMPE27
CMPE26
CMPE25
CMPE24
15:0
CMPE15
CMPE14
CMPE13
CMPE12
CMPE11
CMPE10
CMPE9
CMPE8
70F0 ADCCMP1
31:16
DCMPHI
0000
15:0
DCMPLO
0000
Note
1:
2:
3:
CMPE7
CMPE6
This bit or register is not available on 64-pin devices.
This register is for internal ADC input sources (i.e., VBAT, and CTMU Temperature Sensor.
Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory programmed DEVADCx Flash locations starting at 0xBFC45000 into the ADCxCFG registers starting at
0xBF887D00, respectively.
0000
PIC32MK GP/MC Family
70B0 ADCCSS2
SH1ALT
0000
—
70A0 ADCCSS1
SH2ALT
0000
—
15:0 AGIEN47(1) AGIEN46(1) AGIEN45(1)
SH3ALT
0000
DIGEN2
—
7050 ADCIMCON2
SH4ALT
DIGEN3
7030 ADCTRGMODE 31:16
7040 ADCIMCON1
SH5ALT
DIGEN7
0000
0000
—
CONCLKDIV
VREFSEL
23/7
CVDCPL
ADCSEL
15:0
27/11
TRBMST
15:0 BGVRIEN REFFLTIEN
7020 ADCCON3
28/12
All Resets
Register
Name
ADC REGISTER MAP
Bit Range
TABLE 25-2:
Virtual
Address
2016-2021 Microchip Technology Inc.
25.2
7100 ADCCMPEN2
7110 ADCCMP2
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
CMPE27
CMPE26
CMPE25
CMPE24
15:0
CMPE15
CMPE14
CMPE13
CMPE12
CMPE11
CMPE10
CMPE9
CMPE8
23/7
CMPE23(1) CMPE22(1)
CMPE7
31:16
DCMPHI
15:0
DCMPLO
31:16
—
—
—
—
CMPE27
CMPE26
CMPE25
CMPE24
15:0
CMPE15
CMPE14
CMPE13
CMPE12
CMPE11
CMPE10
CMPE9
CMPE8
7130 ADCCMP3
31:16
DCMPHI
15:0
DCMPLO
CMPE7
31:16
—
—
—
—
CMPE27
CMPE26
CMPE25
CMPE24
15:0
CMPE15
CMPE14
CMPE13
CMPE12
CMPE11
CMPE10
CMPE9
CMPE8
7150 ADCCMP4
31:16
DCMPHI
15:0
DCMPLO
AFEN
DATA16EN
DFMODE
OVRSAM
AFGIEN
15:0
71B0 ADCFLTR2
31:16
31:16
AFEN
DATA16EN
DFMODE
OVRSAM
AFGIEN
31:16
AFEN
DATA16EN
DFMODE
OVRSAM
AFGIEN
7210 ADCTRG2
2016-2021 Microchip Technology Inc.
7220 ADCTRG3
7230 ADCTRG4
7240 ADCTRG5
7250 ADCTRG6(1)
7260 ADCTRG7
Note
1:
2:
3:
18/2
17/1
16/0
CMPE21(1)
CMPE20(1)
CMPE19
CMPE18
CMPE17
CMPE16 0000
CMPE5
CMPE4
CMPE3
CMPE2
CMPE1
CMPE0
AFRDY
—
AFRDY
—
AFEN
DATA16EN
DFMODE
OVRSAM
AFGIEN
AFRDY
—
0000
0000
CMPE6
CMPE21(1)
CMPE20(1)
CMPE19
CMPE18
CMPE17
CMPE16 0000
CMPE5
CMPE4
CMPE3
CMPE2
CMPE1
CMPE0
0000
0000
0000
CMPE6
CMPE21(1)
CMPE20(1)
CMPE19
CMPE18
CMPE17
CMPE16 0000
CMPE5
CMPE4
CMPE3
CMPE2
CMPE1
CMPE0
0000
0000
0000
—
—
CHNLID
—
—
CHNLID
—
—
CHNLID
—
—
CHNLID
0000
0000
0000
0000
FLTRDATA
15:0
7200 ADCTRG1
19/3
FLTRDATA
15:0
71D0 ADCFLTR4
—
20/4
FLTRDATA
15:0
71C0 ADCFLTR3
AFRDY
CMPE7
21/5
0000
CMPE23(1) CMPE22(1)
7140 ADCCMPEN4
31:16
CMPE6
CMPE23(1) CMPE22(1)
7120 ADCCMPEN3
71A0 ADCFLTR1
22/6
All Resets
Bit Range
Virtual
Address
Register
Name
ADC REGISTER MAP (CONTINUED)
0000
0000
FLTRDATA
0000
0000
31:16
—
—
—
TRGSRC3
—
—
—
TRGSRC2
0000
15:0
—
—
—
TRGSRC1
—
—
—
TRGSRC0
0000
31:16
—
—
—
TRGSRC7
—
—
—
TRGSRC6
0000
15:0
—
—
—
TRGSRC5
—
—
—
TRGSRC4
0000
31:16
—
—
—
TRGSRC11
—
—
—
TRGSRC10
0000
15:0
—
—
—
TRGSRC9
—
—
—
TRGSRC8
0000
31:16
—
—
—
TRGSRC15
—
—
—
TRGSRC14
0000
15:0
—
—
—
TRGSRC13
—
—
—
TRGSRC12
0000
31:16
—
—
—
TRGSRC19(1)
—
—
—
TRGSRC18
0000
15:0
—
—
—
TRGSRC17
—
—
—
TRGSRC16
0000
31:16
—
—
—
TRGSRC23
—
—
—
TRGSRC22
0000
15:0
—
—
—
TRGSRC21
—
—
—
TRGSRC20
0000
31:16
—
—
—
TRGSRC27
—
—
—
TRGSRC26
0000
15:0
—
—
—
TRGSRC25
—
—
—
TRGSRC24
0000
This bit or register is not available on 64-pin devices.
This register is for internal ADC input sources (i.e., VBAT, and CTMU Temperature Sensor.
Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory programmed DEVADCx Flash locations starting at 0xBFC45000 into the ADCxCFG registers starting at
0xBF887D00, respectively.
PIC32MK GP/MC Family
DS60001402H-page 374
TABLE 25-2:
Bits
31/15
30/14
29/13
15:0
—
—
7290 ADCCMPCON2 31:16
—
—
—
15:0
—
—
—
72A0 ADCCMPCON3 31:16
—
—
—
15:0
—
—
—
72B0 ADCCMPCON4 31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
28/12
27/11
26/10
25/9
7280 ADCCMPCON1 31:16
7300 ADCBASE
7320 ADCCNTB
7330 ADCDMAB
7350 ADC0TIME
7360 ADC1TIME
7370 ADC2TIME
7380 ADC3TIME
7390 ADC4TIME
73A0 ADC5TIME
DS60001402H-page 375
73C0 ADCEIEN1
73D0 ADCEIEN2
1:
2:
3:
21/5
20/4
19/3
18/2
17/1
16/0
DCMPED
IEBTWN
IEHIHI
IEHILO
IELOHI
IELOLO
—
—
—
0000
—
—
—
—
—
—
0000
DCMPED
IEBTWN
IEHIHI
IEHILO
IELOHI
IELOLO
—
—
AINID
—
—
—
0000
—
—
—
—
—
—
0000
DCMPED
IEBTWN
IEHIHI
IEHILO
IELOHI
IELOLO
—
—
—
—
0000
—
—
—
—
—
—
0000
DCMPED
IEBTWN
IEHIHI
IEHILO
IELOHI
IELOLO
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
ENDCMP DCMPGIEN
—
—
AINID
—
—
ENDCMP DCMPGIEN
AINID
—
0000
ENDCMP DCMPGIEN
—
—
ENDCMP DCMPGIEN
—
—
—
ADCBASE
0000
31:16
DMAEN
—
RBFIEN5
RBFIEN4
RBFIEN3
RBFIEN2
RBFIEN1
RBFIEN0
WOVERR
—
RBF5
RBF4
RBF3
RBF2
RBF1
RBF0
0000
15:0
DMACEN
—
RAFIEN5
RAFIEN4
RAFIEN3
RAFIEN2
RAFIEN1
RAFIEN0
—
—
RAF5
RAF4
RAF3
RAF2
RAF1
RAF0
0000
31:16
ADCCNTB
0000
15:0
ADCCNTB
0000
31:16
ADCDMAB
0000
15:0
ADCDMAB
0000
31:16
—
—
—
—
LVL27
LVL26
LVL25
LVL24
LVL23(1)
LVL22(1)
LVL21(1)
LVL20(1)
LVL19
LVL18
LVL17
LVL16
0000
15:0
LVL15
LVL14
LVL13
LVL12
LVL11
LVL10
LVL9
LVL8
LVL7
LVL6
LVL5
LVL4
LVL3
LVL2
LVL1
LVL0
0000
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
EIEN27
EIEN26
EIEN25
EIEN24
EIEN23(1)
EIEN22(1)
EIEN21(1)
EIEN20(1)
EIEN19
EIEN18
EIEN17
EIEN16
0000
15:0
EIEN15
EIEN14
EIEN13
EIEN12
EIEN11
EIEN10
EIEN9
EIEN8
EIEN7
EIEN6
EIEN5
EIEN4
EIEN3
EIEN2
EIEN1
EIEN0
0000
31:16
—
—
—
—
—
—
—
—
—
—
EIRDY53
EIRDY52
—
EIRDY50
EIRDY49
—
—
—
EIEN41(1)
EIEN40(1)
EIEN39(1)
EIEN38(1)
EIEN37(1)
EIEN36(1)
EIEN35(1)
EIEN34(1)
EIEN33(1)
15:0 EIRDY47(1) EIRDY46(1) EIRDY45(1)
Note
22/6
ADCEIS
—
—
SELRES
—
—
—
—
—
BCHEN
0300
0000
ADCDIV
—
0300
SAMC
SELRES
BCHEN
0000
ADCDIV
—
0300
SAMC
SELRES
BCHEN
0000
ADCDIV
—
ADCEIS
0000
ADCDIV
SAMC
SELRES
ADCEIS
—
BCHEN
—
ADCEIS
0300
SAMC
SELRES
ADCEIS
—
ADCDIV
—
ADCEIS
—
BCHEN
0300
SAMC
SELRES
BCHEN
0000
ADCDIV
0300
SAMC
0000
EIRDY48 0000
—
This bit or register is not available on 64-pin devices.
This register is for internal ADC input sources (i.e., VBAT, and CTMU Temperature Sensor.
Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory programmed DEVADCx Flash locations starting at 0xBFC45000 into the ADCxCFG registers starting at
0xBF887D00, respectively.
0000
PIC32MK GP/MC Family
7340 ADCTRGSNS
23/7
CVDDATA
AINID
15:0
7310 ADCDSTAT
24/8
All Resets
Register
Name
ADC REGISTER MAP (CONTINUED)
Bit Range
Virtual
Address
2016-2021 Microchip Technology Inc.
TABLE 25-2:
73E0 ADCEISTAT1
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
EIRDY23(1) EIRDY22(1) EIRDY21(1) EIRDY20(1)
19/3
18/2
17/1
16/0
All Resets
Bit Range
Virtual
Address
Register
Name
ADC REGISTER MAP (CONTINUED)
31:16
—
—
—
—
EIRDY27
EIRDY26
EIRDY25
EIRDY24
EIRDY19
EIRDY18
EIRDY17
15:0
EIRDY15
EIRDY14
EIRDY13
EIRDY12
EIRDY11
EIRDY10
EIRDY9
EIRDY8
EIRDY7
EIRDY6
EIRDY5
EIRDY4
EIRDY3
EIRDY2
EIRDY1
EIRDY0
73F0 ADCEISTAT2
31:16
—
—
—
—
—
—
—
—
—
—
EIRDY53
EIRDY52
—
EIRDY50
EIRDY49
EIRDY48 0000
15:0 EIRDY47(1) EIRDY46(1) EIRDY45(1)
—
—
7400 ADCANCON
31:16
—
—
—
—
15:0
WKRDY7
—
WKRDY5
WKRDY4
7600 ADCDATA0
7610 ADCDATA1
7620 ADCDATA2
7630 ADCDATA3
7640 ADCDATA4
7650 ADCDATA5
7660 ADCDATA6
7670 ADCDATA7
7680 ADCDATA8
2016-2021 Microchip Technology Inc.
7690 ADCDATA9
76A0 ADCDATA10
76B0 ADCDATA11
76C0 ADCDATA12
76D0 ADCDATA13
Note
1:
2:
3:
—
EIRDY41(1) EIRDY40(1) EIRDY39(1) EIRDY38(1) EIRDY37(1) EIRDY36(1) EIRDY35(1) EIRDY34(1) EIRDY33(1)
WKUPCLKCNT
WKRDY3
WKRDY2
WKRDY1
WKRDY0
EIRDY16 0000
0000
—
0000
WKIEN7
—
WKIEN5
WKIEN4
WKIEN3
WKIEN2
WKIEN1
WKIEN0
0000
ANEN7
—
ANEN5
ANEN4
ANEN3
ANEN2
ANEN1
ANEN0
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
This bit or register is not available on 64-pin devices.
This register is for internal ADC input sources (i.e., VBAT, and CTMU Temperature Sensor.
Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory programmed DEVADCx Flash locations starting at 0xBFC45000 into the ADCxCFG registers starting at
0xBF887D00, respectively.
PIC32MK GP/MC Family
DS60001402H-page 376
TABLE 25-2:
76E0 ADCDATA14
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Register
Name
ADC REGISTER MAP (CONTINUED)
Bit Range
Virtual
Address
2016-2021 Microchip Technology Inc.
TABLE 25-2:
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
7740 ADCDATA20(1) 31:16
DATA
0000
15:0
DATA
0000
7750 ADCDATA21(1) 31:16
DATA
0000
15:0
DATA
0000
7760 ADCDATA22(1) 31:16
DATA
0000
15:0
DATA
0000
7770 ADCDATA23(1) 31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
7810 ADCDATA33(1) 31:16
DATA
0000
15:0
DATA
0000
7820 ADCDATA34(1) 31:16
DATA
0000
15:0
DATA
0000
7830 ADCDATA35(1) 31:16
DATA
0000
15:0
DATA
0000
76F0 ADCDATA15
7700 ADCDATA16
7710 ADCDATA17
7720 ADCDATA18
7730 ADCDATA19
7780 ADCDATA24
7790 ADCDATA25
77A0 ADCDATA26
77B0 ADCDATA27
DS60001402H-page 377
Note
1:
2:
3:
This bit or register is not available on 64-pin devices.
This register is for internal ADC input sources (i.e., VBAT, and CTMU Temperature Sensor.
Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory programmed DEVADCx Flash locations starting at 0xBFC45000 into the ADCxCFG registers starting at
0xBF887D00, respectively.
PIC32MK GP/MC Family
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Virtual
Address
Register
Name
ADC REGISTER MAP (CONTINUED)
7840 ADCDATA36(1) 31:16
DATA
0000
15:0
DATA
0000
7850 ADCDATA37(1) 31:16
DATA
0000
15:0
DATA
0000
7860 ADCDATA38(1) 31:16
DATA
0000
15:0
DATA
0000
7870 ADCDATA39(1) 31:16
DATA
0000
15:0
DATA
0000
7880 ADCDATA40(1) 31:16
DATA
0000
15:0
DATA
0000
7890 ADCDATA41(1) 31:16
DATA
0000
15:0
DATA
0000
78D0 ADCDATA45(1) 31:16
DATA
0000
15:0
DATA
0000
78E0 ADCDATA46(1) 31:16
DATA
0000
15:0
DATA
0000
78F0 ADCDATA47(1) 31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
31:16
DATA
0000
15:0
DATA
0000
7920 ADCDATA50(2) 31:16
DATA
0000
15:0
DATA
0000
7940 ADCDATA52(2) 31:16
DATA
0000
15:0
DATA
0000
7950 ADCDATA53(2) 31:16
DATA
0000
15:0
DATA
7900 ADCDATA48
7910 ADCDATA49
2016-2021 Microchip Technology Inc.
7E00 ADCSYSCFG0 31:16
15:0
7E10 ADCSYSCFG1 31:16
15:0
7D00 ADC0CFG(3)
Note
1:
2:
3:
0000
—
—
—
—
AN27
AN26
AN25
AN24
AN23(1)
AN22(1)
AN21(1)
AN20(1)
AN19
AN18
AN17
AN16
0FxF
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
FFFF
—
—
—
—
—
—
—
—
—
—
AN53(1)
AN52(1)
—
AN50(1)
AN49
AN48
00xx
AN47(1)
AN46(1)
AN45(1)
—
—
—
AN41(1)
AN40(1)
AN39(1)
AN38(1)
AN37(1)
AN36(1)
AN35(1)
AN34(1)
AN33(1)
—
xxxx
31:16
ADCCFG
0000
15:0
ADCCFG
0000
This bit or register is not available on 64-pin devices.
This register is for internal ADC input sources (i.e., VBAT, and CTMU Temperature Sensor.
Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory programmed DEVADCx Flash locations starting at 0xBFC45000 into the ADCxCFG registers starting at
0xBF887D00, respectively.
PIC32MK GP/MC Family
DS60001402H-page 378
TABLE 25-2:
7D10 ADC1CFG(3)
7D20 ADC2CFG(3)
7D30 ADC3CFG(3)
7D40 ADC4CFG(3)
7D50 ADC5CFG(3)
7D70 ADC7CFG(3)
Note
1:
2:
3:
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Register
Name
ADC REGISTER MAP (CONTINUED)
Bit Range
Virtual
Address
2016-2021 Microchip Technology Inc.
TABLE 25-2:
31:16
ADCCFG
0000
15:0
ADCCFG
0000
31:16
ADCCFG
0000
15:0
ADCCFG
0000
31:16
ADCCFG
0000
15:0
ADCCFG
0000
31:16
ADCCFG
0000
15:0
ADCCFG
0000
31:16
ADCCFG
0000
15:0
ADCCFG
0000
31:16
ADCCFG
0000
15:0
ADCCFG
0000
This bit or register is not available on 64-pin devices.
This register is for internal ADC input sources (i.e., VBAT, and CTMU Temperature Sensor.
Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory programmed DEVADCx Flash locations starting at 0xBFC45000 into the ADCxCFG registers starting at
0xBF887D00, respectively.
PIC32MK GP/MC Family
DS60001402H-page 379
PIC32MK GP/MC Family
REGISTER 25-1:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R-0, HS, HC
TRBEN
TRBERR
R/W-0
R/W-1
FRACT
R/W-0
U-0
—
bit 30
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SIDL
AICPMPEN
CVDEN
R/W-0
R/W-0
R/W-0
HC = Hardware Set
W = Writable bit
‘1’ = Bit is set
Bit
24/16/8/0
R/W-0
R/W-0
TRBSLV
R/W-0
IRQVS
Bit
25/17/9/1
R/W-0
TRBMST
SELRES
U-0
ON
Legend:
R = Readable bit
-n = Value at POR
bit 31
ADCCON1: ADC CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
U-0
STRGSRC
R/W-0
FSSCLKEN FSPBCLKEN
R/W-0
STRGLVL
R/W-0
—
R/W-0
DMABL
HS = Hardware Cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
TRBEN: Turbo Channel Enable bit
1 = Enable the Turbo channel
0 = Disable the Turbo channel
TRBERR: Turbo Channel Error Status bit
1 = An error occurred while setting the Turbo channel and Turbo channel function to be disabled regardless
of the TRBEN bit being set to ‘1’.
0 = Turbo channel error did not occur
Note: The status of this bit is valid only after the TRBEN bit is set.
bit 29-27 TRBMST: Turbo Host ADCx bits
111 = Reserved
110 = Reserved
101 = ADC5
100 = ADC4
011 = ADC3
010 = ADC2
001 = ADC1
000 = ADC0
bit 26-24 TRBSLV: Turbo Client ADCx bits
111 = Reserved
110 = Reserved
101 = ADC5
100 = ADC4
011 = ADC3
010 = ADC2
001 = ADC1
000 = ADC0
bit 23
FRACT: Fractional Data Output Format bit
1 = Fractional
0 = Integer
bit 22-21 SELRES: Shared ADC7 (i.e., AN6-AN53) Resolution bits
11 = 12 bits (default)
10 = 10 bits
01 = 8 bits
00 = 6 bits
DS60001402H-page 380
2016-2021 Microchip Technology Inc.
PIC32MK GP/MC Family
REGISTER 25-1:
ADCCON1: ADC CONTROL REGISTER 1 (CONTINUED)
bit 20-16 STRGSRC: Scan Trigger Source Select bits
11111 = Reserved
11110 = Reserved
11101 = PWM Generator 6 Current-Limit (Motor Control only)
11100 = PWM Generator 5 Current-Limit (Motor Control only)
11011 = PWM Generator 4 Current-Limit (Motor Control only)
11010 = PWM Generator 3 Current-Limit (Motor Control only)
11001 = PWM Generator 2 Current-Limit (Motor Control only)
11000 = PWM Generator 1 Current-Limit (Motor Control only)
10111 = Reserved
10110 = Reserved
10101 = Reserved
10100 = CTMU trip
10011 = Output Compare 4 period end
10010 = Output Compare 3 period end
10001 = Output Compare 2 period end
10000 = Output Compare 1 period end
01111 = PWM Generator 6 trigger (Motor Control only)
01110 = PWM Generator 5 trigger (Motor Control only)
01101 = PWM Generator 4 trigger (Motor Control only)
01100 = PWM Generator 3 trigger (Motor Control only)
01011 = PWM Generator 2 trigger (Motor Control only)
01010 = PWM Generator 1 trigger (Motor Control only)
01001 = Secondary PWM time base (Motor Control only)
01000 = Primary PWM time base (Motor Control only)
00111 = General Purpose Timer5
00110 = General Purpose Timer3
00101 = General Purpose Timer1
00100 = INT0
00011 = Scan trigger
00010 = Software level trigger
00001 = Software edge trigger
00000 = No Trigger
Note:
bit 15
bit 14
bit 13
These triggers only apply to implemented analog inputs AN32-AN53. For AN0-AN27 refer to
ADCTRG1-ADCTRG7.
ON: ADC Module Enable bit
1 = ADC module is enabled
0 = ADC module is disabled
Note: The ON bit should be set only after the ADC module has been configured.
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
2016-2021 Microchip Technology Inc.
DS60001402H-page 381
PIC32MK GP/MC Family
REGISTER 25-1:
bit 12
ADCCON1: ADC CONTROL REGISTER 1 (CONTINUED)
AICPMPEN: Analog Input Charge Pump Enable bit
1 = Analog input charge pump is enabled
0 = Analog input charge pump is disabled (default)
Note 1: For proper analog operation at VDD less than 2.5V, the AICPMPEN bit must be = 1, and the
IOANCPEN bit in the CFGCON register must be set to ‘1’. This bit must not be set if VDD is
greater than 2.5V.
2: ADC throughput rate performance is reduced, as defined in the following table, if AICPMPEN =
1 or IOANCPEN (CFGCON
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