PIC32MM0064GPL036 FAMILY
32-Bit Flash Microcontroller with MIPS32® microAptiv™ UC Core
with Low Power and Low Pin Count
Operating Conditions
Peripheral Features
• 2.0V to 3.6V, -40°C to +125°C, DC to 25 MHz
• 2.0V to 3.6V, -40°C to +85°C, DC to 25 MHz
• Atomic Set, Clear and Invert Operation on Select
Peripheral Registers
• High-Current Sink/Source 11 mA/16 mA on All Ports
• Independent, Low-Power 32 kHz Timer Oscillator
• Two 4-Wire SPI modules (up to 25 MHz non-PPS,
20 MHz PPS):
- 16-byte FIFO
- I2S mode
• Two UARTs:
- RS-232, RS-485 and LIN/J2602 support
- IrDA® with on-chip hardware encoder and decoder
• External Edge and Level Change Interrupt on All Ports
• CRC module
• Hardware Real-Time Clock and Calendar (RTCC)
• Up to 20 Peripheral Pin Select (PPS) Remappable Pins
• Seven Total 16-Bit Timers:
- Timer1: Dedicated 16-bit timer/counter
- Two additional 16-bit timers in each MCCP and SCCP
module
• Capture/Compare/PWM/Timer modules:
- Two 16-bit timers or one 32-bit timer in each module
- PWM resolution down to 21 ns
- One Multiple Output (MCCP) module:
- Flexible configuration as PWM, input capture, output
compare or timers
- Six PWM outputs
- Programmable dead time
- Auto-shutdown
- Two Single Output (SCCP) modules:
- Flexible configuration as PWM, input capture, output
compare or timers
- Single PWM output
• Reference Clock Output (REFO)
• Two Configurable Logic Cells (CLC) with Internal
Connections to Select Peripherals and PPS
Low-Power Modes
• Low-Power modes:
- Idle: CPU off, peripherals run from system clock
- Sleep: CPU and peripherals off:
- Fast wake-up Sleep with retention
- Low-power Sleep with retention
• 0.5 μA Sleep Current for Regulator Retention mode and
5 μA for Regulator Standby mode
• On-Chip 1.8V Voltage Regulator (VREG)
• On-Chip Ultra Low-Power Retention Regulator
High-Performance 32-Bit RISC CPU
• microAptiv™ UC 32-Bit Core with 5-Stage Pipeline
• microMIPS™ Instruction Set for 35% Smaller Code and
98% Performance compared to MIPS32 Instructions
• DC-25 MHz Operating Frequency
• 3.17 CoreMark®/MHz (79 CoreMark) Performance
• 1.53 DMIPS/MHz (37 DMIPS) (Dhrystone 2.1) Performance
• 16-Bit/32-Bit Wide Instructions with 32-Bit Wide Data Path
• Two Sets of 32 Core Register Files (32-bit) to Reduce
Interrupt Latency
• Single-Cycle 32x16 Multiply and Two-Cycle 32x32 Multiply
• Hardware Divide Unit
• 64-Bit, Zero Wait State Flash with ECC to Maximize
Endurance/Retention
Microcontroller Features
• Low Pin Count Packages, Ranging from 20 to 36 Pins,
including UQFN as Small as 4x4 mm
• Up to 64K Flash Memory:
- 20,000 erase/write cycle endurance
- 20 years minimum data retention
- Self-programmable under software control
• Up to 8K Data Memory
• Pin-Compatible with Most PIC24 MCU/dsPIC® DSC Devices
• Multiple Interrupt Vectors with Individually
Programmable Priority
• Fail-Safe Clock Monitor mode
• Configurable Watchdog Timer with On-Chip, Low-Power
RC Oscillator
• Programmable Code Protection
• Selectable Oscillator Options including:
- High-precision, 8 MHz internal Fast RC (FRC) oscillator
- High-speed crystal/resonator oscillator or external clock
- 2x/3x/4x/6x/12x/24x PLL, which can be clocked from the
FRC or primary oscillator
2015-2018 Microchip Technology Inc.
Debug Features
• Two Programming and Debugging Interfaces:
- 2-wire ICSP™ interface with non-intrusive access
and real-time data exchange with application
- 4-wire MIPS® standard Enhanced JTAG interface
• IEEE Standard 1149.2 Compatible (JTAG) Boundary Scan
DS60001324C-page 1
PIC32MM0064GPL036 FAMILY
• Up to 14-Channel, Software-Selectable 10/12-Bit SAR
Analog-to-Digital Converter (ADC):
- 12-bit, up to 222k samples/second conversion rate
- 10-bit, up to 250k samples/second conversion rate
- Sleep mode operation
- Band gap reference input feature
- Windowed threshold compare feature
- Auto-scan feature
• Brown-out Reset (BOR)
Analog Features
• Two Analog Comparators with Input Multiplexing
• Programmable High/Low-Voltage Detect (HLVD)
• 5-Bit DAC with Output Pin
Program Memory (Kbytes)
Data Memory (Kbytes)
General Purpose I/O/PPS
16-Bit Timers Maximum
PWM Outputs Maximum
UART(1)/LIN/J2602
16-Bit Timers
MCCP(3)
SCCP(4)
CLC
SPI(2)/I2S
10/12-Bit ADC (Channels)
Comparators
CRC
RTCC
JTAG
Packages
PIC32MM0064GPL036 FAMILY DEVICES
Pins
TABLE 1:
PIC32MM0016GPL020
20
16
4
16/16
7
8
2
1
1
2
2
2
11
2
Yes
Yes
Yes
SSOP/QFN
PIC32MM0032GPL020
20
32
8
16/16
7
8
2
1
1
2
2
2
11
2
Yes
Yes
Yes
SSOP/QFN
PIC32MM0064GPL020
20
64
8
16/16
7
8
2
1
1
2
2
2
11
2
Yes
Yes
Yes
SSOP/QFN
PIC32MM0016GPL028
28
16
4
22/19
7
8
2
1
1
2
2
2
12
2
Yes
Yes
Yes
SSOP/SOIC/
QFN/UQFN
PIC32MM0032GPL028
28
32
8
22/19
7
8
2
1
1
2
2
2
12
2
Yes
Yes
Yes
SSOP/ SOIC/
QFN/UQFN
PIC32MM0064GPL028
28
64
8
22/19
7
8
2
1
1
2
2
2
12
2
Yes
Yes
Yes
SPDIP/SSOP/
SOIC/QFN/
UQFN
PIC32MM0016GPL036
36/40 16
4
29/20
7
8
2
1
1
2
2
2
14
2
Yes
Yes
Yes
VQFN/UQFN
PIC32MM0032GPL036
36/40 32
8
29/20
7
8
2
1
1
2
2
2
14
2
Yes
Yes
Yes
VQFN/UQFN
PIC32MM0064GPL036
36/40 64
8
29/20
7
8
2
1
1
2
2
2
14
2
Yes
Yes
Yes
VQFN/UQFN
Device
Remappable
Peripherals
Note 1: UART1 has assigned pins. UART2 is remappable.
2: SPI1 has assigned pins. SPI2 is remappable.
3: MCCP can be configured as a PWM with up to 6 outputs, input capture, output compare, 2 x 16-bit timers or
1 x 32-bit timer.
4: SCCP can be configured as a PWM with 1 output, input capture, output compare, 2 x 16-bit timers or 1 x 32-bit timer.
DS60001324C-page 2
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
Pin Diagrams
20-Pin SSOP
1
20
AVDD/VDD
PGEC2/RP1/RA0
2
19
AVSS/VSS
PGED2/RP2/RA1
3
18
RP10/RB15(1)
PGED1/RP14/RB0
4
17
RP9/RB14
PGEC1/RP15/RB1
5
16
RP13/RB13
RP16/RB2
6
15
RP12/RB12
CLKI/RP3/RA2
7
14
VCAP
CLKO/RP4/RA3(1)
8
13
RP8/RB9(1)
PGED3/SOSCI/RP5/RB4
9
12
RP7/RB8(1)
PGEC3/SOSCO/RP6/RA4
10
11
RP11/RB7
PIC32MMXXXXGPL020
MCLR
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
TABLE 2:
COMPLETE PIN FUNCTION DESCRIPTIONS FOR 20-PIN SSOP DEVICES
Pin
Function
Pin
Function
1
MCLR
11 RP11/RB7
2
PGEC2/VREF+/AN0/RP1/OCM1E/INT3/RA0
12 TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)
3
PGED2/VREF-/AN1/RP2/OCM1F/RA1
13 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/C2OUT/OCM1B/
INT2/RB9(1)
4
PGED1/AN2/C1IND/C2INB/RP14/RB0
14 VCAP
5
PGEC1/AN3/C1INC/C2INA/RP15/RB1
15 TDO/AN7/LVDIN/RP12/RB12
6
AN4/RP16/RB2
16 TDI/AN8/RP13/RB13
7
OSC1/CLKI/AN5/C1INB/RP3/OCM1C/RA2
17 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
8
OSC2/CLKO/AN6/C1INA/RP4/OCM1D/RA3(1)
18 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
9
PGED3/SOSCI/RP5/RB4
19 AVSS/VSS
10 PGEC3/SOSCO/SCLKI/RP6/PWRLCLK/RA4
Note 1:
20 AVDD/VDD
Pin has an increased current drive strength.
2015-2018 Microchip Technology Inc.
DS60001324C-page 3
PIC32MM0064GPL036 FAMILY
Pin Diagrams (Continued)
AVDD/VDD
AVSS/VSS
MCLR
PGEC2/RP1/RA0
PGED2/RP2/RA1
20-Pin QFN(2)
20 19 18 17 16
PGED1/RP14/RB0
1
PGEC1/RP15/RB1
RP16/RB2
RP9/RB14
PIC32MMXXXXGPL020 13
RP13/RB13
CLKI/RP3/RA2
4
12
RP12/RB12
(1)
5
11
VCAP
6
7
8
9 10
RP8/RB9
(1)
CLKO/RP4/RA3
RP11/RB7
14
3
RP7/RB8(1)
2
PGED3/SOSCI/RP5/RB4
RP10/RB15(1)
PGEC3/SOSCO/RP6/RA4
15
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
2: The back side thermal pad is not electrically connected.
TABLE 3:
COMPLETE PIN FUNCTION DESCRIPTIONS FOR 20-PIN QFN DEVICES
Pin
Function
Pin
Function
1
PGED1/AN2/C1IND/C2INB/RP14/RB0
11 VCAP
2
PGEC1/AN3/C1INC/C2INA/RP15/RB1
12 TDO/AN7/LVDIN/RP12/RB12
3
AN4/RP16/RB2
13 TDI/AN8/RP13/RB13
4
OSC1/CLKI/AN5/C1INB/RP3/OCM1C/RA2
14 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
5
OSC2/CLKO/AN6/C1INA/RP4/OCM1D/RA3(1)
15 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
6
PGED3/SOSCI/RP5/RB4
16 AVSS/VSS
7
PGEC3/SOSCO/SCLKI/RP6/PWRLCLK/RA4
17 AVDD/VDD
8
RP11/RB7
18 MCLR
9
TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)
19 PGEC2/VREF+/AN0/RP1/OCM1E/INT3/RA0
10 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/
C2OUT/OCM1B/INT2/RB9(1)
Note 1:
20 PGED2/VREF-/AN1/RP2/OCM1F/RA1
Pin has an increased current drive strength.
DS60001324C-page 4
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
Pin Diagrams (Continued)
28-Pin SPDIP(2)/SSOP/SOIC
1
28
VDD/AVDD
RP1/RA0
2
27
VSS/AVSS
RP2/RA1
3
26
RP10/RB15(1)
PGED1/RP14/RB0
4
25
RP9/RB14
PGEC1/RP15/RB1
5
24
RP13/RB13
RP16/RB2
6
23
RP12/RB12
RB3
7
22
PGEC2/RP18/RB11
VSS
8
21
PGED2/RP17/RB10
CLKI/RP3/RA2
9
20
VCAP
19
RP19/RC9
18
RP8/RB9(1)
PIC32MMXXXXGPL028
MCLR
(1)
10
SOSCI/RP5/RB4
11
SOSCO/RP6/RA4
12
17
RP7/RB8(1)
VDD
13
16
RP11/RB7
PGED3/RB5
14
15
PGEC3/RB6
CLKO/RP4/RA3
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
2: Only PIC32MM0064GPL028 comes in a 28-pin SPDIP package.
TABLE 4:
COMPLETE PIN FUNCTION DESCRIPTIONS FOR 28-PIN SPDIP/SSOP/SOIC DEVICES
Pin
Function
Pin
Function
1
MCLR
15 PGEC3/RB6
2
VREF+/AN0/RP1/OCM1E/INT3/RA0
16 RP11/RB7
3
VREF-/AN1/RP2/OCM1F/RA1
17 TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)
4
PGED1/AN2/C1IND/C2INB/RP14/RB0
18 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/C2OUT/OCM1B/INT2/RB9(1)
5
PGEC1/AN3/C1INC/C2INA/RP15/RB1
19 RP19/RC9
6
AN4/C1INB/RP16/RB2
20 VCAP
7
AN11/C1INA/RB3
21 PGED2/TDO/RP17/RB10
8
VSS
22 PGEC2/TDI/RP18/RB11
9
OSC1/CLKI/AN5/RP3/OCM1C/RA2
23 AN7/LVDIN/RP12/RB12
10 OSC2/CLKO/AN6/RP4/OCM1D/RA3(1)
24 AN8/RP13/RB13
11 SOSCI/RP5/RB4
25 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
12 SOSCO/SCLKI/RP6/PWRLCLK/RA4
26 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
13 VDD
27 VSS/AVSS
14 PGED3/RB5
Note 1:
28 VDD/AVDD
Pin has an increased current drive strength.
2015-2018 Microchip Technology Inc.
DS60001324C-page 5
PIC32MM0064GPL036 FAMILY
Pin Diagrams (Continued)
RP9/RB14
RP10/RB15(1)
VSS/AVSS
VDD/AVDD
MCLR
RP1/RA0
RP2/RA1
28-Pin QFN/UQFN(2)
28 27 26 25 24 23 22
PGED1/RP14/RB0
1
21
RP13/RB13
PGEC1/RP15/RB1
2
20
RP12/RB12
RP16/RB2
3
19
PGEC2/RP18/RB11
RB3
4
PIC32MMXXXXGPL028 18
PGED2/RP17/RB10
VSS
VCAP
6
16
RP19/RC9
CLKO/RP4/RA3(1)
7
15
RP8/RB9(1)
RP7/RB8(1)
RP11/RB7
PGEC3/RB6
VDD
9 10 11 12 13 14
PGED3/RB5
8
SOSCO/RP6/RA4
17
SOSCI/RP5/RB4
5
CLKI/RP3/RA2
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
2: The back side thermal pad is not electrically connected.
TABLE 5:
COMPLETE PIN FUNCTION DESCRIPTIONS FOR 28-PIN QFN/UQFN DEVICES
Pin
Function
Pin
Function
1
PGED1/AN2/C1IND/C2INB/RP14/RB0
15 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/C2OUT/OCM1B/
INT2/RB9(1)
2
PGEC1/AN3/C1INC/C2INA/RP15/RB1
16 RP19/RC9
3
AN4/C1INB/RP16/RB2
17 VCAP
4
AN11/C1INA/RB3
18 PGED2/TDO/RP17/RB10
5
VSS
19 PGEC2/TDI/RP18/RB11
6
OSC1/CLKI/AN5/RP3/OCM1C/RA2
20 AN7/LVDIN/RP12/RB12
7
OSC2/CLKO/AN6/RP4/OCM1D/RA3(1)
21 AN8/RP13/RB13
8
SOSCI/RP5/RB4
22 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
9
SOSCO/SCLKI/RP6/PWRLCLK/RA4
23 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
10 VDD
24 VSS/AVSS
11 PGED3/RB5
25 VDD/AVDD
12 PGEC3/RB6
26 MCLR
13 RP11/RB7
27 VREF+/AN0/RP1/OCM1E/INT3/RA0
14 TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)
28 VREF-/AN1/RP2/OCM1F/RA1
Note 1:
Pin has an increased current drive strength.
DS60001324C-page 6
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
PGEC1/RP15/RB1
PGED1/RP14/RB0
RP2/RA1
RP1/RA0
MCLR
VDD/AVDD
VSS/AVSS
RP10/RB15(1)
RP9/RB14
35
34
33
32
31
30
29
28
36-Pin VQFN(2)
36
Pin Diagrams (Continued)
RP16/RB2
1
27
RP13/RB13
RB3
2
26
RP12/RB12
RC0
3
25
PGEC2/RP18/RB11
RC1
4
24
PGED2/RP17/RB10
RC2
5
23
VDD
PIC32MMXXXXGPL036
9
19
RP8/RB9(1)
RP7/RB8(1) 18
SOSCI/RP5/RB4
RP11/RB7 17
RC8
PGEC3/RB6 16
20
PGED3/RB5 15
8
VDD 13
RP19/RC9
CLKO/RP4/RA3(1)
RC3 14
VCAP
21
VSS 12
22
7
RP20/RA9 11
6
SOSCO/RP6/RA4 10
VSS
CLKI/RP3/RA2
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
2: The back side thermal pad is not electrically connected.
TABLE 6:
COMPLETE PIN FUNCTION DESCRIPTIONS FOR 36-PIN VQFN DEVICES
Pin
Function
Pin
Function
1
AN4/C1INB/RP16/RB2
19 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/C2OUT/OCM1B/INT2/RB9(1)
2
AN11/C1INA/RB3
20 RC8
3
AN12/RC0
21 RP19/RC9
4
AN13/RC1
22 VCAP
5
RC2
23 VDD
6
VSS
24 PGED2/TDO/RP17/RB10
7
OSC1/CLKI/AN5/RP3/OCM1C/RA2
25 PGEC2/TDI/RP18/RB11
8
OSC2/CLKO/AN6/RP4/OCM1D/RA3(1)
26 AN7/LVDIN/RP12/RB12
9
SOSCI/RP5/RB4
27 AN8/RP13/RB13
10 SOSCO/SCLKI/RP6/PWRLCLK/RA4
28 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
11 RP20/RA9
29 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
12 VSS
30 VSS/AVSS
13 VDD
31 VDD/AVDD
14 RC3
32 MCLR
15 PGED3/RB5
33 VREF+/AN0/RP1/OCM1E/INT3/RA0
16 PGEC3/RB6
34 VREF-/AN1/RP2/OCM1F/RA1
17 RP11/RB7
35 PGED1/AN2/C1IND/C2INB/RP14/RB0
18 TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)
36 PGEC1/AN3/C1INC/C2INA/RP15/RB1
Note 1:
Pin has an increased current drive strength.
2015-2018 Microchip Technology Inc.
DS60001324C-page 7
PIC32MM0064GPL036 FAMILY
31 RP9/RB14
32 RP10/RB15(1)
33 VSS/AVSS
34 VDD/AVDD
35 MCLR
36 RP1/RA0
37 RP2/RA1
38 RP14/RB0/PGED1
40 N/C
40-Pin UQFN(2)
39 RP15/RB1/PGEC1
Pin Diagrams (Continued)
RP16/RB2
1
30
RP13/RB13
RB3
2
29
RP12/RB12
RC0
3
28
RP18/RB11/PGEC2
RC1
4
27
RP17/RB10/PGED2
RC2
5
26
VDD
VSS
6
25
N/C
PIC32MMXXXXGPL036
RC8
RP7/RB8(1)
RP8/RB9(1) 20
21
N/C 19
RP19/RC9
18
22
10
RP11/RB7 17
9
RB6/PGEC3 16
SOSCI/RP5/RB4
SOSCO/RP6/RA4
RB5/PGED3 15
N/C
VDD 13
VCAP
23
RC3 14
24
8
VSS 12
7
RP20/RA9 11
OSCI/RP3/RA2
OSCO/RP4/RA3(1)
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
2: The back side thermal pad is not electrically connected.
TABLE 7:
COMPLETE PIN FUNCTION DESCRIPTIONS FOR 40-PIN UQFN DEVICES
Pin
Function
Pin
1
AN4/C1INB/RP16/RB2
21 RC8
2
AN11/C1INA/RB3
22 RP19/RC9
3
AN12/RC0
23 N/C
4
AN13/RC1
24 VCAP
5
RC2
25 N/C
6
VSS
26 VDD
7
OSC1/CLKI/AN5/RP3/OCM1C/RA2
27 PGED2/TDO/RP17/RB10
8
OSC2/CLKO/AN6/RP4/OCM1D/RA3(1)
28 PGEC2/TDI/RP18/RB11
9
SOSCI/RP5/RB4
29 AN7/LVDIN/RP12/RB12
Function
10 SOSCO/SCLKI/RP6/PWRLCLK/RA4
30 AN8/RP13/RB13
11 RP20/RA9
31 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
12 VSS
32 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
13 VDD
33 VSS/AVSS
14 RC3
34 VDD/AVDD
15 PGED3/RB5
35 MCLR
16 PGEC3/RB6
36 VREF+/AN0/RP1/OCM1E/INT3/RA0
17 RP11/RB7
37 VREF-/AN1/RP2/OCM1F/RA1
18 TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)
38 PGED1/AN2/C1IND/C2INB/RP14/RB0
19 N/C
39 PGEC1/AN3/C1INC/C2INA/RP15/RB1
20 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/
C2OUT/OCM1B/INT2/RB9(1)
40 N/C
Note 1:
Pin has an increased current drive strength.
DS60001324C-page 8
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Guidelines for Getting Started with 32-Bit Microcontrollers........................................................................................................ 19
3.0 CPU............................................................................................................................................................................................ 23
4.0 Memory Organization ................................................................................................................................................................. 33
5.0 Flash Program Memory.............................................................................................................................................................. 37
6.0 Resets ........................................................................................................................................................................................ 45
7.0 CPU Exceptions and Interrupt Controller ................................................................................................................................... 51
8.0 Oscillator Configuration .............................................................................................................................................................. 65
9.0 I/O Ports ..................................................................................................................................................................................... 79
10.0 Timer1 ........................................................................................................................................................................................ 89
11.0 Watchdog Timer (WDT) ............................................................................................................................................................. 93
12.0 Capture/Compare/PWM/Timer Modules (MCCP and SCCP) .................................................................................................... 97
13.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I2S)....................................................................................................... 111
14.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 119
15.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 125
16.0 12-Bit Analog-to-Digital Converter with Threshold Detect........................................................................................................ 135
17.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 149
18.0 Configurable Logic Cell (CLC).................................................................................................................................................. 153
19.0 Comparator .............................................................................................................................................................................. 165
20.0 Control Digital-to-Analog Converter (CDAC)............................................................................................................................ 171
21.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 175
22.0 Power-Saving Features ........................................................................................................................................................... 179
23.0 Special Features ...................................................................................................................................................................... 183
24.0 Development Support............................................................................................................................................................... 201
25.0 Instruction Set .......................................................................................................................................................................... 205
26.0 Electrical Characteristics .......................................................................................................................................................... 207
27.0 Packaging Information.............................................................................................................................................................. 235
Appendix A: Revision History............................................................................................................................................................. 259
Index .................................................................................................................................................................................................. 261
The Microchip Web Site ..................................................................................................................................................................... 265
Customer Change Notification Service .............................................................................................................................................. 265
Customer Support .............................................................................................................................................................................. 265
Product Identification System ............................................................................................................................................................ 267
2015-2018 Microchip Technology Inc.
DS60001324C-page 9
PIC32MM0064GPL036 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS60001324C-page 10
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
Referenced Sources
This device data sheet is based on the following
individual sections of the “PIC32 Family Reference
Manual”. These documents should be considered as
the general reference for the operation of a particular
module or device feature.
Note:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
To access the documents listed below,
browse the documentation section of the
Microchip web site (www.microchip.com).
Section 1. “Introduction” (DS60001127)
Section 5. “Flash Programming” (DS60001121)
Section 7. “Resets” (DS60001118)
Section 8. “Interrupts” (DS60001108)
Section 10. “Power-Saving Modes” (DS60001130)
Section 14. “Timers” (DS60001105)
Section 19. “Comparator” (DS60001110)
Section 21. “UART” (DS60001107)
Section 23. “Serial Peripheral Interface (SPI)” (DS61106)
Section 25. “12-Bit Analog-to-Digital Converter (ADC) with Threshold Detect” (DS60001359)
Section 28. “RTCC with Timestamp” (DS60001362)
Section 30. “Capture/Compare/PWM/Timer (MCCP and SCCP)” (DS60001381)
Section 33. “Programming and Diagnostics” (DS61129)
Section 36. “Configurable Logic Cell” (DS60001363)
Section 45. “Control Digital-to-Analog Converter (CDAC)” (DS60001327)
Section 50. “CPU for Devices with MIPS32® microAptiv™ and M-Class Cores” (DS60001192)
Section 59. “Oscillators with DCO” (DS60001329)
Section 60. “32-Bit Programmable Cyclic Redundancy Check (CRC)” (DS60001336)
Section 62. “Dual Watchdog Timer” (DS60001365)
2015-2018 Microchip Technology Inc.
DS60001324C-page 11
PIC32MM0064GPL036 FAMILY
NOTES:
DS60001324C-page 12
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
1.0
This data sheet contains device-specific information for
the PIC32MM0064GPL036 family devices.
DEVICE OVERVIEW
This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a comprehensive reference source. To complement
the information in this data sheet, refer to
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32). The
information in this data sheet supersedes
the information in the FRM.
Note:
FIGURE 1-1:
Figure 1-1 illustrates a general block diagram of the core
and peripheral modules in the PIC32MM0064GPL036
family of devices.
Table 1-1 lists the pinout I/O descriptions for the pins
shown in the device pin tables.
PIC32MM0064GPL036 FAMILY BLOCK DIAGRAM
Power-up
Timer
OSC2/CLKO
OSC1/CLKI
SOSCO/SCLKI
SOSCI
Primary
Oscillator
Oscillator
Start-up Timer
FRC/LPRC
Oscillators
Power-on
Reset
Secondary
Oscillator
Watchdog
Timer
Dividers
Brown-out
Reset
PLL
VCAP
SYSCLK
Timing
Generation
PBCLK (1:1 with SYSCLK)
Peripheral Bus Clocked by PBCLK
AVDD, AVSS
VDD, VSS
MCLR
Voltage
Regulator
I/O Change
Notification
Precision
Band Gap
Reference
Timer1
PORTA
MCCP1
Priority
Interrupt
Controller
SCCP2,3
ICD
EJTAG
32
INT
MIPS32® microAptiv™ UC
CPU Core
IS
DS
PORTB
32
32
32
Bus Matrix
PORTC
32
32
32
Peripheral Bus Clocked by PBCLK
JTAG
Boundary
Scan
SPI1,2
5-Bit DAC
CRC
32
12-Bit ADC
UART1,2
Line Buffer
Module
RAM
RTCC
64
64-Bit Wide
Program Flash Memory
2015-2018 Microchip Technology Inc.
Peripheral Bridge
Comparators
Flash
Controller
HLVD
DS60001324C-page 13
PIC32MM0064GPL036 FAMILY
TABLE 1-1:
PIC32MM0064GPL036 FAMILY PINOUT DESCRIPTION
Pin Number
Pin Name 20-Pin 20-Pin
QFN SSOP
28-Pin
28-Pin
QFN/
SPDIP/
UQFN SSOP/SOIC
36-Pin
VQFN
Pin
40-Pin Type
UQFN
Buffer
Type
Description
Analog-to-Digital Converter input channels
AN0
19
2
27
2
33
36
I
ANA
AN1
20
3
28
3
34
37
I
ANA
AN2
1
4
1
4
35
38
I
ANA
AN3
2
5
2
5
36
39
I
ANA
AN4
3
6
3
6
1
1
I
ANA
AN5
4
7
6
9
7
7
I
ANA
AN6
5
8
7
10
8
8
I
ANA
AN7
12
15
20
23
26
29
I
ANA
AN8
13
16
21
24
27
30
I
ANA
AN9
14
17
22
25
28
31
I
ANA
AN10
15
18
23
26
29
32
I
ANA
AN11
—
—
4
7
2
2
I
ANA
AN12
—
—
—
—
3
3
I
ANA
AN13
—
—
—
—
4
4
I
ANA
AVDD
17
20
25
28
31
34
P
—
Analog modules power supply(1)
AVSS
16
19
24
27
30
33
P
—
Analog modules ground(2)
C1INA
5
8
4
7
2
2
I
ANA
Comparator 1 Input A
C1INB
4
7
3
6
1
1
I
ANA
Comparator 1 Input B
C1INC
2
5
2
5
36
39
I
ANA
Comparator 1 Input C
C1IND
1
4
1
4
35
38
I
ANA
Comparator 1 Input D
C1OUT
14
17
22
25
28
31
O
DIG
Comparator 1 output
C2INA
2
5
2
5
36
39
I
ANA
Comparator 2 Input A
C2INB
1
4
1
4
35
38
I
ANA
Comparator 2 Input B
C2OUT
10
13
15
18
19
20
O
DIG
Comparator 2 output
CLKI
4
7
6
9
7
7
I
ST
External Clock input (EC mode)
CLKO
5
8
7
10
8
8
O
DIG
System clock output
CDAC1
14
17
22
25
28
31
O
ANA
Digital-to-Analog Converter output
FSYNC1
15
18
23
26
29
32
I/O
INT0
15
18
23
26
29
32
I
ST
External Interrupt 0
INT1
14
17
22
25
28
31
I
ST
External Interrupt 1
INT2
10
13
15
18
19
20
I
ST
External Interrupt 2
INT3
19
2
27
2
33
36
I
ST
External Interrupt 3
LVDIN
12
15
20
23
26
29
I
ANA
ST/DIG SPI1 frame signal input or output
High/Low-Voltage Detect input
MCLR
18
1
26
1
32
35
I
ST
OCM1A
9
12
14
17
18
18
O
DIG
Master Clear (device Reset)
MCCP1 Output A
OCM1B
10
13
15
18
19
20
O
DIG
MCCP1 Output B
OCM1C
4
7
6
9
7
7
O
DIG
MCCP1 Output C
OCM1D
5
8
7
10
8
8
O
DIG
MCCP1 Output D
OCM1E
19
2
27
2
33
36
O
DIG
MCCP1 Output E
OCM1F
20
3
28
3
34
37
O
DIG
MCCP1 Output F
OSC1
4
7
6
9
7
7
—
—
Primary Oscillator crystal
OSC2
5
8
7
10
8
8
—
—
Primary Oscillator crystal
Legend:
Note 1:
2:
ST = Schmitt Trigger input buffer
DIG = Digital input/output
VDD and AVDD are internally connected.
VSS and AVSS are internally connected.
DS60001324C-page 14
ANA = Analog level input/output
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
TABLE 1-1:
PIC32MM0064GPL036 FAMILY PINOUT DESCRIPTION (CONTINUED)
Pin Number
Pin Name 20-Pin 20-Pin
QFN SSOP
5
28-Pin
28-Pin
QFN/
SPDIP/
UQFN SSOP/SOIC
2
5
36-Pin
VQFN
36
Pin
40-Pin Type
UQFN
39
I
Buffer
Type
ST
Description
PGEC1
2
ICSP™ Port 1 programming clock input
PGEC2
19
2
19
22
25
28
I
ST
ICSP Port 2 programming clock input
PGEC3
7
10
12
15
16
16
I
ST
ICSP Port 3 programming clock input
PGED1
1
4
1
4
35
38
I/O
ST/DIG ICSP Port 1 programming data
PGED2
20
3
18
21
24
27
I/O
ST/DIG ICSP Port 2 programming data
ST/DIG ICSP Port 3 programming data
PGED3
6
9
11
14
15
15
I/O
PWRLCLK
7
10
9
12
10
10
I
RA0
19
2
27
2
33
36
I/O
ST/DIG PORTA digital I/O
RA1
20
3
28
3
34
37
I/O
ST/DIG PORTA digital I/O
RA2
4
7
6
9
7
7
I/O
ST/DIG PORTA digital I/O
RA3
5
8
7
10
8
8
I/O
ST/DIG PORTA digital I/O
RA4
7
10
9
12
10
10
I/O
ST/DIG PORTA digital I/O
RA9
—
—
—
—
11
11
I/O
ST/DIG PORTA digital I/O
RB0
1
4
1
4
35
38
I/O
ST/DIG PORTB digital I/O
RB1
2
5
2
5
36
39
I/O
ST/DIG PORTB digital I/O
RB2
3
6
3
6
1
1
I/O
ST/DIG PORTB digital I/O
RB3
—
—
4
7
2
2
I/O
ST/DIG PORTB digital I/O
ST
Real-Time Clock 50/60 Hz clock input
RB4
6
9
8
11
9
9
I/O
ST/DIG PORTB digital I/O
RB5
—
—
11
14
15
15
I/O
ST/DIG PORTB digital I/O
RB6
—
—
12
15
16
16
I/O
ST/DIG PORTB digital I/O
RB7
8
11
13
16
17
17
I/O
ST/DIG PORTB digital I/O
RB8
9
12
14
17
18
18
I/O
ST/DIG PORTB digital I/O
RB9
10
13
15
18
19
20
I/O
ST/DIG PORTB digital I/O
RB10
—
—
18
21
24
27
I/O
ST/DIG PORTB digital I/O
RB11
—
—
19
22
25
28
I/O
ST/DIG PORTB digital I/O
RB12
12
15
20
23
26
29
I/O
ST/DIG PORTB digital I/O
RB13
13
16
21
24
27
30
I/O
ST/DIG PORTB digital I/O
RB14
14
17
22
25
28
31
I/O
ST/DIG PORTB digital I/O
RB15
15
18
23
26
29
32
I/O
ST/DIG PORTB digital I/O
RC0
—
—
—
—
3
3
I/O
ST/DIG PORTC digital I/O
RC1
—
—
—
—
4
4
I/O
ST/DIG PORTC digital I/O
RC2
—
—
—
—
5
5
I/O
ST/DIG PORTC digital I/O
RC3
—
—
—
—
14
14
I/O
ST/DIG PORTC digital I/O
RC8
—
—
—
—
20
21
I/O
ST/DIG PORTC digital I/O
RC9
—
—
16
19
21
22
I/O
ST/DIG PORTC digital I/O
REFCLKI
10
13
15
18
19
20
I
ST
Reference clock input
REFCLKO
15
18
23
26
29
32
O
DIG
Reference clock output
Legend:
Note 1:
2:
ST = Schmitt Trigger input buffer
DIG = Digital input/output
VDD and AVDD are internally connected.
VSS and AVSS are internally connected.
2015-2018 Microchip Technology Inc.
ANA = Analog level input/output
DS60001324C-page 15
PIC32MM0064GPL036 FAMILY
TABLE 1-1:
PIC32MM0064GPL036 FAMILY PINOUT DESCRIPTION (CONTINUED)
Pin Number
Pin Name 20-Pin 20-Pin
QFN SSOP
28-Pin
28-Pin
QFN/
SPDIP/
UQFN SSOP/SOIC
36-Pin
VQFN
Pin
40-Pin Type
UQFN
Buffer
Type
Description
RP1
19
2
27
2
33
36
I/O
ST/DIG Remappable peripherals (input or output)
RP2
20
3
28
3
34
37
I/O
ST/DIG
RP3
4
7
6
9
7
7
I/O
ST/DIG
RP4
5
8
7
10
8
8
I/O
ST/DIG
RP5
6
9
8
11
9
9
I/O
ST/DIG
RP6
7
10
9
12
10
10
I/O
ST/DIG
RP7
9
12
14
17
18
18
I/O
ST/DIG
RP8
10
13
15
18
19
20
I/O
ST/DIG
RP9
14
17
22
25
28
31
I/O
ST/DIG
RP10
15
18
23
26
29
32
I/O
ST/DIG
RP11
8
11
13
16
17
17
I/O
ST/DIG
RP12
12
15
20
23
26
29
I/O
ST/DIG
RP13
13
16
21
24
27
30
I/O
ST/DIG
RP14
1
4
1
4
35
38
I/O
ST/DIG
RP15
2
5
2
5
36
39
I/O
ST/DIG
RP16
3
6
3
6
1
1
I/O
ST/DIG
RP17
—
—
18
21
24
27
I/O
ST/DIG
RP18
—
—
19
22
25
28
I/O
ST/DIG
RP19
—
—
16
19
21
22
I/O
ST/DIG
RP20
—
—
—
—
11
11
I/O
ST/DIG
RTCC
14
17
22
25
28
31
O
DIG
Real-Time Clock alarm/seconds output
SCK1
9
12
14
17
18
18
I/O
SCLKI
7
10
9
12
10
10
I
ST/DIG SPI1 clock (input or output)
ST
Secondary Oscillator external clock input
SDI1
14
17
22
25
28
31
I
ST
SPI1 data input
SDO1
10
13
15
18
19
20
O
DIG
SPI1 data output
SOSCI
6
9
8
11
9
9
—
—
Secondary Oscillator crystal
SOSCO
7
10
9
12
10
10
—
—
Secondary Oscillator crystal
SS1
15
18
23
26
29
32
I
ST
SPI1 slave select input
T1CK
10
13
15
18
19
20
I
ST
Timer1 external clock input
T1G
10
13
15
18
19
20
I
ST
Timer1 clock gate input
TCK
9
12
14
17
18
18
I
ST
JTAG clock input
TDI
13
16
19
22
25
28
I
ST
JTAG data input
JTAG data output
TDO
12
15
18
21
24
27
O
DIG
TMS
10
13
15
18
19
20
I
ST
JTAG mode select input
U1BCLK
10
13
15
18
19
20
O
DIG
UART1 IrDA® 16x baud clock output
U1CTS
9
12
14
17
18
18
I
ST
UART1 transmission control input
U1RTS
10
13
15
18
19
20
O
DIG
UART1 reception control output
U1RX
15
18
23
26
29
32
I
ST
UART1 receive data input
14
17
22
25
28
31
O
DIG
UART1 transmit data output
U1TX
Legend:
Note 1:
2:
ST = Schmitt Trigger input buffer
DIG = Digital input/output
VDD and AVDD are internally connected.
VSS and AVSS are internally connected.
DS60001324C-page 16
ANA = Analog level input/output
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
TABLE 1-1:
PIC32MM0064GPL036 FAMILY PINOUT DESCRIPTION (CONTINUED)
Pin Number
Pin Name 20-Pin 20-Pin
QFN SSOP
28-Pin
28-Pin
QFN/
SPDIP/
UQFN SSOP/SOIC
VCAP
11
14
17
20
VDD
17
20
10,25
13,28
36-Pin
VQFN
22
Pin
40-Pin Type
UQFN
24
13,23,31 13,26,
34
Buffer
Type
P
—
Core voltage regulator filter capacitor
connection
P
—
Digital modules power supply(1)
VREF-
20
3
28
3
34
37
I
ANA
VREF+
19
2
27
2
33
36
I
ANA
VSS
16
19
5,24
8,27
6,12,30
6,12,
33
P
—
Legend:
Note 1:
2:
ST = Schmitt Trigger input buffer
DIG = Digital input/output
VDD and AVDD are internally connected.
VSS and AVSS are internally connected.
2015-2018 Microchip Technology Inc.
Description
ADC negative reference
ADC and DAC positive reference
Digital modules ground(2)
ANA = Analog level input/output
DS60001324C-page 17
PIC32MM0064GPL036 FAMILY
NOTES:
DS60001324C-page 18
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
2.0
Note:
2.1
GUIDELINES FOR GETTING
STARTED WITH 32-BIT
MICROCONTROLLERS
This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a comprehensive reference source. To complement
the information in this data sheet, refer to
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
The information in this data sheet
supersedes the information in the FRM.
Basic Connection Requirements
Getting started with the PIC32MM0064GPL036 family
of 32-bit Microcontrollers (MCUs) requires attention to
a minimal set of device pin connections before
proceeding with development. The following is a list of
pin names, which must always be connected:
• All VDD and VSS pins (see Section 2.2
“Decoupling Capacitors”)
• All AVDD and AVSS pins, even if the ADC module
is not used (see Section 2.2 “Decoupling
Capacitors”)
• MCLR pin (see Section 2.3 “Master Clear
(MCLR) Pin”)
• VCAP pin (see Section 2.4 “Capacitor on
Internal Voltage Regulator (VCAP)”)
• PGECx/PGEDx pins, used for In-Circuit Serial
Programming™ (ICSP™) and debugging
purposes (see Section 2.6 “ICSP Pins”)
• OSC1 and OSC2 pins, when external oscillator
source is used (see Section 2.8 “External
Oscillator Pins”)
The following pin(s) may be required as well:
VREF+/VREF- pins, used when external voltage
reference for the ADC module is implemented.
Note:
2.2
Decoupling Capacitors
The use of decoupling capacitors on power supply
pins, such as VDD, VSS, AVDD and AVSS, is required.
See Figure 2-1.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A value of 0.1 µF
(100 nF), 10-20V is recommended. The capacitor
should be a low Equivalent Series Resistance
(low-ESR) capacitor and have resonance frequency
in the range of 20 MHz and higher. It is further
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close to
the pins as possible. It is recommended that the
capacitors be placed on the same side of the board
as the device. If space is constricted, the capacitor
can be placed on another layer on the PCB using a
via; however, ensure that the trace length from the
pin to the capacitor is within one-quarter inch
(6 mm) in length.
• Handling high-frequency noise: If the board is
experiencing high-frequency noise, upward of tens
of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor.
The value of the second capacitor can be in the
range of 0.01 µF to 0.001 µF. Place this second
capacitor next to the primary decoupling capacitor.
In high-speed circuit designs, consider implementing a decade pair of capacitances, as close to the
power and ground pins as possible. For example,
0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first, and
then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track inductance.
The AVDD and AVSS pins must be
connected, regardless of ADC use and
the ADC voltage reference source.
The back side thermal pad, if present, is
not electrically connected.
2015-2018 Microchip Technology Inc.
DS60001324C-page 19
PIC32MM0064GPL036 FAMILY
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
VDD
0.1 µF
Ceramic
MCLR
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS(1,2,3)
VDD
VSS
R1
VCAP
R
VDD
10 µF
CEFC
Place the components illustrated in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
R
0.1 µF(2)
PIC32
ICSP™
VSS/AVSS
VDD
VSS
VDD/AVDD
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
Note 1:
BULK CAPACITORS
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.
2.3
R1(1)
MCLR
C
2.2.1
10k
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
• Device Reset
• Device Programming and Debugging
Pulling The MCLR pin low generates a device Reset.
Figure 2-2 illustrates a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
2.4
1
5
4
2
3
6
C
1 k
PIC32
VDD
VSS
NC
PGECx(3)
PGEDx(3)
470 R1 1 k will limit any current flowing into
MCLR from the external capacitor, C, in the event of
MCLR pin breakdown, due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS). Ensure that the
MCLR pin VIH and VIL specifications are met without
interfering with the debug/programmer tools.
2:
The capacitor can be sized to prevent unintentional
Resets from brief glitches or to extend the device
Reset period during POR.
3:
No pull-ups or bypass capacitors are allowed on active
debug/program PGECx/PGEDx pins.
Capacitor on Internal Voltage
Regulator (VCAP)
A low-ESR ( VIN0 = VIN+ < VINWhen CPOL = 1:
1 = VIN+ < VIN0 = VIN+ > VIN-
DS60001324C-page 168
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
REGISTER 19-2:
CMxCON: COMPARATOR x CONTROL REGISTERS
(COMPARATORS 1 AND 2) (CONTINUED)
bit 7-6
EVPOL: Trigger/Event/Interrupt Polarity Select bits
11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt is generated on transition of the comparator output:
If CPOL = 0 (non-inverted polarity):
High-to-low transition only.
If CPOL = 1 (inverted polarity):
Low-to-high transition only.
01 = Trigger/event/interrupt is generated on transition of the comparator output:
If CPOL = 0 (non-inverted polarity):
Low-to-high transition only.
If CPOL = 1 (inverted polarity):
High-to-low transition only.
00 = Trigger/event/interrupt generation is disabled
bit 5
Unimplemented: Read as ‘0’
bit 4
CREF: Comparator Reference Select bit (non-inverting input)
1 = Non-inverting input connects to the internal reference defined by the CVREFSEL bit in the CMSTAT register
0 = Non-inverting input connects to the CxINA pin
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
CCH: Comparator Channel Select bits
11 = Inverting input of the comparator connects to the band gap reference voltage
10 = Inverting input of the comparator connects to the CxIND pin
01 = Inverting input of the comparator connects to the CxINC pin
00 = Inverting input of the comparator connects to the CxINB pin
2015-2018 Microchip Technology Inc.
DS60001324C-page 169
PIC32MM0064GPL036 FAMILY
NOTES:
DS60001324C-page 170
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
20.0
Note:
CONTROL
DIGITAL-TO-ANALOG
CONVERTER (CDAC)
The Control Digital-to-Analog Converter (CDAC)
generates analog voltage corresponding to the digital
input.
The CDAC has the following features:
This data sheet summarizes the
features of the PIC32MM0064GPL036
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 45. “Control
Digital-to-Analog Converter (CDAC)”
(DS60001327) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32). The information in this data sheet supersedes
the information in the FRM.
FIGURE 20-1:
• 32 Output Levels are Available
• Internally Connected to Comparators to Conserve
Device Pins
• Output can be Connected to a Pin
A block diagram of the CDAC module is illustrated in
Figure 20-1.
CDAC BLOCK DIAGRAM
REFSEL
VREF+
AVDD
DACDAT
R
R
Output to
Comparators
R
32 Steps
R
32-to-1 MUX
R
CDAC1
DACOE
R
R
AVSS
2015-2018 Microchip Technology Inc.
DS60001324C-page 171
CDAC Control Registers
CDAC REGISTER MAP
0980 DAC1CON
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
15:0
ON
—
—
—
—
—
—
—
—
—
—
—
DACOE
—
—
—
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
The register in this table has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively.
20/4
19/3
—
—
18/2
17/1
16/0
DACDAT
—
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF80_#)
TABLE 20-1:
0000
REFSEL
0000
PIC32MM0064GPL036 FAMILY
DS60001324C-page 172
20.1
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
REGISTER 20-1:
Bit
Range
31:24
23:16
15:8
7:0
DAC1CON: CDAC CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
—
—
—
R/W-0
U-0
U-0
DACDAT
U-0
ON
—
—
—
—
—
—
DACOE
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
REFSEL
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-21 Unimplemented: Read as ‘0’
bit 20-16 DACDAT: CDAC Voltage Reference Selection bits
11111 = (DACDAT * VREF+/32) or (DACDAT * AVDD/32) volts depending on the REFSEL bits
•
•
•
00000 = 0.0 volts
bit 15
ON: Voltage Reference Enable bit
1 = Voltage reference is enabled
0 = Voltage reference is disabled
bit 14-9
Unimplemented: Read as ‘0’
bit 8
DACOE: CDAC Voltage Reference Output Enable bit
1 = Voltage level is output on the CDAC1 pin
0 = Voltage level is disconnected from the CDAC1 pin
bit 7-2
Unimplemented: Read as ‘0’
bit 1-0
REFSEL: CDAC Voltage Reference Source Select bits
11 = Reference voltage is AVDD
10 = No reference is selected – output is AVSS
01 = Reference voltage is the VREF+ input pin voltage
00 = No reference is selected – output is AVSS
2015-2018 Microchip Technology Inc.
DS60001324C-page 173
PIC32MM0064GPL036 FAMILY
NOTES:
DS60001324C-page 174
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
21.0
The HLVD Control register (see Register 21-1)
completely controls the operation of the HLVD module.
This allows the circuitry to be “turned off” by the user
under software control, which minimizes the current
consumption for the device.
HIGH/LOW-VOLTAGE DETECT
(HLVD)
The High/Low-Voltage Detect (HLVD) module is a
programmable circuit that allows the user to specify
both the device voltage trip point and the direction of
change.
An interrupt flag is set if the device experiences an
excursion past the trip point in the direction of change.
If the interrupt is enabled, the program execution will
branch to the interrupt vector address and the software
can then respond to the interrupt.
FIGURE 21-1:
VDD
HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM
Externally Generated
Trip Point
VDD
LVDIN
HLVDL
16-to-1 MUX
ON VDIR
Set
HLVDIF
Band Gap
1.2V Typical
ON
2015-2018 Microchip Technology Inc.
DS60001324C-page 175
High/Low-Voltage Detect Registers
Virtual Address
(BF80_#)
Register
Name(1)
TABLE 21-1:
2310
HLVDCON
HIGH/LOW-VOLTAGE DETECT REGISTER MAP
31/15
30/14
29/13
28/12
31:16
—
15:0
ON
27/11
26/10
—
—
—
—
—
—
SIDL
—
VDIR
BGVST
25/9
24/8
23/7
22/6
21/5
20/4
19/3
—
—
—
—
—
—
—
IRVST
HLEVT
—
—
—
—
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
The register in this table has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively.
18/2
17/1
16/0
—
—
—
HLVDL
All Resets
Bit Range
Bits
0000
0000
PIC32MM0064GPL036 FAMILY
DS60001324C-page 176
21.1
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
REGISTER 21-1:
Bit
Range
31:24
23:16
15:8
7:0
HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
Bit
Bit
31/23/15/7 30/22/14/6
U-0
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
R/W-0
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
ON
—
SIDL
—
VDIR
BGVST
IRVST
HLEVT
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
HLVDL
Legend:
HC = Hardware Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: HLVD Power Enable bit
1 = HLVD is enabled
0 = HLVD is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: HLVD Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
Unimplemented: Read as ‘0’
bit 11
VDIR: Voltage Change Direction Select bit
1 = Event occurs when voltage equals or exceeds the trip point (HLVDL)
0 = Event occurs when voltage equals or falls below the trip point (HLVDL)
bit 10
BGVST: Band Gap Voltage Stable Flag bit
1 = Indicates that the band gap voltage is stable
0 = Indicates that the band gap voltage is unstable
bit 9
IRVST: Internal Reference Voltage Stable Flag bit
1 = Internal reference voltage is stable; the High-Voltage Detect logic generates the interrupt flag at the
specified voltage range
0 = Internal reference voltage is unstable; the High-Voltage Detect logic will not generate the interrupt flag
at the specified voltage range and the HLVD interrupt should not be enabled
bit 8
HLEVT: High/Low-Voltage Detection Event Status bit
1 = Indicates HLVD event is active
0 = Indicates HLVD event is not active
bit 7-4
Unimplemented: Read as ‘0’
Note 1:
The voltage is typical. It is for design guidance only and not tested. Refer to Table 26-13 in Section 26.0
“Electrical Characteristics” for minimum and maximum values.
2015-2018 Microchip Technology Inc.
DS60001324C-page 177
PIC32MM0064GPL036 FAMILY
REGISTER 21-1:
HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER (CONTINUED)
bit 3-0
HLVDL: High/Low-Voltage Detection Limit bits
1111 = External analog input is used (input comes from the LVDIN pin and is compared with 1.2V band gap)
1110 = VDD trip point is 2.11V(1)
1101 = VDD trip point is 2.21V(1)
1100 = VDD trip point is 2.30V(1)
1011 = VDD trip point is 2.40V(1)
1010 = VDD trip point is 2.52V(1)
1001 = VDD trip point is 2.63V(1)
1000 = VDD trip point is 2.82V(1)
0111 = VDD trip point is 2.92V(1)
0110 = VDD trip point is 3.13V(1)
0101 = VDD trip point is 3.44V(1)
0100-0000 = Reserved; do not use
Note 1:
The voltage is typical. It is for design guidance only and not tested. Refer to Table 26-13 in Section 26.0
“Electrical Characteristics” for minimum and maximum values.
DS60001324C-page 178
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
22.0
Note:
POWER-SAVING FEATURES
This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To complement the information in this data sheet,
refer to Section 10. “Power-Saving
Modes” (DS60001130) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32). The information in this data sheet supersedes the
information in the FRM.
This section describes power-saving features for the
PIC32MM0064GPL036 family devices. These devices
offer various methods and modes that allow the application to balance power consumption with device
performance. In all of the methods and modes
described in this section, power saving is controlled by
software. The peripherals and CPU can be halted or
disabled to reduce power consumption.
22.1
Sleep Mode
In Sleep mode, the CPU and most peripherals are
halted, and the associated clocks are disabled. Some
peripherals can continue to operate in Sleep mode and
can be used to wake the device from Sleep. See the
individual peripheral module sections for descriptions
of behavior in Sleep. The device enters Sleep mode
when the SLPEN bit (OSCCON) is set and a WAIT
instruction is executed.
Sleep mode includes the following characteristics:
• There can be a wake-up delay based on the
oscillator selection.
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode.
• The BOR circuit remains operative during Sleep mode.
• If WDT is enabled, the Run mode counter is not
cleared upon entry to Sleep and the Sleep mode
counter is reset upon entering Sleep.
• Some peripherals can continue to operate at
limited functionality in Sleep mode. These peripherals include I/O pins that detect a change in the
input signal, WDT, ADC, UART and peripherals
that use an external clock input or the internal
LPRC oscillator (e.g., RTCC and Timer1).
• I/O pins continue to sink or source current in the same
manner as they do when the device is not in Sleep.
• The on-chip regulator enters Standby mode if the
VREGS bit (PWRCON) is set.
• A separate special low-power, low-voltage/
retention regulator is activated if the RETVR
Configuration bit (FPOR) is programmed to
zero and the RETEN bit (PWRCON) is set.
2015-2018 Microchip Technology Inc.
The processor will exit, or “wake-up”, from Sleep on
one of the following events:
• On any interrupt from an enabled source that is
operating in Sleep. The interrupt priority must be
greater than the current CPU priority.
• On any form of device Reset.
• On a WDT time-out.
If the interrupt priority is lower than, or equal to, the
current priority, the CPU will remain halted, but the
Peripheral Bus Clock (PBCLK) will start running and
the device will enter into Idle mode. To set or clear the
SLPEN bit, an unlock sequence must be executed.
Refer to Section 23.4 “System Registers Write
Protection” for details.
22.2
Idle Mode
In Idle mode, the CPU is halted; however, all clocks are
still enabled. This allows peripherals to continue to
operate. Peripherals can be individually configured to
halt when entering Idle by setting their respective SIDL
bit. Latency, when exiting Idle mode, is very low due to
the CPU oscillator source remaining active.
The device enters Idle mode when the SLPEN bit
(OSCCON) is clear and a WAIT instruction is
executed.
The processor will wake or exit from Idle mode on the
following events:
• On any interrupt event for which the interrupt
source is enabled. The priority of the interrupt
event must be greater than the current priority of
the CPU. If the priority of the interrupt event is
lower than, or equal to, the current priority of the
CPU, the CPU will remain halted and the device
will remain in Idle mode.
• On any form of device Reset.
• On a WDT time-out interrupt.
To set or clear the SLPEN bit, an unlock sequence
must be executed. Refer to Section 23.4 “System
Registers Write Protection” for details.
DS60001324C-page 179
PIC32MM0064GPL036 FAMILY
22.3
Peripheral Module Disable
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers do not take effect and read
values are invalid.
To disable a peripheral, the associated PMDx bit must
be set to ‘1’. To enable a peripheral, the associated
PMDx bit must be cleared (default).
TABLE 22-1:
To prevent accidental configuration changes under
normal operation, writes to the PMDx registers are not
allowed. Attempted writes appear to execute normally,
but the contents of the registers remain unchanged. To
change these registers, they must be unlocked in
hardware. The register lock is controlled by the
PMDLOCK bit in PMDCON register (PMDCON).
Setting PMDLOCK prevents writes to the control
registers; clearing PMDLOCK allows writes. To set or
clear PMDLOCK, an unlock sequence must be
executed. Refer to Section 23.4 “System Registers
Write Protection” for details.
Table 22-1 lists the module disable bits and locations
for all modules.
PERIPHERAL MODULE DISABLE BITS AND LOCATIONS
Peripheral
PMDx Bit Name
Register Name and Bit Location
Analog-to-Digital Converter (ADC)
ADCMD
PMD1
Voltage Reference (VR)
VREFMD
PMD1
High/Low-Voltage Detect (HLVD)
HLVDMD
PMD1
Comparator 1 (CMP1)
CMP1MD
PMD2
Comparator 2 (CMP2)
CMP2MD
PMD2
Configurable Logic Cell 1 (CLC1)
CLC1MD
PMD2
Configurable Logic Cell 2 (CLC2)
CLC2MD
PMD2
Multiple Outputs Capture/Compare/PWM/
Timer1 (MCCP1)
CCP1MD
PMD3
Single Output Capture/Compare/PWM/Timer2
(SCCP2)
CCP2MD
PMD3
Single Output Capture/Compare/PWM/Timer3
(SCCP3)
CCP3MD
PMD3
Timer1 (TMR1)
T1MD
PMD4
Universal Asynchronous Receiver
Transmitter 1 (UART1)
U1MD
PMD5
Universal Asynchronous Receiver
Transmitter 2 (UART2)
U2MD
PMD5
Serial Peripheral Interface 1 (SPI1)
SPI1MD
PMD5
Serial Peripheral Interface 2 (SPI2)
SPI2MD
PMD5
Real-Time Clock and Calendar (RTCC)
RTCCMD
PMD6
Reference Clock Output (REFCLKO)
REFOMD
PMD6
CRCMD
PMD7
Programmable Cyclic Redundancy Check
(CRC)
DS60001324C-page 180
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
On-Chip Voltage Regulator
Low-Power Modes
22.4
The main on-chip regulator always consumes an incremental amount of current over IDD/IPD, including when
the device is in Sleep mode, even though the core digital
logic does not require power. To provide additional
savings in applications where power resources are
critical, the regulator can be made to enter Standby mode
TABLE 22-2:
and/or Retention mode. Standby mode is controlled by
the VREGS bit (PWRCON), and Retention mode is
controlled by the RETEN (PWRCON) and RETVR
(FPOR) bits. The available Regulator Low-Power
modes are listed in Table 22-2. For more information
about the wake-up time and the current consumption for
different modes, refer to the electrical specifications listed
in Table 26-6 and Table 26-22.
VOLTAGE REGULATOR LOW-POWER MODES
VREGS Bit
(PWRCON)
RETEN Bit
(PWRCON)
RETVR Bit
(FPOR)
Wake-up Time
(Table 26-22)
Current
(Table 26-6)
Normal
1
0
1
Fastest
Highest
Standby Only
0
0
1
Medium
Medium
Retention Only
1
1
0
Medium
Medium
Standby and
Retention
0
1
0
Slowest
Lowest
Mode
22.4.1
REGULATOR STANDBY MODE
Whenever the device goes into Sleep mode, the
regulator can be made to enter Standby mode. This
feature is controlled by the VREGS bit (PWRCON).
Clearing the VREGS bit enables Standby mode. If
Standby mode is used, the voltage regulator needs
some time to switch to normal operation mode and
generate output. During this time, the code execution is
disabled. The delay is applied every time the device
resumes operation after Standby mode.
22.4.2
REGULATOR RETENTION MODE
When in Sleep mode, the device can use a separate
low-power, low-voltage/retention regulator to power
critical circuits. This regulator, which operates at 1V
nominal, maintains power to data RAM, WDT, Timer1
2015-2018 Microchip Technology Inc.
and the RTCC, while all other core digital logic is
powered down. The low-voltage/retention regulator is
available only when Sleep mode is invoked. It is controlled by the RETVR Configuration bit (FPOR) and
in firmware by the RETEN bit (PWRCON). RETVR
must be programmed to zero (= 0) and the RETEN bit
must be set (= 1) for the retention regulator to be
enabled.
22.5
Low-Power Brown-out Reset
The PIC32MM0064GPL036 family devices have a
second low-power Brown-out Reset circuit with a
reduced precision of the trip point. This low-power BOR
circuit can be activated when the main BOR is disabled.
The circuit is enabled by programming the LPBOREN
Configuration bit (FPOR) to ‘1’.
DS60001324C-page 181
Virtual Address
(BF80_#)
Register
Name(1)
2C00
PMDCON
2C10
PMD1
PMD2
2C30
PMD3
2C50
PMD4
PMD5
2C60
PMD6
2C70
PMD7
31/15
30/14
29/13
28/12
31:16
—
—
—
15:0
—
—
—
31:16
—
—
15:0
—
31:16
15:0
All Resets
Bit Range
Bits
2C20
2C40
PERIPHERAL MODULE DISABLE REGISTER MAP
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
PMDLOCK
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
HLVDMD
—
—
—
—
FFEF
—
—
VREFMD
—
—
—
—
—
—
—
—
—
—
—
ADCMD
EFFE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FCFF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FFFF
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
F8FF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FFFF
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T1MD
FFFE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
r
r
FFFC
15:0
—
—
—
—
—
—
SPI2MD
SPI1MD
—
—
—
—
—
—
U2MD
U1MD
FCFC
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FFFF
15:0
—
—
—
—
—
—
—
REFOMD
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FFFF
15:0
—
—
—
—
—
—
—
—
—
—
—
—
CRCMD
—
—
—
FFF7
CLC2MD CLC1MD
CCP3MD CCP2MD CCP1MD
Legend: — = unimplemented, read as ‘1’; r = reserved bit, maintain as ‘1’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively.
CMP2MD CMP1MD FFFC
RTCCMD FEFE
PIC32MM0064GPL036 FAMILY
DS60001324C-page 182
TABLE 22-3:
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
23.0
Note:
23.1
SPECIAL FEATURES
This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 33. “Programming
and Diagnostics” (DS61129) in the
“PIC32 Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32). The information in this data sheet supersedes the
information in the FRM.
Code Execution from RAM
PIC32MM0064GPL036 family devices allow executing
the code from RAM. The starting boundary of this
special RAM space can be adjusted using the
EXECADDR bits in the CFGCON register with a
1-Kbyte step. Writing a non-zero value to these bits will
move the boundary, effectively reducing the total
amount of program memory space in RAM. Refer to
Table 23-5 and Register 23-7 for more information.
23.3
To unlock the registers, the following steps should be
done:
1.
2.
5.
Disable interrupts prior to the system unlock
sequence.
Execute the system unlock sequence by writing
the key values of 0xAA996655 and
0x556699AA to the SYSKEY register, in two
back-to-back assembly or ‘C’ instructions.
Write the new value to the required register.
Write a non-key value (such as 0x00000000) to
the SYSKEY register to perform a lock.
Re-enable interrupts.
The registers that require this unlocking sequence are
listed in Table 23-2.
TABLE 23-2:
Register
Name
The Device ID identifies the device used. The ID can be
read from the DEVID register. The Device IDs for
PIC32MM0064GPL036 family devices are listed in
Table 23-1. Also refer to Table 23-5 and Register 23-8
for more information.
DEVICE IDs FOR
PIC32MM0064GPL036 FAMILY
DEVICES
Device
DEVID
PIC32MM0016GPL020
0x06B04053
PIC32MM0032GPL020
0x06B0C053
PIC32MM0064GPL020
0x06B14053
PIC32MM0016GPL028
0x06B02053
PIC32MM0032GPL028
0x06B0A053
PIC32MM0064GPL028
0x06B12053
PIC32MM0016GPL036
0x06B06053
PIC32MM0032GPL036
0x06B0E053
PIC32MM0064GPL036
0x06B16053
2015-2018 Microchip Technology Inc.
SYSTEM LOCKED REGISTERS
Register Description
Peripheral
OSCCON
Oscillator Control
Oscillator
SPLLCON
System PLL Control
Oscillator
OSCTUN
FRC Tuning
Oscillator
PMDCON
Peripheral Module
Disable Control
PMD
RSWRST
RPCON
Device ID
TABLE 23-1:
System Registers Write Protection
The critical registers in the PIC32MM0064GPL036 family
devices are protected (locked) from an accidental write.
If the registers are locked, a special unlock sequence is
required to modify the content of these registers.
3.
4.
Configuration Bits
PIC32MM0064GPL036 family devices contain a
Boot Flash Memory (BFM) with an associated configuration space. All Configuration Words are listed
in Table 23-3 and Table 23-4; Register 23-1 through
Register 23-6 describe the configuration options.
23.2
23.4
RNMICON
Software Reset
Reset
Peripheral Pin Select
Configuration
I/O Ports
Non-Maskable Interrupt
Control
Reset
PWRCON
Power Control
Reset
RTCCON1
RTCC Control 1
RTCC
The SYSKEY register read value indicates the status.
A value of ‘0’ indicates the system registers are locked.
A value of ‘1’ indicates the system registers are
unlocked. For more information about the SYSKEY
register, refer to Table 23-5 and Register 23-9.
DS60001324C-page 183
PIC32MM0064GPL036 FAMILY
23.5
Band Gap Voltage Reference
PIC32MM0064GPL036 family devices have a precision
voltage reference band gap circuit used by many
modules. The analog buffers are implemented between
the band gap circuit and these modules. The buffers
are automatically enabled by the hardware if some part
of the device needs the band gap reference. The stabilization time is required when the buffer is switched on.
The software can enable these buffers in advance to
allow the band gap voltage to stabilize before the
module uses it. The ANCFG register contains bits to
enable the band gap buffers for the comparators
(VBGCMP bit) and ADC (VBGADC bit). Refer to
Table 23-6 and Register 23-10 for more information.
23.6
Programming and Diagnostics
PIC32MM0064GPL036 family devices provide a
complete range of programming and diagnostic
features:
• Simplified Field Programmability using Two-Wire
In-Circuit Serial Programming™ (ICSP™)
Interfaces
• Debugging using ICSP
• Programming and Debugging Capabilities using
the EJTAG Extension of JTAG
• JTAG Boundary Scan Testing for Device and
Board Diagnostics
DS60001324C-page 184
23.7
Unique Device Identifier (UDID)
PIC32MM0064GPL036 family devices are individually
encoded during final manufacturing with a Unique
Device Identifier or UDID. The UDID cannot be erased
by a bulk erase command or any other user accessible
means. This feature allows for manufacturing traceability of Microchip Technology devices in applications
where this is a requirement. It may also be used by the
application manufacturer for any number of things that
may require unique identification, such as:
• Tracking the device
• Unique serial number
• Unique security key
The UDID comprises five 32-bit program words. When
taken together, these fields form a unique 160-bit
identifier.
The UDID is stored in five read-only locations, located
from 0xBFC41840 to 0xBFC41854 in the device
configuration space. Table 23-7 lists the addresses of
the Identifier Words.
23.8
Reserved Registers
PIC32MM0064GPL036 family devices have 3 reserved
registers, located at 0xBF800400, 0xBF800480 and
0xBF802280. The application code must not modify
these reserved locations. Table 23-8 lists the addresses
of these reserved registers.
2015-2018 Microchip Technology Inc.
Configuration Words and System Registers
CONFIGURATION WORDS SUMMARY
Register
Name
TABLE 23-3:
Virtual Address
(BFC0_#)
17C0
RESERVED
17C4
17C8
Bits
FDEVOPT
FICD
FPOR
17D0
FWDT
17D4
FOSCSEL
17D8
FSEC
17DC
17E0
17E4
RESERVED
RESERVED
RESERVED
31\15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
15:0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
31:16
USERID
15:0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
SOSCHP
r-1
r-1
r-1
31:16
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
15:0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
JTAGEN
r-1
r-1
31:16
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
15:0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
LPBOREN
RETVR
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
31:16
15:0
31:16
15:0
FWDTEN RCLKSEL
r-1
RWDTPS
r-1
r-1
r-1
r-1
FCKSM
r-1
SOSCSEL
r-1
r-1
r-1
WINDIS
r-1
r-1
OSCIOFNC POSCMOD
ICS
FWDTWINSZ
BOREN
r-1
r-1
r-1
r-1
SWDTPS
r-1
r-1
r-1
r-1
r-1
IESO
SOSCEN
r-1
PLLSRC
r-1
r-1
FNOSC
31:16
CP
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
15:0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
31:16
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
15:0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
31:16
r-0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
15:0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
31:16
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
15:0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
Legend: r-0 = Reserved bit, must be programmed as ‘0’; r-1 = Reserved bit, must be programmed as ‘1’.
DS60001324C-page 185
PIC32MM0064GPL036 FAMILY
17CC
Bit Range
2015-2018 Microchip Technology Inc.
23.9
Virtual Address
(BFC0_#)
Register
Name
ALTERNATE CONFIGURATION WORDS SUMMARY
1740
RESERVED
1744
1748
AFDEVOPT
AFICD
174C
AFPOR
1750
AFWDT
1754
AFOSCSEL
1758
AFSEC
175C
1760
1764
RESERVED
RESERVED
RESERVED
Bit Range
Bits
31\15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
15:0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
31:16
USERID
15:0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
SOSCHP
r-1
r-1
r-1
31:16
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
15:0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
JTAGEN
r-1
r-1
31:16
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
15:0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
31:16
r-1
15:0
FWDTEN
RCLKSEL
RWDTPS
r-1
r-1
WINDIS
31:16
r-1
r-1
r-1
r-1
r-1
15:0
FCKSM
r-1
SOSCSEL
r-1
r-1
31:16
CP
r-1
r-1
r-1
r-1
r-1
r-1
15:0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
31:16
r-1
r-1
r-1
r-1
r-1
r-1
15:0
r-1
r-1
r-1
r-1
r-1
31:16
r-0
r-1
r-1
r-1
15:0
r-1
r-1
r-1
31:16
r-1
r-1
15:0
r-1
r-1
r-1
ICS
r-1
LPBOREN RETVR
r-1
FWDTWINSZ
BOREN
r-1
r-1
r-1
r-1
r-1
SWDTPS
r-1
r-1
r-1
r-1
r-1
IESO
SOSCEN
r-1
PLLSRC
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
OSCIOFNC POSCMOD
Legend: r-0 = Reserved bit, must be programmed as ‘0’; r-1 = Reserved bit, must be programmed as ‘1’.
r-1
FNOSC
PIC32MM0064GPL036 FAMILY
DS60001324C-page 186
TABLE 23-4:
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
REGISTER 23-1:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
R/P
FDEVOPT/AFDEVOPT: DEVICE OPTIONS CONFIGURATION REGISTER
Bit
Bit
30/22/14/6 29/21/13/5
R/P
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
USERID
R/P
R/P
R/P
R/P
R/P
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
USERID
r-1
r-1
r-1
r-1
R/P
r-1
r-1
r-1
—
—
—
—
SOSCHP
—
—
—
Legend:
r = Reserved bit
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 USERID: User ID bits (2 bytes which can be programmed to any value)
bit 15-4
Reserved: Program as ‘1’
bit 3
SOSCHP: Secondary Oscillator (SOSC) High-Power Enable bit
1 = SOSC operates in Normal Power mode
0 = SOSC operates in High-Power mode
bit 2-0
Reserved: Program as ‘1’
2015-2018 Microchip Technology Inc.
DS60001324C-page 187
PIC32MM0064GPL036 FAMILY
REGISTER 23-2:
Bit
Range
31:24
23:16
15:8
7:0
FICD/AFICD: ICD/DEBUG CONFIGURATION REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
R/P
r-1
r-1
r-1
—
—
—
R/P
ICS
R/P
r-1
r-1
JTAGEN
—
—
Legend:
r = Reserved bit
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-5
Reserved: Program as ‘1’
bit 4-3
ICS: ICE/ICD Communication Channel Selection bits
11 = Communicates on PGEC1/PGED1
10 = Communicates on PGEC2/PGED2
01 = Communicates on PGEC3/PGED3
00 = Not connected
bit 2
JTAGEN: JTAG Enable bit
1 = JTAG is enabled
0 = JTAG is disabled
bit 1-0
Reserved: Program as ‘1’
DS60001324C-page 188
x = Bit is unknown
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
REGISTER 23-3:
Bit
Range
31:24
23:16
15:8
7:0
FPOR/AFPOR: POWER-UP SETTINGS CONFIGURATION REGISTER
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
R/P
R/P
r-1
r-1
r-1
r-1
R/P
R/P
—
—
—
—
LPBOREN
RETVR
BOREN
Legend:
r = Reserved bit
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4
Reserved: Program as ‘1’
bit 3
LPBOREN: Low-Power BOR Enable bit
1 = Low-Power BOR is enabled when the main BOR is disabled
0 = Low-Power BOR is disabled
bit 2
RETVR: Retention Voltage Regulator Enable bit
1 = Retention regulator is disabled
0 = Retention regulator is enabled and controlled by the RETEN bit during Sleep
bit 1-0
BOREN: Brown-out Reset Enable bits
11 = Brown-out Reset is enabled in hardware; SBOREN bit is disabled
10 = Brown-out Reset is enabled only while device is active and is disabled in Sleep; SBOREN bit is disabled
01 = Brown-out Reset is controlled with the SBOREN bit setting
00 = Brown-out Reset is disabled in hardware; SBOREN bit is disabled
2015-2018 Microchip Technology Inc.
DS60001324C-page 189
PIC32MM0064GPL036 FAMILY
REGISTER 23-4:
Bit
Range
31:24
23:16
15:8
7:0
FWDT/AFWDT: WATCHDOG TIMER CONFIGURATION REGISTER
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
FWDTEN
R/P
WINDIS
RCLKSEL
R/P
R/P
RWDTPS
FWDTWINSZ
R/P
SWDTPS
Legend:
r = Reserved bit
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Reserved: Program as ‘1’
bit 15
FWDTEN: Watchdog Timer Enable bit
1 = WDT is enabled
0 = WDT is disabled
bit 14-13 RCLKSEL: Run Mode Watchdog Timer Clock Source Selection bits
11 = Clock source is the LPRC oscillator (same as for Sleep mode)
10 = Clock source is the FRC oscillator
01 = Reserved
00 = Clock source is the system clock
bit 12-8
RWDTPS: Run Mode Watchdog Timer Postscale Select bits
From 10100 to 11111 = 1:1048576.
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
bit 7
WINDIS: Windowed Watchdog Timer Disable bit
1 = Windowed mode is disabled
0 = Windowed mode is enabled
DS60001324C-page 190
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
REGISTER 23-4:
FWDT/AFWDT: WATCHDOG TIMER CONFIGURATION REGISTER (CONTINUED)
bit 6-5
FWDTWINSZ: Watchdog Timer Window Size bits
11 = Watchdog Timer window size is 25%
10 = Watchdog Timer window size is 37.5%
01 = Watchdog Timer window size is 50%
00 = Watchdog Timer window size is 75%
bit 4-0
SWDTPS: Sleep Mode Watchdog Timer Postscale Select bits
From 10100 to 11111 = 1:1048576.
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
2015-2018 Microchip Technology Inc.
DS60001324C-page 191
PIC32MM0064GPL036 FAMILY
REGISTER 23-5:
Bit
Range
31:24
23:16
15:8
7:0
FOSCSEL/AFOSCSEL: OSCILLATOR SELECTION CONFIGURATION
REGISTER
Bit
Bit
31/23/15/7 30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
R/P
R/P
r-1
R/P
r-1
R/P
R/P
R/P
—
SOSCSEL
—
OSCIOFNC
R/P
FCKSM
R/P
r-1
R/P
r-1
R/P
IESO
SOSCEN
—
PLLSRC
—
POSCMOD
R/P
R/P
FNOSC
Legend:
r = Reserved bit
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Reserved: Program as ‘1’
bit 15-14
FCKSM: Clock Switching and Fail-Safe Clock Monitor Enable bits
11 = Clock switching is enabled; Fail-Safe Clock Monitor is enabled
10 = Clock switching is disabled; Fail-Safe Clock Monitor is enabled
01 = Clock switching is enabled; Fail-Safe Clock Monitor is disabled
00 = Clock switching is disabled; Fail-Safe Clock Monitor is disabled
bit 13
Reserved: Program as ‘1’
bit 12
SOSCSEL: Secondary Oscillator (SOSC) External Clock Enable bit
1 = Crystal is used (RA4 and RB4 pins are controlled by SOSC)
0 = External clock is connected to the SOSCO pin (RA4 and RB4 pins are controlled by I/O PORTx registers)
bit 11
Reserved: Program as ‘1’
bit 10
OSCIOFNC: System Clock on CLKO Pin Enable bit
1 = OSC2/CLKO pin operates as normal I/O
0 = System clock is connected to the OSC2/CLKO pin
bit 9-8
POSCMOD: Primary Oscillator (POSC) Mode Selection bits
11 = Primary Oscillator is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = External Clock (EC) mode is selected
bit 7
IESO: Two-Speed Start-up Enable bit
1 = Two-Speed Start-up is enabled
0 = Two-Speed Start-up is disabled
bit 6
SOSCEN: Secondary Oscillator (SOSC) Enable bit
1 = Secondary Oscillator is enabled
0 = Secondary Oscillator is disabled
bit 5
Reserved: Program as ‘1’
bit 4
PLLSRC: System PLL Input Clock Selection bit
1 = FRC oscillator is selected as the PLL reference input on a device Reset
0 = Primary Oscillator (POSC) is selected as the PLL reference input on a device Reset
bit 3
Reserved: Program as ‘1’
DS60001324C-page 192
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
REGISTER 23-5:
bit 2-0
FNOSC: Oscillator Selection bits
110 and 111 = Reserved (selects Fast RC (FRC) Oscillator with Divide-by-N)
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Reserved
010 = Primary Oscillator (XT, HS, EC)
001 = Primary or FRC Oscillator with PLL
000 = Fast RC (FRC) Oscillator with Divide-by-N
REGISTER 23-6:
Bit
Range
31:24
23:16
15:8
7:0
FOSCSEL/AFOSCSEL: OSCILLATOR SELECTION CONFIGURATION
REGISTER (CONTINUED)
FSEC/AFSEC: CODE-PROTECT CONFIGURATION REGISTER
Bit
Bit
31/23/15/7 30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/P
r-1
r-1
r-1
r-1
r-1
r-1
r-1
CP
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
Legend:
r = Reserved bit
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
CP: Code Protection Enable bit
1 = Code protection is disabled
0 = Code protection is enabled
bit 30-0
Reserved: Program as ‘1’
2015-2018 Microchip Technology Inc.
x = Bit is unknown
DS60001324C-page 193
Register
Name
CFGCON
3B20
3B30
DEVID
SYSKEY
Bit Range
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
15:0
31:16
15:0
23/7
22/6
21/5
—
—
—
19/3
18/2
17/1
16/0
—
—
—
EXECADDR
VER
ID
ID
SYSKEY
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Reset values are dependent on the device variant.
20/4
—
JTAGEN
All Resets(1)
Virtual Address
(BF80_#)
3B00
RAM CONFIGURATION, DEVICE ID AND SYSTEM LOCK REGISTERS MAP
0000
000x
xxxx
xxxx
0000
0001
PIC32MM0064GPL036 FAMILY
DS60001324C-page 194
TABLE 23-5:
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
REGISTER 23-7:
Bit
Range
31:24
23:16
15:8
7:0
CFGCON: CONFIGURATION CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
Bit
25/17/9/1
Bit
24/16/8/0
U-0
r-0
U-0
r-0
r-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
R/W-y
U-0
r-1
r-1
—
JTAGEN
—
—
—
EXECADDR
Legend:
r = Reserved bit
y = Value set from Configuration bits on Reset
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 Unimplemented: Read as ‘0’
bit 27
Reserved: Must be written as ‘0’
bit 26
Unimplemented: Read as ‘0’
bit 25-24 Reserved: Must be written as ‘0’
bit 23-16 EXECADDR: RAM Program Space Start Address bits
11111111 = RAM program space starts at the 255-Kbyte boundary (from 0xA003FC00)
•
•
•
00000010 = RAM program space starts at the 2-Kbyte boundary (from 0xA0000800)
00000001 = RAM program space starts at the 1-Kbyte boundary (from 0xA0000400)
00000000 = All data RAM is allocated to program space (from 0xA0000000)
bit 15-4
Unimplemented: Read as ‘0’
bit 3
JTAGEN: JTAG Enable bit
1 = JTAG port is enabled
0 = JTAG port is disabled
The Reset value of this bit is the value of the JTAGEN (FICD) Configuration bit.
bit 2
Unimplemented: Read as ‘0’
bit 1-0
Reserved: Must be written as ‘1’
2015-2018 Microchip Technology Inc.
DS60001324C-page 195
PIC32MM0064GPL036 FAMILY
REGISTER 23-8:
Bit
Range
31:24
23:16
15:8
7:0
DEVID: DEVICE ID REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
VER(1)
ID(1)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
ID
R-x
(1)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
ID(1)
R-x
R-x
R-x
R-x
ID(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 VER: Revision Identifier bits(1)
bit 27-0
DEVID: Device ID bits(1)
Note 1:
Reset values are dependent on the device variant.
REGISTER 23-9:
Bit
Range
31:24
23:16
15:8
7:0
SYSKEY: SYSTEM UNLOCK REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
W-0
W-0
W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
SYSKEY
W-0
W-0
W-0
W-0
W-0
SYSKEY
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
SYSKEY
W-0
W-0
SYSKEY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
SYSKEY: Unlock and Lock Key bits
DS60001324C-page 196
2015-2018 Microchip Technology Inc.
Virtual Address
(BF80_#)
Register
Name
2300
ANCFG(1)
BAND GAP REGISTER MAP
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
All Resets
Bits
Bit Range
2015-2018 Microchip Technology Inc.
TABLE 23-6:
18/2
17/1
16/0
—
—
—
0000
—
0000
VBGADC VBGCMP
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
PIC32MM0064GPL036 FAMILY
DS60001324C-page 197
PIC32MM0064GPL036 FAMILY
REGISTER 23-10: ANCFG: BAND GAP CONTROL REGISTER
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6
31:24
23:16
15:8
7:0
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0, HS, HC
R/W-0, HS, HC
U-0
—
—
—
—
—
VBGADC
VBGCMP
—
Legend:
HC = Hardware Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-3 Unimplemented: Read as ‘0’
bit 2
VBGADC: ADC Band Gap Enable bit
1 = ADC band gap is enabled
0 = ADC band gap is disabled
bit 1
VBGCMP: Comparator Band Gap Enable bit
1 = Comparator band gap is enabled
0 = Comparator band gap is disabled
bit 0
Unimplemented: Read as ‘0’
DS60001324C-page 198
2015-2018 Microchip Technology Inc.
Virtual Address
(BF80_#)
Register
Name
1840
UDID1
1844
1848
184C
UDID2
UDID3
UDID4
UDID5
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
xxxx
UDID Word 1
15:0
All Resets
Bits
xxxx
31:16
xxxx
UDID Word 2
15:0
xxxx
31:16
xxxx
UDID Word 3
15:0
xxxx
31:16
xxxx
UDID Word 4
15:0
xxxx
31:16
xxxx
UDID Word 5
15:0
xxxx
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Register
Name
RESERVED REGISTERS MAP
Virtual Address
(BF80_#)
TABLE 23-8:
0400
RESERVED1
0480
2280
RESERVED2
RESERVED3
31:16
15:0
31:16
15:0
31:16
15:0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
Reserved Register 1
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Bits
0000
0000
Reserved Register 2
0000
0000
Reserved Register 3
DS60001324C-page 199
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0C00
0000
PIC32MM0064GPL036 FAMILY
1850
UNIQUE DEVICE IDENTIFIER (UDID) REGISTER MAP
Bit Range
2015-2018 Microchip Technology Inc.
TABLE 23-7:
PIC32MM0064GPL036 FAMILY
NOTES:
DS60001324C-page 200
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
24.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
24.1
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2015-2018 Microchip Technology Inc.
DS60001324C-page 201
PIC32MM0064GPL036 FAMILY
24.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16 and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other
relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler
to produce its object file. Notable features of the
assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
24.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
24.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
24.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS60001324C-page 202
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
24.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
24.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2015-2018 Microchip Technology Inc.
24.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
24.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the
target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
24.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
DS60001324C-page 203
PIC32MM0064GPL036 FAMILY
24.11 Demonstration/Development
Boards, Evaluation Kits and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
24.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS60001324C-page 204
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
25.0
INSTRUCTION SET
The PIC32MM0064GPL036 family instruction set
complies with the MIPS® Release 3 instruction set
architecture. Only microMIPS32™ instructions are
supported. The PIC32MM0064GPL036 family does not
have the following features:
• Core extend instructions
• Coprocessor 1 instructions
• Coprocessor 2 instructions
Note:
Refer to the “MIPS® Architecture for
Programmers
Volume
II-B:
The
microMIPS32™ Instruction Set” at
www.imgtec.com for more information.
2015-2018 Microchip Technology Inc.
DS60001324C-page 205
PIC32MM0064GPL036 FAMILY
NOTES:
DS60001324C-page 206
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
26.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC32MM0064GPL036 family electrical characteristics. Additional information
will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC32MM0064GPL036 family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other
conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +4.0V
Voltage on any general purpose digital or analog pin (not 5.5V tolerant) with respect to VSS ....... -0.3V to (VDD + 0.3V)
Voltage on any general purpose digital or analog pin (5.5V tolerant) with respect to VSS:
When VDD = 0V: .......................................................................................................................... -0.3V to +4.0V
When VDD 2.0V: ....................................................................................................................... -0.3V to +6.0V
Voltage on AVDD with respect to VSS ..........................................................................................................................VDD
Voltage on AVSS with respect to VSS .......................................................................................................................... VSS
Maximum current out of VSS pin ...........................................................................................................................100 mA
Maximum current into VDD pin(1) ...........................................................................................................................300 mA
Maximum output current sunk by I/O pin ................................................................................................................ 11 mA
Maximum output current sourced by I/O pin ...........................................................................................................16 mA
Maximum output current sunk by I/O pin with increased current drive strength (RA3, RB8, RB9 and RB15) ........17 mA
Maximum output current sourced by I/O pin with increased current drive strength (RA3, RB8, RB9 and RB15) ..........24 mA
Maximum current sunk by all ports .......................................................................................................................300 mA
Maximum current sourced by all ports(1) ...............................................................................................................300 mA
Note 1:
†
Maximum allowable current is a function of device maximum power dissipation (see Table 26-1).
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
2015-2018 Microchip Technology Inc.
DS60001324C-page 207
PIC32MM0064GPL036 FAMILY
26.1
DC Characteristics
FIGURE 26-1:
PIC32MM0064GPL036 FAMILY VOLTAGE-FREQUENCY GRAPH
3.6V
Voltage (VDD)
3.6V
PIC32MM00XXGPL0XX
2.0V(1)
2.0V(1)
25 MHz
DC
Frequency
Note 1:
TABLE 26-1:
Lower operating boundary is 2.0V or VBOR when BOR is enabled.
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
TJ
-40
—
+100
°C(1)
TJ
-40
—
+140
°C(2)
TA
-40
—
+85
°C(1)
TA
-40
—
+125
°C(2)
PIC32MM00XXGPL0XX:
Operating Junction Temperature Range
PIC32MM00XXGPL0XX:
Operating Ambient Temperature Range
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
I/O Pin Power Dissipation:
PI/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
Note 1:
2:
85°C rated parts.
125°C rated parts.
DS60001324C-page 208
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
TABLE 26-2:
PACKAGE THERMAL RESISTANCE(1)
Package
Symbol
Typ
Unit
20-Pin SSOP
JA
87.3
°C/W
20-Pin QFN
JA
43.0
°C/W
28-Pin SPDIP
JA
60.0
°C/W
28-Pin SSOP
JA
71.0
°C/W
28-Pin SOIC
JA
69.7
°C/W
28-Pin UQFN
JA
27.5
°C/W
28-Pin QFN
JA
20.0
°C/W
36-Pin VQFN
JA
31.1
°C/W
40-Pin UQFN
JA
41.0
°C/W
Note 1:
Junction to ambient thermal resistance; Theta-JA (JA) numbers are achieved by package simulations.
TABLE 26-3:
OPERATING VOLTAGE SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
2.0
3.6
V
BOR disabled
BOR enabled
DC10
VDD
Supply Voltage
VBOR
3.6
V
DC16
VPOR(1)
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
VSS
—
V
DC17A
SVDD(1)
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05
—
V/ms
DC17B
VBOR
Brown-out Reset
Voltage on VDD
Transition, High-to-Low
1.94
2.22
V
Note 1:
If the VPOR or SVDD parameters are not met, or the application experiences slow power-down VDD ramp
rates, it is recommended to enable and use BOR.
2015-2018 Microchip Technology Inc.
0-3.3V in 66 ms,
0-2.0V in 40 ms
DS60001324C-page 209
PIC32MM0064GPL036 FAMILY
TABLE 26-4:
OPERATING CURRENT (IDD)(2)
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)
Parameter No.
Typical(1)
Max
Units
VDD
0.45
0.65
mA
2.0V
0.45
0.65
mA
3.3V
2.5
3.5
mA
2.0V
2.5
3.5
mA
3.3V
7.0
9.2
mA
2.0V
7.0
9.2
mA
3.3V
0.26
0.35
mA
2.0V
0.26
0.35
mA
3.3V
0.70
0.90
mA
3.3V
DC19
DC23
DC24
DC25A
DS25B
Note 1:
2:
Conditions
FSYS = 1 MHz
FSYS = 8 MHz
FSYS = 25 MHz
FSYS = 32 kHz
FSYS = 32 kHz, +125°C
Data in the “Typical” column is at +25°C unless otherwise stated. Parameters are for design
guidance only and are not tested.
Base IDD current is measured with:
• Oscillator is configured in EC mode without PLL (FNOSC (FOSCSEL) = 010 and
POSCMOD (FOSCSEL) = 00)
• OSC1 pin is driven with external square wave with levels from 0.3V to VDD – 0.3V
• OSC2 is configured as an I/O in Configuration Words (OSCIOFNC (FOSCSEL) = 1)
• FSCM is disabled (FCKSM (FOSCSEL) = 00)
• Secondary Oscillator circuits are disabled (SOSCEN (FOSCSEL) = 0 and
SOSCSEL (FOSCSEL) = 0)
• Main and low-power BOR circuits are disabled (BOREN (FPOR) = 00 and
LPBOREN (FPOR) = 0)
• Watchdog Timer is disabled (FWDTEN (FWDT) = 0)
• All I/O pins (except OSC1) are configured as outputs and driving low
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• NOP instructions are executed
DS60001324C-page 210
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
TABLE 26-5:
IDLE CURRENT (IIDLE)(2)
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)
Parameter No.
DC40A
DC41A
DC42A
DC44A
DC40B
DC41B
DC42B
DC44B
Typical(1)
Max
Units
VDD
0.26
0.46
mA
2.0V
0.26
0.46
mA
3.3V
0.85
1.5
mA
2.0V
0.85
1.5
mA
3.3V
2.3
3.7
mA
2.0V
2.3
3.7
mA
3.3V
0.18
0.34
mA
2.0V
0.18
0.34
mA
3.3V
0.6
1
mA
2.0V
0.6
1
mA
3.3V
1.4
2.1
mA
2.0V
1.4
2.1
mA
3.3V
2.9
4.3
mA
2.0V
2.9
4.3
mA
3.3V
0.4
0.64
mA
2.0V
0.4
0.64
mA
3.3V
Conditions
FSYS = 1 MHz
FSYS = 8 MHz
FSYS = 25 MHz
FSYS = 32 kHz
FSYS = 1 MHz, +125°C
FSYS = 8 MHz, +125°C
FSYS = 25 MHz, +125°C
FSYS = 32 kHz, +125°C
Data in the “Typical” column is at +25°C unless otherwise stated. Parameters are for design
guidance only and are not tested.
2: Base IIDLE current is measured with:
• Oscillator is configured in EC mode without PLL (FNOSC (FOSCSEL) = 010 and
POSCMOD (FOSCSEL) = 00)
• OSC1 pin is driven with external square wave with levels from 0.3V to VDD – 0.3V
• OSC2 is configured as I/O in Configuration Words (OSCIOFNC (FOSCSEL) = 1)
• FSCM is disabled (FCKSM (FOSCSEL) = 00)
• Secondary Oscillator circuits are disabled (SOSCEN (FOSCSEL) = 0 and
SOSCSEL (FOSCSEL) = 0)
• Main and low-power BOR circuits are disabled (BOREN (FPOR) = 00 and
LPBOREN (FPOR) = 0)
• Watchdog Timer is disabled (FWDTEN (FWDT) = 0)
• All I/O pins (excepting OSC1) are configured as outputs and driving low
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
Note 1:
2015-2018 Microchip Technology Inc.
DS60001324C-page 211
PIC32MM0064GPL036 FAMILY
TABLE 26-6:
POWER-DOWN CURRENT (IPD)(2)
Parameter
Typical(1)
No.
Max
Units
Operating
Temperature
DC60
134
198
µA
-40°C
136
208
µA
+25°C
141
217
µA
+85°C
350
640
µA
+125°C
139
209
µA
-40°C
141
217
µA
+25°C
143
231
µA
+85°C
400
650
µA
+125°C
4.3
11.7
µA
-40°C
5.1
15.6
µA
+25°C
35
55
µA
+85°C
40
90
µA
+125°C
6.1
16.8
µA
-40°C
DC61
DC62
DC63
6.9
20.1
µA
+25°C
12.7
36.0
µA
+85°C
60
100
µA
+125°C
2.3
—
µA
-40°C
2.7
—
µA
+25°C
5.2
—
µA
+85°C
2.3
—
µA
-40°C
2.7
—
µA
+25°C
5.4
—
µA
+85°C
10.1
—
µA
+125°C
0.28
—
µA
-40°C
0.44
—
µA
+25°C
2.52
—
µA
+85°C
0.29
—
µA
-40°C
0.44
—
µA
+25°C
2.62
—
µA
+85°C
10.1
—
µA
+125°C
VDD
Conditions
2.0V
Sleep with active main voltage regulator
(VREGS (PWRCON) = 1,
RETEN (PWRCON) =0)
3.3V
2.0V
Sleep with main voltage regulator in
Standby mode
(VREGS (PWRCON) = 0,
RETEN (PWRCON) = 0)
3.3V
2.0V
3.3V
Sleep with enabled retention voltage
regulator (VREGS (PWRCON) = 1,
RETEN (PWRCON) = 1,
RETVR (FPOR) = 0)
2.0V
3.3V
Sleep with enabled retention voltage
regulator (VREGS (PWRCON) = 0,
RETEN (PWRCON) = 1,
RETVR (FPOR) = 0)
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design
guidance only and are not tested.
2: Base IPD is measured with:
• Oscillator is configured in FRC mode without PLL (FNOSC (FOSCSEL) = 000)
• OSC2 is configured as I/O in Configuration Words (OSCIOFNC (FOSCSEL) = 1)
• FSCM is disabled (FCKSM (FOSCSEL) = 00)
• Secondary Oscillator circuits are disabled (SOSCEN (FOSCSEL) = 0 and
SOSCSEL (FOSCSEL) = 0)
• Main and low-power BOR circuits are disabled (BOREN (FPOR) = 00 and
LPBOREN (FPOR) = 0)
• Watchdog Timer is disabled (FWDTEN (FWDT) = 0)
• All I/O pins are configured as outputs and driving low
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
Note 1:
DS60001324C-page 212
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
TABLE 26-7:
INCREMENTAL PERIPHERALCURRENT(2)
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Parameter No.
Typ(1)
Units
Conditions
Brown-out Reset Incremental Current (BOR)
DC71A
2.7
µA
DC71B
3.4
µA
+125°C
Watchdog Timer Incremental Current (WDT)
DC72A
80
nA
with LPRC
DC72B
140
nA
+125°C with LPRC
High/Low-Voltage Detect Incremental Current (HLVD)
DC73
2.1
µA
Real-Time Clock and Calendar Incremental Current (RTCC)
DC74A
1.0
µA
with SOSC
DC74B
2.0
µA
+125°C with SOSC
DC75A
0.4
µA
with LPRC
DC75B
0.65
µA
+125°C with LPRC
ADC Incremental Current (ADC
DC76A
450
µA
12-bit, 100 ksps, with FRC
DC76B
590
µA
+125°C, 12-bit, 100 ksps, with FRC
FRC Oscillator Incremental Current (FRC)
DC78A
305
µA
DC78B
350
µA
+125°C
PLL Incremental Current (PLL)
DC79A
1230
µA
FVCO = 24 MHz
DC79B
1550
µA
FVCO = 24MHz +125°C
DC80A
1550
µA
FVCO = 48 MHz
DC80B
1850
µA
FVCO = 48MHz +125°C
Digital-to-Analog Converter Incremental Current, CDAC (DAC)
DC81A
27.5
µA
DC81B
40.0
µA
+125°C
Low-Power BOR Incremental Current (LPBOR)
DC82A
200
nA
DC82B
420
nA
+125°C
Comparator Incremental Current (CMP)
DC83A
24.0
µA
DC83B
38.0
µA
+125°C
Note 1: Data in the “Typ” column is for design guidance only and is not tested.
2: The current is an additional current consumed when the module is enabled. This current should be
added to the base IPD current.
2015-2018 Microchip Technology Inc.
DS60001324C-page 213
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TABLE 26-8:
I/O PIN INPUT SPECIFICATIONS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param
Symbol
No.
VIL
Characteristic
Min
Typ(1)
Max
Units
Conditions
Input Low Voltage(2)
DI10
I/O Pins with ST Buffer
VSS
—
0.2 VDD
V
DI15
MCLR
VSS
—
0.2 VDD
V
DI16
OSC1/CLKI (XT mode)
VSS
—
0.2 VDD
V
OSC1/CLKI (HS mode)
VSS
—
0.2 VDD
V
I/O Pins with ST Buffer:
without 5V Tolerance
with 5V Tolerance
0.8 VDD
0.8 VDD
—
—
VDD
5.5
V
V
DI25
MCLR
0.8 VDD
—
VDD
V
DI26
OSCI/CLKI (XT mode)
0.7 VDD
—
VDD
V
DI27
OSC1/CLKI (HS mode)
0.7 VDD
—
VDD
V
CNPUx Pull-up Current
—
350
—
µA
VPIN = 0V, VDD = 3.3V
CNPDx Pull-Down Current
—
300
—
µA
VPIN = 3.3V, VDD = 3.3V
DI17
VIH
DI20
DI30
ICNPU
DI30A ICNPD
IIL
Input High Voltage(2)
Input Leakage Current
DI50
I/O Pins – 5V Tolerant
—
0.1
1.0
µA
VPIN = 3.3V, VDD = 3.3V,
pin at high-impedance
DI51
I/O Pins – Not 5V Tolerant
—
0.1
1.0
µA
VPIN = 3.3V, VDD = 3.3V,
pin at high-impedance
DI55
MCLR
—
0.1
1.0
µA
VPIN = 3.3V, VDD = 3.3V
DI56
OSC1/CLKI
—
0.1
1.0
µA
VPIN = 3.3V, VDD = 3.3V
Note 1:
2:
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Refer to Table 1-1 for I/O pin buffer types.
DS60001324C-page 214
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
TABLE 26-9:
I/O PIN INPUT INJECTION CURRENT SPECIFICATIONS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param.
No.
Symbol
Characteristics
Min.
Max.
Units
Conditions
DI60a
IICL
Input Low Injection
Current
0
-5(1,4)
mA
This parameter applies to all pins,
except VDD, VSS, MCLR and
VCAP.
DI60b
IICH
Input High Injection
Current
0
+5(2,3,4)
mA
This parameter applies to all pins,
except VDD, VSS, MCLR, VCAP
and all 5V tolerant pins.
0
+0(2,3,4)
mA
5V tolerant pins.
+20(5)
mA
Absolute instantaneous sum of
all ± input injection currents from
all I/O pins,
( | IICL + | IICH | ) IICT
IICT
DI60c
Note 1:
2:
3:
4:
5:
Total Input Injection
Current (sum of all I/O
and control pins)
-20
(5)
VIL Source < (VSS – 0.3). Characterized but not tested.
VIH Source > (VDD + 0.3) for non-5V tolerant pins only.
Digital 5V tolerant pins do not have an internal high-side diode to VDD, and therefore, cannot tolerate any
“positive” input injection current.
Injection currents can affect the ADC results.
Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, are permitted
provided the “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit.
2015-2018 Microchip Technology Inc.
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TABLE 26-10: I/O PIN OUTPUT SPECIFICATIONS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param
No.
Symbol
VOL
DO10
Characteristic
RA3, RB8, RB9 and RB15 I/O Ports
VOH
DO20
Units
Conditions
—
0.36
V
IOL = 6.0 mA, VDD = 3.6V
—
0.21
V
IOL = 3.0 mA, VDD = 2V
—
0.16
V
IOL = 6.0 mA, VDD = 3.6V
—
0.12
V
IOL = 3.0 mA, VDD = 2V
3.25
—
V
IOH = -6.0 mA, VDD = 3.6V
1.4
—
V
IOH = -3.0 mA, VDD = 2V
3.3
—
V
IOH = -6.0 mA, VDD = 3.6V
1.55
—
V
IOH = -3.0 mA, VDD = 2V
Output High Voltage
I/O Ports
DO26
Max
Output Low Voltage
I/O Ports
DO16
Min
RA3, RB8, RB9 and RB15 I/O Ports
TABLE 26-11: PROGRAM FLASH MEMORY SPECIFICATIONS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
D130
EP
Cell Endurance
10000 20000
—
E/W
D131
VICSP
VDD for In-Circuit Serial
Programming™ (ICSP™)
VBOR
—
3.6
V
D132
VRTSP
VDD for Run-Time
Self-Programming (RTSP)
2.0
—
3.6
V
D133
TIW
Self-Timed Double-Word
Write Cycle Time
19.7
21.0
22.3
µs
8 bytes, data is not all ‘1’s
Self-Timed Row Write
Cycle Time
1.3
1.4
1.5
ms
256 bytes, data is not all ‘1’s,
SYSCLK > 2 MHz
2048 bytes
D133
TIE
Self-Timed Page Erase
Time
15.0
16.0
17.0
ms
D134
TRETD
Characteristic Retention
20
—
—
Year
D136
TCE
Self-Timed Chip Erase
Time
16.0
17.0
18.0
ms
Note 1:
If no other specifications are violated
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
DS60001324C-page 216
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TABLE 26-12: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param
No.
Symbol
Characteristics
Min
Typ(1)
Max
Units
Comments
DVR10
VBG
Band Gap Reference Voltage
1.163
1.2
1.237
V
DVR20
VRGOUT
Regulator Output Voltage
—
1.8
—
V
VDD > 1.9V
DVR21
CEFC
External Filter Capacitor Value
4.7
10
—
µF
Series Resistance < 3
recommended; < 5 required
DVR30
VLVR
Low-Voltage Regulator
Output Voltage
0.9
—
1.2
V
RETEN = 1,
RETVR (FPOR) = 0
Note 1:
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
TABLE 26-13: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param
No.
DC18
Symbol
VHLVD(1)
Min
Typ(2)
Max
Units
HLVDL = 0110
2.95
—
3.45
V
HLVDL = 0111
2.75
—
3.13
V
HLVDL = 1000
2.65
—
3.01
V
HLVDL = 1001
2.45
—
2.83
V
HLVDL = 1010
2.35
—
2.72
V
HLVDL = 1011
2.25
—
2.57
V
HLVDL = 1100
2.15
—
2.46
V
HLVDL = 1101
2.08
—
2.35
V
HLVDL = 1110
2.00
—
2.24
V
HLVDL = 1111
—
1.2
—
V
Characteristic
HLVD Voltage on VDD
Transition
HLVD Voltage on
LVDIN Pin Transition
DC101
VTHL
Note 1:
2:
Trip points for values of HLVD, from ‘0000’ to ‘0101’, are not implemented.
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2015-2018 Microchip Technology Inc.
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TABLE 26-14: COMPARATOR SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Typ(2)
Max
Units
D300
VIOFF
Input Offset Voltage
-60
12
60
mV
D301
VICM
Input Common-Mode Voltage
0
—
VDD
V(1)
D307
TRESP(1)
Response Time
—
150
—
ns
Note 1:
2:
Measured with one input at VDD/2 and the other transitioning from VSS to VDD.
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
TABLE 26-15: VOLTAGE REFERENCE (CDAC) SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Typ(2)
Max
Units
VRD310
TSET
Settling Time(1)
—
—
10
µs
VRD311
VRA
Accuracy
-1
—
1
LSb
VRD312
VRUR
Unit Resistor Value (R)
—
4.5
—
k
Note 1:
2:
Measures the interval while VRDAT transitions from ‘11111’ to ‘00000’.
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
DS60001324C-page 218
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26.2
AC Characteristics and Timing Parameters
FIGURE 26-2:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2/CLKO
Load Condition 2 – for OSC2/CLKO
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2/CLKO
15 pF for OSC2/CLKO output
VSS
TABLE 26-16: CAPACITIVE LOADING CONDITIONS ON OUTPUT PINS
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
DO50
COSCO
OSC2/CLKO Pin
—
15
pF
In XT and HS modes when
external clock is used to drive
OSC1/CLKI
DO56
CIO
All I/O Pins and OSC2
—
50
pF
EC mode
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FIGURE 26-3:
EXTERNAL CLOCK TIMING
OSCI
OS10
OS30
OS30
OS31
OS31
CLKO
OS40
OS41
TABLE 26-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param
Symbol
No.
OS10
FOSC
Characteristic
Min
Typ(1)
Max
Units
External CLKI Frequency
DC
2
—
—
25
12.5
MHz
MHz
EC
ECPLL(2)
Oscillator Frequency
3.5
3.5
10
10
31
—
—
—
—
—
10
10
25
25
50
MHz
MHz
MHz
MHz
kHz
XT
XTPLL(2)
HS
HSPLL(2)
SOSC
Conditions
OS30
TosL,
TosH
External Clock in (OSC1) 0.45 x TOSC
High or Low Time
—
0.55 x TOSC
ns
EC
OS31
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
—
—
20
ns
EC
OS40
TckR
CLKO Rise Time(3)
—
15
20
ns
OS41
TckF
CLKO Fall Time(3)
—
15
20
ns
Note 1:
2:
3:
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
PLL dividers and postscalers must be configured so that the system clock frequency does not exceed the
maximum operating frequency.
Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
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TABLE 26-18: PLL CLOCK TIMING SPECIFICATIONS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Max
Units
OS50
FPLLI
PLL Input Frequency Range(1)
2
24
MHz
OS54
FPLLO
PLL Output Frequency Range(1)
16
96
MHz
OS52
TLOCK
PLL Start-up Time (Lock Time)
—
24
µs
OS53
DCLK
CLKO Stability (Jitter)
-0.12
0.12
%
Note 1:
These parameters are characterized but not tested in manufacturing.
TABLE 26-19: INTERNAL OSCILLATOR ACCURACY(1)
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param No.
F20A
Characteristic
FRC Accuracy @ 8 MHz
MHz(3)
Min
Typ(2)
Max
Units
-5
—
5
%
F20B
FRC Accuracy @ 8
-3
—
3
%
F21A
LPRC @ 32 kHz(3)
-20
—
20
%
F21B
LPRC @ 32 kHz
-30
—
30
%
F22
FRC Tune Step-Size (in OSCTUN register)
—
0.05
—
%/Bit
Note 1:
2:
3:
To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB)
must be kept to a minimum.
Data in the “Typ” column is 3.3V unless otherwise stated. Parameters are for design guidance only and
are not tested.
-40°C to +85°C.
TABLE 26-20: INTERNAL OSCILLATOR START-UP TIME
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Max
Units
FR0
TFRC
FRC Oscillator Start-up Time
2
µs
FR1
TLPRC
Low-Power RC Oscillator Start-up Time
70
µs
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FIGURE 26-4:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note:
Refer to Figure 26-2 for load conditions.
TABLE 26-21: CLKO AND I/O TIMING REQUIREMENTS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
—
10
25
ns
DO31
TIOR
Port Output Rise Time
DO32
TIOF
Port Output Fall Time
—
10
25
ns
DI35
TINP
INTx Input Pin High or Low Time
10
—
—
ns
TRBP
CNx Input Pin High or Low Time
10
—
—
ns
DI40
Note 1:
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
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TABLE 26-22: RESET, BROWN-OUT RESET AND SLEEP MODES TIMING SPECIFICATIONS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
Conditions
SY10
TMCL
MCLR Pulse Width (Low)
2
—
—
µs
SY13
TIOZ
I/O High-Impedance from
MCLR Low
—
1
—
µs
SY25
TBOR
Brown-out Reset Pulse
Width
1
—
—
µs
SY45
TRST
Reset State Time
—
25
—
µs
SY71
TWAKE(2)
Wake-up Time with Main
Voltage Regulator
—
22
—
µs
Sleep wake-up with
VREGS = 0, RETEN = 0,
RETVR = 1
—
3.8
—
µs
Sleep wake-up with
VREGS = 1, RETEN = 0,
RETVR = 1
—
163
—
µs
Sleep wake-up with
VREGS = 0, RETEN = 1,
RETVR = 0
—
23
—
µs
Sleep wake-up with
VREGS = 1, RETEN = 1,
RETVR = 0
SY72
TWAKELVR(2) Wake-up Time with
Retention Low-Voltage
Regulator
Note 1:
2:
VDD VBOR
Data in the “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The parameters are measured with the external clock source (EC). To get the full wake-up time, the
oscillator start-up time must be added.
2015-2018 Microchip Technology Inc.
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FIGURE 26-5:
TIMER1 EXTERNAL CLOCK TIMING CHARACTERISTICS
T1CK
TA11
TA10
TA20
TA15
TMR1
TABLE 26-23: MCCP/SCCP TIMER1 EXTERNAL CLOCK TIMING CHARACTERISTICS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param.
No.
Characteristics(1)
Symbol
Min
Max
1
—
10
—
1
—
Asynchronous
10
—
ns
Synchronous
2
—
TPBCLK
TA10
TCKH
T1CK High Time Synchronous
TA11
TCKL
T1CK Low Time Synchronous
TA15
TCKP
T1CK Input
Period
Asynchronous
20
—
TA20
TCKEXTMRL Delay from External T1CK Clock
Edge to Timer Increment
—
3
Asynchronous
Note 1:
Units
Conditions
TPBCLK Must also meet Parameter TA15
ns
TPBCLK Must also meet Parameter TA15
ns
TPBCLK Synchronous mode
These parameters are characterized but not tested in manufacturing.
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FIGURE 26-6:
MCCP/SCCP TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS
TCKIx
TMR10
TMR11
TMR15
TMR20
CCPxTMR
TABLE 26-24: MCCP/SCCP TIMING REQUIREMENTS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param.
No.
TMR10
TMR11
TMR15
Symbol
TCKH
TCKL
TCKP
Characteristics(1)
TCKIx High Time
TCKIx Low Time
Min
Max
Synchronous
1
—
Asynchronous
10
—
Synchronous
1
—
Asynchronous
10
—
ns
TCKIx Input Period Synchronous
Asynchronous
ns
TPBCLK Must also meet
Parameter TMR15
2
—
TPBCLK
—
ns
—
1
TPBCLK
TCKEXTMRL Delay from External TCKIx Clock Edge
to Timer Increment
Note 1:
These parameters are characterized but not tested in manufacturing.
Conditions
TPBCLK Must also meet
Parameter TMR15
20
TMR20
2015-2018 Microchip Technology Inc.
Units
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FIGURE 26-7:
MCCP AND SCCP INPUT CAPTURE x MODE TIMING CHARACTERISTICS
ICMx
IC10
IC11
IC15
TABLE 26-25: MCCP AND SCCP INPUT CAPTURE x MODE TIMING REQUIREMENTS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param.
Symbol
No.
Characteristics(1)
Min
Max
Units
Conditions
IC10
TICL
ICMx Input Low Time
25
—
ns
Must also meet Parameter IC15
IC11
TICH
ICMx Input High Time
25
—
ns
Must also meet Parameter IC15
IC15
TICP
ICMx Input Period
50
—
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
FIGURE 26-8:
MCCP AND SCCP OUTPUT COMPARE x MODE TIMING CHARACTERISTICS
OCMx
OC11
OC10
Note: Refer to Figure 26-2 for load conditions.
TABLE 26-26: MCCP AND SCCP OUTPUT COMPARE x MODE TIMING REQUIREMENTS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param.
No.
Symbol
Characteristics(1)
Min
Typ
Max
Units
OC10
TOCF
OCMx Output Fall Time
—
10
25
ns
OC11
TOCR
OCMx Output Rise Time
—
10
25
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
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FIGURE 26-9:
MCCP AND SCCP PWMx MODE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCMx is Tri-Stated
OCMx
TABLE 26-27: MCCP AND SCCP PWM MODE TIMING REQUIREMENTS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param
No.
OC15
OC20
Note 1:
Characteristics(1)
Symbol
Min
Max
Units
TFD
Fault Input to PWM I/O Change
—
30
ns
TFLT
Fault Input Pulse Width
10
—
ns
These parameters are characterized but not tested in manufacturing.
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FIGURE 26-10:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP10
SCKx
(CKP = 1)
SP35
SDOx
MSb
SDIx
LSb
MSb In
LSb In
SP40 SP41
FIGURE 26-11:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP10
SCKx
(CKP = 1)
SP35
SDOx
MSb
SDIx
MSb In
SP40
DS60001324C-page 228
LSb
LSb In
SP41
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TABLE 26-28: SPIx MODULE MASTER MODE TIMING REQUIREMENTS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param.
No.
Characteristics(1)
Symbol
Min
Max
Units
SP10
TSCL, TSCH
SCKx Output Low or High Time
10
—
ns
SP35
TSCH2DOV,
TSCL2DOV
SDOx Data Output Valid after SCKx Edge
—
7
ns
SP36
TDOV2SC,
TDOV2SCL
SDOx Data Output Setup to First SCKx Edge
7
—
ns
SP40
TDIV2SCH,
TDIV2SCL
Setup Time of SDIx Data Input to SCKx Edge
7
—
ns
SP41
TSCH2DIL,
TSCL2DIL
Hold Time of SDIx Data Input to SCKx Edge
7
—
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
FIGURE 26-12:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SCKx
(CKP = 1)
SP35
SDOx
MSb
LSb
SP51
SDIx
MSb In
SP40
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LSb In
SP41
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FIGURE 26-13:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SCKx
(CKP = 1)
SP35
MSb
SDOx
LSb
SP51
SDIx
LSb In
MSb In
SP40
SP41
TABLE 26-29: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param.No.
Symbol
Characteristics(1)
Min
Max
Units
—
ns
SP70
TSCL
SCKx Input Low Time
10
SP71
TSCH
SCKx Input High Time
10
—
ns
SP35
TSCH2DOV,
TSCL2DOV
SDOx Data Output Valid after SCKx Edge
—
10
ns
SP40
TDIV2SCH,
TDIV2SCL
Setup Time of SDIx Data Input to SCKx Edge
0
—
ns
SP41
TSCH2DIL,
TSCL2DIL
Hold Time of SDIx Data Input to SCKx Edge
7
—
ns
SP50
TSSL2SCH,
TSSL2SCL
SSx to SCKx or SCKx Input
40
—
ns
SP51
TSSH2DOZ
SSx to SDOx Output High-Impedance
2.5
12
ns
SP52
TSCH2SSH
TSCL2SSH
SSx after SCKx Edge
10
—
ns
SP60
TSSL2DOV
SDOx Data Output Valid after SSx Edge
—
12.5
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
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TABLE 26-30: ADC MODULE INPUTS SPECIFICATIONS
Operating Conditions: 2.2V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Max
Units
VDD
VDD
V
VSS
VSS
V
Reference Inputs
AD01
AVDD
Module VDD Supply
AD02
AVSS
Module VSS Supply
Analog Inputs
AD10
VINH-VINL
Full-Scale Input Span
VREFL
VREFH
V
AD11
VIN
Absolute Input Voltage
VSS – 0.3
VDD + 0.3
V
AD12
VINL
Absolute VINL Input Voltage
VSS – 0.3
VDD + 0.3
V
AD17
RIN
Recommended Impedance of Analog
Voltage Source
—
1.2K
TABLE 26-31: ADC ACCURACY AND CONVERSION TIMING REQUIREMENTS FOR 12-BIT MODE(1)
Operating Conditions: VDD = AVDD = VREFH 2.9V, AVSS = VREFL = 0V, -40°C < TA < +125°C
Param
No.
Symbol
Characteristic
Min
Typ(2)
Max
Units
ADC Accuracy
AD20B
Nr
Resolution
—
12
—
bits
AD21B
INL
Integral Nonlinearity
—
±2.5
±3.5
LSb
AD22B
DNL
Differential Nonlinearity
—
±0.75
+1.75/-0.95
LSb
AD23B
GERR
Gain Error
–
±2
±3
LSb
AD24B
EOFF
Offset Error
—
±1
±2
LSb
Clock Parameters
AD50B
TAD
ADC Clock Period
250
—
—
ns
AD50B(3) TAD
ADC Clock Period
300
—
—
ns
AD56B(3)
FCNV
FCNV Throughput Rate
—
—
185
ksps
AD56B
FCNV
Throughput Rate
—
—
222
ksps
AD55B
tCONV
Conversion Time
—
16
—
TAD
AD61B
tPSS
Sample Start Delay from Setting
Sample bit (SAMP)
2
—
3
TAD
Note 1:
2:
Measurements are taken with the external VREF+ and VREF- used as the ADC voltage reference.
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2.2V < (VDD = AVDD = VREFH) < 2.9V, AVSS = VREFL = 0V, -40°C < TA < +125°C
Conversion Rate
3:
2015-2018 Microchip Technology Inc.
DS60001324C-page 231
PIC32MM0064GPL036 FAMILY
TABLE 26-32: ADC ACCURACY AND CONVERSION TIMING REQUIREMENTS FOR 10-BIT MODE(1)
Operating Conditions: VDD = AVDD = VREFH 2.9V, AVSS = VREFL = 0V, -40°C < TA < +125°C
Param
No.
Symbol
Characteristic
Min
Typ(2)
Max
Units
10
—
bits
ADC Accuracy
AD20A
Nr
Resolution
—
AD21A
INL
Integral Nonlinearity
—
±2.5
±3.5
LSb
AD22A
DNL
Differential Nonlinearity
—
±0.75
+1.75/-0.95
LSb
AD23A
GERR
Gain Error
—
±2
±3
LSb
AD24A
EOFF
Offset Error
—
±1
±2
LSb
—
—
ns
Clock Parameters
AD50A
TAD
ADC Clock Period
250
AD50A(3)
TAD
ADC Clock Period
300
—
—
ns
AD61A
tPSS
Sample Start Delay from Setting
Sample bit (SAMP)
2
—
3
TAD
Conversion Rate
AD55A
tCONV
Conversion Time
—
14
—
TAD
AD56A
FCNV
Throughput Rate
—
—
250
ksps
AD56A(3) FCNV
Throughput Rate
—
—
187
ksps
Note 1:
2:
3:
Measurements are taken with the external VREF+ and VREF- used as the ADC voltage reference.
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2.2V < (VDD = AVDD = VREFH) < 2.9V, AVSS = VREFL = 0V, -40°C < TA < +125°C
DS60001324C-page 232
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
FIGURE 26-14:
EJTAG TIMING CHARACTERISTICS
TTCKcyc
TTCKhigh
TTCKlow
Trf
TCK
Trf
TMS
TDI
TTsetup TThold
Trf
Trf
TDO
TRST*
TTRST*low
TTDOout
TTDOzstate
Undefined
Defined
Trf
TABLE 26-33: EJTAG TIMING REQUIREMENTS
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +125°C (unless otherwise stated)
Param.
No.
Symbol
Description(1)
Min
Max
Units
EJ1
TTCKCYC
TCK Cycle Time
25
—
ns
EJ2
TTCKHIGH
TCK High Time
10
—
ns
EJ3
TTCKLOW
TCK Low Time
10
—
ns
EJ4
TTSETUP
TAP Signals Setup Time before
Rising TCK
5
—
ns
EJ5
TTHOLD
TAP Signals Hold Time after
Rising TCK
3
—
ns
EJ6
TTDOOUT
TDO Output Delay Time from
Falling TCK
—
5
ns
EJ7
TTDOZSTATE TDO 3-State Delay Time from
Falling TCK
—
5
ns
EJ8
TTRSTLOW
TRST Low Time
25
—
ns
EJ9
TRF
TAP Signals Rise/Fall Time,
All Input and Output
—
—
ns
Note 1:
Conditions
These parameters are characterized but not tested in manufacturing.
2015-2018 Microchip Technology Inc.
DS60001324C-page 233
PIC32MM0064GPL036 FAMILY
NOTES:
DS60001324C-page 234
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
27.0
PACKAGING INFORMATION
27.1
Package Marking Information
20-Lead SSOP
Example
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
PIC32MM0016
GPL020
1810017
20-Lead QFN
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
32MM0016
GPL020
1810017
28-Lead SPDIP
Example
PIC32MM0064GPL028
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SOIC (7.5 mm)
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
Legend: XX...X
YY
WW
NNN
*
Note:
1810017
PIC32MM0032GPL028
1810017
Customer-specific information
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
All packages are Pb-free
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2015-2018 Microchip Technology Inc.
DS60001324C-page 235
PIC32MM0064GPL036 FAMILY
27.1
Package Marking Information (Continued)
28-Lead SSOP
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
28-Lead QFN
XXXXXXXX
XXXXXXXX
YYWWNNN
28-Lead UQFN
XXXXXXXX
XXXXXXXX
YYWWNNN
36-Lead VQFN
XXXXXXXX
XXXXXXXX
YYWWNNN
40-Lead UQFN
XXXXXXXX
XXXXXXXX
YYWWNNN
DS60001324C-page 236
Example
PIC32MM0064
GPL028
1810017
Example
32MM0032
GPL028
1810017
Example
32MM0032
GPL028
1810017
Example
32MM0064
GPL036
1810017
Example
32MM0064
GPL036
1810017
2015-2018 Microchip Technology Inc.
PIC32MM0064GPL036 FAMILY
27.2
Package Details
The following sections give the technical details of the packages.
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