PIC32MM0256GPM048-I/PT

PIC32MM0256GPM064 FAMILY 32-Bit Flash Microcontroller with MIPS32® microAptiv™ UC Core, Low Power and USB Operating Conditions Peripheral Features • • USB 2.0 Compliant Full-Speed and Low-Speed Device, Host and On-The-Go (OTG) Controller: - Dedicated DMA - Device mode operation from FRC oscillator;  no crystal oscillator required • Atomic Set, Clear and Invert Operation on Select Peripheral Registers • High-Current Sink/Source • Independent, Low-Power 32 kHz Timer Oscillator • Three 4-Wire SPI modules: - 16-byte FIFO - Variable width - I2S mode • Three I2C Master and Slave w/Address Masking and IPMI Support • Three Enhanced Addressable UARTs: - RS-232, RS-485 and LIN/J2602 support - IrDA® with on-chip hardware encoder and decoder • External Edge and Level Change Interrupt on All Ports • Hardware Real-Time Clock and Calendar (RTCC) • Up to 24 Peripheral Pin Select (PPS) Remappable Pins • 21 Total 16-Bit Timers: - Three dedicated 16-bit timers/counters - Two can be concatenated to form a 32-bit timer - Two additional 16-bit timers in each MCCP and SCCP module, totaling 18 • Capture/Compare/PWM/Timer modules: - Two 16-bit timers or one 32-bit timer in each module - PWM resolution down to 21 ns - Three Multiple Output (MCCP) modules: - Flexible configuration as PWM, input capture, output compare or timers - Six PWM outputs - Programmable dead time - Auto-shutdown - Six Single Output (SCCP) modules: - Flexible configuration as PWM, input capture, output compare or timers - Single PWM output • Reference Clock Output (REFO) • Four Configurable Logic Cells (CLCs) with Internal Connections to Select Peripherals and PPS • Four-Channel Hardware DMA with Automatic Data Size Detection and CRC Engine 2.0V to 3.6V, -40ºC to +125ºC, DC to 25 MHz Low-Power Modes • Low-Power modes: - Idle – CPU off, peripherals run from system clock - Sleep – CPU and peripherals off: - Fast wake-up Sleep with retention - Low-power Sleep with retention • 0.65 μA Sleep current for RAM Retention  Regulator mode and 5 μA for Regulator Standby mode • On-Chip 1.8V Voltage Regulator (VREG) • On-Chip Ultra Low-Power Retention Regulator High-Performance 32-Bit RISC CPU • microAptiv™ UC 32-Bit Core with 5-Stage Pipeline • microMIPS™ Instruction Set for 35% Smaller Code and 98% Performance compared to MIPS32 Instructions • 1.53 DMIPS/MHz (37 DMIPS) (Dhrystone 2.1) Performance • 3.17 CoreMark®/MHz (79 CoreMark) Performance • 16-Bit/32-Bit Wide Instructions with 32-Bit Wide Data Path • Two Sets of 32 Core Register Files (32-bit) to Reduce Interrupt Latency • Single-Cycle 32x16 Multiply and Two-Cycle 32x32 Multiply • 64-Bit, Zero Wait State Flash with ECC to Maximize Endurance/Retention Microcontroller Features • Up to 256K Flash Memory: - 20,000 erase/write cycle endurance - 20 years minimum data retention - Self-programmable under software control • Up to 32K SRAM Memory • Multiple Interrupt Vectors with Individually  Programmable Priority • Fail-Safe Clock Monitor mode • Configurable Watchdog Timer with On-Chip, Low-Power RC Oscillator • Programmable Code Protection • Selectable Oscillator Options Including: - High-precision, 8 MHz Internal RC (FRC) Oscillator – 2x/3x/4x/6x/12x/24x PLL, which can be clocked from FRC or the Primary Oscillator - Primary high-speed, crystal/resonator oscillator or external clock Debug Features • Two Programming and Debugging Interfaces: - Two-wire ICSP™ interface with non-intrusive access and real-time data exchange with application - Four-wire MIPS® standard Enhanced JTAG interface • IEEE Standard 1149.2 Compatible (JTAG) Boundary Scan  2016-2019 Microchip Technology Inc. DS60001387D-page 1 PIC32MM0256GPM064 FAMILY Analog Features Three Analog Comparators with Input Multiplexing Programmable High/Low-Voltage Detect (HLVD) 5-Bit Comparator Voltage Reference DAC with Pin Output Up to 24-Channel, Software-Selectable 10/12-Bit SAR Analog-to-Digital Converter (ADC): - 12-bit 200K samples/second conversion rate (single Sample-and-Hold) 16-Bit Timers Maximum PWM Outputs Maximum Dedicated 16-Bit Timers UART(1)/LIN/J2602 MCCP(4) SCCP(3) CLC SPI(2)/I2S 10/12-Bit ADC (External Channels) Comparators CRC I2C USB 28 64 16 21/18 21 18 3 3 3 6 4 3 12 3 Yes Yes 3 Yes SSOP/QFN/ UQFN PIC32MM0128GPM028 28 128 16 21/18 21 18 3 3 3 6 4 3 12 3 Yes Yes 3 Yes SSOP/QFN/ UQFN PIC32MM0256GPM028 28 256 32 21/18 21 18 3 3 3 6 4 3 12 3 Yes Yes 3 Yes SSOP/QFN/ UQFN 64 PIC32MM0064GPM036 36/40 Packages Data Memory (Kbytes) PIC32MM0064GPM028 Remappable Peripherals RTCC Device Program Memory (Kbytes) PIC32MM0256GPM064 FAMILY DEVICES Pins TABLE 1: General Purpose I/O/PPS • • • • - 10-bit 300k samples/second conversion rate (single Sample-and-Hold) - Sleep mode operation - Low-voltage boost for input - Band gap reference input feature - Windowed threshold compare feature - Auto-scan feature • Brown-out Reset (BOR) 16 27/20 21 20 3 3 3 6 4 3 15 3 Yes Yes 3 Yes VQFN/UQFN PIC32MM0128GPM036 36/40 128 16 27/20 21 20 3 3 3 6 4 3 15 3 Yes Yes 3 Yes VQFN/UQFN PIC32MM0256GPM036 36/40 256 32 27/20 21 20 3 3 3 6 4 3 15 3 Yes Yes 3 Yes VQFN/UQFN PIC32MM0064GPM048 48 64 16 38/24 21 24 3 3 3 6 4 3 17 3 Yes Yes 3 Yes UQFN/TQFP PIC32MM0128GPM048 48 128 16 38/24 21 24 3 3 3 6 4 3 17 3 Yes Yes 3 Yes UQFN/TQFP PIC32MM0256GPM048 48 256 32 38/24 21 24 3 3 3 6 4 3 17 3 Yes Yes 3 Yes UQFN/TQFP PIC32MM0064GPM064 64 64 16 52/24 21 24 3 3 3 6 4 3 20 3 Yes Yes 3 Yes QFN/TQFP PIC32MM0128GPM064 64 128 16 52/24 21 24 3 3 3 6 4 3 20 3 Yes Yes 3 Yes QFN/TQFP PIC32MM0256GPM064 64 256 32 52/24 21 24 3 3 3 6 4 3 20 3 Yes Yes 3 Yes QFN/TQFP Note 1: 2: 3: 4: UART1 has assigned pins. UART2 and UART3 are remappable. SPI1 and SPI3 have assigned pins. SPI2 is remappable. SCCP can be configured as a PWM with one output, input capture, output compare, 2 x 16-bit timers or 1 x 32-bit timer. MCCP can be configured as a PWM with up to six outputs, input capture, output compare, 2 x 16-bit timers or  1 x 32-bit timer. DS60001387D-page 2  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY Pin Diagrams 28-Pin SSOP 1 28 AVDD/VDD 2 27 AVSS/VSS PGED2/RP2/RA1 3 26 RP17/RB15(1) 25 RP16/RB14 24 RP15/RB13(1) 23 VUSB3V3 22 D+/RB11 21 D-/RB10 20 VCAP 19 PGEC3/TDO/RP18/RC9(1) PGED1/RP6/RB0 4 PGEC1/RP7/RB1 5 RP8/RB2 6 TDI/RP9/RB3 7 VSS 8 OSC1/RP3/RA2 9 PIC32MM0256GPM028 MCLR PGEC2/RP1/RA0 (1) OSC2/RP4/RA3 10 SOSCI/RP10/RB4 11 18 TMS/RP14/RB9(1,2) SOSCO/RP5/RA4 12 17 VDD 13 16 TCK/RP13/RB8(1) RP12/RB7 PGED3/RP11/RB5 14 15 VBUS/RB6 Legend: Shaded pins are up to 5V tolerant. Note 1: High drive strength pin. 2: This pin may toggle during ICSP programming. Refer to Section 2.6 “JTAG”. TABLE 2: Pin COMPLETE PIN FUNCTION DESCRIPTIONS FOR 28-PIN SSOP DEVICES Function Pin Function 1 MCLR 15 VBUS/RB6 2 PGEC2/VREF+/CVREF+/AN0/RP1/OCM1E/INT3/RA0 16 RP12/SDA3/SDI3/OCM3F/RB7 3 PGED2/VREF-/AN1/RP2/OCM1F/RA1 17 TCK/RP13/SCL1/U1CTS/SCK1/OCM1A/RB8(1) 4 PGED1/AN2/C1IND/C2INB/C3INC/RP6/OCM2C/RB0 18 TMS/REFCLKI/RP14/SDA1/T1CK/T1G/T2CK/T2G/U1RTS/U1BCLK/SDO1/OCM1B/ INT2/RB9(1,3) 5 PGEC1/AN3/C1INC/C2INA/RP7/OCM2D/RB1 19 PGEC3/TDO/RP18/ASCL1(2)/T3CK/T3G/USBOEN/SDO3/OCM2A/RC9(1) 6 AN4/C1INB/RP8/SDA2/OCM2E/RB2 20 VCAP 7 TDI/AN11/C1INA/RP9/SCL2/OCM2F/RB3 21 D-/RB10 8 VSS 22 D+/RB11 9 OSC1/CLKI/AN5/RP3/OCM1C/RA2 23 VUSB3V3 10 OSC2/CLKO/AN6/C3IND/RP4/OCM1D/RA3(1) 24 AN8/LVDIN/RP15/SCL3/SCK3/OCM3A/RB13(1) 11 SOSCI/AN7/RP10/OCM3C/RB4 25 CVREF/AN9/C3INB/RP16/RTCC/U1TX/VBUSON/SDI1/OCM3B/INT1/RB14 12 SOSCO/SCLKI/RP5/PWRLCLK/OCM3D/RA4 26 AN10/C3INA/REFCLKO/RP17/U1RX/SS1/FSYNC1/OCM2B/INT0/RB15(1) 13 VDD 27 AVSS/VSS 14 PGED3/RP11/ASDA1(2)/USBID/SS3/FSYNC3/ OCM3E/RB5 28 AVDD/VDD Note 1: 2: 3: High drive strength pin. Alternate pin assignments for I2C1 as determined by the I2C1SEL Configuration bit. This pin may toggle during ICSP programming. Refer to Section 2.6 “JTAG”.  2016-2019 Microchip Technology Inc. DS60001387D-page 3 PIC32MM0256GPM064 FAMILY Pin Diagrams (Continued) RP16/RB14 RP17/RB15(1) AVSS/VSS AVDD/VDD MCLR PGEC2/RP1/RA0 PGED2/RP2/RA1 28-Pin QFN/UQFN(3) 28 27 26 25 24 23 22 21 RP15/RB13(1) 2 20 VUSB3V3 RP8/RB2 3 19 D+/RB11 TDI/RP9/RB3 4 PIC32MM0256GPM028 18 D-/RB10 Vss 5 17 VCAP OSC1/RP3/RA2 6 16 PGEC3/TDO/RP18/RC9(1) (1) 7 15 TMS/RP14/RB9(1,2) Legend: Note 1: 2: 3: TABLE 3: TCK/RP13/RB8(1) RP12/RB7 VBUS/RB6 9 10 11 12 13 14 PGED3/RP11/RB5 8 VDD OSC2/RP4/RA3 SOSCO/RP5/RA4 1 PGEC1/RP7/RB1 SOSCI/RP10/RB4 PGED1/RP6/RB0 Shaded pins are up to 5V tolerant. High drive strength pin. This pin may toggle during ICSP programming. Refer to Section 2.6 “JTAG”. The back side thermal pad is not electrically connected. COMPLETE PIN FUNCTION DESCRIPTIONS FOR 28-PIN QFN/UQFN DEVICES Pin Function Pin Function 1 PGED1/AN2/C1IND/C2INB/C3INC/RP6/OCM2C/RB0 15 TMS/REFCLKI/RP14/SDA1/T1CK/T1G/T2CK/T2G/U1RTS/U1BCLK/SDO1/ OCM1B/INT2/RB9(1,3) 2 PGEC1/AN3/C1INC/C2INA/RP7/OCM2D/RB1 16 PGEC3/TDO/RP18/ASCL1(2)/T3CK/T3G/USBOEN/SDO3/OCM2A/RC9(1) 3 AN4/C1INB/RP8/SDA2/OCM2E/RB2 17 VCAP 4 TDI/AN11/C1INA/RP9/SCL2/OCM2F/RB3 18 D-/RB10 5 VSS 19 D+/RB11 6 OSC1/CLKI/AN5/RP3/OCM1C/RA2 20 VUSB3V3 7 OSC2/CLKO/AN6/C3IND/RP4/OCM1D/RA3(1) 21 AN8/LVDIN/RP15/SCL3/SCK3/OCM3A/RB13(1) 8 SOSCI/AN7/RP10/OCM3C/RB4 22 CVREF/AN9/C3INB/RP16/RTCC/U1TX/VBUSON/SDI1/OCM3B/INT1/RB14 9 SOSCO/SCLKI/RP5/PWRLCLK/OCM3D/RA4 23 AN10/C3INA/REFCLKO/RP17/U1RX/SS1/FSYNC1/OCM2B/INT0/RB15(1) 10 VDD 24 AVSS/VSS 11 PGED3/RP11/ASDA1(2)/USBID/SS3/FSYNC3/OCM3E/RB5 25 AVDD/VDD 12 VBUS/RB6 26 MCLR 13 RP12/SDA3/SDI3/OCM3F/RB7 27 PGEC2/VREF+/CVREF+/AN0/RP1/OCM1E/INT3/RA0 14 TCK/RP13/SCL1/U1CTS/SCK1/OCM1A/RB8(1) 28 PGED2/VREF-/AN1/RP2/OCM1F/RA1 Note 1: 2: 3: High drive strength pin. Alternate pin assignments for I2C1 as determined by the I2C1SEL Configuration bit. This pin may toggle during ICSP programming. Refer to Section 2.6 “JTAG”. DS60001387D-page 4  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY Legend: Note 1: 2: 3: TABLE 4: PGED2/RP2/RA1 PGEC2/RP1/RA0 MCLR AVDD/VDD AVSS/VSS RP17/RB15(1) RP16/RB14 33 32 31 30 29 28 PGED1/RP6/RB0 34 PGEC1/RP7/RB1 35 36-Pin QFN(3) 36 Pin Diagrams (Continued) RP8/RB2 1 27 RP15/RB13(1) TDI/RP9/RB3 2 26 VUSB3V3 RC0 3 25 D+/RB11 RC1 4 24 D-/RB10 PIC32MM0256GPM036 16 17 18 RP12/RB7 TCK/RP13/RB8(1) VDD VBUS/RB6 TMS/RP14/RB9(1,2) 15 RC8 19 14 20 9 RC3 8 SOSCI/RP10/RB4 PGED3/RP11/RB5 PGEC3/TDO/RP18/RC9(1) OSC2/RP4/RA3(1) 13 21 12 7 VSS VCAP OSC1/RP3/RA2 11 VDD 22 10 23 6 RP24/RA9 5 VSS SOSCO/RP5/RA4 RP19/RC2 Shaded pins are up to 5V tolerant. High drive strength pin. This pin may toggle during ICSP programming. Refer to Section 2.6 “JTAG”. The back side thermal pad is not electrically connected. COMPLETE PIN FUNCTION DESCRIPTIONS FOR 36-PIN QFN DEVICES Pin Function Pin Function 19 TMS/REFCLKI/RP14/SDA1/T1CK/T1G/U1RTS/U1BCLK/SDO1/OCM1B/INT2/RB9(1,3) 1 AN4/C1INB/RP8/SDA2/OCM2E/RB2 2 TDI/AN11/C1INA/RP9/SCL2/OCM2F/RB3 20 AN14/LVDIN/C2INC/RC8 3 AN12/C2IND/T2CK/T2G/RC0 21 PGEC3/TDO/RP18/ASCL1(2)/USBOEN/SDO3/RC9(1) 4 AN13/T3CK/T3G/RC1 22 VCAP 5 RP19/OCM2A/RC2 23 VDD 6 VSS 24 D-/RB10 7 OSC1/CLKI/AN5/RP3/OCM1C/RA2 25 D+/RB11 8 OSC2/CLKO/AN6/C3IND/RP4/OCM1D/RA3(1) 26 VUSB3V3 9 SOSCI/AN7/RP10/OCM3C/RB4 27 AN8/RP15/SCL3/SCK3/RB13(1) 10 SOSCO/SCLKI/RP5/PWRLCLK/OCM3D/RA4 28 CVREF/AN9/C3INB/RP16/RTCC/U1TX/VBUSON/SDI1/OCM3B/INT1/RB14 11 RP24/OCM3A/RA9 29 AN10/C3INA/REFCLKO/RP17/U1RX/SS1/FSYNC1/OCM2B/INT0/RB15(1) 12 VSS 30 AVSS/VSS 13 VDD 31 AVDD/VDD 14 RC3 32 MCLR 15 PGED3/RP11/ASDA1(2)/USBID/SS3/FSYNC3/OCM3E/RB5 33 PGEC2/VREF+/CVREF+/AN0/RP1/OCM1E/INT3/RA0 16 VBUS/RB6 34 PGED2/VREF-/AN1/RP2/OCM1F/RA1 17 RP12/SDA3/SDI3/OCM3F/RB7 35 PGED1/AN2/C1IND/C2INB/C3INC/RP6/OCM2C/RB0 18 TCK/RP13/SCL1/U1CTS/SCK1/OCM1A/RB8(1) 36 PGEC1/AN3/C1INC/C2INA/RP7/OCM2D/RB1 Note 1: 2: 3: High drive strength pin. Alternate pin assignments for I2C1 as determined by the I2C1SEL Configuration bit. This pin may toggle during ICSP programming. Refer to Section 2.6 “JTAG”.  2016-2019 Microchip Technology Inc. DS60001387D-page 5 PIC32MM0256GPM064 FAMILY 31 1 30 2 29 3 28 OSC2/RP4/RA3(1) SOSCI/RP10/RB4 SOSCO/RP5/RA4 27 4 PIC32MM0256GPM036 5 26 20 19 18 RP15/RB13(1) VUSB3V3 D+/RB11 D-/RB10 VDD N/C VCAP N/C PGEC3/TDO/RP18/RC9(1) RC8 TCK/RP13/RB8(1) N/C TMS/RP14/RB9(1,2) 17 21 16 22 10 15 23 9 14 24 8 13 25 7 12 6 11 TABLE 5: 32 RP8/RB2 TDI/RP9/RB3 RC0 RC1 RP19/RC2 VSS OSC1/RP3/RA2 RP24/RA9 VSS VDD RC3 PGED3/RP11/RB5 VBUS/RB6 RP12/RB7 Legend: Note 1: 2: 3: 33 34 35 36 37 38 40 40-Pin UQFN(3) 39 N/C PGEC1/RP7/RB1 PGED1/RP6/RB0 PGED2/RP2/RA1 PGEC2/RP1/RA0 MCLR AVDD/VDD AVSS/VSS RP17/RB15(1) RP16/RB14 Pin Diagrams (Continued) Shaded pins are up to 5V tolerant. High drive strength pin. This pin may toggle during ICSP programming. Refer to Section 2.6 “JTAG”. The back side thermal pad is not electrically connected. COMPLETE PIN FUNCTION DESCRIPTIONS FOR 40-PIN UQFN DEVICES Pin Function Pin Function 1 AN4/C1INB/RP8/SDA2/OCM2E/RB2 21 AN14/LVDIN/C2INC/RC8 2 TDI/AN11/C1INA/RP9/SCL2/OCM2F/RB3 22 PGEC3/TDO/RP18/ASCL1(2)/SDO3/USBOEN/RC9(1) 3 AN12/C2IND/T2CK/T2G/RC0 23 N/C 4 AN13/T3CK/T3G/RC1 24 VCAP 5 RP19/OCM2A/RC2 25 N/C 6 VSS 26 VDD 7 OSC1/CLKI/AN5/RP3/OCM1C/RA2 27 D-/RB10 8 OSC2/CLKO/AN6/C3IND/RP4/OCM1D/RA3(1) 28 D+/RB11 9 SOSCI/AN7/RP10/OCM3C/RB4 10 SOSCO/SCLKI/RP5/PWRLCLK/OCM3D/RA4 29 VUSB3V3 30 AN8/RP15/SCL3/SCK3/RB13(1) 11 RP24/OCM3A/RA9 31 CVREF/AN9/C3INB/RP16/RTCC/U1TX/VBUSON/SDI1/OCM3B/INT1/RB14 12 VSS 32 AN10/C3INA/REFCLKO/RP17/U1RX/SS1/FSYNC1/OCM2B/INT0/RB15(1) 13 VDD 33 AVSS/VSS 14 RC3 34 AVDD/VDD 15 PGED3/RP11/ASDA1(2)/USBID/SS3/FSYNC3/OCM3E/RB5 35 MCLR 16 VBUS/RB6 36 PGEC2/VREF+/CVREF+/AN0/RP1/OCM1E/INT3/RA0 17 RP12/SDA3/SDI3/OCM3F/RB7 37 PGED2/VREF-/AN1/RP2/OCM1F/RA1 18 TCK/RP13/SCL1/U1CTS/SCK1/OCM1A/RB8(1) 38 PGED1/AN2/C1IND/C2INB/C3INC/RP6/OCM2C/RB0 19 N/C 39 PGEC1/AN3/C1INC/C2INA/RP7/OCM2D/RB1 20 TMS/REFCLKI/RP14/SDA1/T1CK/T1G/U1RTS/U1BCLK/ SDO1/OCM1B/INT2/RB9(1,3) 40 N/C Note 1: 2: 3: High drive strength pin. Alternate pin assignments for I2C1 as determined by the I2C1SEL Configuration bit. This pin may toggle during ICSP programming. Refer to Section 2.6 “JTAG”. DS60001387D-page 6  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY Pin Diagrams (Continued) 48 47 46 45 44 43 42 41 40 39 38 37 TCK/RP13/RB8(1) RP12/RB7 VBUS/RB6 PGED3/RP11/RB5 RC12 VDD VSS RC5 RC4 RC3 RD0(1) RP24/RA9 48-Pin UQFN, TQFP(3) 1 2 3 4 5 6 7 8 9 10 11 12 PIC32MM0256GPM048 36 35 34 33 32 31 30 29 28 27 26 25 SOSCO/RP5/RA4 SOSCI/RP10/RB4 RA8(1) OSC2/RP4/RA3(1) OSC1/RP3/RA2 VSS VDD RP19/RC2 RC1 RC0 TDI/RP9/RB3 RP8/RB2 RP22/RA10(1) RP21/RA7 RP16/RB14 RP17/RB15(1) AVSS/VSS AVDD/VDD MCLR RA6 PGEC2/RP1/RA0 PGED2/RP2/RA1 PGED1/RP6/RB0 PGEC1/RP7/RB1 13 14 15 16 17 18 19 20 21 22 23 24 TMS/RP14/RB9 (1,2) RP23/RC6 RP20/RC7 RC8 PGEC3/TDO/RP18/RC9 (1) VSS VCAP RA15 D-/RB10 D+/RB11 VUSB3V3 RP15/RB13 (1) Legend: Note 1: 2: 3: Shaded pins are up to 5V tolerant. High drive strength pin. This pin may toggle during ICSP programming. Refer to Section 2.6 “JTAG”. The back side thermal pad is not electrically connected.  2016-2019 Microchip Technology Inc. DS60001387D-page 7 PIC32MM0256GPM064 FAMILY TABLE 6: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 48-PIN UQFN/TQFP DEVICES Pin Function (1,3) Pin Function 25 AN4/C1INB/RP8/SDA2/OCM2E/RB2 1 TMS/RP14/SDA1/OCM1B/INT2/RB9 2 RP23/RC6 26 TDI/AN11/C1INA/RP9/SCL2/OCM2F/RB3 3 RP20/RC7 27 AN12/C2IND/T2CK/T2G/RC0 4 AN14/LVDIN/C2INC/RC8 28 AN13/T3CK/T3G/RC1 5 PGEC3/TDO/RP18/ASCL1(2)/USBOEN/RC9(1) 29 RP19/OCM2A/RC2 30 VDD 6 VSS 7 VCAP 31 VSS 8 RTCC/RA15 32 OSC1/CLKI/AN5/RP3/OCM1C/RA2 9 D-/RB10 33 OSC2/CLKO/AN6/C3IND/RP4/RA3(1) 10 D+/RB11 34 SDO3/RA8(1) 11 VUSB3V3 35 SOSCI/AN7/RP10/OCM3C/RB4 12 AN8/RP15/SCL3/RB13(1) 36 SOSCO/SCLKI/RP5/PWRLCLK/OCM3D/RA4 13 RP22/SCK3/RA10(1) 37 RP24/OCM3A/RA9 14 RP21/SDI3/RA7 38 REFCLKI/T1CK/T1G/U1RTS/U1BCLK/SDO1/RD0(1) 15 CVREF/AN9/C3INB/RP16/VBUSON/SDI1/OCM3B/INT1/RB14 39 OCM2B/RC3 16 AN10/C3INA/REFCLKO/RP17/SS1/FSYNC1/INT0/RB15(1) 40 OCM1E/INT3/RC4 17 AVSS/VSS 41 AN15/OCM1D/RC5 18 AVDD/VDD 42 VSS 19 MCLR 43 VDD 20 AN19/U1RX/RA6 44 U1TX/RC12 21 PGEC2/VREF+/CVREF+/AN0/RP1/RA0 45 PGED3/RP11/ASDA1(2)/USBID/SS3/FSYNC3/OCM3E/RB5 22 PGED2/VREF-/AN1/RP2/OCM1F/RA1 46 VBUS/RB6 23 PGED1/AN2/C1IND/C2INB/C3INC/RP6/OCM2C/RB0 47 RP12/SDA3/OCM3F/RB7 24 PGEC1/AN3/C1INC/C2INA/RP7/OCM2D/RB1 48 TCK/RP13/SCL1/U1CTS/SCK1/OCM1A/RB8(1) Note 1: 2: 3: High drive strength pin. Alternate pin assignments for I2C1 as determined by the I2C1SEL Configuration bit. This pin may toggle during ICSP programming. Refer to Section 2.6 “JTAG”. DS60001387D-page 8  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RP22/RA10(1) RP15/RB13(1) VUSB3V3 D+/RB11 D-/RB10 RA14 RA15 VDD VCAP PGEC3/TDO/RP18/RC9(1) RA5 RD1 RC8 RP20/RC7 RP23/RC6 TMS/RP14/RB9(1,3) 64-Pin QFN, TQFP(3) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC32MM0256GPM064 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TCK/RP13/RB8(1) RC13(1) RP12/RB7 RC10 VBUS/RB6 PGED3/RP11/RB5 RC15 RC14 RC12 VDD VSS RC5 RC4 RC3 RD0(1) RD3 VDD VSS RC0 RC1 RP19/RC2 RC11 VDD VSS OSC1/RP3/RA2 OSC2/RP4/RA3(1) RA8(1) SOSCI/RP10/RB4 SOSCO/RP5/RA4 RP24/RA9 RD4 RD2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RP21/RA7 RP16/RB14 RP17/RB15(1) AVSS/VSS AVDD/VDD RA13 RA12 RA11 MCLR RA6 PGEC2/RP1/RA0 PGED2/RP2/RA1 PGED1/RP6/RB0 PGEC1/RP7/RB1 RP8/RB2 TDI/RP9/RB3 Legend: Note 1: 2: 3: Shaded pins are up to 5V tolerant. High drive strength pin. This pin may toggle during ICSP programming. Refer to Section 2.6 “JTAG”. The back side thermal pad is not electrically connected.  2016-2019 Microchip Technology Inc. DS60001387D-page 9 PIC32MM0256GPM064 FAMILY TABLE 7: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 64-PIN QFN/TQFP DEVICES Pin Function Pin Function 1 RP21/SDI3/RA7 33 OCM3B/RD3 2 CVREF/AN9/C3INB/RP16/VBUSON/RB14 34 REFCLKI/T1CK/T1G/U1RTS/U1BCLK/SDO1/RD0(1) 3 AN10/C3INA/REFCLKO/RP17/RB15(1) 35 OCM2B/RC3 4 AVSS 36 OCM1E/INT3/RC4 5 AVDD 37 AN15/OCM1D/RC5 6 AN16/U1CTS/RA13 38 VSS 7 AN17/OCM1A/RA12 39 VDD 8 AN18/RA11 40 U1TX/RC12 9 MCLR 41 OCM3D/RC14 10 AN19/U1RX/RA6 42 OCM3E/RC15 11 PGEC2/VREF+/CVREF+/AN0/RP1/RA0 43 PGED3/RP11/ASDA1(2)/USBID/RB5 12 PGED2/VREF-/AN1/RP2/OCM1F/RA1 44 VBUS/RB6 13 PGED1/AN2/C1IND/C2INB/C3INC/RP6/OCM2C/RB0 45 OCM3F/RC10 14 PGEC1/AN3/C1INC/C2INA/RP7/OCM2D/RB1 46 RP12/SDA3/RB7 15 AN4/C1INB/RP8/SDA2/OCM2E/RB2 47 SCK1/RC13(1) 16 TDI/AN11/C1INA/RP9/SCL2/OCM2F/RB3 48 TCK/RP13/SCL1/RB8(1) 17 VDD 49 TMS/RP14/SDA1/INT2/RB9(1,3) 18 VSS 50 RP23/RC6 19 AN12/C2IND/T2CK/T2G/RC0 51 RP20/RC7 20 AN13/T3CK/T3G/RC1 52 AN14/LVDIN/C2INC/RC8 21 RP19/OCM2A/RC2 53 OCM1B/RD1 22 SS3/FSYNC3/RC11 54 OCM3A/RA5 23 VDD 55 PGEC3/TDO/RP18/ASCL1(2)/USBOEN/RC9(1) 24 VSS 56 VCAP 25 OSC1/CLKI/AN5/RP3/OCM1C/RA2 57 VDD 26 OSC2/CLKO/AN6/C3IND/RP4/RA3(1) 58 RTCC/RA15 27 SDO3/RA8(1) 59 OCM3C/RA14 28 SOSCI/AN7/RP10/RB4 60 D-/RB10 29 SOSCO/SCLKI/RP5/PWRLCLK/RA4 61 D+/RB11 30 RP24/RA9 62 VUSB3V3 31 SDI1/INT1/RD4 63 AN8/RP15/SCL3/RB13(1) 32 SS1/FSYNC1/INT0/RD2 64 RP22/SCK3/RA10(1) Note 1: 2: 3: High drive strength pin. Alternate pin assignments for I2C1 as determined by the I2C1SEL Configuration bit. This pin may toggle during ICSP programming. Refer to Section 2.6 “JTAG”. DS60001387D-page 10  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Guidelines for Getting Started with 32-Bit Microcontrollers........................................................................................................ 23 3.0 CPU............................................................................................................................................................................................ 29 4.0 Memory Organization ................................................................................................................................................................. 39 5.0 Flash Program Memory.............................................................................................................................................................. 45 6.0 Resets ........................................................................................................................................................................................ 53 7.0 CPU Exceptions and Interrupt Controller ................................................................................................................................... 59 8.0 Direct Memory Access (DMA) Controller ................................................................................................................................... 77 9.0 Oscillator Configuration .............................................................................................................................................................. 97 10.0 I/O Ports ................................................................................................................................................................................... 113 11.0 Timer1 ...................................................................................................................................................................................... 127 12.0 Timer2 and Timer3 .................................................................................................................................................................. 131 13.0 Watchdog Timer (WDT) ........................................................................................................................................................... 137 14.0 Capture/Compare/PWM/Timer Modules (MCCP and SCCP) .................................................................................................. 141 15.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I2S)....................................................................................................... 157 16.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 165 17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 173 18.0 USB On-The-Go (OTG)............................................................................................................................................................ 179 19.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 207 20.0 12-Bit ADC Converter with Threshold Detect........................................................................................................................... 215 21.0 Configurable Logic Cell (CLC).................................................................................................................................................. 227 22.0 Comparator .............................................................................................................................................................................. 243 23.0 Voltage Reference (CVREF) ..................................................................................................................................................... 249 24.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 253 25.0 Power-Saving Features ........................................................................................................................................................... 257 26.0 Special Features ...................................................................................................................................................................... 263 27.0 Instruction Set .......................................................................................................................................................................... 281 28.0 Development Support............................................................................................................................................................... 283 29.0 Electrical Characteristics .......................................................................................................................................................... 285 30.0 Packaging Information.............................................................................................................................................................. 317 Appendix A: Revision History............................................................................................................................................................. 347 Index ................................................................................................................................................................................................. 349 The Microchip Website ...................................................................................................................................................................... 353 Customer Change Notification Service .............................................................................................................................................. 353 Customer Support .............................................................................................................................................................................. 353 Product Identification System ............................................................................................................................................................ 355  2016-2019 Microchip Technology Inc. DS60001387D-page 11 PIC32MM0256GPM064 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Website; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products. DS60001387D-page 12  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY Referenced Sources This device data sheet is based on the following individual sections of the “PIC32 Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note: • • • • • • • • • • • • • • • • • • • • • • • To access the documents listed below, browse the documentation section of the Microchip website (www.microchip.com). Section 1. “Introduction” (www.microchip.com/DS60001127) Section 5. “Flash Programming” (www.microchip.com/DS60001121) Section 7. “Resets” (www.microchip.com/DS60001118) Section 8. “Interrupts” (www.microchip.com/DS60001108) Section 10. “Power-Saving Modes” (www.microchip.com/DS60001130) Section 12. “I/O Ports” (www.microchip.com/DS60001120) Section 14. “Timers” (www.microchip.com/DS60001105) Section 19. “Comparator” (www.microchip.com/DS60001110) Section 20. “Comparator Voltage Reference” (www.microchip.com/DS61109) Section 21. “UART” (www.microchip.com/DS60001107) Section 23. “Serial Peripheral Interface (SPI)” (www.microchip.com/DS61106) Section 24. “Inter-Integrated Circuit™ (I2C™)” (www.microchip.com/DS60001116) Section 25. “12-Bit Analog-to-Digital Converter (ADC) with Threshold Detect” (www.microchip.com/DS60001359) Section 27. “USB On-The-Go (OTG)” (www.microchip.com/DS61126) Section 28. “RTCC with Timestamp” (www.microchip.com/DS60001362) Section 30. “Capture/Compare/PWM/Timer (MCCP and SCCP)” (www.microchip.com/DS60001381) Section 31. “DMA Controller” (www.microchip.com/DS60001117) Section 33. “Programming and Diagnostics” (www.microchip.com/DS61129) Section 36. “Configurable Logic Cell” (www.microchip.com/DS60001363) Section 48. “Memory Organization and Permissions” (DS60001214) Section 50. “CPU for Devices with MIPS32® microAptiv™ and M-Class Cores” (www.microchip.com/DS60001192) Section 59. “Oscillators with DCO” (www.microchip.com/DS60001329) Section 62. “Dual Watchdog Timer” (www.microchip.com/DS60001365)  2016-2019 Microchip Technology Inc. DS60001387D-page 13 PIC32MM0256GPM064 FAMILY NOTES: DS60001387D-page 14  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 1.0 DEVICE OVERVIEW Note: This data sheet contains device-specific information for the PIC32MM0256GPM064 family devices. This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the PIC32 Family Reference Manuals, which are available from the Microchip website (www.microchip.com/PIC32). The information in this data sheet supersedes the information in the FRM. FIGURE 1-1: Figure 1-1 illustrates a general block diagram of the core and peripheral modules in the PIC32MM0256GPM064 family of devices. Table 1-1 lists the pinout I/O descriptions for the pins shown in the device pin tables. PIC32MM0256GPM064 FAMILY BLOCK DIAGRAM Power-up Timer OSC2/CLKO OSC1/CLKI SOSCO, SCLKI, SOSCI Primary Oscillator Oscillator Start-up Timer FRC/LPRC Oscillators Power-on Reset Secondary Oscillator Watchdog Timer Dividers Brown-out Reset PLL VCAP SYSCLK Timing Generation PBCLK (1:1 with SYSCLK) Peripheral Bus Clocked by PBCLK AVDD, AVSS VDD, VSS MCLR Voltage Regulator Precision Band Gap Reference I/O Change Notification PORTA Timer1,2,3 JTAG BSCAN INT EJTAG MIPS32® microAptiv™ UC CPU Core DS IS PORTB 32 32 ICD MCCP1,2,3 32 Flash Controller (write) 32 DMA with CRC 32 32 USB 32 Bus Matrix PORTC 32 32 32 Peripheral Bus Clocked by PBCLK Priority Interrupt Controller SCCP4-9 SPI1,2,3 I2C1,2,3 32 12-Bit ADC UART1,2,3 Flash Line Buffer RAM RTCC 64 PORTD 64-Bit Wide Program Flash Memory  2016-2019 Microchip Technology Inc. Peripheral Bridge Comparators Flash Controller HLVD DS60001387D-page 15 PIC32MM0256GPM064 FAMILY TABLE 1-1: PIC32MM0256GPM064 FAMILY PINOUT DESCRIPTION Pin Number 64-Pin QFN/ TQFP Pin Type Buffer Type 21 11 I ANA 22 12 I ANA 38 23 13 I ANA 39 24 14 I ANA 1 1 25 15 I ANA 7 7 32 25 I ANA 7 8 8 33 26 I ANA 11 8 9 9 35 28 I ANA 24 21 27 30 12 63 I ANA 28-Pin SSOP 28-Pin QFN/ UQFN 36-Pin QFN 40-Pin UQFN 48-Pin QFN/ TQFP AN0 2 27 33 36 AN1 3 28 34 37 AN2 4 1 35 AN3 5 2 36 AN4 6 3 AN5 9 6 AN6 10 AN7 AN8 Pin Name Description Analog-to-Digital Converter input channels AN9 25 22 28 31 15 2 I ANA AN10 26 23 29 32 16 3 I ANA AN11 7 4 2 2 26 16 I ANA AN12 — — 3 3 27 19 I ANA AN13 — — 4 4 28 20 I ANA AN14 — — 20 21 4 52 I ANA AN15 — — — — 41 37 I ANA AN16 — — — — — 6 I ANA AN17 — — — — — 7 I ANA AN18 — — — — — 8 I ANA AN19 — — — — 20 10 I ANA AVDD 28 25 31 34 18 5 P — Analog modules power supply AVSS 27 24 30 33 17 4 P — Analog modules ground C1INA 7 4 2 2 26 16 I ANA Comparator 1 Input A C1INB 6 3 1 1 25 15 I ANA Comparator 1 Input B C1INC 5 2 36 39 24 14 I ANA Comparator 1 Input C C1IND 4 1 35 38 23 13 I ANA Comparator 1 Input D C2INA 5 2 36 39 24 14 I ANA Comparator 2 Input A C2INB 4 1 35 38 23 13 I ANA Comparator 2 Input B Comparator 2 Input C C2INC — — 20 21 4 52 I ANA C2IND — — 3 3 27 19 I ANA Comparator 2 Input D C3INA 26 23 29 32 16 3 I ANA Comparator 3 Input A C3INB 25 22 28 31 15 2 I ANA Comparator 3 Input B C3INC 4 1 35 38 23 13 I ANA Comparator 3 Input C C3IND 10 7 8 8 33 26 I ANA Comparator 3 Input D CLKI 9 6 7 7 32 25 I ST External Clock source input (EC mode) CLKO 10 7 8 8 33 26 O DIG System clock output CVREF 25 22 28 31 15 2 O ANA Comparator voltage reference output CVREF+ 2 27 33 36 21 11 I ANA Positive comparator voltage reference input D+ 22 19 25 28 10 61 I/O — USB transceiver differential plus line D- 21 18 24 27 9 60 I/O — USB transceiver differential minus line FSYNC1 26 23 29 32 16 32 I/O ST/DIG SPI1 frame signal input or output FSYNC3 14 11 15 15 45 22 I/O ST/DIG SPI3 frame signal input or output Legend: ST = Schmitt Trigger input buffer I2C = I2C/SMBus input buffer DS60001387D-page 16 DIG = Digital input/output ANA = Analog level input/output P = Power  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY TABLE 1-1: PIC32MM0256GPM064 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number 28-Pin SSOP 28-Pin QFN/ UQFN 36-Pin QFN 40-Pin UQFN 48-Pin QFN/ TQFP 64-Pin QFN/ TQFP Pin Type Buffer Type INT0 26 23 29 32 16 32 I ST External Interrupt 0 INT1 25 22 28 31 15 31 I ST External Interrupt 1 INT2 18 15 19 20 1 49 I ST External Interrupt 2 INT3 2 27 33 36 40 36 I ST LVDIN 24 21 20 21 4 52 I ANA Pin Name Description External Interrupt 3 High/Low-Voltage Detect input MCLR 1 26 32 35 19 9 I ST Master Clear (device Reset) OCM1A 17 14 18 18 48 7 O DIG MCCP1 Output A OCM1B 18 15 19 20 1 53 O DIG MCCP1 Output B OCM1C 9 6 7 7 32 25 O DIG MCCP1 Output C OCM1D 10 7 8 8 41 37 O DIG MCCP1 Output D OCM1E 2 27 33 36 40 36 O DIG MCCP1 Output E OCM1F 3 28 34 37 22 12 O DIG MCCP1 Output F OCM2A 19 16 5 5 29 21 O DIG MCCP2 Output A OCM2B 26 23 29 32 39 35 O DIG MCCP2 Output B OCM2C 4 1 35 38 23 13 O DIG MCCP2 Output C OCM2D 5 2 36 39 24 14 O DIG MCCP2 Output D OCM2E 6 3 1 1 25 15 O DIG MCCP2 Output E OCM2F 7 4 2 2 26 16 O DIG MCCP2 Output F OCM3A 24 21 11 11 37 54 O DIG MCCP3 Output A OCM3B 25 22 28 31 15 33 O DIG MCCP3 Output B OCM3C 11 8 9 9 35 59 O DIG MCCP3 Output C OCM3D 12 9 10 10 36 41 O DIG MCCP3 Output D OCM3E 14 11 15 15 45 42 O DIG MCCP3 Output E OCM3F 16 13 17 17 47 45 O DIG MCCP3 Output F OSC1 9 6 7 7 32 25 — — Primary Oscillator crystal OSC2 10 7 8 8 33 26 — — Primary Oscillator crystal PGEC1 5 2 36 39 24 14 I ST ICSP™ Port 1 programming clock input PGEC2 2 27 33 36 21 11 I ST ICSP Port 2 programming clock input PGEC3 19 16 21 22 5 55 I ST ICSP Port 3 programming clock input PGED1 4 1 35 38 23 13 I/O ST/DIG ICSP Port 1 programming data PGED2 3 28 34 37 22 12 I/O ST/DIG ICSP Port 2 programming data PGED3 14 11 15 15 45 43 I/O ST/DIG ICSP Port 3 programming data 12 9 10 10 36 29 I PWRLCLK Legend: ST = Schmitt Trigger input buffer I2C = I2C/SMBus input buffer  2016-2019 Microchip Technology Inc. ST DIG = Digital input/output ANA = Analog level input/output Real-Time Clock 50/60 Hz clock input P = Power DS60001387D-page 17 PIC32MM0256GPM064 FAMILY TABLE 1-1: PIC32MM0256GPM064 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number 28-Pin SSOP 28-Pin QFN/ UQFN 36-Pin QFN 40-Pin UQFN 48-Pin QFN/ TQFP 64-Pin QFN/ TQFP Pin Type 2 27 33 36 21 11 I/O RA1 3 28 34 37 22 12 I/O ST/DIG RA2 9 6 7 7 32 25 I/O ST/DIG RA3 10 7 8 8 33 26 I/O ST/DIG RA4 12 9 10 10 36 29 I/O ST/DIG RA5 — — — — — 54 I/O ST/DIG RA6 — — — — 20 10 I/O ST/DIG RA7 — — — — 14 1 I/O ST/DIG RA8 — — — — 34 27 I/O ST/DIG RA9 — — 11 11 37 30 I/O ST/DIG RA10 — — — — 13 64 I/O ST/DIG RA11 — — — — — 8 I/O ST/DIG RA12 — — — — — 7 I/O ST/DIG RA13 — — — — — 6 I/O ST/DIG RA14 — — — — — 59 I/O ST/DIG RA15 — — — — 8 58 I/O ST/DIG RB0 4 1 35 38 23 13 I/O ST/DIG PORTB digital I/Os RB1 5 2 36 39 24 14 I/O ST/DIG RB2 6 3 1 1 25 15 I/O ST/DIG RB3 7 4 2 2 26 16 I/O ST/DIG RB4 11 8 9 9 35 28 I/O ST/DIG RB5 14 11 15 15 45 43 I/O ST/DIG RB6 15 12 16 16 46 44 I/O ST/DIG RB7 16 13 17 17 47 46 I/O ST/DIG RB8 17 14 18 18 48 48 I/O ST/DIG Pin Name RA0 Buffer Type ST/DIG PORTA digital I/Os RB9 18 15 19 20 1 49 I/O ST/DIG RB10 21 18 24 27 9 60 I/O ST/DIG RB11 22 19 25 28 10 61 I/O ST/DIG RB13 24 21 27 30 12 63 I/O ST/DIG RB14 25 22 28 31 15 2 I/O ST/DIG RB15 26 23 29 32 16 3 I/O ST/DIG Legend: ST = Schmitt Trigger input buffer I2C = I2C/SMBus input buffer DS60001387D-page 18 Description DIG = Digital input/output ANA = Analog level input/output P = Power  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY TABLE 1-1: PIC32MM0256GPM064 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number 28-Pin SSOP 28-Pin QFN/ UQFN 36-Pin QFN 40-Pin UQFN 48-Pin QFN/ TQFP 64-Pin QFN/ TQFP Pin Type RC0 — — 3 3 27 19 I/O ST/DIG PORTC digital I/Os RC1 — — 4 4 28 20 I/O ST/DIG RC2 — — 5 5 29 21 I/O ST/DIG RC3 — — 14 14 39 35 I/O ST/DIG RC4 — — — — 40 36 I/O ST/DIG Pin Name Buffer Type Description RC5 — — — — 41 37 I/O ST/DIG RC6 — — — — 2 50 I/O ST/DIG RC7 — — — — 3 51 I/O ST/DIG RC8 — — 20 21 4 52 I/O ST/DIG RC9 19 16 21 22 5 55 I/O ST/DIG RC10 — — — — — 45 I/O ST/DIG RC11 — — — — — 22 I/O ST/DIG RC12 — — — — 44 40 I/O ST/DIG RC13 — — — — — 47 I/O ST/DIG RC14 — — — — — 41 I/O ST/DIG RC15 — — — — — 42 I/O ST/DIG RD0 — — — — 38 34 I/O ST/DIG PORTD digital I/Os RD1 — — — — — 53 I/O ST/DIG RD2 — — — — — 32 I/O ST/DIG RD3 — — — — — 33 I/O ST/DIG RD4 — — — — — 31 I/O ST/DIG REFCLKI 18 15 19 20 38 34 I ST External reference clock input REFCLKO 26 23 29 32 16 3 O ST External reference clock output RP1 2 27 33 36 21 11 I/O ST/DIG Remappable peripherals (input or output) RP2 3 28 34 37 22 12 I/O ST/DIG RP3 9 6 7 7 32 25 I/O ST/DIG RP4 10 7 8 8 33 26 I/O ST/DIG RP5 12 9 10 10 36 29 I/O ST/DIG RP6 4 1 35 38 23 13 I/O ST/DIG RP7 5 2 36 39 24 14 I/O ST/DIG RP8 6 3 1 1 25 15 I/O ST/DIG RP9 7 4 2 2 26 16 I/O ST/DIG RP10 11 8 9 9 35 28 I/O ST/DIG RP11 14 11 15 15 45 43 I/O ST/DIG RP12 16 13 17 17 47 46 I/O ST/DIG RP13 17 14 18 18 48 48 I/O ST/DIG RP14 18 15 19 20 1 49 I/O ST/DIG RP15 24 21 27 30 12 63 I/O ST/DIG RP16 25 22 28 31 15 2 I/O ST/DIG RP17 26 23 29 32 16 3 I/O ST/DIG RP18 19 16 21 22 5 55 I/O ST/DIG RP19 — — 5 5 29 21 I/O ST/DIG RP20 — — — — 3 51 I/O ST/DIG Legend: ST = Schmitt Trigger input buffer I2C = I2C/SMBus input buffer  2016-2019 Microchip Technology Inc. DIG = Digital input/output ANA = Analog level input/output P = Power DS60001387D-page 19 PIC32MM0256GPM064 FAMILY TABLE 1-1: PIC32MM0256GPM064 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number 28-Pin SSOP 28-Pin QFN/ UQFN 36-Pin QFN 40-Pin UQFN 48-Pin QFN/ TQFP 64-Pin QFN/ TQFP Pin Type RP21 — — — — 14 1 I/O ST/DIG Remappable peripherals (input or output) RP22 — — — — 13 64 I/O ST/DIG RP23 — — — — 2 50 I/O ST/DIG RP24 — — 11 11 37 30 I/O ST/DIG RTCC 25 22 28 31 8 58 O DIG SCK1 17 14 18 18 48 47 I/O ST/DIG SPI1 clock (input or output) SCK3 24 21 27 30 13 64 I/O ST/DIG SPI3 clock (input or output) Pin Name Buffer Type Description Real-Time Clock/Calendar alarm/seconds output SCL1 17 14 18 18 48 48 I/O I2C I2C1 synchronous serial clock input/output ASCL1 19 16 21 22 5 55 I/O I2C Alternate I2C1 synchronous serial clock input/ output SCL2 7 4 2 2 26 16 I/O I2C I2C2 synchronous serial clock input/output SCL3 24 21 27 30 12 63 I/O I2C I2C3 synchronous serial clock input/output SCLKI 12 9 10 10 36 29 I ST Secondary Oscillator digital clock input SDA1 18 15 19 20 1 49 I/O I2C I2C1 data input/output ASDA1 14 11 15 15 45 43 I/O I2C Alternate I2C1 data input/output SDA2 6 3 1 1 25 15 I/O I2C I2C2 data input/output SDA3 16 13 17 17 47 46 I/O I2C I2C3 data input/output SDI1 25 22 28 31 15 31 I ST SPI1 data input SDI3 16 13 17 17 14 1 I ST SPI3 data input SDO1 18 15 19 20 38 34 O DIG SPI1 data output SDO3 19 16 21 22 34 27 O DIG SPI3 data output SOSCI 11 8 9 9 35 28 — — Secondary Oscillator crystal SOSCO 12 9 10 10 36 29 — — Secondary Oscillator crystal SS1 26 23 29 32 16 32 I ST SPI1 slave select input SS3 14 11 15 15 45 22 I ST SPI3 slave select input T1CK 18 15 19 20 38 34 I ST Timer1 external clock input T2CK 18 15 3 3 27 19 I ST Timer2 external clock input T3CK 19 16 4 4 28 20 I ST Timer3 external clock input T1G 18 15 19 20 38 34 I ST Timer1 clock gate input T2G 18 15 3 3 27 19 I ST Timer2 clock gate input T3G 19 16 4 4 28 20 I ST Timer3 clock gate input TCK 17 14 18 18 48 48 I ST JTAG clock input TDI 7 4 2 2 26 16 I ST JTAG data input TDO 19 16 21 22 5 55 O DIG JTAG data output 18 15 19 20 1 49 I ST JTAG mode select input TMS Legend: ST = Schmitt Trigger input buffer I2C = I2C/SMBus input buffer DS60001387D-page 20 DIG = Digital input/output ANA = Analog level input/output P = Power  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY TABLE 1-1: PIC32MM0256GPM064 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number 28-Pin SSOP 28-Pin QFN/ UQFN 36-Pin QFN 40-Pin UQFN 48-Pin QFN/ TQFP 64-Pin QFN/ TQFP Pin Type Buffer Type U1BCLK 18 15 19 20 38 34 O DIG U1CTS 17 14 18 18 48 6 I ST UART1 Clear-to-Send U1RTS 18 15 19 20 38 34 O DIG UART1 Ready-to-Send U1RX 26 23 29 32 20 10 I ST UART1 receive data input U1TX 25 22 28 31 44 40 O DIG UART1 transmit data output USBID 14 11 15 15 45 43 I ST USB OTG ID (OTG mode only) USBOEN 19 16 21 22 5 55 O — USB transceiver output enable flag VBUSON 25 22 28 31 15 2 O — USB host and On-The-Go (OTG) bus power control output; only available in external USB Transceiver mode USB VBUS connection (5V nominal) Pin Name Description UART1 IrDA® 16x baud clock output VBUS 15 12 16 16 46 44 P — VUSB3V3 23 20 26 29 11 62 P — USB transceiver power input (3.3V nominal) VCAP 20 17 22 24 7 56 P — Core voltage regulator filter capacitor  connection VDD 13,28 10,25 18,30, 43 17,23, 39,57 P — Digital modules power supply VREF- 3 28 34 37 22 12 I ANA Analog-to-Digital Converter negative  reference VREF+ 2 27 33 36 21 11 I ANA Analog-to-Digital Converter positive  reference 8,27 5,24 P — VSS Legend: 13,23,31 13,26, 34 6,12,30 6,12,33 6,17,31, 18,24, 42 38 ST = Schmitt Trigger input buffer I2C = I2C/SMBus input buffer  2016-2019 Microchip Technology Inc. DIG = Digital input/output ANA = Analog level input/output Digital modules ground P = Power DS60001387D-page 21 PIC32MM0256GPM064 FAMILY NOTES: DS60001387D-page 22  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 2.0 Note: 2.1 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC32 Family Reference Manual”, which is available from the Microchip website (www.microchip.com/PIC32). The information in this data sheet supersedes the information in the FRM. Basic Connection Requirements Getting started with the PIC32MM0256GPM064 family of 32-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • All VDD and VSS pins  (see Section 2.2 “Decoupling Capacitors”) • All AVDD and AVSS pins, even if the ADC module is not used (see Section 2.2 “Decoupling Capacitors”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • VCAP pin (see Section 2.4 “Voltage Regulator Pin (VCAP)”) • PGECx/PGEDx pins, used for In-Circuit Serial Programming™ (ICSP™) and debugging  purposes (see Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins, when external oscillator source is used (see Section 2.7 “External Oscillator Pins”) • VUSB3V3 pin, this pin must be powered for USB  operation (see Section 18.4 “Powering the USB Transceiver”) 2.2 Decoupling Capacitors The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS, is required. See Figure 2-1. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A value of 0.1 µF (100 nF), 10-20V is recommended. The capacitor should be a low Equivalent Series Resistance  (low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is further recommended that ceramic capacitors be used. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended that the capacitors be placed on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. • Handling high-frequency noise: If the board is experiencing high-frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances, as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF. • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the  decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a  minimum, thereby reducing PCB track inductance. The following pin(s) may be required as well: VREF+/VREF- pins, used when external voltage reference for the ADC module is implemented. Note: The AVDD and AVSS pins must be connected, regardless of ADC use and the ADC voltage reference source.  2016-2019 Microchip Technology Inc. DS60001387D-page 23 PIC32MM0256GPM064 FAMILY FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION VDD 0.1 µF Ceramic VDD VCAP/VCORE R R1 MCLR C VSS 10 µF CEFC VUSB3V3 VDD 0.1 µF(2) 0.1 µF Ceramic ICSP™ VSS VDD AVSS AVDD 0.1 µF Ceramic Refer to Section 18.4 “Powering the USB Transceiver” for requirements of this pin. Note 1: 2.2.1 BULK CAPACITORS The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 µF to 47 µF. This capacitor should be located as close to the device as possible. 2.3 EXAMPLE OF MCLR PIN CONNECTIONS(1,2,3) R VSS 0.1 µF Ceramic Note 1: USB Power(1) VDD VSS VDD Place the components illustrated in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. FIGURE 2-2: PIC32 0.1 µF Ceramic For example, as illustrated in Figure 2-2, it is recommended that the capacitor, C, be isolated from the MCLR pin during programming and debugging operations. Master Clear (MCLR) Pin 1 5 4 2 3 6 10k C R1(1) 1 k MCLR PIC32 VDD VSS NC PGECx(3) PGEDx(3) 470 R1  1 k will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met without interfering with the debugger/programmer tools. 2: The capacitor can be sized to prevent unintentional Resets from brief glitches or to extend the device Reset period during POR. 3: No pull-ups or bypass capacitors are allowed on active debug/program PGECx/PGEDx pins. The MCLR pin provides for two specific device functions: • Device Reset • Device Programming and Debugging Pulling The MCLR pin low generates a device Reset. Figure 2-2 illustrates a typical MCLR circuit. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. Note: When MCLR is used to wake the device from Retention Sleep, a POR Reset will occur. DS60001387D-page 24  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 2.4 Voltage Regulator Pin (VCAP) FIGURE 2-3: A low-ESR (< 5Ω) capacitor is required on the VCAP pin to stabilize the output voltage of the on-chip voltage regulator. The VCAP pin must not be connected to VDD and must use a capacitor of 10 µF connected to ground. The type can be ceramic or tantalum. Suitable examples of capacitors are shown in Table 2-1. Capacitors with equivalent specification can be used. FREQUENCY vs. ESR PERFORMANCE FOR SUGGESTED VCAP 10 ESR () 1 The placement of this capacitor should be close to VCAP. It is recommended that the trace length not exceed 0.25 inch (6 mm). Refer to Section 29.0 “Electrical Characteristics” for additional information. 0.1 0.01 Designers may use Figure 2-3 to evaluate ESR equivalence of candidate devices. 0.001 0.01 0.1 1 10 100 Frequency (MHz) 1000 10,000 Note: Typical data measurement at +25°C, 0V DC bias. . TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS Make Part # Nominal Capacitance Base Tolerance Rated Voltage Temp. Range TDK C3216X7R1C106K 10 µF ±10% 16V -55 to +125ºC TDK C3216X5R1C106K 10 µF ±10% 16V -55 to +85ºC Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to +125ºC Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to +85ºC Murata GRM319R61C106KE15D 10 µF ±10% 16V -55 to +85ºC  2016-2019 Microchip Technology Inc. DS60001387D-page 25 PIC32MM0256GPM064 FAMILY 2.4.1 CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller. However, some care is needed in selecting the capacitor to ensure that it maintains sufficient capacitance over the intended operating range of the application. Typical low-cost, 10 µF ceramic capacitors are available in X5R, X7R and Y5V dielectric ratings (other types are also available, but are less common). The initial tolerance specifications for these types of capacitors are often specified as ±10% to ±20% (X5R and X7R) or -20%/+80% (Y5V). However, the effective capacitance that these capacitors provide in an application circuit will also vary based on additional factors, such as the applied DC bias voltage and the temperature. The total in-circuit tolerance is, therefore, much wider than the initial tolerance specification. The X5R and X7R capacitors typically exhibit satisfactory temperature stability (ex: ±15% over a wide temperature range, but consult the manufacturer’s data sheets for exact specifications). However, Y5V capacitors typically have extreme temperature tolerance specifications of +22%/-82%. Due to the extreme temperature tolerance, a 10 µF nominal rated Y5V type capacitor may not deliver enough total capacitance to meet minimum internal voltage regulator stability and transient response requirements. Therefore, Y5V capacitors are not recommended for use with the internal regulator. In addition to temperature tolerance, the effective capacitance of large value ceramic capacitors can vary substantially, based on the amount of DC voltage applied to the capacitor. This effect can be very significant, but is often overlooked or is not always documented. Typical DC bias voltage vs. capacitance graph for X7R type capacitors is shown in Figure 2-4. Capacitance Change (%) FIGURE 2-4: When selecting a ceramic capacitor to be used with the internal voltage regulator, it is suggested to select a high-voltage rating, so that the operating voltage is a small percentage of the maximum rated capacitor voltage. The minimum DC rating for the ceramic capacitor on VCAP is 16V. Suggested capacitors are shown in Table 2-1. 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin Input Voltage High (VIH) and Input Voltage Low (VIL) requirements. Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 3 or MPLAB REAL ICE™ In-Circuit Emulator. For more information on MPLAB® ICD 3 and REAL ICE connection requirements, refer to the following documents that are available from the Microchip website. • “Using MPLAB® ICD 3” (poster) (DS51765) • “Development Tools Design Advisory” (DS51764) • “MPLAB® REAL ICE™ In-Circuit Emulator User’s Guide” (DS51616) • “Using MPLAB® REAL ICE™ In-Circuit Emulator” (poster) (DS51749) DC BIAS VOLTAGE vs. CAPACITANCE CHARACTERISTICS 10 0 -10 16V Capacitor -20 -30 -40 10V Capacitor -50 -60 -70 6.3V Capacitor -80 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DC Bias Voltage (VDC) DS60001387D-page 26  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 2.6 JTAG The TMS, TDO, TDI and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard. It is recommended to keep the trace length between the JTAG connector, and the JTAG pins on the device, as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits, and pin Input Voltage High (VIH) and Input Voltage Low (VIL) requirements. avoid any traces on the other side of the board where the crystal is placed. A suggested layout is illustrated in Figure 2-5. For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate website: (www.microchip.com). • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” FIGURE 2-5: SUGGESTED OSCILLATOR CIRCUIT PLACEMENT Note 1: The TMS pin function may be active multiple times during ICSP device Erase, Programming and Debugging. When the TMS function is active, the integrated pull-up resistor, ~6k, will pull the pin to VDD. When the TMS function is inactive, the pin will be tri-state. The TMS function being enabled and disabled repeatedly results in the pin “toggling.” • Do not connect circuity to the TMS pin that could be adversely affected by the toggling. • If circuity connected to the TMS pin is sensitive to the “toggling” do not program the device in circuit. • Use a strong pull-down resistor such as 1k between the TMS pin to ground to overpower the pull-up. 2.7 External Oscillator Pins This family of devices has options for two external oscillators: a high-frequency Primary Oscillator and a low-frequency Secondary Oscillator (refer to Section 9.0 “Oscillator Configuration” for details). Oscillator Secondary Guard Trace Guard Ring Main Oscillator 2.8 Unused I/Os To minimize power consumption, unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic low or logic high state. Alternatively, inputs can be reserved by ensuring the pin is always configured as an input and externally connecting the pin to VSS or VDD. A current-limiting resistor may be used to create this connection if there is any risk of inadvertently configuring the pin as an output with the logic output state opposite of the chosen power rail. The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board,  2016-2019 Microchip Technology Inc. DS60001387D-page 27 PIC32MM0256GPM064 FAMILY NOTES: DS60001387D-page 28  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 3.0 Note: CPU This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 50. “CPU for Devices with MIPS32® microAptiv™ and M-Class Cores” (www.microchip.com/ DS60001192) in the “PIC32 Family Reference Manual”. MIPS32® microAptiv™ UC microprocessor core resources are available at: www.imgtec.com. The information in this data sheet supersedes the information in the FRM. The MIPS32® microAptiv™ UC microprocessor core is the heart of the PIC32MM0256GPM064 family devices. The CPU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of the instruction execution to the proper destinations. 3.1 Features The PIC32MM0256GPM064 family processor core key features include: • Five-Stage Pipeline • 32-Bit Address and Data Paths • MIPS32 Enhanced Architecture: - Multiply-add and multiply-subtract instructions. - Targeted multiply instruction. - Zero and one detect instructions. - WAIT instruction. - Conditional move instructions. - Vectored interrupts. - Atomic interrupt enable/disable. - One GPR shadow set to minimize latency of interrupts. - Bit field manipulation instructions. • microMIPS™ Instruction Set: - microMIPS allows improving the code size density over MIPS32, while maintaining MIPS32 performance. - microMIPS supports all MIPS32 instructions (except for branch-likely instructions) with new optimized 32-bit encoding. Frequent MIPS32 instructions are available as 16-bit instructions. - Added seventeen new and thirty-five MIPS32® corresponding, commonly used instructions in 16-bit opcode format. - Stack Pointer implicit in instruction. - MIPS32 assembly and ABI compatible.  2016-2019 Microchip Technology Inc. • Memory Management Unit with Simple Fixed Mapping Translation (FMT) Mechanism • Multiply/Divide Unit (MDU): - Configurable using high-performance  multiplier array. - Maximum issue rate of one 32x16 multiply per clock. - Maximum issue rate of one 32x32 multiply every other clock. - Early-in iterative divide. Minimum 11 and maximum 33 clock latency (dividend (rs) sign extension dependent). • Power Control: - No minimum frequency: 0 MHz. - Power-Down mode (triggered by WAIT instruction). • EJTAG Debug/Profiling: - CPU control with start, stop and single stepping. - Software breakpoints via the SDBBP instruction. - Simple hardware breakpoints on virtual addresses, four instructions and  two data breakpoints. - PC and/or load/store address sampling for profiling. - Performance counters. - Supports Fast Debug Channel (FDC). A block diagram of the PIC32MM0256GPM064 family processor core is shown in Figure 3-1. DS60001387D-page 29 PIC32MM0256GPM064 FAMILY FIGURE 3-1: PIC32MM0256GPM064 FAMILY MICROPROCESSOR CORE BLOCK DIAGRAM MIPS32® microAptiv™ UC Microprocessor Core SYSCLK Decode (microMIPS™) System Bus MMU GPR (two sets) Execution Unit ALU/Shift Atomic/LdSt MCU ASE System Interface System Coprocessor Interrupt Interface 2-Wire Debug DS60001387D-page 30 Enhanced MDU Debug/Profiling Breakpoints Fast Debug Channel Performance Counters Power Management EJTAG  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 3.2 Architecture Overview 3.2.2 The MIPS32® microAptiv™ UC microprocessor core in the PIC32MM0256GPM064 family devices contains several logic blocks, working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: • • • • • • • • Execution Unit General Purpose Register (GPR) Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Memory Management Unit (MMU) Power Management microMIPS Instructions Decoder Enhanced JTAG (EJTAG) Controller 3.2.1 EXECUTION UNIT The processor core execution unit implements a load/ store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous Multiply/ Divide Unit (MDU). The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port, and is fully bypassed to minimize operation latency in the pipeline. The execution unit includes: • 32-bit adder used for calculating the data address • Address unit for calculating the next instruction address • Logic for branch determination and branch target address calculation • Load aligner • Bypass multiplexers used to avoid Stalls when executing instruction streams where data producing instructions are followed closely by consumers for their results • Leading zero/one detect unit for implementing the CLZ and CLO instructions • Arithmetic Logic Unit (ALU) for performing  arithmetic and bitwise logical operations • Shifter and store aligner TABLE 3-1: MULTIPLY/DIVIDE UNIT (MDU) The microAptiv UC core includes a Multiply/Divide Unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline operates in parallel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows the longrunning MDU operations to be partially masked by system Stalls and/or other Integer Unit instructions. The high-performance MDU consists of a 32x16 booth recoded multiplier, Result/Accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (‘32’ of 32x16) represents the rs operand. The second number (‘16’ of 32x16) represents the rt operand. The microAptiv UC core only checks the value of the rt operand to determine how many times the operation must pass through the multiplier. The 16x16 and 32x16 operations pass through the multiplier once. A 32x32 operation passes through the multiplier twice. The MDU supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issuance of back-to-back, 32x32 multiply operations. The multiply operand size is automatically determined by logic built into the MDU. Divide operations are implemented with a simple 1-bit-per-clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit wide rs, 15 iterations are skipped, and for a 24-bit wide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline Stall until the divide operation has completed. Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be re-issued), and latency (number of cycles until a result is available) for the microAptiv UC core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks. MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate MULT/MULTU, MADD/MADDU, MSUB/MSUBU 16 bits 1 1 32 bits 2 2 MUL (GPR destination) 16 bits 2 1 DIV/DIVU  2016-2019 Microchip Technology Inc. 32 bits 3 2 8 bits 12 11 16 bits 19 18 24 bits 26 25 32 bits 33 32 DS60001387D-page 31 PIC32MM0256GPM064 FAMILY The MIPS® architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the general purpose register file. In addition to the HI/LO targeted operations, the MIPS architecture also defines a Multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction, required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased. 3.2.3 SYSTEM CONTROL  COPROCESSOR (CP0) In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processor’s diagnostics capability, the operating modes (Kernel, User and Debug) and whether interrupts are enabled or disabled. These configuration options and other system information are available by accessing the CP0 registers listed in Table 3-2. Two other instructions, Multiply-Add (MADD) and Multiply-Subtract (MSUB), are used to perform the multiply-accumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. DS60001387D-page 32  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY TABLE 3-2: Register Number COPROCESSOR 0 REGISTERS Register Name Function 0-3 Reserved Reserved in the microAptiv™ UC. 4 UserLocal User information that can be written by privileged software and read via  RDHWR Register 29. 5-6 Reserved Reserved in the microAptiv UC. 7 HWREna Enables access via the RDHWR instruction to selected hardware registers in  Non-Privileged mode. 8 BadVAddr(1) Reports the address for the most recent address related exception. 9 Count(1) Processor cycle count. 10 Reserved Reserved in the microAptiv UC. 11 Compare(1) Timer interrupt control. 12 Status/ IntCtl/ SRSCtl/ SRSMap1/ View_IPL/ SRSMAP2 Processor status and control; interrupt control and shadow set control. 13 Cause(1)/ View_RIPL Cause of last exception. 14 EPC(1) Program Counter at last exception. 15 PRId/ EBase/ CDMMBase Processor identification and revision; exception base address; Common Device  Memory Map Base register. 16 CONFIG/ CONFIG1/ CONFIG2/ CONFIG3/ CONFIG7 Configuration registers. 7-22 Reserved Reserved in the microAptiv UC. 23 Debug/ Debug2/ TraceControl/ TraceControl2/ UserTraceData1/ TraceBPC(2) EJTAG Debug register. EJTAG Debug Register 2. EJTAG Trace Control register. EJTAG Trace Control Register 2. EJTAG User Trace Data 1 register. EJTAG Trace Breakpoint register. 24 DEPC(2)/ UserTraceData2 Program Counter at last debug exception. EJTAG User Trace Data 2 register. 25 PerfCtl0/ PerfCnt0/ PerfCtl1/ PerfCnt1 Performance Counter 0 control. Performance Counter 0. Performance Counter 1 control. Performance Counter 1. 26 ErrCtl Software parity check enable. 27 CacheErr Records information about SRAM parity errors. 28-29 Reserved Reserved in the PIC32 core. 30 ErrorEPC(1) Program Counter at last error. 31 DeSAVE(2) Debug Handler Scratchpad register. Note 1: 2: Registers used in exception processing. Registers used in debug.  2016-2019 Microchip Technology Inc. DS60001387D-page 33 PIC32MM0256GPM064 FAMILY 3.3 Power Management The processor core offers a number of power management features, including low-power design, active power management and Power-Down modes of operation. The core is a static design that supports slowing or halting of the clocks, which reduces system power consumption during Idle periods. The mechanism for invoking Power-Down mode is implemented through execution of the WAIT instruction, used to initiate Sleep or Idle. The majority of the power consumed by the processor core is in the clock tree and clocking registers. The PIC32MM family makes extensive use of local gated clocks to reduce this dynamic power consumption. 3.4 The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the microAptiv UC core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification specify which registers are selected and how they are used. 3.5 MIPS32® microAptiv™ UC Core Configuration Register 3-1 through Register 3-4 show the default configuration of the microAptiv UC core, which is included on PIC32MM0256GPM064 family devices. EJTAG Debug Support The microAptiv UC core has an Enhanced JTAG (EJTAG) interface for use in the software debug. In addition to the standard mode of operation, the microAptiv UC core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a Debug Exception Return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine. DS60001387D-page 34  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 3-1: Bit Range 31:24 23:16 15:8 7:0 CONFIG: CONFIGURATION REGISTER; CP0 REGISTER 16, SELECT 0 Bit 31/23/15/7 Bit 30/22/14/6 r-1 R/W-0 — Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-1 R/W-0 R/W-0 Bit 25/17/9/1 R/W-1 R/W-0 r-0 r-0 R-0 R-1 R-0 — UDI SB MDU — R-0 R-0 R-0 R-0 R-0 AT[1:0] r-0 r-0 — r-0 R-1 — — DS R-1 R-0 AR[2:0] R-1 r-0 r-0 r-0 r-0 MT[0] — — — — R-1 MT[2:1] R/W-0 R/W-1 R/W-0 K0[2:0] Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31 Bit 24/16/8/0 KU[2:0](1) K23[2:0] BE Bit 26/18/10/2 x = Bit is unknown Reserved: This bit is hardwired to ‘1’ to indicate the presence of the CONFIG1 register bit 30-28 K23[2:0]: Cacheability of the kseg2 and kseg3 Segments bits 010 = Cache is not implemented bit 27-25 KU[2:0]: Cacheability of the kuseg and useg Segments bits(1) 010 = Cache is not implemented bit 24-23 Reserved: Must be written as zeros; returns zeros on reads bit 22 UDI: User-Defined bit 0 = CorExtend user-defined instructions are not implemented bit 21 SB: SimpleBE bit 1 = Only Simple Byte Enables are allowed on the internal bus interface bit 20 MDU: Multiply/Divide Unit bit 0 = Fast, high-performance MDU bit 19-17 Reserved: Must be written as zeros; returns zeros on reads bit 16 DS: Dual SRAM Interface bit 1 = Dual instruction/data SRAM interface bit 15 BE: Endian Mode bit 0 = Little-endian bit 14-13 AT[1:0]: Architecture Type bits 00 = MIPS32® bit 12-10 AR[2:0]: Architecture Revision Level bits 001 = MIPS32 Release 2 bit 9-7 MT[2:0]: MMU Type bits 011 = Fixed mapping bit 6-3 Reserved: Must be written as zeros; returns zeros on reads bit 2-0 K0[2:0]: kseg0 Coherency Algorithm bits 010 = Cache is not implemented Note 1: The KU[2:0] bits are not usable as this device does not support User mode.  2016-2019 Microchip Technology Inc. DS60001387D-page 35 PIC32MM0256GPM064 FAMILY REGISTER 3-2: Bit Range 31:24 23:16 15:8 7:0 CONFIG1: CONFIGURATION REGISTER 1; CP0 REGISTER 16, SELECT 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 r-1 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R-1 R-0 R-0 R-1 R-0 — — — PC WR CA EP FP Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 Reserved: This bit is hardwired to ‘1’ to indicate the presence of the CONFIG2 register bit 30-5 Unimplemented: Read as ‘0’ bit 4 PC: Performance Counter bit 1 = The processor core contains performance counters bit 3 WR: Watch Register Presence bit 0 = No Watch registers are present bit 2 CA: Code Compression Implemented bit 0 = No MIPS16e® are present bit 1 EP: EJTAG Present bit 1 = Core implements EJTAG bit 0 FP: Floating Point Unit bit 0 = Floating point unit is not implemented DS60001387D-page 36  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 3-3: Bit Range 31:24 23:16 15:8 7:0 CONFIG3: CONFIGURATION REGISTER 3; CP0 REGISTER 16, SELECT 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 r-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R-0 R-1 R-0 R-0 R-0 R-1 R-1 MCU ISAONEXC R-1 R-1 U-0 U-0 U-0 R-0 ULRI RXI — — — ITL — IPLW[1:0] R-0 R-1 ISA[1:0] MMAR[2:0] U-0 R-1 R-1 R-0 R-1 U-0 U-0 R-0 — VEIC VINT SP CDMM — — TL Legend: r = Reserved bit y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31 Reserved: This bit is hardwired as ‘0’ bit 30-23 Unimplemented: Read as ‘0’ bit 22-21 IPLW[1:0]: Width of the Status IPL and Cause RIPL bits 01 = IPL and RIPL bits are 8 bits in width bit 20-18 MMAR[2:0]: microMIPS™ Architecture Revision Level bits 000 = Release 1 bit 17 MCU: MIPS® MCU ASE Implemented bit 1 = MCU ASE is implemented bit 16 ISAONEXC: ISA on Exception bit 1 = microMIPS is used on entrance to an exception vector bit 15-14 ISA[1:0]: Instruction Set Availability bits 01 = Only microMIPS is implemented bit 13 ULRI: UserLocal Register Implemented bit 1 = UserLocal Coprocessor 0 register is implemented bit 12 RXI: RIE and XIE Implemented in PageGrain bit 1 = RIE and XIE bits are implemented bit 11-9 Unimplemented: Read as ‘0’ bit 8 ITL: Indicates that iFlowtrace™ Hardware is Present bit 0 = The iFlowtrace hardware is not implemented in the core bit 7 Unimplemented: Read as ‘0’ bit 6 VEIC: External Vector Interrupt Controller bit 1 = Support for an external interrupt controller is implemented. bit 5 VINT: Vector Interrupt bit 1 = Vector interrupts are implemented bit 4 SP: Small Page bit 0 = 4-Kbyte page size bit 3 CDMM: Common Device Memory Map bit 1 = CDMM is implemented bit 2-1 Unimplemented: Read as ‘0’ bit 0 TL: Trace Logic bit 0 = Trace logic is not implemented  2016-2019 Microchip Technology Inc. x = Bit is unknown DS60001387D-page 37 PIC32MM0256GPM064 FAMILY REGISTER 3-4: Bit Range 31:24 23:16 15:8 7:0 CONFIG5: CONFIGURATION REGISTER 5; CP0 REGISTER 16, SELECT 5 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-1 — — — — — — — NF Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-1 Unimplemented: Read as ‘0’ bit 0 NF: Nested Fault bit 1 = Nested Fault feature is implemented DS60001387D-page 38 x = Bit is unknown  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 4.0 MEMORY ORGANIZATION PIC32MM microcontrollers provide 4 GBytes of unified virtual memory address space. All memory regions, including program memory, data memory, SFRs and Configuration registers, reside in this address space at their respective unique addresses. The data memory can be made executable, allowing the CPU to execute code from data memory. Key features include: • 32-Bit Native Data Width • Separate Boot Flash Memory (BFM) for  Protected Code • Robust Bus Exception Handling to Intercept  Runaway Code • Simple Memory Mapping with Fixed Mapping Translation (FMT) Unit The PIC32MM0256GPM064 family devices implement two address spaces: virtual and physical. All hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions. Physical addresses are used by peripherals, such as Flash controllers, that access memory independently of the CPU. The virtual address space is divided into two segments of 512 Mbytes each, labeled kseg0 and kseg1. The Program Flash Memory (PFM) and Data RAM Memory (DRM) are accessible from either kseg0 or kseg1, while the Boot Flash Memory (BFM) and peripheral SFRs are accessible only from kseg1. The Fixed Mapping Translation (FMT) unit translates the memory segments into corresponding physical address regions. Figure 4-1 through Figure 4-3 illustrate the fixed mapping scheme, implemented by the PIC32MM0256GPM064 family core, between the virtual and physical address space. The mapping of the memory segments depends on the CPU error level, set by the ERL bit in the CPU STATUS Register. Error level is set (ERL = 1) by the CPU on a Reset, Soft Reset or Non-Maskable Interrupt (NMI). In this mode, the CPU can access memory by the physical address. This mode is provided for compatibility with other MIPS processor cores that use a TLB-based MMU. The C start-up code clears the ERL bit to zero, so that when application software starts up, it sees the proper virtual to physical memory mapping.  2016-2019 Microchip Technology Inc. 4.1 Alternate Configuration Bits Space Every Configuration Word has an associated Alternate Word (designated by the letter A as the first letter in the name of the word). During device start-up, Primary Words are read, and if uncorrectable ECC errors are found, the BCFGERR (RCON[27]) flag is set and Alternate Words are used. If uncorrectable ECC errors are found in Primary and Alternate Words, the BCFGFAIL (RCON[26]) flag is set, and the default configuration is used. The Primary Configuration bits’ area is located at the address range, from 0x1FC01780 to 0x1FC017E8. The Alternate Configuration bits’ area is located at the address range, from 0x1FC01700 to 0x1FC01768. 4.2 Bus Matrix (BMX) The BMX is a switch fabric that connects the system bus initiators (Flash controller, CPU instruction, CPU data, system DMA and USB) to bus targets (RAM, Flash and peripherals without integrated DMA). All data and instructions are transferred through this bus. Only one initiator can connect to a given target at a time. Multiple initiators can be active at one time provided each one has a separate target. Multiple priority modes (Round Robin, Fixed CPU Highest and Fixed CPU Lowest) are available to allow the priority to be tailored to the application needs. Mode 0 is a Fixed Priority mode with the CPU having the highest priority (refer to Table 4-1). For most applications, this mode should be sufficient; however, it is possible for the CPU to generate sufficient bus traffic to ‘starve’ the other initiators attempting to access Flash memory, preventing them from performing transfers in the required time limit. If this ‘starvation’ occurs, the Round Robin or CPU Lowest mode should be chosen. Mode 1 is a Fixed Priority mode with the CPU having the lowest priority (refer to Table 4-1). This mode can reduce the latency of DMA transfers because the DMA engines have a higher priority than the CPU. Mode 2 is a Round Robin or Rotating Priority mode. The initiator’s priority for each target rotates with every access. This ensures, not that the initiator is starved, but the latency for accesses changes with every access; this makes the latency variable. The Arbitration mode is selected by the BMXARB[1:0] bits (CFGCON[25:24]). Note: The CPU has two initiators: one for data and the other for instructions. In all Arbitration modes, the CPU data initiator has higher priority than the CPU instruction initiator. DS60001387D-page 39 PIC32MM0256GPM064 FAMILY TABLE 4-1: FIXED MODES ORDER OF PRIORITY Mode 1 Mode 0 CPU Lowest CPU Highest Highest Priority Flash Controller Flash Controller DMA CPU USB USB CPU DMA Lowest Priority Note: The Arbitration mode chosen only has an effect on system performance when a contention for a target occurs. Refer to Section 48. “Memory Organization and Permissions” (www.microchip.com/DS60001214) in the “PIC32 Family Reference Manual” for more information regarding Bus Matrix operation. 4.3 Flash Line Buffer The Flash line buffer is a buffer that resides between the Bus Matrix and the Flash memory. When a Flash fetch is generated, an aligned double word (64 bits) is read. This is then placed in the Flash line buffer. If the next initiator requested address’s data are contained in the Flash line buffer, they are read directly without requiring another Flash fetch; if they are not in the Flash line buffer, a Flash fetch is generated. The Flash controller, when programming memory, always has the highest priority regardless of the priority mode setting. DS60001387D-page 40  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY MEMORY MAP FOR DEVICES WITH 64 Kbytes OF PROGRAM MEMORY(1) FIGURE 4-1: Virtual Memory Map Reserved 16 Kbytes RAM Reserved Reserved 0x9F800000 SFRs(2) 0x9F80FFFF 0x9F810000 Reserved 0x9FBFFFFF 0x9FC00000 Boot Flash(2) 0x9FC016FF 0x9FC01700 Configuration Bits(2,3) 0x9FC017FF 0x9FC01800 Reserved 0x9FFFFFFF 0xA0000000 16 Kbytes RAM 0xA0003FFF 0xA0004000 Reserved 0xBCFFFFFF 0xBD000000 64 Kbytes Flash 0xBD00FFFF 0xBD010000 Reserved 0xBF7FFFFF 0xBF800000 SFRs 0xBF80FFFF 0xBF810000 Reserved 0xBFBFFFFF 0xBFC00000 Boot Flash 0xBFC016FF 0xBFC01700 Configuration Bits(3) 0xBFC017FF 0xBFC01800 Reserved 0xFFFFFFFF Note 1: 2: 3: kseg0 64 Kbytes Flash Physical Memory Map 16 Kbytes RAM Reserved 64 Kbytes Flash Reserved SFRs Reserved Boot Flash Configuration Bits(3) kseg1 0x00000000 0x7FFFFFFF 0x80000000 0x80003FFF 0x80004000 0x9CFFFFFF 0x9D000000 0x9D00FFFF 0x9D010000 0x9F7FFFFF Reserved 0x00000000 0x00003FFF 0x00004000 0x1CFFFFFF 0x1D000000 0x1D00FFFF 0x1D010000 0x1F7FFFFF 0x1F800000 0x1F80FFFF 0x1F810000 0x1FBFFFFF 0x1FC00000 0x1FC016FF 0x1FC01700 0x1FC017FF 0x1FC01800 0xFFFFFFFF Memory areas are not shown to scale. This region should be accessed from kseg1 space only. Primary Configuration bits’ area is located at the address range, from 0x1FC01780 to 0x1FC017E8. Alternate Configuration bits’ area is located at the address range, from 0x1FC01700 to 0x1FC01768. Refer to Section 4.1 “Alternate Configuration Bits Space” for more information.  2016-2019 Microchip Technology Inc. DS60001387D-page 41 PIC32MM0256GPM064 FAMILY MEMORY MAP FOR DEVICES WITH 128 Kbytes OF PROGRAM MEMORY(1) FIGURE 4-2: Virtual Memory Map Reserved 16 Kbytes RAM Reserved 128 Kbytes Flash 0x9F800000 SFRs(2) 0x9F80FFFF 0x9F810000 Reserved 0x9FBFFFFF 0x9FC00000 Boot Flash(2) 0x9FC016FF 0x9FC01700 Configuration Bits(2,3) 0x9FC017FF 0x9FC01800 Reserved 0x9FFFFFFF 0xA0000000 16 Kbytes RAM 0xA0003FFF 0xA0004000 Reserved 0xBCFFFFFF 0xBD000000 128 Kbytes Flash 0xBD01FFFF 0xBD020000 Reserved 0xBF7FFFFF 0xBF800000 SFRs 0xBF80FFFF 0xBF810000 Reserved 0xBFBFFFFF 0xBFC00000 Boot Flash 0xBFC016FF 0xBFC01700 Configuration Bits(3) 0xBFC017FF 0xBFC01800 Reserved 0xFFFFFFFF Note 1: 2: 3: DS60001387D-page 42 kseg0 Reserved Physical Memory Map 16 Kbytes RAM Reserved 128 Kbytes Flash Reserved SFRs Reserved Boot Flash Configuration Bits(3) Reserved kseg1 0x00000000 0x7FFFFFFF 0x80000000 0x80003FFF 0x80004000 0x9CFFFFFF 0x9D000000 0x9D01FFFF 0x9D020000 0x9F7FFFFF 0x00000000 0x80003FFF 0x80004000 0x1CFFFFFF 0x1D000000 0x1D01FFFF 0x1D020000 0x1F7FFFFF 0x1F800000 0x1F80FFFF 0x1F810000 0x1FBFFFFF 0x1FC00000 0x1FC016FF 0x1FC01700 0x1FC017FF 0x1FC01800 0xFFFFFFFF Memory areas are not shown to scale. This region should be accessed from kseg1 space only. Primary Configuration bits’ area is located at the address range, from 0x1FC01780 to 0x1FC017E8. Alternate Configuration bits’ area is located at the address range, from 0x1FC01700 to 0x1FC01768. Refer to Section 4.1 “Alternate Configuration Bits Space” for more information.  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY MEMORY MAP FOR DEVICES WITH 256 Kbytes OF PROGRAM MEMORY(1) FIGURE 4-3: Virtual Memory Map Reserved 32 Kbytes RAM Reserved Reserved 0x9F800000 SFRs(2) 0x9F80FFFF 0x9F810000 Reserved 0x9FBFFFFF 0x9FC00000 Boot Flash(2) 0x9FC016FF 0x9FC01700 Configuration Bits(2,3) 0x9FC017FF 0x9FC01800 Reserved 0x9FFFFFFF 0xA0000000 32 Kbytes RAM 0xA0007FFF 0xA0008000 Reserved 0xBCFFFFFF 0xBD000000 256 Kbytes Flash 0xBD03FFFF 0xBD040000 Reserved 0xBF7FFFFF 0xBF800000 SFRs 0xBF80FFFF 0xBF810000 Reserved 0xBFBFFFFF 0xBFC00000 Boot Flash 0xBFC016FF 0xBFC01700 Configuration Bits(3) 0xBFC017FF 0xBFC01800 Reserved 0xFFFFFFFF Note 1: 2: 3: kseg0 256 Kbytes Flash Physical Memory Map 32 Kbytes RAM Reserved 256 Kbytes Flash Reserved SFRs Reserved Boot Flash Configuration Bits(3) Reserved kseg1 0x00000000 0x7FFFFFFF 0x80000000 0x80007FFF 0x80008000 0x9CFFFFFF 0x9D000000 0x9D003FFF 0x9D004000 0x9F7FFFFF 0x00000000 0x00007FFF 0x00008000 0x1CFFFFFF 0x1D000000 0x1D03FFFF 0x1D040000 0x1F7FFFFF 0x1F800000 0x1F80FFFF 0x1F810000 0x1FBFFFFF 0x1FC00000 0x1FC016FF 0x1FC01700 0x1FC017FF 0x1FC01800 0xFFFFFFFF Memory areas are not shown to scale. This region should be accessed from kseg1 space only. Primary Configuration bits’ area is located at the address range, from 0x1FC01780 to 0x1FC017E8. Alternate Configuration bits’ area is located at the address range, from 0x1FC01700 to 0x1FC01768. Refer to Section 4.1 “Alternate Configuration Bits Space” for more information.  2016-2019 Microchip Technology Inc. DS60001387D-page 43 PIC32MM0256GPM064 FAMILY NOTES: DS60001387D-page 44  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 5.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. “Flash Programming” (www.microchip.com/DS60001121) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. PIC32MM0256GPM064 family devices contain an internal Flash program memory for executing user code. The program and Boot Flash can be writeprotected. The erase page size is 512 32-bit words. The program row size is 64 32-bit words. The memory can be programmed by rows or by two 32-bit words, called double-words. Note: Double-words must be 64-bit aligned. The devices implement a 6-bit Error Correcting Code (ECC). The memory control block contains a logic to write and read ECC bits to and from the Flash memory. The Flash is programmed at the same time as the corresponding ECC bits. The ECC provides improved resistance to Flash errors. The ECC single-bit error generates an interrupt and can be transparently corrected. The ECC double-bit error results in a bus error exception. There are three methods by which the user can program this memory: • Run-Time Self-Programming (RTSP) • EJTAG Programming • In-Circuit Serial Programming™ (ICSP™) RTSP is performed by software executing from either Flash or RAM memory. Information about RTSP techniques is described in Section 5. “Flash Programming” (www.microchip.com/DS60001121) in the “PIC32 Family Reference Manual”. EJTAG programming is performed using the JTAG port of the device. ICSP programming requires fewer connections than for EJTAG programming. The EJTAG and ICSP methods are described in the “PIC32 Flash Programming Specification” (DS60001145), which is available for download from the Microchip website. 5.1 Flash Controller Registers Write Protection The NVMPWP and NVMBWP registers, and the WR bit in the NVMCON register are protected (locked) from an accidental write. Each time a special unlock sequence is required to modify the content of these registers or bits. To unlock, the following steps should be done: 1. 2. 3. 4. 5. Disable interrupts prior to the unlock sequence. Execute the system unlock sequence by writing the key values of 0xAA996655 and 0x556699AA to the NVMKEY register. Write the new value to the required bits. Re-enable interrupts. Relock the system. Refer to Example 5-1. EXAMPLE 5-1: // unlock sequence NVMKEY = 0xAA996655; NVMKEY = 0x556699AA; // relock NVMKEY = 0;  2016-2019 Microchip Technology Inc. DS60001387D-page 45 Flash Control Registers Register Name FLASH CONTROLLER REGISTER MAP Virtual Address (BF80_#) TABLE 5-1: 2930 NVMCON(1) 2940 2950 2960 2970 NVMKEY (1) NVMADDR NVMDATA0 NVMDATA1 2980 NVMSRCADDR 2990 29A0 (1) NVMPWP (1) NVMBWP 31/15 30/14 31:16 — — 15:0 WR WREN 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 — — — — — — — — — — — r — — — — — — — WRERR LVDERR 31:16 16/0 — — — NVMOP[3:0] 31:16 0000 0000 0000 NVMADDR[31:0] 15:0 31:16 0000 0000 NVMDATA0[31:0] 15:0 31:16 0000 0000 NVMDATA1[31:0] 15:0 31:16 0000 0000 NVMSRCADDR[31:0] 15:0 31:16 PWPULOCK 0000 — — — — — — — — — — — — — — — — — — — — — — 0000 — — — — BWP2 BWP1 BWP0 — — — — — — — — 8700 15:0 PWP[23:16] 8000 PWP[15:0] — 15:0 BWPULOCK 0000 0000 0000 Legend: — = unimplemented, read as ‘0’; r = Reserved bit. Reset values are shown in hexadecimal. Note 1: 17/1 NVMKEY[31:0] 15:0 31:16 18/2 All Resets Bit Range Bits These registers have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. PIC32MM0256GPM064 FAMILY DS60001387D-page 46 5.2  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 5-1: Bit Range 31:24 23:16 15:8 7:0 NVMCON: PROGRAMMING CONTROL REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — r-0 U-0 U-0 U-0 — R/W-0, HC (1,3) WR — — R/W-0 (1) R-0, HS, HC (1,2) WREN WRERR R-0, HS, HC (1,2) LVDERR U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 NVMOP[3:0] Legend: HS = Hardware Settable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared r = Reserved bit bit 31-16 Unimplemented: Read as ‘0’ bit 15 WR: Write Control bit(1,3) This bit cannot be cleared and can be set only when WREN = 1, and the unlock sequence has been performed. 1 = Initiates a Flash operation 0 = Flash operation is complete or inactive bit 14 WREN: Write Enable bit(1) 1 = Enables writes to the WR bit and disables writes to the NVMOP[3:0] bits 0 = Disables writes to the WR bit and enables writes to the NVMOP[3:0] bits bit 13 WRERR: Write Error bit(1,2) This bit can be cleared only by setting the NVMOP[3:0] bits = 0000 and initiating a Flash operation. 1 = Program or erase sequence did not complete successfully 0 = Program or erase sequence completed normally bit 12 LVDERR: Low-Voltage Detect Error bit(1,2) This bit can be cleared only by setting the NVMOP[3:0] bits = 0000 and initiating a Flash operation. 1 = Low-voltage is detected (possible data corruption if WRERR is set) 0 = Voltage level is acceptable for programming bit 11 Reserved: Maintain as ‘0’ bit 10-4 Unimplemented: Read as ‘0’ Note 1: 2: 3: These bits are only reset by a Power-on Reset (POR) and are not affected by other Reset sources. These bits are cleared by setting NVMOP[3:0] = 0000 and initiating a Flash operation (i.e., WR). This bit is only writable when the NVMKEY unlock sequence is followed. Refer to Example 5-1.  2016-2019 Microchip Technology Inc. DS60001387D-page 47 PIC32MM0256GPM064 FAMILY REGISTER 5-1: NVMCON: PROGRAMMING CONTROL REGISTER (CONTINUED) bit 3-0 NVMOP[3:0]: NVM Operation bits These bits are only writable when WREN = 0. 1111 = Reserved • • • 1000 = Reserved 0111 = Program Erase Operation: Erases all of Program Flash Memory (all pages must be unprotected, PWP[23:0] = 0x000000, Boot Flash Memory is not erased) 0110 = Reserved 0101 = Reserved 0100 = Page Erase Operation: Erases page selected by NVMADDR if it is not write-protected 0011 = Row Program Operation: Programs row selected by NVMADDR if it is not write-protected 0010 = Double-Word Program Operation: Programs two words to address selected by NVMADDR if it is not write-protected 0001 = Reserved 0000 = No operation (clears the WRERR and LVDERR status bits when executed) Note 1: 2: 3: These bits are only reset by a Power-on Reset (POR) and are not affected by other Reset sources. These bits are cleared by setting NVMOP[3:0] = 0000 and initiating a Flash operation (i.e., WR). This bit is only writable when the NVMKEY unlock sequence is followed. Refer to Example 5-1. REGISTER 5-2: Bit Range 31:24 23:16 15:8 7:0 NVMKEY: PROGRAMMING UNLOCK REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY[31:24] W-0 NVMKEY[23:16] W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY[15:8] W-0 NVMKEY[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 Note: x = Bit is unknown NVMKEY[31:0]: Programming Unlock Register bits These bits are write-only and read as ‘0’ on any read. This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM. Refer to Example 5-1. DS60001387D-page 48  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 5-3: Bit Range 31:24 23:16 15:8 7:0 NVMADDR: FLASH ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR[31:24](1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR[23:16](1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR[15:8] NVMADDR[7:0](1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 x = Bit is unknown NVMADDR[31:0]: Flash Address bits(1) NVMOP[3:0] Selection Flash Address Bits (NVMADDR[31:0]) Page Erase Address identifies the page to erase (NVMADDR[10:0] are ignored). Row Program Address identifies the row to program (NVMADDR[7:0] are ignored). Double-Word Program Address identifies the double-word (64-bit) to program (NVMADDR[2:0] bits are ignored). Note: Must be 64-bit aligned. Note 1: Note: For all other NVMOP[3:0] bits settings, the Flash address is ignored. See the NVMCON register (Register 5-1) for additional information on these bits. The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other Reset sources.  2016-2019 Microchip Technology Inc. DS60001387D-page 49 PIC32MM0256GPM064 FAMILY REGISTER 5-4: Bit Range 31:24 23:16 15:8 7:0 NVMDATAx: FLASH DATA x REGISTER (x = 0-1) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATAx[31:24] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATAx[23:16] R/W-0 NVMDATAx[15:8] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATAx[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 NVMDATAx[31:0]: Flash Data x bits Double-Word Program: Writes NVMDATA1:NVMDATA0 to the target Flash address defined in NVMADDR. NVMDATA0 contains the least significant instruction word. Note: The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other Reset sources. REGISTER 5-5: Bit Range 31:24 23:16 15:8 7:0 NVMSRCADDR: SOURCE DATA ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR[31:24] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR[23:16] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR[15:8] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 Note: x = Bit is unknown NVMSRCADDR[31:0]: Source Data Address bits The system physical address of the data to be programmed into the Flash when the NVMOP[3:0] bits (NVMCON[3:0]) are set to perform row programming. The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other Reset sources. DS60001387D-page 50  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 5-6: Bit Range 31:24 23:16 15:8 7:0 NVMPWP: PROGRAM FLASH WRITE-PROTECT REGISTER Bit 31/23/15/7 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 PWPULOCK — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWP[23:16] R/W-0 PWP[15:8] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWP[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31 x = Bit is unknown PWPULOCK: Program Flash Memory Page Write-Protect Unlock bit 1 = Register is not locked and can be modified 0 = Register is locked and cannot be modified This bit is only clearable and cannot be set except by any Reset. bit 30-24 Unimplemented: Read as ‘0’ bit 23-0 PWP[23:0]: Flash Program Write-Protect (Page) Address bits Physical memory below address, 0x1DXXXXXX, is write-protected, where ‘XXXXXX’ is specified by PWP[23:0]. When the PWP[23:0] bits have a value of ‘0’, write protection is disabled for the entire Program Flash Memory. If the specified address falls within the page, the entire page and all pages below the current page will be protected. Note: The bits in this register are only writable when the NVMKEY unlock sequence is followed. Refer to Example 5-1.  2016-2019 Microchip Technology Inc. DS60001387D-page 51 PIC32MM0256GPM064 FAMILY REGISTER 5-7: Bit Range 31:24 23:16 15:8 7:0 NVMBWP: BOOT FLASH (PAGE) WRITE-PROTECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — R/W-1 U-0 U-0 U-0 U-0 — R/W-1 (1) BWP2 — R/W-1 (1) BWP1 — R/W-1 (1) BWPULOCK — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 BWP0 U-0 — — — — — — — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 BWPULOCK: Boot Alias Write-Protect Unlock bit 1 = BWPx bits are not locked and can be modified 0 = BWPx bits are locked and cannot be modified This bit is only clearable and cannot be set except by any Reset. bit 14-11 Unimplemented: Read as ‘0’ bit 10 BWP2: Boot Alias Page 2 Write-Protect bit(1) 1 = Write protection for physical address, 0x01FC08000 through 0x1FC0BFFF, is enabled 0 = Write protection for physical address, 0x01FC08000 through 0x1FC0BFFF, is disabled bit 9 BWP1: Boot Alias Page 1 Write-Protect bit(1) 1 = Write protection for physical address, 0x01FC04000 through 0x1FC07FFF, is enabled 0 = Write protection for physical address, 0x01FC04000 through 0x1FC07FFF, is disabled bit 8 BWP0: Boot Alias Page 0 Write-Protect bit(1) 1 = Write protection for physical address, 0x01FC00000 through 0x1FC03FFF, is enabled 0 = Write protection for physical address, 0x01FC00000 through 0x1FC03FFF, is disabled bit 7-0 Unimplemented: Read as ‘0’ Note 1: These bits are only available when the NVMKEY unlock sequence is performed and the associated lock bit (BWPULOCK) is set. Note: The bits in this register are only writable when the NVMKEY unlock sequence is followed. Refer to Example 5-1. DS60001387D-page 52  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 6.0 RESETS Note: This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. “Resets” (www.microchip.com/DS60001118) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The device Reset sources are as follows: • Power-on Reset (POR) • Master Clear Reset Pin (MCLR) • Software Reset (SWR) FIGURE 6-1: • Watchdog Timer Reset (WDTR) • Brown-out Reset (BOR) • Configuration Mismatch Reset (CMR) EXAMPLE 6-1: SOFTWARE RESET CODE // interrupts should be disabled SYSKEY = 0; // force lock SYSKEY = 0xAA996655; // unlock SYSKEY = 0x556699AA; RSWRST = 1; unsigned long int bitBucket =RSWRST; // initiate the reset while(1); A simplified block diagram of the Reset module is illustrated in Figure 6-1. Refer to Example 6-1 for example Software Reset code. SYSTEM RESET BLOCK DIAGRAM MCLR Glitch Filter Sleep or Idle MCLR WDTR WDT Time-out NMI Time-out Voltage Regulator Enabled POR SYSRST VDD VDD Rise Detect Brown-out Reset Configuration Mismatch Reset Software Reset  2016-2019 Microchip Technology Inc. BOR CMR SWR DS60001387D-page 53 Reset Control Registers Virtual Address (BF80_#) Register Name(1) TABLE 6-1: 26E0 RCON 26F0 RSWRST 2700 RNMICON 2710 PWRCON RESETS REGISTER MAP 31/15 30/14 31:16 PORIO PORCORE 15:0 — — 31:16 — — 15:0 — — 31:16 — — 29/13 28/12 27/11 26/10 25/9 24/8 — — BCFGERR — — — BCFGFAIL — — — CMR — — — — — — — — — — — — — — — — — — WDTR 15:0 23/7 20/4 22/6 21/5 — — — — — — — — C000 EXTR SWR — WDTO SLEEP IDLE BOR POR 0003 — — — — — — — — 0000 — — — — — — — 18/2 17/1 16/0 SWNMI — — — GNMI — CF SWRST 0000 WDTS NMICNT[15:0] 0000 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — — SBOREN RETEN VREGS 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: 19/3 All Resets Bit Range Bits All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. PIC32MM0256GPM064 FAMILY DS60001387D-page 54 6.1  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 6-1: Bit Range 31:24 23:16 15:8 7:0 RCON: RESET CONTROL REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 R/W-0, HS R/W-0, HS U-0 U-0 R/W-1, HS R/W-1, HS PORIO PORCORE — — BCFGERR BCFGFAIL — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS U-0 — — — — — — CMR — R/W-0, HS (1) R/W-0, HS (1) U-0 R/W-0, HS (1) R/W-0, HS (1) R/W-0, HS (1,2) R/W-1, HS (1) R/W-1, HS (1) EXTR SWR — WDTO SLEEP IDLE BOR Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31 PORIO: VDD POR Flag bit Set by hardware at detection of a VDD POR event. 1 = A Power-on Reset has occurred due to VDD voltage 0 = A Power-on Reset has not occurred due to VDD voltage bit 30 PORCORE: Core Voltage POR Flag bit Set by hardware at detection of a core POR event. 1 = A Power-on Reset has occurred due to core voltage 0 = A Power-on Reset has not occurred due to core voltage POR x = Bit is unknown bit 29-28 Unimplemented: Read as ‘0’ bit 27 BCFGERR: Primary Configuration Registers Error Flag bit 1 = An error occurred during a read of the Primary Configuration registers 0 = No error occurred during a read of the Primary Configuration registers bit 26 BCFGFAIL: Primary/Alternate Configuration Registers Error Flag bit 1 = An error occurred during a read of the Primary and Alternate Configuration registers 0 = No error occurred during a read of the Primary and Alternate Configuration registers bit 25-10 Unimplemented: Read as ‘0’ bit 9 CMR: Configuration Mismatch Reset Flag bit 1 = Configuration Mismatch Reset has occurred 0 = A Configuration Mismatch Reset has not occurred bit 8 Unimplemented: Read as ‘0’ bit 7 EXTR: External Reset (MCLR) Pin Flag bit(1) 1 = Master Clear (pin) Reset has occurred 0 = Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset Flag bit(1) 1 = Software Reset was executed 0 = Software Reset was not executed bit 5 Unimplemented: Read as ‘0’ bit 4 WDTO: Watchdog Timer Time-out Flag bit(1) 1 = WDT time-out has occurred 0 = WDT time-out has not occurred Note 1: 2: User software must clear these bits to view the next detection. The IDLE bit will also be set when the device wakes from Sleep.  2016-2019 Microchip Technology Inc. DS60001387D-page 55 PIC32MM0256GPM064 FAMILY REGISTER 6-1: RCON: RESET CONTROL REGISTER (CONTINUED) bit 3 SLEEP: Wake from Sleep Flag bit(1) 1 = Device was in Sleep mode 0 = Device was not in Sleep mode bit 2 IDLE: Wake from Idle Flag bit(1,2) 1 = Device was in Idle mode 0 = Device was not in Idle mode bit 1 BOR: Brown-out Reset Flag bit(1) 1 = Brown-out Reset has occurred 0 = Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit(1) 1 = Power-on Reset has occurred 0 = Power-on Reset has not occurred Note 1: 2: User software must clear these bits to view the next detection. The IDLE bit will also be set when the device wakes from Sleep. REGISTER 6-2: Bit Range 31:24 23:16 15:8 7:0 RSWRST: SOFTWARE RESET REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — U-0 U-0 U-0 U-0 U-0 — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared — SWRST x = Bit is unknown bit 31-1 Unimplemented: Read as ‘0’ bit 0 SWRST: Software Reset Trigger bit(1,2) 1 = Enables Software Reset event 0 = No effect Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section 26.4 “System Registers Write Protection” for details. Once this bit is set, any read of the RSWRST register will cause a Reset to occur. 2: DS60001387D-page 56 W-0, HC (1,2)  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 6-3: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 — — — — R/W-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R/W-0 — — — WDTR U-0 R/W-0 U-0 R/W-0 R/W-0 SWNMI — — — GNMI — CF WDTS R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NMICNT[15:8] R/W-0 7:0 RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER(2) R/W-0 R/W-0 R/W-0 R/W-0 NMICNT[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-25 Unimplemented: Read as ‘0’ bit 24 WDTR: Watchdog Timer Time-out Flag bit 1 = A Run mode WDT time-out has occurred and caused an NMI 0 = WDT time-out has not occurred Setting this bit will cause a WDT NMI event and the NMICNTx bits will begin counting. bit 23 SWNMI: Software NMI Trigger bit 1 = An NMI has been generated 0 = An NMI has not been generated bit 22-20 Unimplemented: Read as ‘0’ bit 19 GNMI: Software General NMI Trigger bit 1 = A general NMI has been generated 0 = A general NMI has not been generated bit 18 Unimplemented: Read as ‘0’ bit 17 CF: Clock Fail Detect bit 1 = FSCM has detected clock failure and caused an NMI 0 = FSCM has not detected clock failure Setting this bit will cause a CF NMI event, but will not cause a clock switch to the FRC. bit 16 WDTS: Watchdog Timer Time-out in Sleep Mode Flag bit 1 = WDT time-out has occurred during Sleep mode and caused a wake-up from Sleep 0 = WDT time-out has not occurred during Sleep mode Setting this bit will cause a WDT NMI. bit 15-0 NMICNT[15:0]: NMI Reset Counter Value bits These bits specify the reload value used by the NMI Reset counter. 0xFFFF-0x0001 = Number of SYSCLK cycles before a device Reset occurs(1) 0x0000 = No delay between NMI assertion and device Reset event Note 1: If a Watchdog Timer NMI event (when not in Sleep or Idle mode) is cleared before this counter reaches ‘0’, no device Reset is asserted. This NMI Reset counter is only applicable to the Watchdog Timer NMI event. The system unlock sequence must be performed before the RNMICON register can be written. Refer to Section 26.4 “System Registers Write Protection” for details. 2:  2016-2019 Microchip Technology Inc. DS60001387D-page 57 PIC32MM0256GPM064 FAMILY REGISTER 6-4: Bit Range 31:24 23:16 15:8 7:0 PWRCON: POWER CONTROL REGISTER(2) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — SBOREN RETEN(1) VREGS Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-3 Unimplemented: Read as ‘0’ bit 2 SBOREN: BOR Enable bit Enables the BOR for select BOREN Configuration bit settings. 1 = Writing a ‘1’ to this bit enables the BOR for select BOREN configuration values 0 = Writing a ‘0’ to this bit enables the BOR for select BOREN configuration values bit 1 RETEN: Output Level of the Regulator During Sleep Selection bit(1) 1 = Writing a ‘1’ to this bit will cause the main regulator to be put in a low-power state during Sleep mode(3) 0 = Writing a ‘0’ to this bit will have no effect bit 0 VREGS: Voltage Regulator Standby Enable bit 1 = Voltage regulator will remain active during Sleep mode 0 = Voltage regulator will go into Standby mode during Sleep mode Note 1: 2: 3: Refer to Section 25.0 “Power-Saving Features” for details. The SYSKEY register is used to unlock this register. The RETEN bit in the device configuration must also be set to enable this mode. DS60001387D-page 58  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 7.0 Note: CPU EXCEPTIONS AND INTERRUPT CONTROLLER This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Interrupts” (www.microchip.com/DS60001108) and Section 50. “CPU for Devices with MIPS32® microAptiv™ and M-Class Cores” (www.microchip.com/DS60001192) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. PIC32MM0256GPM064 family devices generate interrupt requests in response to interrupt events from peripheral modules. The interrupt control module exists externally to the CPU logic and prioritizes the interrupt events before presenting them to the CPU. The PIC32MM0256GPM064 family device interrupt module includes the following features: • • • • • • • • • Single Vector or Multivector Mode Operation Five External Interrupts with Edge Polarity Control Interrupt Proximity Timer Module Freeze in Debug mode Seven User-Selectable Priority Levels for Each Vector Four User-Selectable Subpriority Levels within Each Priority One Shadow Register Set that can be Used for Any Priority Level, Eliminating Software Context Switch and Reducing Interrupt Latency Software can Generate any Interrupt User-Configurable Interrupt Vectors’ Offset and Vector Table Location Figure 7-1 shows the block diagram for the interrupt controller and CPU exceptions. The CPU handles interrupt events as part of the exception handling mechanism, which is described in Section 7.1 “CPU Exceptions”. CPU EXCEPTIONS AND INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM Interrupt Requests FIGURE 7-1: Vector Number and Offset Interrupt Controller Priority Level CPU Core (Exception Handling) Shadow Set Number SYSCLK  2016-2019 Microchip Technology Inc. DS60001387D-page 59 CPU Exceptions CPU Coprocessor 0 contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including boundary cases in data, external events or program errors. Table 7-1 lists the exception types in order of priority. TABLE 7-1: Exception Type (In Order of Priority) MIPS32® microAptiv™ UC MICROPROCESSOR CORE EXCEPTION TYPES Description Branches to Status Bits Set Debug Bits Set EXCCODE XC32 Function Name Highest Priority  2016-2019 Microchip Technology Inc. Reset Assertion of MCLR. 0xBFC0_0000 BEV, ERL — — _on_reset Soft Reset Execution of a RESET instruction. 0xBFC0_0000 BEV, SR, ERL — — _on_reset DSS EJTAG debug single step. 0xBFC0_0480 (ProbEn = 0 in ECR) 0xBFC0_0200 (ProbEn = 1 in ECR) — DSS — — DINT EJTAG debug interrupt. Caused by setting the EjtagBrk bit in the ECR register. 0xBFC0_0480 (ProbEn = 0 in ECR) 0xBFC0_0200 (ProbEn = 1 in ECR) — DINT — — NMI Non-Maskable Interrupt. 0xBFC0_0000 BEV, NMI, ERL — — Interrupt Assertion of unmasked hardware or software  interrupt signal. See Table 7-2 IPL[2:0] — Int (0x00) DIB EJTAG debug hardware instruction break matched. 0xBFC0_0480 (ProbEn = 0 in ECR) 0xBFC0_0200 (ProbEn = 1 in ECR) — DIB — AdEL Load address alignment error. EBASE + 0x180 EXL — IBE Instruction fetch bus error. EBASE + 0x180 EXL — IBE (0x06) _general_exception_handler DBp EJTAG breakpoint (execution of SDBBP  instruction). 0xBFC0_0480 (ProbEn = 0 in ECR) 0xBFC0_0200 (ProbEn = 1 in ECR) DBp — — — Sys Execution of SYSCALL instruction. EBASE + 0x180 EXL — Sys (0x08) _general_exception_handler Bp Execution of BREAK instruction. EBASE + 0x180 EXL — Bp (0x09) _general_exception_handler _nmi_handler See Table 7-2 — ADEL (0x04) _general_exception_handler PIC32MM0256GPM064 FAMILY DS60001387D-page 60 7.1  2016-2019 Microchip Technology Inc. TABLE 7-1: Exception Type (In Order of Priority) MIPS32® microAptiv™ UC MICROPROCESSOR CORE EXCEPTION TYPES (CONTINUED) Description Branches to Status Bits Set Debug Bits Set EXCCODE XC32 Function Name CpU Execution of a coprocessor instruction for a  coprocessor that is not enabled. EBASE + 0x180 CU, EXL — RI Execution of a reserved instruction. EBASE + 0x180 EXL — RI (0x0A) _general_exception_handler Ov Execution of an arithmetic instruction that  overflowed. EBASE + 0x180 EXL — Ov (0x0C) _general_exception_handler Tr Execution of a trap (when trap condition is true). EBASE + 0x180 EXL — Tr (0x0D) _general_exception_handler DDBL EJTAG data address break (address only) or EJTAG data value break on load (address and value). 0xBFC0_0480 (ProbEn = 0 in ECR) 0xBFC0_0200 (ProbEn = 1 in ECR) — DDBL for a load instruction or DDBS for a store instruction — — DDBS EJTAG data address break (address only) or EJTAG data value break on store (address and value). 0xBFC0_0480 (ProbEn = 0 in ECR) 0xBFC0_0200 (ProbEn = 1 in ECR) — DDBL for a load instruction or DDBS for a store instruction — — AdES Store address alignment error. EBASE + 0x180 EXL — ADES (0x05) _general_exception_handler DBE Load or store bus error. EBASE + 0x180 EXL — DBE (0x07) _general_exception_handler CBrk EJTAG complex breakpoint. 0xBFC0_0480 (ProbEn = 0 in ECR) 0xBFC0_0200 (ProbEn = 1 in ECR) — DIBImpr, DDBLImpr and/or DDBSImpr — — DS60001387D-page 61 PIC32MM0256GPM064 FAMILY Lowest Priority CpU (0x0B) _general_exception_handler Interrupts The PIC32MM0256GPM064 family uses fixed offset for vector spacing. For details, refer to Section 8. “Interrupts” (DS61108) in the “PIC32 Family Reference Manual”. Table 7-2 provides the interrupt related vectors and bits information. TABLE 7-2: INTERRUPTS Interrupt Source Core Timer Interrupt Related Bits Location MPLAB® XC32 Vector Name Vector Number Flag Enable Priority Subpriority Persistent Interrupt _CORE_TIMER_VECTOR 0 IFS0[0] IEC0[0] IPC0[4:2] IPC0[1:0] No Core Software 0 _CORE_SOFTWARE_0_VECTOR 1 IFS0[1] IEC0[1] IPC0[12:10] IPC0[9:8] No Core Software 1 _CORE_SOFTWARE_1_VECTOR 2 IFS0[2] IEC0[2] IPC0[20:18] IPC0[17:16] No External 0 _EXTERNAL_0_VECTOR 3 IFS0[3] IEC0[3] IPC0[28:26] IPC0[25:24] No External 1 _EXTERNAL_1_VECTOR 4 IFS0[4] IEC0[4] IPC1[4:2] IPC1[1:0] No External 2 _EXTERNAL_2_VECTOR 5 IFS0[5] IEC0[5] IPC1[12:10] IPC1[9:8] No External 3 _EXTERNAL_3_VECTOR 6 IFS0[6] IEC0[6] IPC1[20:18] IPC1[17:16] No External 4 PORTA Change Notification _EXTERNAL_4_VECTOR 7 IFS0[7] IEC0[7] IPC1[28:26] IPC1[25:24] No _CHANGE_NOTICE_A_VECTOR 8 IFS0[8] IEC0[8] IPC2[4:2] IPC2[1:0] No PORTB Change Notification _CHANGE_NOTICE_B_VECTOR 9 IFS0[9] IEC0[9] IPC2[12:10] IPC2[9:8] No PORTC Change Notification _CHANGE_NOTICE_C_VECTOR 10 IFS0[10] IEC0[10] IPC2[20:18] IPC2[17:16] No PORTD Change Notification _CHANGE_NOTICE_D_VECTOR No 11 IFS0[11] IEC0[11] IPC2[28:26] IPC2[25:24] RESERVED 12 IFS0[12] IEC0[12] IPC3[4:2] IPC3[1:0] No RESERVED 13 IFS0[13] IEC0[13] IPC3[12:10] IPC3[9:8] No RESERVED 14 IFS0[14] IEC0[14] IPC3[20:18] IPC3[17:16] No RESERVED 15 IFS0[15] IEC0[15] IPC3[28:26] IPC3[25:24] No RESERVED 16 IFS0[16] IEC0[16] IPC4[4:2] IPC4[1:0] No  2016-2019 Microchip Technology Inc. Timer1 _TIMER_1_VECTOR 17 IFS0[17] IEC0[17] IPC4[12:10] IPC4[9:8] No Timer2 _TIMER_2_VECTOR 18 IFS0[18] IEC0[18] IPC4[20:18] IPC4[17:16] No Timer3 _TIMER_3_VECTOR No 19 IFS0[19] IEC0[19] IPC4[28:26] IPC4[25:24] RESERVED 20 IFS0[20] IEC0[20] IPC5[4:2] IPC5[1:0] No RESERVED 21 IFS0[21] IEC0[21] IPC5[12:10] IPC5[9:8] No RESERVED 22 IFS0[22] IEC0[22] IPC5[20:18] IPC5[17:16] No No Comparator 1 _COMPARATOR_1_VECTOR 23 IFS0[23] IEC0[23] IPC5[28:26] IPC5[25:24] Comparator 2 _COMPARATOR_2_VECTOR 24 IFS0[24] IEC0[24] IPC6[4:2] IPC6[1:0] No Comparator 3 _COMPARATOR_3_VECTOR 25 IFS0[25] IEC0[25] IPC6[12:10] IPC6[9:8] No PIC32MM0256GPM064 FAMILY DS60001387D-page 62 7.2  2016-2019 Microchip Technology Inc. TABLE 7-2: INTERRUPTS (CONTINUED) Interrupt Related Bits Location Vector Number Flag Enable Priority Subpriority Persistent Interrupt RESERVED 26 IFS0[26] IEC0[26] IPC6[20:18] IPC6[17:16] No RESERVED 27 IFS0[27] IEC0[27] IPC6[28:26] IPC6[25:24] No RESERVED 28 IFS0[28] IEC0[28] IPC7[4:2] IPC7[1:0] No 29 IFS0[29] IEC0[29] IPC7[12:10] IPC7[9:8] No RESERVED 30 IFS0[30] IEC0[30] IPC7[20:18] IPC7[17:16] No RESERVED 31 IFS0[31] IEC0[31] IPC7[28:26] IPC7[25:24] No _RTCC_VECTOR 32 IFS1[0] IEC1[0] IPC8[4:2] IPC8[1:0] No _ADC_VECTOR 33 IFS1[1] IEC1[1] IPC8[12:10] IPC8[9:8] No RESERVED 34 IFS1[2] IEC1[2] IPC8[20:18] IPC8[17:16] No RESERVED 35 IFS1[3] IEC1[3] IPC8[28:26] IPC8[25:24] No Interrupt Source USB Real-Time Clock Alarm ADC Conversion MPLAB® XC32 Vector Name _USB_VECTOR _HLVD_VECTOR 36 IFS1[4] IEC1[4] IPC9[4:2] IPC9[1:0] Yes Logic Cell 1 _CLC1_VECTOR 37 IFS1[5] IEC1[5] IPC9[12:10] IPC9[9:8] No Logic Cell 2 _CLC2_VECTOR 38 IFS1[6] IEC1[6] IPC9[20:18] IPC9[17:16] No Logic Cell 3 _CLC3_VECTOR 39 IFS1[7] IEC1[7] IPC9[28:26] IPC9[25:24] No Logic Cell 4 _CLC4_VECTOR 40 IFS1[8] IEC1[8] IPC10[4:2] IPC10[1:0] No SPI1 Error _SPI1_ERR_VECTOR 41 IFS1[9] IEC1[9] IPC10[12:10] IPC10[9:8] Yes SPI1 Transmission _SPI1_TX_VECTOR 42 IFS1[10] IEC1[10] IPC10[20:18] IPC10[17:16] Yes SPI1 Reception _SPI1_RX_VECTOR 43 IFS1[11] IEC1[11] IPC10[28:26] IPC10[25:24] Yes _SPI2_ERR_VECTOR 44 IFS1[12] IEC1[12] IPC11[4:2] IPC11[1:0] Yes _SPI2_TX_VECTOR 45 IFS1[13] IEC1[13] IPC11[12:10] IPC11[9:8] Yes SPI2 Error SPI2 Transmission SPI2 Reception SPI3 Error _SPI2_RX_VECTOR 46 IFS1[14] IEC1[14] IPC11[20:18] IPC11[17:16] Yes _SPI3_ERR_VECTOR 47 IFS1[15] IEC1[15] IPC11[28:26] IPC11[25:24] Yes DS60001387D-page 63 SPI3 Transmission _SPI3_TX_VECTOR 48 IFS1[16] IEC1[16] IPC12[4:2] IPC12[1:0] Yes SPI3 Reception _SPI3_RX_VECTOR 49 IFS1[17] IEC1[17] IPC12[12:10] IPC12[9:8] Yes RESERVED 50 IFS1[18] IEC1[18] IPC12[20:18] IPC12[17:16] No RESERVED 51 IFS1[19] IEC1[19] IPC12[28:26] IPC12[25:24] No RESERVED 52 IFS1[20] IEC1[20] IPC13[4:2] IPC13[1:0] No 53 IFS1[21] IEC1[21] IPC13[12:10] IPC13[9:8] Yes UART1 Reception UART1 Transmission UART1 Error _UART1_RX_VECTOR _UART1_TX_VECTOR 54 IFS1[22] IEC1[22] IPC13[20:18] IPC13[17:16] Yes _UART1_ERR_VECTOR 55 IFS1[23] IEC1[23] IPC13[28:26] IPC13[25:24] Yes PIC32MM0256GPM064 FAMILY High/Low-Voltage Detect INTERRUPTS (CONTINUED) Interrupt Related Bits Location MPLAB® XC32 Vector Name Vector Number Flag Enable UART2 Reception _UART2_RX_VECTOR 56 IFS1[24] IEC1[24] IPC14[4:2] IPC14[1:0] Yes UART2 Transmission _UART2_TX_VECTOR 57 IFS1[25] IEC1[25] IPC14[12:10] IPC14[9:8] Yes Interrupt Source UART2 Error UART3 Reception UART3 Transmission Priority Subpriority Persistent Interrupt _UART2_ERR_VECTOR 58 IFS1[26] IEC1[26] IPC14[20:18] IPC14[17:16] Yes _UART3_RX_VECTOR 59 IFS1[27] IEC1[27] IPC14[28:26] IPC14[25:24] Yes _UART3_TX_VECTOR 60 IFS1[28] IEC1[28] IPC15[4:2] IPC15[1:0] Yes _UART3_ERR_VECTOR 61 IFS1[29] IEC1[29] IPC15[12:10] IPC15[9:8] Yes RESERVED 62 IFS1[30] IEC1[30] IPC15[20:18] IPC15[17:16] No RESERVED 63 IFS1[31] IEC1[31] IPC15[28:26] IPC15[25:24] No 64 IFS2[0] IEC2[0] IPC16[4:2] IPC16[1:0] No 65 IFS2[1] IEC2[1] IPC16[12:10] IPC16[9:8] Yes UART3 Error RESERVED I2C1 Slave _I2C1_SLAVE_VECTOR I2C1 Master _I2C1_MASTER_VECTOR 66 IFS2[2] IEC2[2] IPC16[20:18] IPC16[17:16] Yes _I2C1_BUS_VECTOR 67 IFS2[3] IEC2[3] IPC16[28:26] IPC16[25:24] Yes I2C2 Slave _I2C2_SLAVE_VECTOR 68 IFS2[4] IEC2[4] IPC17[4:2] IPC17[1:0] Yes I2C2 Master _I2C2_MASTER_VECTOR 69 IFS2[5] IEC2[5] IPC17[12:10] IPC17[9:8] Yes I2C1 Bus Collision I2C2 Bus Collision _I2C2_BUS_VECTOR 70 IFS2[6] IEC2[6] IPC17[20:18] IPC17[17:16] Yes I2C3 Slave _I2C3_SLAVE_VECTOR 71 IFS2[7] IEC2[7] IPC17[28:26] IPC17[25:24] Yes I2C3 Master _I2C3_MASTER_VECTOR 72 IFS2[8] IEC2[8] IPC18[4:2] IPC18[1:0] Yes _I2C3_BUS_VECTOR 73 IFS2[9] IEC2[9] IPC18[12:10] IPC18[9:8] Yes CCP1 Input Capture or Output Compare _CCP1_VECTOR 74 IFS2[10] IEC2[10] IPC18[20:18] IPC18[17:16] No CCP1 Timer _CCT1_VECTOR 75 IFS2[11] IEC2[11] IPC18[28:26] IPC18[25:24] No CCP2 Input Capture or Output Compare _CCP2_VECTOR 76 IFS2[12] IEC2[12] IPC19[4:2] IPC19[1:0] No CCP2 Timer _CCT2_VECTOR 77 IFS2[13] IEC2[13] IPC19[12:10] IPC19[9:8] No CCP3 Input Capture or Output Compare _CCP3_VECTOR 78 IFS2[14] IEC2[14] IPC19[20:18] IPC19[17:16] No CCP3 Timer _CCT3_VECTOR 79 IFS2[15] IEC2[15] IPC19[28:26] IPC19[25:24] No CCP4 Input Capture or Output Compare _CCP4_VECTOR 80 IFS2[16] IEC2[16] IPC20[4:2] IPC20[1:0] No CCP4 Timer _CCT4_VECTOR 81 IFS2[17] IEC2[17] IPC20[12:10] IPC20[9:8] No CCP5 Input Capture or Output Compare _CCP5_VECTOR 82 IFS2[18] IEC2[18] IPC20[20:18] IPC20[17:16] No CCP5 Timer _CCT5_VECTOR 83 IFS2[19] IEC2[19] IPC20[28:26] IPC20[25:24] No CCP6 Input Capture or Output Compare _CCP6_VECTOR 84 IFS2[20] IEC2[20] IPC21[4:2] IPC21[1:0] No CCP6 Timer _CCT6_VECTOR 85 IFS2[21] IEC2[21] IPC21[12:10] IPC21[9:8] No CCP7 Input Capture or Output Compare _CCP7_VECTOR 86 IFS2[22] IEC2[22] IPC21[20:18] IPC21[17:16] No CCP7 Timer _CCT7_VECTOR 87 IFS2[23] IEC2[23] IPC21[28:26] IPC21[25:24] No I2C3 Bus Collision PIC32MM0256GPM064 FAMILY DS60001387D-page 64 TABLE 7-2:  2016-2019 Microchip Technology Inc.  2016-2019 Microchip Technology Inc. TABLE 7-2: INTERRUPTS (CONTINUED) Interrupt Related Bits Location Interrupt Source MPLAB® XC32 Vector Name Vector Number Flag Enable Priority Subpriority Persistent Interrupt CCP8 Input Capture or Output Compare _CCP8_VECTOR 88 IFS2[24] IEC2[24] IPC22[4:2] IPC22[1:0] No _CCT8_VECTOR 89 IFS2[25] IEC2[25] IPC22[12:10] IPC22[9:8] No CCP9 Input Capture or Output Compare _CCP9_VECTOR 90 IFS2[26] IEC2[26] IPC22[20:18] IPC22[17:16] No CCP9 Timer _CCT9_VECTOR 91 IFS2[27] IEC2[27] IPC22[28:26] IPC22[25:24] No _FRC_TUNE 92 IFS2[28] IEC2[28] IPC23[4:2] IPC23[1:0] No _NVM_VECTOR 94 IFS2[30] IEC2[30] IPC23[20:18] IPC23[17:16] Yes _PERFORMANCE_COUNTER_VECTOR 95 IFS2[31] IEC2[31] IPC23[28:26] IPC23[25:24] No 96 IFS3[0] IEC3[0] IPC24[4:2] IPC24[1:0] No _ECCSB_ERR_VECTOR 97 IFS3[1] IEC3[1] IPC24[12:10] IPC24[9:8] No DMA Channel 0 _DMA0_VECTOR 98 IFS3[2] IEC3[2] IPC24[20:18] IPC24[17:16] No DMA Channel 1 _DMA1_VECTOR 99 IFS3[3] IEC3[3] IPC24[28:26] IPC24[25:24] No DMA Channel 2 _DMA2_VECTOR 100 IFS3[4] IEC3[4] IPC25[4:2] IPC25[1:0] No DMA Channel 3 _DMA3_VECTOR 101 IFS3[5] IEC3[5] IPC25[12:10] IPC25[9:8] No FRC Auto-Tune NVM Program or Erase Complete Core Performance Counter RESERVED Single-Bit ECC Error DS60001387D-page 65 PIC32MM0256GPM064 FAMILY CCP8 Timer Register Name(1) INTCON F010 F020 PRISS INTSTAT F030 F040 F050 F060 F070 F080 F090 F0A0  2016-2019 Microchip Technology Inc. F0B0 F0C0 F0D0 F0E0 F0F0 Legend: Note 1: IPTMR IFS0 IFS1 IFS2 IFS3 IEC0 IEC1 IEC2 IEC3 IPC0 IPC1 IPC2 IPC3 Bit Range Bits 31/15 30/14 29/13 31:16 — — 15:0 — — 28/12 27/11 26/10 — — — — — MVEC — 25/9 24/8 23/7 — — — TPC[2:0] — 22/6 21/5 20/4 — — INT4EP PRI7SS[3:0] PRI6SS[3:0] PRI5SS[3:0] 15:0 PRI3SS[3:0] PRI2SS[3:0] PRI1SS[3:0] — — — — — 15:0 — — — — — — — — — — — SRIPL[2:0] 31:16 18/2 17/1 16/0 INT2EP INT1EP INT0EP VS[6:0] 31:16 31:16 19/3 INT3EP 0000 PRI4SS[3:0] — 0000 0000 — — — SS0 0000 — — — — 0000 SIRQ[7:0] 0000 0000 IPTMR[31:0] 15:0 All Resets Virtual Address (BF80_#) F000 INTERRUPT REGISTER MAP 0000 31:16 — USBIF — — — — CMP3IF CMP2IF CMP1IF — — — T3IF T2IF T1IF — 0000 15:0 — — — — CNDIF CNCIF CNBIF CNAIF INT4IF INT3IF INT2IF INT1IF INT0IF CS1IF CS0IF CTIF 0000 31:16 — — U3EIF U3TXIF U3RXIF U2EIF U2TXIF U2RXIF U1EIF U1TXIF U1RXIF — — — SPI3RXIF SPI3TXIF 0000 15:0 SPI3EIF SPI2EIF SPI1RXIF SPI1TXIF SPI1EIF CLC4IF CLC3IF CLC2IF CLC1IF LVDIF — — AD1IF RTCCIF 0000 31:16 CPCIF NVMIF — FSTIF CCT9IF CCP9IF CCT8IF CCP8IF CCT7IF CCP7IF CCT6IF CCP6IF CCT5IF CCP5IF CCT4IF CCP4IF 0000 15:0 CCT3IF CCP3IF CCT2IF CCP2IF CCT1IF CCP1IF I2C3BCIF I2C3MIF I2C3SIF I2C2BCIF I2C2MIF I2C2SIF I2C1BCIF I2C1MIF I2C1SIF — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — DMA3IF DMA2IF DMA1IF DMA0IF ECCBEIF — 0000 31:16 — USBIE — — — — CMP3IE CMP2IE CMP1IE — — — T3IE T2IE T1IE — 0000 15:0 — — — — CNDIE CNCIE CNBIE CNAIE INT4IE INT3IE INT2IE INT1IE INT0IE CS1IE CS0IE CTIE 0000 31:16 — — U3EIE U3TXIE U3RXIE U2EIE U2TXIE U2RXIE U1EIE U1TXIE U1RXIE — — — SPI2RXIF SPI2TXIF SPI2RXIE SPI2TXIE SPI3RXIE SPI3TXIE 0000 15:0 SPI3EIE SPI2EIE SPI1RXIE SPI1TXIE SPI1EIE CLC4IE CLC3IE CLC2IE CLC1IE LVDIE — — AD1IE RTCCIE 0000 31:16 CPCIE NVMIE — FSTIE CCT9IE CCP9IE CCT8IE CCP8IE CCT7IE CCP7IE CCT6IE CCP6IE CCT5IE CCP5IE CCT4IE CCP4IE 0000 15:0 CCT3IE CCP3IE CCT2IE CCP2IE CCT1IE CCP1IE I2C3BCIE I2C3MIE I2C3SIE I2C2BCIE I2C2MIE I2C2SIE I2C1BCIE I2C1MIE I2C1SIE — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — DMA3IE DMA2IE DMA1IE DMA0IE ECCBEIE — 0000 31:16 — — — INT0IP[2:0] INT0IS[1:0] — — — CS1IP[2:0] CS1IS[1:0] 0000 15:0 — — — CS0IP[2:0] CS0IS[1:0] — — — CTIP[2:0] CTIS[1:0] 0000 31:16 — — — INT4IP[2:0] INT4IS[1:0] — — — INT3IP[2:0] INT3IS[1:0] 0000 15:0 — — — INT2IP[2:0] INT2IS[1:0] — — — INT1IP[2:0] INT1IS[1:0] 0000 31:16 — — — CNDIP[2:0] CNDIS[1:0] — — — CNCIP[2:0] CNCIS[1:0] 0000 15:0 — — — CNBIP[2:0] CNBIS[1:0] — — — CNAIP[2:0] CNAIS[1:0] 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — — — — — 0000 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. PIC32MM0256GPM064 FAMILY DS60001387D-page 66 TABLE 7-3: Register Name(1) F100 IPC4 F120 F130 F140 F160 F170 F180 F190 F1A0 F1B0 F1C0 F1D0 DS60001387D-page 67 F1E0 F1F0 Legend: Note 1: IPC5 IPC6 IPC7 IPC8 IPC9 IPC10 IPC11 IPC12 IPC13 IPC14 IPC15 IPC16 IPC17 IPC18 IPC19 31/15 30/14 29/13 31:16 — — — T3IP[2:0] 15:0 — — — T1IP[2:0] 31:16 — — — CMP1IP[2:0] 15:0 — — — — — — — 31:16 — — — — — — — 15:0 — — — 31:16 — — — 15:0 — — — 31:16 — — — 15:0 — — — AD1IP[2:0] 31:16 — — — 15:0 — — 31:16 — 15:0 28/12 27/11 26/10 18/2 17/1 — — — — 0000 — — — — — 0000 — — — — — — 0000 — — — — — — — 0000 — — — — — — — — — — — — — — — — AD1IS[1:0] — — — RTCCIP[2:0] RTCCIS[1:0] 0000 CLC3IP[2:0] CLC3IS[1:0] — — — CLC2IP[2:0] CLC2IS[1:0] 0000 — CLC1IP[2:0] CLC1IS[1:0] — — — LVDIP[2:0] LVDIS[1:0] 0000 — — SPI1RXIP[2:0] SPI1RXIS[1:0] — — — SPI1TXIP[2:0] SPI1TXIS[1:0] 0000 — — — SPI1EIP[2:0] SPI1EIS[1:0] — — — CLC4IP[2:0] CLC4IS[1:0] 0000 31:16 — — — SPI3EIP[2:0] SPI3EIS[1:0] — — — SPI2RXIP[2:0] SPI2RXIS[1:0] 0000 15:0 — — — SPI2TXIP[2:0] SPI2TXIS[1:0] — — — SPI2EIP[2:0] SPI2EIS[1:0] 0000 31:16 — — — — — — — — — — 0000 15:0 — — — SPI3RXIP[2:0] SPI3RXIS[1:0] — — — SPI3TXIP[2:0] SPI3TXIS[1:0] 0000 31:16 — — — U1EIP[2:0] U1EIS[1:0] — — — U1TXIP[2:0] U1TXIS[1:0] 0000 15:0 — — — U1RXIP[2:0] U1RXIS[1:0] — — — 31:16 — — — U3RXIP[2:0] U3RXIS[1:0] — — — U2EIP[2:0] U2EIS[1:0] 0000 15:0 — — — U2TXIP[2:0] U2TXIS[1:0] — — — U2RXIP[2:0] U2RXIS[1:0] 0000 31:16 — — — — — — 15:0 — — — U3EIP[2:0] U3EIS[1:0] — — — U3TXIP[2:0] U3TXIS[1:0] 0000 31:16 — — — I2C1BCIP[2:0] I2C1BCIS[1:0] — — — I2C1MIP[2:0] I2C1MIS[1:0] 0000 15:0 — — — I2C1SIP[2:0] I2C1SIS[1:0] — — — — — 0000 31:16 — — — I2C3SIP[2:0] I2C3SIS[1:0] — — — I2C2BCIP[2:0] I2C2BCIS[1:0] 0000 15:0 — — — I2C2MIP[2:0] I2C2MIS[1:0] — — — I2C2SIP[2:0] I2C2SIS[1:0] 0000 31:16 — — — CCT1IP[2:0] CCT1IS[1:0] — — — CCP1IP[2:0] CCP1IS[1:0] 0000 15:0 — — — I2C3BCIP[2:0] I2C3BCIS[1:0] — — — I2C3MIP[2:0] I2C3MIS[1:0] 0000 31:16 — — — CCT3IP[2:0] CCT3IS[1:0] — — — CCP3IP[2:0] CCP3IS[1:0] 0000 15:0 — — — CCT2IP[2:0] CCT2IS[1:0] — — — CCP2IP[2:0] CCP2IS[1:0] 0000 CMP3IP[2:0] — — — — — — — 24/8 23/7 22/6 21/5 T3IS[1:0] — — — T1IS[1:0] — — — — CMP1IS[1:0] — — — — — — — — CMP3IS[1:0] — USBIP[2:0] — 25/9 — — USBIS[1:0] — — — — — — — — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. 20/4 19/3 T2IP[2:0] T2IS[1:0] CMP2IP[2:0] — — — — 16/0 0000 CMP2IS[1:0] 0000 — — — 0000 — — — — 0000 — — — — 0000 — — — — — — — — — — — — 0000 0000 PIC32MM0256GPM064 FAMILY F150 Bits Bit Range F110 INTERRUPT REGISTER MAP (CONTINUED) All Resets Virtual Address (BF80_#)  2016-2019 Microchip Technology Inc. TABLE 7-3: Register Name(1) IPC20 F220 F230 F240 F250 Legend: Note 1: IPC21 IPC22 IPC23 IPC24 IPC25 Bit Range F210 Bits 31/15 30/14 29/13 31:16 — — — CCT5IP[2:0] 15:0 — — — CCT4IP[2:0] 31:16 — — — 15:0 — — 31:16 — 15:0 28/12 23/7 22/6 21/5 CCT5IS[1:0] — — — CCP5IP[2:0] CCP5IS[1:0] 0000 CCT4IS[1:0] — — — CCP4IP[2:0] CCP4IS[1:0] 0000 CCT7IP[2:0] CCT7IS[1:0] — — — CCP7IP[2:0] CCP7IS[1:0] 0000 — CCT6IP[2:0] CCT6IS[1:0] — — — CCP6IP[2:0] CCP6IS[1:0] 0000 — — CCT9IP[2:0] CCT9IS[1:0] — — — CCP9IP[2:0] CCP9IS[1:0] 0000 — — — CCT8IP[2:0] CCT8IS[1:0] — — — CCP8IP[2:0] CCP8IS[1:0] 0000 31:16 — — — CPCIP[2:0] CPCIS[1:0] — — — NVMIP[2:0] NVMIS[1:0] 0000 15:0 — — — — — — FSTIP[2:0] FSTIS[1:0] 0000 31:16 — — — DMA1IP[2:0] DMA1IS[1:0] — — — DMA0IP[2:0] DMA0IS[1:0] 0000 15:0 — — — ECCBEIP[2:0] ECCBEIS[1:0] — — — — — — — — 0000 31:16 — — — — — — — — — — — — 0000 15:0 — — — — — — — — 27/11 — — DMA3IP[2:0] 26/10 — — 25/9 — 24/8 — — DMA3IS[1:0] — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. 20/4 19/3 DMA2IP[2:0] 18/2 17/1 16/0 All Resets Virtual Address (BF80_#) F200 INTERRUPT REGISTER MAP (CONTINUED) DMA2IS[1:0] 0000 PIC32MM0256GPM064 FAMILY DS60001387D-page 68 TABLE 7-3:  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 7-1: Bit Range 31:24 23:16 15:8 7:0 INTCON: INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 — — — MVEC — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP — Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VS[6:0] R/W-0 TPC[2:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-23 Unimplemented: Read as ‘0’ bit 22-16 VS[6:0]: Vector Spacing bits Spacing Between Vectors: 0000000 = 0 Bytes 0000001 = 8 Bytes 0000010 = 16 Bytes 0000100 = 32 Bytes 0001000 = 64 Bytes 0010000 = 128 Bytes 0100000 = 256 Bytes 1000000 = 512 Bytes All other values are reserved. The operation of this device is undefined if a reserved value is written to this field. If MVEC = 0, this field is ignored. bit 15-13 Unimplemented: Read as ‘0’ bit 12 MVEC: Multivector Configuration bit 1 = Interrupt controller is configured for Multivectored mode 0 = Interrupt controller is configured for Single Vectored mode bit 11 Unimplemented: Read as ‘0’ bit 10-8 TPC[2:0]: Interrupt Proximity Timer Control bits 111 = Interrupts of Group Priority 7 or lower start the interrupt proximity timer 110 = Interrupts of Group Priority 6 or lower start the interrupt proximity timer 101 = Interrupts of Group Priority 5 or lower start the interrupt proximity timer 100 = Interrupts of Group Priority 4 or lower start the interrupt proximity timer 011 = Interrupts of Group Priority 3 or lower start the interrupt proximity timer 010 = Interrupts of Group Priority 2 or lower start the interrupt proximity timer 001 = Interrupts of Group Priority 1 start the interrupt proximity timer 000 = Disables interrupt proximity timer bit 7-5 Unimplemented: Read as ‘0’ bit 4 INT4EP: External Interrupt 4 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 3 INT3EP: External Interrupt 3 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge  2016-2019 Microchip Technology Inc. DS60001387D-page 69 PIC32MM0256GPM064 FAMILY REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER (CONTINUED) bit 2 INT2EP: External Interrupt 2 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 1 INT1EP: External Interrupt 1 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 0 INT0EP: External Interrupt 0 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge REGISTER 7-2: Bit Range 31:24 23:16 15:8 7:0 PRISS: PRIORITY SHADOW SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 R/W-0 (1) R/W-0 R/W-0 R/W-0 R/W-0 (1) R/W-0 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRI7SS[3:0] PRI6SS[3:0] PRI4SS[3:0](1) PRI5SS[3:0] R/W-0 R/W-0 R/W-0 R/W-0 PRI3SS[3:0](1) R/W-0 R/W-0 R/W-0 PRI1SS[3:0](1) R/W-0 R/W-0 PRI2SS[3:0](1) R/W-0 U-0 U-0 U-0 R/W-0 — — — SS0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 PRI7SS[3:0]: Interrupt with Priority Level 7 Shadow Set bits(1) 1111 = Reserved • • • 0010 = Reserved 0001 = Interrupt with a priority level of 7 uses Shadow Set 1 0000 = Interrupt with a priority level of 7 uses Shadow Set 0 bit 27-24 PRI6SS[3:0]: Interrupt with Priority Level 6 Shadow Set bits(1) 1111 = Reserved • • • 0010 = Reserved 0001 = Interrupt with a priority level of 6 uses Shadow Set 1 0000 = Interrupt with a priority level of 6 uses Shadow Set 0 Note 1: These bits are ignored if the MVEC bit (INTCON[12]) = 0. DS60001387D-page 70  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 7-2: PRISS: PRIORITY SHADOW SELECT REGISTER (CONTINUED) bit 23-20 PRI5SS[3:0]: Interrupt with Priority Level 5 Shadow Set bits(1) 1111 = Reserved • • • 0010 = Reserved 0001 = Interrupt with a priority level of 5 uses Shadow Set 1 0000 = Interrupt with a priority level of 5 uses Shadow Set 0 bit 19-16 PRI4SS[3:0]: Interrupt with Priority Level 4 Shadow Set bits(1) 1111 = Reserved • • • 0010 = Reserved 0001 = Interrupt with a priority level of 4 uses Shadow Set 1 0000 = Interrupt with a priority level of 4 uses Shadow Set 0 bit 15-12 PRI3SS[3:0]: Interrupt with Priority Level 3 Shadow Set bits(1) 1111 = Reserved • • • 0010 = Reserved 0001 = Interrupt with a priority level of 3 uses Shadow Set 1 0000 = Interrupt with a priority level of 3 uses Shadow Set 0 bit 11-8 PRI2SS[3:0]: Interrupt with Priority Level 2 Shadow Set bits(1) 1111 = Reserved • • • 0010 = Reserved 0001 = Interrupt with a priority level of 2 uses Shadow Set 1 0000 = Interrupt with a priority level of 2 uses Shadow Set 0 bit 7-4 PRI1SS[3:0]: Interrupt with Priority Level 1 Shadow Set bits(1) 1111 = Reserved • • • 0010 = Reserved 0001 = Interrupt with a priority level of 1 uses Shadow Set 1 0000 = Interrupt with a priority level of 1 uses Shadow Set 0 bit 3-1 Unimplemented: Read as ‘0’ bit 0 SS0: Single Vector Shadow Register Set bit 1 = Single vector is presented with a shadow set 0 = Single vector is not presented with a shadow set Note 1: These bits are ignored if the MVEC bit (INTCON[12]) = 0.  2016-2019 Microchip Technology Inc. DS60001387D-page 71 PIC32MM0256GPM064 FAMILY REGISTER 7-3: Bit Range 31:24 23:16 15:8 7:0 INTSTAT: INTERRUPT STATUS REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC (1) R-0, HS, HC R-0, HS, HC R-0, HS, HC — — — — — R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC SRIPL[2:0] R-0, HS, HC SIRQ[7:0] Legend: HS = Hardware Settable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-11 Unimplemented: Read as ‘0’ bit 10-8 SRIPL[2:0]: Requested Priority Level for Single Vector Mode bits(1) 111-000 = The priority level of the latest interrupt presented to the CPU bit 7-0 SIRQ[7:0]: Last Interrupt Request Serviced Status bits 11111111-00000000 = The last interrupt request number serviced by the CPU Note 1: This value should only be used when the interrupt controller is configured for Single Vector mode. REGISTER 7-4: Bit Range 31:24 23:16 15:8 7:0 IPTMR: INTERRUPT PROXIMITY TIMER REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IPTMR[31:24] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IPTMR[23:16] R/W-0 IPTMR[15:8] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IPTMR[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 x = Bit is unknown IPTMR[31:0]: Interrupt Proximity Timer Reload bits Used by the interrupt proximity timer as a reload value when the interrupt proximity timer is triggered by an interrupt event. DS60001387D-page 72  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 7-5: Bit Range 31:24 23:16 15:8 7:0 IFSx: INTERRUPT FLAG STATUS REGISTER x Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS[31:24] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS[23:16] R/W-0 IFS[15:8] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 Note: IFS[31:0]: Interrupt Flag Status bits 1 = Interrupt request has occurred 0 = No interrupt request has occurred This register represents a generic definition of the IFSx register. Refer to Table 7-3 for the exact bit definitions. REGISTER 7-6: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown IECx: INTERRUPT ENABLE CONTROL REGISTER x Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC[31:24] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC[23:16] R/W-0 IEC[15:8] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 Note: x = Bit is unknown IEC[31-0]: Interrupt Enable bits 1 = Interrupt is enabled 0 = Interrupt is disabled This register represents a generic definition of the IECx register. Refer to Table 7-3 for the exact bit definitions.  2016-2019 Microchip Technology Inc. DS60001387D-page 73 PIC32MM0256GPM064 FAMILY REGISTER 7-7: Bit Range 31:24 23:16 15:8 7:0 IPCx: INTERRUPT PRIORITY CONTROL REGISTER x Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 IP3[2:0] R/W-0 R/W-0 IS3[1:0] R/W-0 R/W-0 R/W-0 R/W-0 IP2[2:0] R/W-0 R/W-0 IS2[1:0] IP1[2:0] R/W-0 R/W-0 R/W-0 R/W-0 IS1[1:0] R/W-0 R/W-0 IP0[2:0] R/W-0 IS0[1:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28-26 IP3[2:0]: Interrupt Priority 3 bits 111 = Interrupt priority is 7 • • • 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 25-24 IS3[1:0]: Interrupt Subpriority 3 bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 23-21 Unimplemented: Read as ‘0’ bit 20-18 IP2[2:0]: Interrupt Priority 2 bits 111 = Interrupt priority is 7 • • • 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 17-16 IS2[1:0]: Interrupt Subpriority 2 bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 15-13 Unimplemented: Read as ‘0’ Note: This register represents a generic definition of the IPCx register. Refer to Table 7-3 for the exact bit definitions. DS60001387D-page 74  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 7-7: IPCx: INTERRUPT PRIORITY CONTROL REGISTER x (CONTINUED) bit 12-10 IP1[2:0]: Interrupt Priority 1 bits 111 = Interrupt priority is 7 • • • 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 9-8 IS1[1:0]: Interrupt Subpriority 1 bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-2 IP0[2:0]: Interrupt Priority 0 bits 111 = Interrupt priority is 7 • • • 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 1-0 IS0[1:0]: Interrupt Subpriority 0 bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Note: This register represents a generic definition of the IPCx register. Refer to Table 7-3 for the exact bit definitions.  2016-2019 Microchip Technology Inc. DS60001387D-page 75 PIC32MM0256GPM064 FAMILY NOTES: DS60001387D-page 76  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 8.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER Note 1: This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. “DMA Controller” (www.microchip.com/DS60001117) in the “PIC32 Family Reference Manual”. The Direct Memory Access (DMA) Controller is a bus master module useful for data transfers between peripherals and memory without CPU intervention. The source and destination of a DMA transfer can be any of the memory-mapped modules, that do not have a dedicated DMA, existent in the PIC32 (such as SPI, UART, PMP, etc.) or the memory itself. The following are some of the key features of the DMA Controller module: • Four Identical Channels, Each Featuring: - Auto-Increment Source and Destination Address registers - Source and Destination Pointers - Memory to memory and memory to peripheral transfers • Automatic Word Size Detection: - Transfer granularity, down to byte level - Bytes need not be word-aligned at source and destination • Fixed Priority Channel Arbitration FIGURE 8-1: • Flexible DMA Channel Operating modes: - Manual (software) or automatic (interrupt) DMA requests - One-Shot or Auto-Repeat Block Transfer modes - Channel-to-channel chaining • Flexible DMA Requests: - A DMA request can be selected from any of the peripheral interrupt sources - Each channel can select any (appropriate) observable interrupt as its DMA request source - A DMA transfer abort can be selected from any of the peripheral interrupt sources - Pattern (data) match transfer termination • Multiple DMA Channel Status Interrupts: - DMA channel block transfer complete - Source empty or half empty - Destination full or half full - DMA transfer aborted due to an external event - Invalid DMA address generated • DMA Debug Support Features: - Most recent address accessed by a DMA channel - Most recent DMA channel to transfer data • CRC Generation module: - CRC module can be assigned to any of the available channels - CRC module is highly configurable • User Selectable Bus Arbitration Priority (refer to Section 4.2 “Bus Matrix (BMX)”) • Eight System Clocks Per Cell Transfer DMA BLOCK DIAGRAM INT Controller Peripheral Bus System IRQ Address Decoder Channel 0 Control I0 Channel 1 Control I1 SE L Y Bus Matrix I2 Global Control (DMACON) Channel 3 Control I3 L SE Channel Priority Arbitration BMXARB[1:0]  2016-2019 Microchip Technology Inc. DS60001387D-page 77 DMA Control Registers Virtual Address (BF88_#) Register Name(1) TABLE 8-1: 8900 DMACON 8910 DMA CONTROLLER REGISTER MAP DMASTAT 8920 DMAADDR 8930 DCRCCON 8940 DCRCDATA 8950 DCRCXOR 31/15 30/14 29/13 31:16 — — — 15:0 ON — — 31:16 — — — — 15:0 — — — — 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 — — — — — — — — — — — — — — — — — — — — RDWR SUSPEND DMABUSY 31:16 DMACH[2:0] — — 15:0 — — BYTO[1:0] — WBO — PLEN[4:0] 31:16 15:0 31:16 15:0 — BITO — CRCEN DCRCDATA[31:0] DCRCXOR[31:0] 0000 0000 0000 DMAADDR[31:0] 15:0 31:16 All Resets Bit Range Bits 0000 — — CRCAPP CRCTYP — — — — — — CRCCH[2:0] — 0000 0000 0000 0000 0000 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 10.1 “CLR, SET and INV Registers” for more information. PIC32MM0256GPM064 FAMILY DS60001387D-page 78 8.1  2016-2019 Microchip Technology Inc. Virtual Address (BF88_#) Register Name(1) 8960 DCH0CON DCH0INT DCH0SSA 89A0 DCH0DSA 89B0 89C0 DCH0SSIZ DCH0DSIZ 89D0 DCH0SPTR 89E0 DCH0DPTR 89F0 DCH0CSIZ 8A00 DCH0CPTR 8A10 8A20 DCH0DAT DCH1CON DS60001387D-page 79 8A30 DCH1ECON 8A40 DCH1INT 30/14 29/13 28/12 27/11 26/10 25/9 31:16 — — — — — — — — — — 15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED 31:16 — — — — — — — — PATEN SIRQEN AIRQEN — — 15:0 24/8 CHSIRQ[7:0] 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — CHCHN CHAEN — — — — — CHEDET CHPRI[1:0] CHAIRQ[7:0] CFORCE CABORT 0000 0000 00FF — FF00 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 31:16 — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — — 0000 — — 0000 — 0000 — 0000 CHSPTR[15:0] — — — — — — — — — — — — — — — — — — — — — — — — — — 0000 CHCSIZ[15:0] 15:0 — 0000 CHCPTR[15:0] 31:16 — — — — — — — — 0000 15:0 — — — — — — — — 31:16 — — — — — — — — — — — — — — 15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET 31:16 — — — — — — — — 15:0 CHSIRQ[7:0] 0000 0000 CHDPTR[15:0] 15:0 31:16 — CHDSIZ[15:0] 15:0 31:16 — — 15:0 31:16 0000 CHSSIZ[15:0] 15:0 31:16 0000 CHDSA[31:0] 15:0 31:16 0000 CHSSA[31:0] 15:0 CHPDAT[7:0] 0000 CHPRI[1:0] CHAIRQ[7:0] CFORCE CABORT 0000 00FF PATEN SIRQEN AIRQEN — — — FF00 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 10.1 “CLR, SET and INV Registers” for more information. PIC32MM0256GPM064 FAMILY 8990 31/15 All Resets Bits 8970 DCH0ECON 8980 DMA CHANNELS 0-3 REGISTER MAP Bit Range  2016-2019 Microchip Technology Inc. TABLE 8-2: Virtual Address (BF88_#) Register Name(1) 8A50 DCH1SSA 8A60 8A70 8A80 DCH1DSA DCH1SSIZ DCH1DSIZ 8AA0 DCH1DPTR DCH1CSIZ 8AC0 DCH1CPTR 8AD0 8AE0 DCH1DAT DCH2CON  2016-2019 Microchip Technology Inc. 8AF0 DCH2ECON 8B00 8B10 8B20 8B30 DCH2INT DCH2SSA DCH2DSA DCH2SSIZ 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 31:16 — — — — — — — 15:0 — — — — — — — — — — — — — — — 19/3 18/2 17/1 16/0 0000 0000 0000 — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — — 0000 — — 0000 — 0000 — 0000 CHSPTR[15:0] — — — — — — — — — — — — — — — — — — — — — — — — — — 0000 CHCSIZ[15:0] 15:0 — 0000 CHCPTR[15:0] 31:16 — — — — — — — — 0000 15:0 — — — — — — — — 31:16 — — — — — — — — — — — — — — 15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET 31:16 — — — — — — — — 15:0 CHSIRQ[7:0] 0000 0000 CHDPTR[15:0] 15:0 31:16 20/4 CHDSIZ[15:0] 15:0 31:16 — — 15:0 31:16 21/5 CHSSIZ[15:0] 15:0 31:16 22/6 CHDSA[31:0] 15:0 31:16 23/7 CHSSA[31:0] 15:0 31:16 24/8 All Resets Bit Range Bits 8A90 DCH1SPTR 8AB0 DMA CHANNELS 0-3 REGISTER MAP (CONTINUED) CHPDAT[7:0] 0000 CHPRI[1:0] CHAIRQ[7:0] CFORCE CABORT 0000 00FF PATEN SIRQEN AIRQEN — — — FF00 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 31:16 0000 0000 CHDSA[31:0] 15:0 31:16 0000 CHSSA[31:0] 15:0 — — — — — 15:0 — — — — CHSSIZ[15:0] 0000 — — — — — — — 0000 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 10.1 “CLR, SET and INV Registers” for more information. PIC32MM0256GPM064 FAMILY DS60001387D-page 80 TABLE 8-2: Virtual Address (BF88_#) Register Name(1) 8B40 DCH2DSIZ 8B60 DCH2DPTR DCH2CSIZ 8B90 8BA0 DCH2DAT DCH3CON 8BB0 DCH3ECON 8BC0 DCH3INT 8BD0 DCH3SSA 8BE0 DCH3DSA 8BF0 8C00 DCH3SSIZ DCH3DSIZ DS60001387D-page 81 8C10 DCH3SPTR 8C20 DCH3DPTR 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — — 0000 — — 0000 15:0 31:16 CHDSIZ[15:0] — — — — — — — 15:0 31:16 — — — — — — — 0000 — — — — — — — — — — — — — — — — — — — 0000 CHCSIZ[15:0] 15:0 — 0000 CHCPTR[15:0] 31:16 — — — — — — — — 0000 15:0 — — — — — — — — 31:16 — — — — — — — — — — — — — — 15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET 31:16 — — — — — — — — 15:0 CHSIRQ[7:0] 0000 0000 CHDPTR[15:0] 15:0 31:16 — CHSPTR[15:0] 15:0 31:16 — 0000 CHPDAT[7:0] 0000 CHPRI[1:0] CHAIRQ[7:0] CFORCE CABORT 0000 00FF PATEN SIRQEN AIRQEN — — — FF00 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 31:16 — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — — 0000 — — — — — — — — — — — — — — 0000 CHDSIZ[15:0] 15:0 31:16 0000 CHSSIZ[15:0] 15:0 31:16 0000 CHDSA[31:0] 15:0 31:16 0000 CHSSA[31:0] 15:0 — 0000 CHSPTR[15:0] — — — — — 15:0 — — — — CHDPTR[15:0] 0000 0000 0000 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 10.1 “CLR, SET and INV Registers” for more information. PIC32MM0256GPM064 FAMILY 8B80 DCH2CPTR 31:16 All Resets Bits 8B50 DCH2SPTR 8B70 DMA CHANNELS 0-3 REGISTER MAP (CONTINUED) Bit Range  2016-2019 Microchip Technology Inc. TABLE 8-2: Virtual Address (BF88_#) Register Name(1) 8C30 DCH3CSIZ DCH3DAT 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 15:0 31:16 All Resets Bit Range Bits 8C40 DCH3CPTR 8C50 DMA CHANNELS 0-3 REGISTER MAP (CONTINUED) CHCSIZ[15:0] — — — — — — — 15:0 — — 0000 CHCPTR[15:0] 31:16 — — — — — — — — 15:0 — — — — — — — — — 0000 0000 CHPDAT[7:0] 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 10.1 “CLR, SET and INV Registers” for more information. PIC32MM0256GPM064 FAMILY DS60001387D-page 82 TABLE 8-2:  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 8-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 DMACON: DMA CONTROLLER CONTROL REGISTER Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 (1) U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 — — SUSPEND DMABUSY — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — ON Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: DMA On bit(1) 1 = DMA module is enabled 0 = DMA module is disabled bit 14-13 Unimplemented: Read as ‘0’ bit 12 SUSPEND: DMA Suspend bit 1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus 0 = DMA operates normally bit 11 DMABUSY: DMA Module Busy bit 1 = DMA module is active 0 = DMA module is disabled and not actively transferring data bit 10-0 Unimplemented: Read as ‘0’ Note 1: The user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.  2016-2019 Microchip Technology Inc. DS60001387D-page 83 PIC32MM0256GPM064 FAMILY REGISTER 8-2: Bit Range 31:24 23:16 15:8 7:0 DMASTAT: DMA STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — RDWR DMACH[2:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as ‘0’ bit 3 RDWR: DMA Read/Write Status bit 1 = Last DMA bus access was a read 0 = Last DMA bus access was a write bit 2-0 DMACH[2:0]: DMA Channel bits These bits contain the value of the most recent active DMA channel. REGISTER 8-3: Bit Range 31:24 23:16 15:8 7:0 DMAADDR: DMA ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R-0 R-0 R-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DMAADDR[31:24] R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DMAADDR[23:16] R-0 R-0 DMAADDR[15:8] R-0 R-0 R-0 R-0 R-0 DMAADDR[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 DMAADDR[31:0]: DMA Module Address bits These bits contain the address of the most recent DMA access. DS60001387D-page 84  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 8-4: Bit Range 31:24 23:16 15:8 7:0 DCRCCON: DMA CRC CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 R/W-0 R/W-0 — — U-0 U-0 BYTO[1:0] U-0 U-0 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 U-0 U-0 R/W-0 WBO(1) — — BITO U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 R/W-0 U-0 U-0 PLEN[4:0] CRCEN CRCAPP(1) CRCTYP — — R/W-0 CRCCH[2:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as ‘0’ bit 29-28 BYTO[1:0]: CRC Byte Order Selection bits 11 = Endian byte swap on half-word boundaries (source half-word order with reverse source byte order per half-word) 10 = Swap half-words on word boundaries (reverse source half-word order with source byte order per half-word) 01 = Endian byte swap on word boundaries (reverse source byte order) 00 = No swapping (source byte order) bit 27 WBO: CRC Write Byte Order Selection bit(1) 1 = Source data are written to the destination re-ordered, as defined by BYTO[1:0] 0 = Source data are written to the destination unaltered bit 26-25 Unimplemented: Read as ‘0’ bit 24 BITO: CRC Bit Order Selection bit When CRCTYP (DCRCCON[5]) = 1 (CRC module is in IP Header mode): 1 = The IP header checksum is calculated Least Significant bit (LSb) first (reflected) 0 = The IP header checksum is calculated Most Significant bit (MSb) first (not reflected) When CRCTYP (DCRCCON[5]) = 0 (CRC module is in LFSR mode): 1 = The LFSR CRC is calculated Least Significant bit first (reflected) 0 = The LFSR CRC is calculated Most Significant bit first (not reflected) bit 23-13 Unimplemented: Read as ‘0’ bit 12-8 PLEN[4:0]: Polynomial Length bits When CRCTYP (DCRCCON[5]) = 1 (CRC module is in IP Header mode): These bits are unused. When CRCTYP (DCRCCON[5]) = 0 (CRC module is in LFSR mode): Denotes the length of the polynomial – 1. bit 7 CRCEN: CRC Enable bit 1 = CRC module is enabled and channel transfers are routed through the CRC module 0 = CRC module is disabled and channel transfers proceed normally bit 6 CRCAPP: CRC Append Mode bit(1) 1 = The DMA transfers data from the source into the CRC but not to the destination; when a block transfer completes, the DMA writes the calculated CRC value to the location given by CHxDSA 0 = The DMA transfers data from the source through the CRC, obeying WBO as it writes the data to the destination Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.  2016-2019 Microchip Technology Inc. DS60001387D-page 85 PIC32MM0256GPM064 FAMILY REGISTER 8-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED) bit 5 CRCTYP: CRC Type Selection bit 1 = The CRC module will calculate an IP header checksum 0 = The CRC module will calculate an LFSR CRC bit 4-3 Unimplemented: Read as ‘0’ bit 2-0 CRCCH[2:0]: CRC Channel Select bits 111 = CRC is assigned to Channel 7 110 = CRC is assigned to Channel 6 101 = CRC is assigned to Channel 5 100 = CRC is assigned to Channel 4 011 = CRC is assigned to Channel 3 010 = CRC is assigned to Channel 2 001 = CRC is assigned to Channel 1 000 = CRC is assigned to Channel 0 Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set. DS60001387D-page 86  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 8-5: Bit Range 31:24 23:16 15:8 7:0 DCRCDATA: DMA CRC DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA[31:24] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA[23:16] R/W-0 R/W-0 DCRCDATA[15:8] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 DCRCDATA[31:0]: CRC Data Register bits Writing to this register will seed the CRC generator. Reading from this register will return the current value of the CRC. Bits greater than PLEN will return ‘0’ on any read. When CRCTYP (DCRCCON[5]) = 1 (CRC module is in IP Header mode): Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written to this register are converted and read back in ‘1’s complement form (current IP header checksum value). When CRCTYP (DCRCCON[5]) = 0 (CRC module is in LFSR mode): Bits greater than PLEN will return ‘0’ on any read. REGISTER 8-6: Bit Range 31:24 23:16 15:8 7:0 DCRCXOR: DMA CRCXOR ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR[31:24] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR[23:16] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR[15:8] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 DCRCXOR[31:0]: CRC XOR Register bits When CRCTYP (DCRCCON[5]) = 1 (CRC module is in IP Header mode): This register is unused. When CRCTYP (DCRCCON[5]) = 0 (CRC module is in LFSR mode): 1 = Enables the XOR input to the Shift register 0 = Disables the XOR input to the Shift register; data are shifted in directly from the previous stage in the register  2016-2019 Microchip Technology Inc. DS60001387D-page 87 PIC32MM0256GPM064 FAMILY REGISTER 8-7: Bit Range 31:24 23:16 15:8 7:0 DCHxCON: DMA CHANNEL x CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 CHBUSY — — — — — — CHCHNS(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 CHEN(2) CHAED CHCHN CHAEN — CHEDET R/W-0 CHPRI[1:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 CHBUSY: Channel Busy bit 1 = Channel is active or has been enabled 0 = Channel is inactive or has been disabled bit 14-9 Unimplemented: Read as ‘0’ bit 8 CHCHNS: Chain Channel Selection bit(1) 1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete) 0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete) bit 7 CHEN: Channel Enable bit(2) 1 = Channel is enabled 0 = Channel is disabled bit 6 CHAED: Channel Allow Events if Disabled bit 1 = Channel start/abort events will be registered, even if the channel is disabled 0 = Channel start/abort events will be ignored if the channel is disabled bit 5 CHCHN: Channel Chain Enable bit 1 = Allows channel to be chained 0 = Does not allow channel to be chained bit 4 CHAEN: Channel Automatic Enable bit 1 = Channel is continuously enabled and not automatically disabled after a block transfer is complete 0 = Channel is disabled on a block transfer complete bit 3 Unimplemented: Read as ‘0’ bit 2 CHEDET: Channel Event Detected bit 1 = An event has been detected 0 = No events have been detected bit 1-0 CHPRI[1:0]: Channel Priority bits 11 = Channel has Priority 3 (highest) 10 = Channel has Priority 2 01 = Channel has Priority 1 00 = Channel has Priority 0 Note 1: 2: The chain selection bit takes effect when chaining is enabled (CHCHN = 1). When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if available on the device variant) to see when the channel is suspended, as it may take some clock cycles to complete a current transaction before the channel is suspended. DS60001387D-page 88  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 8-8: Bit Range 31:24 23:16 15:8 7:0 DCHxECON: DMA CHANNEL x EVENT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 (1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CHAIRQ[7:0] CHSIRQ[7:0](1) S-0 S-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CFORCE CABORT PATEN SIRQEN AIRQEN — — — Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23-16 CHAIRQ[7:0]: Channel Transfer Abort IRQ bits(1) 11111111 = Interrupt 255 will abort any transfers in progress and sets the CHTAIF flag • • • 00000001 = Interrupt 1 will abort any transfers in progress and sets the CHTAIF flag 00000000 = Interrupt 0 will abort any transfers in progress and sets the CHTAIF flag bit 15-8 CHSIRQ[7:0]: Channel Transfer Start IRQ bits(1) 11111111 = Interrupt 255 will initiate a DMA transfer • • • 00000001 = Interrupt 1 will initiate a DMA transfer 00000000 = Interrupt 0 will initiate a DMA transfer bit 7 CFORCE: DMA Forced Transfer bit 1 = A DMA transfer is forced to begin when this bit is written to a ‘1’ 0 = This bit always reads ‘0’ bit 6 CABORT: DMA Abort Transfer bit 1 = A DMA transfer is aborted when this bit is written to a ‘1’ 0 = This bit always reads ‘0’ bit 5 PATEN: Channel Pattern Match Abort Enable bit 1 = Aborts transfer and clears CHEN on pattern match 0 = Pattern match is disabled bit 4 SIRQEN: Channel Start IRQ Enable bit 1 = Starts channel cell transfer if an interrupt matching CHSIRQx occurs 0 = Interrupt number CHSIRQx is ignored and does not start a transfer bit 3 AIRQEN: Channel Abort IRQ Enable bit 1 = Channel transfer is aborted if an interrupt matching CHAIRQx occurs 0 = Interrupt number CHAIRQx is ignored and does not terminate a transfer bit 2-0 Unimplemented: Read as ‘0’ Note 1: See Table 7-2 for the list of available interrupt IRQ sources.  2016-2019 Microchip Technology Inc. DS60001387D-page 89 PIC32MM0256GPM064 FAMILY REGISTER 8-9: Bit Range 31:24 23:16 15:8 7:0 DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23 CHSDIE: Channel Source Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 22 CHSHIE: Channel Source Half Empty Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 21 CHDDIE: Channel Destination Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 20 CHDHIE: Channel Destination Half Full Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 19 CHBCIE: Channel Block Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 18 CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 17 CHTAIE: Channel Transfer Abort Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 16 CHERIE: Channel Address Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 15-8 Unimplemented: Read as ‘0’ bit 7 CHSDIF: Channel Source Done Interrupt Flag bit 1 = Channel Source Pointer has reached end of source (CHSPTRx = CHSSIZx) 0 = No interrupt is pending bit 6 CHSHIF: Channel Source Half Empty Interrupt Flag bit 1 = Channel Source Pointer has reached midpoint of source (CHSPTRx = CHSSIZx/2) 0 = No interrupt is pending DS60001387D-page 90  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 8-9: DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER (CONTINUED) bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit 1 = Channel Destination Pointer has reached end of destination (CHDPTRx = CHDSIZx) 0 = No interrupt is pending bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit 1 = Channel Destination Pointer has reached midpoint of destination (CHDPTRx = CHDSIZx/2) 0 = No interrupt is pending bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit 1 = A block transfer has been completed (the larger of CHSSIZx/CHDSIZx bytes has been transferred) or a pattern match event occurs 0 = No interrupt is pending bit 2 CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit 1 = A cell transfer has been completed (CHCSIZx bytes have been transferred) 0 = No interrupt is pending bit 1 CHTAIF: Channel Transfer Abort Interrupt Flag bit 1 = An interrupt matching CHAIRQx has been detected and the DMA transfer has been aborted 0 = No interrupt is pending bit 0 CHERIF: Channel Address Error Interrupt Flag bit 1 = A channel address error has been detected (either the source or the destination address is invalid) 0 = No interrupt is pending  2016-2019 Microchip Technology Inc. DS60001387D-page 91 PIC32MM0256GPM064 FAMILY REGISTER 8-10: Bit Range DCHxSSA: DMA CHANNEL x SOURCE START ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 31:24 Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA[31:24](1) 23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA[23:16] 15:8 R/W-0 CHSSA[15:8](1) R/W-0 7:0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA[7:0](1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 Note 1: CHSSA[31:0] Channel Source Start Address bits(1) Channel source start address. This must be the physical address of the source. REGISTER 8-11: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown DCHxDSA: DMA CHANNEL x DESTINATION START ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA[31:24](1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA[23:16] R/W-0 CHDSA[15:8](1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) CHDSA[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 CHDSA[31:0]: Channel Destination Start Address bits(1) Channel destination start address. Note 1: This must be the physical address of the source. DS60001387D-page 92  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 8-12: Bit Range 31:24 23:16 15:8 7:0 DCHxSSIZ: DMA CHANNEL x SOURCE SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSIZ[15:8] R/W-0 CHSSIZ[7:0] Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHSSIZ[15:0]: Channel Source Size bits 1111111111111111 = 65,535-byte source size • • • 0000000000000010 = 2-byte source size 0000000000000001 = 1-byte source size 0000000000000000 = 65,536-byte source size REGISTER 8-13: Bit Range 31:24 23:16 15:8 7:0 DCHxDSIZ: DMA CHANNEL x DESTINATION SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSIZ[15:8] R/W-0 CHDSIZ[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHDSIZ[15:0]: Channel Destination Size bits 1111111111111111 = 65,535-byte destination size • • • 0000000000000010 = 2-byte destination size 0000000000000001 = 1-byte destination size 0000000000000000 = 65,536-byte destination size  2016-2019 Microchip Technology Inc. DS60001387D-page 93 PIC32MM0256GPM064 FAMILY REGISTER 8-14: Bit Range 31:24 23:16 15:8 7:0 DCHxSPTR: DMA CHANNEL x SOURCE POINTER REGISTER(1) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHSPTR[15:8] R-0 R-0 CHSPTR[7:0] Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHSPTR[15:0]: Channel Source Pointer bits 1111111111111111 = Points to Byte 65,535 of the source • • • 0000000000000001 = Points to Byte 1 of the source 0000000000000000 = Points to Byte 0 of the source Note 1: When in Pattern Detect mode, this register is reset on a pattern detect. REGISTER 8-15: Bit Range 31:24 23:16 15:8 7:0 DCHxDPTR: DMA CHANNEL x DESTINATION POINTER REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHDPTR[15:8] R-0 R-0 CHDPTR[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHDPTR[15:0]: Channel Destination Pointer bits 1111111111111111 = Points to Byte 65,535 of the destination • • • 0000000000000001 = Points to Byte 1 of the destination 0000000000000000 = Points to Byte 0 of the destination DS60001387D-page 94  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 8-16: Bit Range 31:24 23:16 15:8 7:0 DCHxCSIZ: DMA CHANNEL x CELL SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHCSIZ[15:8] R/W-0 CHCSIZ[7:0] Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHCSIZ[15:0]: Channel Cell Size bits 1111111111111111 = 65,535 bytes are transferred on an event • • • 0000000000000010 = 2 bytes are transferred on an event 0000000000000001 = 1 byte is transferred on an event 0000000000000000 = 65,536 bytes are transferred on an event REGISTER 8-17: Bit Range 31:24 23:16 15:8 7:0 DCHxCPTR: DMA CHANNEL x CELL POINTER REGISTER(1) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHCPTR[15:8] R-0 R-0 CHCPTR[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHCPTR[7:0]: Channel Cell Progress Pointer bits 1111111111111111 = 65,535 bytes have been transferred since the last event • • • 0000000000000001 = 1 byte has been transferred since the last event 0000000000000000 = 0 bytes have been transferred since the last event Note 1: When in Pattern Detect mode, this register is reset on a pattern detect.  2016-2019 Microchip Technology Inc. DS60001387D-page 95 PIC32MM0256GPM064 FAMILY REGISTER 8-18: Bit Range 31:24 23:16 15:8 7:0 DCHxDAT: DMA CHANNEL x PATTERN DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHPDAT[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 CHPDAT[7:0]: Channel Data Register bits Pattern Terminate mode: Data to be matched must be stored in this register to allow terminate on match. All Other modes: Unused. DS60001387D-page 96  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 9.0 Note: OSCILLATOR CONFIGURATION This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 59. “Oscillators with DCO” (www.microchip.com/DS60001329) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. 9.2 Clock Switching Operation With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC32 devices have a safeguard lock built into the switching process. Note: The PIC32MM0256GPM064 family oscillator system has the following modules and features: • A Total of Five External and Internal Oscillator Options as Clock Sources • On-Chip PLL with User-Selectable Multiplier and Output Divider to Boost Operating Frequency on Select Internal and External Oscillator Sources • On-Chip User-Selectable Divisor Postscaler on Select Oscillator Sources • Software-Controllable Switching between  Various Clock Sources • A Fail-Safe Clock Monitor (FSCM) that Detects Clock Failure and Permits Safe Application  Recovery or Shutdown • Flexible Reference Clock Output A block diagram of the oscillator system is provided in Figure 9-1. 9.1 Fail-Safe Clock Monitor (FSCM) The PIC32MM0256GPM064 family oscillator system includes a Fail-Safe Clock Monitor (FSCM). The FSCM monitors the SYSCLK for continuous operation. If it detects that the SYSCLK has failed, it switches the SYSCLK over to the FRC oscillator and triggers a NonMaskable Interrupt (NMI). When the NMI is executed, software can attempt to restart the main oscillator or shut down the system. In Sleep mode, both the SYSCLK and the FSCM halt, which prevents FSCM detection. 9.2.1 ENABLING CLOCK SWITCHING To enable clock switching, the FCKSM1 Configuration bit in FOSC must be programmed to ‘0’. (Refer to Section 26.1 “Configuration Bits” for further details.) If the FCKSM1 Configuration bit is unprogrammed (‘1’), the clock switching function and Fail-Safe Clock Monitor function are disabled; this is the default setting. The NOSC[2:0] control bits (OSCCON[10:8]) do not control the clock selection when clock switching is disabled. However, the COSC[2:0] bits (OSCCON[14:12]) will reflect the clock source selected by the FNOSC[2:0] Configuration bits. The OSWEN control bit (OSCCON[0]) has no effect when clock switching is disabled; it is held at ‘0’ at all times. 9.2.2 OSCILLATOR SWITCHING SEQUENCE At a minimum, performing a clock switch requires this basic sequence: 1. 2. 3. 4.  2016-2019 Microchip Technology Inc. The Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMOD[1:0] Configuration bits. While an application can switch to and from Primary Oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. If desired, read the COSC[2:0] bits (OSCCON[14:12]) to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register. Write the appropriate value to the NOSC[2:0] bits (OSCCON[10:8]) for the new oscillator source. Set the OSWEN bit to initiate the oscillator switch. DS60001387D-page 97 PIC32MM0256GPM064 FAMILY Once the basic sequence is completed, the system clock hardware responds automatically as follows: A recommended code sequence for a clock switch includes the following: 1. 1. 2. 3. 4. 5. 6. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. If a valid clock switch has been initiated, the LOCK (OSCTUN[11]) and CF (OSCCON[3]) bits are cleared. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware will wait until the OST expires. If the new source is using the PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). The hardware waits for ten clock cycles from the new clock source and then performs the clock switch. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSC[2:0] bits values are transferred to the COSC[2:0] bits. The old clock source is turned off if it is not being used by a peripheral, or enabled by device configuration or a control register. Note 1: The processor will continue to execute code throughout the clock switching sequence. Timing-sensitive code should not be executed during this time. 2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transitional clock source between the two PLL modes. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for OSCCON by writing 0xAA996655 and 0x556699AA to the SYSKEY register. Write the new oscillator source to the NOSC[2:0] bits. Set the OSWEN bit. Relock the OSCCON register. Continue to execute code that is not clock-sensitive (optional). 2. 3. 4. 5. 6. The core sequence for unlocking the OSCCON register and initiating a clock switch is shown in Example 9-1. EXAMPLE 9-1: SYSKEY = 0x00000000; SYSKEY = 0xAA996655; SYSKEY = 0x556699AA; // force lock // unlock OSCCONbits.NOSC = 3; // select the new clock source OSCCONSET = 1; // set the OSWEN bit SYSKEY = 0x00000000; // force lock while (OSCCONbits.OSWEN); // optional wait for  switch operation BSET OSCCON, #0 9.3 Two-Speed Start-up Two-Speed Start-up is enabled by the IESO Configuration bit. When enabled, the device will start operating from a POR or any Reset with the FRC as the clock source. When the PLL is ready, the clock module will automatically switch to the PLL source using the PLL settings from the SPLLCON register. Note: DS60001387D-page 98 BASIC CODE SEQUENCE FOR CLOCK SWITCHING If using PLL operation, with PLL configuration values other than the default values, Two-Speed start-up should not be used. In this case, it is recommended that the device be configured with FRC as the clock source. After start-up, user code can modify the PLL configuration and then request a clock switch to the PLL source.  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 9.4 FRC Active Clock Tuning PIC32MM0256GPM064 family devices include an automatic mechanism to calibrate the FRC during run time. This system uses active clock tuning from a source of known accuracy to maintain the FRC within a very narrow margin of its nominal 8 MHz frequency. This allows for a frequency accuracy that is well within the requirements of the “USB 2.0 Specification” regarding full-speed USB devices. Note: The self-tune feature maintains sufficient accuracy for operation in USB Device mode. For applications that function as a USB host, a high-accuracy clock source (±0.05%) is still required. The self-tune system is controlled by the bits in the upper half of the OSCTUN register. Setting the ON bit (OSCTUN[15]) enables the self-tuning feature, allowing the hardware to calibrate to a source selected by the SRC bit (OSCTUN[12]). When SRC = 1, the system uses the Start-of-Frame (SOF) packets from an external USB host for its source. When SRC = 0, the system uses the crystal-controlled SOSC for its calibration source. Regardless of the source, the system uses the TUN[5:0] bits (OSCTUN[5:0]) to change the FRC Oscillator’s frequency. Frequency monitoring and adjustment is dynamic, occurring continuously during run time. While the system is active, the TUNx bits cannot be written to by software. Note: The self-tune system can generate a hardware interrupt, FSTIF. The interrupt can result from a drift of the FRC from the reference, by greater than 0.2% in either direction, or whenever the frequency deviation is beyond the ability of the TUNx bits to correct (i.e., greater than 1.5%). The LOCK and ORNG status bits (OSCTUN[11,9]) are used to indicate these conditions. The POL and ORPOL bits (OSCTUN[10,8]) configure the FSTIF interrupt to occur in the presence or the absence of the conditions. It is the user’s responsibility to monitor both the LOCK and ORNG bits to determine the exact cause of the interrupt. Note: The POL and ORPOL bits should be ignored when the self-tune system is disabled (ON = 0). Note: After exiting out of self-tune, six writes may be required to update the TUN[5:0] bits. To use the USB as a reference clock tuning source (SRC = 1), the microcontroller must be configured for USB device operation and connected to a non-suspended USB host or hub port. If the SOSC is to be used as the reference clock tuning source (SRC = 0), the SOSC must also be enabled for clock tuning to occur.  2016-2019 Microchip Technology Inc. DS60001387D-page 99 PIC32MM0256GPM064 FAMILY PIC32MM0256GPM064 FAMILY OSCILLATOR DIAGRAM(1) FIGURE 9-1: 48 MHz to USB 2 Reference Clock 2 MHz ≤ FIN ≤ 24 MHz 16 MHz ≤ FVCO ≤ 96 MHz REFO1CON REFCLKI System PLL FIN(1) PLLICLK PLL x M Fvco(1) PLLMULT[6:0] (M) SPLLVCO PLLODIV[2:0] (N) N REFO1TRIM ROTRIM[8:0] (M) POSC FRC LPRC SOSC 2 OE M    N + -------- 512 REFCLKO RODIV[14:0] (N) SYSCLK To MCCP, SCCP, SPIx and UARTs FPLL(1) ROSEL[3:0] SPLL Primary Oscillator (POSC) POSC (HS, EC) OSC1/ CLKI POSCMOD[1:0] OSC2 To ADC, WDT, UART and Flash Controller FRC Oscillator 8 MHz FRCDIV SYSCLK (FSYS) LPRC PBCLK (FPB) FRCDIV[2:0] (N) TUN[5:0] LPRC Oscillator Postscaler N 32 kHz Secondary Oscillator (SOSC) 32.768 kHz SOSCEN SOSCO/ SCLKI SOSCSEL SOSC Clock Control Logic Fail-Safe Clock Monitor SOSCI NOSC[2:0] COSC[2:0] OSWEN FCKSM[1:0] FNOSC[2:0] To Timer1, WDT, RTCC To Timer1, RTCC, MCCP/SCCP and CLC Note 1: Refer to Table 29-19 in Section 29.0 “Electrical Characteristics” for frequency limitations. DS60001387D-page 100  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY FIGURE 9-2: REFERENCE OSCILLATOR 2 48 MHz to USB VCO 16-96 MHz 25 MHz Max(2) N REFCLKO ROSEL[3:0] (Note 1) RODIV[14:0] PLLMULT[6:0] ROTRIM[8:0] SYSCLK PBCLK 25 MHz Max N SPI Module OE SPI Module 50 MHz Max MCLKSEL COSC[2:0] PLLODIV[2:0] PLLICLK MCCP/SCCP Module FRC CLKSEL[1:0] UART UART Module CLKSEL[1:0] Note 1: 2: Support circuitry for crystal is not shown. In Retention mode, the maximum peripheral output frequency to an I/O pin must be limited to 33 kHz or less.  2016-2019 Microchip Technology Inc. DS60001387D-page 101 Oscillator Control Registers Register Name(2) 2680 OSCCON 26A0 OSCILLATOR CONFIGURATION REGISTER MAP SPLLCON 2720 REFO1CON 2730 REFO1TRIM 2770 CLKSTAT 2880 OSCTUN Bit Range Bits 31/15 30/14 29/13 28/12 27/11 31:16 — — 15:0 — — — — — 31:16 — — — — — 15:0 — — — — — 31:16 — 15:0 ON COSC[2:0] 26/10 — 25/9 23/7 22/6 21/5 FRCDIV[2:0] — — — NOSC[2:0] CLKLOCK — — PLLODIV[2:0] — — 24/8 — PLLICLK 19/3 18/2 17/1 16/0 — — — — — 0000 SLPEN CF — SOSCEN OSWEN xx0x — — — PLLMULT[6:0] — 0001 r — — — — — — — — — — — — 0000 RODIV[14:0] — SIDL OE 31:16 RSLP — DIVSWEN ACTIVE — ROTRIM[8:0] 0000 0000 ROSEL[3:0] 0000 15:0 — — — — — — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — r 31:16 — — — — — — — — — — 15:0 ON r SIDL SRC LOCK POL ORNG ORPOL — — SPLLRDY USBRDY LPRCRDY SOSCRDY Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’; r = reserved bit. Reset values are shown in hexadecimal. Note 1: Reset values are dependent on the FOSCSEL Configuration bits and the type of Reset. 2: 20/4 All Resets(1) Virtual Address (BF80_#) TABLE 9-1: — All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. — r POSCRDY SPDIVRDY FRCRDY 0000 — — TUN[5:0] — — 0000 0000 PIC32MM0256GPM064 FAMILY DS60001387D-page 102 9.5  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 9-1: Bit Range 31:24 23:16 15:8 7:0 OSCCON: OSCILLATOR CONTROL REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 R/W-0 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 FRCDIV[2:0] U-0 U-0 U-0 — — — — — — — — U-0 R-y R-y R-y U-0 R/W-y R/W-y R/W-y — COSC[2:0] — NOSC[2:0] R/W-0 U-0 U-0 R/W-0 R/W-0, HS U-0 R/W-y R/W-y CLKLOCK — — SLPEN CF — SOSCEN OSWEN(1) Legend: HS = Hardware Settable bit y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-27 Unimplemented: Read as ‘0’ bit 26-24 FRCDIV[2:0]: Internal Fast RC (FRC) Oscillator Clock Divider bits 111 = FRC divided by 256 110 = FRC divided by 64 101 = FRC divided by 32 100 = FRC divided by 16 011 = FRC divided by 8 010 = FRC divided by 4 001 = FRC divided by 2 000 = FRC divided by 1 (default setting) bit 23-15 Unimplemented: Read as ‘0’ bit 14-12 COSC[2:0]: Current Oscillator Selection bits 111-110 = Reserved (selects internal Fast RC (FRC) Oscillator divided by FRCDIV[2:0] bits (FRCDIV)) 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Reserved 010 = Primary Oscillator (POSC) (XT, HS or EC) 001 = System PLL (SPLL) 000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV[2:0] bits (FRCDIV) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC[2:0]: New Oscillator Selection bits 111-110 = Reserved (selects internal Fast RC (FRC) Oscillator divided by FRCDIV[2:0] bits (FRCDIV)) 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Reserved 010 = Primary Oscillator (POSC) (XT, HS or EC) 001 = System PLL (SPLL) 000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV[2:0] bits (FRCDIV) On Reset, these bits are set to the value of the FNOSC[2:0] Configuration bits (FOSCSEL[2:0]). Note 1: The Reset value for this bit depends on the setting of the IESO (FOSCSEL[7]) bit. When IESO = 1, the Reset value is ‘1’. When IESO = 0, the Reset value is ‘0’. Note: Writes to this register require an unlock sequence. Refer to Section 26.4 “System Registers Write Protection” for details.  2016-2019 Microchip Technology Inc. DS60001387D-page 103 PIC32MM0256GPM064 FAMILY REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enable bit 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified bit 6-5 Unimplemented: Read as ‘0’ bit 4 SLPEN: Sleep Mode Enable bit 1 = Device will enter Sleep mode when a WAIT instruction is executed 0 = Device will enter Idle mode when a WAIT instruction is executed bit 3 CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 2 Unimplemented: Read as ‘0’ bit 1 SOSCEN: Secondary Oscillator (SOSC) Enable bit 1 = Enables the Secondary Oscillator 0 = Disables the Secondary Oscillator bit 0 OSWEN: Oscillator Switch Enable bit(1) 1 = Initiates an oscillator switch to a selection specified by the NOSC[2:0] bits 0 = Oscillator switch is complete Note 1: The Reset value for this bit depends on the setting of the IESO (FOSCSEL[7]) bit. When IESO = 1, the Reset value is ‘1’. When IESO = 0, the Reset value is ‘0’. Note: Writes to this register require an unlock sequence. Refer to Section 26.4 “System Registers Write Protection” for details. DS60001387D-page 104  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 9-2: Bit Range 31:24 23:16 15:8 7:0 SPLLCON: SYSTEM PLL CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — U-0 R/W-0 R/W-0 R/W-0 R/W-0 — PLLMULT[6:0] Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 PLLODIV[2:0](1) R/W-0 R/W-0 R/W-1 U-0 (1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-y r-0 U-0 U-0 U-0 U-0 U-0 U-0 PLLICLK(1) — — — — — — — Legend: r = Reserved bit y = Values set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-27 Unimplemented: Read as ‘0’ bit 26-24 PLLODIV[2:0]: System PLL Output Clock Divider bits(1) 111 = PLL divide-by-256 110 = PLL divide-by-64 101 = PLL divide-by-32 100 = PLL divide-by-16 011 = PLL divide-by-8 010 = PLL divide-by-4 001 = PLL divide-by-2 000 = PLL divide-by-1 (default setting) bit 23 Unimplemented: Read as ‘0’ bit 22-16 PLLMULT[6:0]: System PLL Multiplier bits(1) 111111-0000111 = Reserved 0000110 = 24x 0000101 = 12x 0000100 = 8x 0000011 = 6x 0000010 = 4x 0000001 = 3x (default setting) 0000000 = 2x bit 15-8 Unimplemented: Read as ‘0’ bit 7 PLLICLK: System PLL Input Clock Source bit(1) 1 = FRC is selected as the input to the system PLL (not divided) 0 = POSC is selected as the input to the system PLL; the POR default value is specified by the PLLSRC bit The POR default value is specified by the PLLSRC Configuration bit in the FOSCSEL register. Refer to Register 26-9 in Section 26.0 “Special Features” for more information. bit 6 Reserved: Maintain as ‘0’ bit 5-0 Unimplemented: Read as ‘0’ Note 1: Do not change the SPLLCON bits while the PLL is running. If the PLL configuration needs to be changed, switch to a non-PLL source, reconfigure the PLL and then switch to the PLL source. Note: Writes to this register require an unlock sequence. Refer to Section 26.4 “System Registers Write Protection” for details.  2016-2019 Microchip Technology Inc. DS60001387D-page 105 PIC32MM0256GPM064 FAMILY REGISTER 9-3: Bit Range 31:24 23:16 15:8 7:0 REFO1CON: REFERENCE OSCILLATOR CONTROL REGISTER Bit Bit 31/23/15/7 30/22/14/6 U-0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — R/W-0 RODIV[14:8] R/W-0 RODIV[7:0] R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R-0, HS, HC ON(1) — SIDL OE RSLP(2) — DIVSWEN ACTIVE(1) U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — ROSEL[3:0](3) Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31 x = Bit is unknown Unimplemented: Read as ‘0’ bit 30-16 RODIV[14:0]: Reference Clock Divider bits The value selects the reference clock divider bits (see Figure 9-1 for details). A value of ‘0’ selects no divider. bit 15 ON: Reference Oscillator Output Enable bit(1) 1 = Reference oscillator module is enabled 0 = Reference oscillator module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Peripheral Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 OE: Reference Clock Output Enable bit 1 = Reference clock is driven out on the REFO1 pin 0 = Reference clock is not driven out on the REFO1 pin bit 11 RSLP: Reference Oscillator Module Run in Sleep bit(2) 1 = Reference oscillator module output continues to run in Sleep 0 = Reference oscillator module output is disabled in Sleep bit 10 Unimplemented: Read as ‘0’ bit 9 DIVSWEN: Divider Switch Enable bit 1 = Divider switch is in progress 0 = Divider switch is complete bit 8 ACTIVE: Reference Clock Request Status bit(1) 1 = Reference clock request is active 0 = Reference clock request is not active bit 7-4 Unimplemented: Read as ‘0’ Note 1: 2: 3: Do not write to this register when the ON bit is not equal to the ACTIVE bit. This bit is ignored when the ROSEL[3:0] bits = 0000. The ROSEL[3:0] bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result. DS60001387D-page 106  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 9-3: REFO1CON: REFERENCE OSCILLATOR CONTROL REGISTER (CONTINUED) bit 3-0 ROSEL[3:0]: Reference Clock Source Select bits(3) 1111 = Reserved 1001 = REFCLKI pin • • • 0111 = System PLL VCO output (not divided) 0110 = Reserved 0101 = SOSC 0100 = LPRC 0011 = FRC 0010 = POSC 0001 = Reserved 0000 = SYSCLK Note 1: 2: 3: Do not write to this register when the ON bit is not equal to the ACTIVE bit. This bit is ignored when the ROSEL[3:0] bits = 0000. The ROSEL[3:0] bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result.  2016-2019 Microchip Technology Inc. DS60001387D-page 107 PIC32MM0256GPM064 FAMILY REGISTER 9-4: Bit Range 31:24 23:16 15:8 7:0 REFO1TRIM: REFERENCE OSCILLATOR TRIM REGISTER(1,2,3) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 ROTRIM[8:1] R/W-0 U-0 U-0 U-0 U-0 ROTRIM[0] — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-23 ROTRIM[8:0]: Reference Oscillator Trim bits 111111111 = 511/512 divisor added to the RODIVx value 111111110 = 510/512 divisor added to the RODIVx value • • • 100000000 = 256/512 divisor added to the RODIVx value • • • 000000010 = 2/512 divisor added to the RODIVx value 000000001 = 1/512 divisor added to the RODIVx value 000000000 = 0 divisor added to the RODIVx value bit 22-0 Note 1: 2: 3: Unimplemented: Read as ‘0’ While the ON bit (REFO1CON[15]) is ‘1’, writes to this register do not take effect until the DIVSWEN bit is also set to ‘1’. Do not write to this register when the ON bit (REFO1CON[15]) is not equal to the ACTIVE bit (REFO1CON[8]). Specified values in this register do not take effect if RODIV[14:0] (REFO1CON[30:16]) = 0. DS60001387D-page 108  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 9-5: Bit Range 31:24 23:16 15:8 7:0 CLKSTAT: CLOCK STATUS REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 r-1 — — — — — — — — R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC r-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC SPLLRDY USBRDY LPRCRDY SOSCRDY — POSCRDY SPDIVRDY Legend: HS = Hardware Settable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-9 Unimplemented: Read as ‘0’ bit 8 Reserved: Read as ‘1’ bit 7 SPLLRDY: PLL Lock bit 1 = PLL is locked and ready 0 = PLL is not locked bit 6 USBRDY: USB Oscillator Ready bit 1 = USB oscillator is running 0 = USB oscillator is not running bit 5 LPRCRDY: LPRC Oscillator Ready bit 1 = LPRC oscillator is enabled 0 = LPRC oscillator is not enabled bit 4 SOSCRDY: Secondary Oscillator (SOSC) Ready bit 1 = SOSC is enabled and the Oscillator Start-up Timer (OST) has expired 0 = SOSC is not enabled or the Oscillator Start-up Timer has not expired bit 3 Reserved: Read as ‘0’ bit 2 POSCRDY: Primary Oscillator (POSC) Ready bit 1 = POSC is enabled and the Oscillator Start-up Timer has expired 0 = POSC is not enabled or the Oscillator Start-up Timer has not expired bit 1 SPDIVRDY: System PLL (with postscaler, SPLLDIV) Clock Ready Status bit 1 = SPLLDIV is enabled and the PLL start-up timer has expired 0 = SPLLDIV is not enabled or the PLL start-up timer has not expired bit 0 FRCRDY: Fast RC (FRC) Oscillator Ready bit 1 = FRC oscillator is enabled 0 = FRC oscillator is not enabled  2016-2019 Microchip Technology Inc. FRCRDY r = Reserved bit DS60001387D-page 109 PIC32MM0256GPM064 FAMILY REGISTER 9-6: Bit Range 31:24 23:16 15:8 7:0 OSCTUN: FRC TUNING REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ON — SIDL SRC LOCK POL ORNG ORPOL U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — R/W-0 (1) TUN[5:0] Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Self-Tune Enable bit 1 = FRC self-tuning is enabled; the TUNx bits are controlled by hardware 0 = FRC self-tuning is disabled; the TUNx bits are readable and writable bit 14 Reserved: Used by debugger bit 13 SIDL: FRC Self-Tune Stop in Idle bit 1 = Self-tuning stops during Idle mode 0 = Self-tuning continues during Idle mode bit 12 SRC: FRC Self-Tune Reference Clock Source bit 1 = The USB host clock is used to tune the FRC 0 = The 32.768 kHz SOSC clock is used to tune the FRC bit 11 LOCK: FRC Self-Tune Lock Status bit 1 = FRC accuracy is currently within ±0.2% of the SRC reference accuracy 0 = FRC accuracy may not be within ±0.2% of the SRC reference accuracy bit 10 POL: FRC Self-Tune Lock Interrupt Polarity bit 1 = A self-tune lock interrupt is generated when LOCK is ‘0’ 0 = A self-tune lock interrupt is generated when LOCK is ‘1’ bit 9 ORNG: FRC Self-Tune Out of Range Status bit 1 = SRC reference clock error is beyond the range of TUN[5:0]; no tuning is performed 0 = SRC reference clock is within the tunable range; tuning is performed bit 8 ORPOL: FRC Self-Tune Out of Range Interrupt Polarity bit 1 = A self-tune out of range interrupt is generated when STOR is ‘0’ 0 = A self-tune out of range interrupt is generated when STOR is ‘1’ bit 7-6 Unimplemented: Read as ‘0’ Note 1: Note: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step-size is an approximation and is neither characterized, nor tested. Writes to this register require an unlock sequence. Refer to Section 26.4 “System Registers Write Protection” for details. DS60001387D-page 110  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 9-6: bit 5-0 Note 1: Note: OSCTUN: FRC TUNING REGISTER (CONTINUED) TUN[5:0]: FRC Oscillator Tuning bits(1) 100000 = Center frequency – 1.50% 100001 = • • • 111111 = 000000 = Center frequency; oscillator runs at a nominal frequency (8 MHz) 000001 = • • • 011110 = 011111 = Center frequency + 1.453% OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step-size is an approximation and is neither characterized, nor tested. Writes to this register require an unlock sequence. Refer to Section 26.4 “System Registers Write Protection” for details.  2016-2019 Microchip Technology Inc. DS60001387D-page 111 PIC32MM0256GPM064 FAMILY NOTES: DS60001387D-page 112  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 10.0 Note: I/O PORTS Many of the device pins are shared among the peripherals and the Parallel I/O (PIO) ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity. Some pins in the devices are 5V tolerant pins. Some of the key features of the I/O ports are: This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. “I/O Ports” (www.microchip.com/DS60001120) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. FIGURE 10-1: • Individual Output Pin Open-Drain Enable/Disable • Individual Input Pin Weak Pull-up and Pull-Down • Monitor Selective Inputs and Generate Interrupt when Change in Pin State is Detected • Operation during Sleep and Idle modes • Fast Bit Manipulation using the CLR, SET and INV Registers Figure 10-1 illustrates a block diagram of a typical multiplexed I/O port. BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data I/O 1 Output Enable 0 VDD PIO Module WR TRISx Output Data 0 Read TRISx Data Bus 1 D Q CK TRIS Latch D WR LATx + WR PORTx Q CK Data Latch Read LATx Input Data Read PORTx Note 1: Refer to Section 29.0 “Electrical Characteristics” for ESD resistor value.  2016-2019 Microchip Technology Inc. DS60001387D-page 113 PIC32MM0256GPM064 FAMILY 10.1 CLR, SET and INV Registers Every I/O module register has a corresponding CLR (Clear), SET (Set) and INV (Invert) register designed to provide fast atomic bit manipulations. As the name of the register implies, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as ‘1’ are modified. Bits specified as ‘0’ are not modified. Reading SET, CLR and INV registers returns undefined values. To see the effects of a write operation to a SET, CLR or INV register, the base register must be read. 10.2 Parallel I/O (PIO) Ports All port pins have 14 registers directly associated with their operation as digital I/Os. The Data Direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. The LATx register controls the pin level when it is configured as an output. Reads from the PORTx register read the port pins, while writes to the port pins write the latch, LATx. 10.3 Open-Drain Configuration In addition to the PORTx, LATx and TRISx registers for data control, the port pins can also be individually configured for either digital or open-drain outputs. This is controlled by the Open-Drain Control x register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V), on any desired 5V tolerant pins, by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. 10.4 Configuring Analog and Digital Port Pins When the PORTx register is read, all pins configured as analog input channels are read as cleared (a low level). Pins configured as digital inputs do not convert an analog input. Analog levels on any pin defined as a digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the device specifications. The ANSELx register controls the operation of the analog port pins. The port pins that are to function as analog inputs must have their corresponding ANSELx and TRISx bits set. In order to use port pins for I/O functionality with digital modules, such as timers, UARTs, etc., the corresponding ANSELx bit must be cleared. The ANSELx register has a default value of 0xFFFF. Therefore, all pins that share analog functions are analog (not digital) by default. If the TRISx bit is cleared (output) while the ANSELx bit is set, the digital output level (VOH or VOL) is used by an analog peripheral, such as the ADC or comparator module. DS60001387D-page 114 10.5 I/O Port Write/Read Timing One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP. There is a three-instruction cycle delay in the port read synchronizer. When a port or port bit is read, the returned value is the value that was present on the port three system clocks prior. 10.6 GPIO Port Merging Port merging creates a 32-bit wide port from two GPIO ports. When the PORT32 bit is set, the next I/O port is mapped to the upper 16 bits of the lower port. Only the next higher letter port can be merged to a given port (i.e., PORTA can only be merged with PORTB). Note: 10.7 All 32 pins may not be available. Refer to the pin diagrams for information regarding GPIO port pin availability. Input Change Notification (ICN) The Input Change Notification function of the I/O ports allows the PIC32MM devices to generate interrupt requests to the processor in response to a Change-ofState (COS) on the input pins. This feature can detect input Change-of-States, even in Sleep mode, when the clocks are disabled. Every I/O port pin can be selected (enabled) for generating an interrupt request on a Change-of-State. Five control registers are associated with the Change Notification (CN) functionality of each I/O port. To enable the Change Notification feature for the port, the ON bit (CNCONx[15]) must be set. The CNEN0x and CNEN1x registers contain the CN interrupt enable control bits for each of the input pins. The setting of these bits enables a CN interrupt for the corresponding pins. Also, these bits, in combination with the CNSTYLE bit (CNCONx[11]), define a type of transition when the interrupt is generated. Possible CN event options are listed in Table 10-1. TABLE 10-1: CHANGE NOTIFICATION EVENT OPTIONS CNSTYLE Bit CNEN1x CNEN0x Change Notification Event (CNCONx[11]) Bit Bit Description 0 Does not matter 0 Disabled 0 Does not matter 1 Detects a mismatch between the last read state and the current state of the pin 1 0 0 Disabled 1 0 1 Detects a positive transition only (from ‘0’ to ‘1’) 1 1 0 Detects a negative transition only (from ‘1’ to ‘0’) 1 1 1 Detects both positive and negative transitions  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY The CNSTATx register indicates whether a change occurred on the corresponding pin since the last read of the PORTx bit. In addition to the CNSTATx register, the CNFx register is implemented for each port. This register contains flags for Change Notification events. These flags are set if the valid transition edge, selected in the CNEN0x and CNEN1x registers, is detected. CNFx stores the occurrence of the event. CNFx bits must be cleared in software to get the next Change Notification interrupt. The CN interrupt is generated only for the I/Os configured as inputs (corresponding TRISx bits must be set). 10.9.1 10.8 In comparison, some digital only peripheral modules are never included in the PPS feature. This is because the peripheral’s function requires special I/O circuitry on a specific port and cannot be easily connected to multiple pins. These modules include I2C among others. A similar requirement excludes all modules with analog inputs, such as the Analog-to-Digital Converter (ADC). Pin Pull-up and Pull-Down Each I/O pin also has a weak pull-up and a weak pulldown connected to it. The pull-ups act as a current source, or sink source, connected to the pin and eliminate the need for external resistors when push button or keypad devices are connected. The pull-ups and pull-downs are enabled separately using the CNPUx and the CNPDx registers, which contain the control bits for each of the pins. Setting any of the control bits enables the weak pull-ups and/or pull-downs for the corresponding pins. 10.9 Peripheral Pin Select (PPS) A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low pin count devices. In an application where more than one peripheral needs to be assigned to a single pin, inconvenient work arounds in application code, or a complete redesign, may be the only option. PPS configuration provides an alternative to these choices by enabling peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the device to their entire application, rather than trimming the application to fit the device. The PPS configuration feature operates over a fixed subset of digital I/O pins. Users may independently map the input and/or output of most digital peripherals to these I/O pins. PPS is performed in software and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established.  2016-2019 Microchip Technology Inc. AVAILABLE PINS The number of available pins is dependent on the particular device and its pin count. Pins that support the PPS feature include the designation, “RPn”, in their full pin designation, where “RP” designates a Remappable Peripheral and “n” is the remappable port number. 10.9.2 AVAILABLE PERIPHERALS The peripherals managed by the PPS are all digital only peripherals. These include general serial communications (UART and SPI), general purpose timer clock inputs, timer-related peripherals (MCCP, SCCP) and others. A key difference between remappable and nonremappable peripherals is that remappable peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non-remappable peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. When a remappable peripheral is active on a given I/O pin, it takes priority over all other digital I/Os and digital communication peripherals associated with the pin. Priority is given regardless of the type of peripheral that is mapped. Remappable peripherals never take priority over any analog functions associated with the pin. 10.9.3 CONTROLLING PPS PPS features are controlled through two sets of SFRs: one to map peripheral inputs and one to map outputs. Because they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on whether an input or output is being mapped. DS60001387D-page 115 PIC32MM0256GPM064 FAMILY 10.9.4 INPUT MAPPING FIGURE 10-2: The inputs of the PPS options are mapped on the basis of the peripheral. That is, a control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers (refer to the peripheral pins listed in Table 10-2) are used to configure peripheral input mapping (see Register 10-1). Each register contains sets of 5-bit fields. Programming these bits with a number of the remappable pin will connect the peripheral to this RPn pin (refer to Table 10-3). For any given device, the valid range of values for any bit field is shown in Table 10-2. REMAPPABLE INPUT EXAMPLE FOR U2RX U2RXR[4:0] 1 RP1 2 RP2 3 U2RX Input to Peripheral RP3 For example, Figure 10-2 illustrates the remappable pin selection for the U2RX input. n RPn Note: TABLE 10-2: For input only, PPS functionality does not have priority over TRISx settings. Therefore, when configuring an RPn pin for input, the corresponding bit in the TRISx register must also be configured for input (set to ‘1’). INPUT PIN SELECTION Input Name Function Name Register Function Bits External Interrupt 4 INT4 RPINR1 INT4R[4:0] MCCP1 Input Capture ICM1 RPINR2 ICM1R[4:0] MCCP2 Input Capture ICM2 RPINR2 ICM2R[4:0] MCCP3 Input Capture ICM3 RPINR3 ICM3R[4:0] SCCP4 Input Capture ICM4 RPINR3 ICM4R[4:0] Output Compare Fault A OCFA RPINR5 OCFAR[4:0] Output Compare Fault B OCFB RPINR5 OCFBR[4:0] CCP Clock Input A TCKIA RPINR6 TCKIAR[4:0] CCP Clock Input B TCKIB RPINR6 TCKIBR[4:0] SCCP5 Input Capture ICM5 RPINR7 ICM5R[4:0] SCCP6 Input Capture ICM6 RPINR7 ICM6R[4:0] SCCP7 Input Capture ICM7 RPINR7 ICM7R[4:0] SCCP8 Input Capture ICM8 RPINR7 ICM8R[4:0] SCCP9 Input Capture ICM9 RPINR8 ICM9R[4:0] UART3 Receive U3RX RPINR8 U3RXR[4:0] UART2 Receive U2RX RPINR9 U2RXR[4:0] UART2 Clear-to-Send U2CTS RPINR9 U2CTSR[4:0] UART3 Clear-to-Send U3CTS RPINR10 U3CTSR[4:0] SPI2 Data Input SDI2 RPINR11 SDI2R[4:0] SPI2 Clock Input SCK2IN RPINR11 SCK2INR[4:0] SS2IN RPINR11 SS2INR[4:0] CLC Input A CLCINA RPINR12 CLCINAR[4:0] CLC Input B CLCINB RPINR12 CLCINBR[4:0] SPI2 Slave Select Input DS60001387D-page 116  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY TABLE 10-3: REMAPPABLE INPUT SOURCES PIN ASSIGNMENTS(1) Value RPn Pins Pin Assignment Value RPn Pins Pin Assignment 00001 RP1 RA0 Pin 01110 RP14 RB9 Pin 00010 RP2 RA1 Pin 01111 RP15 RB13 Pin 00011 RP3 RA2 Pin 10000 RP16 RB14 Pin 00100 RP4 RA3 Pin 10001 RP17 RB15 Pin 00101 RP5 RA4 Pin 10010 RP18 RC9 Pin 00110 RP6 RB0 Pin 10011 RP19 RC2 Pin 00111 RP7 RB1 Pin 10100 RP20 RC7 Pin 01000 RP8 RB2 Pin 10101 RP21 RA7 Pin 01001 RP9 RB3 Pin 10110 RP22 RA10 Pin 01010 RP10 RB4 Pin 10111 RP23 RC6 Pin RP24 01011 RP11 RB5 Pin 11000 01100 RP12 RB7 Pin 11001-11111 01101 RP13 RB8 Pin Note 1: RA9 Pin Reserved All RPn pins are not available on all packages.  2016-2019 Microchip Technology Inc. DS60001387D-page 117 PIC32MM0256GPM064 FAMILY 10.9.5 OUTPUT MAPPING 10.9.6 In contrast to inputs, the outputs of the PPS options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. Like the RPINRx registers, each register contains sets of 4-bit fields. The value of the bit field corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see Table 10-4 and Figure 10-3). A null output is associated with the output register Reset value of ‘0’. This is done to ensure that remappable outputs remain disconnected from all output pins by default. CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC32MM0256GPM064 family devices include two features to prevent alterations to the peripheral map: • Control register lock sequence • Configuration bit select lock 10.9.6.1 Control Register Lock RP1R[3:0] Under normal operation, writes to the RPORx and RPINRx registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit in the RPCON register. Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. 0 To set or clear the IOLOCK bit, an unlock sequence must be executed. Refer to Section 26.4 “System Registers Write Protection” for details. FIGURE 10-3: EXAMPLE OF MULTIPLEXING OF REMAPPABLE OUTPUT FOR RP0 Default U2TX Output SDO2 Output 1 2 Output Data CLC2OUT DS60001387D-page 118 RP1 9  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY TABLE 10-4: OUTPUT PIN SELECTION Output Function Number Function Output Name 0 None Not Connected 1 C1OUT Comparator 1 Output 2 C2OUT Comparator 2 Output 3 C3OUT Comparator 3 Output 4 U2TX UART2 Transmit 5 U2RTS UART2 Request-to-Send 6 U3TX UART3 Transmit 7 U3RTS UART3 Request-to-Send 8 SDO2 SPI2 Data Output 9 SCK2OUT SPI2 Clock Output 10 SS2OUT SPI2 Slave Select Output 11 OCM4 SCCP4 Output Compare Output 12 OCM5 SCCP5 Output Compare Output 13 OCM6 SCCP6 Output Compare Output 14 OCM7 SCCP7 Output Compare Output 15 OCM8 SCCP8 Output Compare Output 16 OCM9 SCCP9 Output Compare Output 17 CLC1OUT CLC1 Output 18 CLC2OUT CLC2 Output 19 CLC3OUT CLC3 Output 20 CLC4OUT CLC4 Output  2016-2019 Microchip Technology Inc. DS60001387D-page 119 Virtual Address (BF80_#) Register Name(1) TABLE 10-5: 2BB0 ANSELA 2BD0 PORTA 2BE0 LATA 2BF0 2C10 ODCA CNPUA CNPDA 2C20 CNCONA 2C30 CNEN0A  2016-2019 Microchip Technology Inc. 2C40 CNSTATA 2C50 CNEN1A 2C60 Legend: Note 1: 2: 3: 4: 5: CNFA 31/15 30/14 29/13 31:16 — — — 15:0 — — 31:16 — — — — — — — 0000 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — ANSA[3:0] 384F TRISA[15:0](3) — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 ON — — — 31:16 — — — — — — CNSTYLE PORT32 — — 0000 — — — — — — — — — 0000 — — — — — — — — — — 0000 — — — — — — — — — — 0000 — — — — — — — — — — — — — — — — — — — — — CNIE0A[15:0](3) — — — — — — — — 0000 CNSTATA[15:0](3) 15:0 — — — — — — — — — — — — — — — — — 0000 0000 CNIE1A[15:0](3) 15:0 — 0000 — 15:0 — 0000 0000 CNPDA[15:0](4) — 0000 0000 CNPUA[15:0](3) — 0000 0000 ODCA[15:0](3) — 0000 xxxx LATA[15:0](3) — 0000 021F RA[15:0](3) — 15:0 — ANSA6(3) — — 31:16 — — — 31:16 31:16 — — 15:0 31:16 16/0 23/7 15:0 31:16 17/1 24/8 15:0 31:16 18/2 25/9 15:0 31:16 19/3 26/10 15:0 31:16 20/4 27/11 15:0 31:16 21/5 28/12 ANSA[13:11](2) — 22/6 All Resets TRISA Bit Range Bits 2BC0 2C00 PORTA REGISTER MAP 0000 0000 CNFA[15:0](3) x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. These bits are not available on 48, 36 or 28-pin devices. These bits are not available on 28-pin and 36-pin devices. These bits are not available on 28-pin devices. Digital exclusions. 0000 0000 PIC32MM0256GPM064 FAMILY DS60001387D-page 120 10.10 I/O Ports Control Registers Virtual Address (BF80_#) Register Name(1) 2CB0 ANSELB 2CD0 2CE0 2D00 2D10 TRISB PORTB LATB ODCB CNPUB CNPDB 2D20 CNCONB 2D30 CNEN0B 2D40 CNSTATB 2D50 2D60 CNEN1B CNFB 31/15 30/14 29/13 31:16 — — — 15:0 — — 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — ANSB[4:0] E01F TRISB[15:0] — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 ON — — — 31:16 — — — — — — CNSTYLE PORT32 — — 0000 — — — — — — — — — 0000 — — — — — — — — — — 0000 — — — — — — — — — — 0000 — — — — — — — — — — — — — — — — — — — — — CNIE0B[15:0] — — — — — — 15:0 — — 0000 CNSTATB[15:0] — — — — — — — 15:0 — — — — — — — — — — 0000 0000 CNIE1B[15:0] — 0000 — 15:0 — 0000 0000 CNPDB[15:0] — 0000 0000 CNPUB[15:0] — 0000 0000 ODCB[15:0] — 0000 0000 LATB[15:0] — 0000 FFFF RB[15:0] — 15:0 — 19/3 — 31:16 — 20/4 31:16 31:16 — 21/5 15:0 31:16 0000 22/6 15:0 31:16 — 23/7 15:0 31:16 — 24/8 15:0 31:16 — 25/9 15:0 31:16 16/0 26/10 15:0 31:16 17/1 27/11 ANSB[13:11] — 18/2 28/12 0000 0000 CNFB[15:0] DS60001387D-page 121 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. 2: The ANSB[13:11] and ANSB6 bits are not available on 48, 36 or 28-pin devices. 0000 0000 PIC32MM0256GPM064 FAMILY 2CF0 Bits All Resets 2CC0 PORTB REGISTER MAP Bit Range  2016-2019 Microchip Technology Inc. TABLE 10-6: Virtual Address (BF80_#) Register Name(1) 2DB0 ANSELC 2DD0 PORTC 2DE0 LATC 2DF0 ODCC 2E00 CNPUC 2E10 2E30 CNPDC CNCONC CNEN0C 2E40 CNSTATC  2016-2019 Microchip Technology Inc. 2E50 CNEN1C 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 — — — — — — 15:0 — — — — — — 31:16 — — — — — — 0000 0003 — — — — 0000 — — — — — 0000 — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — ANSC8(4) — — — 21/5 20/4 19/3 18/2 — — — — — ANSC5(4) — — — — — — — — — — — — — TRISC[15:0](3) — — — — — — — — FFFF RC[15:0](3) — — — — — — — — 0000 LATC[15:0](3) — — — — — — — — 0000 ODCC[15:0](3) — — — — — — — — 0000 CNPUC[15:0](3) 15:0 31:16 — ANSC[1:0](4) — 15:0 31:16 — — 22/6 15:0 31:16 — 23/7 15:0 31:16 16/0 24/8 15:0 31:16 17/1 All Resets TRISC Bit Range Bits 2DC0 2E20 PORTC REGISTER MAP — — — — — — — — — 0000 CNPDC[15:0](3) 15:0 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ON — — — CNSTYLE PORT32 — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 CNIE0C[15:0](3) 15:0 31:16 — — — — — — — — — — — — — — 0000 — — 0000 CNIE1C[15:0](3) 15:0 31:16 — CNSTATC[15:0](3) 15:0 31:16 — — — — — — — — — — 0000 2E60 CNFC Legend: Note 1: 2: 3: 4: 5: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. Bit[8] is not available on 28-pin devices; bit[5] is not available on 36 or 28-pin devices; bits[1:0] are not available on 28-pin devices. Bits[15:13] and bits[11:10] are not available on 48-pin devices; bits[15:10] and bits[7:5] are not available on 36-pin devices; bits[15:10] and bits[8:0] are not available on 28-pin devices. These bits are not available on 28-pin devices. Digital exclusions. 15:0 CNFC[15:0](3) 0000 PIC32MM0256GPM064 FAMILY DS60001387D-page 122 TABLE 10-7: Virtual Address (BF80_#) Register Name(2) 2EB0 ANSELD 2ED0 2EE0 2F00 2F10 2F20 2F30 2F40 2F50 2F60 2F70 DS60001387D-page 123 2F80 TRISD PORTD LATD ODCD CNPUD CNPDD CNCOND CNEN0D CNSTATD CNEN1D CNFD SR0D SR1D 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — — — — — 0000 TRISD[3:0](1) — — 030F RD[3:0](1) — — 0000 LATD[3:0](1) — — — 0000 ODCD[3:0](1) — — — 0000 CNPUD[3:0](1) — — — 0000 CNPDD[3:0](1) 0000 15:0 ON — — — CNSTYLE PORT32 — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: Bits[3:1] are not available on 48-pin devices; bits are not available on 36 and 28-pin devices. 2: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. CNIE0D[3:0](1) — — — 0000 CNSTATD[3:0](1) — — — 0000 CNIE1D[3:0](1) — — — 0000 CNFD[3:0](1) — — — 0000 SR0D[3:0](1) — — — SR1D[3:0](1) 0000 0000 PIC32MM0256GPM064 FAMILY 2EF0 Bits All Resets 2EC0 PORTD REGISTER MAP Bit Range  2016-2019 Microchip Technology Inc. TABLE 10-8: Virtual Address (BF80_#) Register Name(1) 2A00 RPCON 2A20 2A30 2A40 RPINR1 RPINR2 RPINR3 RPINR5 2A70 RPINR6 2A90 2AA0 RPINR7 RPINR8 RPINR9 2AB0 RPINR10  2016-2019 Microchip Technology Inc. 2AC0 RPINR11 2AD0 RPINR12 2B10 2B20 2B30 RPOR0 RPOR1 RPOR2 31/15 30/14 29/13 28/12 31:16 — — — 15:0 — — — 31:16 — — — 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — 0000 — IOLOCK — — — — — — — — — — — 0000 — — — — — — — — — — — — — 0000 15:0 31:16 — — — All Resets Bit Range Bits 2A60 2A80 PERIPHERAL PIN SELECT REGISTER MAP ICM2R[4:0] — — — INT4R[4:0] 0000 ICM1R[4:0] 0000 15:0 — — — — — — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — ICM3R[4:0] 31:16 — — — — — — OCFAR[4:0] 15:0 — — — — — 31:16 — — — — — 15:0 — — — TCKIBR[4:0] 31:16 — — — 15:0 — — 31:16 — OCFBR[4:0] 0000 0000 — — — — — — — — — — — — — — — — — — — TCKIAR[4:0] 0000 ICM8R[4:0] — — — ICM7R[4:0] 0000 — ICM6R[4:0] — — — ICM5R[4:0] — — U3RXR[4:0] — — — — — — ICM9R[4:0] — — — U2RXR[4:0] — — — — — — — — 0000 15:0 — — — 31:16 — — — 15:0 — — — 31:16 — — — 15:0 — — 31:16 — 15:0 — — — — — U2CTSR[4:0] — — — — — — — — — — — — 31:16 — — — 15:0 — — — 31:16 — — — 15:0 — — — 31:16 — — 15:0 — 31:16 15:0 — — — — — — 0000 — — — 0000 — 0000 — — 0000 0000 0000 — — — — — — — — — — 0000 — — — — — — — — — — — 0000 — — — — — — SS2INR[4:0] 0000 SCK2INR[4:0] — — — SDI2R[4:0] 0000 CLCINBR[4:0] — — — CLCINAR[4:0] — — — RP4R[4:0] — — — RP3R[4:0] 0000 RP2R[4:0] — — — RP1R[4:0] 0000 — RP8R[4:0] — — — RP7R[4:0] 0000 — — RP6R[4:0] — — — RP5R[4:0] 0000 — — — RP12R[4:0] — — — RP11R[4:0] 0000 — — — RP10R[4:0] — — — RP9R[4:0] 0000 U3RTSR[4:0] — — — — — — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. — — 0000 — — 0000 PIC32MM0256GPM064 FAMILY DS60001387D-page 124 TABLE 10-9: Virtual Address (BF80_#) Register Name(1) 2B40 RPOR3 2B50 2B60 PERIPHERAL PIN SELECT REGISTER MAP (CONTINUED) RPOR4 RPOR5 31/15 30/14 29/13 31:16 — — — 15:0 — — — 31:16 — — 15:0 — 31:16 15:0 28/12 27/11 26/10 25/9 24/8 20/4 23/7 22/6 21/5 RP16R[4:0] — — — RP15R[4:0] 0000 RP14R[4:0] — — — RP13R[4:0] 0000 — RP20R[4:0] — — — RP19R[4:0] 0000 — — RP18R[4:0] — — — RP17R[4:0] 0000 — — — RP24R[4:0] — — — RP23R[4:0] — — — RP22R[4:0] — — — — 19/3 — 18/2 — 17/1 16/0 All Resets Bits Bit Range  2016-2019 Microchip Technology Inc. TABLE 10-9: 0000 — — 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. PIC32MM0256GPM064 FAMILY DS60001387D-page 125 PIC32MM0256GPM064 FAMILY REGISTER 10-1: Bit Range 31:24 23:16 15:8 7:0 CNCONx: CHANGE NOTIFICATION CONTROL FOR PORTx REGISTER (x = A-D) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 ON — — — CNSTYLE PORT32 — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Change Notification (CN) Control On bit 1 = CN is enabled 0 = CN is disabled bit 14-12 Unimplemented: Read as ‘0’ bit 11 CNSTYLE: Change Notification Style Selection bit 1 = Edge style (detects edge transitions, CNFx bits are used for a Change Notice event) 0 = Mismatch style (detects change from last port read, CNSTATx bits are used for a Change Notification event) bit 10 PORT32: Merge Ports bit Maps the next higher GPIO’s control and status registers to the upper half, bits[31:16], of this port. 1 = Merging of this port and the next port is enabled 0 = Merging is disabled; all ports are accessed through their registers bit 9-0 Unimplemented: Read as ‘0’ DS60001387D-page 126  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 11.0 Note: TIMER1 PIC32MM0256GPM064 family devices feature one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. This timer can be clocked from different sources, such as the Peripheral Bus Clock (PBCLK), Secondary Oscillator (SOSC), T1CK pin or LPRC oscillator. This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Timers” (www.microchip.com/DS60001105) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. The following modes are supported by Timer1: • • • • Synchronous Internal Timer Synchronous Internal Gated Timer Synchronous External Timer Asynchronous External Timer The timer has a selectable clock prescaler and can operate in Sleep and Idle modes. FIGURE 11-1: TIMER1 BLOCK DIAGRAM PR1 Equal Trigger to ADC TSYNC 16-Bit Comparator 1 Reset T1IF Event Flag Sync TMR1 0 0 1 Q TGATE D TGATE Q TCS ON SOSC 00 T1CK 01 LPRC 10 TECS[1:0]  2016-2019 Microchip Technology Inc. x1 Gate Sync 10 PBCLK 00 Prescaler 1, 8, 64, 256 2 TCKPS[1:0] DS60001387D-page 127 Timer1 Control Register 8000 T1CON 8010 TMR1 8020 PR1 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — 15:0 ON — SIDL — — — — — TWDIS TWIP — 31:16 — — — — — — TECS[1:0] — 15:0 31:16 — 23/7 22/6 21/5 20/4 19/3 — — — — 2: 17/1 16/0 — — — 0000 TSYNC TCS — 0000 0000 — — TGATE — — — — — — — — — — — — — — — — TCKPS[1:0] TMR1[15:0] — — — — — 15:0 — — — — 0000 PR1[15:0](2) Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: 18/2 All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. PR1 values of ‘0’ and ‘1’ are reserved. All Resets TIMER1 REGISTER MAP Bit Range Register Name(1) Virtual Address (BF80_#) TABLE 11-1: 0000 FFFF PIC32MM0256GPM064 FAMILY DS60001387D-page 128 11.1  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 11-1: Bit Range 31:24 23:16 15:8 7:0 T1CON: TIMER1 CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 R/W-0 R-0 U-0 R/W-0 R/W-0 ON — SIDL TWDIS TWIP — R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 TGATE — — TSYNC TCS — TCKPS[1:0] TECS[1:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Timer1 On bit 1 = Timer1 is enabled 0 = Timer1 is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Timer1 Stop in Idle Mode bit 1 = Discontinues operation when device enters Idle mode 0 = Continues operation even in Idle mode bit 12 TWDIS: Asynchronous Timer1 Write Disable bit 1 = Writes to TMR1 are ignored until pending write operation completes 0 = Back-to-back writes are enabled (Legacy Asynchronous Timer mode functionality) bit 11 TWIP: Asynchronous Timer1 Write in Progress bit In Asynchronous Timer1 mode: 1 = Asynchronous write to TMR1 register is in progress 0 = Asynchronous write to TMR1 register is complete In Synchronous Timer1 mode: This bit is read as ‘0’. bit 10 Unimplemented: Read as ‘0’ bit 9-8 TECS[1:0]: Timer1 External Clock Selection bits 11 = Reserved 10 = External clock comes from the LPRC 01 = External clock comes from the T1CK Pin 00 = External clock comes from the Secondary Oscillator (SOSC) bit 7 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 6 Unimplemented: Read as ‘0’ bit 5-4 TCKPS[1:0]: Timer1 Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value  2016-2019 Microchip Technology Inc. DS60001387D-page 129 PIC32MM0256GPM064 FAMILY REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER (CONTINUED) bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Selection bit When TCS = 1: 1 = External clock input is synchronized 0 = External clock input is not synchronized When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = External clock is defined by the TECS[1:0] bits 0 = Internal peripheral clock bit 0 Unimplemented: Read as ‘0’ DS60001387D-page 130  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 12.0 Note: TIMER2 AND TIMER3 A single 32-bit synchronous timer is available by combining Timer2 with Timer3. The resulting 32-bit timer can operate in three modes: This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Timers” (www.microchip.com/DS60001105) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. • Synchronous Internal 32-Bit Timer • Synchronous Internal 32-Bit Gated Timer • Synchronous External 32-Bit 12.1 • • • • This family of PIC32 devices features four synchronous 16-bit timers (default) that can operate as a freerunning interval timer for various timing applications and counting external events. The following modes are supported: Additional Supported Features Selectable Clock Prescaler Timers Operational during CPU Idle ADC Event Trigger (only Timer3) Fast Bit Manipulation using CLR, SET and INV Registers • Synchronous Internal 16-Bit Timer • Synchronous Internal 16-Bit Gated Timer • Synchronous External 16-Bit Timer FIGURE 12-1: TIMER2 AND TIMER3 BLOCK DIAGRAM (TYPE A, 16-BIT) Sync TMRx ADC Event Trigger(1) Equal Comparator x 16 PRx Reset TxIF Event Flag 0 1 TGATE (TxCON[7]) Q TGATE (TxCON[7]) D Q TCS (TxCON[1]) ON (TxCON[15]) TxCK x 1 Gate Sync PBCLK 1 0 0 0 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON[6:4]) Note 1: ADC Event Trigger is only available on Timer3.  2016-2019 Microchip Technology Inc. DS60001387D-page 131 PIC32MM0256GPM064 FAMILY FIGURE 12-2: TIMER2/3 BLOCK DIAGRAM (TYPE B, 32-BIT) Data Bus[31:0] [31:0] Reset (Timer3 Only) TMRy Most Significant Half-Word ADC Event Trigger Equal Sync Least Significant Half-Word Comparator x 32 PRy TyIF Event Flag TMRx PRx 0 1 TGATE (TxCON[7]) Q TGATE (TxCON[7]) D Q TCS (TxCON[1]) ON (TxCON[15]) (Type B Timers Only) TxCK Note: x1 Gate Sync 10 TPBCLK 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON[6:4]) The timer configuration bit, T32 (T2CON[3]), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register and interrupt bits are respective to the T3CON register. DS60001387D-page 132  2016-2019 Microchip Technology Inc. Timer2/3 Control Registers 8040 T2CON 8050 TMR2 PR2 8080 T3CON 8090 TMR3 80A0 PR3 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — 15:0 ON 31:16 — — — — — — — — SIDL — — — — — — — — — — 15:0 31:16 23/7 22/6 — — — — TGATE — — 20/4 — — TCKPS[2:0] 2: 18/2 17/1 16/0 — — — — 0000 T32 — TCS — 0000 0000 — — — — — — — — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 0000 PR2[15:0](2) 31:16 — — — — — — — — — 15:0 ON — SIDL — — — — — TGATE 31:16 — — — — — — — — — 15:0 FFFF — — TCS — 0000 — TCKPS[2:0] — — — — — — 0000 — — — — — — — TMR3[15:0] — — — — — 15:0 — — — — 0000 PR3[15:0](2) Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: 19/3 TMR2[15:0] 15:0 31:16 21/5 All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. PR2 and PR3 values of ‘0’ and ‘1’ are reserved. All Resets Bits 0000 FFFF DS60001387D-page 133 PIC32MM0256GPM064 FAMILY 8060 TIMER2/3 REGISTER MAP Bit Range Register Name(1) TABLE 12-1: Virtual Address (BF80_#)  2016-2019 Microchip Technology Inc. 12.2 PIC32MM0256GPM064 FAMILY 12.3 Control Register REGISTER 12-1: Bit Range 31:24 23:16 15:8 7:0 T2CON: TIMER2 CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — R/W-0 (1,3) ON R/W-0 — — U-0 — R/W-0 (4) SIDL R/W-0 TGATE(3) R/W-0 — — — — — U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 (2) U-0 R/W-0 (3) U-0 TCKPS[2:0](3) T32 — TCS — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Timer2 On bit(1,3) 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Timer2 Stop in Idle Mode bit(4) 1 = Discontinues operation when device enters Idle mode 0 = Continues operation when device is in Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 TGATE: Timer Gated Time Accumulation Enable bit(3) When TCS = 1: This bit is ignored and is read as ‘0’. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 6-4 TCKPS[2:0]: Timer Input Clock Prescale Select bits(3) 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value Note 1: The user’s software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. This bit is only available on even numbered timers (Timer2). While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1). All timer functions are set through the even numbered timers. While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode. 2: 3: 4: DS60001387D-page 134  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 12-1: T2CON: TIMER2 CONTROL REGISTER (CONTINUED) bit 3 T32: 32-Bit Timer Mode Select bit(2) 1 = Odd numbered and even numbered timers form a 32-bit timer 0 = Odd numbered and even numbered timers form a separate 16-bit timer bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer Clock Source Select bit(3) 1 = External clock from T2CK pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as ‘0’ Note 1: The user’s software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. This bit is only available on even numbered timers (Timer2). While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1). All timer functions are set through the even numbered timers. While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode. 2: 3: 4:  2016-2019 Microchip Technology Inc. DS60001387D-page 135 PIC32MM0256GPM064 FAMILY REGISTER 12-2: Bit Range 31:24 23:16 15:8 7:0 T3CON: TIMER3 CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ON — SIDL — — — — — R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — — TCS — TGATE TCKPS[2:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Timer3 On bit 1 = Timer3 is enabled 0 = Timer3 is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Timer3 Stop in Idle Mode bit 1 = Discontinues operation when device enters Idle mode 0 = Continues operation even in Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 TGATE: Timer3 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 6-4 TCKPS[2:0]: Timer3 Input Clock Prescale Select bits 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer3 Clock Source Select bit 1 = External clock is from the T3CK pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as ‘0’ DS60001387D-page 136  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 13.0 WATCHDOG TIMER (WDT) Note: Some of the key features of the WDT module are: • Configuration or Software Controlled • User-Configurable Time-out Period • Different Time-out Periods for Run and Sleep/Idle modes • Operates from LPRC Oscillator in Sleep/Idle modes • Different Clock Sources for Run mode • Can Wake the Device from Sleep or Idle This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 62. “Dual Watchdog Timer” (www.microchip.com/DS60001365) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. EXAMPLE 13-1: When enabled, the Watchdog Timer (WDT) can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode. FIGURE 13-1: WATCHDOG TIMER CODE unsigned short *pWdtClr; // 16-bit variable // create a pointer to the upper half of WDTCON pWdtClr = (unsigned short*)&WDTCON + 1; main() { ...user code *pWdtClr = 0x5743; } // clear the WDT WATCHDOG TIMER BLOCK DIAGRAM Power Save Mode WDT LPRC Oscillator Power Save CLKSEL[1:0] SYSCLK Reserved FRC Oscillator LPRC Oscillator ON 25-Bit Counter Power Save Reset Comparator Wake-up and NMI SLPDIV[4:0] Run Mode WDT 00 01 Power Save 25-Bit Counter Comparator NMI and Start NMI Counter 10 11 Reset RUNDIV[4:0] WDTCLRKEY[15:0] = 5743h ON All Resets Any System Clock Switch  2016-2019 Microchip Technology Inc. DS60001387D-page 137 Watchdog Timer Control Registers Virtual Address (BF80_#) Register Name TABLE 13-1: 3990 WDTCON(1) WATCHDOG TIMER REGISTER MAP 31/15 30/14 29/13 ON — — 28/12 27/11 26/10 31:16 15:0 25/9 24/8 23/7 22/6 21/5 19/3 WDTCLRKEY[15:0] RUNDIV[4:0] CLKSEL[1:0] Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: 20/4 This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. 18/2 17/1 16/0 All Resets Bit Range Bits 0000 SLPDIV[4:0] WDTWINEN xxxx PIC32MM0256GPM064 FAMILY DS60001387D-page 138 13.1  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 13-1: Bit Range 31:24 23:16 15:8 7:0 WDTCON: WATCHDOG TIMER CONTROL REGISTER Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 R-y R-y R-y W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 WDTCLRKEY[15:8] W-0 WDTCLRKEY[7:0] R/W-0 (1) U-0 — — R-y R-y R-y ON U-0 CLKSEL[1:0] R-y R-y R-y R-y RUNDIV[4:0] R-y R-y SLPDIV[4:0] R/W-y WDTWINEN Legend: y = Values set from Configuration bits on Reset R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 WDTCLRKEY[15:0]: Watchdog Timer Clear Key bits To clear the Watchdog Timer to prevent a time-out, software must write the value, 0x5743, to the upper 16 bits of this register address using a single 16-bit write. bit 15 ON: Watchdog Timer Enable bit(1) 1 = The WDT is enabled 0 = The WDT is disabled bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 RUNDIV[4:0]: Shadow Copy of Watchdog Timer Postscaler Value for Run Mode from Configuration bits On Reset, these bits are set to the values of the RWDTPS[4:0] Configuration bits in FWDT. bit 7-6 CLKSEL[1:0]: Shadow Copy of Watchdog Timer Clock Selection Value for Run Mode from Configuration bits On Reset, these bits are set to the values of the RCLKSEL[1:0] Configuration bits in FWDT. bit 5-1 SLPDIV[4:0]: Shadow Copy of Watchdog Timer Postscaler Value for Sleep/Idle Mode from Configuration bits On Reset, these bits are set to the values of the SWDTPS[4:0] Configuration bits in FWDT. bit 0 WDTWINEN: Watchdog Timer Window Enable bit On Reset, this bit is set to the inverse of the value of the WINDIS Configuration bit in FWDT. 1 = Windowed mode is enabled 0 = Windowed mode is disabled Note 1: This bit only has control when FWDTEN (FWDT[15]) = 0.  2016-2019 Microchip Technology Inc. DS60001387D-page 139 PIC32MM0256GPM064 FAMILY NOTES: DS60001387D-page 140  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 14.0 Note: 14.1 CAPTURE/COMPARE/PWM/ TIMER MODULES (MCCP AND SCCP) This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 30. “Capture/Compare/PWM/ Timer (MCCP and SCCP)” (www.microchip.com/DS60001381) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. Introduction PIC32MM0256GPM064 family devices include nine Capture/Compare/PWM/Timer (CCP) modules. These modules are similar to the multipurpose timer modules found on many other 32-bit microcontrollers. They also provide the functionality of the comparable input capture, output compare and general purpose timer peripherals found in all earlier PIC32 devices. CCP modules can operate in one of three major modes: • General Purpose Timer • Input Capture • Output Compare/PWM There are two different forms of the module, distinguished by the number of PWM outputs that the module can generate. Single Capture/Compare/PWM/Timer (SCCPs) output modules provide only one PWM output. Multiple Capture/Compare/PWM/Timer (MCCPs) output modules can provide up to six outputs and an extended range of output control features, depending on the pin count of the particular device. All modules (SCCP and MCCP) include these features: • User-Selectable Clock Inputs, including System Clock and External Clock Input Pins • Input Clock Prescaler for Time Base • Output Postscaler for module Interrupt Events or Triggers • Synchronization Output Signal for coordinating other MCCP/SCCP modules with  User-Configurable Alternate and Auxiliary Source Options  2016-2019 Microchip Technology Inc. • Fully Asynchronous Operation in all modes and in Low-Power Operation • Special Output Trigger for ADC Conversions • 16-Bit and 32-Bit General Purpose Timer modes with Optional Gated Operation for Simple Time Measurements • Capture modes: - Backward compatible with previous input capture peripherals of the PIC32 family - 16-bit or 32-bit capture of time base on  external event - Up to four-level deep FIFO capture buffer - Capture source input multiplexer - Gated capture operation to reduce  noise-induced false captures • Output Compare/PWM modes: - Backward compatible with previous output compare peripherals of the PIC32 family - Single Edge and Dual Edge Compare modes - Center-Aligned Compare mode MCCP modules also include these extended PWM  features: • • • • • • • • Single Output Steerable mode Brush DC Motor (Forward and Reverse) modes Half-Bridge with Dead-Time Delay mode Push-Pull PWM mode Output Scan mode Center-Aligned Compare mode Variable Frequency Pulse mode Auto-Shutdown with Programmable Source and Shutdown State • Programmable Output Polarity The SCCP and MCCP modules can be operated in only one of the three major modes (Capture, Compare or Timer) at any time. The other modes are not available unless the module is reconfigured. A conceptual block diagram for the module is shown in Figure 14-1. All three modes use the time base generator and the common Timer register pair (CCPxTMR). Other shared hardware components, such as comparators and buffer registers, are activated and used as a particular mode requires. Table 14-2 summarizes the various Output Compare modes. DS60001387D-page 141 PIC32MM0256GPM064 FAMILY TABLE 14-1: OUTPUT COMPARE/PWM MODES T32 MOD[3:0] 0 1 0 1 0 1 0 0 0 0 0001 0001 0010 0010 0011 0011 0100 0101 0110 0111 FIGURE 14-1: Operating Mode Output High on Compare (16-bit), Single Edge mode Output High on Compare (32-bit), Single Edge mode Output Low on Compare (16-bit), Single Edge mode Output Low on Compare (32-bit), Single Edge mode Output Toggle on Compare (16-bit), Single Edge mode Output Toggle on Compare (32-bit), Single Edge mode Dual Edge Compare (16-bit), Dual Edge mode Dual Edge Compare (16-bit buffered), PWM mode Center-Aligned Pulse (16-bit buffered), Center PWM mode Variable Frequency Pulse (16-bit) MCCP/SCCP CONCEPTUAL BLOCK DIAGRAM CCPxIF CCTxIF External Capture Input Input Capture CCP Sync Out Special Event Trigger Out (ADC) Auxiliary Output Clock Sources Time Base Generator CCPxTMR T32 CCSEL MOD[3:0] Compare/PWM Output(s) Output Compare/ Sync and Gating Sources 16/32-Bit PWM Timer OCFA/OCFB 14.2 Registers Each MCCP/SCCP module has up to seven control and status registers: • CCPxCON1 (Register 14-1) controls many of the features common to all modes, including input clock selection, time base prescaling, timer synchronization, Trigger mode operations and postscaler selection for all modes. The module is also enabled and the operational mode is selected from this register. • CCPxCON2 (Register 14-2) controls auto- shutdown and restart operation, primarily for PWM operations, and also configures other input capture and output compare features, and  configures auxiliary output operation. DS60001387D-page 142 • CCPxCON3 (Register 14-3) controls multiple  output PWM dead time, controls the output of the output compare and PWM modes, and configures the PWM Output mode for the MCCP modules. • CCPxSTAT (Register 14-4) contains read-only status bits showing the state of module operations. Each module also includes eight buffer/counter registers that serve as Timer Value registers or data holding buffers: • CCPxTMR is the 32-Bit Timer/Counter register • CCPxPR is the 32-Bit Timer Period register • CCPxR is the 32-bit primary data buffer for output compare operations • CCPxBUF(H/L) is the 32-Bit Buffer register pair, which is used in input capture FIFO operations  2016-2019 Microchip Technology Inc. 0100 CCP1CON1 0110 CCP1CON2 0120 CCP1CON3 0130 CCP1STAT 0150 0160 0170 0180 CCP1TMR CCP1PR CCP1RA CCP1RB CCP1BUF 0200 CCP2CON1 0210 CCP2CON2 0220 CCP2CON3 0230 CCP2STAT DS60001387D-page 143 0240 0250 CCP2TMR CCP2PR 31/15 30/14 31:16 OPSSRC RTRGEN — 15:0 ON — SIDL — OCFEN OCEEN OCDEN OCCEN OCBEN OCAEN — SSDG — — — — 31:16 OENSYNC 29/13 15:0 PWMRSEN ASDGM 28/12 27/11 — 26/10 24/8 23/7 OPS[3:0] CCPSLP TMRSYNC OSCNT[2:0] 25/9 TRIGEN CLKSEL[2:0] 31:16 OETRIG 15:0 — — — — — — — 31:16 — — — — — — 15:0 — — — — — ICGARM — 22/6 21/5 20/4 19/3 18/2 ONESHOT ALTSYNC TMRPS[1:0] T32 ICGSM[1:0] — 17/1 16/0 SYNC[4:0] CCSEL 0000 MOD[3:0] AUXOUT[1:0] 0000 ICS[2:0] 0100 ASDG[7:0] OUTM[2:0] POLACE POLBDF All Resets Bits 0000 — — PSSACE[1:0] PSSBDF[1:0] — — — — — — — — r r r r r 0000 — — CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE 0000 DT[5:0] 0000 0000 31:16 TMRH[15:0] 0000 15:0 TMRL[15:0] 0000 31:16 PRH[15:0] 0000 15:0 PRL[15:0] 31:16 — — — — — — — — 15:0 31:16 — 0000 — — — — — — — — — — — — — — CMPA[15:0] — — — — — — — — — 0000 0000 0000 15:0 CMPB[15:0] 0000 31:16 BUFH[15:0] 0000 15:0 BUFL[15:0] 31:16 OPSSRC RTRGEN — 15:0 ON — SIDL — OCFEN OCEEN OCDEN OCCEN OCBEN OCAEN — SSDG — — — — 31:16 OENSYNC 15:0 PWMRSEN ASDGM — OPS[3:0] CCPSLP TMRSYNC OSCNT[2:0] TRIGEN CLKSEL[2:0] 31:16 OETRIG 15:0 — — — — — — — 31:16 — — — — — — 15:0 — — — — — ICGARM — OUTM[2:0] 0000 ONESHOT ALTSYNC TMRPS[1:0] T32 ICGSM[1:0] — SYNC[4:0] CCSEL 0000 MOD[3:0] AUXOUT[1:0] 0000 ICS[2:0] 0100 ASDG[7:0] POLACE POLBDF 0000 — — PSSACE[1:0] PSSBDF[1:0] — — — — — — — — r r r r r 0000 — — CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE 0000 DT[5:0] 0000 0000 31:16 TMRH[15:0] 0000 15:0 TMRL[15:0] 0000 31:16 PRH[15:0] 0000 15:0 PRL[15:0] 0000 Legend: — = unimplemented, read as ‘0’; r = reserved bit. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. PIC32MM0256GPM064 FAMILY 0140 MCCP/SCCP REGISTER MAP Bit Range Register Name(1) Virtual Address (BF80_#)  2016-2019 Microchip Technology Inc. TABLE 14-2: 0270 0280 CCP2RB CCP2BUF 0300 CCP3CON1 0310 CCP3CON2 0320 CCP3CON3 0330 CCP3STAT 0340 0350 0360 0370  2016-2019 Microchip Technology Inc. 0380 CCP3TMR CCP3PR CCP3RA CCP3RB CCP3BUF 0400 CCP4CON1 0410 CCP4CON2 0420 CCP4CON3 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — — — — 15:0 31:16 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Register Name(1) CCP2RA Bits Bit Range Virtual Address (BF80_#) 0260 MCCP/SCCP REGISTER MAP (CONTINUED) — — — — — — — — 0000 — — — — — — — CMPA[15:0] — — — — — — — — — 0000 0000 15:0 CMPB[15:0] 0000 31:16 BUFH[15:0] 0000 15:0 BUFL[15:0] 31:16 OPSSRC RTRGEN — 15:0 ON — SIDL — OCFEN OCEEN OCDEN OCCEN OCBEN OCAEN — SSDG — — — — 31:16 OENSYNC 15:0 PWMRSEN ASDGM — OPS[3:0] CCPSLP TMRSYNC OSCNT[2:0] TRIGEN CLKSEL[2:0] 31:16 OETRIG 15:0 — — — — — — — 31:16 — — — — — — 15:0 — — — — — ICGARM — 0000 ONESHOT ALTSYNC TMRPS[1:0] T32 ICGSM[1:0] — SYNC[4:0] CCSEL 0000 MOD[3:0] AUXOUT[1:0] 0000 ICS[2:0] 0100 ASDG[7:0] OUTM[2:0] POLACE POLBDF 0000 — — PSSACE[1:0] PSSBDF[1:0] — — — — — — — — r r r r r 0000 — — CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE 0000 DT[5:0] 0000 0000 31:16 TMRH[15:0] 0000 15:0 TMRL[15:0] 0000 31:16 PRH[15:0] 0000 15:0 PRL[15:0] 31:16 — — — — — — — — 15:0 31:16 — 0000 — — — — — — — — — — — — — — CMPA[15:0] — — — — — — — — — 0000 0000 0000 15:0 CMPB[15:0] 0000 31:16 BUFH[15:0] 0000 15:0 BUFL[15:0] 0000 31:16 OPSSRC RTRGEN — 15:0 ON — SIDL — — — — — — OCAEN — SSDG — — — — — — — — — — POLACE — PSSACE[1:0] — — 0000 — — — — — — — — — — — 0000 31:16 OENSYNC 15:0 PWMRSEN ASDGM 31:16 OETRIG 15:0 — — CCPSLP TMRSYNC OSCNT[2:0] — — OPS[3:0] — TRIGEN CLKSEL[2:0] ONESHOT ALTSYNC TMRPS[1:0] T32 ICGSM[1:0] — SYNC CCSEL 0000 MOD[3:0] AUXOUT[1:0] 0000 ICS[2:0] 0100 ASDG[7:0] Legend: — = unimplemented, read as ‘0’; r = reserved bit. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. 0000 — PIC32MM0256GPM064 FAMILY DS60001387D-page 144 TABLE 14-2: 0440 0450 0460 0480 CCP4PR CCP4RA CCP4RB CCP4BUF 0500 CCP5CON1 0510 CCP5CON2 0520 CCP5CON3 0530 CCP5STAT 0540 0550 0560 DS60001387D-page 145 0570 0580 CCP5TMR CCP5PR CCP5RA CCP5RB CCP5BUF 31/15 30/14 29/13 28/12 27/11 31:16 — — — — 15:0 — — — — 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 — — — — — — — r r r — ICGARM — — CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS 16/0 r r 0000 ICOV ICBNE 0000 17/1 31:16 TMRH[15:0] 0000 15:0 TMRL[15:0] 0000 31:16 PRH[15:0] 0000 15:0 PRL[15:0] 31:16 — — — — — — — — 15:0 31:16 — 0000 — — — — — — — — — — — — — — CMPA[15:0] — — — — — — — — — 0000 0000 0000 15:0 CMPB[15:0] 0000 31:16 BUFH[15:0] 0000 15:0 BUFL[15:0] 0000 31:16 OPSSRC RTRGEN — 15:0 ON — SIDL — OCFEN OCEEN OCDEN OCCEN OCBEN OCAEN — SSDG — — — — — — — — — — POLACE — PSSACE[1:0] — — 0000 31:16 OENSYNC 15:0 PWMRSEN ASDGM — OPS[3:0] CCPSLP TMRSYNC OSCNT[2:0] TRIGEN CLKSEL[2:0] ONESHOT ALTSYNC TMRPS[1:0] T32 ICGSM[1:0] — SYNC[4:0] CCSEL 0000 MOD[3:0] AUXOUT[1:0] 0000 ICS[2:0] 0100 ASDG[7:0] 0000 31:16 OETRIG 15:0 — — — — — — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — r r r r r 0000 15:0 — — — — — ICGARM — — CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE 0000 31:16 TMRH[15:0] 0000 15:0 TMRL[15:0] 0000 31:16 PRH[15:0] 0000 15:0 PRL[15:0] 31:16 — — — — — — — — 15:0 31:16 — 0000 — — — — — — — — — — — — — — CMPA[15:0] — — — — — — — — — 0000 0000 0000 15:0 CMPB[15:0] 0000 31:16 BUFH[15:0] 0000 15:0 BUFL[15:0] 0000 Legend: — = unimplemented, read as ‘0’; r = reserved bit. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. PIC32MM0256GPM064 FAMILY 0470 CCP4TMR Bits All Resets 0430 CCP4STAT MCCP/SCCP REGISTER MAP (CONTINUED) Bit Range Register Name(1) Virtual Address (BF80_#)  2016-2019 Microchip Technology Inc. TABLE 14-2: 0610 CCP6CON2 0620 CCP6CON3 0630 CCP6STAT 0640 0650 0660 0670 0680 CCP6TMR CCP6PR CCP6RA CCP6RB CCP6BUF 0700 CCP7CON1 0710 CCP7CON2  2016-2019 Microchip Technology Inc. 0720 CCP7CON3 0730 CCP7STAT 0740 0750 CCP7TMR CCP7PR Bits 31/15 30/14 31:16 OPSSRC RTRGEN — 15:0 ON — SIDL — OCFEN OCEEN OCDEN OCCEN OCBEN OCAEN — SSDG — — — — — — — — — — POLACE — PSSACE[1:0] — — 0000 31:16 OENSYNC 29/13 15:0 PWMRSEN ASDGM 28/12 27/11 — 26/10 24/8 23/7 OPS[3:0] CCPSLP TMRSYNC OSCNT[2:0] 25/9 TRIGEN CLKSEL[2:0] 22/6 21/5 20/4 19/3 ONESHOT ALTSYNC TMRPS[1:0] T32 ICGSM[1:0] — 18/2 17/1 16/0 SYNC[4:0] CCSEL 0000 MOD[3:0] AUXOUT[1:0] All Resets Bit Range Register Name(1) Virtual Address (BF80_#) 0600 CCP6CON1 MCCP/SCCP REGISTER MAP (CONTINUED) 0000 ICS[2:0] 0100 ASDG[7:0] 0000 31:16 OETRIG 15:0 — — — — — — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — r r r r r 0000 15:0 — — — — — ICGARM — — CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE 0000 31:16 TMRH[15:0] 0000 15:0 TMRL[15:0] 0000 31:16 PRH[15:0] 0000 15:0 PRL[15:0] 31:16 — — — — — — — — 15:0 31:16 — 0000 — — — — — — — — — — — — — — CMPA[15:0] — — — — — — — — — 0000 0000 0000 15:0 CMPB[15:0] 0000 31:16 BUFH[15:0] 0000 15:0 BUFL[15:0] 0000 31:16 OPSSRC RTRGEN — 15:0 ON — SIDL — OCFEN OCEEN OCDEN OCCEN OCBEN OCAEN — SSDG — — — — — — — — — — POLACE — PSSACE[1:0] — — 0000 31:16 OENSYNC 15:0 PWMRSEN ASDGM — OPS[3:0] CCPSLP TMRSYNC OSCNT[2:0] TRIGEN CLKSEL[2:0] ONESHOT ALTSYNC TMRPS[1:0] T32 ICGSM[1:0] — SYNC[4:0] CCSEL 0000 MOD[3:0] AUXOUT[1:0] 0000 ICS[2:0] 0100 ASDG[7:0] 0000 31:16 OETRIG 15:0 — — — — — — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — r r r r r 0000 15:0 — — — — — ICGARM — — CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE 0000 31:16 TMRH[15:0] 0000 15:0 TMRL[15:0] 0000 31:16 PRH[15:0] 0000 15:0 PRL[15:0] 0000 Legend: — = unimplemented, read as ‘0’; r = reserved bit. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. PIC32MM0256GPM064 FAMILY DS60001387D-page 146 TABLE 14-2: CCP7RA 0770 0780 CCP7RB CCP7BUF 0800 CCP8CON1 0820 CCP8CON3 0830 CCP8STAT 0840 0850 0860 0870 0880 CCP8TMR CCP8PR CCP8RA CCP8RB CCP8BUF 0900 CCP9CON1 DS60001387D-page 147 0910 CCP9CON2 0920 CCP9CON3 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — — — — 15:0 31:16 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — 0000 — — — — — — — CMPA[15:0] — — — — — — — — — 0000 0000 15:0 CMPB[15:0] 0000 31:16 BUFH[15:0] 0000 15:0 BUFL[15:0] 0000 31:16 OPSSRC RTRGEN — 15:0 ON — SIDL — OCFEN OCEEN OCDEN OCCEN OCBEN OCAEN — SSDG — — — — — — — — — — POLACE — PSSACE[1:0] — — 0000 31:16 OENSYNC 15:0 PWMRSEN ASDGM — OPS[3:0] CCPSLP TMRSYNC OSCNT[2:0] TRIGEN CLKSEL[2:0] ONESHOT ALTSYNC TMRPS[1:0] T32 ICGSM[1:0] — SYNC[4:0] CCSEL 0000 MOD[3:0] AUXOUT[1:0] 0000 ICS[2:0] 0100 ASDG[7:0] 0000 31:16 OETRIG 15:0 — — — — — — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — r r r r r 0000 15:0 — — — — — ICGARM — — CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE 0000 31:16 TMRH[15:0] 0000 15:0 TMRL[15:0] 0000 31:16 PRH[15:0] 0000 15:0 PRL[15:0] 31:16 — — — — — — — — 15:0 31:16 — 0000 — — — — — — — — — — — — — — CMPA[15:0] — — — — — — — — — 0000 0000 0000 15:0 CMPB[15:0] 0000 31:16 BUFH[15:0] 0000 15:0 BUFL[15:0] 0000 31:16 OPSSRC RTRGEN — 15:0 ON — SIDL — OCFEN OCEEN OCDEN OCCEN OCBEN OCAEN — SSDG — — — — — — — — — — POLACE — PSSACE[1:0] — — 0000 — — — — — — — — — — — 0000 31:16 OENSYNC 15:0 PWMRSEN ASDGM 31:16 OETRIG 15:0 — — CCPSLP TMRSYNC OSCNT[2:0] — — OPS[3:0] — TRIGEN CLKSEL[2:0] ONESHOT ALTSYNC TMRPS[1:0] T32 ICGSM[1:0] — SYNC[4:0] CCSEL 0000 MOD[3:0] AUXOUT[1:0] 0000 ICS[2:0] 0100 ASDG[7:0] Legend: — = unimplemented, read as ‘0’; r = reserved bit. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. 0000 — PIC32MM0256GPM064 FAMILY 0810 CCP8CON2 Bits All Resets Register Name(1) 0760 MCCP/SCCP REGISTER MAP (CONTINUED) Bit Range Virtual Address (BF80_#)  2016-2019 Microchip Technology Inc. TABLE 14-2: 0940 0950 0960 0970 0980 CCP9TMR CCP9PR CCP9RA CCP9RB CCP9BUF 31/15 30/14 29/13 28/12 27/11 31:16 — — — — 15:0 — — — — 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 — — — — — — — r r r — ICGARM — — CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS 16/0 All Resets Bits Bit Range Register Name(1) Virtual Address (BF80_#) 0930 CCP9STAT MCCP/SCCP REGISTER MAP (CONTINUED) r r 0000 ICOV ICBNE 0000 17/1 31:16 TMRH[15:0] 0000 15:0 TMRL[15:0] 0000 31:16 PRH[15:0] 0000 15:0 PRL[15:0] 31:16 — — — — — — — — 15:0 31:16 — 0000 — — — — — — — — — — — — — — CMPA[15:0] — — — — — — — — — 0000 0000 0000 15:0 CMPB[15:0] 0000 31:16 BUFH[15:0] 0000 15:0 BUFL[15:0] 0000 Legend: — = unimplemented, read as ‘0’; r = reserved bit. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. PIC32MM0256GPM064 FAMILY DS60001387D-page 148 TABLE 14-2:  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 14-1: CCPxCON1: CAPTURE/COMPARE/PWMx CONTROL 1 REGISTER Bit Range Bit 31/23/15/7 31:24 23:16 15:8 7:0 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 OPSSRC(1) RTRGEN(2) — — R/W-0 OPS[3:0](3) R/W-0 R/W-0 R/W-0 TRIGEN ONESHOT ALTSYNC R/W-0 (1) U-0 R/W-0 R/W-0 R/W-0 — SIDL CCPSLP TMRSYNC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T32 CCSEL ON TMRPS[1:0] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SYNC[4:0] R/W-0 CLKSEL[2:0] R/W-0 R/W-0 R/W-0 MOD[3:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31 OPSSRC: Output Postscaler Source Select bit(1) 1 = Output postscaler scales the Special Event Trigger output events 0 = Output postscaler scales the timer interrupt events bit 30 RTRGEN: Retrigger Enable bit(2) 1 = Time base can be retriggered when CCPTRIG = 1 0 = Time base may not be retriggered when CCPTRIG = 1 x = Bit is unknown bit 29-28 Unimplemented: Read as ‘0’ bit 27-24 OPS[3:0]: CCPx Interrupt Output Postscale Select bits(3) 1111 = Interrupt every 16th time base period match 1110 = Interrupt every 15th time base period match ... 0100 = Interrupt every 5th time base period match 0011 = Interrupt every 4th time base period match or 4th input capture event 0010 = Interrupt every 3rd time base period match or 3rd input capture event 0001 = Interrupt every 2nd time base period match or 2nd input capture event 0000 = Interrupt after each time base period match or input capture event bit 23 TRIGEN: CCPx Triggered Enable bit 1 = Triggered operation of the timer is enabled 0 = Triggered operation of the timer is disabled bit 22 ONESHOT: One-Shot Mode Enable bit 1 = One-Shot Triggered mode is enabled; trigger duration is set by OSCNT[2:0] 0 = One-Shot Triggered mode is disabled bit 21 ALTSYNC: CCPx Clock Select bit 1 = An alternate signal is used as the module synchronization output signal 0 = The module synchronization output signal is the Time Base Reset/rollover event Note 1: 2: 3: This control bit has no function in Input Capture modes. This control bit has no function when TRIGEN = 0. Values greater than ‘0011’ will cause a FIFO buffer overflow in Input Capture mode.  2016-2019 Microchip Technology Inc. DS60001387D-page 149 PIC32MM0256GPM064 FAMILY REGISTER 14-1: CCPxCON1: CAPTURE/COMPARE/PWMx CONTROL 1 REGISTER (CONTINUED) bit 20-16 SYNC[4:0]: CCPx Synchronization Source Select bits 11111 = Off 11110 = Reserved ... 11100 = Reserved 11011 = Time base is synchronized to the start of ADC conversion 11010 = Time base is synchronized to Comparator 3 11001 = Time base is synchronized to Comparator 2 11000 = Time base is synchronized to Comparator 1 10111 = Reserved ... 10010 = Reserved 10011 = Time base is synchronized to CLC4 10010 = Time base is synchronized to CLC3 10001 = Time base is synchronized to CLC2 10001 = Time base is synchronized to CLC1 01111 = Time base is synchronized to SCCP9 01110 = Time base is synchronized to SCCP8 01101 = Time base is synchronized to the INT4 Pin (Remappable) 01100 = Time base is synchronized to the INT3 Pin 01011 = Time base is synchronized to the INT2 Pin 01010 = Time base is synchronized to the INT1 Pin 01001 = Time base is synchronized to the INT0 Pin 01000 = Reserved ... 00101 = Reserved 00100 = Time base is synchronized to SCCP3 00011 = Time base is synchronized to SCCP2 00010 = Time base is synchronized to MCCP1 00001 = Time base is synchronized to this MCCP/SCCP 00000 = No external synchronization; timer rolls over at FFFFh or matches with the Timer Period register bit 15 ON: CCPx Module Enable bit(1) 1 = Module is enabled with the operating mode specified by the MOD[3:0] bits 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: CCPx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 CCPSLP: CCPx Sleep Mode Enable bit 1 = Module continues to operate in Sleep modes 0 = Module does not operate in Sleep modes bit 11 TMRSYNC: Time Base Clock Synchronization bit 1 = Module time base clock is synchronized to internal system clocks; timing restrictions apply 0 = Module time base clock is not synchronized to internal system clocks Note 1: 2: 3: This control bit has no function in Input Capture modes. This control bit has no function when TRIGEN = 0. Values greater than ‘0011’ will cause a FIFO buffer overflow in Input Capture mode. DS60001387D-page 150  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 14-1: CCPxCON1: CAPTURE/COMPARE/PWMx CONTROL 1 REGISTER (CONTINUED) bit 10-8 CLKSEL[2:0]: CCPx Time Base Clock Select bits 111 = TCKIA pin (remappable) 110 = TCKIB pin (remappable) 101 = Reserved 100 = Reserved 011 = CLC1 output for MCCP1 CLC2 output for MCCP2 CLC3 output for MCCP3 CLC1 output for SCCP4 CLC2 output for SCCP5 CLC3 output for SCCP6 CLC4 output for SCCP7 CLC1 output for SCCP8 CLC1 output for SCCP9 010 = Secondary Oscillator (SOSC) clock 001 = REFO1 output clock 000 = System clock (TCY) bit 7-6 TMRPS[1:0]: CCPx Time Base Prescale Select bits 11 = 1:64 prescaler 10 = 1:16 prescaler 01 = 1:4 prescaler 00 = 1:1 prescaler bit 5 T32: 32-Bit Time Base Select bit 1 = 32-bit time base for timer, single edge output compare or input capture function 0 = 16-bit time base for timer, single edge output compare or input capture function bit 4 CCSEL: Capture/Compare Mode Select bit 1 = Input Capture mode 0 = Output Compare/PWM or Timer mode (exact function is selected by the MOD[3:0] bits) bit 3-0 MOD[3:0]: CCPx Mode Select bits CCSEL = 1 (Input Capture modes): 1xxx = Reserved 011x = Reserved 0101 = Capture every 16th rising edge 0100 = Capture every 4th rising edge 0011 = Capture every rising and falling edge 0010 = Capture every falling edge 0001 = Capture every rising edge 0000 = Capture every rising and falling edge (Edge Detect mode) CCSEL = 0 (Output Compare modes): 1111 = External Input mode: Pulse generator is disabled, source is selected by ICS[2:0] 1110 = Reserved 110x = Reserved 10xx = Reserved 0111 = Variable Frequency Pulse mode 0110 = Center-Aligned Pulse Compare mode, buffered 0101 = Dual Edge Compare mode, buffered 0100 = Dual Edge Compare mode 0011 = 16-Bit/32-Bit Single Edge mode: Toggles output on compare match 0010 = 16-Bit/32-Bit Single Edge mode: Drives output low on compare match 0001 = 16-Bit/32-Bit Single Edge mode: Drives output high on compare match 0000 = 16-Bit/32-Bit Timer mode: Output functions are disabled Note 1: 2: 3: This control bit has no function in Input Capture modes. This control bit has no function when TRIGEN = 0. Values greater than ‘0011’ will cause a FIFO buffer overflow in Input Capture mode.  2016-2019 Microchip Technology Inc. DS60001387D-page 151 PIC32MM0256GPM064 FAMILY REGISTER 14-2: Bit Range 31:24 23:16 15:8 7:0 CCPxCON2: CAPTURE/COMPARE/PWMx CONTROL 2 REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 OENSYNC — OCFEN(1) OCEEN(1) OCDEN(1) OCCEN(1) OCBEN(1) OCAEN R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ICGSM[1:0] — AUXOUT[1:0] ICS[2:0] R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 PWMRSEN ASDGM — SSDG — — — U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ASDG[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31 OENSYNC: Output Enable Synchronization bit 1 = Update by output enable bits occurs on the next Time Base Reset or rollover 0 = Update by output enable bits occurs immediately bit 30 Unimplemented: Read as ‘0’ x = Bit is unknown bit 29-24 OC[F:A]EN: Output Enable/Steering Control bits(1) 1 = OCx pin is controlled by the CCPx module and produces an output compare or PWM signal 0 = OCx pin is not controlled by the CCPx module; the pin is available to the port logic or another peripheral multiplexed on the pin bit 23-22 ICGSM[1:0]: Input Capture Gating Source Mode Control bits 11 = Reserved 10 = One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1) 01 = One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0) 00 = Level-Sensitive mode: A high level from gating source will enable future capture events; a low level will disable future capture events bit 21 Unimplemented: Read as ‘0’ bit 20-19 AUXOUT[1:0]: Auxiliary Output Signal on Event Selection bits 11 = Input capture or output compare event; no signal in Timer mode 10 = Signal output depends on module operating mode 01 = Time base rollover event (all modes) 00 = Disabled bit 18-16 ICS[2:0]: Input Capture Source Select bits 111 = CLC4 output 110 = CLC3 output 101 = CLC2 output 100 = CLC1 output 011 = Comparator 3 output 010 = Comparator 2 output 001 = Comparator 1 output 000 = ICMx pin(2) bit 15 PWMRSEN: CCPx PWM Restart Enable bit 1 = ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input has ended 0 = ASEVT must be cleared in software to resume PWM activity on output pins Note 1: 2: OCFEN through OCBEN (bits[29:25]) are implemented in MCCP modules only. This pin is remappable from SCCP modules. DS60001387D-page 152  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 14-2: CCPxCON2: CAPTURE/COMPARE/PWMx CONTROL 2 REGISTER (CONTINUED) bit 14 ASDGM: CCPx Auto-Shutdown Gate Mode Enable bit 1 = Waits until the next Time Base Reset or rollover for shutdown to occur 0 = Shutdown event occurs immediately bit 13 Unimplemented: Read as ‘0’ bit 12 SSDG: CCPx Software Shutdown/Gate Control bit 1 = Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting the ASDGM bit still applies) 0 = Normal module operation bit 11-8 Unimplemented: Read as ‘0’ bit 7-0 ASDG[7:0]: CCPx Auto-Shutdown/Gating Source Enable bits 1xxx xxxx = Auto-shutdown is controlled by the OCFB pin (remappable) x1xx xxxx = Auto-shutdown is controlled by the OCFA pin (remappable) xx1x xxxx = Auto-shutdown is controlled by CLC1 for MCCP1 Auto-shutdown is controlled by CLC2 for MCCP2 Auto-shutdown is controlled by CLC3 for MCCP3 Auto-shutdown is controlled by CLC1 for SCCP4 Auto-shutdown is controlled by CLC2 for SCCP5 Auto-shutdown is controlled by CLC3 for SCCP6 Auto-shutdown is controlled by CLC4 for SCCP7 Auto-shutdown is controlled by CLC1 for SCCP8 Auto-shutdown is controlled by CLC2 for SCCP9 xxx1 xxxx = Auto-shutdown is controlled by the SCCP4 output for MCCP1/MCCP2/MCCP3 Auto-shutdown is controlled by the MCCP1 output for SCCP4/SCCP5/SCCP6/SCCP7/ SCCP8/SCCP9 xxxx 1xxx = Auto-shutdown is controlled by the SCCP5 output for MCCP1/MCCP2/MCCP3 Auto-shutdown is controlled by the MCCP2 output for SCCP4/SCCP5/SCCP6/SCCP7/ SCCP8/SCCP9 xxxx x1xx = Auto-shutdown is controlled by Comparator 3 xxxx xx1x = Auto-shutdown is controlled by Comparator 2 xxxx xxx1 = Auto-shutdown is controlled by Comparator 1 Note 1: 2: OCFEN through OCBEN (bits[29:25]) are implemented in MCCP modules only. This pin is remappable from SCCP modules.  2016-2019 Microchip Technology Inc. DS60001387D-page 153 PIC32MM0256GPM064 FAMILY REGISTER 14-3: Bit Range 31:24 CCPxCON3: CAPTURE/COMPARE/PWMx CONTROL 3 REGISTER Bit 31/23/15/7 Bit 30/22/14/6 R/W-0 R/W-0 OETRIG U-0 23:16 15:8 7:0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 R/W-0 R/W-0 U-0 R/W-0 OSCNT[2:0] U-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 OUTM[2:0](1) — R/W-0 Bit 25/17/9/1 R/W-0 R/W-0 R/W-0 R/W-0 (1) — — POLACE POLBDF(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — PSSACE[1:0] PSSBDF[1:0] DT[5:0](1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 OETRIG: PWM Dead-Time Select bit 1 = For Triggered mode (TRIGEN = 1), the module does not drive enabled output pins until triggered 0 = Normal output pin operation bit 30-28 OSCNT[2:0]: One-Shot Event Count bits Extends the duration of a one-shot trigger event by an additional n clock cycles (n + 1 total cycles). 111 = 7 timer count periods (8 cycles total) 110 = 6 timer count periods (7 cycles total) 101 = 5 timer count periods (6 cycles total) 100 = 4 timer count periods (5 cycles total) 011 = 3 timer count periods (4 cycles total) 010 = 2 timer count periods (3 cycles total) 001 = 1 timer count period (2 cycles total) 000 = Does not extend the one-shot trigger event (the event takes 1 timer count period) bit 27 Unimplemented: Read as ‘0’ bit 26-24 OUTM[2:0]: PWMx Output Mode Control bits(1) 111 = Reserved 110 = Output Scan mode 101 = Brush DC Output mode, forward 100 = Brush DC Output mode, reverse 011 = Reserved 010 = Half-Bridge Output mode 001 = Push-Pull Output mode 000 = Steerable Single Output mode bit 23-22 Unimplemented: Read as ‘0’ bit 21 POLACE: CCPx Output Pins, OCxA, OCxC and OCxE, Polarity Control bit 1 = Output pin polarity is active-low 0 = Output pin polarity is active-high bit 20 POLBDF: CCPx Output Pins, OCxB, OCxD and OCxF, Polarity Control bit(1) 1 = Output pin polarity is active-low 0 = Output pin polarity is active-high Note 1: These bits are implemented in MCCP modules only. DS60001387D-page 154  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 14-3: CCPxCON3: CAPTURE/COMPARE/PWMx CONTROL 3 REGISTER (CONTINUED) bit 19-18 PSSACE[1:0]: PWMx Output Pins, OCxA, OCxC and OCxE, Shutdown State Control bits 11 = Pins are driven active when a shutdown event occurs 10 = Pins are driven inactive when a shutdown event occurs 0x = Pins are in a high-impedance state when a shutdown event occurs bit 17-16 PSSBDF[1:0]: PWMx Output Pins, OCxB, OCxD and OCxF, Shutdown State Control bits(1) 11 = Pins are driven active when a shutdown event occurs 10 = Pins are driven inactive when a shutdown event occurs 0x = Pins are in a high-impedance state when a shutdown event occurs bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 DT[5:0]: PWM Dead-Time Select bits(1) 111111 = Insert 63 dead-time delay periods between complementary output signals 111110 = Insert 62 dead-time delay periods between complementary output signals ... 000010 = Insert 2 dead-time delay periods between complementary output signals 000001 = Insert 1 dead-time delay period between complementary output signals 000000 = Dead-time logic is disabled Note 1: These bits are implemented in MCCP modules only.  2016-2019 Microchip Technology Inc. DS60001387D-page 155 PIC32MM0256GPM064 FAMILY REGISTER 14-4: Bit Range Bit Bit 31/23/15/7 30/22/14/6 31:24 23:16 15:8 7:0 CCPxSTAT: CAPTURE/COMPARE/PWMx STATUS REGISTER Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 r-x r-x r-x r-x r-x — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/C-0 U-0 U-0 — — — — — ICGARM(1) — — R-0 W1-0 W1-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE Legend: C = Clearable bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-21 Unimplemented: Read as ‘0’ bit 20-16 Reserved bit 15-11 Unimplemented: Read as ‘0’ bit 10 ICGARM: Input Capture Gate Arm bit(1) A write of ‘1’ to this location will arm the input capture gating logic for a one-shot gate event when ICGSM[1:0] = 01 or 10. The bit location reads as ‘0’. bit 9-8 Unimplemented: Read as ‘0’ bit 7 CCPTRIG: CCPx Trigger Status bit 1 = Timer has been triggered and is running (set by hardware or writing to TRSET) 0 = Timer has not been triggered and is held in Reset (cleared by writing to TRCLR) bit 6 TRSET: CCPx Trigger Set Request bit Write ‘1’ to this location to trigger the timer when TRIGEN = 1 (location always reads ‘0’). bit 5 TRCLR: CCPx Trigger Clear Request bit Write ‘1’ to this location to cancel the timer trigger when TRIGEN = 1 (location always reads ‘0’). bit 4 ASEVT: CCPx Auto-Shutdown Event Status/Control bit 1 = A shutdown event is in progress; CCPx outputs are in the shutdown state 0 = CCPx outputs operate normally bit 3 SCEVT: Single Edge Compare Event Status bit 1 = A single edge compare event has occurred 0 = A single edge compare event has not occurred bit 2 ICDIS: Input Capture Disable bit 1 = Event on input capture pin does not generate a capture event 0 = Event on input capture pin will generate a capture event bit 1 ICOV: Input Capture Buffer Overflow Status bit 1 = The input capture FIFO buffer has overflowed 0 = The input capture FIFO buffer has not overflowed bit 0 ICBNE: Input Capture Buffer Status bit 1 = The input capture buffer has data available 0 = The input capture buffer is empty Note 1: This is not a physical bit location and will always read as ‘0’. A write of ‘1’ will initiate the hardware event. DS60001387D-page 156  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 15.0 SERIAL PERIPHERAL INTERFACE (SPI) AND INTER-IC SOUND (I2S) Note: as digital audio devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, Analog-to-Digital Converters (ADC), etc. The SPI/I2S module is compatible with Motorola® SPI and SIOP interfaces. This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 23. “Serial Peripheral Interface (SPI)” (www.microchip.com/ DS61106) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. Some of the key features of the SPI module are: • • • • • Master and Slave modes Support Four Different Clock Formats Enhanced Framed SPI Protocol Support User-Configurable 8-Bit, 16-Bit and 32-Bit Data Width Separate SPI FIFO Buffers for Receive and Transmit: - FIFO buffers act as 4/8/16-level deep FIFOs based on 32/16/8-bit data width • Programmable Interrupt Event on every 8-Bit,  16-Bit and 32-Bit Data Transfer • Operation during Sleep and Idle modes • Audio Codec Support: The SPI/I2S module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices, as well FIGURE 15-1: SPI/I2S MODULE BLOCK DIAGRAM Internal Data Bus SPIxBUF Read Write FIFOs Share Address SPIxBUF SPIxRXB FIFO SPIxTXB FIFO Transmit Receive SPIxSR SDIx bit 0 SDOx SSx/FSYNC1 Slave Select and Frame Sync Control SCKx Shift Control Clock Control MCLKSEL Edge Select REFOCLK Baud Rate Generator PBCLK MSTEN Note: Access the SPIxTXB and SPIxRXB FIFOs via the SPIxBUF register.  2016-2019 Microchip Technology Inc. DS60001387D-page 157 SPI Control Registers Virtual Address (BF80_#) Register Name(1) TABLE 15-1: 8100 SPI1CON 8130 SPI1BUF SPI1BRG 8140 SPI1CON2 8200 SPI2CON 8210 SPI2STAT 8220 8230 SPI2BUF SPI2BRG 8240 SPI2CON2  2016-2019 Microchip Technology Inc. 8300 SPI3CON 8310 SPI3STAT 8330 8320 SPI3BUF SPI3BRG 8340 SPI3CON2 31/15 31:16 FRMEN 15:0 ON — SIDL 31:16 — — — 15:0 — — — 30/14 29/13 FRMSYNC FRMPOL 28/12 27/11 MSSEN FRMSYPW DISSDO MODE32 26/10 25/9 24/8 FRMCNT[2:0] MODE16 SMP CKE RXBUFELM[4:0] FRMERR SPIBUSY — — 31:16 SPITUR 23/7 22/6 MCLKSEL — SSEN CKP — — SRMT 21/5 20/4 — — MSTEN DISSDI 19/3 18/2 17/1 — — SPIFE STXISEL[1:0] — SPIROV SPIRBE ENHBUF 0000 SRXISEL[1:0] TXBUFELM[4:0] — SPITBE — 31:16 — — — 15:0 — — — 31:16 — — — 15:0 SPISGNEXT — — 31:16 FRMEN FRMSYNC FRMPOL 15:0 ON — SIDL 31:16 — — — 15:0 — — — — — — — — 0000 0000 0000 — — — — — — — — — BRG[12:0] — — — — — FRMERREN SPIROVEN SPITUREN IGNROV IGNTUR MSSEN FRMSYPW DISSDO MODE32 FRMCNT[2:0] MODE16 SMP CKE RXBUFELM[4:0] FRMERR SPIBUSY — — 31:16 SPITUR — — — — — — AUDEN — — — AUDMONO — AUDMOD[1:0] MCLKSEL — — — — — SSEN CKP — — SRMT 31:16 — — — 15:0 — — — 31:16 — — — 15:0 SPISGNEXT — — 31:16 FRMEN FRMSYNC FRMPOL 15:0 ON — SIDL 31:16 — — — 15:0 — — — — — — — — MSTEN DISSDI STXISEL[1:0] — SPIROV SPIRBE SPIFE SRXISEL[1:0] TXBUFELM[4:0] — SPITBE — — — — — FRMERREN SPIROVEN SPITUREN IGNROV IGNTUR MSSEN FRMSYPW DISSDO MODE32 FRMCNT[2:0] MODE16 SMP CKE RXBUFELM[4:0] FRMERR SPIBUSY — — 31:16 SPITUR 31:16 — — — 15:0 — — — 31:16 — — — 15:0 SPISGNEXT — — — — — — — — — — — FRMERREN SPIROVEN SPITUREN IGNROV IGNTUR 0000 0000 0000 0000 — — — — — — — — — — — — — — — AUDEN — — — AUDMONO — AUDMOD[1:0] MCLKSEL — — — — — SSEN CKP — — SRMT 0000 0000 — MSTEN DISSDI STXISEL[1:0] — SPIROV SPIRBE SPIFE SRXISEL[1:0] TXBUFELM[4:0] — SPITBE — 0000 0000 ENHBUF 0000 0000 0000 SPITBF SPIRBF 0008 0000 0000 — — — — — — — — — BRG[12:0] — 0000 SPITBF SPIRBF 0008 DATA[31:0] 15:0 0000 ENHBUF 0000 BRG[12:0] — 0000 0000 — DATA[31:0] 15:0 0000 SPITBF SPIRBF 0008 DATA[31:0] 15:0 0000 0000 — — — — — — — AUDEN — — — AUDMONO — AUDMOD[1:0] Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: 16/0 All Resets Bit Range Bits 8110 SPI1STAT 8120 SPI1, SPI2 AND SPI3 REGISTER MAP All registers in this table, except SPIxBUF, have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. 0000 0000 PIC32MM0256GPM064 FAMILY DS60001387D-page 158 15.1 PIC32MM0256GPM064 FAMILY REGISTER 15-1: Bit Range 31:24 23:16 15:8 7:0 SPIxCON: SPIx CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 MCLKSEL(1) — — — — — SPIFE ENHBUF(1) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MODE32 MODE16 SMP R/W-0 (2) R/W-0 R/W-0 R/W-0 (4) ON — SIDL R/W-0 R/W-0 (3) R/W-0 R/W-0 MSTEN DISSDI(4) SSEN CKP DISSDO FRMCNT[2:0] STXISEL[1:0] CKE R/W-0 SRXISEL[1:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 FRMEN: Framed SPI Support bit 1 = Framed SPI support is enabled (SSx pin is used as the FSYNC1 input/output) 0 = Framed SPI support is disabled bit 30 FRMSYNC: Frame Sync Pulse Direction Control on SSx Pin bit (Framed SPI mode only) 1 = Frame sync pulse input (Slave mode) 0 = Frame sync pulse output (Master mode) bit 29 FRMPOL: Frame Sync Polarity bit (Framed SPI mode only) 1 = Frame pulse is active-high 0 = Frame pulse is active-low bit 28 MSSEN: Master Mode Slave Select Enable bit 1 = Slave select SPI support is enabled; the SSx pin is automatically driven during transmission in Master mode, polarity is determined by the FRMPOL bit 0 = Slave select SPI support is disabled bit 27 FRMSYPW: Frame Sync Pulse-Width bit 1 = Frame sync pulse is one character wide 0 = Frame sync pulse is one clock wide bit 26-24 FRMCNT[2:0]: Frame Sync Pulse Counter bits Controls the number of data characters transmitted per pulse. This bit is only valid in Framed mode. 111 = Reserved 110 = Reserved 101 = Generates a frame sync pulse on every 32 data characters 100 = Generates a frame sync pulse on every 16 data characters 011 = Generates a frame sync pulse on every 8 data characters 010 = Generates a frame sync pulse on every 4 data characters 001 = Generates a frame sync pulse on every 2 data characters 000 = Generates a frame sync pulse on every data character Note 1: 2: 3: 4: These bits can only be written when the ON bit = 0. Refer to Section 29.0 “Electrical Characteristics” for maximum clock frequency requirements. This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI mode (FRMEN = 1). When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual value of the CKP bit. These bits are present for legacy compatibility and are superseded by PPS functionality on these devices (see Section 10.9 “Peripheral Pin Select (PPS)” for more information).  2016-2019 Microchip Technology Inc. DS60001387D-page 159 PIC32MM0256GPM064 FAMILY REGISTER 15-1: SPIxCON: SPIx CONTROL REGISTER (CONTINUED) MCLKSEL: Master Clock Enable bit(1) 1 = REFO1 is used by the Baud Rate Generator 0 = PBCLK is used by the Baud Rate Generator bit 23 bit 22-18 Unimplemented: Read as ‘0’ bit 17 SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only) 1 = Frame synchronization pulse coincides with the first bit clock 0 = Frame synchronization pulse precedes the first bit clock bit 16 ENHBUF: Enhanced Buffer Enable bit(1) 1 = Enhanced Buffer mode is enabled 0 = Enhanced Buffer mode is disabled bit 15 ON: SPIx Module On bit 1 = SPIx module is enabled 0 = SPIx module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: SPIx Stop in Idle Mode bit 1 = Discontinues operation when CPU enters Idle mode 0 = Continues operation in Idle mode bit 12 DISSDO: Disable SDOx Pin bit(4) 1 = SDOx pin is not used by the module; the pin is controlled by the associated PORTx register 0 = SDOx pin is controlled by the module bit 11-10 MODE[32,16]: 32/16/8-Bit Communication Select bits When AUDEN = 1: MODE32 MODE16 Communication 1 1 24-bit data, 32-bit FIFO, 32-bit channel/64-bit frame 1 0 32-bit data, 32-bit FIFO, 32-bit channel/64-bit frame 0 1 16-bit data, 16-bit FIFO, 32-bit channel/64-bit frame 0 0 16-bit data, 16-bit FIFO, 16-bit channel/32-bit frame When AUDEN = 0: MODE32 MODE16 Communication 1 x 32-bit 0 1 16-bit 0 0 8-bit bit 9 SMP: SPIx Data Input Sample Phase bit Master mode (MSTEN = 1): 1 = Input data are sampled at end of data output time 0 = Input data are sampled at middle of data output time Slave mode (MSTEN = 0): SMP value is ignored when SPIx is used in Slave mode. The module always uses SMP = 0. bit 8 CKE: SPIx Clock Edge Select bit(2) 1 = Serial output data change on transition from active clock state to Idle clock state (see the CKP bit) 0 = Serial output data change on transition from Idle clock state to active clock state (see the CKP bit) Note 1: These bits can only be written when the ON bit = 0. Refer to Section 29.0 “Electrical Characteristics” for maximum clock frequency requirements. This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI mode (FRMEN = 1). When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual value of the CKP bit. These bits are present for legacy compatibility and are superseded by PPS functionality on these devices (see Section 10.9 “Peripheral Pin Select (PPS)” for more information). 2: 3: 4: DS60001387D-page 160  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 15-1: SPIxCON: SPIx CONTROL REGISTER (CONTINUED) bit 7 SSEN: Slave Select Enable (Slave mode) bit 1 = SSx pin is used for Slave mode 0 = SSx pin is not used for Slave mode, pin is controlled by port function bit 6 CKP: Clock Polarity Select bit(3) 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode bit 4 DISSDI: Disable SDIx bit(4) 1 = SDIx pin is not used by the SPIx module (pin is controlled by port function) 0 = SDIx pin is controlled by the SPIx module bit 3-2 STXISEL[1:0]: SPIx Transmit Buffer Empty Interrupt Mode bits 11 = Interrupt is generated when the buffer is not full (has one or more empty elements) 10 = Interrupt is generated when the buffer is empty by one-half or more 01 = Interrupt is generated when the buffer is completely empty 00 = Interrupt is generated when the last transfer is shifted out of SPIxSR and transmit operations are complete bit 1-0 SRXISEL[1:0]: SPIx Receive Buffer Full Interrupt Mode bits 11 = Interrupt is generated when the buffer is full 10 = Interrupt is generated when the buffer is full by one-half or more 01 = Interrupt is generated when the buffer is not empty 00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty) Note 1: These bits can only be written when the ON bit = 0. Refer to Section 29.0 “Electrical Characteristics” for maximum clock frequency requirements. This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI mode (FRMEN = 1). When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual value of the CKP bit. These bits are present for legacy compatibility and are superseded by PPS functionality on these devices (see Section 10.9 “Peripheral Pin Select (PPS)” for more information). 2: 3: 4:  2016-2019 Microchip Technology Inc. DS60001387D-page 161 PIC32MM0256GPM064 FAMILY REGISTER 15-2: Bit Range 31:24 23:16 15:8 7:0 SPIxCON2: SPIx CONTROL REGISTER 2 Bit 31/23/15/7 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPISGNEXT — — FRMERREN SPIROVEN R/W-0 U-0 U-0 U-0 R/W-0 SPITUREN IGNROV U-0 AUDEN(1) — — — AUDMONO(1,2) — IGNTUR R/W-0 R/W-0 AUDMOD[1:0](1,2) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 SPISGNEXT: SPIx Sign-Extend Read Data from the RX FIFO bit 1 = Data from RX FIFO are sign-extended 0 = Data from RX FIFO are not sign-extended bit 14-13 Unimplemented: Read as ‘0’ bit 12 FRMERREN: Enable Interrupt Events via FRMERR bit 1 = Frame error overflow generates error events 0 = Frame error does not generate error events bit 11 SPIROVEN: Enable Interrupt Events via SPIROV bit 1 = Receive Overflow (ROV) generates error events 0 = Receive Overflow does not generate error events bit 10 SPITUREN: Enable Interrupt Events via SPITUR bit 1 = Transmit Underrun (TUR) generates error events 0 = Transmit Underrun does not generate error events bit 9 IGNROV: Ignore Receive Overflow (ROV) bit (for audio data transmissions) 1 = A ROV is not a critical error; during ROV, data in the FIFO are not overwritten by receive data 0 = A ROV is a critical error which stops SPIx operation bit 8 IGNTUR: Ignore Transmit Underrun (TUR) bit (for audio data transmissions) 1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty 0 = A TUR is a critical error which stops SPIx operation bit 7 AUDEN: Enable Audio Codec Support bit(1) 1 = Audio protocol is enabled 0 = Audio protocol is disabled bit 6-4 Unimplemented: Read as ‘0’ bit 3 AUDMONO: Transmit Audio Data Format bit(1,2) 1 = Audio data are mono (each data word is transmitted on both left and right channels) 0 = Audio data are stereo bit 2 Unimplemented: Read as ‘0’ bit 1-0 AUDMOD[1:0]: Audio Protocol Mode bits(1,2) 11 = PCM/DSP mode 10 = Right Justified mode 01 = Left Justified mode 00 = I2S mode Note 1: 2: These bits can only be written when the ON bit = 0. These bits are only valid for AUDEN = 1. DS60001387D-page 162  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 15-3: Bit Range 31:24 23:16 15:8 7:0 SPIxSTAT: SPIx STATUS REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 U-0 U-0 U-0 — — — U-0 U-0 U-0 RXBUFELM[4:0] R-0 R-0 R-0 — — — U-0 U-0 U-0 R/C-0, HS R-0 TXBUFELM[4:0] U-0 U-0 R-0 — — — FRMERR SPIBUSY — — SPITUR R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0 SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28-24 RXBUFELM[4:0]: Receive Buffer Element Count bits (valid only when ENHBUF = 1) bit 23-21 Unimplemented: Read as ‘0’ bit 20-16 TXBUFELM[4:0]: Transmit Buffer Element Count bits (valid only when ENHBUF = 1) bit 15-13 Unimplemented: Read as ‘0’ bit 12 FRMERR: SPIx Frame Error status bit 1 = Frame error detected 0 = No frame error detected This bit is only valid when FRMEN = 1. bit 11 SPIBUSY: SPIx Activity Status bit 1 = SPIx peripheral is currently busy with some transactions 0 = SPIx peripheral is currently Idle bit 10-9 Unimplemented: Read as ‘0’ bit 8 SPITUR: Transmit Underrun (TUR) bit 1 = Transmit buffer has encountered an underrun condition 0 = Transmit buffer has no underrun condition This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling the module. bit 7 SRMT: Shift Register Empty bit (valid only when ENHBUF = 1) 1 = When the SPIx Shift register is empty 0 = When the SPIx Shift register is not empty bit 6 SPIROV: Receive Overflow (ROV) Flag bit 1 = New data are completely received and discarded; the user software has not read the previous data in the SPIxBUF register 0 = No overflow has occurred This bit is set in hardware; it can only be cleared (= 0) in software. bit 5 SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1) 1 = RX FIFO is empty (CPU Read Pointer (CRPTR) = SPI Write Pointer (SWPTR)) 0 = RX FIFO is not empty (CRPTR SWPTR) bit 4 Unimplemented: Read as ‘0’  2016-2019 Microchip Technology Inc. DS60001387D-page 163 PIC32MM0256GPM064 FAMILY REGISTER 15-3: SPIxSTAT: SPIx STATUS REGISTER (CONTINUED) bit 3 SPITBE: SPIx Transmit Buffer Empty Status bit 1 = Transmit buffer, SPIxTXB, is empty 0 = Transmit buffer, SPIxTXB, is not empty Automatically set in hardware when SPIx transfers data from SPIxTXB to SPIxSR. Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB. bit 2 Unimplemented: Read as ‘0’ bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit has not yet started, SPIxTXB is full 0 = Transmit buffer is not full Standard Buffer mode: Automatically set in hardware when the core writes to the SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR. Enhanced Buffer mode: Set when CPU Write Pointer (CWPTR) + 1 = SPI Read Pointer (SRPTR); cleared otherwise. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive buffer, SPIxRXB, is full 0 = Receive buffer, SPIxRXB, is not full Standard Buffer mode: Automatically set in hardware when the SPIx module transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB. Enhanced Buffer mode: Set when SWPTR + 1 = CRPTR; cleared otherwise. REGISTER 15-4: SPIxBRG: SPIx BAUD RATE REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — 23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — 15:8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — 7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BRG[12:8] R/W-0 BRG[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-13 Unimplemented: Write ‘0’; ignore read bit 12-0 BRG[12:0]: Baud Rate Divisor bits DS60001387D-page 164  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 16.0 Note: INTER-INTEGRATED CIRCUIT (I2C) This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “Inter-Integrated Circuit™ (I2C™)” (www.microchip.com/DS60001116) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. The I2C module provides complete hardware support for both Slave and Multi-Master modes of the I2C serial communication standard. Each I2C module has a 2-pin interface: Each I2C module offers the following key features: • I2C Interface Supporting Both Master and Slave Operation • I2C Slave mode Supports 7-Bit and  10-Bit Addressing • I2C Master mode Supports 7-Bit and  10-Bit Addressing • I2C Port allows Bidirectional Transfers between Master and Slaves • Serial Clock Synchronization for the I2C Port can be used as a Handshake Mechanism to Suspend and Resume Serial Transfer (SCLREL control) • I2C Supports Multi-Master Operation; Detects Bus Collision and Arbitrates Accordingly • Provides Support for Address Bit Masking • SMBus Support Figure 16-1 illustrates the I2C module block diagram. • SCLx pin is clock • SDAx pin is data  2016-2019 Microchip Technology Inc. DS60001387D-page 165 PIC32MM0256GPM064 FAMILY FIGURE 16-1: I2Cx BLOCK DIAGRAM Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read PBCLK DS60001387D-page 166  2016-2019 Microchip Technology Inc. I2C Control Registers TABLE 16-1: 1500 I2C1CON 1510 I2C1STAT 1520 I2C1ADD 1540 I2C1BRG 1560 I2C1TRN I2C1RCV 1600 I2C2CON 1610 I2C2STAT 1620 I2C2ADD 1630 I2C2MSK 1640 I2C2BRG DS60001387D-page 167 1650 I2C2TRN 1660 I2C2RCV 30/14 31:16 — — — — — — — — — PCIE 15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN 31:16 — — — — — — — — — — — 15:0 ACKSTAT TRSTAT 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 17/1 16/0 All Resets Bit Range 31/15 20/4 19/3 18/2 SCIE BOEN SDAHT SBCDE r r ACKDT ACKEN RCEN PEN RSEN SEN 1000 — — — — — 0000 0000 ACKTIM — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 31:16 — — — — — — — — — — — — — — — — 0000 — — — — — — — — 0000 — — — — — — — — — 0000 — — — — — — — — 0000 — — — — — — 0000 15:0 — — — — — — 31:16 — — — — — — 15:0 — — — — — — 31:16 — — — — — — — 31:16 — — — — — — — — 15:0 I2C1 Address Register — 0000 — I2C1 Address Mask Register 0000 Baud Rate Generator Register 15:0 — — — — — — — — 31:16 — — — — — — — — 0000 I2C1 Transmit Register — 0000 — 15:0 — — — — — — — — 31:16 — — — — — — — — — PCIE SCIE BOEN SDAHT SBCDE r r 15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ACKSTAT TRSTAT I2C1 Receive Register 0000 0000 ACKTIM — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 31:16 — — — — — — — — — — — — — — — — 0000 — — — — — — — — 0000 — — — — — — — — — 0000 — — — — — — — — 0000 — — — — — — 0000 15:0 — — — — — — 31:16 — — — — — — 15:0 — — — — — — 31:16 — — — — — — — 31:16 — — — — — — — — 15:0 I2C2 Address Register — — 0000 I2C2 Address Mask Register 0000 Baud Rate Generator Register 15:0 — — — — — — — — 31:16 — — — — — — — — 15:0 — — — — — — — — 0000 I2C2 Transmit Register — — I2C2 Receive Register Legend: — = unimplemented, read as ‘0’; r = reserved bit. Reset values are shown in hexadecimal. Note 1: All registers in this table, except I2CxRCV, have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. 0000 0000 PIC32MM0256GPM064 FAMILY 1530 I2C1MSK 1550 I2C1, I2C2 AND I2C3 REGISTER MAP Bits Register Name(1) Virtual Address (BF80_#)  2016-2019 Microchip Technology Inc. 16.1 1710 I2C3STAT 1720 I2C3ADD 1730 I2C3MSK 1740 I2C3BRG I2C3TRN 1760 I2C3RCV 31/15 30/14 31:16 — — — — — — — — — PCIE 15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN 31:16 — — — — — — — — — — — 15:0 ACKSTAT TRSTAT 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 17/1 16/0 All Resets Bit Range Register Name(1) Virtual Address (BF80_#) Bits 1700 I2C3CON 1750 I2C1, I2C2 AND I2C3 REGISTER MAP (CONTINUED) 20/4 19/3 18/2 SCIE BOEN SDAHT SBCDE r r ACKDT ACKEN RCEN PEN RSEN SEN 1000 — — — — — 0000 0000 ACKTIM — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 31:16 — — — — — — — — — — — — — — — — 0000 — — — — — — — — 0000 — — — — — — — — — 0000 — — — — — — — — 0000 — — — — — — 0000 15:0 — — — — — — 31:16 — — — — — — 15:0 — — — — — — 31:16 — — — — — — — 31:16 — — — — — — — — 15:0 I2C2 Address Register — — 0000 I2C2 Address Mask Register 0000 Baud Rate Generator Register 15:0 — — — — — — — — 31:16 — — — — — — — — 15:0 — — — — — — — — 0000 I2C2 Transmit Register — — I2C2 Receive Register Legend: — = unimplemented, read as ‘0’; r = reserved bit. Reset values are shown in hexadecimal. Note 1: All registers in this table, except I2CxRCV, have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. 0000 0000 PIC32MM0256GPM064 FAMILY DS60001387D-page 168 TABLE 16-1:  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 16-1: Bit Range 31:24 23:16 15:8 7:0 I2CxCON: I2Cx CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r-0 r-0 — PCIE SCIE BOEN SDAHT SBCDE — — R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN Legend: r = Reserved bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-23 Unimplemented: Read as ‘0’ bit 22 PCIE: Stop Condition Interrupt Enable bit (I2C Slave mode only) 1 = Enables interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled bit 21 SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only) 1 = Enables interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled bit 20 BOEN: Buffer Overwrite Enable bit (I2C Slave mode only) 1 = I2CxRCV is updated and an ACK is generated for a received address/data byte, ignoring the state of the I2COV bit (I2CxSTAT[6]) only if the RBF bit (I2CxSTAT[1]) = 0 0 = I2CxRCV is only updated when the I2COV bit (I2CxSTAT[6]) is clear bit 19 SDAHT: SDAx Hold Time Selection bit 1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx 0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx bit 18 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) 1 = Enables slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 17-16 Reserved: Maintain as ‘0’ bit 15 ON: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module; all I2C pins are controlled by port functions bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: I2Cx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Releases SCLx clock 0 = Holds SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear at the beginning of slave transmission. Hardware is clear at the end of slave reception. If STREN = 0: Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware is clear at the beginning of slave transmission.  2016-2019 Microchip Technology Inc. DS60001387D-page 169 PIC32MM0256GPM064 FAMILY REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 11 STRICT: Strict I2C Reserved Address Rule Enable bit 1 = Strict reserved addressing is enforced; device does not respond to reserved address space or generates addresses in reserved address space 0 = Strict I2C reserved address rule is not enabled bit 10 A10M: 10-Bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control is disabled 0 = Slew rate control is enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enables I/O pin thresholds compliant with the SMBus specification 0 = Disables SMBus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address is disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with the SCLREL bit. 1 = Enables software or receives clock stretching 0 = Disables software or receives clock stretching bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit  (when operating as I2C master, applicable during master receive) 1 = Initiates Acknowledge sequence on the SDAx and SCLx pins and transmits the ACKDT data bit; hardware is clear at the end of the master Acknowledge sequence 0 = Acknowledge sequence is not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C; hardware is clear at the end of the eighth bit of the master receive data byte 0 = Receive sequence is not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiates Stop condition on SDAx and SCLx pins; hardware is clear at the end of the master Stop sequence 0 = Stop condition is not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiates Repeated Start condition on SDAx and SCLx pins; hardware is clear at the end of the master Repeated Start sequence 0 = Repeated Start condition is not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiates Start condition on SDAx and SCLx pins; hardware is clear at the end of the master Start sequence 0 = Start condition is not in progress DS60001387D-page 170  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 16-2: Bit Range 31:24 23:16 15:8 7:0 I2CxSTAT: I2Cx STATUS REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0, HSC R-0, HSC R/C-0, HSC U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT ACKTIM — — BCL GCSTAT ADD10 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D/A P S R/W RBF TBF Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared C = Clearable bit bit 31-16 Unimplemented: Read as ‘0’ bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation) 1 = NACK received from slave 0 = ACK received from slave Hardware is set or clear at the end of slave Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware is set at the beginning of master transmission. Hardware is clear at the end of slave Acknowledge. bit 13 ACKTIM: Acknowledge Time Status bit (valid in I2C Slave mode only) 1 = I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCLx clock 0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCLx clock bit 12-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware is set at detection of a bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware is set when the address matches the general call address. Hardware is clear at Stop detection. bit 8 ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware is set at match of the 2nd byte of matched 10-bit address. Hardware is clear at Stop detection. bit 7 IWCOL: I2Cx Write Collision Detect bit 1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware is set at occurrence of a write to I2CxTRN while busy (cleared by software). bit 6 I2COV: I2Cx Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware is set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).  2016-2019 Microchip Technology Inc. DS60001387D-page 171 PIC32MM0256GPM064 FAMILY REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 5 D/A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was a device address Hardware is clear at a device address match. Hardware is set by reception of a slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. bit 2 R/W: Read/Write Information bit (when operating as I2C slave) 1 = Read – Indicates data transfer is output from slave 0 = Write – Indicates data transfer is input to slave Hardware is set or clear after reception of an I 2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive is complete, I2CxRCV is full 0 = Receive is not complete, I2CxRCV is empty Hardware is set when I2CxRCV is written with the received byte. Hardware is clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit is in progress, I2CxTRN is full 0 = Transmit is complete, I2CxTRN is empty Hardware is set when software writes to I2CxTRN. Hardware is clear at completion of the data transmission. DS60001387D-page 172  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 17.0 Note: UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. “UART” (www.microchip.com/DS60001107) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. The UART module is one of the serial I/O modules available in the PIC32MM0256GPM064 family devices. The UART is a full-duplex, asynchronous communication channel that communicates with peripheral devices and personal computers through protocols, such as RS-232, RS-485, LIN/J2602 and IrDA®. The module also supports the hardware flow control option with the UxCTS and UxRTS pins, and also includes an IrDA® encoder and decoder. The primary features of the UART module are: • • • • • • • • • • • • • • • • • • Full-Duplex, 8-Bit or 9-Bit Data Transmission Even, Odd or No Parity Options (for 8-bit data) One or Two Stop Bits Hardware Auto-Baud Feature Hardware Flow Control Option Fully Integrated Baud Rate Generator (BRG) with 16-Bit Prescaler Baud rates ranging from 47.4 bps to 6.25 Mbps at 25 MHz 8-Level Deep First-In-First-Out (FIFO) Transmit Data Buffer 8-Level Deep FIFO Receive Data Buffer Parity, Framing and Buffer Overrun Error Detection Support for Interrupt Only on Address Detect  (9th bit = 1) Separate Transmit and Receive Interrupts Loopback mode for Diagnostic Support LIN/J2602 Protocol Support IrDA Encoder and Decoder with 16x Baud Clock Output for External IrDA Encoder/Decoder Support Supports Separate UART Baud Clock Input Ability to Continue to Run when a Receive  Overflow Condition Exists Ability to Run and Receive Data during Sleep mode Figure 17-1 illustrates a simplified block diagram of the UART module. FIGURE 17-1: UARTx SIMPLIFIED BLOCK DIAGRAM PBCLK Baud Rate Generator IrDA® Hardware Flow Control UxRTS/BCLKx UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX  2016-2019 Microchip Technology Inc. DS60001387D-page 173 UART Control Registers 1800 U1MODE(1) 1810 U1STA(1) 1820 U1TXREG 1830 U1RXREG 1840 UART1, UART2 AND UART3 REGISTER MAP U1BRG(1) 31/15 30/14 31:16 — — — 15:0 ON — SIDL 31:16 1910 1920 U2TXREG 1930 U2RXREG 1940 U2BRG(1)  2016-2019 Microchip Technology Inc. 2000 U3MODE(1) 2010 U3STA(1) 2020 U3TXREG 2030 U3RXREG 2040 U3BRG(1) 28/12 27/11 26/10 25/9 24/8 23/7 — — — — — SLPEN ACTIVE — — — CLKSEL[1:0] OVFDIS IREN RTSMD — WAKE LPBACK ABAUD RXINV BRGH PDSEL[1:0] STSEL UEN[1:0] 21/5 20/4 19/3 18/2 17/1 16/0 UART1 ADDR[7:0] 15:0 UTXISEL[1:0] UTXINV URXEN UTXBRK UTXEN UTXBF TRMT — — — — — — — — 15:0 — — — — — — — TX8 31:16 — — — — — — — — 15:0 — — — — — — — RX8 31:16 — — — — — — — 15:0 — URXISEL[1:0] — — ADDEN RIDLE PERR FERR OERR URXDA — — — — — — UART1 Transmit Register — — — — — — — — — — — — — — — ON — SIDL IREN RTSMD — — — UEN[1:0] — — — UTXISEL[1:0] UTXINV URXEN UTXBRK UTXEN UTXBF TRMT — — — — — — — — — — — SLPEN ACTIVE — — — CLKSEL[1:0] OVFDIS WAKE LPBACK ABAUD RXINV BRGH PDSEL[1:0] STSEL 15:0 — — — — — — — TX8 31:16 — — — — — — — — 15:0 — — — — — — — RX8 31:16 — — — — — — — 15:0 — URXISEL[1:0] — — — ADDEN RIDLE PERR FERR OERR URXDA — — — — — — — — — — — — — — — — — — — — — — 15:0 ON — SIDL IREN RTSMD — 31:16 — — UEN[1:0] — — — SLPEN ACTIVE — — — CLKSEL[1:0] OVFDIS WAKE LPBACK ABAUD RXINV BRGH PDSEL[1:0] STSEL UART2 ADDR[7:0] 15:0 UTXISEL[1:0] UTXINV URXEN UTXBRK UTXEN UTXBF TRMT — — — — — — — — 15:0 — — — — — — — TX8 31:16 — — — — — — — — 15:0 — — — — — — — RX8 31:16 — — — — — — — — URXISEL[1:0] — — — ADDEN RIDLE PERR FERR OERR URXDA — — — — — — — 0000 0000 0000 — — — — Baud Rate Generator Prescaler Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: These registers have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. — — 0000 0000 0110 0000 0000 — — — UART2 Receive Register — 0110 0000 UART2 Transmit Register — 0000 0000 UART2 MASK[7:0] 31:16 0000 0000 Baud Rate Generator Prescaler 31:16 0000 0000 UART2 Receive Register — 0000 0000 UART2 Transmit Register — 0000 0000 UART2 ADDR[7:0] 15:0 0110 0000 UART2 MASK[7:0] 31:16 0000 0000 UART1 Receive Register — 0000 0000 Baud Rate Generator Prescaler 31:16 15:0 22/6 UART1 MASK[7:0] 31:16 31:16 1900 U2MODE(1) 15:0 U2STA(1) 29/13 All Resets Bit Range Bits Register Name Virtual Address (BF80_#) TABLE 17-1: 0000 0000 — — — 0000 0000 PIC32MM0256GPM064 FAMILY DS60001387D-page 174 17.1 PIC32MM0256GPM064 FAMILY REGISTER 17-1: Bit Range 31:24 23:16 15:8 7:0 UxMODE: UARTx MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 SLPEN ACTIVE — — — R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 ON — SIDL IREN RTSMD — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH CLKSEL[1:0] OVFDIS R/W-0 R/W-0 UEN[1:0](1) R/W-0 PDSEL[1:0] R/W-0 STSEL Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23 SLPEN: UARTx Run During Sleep Enable bit 1 = UARTx clock runs during Sleep 0 = UARTx clock is turned off during Sleep bit 22 ACTIVE: UARTx Running Status bit 1 = UARTx is active (UxMODE register shouldn’t be updated) 0 = UARTx is not active (UxMODE register can be updated) bit 21-19 Unimplemented: Read as ‘0’ bit 18-17 CLKSEL: UARTx Clock Selection bits 11 = The UARTx clock is the Reference Output (REFO1) clock 10 = The UARTx clock is the FRC oscillator clock 01 = The UARTx clock is the SYSCLK 00 = The UARTx clock is the PBCLK bit 16 OVFDIS: Run During Overflow Condition Mode bit 1 = When an Overflow Error (OERR) condition is detected, the shift register continues to run to remain synchronized 0 = When an Overflow Error (OERR) condition is detected, the shift register stops accepting new data (Legacy mode) bit 15 ON: UARTx Enable bit 1 = UARTx is enabled; UARTx pins are controlled by UARTx, as defined by the UEN[1:0] and UTXEN control bits 0 = UARTx is disabled; all UARTx pins are controlled by the corresponding bits in the PORTx, TRISx and LATx registers, UARTx power consumption is minimal bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: UARTx Stop in Idle Mode bit 1 = Discontinues operation when device enters Idle mode 0 = Continues operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit 1 = IrDA is enabled 0 = IrDA is disabled Note 1: These bits are present for legacy compatibility and are superseded by PPS functionality on these devices (see Section 10.9 “Peripheral Pin Select (PPS)” for more information).  2016-2019 Microchip Technology Inc. DS60001387D-page 175 PIC32MM0256GPM064 FAMILY REGISTER 17-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN[1:0]: UARTx Enable bits(1) 11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by corresponding bits in the PORTx register bit 7 WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit 1 = Wake-up is enabled 0 = Wake-up is disabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Loopback mode is enabled 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enables baud rate measurement on the next character – requires reception of a Sync character (0x55); cleared by hardware upon completion 0 = Baud rate measurement is disabled or has completed bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode – 4x baud clock is enabled 0 = Standard Speed mode – 16x baud clock is enabled bit 2-1 PDSEL[1:0]: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Selection bit 1 = 2 Stop bits 0 = 1 Stop bit Note 1: These bits are present for legacy compatibility and are superseded by PPS functionality on these devices (see Section 10.9 “Peripheral Pin Select (PPS)” for more information). DS60001387D-page 176  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 17-2: Bit Range 31:24 23:16 15:8 7:0 UxSTA: UARTx STATUS AND CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MASK[7:0] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1 UTXINV URXEN UTXBRK UTXEN UTXBF TRMT R/W-0 R-1 R-0 R-0 R/W-0 R-0 ADDEN RIDLE PERR FERR OERR URXDA ADDR[7:0] UTXISEL[1:0] R/W-0 R/W-0 URXISEL[1:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 MASK[7:0]: UARTx Address Match Mask bits Used to mask the ADDR[7:0] bits. For MASK[x]: 1 = ADDR[x] is used to detect the address match 0 = ADDR[x] is not used to detect the address match bit 23-16 ADDR[7:0]: UARTx Automatic Address Mask bits When the ADDEN bit is ‘1’, this value defines the address character to use for automatic address detection. bit 15-14 UTXISEL[1:0]: UARTx TX Interrupt Mode Selection bits 11 = Reserved, do not use 10 = Interrupt is generated and asserted while the transmit buffer is empty 01 = Interrupt is generated and asserted when all characters have been transmitted 00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space bit 13 UTXINV: UARTx Transmit Polarity Inversion bit If IrDA mode is Disabled (i.e., IREN (UxMODE[12]) is ‘0’): 1 = UxTX Idle state is ‘0’ 0 = UxTX Idle state is ‘1’ If IrDA mode is Enabled (i.e., IREN (UxMODE[12]) is ‘1’): 1 = IrDA® encoded UxTX Idle state is ‘1’ 0 = IrDA encoded UxTX Idle state is ‘0’ bit 12 URXEN: UARTx Receiver Enable bit 1 = UARTx receiver is enabled, UxRX pin is controlled by UARTx (if ON = 1) 0 = UARTx receiver is disabled, UxRX pin is ignored by the UARTx module bit 11 UTXBRK: UARTx Transmit Break bit 1 = Sends Break on next transmission; Start bit, followed by twelve ‘0’ bits, followed by Stop bit, cleared by hardware upon completion 0 = Break transmission is disabled or has completed bit 10 UTXEN: UARTx Transmit Enable bit 1 = UARTx transmitter is enabled, UxTX pin is controlled by UARTx (if ON = 1) 0 = UARTx transmitter is disabled, any pending transmission is aborted and the buffer is reset bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register (TSR) is Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued in the transmit buffer  2016-2019 Microchip Technology Inc. DS60001387D-page 177 PIC32MM0256GPM064 FAMILY REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 7-6 URXISEL[1:0]: UARTx Receive Interrupt Mode Selection bits 11 = Reserved 10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full 01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full 00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least one data character) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled; if 9-bit mode is not selected, this control bit has no effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Data are being received bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit resets the receiver buffer and RSR to the empty state. 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty DS60001387D-page 178  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 18.0 USB ON-THE-GO (OTG) Note 1: This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. “USB OnThe-Go (OTG)” (www.microchip.com/ DS61126) in the “PIC32 Family Reference Manual”. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The information in this data sheet supersedes the information in the FRM. The Universal Serial Bus (USB) module contains analog and digital components to provide a USB 2.0 full-speed and low-speed embedded Host, full-speed Device or OTG implementation, with a minimum of external components. This module in Host mode is intended for use as an embedded host, and therefore, does not implement a UHCI or OHCI controller. The USB module consists of the clock generator, the USB voltage comparators, the transceiver, the Serial Interface Engine (SIE), a dedicated USB DMA Controller, pull-up and pull-down resistors, and the register interface. A block diagram of the PIC32 USB OTG module is presented in Figure 18-1. 18.1 Reclaiming USB Pins When the USB Module is Operating Select USB pins that are not used on all USB operating modes (USBID and VBUSON) can be reclaimed when the module is operating in a mode that does not require them. These pins can be reclaimed by clearing the appropriate device Configuration bit (refer to Register 26-1). 18.2 All USB signaling pins, D+, D-, VBUS, VBUSON and USBID, can be reclaimed and used for GPIO or other peripherals if available on the pin when the USB module is disabled. For proper operation of the RB10 and RB11 pins, the USB module must be disabled, but powered. Refer to Section 18.1 “Reclaiming USB Pins When the USB Module is Operating” for more information. 18.3 Introduction The clock generator provides the 48 MHz clock required for USB full-speed and low-speed communication. The voltage comparators monitor the voltage on the VBUS pin to determine the state of the bus. The transceiver provides the analog translation between the USB bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint buffers, and generates the hardware protocol for data transfers. The dedicated USB DMA Controller transfers data between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the need for external signaling components. The register interface allows the CPU to configure and communicate with the module. The USB module includes the following features: • • • • • • • • • USB Full-Speed Support for Host and Device Low-Speed Support for Host and Device USB OTG Support Integrated Signaling Resistors Integrated Analog Comparators for VBUS  Monitoring Integrated USB Transceiver Transaction Handshaking performed by Hardware Endpoint Buffering anywhere in System RAM Integrated DMA to access System RAM and Flash Note: The implementation and use of the USB specifications, as well as other third party specifications or technologies, may require licensing; including, but not limited to, USB Implementers Forum, Inc. (also referred to as USB-IF). The user is fully responsible for investigating and satisfying any applicable licensing obligations. Note: Adding any circuitry to the USB D+/D- pins, other than the connection to a USB connector, may degrade the USB signal quality and violate USB specifications. For example: • USBID and VBUSON can be reclaimed in Device mode • VBUSON can be reclaimed in Host mode if it is not used for the power VBUS control  2016-2019 Microchip Technology Inc. Reclaiming USB Pins When the USB Module is Disabled DS60001387D-page 179 PIC32MM0256GPM064 FAMILY 18.4 Powering the USB Transceiver The VUSB3V3 pin is used to power the USB transceiver. During USB operation, this provides the power for USB transceiver drivers. When the USB module is disabled, this pin can be used to bias the transceiver circuit to prevent additional current draw when using RB10 and/or RB11 as GPIOs. Available options for VUSB power: 1. 2. 3. For USB operation, an external power source is required. For voltage compliant USB operation, the voltage applied to VUSB3V3 must be in the range specified by Parameter USB313 in Table 29-38 regardless of the device operating voltage. If the device VDD voltage meets these requirements, it can be used to power VUSB3V3. For non-USB operation with RB11 and/or RB10 as GPIOs, the USB module must be disabled and power applied to VUSB3V3 via VDD. For non-USB operation without using RB11 and/or RB10, the VUSB3V3 pin should be connected to ground. This configuration has the lowest operating current. Note: 18.4.1 OPERATION OF PORT PINS SHARED WITH THE USB TRANSCEIVER The USB transceiver shares pins with GPIO port pins. The D+ pin is shared with RB11 and the D- pin is shared with RB10. When the USB module is enabled, the pins are controlled by the module as D+ and D-, and are not usable as GPIOs. When the module is disabled, the pins can be used as RB11 and RB10 GPIOs if the VUSB3V3 pin is powered internally or externally. Refer to Section 18.4 “Powering the USB Transceiver” for more information. To prevent additional current draw, VUSB3V3 must either be powered or grounded. DS60001387D-page 180  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY FIGURE 18-1: PIC32MM0256GPM064 FAMILY USB INTERFACE DIAGRAM USBEN USB Suspend CPU Clock not POSC Sleep Primary Oscillator (POSC) UFIN OSC1 FOUT PLL = 96 MHz Div 2 PLL(5) PLLMULT[6:0] USB Suspend To Clock Generator for Core and Peripherals OSC2 Sleep or Idle USB Module SRP Charge VBUS/RB6(2) SRP Discharge USB Voltage Comparators 48 MHz USB Clock(1) Full-Speed Pull-up D+/RB11(3) Registers and Control Interface Host Pull-Down SIE Transceiver Low-Speed Pull-up D-/RB10(3) System Memory DMA Host Pull-down ID Pull-up USBID/RB5(4) VBUSON/RB14(4) VUSB3V3 Transceiver Power 3.3V Note 1: A 48 MHz clock is required for proper USB operation. 2: This pin can be used as a GPIO when the USB module is disabled. 3: This pin can be used as a GPIO if the USB module is disabled and powered by an external source. 4: This pin is controlled by the USB module when the module is enabled in Host or OTG mode. If the module is disabled or enabled in a mode that does not require it, this pin can be reclaimed via a device Configuration bit (refer to Register 26-1).  2016-2019 Microchip Technology Inc. DS60001387D-page 181 Virtual Address (BF88_#) Register Name(1) 8440 U1OTGIR(2) U1OTGIE 8460 U1OTGSTAT(3) 8470 8480 8600 8610 8620 8630  2016-2019 Microchip Technology Inc. 8640 8650 8660 Legend: Note 1: 2: 3: 4: U1OTGCON U1PWRC U1IR(2) U1IE U1EIR(2) U1EIE U1STAT(3) U1CON U1ADDR 16/0 All Resets Bits — — 0000 — VBUSVDIF 0000 — — — 0000 SESVDIE SESENDIE — VBUSVDIE 0000 — — — — — 0000 LSTATE — SESVD SESEND — VBUSVD 0000 — — — — — — 0000 VBUSON OTGEN VBUSCHG VBUSDIS 0000 — — — — — 0000 — USLPGRD USBBUSY — USUSPEND USBPWR 0000 — — — — — — 0000 URSTIF 0000 DETACHIF 0000 — 0000 URSTIE 0000 DETACHIE 0000 — 0000 Bit Range 8450 USB OTG REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — IDIF T1MSECIF LSTATEIF ACTVIF 31:16 — — — — — — — — — — — — — 15:0 — — — — — — — — IDIE T1MSECIE LSTATEIE ACTVIE 31:16 — — — — — — — — — — — 15:0 — — — — — — — — ID — 31:16 — — — — — — — — — — 15:0 — — — — — — — — DPPULUP 31:16 — — — — — — — — — — — 15:0 — — — — — — — — UACTPND(4) — 31:16 — — — — — — — — — — 23/7 15:0 — — — — — — — — STALLIF 31:16 — — — — — — — — — 15:0 — — — — — — — — STALLIE 31:16 — — — — — — — — — 22/6 21/5 20/4 — — ATTACHIE RESUMEIE — — 18/2 17/1 — — SESVDIF SESENDIF DMPULUP DPPULDWN DMPULDWN ATTACHIF RESUMEIF 19/3 IDLEIF TRNIF SOFIF UERRIF — — — — IDLEIE TRNIE SOFIE UERRIE — — — — 15:0 — — — — — — — — BTSEF BMXEF DMAEF BTOEF DFN8EF CRC16EF 31:16 — — — — — — — — — — — — — — CRC5EF EOFEF — CRC5EE PIDEF — 0000 0000 0000 15:0 — — — — — — — — BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — DIR PPBI — — 0000 31:16 — — — — — — — — — — — — — — 0000 SE0(4) USBEN 0000 SOFEN 0000 — — 0000 ENDPT[3:0](4) 15:0 — — — — — — — — JSTATE(4) 31:16 — — — — — — — — — 15:0 — — — — — — — — LSPDEN — PKTDIS TOKBUSY — — EOFEE USBRST HOSTEN RESUME PPBRST — — — — DEVADDR[6:0] PIDEE 0000 0000 0000 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table (except as noted) have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 10.1 “CLR, SET and INV Registers” for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for these bits is undefined. PIC32MM0256GPM064 FAMILY DS60001387D-page 182 TABLE 18-1: Virtual Address (BF88_#) Register Name(1) 8670 U1BDTP1 8690 86B0 86C0 86D0 U1FRML(3) U1FRMH(3) U1TOK U1SOF U1BDTP2 U1BDTP3 86E0 U1CNFG1 8700 U1EP0 8710 8720 8730 8740 DS60001387D-page 183 8750 U1EP1 U1EP2 U1EP3 U1EP4 U1EP5 20/4 19/3 18/2 17/1 16/0 — — — — — 0000 — 0000 0000 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — — — — — — 15:0 — — — — — — — — 31:16 — — — — — — — — 15:0 — — — — — — — — 31:16 — — — — — — — — — — — 15:0 — — — — — — — — — — 31:16 — — — — — — — — — — 15:0 — — — — — — — — 31:16 — — — — — — — — 15:0 — — — — — — — — 31:16 — — — — — — — — 15:0 — — — — — — — — 31:16 — — — — — — — — 15:0 — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — UTEYE UOEMON — USBSIDL 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 BDTPTRL[7:1] — — — — — — — — — — — — — — — — — — — FRML[7:0] 0000 FRMH[2:0] — PID[3:0] — — 0000 — — EP[3:0] — — — — — — — — — — — — — — — — — — — — — — LSDEV — — 0000 0000 BDTPTRH[7:0] — 0000 0000 — CNT[7:0] — 0000 — 0000 0000 BDTPTRU[7:0] 0000 0000 0000 UASUSPND 0001 8760 U1EP6 Legend: Note 1: 2: 3: 4: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table (except as noted) have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 10.1 “CLR, SET and INV Registers” for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for these bits is undefined. PIC32MM0256GPM064 FAMILY 86A0 Bits All Resets 8680 USB OTG REGISTER MAP (CONTINUED) Bit Range  2016-2019 Microchip Technology Inc. TABLE 18-1: Virtual Address (BF88_#) Register Name(1) 8770 U1EP7 87A0 87B0 87C0 87D0 87E0 87F0 Legend: Note 1: 2: 3: 4: U1EP8 U1EP9 U1EP10 U1EP11 U1EP12 U1EP13 U1EP14 U1EP15 16/0 All Resets 8790 Bits — — 0000 EPSTALL EPHSHK 0000 — — 0000 EPTXEN EPSTALL EPHSHK 0000 — — — — 0000 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 — — — — — — 0000 — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 — — — — — — — — 0000 — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 — — — — — — — — — — 0000 — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 — — — — — — — — — — — — 0000 — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 — — — — — — — — — — — — — — 0000 — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 — — — — — — — — — — — — — — — — 0000 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 Bit Range 8780 USB OTG REGISTER MAP (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN 31:16 — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — EPCONDIS EPRXEN 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — 31:16 — — — — — — — — — — 15:0 — — — — — — — — — 31:16 — — — — — — — — 15:0 — — — — — — — 31:16 — — — — — — 15:0 — — — — — 31:16 — — — — 15:0 — — — 31:16 — — 15:0 — 31:16 15:0 20/4 19/3 18/2 17/1 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table (except as noted) have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 10.1 “CLR, SET and INV Registers” for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for these bits is undefined. PIC32MM0256GPM064 FAMILY DS60001387D-page 184 TABLE 18-1:  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 18.5 Control Registers REGISTER 18-1: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER Bit Bit Bit Range 31/23/15/7 30/22/14/6 31:24 23:16 15:8 7:0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS U-0 R/WC-0, HS IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF Legend: WC = Write ‘1’ to Clear bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 IDIF: ID State Change Indicator bit 1 = Change in ID state is detected 0 = No change in ID state is detected bit 6 T1MSECIF: 1 Millisecond Timer bit 1 = 1 millisecond timer has expired 0 = 1 millisecond timer has not expired bit 5 LSTATEIF: Line State Stable Indicator bit 1 = USB line state has been stable for 1 ms, but different from last time 0 = USB line state has not been stable for 1 ms bit 4 ACTVIF: Bus Activity Indicator bit 1 = Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up 0 = Activity has not been detected bit 3 SESVDIF: Session Valid Change Indicator bit 1 = VBUS voltage has dropped below the session end level 0 = VBUS voltage has not dropped below the session end level bit 2 SESENDIF: B-Device VBUS Change Indicator bit 1 = Change on the session end input was detected 0 = No change on the session end input was detected bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVDIF: A-Device VBUS Change Indicator bit 1 = Change on the session valid input was detected 0 = No change on the session valid input was detected  2016-2019 Microchip Technology Inc. DS60001387D-page 185 PIC32MM0256GPM064 FAMILY REGISTER 18-2: Bit Range 31:24 23:16 15:8 7:0 U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 IDIE: ID Interrupt Enable bit 1 = ID interrupt is enabled 0 = ID interrupt is disabled bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 = 1 millisecond timer interrupt is enabled 0 = 1 millisecond timer interrupt is disabled bit 5 LSTATEIE: Line State Interrupt Enable bit 1 = Line state interrupt is enabled 0 = Line state interrupt is disabled bit 4 ACTVIE: Bus Activity Interrupt Enable bit 1 = Activity interrupt is enabled 0 = Activity interrupt is disabled bit 3 SESVDIE: Session Valid Interrupt Enable bit 1 = Session valid interrupt is enabled 0 = Session valid interrupt is disabled bit 2 SESENDIE: B-Session End Interrupt Enable bit 1 = B-session end interrupt is enabled 0 = B-session end interrupt is disabled bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVDIE: A-VBUS Valid Interrupt Enable bit 1 = A-VBUS valid interrupt is enabled 0 = A-VBUS valid interrupt is disabled DS60001387D-page 186  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 18-3: Bit Range 31:24 23:16 15:8 7:0 U1OTGSTAT: USB OTG STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 U-0 R-0 U-0 R-0 R-0 U-0 R-0 ID — LSTATE — SESVD SESEND — VBUSVD Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 ID: ID Pin State Indicator bit 1 = No cable is attached or a “Type B” cable has been inserted into the USB receptacle 0 = A “Type A” OTG cable has been inserted into the USB receptacle bit 6 Unimplemented: Read as ‘0’ bit 5 LSTATE: Line State Stable Indicator bit 1 = USB line state (SE0 (U1CON[6] and JSTATE (U1CON[7]) has been stable for the previous 1 ms 0 = USB line state (SE0 (U1CON[6] and JSTATE (U1CON[7]) has not been stable for the previous 1 ms bit 4 Unimplemented: Read as ‘0’ bit 3 SESVD: Session Valid Indicator bit 1 = The VBUS voltage is above VA_SESS_VLD (as defined in the USB OTG Specification) on the A or B-device 0 = The VBUS voltage is below VA_SESS_VLD on the A or B-device bit 2 SESEND: B-Device Session End Indicator bit 1 = The VBUS voltage is above VB_SESS_END (as defined in the USB OTG Specification) on the B-device 0 = The VBUS voltage is below VB_SESS_END on the B-device bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVD: A-Device VBUS Valid Indicator bit 1 = The VBUS voltage is above VA_VBUS_VLD (as defined in the USB OTG Specification) on the A-device 0 = The VBUS voltage is below VA_VBUS_VLD on the A-device  2016-2019 Microchip Technology Inc. DS60001387D-page 187 PIC32MM0256GPM064 FAMILY REGISTER 18-4: Bit Range 31:24 23:16 15:8 7:0 U1OTGCON: USB OTG CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VBUSON OTGEN VBUSCHG VBUSDIS DPPULUP DMPULUP DPPULDWN DMPULDWN Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 DPPULUP: D+ Pull-Up Enable bit 1 = D+ data line pull-up resistor is enabled 0 = D+ data line pull-up resistor is disabled bit 6 DMPULUP: D- Pull-Up Enable bit 1 = D- data line pull-up resistor is enabled 0 = D- data line pull-up resistor is disabled bit 5 DPPULDWN: D+ Pull-Down Enable bit 1 = D+ data line pull-down resistor is enabled 0 = D+ data line pull-down resistor is disabled bit 4 DMPULDWN: D- Pull-Down Enable bit 1 = D- data line pull-down resistor is enabled 0 = D- data line pull-down resistor is disabled bit 3 VBUSON: VBUS Power-on bit 1 = VBUS line is powered 0 = VBUS line is not powered bit 2 OTGEN: OTG Functionality Enable bit 1 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control 0 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control bit 1 VBUSCHG: VBUS Charge Enable bit 1 = VBUS line is charged through a pull-up resistor 0 = VBUS line is not charged through a resistor bit 0 VBUSDIS: VBUS Discharge Enable bit 1 = VBUS line is discharged through a pull-down resistor 0 = VBUS line is not discharged through a resistor DS60001387D-page 188  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 18-5: U1PWRC: USB POWER CONTROL REGISTER Bit Bit Bit Range 31/23/15/7 30/22/14/6 31:24 23:16 15:8 7:0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UACTPND — — USLPGRD USBBUSY(1) — USUSPEND USBPWR(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 UACTPND: USB Activity Pending bit 1 = USB bus activity has been detected, but an interrupt is pending; it has not been generated yet 0 = An interrupt is not pending bit 6-5 Unimplemented: Read as ‘0’ bit 4 USLPGRD: USB Sleep Entry Guard bit 1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending 0 = USB module does not block Sleep entry bit 3 USBBUSY: USB Module Busy bit(1) 1 = USB module is active or disabled, but not ready to be enabled 0 = USB module is not active and is ready to be enabled bit 2 Unimplemented: Read as ‘0’ bit 1 USUSPEND: USB Suspend Mode bit 1 = USB module is placed in Suspend mode (The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.) 0 = USB module operates normally bit 0 USBPWR: USB Operation Enable bit(1) 1 = USB module is turned on 0 = USB module is disabled (Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power consumption.) Note 1: When USBPWR = 0 and USBBUSY = 1, status from all other registers is invalid and writes to all USB module registers produce undefined results.  2016-2019 Microchip Technology Inc. DS60001387D-page 189 PIC32MM0256GPM064 FAMILY REGISTER 18-6: U1IR: USB INTERRUPT REGISTER Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R-0 IDLEIF TRNIF(3) SOFIF UERRIF(4) R/WC-0, HS (5) STALLIF ATTACHIF(1) RESUMEIF(2) Legend: WC = Write ‘1’ to Clear bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared URSTIF DETACHIF(6) x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 STALLIF: Stall Handshake Interrupt bit 1 = In Host mode, a Stall handshake was received during the handshake phase of the transaction; in Device mode, a Stall handshake was transmitted during the handshake phase of the transaction 0 = Stall handshake has not been sent bit 6 ATTACHIF: Peripheral Attach Interrupt bit(1) 1 = Peripheral attachment was detected by the USB module 0 = Peripheral attachment was not detected bit 5 RESUMEIF: Resume Interrupt bit(2) 1 = K-State is observed on the D+ or D- pin for 2.5 µs 0 = K-State is not observed bit 4 IDLEIF: Idle Detect Interrupt bit 1 = Idle condition detected (constant Idle state of 3 ms or more) 0 = No Idle condition detected bit 3 TRNIF: Token Processing Complete Interrupt bit(3) 1 = Processing of current token is complete; a read of the U1STAT register will provide endpoint information 0 = Processing of current token not complete bit 2 SOFIF: SOF Token Interrupt bit 1 = SOF token received by the peripheral or the SOF threshold reached by the host 0 = SOF token was not received nor threshold reached bit 1 UERRIF: USB Error Condition Interrupt bit(4) 1 = Unmasked error condition has occurred 0 = Unmasked error condition has not occurred Note 1: 2: 3: 4: 5: 6: This bit is only valid if the HOSTEN bit is set (see Register 18-11), there is no activity on the USB for 2.5 µs and the current bus state is not SE0. When not in Suspend mode, this interrupt should be disabled. Clearing this bit will cause the STAT FIFO to advance. Only error conditions enabled through the U1EIE register will set this bit. Device mode. Host mode. DS60001387D-page 190  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 18-6: U1IR: USB INTERRUPT REGISTER (CONTINUED) URSTIF: USB Reset Interrupt bit (Device mode)(5) 1 = Valid USB Reset has occurred 0 = No USB Reset has occurred bit 0 DETACHIF: USB Detach Interrupt bit (Host mode)(6) 1 = Peripheral detachment was detected by the USB module 0 = Peripheral detachment was not detected Note 1: 2: 3: 4: 5: 6: This bit is only valid if the HOSTEN bit is set (see Register 18-11), there is no activity on the USB for 2.5 µs and the current bus state is not SE0. When not in Suspend mode, this interrupt should be disabled. Clearing this bit will cause the STAT FIFO to advance. Only error conditions enabled through the U1EIE register will set this bit. Device mode. Host mode.  2016-2019 Microchip Technology Inc. DS60001387D-page 191 PIC32MM0256GPM064 FAMILY REGISTER 18-7: Bit Range 31:24 23:16 15:8 7:0 U1IE: USB INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IDLEIE TRNIE SOFIE UERRIE(1) STALLIE ATTACHIE RESUMEIE URSTIE(2) DETACHIE(3) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 STALLIE: Stall Handshake Interrupt Enable bit 1 = Stall interrupt is enabled 0 = Stall interrupt is disabled bit 6 ATTACHIE: Attach Interrupt Enable bit 1 = Attach interrupt is enabled 0 = Attach interrupt is disabled bit 5 RESUMEIE: Resume Interrupt Enable bit 1 = Resume interrupt is enabled 0 = Resume interrupt is disabled bit 4 IDLEIE: Idle Detect Interrupt Enable bit 1 = Idle interrupt is enabled 0 = Idle interrupt is disabled bit 3 TRNIE: Token Processing Complete Interrupt Enable bit 1 = TRNIF interrupt is enabled 0 = TRNIF interrupt is disabled bit 2 SOFIE: SOF Token Interrupt Enable bit 1 = SOFIF interrupt is enabled 0 = SOFIF interrupt is disabled bit 1 UERRIE: USB Error Interrupt Enable bit(1) 1 = USB error interrupt is enabled 0 = USB error interrupt is disabled bit 0 URSTIE: USB Reset Interrupt Enable bit(2) 1 = URSTIF interrupt is enabled 0 = URSTIF interrupt is disabled DETACHIE: USB Detach Interrupt Enable bit(3) 1 = DATTCHIF interrupt is enabled 0 = DATTCHIF interrupt is disabled Note 1: 2: 3: For an interrupt to propagate USBIF, the UERRIE bit (U1IE[1]) must be set. Device mode. Host mode. DS60001387D-page 192  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 18-8: Bit Range 31:24 23:16 15:8 7:0 U1EIR: USB ERROR INTERRUPT STATUS REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS BTSEF BMXEF DMAEF(1) BTOEF(2) R/WC-0, HS (4) DFN8EF CRC16EF CRC5EF EOFEF(3,5) Legend: WC = Write ‘1’ to Clear bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared PIDEF x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 BTSEF: Bit Stuff Error Flag bit 1 = Packet rejected due to bit stuff error 0 = Packet accepted bit 6 BMXEF: Bus Matrix Error Flag bit 1 = Invalid base address of the BDT or the address of an individual buffer pointed to by a BDT entry 0 = No address error bit 5 DMAEF: DMA Error Flag bit(1) 1 = USB DMA error condition detected 0 = No DMA error bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit(2) 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out has occurred bit 3 DFN8EF: Data Field Size Error Flag bit 1 = Data field received is not an integral number of bytes 0 = Data field received is an integral number of bytes bit 2 CRC16EF: CRC16 Failure Flag bit 1 = Data packet rejected due to CRC16 error 0 = Data packet accepted Note 1: 2: 3: 4: 5: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the received data packet causing it to be truncated. This type of error occurs when more than 16-bit times of Idle from the previous End-of-Packet (EOP) has elapsed. This type of error occurs when the module is transmitting or receiving data and the SOF counter has reached zero. Device mode. Host mode.  2016-2019 Microchip Technology Inc. DS60001387D-page 193 PIC32MM0256GPM064 FAMILY REGISTER 18-8: U1EIR: USB ERROR INTERRUPT STATUS REGISTER (CONTINUED) CRC5EF: CRC5 Host Error Flag bit(4) 1 = Token packet rejected due to CRC5 error 0 = Token packet accepted bit 1 EOFEF: EOF Error Flag bit(3,5) 1 = EOF error condition detected 0 = No EOF error condition bit 0 PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed Note 1: 2: 3: 4: 5: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the received data packet causing it to be truncated. This type of error occurs when more than 16-bit times of Idle from the previous End-of-Packet (EOP) has elapsed. This type of error occurs when the module is transmitting or receiving data and the SOF counter has reached zero. Device mode. Host mode. DS60001387D-page 194  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 18-9: Bit Range 31:24 23:16 15:8 7:0 U1EIE: USB ERROR INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE CRC5EE(1) EOFEE(2) PIDEE Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = BTSEF interrupt is enabled 0 = BTSEF interrupt is disabled bit 6 BMXEE: Bus Matrix Error Interrupt Enable bit 1 = BMXEF interrupt is enabled 0 = BMXEF interrupt is disabled bit 5 DMAEE: DMA Error Interrupt Enable bit 1 = DMAEF interrupt is enabled 0 = DMAEF interrupt is disabled bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = BTOEF interrupt is enabled 0 = BTOEF interrupt is disabled bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit 1 = DFN8EF interrupt is enabled 0 = DFN8EF interrupt is disabled bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit 1 = CRC16EF interrupt is enabled 0 = CRC16EF interrupt is disabled bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit(1) 1 = CRC5EF interrupt is enabled 0 = CRC5EF interrupt is disabled EOFEE: EOF Error Interrupt Enable bit(2) 1 = EOF interrupt is enabled 0 = EOF interrupt is disabled bit 0 Note 1: 2: PIDEE: PID Check Failure Interrupt Enable bit 1 = PIDEF interrupt is enabled 0 = PIDEF interrupt is disabled Device mode. Host mode.  2016-2019 Microchip Technology Inc. DS60001387D-page 195 PIC32MM0256GPM064 FAMILY REGISTER 18-10: U1STAT: USB STATUS REGISTER(1) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-x R-x R-x R-x R-x R-x U-0 U-0 DIR PPBI — — ENDPT[3:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-4 ENDPT[3:0]: Encoded Number of Last Endpoint Activity bits (Represents the number of the BDT, updated by the last USB transfer.) 1111 = Endpoint 15 1110 = Endpoint 14 • • • 0001 = Endpoint 1 0000 = Endpoint 0 bit 3 DIR: Last Buffer Descriptor Direction Indicator bit 1 = Last transaction was a transmit transfer (TX) 0 = Last transaction was a receive transfer (RX) bit 2 PPBI: Ping-Pong Buffer Descriptor Pointer Indicator bit 1 = Last transaction was to the Odd buffer descriptor bank 0 = Last transaction was to the Even buffer descriptor bank bit 1-0 Unimplemented: Read as ‘0’ Note 1: The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. The U1STAT value is only valid when TRNIF (U1IR[3]) is active. Clearing the TRNIF bit advances the FIFO. The data in the register are invalid when TRNIF = 0. DS60001387D-page 196  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 18-11: U1CON: USB CONTROL REGISTER Bit Bit Bit Range 31/23/15/7 30/22/14/6 31:24 23:16 15:8 7:0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 JSTATE SE0 PKTDIS(4) (1,5) TOKBUSY USBRST HOSTEN(2) RESUME(3) PPBRST USBEN(4) SOFEN(5) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 JSTATE: Live Differential Receiver JSTATE Flag bit 1 = JSTATE was detected on the USB 0 = JSTATE was not detected bit 6 SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero was detected on the USB 0 = Single-ended zero was not detected bit 5 PKTDIS: Packet Transfer Disable bit(4) 1 = Token and packet processing are disabled (set upon SETUP token received) 0 = Token and packet processing are enabled TOKBUSY: Token Busy Indicator bit(1,5) 1 = Token is being executed by the USB module 0 = No token is being executed bit 4 USBRST: Module Reset bit 1 = USB Reset is generated 0 = USB Reset is terminated bit 3 HOSTEN: Host Mode Enable bit(2) 1 = USB host capability is enabled 0 = USB host capability is disabled bit 2 RESUME: Resume Signaling Enable bit(3) 1 = Resume signaling is activated 0 = Resume signaling is disabled Note 1: 2: 3: 4: 5: Software is required to check this bit before issuing another token command to the U1TOK register (see Register 18-15). All host control logic is reset any time that the value of this bit is toggled. Software must set RESUME for 10 ms in Device mode, or for 25 ms in Host mode, and then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the Resume  signaling when this bit is cleared. Device mode. Host mode.  2016-2019 Microchip Technology Inc. DS60001387D-page 197 PIC32MM0256GPM064 FAMILY REGISTER 18-11: U1CON: USB CONTROL REGISTER (CONTINUED) bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Resets all Even/Odd Buffer Pointers to the Even buffer descriptor banks 0 = Even/Odd Buffer Pointers are not reset bit 0 USBEN: USB Module Enable bit(4) 1 = USB module and supporting circuitry are enabled 0 = USB module and supporting circuitry are disabled SOFEN: SOF Enable bit(5) 1 = SOF token is sent every 1 ms 0 = SOF token is disabled Note 1: 2: 3: 4: 5: Software is required to check this bit before issuing another token command to the U1TOK register (see Register 18-15). All host control logic is reset any time that the value of this bit is toggled. Software must set RESUME for 10 ms in Device mode, or for 25 ms in Host mode, and then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the Resume  signaling when this bit is cleared. Device mode. Host mode. DS60001387D-page 198  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 18-12: U1ADDR: USB ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPDEN DEVADDR[6:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 LSPDEN: Low-Speed Enable Indicator bit 1 = Next token command to be executed at low speed 0 = Next token command to be executed at full speed bit 6-0 DEVADDR[6:0]: 7-Bit USB Device Address bits  2016-2019 Microchip Technology Inc. DS60001387D-page 199 PIC32MM0256GPM064 FAMILY REGISTER 18-13: U1FRML: USB FRAME NUMBER LOW REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 FRML[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 FRML[7:0]: 11-Bit Frame Number Lower bits These register bits are updated with the current frame number whenever a SOF token is received. REGISTER 18-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — FRMH[2:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-3 Unimplemented: Read as ‘0’ bit 2-0 FRMH[2:0]: Upper 3 Bits of the Frame Numbers bits These register bits are updated with the current frame number whenever a SOF token is received. DS60001387D-page 200  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 18-15: U1TOK: USB TOKEN REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — R/W-0 R/W-0 — R/W-0 (1) — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PID[3:0] EP[3:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-4 PID[3:0]: Token Type Indicator bits(1) 1101 = SETUP (TX) token type transaction 1001 = IN (RX) token type transaction 0001 = OUT (TX) token type transaction bit 3-0 EP[3:0]: Token Command Endpoint Address bits The 4-bit value must specify a valid endpoint. Note 1: All other values not listed are reserved and must not be used. REGISTER 18-16: U1SOF: USB SOF THRESHOLD REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 CNT[7:0]: SOF Threshold Value bits Typical Values of the Threshold are: 01001010 = 64-byte packet 00101010 = 32-byte packet 00011010 = 16-byte packet 00010010 = 8-byte packet  2016-2019 Microchip Technology Inc. DS60001387D-page 201 PIC32MM0256GPM064 FAMILY REGISTER 18-17: U1BDTP1: USB BUFFER DESCRIPTOR TABLE PAGE 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 BDTPTRL[7:1] — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-1 BDTPTRL[7:1]: BDT Base Address bits This 7-bit value provides Address bits 7 through 1 of the BDT base address, which defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. bit 0 Unimplemented: Read as ‘0’ REGISTER 18-18: U1BDTP2: USB BUFFER DESCRIPTOR TABLE PAGE 2 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDTPTRH[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 BDTPTRH[7:0]: BDT Base Address bits This 8-bit value provides Address bits 7 through 0 of the BDT base address, which defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. DS60001387D-page 202  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 18-19: U1BDTP3: USB BUFFER DESCRIPTOR TABLE PAGE 3 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDTPTRU[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 BDTPTRU[7:0]: BDT Base Address bits This 8-bit value provides Address bits 7 through 0 of the BDT base address, defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned.  2016-2019 Microchip Technology Inc. DS60001387D-page 203 PIC32MM0256GPM064 FAMILY REGISTER 18-20: U1CNFG1: USB CONFIGURATION 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 UTEYE UOEMON — USBSIDL LSDEV — — UASUSPND Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test is enabled 0 = Eye pattern test is disabled bit 6 UOEMON: USB OE Monitor Enable bit 1 = OE signal is active; it indicates intervals during which the D+/D- lines are driving 0 = OE signal is inactive bit 5 Unimplemented: Read as ‘0’ bit 4 USBSIDL: USB Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 3 LSDEV: USB Low-Speed Device Enable bit 1 = USB macro operates in Low-Speed Device Only mode 0 = USB macro operates in OTG, Host or Fast Speed Device mode bit 2-1 Unimplemented: Read as ‘0’ bit 0 UASUSPND: Automatic Suspend Enable bit 1 = USB module automatically suspends upon entry to Sleep mode; see the USUSPEND bit (U1PWRC[1]) in Register 18-5 0 = USB module does not automatically suspend upon entry to Sleep mode; software must use the USUSPEND bit (U1PWRC[1]) to suspend the module, including the USB 48 MHz clock DS60001387D-page 204  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 18-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only) 1 = Direct connection to a low-speed device is enabled 0 = Direct connection to a low-speed device is disabled; hub required with PRE_PID bit 6 RETRYDIS: Retry Disable bit (Host mode and U1EP0 only) 1 = Retry NACK’d transactions are disabled 0 = Retry NACK’d transactions are enabled; retry done in hardware bit 5 Unimplemented: Read as ‘0’ bit 4 EPCONDIS: Bidirectional Endpoint Control bit If EPTXEN = 1 and EPRXEN = 1: 1 = Disables Endpoint n from control transfers; only TX and RX transfers are allowed 0 = Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed Otherwise, this bit is ignored. bit 3 EPRXEN: Endpoint Receive Enable bit 1 = Endpoint n receive is enabled 0 = Endpoint n receive is disabled bit 2 EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint n transmit is enabled 0 = Endpoint n transmit is disabled bit 1 EPSTALL: Endpoint Stall Status bit 1 = Endpoint n was stalled 0 = Endpoint n was not stalled bit 0 EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint handshake is enabled 0 = Endpoint handshake is disabled (typically used for isochronous endpoints)  2016-2019 Microchip Technology Inc. DS60001387D-page 205 PIC32MM0256GPM064 FAMILY NOTES: DS60001387D-page 206  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 19.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 28. “RTCC with Timestamp” (www.microchip.com/ DS60001362) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. The RTCC module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no CPU intervention. Lowpower optimization provides extended battery lifetime while keeping track of time. Key features of the RTCC module are: • • • • • • • • • • • • • • • FIGURE 19-1: Time: Hours, Minutes and Seconds 24-Hour Format (military time) Visibility of One-Half Second Period Provides Calendar: Weekday, Date, Month and Year Alarm Intervals are Configurable for Half of a Second, 1 Second, 10 Seconds, 1 Minute, 10 Minutes, 1 Hour, 1 Day, 1 Week, 1 Month and 1 Year Alarm Repeat with Decrementing Counter Alarm with Indefinite Repeat: Chime Year Range: 2000 to 2099 Leap Year Correction BCD Format for Smaller Firmware Overhead Optimized for Long-Term Battery Operation Fractional Second Synchronization User Calibration of the Clock Crystal Frequency with Auto-Adjust Uses External 32.768 kHz Crystal, 32 kHz Internal Oscillator, PWRLCLK Input Pin or Peripheral Clock Alarm Pulse, Seconds Clock or Internal Clock  Output on RTCC Pin RTCC BLOCK DIAGRAM CLKSEL[1:0] PWRLCLK Input Pin Peripheral Clock (PBCLK) 32.768 kHz Input from Secondary Oscillator (SOSC) 32 kHz Input from Internal Oscillator (LPRC) TRTC RTCC Prescalers 0.5 seconds RTCC Timer Alarm Event YEAR, MTH, DAY RTCVAL WKDAY HR, MIN, SEC Comparator MTH, DAY Compare Registers with Masks WKDAY ALRMVAL HR, MIN, SEC Repeat Counter RTCC Interrupt Alarm Pulse RTCC Interrupt Logic Seconds Pulse RTCC Pin(1) TRTC RTCOE OUTSEL[2:0] Note 1: In Retention mode, the maximum peripheral output frequency to an I/O pin must be limited to 33 kHz or less.  2016-2019 Microchip Technology Inc. DS60001387D-page 207 RTCC Control Registers RTCC REGISTER MAP 0000 RTCCON1 0010 RTCCON2 0030 RTCSTAT 0040 RTCTIME 0050 RTCDATE 0060 ALMTIME 0070 ALMDATE 31/15 29/13 28/12 31:16 ALRMEN CHIME — — 15:0 — — ON 30/14 — 27/11 26/10 25/9 24/8 23/7 RTCOE 22/6 21/5 20/4 AMASK[3:0] WRLOCK 18/2 17/1 16/0 — — — — — — CLKSEL[1:0] 0000 — 0000 ALMRPT[7:0] — — — — — — — — — — — — — — — — — — 31:16 OUTSEL[2:0] 0000 DIV[15:0] 15:0 FDIV[4:0] 31:16 — — 15:0 — — 31:16 — 15:0 — — — — — — HRTEN[2:0] 31:16 15:0 — 31:16 — 15:0 — — — — ALMEVT — — SYNC HRONE[3:0] — SECONE[3:0] — — — — YRTEN[3:0] YRONE[3:0] — — — MTHTEN — DAYONE[3:0] — — — — — HRONE[3:0] — SECONE[3:0] — — — — — — — — MTHTEN — — — — SECTEN[3:0] DAYTEN[1:0] HRTEN[2:0] SECTEN[3:0] 31:16 — — — 15:0 — — DAYTEN[1:0] — — — — — DAYONE[3:0] 0000 0000 PS[1:0] MINTEN[2:0] — ALMSYNC HALFSEC MINONE[3:0] — — — 0000 MINONE[3:0] All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. — MTHONE[3:0] — WDAY[2:0] xx00 0000 WDAY[2:0] — 0000 xxxx — MTHONE[3:0] MINTEN[2:0] Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: 19/3 All Resets Bit Range Bits Register Name(1) Virtual Address (BF80_#) TABLE 19-1: xxxx — xx00 0000 0000 PIC32MM0256GPM064 FAMILY DS60001387D-page 208 19.1  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 19-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 RTCCON1: RTCC CONTROL 1 REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 ALRMEN CHIME — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 ON — — R/W-0 R/W-0 R/W-0 AMASK[3:0] R/W-0 (1) R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 — WRLOCK — — — R/W-0 U-0 U-0 U-0 U-0 — — — — ALMRPT[7:0] RTCOE OUTSEL[2:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 ALRMEN: Alarm Enable bit 1 = Alarm is enabled 0 = Alarm is disabled bit 30 CHIME: Chime Enable bit 1 = Chime is enabled; ALMRPT[7:0] bits are allowed to underflow from ‘00’ to ‘FF’ 0 = Chime is disabled; ALMRPT[7:0] bits stop once they reach ‘00’ bit 29-28 Unimplemented: Read as ‘0’ bit 27-24 AMASK[3:0]: Alarm Mask Configuration bits 11xx = Reserved, do not use 101x = Reserved, do not use 1001 = Once a year (or once every four years when configured for February 29th) 1000 = Once a month 0111 = Once a week 0110 = Once a day 0101 = Every hour 0100 = Every ten minutes 0011 = Every minute 0010 = Every ten seconds 0001 = Every second 0000 = Every half-second bit 23-16 ALMRPT[7:0]: Alarm Repeat Counter Value bits(1) 11111111 = Alarm will repeat 255 more times 11111110 = Alarm will repeat 254 more times ••• 00000010 = Alarm will repeat 2 more times 00000001 = Alarm will repeat 1 more time 00000000 = Alarm will not repeat bit 15 ON: RTCC Enable bit 1 = RTCC is enabled and counts from selected clock source 0 = RTCC is disabled bit 14-12 Unimplemented: Read as ‘0’ Note 1: The counter decrements on any alarm event. The counter is prevented from rolling over from ‘00’ to ‘FF’ unless CHIME = 1.  2016-2019 Microchip Technology Inc. DS60001387D-page 209 PIC32MM0256GPM064 FAMILY REGISTER 19-1: RTCCON1: RTCC CONTROL 1 REGISTER (CONTINUED) bit 11 WRLOCK: RTCC Registers Write Lock bit 1 = Registers associated with accurate timekeeping are locked 0 = Registers associated with accurate timekeeping may be written to by user bit 10-8 Unimplemented: Read as ‘0’ bit 7 RTCOE: RTCC Output Enable bit 1 = RTCC clock output is enabled; signal selected by OUTSEL[2:0] is presented on the RTCC pin 0 = RTCC clock output is disabled bit 6-4 OUTSEL[2:0]: RTCC Signal Output Selection bits 111 = Reserved ••• 011 = Reserved 010 = RTCC input clock source (user-defined divided output based on the combination of the RTCCON2 bits, DIV[15:0] and PS[1:0]) 001 = Seconds clock 000 = Alarm event bit 3-0 Unimplemented: Read as ‘0’ Note 1: The counter decrements on any alarm event. The counter is prevented from rolling over from ‘00’ to ‘FF’ unless CHIME = 1. DS60001387D-page 210  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 19-2: Bit Range 31:24 23:16 15:8 7:0 RTCCON2: RTCC CONTROL 2 REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 — — — U-0 U-0 R/W-0 R/W-0 — — DIV[15:8] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DIV[7:0] FDIV[4:0] U-0 U-0 — — R/W-0 R/W-0 PS[1:0] CLKSEL[1:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 DIV[15:0]: Clock Divide bits Sets the period of the clock divider counter for the seconds output. bit 15-11 FDIV[4:0]: Fractional Clock Divide bits 11111 = Clock period increases by 31 RTCC input clock cycles every 16 seconds 11101 = Clock period increases by 30 RTCC input clock cycles every 16 seconds ••• 00010 = Clock period increases by 2 RTCC input clock cycles every 16 seconds 00001 = Clock period increases by 1 RTCC input clock cycle every 16 seconds 00000 = No fractional clock division bit 10-6 Unimplemented: Read as ‘0’ bit 5-4 PS[1:0]: Prescale Select bits Sets the prescaler for the seconds output. 11 = 1:256 10 = 1:64 01 = 1:16 00 = 1:1 bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CLKSEL[1:0]: Clock Select bits 11 = Peripheral clock (FCY) 10 = PWRLCLK input pin 01 = LPRC 00 = SOSC  2016-2019 Microchip Technology Inc. DS60001387D-page 211 PIC32MM0256GPM064 FAMILY REGISTER 19-3: Bit Range 31:24 23:16 15:8 7:0 RTCSTAT: RTCC STATUS REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R-0, HS, HC U-0 U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC — — ALMEVT — — SYNC ALMSYNC HALFSEC Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-6 Unimplemented: Read as ‘0’ bit 5 ALMEVT: Alarm Event bit 1 = An alarm event has occurred 0 = An alarm event has not occurred bit 4-3 Unimplemented: Read as ‘0’ bit 2 SYNC: Synchronization Status bit 1 = Time registers may change during software read 0 = Time registers may be read safely bit 1 ALMSYNC: Alarm Synchronization Status bit 1 = Alarm registers (ALMTIME and ALMDATE) and RTCCON1 should not be modified; the ALRMEN and ALMRPT[7:0] bits may change during software read 0 = Alarm registers and Alarm Control registers may be modified safely bit 0 HALFSEC: Half-Second Status bit 1 = Second half of 1-second period 0 = First half of 1-second period DS60001387D-page 212  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 19-4: Bit Range 31:24 23:16 15:8 7:0 RTCTIME/ALMTIME: RTCC TIME/ALARM REGISTERS Bit 31/23/15/7 Bit 30/22/14/6 U-0 R/W-0 — U-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HRTEN[2:0] R/W-0 — R/W-0 Bit 29/21/13/5 R/W-0 HRONE[3:0] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MINTEN[2:0] R/W-0 R/W-0 R/W-0 R/W-0 MINONE[3:0] SECTEN[3:0] R/W-0 R/W-0 SECONE[3:0] U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31 x = Bit is unknown Unimplemented: Read as ‘0’ bit 30-28 HRTEN[2:0]: Binary Coded Decimal Value of Hours 10-Digit bits Contains a value from 0 to 2. bit 27-24 HRONE[3:0]: Binary Coded Decimal Value of Hours 1-Digit bits Contains a value from 0 to 9. bit 23 Unimplemented: Read as ‘0’ bit 22-20 MINTEN[2:0]: Binary Coded Decimal Value of Minutes 10-Digit bits Contains a value from 0 to 5. bit 19-16 MINONE[3:0]: Binary Coded Decimal Value of Minutes 1-Digit bits Contains a value from 0 to 9. bit 15-12 SECTEN[2:0]: Binary Coded Decimal Value of Seconds 10-Digit bits Contains a value from 0 to 5. bit 11-8 SECONE[3:0]: Binary Coded Decimal Value of Seconds 1-Digit bits Contains a value from 0 to 9. bit 7-0 Unimplemented: Read as ‘0’  2016-2019 Microchip Technology Inc. DS60001387D-page 213 PIC32MM0256GPM064 FAMILY REGISTER 19-5: Bit Range 31:24 23:16 15:8 7:0 RTCDATE/ALMDATE: RTCC DATE/ALARM REGISTERS Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — MTHTEN U-0 U-0 R/W-0 R/W-0 — — U-0 U-0 U-0 U-0 U-0 — — — — — MTHONE[3:0] R/W-0 R/W-0 DAYTEN[1:0] R/W-0 R/W-0 DAYONE[3:0] R/W-0 R/W-0 R/W-0 WDAY[2:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-21 Unimplemented: Read as ‘0’ bit 20 MTHTEN: Binary Coded Decimal Value of Months 10-Digit bit Contains a value from 0 to 1. bit 19-16 MTHONE[3:0]: Binary Coded Decimal Value of Months 1-Digit bits Contains a value from 0 to 9. bit 15-14 Unimplemented: Read as ‘0’ bit 13-12 DAYTEN[1:0]: Binary Coded Decimal Value of Days 10-Digit bits Contains a value from 0 to 3. bit 11-8 DAYONE[3:0]: Binary Coded Decimal Value of Days 1-Digit bits Contains a value from 0 to 9. bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY[2:0]: Binary Coded Decimal Value of Weekdays Digit bits Contains a value from 0 to 6. DS60001387D-page 214  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 20.0 Note: 20.1 12-BIT ADC CONVERTER WITH THRESHOLD DETECT This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 25. “12-Bit Analog-to-Digital Converter (ADC) with Threshold Detect” (www.microchip.com/DS60001359) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. Introduction The 12-bit ADC Converter with Threshold Detect includes the following features: • Successive Approximation Register (SAR)  Conversion • Conversion Speeds of up to 300 ksps • User-Selectable Resolution of 10 or 12 Bits • Up to 24 Analog Inputs (internal and external) • External Voltage Reference Input Pins • Unipolar Differential Sample-and-Hold  Amplifier (SHA) FIGURE 20-1: • Automated Threshold Scan and Compare  Operation to Pre-Evaluate Conversion Results • Selectable Conversion Trigger Source • Fixed-Length Configurable Conversion Result Buffer • Eight Options for Result Alignment and Encoding • Configurable Interrupt Generation • Operation during CPU Sleep and Idle modes Figure 20-1 illustrates a block diagram of the 12-bit ADC. The 12-bit ADC has external analog inputs, AN0 through AN19, and four internal analog inputs connected to VDD, VSS, VCORE and band gap. In addition, there are two analog input pins for external voltage reference connections. The analog inputs are connected through a multiplexer to the SHA. Unipolar differential conversions are possible on all inputs (see Figure 20-1). The Automatic Input Scan mode sequentially converts multiple analog inputs. A special control register specifies which inputs will be included in the scanning sequence. The 12-bit ADC is connected to a 22-word result buffer. The 12-bit result is converted to one of eight output formats in either 32-bit or 16-bit word widths. ADC BLOCK DIAGRAM VREF+ AVDD VREF- AVSS VCFG[2:0] AVDD AVSS VCORE Band Gap AN19 ADC1BUF0 ADC1BUF1 VREFH AN0 VREFL ADC1BUF2 SHA Channel Scan + SAR ADC – CH0SA[4:0] CSCNA AVss  2016-2019 Microchip Technology Inc. ADC1BUF20 ADC1BUF21 DS60001387D-page 215 PIC32MM0256GPM064 FAMILY 20.2 Control Registers The ADC module has the following Special Function Registers (SFRs): • • • • AD1CON1: ADC Control Register 1 AD1CON2: ADC Control Register 2 AD1CON3: ADC Control Register 3 AD1CON5: ADC Control Register 5 The AD1CON1, AD1CON2, AD1CON3 and AD1CON5 registers control the operation of the ADC module. • AD1CHS: ADC Input Select Register The AD1CHS register selects the input pins to be connected to the SHA. DS60001387D-page 216 • AD1CSS: ADC Input Scan Select Register The AD1CSS register selects inputs to be sequentially scanned. • AD1CHIT: ADC Compare Hit Register The AD1CHIT register indicates the channels meeting specified comparison requirements. Table 20-1 provides a summary of all ADC related registers, including their addresses and formats. Corresponding registers appear after the summary, followed by a detailed description of each register. All unimplemented registers and/or bits within a register read as zero.  2016-2019 Microchip Technology Inc. Virtual Address (BF80_#) Register Name(2) 2100 ADC1BUF0 2110 2120 2130 2150 2160 2170 2180 2190 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 21A0 ADC1BUF10 21B0 ADC1BUF11 21C0 ADC1BUF12 DS60001387D-page 217 21D0 ADC1BUF13 21E0 ADC1BUF14 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 ADC1BUF0[31:0] ADC1BUF1[31:0] ADC1BUF2[31:0] ADC1BUF3[31:0] ADC1BUF4[31:0] ADC1BUF5[31:0] ADC1BUF6[31:0] ADC1BUF7[31:0] ADC1BUF8[31:0] ADC1BUF9[31:0] ADC1BUF10[31:0] ADC1BUF11[31:0] ADC1BUF12[31:0] ADC1BUF13[31:0] ADC1BUF14[31:0] Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: The CSS[19:12] bits are not implemented in 28-pin devices. The CSS[19:15] bits are not implemented in 36-pin and 40-pin devices. The CSS[17:14] bits are not implemented in 48-pin devices. 2: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. All Resets Bits 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PIC32MM0256GPM064 FAMILY 2140 ADC REGISTER MAP Bit Range  2016-2019 Microchip Technology Inc. TABLE 20-1: 2200 ADC1BUF16 2210 ADC1BUF17 2220 ADC1BUF18 2230 ADC1BUF19 2240 ADC1BUF20 2250 ADC1BUF21 2270 2280  2016-2019 Microchip Technology Inc. 2290 22A0 AD1CON1 AD1CON2 AD1CON3 AD1CHS AD1CSS 22C0 AD1CON5 22D0 AD1CHIT 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 24/8 23/7 22/6 21/5 20/4 18/2 17/1 16/0 0000 ADC1BUF15[31:0] 15:0 31:16 0000 0000 ADC1BUF16[31:0] 15:0 31:16 0000 0000 ADC1BUF17[31:0] 15:0 31:16 0000 0000 ADC1BUF18[31:0] 15:0 31:16 0000 0000 ADC1BUF19[31:0] 15:0 31:16 0000 0000 ADC1BUF20[31:0] 15:0 31:16 0000 0000 ADC1BUF21[31:0] 15:0 31:16 — 15:0 ON 31:16 — 15:0 — — — — — SIDL — — — — — VCFG[2:0] OFFCAL 31:16 — — — 15:0 ADRC EXTSAM — 31:16 — — — 15:0 — — — 31:16 — — — — 0000 — — — — — — — — — BUFS — — — — — FORM[2:0] — BUFREGEN CSCNA — — — — SSRC[3:0] — — — — — — — MODE12 ASAM SAMP DONE 0000 — — — — 0000 — — — — — — — — — — — — — — — — — BUFM — 0000 — — 0000 — — — 0000 — — — 0000 — CHONA[2:0] — CHOSA[4:0] 0000 CSS[19:16] 0000 CSS[15:0](1) 0000 31:16 — — — — — — — — — — — — 15:0 ASEN LPEN — BGREQ — — ASINT[1:0] — — — — 31:16 — — — — — — — — — — — — 0000 — ADCS[7:0] — CSS[30:27] — SMPI[3:0] SAMC[4:0] 15:0 15:0 19/3 All Resets Bit Range Register Name(2) Virtual Address (BF80_#) Bits 21F0 ADC1BUF15 2260 ADC REGISTER MAP (CONTINUED) — — — WM[1:0] — CM[1:0] CHH[19:16] CHH[15:0] Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: The CSS[19:12] bits are not implemented in 28-pin devices. The CSS[19:15] bits are not implemented in 36-pin and 40-pin devices. The CSS[17:14] bits are not implemented in 48-pin devices. 2: All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. 0000 0000 0000 0000 PIC32MM0256GPM064 FAMILY DS60001387D-page 218 TABLE 20-1: PIC32MM0256GPM064 FAMILY REGISTER 20-1: Bit Range 31:24 23:16 15:8 7:0 AD1CON1: ADC CONTROL REGISTER 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 ON — SIDL — — R/W-0 R/W-0 R/W-0 R/W-0 SSRC[3:0] FORM[2:0] R/W-0 R/W-0 MODE12 ASAM R/W-0, HSC (2) SAMP Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0, HSC (1) DONE x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: ADC Operating Mode bit 1 = ADC module is operating 0 = ADC is off bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: ADC Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-11 Unimplemented: Read as ‘0’ bit 10-8 FORM[2:0]: Data Output Format bits For 12-Bit Operation (MODE12 bit = 1): 111 = Signed fractional 32-bit (DOUT = sddd dddd dddd 0000 0000 0000 0000) 110 = Fractional 32-bit (DOUT = dddd dddd dddd 0000 0000 0000 0000 0000) 101 = Signed integer 32-bit (DOUT = ssss ssss ssss ssss ssss sddd dddd dddd) 100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 dddd dddd dddd) 011 = Signed fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dddd 0000) 010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dddd 0000) 001 = Signed integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sddd dddd dddd) 000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 dddd dddd dddd) For 10-Bit Operation (MODE12 bit = 0): 111 = Signed fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000) 110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000) 101 = Signed integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd) 100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) 011 = Signed fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000) 010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000) 001 = Signed integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd) 000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) Note 1: The DONE bit is not persistent in Automatic modes; it is cleared by hardware at the beginning of the  next sample. The SAMP bit is cleared and cannot be written if the ADC is disabled (ON bit = 0). 2:  2016-2019 Microchip Technology Inc. DS60001387D-page 219 PIC32MM0256GPM064 FAMILY REGISTER 20-1: AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED) bit 7-4 SSRC[3:0]: Conversion Trigger Source Select bits 1111 = CLC2 module event ends sampling and starts conversion 1110 = CLC1 module event ends sampling and starts conversion 1101 = SCCP6 module event ends sampling and starts conversion 1100 = SCCP5 module event ends sampling and starts conversion 1011 = SCCP4 module event ends sampling and starts conversion 1010 = MCCP3 module event ends sampling and starts conversion 1001 = MCCP2 module event ends sampling and starts conversion 1000 = MCCP1 module event ends sampling and starts conversion 0111 = Internal counter ends sampling and starts conversion (auto-convert) 0110 = Timer1 period match ends sampling and starts conversion (can trigger during Sleep mode) 0101 = Timer1 period match ends sampling and starts conversion (will not trigger during Sleep mode) 0100-0011 = Reserved 0010 = Timer3 period match ends sampling and starts conversion 0001 = Active transition on INT0 pin ends sampling and starts conversion 0000 = Clearing the SAMP bit ends sampling and starts conversion bit 3 MODE12: 12-Bit Operation Mode bit 1 = 12-bit ADC operation 0 = 10-bit ADC operation bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set 0 = Sampling begins when SAMP bit is set bit 1 SAMP: ADC Sample Enable bit(2) 1 = The ADC Sample-and-Hold Amplifier (SHA) is sampling 0 = The ADC SHA is holding When ASAM = 0, writing ‘1’ to this bit starts sampling. When SSRC[3:0 = 0000, writing ‘0’ to this bit will end sampling and start conversion. bit 0 DONE: ADC Conversion Status bit(1) 1 = Analog-to-Digital conversion is done 0 = Analog-to-Digital conversion is not done or has not started Clearing this bit will not affect any operation in progress. Note 1: The DONE bit is not persistent in Automatic modes; it is cleared by hardware at the beginning of the  next sample. The SAMP bit is cleared and cannot be written if the ADC is disabled (ON bit = 0). 2: DS60001387D-page 220  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 20-2: Bit Range 31:24 23:16 15:8 7:0 AD1CON2: ADC CONTROL REGISTER 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 VCFG[2:0] R/W-0 U-0 BUFS — R/W-0 R/W-0 R/W-0 U-0 OFFCAL BUFREGEN CSCNA — — R/W-0 R/W-0 R/W-0 R/W-0 U-0 BUFM — R/W-0 SMPI[3:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-13 VCFG[2:0]: Voltage Reference Configuration bits ADC VR+ ADC VR- 000 001 AVDD AVDD AVSS External VREF- Pin 010 011 External VREF+ Pin External VREF+ Pin AVSS External VREF- Pin 1xx Unimplemented; do not use bit 12 OFFCAL: Input Offset Calibration Mode Select bit 1 = Enables Offset Calibration mode: The inputs of the SHA are connected to the negative reference 0 = Disables Offset Calibration mode: The inputs to the SHA are controlled by AD1CHS or AD1CSS bit 11 BUFREGEN: ADC Buffer Register Enable bit 1 = Conversion result is loaded into the buffer location determined by the converted channel 0 = ADC result buffer is treated as a FIFO bit 10 CSCNA: Scan Input Selections for CH0+ SHA Input for Input Multiplexer Setting bit 1 = Scans inputs 0 = Does not scan inputs Unimplemented: Read as ‘0’ bit 9-8 bit 7 BUFS: Buffer Fill Status bit Only valid when BUFM = 1 (ADC buffers split into 2 x 11-word buffers). 1 = ADC is currently filling Buffers 11-21, user should access data in 0-10 0 = ADC is currently filling Buffers 0-10, user should access data in 11-21 bit 6 bit 5-2 Unimplemented: Read as ‘0’ SMPI[3:0]: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence • • • 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence bit 1 BUFM: ADC Result Buffer Mode Select bit 1 = Buffer configured as two 11-word buffers, ADC1BUF(0...10), ADC1BUF(11...21) 0 = Buffer configured as one 22-word buffer, ADC1BUF(0...21) bit 0 Unimplemented: Read as ‘0’  2016-2019 Microchip Technology Inc. DS60001387D-page 221 PIC32MM0256GPM064 FAMILY REGISTER 20-3: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 AD1CON3: ADC CONTROL REGISTER 3 Bit Bit 30/22/14/6 29/21/13/5 U-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC EXTSAM — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SAMC[4:0] R/W-0 ADCS[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ADRC: ADC Conversion Clock Source (TSRC) bit 1 = Clock derived from the Fast RC (FRC) oscillator 0 = Clock derived from the Peripheral Bus Clock (PBCLK, 1:1 with SYSCLK) bit 14 EXTSAM: Extended Sampling Time bit 1 = ADC is still sampling after SAMP bit = 0 0 = ADC stops sampling when SAMP bit = 0 bit 13 Unimplemented: Read as ‘0’ bit 12-8 SAMC[4:0]: Auto-Sample Time bits 11111 = 31 TAD • • • 00001 = 1 TAD 00000 = 0 TAD (Not allowed) bit 7-0 ADCS[7:0]: ADC Conversion Clock Select bits 11111111 = 2 • TSRC • ADCS[7:0] = 510 • TSRC = TAD • • • 00000001 = 2 • TSRC • ADCS[7:0] = 2 • TSRC = TAD 00000000 = 1 • TSRC = TAD Where TSRC is a period of clock selected by the ADRC bit (AD1CON3[15]). DS60001387D-page 222  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 20-4: Bit Range 31:24 23:16 15:8 7:0 AD1CON5: ADC CONTROL REGISTER 5 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 ASEN LPEN — BGREQ — — R/W-0 (1) U-0 U-0 U-0 U-0 R/W-0 — — — — R/W-0 ASINT[1:0] R/W-0 WM[1:0] R/W-0 CM[1:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ASEN: Auto-Scan Enable bit 1 = Auto-scan is enabled 0 = Auto-scan is disabled bit 14 LPEN: Low-Power Enable bit 1 = Low power is enabled after scan 0 = Full power is enabled after scan bit 13 Unimplemented: Read as ‘0’ bit 12 BGREQ: Band Gap Request bit 1 = Band gap is enabled when the ADC is enabled and active 0 = Band gap is not enabled by the ADC bit 11-10 Unimplemented: Read as ‘0’ bit 9-8 ASINT[1:0]: Auto-Scan (Threshold Detect) Interrupt Mode bits(1) 11 = Interrupt after Threshold Detect sequence has completed and a valid compare has occurred 10 = Interrupt after valid compare has occurred 01 = Interrupt after Threshold Detect sequence has completed 00 = No interrupt bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 WM[1:0]: Write Mode bits 11 = Reserved 10 = Auto-compare only (conversion results are not saved, but interrupts are generated when a valid match occurs, as defined by the CM[1:0] and ASINT[1:0] bits) 01 = Convert and save (conversion results saved to locations as determined by register bits when a match occurs, as defined by the CM[1:0] bits) 00 = Legacy operation (conversion data saved to location determined by buffer register bits) bit 1-0 CM[1:0]: Compare Mode bits 11 = Outside Window mode (valid match occurs if the conversion result is outside of the window defined by the corresponding buffer pair) 10 = Inside Window mode (valid match occurs if the conversion result is inside the window defined by the corresponding buffer pair) 01 = Greater Than mode (valid match occurs if the result is greater than value in the corresponding buffer register) 00 = Less Than mode (valid match occurs if the result is less than value in the corresponding buffer register) Note 1: The ASINT[1:0] bits setting only takes effect when ASEN (AD1CON5[15]) = 1. Interrupt generation is governed by the SMPI[3:0] bits field.  2016-2019 Microchip Technology Inc. DS60001387D-page 223 PIC32MM0256GPM064 FAMILY REGISTER 20-5: Bit Range 31:24 23:16 15:8 7:0 AD1CHS: ADC INPUT SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA[2:0] CH0SA[4:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-8 Unimplemented: Read as ‘0’ bit 7-5 CH0NA[2:0]: Negative Input Select bits 111-001 = Reserved 000 = Negative input is AVSS bit 4-0 CH0SA[4:0]: Positive Input Select bits 11111 = Reserved 11110 = Positive input is AVDD 11101 = Positive input is AVSS 11100 = Positive input is Band Gap Reference (VBG) 11011 = VDD core 10100-10110 = Reserved 10011 = Positive input is AN19(2) 10010 = Positive input is AN18(1) 10001 = Positive input is AN17(1) 10000 = Positive input is AN16(1) 01111 = Positive input is AN15(2) 01110 = Positive input is AN14(3) 01101 = Positive input is AN13(3) 01100 = Positive input is AN12(3) 01011 = Positive input is AN11 01010 = Positive input is AN10 01001 = Positive input is AN9 01000 = Positive input is AN8 00111 = Positive input is AN7 00110 = Positive input is AN6 00101 = Positive input is AN5 00100 = Positive input is AN4 00011 = Positive input is AN3 00010 = Positive input is AN2 00001 = Positive input is AN1 00000 = Positive input is AN0 Note 1: 2: 3: x = Bit is unknown This option is not available in 28, 36, 40 or 48-pin packages. This option is not available in 28, 36 or 40-pin packages. This option is not available in 28-pin packages. DS60001387D-page 224  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY ) REGISTER 20-6: Bit Range 31:24 23:16 15:8 7:0 AD1CSS: ADC INPUT SCAN SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — U-0 CSS[30:27] — U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 — — R/W-0 (1,2,3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS[19:16] CSS[15:8] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31 x = Bit is unknown Unimplemented: Read as ‘0’ bit 30-27 CSS[30:27]: ADC Input Pin Scan Selection bits 1 = Selects ANx for the input scan 0 = Skips ANx for the input scan bit 26-20 Unimplemented: Read as ‘0’ bit 19-0 CSS[19:0]: ADC Input Pin Scan Selection bits(1,2,3) 1 = Selects ANx for the input scan 0 = Skips ANx for the input scan Note 1: 2: 3: The CSS[19:12] bits are not implemented in 28-pin devices The CSS[19:15] bits are not implemented in 36-pin and 40-pin devices The CSS[17:14] bits are not implemented in 48-pin devices  2016-2019 Microchip Technology Inc. DS60001387D-page 225 PIC32MM0256GPM064 FAMILY REGISTER 20-7: Bit Range 31:24 23:16 15:8 7:0 AD1CHIT: ADC COMPARE HIT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit 29/21/13/5 28/20/12/4 U-0 U-0 U-0 — — — U-0 U-0 U-0 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 — — — — U-0 R/W-0 R/W-0 R/W-0 (1,2,3) R/W-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHH[19:16] CHH[15:8] — R/W-0 (1,2,3) CHH[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-20 Unimplemented: Read as ‘0’ bit 19-0 CHH[19:0]: ADC Compare Hit bits(1,2,3) If CM[1:0] = 11: 1 = ADC Result Buffer n has been written with data or a match has occurred 0 = ADC Result Buffer n has not been written with data For All Other Values of CM[1:0]: 1 = A match has occurred on ADC Result Channel n 0 = No match has occurred on ADC Result Channel n Note 1: 2: 3: The CHH[19:12] bits are not implemented in 28-pin devices The CHH[19:15] bits are not implemented in 36-pin and 40-pin devices The CHH[17:14] bits are not implemented in 48-pin devices DS60001387D-page 226  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 21.0 CONFIGURABLE LOGIC CELL (CLC) Note: This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 36. “Configurable Logic Cell” (www.microchip.com/DS60001363) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. CLCIN[0] CLCIN[1] CLCIN[2] CLCIN[3] CLCIN[4] CLCIN[5] CLCIN[6] CLCIN[7] CLCIN[8] CLCIN[9] CLCIN[10] CLCIN[11] CLCIN[12] CLCIN[13] CLCIN[14] CLCIN[15] CLCIN[16] CLCIN[17] CLCIN[18] CLCIN[19] CLCIN[20] CLCIN[21] CLCIN[22] CLCIN[23] CLCIN[24] CLCIN[25] CLCIN[26] CLCIN[27] CLCIN[28] CLCIN[29] CLCIN[30] CLCIN[31] There are four input gates to the selected logic function. These four input gates select from a pool of up to 32 signals that are selected using four data source selection multiplexers. Figure 21-1 shows an overview of the module. Figure 21-3 shows the details of the data source multiplexers and logic input gate connections. CLCx MODULE Input Data Selection Gates FIGURE 21-1: The Configurable Logic Cell (CLC) module allows the user to specify combinations of signals as inputs to a logic function and to use the logic output to control other peripherals or I/O pins. This provides greater flexibility and potential in embedded designs since the CLC module can operate outside the limitations of software execution, and supports a vast amount of output designs. See Figure 21-2 LCOE ON Gate 1 Gate 2 CLCx Output Logic Gate 3 Function Logic Output Gate 4 LCPOL MODE[2:0] TRISx Control CLCx Interrupt det INTP INTN Sets CLCxIF Flag Interrupt det See Figure 21-3 Note: All register bits shown in this figure can be found in the CLCxCON register.  2016-2019 Microchip Technology Inc. DS60001387D-page 227 PIC32MM0256GPM064 FAMILY FIGURE 21-2: CLCx LOGIC FUNCTION COMBINATORIAL OPTIONS AND – OR OR – XOR Gate 1 Gate 1 Gate 2 Logic Output Gate 3 Gate 2 Logic Output Gate 3 Gate 4 Gate 4 MODE[2:0] = 000 MODE[2:0] = 001 4-Input AND S-R Latch Gate 1 Gate 1 Gate 2 Gate 2 Logic Output Gate 3 Gate 4 S Gate 3 Q R Gate 4 MODE[2:0] = 010 MODE[2:0] = 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R Gate 4 Gate 2 D S Gate 4 Q Logic Output Logic Output D Gate 2 Q Logic Output Gate 1 Gate 1 R R Gate 3 Gate 3 MODE[2:0] = 100 MODE[2:0] = 101 J-K Flip-Flop with R 1-Input Transparent Latch with S and R Gate 4 Gate 2 J Q Logic Output Gate 1 K Gate 4 R Gate 2 D Gate 1 LE Gate 3 S Q Logic Output R Gate 3 MODE[2:0] = 110 DS60001387D-page 228 MODE[2:0] = 111  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY FIGURE 21-3: CLCx INPUT SOURCE SELECTION DIAGRAM Data Selection CLCIN[0] CLCIN[1] CLCIN[2] CLCIN[3] CLCIN[4] CLCIN[5] CLCIN[6] CLCIN[7] 000 Data Gate 1 Data 1 Non-Inverted G1D1T Data 1 Inverted G1D1N 111 DS1x (CLCxSEL[2:0]) G1D2T G1D2N CLCIN[8] CLCIN[9] CLCIN[10] CLCIN[11] CLCIN[12] CLCIN[13] CLCIN[14] CLCIN[15] G1D3T Data 2 Non-Inverted Data 2 Inverted G1D4T 000 G1D4N Data Gate 2 Data 3 Non-Inverted Data 3 Inverted Gate 2 (Same as Data Gate 1) Data Gate 3 111 Gate 3 DS3x (CLCxSEL[10:8]) CLCIN[24] CLCIN[25] CLCIN[26] CLCIN[27] CLCIN[28] CLCIN[29] CLCIN[30] CLCIN[31] G1D3N G1POL (CLCxCON[0]) 111 DS2x (CLCxSEL[6:4]) CLCIN[16] CLCIN[17] CLCIN[18] CLCIN[19] CLCIN[20] CLCIN[21] CLCIN[22] CLCIN[23] Gate 1 000 (Same as Data Gate 1) Data Gate 4 000 Gate 4 Data 4 Non-Inverted (Same as Data Gate 1) Data 4 Inverted 111 DS4x (CLCxSEL[14:12])  2016-2019 Microchip Technology Inc. DS60001387D-page 229 PIC32MM0256GPM064 FAMILY 21.1 Control Registers The CLCx module is controlled by the following registers: • CLCxCON • CLCxSEL • CLCxGLS The CLCx Control register (CLCxCON) is used to enable the module and interrupts, control the output enable bit, select output polarity and select the logic function. The CLCx Control registers also allow the user to control the logic polarity of not only the cell output, but also some intermediate variables. DS60001387D-page 230 The CLCx Source Select register (CLCxSEL) allows the user to select up to four data input sources using the four data input selection multiplexers. Each multiplexer has a list of eight data sources available. The CLCx Gate Logic Select register (CLCxGLS) allows the user to select which outputs from each of the selection MUXes are used as inputs to the input gates of the logic cell. Each data source MUX outputs both a true and a negated version of its output. All of these eight signals are enabled, ORed together by the logic cell input gates. If no gate inputs are selected, the input to the gate will be zero or one, depending on the GxPOL bits.  2016-2019 Microchip Technology Inc. Virtual Address (BF80_#) Register Name(1) 2480 CLC1CON CLC1SEL 24A0 CLC1GLS CLC2CON CLC2SEL 2520 CLC2GLS 2580 CLC3CON 2590 CLC3SEL 25A0 CLC3GLS 2600 CLC4CON 2610 CLC4SEL 2620 CLC4GLS 31/15 30/14 28/12 32:16 — 15:0 ON — — — — SIDL — 32:16 — — — — — 15:0 — 32:16 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0000 15:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0000 32:16 — — — — — — — — — — — — G4POL G3POL G2POL G1POL 0000 15:0 ON — SIDL — INTP INTN — — LCOE LCOUT LCPOL — — 32:16 — — — — — — — — — — — — — 15:0 — 32:16 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0000 15:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0000 32:16 — — — — — — — — — — — — G4POL G3POL G2POL G1POL 0000 15:0 ON — SIDL — INTP INTN — — LCOE LCOUT LCPOL — — 32:16 — — — — — — — — — — — — — 15:0 — 32:16 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0000 15:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0000 32:16 — — — — — — — — — — — — G4POL G3POL G2POL G1POL 0000 15:0 ON — SIDL — INTP INTN — — LCOE LCOUT LCPOL — — 32:16 — — — — — — — — — — — — — 15:0 — 32:16 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0000 15:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0000 DS4[2:0] 27/11 26/10 25/9 24/8 — — — — — INTP INTN — — LCOE — — — — — — DS4[2:0] DS3[2:0] — DS4[2:0] DS4[2:0] 21/5 20/4 19/3 18/2 — — — G4POL G3POL LCOUT LCPOL — — — — — DS2[2:0] — DS3[2:0] — 22/6 — DS3[2:0] — 23/7 — DS3[2:0] — DS2[2:0] G1POL — — — 0000 — 0000 — DS1[2:0] — 0000 0000 MODE[2:0] — 0000 0000 MODE[2:0] — 0000 0000 DS1[2:0] — 0000 0000 — MODE[2:0] — DS60001387D-page 231 All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. G2POL DS1[2:0] — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: — — DS2[2:0] 16/0 MODE[2:0] — DS2[2:0] 17/1 0000 — DS1[2:0] 0000 0000 PIC32MM0256GPM064 FAMILY 2510 29/13 All Resets Bits 2490 2500 CLC1, CLC2 AND CLC3 REGISTER MAP Bit Range  2016-2019 Microchip Technology Inc. TABLE 21-1: PIC32MM0256GPM064 FAMILY REGISTER 21-1: Bit Range 31:24 CLCxCON: CLCx CONTROL REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — 23:16 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — G4POL G3POL G2POL G1POL 15:8 R/W-0 U-0 R/W-0 U-0 U-0 — SIDL — INTP R/W-0 (1) U-0 ON R/W-0 (1) R/W-0 R-0, HS, HC R/W-0 U-0 U-0 LCOE LCOUT LCPOL — — 7:0 INTN R/W-0 — — R/W-0 R/W-0 MODE Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-20 Unimplemented: Read as ‘0’ bit 19 G4POL: Gate 4 Polarity Control bit 1 = The output of Channel 4 logic is inverted when applied to the logic cell 0 = The output of Channel 4 logic is not inverted bit 18 G3POL: Gate 3 Polarity Control bit 1 = The output of Channel 3 logic is inverted when applied to the logic cell 0 = The output of Channel 3 logic is not inverted bit 17 G2POL: Gate 2 Polarity Control bit 1 = The output of Channel 2 logic is inverted when applied to the logic cell 0 = The output of Channel 2 logic is not inverted bit 16 G1POL: Gate 1 Polarity Control bit 1 = The output of Channel 1 logic is inverted when applied to the logic cell 0 = The output of Channel 1 logic is not inverted bit 15 ON: CLCx Enable bit 1 = CLCx is enabled and mixing input signals 0 = CLCx is disabled and has logic zero outputs bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: CLCx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 Unimplemented: Read as ‘0’ bit 11 INTP: CLCx Positive Edge Interrupt Enable bit(1) 1 = Interrupt will be generated when a rising edge occurs on LCOUT 0 = Interrupt will not be generated bit 10 INTN: CLCx Negative Edge Interrupt Enable bit(1) 1 = Interrupt will be generated when a falling edge occurs on LCOUT 0 = Interrupt will not be generated bit 9-8 Unimplemented: Read as ‘0’ bit 7 LCOE: CLCx Port Enable bit 1 = CLCx port pin output is enabled 0 = CLCx port pin output is disabled Note 1: The INTP and INTN bits should not be set at the same time for proper interrupt functionality. DS60001387D-page 232  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 21-1: CLCxCON: CLCx CONTROL REGISTER (CONTINUED) bit 6 LCOUT: CLCx Data Output Status bit 1 = CLCx output high 0 = CLCx output low bit 5 LCPOL: CLCx Output Polarity Control bit 1 = The output of the module is inverted 0 = The output of the module is not inverted bit 4-3 Unimplemented: Read as ‘0’ bit 2-0 MODE: CLCx Mode bits 111 = Cell is a 1-input transparent latch with S and R 110 = Cell is a JK flip-flop with R 101 = Cell is a 2-input D flip-flop with R 100 = Cell is a 1-input D flip-flop with S and R 011 = Cell is an SR latch 010 = Cell is a 4-input AND 001 = Cell is an OR-XOR 000 = Cell is a AND-OR Note 1: The INTP and INTN bits should not be set at the same time for proper interrupt functionality.  2016-2019 Microchip Technology Inc. DS60001387D-page 233 PIC32MM0256GPM064 FAMILY REGISTER 21-2: Bit Range 31:24 23:16 15:8 7:0 CLCxSEL: CLCx INPUT MUX SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — U-0 — DS4[2:0] R/W-0 R/W-0 — DS2[2:0] DS3[2:0] R/W-0 — R/W-0 R/W-0 DS1[2:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-15 Unimplemented: Read as ‘0’ bit 14-12 DS4[2:0]: Data Selection MUX 4 Signal Selection bits For CLC1: 111 = SCCP5 OCMP compare match event 110 = MCCP1 OCMP compare match event 101 = RTCC event 100 = CMP3 out 011 = SPI1 SDI1 in 010 = SCCP5 OCM5 output 001 = CLC2 out 000 = CLCINB I/O pin For CLC2: 111 = SCCP5 OCMP compare match event 110 = MCCP1 OCMP compare match event 101 = RTCC event 100 = CMP3 out 011 = SPI2 SDI2 in 010 = SCCP5 OCM5 output 001 = CLC1 out 000 = CLCINB I/O pin For CLC3: 111 = SCCP7 OCMP compare match event 110 = MCCP2 OCMP compare match event 101 = RTCC event 100 = CMP3 out 011 = SPI3 SDI3 in 010 = SCCP7 OCM7A output 001 = CLC4 out 000 = CLCINB I/O pin For CLC4: 111 = SCCP7 OCMP compare match event 110 = MCCP3 OCMP compare match event 101 = RTCC event 100 = CMP3 out 011 = Reserved 010 = SCCP7 OCM3 output 001 = CLC3 out 000 = CLCINB I/O pin DS60001387D-page 234  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 21-2: CLCxSEL: CLCx INPUT MUX SELECT REGISTER (CONTINUED) bit 11 Unimplemented: Read as ‘0’ bit 10-8 DS3[2:0]: Data Selection MUX 3 Signal Selection bits For CLC1: 111 = SCCP5 OCMP compare match event 110 = SCCP4 OCMP compare match event 101 = SCCP4 OCM4 output 100 = UART1 RX in 011 = SPI1 SDO1 out 010 = CMP2 out 001 = CLC1 out 000 = CLCINA I/O pin For CLC2: 111 = SCCP5 OCMP compare match event 110 = SCCP4 OCMP compare match event 101 = SCCP4 OCM4 output 100 = UART2 RX in 011 = SPI2 SDO2 out 010 = CMP2 out 001 = CLC2 out 000 = CLCINA I/O pin For CLC3: 111 = SCCP7 OCMP compare match event 110 = SCCP6 OCMP compare match event 101 = SCCP6 OCM6 output 100 = UART3 RX in 011 = SPI3 SDO3 out 010 = CMP2 out 001 = CLC3 out 000 = CLCINA I/O pin For CLC4: 111 = SCCP7 OCMP compare match event 110 = SCCP6 OCMP compare match event 101 = SCCP6 OCM2 output 100 = Reserved 011 = Reserved 010 = CMP2 out 001 = CLC4 out 000 = CLCINA I/O pin bit 7 Unimplemented: Read as ‘0’  2016-2019 Microchip Technology Inc. DS60001387D-page 235 PIC32MM0256GPM064 FAMILY REGISTER 21-2: CLCxSEL: CLCx INPUT MUX SELECT REGISTER (CONTINUED) bit 6-4 DS2[2:0]: Data Selection MUX 2 Signal Selection bits For CLC1: 111 = Unused 110 = MCCP1 OCMP compare match event 101 = DMA Channel 0 interrupt 100 = ADC end of conversion 011 = UART1 TX out 010 = CMP1 out 001 = CLC2 out 000 = CLCINB I/O pin For CLC2: 111 = Unused 110 = MCCP1 OCMP compare match event 101 = DMA Channel 1 interrupt 100 = ADC end of conversion 011 = UART2 TX out 010 = CMP1 out 001 = CLC1 out 000 = CLCINB I/O pin For CLC3: 111 = Reserved 110 = MCCP2 OCMP compare match event 101 = DMA Channel 0 interrupt 100 = ADC end of conversion 011 = UART3 TX out 010 = CMP1 out 001 = CLC4 out 000 = CLCINB I/O pin For CLC4: 111 = Reserved 110 = MCCP3 OCMP compare match event 101 = DMA Channel 1 interrupt 100 = ADC end of conversion 011 = Reserved 010 = CMP1 out 001 = CLC3 out 000 = CLCINB I/O pin bit 3 Unimplemented: Read as ‘0’ DS60001387D-page 236  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 21-2: bit 2-0 CLCxSEL: CLCx INPUT MUX SELECT REGISTER (CONTINUED) DS1[2:0]: Data Selection MUX 1 Signal Selection bits For CLC1: 111 = MCCP1 OCM1C output 110 = MCCP1 OCM1B output 101 = MCCP1 OCM1A output 100 = REFO1 output 011 = LPRC clock 010 = SOSC clock 001 = System clock 000 = CLCINA I/O pin For CLC2: 111 = MCCP1 OCM1F output 110 = MCCP1 OCM1E output 101 = MCCP1 OCM1D output 100 = REFO1 output 011 = LPRC clock 010 = SOSC clock 001 = System clock 000 = CLCINA I/O pin For CLC3: 111 = MCCP2 OCM1C output 110 = MCCP2 OCM1B output 101 = MCCP2 OCM1A output 100 = REFO1 output 011 = LPRC clock 010 = SOSC clock 001 = System clock 000 = CLCINA I/O pin For CLC4: 111 = MCCP3 OCM1F output 110 = MCCP3 OCM1E output 101 = MCCP3 OCM1D output 100 = REFO1 output 011 = LPRC clock 010 = SOSC clock 001 = System clock 000 = CLCINA I/O pin  2016-2019 Microchip Technology Inc. DS60001387D-page 237 PIC32MM0256GPM064 FAMILY REGISTER 21-3: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 CLCxGLS: CLCx GATE LOGIC INPUT SELECT REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31 G4D4T: Gate 4 Data Source 4 True Enable bit 1 = The Data Source 4 signal is enabled for Gate 4 0 = The Data Source 4 signal is disabled for Gate 4 bit 30 G4D4N: Gate 4 Data Source 4 Negated Enable bit 1 = The Data Source 4 inverted signal is enabled for Gate 4 0 = The Data Source 4 inverted signal is disabled for Gate 4 bit 29 G4D3T: Gate 4 Data Source 3 True Enable bit 1 = The Data Source 3 signal is enabled for Gate 4 0 = The Data Source 3 signal is disabled for Gate 4 bit 28 G4D3N: Gate 4 Data Source 3 Negated Enable bit 1 = The Data Source 3 inverted signal is enabled for Gate 4 0 = The Data Source 3 inverted signal is disabled for Gate 4 bit 27 G4D2T: Gate 4 Data Source 2 True Enable bit 1 = The Data Source 2 signal is enabled for Gate 4 0 = The Data Source 2 signal is disabled for Gate 4 bit 26 G4D2N: Gate 4 Data Source 2 Negated Enable bit 1 = The Data Source 2 inverted signal is enabled for Gate 4 0 = The Data Source 2 inverted signal is disabled for Gate 4 bit 25 G4D1T: Gate 4 Data Source 1 True Enable bit 1 = The Data Source 1 signal is enabled for Gate 4 0 = The Data Source 1 signal is disabled for Gate 4 bit 24 G4D1N: Gate 4 Data Source 1 Negated Enable bit 1 = The Data Source 1 inverted signal is enabled for Gate 4 0 = The Data Source 1 inverted signal is disabled for Gate 4 bit 23 G3D4T: Gate 3 Data Source 4 True Enable bit 1 = The Data Source 4 signal is enabled for Gate 3 0 = The Data Source 4 signal is disabled for Gate 3 bit 22 G3D4N: Gate 3 Data Source 4 Negated Enable bit 1 = The Data Source 4 inverted signal is enabled for Gate 3 0 = The Data Source 4 inverted signal is disabled for Gate 3 bit 21 G3D3T: Gate 3 Data Source 3 True Enable bit 1 = The Data Source 3 signal is enabled for Gate 3 0 = The Data Source 3 signal is disabled for Gate 3 DS60001387D-page 238 x = Bit is unknown  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 21-3: CLCxGLS: CLCx GATE LOGIC INPUT SELECT REGISTER (CONTINUED) bit 20 G3D3N: Gate 3 Data Source 3 Negated Enable bit 1 = The Data Source 3 inverted signal is enabled for Gate 3 0 = The Data Source 3 inverted signal is disabled for Gate 3 bit 19 G3D2T: Gate 3 Data Source 2 True Enable bit 1 = The Data Source 2 signal is enabled for Gate 3 0 = The Data Source 2 signal is disabled for Gate 3 bit 18 G3D2N: Gate 3 Data Source 2 Negated Enable bit 1 = The Data Source 2 inverted signal is enabled for Gate 3 0 = The Data Source 2 inverted signal is disabled for Gate 3 bit 17 G3D1T: Gate 3 Data Source 1 True Enable bit 1 = The Data Source 1 signal is enabled for Gate 3 0 = The Data Source 1 signal is disabled for Gate 3 bit 16 G3D1N: Gate 3 Data Source 1 Negated Enable bit 1 = The Data Source 1 inverted signal is enabled for Gate 3 0 = The Data Source 1 inverted signal is disabled for Gate 3 bit 15 G2D4T: Gate 2 Data Source 4 True Enable bit 1 = The Data Source 4 signal is enabled for Gate 2 0 = The Data Source 4 signal is disabled for Gate 2 bit 14 G2D4N: Gate 2 Data Source 4 Negated Enable bit 1 = The Data Source 4 inverted signal is enabled for Gate 2 0 = The Data Source 4 inverted signal is disabled for Gate 2 bit 13 G2D3T: Gate 2 Data Source 3 True Enable bit 1 = The Data Source 3 signal is enabled for Gate 2 0 = The Data Source 3 signal is disabled for Gate 2 bit 12 G2D3N: Gate 2 Data Source 3 Negated Enable bit 1 = The Data Source 3 inverted signal is enabled for Gate 2 0 = The Data Source 3 inverted signal is disabled for Gate 2 bit 11 G2D2T: Gate 2 Data Source 2 True Enable bit 1 = The Data Source 2 signal is enabled for Gate 2 0 = The Data Source 2 signal is disabled for Gate 2 bit 10 G2D2N: Gate 2 Data Source 2 Negated Enable bit 1 = The Data Source 2 inverted signal is enabled for Gate 2 0 = The Data Source 2 inverted signal is disabled for Gate 2 bit 9 G2D1T: Gate 2 Data Source 1 True Enable bit 1 = The Data Source 1 signal is enabled for Gate 2 0 = The Data Source 1 signal is disabled for Gate 2 bit 8 G2D1N: Gate 2 Data Source 1 Negated Enable bit 1 = The Data Source 1 inverted signal is enabled for Gate 2 0 = The Data Source 1 inverted signal is disabled for Gate 2 bit 7 G1D4T: Gate 1 Data Source 4 True Enable bit 1 = The Data Source 4 signal is enabled for Gate 1 0 = The Data Source 4 signal is disabled for Gate 1 bit 6 G1D4N: Gate 1 Data Source 4 Negated Enable bit 1 = The Data Source 4 inverted signal is enabled for Gate 1 0 = The Data Source 4 inverted signal is disabled for Gate 1 bit 5 G1D3T: Gate 1 Data Source 3 True Enable bit 1 = The Data Source 3 signal is enabled for Gate 1 0 = The Data Source 3 signal is disabled for Gate 1  2016-2019 Microchip Technology Inc. DS60001387D-page 239 PIC32MM0256GPM064 FAMILY REGISTER 21-3: CLCxGLS: CLCx GATE LOGIC INPUT SELECT REGISTER (CONTINUED) bit 4 G1D3N: Gate 1 Data Source 3 Negated Enable bit 1 = The Data Source 3 inverted signal is enabled for Gate 1 0 = The Data Source 3 inverted signal is disabled for Gate 1 bit 3 G1D2T: Gate 1 Data Source 2 True Enable bit 1 = The Data Source 2 signal is enabled for Gate 1 0 = The Data Source 2 signal is disabled for Gate 1 bit 2 G1D2N: Gate 1 Data Source 2 Negated Enable bit 1 = The Data Source 2 inverted signal is enabled for Gate 1 0 = The Data Source 2 inverted signal is disabled for Gate 1 bit 1 G1D1T: Gate 1 Data Source 1 True Enable bit 1 = The Data Source 1 signal is enabled for Gate 1 0 = The Data Source 1 signal is disabled for Gate 1 bit 0 G1D1N: Gate 1 Data Source 1 Negated Enable bit 1 = The Data Source 1 inverted signal is enabled for Gate 1 0 = The Data Source 1 inverted signal is disabled for Gate 1 DS60001387D-page 240  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 22.0 Note: COMPARATOR This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Comparator” (www.microchip.com/DS60001110) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. FIGURE 22-1: The comparator module provides three dual input comparators. The inputs to the comparator can be configured to use any one of five external analog inputs (CxINA, CxINB, CxINC, CxIND and CVREF+). The comparator outputs may be directly connected to the CxOUT pins. When the respective COE bit equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. A simplified block diagram of the module in shown in Figure 22-1. Each comparator has its own control register, CMxCON (Register 22-2), for enabling and configuring its operation. The output and event status of two comparators is provided in the CMSTAT register (Register 22-1). THREE DUAL COMPARATOR MODULES BLOCK DIAGRAM EVPOL[1:0] CCH[1:0] Input Select Logic CPOL Trigger/Interrupt Logic CEVT COE VIN- CxINB 00 CxINC 01 CxIND 10 Band Gap 11 VIN+ C1 COUT – C1OUT Pin EVPOL[1:0] CPOL Trigger/Interrupt Logic CEVT COE VINVIN+ C2 COUT C2OUT Pin 0 CxINA + Comparator Voltage Reference 0 CVREF+ 1 CVREFSEL EVPOL[1:0] 1 CPOL Trigger/Interrupt Logic CEVT COE VINVIN+ C3 COUT C3OUT Pin CREF  2016-2019 Microchip Technology Inc. DS60001387D-page 243 Comparator Control Registers Virtual Address (BF80_#) Register Name(1) TABLE 22-1: 2300 CMSTAT 2310 CM1CON 2330 2350 COMPARATORS 1, 2 AND 3 REGISTER MAP CM2CON CM3CON 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 — 15:0 — — — — — — — SIDL — — — 24/8 23/7 22/6 21/5 20/4 19/3 — — — — — — — C3EVT C2EVT C1EVT 0000 — CVREFSEL — — — — — C3OUT C2OUT C1OUT 0000 — — — — — — — — 0000 EVPOL[1:0] — CREF — — — — — — — EVPOL[1:0] 31:16 — — — — — — — — 15:0 ON COE CPOL — — — CEVT COUT 31:16 — — — — — — — — 15:0 ON COE CPOL — — — CEVT COUT 31:16 — — — — — — — — 15:0 ON COE CPOL — — — CEVT COUT — — CREF — — — — — — — EVPOL[1:0] — CREF — — — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: 18/2 All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. 17/1 16/0 All Resets Bit Range Bits CCH[1:0] — — CCH[1:0] — — CCH[1:0] 0000 0000 0000 0000 0000 PIC32MM0256GPM064 FAMILY DS60001387D-page 244 22.1  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 22-1: Bit Range 31:24 23:16 15:8 7:0 CMSTAT: COMPARATOR MODULE STATUS REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit Bit 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — U-0 — U-0 U-0 U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC C1EVT — — — — — C3EVT C2EVT U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — SIDL — — — — CVREFSEL U-0 U-0 U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC — — — — — C3OUT C2OUT C1OUT Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-19 Unimplemented: Read as ‘0’ bit 18 C3EVT: Comparator 3 Event Status bit (read-only) Shows the current event status of Comparator 3 (CM3CON[9]). bit 17 C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON[9]). bit 16 C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON[9]). bit 15-14 Unimplemented: Read as ‘0’ bit 13 SIDL: Comparator Stop in Idle Mode bit 1 = Discontinues operation of all comparators when device enters Idle mode 0 = Continues operation of all enabled comparators in Idle mode bit 12-9 Unimplemented: Read as ‘0’ bit 8 CVREFSEL: Comparator Reference Voltage Select Enable bit 1 = External voltage reference from the CVREF+ pin is selected 0 = Internal band gap voltage reference is selected bit 7-3 Unimplemented: Read as ‘0’ bit 2 C3OUT: Comparator 3 Output Status bit (read-only) Shows the current output of Comparator 3 (CM3CON[8]). bit 1 C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON[8]). bit 0 C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON[8]).  2016-2019 Microchip Technology Inc. DS60001387D-page 245 PIC32MM0256GPM064 FAMILY REGISTER 22-2: Bit Range 31:24 23:16 15:8 7:0 CMxCON: COMPARATOR x CONTROL REGISTERS  (COMPARATORS 1, 2 AND 3) Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC ON COE CPOL — — — CEVT COUT R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — CREF — — EVPOL[1:0] CCH[1:0] Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 14 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only bit 13 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 12-10 Unimplemented: Read as ‘0’ bit 9 CEVT: Comparator Event bit 1 = Comparator event that is defined by EVPOL[1:0] has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred bit 8 COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1: 1 = VIN+ < VIN0 = VIN+ > VIN- DS60001387D-page 246  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 22-2: CMxCON: COMPARATOR x CONTROL REGISTERS  (COMPARATORS 1, 2 AND 3) (CONTINUED) bit 7-6 EVPOL[1:0]: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt is generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt is generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled bit 5 Unimplemented: Read as ‘0’ bit 4 CREF: Comparator Reference Select bit (non-inverting input) 1 = Non-inverting input connects to the internal reference defined by the CVREFSEL bit in CMSTAT register 0 = Non-inverting input connects to the CxINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH[1:0]: Comparator Channel Select bits 11 = Inverting input of the comparator connects to the band gap reference voltage 10 = Inverting input of the comparator connects to the CxIND pin 01 = Inverting input of the comparator connects to the CxINC pin 00 = Inverting input of the comparator connects to the CxINB pin  2016-2019 Microchip Technology Inc. DS60001387D-page 247 PIC32MM0256GPM064 FAMILY NOTES: DS60001387D-page 248  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 23.0 Note: VOLTAGE REFERENCE (CVREF) This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 20. “Comparator Voltage Reference” (www.microchip.com/ DS61109) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. The CVREF module is a 32-TAP DAC that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently from them. The module’s supply reference can be provided from either the device VDD/VSS or an external voltage reference pin. The CVREF output is available for the comparators and for pin output. The voltage reference has the following features: • 32 Output Levels are Available • Internally Connected to Comparators to Conserve Device Pins • Output can be Connected to a Pin A block diagram of the CVREF module is illustrated in Figure 23-1. FIGURE 23-1: VOLTAGE REFERENCE BLOCK DIAGRAM REFSEL[1:0] CVREF+ AVDD DACDAT[4:0] R R Output to Comparators R 32 Steps R 32-to-1 MUX R CVREF DACOE R R AVSS  2016-2019 Microchip Technology Inc. DS60001387D-page 249 Voltage Reference Control Registers VOLTAGE REFERENCE REGISTER MAP 2380 DAC1CON 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — 15:0 ON — — — — — — — — — — — DACOE — — — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: The register in this table has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively. 20/4 19/3 — — 18/2 17/1 16/0 DACDAT[4:0] — All Resets Bit Range Bits Register Name(1) Virtual Address (BF80_#) TABLE 23-1: 0000 REFSEL[1:0] 0000 PIC32MM0256GPM064 FAMILY DS60001387D-page 250 23.1  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 23-1: Bit Range 31:24 23:16 15:8 7:0 DAC1CON: VOLTAGE REFERENCE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — R/W-0 U-0 U-0 U-0 U-0 DACDAT[4:0] U-0 U-0 R/W-0 ON — — — — — — DACOE U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — REFSEL[1:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-21 Unimplemented: Read as ‘0’ bit 20-16 DACDAT[4:0]: Voltage Reference Selection bits 11111 = (DACDAT[4:0] * CVREF+/32) or (DACDAT[4:0] * AVDD/32) volts depending on the REFSEL[1:0] bits • • • 00000 = 0.0 volts bit 15 ON: Voltage Reference Enable bit 1 = Voltage reference is enabled 0 = Voltage reference is disabled bit 14-9 Unimplemented: Read as ‘0’ bit 8 DACOE: Voltage Reference Output Enable bit 1 = Voltage level is output on the CVREF pin 0 = Voltage level is disconnected from the CVREF pin bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 REFSEL[1:0]: Voltage Reference Source Select bits 11 = Reference voltage is AVDD 10 = No reference is selected – output is AVSS 01 = Reference voltage is the CVREF+ input pin voltage 00 = No reference is selected – output is AVSS  2016-2019 Microchip Technology Inc. DS60001387D-page 251 PIC32MM0256GPM064 FAMILY NOTES: DS60001387D-page 252  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 24.0 HIGH/LOW-VOLTAGE DETECT (HLVD) The HLVD Control register (see Register 24-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned off” by the user under software control, which minimizes the current consumption for the device. The High/Low-Voltage Detect (HLVD) module is a programmable circuit that allows the user to specify both the device voltage trip point and the direction of change. An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. FIGURE 24-1: VDD HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM Externally Generated Trip Point VDD LVDIN HLVDL[3:0] 16-to-1 MUX ON VDIR – Set HLVDIF + Band Gap 1.2V Typical ON  2016-2019 Microchip Technology Inc. DS60001387D-page 253 High/Low-Voltage Detect Registers HIGH/LOW-VOLTAGE DETECT REGISTER MAP 2920 HLVDCON 31/15 30/14 29/13 28/12 31:16 — 15:0 ON 27/11 26/10 — — — — — — SIDL — VDIR BGVST 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — IRVST HLEVT — — — — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: The register in this table has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively. HLVDL[3:0] All Resets Bit Range Bits Register Name(1) Virtual Address (BF80_#) TABLE 24-1: 0000 0000 PIC32MM0256GPM064 FAMILY DS60001387D-page 254 24.1  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 24-1: Bit Range 31:24 23:16 15:8 7:0 HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — R/W-0 U-0 R/W-0 U-0 R/W-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC ON — SIDL — VDIR BGVST IRVST HLEVT U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — HLVDL[3:0] Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: HLVD Power Enable bit 1 = HLVD is enabled 0 = HLVD is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: HLVD Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 Unimplemented: Read as ‘0’ bit 11 VDIR: Voltage Change Direction Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL[3:0]) 0 = Event occurs when voltage equals or falls below trip point (HLVDL[3:0]) bit 10 BGVST: Band Gap Voltage Stable Flag bit 1 = Indicates that the band gap voltage is stable 0 = Indicates that the band gap voltage is unstable bit 9 IRVST: Internal Reference Voltage Stable Flag bit 1 = Internal reference voltage is stable; the High-Voltage Detect logic generates the interrupt flag at the specified voltage range 0 = Internal reference voltage is unstable; the High-Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 8 HLEVT: High/Low-Voltage Detection Event Status bit 1 = Indicates HLVD event is active 0 = Indicates HLVD event is not active bit 7-4 Unimplemented: Read as ‘0’  2016-2019 Microchip Technology Inc. DS60001387D-page 255 PIC32MM0256GPM064 FAMILY REGISTER 24-1: bit 3-0 HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER (CONTINUED) HLVDL[3:0]: High/Low-Voltage Detection Limit bits 1111 = External analog input is used (input comes from the LVDIN pin and compared with 1.2V band gap) 1110 = VDD trip point is between 2.00V and 2.22V 1101 = VDD trip point is between 2.08V and 2.33V 1100 = VDD trip point is between 2.15V and 2.44V 1011 = VDD trip point is between 2.25V and 2.55V 1010 = VDD trip point is between 2.35V and 2.69V 1001 = VDD trip point is between 2.45V and 2.80V 1000 = VDD trip point is between 2.65V and 2.98V 0111 = VDD trip point is between 2.75V and 3.09V 0110 = VDD trip point is between 2.95V and 3.30V 0101 = VDD trip point is between 3.25V and 3.63V 0100-0000 = Reserved; do not use. DS60001387D-page 256  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 25.0 POWER-SAVING FEATURES Note: This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “Power-Saving Modes” (www.microchip.com/DS60001130) in the “PIC32 Family “Reference Manual”. The information in this data sheet supersedes the information in the FRM. TABLE 25-1: Operating Mode This section describes the power-saving features for the PIC32MM0256GPM064 family devices. These devices offer various methods and modes that allow the application to balance power consumption with device performance. In all of the methods and modes described in this section, power saving is controlled by software. The peripherals and CPU can be halted or disabled to reduce power consumption. Table 25-1 summarizes the different operating modes available in XLP Technology. POWER-SAVING OPERATING MODES FOR XLP TECHNOLOGY DEVICES Active Clocks Active Peripherals Wake-up Sources Typical Current(1) Wake-up Time Typical Usage Low-Voltage/ Retention Sleep • • • • RTCC WDT Timer1 BOR Change Notice (CN) WDT, RTCC and CN 450 nA Most low-power  applications Sleep Same as  • Timer1 Low-Voltage/ • Timer2/3 Retention Sleep • WDT • SCCP/MCCP • SPI • I2C • UART • RTCC • ADC • CLC • Comparators (CMP) • CVREF • HLVD • INTx • REFO • HLVD • BOR Same as  Low-Voltage/ Retention Sleep 4-5 µA Most low-power  applications 4-5 times the Sleep current Most low-power  applications Timer1/SOSC INTRC/LPRC A/D RC REFO • • • • • Sleep with fast Same as Sleep wake-up Same as Sleep Same as Sleep Idle All clocks All peripherals All device wake-up 33% of run  current sources Any time the device is waiting for an event to occur (e.g., external or peripheral interrupts) All clocks All peripherals Not applicable Normal operation Run Note 1: 8 mA (24 MHz) Values listed are approximations of typical values intended for generalized comparisons. Refer to Section 29.0 “Electrical Characteristics” for actual values and operating conditions.  2016-2019 Microchip Technology Inc. DS60001387D-page 257 PIC32MM0256GPM064 FAMILY 25.1 Sleep Mode In Sleep mode, the CPU and most peripherals are halted and the associated clocks are disabled. Some peripherals can continue to operate in Sleep mode and can be used to wake the device from Sleep. See the individual peripheral module sections for descriptions of behavior in Sleep. The device enters Sleep mode when the SLPEN bit (OSCCON[4]) is set and a WAIT instruction is executed. Sleep mode includes the following characteristics: 25.3 Retention Sleep Mode Retention Sleep uses a separate voltage regulator to provide the lowest power Sleep mode. This mode has a longer wake-up time than Sleep or Standby Sleep. This mode is entered by clearing the RETVR Configuration bit (FPOR[2]) and setting the RETEN bit (PWRCON[1]) prior to entering Sleep mode, and executing a WAIT instruction. Only select peripherals, such as Timer1, WDT, RTCC and REFO, can operate in Retention Sleep mode. • There can be a Wake-up Delay based on the Oscillator Selection • The Fail-Safe Clock Monitor (FSCM) does not Operate During Sleep mode • The BOR Circuit remains Operative during Sleep mode • The WDT, if Enabled, is not Automatically Cleared prior to Entering Sleep mode • Some Peripherals can Continue to Operate at  Limited Functionality in Sleep mode; these  Peripherals include I/O Pins that Detect a Change in the Input Signal, WDT, ADC, UART and  Peripherals that Use an External Clock Input or the Internal LPRC Oscillator (e.g., RTCC and Timer1) • I/O Pins Continue to Sink or Source Current in the Same Manner as they do when the Device is not in Sleep 25.4 The processor will exit, or “wake-up”, from Sleep on one of the following events: The processor will wake or exit from Idle mode on the following events: • On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority. • On any form of device Reset. • On a WDT time-out. • On any interrupt event for which the interrupt source is enabled. The priority of the interrupt event must be greater than the current priority of the CPU. If the priority of the interrupt event is lower than or equal to the current priority of the CPU, the CPU will remain halted and the device will remain in Idle mode. • On any form of device Reset. • On a WDT time-out interrupt. If the interrupt priority is lower than or equal to the current priority, the CPU will remain halted, but the Peripheral Bus Clock (PBCLK) will start running and the device will enter into Idle mode. To set or clear the SLPEN bit, an unlock sequence must be executed. Refer to Section 26.4 “System Registers Write Protection” for details. 25.2 Note: In Retention mode, the maximum peripheral output frequency to an I/O pin must be less than 33 kHz. Note: When MCLR is used to wake the device from Retention Sleep, a POR Reset will occur. Idle Mode In Idle mode, the CPU is halted; however, all clocks are still enabled. This allows peripherals to continue to operate. Peripherals can be individually configured to halt when entering Idle by setting their respective SIDL bit. Latency, when exiting Idle mode, is very low due to the CPU oscillator source remaining active. The device enters Idle mode when the SLPEN bit (OSCCON[4]) is clear and a WAIT instruction is executed. To set or clear the SLPEN bit, an unlock sequence must be executed. Refer to Section 26.4 “System Registers Write Protection” for details. Standby Sleep Mode Standby Sleep mode places the voltage regulator in Standby mode. This mode draws less power than Sleep mode but has a longer wake-up time. Standby Sleep mode is entered by clearing the VREGS bit (PWRCON[0]) prior to entering Sleep by executing a WAIT instruction. All peripherals that can operate in Sleep mode can operate in Standby Sleep mode. DS60001387D-page 258  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 25.5 Peripheral Module Disable The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled using the appropriate PMDx control bit, the peripheral is in a minimum power consumption state. The control and status registers associated with the peripheral are also disabled, so writes to those registers do not take effect and read values are invalid. To disable a peripheral, the associated PMDx bit must be set to ‘1’. To enable a peripheral, the associated PMDx bit must be cleared (default). TABLE 25-2: To prevent accidental configuration changes under normal operation, writes to the PMDx registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the PMDLOCK bit in the PMDCON register (PMDCON[11]). Setting PMDLOCK prevents writes to the control registers; clearing PMDLOCK allows writes. To set or clear PMDLOCK, an unlock sequence must be executed. Refer to Section 26.4 “System Registers Write Protection” for details. Table 25-2 lists the module disable bits locations for all modules. PERIPHERAL MODULE DISABLE BITS AND LOCATIONS Peripheral PMDx Bit Name Register Name and Bit Location Analog-to-Digital Converter (ADC) ADCMD PMD1[0] Voltage Reference (VR) VREFMD PMD1[12] High/Low-Voltage Detect (HLVD) HLVDMD PMD1[20] Comparator 1 (CMP1) CMP1MD PMD2[0] Comparator 2 (CMP2) CMP2MD PMD2[1] Comparator 3 (CMP3) CMP3MD PMD2[2] Configurable Logic Cell 1 (CLC1) CLC1MD PMD2[24] Configurable Logic Cell 2 (CLC2) CLC2MD PMD2[25] Configurable Logic Cell 3 (CLC3) CLC3MD PMD2[26] Configurable Logic Cell 4 (CLC4) CLC4MD PMD2[27] Multiple Outputs Capture/Compare/PWM/ Timer1 (MCCP1) CCP1MD PMD3[8] Multiple Outputs Capture/Compare/PWM/ Timer2 (MCCP2) CCP2MD PMD3[9] Multiple Outputs Capture/Compare/PWM/ Timer3 (MCCP3) CCP3MD PMD3[10] Single Output Capture/Compare/PWM/ Timer4 (SCCP4) CCP4MD PMD3[11] Single Output Capture/Compare/PWM/ Timer5 (SCCP5) CCP5MD PMD3[12] Single Output Capture/Compare/PWM/ Timer6 (SCCP6) CCP6MD PMD3[13] Single Output Capture/Compare/PWM/ Timer7 (SCCP7) CCP7MD PMD3[14] Single Output Capture/Compare/PWM/ Timer8 (SCCP8) CCP8MD PMD3[15] Single Output Capture/Compare/PWM/ Timer9 (SCCP9) CCP9MD PMD3[16] Timer1 (TMR1) T1MD PMD4[0] Timer2 (TMR2) T2MD PMD4[1] Timer3 (TMR3) T3MD PMD4[2] Universal Asynchronous Receiver  Transmitter 1 (UART1) U1MD PMD5[0]  2016-2019 Microchip Technology Inc. DS60001387D-page 259 PIC32MM0256GPM064 FAMILY TABLE 25-2: PERIPHERAL MODULE DISABLE BITS AND LOCATIONS (CONTINUED) Peripheral PMDx Bit Name Register Name and Bit Location Universal Asynchronous Receiver  Transmitter 2 (UART2) U2MD PMD5[1] Universal Asynchronous Receiver  Transmitter 3 (UART3) U3MD PMD5[2] Serial Peripheral Interface 1 (SPI1) SPI1MD PMD5[8] Serial Peripheral Interface 2 (SPI2) SPI2MD PMD5[9] Serial Peripheral Interface 3 (SPI3) SPI3MD PMD5[10] Inter-Integrated Circuit Interface 1 (I2C1) I2C1MD PMD5[16] Inter-Integrated Circuit Interface 2 (I2C2) I2C2MD PMD5[17] Inter-Integrated Circuit Interface 3 (I2C3) I2C3MD PMD5[18] Universal Serial Bus (USB) USBMD PMD5[24] Real-Time Clock and Calendar (RTCC) RTCCMD PMD6[0] Reference Clock Output (REFO1) REFOMD PMD6[8] Direct Memory Access (DMA) DMAMD PMD7[4] DS60001387D-page 260  2016-2019 Microchip Technology Inc. Virtual Address (BF80_#) Register Name(1) 35B0 PMDCON PERIPHERAL MODULE DISABLE REGISTERS MAP 35C0 PMD1 35D0 PMD2 35E0 PMD3 PMD4 3600 PMD5 3610 PMD6 3620 PMD7 30/14 29/13 28/12 31:16 — — — 15:0 — — — 31:16 — — 15:0 — 31:16 15:0 31:16 15:0 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — FFFF — PMDLOCK — — — — — — — — — — — F7FF — — — — — — — — — HLVDMD — — — — FFEF — — VREFMD — — — — — — — — — — — ADCMD EFFE — — — — CLC4MD — — — F0FF — — — — — — — — — CCP8MD CCP7MD CCP6MD CCP5MD — CCP4MD CLC3MD CLC2MD CLC1MD — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CCP3MD CCP2MD CCP1MD CMP3MD CMP2MD CMP1MD FFF8 CCP9MD FFFE 00FF 31:16 — — — — — — — — — — — — — — — — FFFF 15:0 — — — — — — — — — — — — — T3MD T2MD T1MD FFF8 31:16 — — — — — — — USBMD — — — — — I2C3MD I2C2MD I2C1MD FEF8 15:0 — — — — — SPI3MD SPI2MD SPI1MD — — — — — U3MD U2MD U1MD F8F8 31:16 — — — — — — — — — — — — — — — — FEFF 15:0 — — — — — — — REFOMD — — — — — — — 31:16 — — — — — — — — — — — — — — — — FFFF 15:0 — — — — — — — — — — — DMAMD — — — — FFEF Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. RTCCMD FEFE DS60001387D-page 261 PIC32MM0256GPM064 FAMILY 35F0 31/15 All Resets Bits Bit Range  2016-2019 Microchip Technology Inc. TABLE 25-3: PIC32MM0256GPM064 FAMILY 25.6 On-Chip Voltage Regulator  Low-Power Modes The main on-chip regulator always consumes a small incremental amount of current over IDD/IPD, including when the device is in Sleep mode, even though the core digital logic does not require power. To provide additional savings in applications where power resources are critical, the regulator can be made to enter Standby mode on its own whenever the device goes into Sleep mode. This feature is controlled by the VREGS bit (PWRCON[0]). Clearing the VREGS bit enables Standby mode. Note 1: The SYSKEY register is used to unlock the PWRCON register. When in Sleep mode, PIC32MM0256GPM064 family devices may use a separate low-power, low-voltage/ retention regulator to power critical circuits. This regulator, which operates at 1.2V nominal, maintains power to data RAM, WDT, Timer1 and the RTCC, while all other core digital logic is powered down. The low-voltage/ retention regulator is only available when Sleep mode is invoked. It is controlled by the RETVR Configuration bit (FPOR[2]) and in firmware by the RETEN bit TABLE 25-4: (PWRCON[1]). RETVR must be programmed to zero (= 0) and the RETEN bit must be set (= 1) for the regulator to be enabled. When the retention regulator is enabled, the main regulator is off and does not consume power. Note 1: When using the low-voltage/retention regulator, VREGS (PWRCON[0]) must be set to ‘1’. The main voltage regulator takes approximately 10 μS to generate output. During this time, designated as TVREG, code execution is disabled. TVREG is applied every time the device resumes operation after standby (VREGS bit = 0) or retention (RETEN bit = 1, RETVR bit = 0) modes. The TVREG specification is listed in Table 29-12. 25.7 Low-Power Brown-out Reset The PIC32MM0256GPM064 family devices have a second low-power Brown-out Reset circuit with a reduced trip point precision. This low-power BOR circuit can be activated when the main BOR is disabled. It can be done by programming the LPBOREN Configuration bit (FPOR[3]) to one. PERIPHERALS IN VARIOUS WAKE-UP CONDITIONS Base Current Wake-up Time Wake-up Sources Idle Highest (Table 29-5) Idle Lowest (Table 29-23) Change Notice, Interrupt Pins All Usable Peripherals Power Save Mode Idle Sleep High (Table 29-5) Sleep Low (Table 29-23) Change Notice, Interrupt Pins RTCC, ADC, WDT, Timer1, Sleep Change Notice, Interrupt Pins Sleep Fast Wake Low (Table 29-5) Sleep Fast Wake High (Table 29-23) Change Notice, Interrupt Pins RTCC, ADC, WDT, Timer1, Sleep Fast Wake Change Notice, Interrupt Pins Retention Sleep Lowest Retention Sleep Highest Change Notice, Interrupt Pins RTCC, REFO, Timer1, WDT Retention Sleep (Table 29-5) (Table 29-23) DS60001387D-page 262  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 26.0 Note: 26.1 SPECIAL FEATURES This data sheet summarizes the features of the PIC32MM0256GPM064 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 33. “Programming and Diagnostics” (www.microchip.com/ DS61129) in the “PIC32 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. Configuration Bits PIC32MM0256GPM064 family devices contain a Boot Flash Memory (BFM) with an associated configuration space. All Configuration Words are listed in Table 26-3 and Table 26-4, and Register 26-1 through Register 26-6 describe the configuration options. 26.2 Code Execution from RAM PIC32MM0256GPM064 family devices allow executing the code from RAM. The starting boundary of this special RAM space can be adjusted using the EXECADDR[7:0] bits in the CFGCON register with a 1-Kbyte step. Writing a non-zero value to these bits will move the boundary, effectively reducing the total amount of program memory space in RAM. Refer to Table 26-5 and Register 26-7 for more information. 26.3 The Device ID identifies the device used. The ID can be read from the DEVID register. The Device IDs for the PIC32MM0256GPM064 family devices are listed in Table 26-1. Also refer to Table 26-5 and Register 26-8 for more information. DEVICE IDs FOR PIC32MM0256GPM064 FAMILY DEVICES Device DEVID PIC32MM0064GPM028 PIC32MM0128GPM028 PIC32MM0256GPM028 PIC32MM0064GPM036 PIC32MM0128GPM036 PIC32MM0256GPM036 PIC32MM0064GPM048 PIC32MM0128GPM048 PIC32MM0256GPM048 PIC32MM0064GPM064 PIC32MM0128GPM064 PIC32MM0256GPM064 0x07708053 0x07710053 0x07718053 0x0770A053 0x07712053 0x0771A053 0x0772C053 0x07734053 0x0773C053 0x0770E053 0x07716053 0x0771E053  2016-2019 Microchip Technology Inc. System Registers Write Protection The critical registers in the PIC32MM0256GPM064 family devices are protected (locked) to prevent an accidental write. If the registers are locked, a special two-step unlock sequence is required to modify the content of these registers (refer to Example 26-1). Once an unlock sequence is performed, the registers remain unlocked until they are relocked by writing an invalid key value. A system unlock sequence is invalidated by writes to addresses other than SYSKEY. To prevent this, DMA transfers and interrupts should be disabled or the unlock sequence can be performed until a read of SYSKEY indicates a successful unlock (refer to Example 26-2). To unlock the registers, the following steps should be done: 1. 2. 3. 4. 5. 6. Device ID TABLE 26-1: 26.4 Disable interrupts and DMA transfers prior to the system unlock sequence. Write a non-key value (such as 0x00000000) to the SYSKEY register to perform a lock. Execute the system unlock sequence by writing the key values of 0xAA996655 and 0x556699AA to the SYSKEY register, in two back-to-back assembly or ‘C’ instructions. Write the new value to the required register. Write a non-key value (such as 0x00000000) to the SYSKEY register to perform a lock. Re-enable interrupts and DMA transfers. EXAMPLE 26-1: SYSTEM UNLOCK SYSKEY = 0; SYSKEY = AA996655; SYSKEY = 556699AA; // user code to modify SYSKEY = 0; EXAMPLE 26-2: // force lock // unlock sequence // lock sequence register contents // relock SYSTEM UNLOCK WITH DMA AND INTERRUPTS ENABLED While (SYSKEY == 0) // repeat unlock sequence until unlock succeeds { SYSKEY = 0; // force lock SYSKEY = AA996655; // unlock sequence SYSKEY = 556699AA; // lock sequence } // user code to modify register contents SYSKEY = 0; // relock DS60001387D-page 263 PIC32MM0256GPM064 FAMILY The registers that require this unlocking sequence are listed in the Table 26-2. TABLE 26-2: Register Name SYSTEM LOCKED REGISTERS Register Description Peripheral OSCCON Oscillator Control Oscillator SPLLCON System PLL Control Oscillator OSCTUN FRC Tuning Oscillator PMDCON Peripheral Module Disable Control PMD RSWRST Software Reset Reset RPCON Peripheral Pin Select Configuration I/O Ports PWRCON Sleep Power Control System RTCCON1 RTCC Control RTCC The SYSKEY register read value indicates the status. A value of ‘0’ indicates that the system registers are locked. A value of ‘1’ indicates that the system registers are unlocked. For more information about the SYSKEY register refer to Table 26-5 and Register 26-9. 26.5 Band Gap Voltage Reference PIC32MM0256GPM064 family devices have a precision voltage reference band gap circuit used by many modules. The analog buffers are implemented between the band gap circuit and these modules. The buffers are automatically enabled by the hardware if some part of the device needs the band gap reference. The stabilization time is required when the buffer is switched on. The software can enable these buffers in advance to allow the band gap voltage to stabilize before the module uses it. The ANGFG register contains bits to enable the band gap buffers for the comparators (VBGCMP bit) and ADC (VBGADC bit). Refer to Table 26-6 and Register 26-10 for more information. 26.6 26.7 Unique Device Identifier (UDID) PIC32MM0256GPM064 family devices are individually encoded during final manufacturing with a Unique Device Identifier or UDID. The UDID cannot be erased by a bulk erase command or any other user accessible means. This feature allows for manufacturing traceability of Microchip Technology devices in applications where this is a requirement. It may also be used by the application manufacturer for any number of things that may require unique identification, such as: • Tracking the device • Unique serial number • Unique security key The UDID comprises five 32-bit program words. When taken together, these fields form a unique 160-bit identifier. The UDID is stored in five read-only locations, located from 0xBFC41840 to 0xBFC41850 in the device configuration space. Table 26-7 lists the addresses of the Identifier Words. 26.8 Reserved Registers PIC32MM0256GPM064 family devices have three reserved registers, located at 0xBF800400, 0xBF800480 and 0xBF802280. The application code must not modify these reserved locations. Table 26-8 lists the addresses of these reserved registers. Programming and Diagnostics PIC32MM0256GPM064 family devices provide a complete range of programming and diagnostic features: • Simplified field programmability using two-wire  In-Circuit Serial Programming™ (ICSP™) interfaces • Debugging using ICSP • Programming and debugging capabilities using the EJTAG extension of JTAG • JTAG boundary scan testing for device and board diagnostics DS60001387D-page 264  2016-2019 Microchip Technology Inc. Configuration Word Registers CONFIGURATION WORDS SUMMARY Register Name TABLE 26-3: Virtual Address (BFC0_#) 17C0 RESERVED 17C4 17C8 Bits FDEVOPT FICD FPOR 17D0 FWDT 17D4 FOSCSEL 17D8 FSEC 17DC 17E0 17E4 RESERVED RESERVED RESERVED 31\15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 31:16 USERID[15:0] 15:0 FVBUSIO FUSBIDIO r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ALTI2C SOSCHP r-1 r-1 r-1 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 JTAGEN r-1 r-1 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 LPBOREN RETVR r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 31:16 r-1 15:0 FWDTEN 31:16 r-1 15:0 RCLKSEL[1:0] r-1 FCKSM[1:0] RWDTPS[4:0] r-1 r-1 r-1 r-1 r-1 SOSCSEL r-1 OSCIOFNC r-1 WINDIS r-1 r-1 POSCMOD[1:0] ICS[1:0] FWDTWINSZ[1:0] BOREN[1:0] r-1 r-1 r-1 r-1 SWDTPS[4:0] r-1 r-1 r-1 r-1 r-1 IESO SOSCEN r-1 PLLSRC r-1 r-1 FNOSC[2:0] 31:16 CP r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 31:16 r-0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 Legend: r-0 = Reserved bit, must be programmed as ‘0’; r-1 = Reserved bit, must be programmed as ‘1’. DS60001387D-page 265 PIC32MM0256GPM064 FAMILY 17CC Bit Range  2016-2019 Microchip Technology Inc. 26.9 Virtual Address (BFC0_#) Register Name ALTERNATE CONFIGURATION WORDS SUMMARY 1740 RESERVED 1744 1748 AFDEVOPT AFICD 174C AFPOR 1750 AFWDT 1754 AFOSCSEL 1758 AFSEC 175C 1760 1764 RESERVED RESERVED RESERVED Bit Range Bits 31\15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 31:16 USERID[15:0] 15:0 FVBUSIO FUSBIDIO r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ALTI2C SOSCHP r-1 r-1 r-1 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 JTAGEN r-1 r-1 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 31:16 r-1 15:0 FWDTEN 31:16 r-1 15:0 RCLKSEL[1:0] r-1 FCKSM[1:0] RWDTPS[4:0] r-1 r-1 r-1 r-1 r-1 SOSCSEL r-1 OSCIOFNC r-1 WINDIS r-1 r-1 POSCMOD[1:0] ICS[1:0] r-1 LPBOREN RETVR r-1 FWDTWINSZ[1:0] BOREN[1:0] r-1 r-1 r-1 r-1 r-1 SWDTPS[4:0] r-1 r-1 r-1 r-1 r-1 IESO SOSCEN r-1 PLLSRC r-1 r-1 FNOSC[2:0] 31:16 CP r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 31:16 r-0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 31:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 15:0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1  2016-2019 Microchip Technology Inc. Legend: r-0 = Reserved bit, must be programmed as ‘0’; r-1 = Reserved bit, must be programmed as ‘1’. PIC32MM0256GPM064 FAMILY DS60001387D-page 266 TABLE 26-4: PIC32MM0256GPM064 FAMILY REGISTER 26-1: Bit Range 31:24 23:16 15:8 7:0 FDEVOPT/AFDEVOPT: DEVICE OPTIONS CONFIGURATION REGISTER Bit 31/23/15/7 R/P Bit Bit 30/22/14/6 29/21/13/5 R/P Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/P R/P R/P R/P R/P R/P R/P R/P R/P USERID[15:8] R/P R/P R/P R/P R/P R/P R/P r-1 r-1 r-1 r-1 r-1 r-1 FVBUSIO FUSBIDIO — — — — — — r-1 r-1 r-1 R/P R/P r-1 r-1 r-1 — — — ALTI2C SOSCHP — — — USERID[7:0] Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 USERID[15:0]: User ID bits (2 bytes which can programmed to any value) bit 15 FVBUSIO: USB VBUS_ON Selection bit 1 = VBUSON pin is controlled by the USB module 0 = VBUSON pin is controlled by the port function bit 14 FUSBIDIO: USB USBID Selection bit 1 = USBID pin is controlled by the USB module 0 = USBID pin is controlled by the port function bit 13-5 Reserved: Program as ‘1’ bit 4 ALTI2C: Alternate I2C1 Location Select bit 1 = SDA1 and SCL1 are on pins, RB8 and RB9 0 = SDA1 and SCL1 are moved to alternate I2C locations, RB5 and RC9 bit 3 SOSCHP: Secondary Oscillator (SOSC) High-Power Enable bit 1 = SOSC operates in normal power mode 0 = SOSC operates in High-Power mode bit 2-0 Reserved: Program as ‘1’  2016-2019 Microchip Technology Inc. DS60001387D-page 267 PIC32MM0256GPM064 FAMILY REGISTER 26-2: Bit Range 31:24 23:16 15:8 7:0 FICD/AFICD: ICD/DEBUG CONFIGURATION REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 R/P R/P R/P r-1 r-1 — — — JTAGEN — — ICS[1:0] Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-5 Reserved: Program as ‘1’ bit 4-3 ICS[1:0]: ICE/ICD Communication Channel Selection bits 11 = Communicates on PGEC1/PGED1 10 = Communicates on PGEC2/PGED2 01 = Communicates on PGEC3/PGED3 00 = Not connected bit 2 JTAGEN: JTAG Enable bit 1 = JTAG is enabled 0 = JTAG is disabled bit 1-0 Reserved: Program as ‘1’ DS60001387D-page 268 x = Bit is unknown  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 26-3: Bit Range 31:24 23:16 15:8 7:0 FPOR/AFPOR: POWER-UP SETTINGS CONFIGURATION REGISTER Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 R/P R/P R/P R/P — — — — LPBOREN RETVR BOREN[1:0] Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-4 Reserved: Program as ‘1’ bit 3 LPBOREN: Low-Power BOR Enable bit 1 = Low-Power BOR is enabled when main BOR is disabled 0 = Low-Power BOR is disabled bit 2 RETVR: Retention Voltage Regulator Enable bit 1 = Retention regulator is disabled 0 = Retention regulator is enabled and controlled by the RETEN bit during Sleep bit 1-0 BOREN[1:0]: Brown-out Reset Enable bits 11 = Brown-out Reset is enabled in hardware; SBOREN bit is disabled 10 = Brown-out Reset is enabled only while device is active and disabled in Sleep; SBOREN bit is disabled 01 = Brown-out Reset is controlled with the SBOREN bit setting 00 = Brown-out Reset is disabled in hardware; SBOREN bit is disabled  2016-2019 Microchip Technology Inc. DS60001387D-page 269 PIC32MM0256GPM064 FAMILY REGISTER 26-4: Bit Range 31:24 23:16 15:8 7:0 FWDT/AFWDT: WATCHDOG TIMER CONFIGURATION REGISTER Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P FWDTEN R/P WINDIS RCLKSEL[1:0] R/P R/P RWDTPS[4:0] FWDTWINSZ[1:0] R/P SWDTPS[4:0] Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Reserved: Program as ‘1’ bit 15 FWDTEN: Watchdog Timer Enable bit 1 = WDT is enabled 0 = WDT is disabled bit 14-13 RCLKSEL[1:0]: Run Mode Watchdog Timer Clock Source Selection bits 11 = Clock source is the LPRC oscillator (same as for Sleep mode) 10 = Clock source is the FRC oscillator 01 = Reserved 00 = Clock source is the system clock bit 12-8 RWDTPS[4:0]: Run Mode Watchdog Timer Postscale Select bits From 10100 to 11111 = 1:1048576. 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 bit 7 WINDIS: Windowed Watchdog Timer Disable bit 1 = Windowed mode is disabled 0 = Windowed mode is enabled DS60001387D-page 270  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 26-4: FWDT/AFWDT: WATCHDOG TIMER CONFIGURATION REGISTER (CONTINUED) bit 6-5 FWDTWINSZ[1:0]: Watchdog Timer Window Size bits 11 = Watchdog Timer window size is 25% 10 = Watchdog Timer window size is 37.5% 01 = Watchdog Timer window size is 50% 00 = Watchdog Timer window size is 75% bit 4-0 SWDTPS[4:0]: Sleep Mode Watchdog Timer Postscale Select bits From 10100 to 11111 = 1:1048576. 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1  2016-2019 Microchip Technology Inc. DS60001387D-page 271 PIC32MM0256GPM064 FAMILY REGISTER 26-5: Bit Range 31:24 23:16 15:8 7:0 FOSCSEL/AFOSCSEL: OSCILLATOR SELECTION CONFIGURATION  REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — R/P R/P r-1 R/P r-1 R/P R/P R/P FCKSM[1:0] R/P (1) IESO — SOSCSEL — OSCIOFNC R/P r-1 R/P r-1 R/P SOSCEN — PLLSRC — POSCMOD[1:0] R/P R/P FNOSC[2:0] Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Reserved: Program as ‘1’ bit 15-14 FCKSM[1:0]: Clock Switching and Fail-Safe Clock Monitor Enable bits 11 = Clock switching is enabled; Fail-Safe Clock Monitor is enabled 10 = Clock switching is disabled; Fail-Safe Clock Monitor is enabled 01 = Clock switching is enabled; Fail-Safe Clock Monitor is disabled 00 = Clock switching is disabled; Fail-Safe Clock Monitor is disabled bit 13 Reserved: Program as ‘1’ bit 12 SOSCSEL: Secondary Oscillator (SOSC) External Clock Enable bit 1 = Crystal is used (RA4 and RB4 pins are controlled by the SOSC) 0 = External clock connected to the SOSCO pin is used (RA4 and RB4 pins are controlled by I/O PORTx registers) bit 11 Reserved: Program as ‘1’ bit 10 OSCIOFNC: System Clock on CLKO Pin Enable bit 1 = CLKO/OSC2 pin operates as normal I/O 0 = System clock is connected to the CLKO/OSC2 pin bit 9-8 POSCMOD[1:0]: Primary Oscillator (POSC) Mode Selection bits 11 = Primary Oscillator is disabled 10 = HS Oscillator mode is selected 01 = XT Oscillator mode is selected 00 = External Clock (EC) mode is selected bit 7 IESO: Two-Speed Start-up Enable bit(1) 1 = Two-Speed Start-up is enabled 0 = Two-Speed Start-up is disabled bit 6 SOSCEN: Secondary Oscillator (SOSC) Enable bit 1 = Secondary Oscillator enable 0 = Secondary Oscillator disable bit 5 Reserved: Program as ‘1’ bit 4 PLLSRC: System PLL Input Clock Selection bit 1 = FRC oscillator is selected as the PLL reference input on a device Reset 0 = Primary Oscillator (POSC) is selected as the PLL reference input on a device Reset bit 3 Reserved: Program as ‘1’ Note 1: Refer to Section 9.3 “Two-Speed Start-up” for Two-Speed Start-up operation and limitations. DS60001387D-page 272  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 26-5: FOSCSEL/AFOSCSEL: OSCILLATOR SELECTION CONFIGURATION  REGISTER (CONTINUED) bit 2-0 FNOSC[2:0]: Oscillator Selection bits 110 and 111 = Reserved (selects Fast RC (FRC) Oscillator with Divide-by-N) 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Reserved 010 = Primary Oscillator (XT, HS, EC) 001 = Primary or FRC Oscillator with PLL 000 = Fast RC Oscillator (FRC) with Divide-by-N Note 1: Refer to Section 9.3 “Two-Speed Start-up” for Two-Speed Start-up operation and limitations. REGISTER 26-6: Bit Range 31:24 23:16 15:8 7:0 FSEC/AFSEC: CODE-PROTECT CONFIGURATION REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/P r-1 r-1 r-1 r-1 r-1 r-1 r-1 CP — — — — — — — r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31 CP: Code Protection Enable bit 1 = Code protection is disabled 0 = Code protection is enabled bit 30-0 Reserved: Program as ‘1’  2016-2019 Microchip Technology Inc. x = Bit is unknown DS60001387D-page 273 CFGCON 3660 DEVID 3670 SYSKEY 31/15 30/14 29/13 28/12 27/11 26/10 31:16 — — — — BMXERRDIS — BMXARB[1:0] 15:0 — — — — — — — 31:16 25/9 24/8 23/7 22/6 21/5 — — — — 20/4 19/3 18/2 17/1 16/0 — r r EXECADDR[7:0] VER[3:0] DEVID[27:16] — JTAGEN All Resets(1) Bit Range Bits Register Name Virtual Address (BF80_#) 3640 RAM CONFIGURATION, DEVICE ID AND SYSTEM LOCK REGISTERS MAP 0000 0003 xxxx 15:0 DEVID[15:0] 31:16 SYSKEY[31:16] 0000 15:0 SYSKEY[15:0] 0001 Legend: x = unknown value on Reset; r = reserved bit; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: Reset values are dependent on the device variant. xxxx PIC32MM0256GPM064 FAMILY DS60001387D-page 274 TABLE 26-5:  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY REGISTER 26-7: Bit Range 31:24 23:16 15:8 7:0 CFGCON: CONFIGURATION CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 R/W-0 U-0 R/W-0 R/W-0 — BMXERRDIS — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-P U-0 r-1 r-1 — — — — JTAGEN — — — BMXARB[1:0] EXECADDR[7:0] Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 Unimplemented: Read as ‘0’ bit 27 BMXERRDIS: Bus Matrix (BMX) Exception Error Disable bit 1 = Disables BMX error exception generation(1) 0 = Enables BMX error exception generation bit 26 Unimplemented: Read as ‘0’ bit 25-24 BMXARB[1:0]: Bus Matrix Arbitration Mode Select bits 11 = Reserved 10 = Mode 2 – Round Robin 01 = Mode 1 – Fixed with CPU as the lowest priority 00 = Mode 0 – Fixed with CPU as the highest priority bit 23-16 EXECADDR[7:0]: RAM Program Space Start Address bits 11111111 = RAM program space starts at the 255-Kbyte boundary (from 0xA003FC00) • • • 00000010 = RAM program space starts at 2-Kbyte boundary (from 0xA0000800) 00000001 = RAM program space starts at 1-Kbyte boundary (from 0xA0000400) 00000000 = All data RAM is allocated to program space (from 0xA0000000) bit 15-4 Unimplemented: Read as ‘0’ bit 3 JTAGEN: JTAG Enable bit 1 = Enables 4-wire JTAG 0 = Disables 4-wire JTAG bit 2 Unimplemented: Read as ‘0’ bit 1-0 Reserved: Maintain as ‘1’ Note 1: An exception is not generated when an unimplemented address is accessed. The returned value on a read operation of unimplemented memory is 0x00000000.  2016-2019 Microchip Technology Inc. DS60001387D-page 275 PIC32MM0256GPM064 FAMILY REGISTER 26-8: Bit Range 31:24 23:16 15:8 7:0 DEVID: DEVICE ID REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-x R-x R-x R-x R-x R-x R-x R-x VER[3:0](1) R-x R-x ID[27:24](1) R-x R-x ID[23:16] R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x (1) R-x ID[15:8](1) R-x R-x R-x R-x ID[7:0] (1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 VER[3:0]: Revision Identifier bits(1) bit 27-0 DEVID[27:0]: Device ID bits(1) Note 1: Reset values are dependent on the device variant. REGISTER 26-9: Bit Range 31:24 23:16 15:8 7:0 SYSKEY: SYSTEM UNLOCK REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 W-0 W-0 W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 R/W-1 SYSKEY[31:24] W-0 W-0 W-0 W-0 W-0 SYSKEY[23:16] W-0 W-0 W-0 W-0 W-0 SYSKEY[15:8] W-0 W-0 W-0 W-0 W-0 SYSKEY[7:0] Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 x = Bit is unknown SYSKEY[31:0]: Unlock and Lock Key bits A write of 0xAA996655, followed by a write of 0x556699AA to SYSKEY, is required to unlock select system registers. Refer to Example 26-1. Bit 0 Indicates System Lock Status: 1 = The system is unlocked 0 = The system is locked DS60001387D-page 276  2016-2019 Microchip Technology Inc. Virtual Address (BF80_#) 2300 BAND GAP REGISTER MAP ANCFG(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 31:16 — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — All Resets Bit Range Bits Register Name  2016-2019 Microchip Technology Inc. TABLE 26-6: 18/2 17/1 16/0 — — — 0000 — 0000 VBGADC VBGCMP Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. PIC32MM0256GPM064 FAMILY DS60001387D-page 277 PIC32MM0256GPM064 FAMILY REGISTER 26-10: ANCFG: BAND GAP CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0, HS, HC R/W-0, HS, HC U-0 — — — — — VBGADC VBGCMP — Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-3 Unimplemented: Read as ‘0’ bit 2 VBGADC: ADC Band Gap Enable bit 1 = ADC band gap is enabled 0 = ADC band gap is disabled bit 1 VBGCMP: Comparator Band Gap Enable bit 1 = Comparator band gap is enabled 0 = Comparator band gap is disabled bit 0 Unimplemented: Read as ‘0’ DS60001387D-page 278  2016-2019 Microchip Technology Inc. Virtual Address (BF84_#) Register Name 1840 UDID1 1844 1848 184C UDID2 UDID3 UDID4 UDID5 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 xxxx UDID Word 1[31:0] 15:0 31:16 xxxx xxxx UDID Word 2[31:0] 15:0 31:16 xxxx xxxx UDID Word 3[31:0] 15:0 31:16 xxxx xxxx UDID Word 4[31:0] 15:0 31:16 xxxx xxxx UDID Word 5[31:0] 15:0 All Resets Bits xxxx Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Register Name RESERVED REGISTERS MAP Virtual Address (BF80_#) TABLE 26-8: 2900 RESERVED1 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 Reserved Register 1[31:0] Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits 0000 0000 DS60001387D-page 279 PIC32MM0256GPM064 FAMILY 1850 UNIQUE DEVICE IDENTIFIER (UDID) REGISTER MAP Bit Range  2016-2019 Microchip Technology Inc. TABLE 26-7: PIC32MM0256GPM064 FAMILY NOTES: DS60001387D-page 280  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 27.0 INSTRUCTION SET The PIC32MM0256GPM064 family instruction set complies with the MIPS® Release 3 instruction set architecture. Only microMIPS32™ instructions are supported. The PIC32MM0256GPM064 family does not have the following features: • Core extend instructions • Coprocessor 1 instructions • Coprocessor 2 instructions Note: Refer to the “MIPS® Architecture for Programmers Volume II-B: The microMIPS32™ Instruction Set” at www.imgtec.com for more information.  2016-2019 Microchip Technology Inc. DS60001387D-page 281 PIC32MM0256GPM064 FAMILY NOTES: DS60001387D-page 282  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 28.0 DEVELOPMENT SUPPORT Move a design from concept to production in record time with Microchip’s award-winning development tools. Microchip tools work together to provide state of the art debugging for any project with easy-to-use Graphical User Interfaces (GUIs) in our free MPLAB® X and Atmel Studio Integrated Development Environments (IDEs), and our code generation tools. Providing the ultimate ease-of-use experience, Microchip’s line of programmers, debuggers and emulators work seamlessly with our software tools. Microchip development boards help evaluate the best silicon device for an application, while our line of third party tools round out our comprehensive development tool solutions. Microchip’s MPLAB X and Atmel Studio ecosystems provide a variety of embedded design tools to consider, which support multiple devices, such as PIC® MCUs, AVR® MCUs, SAM MCUs and dsPIC® DSCs. MPLAB X tools are compatible with Windows®, Linux® and Mac® operating systems while Atmel Studio tools are compatible with Windows. Go to the following website for more information and details: https://www.microchip.com/development-tools/  2016-2019 Microchip Technology Inc. DS60001387D-page 283 PIC32MM0256GPM064 FAMILY NOTES: DS60001387D-page 284  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MM0256GPM064 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MM0256GPM064 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +4.0V Voltage on any general purpose digital or analog pin (not 5.5V tolerant) with respect to VSS ........ -0.3V to (VDD + 0.3V) Voltage on any general purpose digital or analog pin (5.5V tolerant) with respect to VSS: When VDD = 0V: .......................................................................................................................... -0.3V to +4.0V When VDD  2.0V: ....................................................................................................................... -0.3V to +6.0V Voltage on AVDD with respect to VDD .................................................... (VDD – 0.3V) to (lesser of: 4.0V or (VDD + 0.3V)) Voltage on AVSS with respect to VSS ......................................................................................................... -0.3V to +0.3V Maximum current out of VSS pin ...........................................................................................................................100 mA Maximum current into VDD pin(1) ...........................................................................................................................300 mA Maximum output current sunk by I/O pin ................................................................................................................ 11 mA Maximum output current sourced by I/O pin ...........................................................................................................16 mA Maximum output current sunk by I/O pin with increased current drive strength  (RA3, RA8, RA10, RB8, RB9, RB13, RB15, RC9, RC13 and RD0) .......................................................................17 mA Maximum output current sourced by I/O pin with increased current drive strength  (RA3, RA8, RA10, RB8, RB9, RB13, RB15, RC9, RC13 and RD0) .......................................................................24 mA Maximum current sunk by all ports .......................................................................................................................300 mA Maximum current sourced by all ports(1) ...............................................................................................................300 mA Note 1: † Maximum allowable current is a function of device maximum power dissipation (see Table 29-1). NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2016-2019 Microchip Technology Inc. DS60001387D-page 285 PIC32MM0256GPM064 FAMILY 29.1 DC Characteristics FIGURE 29-1: PIC32MM0256GPM064 FAMILY VOLTAGE-FREQUENCY GRAPH 3.6V 3.6V Voltage (VDD) PIC32MM0XXXGPM0XX 2.0V 2.0V 0V 25 MHz Frequency TABLE 29-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +125 °C PIC32MM0XXXGPM0XX: Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W PDMAX (TJ – TA)/JA W I/O Pin Power Dissipation: PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation TABLE 29-2: PACKAGE THERMAL RESISTANCE(1) Package Symbol Typ Unit 28-Pin SSOP JA 71.0 °C/W 28-Pin QFN JA 69.7 °C/W 28-Pin UQFN JA 26 °C/W 36-Pin VQFN JA 30.0 °C/W 40-Pin UQFN JA 41 °C/W 48-Pin UQFN JA 24.5 °C/W 48-Pin TQFP JA 51 °C/W 64-Pin QFN JA 29.4 °C/W 64-Pin TQFP JA 44.5 °C/W Note 1: Junction to ambient thermal resistance; Theta-JA (JA) numbers are achieved by package simulations. DS60001387D-page 286  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY TABLE 29-3: OPERATING VOLTAGE SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +125°C  (unless otherwise stated) DC CHARACTERISTICS Param Symbol No. DC10 DC16 Characteristic Min Typ Max Units Conditions VDD VPOR(1) Supply Voltage 2.0 — 3.6 V VDD Start Voltage VSS — 100 mV to Ensure Internal Power-on Reset Signal DC17a SVDD(1) Recommended 0.05 — — V/ms 0-3.3V in 66 ms, VDD Rise Rate 0-2.0V in 40 ms to Ensure Internal Power-on Reset Signal DC17b VBOR Brown-out Reset  2.0 — 2.083 V Voltage on VDD  Transition, High-to-Low Note 1: If the VPOR or SVDD parameters are not met, or the application experiences slow power-down VDD ramp rates, it is recommended to enable and use BOR. TABLE 29-4: OPERATING CURRENT (IDD)(2,3) DC CHARACTERISTICS Parameter No. DC19 DC19b DC23 DC23b DC24 DC24b DC25 DC25b Note 1: 2: 3: Typical(1) Max Units Operating Temperature VDD Conditions 0.72 0.96 mA -40°C to +85°C 2.0V FSYS = 1 MHz — 0.96 mA -40°C to +85°C 3.3V — 1.4 mA -40°C to +125°C 3.3V 2.5 3.7 mA -40°C to +85°C 2.0V FSYS = 8 MHz 2.5 3.7 mA -40°C to +85°C 3.3V 2.5 4.2 mA -40°C to +125°C 3.3V 7.9 10.2 mA -40°C to +85°C 2.0V FSYS = 25 MHz 7.9 10.2 mA -40°C to +85°C 3.3V 7.9 12.5 mA -40°C to +125°C 3.3V 0.4 0.8 mA -40°C to +85°C 2.0V LPRC, FSYS = 32 kHz 0.4 0.8 mA -40°C to +85°C 3.3V 0.4 1 mA -40°C to +125°C 3.3V Typical parameters are for design guidance only and are not tested. IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: • Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from  rail-to-rail (EC Clock Overshoot/Undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as outputs and driving low • MCLR = VDD; WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating or being clocked (defined PMDx bits are all ones) • CPU executing: while(1) { NOP(); } JTAG is disabled  2016-2019 Microchip Technology Inc. DS60001387D-page 287 PIC32MM0256GPM064 FAMILY TABLE 29-5: IDLE CURRENT (IIDLE)(2) DC CHARACTERISTICS Parameter No. Typical(1) Max Units Operating Temperature VDD 0.69 0.84 mA -40°C to +85°C 2.0V 0.69 0.84 mA -40°C to +85°C 3.3V 0.69 1.2 mA -40°C to +125°C 2.0V 0.69 1.2 mA -40°C to +125°C 3.3V 0.98 1.7 mA -40°C to +85°C 2.0V 0.98 1.7 mA -40°C to +85°C 3.3V 0.98 2.3 mA -40°C to +125°C 2.0V 0.98 2.3 mA -40°C to +125°C 3.3V 2.9 3.7 mA -40°C to +85°C 2.0V 2.9 3.7 mA -40°C to +85°C 3.3V DC42b 2.9 4.5 mA -40°C to +125°C 2.0V 2.9 4.5 mA -40°C to +125°C 3.3V DC44 0.36 0.7 mA -40°C to +85°C 2.0V 0.36 0.7 mA -40°C to +85°C 3.3V 0.40 1 mA -40°C to +125°C 2.0V 0.40 1 mA -40°C to +125°C 3.3V DC40 DC40b DC41 DC41b DC42 DC44b Note 1: 2: Conditions FSYS = 1 MHz FSYS = 8 MHz FSYS = 25 MHz FSYS = 32 kHz FSYS = 32 kHz Parameters are for design guidance only and are not tested. Base IIDLE current is measured with the core in Idle, the clock on and all modules turned off. OSC1 driven with external square wave from rail-to-rail (EC Clock Overshoot/Undershoot < 250 mV required).  Peripheral Module Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled  to VSS. DS60001387D-page 288  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY TABLE 29-6: POWER-DOWN CURRENT (IPD)(2) DC CHARACTERISTICS Parameter Typical(1) No. Max Units DC60 130 255 µA -40°C 130 255 µA +25°C 145 265 µA +85°C 185 400 µA +125°C 130 255 µA -40°C 130 265 µA +25°C 145 275 µA +85°C 200 400 µA +125°C 3.5 12 µA -40°C 4.5 22 µA +25°C 15 35 µA +85°C 18 100 µA +125°C 4 17 µA -40°C 5 30 µA +25°C 18 38 µA +85°C 55 110 µA +125°C 4.3 — µA -40°C 5 — µA +25°C 10 — µA +85°C 47 — µA +125°C DC61 DC62 DC63 Note 1: 2: Operating Temperature 5 — µA -40°C 5.6 — µA +25°C 12 — µA +85°C .3 — µA -40°C .4 — µA +25°C 3.5 — µA +85°C 0.35 — µA -40°C 0.45 — µA +25°C 4.5 — µA +85°C 37 — µA +125°C VDD Conditions 2.0V Sleep with active main Voltage Regulator (VREGS (PWRCON[0]) bit = 1,  RETEN (PWRCON[1]) bit = 0) 3.3V 2.0V Sleep with main Voltage Regulator in Standby mode  (VREGS (PWRCON[0]) bit = 0,  RETEN (PWRCON[1]) bit = 0) 3.3V 2.0V Sleep with enabled Retention  Voltage Regulator  (RETEN (PWRCON[1]) bit = 1,  RETVR (FPOR[2]) bit = 0) 3.3V 2.0V 3.3V Sleep with enabled Retention  Voltage Regulator  (VREGS (PWRCON[0]) bit = 0,  RETEN (PWRCON[1]) bit = 1,  RETVR (FPOR[2]) bit = 0) Parameters are for design guidance only and are not tested. Base IPD is measured with: • Oscillator is configured in FRC mode without PLL (FNOSC[2:0] (FOSCSEL[2:0]) = 000) • OSC1 pin is driven with external square wave from rail-to-rail  (EC Clock Overshoot/Undershoot < 250 mV required) • OSC2 is configured as an I/O in Configuration Words (OSCIOFNC (FOSCSEL[10]) = 1) • FSCM is disabled (FCKSM[1:0] (FOSCSEL[15:14]) = 00) • Secondary Oscillator circuits are disabled (SOSCEN (FOSCSEL[6]) = 0 and  SOSCSEL (FOSCSEL[12]) = 0) • Main and low-power BOR circuits are disabled (BOREN[1:0] (FPOR[1:0]) = 00 and  LPBOREN (FPOR[3]) = 0) • Watchdog Timer is disabled (FWDTEN (FWDT[15]) = 0) • All I/O pins (excepting OSC1) are configured as outputs and driven low • No peripheral modules are operating or being clocked (defined PMDx bits are all ones)  2016-2019 Microchip Technology Inc. DS60001387D-page 289 PIC32MM0256GPM064 FAMILY TABLE 29-7: CURRENT(2) DC CHARACTERISTICS Parameter No. Typical(1) Max Units Operating Temperature VDD Conditions Incremental Current Brown-out Reset (BOR) DC71 DC71c 3 — µA -40°C to +85°C 2.0V 4 — µA -40°C to +85°C 3.3V 5.3 — µA -40°C to +125°C 3.3V Brown-out Reset incremental current (BOR) Incremental Current Watchdog Timer (WDT) DC72 DC72c 0.22 — µA -40°C to +85°C 2.0V 0.3 — µA -40°C to +85°C 3.3V 0.4 — µA -40°C to +125°C 3.3V Watchdog Timer incremental current (∆WDT), LPRC on Incremental Current High/Low-Voltage Detect (HLVD) DC73 2.1 — µA -40°C to +85°C 2.0V 2.4 — µA -40°C to +85°C 3.3V 3.1 — µA -40°C to +125°C 3.3V High/Low-Voltage Detect  incremental current (∆HLVD) Incremental Current Real-Time Clock and Calendar (RTCC) DC74 DC74b DC75 DC75b 1.1 — µA -40°C to +85°C 2.0V 1.2 — µA -40°C to +85°C 3.3V 3.4 — µA -40°C to +125°C 3.3V 0.35 — µA -40°C to +85°C 2.0V 0.45 — µA -40°C to +85°C 3.3V 0.65 — µA -40°C to +125°C 3.3V RTCC (with SOSC) RTCC (with LPRC) Incremental Current ADC (ADC DC76 DC76b 450 — µA -40°C to +85°C 2.0V 475 — µA -40°C to +85°C 3.3V 600 — µA -40°C to +125°C 3.3V ΔADC (with Timer1 and  ADC internal oscillator enabled) Incremental Current Fast RC Oscillator (FRC) DC78 DC78b 300 — µA -40°C to +85°C 2.0V 310 — µA -40°C to +85°C 3.3V 350 — µA -40°C to +125°C 3.3V ΔFRC Incremental Current PLL (PLL) DC79 DC79a DC79b 1200 — µA -40°C to +85°C 2.0V 1340 — µA -40°C to +85°C 3.3V 1460 — µA -40°C to +85°C 2.0V 1600 — µA -40°C to +85°C 3.3V 1850 — µA -40°C to +125°C 3.3V ΔPLL (24 MHz) ΔPLL (48 MHz) ΔPLL (48 MHz) Incremental Current Voltage Reference CVREF (VREF) DC80 DC80b Note 1: 2: 30 — µA -40°C to +85°C 2.0V 35 — µA -40°C to +85°C 3.3V 50 — µA -40°C to +125°C 3.3V ΔVREF Data in the “Typical” column are for design guidance only and is not tested. The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. DS60001387D-page 290  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY TABLE 29-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. VIL Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C Min Typ(1) Max Units Input Low Voltage(3) DI10 I/O Pins with ST Buffer VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSC1 (XT mode) VSS — 0.2 VDD V OSC1 (HS mode) VSS — 0.2 VDD V I/O Pins with ST Buffer: Without 5V Tolerance With 5V Tolerance 0.8 VDD 0.8 VDD — — VDD 5.5 V V DI25 MCLR 0.8 VDD — VDD V DI26 OSCI (XT mode) 0.7 VDD — VDD V OSCI (HS mode) DI17 VIH DI20 DI27 DI30 ICNPU DI30A ICNPD IIL Conditions Input High Voltage(3) 0.7 VDD — VDD V CNPUx Pull-up Current 150 350 450 µA VDD = 3.3V, VPIN = VSS CNPDx Pull-Down Current 230 300 500 µA VDD = 3.3V, VPIN = VDD Input Leakage Current(2) DI50 I/O Pins – 5V Tolerant — — 1 µA VSS  VPIN  VDD, pin at high-impedance DI51 I/O Pins – Not 5V Tolerant — — 1 µA VSS  VPIN  VDD, pin at high-impedance DI55 MCLR — — 1 µA VSS VPIN VDD DI56 OSC1/CLKI — — 1 µA VSS VPIN VDD,  XT and HS modes Note 1: 2: 3: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Negative current is defined as current sourced by the pin. Refer to Table 1-1 for I/O pin buffer types.  2016-2019 Microchip Technology Inc. DS60001387D-page 291 PIC32MM0256GPM064 FAMILY TABLE 29-9: DC CHARACTERISTICS: I/O PIN INPUT INJECTION CURRENT SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. Characteristics Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C Min. Typical(1) Max. Units Conditions DI60a IICL Input Low Injection Current 0 — -5(2,5) mA This parameter applies to all pins. Maximum IICH current for this exception is 0 mA. DI60b IICH Input High Injection Current 0 — +5(3,4,5) mA This parameter applies to all pins, with the exception of all 5V tolerant pins and SOSCI. Maximum IICH current for these exceptions is 0 mA. DI60c IICT Total Input Injection Current (sum of all I/O and control pins) -20(6) — +20(6) mA Absolute instantaneous sum of all ± input injection currents from all I/O pins: ( | IICL + | IICH | )  IICT Note 1: 2: 3: 4: 5: 6: Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design  guidance only and are not tested. VIL Source < (VSS – 0.3). Characterized but not tested. VIH Source > (VDD + 0.3) for non-5V tolerant pins only. Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any “positive” input injection current. Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts  (i.e., VIH Source > (VDD + 0.3) or VIL Source < (VSS – 0.3)). Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, are permitted  provided the “absolute instantaneous” sum of the input injection currents from all pins do not  exceed the specified limit. If Note 2, IICL = (((VSS – 0.3) – VIL Source)/RS). If Note 3,  IICH = (((IICH Source – (VDD + 0.3))/RS). RS = Resistance between input source voltage and device pin. If (VSS – 0.3)  VSOURCE  (VDD + 0.3), Injection Current = 0. DS60001387D-page 292  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY TABLE 29-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. VOL DO10 Characteristic OSC2/CLKO VOH Min Typ(1) — — .4 V IOL = 6.6 mA, VDD = 3.6V — — .21 V IOL = 5.0 mA, VDD = 2V — — .16 V IOL = 6.6 mA, VDD = 3.6V — — .12 V IOL = 5.0 mA, VDD = 2V 3.25 — — V IOH = -6.0 mA, VDD = 3.6V 1.4 — — V IOH = -3.0 mA, VDD = 2V 3.3 — — V IOH = -6.0 mA, VDD = 3.6V 1.55 — — V IOH = -1.0 mA, VDD = 2V Max Units Conditions Output Low Voltage I/O Ports DO16 Output High Voltage DO20 I/O Ports DO26 OSC2/CLKO Note 1: Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C Min Typ(1) Max Units — E/W Conditions Program Flash Memory D130 EP Cell Endurance D131 VPR VDD for Read 10000 20000 2.0 — 3.6 V VBOR — 3.6 V D131B VICSP Vdd for In-Circuit Serial Programming™ (ICSP)™ D132B VDD for Self-Timed Write 2.0 — 3.6 V D133A TIW Self-Timed Double-Word Write Cycle Time 61.4 62.5 63.6 µs 8 bytes, data are not all ‘1’s Self-Timed Row Write Cycle Time 1.41 1.44 1.47 ms 512 bytes, data are not all ‘1’s; SYSCLK > 2 MHz D133B TIE Self-Timed Page Erase Time 4.18 4.26 4.33 ms 2048 bytes D134 TRETD Characteristic Retention D136 TCE Self-Timed Chip Erase Time Note 1: 20 — — Year 16.6 16.9 17.3 ms If no other specifications are violated Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated.  2016-2019 Microchip Technology Inc. DS60001387D-page 293 PIC32MM0256GPM064 FAMILY TABLE 29-12: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param No. Symbol Characteristics Min Typ Max Units Comments DVR10 VBG Internal Band Gap Reference — 1.2 — V DVR20 VRGOUT Regulator Output Voltage — 1.8 — V VDD > 1.9V DVR21 CEFC External Filter Capacitor Value 4.7 10 — µF Series Resistance < 3  recommended; < 5  required DVR30 VLVR Low-Voltage Regulator  Output Voltage 0.9 — 1.2 V RETEN = 1,  RETVR (FPOR[2]) = 0 TABLE 29-13: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Symbol No. DC18 VHLVD DC101 VTHL Characteristic Min Typ Max Units HLVD Voltage on VDD HLVDL[3:0] = 0101 Transition HLVDL[3:0] = 0110 3.25 — 3.63 V 2.95 — 3.30 V HLVDL[3:0] = 0111 2.75 — 3.09 V HLVDL[3:0] = 1000 2.65 — 2.98 V HLVDL[3:0] = 1001 2.45 — 2.80 V HLVDL[3:0] = 1010 2.35 — 2.69 V HLVDL[3:0] = 1011 2.25 — 2.55 V HLVDL[3:0] = 1100 2.15 — 2.44 V HLVDL[3:0] = 1101 2.08 — 2.33 V HLVDL[3:0] = 1110 2.00 — 2.22 V HLVDL[3:0] = 1111 — 1.2 — V HLVD Voltage on  LVDIN Pin Transition DS60001387D-page 294 Conditions  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY TABLE 29-14: COMPARATOR DC SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param No. Symbol D300 VIOFF Input Offset Voltage D301 VICM Input Common-Mode Voltage D307 TRESP Response Time Note 1: 2: Characteristic Min Typ Max Units Comments -20 — +20 mV (Note 1) VSS – 0.3V — VDD + 0.3V V (Note 1) — 150 — ns (Note 2) Parameters are characterized but not tested. Measured with one input at VDD/2 and the other transitioning from VSS to VDD, 40 mV step, 15 mV overdrive. TABLE 29-15: VOLTAGE REFERENCE DC SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param No. Symbol Characteristic Min Typ Max Units VRD310 TSET Settling Time — — 10 µs VRD311 VRAA Absolute Accuracy -1 — 1 LSb VRD312 VRUR Unit Resistor Value (R) — 4.5 — k Note 1: Comments (Note 1) Measures the interval while DACDAT[4:0] transitions from ‘11111’ to ‘00000’.  2016-2019 Microchip Technology Inc. DS60001387D-page 295 PIC32MM0256GPM064 FAMILY 29.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC32MM0256GPM064 family AC characteristics and timing parameters. TABLE 29-16: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C Operating voltage VDD range as described in Section 29.1 “DC Characteristics”. AC CHARACTERISTICS FIGURE 29-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2/CLKO Load Condition 2 – for OSC2/CLKO VDD/2 CL Pin RL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSC2/CLKO 15 pF for OSC2/CLKO output VSS TABLE 29-17: CAPACITIVE LOADING CONDITIONS ON OUTPUT PINS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions DO50 COSCO OSC2/CLKO Pin — — TBD pF In XT and HS modes when external clock is used to drive OSC1/CLKI DO56 CIO All I/O Pins and OSC2 — — TBD pF EC mode DO58 CB SCLx, SDAx — — TBD pF In I2C mode Legend: TBD = To Be Determined Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS60001387D-page 296  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY FIGURE 29-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS40 OS41 TABLE 29-18: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +125°C for Industrial AC CHARACTERISTICS Param Symbol No. OS10 FOSC Characteristic Min Typ(1) Max Units External CLKI Frequency DC 2 — — 25 48 MHz MHz EC ECPLL(2) Oscillator Frequency 3.5 3.5 10 10 31 — — — — — 10 10 32 24 50 MHz MHz MHz MHz kHz XT XTPLL HS HSPLL SOSC Conditions OS20 TOSC TOSC = 1/FOSC — — — — OS25 TCY Instruction Cycle Time 40 — DC ns OS30 TosL, TosH External Clock in (OSC1) 0.45 x TOSC High or Low Time — — ns EC OS31 TosR, TosF External Clock in (OSC1) Rise or Fall Time — — TBD ns EC OS40 TckR CLKO Rise Time(3) — 15 30 ns — 15 30 ns OS41 TckF CLKO Fall Time(3) See Parameter OS10 for FOSC value Legend: TBD = To Be Determined Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Represents input to the system clock prescaler. PLL dividers and postscalers must still be configured so that the system clock frequency does not exceed the maximum frequency, as shown in Figure 29-1. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.  2016-2019 Microchip Technology Inc. DS60001387D-page 297 PIC32MM0256GPM064 FAMILY TABLE 29-19: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +125°C for Industrial AC CHARACTERISTICS Param Symbol No. Characteristic Min Typ Max Units OS50 FPLLI PLL Input Frequency Range(1) 2 — 24 MHz OS54 FPLLO PLL Output Frequency Range(1) 16 — 96 MHz OS52 TLOCK PLL Start-up Time  (Lock Time) — — 24 µs OS53 DCLK CLKO Stability (Jitter) -0.12 — 0.12 % Note 1: Conditions These parameters are characterized but not tested in manufacturing. TABLE 29-20: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Characteristic F20 FRC Accuracy @ 8 MHz F21 LPRC @ 32 kHz F21b FRC Tune Step-Size  (in OSCTUN register) F22 Note 1: Min Typ Max Units Conditions 2.0 — 2 % 2.0V  VDD 3.6V, -40°C  TA 0°C(1) 1.5 — 1.5 % 2.0V  VDD 3.6V, 0°C  TA +85°C -5 — 5 % 2.0V  VDD 3.6V, +85°C  TA +125°C -.20 — .20 % 2.0V  VDD 3.6V, 0°C  TA +85°C,  self-tune enabled and locked -20 — 20 % VCAP Output Voltage = 1.8V -30 — 30 % 2.0V  VDD 3.6V, -40°C  TA +125°C — .05 — %/bit To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB) must be kept to a minimum. TABLE 29-21: RC OSCILLATOR START-UP TIME AC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +125°C for Industrial Min Typ Max Units FR0 TFRC FRC Oscillator Start-up Time — — 2 µs FR1 TLPRC Low-Power RC Oscillator Start-up Time — — 70 µs DS60001387D-page 298 Conditions  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY FIGURE 29-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Old Value New Value DO31 DO32 Note: Refer to Figure 29-2 for load conditions. TABLE 29-22: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +125°C for Industrial Min Typ(1) Max Units ns DO31 TIOR Port Output Rise Time — 10 25 DO32 TIOF Port Output Fall Time — 10 25 ns DI35 TINP INTx Pin High or Low Time (input) 1 — — TCY DI40 TRBP CNx High or Low Time (input) 1 — — TCY Note 1: Conditions Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated.  2016-2019 Microchip Technology Inc. DS60001387D-page 299 PIC32MM0256GPM064 FAMILY TABLE 29-23: RESET AND BROWN-OUT RESET REQUIREMENTS AC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +125°C for Industrial Min Typ(1) Max Units Conditions SY10 TMCL MCLR Pulse Width (Low) 2 — — µs SY13 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset — 1 — µs Device running or in Idle SY25 TBOR Brown-out Reset Pulse Width 1 — — µs VDD VBOR SY45 TRST Internal State Reset Time — 25 — µs SY71 TPM Program Memory  Wake-up Time — 22 — µs Sleep wake-up with  VREGS = 0 — 3.8 — µs Sleep wake-up with  VREGS = 1 — 163 — µs Sleep wake-up with  VREGS = 0 — 23 — µs Sleep wake-up with  VREGS = 1 SY72 TLVR Note 1: Low-Voltage Regulator Wake-up Time Parameters are for design guidance and are not tested. DS60001387D-page 300  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY FIGURE 29-5: TIMER1 EXTERNAL CLOCK TIMING CHARACTERISTICS T1CK TA10 TA11 TA15 TA20 TMR1 Note: Refer to Figure 29-2 for load conditions. TABLE 29-24: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +125°C AC CHARACTERISTICS Param No. TA10 TA11 TA15 Symbol TTXH TTXL TTXP Characteristics(1) T1CK High Time T1CK Low Time Typ. Max. Units Conditions Synchronous, [(12.5 ns or 1 TPBCLK)/N] + 20 ns with Prescaler — — ns Must also meet Parameter TA15(2) Asynchronous, with Prescaler — — ns Synchronous, [(12.5 ns or 1 TPBCLK)/N] + 20 ns with Prescaler — — ns Asynchronous, with Prescaler 10 — — ns [(Greater of 20 ns or 2 TPBCLK)/N] + 30 ns — — ns VDD > 2.0V(2) [(Greater of 20 ns or 2 TPBCLK)/N] + 50 ns — — ns VDD < 2.0V(2) 20 — — ns VDD > 2.0V 50 — — ns VDD < 2.0V 1 TPBCLK T1CK Synchronous, Input Period with Prescaler Asynchronous, with Prescaler TA20 TCKEXTMRL Delay from External T1CK Clock Edge to Timer  Increment Note 1: 2: Min. 10 — Must also meet Parameter TA15(2) This parameter is characterized but not tested in manufacturing. N = Prescale Value (1, 8, 64, 256).  2016-2019 Microchip Technology Inc. DS60001387D-page 301 PIC32MM0256GPM064 FAMILY FIGURE 29-6: MCCP AND SCCP INPUT CAPTURE MODE TIMING CHARACTERISTICS ICMx IC10 IC11 IC15 Note: Refer to Figure 29-2 for load conditions. TABLE 29-25: MCCP AND SCCP INPUT CAPTURE MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +125°C AC CHARACTERISTICS Param Symbol No. Characteristics(1) Min. Max. Units Conditions IC10 TCCL ICMx Input Low Time [(12.5 ns or 1 TPBCLK)/N] + 25 ns — ns Must also meet  Parameter IC15 IC11 TCCH ICMx Input High Time [(12.5 ns or 1 TPBCLK)/N] + 25 ns — ns Must also meet  Parameter IC15 IC15 TCCP ICMx Input Period — ns Note 1: [(25 ns or 2 TPBCLK)/N] + 50 ns These parameters are characterized but not tested in manufacturing. FIGURE 29-7: MCCP AND SCCP OUTPUT COMPARE MODE TIMING CHARACTERISTICS OCMx OC11 OC10 Note: Refer to Figure 29-2 for load conditions. TABLE 29-26: MCCP AND SCCP OUTPUT COMPARE MODE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +125°C Characteristics(1) Min. Typical Max. Units Conditions OC10 TCCF OCMx Output Fall Time — — — ns See Parameter DO32 OC11 TCCR OCMx Output Rise Time — — — ns See Parameter DO31 Note 1: These parameters are characterized but not tested in manufacturing. DS60001387D-page 302  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY FIGURE 29-8: MCCP AND SCCP PWM MODE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCMx is Tri-Stated OCx Note: Refer to Figure 29-2 for load conditions. TABLE 29-27: MCCP AND SCCP PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. Characteristics(1) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +125°C Min Typical Max Units OC15 TFD Fault Input to PWM I/O Change — — 50 ns OC20 TFLT Fault Input Pulse Width 10 — — ns Note 1: Conditions These parameters are characterized but not tested in manufacturing.  2016-2019 Microchip Technology Inc. DS60001387D-page 303 PIC32MM0256GPM064 FAMILY FIGURE 29-9: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 SDOx MSb Bit 14 - - - - - -1 SP31 SDIx LSb SP30 MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure 29-2 for load conditions. TABLE 29-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V(unless otherwise stated) Operating temperature -40°C  TA  +125°C AC CHARACTERISTICS Param No. Symbol Characteristics(1) Min. Typical(2) Max. Units SP10 TSCL SCKx Output Low Time(3) TSCK/2 — — ns SP11 TSCH SCKx Output High Time(3) TSCK/2 — — ns Time(4) Conditions SP20 TSCF SCKx Output Fall — — — ns See Parameter DO32 SP21 TSCR SCKx Output Rise Time(4) — — — ns See Parameter DO31 SP30 TDOF SDOx Data Output  Fall Time(4) — — — ns See Parameter DO32 SP31 TDOR SDOx Data Output  Rise Time(4) — — — ns See Parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid TSCL2DOV after SCKx Edge — — 7 ns VDD > 2.0V — — 10 ns VDD < 2.0V SP40 TDIV2SCH, Setup Time of SDIx Data  TDIV2SCL Input to SCKx Edge 5 — — ns SP41 TSCH2DIL, Hold Time of SDIx Data  TSCL2DIL Input to SCKx Edge 5 — — ns Note 1: 2: 3: 4: These parameters are characterized but not tested in manufacturing. Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design  guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 10 pF load on all SPIx pins. DS60001387D-page 304  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY FIGURE 29-10: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP11 SP10 SCKx (CKP = 1) SP21 SP20 SP20 SP21 SP35 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SDIx Bit 14 - - - -1 MSb In SP40 LSb In SP41 Note: Refer to Figure 29-2 for load conditions. TABLE 29-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +125°C AC CHARACTERISTICS Param No. Characteristics(1) Min. Typ.(2) Max. Units TSCL SCKx Output Low Time(3) TSCK/2 — — ns SP11 TSCH SCKx Output High Time(3) TSCK/2 — — ns SP20 TSCF SCKx Output Fall Time(4) — — — ns See Parameter DO32 SP10 Symbol Time(4) Conditions SP21 TSCR SCKx Output Rise — — — ns See Parameter DO31 SP30 TDOF SDOx Data Output Fall Time(4) — — — ns See Parameter DO32 SP31 TDOR SDOx Data Output Rise Time(4) — — — ns See Parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid TSCL2DOV after SCKx Edge — — 7 ns VDD > 2.0V — — 10 ns VDD < 2.0V SP36 TDOV2SC, SDOx Data Output Setup TDOV2SCL to First SCKx Edge 7 — — ns SP40 TDIV2SCH, Setup Time of SDIx Data TDIV2SCL Input to SCKx Edge 7 — — ns VDD > 2.0V 10 — — ns VDD < 2.0V SP41 TSCH2DIL, Hold Time of SDIx Data TSCL2DIL Input to SCKx Edge 7 — — ns VDD > 2.0V 10 — — ns VDD < 2.0V Note 1: 2: 3: 4: These parameters are characterized but not tested in manufacturing. Data in the “Typ.” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 10 pF load on all SPIx pins.  2016-2019 Microchip Technology Inc. DS60001387D-page 305 PIC32MM0256GPM064 FAMILY FIGURE 29-11: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 SDOx MSb Bit 14 - - - - - -1 LSb SP51 SP30, SP31 SDIx MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 29-2 for load conditions. TABLE 29-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions:2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +125°C AC CHARACTERISTICS Param No. Characteristics(1) Symbol Min. Typ.(2) Max. Units ns Conditions SP70 TSCL SCKx Input Low Time(3) TSCK/2 — — SP71 TSCH SCKx Input High Time(3) TSCK/2 — — ns SP72 TSCF SCKx Input Fall Time — — — ns See Parameter DO32 SP73 TSCR SCKx Input Rise Time — — — ns See Parameter DO31 SP30 TDOF SDOx Data Output Fall Time(4) — — — ns See Parameter DO32 SP31 TDOR SDOx Data Output Rise Time(4) — — — ns See Parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid after  TSCL2DOV SCKx Edge — — 7 ns VDD > 2.0V — — 10 ns VDD < 2.0V SP40 TDIV2SCH, Setup Time of SDIx Data Input TDIV2SCL to SCKx Edge 5 — — ns SP41 TSCH2DIL, Hold Time of SDIx Data Input TSCL2DIL to SCKx Edge 5 — — ns SP50 TSSL2SCH, SSx  to SCKx  or SCKx Input TSSL2SCL 88 — — ns SP51 TSSH2DOZ SSx  to SDOx Output  High-Impedance(4) 2.5 — 12 ns SP52 TSCH2SSH SSx after SCKx Edge TSCL2SSH 10 — — ns Note 1: 2: 3: 4: These parameters are characterized but not tested in manufacturing. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Assumes 10 pF load on all SPIx pins. DS60001387D-page 306  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY FIGURE 29-12: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30, SP31 SDIx MSb In SP40 Bit 14 - - - -1 SP51 LSb In SP41 Note: Refer to Figure 29-2 for load conditions.  2016-2019 Microchip Technology Inc. DS60001387D-page 307 PIC32MM0256GPM064 FAMILY TABLE 29-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +125°C AC CHARACTERISTICS Param No. Characteristics(1) Symbol Min. Typical(2) Max. Units ns Conditions SP70 TSCL SCKx Input Low Time(3) TSCK/2 — — SP71 TSCH SCKx Input High Time(3) TSCK/2 — — ns SP72 TSCF SCKx Input Fall Time — — 10 ns SP73 TSCR SCKx Input Rise Time — — 10 ns SP30 TDOF SDOx Data Output Fall Time(4) — — — ns See Parameter DO32 SP31 TDOR SDOx Data Output Rise Time(4) — — — ns See Parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge — — 10 ns VDD > 2.0V — — 15 ns VDD < 2.0V SP40 TDIV2SCH, Setup Time of SDIx Data Input TDIV2SCL to SCKx Edge 0 — — ns SP41 TSCH2DIL, TSCL2DIL 7 — — ns SP50 TSSL2SCH, SSx  to SCKx  or  TSSL2SCL SCKx  Input 88 — — ns SP51 TSSH2DOZ SSx  to SDOx Output High-Impedance(4) 2.5 — 12 ns SP52 TSCH2SSH SSx  after SCKx Edge TSCL2SSH 10 — — ns SP60 TSSL2DOV — — 12.5 ns Note 1: 2: 3: 4: Hold Time of SDIx Data Input to SCKx Edge SDOx Data Output Valid after SSx Edge These parameters are characterized but not tested in manufacturing. Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Assumes 10 pF load on all SPIx pins. DS60001387D-page 308  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY FIGURE 29-13: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 Start Condition Stop Condition SDAx Note: Refer to Figure 29-2 for load conditions. FIGURE 29-14: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 29-2 for load conditions.  2016-2019 Microchip Technology Inc. DS60001387D-page 309 PIC32MM0256GPM064 FAMILY TABLE 29-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +125°C AC CHARACTERISTICS Param No. IM10 Sym Min.(1) Characteristics Max. Units TLO:SCL Clock Low Time 100 kHz mode TSYSCLK * (BRG + 2) — µs 400 kHz mode TSYSCLK * (BRG + 2) — µs TSYSCLK * (BRG + 2) — µs THI:SCL Clock High Time 100 kHz mode TSYSCLK * (BRG + 2) — µs 400 kHz mode TSYSCLK * (BRG + 2) — µs 1 MHz mode(2) TSYSCLK * (BRG + 2) — µs (2) 1 MHz mode IM11 IM20 IM21 IM25 IM26 IM30 IM31 IM33 IM34 IM40 IM45 TF:SCL TR:SCL SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode — 300 ns 20 + 0.1 CB 300 ns 1 MHz mode(2) — 100 ns SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode — 1000 ns TSU:DAT Data Input Setup Time THD:DA Data Input T Hold Time 20 + 0.1 CB 300 ns 1 MHz mode(2) — 300 ns 100 kHz mode 250 — ns 400 kHz mode 100 — ns 1 MHz mode(2) 100 — ns 100 kHz mode 0 — µs 400 kHz mode 0 0.9 µs 1 MHz mode(2) 0 0.3 µs TPBCLK * (BRG + 2) — µs TPBCLK * (BRG + 2) — µs 1 MHz mode(2) TPBCLK * (BRG + 2) TSU:STA Start Condition 100 kHz mode Setup Time 400 kHz mode — µs TPBCLK * (BRG + 2) — µs TPBCLK * (BRG + 2) — µs 1 MHz mode(2) TPBCLK * (BRG + 2) — µs THD:STA Start Condition 100 kHz mode Hold Time 400 kHz mode TSU:STO Stop Condition 100 kHz mode Setup Time 400 kHz mode TPBCLK * (BRG + 2) — µs TPBCLK * (BRG + 2) — µs 1 MHz mode(2) TPBCLK * (BRG + 2) — µs THD:ST Stop Condition 100 kHz mode O Hold Time 400 kHz mode TPBCLK * (BRG + 2) — ns TPBCLK * (BRG + 2) — ns 1 MHz mode(2) TPBCLK * (BRG + 2) — ns TAA:SCL Output Valid from Clock 100 kHz mode — 3500 ns 400 kHz mode — 1000 ns 1 MHz mode(2) — 350 ns TBF:SDA Bus Free Time 100 kHz mode 4.7 — µs 400 kHz mode 1.3 — µs 1 MHz mode(2) 0.5 — µs Conditions CB is specified to be from  10 to 400 pF CB is specified to be from  10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated The amount of time the bus must be free before a new transmission can start IM50 CB Bus Capacitive Loading — — pF See Parameter DO58 IM51 TPGD Pulse Gobbler Delay 52 312 ns (Note 3) Note 1: 2: 3: I2 BRG is the value of the C Baud Rate Generator. Maximum Pin Capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). The typical value for this parameter is 104 ns. DS60001387D-page 310  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY FIGURE 29-15: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Start Condition Stop Condition Note: Refer to Figure 29-2 for load conditions. FIGURE 29-16: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure 29-2 for load conditions.  2016-2019 Microchip Technology Inc. DS60001387D-page 311 PIC32MM0256GPM064 FAMILY TABLE 29-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +125°C AC CHARACTERISTICS Param No. IS10 IS11 IS20 IS21 IS25 Sym Characteristics TLO:SCL Clock Low Time THI:SCL TF:SCL TR:SCL Clock High Time Min. Max. Units Conditions 100 kHz mode 4.7 — µs PBCLK must operate at a minimum of 800 kHz 400 kHz mode 1.3 — µs PBCLK must operate at a minimum of 3.2 MHz 1 MHz mode(1) 0.5 — µs 100 kHz mode 4.0 — µs PBCLK must operate at a minimum of 800 kHz 400 kHz mode 0.6 — µs PBCLK must operate at a minimum of 3.2 MHz 1 MHz mode(1) 0.5 — µs SDAx and SCLx Fall  Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) — 100 ns SDAx and SCLx Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) — 300 ns 100 kHz mode 250 — ns 400 kHz mode 100 — ns (1) 100 — ns 0 — ns TSU:DAT Data Input Setup Time 1 MHz mode IS26 IS30 IS31 IS33 THD:DAT Data Input Hold Time 100 kHz mode 400 kHz mode 0 0.9 µs 1 MHz mode(1) 0 0.3 µs 4700 — ns 600 — ns TSU:STA Start Condition 100 kHz mode Setup Time 400 kHz mode 1 MHz mode(1) 250 — ns THD:STA Start Condition 100 kHz mode Hold Time 400 kHz mode 4000 — ns 600 — ns 1 MHz mode(1) 250 — ns TSU:STO Stop Condition 100 kHz mode Setup Time 400 kHz mode 4000 — ns 600 — ns (1) 600 — ns THD:STO Stop Condition 100 kHz mode Hold Time 400 kHz mode 4000 — ns 600 — ns 1 MHz mode(1) 250 — ns 100 kHz mode 0 3500 ns 400 kHz mode 0 1000 ns 0 350 ns 4.7 — µs 1 MHz mode IS34 IS40 TAA:SCL Output Valid from Clock (1) 1 MHz mode IS45 IS50 TBF:SDA Bus Free Time 100 kHz mode CB Note 1: 400 kHz mode 1.3 — µs 1 MHz mode(1) 0.5 — µs — — pF Bus Capacitive Loading CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated The amount of time the bus must be free before a new transmission can start See Parameter DO58 Maximum Pin Capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). DS60001387D-page 312  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY TABLE 29-34: ADC MODULE INPUTS SPECIFICATIONS Operating Conditions: 2.0V  VDD  3.6V, -40°C  TA  +125°C (unless otherwise stated) Param No. Symbol Characteristic Min Max Units Reference Inputs AD05 VREFH Reference Voltage High AVSS + 1.7 AVDD V AD06 VREFL Reference Voltage Low AVSS AVDD – 1.7 V AD07 VREF Absolute Reference Voltage AVSS – 0.3 AVDD + 0.3 V AD10 VINH-VINL Full-Scale Input Span VREFL VREFH V AD11 VIN Absolute Input Voltage AVSS – 0.3 AVDD + 0.3 V AD12 VINL Absolute VINL Input Voltage AVSS – 0.3 AVDD + 0.3 V AD17 RIN Recommended Impedance of Analog Voltage Source — 2.5K  Analog Inputs TABLE 29-35: ADC ACCURACY AND CONVERSION TIMING REQUIREMENTS FOR 12-BIT MODE(1) Operating Conditions: VDD = 3.3V, AVSS = VREFL = 0V, AVDD = VREFH = 3.3V, -40°C  TA  +125°C Param No. Symbol Characteristic Min Typ(2) Max Units — 12 — bits ADC Accuracy AD20B Nr Resolution AD21B INL Integral Nonlinearity AD21D AD22B DNL — ±2.5 ±3.5 LSb -3.5 — ±3.5 LSb — ±0.75 +1.75/-0.95 LSb +1.75 LSb Differential Nonlinearity AD22D -0.95 AD23B GERR Gain Error – +2 +3 LSb AD24B EOFF Offset Error — +1 +2 LSb AD50B TAD ADC Clock Period 280 — — ns 12-Bit Mode 300 2 — 3 TAD Clock Parameters AD50D AD61B tPSS Sample Start Delay from Setting Sample bit (SAMP) AD55B tCONV Conversion Time — 14 — TAD AD56B FCNV Throughput Rate — — 200 ksps Conversion Rate AD56D Note 1: 2: Measurements are taken with the external VREF+ and VREF- used as the ADC voltage reference. Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2016-2019 Microchip Technology Inc. DS60001387D-page 313 PIC32MM0256GPM064 FAMILY TABLE 29-36: ADC ACCURACY AND CONVERSION TIMING REQUIREMENTS FOR 10-BIT MODE(1) Operating Conditions: VDD = 3.3V, AVSS = VREFL = 0V, AVDD = VREFH = 3.3V, -40°C  TA  +125°C Param No. Symbol Characteristic Min Typ(2) Max Units ADC Accuracy AD20A Nr Resolution — 10 — bits AD21A INL Integral Nonlinearity — ±0.5 — LSb AD22A DNL Differential Nonlinearity — ±0.5 — LSb AD23A GERR Gain Error — +0.75 — LSb AD24A EOFF Offset Error — +0.25 — LSb AD50A TAD ADC Clock Period 200 — — ns AD61A tPSS Sample Start Delay from Setting Sample bit (SAMP) 2 — 3 TAD AD55A tCONV Conversion Time — 12 — TAD AD56A FCNV Throughput Rate — — 300 ksps Note 1: 2: Measurements are taken with the external VREF+ and VREF- used as the ADC voltage reference. Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Clock Parameters Conversion Rate DS60001387D-page 314  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY FIGURE 29-17: EJTAG TIMING CHARACTERISTICS TTCKcyc TTCKhigh TTCKlow Trf TCK Trf TMS TDI TTsetup TThold Trf Trf TDO TRST* TTRST*low TTDOout TTDOzstate Defined Trf Undefined TABLE 29-37: EJTAG TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +125°C AC CHARACTERISTICS Param No. Symbol Description(1) Min. Max. Units EJ1 TTCKCYC TCK Cycle Time 25 — ns EJ2 TTCKHIGH TCK High Time 10 — ns EJ3 TTCKLOW TCK Low Time 10 — ns EJ4 TTSETUP TAP Signals Setup Time before Rising TCK 5 — ns EJ5 TTHOLD TAP Signals Hold Time after Rising TCK 3 — ns EJ6 TTDOOUT TDO Output Delay Time from Falling TCK — 5 ns EJ7 TTDOZSTATE TDO 3-State Delay Time from Falling TCK — 5 ns EJ8 TTRSTLOW TRST Low Time 25 — ns EJ9 TRF TAP Signals Rise/Fall Time, All Input and Output — — ns Note 1: Conditions These parameters are characterized but not tested in manufacturing.  2016-2019 Microchip Technology Inc. DS60001387D-page 315 PIC32MM0256GPM064 FAMILY TABLE 29-38: USB OTG ELECTRICAL SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +125°C for Industrial AC CHARACTERISTICS Param. Symbol No. Characteristics(1) USB313 VUSB3V3 USB Voltage Min. Typical Max. Units Conditions 3.0 — 3.6 V Voltage on VUSB3V3 must be in this range for proper USB operation USB315 VILUSB Input Low Voltage for USB Buffer — — 0.8 V USB316 VIHUSB Input High Voltage for USB Buffer 2.0 — — V USB318 VDIFS Differential Input Sensitivity — — 0.2 V USB319 VCM Differential Common-Mode Range 0.8 — 2.5 V The difference between D+ and D- must exceed this value while VCM is met USB320 ZOUT Driver Output Impedance 28.0 — 44.0  USB321 VOL Voltage Output Low 0.0 — 0.3 V 14.25 k load connected to 3.6V USB322 VOH Voltage Output High 2.8 — 3.6 V 14.25 k load connected to ground Note 1: These parameters are characterized but not tested in manufacturing. DS60001387D-page 316  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 30.0 PACKAGING INFORMATION 30.1 Package Marking Information 28-Lead SSOP (5.30 mm) XXXXXXXXXXXX XXXXXXXXXXXX Example PIC32MM0064 GPM028 YYWWNNN 1610017 28-Lead QFN (6x6 mm) XXXXXXXX XXXXXXXX YYWWNNN 32MM0064 GPM028 1610017 28-Lead UQFN (4x4x0.6 mm) XXXXXXXX XXXXXXXX YYWWNNN Legend: XX...X YY WW NNN * Note: Example 32MM0064 GPM028 1610017 36-Lead VQFN (6x6x1.0 mm) XXXXXXXX XXXXXXXX YYWWNNN Example Example 32MM0064 GPM036 1610017 Customer-specific information Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code  All packages are Pb-free In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2016-2019 Microchip Technology Inc. DS60001387D-page 317 PIC32MM0256GPM064 FAMILY 30.1 Package Marking Information (Continued) 40-Lead UQFN (5x5x0.5 mm) XXXXXXX XXXXXXX XXXXXXX YYWWNNN 48-Lead UQFN (6x6 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 48-Lead TQFP (7x7x1.0 mm) 1 XXXXXXX XXXYYWW NNN 64-Lead QFN (9x9x0.9 mm) XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 64-Lead TQFP (10x10x1 mm) XXXXXXXXX XXXXXXXXX XXXXXXXXX YYWWNNN DS60001387D-page 318 Example 32MM 0064 GPM036 1610017 Example 32MM0064 GPM048 1610017 Example 0128GPM 0481610 017 Example PIC32MM0064 GPM064 1650017 Example PIC32MM 0064GPM064 1620017  2016-2019 Microchip Technology Inc. PIC32MM0256GPM064 FAMILY 30.2 Package Details The following sections give the technical details of the packages. /HDG3ODVWLF6KULQN6PDOO2XWOLQH66PP%RG\>6623@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ ' $ % 1 '$780$ '$780% ( (   ;E  H & $ % 7239,(: $ $ & $ $ 6($7,1* 3/$1( ;  & 6,'(9,(: $ + F / / 9,(:$$ 0LFURFKLS7HFKQRORJ\'UDZLQJ&5HY&6KHHWRI  2016-2019 Microchip Technology Inc. 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