PIC32MX1XX/2XX 28/36/44-PIN
32-bit Microcontrollers (up to 256 KB Flash and 64 KB SRAM) with
Audio and Graphics Interfaces, USB, and Advanced Analog
Operating Conditions
- Programmable references with 32 voltage points
• 2.3V to 3.6V, -40ºC to +105ºC, DC to 40 MHz
• 2.3V to 3.6V, -40ºC to +85ºC, DC to 50 MHz
Timers/Output Compare/Input Capture
Core: 50 MHz/83 DMIPS MIPS32® M4K®
• MIPS16e® mode for up to 40% smaller code size
• Code-efficient (C and Assembly) architecture
• Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply
Clock Management
•
•
•
•
•
Communication Interfaces
0.9% internal oscillator
Programmable PLLs and oscillator clock sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer
Fast wake-up and start-up
• USB 2.0-compliant Full-speed OTG controller
• Two UART modules (12.5 Mbps):
- Supports LIN 2.0 protocols and IrDA® support
• Two 4-wire SPI modules (25 Mbps)
• Two I2C modules (up to 1 Mbaud) with SMBus support
• PPS to allow function remap
• Parallel Master Port (PMP)
Power Management
•
•
•
•
• Five General Purpose Timers:
- Five 16-bit and up to two 32-bit Timers/Counters
• Five Output Compare (OC) modules
• Five Input Capture (IC) modules
• Peripheral Pin Select (PPS) to allow function remap
• Real-Time Clock and Calendar (RTCC) module
Low-power management modes (Sleep and Idle)
Integrated Power-on Reset and Brown-out Reset
0.5 mA/MHz dynamic current (typical)
44 μA IPD current (typical)
Direct Memory Access (DMA)
• Four channels of hardware DMA with automatic data
size detection
• Two additional channels dedicated for USB
• Programmable Cyclic Redundancy Check (CRC)
Audio Interface Features
• Data communication: I2S, LJ, RJ, and DSP modes
• Control interface: SPI and I2C
• Master clock:
- Generation of fractional clock frequencies
- Can be synchronized with USB clock
- Can be tuned in run-time
Input/Output
• 10 mA source/sink on all I/O pins and up to 14 mA on
non-standard VOH
• 5V-tolerant pins
• Selectable open drain, pull-ups, and pull-downs
• External interrupts on all I/O pins
Advanced Analog Features
• ADC Module:
- 10-bit 1.1 Msps rate with one S&H
- Up to 10 analog inputs on 28-pin devices and 13
analog inputs on 44-pin devices
• Flexible and independent ADC trigger sources
• Charge Time Measurement Unit (CTMU):
- Supports mTouch™ capacitive touch sensing
- Provides high-resolution time measurement (1 ns)
- On-chip temperature measurement capability
• Comparators:
- Up to three Analog Comparator modules
Class B Support
• Class B Safety Library, IEC 60730
Debugger Development Support
•
•
•
•
In-circuit and in-application programming
4-wire MIPS® Enhanced JTAG interface
Unlimited program and six complex data breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Packages
Type
SOIC
SSOP
SPDIP
Pin Count
28
28
28
28
44
36
44
I/O Pins (up to)
21
21
21
21
34
25
34
34
Contact/Lead Pitch
1.27
0.65
0.100''
0.65
0.65
0.50
0.50
0.80
Dimensions
17.90x7.50x2.65
10.2x5.3x2
1.365''x.285''x.135''
6x6x0.9
8x8x0.9
5x5x0.9
6x6x0.9
10x10x1
Note:
QFN
VTLA
TQFP
44
All dimensions are in millimeters (mm) unless specified.
2011-2019 Microchip Technology Inc.
DS60001168L-page 1
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
Packages
2
5
3
N
2
Y
4/0
Y
10
Y
21
Y
PIC32MX110F016C
36
16+3
4
24
5/5/5
2
2
5
3
N
2
Y
4/0
Y
12
Y
25
Y
VTLA
Pins
I/O Pins
2
RTCC
5/5/5
CTMU
20
PMP
4
I2C
16+3
SPI/I2S
28
UART
PIC32MX110F016B
SOIC,
SSOP,
SPDIP,
QFN
Device
JTAG
USB On-The-Go (OTG)
Analog Comparators
External Interrupts(3)
Timers(2)/Capture/Compare
Remappable Pins
Data Memory (KB)
Program Memory (KB)(1)
Remappable Peripherals
10-bit 1 Msps ADC (Channels)
PIC32MX1XX 28/36/44-PIN GENERAL PURPOSE FAMILY FEATURES
DMA Channels
(Programmable/Dedicated)
TABLE 1:
PIC32MX110F016D
44
16+3
4
32
5/5/5
2
2
5
3
N
2
Y
4/0
Y
13
Y
35
Y
VTLA,
TQFP,
QFN
PIC32MX120F032B
28
32+3
8
20
5/5/5
2
2
5
3
N
2
Y
4/0
Y
10
Y
21
Y
SOIC,
SSOP,
SPDIP,
QFN
PIC32MX120F032C
36
32+3
8
24
5/5/5
2
2
5
3
N
2
Y
4/0
Y
12
Y
25
Y
VTLA
PIC32MX120F032D
44
32+3
8
32
5/5/5
2
2
5
3
N
2
Y
4/0
Y
13
Y
35
Y
VTLA,
TQFP,
QFN
PIC32MX130F064B
28
64+3
16
20
5/5/5
2
2
5
3
N
2
Y
4/0
Y
10
Y
21
Y
SOIC,
SSOP,
SPDIP,
QFN
PIC32MX130F064C
36
64+3
16
24
5/5/5
2
2
5
3
N
2
Y
4/0
Y
12
Y
25
Y
VTLA
Y
VTLA,
TQFP,
QFN
SOIC,
SSOP,
SPDIP,
QFN
PIC32MX130F064D
44
64+3
16
32
5/5/5
2
2
5
3
N
2
Y
4/0
Y
13
Y
35
PIC32MX150F128B
28
128+3
32
20
5/5/5
2
2
5
3
N
2
Y
4/0
Y
10
Y
21
Y
PIC32MX150F128C
36
128+3
32
24
5/5/5
2
2
5
3
N
2
Y
4/0
Y
12
Y
25
Y
VTLA
PIC32MX150F128D
44
128+3
32
32
5/5/5
2
2
5
3
N
2
Y
4/0
Y
13
Y
35
Y
VTLA,
TQFP,
QFN
PIC32MX130F256B
28
256+3
16
20
5/5/5
2
2
5
3
N
2
Y
4/0
Y
10
Y
21
Y
SSOP,
SPDIP,
QFN
PIC32MX130F256D
44
256+3
16
32
5/5/5
2
2
5
3
N
2
Y
4/0
Y
13
Y
35
Y
VTLA,
TQFP,
QFN
PIC32MX170F256B
28
256+3
64
20
5/5/5
2
2
5
3
N
2
Y
4/0
Y
10
Y
21
Y
SOIC,
SSOP,
SPDIP,
QFN
PIC32MX170F256D
44
256+3
64
32
5/5/5
2
2
5
3
N
2
Y
4/0
Y
13
Y
35
Y
VTLA,
TQFP,
QFN
Note 1:
2:
3:
This device features 3 KB of boot Flash memory.
Four out of five timers are remappable.
Four out of five external interrupts are remappable.
DS60001168L-page 2
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
PIC32MX2XX 28/36/44-PIN USB FAMILY FEATURES
Program Memory (KB)(1)
Data Memory (KB)
Remappable Pins
Timers(2)/Capture/Compare
UART
SPI/I2S
External Interrupts(3)
Analog Comparators
USB On-The-Go (OTG)
I2C
PMP
DMA Channels
(Programmable/Dedicated)
CTMU
10-bit 1 Msps ADC (Channels)
RTCC
I/O Pins
JTAG
PIC32MX210F016B
28
16+3
4
19
5/5/5
2
2
5
3
Y
2
Y
4/2
Y
9
Y
19
Y
PIC32MX210F016C
36
16+3
4
23
5/5/5
2
2
5
3
Y
2
Y
4/2
Y
12
Y
25
Y
PIC32MX210F016D
44
16+3
4
31
5/5/5
2
2
5
3
Y
2
Y
4/2
Y
13
Y
33
Y
PIC32MX220F032B
28
32+3
8
19
5/5/5
2
2
5
3
Y
2
Y
4/2
Y
9
Y
19
Y
PIC32MX220F032C
36
32+3
8
23
5/5/5
2
2
5
3
Y
2
Y
4/2
Y
12
Y
23
Y
PIC32MX220F032D
44
32+3
8
31
5/5/5
2
2
5
3
Y
2
Y
4/2
Y
13
Y
33
Y
PIC32MX230F064B
28
64+3
16
19
5/5/5
2
2
5
3
Y
2
Y
4/2
Y
9
Y
19
Y
PIC32MX230F064C
36
64+3
16
23
5/5/5
2
2
5
3
Y
2
Y
4/2
Y
12
Y
23
Y
PIC32MX230F064D
44
64+3
16
31
5/5/5
2
2
5
3
Y
2
Y
4/2
Y
13
Y
33
Y
PIC32MX250F128B
28
128+3
32
19
5/5/5
2
2
5
3
Y
2
Y
4/2
Y
9
Y
19
Y
PIC32MX250F128C
36
128+3
32
23
5/5/5
2
2
5
3
Y
2
Y
4/2
Y
12
Y
23
Y
PIC32MX250F128D
44
128+3
32
31
5/5/5
2
2
5
3
Y
2
Y
4/2
Y
13
Y
33
Y
PIC32MX230F256B
28
256+3
16
19
5/5/5
2
2
5
3
Y
2
Y
4/2
Y
9
Y
19
Y
PIC32MX230F256D
44
256+3
16
31
5/5/5
2
2
5
3
Y
2
Y
4/2
Y
13
Y
33
Y
PIC32MX270F256B
28
256+3
64
19
5/5/5
2
2
5
3
Y
2
Y
4/2
Y
9
Y
19
Y
PIC32MX270F256D
44
256+3
64
31
5/5/5
2
2
5
3
Y
2
Y
4/2
Y
13
Y
33
Y
Device
Pins
Remappable Peripherals
Note 1:
2:
3:
Packages
TABLE 2:
SOIC,
SSOP,
SPDIP,
QFN
VTLA
VTLA,
TQFP,
QFN
SOIC,
SSOP,
SPDIP,
QFN
VTLA
VTLA,
TQFP,
QFN
SOIC,
SSOP,
SPDIP,
QFN
VTLA
VTLA,
TQFP,
QFN
SOIC,
SSOP,
SPDIP,
QFN
VTLA
VTLA,
TQFP,
QFN
SSOP,
SPDIP,
QFN
VTLA,
TQFP,
QFN
SOIC,
SSOP,
SPDIP,
QFN
VTLA,
TQFP,
QFN
This device features 3 KB of boot Flash memory.
Four out of five timers are remappable.
Four out of five external interrupts are remappable.
2011-2019 Microchip Technology Inc.
DS60001168L-page 3
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
Pin Diagrams
TABLE 3:
PIN NAMES FOR 28-PIN GENERAL PURPOSE DEVICES
28-PIN SOIC, SPDIP, SSOP (TOP VIEW)(1,2,3)
1
1
28
SSOP
28
1
SOIC
28
SPDIP
PIC32MX110F016B
PIC32MX120F032B
PIC32MX130F064B
PIC32MX130F256B
PIC32MX150F128B
PIC32MX170F256B
Pin #
1
2
Full Pin Name
Pin #
Full Pin Name
MCLR
15
PGEC3/RPB6/PMD6/RB6
VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0
16
TDI/RPB7/CTED3/PMD5/INT0/RB7
3
VREF-/CVREF-/AN1/RPA1/CTED2/RA1
17
TCK/RPB8/SCL1/CTED10/PMD4/RB8
4
PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
18
TDO/RPB9/SDA1/CTED4/PMD3/RB9
5
PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
19
VSS
6
AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
20
VCAP
7
AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
21
PGED2/RPB10/CTED11/PMD2/RB10
8
VSS
22
PGEC2/TMS/RPB11/PMD1/RB11
9
OSC1/CLKI/RPA2/RA2
23
AN12/PMD0/RB12
10
OSC2/CLKO/RPA3/PMA0/RA3
24
AN11/RPB13/CTPLS/PMRD/RB13
11
SOSCI/RPB4/RB4
25
CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
12
SOSCO/RPA4/T1CK/CTED9/PMA1/RA4
26
AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
13
VDD
27
AVSS
28
AVDD
14
Note
PGED3/RPB5/PMD7/RB5
1:
2:
3:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
DS60001168L-page 4
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 4:
PIN NAMES FOR 28-PIN USB DEVICES
28-PIN SOIC, SPDIP, SSOP (TOP VIEW)(1,2,3)
1
1
28
SSOP
28
1
SOIC
28
SPDIP
PIC32MX210F016B
PIC32MX220F032B
PIC32MX230F064B
PIC32MX230F256B
PIC32MX250F128B
PIC32MX270F256B
Pin #
Full Pin Name
Pin #
Full Pin Name
1
MCLR
15
VBUS
2
PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0
16
TDI/RPB7/CTED3/PMD5/INT0/RB7
3
PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1
17
TCK/RPB8/SCL1/CTED10/PMD4/RB8
4
PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0
18
TDO/RPB9/SDA1/CTED4/PMD3/RB9
5
PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1
19
VSS
6
AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2
20
VCAP
7
AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3
21
PGED2/RPB10/D+/CTED11/RB10
8
VSS
22
PGEC2/RPB11/D-/RB11
9
OSC1/CLKI/RPA2/RA2
23
VUSB3V3
10
OSC2/CLKO/RPA3/PMA0/RA3
24
AN11/RPB13/CTPLS/PMRD/RB13
11
SOSCI/RPB4/RB4
25
CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14
12
AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
SOSCO/RPA4/T1CK/CTED9/PMA1/RA4
26
13
VDD
27
AVSS
14
TMS/RPB5/USBID/RB5
28
AVDD
Note
1:
2:
3:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
2011-2019 Microchip Technology Inc.
DS60001168L-page 5
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 5:
PIN NAMES FOR 28-PIN GENERAL PURPOSE DEVICES
28-PIN QFN (TOP VIEW)(1,2,3.4)
PIC32MX110F016B
PIC32MX120F032B
PIC32MX130F064B
PIC32MX130F256B
PIC32MX150F128B
PIC32MX170F256B
Pin #
Full Pin Name
28
1
Pin #
Full Pin Name
1
PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
15
TDO/RPB9/SDA1/CTED4/PMD3/RB9
2
PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
16
VSS
3
AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
17
VCAP
4
AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
18
PGED2/RPB10/CTED11/PMD2/RB10
5
VSS
19
PGEC2/TMS/RPB11/PMD1/RB11
6
OSC1/CLKI/RPA2/RA2
20
AN12/PMD0/RB12
7
OSC2/CLKO/RPA3/PMA0/RA3
21
AN11/RPB13/CTPLS/PMRD/RB13
8
SOSCI/RPB4/RB4
22
CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
9
SOSCO/RPA4/T1CK/CTED9/PMA1/RA4
23
AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
10
VDD
24
AVSS
11
PGED3/RPB5/PMD7/RB5
25
AVDD
12
PGEC3/RPB6/PMD6/RB6
26
MCLR
13
TDI/RPB7/CTED3/PMD5/INT0/RB7
27
VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0
14
TCK/RPB8/SCL1/CTED10/PMD4/RB8
28
VREF-/CVREF-/AN1/RPA1/CTED2/RA1
Note
1:
2:
3:
4:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
Shaded pins are 5V tolerant.
DS60001168L-page 6
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 6:
PIN NAMES FOR 28-PIN USB DEVICES
28-PIN QFN (TOP VIEW)(1,2,3,4)
PIC32MX210F016B
PIC32MX220F032B
PIC32MX230F064B
PIC32MX230F256B
PIC32MX250F128B
PIC32MX270F256B
Pin #
Full Pin Name
28
1
Pin #
Full Pin Name
1
PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0
15
TDO/RPB9/SDA1/CTED4/PMD3/RB9
2
PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1
16
VSS
3
AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2
17
VCAP
4
AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3
18
PGED2/RPB10/D+/CTED11/RB10
5
VSS
19
PGEC2/RPB11/D-/RB11
6
OSC1/CLKI/RPA2/RA2
20
VUSB3V3
7
OSC2/CLKO/RPA3/PMA0/RA3
21
AN11/RPB13/CTPLS/PMRD/RB13
8
SOSCI/RPB4/RB4
22
CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14
9
SOSCO/RPA4/T1CK/CTED9/PMA1/RA4
23
AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
10
VDD
24
AVSS
11
TMS/RPB5/USBID/RB5
25
AVDD
12
VBUS
26
MCLR
13
TDI/RPB7/CTED3/PMD5/INT0/RB7
27
PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0
14
TCK/RPB8/SCL1/CTED10/PMD4/RB8
28
PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1
Note
1:
2:
3:
4:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
Shaded pins are 5V tolerant.
2011-2019 Microchip Technology Inc.
DS60001168L-page 7
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 7:
PIN NAMES FOR 36-PIN GENERAL PURPOSE DEVICES
36-PIN VTLA (BOTTOM VIEW)(1,2,3,5)
PIC32MX110F016C
PIC32MX120F032C
PIC32MX130F064C
PIC32MX150F128C
1
36
Pin #
Full Pin Name
Pin #
Full Pin Name
1
AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
19
2
AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
20
RPC9/CTED7/RC9
3
PGED4(4)/AN6/RPC0/RC0
21
VSS
4
PGEC4(4)/AN7/RPC1/RC1
22
VCAP
5
VDD
23
VDD
6
VSS
24
PGED2/RPB10/CTED11/PMD2/RB10
7
OSC1/CLKI/RPA2/RA2
25
PGEC2/TMS/RPB11/PMD1/RB11
8
OSC2/CLKO/RPA3/PMA0/RA3
26
AN12/PMD0/RB12
TDO/RPB9/SDA1/CTED4/PMD3/RB9
9
SOSCI/RPB4/RB4
27
AN11/RPB13/CTPLS/PMRD/RB13
10
SOSCO/RPA4/T1CK/CTED9/PMA1/RA4
28
CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
11
RPC3/RC3
29
AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
12
VSS
30
AVSS
13
VDD
31
AVDD
14
VDD
32
MCLR
15
PGED3/RPB5/PMD7/RB5
33
VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0
16
PGEC3/RPB6/PMD6/RB6
34
VREF-/CVREF-/AN1/RPA1/CTED2/RA1
17
TDI/RPB7/CTED3/PMD5/INT0/RB7
35
PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
18
TCK/RPB8/SCL1/CTED10/PMD4/RB8
36
PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
Note
1:
2:
3:
4:
5:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
This pin function is not available on PIC32MX110F016C and PIC32MX120F032C devices.
Shaded pins are 5V tolerant.
DS60001168L-page 8
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 8:
PIN NAMES FOR 36-PIN USB DEVICES
36-PIN VTLA (BOTTOM VIEW)(1,2,3,5)
PIC32MX210F016C
PIC32MX220F032C
PIC32MX230F064C
PIC32MX250F128C
1
36
Pin #
Full Pin Name
Pin #
Full Pin Name
1
AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2
19
2
AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3
20
RPC9/CTED7/RC9
3
PGED4(4)/AN6/RPC0/RC0
21
VSS
4
PGEC4(4)/AN7/RPC1/RC1
22
VCAP
5
VDD
23
VDD
6
VSS
24
PGED2/RPB10/D+/CTED11/RB10
7
OSC1/CLKI/RPA2/RA2
25
PGEC2/RPB11/D-/RB11
8
OSC2/CLKO/RPA3/PMA0/RA3
26
VUSB3V3
TDO/RPB9/SDA1/CTED4/PMD3/RB9
9
SOSCI/RPB4/RB4
27
AN11/RPB13/CTPLS/PMRD/RB13
10
SOSCO/RPA4/T1CK/CTED9/PMA1/RA4
28
CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14
11
AN12/RPC3/RC3
29
AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
12
VSS
30
AVSS
13
VDD
31
AVDD
14
VDD
32
MCLR
15
TMS/RPB5/USBID/RB5
33
PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0
16
VBUS
34
PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1
17
TDI/RPB7/CTED3/PMD5/INT0/RB7
35
PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0
18
TCK/RPB8/SCL1/CTED10/PMD4/RB8
36
PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1
Note
1:
2:
3:
4:
5:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
This pin function is not available on PIC32MX210F016C and PIC32MX120F032C devices.
Shaded pins are 5V tolerant.
2011-2019 Microchip Technology Inc.
DS60001168L-page 9
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 9:
PIN NAMES FOR 44-PIN GENERAL PURPOSE DEVICES
44-PIN QFN (TOP VIEW)(1,2,3,5)
PIC32MX110F016D
PIC32MX120F032D
PIC32MX130F064D
PIC32MX130F256D
PIC32MX150F128D
PIC32MX170F256D
44
Pin #
Full Pin Name
1
Pin #
Full Pin Name
1
RPB9/SDA1/CTED4/PMD3/RB9
23
AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
2
RPC6/PMA1/RC6
24
AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
3
RPC7/PMA0/RC7
25
AN6/RPC0/RC0
4
RPC8/PMA5/RC8
26
AN7/RPC1/RC1
5
RPC9/CTED7/PMA6/RC9
27
AN8/RPC2/PMA2/RC2
6
VSS
28
VDD
7
VCAP
29
VSS
8
PGED2/RPB10/CTED11/PMD2/RB10
30
OSC1/CLKI/RPA2/RA2
OSC2/CLKO/RPA3/RA3
9
PGEC2/RPB11/PMD1/RB11
31
10
AN12/PMD0/RB12
32
TDO/RPA8/PMA8/RA8
11
AN11/RPB13/CTPLS/PMRD/RB13
33
SOSCI/RPB4/RB4
12
PGED4(4)/TMS/PMA10/RA10
34
SOSCO/RPA4/T1CK/CTED9/RA4
13
PGEC4(4)
35
TDI/RPA9/PMA9/RA9
14
CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
36
RPC3/RC3
15
AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
37
RPC4/PMA4/RC4
16
AVSS
38
RPC5/PMA3/RC5
17
AVDD
39
VSS
18
MCLR
40
VDD
19
VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0
41
PGED3/RPB5/PMD7/RB5
20
VREF-/CVREF-/AN1/RPA1/CTED2/RA1
42
PGEC3/RPB6/PMD6/RB6
21
PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
43
RPB7/CTED3/PMD5/INT0/RB7
22
PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
44
RPB8/SCL1/CTED10/PMD4/RB8
Note
/TCK/CTED8/PMA7/RA7
1:
2:
3:
4:
5:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
This pin function is not available on PIC32MX110F016D and PIC32MX120F032D devices.
Shaded pins are 5V tolerant.
DS60001168L-page 10
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 10:
PIN NAMES FOR 44-PIN USB DEVICES
44-PIN QFN (TOP VIEW)(1,2,3,5)
PIC32MX210F016D
PIC32MX220F032D
PIC32MX230F064D
PIC32MX230F256D
PIC32MX250F128D
PIC32MX270F256D
44
Pin #
1
2
Full Pin Name
Pin #
1
Full Pin Name
RPB9/SDA1/CTED4/PMD3/RB9
23
AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2
RPC6/PMA1/RC6
24
AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3
3
RPC7/PMA0/RC7
25
AN6/RPC0/RC0
4
RPC8/PMA5/RC8
26
AN7/RPC1/RC1
5
RPC9/CTED7/PMA6/RC9
27
AN8/RPC2/PMA2/RC2
6
VSS
28
VDD
7
VCAP
29
VSS
8
PGED2/RPB10/D+/CTED11/RB10
30
OSC1/CLKI/RPA2/RA2
9
PGEC2/RPB11/D-/RB11
31
OSC2/CLKO/RPA3/RA3
10
VUSB3V3
32
TDO/RPA8/PMA8/RA8
11
AN11/RPB13/CTPLS/PMRD/RB13
33
SOSCI/RPB4/RB4
12
PGED4/TMS/PMA10/RA10
34
SOSCO/RPA4/T1CK/CTED9/RA4
13
PGEC4/TCK/CTED8/PMA7/RA7
35
TDI/RPA9/PMA9/RA9
14
CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14
36
AN12/RPC3/RC3
15
AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
37
RPC4/PMA4/RC4
16
AVSS
38
RPC5/PMA3/RC5
17
AVDD
39
VSS
18
MCLR
40
VDD
19
PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0
41
RPB5/USBID/RB5
20
PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1
42
VBUS
21
PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0
43
RPB7/CTED3/PMD5/INT0/RB7
22
PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1
44
RPB8/SCL1/CTED10/PMD4/RB8
Note
1:
2:
3:
4:
5:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
This pin function is not available on PIC32MX110F016D and PIC32MX120F032D devices.
Shaded pins are 5V tolerant.
2011-2019 Microchip Technology Inc.
DS60001168L-page 11
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 11:
PIN NAMES FOR 44-PIN GENERAL PURPOSE DEVICES
44-PIN TQFP (TOP VIEW)(1,2,3,5)
PIC32MX110F016D
PIC32MX120F032D
PIC32MX130F064D
PIC32MX130F256D
PIC32MX150F128D
PIC32MX170F256D
44
1
Pin #
1
Full Pin Name
Pin #
Full Pin Name
RPB9/SDA1/CTED4/PMD3/RB9
23
AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
2
RPC6/PMA1/RC6
24
AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
3
RPC7/PMA0/RC7
25
AN6/RPC0/RC0
4
RPC8/PMA5/RC8
26
AN7/RPC1/RC1
5
RPC9/CTED7/PMA6/RC9
27
AN8/RPC2/PMA2/RC2
6
VSS
28
VDD
7
VCAP
29
VSS
8
PGED2/RPB10/CTED11/PMD2/RB10
30
OSC1/CLKI/RPA2/RA2
9
PGEC2/RPB11/PMD1/RB11
31
OSC2/CLKO/RPA3/RA3
10
AN12/PMD0/RB12
32
TDO/RPA8/PMA8/RA8
11
AN11/RPB13/CTPLS/PMRD/RB13
33
SOSCI/RPB4/RB4
12
PGED4(4)/TMS/PMA10/RA10
34
SOSCO/RPA4/T1CK/CTED9/RA4
13
PGEC4(4)/TCK/CTED8/PMA7/RA7
35
TDI/RPA9/PMA9/RA9
14
CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
36
RPC3/RC3
15
AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
37
RPC4/PMA4/RC4
16
AVSS
38
RPC5/PMA3/RC5
17
AVDD
39
VSS
18
MCLR
40
VDD
19
VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0
41
PGED3/RPB5/PMD7/RB5
20
VREF-/CVREF-/AN1/RPA1/CTED2/RA1
42
PGEC3/RPB6/PMD6/RB6
21
PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
43
RPB7/CTED3/PMD5/INT0/RB7
PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
44
RPB8/SCL1/CTED10/PMD4/RB8
22
Note
1:
2:
3:
4:
5:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
This pin function is not available on PIC32MX110F016D and PIC32MX120F032D devices.
Shaded pins are 5V tolerant.
DS60001168L-page 12
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 12:
PIN NAMES FOR 44-PIN USB DEVICES
44-PIN TQFP (TOP VIEW)(1,2,3,5)
PIC32MX210F016D
PIC32MX220F032D
PIC32MX230F064D
PIC32MX230F256D
PIC32MX250F128D
PIC32MX270F256D
44
1
Pin #
Full Pin Name
Pin #
Full Pin Name
1
RPB9/SDA1/CTED4/PMD3/RB9
23
AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2
2
RPC6/PMA1/RC6
24
AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3
3
RPC7/PMA0/RC7
25
AN6/RPC0/RC0
4
RPC8/PMA5/RC8
26
AN7/RPC1/RC1
5
RPC9/CTED7/PMA6/RC9
27
AN8/RPC2/PMA2/RC2
6
VSS
28
VDD
7
VCAP
29
VSS
8
PGED2/RPB10/D+/CTED11/RB10
30
OSC1/CLKI/RPA2/RA2
OSC2/CLKO/RPA3/RA3
9
PGEC2/RPB11/D-/RB11
31
10
VUSB3V3
32
TDO/RPA8/PMA8/RA8
11
AN11/RPB13/CTPLS/PMRD/RB13
33
SOSCI/RPB4/RB4
12
PGED4(4)/TMS/PMA10/RA10
34
SOSCO/RPA4/T1CK/CTED9/RA4
13
PGEC4 /TCK/CTED8/PMA7/RA7
35
TDI/RPA9/PMA9/RA9
14
CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14
36
AN12/RPC3/RC3
15
AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
37
RPC4/PMA4/RC4
16
AVSS
38
RPC5/PMA3/RC5
17
AVDD
39
VSS
18
MCLR
40
VDD
19
PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0
41
RPB5/USBID/RB5
20
PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1
42
VBUS
21
PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0
43
RPB7/CTED3/PMD5/INT0/RB7
22
PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1
44
RPB8/SCL1/CTED10/PMD4/RB8
Note
(4)
1:
2:
3:
4:
5:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
This pin function is not available on PIC32MX210F016D and PIC32MX220F032D devices.
Shaded pins are 5V tolerant.
2011-2019 Microchip Technology Inc.
DS60001168L-page 13
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 13:
PIN NAMES FOR 44-PIN GENERAL PURPOSE DEVICES
44-PIN VTLA (BOTTOM VIEW)(1,2,3,5)
PIC32MX110F016D
PIC32MX120F032D
PC32MX130F064D
PIC32MX130F256D
PIC32MX150F128D
PIC32MX170F256D
1
44
Pin #
Full Pin Name
Pin #
Full Pin Name
1
RPB9/SDA1/CTED4/PMD3/RB9
23
AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
2
RPC6/PMA1/RC6
24
AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
3
RPC7/PMA0/RC7
25
AN6/RPC0/RC0
4
RPC8/PMA5/RC8
26
AN7/RPC1/RC1
5
RPC9/CTED7/PMA6/RC9
27
AN8/RPC2/PMA2/RC2
6
VSS
28
VDD
7
VCAP
29
VSS
8
PGED2/RPB10/CTED11/PMD2/RB10
30
OSC1/CLKI/RPA2/RA2
OSC2/CLKO/RPA3/RA3
9
PGEC2/RPB11/PMD1/RB11
31
10
AN12/PMD0/RB12
32
TDO/RPA8/PMA8/RA8
11
AN11/RPB13/CTPLS/PMRD/RB13
33
SOSCI/RPB4/RB4
12
PGED4(4)/TMS/PMA10/RA10
34
SOSCO/RPA4/T1CK/CTED9/RA4
13
PGEC4(4)/TCK/CTED8/PMA7/RA7
35
TDI/RPA9/PMA9/RA9
14
CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
36
RPC3/RC3
15
AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
37
RPC4/PMA4/RC4
16
AVSS
38
RPC5/PMA3/RC5
17
AVDD
39
VSS
18
MCLR
40
VDD
19
VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0
41
PGED3/RPB5/PMD7/RB5
20
VREF-/CVREF-/AN1/RPA1/CTED2/RA1
42
PGEC3/RPB6/PMD6/RB6
21
PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
43
RPB7/CTED3/PMD5/INT0/RB7
22
PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
44
RPB8/SCL1/CTED10/PMD4/RB8
Note
1:
2:
3:
4:
5:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
This pin function is not available on PIC32MX110F016D and PIC32MX120F032D devices.
Shaded pins are 5V tolerant.
DS60001168L-page 14
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 14:
PIN NAMES FOR 44-PIN USB DEVICES
44-PIN VTLA (BOTTOM VIEW)(1,2,3,5)
PIC32MX210F016D
PIC32MX220F032D
PIC32MX230F064D
PIC32MX230F256D
PIC32MX250F128D
PIC32MX270F256D
44
Pin #
Full Pin Name
Pin #
Full Pin Name
1
RPB9/SDA1/CTED4/PMD3/RB9
23
AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2
2
RPC6/PMA1/RC6
24
AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3
3
RPC7/PMA0/RC7
25
AN6/RPC0/RC0
4
RPC8/PMA5/RC8
26
AN7/RPC1/RC1
5
RPC9/CTED7/PMA6/RC9
27
AN8/RPC2/PMA2/RC2
6
VSS
28
VDD
7
VCAP
29
VSS
8
PGED2/RPB10/D+/CTED11/RB10
30
OSC1/CLKI/RPA2/RA2
OSC2/CLKO/RPA3/RA3
9
PGEC2/RPB11/D-/RB11
31
10
VUSB3V3
32
TDO/RPA8/PMA8/RA8
11
AN11/RPB13/CTPLS/PMRD/RB13
33
SOSCI/RPB4/RB4
12
PGED4(4)/TMS/PMA10/RA10
34
SOSCO/RPA4/T1CK/CTED9/RA4
13
PGEC4 /TCK/CTED8/PMA7/RA7
35
TDI/RPA9/PMA9/RA9
14
CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14
36
AN12/RPC3/RC3
15
AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
37
RPC4/PMA4/RC4
16
AVSS
38
RPC5/PMA3/RC5
17
AVDD
39
VSS
18
MCLR
40
VDD
19
PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0
41
RPB5/USBID/RB5
20
PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1
42
VBUS
21
PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0
43
RPB7/CTED3/PMD5/INT0/RB7
22
PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1
44
RPB8/SCL1/CTED10/PMD4/RB8
Note
(4)
1:
2:
3:
4:
5:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
This pin function is not available on PIC32MX210F016D and PIC32MX220F032D devices.
Shaded pins are 5V tolerant.
2011-2019 Microchip Technology Inc.
DS60001168L-page 15
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 19
2.0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................ 27
3.0 CPU ............................................................................................................................................................................................ 37
4.0 Memory Organization ................................................................................................................................................................. 41
5.0 Flash Program Memory .............................................................................................................................................................. 57
6.0 Resets ........................................................................................................................................................................................ 63
7.0 Interrupt Controller ..................................................................................................................................................................... 67
8.0 Oscillator Configuration .............................................................................................................................................................. 77
9.0 Direct Memory Access (DMA) Controller ................................................................................................................................... 87
10.0 USB On-The-Go (OTG)............................................................................................................................................................ 107
11.0 I/O Ports ................................................................................................................................................................................... 131
12.0 Timer1 ...................................................................................................................................................................................... 147
13.0 Timer2/3, Timer4/5 ................................................................................................................................................................... 151
14.0 Watchdog Timer (WDT) ........................................................................................................................................................... 157
15.0 Input Capture............................................................................................................................................................................ 161
16.0 Output Compare ....................................................................................................................................................................... 165
17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 169
18.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 177
19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 185
20.0 Parallel Master Port (PMP)....................................................................................................................................................... 193
21.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 203
22.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 213
23.0 Comparator .............................................................................................................................................................................. 223
24.0 Comparator Voltage Reference (CVREF).................................................................................................................................. 227
25.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 231
26.0 Power-Saving Features ........................................................................................................................................................... 237
27.0 Special Features ...................................................................................................................................................................... 243
28.0 Instruction Set .......................................................................................................................................................................... 255
29.0 Development Support............................................................................................................................................................... 257
30.0 Electrical Characteristics .......................................................................................................................................................... 261
31.0 50 MHz Electrical Characteristics............................................................................................................................................. 305
32.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 311
33.0 Packaging Information.............................................................................................................................................................. 315
The Microchip Web Site ..................................................................................................................................................................... 347
Customer Change Notification Service .............................................................................................................................................. 347
Customer Support .............................................................................................................................................................................. 347
Product Identification System............................................................................................................................................................. 348
DS60001168L-page 16
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
2011-2019 Microchip Technology Inc.
DS60001168L-page 17
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
Referenced Sources
This device data sheet is based on the following
individual chapters of the “PIC32 Family Reference
Manual”. These documents should be considered as
the general reference for the operation of a particular
module or device feature.
Note:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
To access the following documents, refer
to the Documentation > Reference
Manuals section of the Microchip PIC32
website: http://www.microchip.com/pic32
Section 1. “Introduction” (DS60001127)
Section 2. “CPU” (DS60001113)
Section 3. “Memory Organization” (DS60001115)
Section 5. “Flash Program Memory” (DS60001121)
Section 6. “Oscillator Configuration” (DS60001112)
Section 7. “Resets” (DS60001118)
Section 8. “Interrupt Controller” (DS60001108)
Section 9. “Watchdog Timer and Power-up Timer” (DS60001114)
Section 10. “Power-Saving Features” (DS60001130)
Section 12. “I/O Ports” (DS60001120)
Section 13. “Parallel Master Port (PMP)” (DS60001128)
Section 14. “Timers” (DS60001105)
Section 15. “Input Capture” (DS60001122)
Section 16. “Output Compare” (DS60001111)
Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS60001104)
Section 19. “Comparator” (DS60001110)
Section 20. “Comparator Voltage Reference (CVREF)” (DS60001109)
Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107)
Section 23. “Serial Peripheral Interface (SPI)” (DS60001106)
Section 24. “Inter-Integrated Circuit (I2C)” (DS60001116)
Section 27. “USB On-The-Go (OTG)” (DS60001126)
Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125)
Section 31. “Direct Memory Access (DMA) Controller” (DS60001117)
Section 32. “Configuration” (DS60001124)
Section 33. “Programming and Diagnostics” (DS60001129)
Section 37. “Charge Time Measurement Unit (CTMU)” (DS60001167)
DS60001168L-page 18
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
1.0
DEVICE OVERVIEW
Note:
This document contains device-specific information for
PIC32MX1XX/2XX 28/36/44-pin Family of devices.
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to documents listed in the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
FIGURE 1-1:
Figure 1-1 illustrates a general block diagram of the
core and peripheral modules in the PIC32MX1XX/2XX
28/36/44-pin Family of devices.
Table 1-1 lists the functions of the various pins shown
in the pinout diagrams.
BLOCK DIAGRAM
OSC2/CLKO
OSC1/CLKI
VCAP
OSC/SOSC
Oscillators
Power-up
Timer
FRC/LPRC
Oscillators
Voltage
Regulator
PLL
Oscillator
Start-up Timer
PLL-USB
Watchdog
Timer
USBCLK
SYSCLK
PBCLK
Timing
Generation
Brown-out
Reset
Peripheral Bus Clocked by SYSCLK
CTMU
PORTA
Timer1-Timer5
INT
®
MIPS32 M4K
CPU Core
PORTC
IS
32
Remappable
Pins
®
DS
32
32
ICD
EJTAG
USB
PORTB
32
32
32
Bus Matrix
32
32
PWM
OC1-OC5
Peripheral Bus Clocked by PBCLK
Priority
Interrupt
Controller
DMAC
JTAG
BSCAN
MCLR
Power-on
Reset
Precision
Band Gap
Reference
Dividers
VDD, VSS
IC1-IC5
SPI1-SPI2
I2C1-I2C2
32
32
32
Data RAM
Peripheral Bridge
PMP
32-bit Wide
Program Flash Memory
Flash
Controller
10-bit ADC
UART1-UART2
RTCC
Comparators 1-3
Note:
Some features are not available on all devices. Refer to the family features tables (Table 1 and Table 2) for availability.
2011-2019 Microchip Technology Inc.
DS60001168L-page 19
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin Number(1)
28-pin
QFN
28-pin
SSOP/
SPDIP/
SOIC
36-pin
VTLA
44-pin
QFN/
TQFP/
VTLA
Pin
Type
Buffer
Type
AN0
27
2
33
19
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
28
1
2
3
4
—
—
—
23
22
21
3
4
5
6
7
—
—
—
26
25
24
20(2)
23(2)
I
Analog
CLKI
6
9
20
21
22
23
24
25
26
27
15
14
11
10(2)
36(3)
30
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
AN12
34
35
36
1
2
3
4
—
29
28
27
26(2)
11(3)
7
I
I
I
I
I
I
I
I
I
I
I
I
Pin Name
Description
Analog input channels.
ST/CMOS External clock source input. Always
associated with OSC1 pin function.
CLKO
7
10
8
31
O
—
Oscillator crystal output. Connects to
crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in
RC and EC modes. Always associated
with OSC2 pin function.
OSC1
6
9
7
30
I
ST/CMOS Oscillator crystal input. ST buffer when
configured in RC mode; CMOS
otherwise.
OSC2
7
10
8
31
O
—
Oscillator crystal output. Connects to
crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in
RC and EC modes.
SOSCI
8
11
9
33
I
ST/CMOS 32.768 kHz low-power oscillator crystal
input; CMOS otherwise.
SOSCO
9
12
10
34
O
—
32.768 kHz low-power oscillator crystal
output.
REFCLKI
PPS
PPS
PPS
PPS
I
ST
Reference Input Clock
REFCLKO
PPS
PPS
PPS
PPS
O
—
Reference Output Clock
IC1
PPS
PPS
PPS
PPS
I
ST
Capture Inputs 1-5
IC2
PPS
PPS
PPS
PPS
I
ST
IC3
PPS
PPS
PPS
PPS
I
ST
IC4
PPS
PPS
PPS
PPS
I
ST
IC5
PPS
PPS
PPS
PPS
I
ST
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
PPS = Peripheral Pin Select
— = N/A
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: Pin number for PIC32MX1XX devices only.
3: Pin number for PIC32MX2XX devices only.
DS60001168L-page 20
I
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
OC1
OC2
OC3
OC4
OC5
OCFA
OCFB
INT0
INT1
INT2
INT3
INT4
RA0
28-pin
QFN
28-pin
SSOP/
SPDIP/
SOIC
36-pin
VTLA
44-pin
QFN/
TQFP/
VTLA
Pin
Type
Buffer
Type
PPS
PPS
PPS
PPS
PPS
PPS
PPS
13
PPS
PPS
PPS
PPS
27
PPS
PPS
PPS
PPS
PPS
PPS
PPS
16
PPS
PPS
PPS
PPS
2
PPS
PPS
PPS
PPS
PPS
PPS
PPS
17
PPS
PPS
PPS
PPS
33
PPS
PPS
PPS
PPS
PPS
PPS
PPS
43
PPS
PPS
PPS
PPS
19
O
O
O
O
O
I
I
I
I
I
I
I
—
—
—
—
—
ST
ST
ST
ST
ST
ST
ST
Description
Output Compare Output 1
Output Compare Output 2
Output Compare Output 3
Output Compare Output 4
Output Compare Output 5
Output Compare Fault A Input
Output Compare Fault B Input
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
I/O
ST
PORTA is a bidirectional I/O port
RA1
28
3
34
20
I/O
ST
RA2
6
9
7
30
I/O
ST
RA3
7
10
8
31
I/O
ST
RA4
9
12
10
34
I/O
ST
RA7
—
—
—
13
I/O
ST
RA8
—
—
—
32
I/O
ST
RA9
—
—
—
35
I/O
ST
RA10
—
—
—
12
I/O
ST
RB0
1
4
35
21
I/O
ST
PORTB is a bidirectional I/O port
RB1
2
5
36
22
I/O
ST
RB2
3
6
1
23
I/O
ST
RB3
4
7
2
24
I/O
ST
RB4
8
11
9
33
I/O
ST
RB5
11
14
15
41
I/O
ST
RB6
12(2)
15(2)
16(2)
42(2)
I/O
ST
RB7
13
16
17
43
I/O
ST
RB8
14
17
18
44
I/O
ST
RB9
15
18
19
1
I/O
ST
RB10
18
21
24
8
I/O
ST
RB11
19
22
25
9
I/O
ST
RB12
20(2)
23(2)
26(2)
10(2)
I/O
ST
RB13
21
24
27
11
I/O
ST
RB14
22
25
28
14
I/O
ST
RB15
23
26
29
15
I/O
ST
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
PPS = Peripheral Pin Select
— = N/A
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: Pin number for PIC32MX1XX devices only.
3: Pin number for PIC32MX2XX devices only.
2011-2019 Microchip Technology Inc.
DS60001168L-page 21
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
28-pin
QFN
28-pin
SSOP/
SPDIP/
SOIC
36-pin
VTLA
44-pin
QFN/
TQFP/
VTLA
Pin
Type
Buffer
Type
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RC8
RC9
T1CK
T2CK
T3CK
T4CK
T5CK
—
—
—
—
—
—
—
—
—
—
9
PPS
PPS
PPS
PPS
—
—
—
—
—
—
—
—
—
—
12
PPS
PPS
PPS
PPS
3
4
—
11
—
—
—
—
—
20
10
PPS
PPS
PPS
PPS
25
26
27
36
37
38
2
3
4
5
34
PPS
PPS
PPS
PPS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
PORTC is a bidirectional I/O port
U1CTS
PPS
PPS
PPS
PPS
I
ST
UART1 clear to send
U1RTS
U1RX
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
O
I
—
ST
UART1 ready to send
UART1 receive
U1TX
PPS
PPS
PPS
PPS
O
—
UART1 transmit
U2CTS
PPS
PPS
PPS
PPS
I
ST
UART2 clear to send
U2RTS
U2RX
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
O
—
UART2 ready to send
I
ST
UART2 receive
U2TX
PPS
PPS
PPS
PPS
O
—
SCK1
22
25
28
14
I/O
ST
SDI1
PPS
PPS
PPS
PPS
I
ST
UART2 transmit
Synchronous serial clock input/output for
SPI1
SPI1 data in
SDO1
PPS
PPS
PPS
PPS
O
—
SPI1 data out
SS1
PPS
PPS
PPS
PPS
I/O
ST
SCK2
23
26
29
15
I/O
ST
SDI2
PPS
PPS
PPS
PPS
I
ST
SPI1 slave synchronization or frame
pulse I/O
Synchronous serial clock input/output for
SPI2
SPI2 data in
SDO2
PPS
PPS
PPS
PPS
O
—
SPI2 data out
SS2
PPS
PPS
PPS
PPS
I/O
ST
Pin Name
Description
Timer1 external clock input
Timer2 external clock input
Timer3 external clock input
Timer4 external clock input
Timer5 external clock input
SPI2 slave synchronization or frame
pulse I/O
SCL1
14
17
18
44
I/O
ST
Synchronous serial clock input/output for
I2C1
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
PPS = Peripheral Pin Select
— = N/A
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: Pin number for PIC32MX1XX devices only.
3: Pin number for PIC32MX2XX devices only.
DS60001168L-page 22
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
28-pin
QFN
28-pin
SSOP/
SPDIP/
SOIC
36-pin
VTLA
44-pin
QFN/
TQFP/
VTLA
Pin
Type
Buffer
Type
SDA1
15
18
19
1
I/O
ST
SCL2
4
7
2
24
I/O
ST
SDA2
3
6
1
23
I/O
ST
19(2)
11(3)
14
13
15
4
28
22(2)
14(3)
17
16
18
7
3
25(2)
15(3)
18
17
19
2
34
12
I
ST
13
35
32
24
20
I
O
O
O
I
ST
—
—
ST
Analog
27
22
4
2
25
7
33
28
2
19
14
24
I
O
Analog
Analog
Pin Name
TMS
TCK
TDI
TDO
RTCC
CVREFCVREF+
CVREFOUT
C1INA
Description
Synchronous serial data input/output for
I2C1
Synchronous serial clock input/output for
I2C2
Synchronous serial data input/output for
I2C2
JTAG Test mode select pin
JTAG test clock input pin
JTAG test data input pin
JTAG test data output pin
Real-Time Clock alarm output
Comparator Voltage Reference (low)
Comparator Voltage Reference (high)
Comparator Voltage Reference output
I
Analog Comparator Inputs
C1INB
3
6
1
23
I
Analog
C1INC
2
5
36
22
I
Analog
C1IND
1
4
35
21
I
Analog
C2INA
2
5
36
22
I
Analog
C2INB
1
4
35
21
I
Analog
C2INC
4
7
2
24
I
Analog
C2IND
3
6
1
23
I
Analog
C3INA
23
26
29
15
I
Analog
C3INB
22
25
28
14
I
Analog
C3INC
27
2
33
19
I
Analog
C3IND
1
4
35
21
I
Analog
C1OUT
PPS
PPS
PPS
PPS
O
—
Comparator Outputs
C2OUT
PPS
PPS
PPS
PPS
O
—
C3OUT
PPS
PPS
PPS
PPS
O
—
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
PPS = Peripheral Pin Select
— = N/A
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: Pin number for PIC32MX1XX devices only.
3: Pin number for PIC32MX2XX devices only.
2011-2019 Microchip Technology Inc.
DS60001168L-page 23
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
28-pin
QFN
28-pin
SSOP/
SPDIP/
SOIC
36-pin
VTLA
44-pin
QFN/
TQFP/
VTLA
Pin
Type
Buffer
Type
PMA0
7
10
8
3
I/O
TTL/ST
PMA1
9
12
10
2
I/O
TTL/ST
23
20(2)
1(3)
19(2)
2(3)
18(2)
3(3)
15
—
—
—
—
—
—
—
—
—
26
23(2)
4(3)
22(2)
5(3)
21(2)
6(3)
18
—
—
—
—
—
—
—
—
—
29
26(2)
35(3)
25(2)
36(3)
24(2)
1(3)
19
27
38
37
4
5
13
32
35
12
15
10(2)
21(3)
9(2)
22(3)
8(2)
23(3)
1
O
O
O
O
O
O
O
O
O
O
—
—
—
—
—
—
—
—
—
—
I/O
TTL/ST
I/O
TTL/ST
I/O
TTL/ST
14
13
12(2)
28(3)
11(2)
27(3)
21
22(2)
4(3)
12(3)
20(3)
17
16
15(2)
3(3)
14(2)
2(3)
24
25(2)
7(3)
15(3)
23(3)
18
17
16(2)
34(3)
15(2)
33(3)
27
28(2)
2(3)
16(3)
26(3)
44
43
42(2)
20(3)
41(2)
19(3)
11
14(2)
24(3)
42(3)
10(3)
I/O
I/O
I/O
TTL/ST
TTL/ST
TTL/ST
I/O
TTL/ST
I/O
TTL/ST
O
—
Parallel Master Port read strobe
O
—
Parallel Master Port write strobe
I
P
Analog
—
Pin Name
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMCS1
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
PMD7
PMRD
PMWR
VBUS
VUSB3V3
Description
Parallel Master Port Address bit 0 input
(Buffered Slave modes) and output
(Master modes)
Parallel Master Port Address bit 1 input
(Buffered Slave modes) and output
(Master modes)
Parallel Master Port address
(Demultiplexed Master modes)
Parallel Master Port Chip Select 1 strobe
Parallel Master Port data (Demultiplexed
Master mode) or address/data
(Multiplexed Master modes)
USB bus power monitor
USB internal transceiver supply. This pin
must be connected to VDD.
VBUSON
22(3)
25(3)
28(3)
14(3)
O
—
USB Host and OTG bus power control
output
21(3)
24(3)
8(3)
I/O
Analog USB D+
D+
18(3)
(3)
(3)
(3)
D19
22
25
9(3)
I/O
Analog USB DLegend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
PPS = Peripheral Pin Select
— = N/A
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: Pin number for PIC32MX1XX devices only.
3: Pin number for PIC32MX2XX devices only.
DS60001168L-page 24
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
28-pin
QFN
28-pin
SSOP/
SPDIP/
SOIC
36-pin
VTLA
44-pin
QFN/
TQFP/
VTLA
Pin
Type
Buffer
Type
USBID
CTED1
CTED2
CTED3
CTED4
CTED5
CTED6
CTED7
CTED8
CTED9
CTED10
CTED11
CTED12
CTED13
CTPLS
PGED1
11(3)
27
28
13
15
22
23
—
—
9
14
18
2
3
21
1
14(3)
2
3
16
18
25
26
—
—
12
17
21
5
6
24
4
15(3)
33
34
17
19
28
29
20
—
10
18
24
36
1
27
35
41(3)
19
20
43
1
14
15
5
13
34
44
8
22
23
11
21
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
ST
PGEC1
2
5
36
22
I
ST
PGED2
18
21
24
8
I/O
ST
PGEC2
19
22
25
9
I
ST
11(2)
27(3)
12(2)
28(3)
—
14(2)
2(3)
15(2)
3(3)
—
15(2)
33(3)
16(2)
34(3)
3
41(2)
19(3)
42(2)
20(3)
12
I/O
ST
I
ST
Pin Name
PGED3
PGEC3
PGED4
Description
USB OTG ID detect
CTMU External Edge Input
CTMU Pulse Output
Data I/O pin for Programming/Debugging
Communication Channel 1
Clock input pin for
Programming/Debugging
Communication Channel 1
Data I/O pin for Programming/Debugging
Communication Channel 2
Clock input pin for
Programming/Debugging
Communication Channel 2
Data I/O pin for Programming/Debugging
Communication Channel 3
Clock input pin for Programming/
Debugging Communication Channel 3
Data I/O pin for Programming/Debugging
Communication Channel 4
PGEC4
—
—
4
13
Clock input pin for Programming/
I
ST
Debugging Communication Channel 4
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
PPS = Peripheral Pin Select
— = N/A
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: Pin number for PIC32MX1XX devices only.
3: Pin number for PIC32MX2XX devices only.
2011-2019 Microchip Technology Inc.
I/O
ST
DS60001168L-page 25
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
MCLR
28-pin
QFN
28-pin
SSOP/
SPDIP/
SOIC
36-pin
VTLA
44-pin
QFN/
TQFP/
VTLA
Pin
Type
Buffer
Type
26
1
32
18
I/P
ST
Description
Master Clear (Reset) input. This pin is an
active-low Reset to the device.
25
28
31
17
P
—
Positive supply for analog modules. This
AVDD
pin must be connected at all times.
24
27
30
16
P
—
Ground reference for analog modules
AVSS
VDD
10
13
5, 13, 14,
28, 40
P
—
Positive supply for peripheral logic and
23
I/O pins
17
20
22
7
P
—
CPU logic filter capacitor connection
VCAP
VSS
5, 16
8, 19
6, 12, 21 6, 29, 39
P
—
Ground reference for logic and I/O pins.
This pin must be connected at all times.
VREF+
27
2
33
19
I
Analog Analog voltage reference (high) input
28
3
34
20
I
Analog Analog voltage reference (low) input
VREFLegend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
PPS = Peripheral Pin Select
— = N/A
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: Pin number for PIC32MX1XX devices only.
3: Pin number for PIC32MX2XX devices only.
DS60001168L-page 26
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2.0
Note:
2.1
GUIDELINES FOR GETTING
STARTED WITH 32-BIT MCUs
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the documents listed in the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
Basic Connection Requirements
Getting started with the PIC32MX1XX/2XX 28/36/44pin Family of 32-bit Microcontrollers (MCUs) requires
attention to a minimal set of device pin connections
before proceeding with development. The following is a
list of pin names, which must always be connected:
• All VDD and VSS pins (see 2.2 “Decoupling
Capacitors”)
• All AVDD and AVSS pins, even if the ADC module
is not used (see 2.2 “Decoupling Capacitors”)
• VCAP pin (see 2.3 “Capacitor on Internal
Voltage Regulator (VCAP)”)
• MCLR pin (see 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins, used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes (see 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins, when external oscillator
source is used (see 2.7 “External Oscillator
Pins”)
The following pins may be required:
• VREF+/VREF- pins – used when external voltage
reference for the ADC module is implemented
Note:
The AVDD and AVSS pins must be connected, regardless of ADC use and the
ADC voltage reference source.
2011-2019 Microchip Technology Inc.
2.2
Decoupling Capacitors
The use of decoupling capacitors on power supply
pins, such as VDD, VSS, AVDD and AVSS is required.
See Figure 2-1.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A value of 0.1 µF
(100 nF), 10-20V is recommended. The capacitor
should be a low Equivalent Series Resistance
(low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is
further recommended that ceramic capacitors be
used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended that
the capacitors be placed on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within onequarter inch (6 mm) in length.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
DS60001168L-page 27
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
Tantalum or
ceramic 10 µF
ESR 3(3)
MCLR
C
0.1 µF
PIC32
VDD
VSS
Connect(2)
VDD
AVSS
VSS
AVDD
VDD
0.1 µF
Ceramic
VSS
VUSB3V3(1)
0.1 µF
Ceramic
0.1 µF
Ceramic
VSS
1K
VDD
10K
R1
VCAP
VDD
0.1 µF
Ceramic
0.1 µF
Ceramic
L1(2)
Note
1:
If the USB module is not used, this pin must be
connected to VDD.
2:
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 3 and the inductor
capacity greater than 10 mA.
2.4
Master Clear (MCLR) Pin
The MCLR
functions:
1:
2.2.1
FIGURE 2-2:
2.3.1
0.1 µF(2)
ICSP™
Note
1
5
4
2
3
6
A low-ESR (3 ohm) capacitor is required on the VCAP
pin, which is used to stabilize the internal voltage
regulator output. The VCAP pin must not be connected
to VDD, and must have a CEFC capacitor, with at least a
6V rating, connected to ground. The type can be
ceramic or tantalum. Refer to 30.0 “Electrical
Characteristics” for additional information on CEFC
specifications.
DS60001168L-page 28
2.5
10k
C
R1(1)
1 k
MCLR
PIC32
PGECx(3)
PGEDx(3)
VDD
VSS
NC
1:
470 R1 1 will limit any current flowing into
MCLR from the external capacitor C, in the event of
MCLR pin breakdown, due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS). Ensure that the
MCLR pin VIH and VIL specifications are met without
interfering with the Debug/Programmer tools.
2:
The capacitor can be sized to prevent unintentional
Resets from brief glitches or to extend the device
Reset period during POR.
3:
No pull-ups or bypass capacitors are allowed on
active debug/program PGECx/PGEDx pins.
BULK CAPACITORS
INTERNAL REGULATOR MODE
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
2
Capacitor on Internal Voltage
Regulator (VCAP)
device
Place the components illustrated in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.
2.3
specific
For example, as illustrated in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
(i.e., ADC conversion rate/2)
Aluminum or electrolytic capacitors should not be
used. ESR 3 from -40ºC to 125ºC @ SYSCLK
frequency (i.e., MIPS).
two
Pulling The MCLR pin low generates a device Reset.
Figure 2-2 illustrates a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
R
1 -
L = -------------------- 2f C
provides
• Device Reset
• Device programming and debugging
Where:
F CNV
f = -------------2
1
f = ---------------------- 2 LC
pin
ICSP Pins
The PGECx and PGEDx pins are used for ICSP and
debugging purposes. It is recommended to keep the
trace length between the ICSP connector and the ICSP
pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a
series resistor is recommended, with the value in the
range of a few tens of Ohms, not to exceed 100 Ohms.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 3 or MPLAB REAL ICE™.
The oscillator circuit should be placed on the same side
of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The
load capacitors should be placed next to the oscillator
itself, on the same side of the board. Use a grounded
copper pour around the oscillator circuit to isolate them
from surrounding circuits. The grounded copper pour
should be routed directly to the MCU ground. Do not
run any signal traces or power traces inside the ground
pour. Also, if using a two-sided board, avoid any traces
on the other side of the board where the crystal is
placed. A suggested layout is illustrated in Figure 2-3.
FIGURE 2-3:
For more information on ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web
site:
SUGGESTED OSCILLATOR
CIRCUIT PLACEMENT
Oscillator
Secondary
• “Using MPLAB® ICD 3” (poster) (DS50001765)
• “MPLAB® ICD 3 Design Advisory” (DS50001764)
• “MPLAB® REAL ICE™ In-Circuit Debugger
User’s Guide” (DS50001616)
• “Using MPLAB® REAL ICE™ Emulator” (poster)
(DS50001749)
2.6
JTAG
The TMS, TDO, TDI and TCK pins are used for testing
and debugging according to the Joint Test Action
Group (JTAG) standard. It is recommended to keep the
trace length between the JTAG connector and the
JTAG pins on the device as short as possible. If the
JTAG connector is expected to experience an ESD
event, a series resistor is recommended with the value
in the range of a few tens of Ohms, not to exceed 100
Ohms.
Guard Trace
Guard Ring
Main Oscillator
2.8
Unused I/Os
Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
to a logic-low state.
Alternatively, inputs can be reserved by connecting the
pin to VSS through a 1k to 10k resistor and configuring
the pin as an input.
Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended
as they will interfere with the programmer/debugger
communications to the device. If such discrete components are an application requirement, they should be
removed from the circuit during programming and
debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the
respective device Flash programming specification for
information on capacitive loading limits and pin input
voltage high (VIH) and input low (VIL) requirements.
2.7
External Oscillator Pins
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 “Oscillator
Configuration” for details).
2011-2019 Microchip Technology Inc.
DS60001168L-page 29
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 2-4:
The following example assumptions are used to
calculate the Primary Oscillator loading capacitor
values:
Circuit A
Typical XT
(4-10 MHz)
C1
• CIN = PIC32_OSC2_Pin Capacitance = ~4-5 pF
• COUT = PIC32_OSC1_Pin Capacitance = ~4-5 pF
• C1 and C2 = XTAL manufacturing recommended
loading capacitance
• Estimated PCB stray capacitance, (i.e.,12 mm
length) = 2.5 pF
1M
OSC2
EXAMPLE 2-1: CRYSTAL LOAD CAPACITOR
CALCULATION
Circuit B
= {( [5 + 15][5 + 15] ) / [5 + 15 + 15 + 5] } + 2.5 pF
C1
Therefore:
= {( [CIN + C1] * [COUT + C2] ) / [CIN + C1 + C2 + COUT] }
+ estimated oscillator PCB stray capacitance
OSC1
Typical HS
(10-25 MHz)
Crystal manufacturer recommended: C1 = C2 = 15 pF
CLOAD
PRIMARY CRYSTAL
OSCILLATOR CIRCUIT
RECOMMENDATIONS
C2
CRYSTAL OSCILLATOR DESIGN
CONSIDERATION
C2
2.8.1
= {( [20][20]) / [40] } + 2.5
= 10 + 2.5 = 12.5 pF
OSC2
Rounded to the nearest standard value or 12 pF in this example for
Primary Oscillator crystals “C1” and “C2”.
Circuit C
The following tips are used to increase oscillator gain,
(i.e., to increase peak-to-peak oscillator signal):
Note:
2.8.1.1
Do not add excessive gain such that the
oscillator signal is clipped, flat on top of
the sine wave. If so, you need to reduce
the gain or add a series resistor, RS, as
shown in circuit “C” in Figure 2-4. Failure
to do so will stress and age the crystal,
which can result in an early failure. Adjust
the gain to trim the max peak-to-peak to
~VDD-0.6V. When measuring the oscillator signal you must use a FET scope
probe or a probe with 1.5 pF or the
scope probe itself will unduly change the
gain and peak-to-peak levels.
C2
Typical XT/HS
(4-25 MHz)
C1
• Select a crystal with a lower “minimum” power drive
rating
• Select an crystal oscillator with a lower XTAL
manufacturing “ESR” rating.
• Add a parallel resistor across the crystal. The smaller
the resistor value the greater the gain. It is recommended to stay in the range of 600k to 1M
• C1 and C2 values also affect the gain of the oscillator.
The lower the values, the higher the gain.
• C2/C1 ratio also affects gain. To increase the gain,
make C1 slightly smaller than C2, which will also help
start-up performance.
OSC1
Rs
1M
OSC2
OSC1
Circuit D
Not Recommended
1M
Rs
OSC1
OSC2
Circuit E
Not Recommended
Additional Microchip References
• AN588 “PICmicro® Microcontroller Oscillator
Design Guide”
• AN826 “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
• AN849 “Basic PICmicro® Oscillator Design”
DS60001168L-page 30
Rs
1M
OSC2
OSC1
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2.9
Typical Application Connection
Examples
Examples of typical application connections are shown
in Figure 2-5 and Figure 2-6.
FIGURE 2-5:
CAPACITIVE TOUCH SENSING WITH GRAPHICS APPLICATION
PIC32MX120F032D
Current Source
To AN6
To AN7
To AN8
To AN9
To AN11
To AN0
CTMU
AN0
AN1
ADC
R1
R1
R1
R1
C1
C2
C3
C4
C5
To AN1
Read the Touch Sensors
Microchip
mTouch™
Library
R1
R2
R2
R2
R2
R2
C1
C2
C3
C4
C5
R3
R3
R3
R3
R3
C1
C2
C3
C4
C5
AN9
To AN5
Process Samples
AN11
User
Application
Display Data
Microchip
Graphics
Library
FIGURE 2-6:
USB
Host
Parallel
Master
Port
LCD Controller
PMPD
Display
Controller
Frame
Buffer
PMPWR
LCD
Panel
AUDIO PLAYBACK APPLICATION
PMPD
USB
PMP
Display
PMPWR
PIC32MX220F032D
I2S
Stereo Headphones
3
Audio
Codec
SPI
3
Speaker
3
MMC SD
SDI
2011-2019 Microchip Technology Inc.
DS60001168L-page 31
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2.10
2.10.1
Considerations When Interfacing
To Remotely Powered Circuits
NON-5V TOLERANT INPUT PINS
A quick review of the maximum rating section in the
Section 30.0 “Electrical Characteristics” will
indicate that the voltage on any non-5V tolerant pin
should not exceed AVDD/VDD+0.3V. Figure 2-7
illustrates a remote circuit using an independent power
source that is powered while connected to a PIC32
non-5V tolerant circuit which is not powered.
FIGURE 2-7:
DS60001168L-page 32
REMOTE CIRCUIT WITH AN INDEPENDENT POWER SOURCE
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
case, it is recommended that users can implement a
digital or analog signal isolation, as shown in Figure 28.
Without proper signal isolation on non-5V tolerant
pins, the remote signal can power the PIC32 through
the high side ESD protection diodes. This violates the
maximum rating specification and can cause improper
initialization of internal PIC32 logic circuits. In this
FIGURE 2-8:
DIGITAL AND ANALOG SIGNAL ISOLATION
Digital signal isolators along with optional level
translation examples are provided in Table 2-1.
Analog/Digital Switch
Optional Coupling
Capacitive Coupling
EXAMPLES OF DIGITAL ISOLATORS WITH OPTIONAL LEVEL TRANSLATION
Inductive Coupling
TABLE 2-1:
ADuM7241 / 40 ARZ (1Mbps)
X
-
-
-
ADuM7241 / 40 CRZ (25 Mbps)
X
-
-
-
ISO721
-
X
-
-
LTV-829S (2 Chan)
-
-
X
-
LTV-849S (4 Chan)
-
-
-
-
FSA266 / NC7WB66
-
-
-
X
2011-2019 Microchip Technology Inc.
DS60001168L-page 33
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2.10.2
5V-TOLERANT INPUT PINS
The internal high-side diode on 5V-tolerant pins, rather
than being connected to VDD, are bussed to an
internal floating node, as shown in Figure 2-9.
Voltages on these pins, if VDD < 2.3V, should not
exceed roughly 3.2V relative to PIC32 VSS. At 3.6V or
above, it will violate the absolute maximum
specification and impact the device reliability.
FIGURE 2-9:
DS60001168L-page 34
If a remotely powered digital only signal can be
guaranteed to always be ≤ 3.2V relative to PIC32 VSS,
then a 5V-tolerant pin can be used without a digital
isolator. This can be assumed when the following is
applicable:
• No ground loop issue
• The logic ground of the two circuits is not at the
same absolute level
• No remote logic low inputs are less than VSS 0.3V
5V-TOLERANT INPUT PINS BUSSED TO AN INTERNAL FLOATING NODE
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2.11
EMI/EMC/EFT (IEC 61000-4-4 and
IEC 61000-4-2) Suppression
Considerations
The use of LDO regulators is preferred to reduce
overall system noise and provide a cleaner power
source.
However,
when
utilizing
switching
Buck/Boost regulators as the local power source for
PIC32 devices, as well as in electrically noisy environments or test conditions required for IEC 610004-4 and IEC 61000-4-2, users should evaluate the
use of T-Filters (i.e., L-C-L) on the power pins, as
shown in Figure 2-10. In addition to a more stable
power source, using this type of T-Filter can greatly
reduce susceptibility to EMI sources and events.
FIGURE 2-10:
EMI/EMC/EFT
SUPPRESSION CIRCUIT
Ferrite Chip SMD
DCR = 0.15ȍ (max)
600 ma ISAT
300ȍ @ 100 MHz
PN#: 1-1624117-3
VDD
0.01 μF
Ferrite
Chips
0.1 μF
VSS
VDD
VDD
VSS
0.1 μF
VSS
VDD
VSS
VDD
VSS
0.1 μF
PIC32
AVDD
AVSS
0.1 μF
VDD
0.1 μF
VSS
VUSB3V3
VSS
VDD
VSS
0.1 μF
VDD
0.1 μF
0.1 μF
0.1 μF
Ferrite
Chips
VDD
0.01 μF
2011-2019 Microchip Technology Inc.
DS60001168L-page 35
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
NOTES:
DS60001168L-page 36
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
3.0
Note:
CPU
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS60001113), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32). Resources
for the MIPS32® M4K® Processor Core
are available at: www.imgtec.com.
The MIPS32® M4K® Processor Core is the heart of the
PIC32MX1XX/2XX family processor. The CPU fetches
instructions, decodes each instruction, fetches source
operands, executes each instruction and writes the
results of instruction execution to the destinations.
3.1
Features
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32 Enhanced Architecture (Release 2)
- Multiply-accumulate and multiply-subtract
instructions
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- Bit field manipulation instructions
FIGURE 3-1:
• MIPS16e® code compression
- 16-bit encoding of 32-bit instructions to
improve code density
- Special PC-relative instructions for efficient
loading of addresses and constants
- SAVE and RESTORE macro instructions for
setting up and tearing down stack frames
within subroutines
- Improved support for handling 8 and 16-bit
data types
• Simple Fixed Mapping Translation (FMT)
mechanism
• Simple dual bus interface
- Independent 32-bit address and data buses
- Transactions can be aborted to improve
interrupt latency
• Autonomous multiply/divide unit
- Maximum issue rate of one 32x16 multiply
per clock
- Maximum issue rate of one 32x32 multiply
every other clock
- Early-in iterative divide. Minimum 11 and
maximum 33 clock latency (dividend (rs) sign
extension-dependent)
• Power control
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
instruction)
- Extensive use of local gated clocks
• EJTAG debug and instruction trace
- Support for single stepping
- Virtual instruction and data address/value
- Breakpoints
MIPS32® M4K® PROCESSOR CORE BLOCK DIAGRAM
CPU
EJTAG
MDU
TAP
Execution Core
(RF/ALU/Shift)
System
Co-processor
2011-2019 Microchip Technology Inc.
FMT
Bus Interface
Off-chip Debug Interface
Dual Bus Interface
Bus Matrix
Power
Management
DS60001168L-page 37
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
3.2
Architecture Overview
3.2.2
The MIPS32 M4K processor core contains several
logic blocks working together in parallel, providing an
efficient high-performance computing engine. The
following blocks are included with the core:
•
•
•
•
•
•
•
•
Execution Unit
Multiply/Divide Unit (MDU)
System Control Coprocessor (CP0)
Fixed Mapping Translation (FMT)
Dual Internal Bus interfaces
Power Management
MIPS16e® Support
Enhanced JTAG (EJTAG) Controller
3.2.1
EXECUTION UNIT
The MIPS32 M4K processor core execution unit implements a load/store architecture with single-cycle ALU
operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two
32-bit General Purpose Registers (GPRs) used for
integer operations and address calculation. The register file consists of two read ports and one write port and
is fully bypassed to minimize operation latency in the
pipeline.
The execution unit includes:
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
address
• Logic for branch determination and branch target
address calculation
• Load aligner
• Bypass multiplexers used to avoid stalls when
executing instruction streams where data
producing instructions are followed closely by
consumers of their results
• Leading Zero/One detect unit for implementing
the CLZ and CLO instructions
• Arithmetic Logic Unit (ALU) for performing bitwise
logical operations
• Shifter and store aligner
TABLE 3-1:
MULTIPLY/DIVIDE UNIT (MDU)
The MIPS32 M4K processor core includes a Multiply/Divide Unit (MDU) that contains a separate pipeline
for multiply and divide operations. This pipeline operates in parallel with the Integer Unit (IU) pipeline and
does not stall when the IU pipeline stalls. This allows
MDU operations to be partially masked by system stalls
and/or other integer unit instructions.
The high-performance MDU consists of a 32x16 booth
recoded multiplier, result/accumulation registers (HI
and LO), a divide state machine, and the necessary
multiplexers and control logic. The first number shown
(‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
PIC32 core only checks the value of the latter (rt) operand to determine how many times the operation must
pass through the multiplier. The 16x16 and 32x16
operations pass through the multiplier once. A 32x32
operation passes through the multiplier twice.
The MDU supports execution of one 16x16 or 32x16
multiply operation every clock cycle; 32x32 multiply
operations can be issued every other clock cycle.
Appropriate interlocks are implemented to stall the
issuance of back-to-back 32x32 multiply operations.
The multiply operand size is automatically determined
by logic built into the MDU.
Divide operations are implemented with a simple 1 bit
per clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand.
If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit
wide rs, 15 iterations are skipped and for a 24-bit wide
rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active
causes an IU pipeline stall until the divide operation is
completed.
Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
MIPS32® M4K® PROCESSOR CORE HIGH-PERFORMANCE INTEGER
MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU
MUL
DIV/DIVU
DS60001168L-page 38
Operand Size (mul rt) (div rs)
Latency
Repeat Rate
16 bits
32 bits
16 bits
32 bits
8 bits
16 bits
24 bits
32 bits
1
2
2
3
12
19
26
33
1
2
1
2
11
18
25
32
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
The MIPS architecture defines that the result of a
multiply or divide operation be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be
transferred to the General Purpose Register file.
In addition to the HI/LO targeted operations, the
MIPS32® architecture also defines a multiply instruction, MUL, which places the least significant results in
the primary register file instead of the HI/LO register
pair. By avoiding the explicit MFLO instruction
required when using the LO register, and by supporting multiple destination registers, the throughput of
multiply-intensive operations is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
TABLE 3-2:
Register
Number
0-6
7
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
3.2.3
SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (Kernel, User and Debug) and
whether interrupts are enabled or disabled. Configuration information, such as presence of options like
MIPS16e, is also available by accessing the CP0
registers, listed in Table 3-2.
COPROCESSOR 0 REGISTERS
Register
Name
Function
Reserved
HWREna
Reserved in the PIC32MX1XX/2XX family core.
Enables access via the RDHWR instruction to selected hardware registers.
8
9
BadVAddr(1)
Count(1)
Reports the address for the most recent address-related exception.
Processor cycle count.
10
11
Reserved
Compare(1)
Reserved in the PIC32MX1XX/2XX family core.
Timer interrupt control.
12
12
Status(1)
IntCtl(1)
Processor status and control.
Interrupt system status and control.
12
12
SRSCtl(1)
SRSMap(1)
Shadow register set status and control.
Provides mapping from vectored interrupt to a shadow set.
13
14
Cause(1)
EPC(1)
Cause of last general exception.
Program counter at last exception.
15
15
PRId
EBASE
Processor identification and revision.
Exception vector base register.
16
16
Config
Config1
Configuration register.
Configuration Register 1.
16
16
Config2
Config3
Configuration Register 2.
Configuration Register 3.
17-22
23
Reserved
Debug(2)
Reserved in the PIC32MX1XX/2XX family core.
Debug control and exception status.
24
25-29
DEPC(2)
Reserved
Program counter at last debug exception.
Reserved in the PIC32MX1XX/2XX family core.
ErrorEPC(1)
DESAVE(2)
Program counter at last error.
Debug handler scratchpad register.
30
31
Note 1:
2:
Registers used in exception processing.
Registers used during debug.
2011-2019 Microchip Technology Inc.
DS60001168L-page 39
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events or program errors. Table 3-3 lists
the exception types in order of priority.
TABLE 3-3:
MIPS32® M4K® PROCESSOR CORE EXCEPTION TYPES
Exception
Description
Reset
Assertion MCLR or a Power-on Reset (POR).
DSS
EJTAG debug single step.
DINT
EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
NMI
Assertion of NMI signal.
Interrupt
Assertion of unmasked hardware or software interrupt signal.
DIB
EJTAG debug hardware instruction break matched.
AdEL
Fetch address alignment error.
Fetch reference to protected address.
IBE
Instruction fetch bus error.
DBp
EJTAG breakpoint (execution of SDBBP instruction).
Sys
Execution of SYSCALL instruction.
Bp
Execution of BREAK instruction.
RI
Execution of a reserved instruction.
CpU
Execution of a coprocessor instruction for a coprocessor that is not enabled.
CEU
Execution of a CorExtend instruction when CorExtend is not enabled.
Ov
Execution of an arithmetic instruction that overflowed.
Tr
Execution of a trap (when trap condition is true).
DDBL/DDBS
EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).
AdEL
Load address alignment error.
Load reference to protected address.
AdES
Store address alignment error.
Store to protected address.
DBE
Load or store bus error.
DDBL
EJTAG data hardware breakpoint matched in load data compare.
3.3
Power Management
The MIPS M4K processor core offers many power management features, including low-power design, active
power management and power-down modes of operation. The core is a static design that supports slowing or
Halting the clocks, which reduces system power consumption during Idle periods.
3.3.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 26.0
“Power-Saving Features”.
DS60001168L-page 40
3.4
EJTAG Debug Support
The MIPS M4K processor core provides an Enhanced
JTAG (EJTAG) interface for use in the software debug
of application and kernel code. In addition to standard
User mode and Kernel modes of operation, the M4K
core provides a Debug mode that is entered after a
debug exception (derived from a hardware breakpoint,
single-step exception, etc.) is taken and continues until
a Debug Exception Return (DERET) instruction is
executed. During this time, the processor executes the
debug exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for transferring test data in and out of the core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification define which
registers are selected and how they are used.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
4.0
Note:
MEMORY ORGANIZATION
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source.For
detailed information, refer to Section 3.
“Memory Organization” (DS60001115),
which
is
available
from
the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
PIC32MX1XX/2XX 28/36/44-pin Family microcontrollers provide 4 GB unified virtual memory address
space. All memory regions, including program, data
memory, Special Function Registers (SFRs), and Configuration registers, reside in this address space at their
respective unique addresses. The program and data
memories can be optionally partitioned into user and
kernel memories. In addition, the data memory can be
made executable, allowing PIC32MX1XX/2XX
28/36/44-pin Family devices to execute from data
memory.
4.1
PIC32MX1XX/2XX 28/36/44-pin
Family Memory Layout
PIC32MX1XX/2XX 28/36/44-pin Family microcontrollers implement two address schemes: virtual and physical. All hardware resources, such as program memory,
data memory and peripherals, are located at their
respective physical addresses. Virtual addresses are
exclusively used by the CPU to fetch and execute
instructions as well as access peripherals. Physical
addresses are used by bus master peripherals, such as
DMA and the Flash controller, that access memory
independently of the CPU.
The memory maps for the PIC32MX1XX/2XX
28/36/44-pin Family devices are illustrated in
Figure 4-1 through Figure 4-6.
Table 4-1 provides SFR memory map details.
Key features include:
• 32-bit native data width
• Separate User (KUSEG) and Kernel
(KSEG0/KSEG1) mode address space
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
program space
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
runaway code
• Simple memory mapping with Fixed Mapping
Translation (FMT) unit
• Cacheable (KSEG0) and non-cacheable (KSEG1)
address regions
2011-2019 Microchip Technology Inc.
DS60001168L-page 41
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX110/210 DEVICES (4 KB RAM, 16 KB FLASH)
Virtual
Memory Map(1)
0xFFFFFFFF
0xBFC00C00
0xBFC00BFF
0xBFC00BF0
Physical
Memory Map(1)
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC00BEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD004000
KSEG1
0xBF8FFFFF
Reserved
Reserved
0xBD003FFF
Program Flash(2)
0xBD000000
0xA0001000
Reserved
0xA0000FFF
RAM(2)
0xA0000000
0x9FC00C00
0x9FC00BFF
0x9FC00BF0
0x1FC00C00
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC00BFF
0x1FC00BF0
0x1FC00BEF
Boot Flash
0x1FC00000
0x9FC00BEF
Boot Flash
Reserved
0x9FC00000
0x1F900000
Reserved
0x9D004000
0x9D003FFF
KSEG0
0x1F8FFFFF
Program Flash(2)
SFRs
0x1F800000
Reserved
0x9D000000
0x80001000
0x1D004000
Reserved
0x1D003FFF
Program Flash(2)
0x1D000000
0x80000FFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
DS60001168L-page 42
Reserved
Reserved
RAM(2)
0x00001000
0x00000FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool
documentation for information).
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX120/220 DEVICES (8 KB RAM, 32 KB FLASH)
Virtual
Memory Map(1)
0xFFFFFFFF
0xBFC00C00
0xBFC00BFF
0xBFC00BF0
Physical
Memory Map(1)
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC00BEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
0xBF8FFFFF
Reserved
0xBD008000
Reserved
KSEG1
SFRs
0xBF800000
0xBD007FFF
Program Flash(2)
0xBD000000
0xA0002000
Reserved
0xA0001FFF
RAM(2)
0xA0000000
0x9FC00C00
0x9FC00BFF
0x9FC00BF0
0x1FC00C00
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC00BFF
0x1FC00BF0
0x1FC00BEF
Boot Flash
0x9FC00BEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x1F8FFFFF
0x9D007FFF
Program Flash(2)
SFRs
KSEG0
Reserved
0x9D008000
0x1F800000
Reserved
0x9D000000
0x80002000
0x1D008000
Reserved
0x1D007FFF
Program Flash(2)
0x1D000000
0x80001FFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
Reserved
Reserved
RAM(2)
0x00002000
0x00001FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool
documentation for information).
2011-2019 Microchip Technology Inc.
DS60001168L-page 43
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX130/230 DEVICES (16 KB RAM, 64 KB FLASH)
Virtual
Memory Map(1)
0xFFFFFFFF
0xBFC00C00
0xBFC00BFF
0xBFC00BF0
Physical
Memory Map(1)
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC00BEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD010000
KSEG1
0xBF8FFFFF
Reserved
Reserved
0xBD00FFFF
Program Flash(2)
0xBD000000
0xA0004000
Reserved
0xA0003FFF
RAM(2)
0xA0000000
0x9FC00C00
0x9FC00BFF
0x9FC00BF0
0x1FC00C00
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC00BFF
0x1FC00BF0
0x1FC00BEF
Boot Flash
0x1FC00000
0x9FC00BEF
Boot Flash
Reserved
0x9FC00000
0x1F900000
Reserved
0x9D010000
0x9D00FFFF
KSEG0
0x1F8FFFFF
Program Flash(2)
SFRs
0x1F800000
Reserved
0x9D000000
0x80004000
0x1D010000
Reserved
0x1D00FFFF
Program Flash(2)
0x1D000000
0x80003FFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
DS60001168L-page 44
Reserved
Reserved
RAM(2)
0x00004000
0x00003FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool
documentation for information).
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX150/250 DEVICES (32 KB RAM, 128 KB FLASH)
Virtual
Memory Map(1)
0xFFFFFFFF
0xBFC00C00
0xBFC00BFF
0xBFC00BF0
Physical
Memory Map(1)
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC00BEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD020000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD01FFFF
Program Flash(2)
0xBD000000
0xA0008000
Reserved
0xA0007FFF
RAM(2)
0xA0000000
0x9FC00C00
0x9FC00BFF
0x9FC00BF0
0x1FC00C00
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC00BFF
0x1FC00BF0
0x1FC00BEF
Boot Flash
0x9FC00BEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
Reserved
0x9D020000
0x9D01FFFF
KSEG0
0x1F8FFFFF
Program Flash(2)
SFRs
0x1F800000
Reserved
0x9D000000
0x80008000
0x1D020000
Reserved
0x1D01FFFF
Program Flash(2)
0x1D000000
0x80007FFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
Reserved
Reserved
RAM(2)
0x00008000
0x00007FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool
documentation for information).
2011-2019 Microchip Technology Inc.
DS60001168L-page 45
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX170/270 DEVICES (64 KB RAM, 256 KB FLASH)
Virtual
Memory Map(1)
0xFFFFFFFF
0xBFC00C00
0xBFC00BFF
0xBFC00BF0
Physical
Memory Map(1)
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC00BEF
Boot Flash
0xBFC00000
Reserved
0xBF900000
SFRs
0xBF800000
KSEG1
0xBF8FFFFF
Reserved
Reserved
0xBD040000
0xBD03FFFF
Program Flash(2)
0xBD000000
Reserved
0xA0010000
0xA000FFFF
RAM(2)
0xA0000000
0x1FC00C00
0x9FC00C00
0x9FC00BFF
0x9FC00BF0
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC00BFF
0x1FC00BF0
0x1FC00BEF
Boot Flash
0x1FC00000
0x9FC00BEF
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x9D040000
0x9D03FFFF
KSEG0
0x1F8FFFFF
Reserved
Program Flash(2)
SFRs
0x1F800000
Reserved
0x9D000000
0x80010000
0x1D040000
Reserved
0x1D03FFFF
Program Flash(2)
0x1D000000
0x8000FFFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
DS60001168L-page 46
Reserved
Reserved
RAM(2)
0x00010000
0x0000FFFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool
documentation for information).
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX130/230 DEVICES (16 KB RAM, 256 KB FLASH)
Virtual
Memory Map(1)
0xFFFFFFFF
0xBFC00C00
0xBFC00BFF
0xBFC00BF0
Physical
Memory Map(1)
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC00BEF
Boot Flash
0xBFC00000
Reserved
0xBF900000
SFRs
0xBF800000
KSEG1
0xBF8FFFFF
Reserved
Reserved
0xBD040000
0xBD03FFFF
Program Flash(2)
0xBD000000
Reserved
0xA0004000
0xA0003FFF
RAM(2)
0xA0000000
0x1FC00C00
0x9FC00C00
0x9FC00BFF
0x9FC00BF0
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC00BFF
0x1FC00BF0
0x1FC00BEF
Boot Flash
0x9FC00BEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x9D040000
0x9D03FFFF
KSEG0
0x1F8FFFFF
Reserved
Program Flash(2)
SFRs
0x1F800000
Reserved
0x9D000000
0x80004000
0x1D040000
Reserved
0x1D03FFFF
Program Flash(2)
0x1D000000
0x80003FFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
Reserved
Reserved
RAM(2)
0x00004000
0x00003FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool
documentation for information).
2011-2019 Microchip Technology Inc.
DS60001168L-page 47
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 4-1:
SFR MEMORY MAP
Virtual Address
Peripheral
Base
Offset
Start
Watchdog Timer
0x0000
RTCC
0x0200
Timer1-5
0x0600
Input Capture 1-5
0x2000
Output Compare 1-5
0x3000
IC1 and IC2
0x5000
SPI1 and SPI2
0x5800
UART1 and UART2
0x6000
PMP
ADC
0x7000
0xBF80
0x9000
CVREF
0x9800
Comparator
0xA000
CTMU
0xA200
Oscillator
0xF000
Device and Revision ID
0xF220
Peripheral Module Disable
0xF240
Flash Controller
0xF400
Reset
0xF600
PPS
0xFA04
Interrupts
0x1000
Bus Matrix
0x2000
DMA
0x3000
0xBF88
USB
0x5050
PORTA-PORTC
0x6000
Configuration
DS60001168L-page 48
0xBFC0
0x0BF0
2011-2019 Microchip Technology Inc.
Bus Matrix Control Registers
BMXCON(1)
2010 BMXDKPBA(1)
2020 BMXDUDBA(1)
2030 BMXDUPBA(1)
2040 BMXDRMSZ
2050 BMXPUPBA(1)
2060
BMXPFMSZ
2070 BMXBOOTSZ
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
31:16
15:0
31:16
15:0
—
—
—
BMXWSDRM
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
0000
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
19/3
18/2
17/1
16/0
BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F
BMXARB
0041
—
0000
BMXDUDBA
—
0000
BMXDUPBA
0000
xxxx
BMXDRMSZ
15:0
15:0
—
—
15:0
31:16
21/5
—
31:16
31:16
22/6
BMXDKPBA
15:0
31:16
20/4
All
Resets
Register
Name
2000
BUS MATRIX REGISTER MAP
Bit Range
Virtual Address
(BF88_#)
TABLE 4-2:
xxxx
—
—
—
—
—
—
—
—
—
—
BMXPUPBA
BMXPFMSZ
—
—
BMXPUPBA
0000
0000
xxxx
xxxx
BMXBOOTSZ
0000
0C00
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information.
DS60001168L-page 49
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2011-2019 Microchip Technology Inc.
4.2
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 4-1:
Bit
Range
BMXCON: BUS MATRIX CONFIGURATION REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
BMX
ERRICD
BMX
ERRDMA
BMX
ERRDS
BMX
ERRIS
U-0
31:24
23:16
15:8
7:0
—
—
—
BMX
ERRIXI
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-1
U-0
U-0
U-0
R/W-0
R/W-0
R/W-1
—
BMX
WSDRM
—
—
—
BMXARB
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-21 Unimplemented: Read as ‘0’
bit 20
BMXERRIXI: Enable Bus Error from IXI bit
1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus
0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus
bit 19
BMXERRICD: Enable Bus Error from ICD Debug Unit bit
1 = Enable bus error exceptions for unmapped address accesses initiated from ICD
0 = Disable bus error exceptions for unmapped address accesses initiated from ICD
bit 18
BMXERRDMA: Bus Error from DMA bit
1 = Enable bus error exceptions for unmapped address accesses initiated from DMA
0 = Disable bus error exceptions for unmapped address accesses initiated from DMA
bit 17
BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode)
1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access
0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access
bit 16
BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in Debug mode)
1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access
0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access
bit 15-7
Unimplemented: Read as ‘0’
bit 6
BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit
1 = Data RAM accesses from CPU have one wait state for address setup
0 = Data RAM accesses from CPU have zero wait states for address setup
bit 5-3
Unimplemented: Read as ‘0’
bit 2-0
BMXARB: Bus Matrix Arbitration Mode bits
111 = Reserved (using these Configuration modes will produce undefined behavior)
•
•
•
011 = Reserved (using these Configuration modes will produce undefined behavior)
010 = Arbitration Mode 2
001 = Arbitration Mode 1 (default)
000 = Arbitration Mode 0
DS60001168L-page 50
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 4-2:
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
BMXDKPBA
R-0
7:0
BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER
R-0
R-0
R-0
R-0
BMXDKPBA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDKPBA: DRM Kernel Program Base Address bits
When non-zero, this value selects the relative base address for kernel program space in RAM
bit 9-0
BMXDKPBA: Read-Only bits
This value is always ‘0’, which forces 1 KB increments
Note 1:
At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
The value in this register must be less than or equal to BMXDRMSZ.
2:
2011-2019 Microchip Technology Inc.
DS60001168L-page 51
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 4-3:
Bit
Range
31:24
23:16
15:8
7:0
BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
BMXDUDBA
R-0
R-0
BMXDUDBA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDUDBA: DRM User Data Base Address bits
When non-zero, the value selects the relative base address for User mode data space in RAM, the value
must be greater than BMXDKPBA.
bit 9-0
BMXDUDBA: Read-Only bits
This value is always ‘0’, which forces 1 KB increments
Note 1:
At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
The value in this register must be less than or equal to BMXDRMSZ.
2:
DS60001168L-page 52
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 4-4:
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
BMXDUPBA
R-0
7:0
BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER
R-0
R-0
R-0
R-0
BMXDUPBA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDUPBA: DRM User Program Base Address bits
When non-zero, the value selects the relative base address for User mode program space in RAM,
BMXDUPBA must be greater than BMXDUDBA.
bit 9-0
BMXDUPBA: Read-Only bits
This value is always ‘0’, which forces 1 KB increments
Note 1:
At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
The value in this register must be less than or equal to BMXDRMSZ.
2:
2011-2019 Microchip Technology Inc.
DS60001168L-page 53
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 4-5:
Bit
Range
31:24
23:16
15:8
7:0
BMXDRMSZ: DATA RAM SIZE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R
R
R
R
R
R
Bit
Bit
28/20/12/4 27/19/11/3
R
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R
R
R
R
R
R
R
R
R
R
R
R
R
BMXDRMSZ
R
R
BMXDRMSZ
R
R
R
R
R
R
R
R
BMXDRMSZ
R
R
BMXDRMSZ
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
BMXDRMSZ: Data RAM Memory (DRM) Size bits
Static value that indicates the size of the Data RAM in bytes:
0x00001000 = Device has 4 KB RAM
0x00002000 = Device has 8 KB RAM
0x00004000 = Device has 16 KB RAM
0x00008000 = Device has 32 KB RAM
0x00010000 = Device has 64 KB RAM
REGISTER 4-6:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
BMXPUPBA: PROGRAM FLASH (PFM) USER PROGRAM BASE ADDRESS
REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
BMXPUPBA
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
BMXPUPBA
R-0
R-0
BMXPUPBA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-20 Unimplemented: Read as ‘0’
bit 19-11 BMXPUPBA: Program Flash (PFM) User Program Base Address bits
bit 10-0
BMXPUPBA: Read-Only bits
This value is always ‘0’, which forces 2 KB increments
Note 1:
At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
The value in this register must be less than or equal to BMXPFMSZ.
2:
DS60001168L-page 54
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 4-7:
Bit
Range
31:24
23:16
15:8
7:0
BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R
R
R
Bit
Bit
28/20/12/4 27/19/11/3
R
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R
R
R
R
R
R
R
R
R
R
R
R
R
BMXPFMSZ
R
R
R
R
R
BMXPFMSZ
R
R
R
R
R
BMXPFMSZ
R
R
R
R
R
BMXPFMSZ
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
BMXPFMSZ: Program Flash Memory (PFM) Size bits
Static value that indicates the size of the PFM in bytes:
0x00004000 = Device has 16 KB Flash
0x00008000 = Device has 32 KB Flash
0x00010000 = Device has 64 KB Flash
0x00020000 = Device has 128 KB Flash
0x00040000 = Device has 256 KB Flash
REGISTER 4-8:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
BMXBOOTSZ: BOOT FLASH (IFM) SIZE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R
R
R
Bit
Bit
28/20/12/4 27/19/11/3
R
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R
R
R
R
R
R
R
R
R
R
R
R
R
BMXBOOTSZ
R
R
R
R
R
BMXBOOTSZ
R
R
R
R
R
BMXBOOTSZ
R
R
R
R
R
BMXBOOTSZ
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
BMXBOOTSZ: Boot Flash Memory (BFM) Size bits
Static value that indicates the size of the Boot PFM in bytes:
0x00000C00 = Device has 3 KB boot Flash
2011-2019 Microchip Technology Inc.
DS60001168L-page 55
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
NOTES:
DS60001168L-page 56
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
5.0
Note:
FLASH PROGRAM MEMORY
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 5. “Flash
Program Memory” (DS60001121), which
is available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
PIC32MX1XX/2XX 28/36/44-pin Family devices contain an internal Flash program memory for executing
user code. There are three methods by which the user
can program this memory:
• Run-Time Self-Programming (RTSP)
• EJTAG Programming
• In-Circuit Serial Programming™ (ICSP™)
2011-2019 Microchip Technology Inc.
RTSP is performed by software executing from either
Flash or RAM memory. Information about RTSP
techniques is available in Section 5. “Flash Program
Memory” (DS60001121) in the “PIC32 Family
Reference Manual”.
EJTAG is performed using the EJTAG port of the
device and an EJTAG capable programmer.
ICSP is performed using a serial data connection to the
device and allows much faster programming times than
RTSP.
The EJTAG and ICSP methods are described in the
“PIC32
Flash
Programming
Specification”
(DS60001145), which can be downloaded from the
Microchip web site.
Note:
The Flash page size on PIC32MX1XX/2XX 28/36/44-pin Family devices is 1
KB and the row size is 128 bytes (256 IW
and 32 IW, respectively).
DS60001168L-page 57
Flash Controller Control Registers
Virtual Address
(BF80_#)
Register
Name
TABLE 5-1:
F400
NVMCON(1)
F410
NVMKEY
F420
NVMADDR(1)
F430
NVMDATA
FLASH CONTROLLER REGISTER MAP
F440 NVMSRCADDR
31/15
30/14
29/13
31:16
—
—
—
15:0
WR
WREN
WRERR
31:16
15:0
31:16
15:0
31:16
15:0
31:16
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LVDERR LVDSTAT
NVMKEY
NVMADDR
NVMDATA
18/2
17/1
16/0
—
—
—
NVMOP
All Resets
Bit Range
Bits
0000
0000
0000
0000
0000
0000
0000
0000
0000
Legend:
NVMSRCADDR
15:0
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information.
0000
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 58
5.1
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 5-1:
Bit
Range
NVMCON: PROGRAMMING CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R-0
R-0
R-0
U-0
U-0
U-0
WR
WREN
WRERR(1)
U-0
U-0
U-0
U-0
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
LVDERR(1) LVDSTAT(1)
W = Writable bit
‘1’ = Bit is set
R/W-0
—
—
—
R/W-0
R/W-0
R/W-0
NVMOP
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
WR: Write Control bit
This bit is writable when WREN = 1 and the unlock sequence is followed.
1 = Initiate a Flash operation. Hardware clears this bit when the operation completes
0 = Flash operation is complete or inactive
bit 14
WREN: Write Enable bit
This is the only bit in this register reset by a device Reset.
1 = Enable writes to WR bit and enables LVD circuit
0 = Disable writes to WR bit and disables LVD circuit
bit 13
WRERR: Write Error bit(1)
This bit is read-only and is automatically set by hardware.
1 = Program or erase sequence did not complete successfully
0 = Program or erase sequence completed normally
bit 12
LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)(1)
This bit is read-only and is automatically set by hardware.
1 = Low-voltage detected (possible data corruption, if WRERR is set)
0 = Voltage level is acceptable for programming
bit 11
LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled)(1)
This bit is read-only and is automatically set and cleared by the hardware.
1 = Low-voltage event is active
0 = Low-voltage event is not active
bit 10-4 Unimplemented: Read as ‘0’
bit 3-0
NVMOP: NVM Operation bits
These bits are writable when WREN = 0.
1111 = Reserved
•
•
•
0111 = Reserved
0110 = No operation
0101 = Program Flash Memory (PFM) erase operation: erases PFM, if all pages are not write-protected
0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected
0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected
0010 = No operation
0001 = Word program operation: programs word selected by NVMADDR, if it is not write-protected
0000 = No operation
Note 1:
This bit is cleared by setting NVMOP == ‘b0000, and initiating a Flash operation (i.e., WR).
2011-2019 Microchip Technology Inc.
DS60001168L-page 59
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 5-2:
Bit
Range
31:24
23:16
15:8
7:0
NVMKEY: PROGRAMMING UNLOCK REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
W-0
W-0
W-0
Bit
Bit
28/20/12/4 27/19/11/3
W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY
W-0
NVMKEY
W-0
W-0
W-0
W-0
W-0
NVMKEY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
NVMKEY: Unlock Register bits
These bits are write-only, and read as ‘0’ on any read
This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.
REGISTER 5-3:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
NVMADDR: FLASH ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
NVMADDR: Flash Address bits
Bulk/Chip/PFM Erase: Address is ignored.
Page Erase: Address identifies the page to erase.
Row Program: Address identifies the row to program.
Word Program: Address identifies the word to program.
DS60001168L-page 60
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 5-4:
Bit
Range
31:24
23:16
15:8
7:0
NVMDATA: FLASH PROGRAM DATA REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
NVMDATA: Flash Programming Data bits
The bits in this register are only reset by a Power-on Reset (POR).
REGISTER 5-5:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
NVMSRCADDR: SOURCE DATA ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR
R/W-0
R/W-0
NVMSRCADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR
R/W-0
R/W-0
NVMSRCADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
NVMSRCADDR: Source Data Address bits
The system physical address of the data to be programmed into the Flash when the NVMOP bits
(NVMCON) are set to perform row programming.
2011-2019 Microchip Technology Inc.
DS60001168L-page 61
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
NOTES:
DS60001168L-page 62
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
6.0
Note:
RESETS
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 7. “Resets”
(DS60001118), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
FIGURE 6-1:
The Reset module combines all Reset sources and
controls the device Master Reset signal, SYSRST. The
following is a list of device Reset sources:
•
•
•
•
•
•
Power-on Reset (POR)
Master Clear Reset pin (MCLR)
Software Reset (SWR)
Watchdog Timer Reset (WDTR)
Brown-out Reset (BOR)
Configuration Mismatch Reset (CMR)
A simplified block diagram of the Reset module is
illustrated in Figure 6-1.
SYSTEM RESET BLOCK DIAGRAM
MCLR
Glitch Filter
Sleep or Idle
WDTR
WDT
Time-out
Voltage
Regulator
Enabled
VDD
MCLR
Power-up
Timer
POR
Brown-out
Reset
BOR
SYSRST
VDD Rise
Detect
Configuration
Mismatch
Reset
Software Reset
2011-2019 Microchip Technology Inc.
CMR
SWR
DS60001168L-page 63
Reset Control Registers
Virtual Address
(BF80_#)
Register
Name(1)
TABLE 6-1:
F600
RCON
Legend:
1:
2:
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
CMR
—
VREGS
—
31:16
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
0000
EXTR
—
SWR
—
—
—
WDTO
—
SLEEP
—
IDLE
—
BOR
—
POR
—
xxxx(2)
0000
—
—
—
—
—
—
SWRST
0000
15:0
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Bits
F610 RSWRST
Note
RESET CONTROL REGISTER MAP
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 64
6.1
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 6-1:
Bit
Range
31:24
23:16
15:8
7:0
RCON: RESET CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
U-0
U-0
U-0
R/W-0, HS
R/W-0
—
—
—
—
—
—
CMR
VREGS
R/W-0, HS
R/W-0, HS
U-0
R/W-0, HS
R/W-0, HS
R/W-0, HS
EXTR
SWR
—
WDTO
SLEEP
IDLE
R/W-1, HS
(1)
R/W-1, HS
(1)
BOR
Legend:
HS = Set by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
POR
x = Bit is unknown
bit 31-10 Unimplemented: Read as ‘0’
bit 9
CMR: Configuration Mismatch Reset Flag bit
1 = Configuration mismatch Reset has occurred
0 = Configuration mismatch Reset has not occurred
bit 8
VREGS: Voltage Regulator Standby Enable bit
1 = Regulator is enabled and is on during Sleep mode
0 = Regulator is set to standby tracking mode
bit 7
EXTR: External Reset (MCLR) Pin Flag bit
1 = Master Clear (pin) Reset has occurred
0 = Master Clear (pin) Reset has not occurred
bit 6
SWR: Software Reset Flag bit
1 = Software Reset was executed
0 = Software Reset as not executed
bit 5
Unimplemented: Read as ‘0’
bit 4
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT Time-out has occurred
0 = WDT Time-out has not occurred
bit 3
SLEEP: Wake From Sleep Flag bit
1 = Device was in Sleep mode
0 = Device was not in Sleep mode
bit 2
IDLE: Wake From Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
bit 1
BOR: Brown-out Reset Flag bit(1)
1 = Brown-out Reset has occurred
0 = Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit(1)
1 = Power-on Reset has occurred
0 = Power-on Reset has not occurred
Note 1:
User software must clear this bit to view next detection.
2011-2019 Microchip Technology Inc.
DS60001168L-page 65
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 6-2:
Bit
Range
31:24
23:16
15:8
7:0
RSWRST: SOFTWARE RESET REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
W-0, HC
—
—
—
—
—
—
—
SWRST(1)
Legend:
HC = Cleared by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-1
Unimplemented: Read as ‘0’
bit 0
SWRST: Software Reset Trigger bit(1)
1 = Enable Software Reset event
0 = No effect
Note 1:
The system unlock sequence must be performed before the SWRST bit is written. Refer to Section 6.
“Oscillator” (DS60001112) in the “PIC32 Family Reference Manual” for details.
DS60001168L-page 66
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
7.0
Note:
INTERRUPT CONTROLLER
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Interrupt Controller” (DS60001108), which is available
from the Documentation > Reference
Manual section of the Microchip PIC32
web site (www.microchip.com/pic32).
PIC32MX1XX/2XX 28/36/44-pin Family devices generate interrupt requests in response to interrupt events
from peripheral modules. The interrupt control module
exists externally to the CPU logic and prioritizes the
interrupt events before presenting them to the CPU.
The PIC32MX1XX/2XX 28/36/44-pin Family interrupt
module includes the following features:
•
•
•
•
Up to 64 interrupt sources
Up to 44 interrupt vectors
Single and multi-vector mode operations
Five external interrupts with edge polarity control
Interrupt proximity timer
Seven user-selectable priority levels for each
vector
Four user-selectable subpriority levels within each
priority
Software can generate any interrupt
User-configurable Interrupt Vector Table (IVT)
location
User-configurable interrupt vector spacing
Note:
The dedicated shadow register set is not
present on PIC32MX1XX/2XX 28/36/44pin Family devices.
A simplified block diagram of the Interrupt Controller
module is illustrated in Figure 7-1.
INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM
Interrupt Requests
FIGURE 7-1:
•
•
•
•
•
•
Vector Number
Interrupt Controller
2011-2019 Microchip Technology Inc.
CPU Core
Priority Level
DS60001168L-page 67
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION
Interrupt Source(1)
IRQ Vector
#
#
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
IPC0
No
Highest Natural Order Priority
CT – Core Timer Interrupt
0
0
IFS0
IEC0
IPC0
CS0 – Core Software Interrupt 0
1
1
IFS0
IEC0
IPC0
IPC0
No
CS1 – Core Software Interrupt 1
2
2
IFS0
IEC0
IPC0
IPC0
No
INT0 – External Interrupt
3
3
IFS0
IEC0
IPC0
IPC0
No
T1 – Timer1
4
4
IFS0
IEC0
IPC1
IPC1
No
IC1E – Input Capture 1 Error
5
5
IFS0
IEC0
IPC1
IPC1
Yes
IC1 – Input Capture 1
6
5
IFS0
IEC0
IPC1
IPC1
Yes
OC1 – Output Compare 1
7
6
IFS0
IEC0
IPC1
IPC1
No
INT1 – External Interrupt 1
8
7
IFS0
IEC0
IPC1
IPC1
No
T2 – Timer2
9
8
IFS0
IEC0
IPC2
IC2E – Input Capture 2
10
9
IFS0 IEC0 IPC2
IPC2
No
IPC2
Yes
IC2 – Input Capture 2
11
9
IFS0 IEC0 IPC2
IPC2
Yes
OC2 – Output Compare 2
12
10
IFS0 IEC0 IPC2
IPC2
No
INT2 – External Interrupt 2
13
11
IFS0 IEC0 IPC2
IPC2
No
T3 – Timer3
14
12
IFS0 IEC0
IPC3
No
IC3E – Input Capture 3
15
13
IFS0 IEC0 IPC3
IPC3
Yes
IC3 – Input Capture 3
16
13
IFS0 IEC0 IPC3
IPC3
Yes
OC3 – Output Compare 3
17
14
IFS0 IEC0 IPC3
IPC3
No
INT3 – External Interrupt 3
18
15
IFS0 IEC0 IPC3
IPC3
No
IPC3
T4 – Timer4
19
16
IFS0 IEC0
IC4E – Input Capture 4 Error
20
17
IFS0 IEC0 IPC4
IPC4
IPC4
No
IPC4
Yes
IC4 – Input Capture 4
21
17
IFS0 IEC0 IPC4
IPC4
Yes
OC4 – Output Compare 4
22
18
IFS0 IEC0 IPC4
IPC4
No
INT4 – External Interrupt 4
23
19
IFS0 IEC0 IPC4
IPC4
No
T5 – Timer5
24
20
IFS0 IEC0
IPC5
No
IC5E – Input Capture 5 Error
25
21
IFS0 IEC0 IPC5
IPC5
Yes
IC5 – Input Capture 5
26
21
IFS0 IEC0 IPC5
IPC5
Yes
OC5 – Output Compare 5
27
22
IFS0 IEC0 IPC5
IPC5
No
AD1 – ADC1 Convert done
28
23
IFS0 IEC0 IPC5
IPC5
Yes
FSCM – Fail-Safe Clock Monitor
29
24
IFS0 IEC0
IPC6
No
RTCC – Real-Time Clock and
Calendar
30
25
IFS0 IEC0 IPC6
IPC6
No
FCE – Flash Control Event
31
26
IFS0 IEC0 IPC6
IPC6
No
CMP1 – Comparator Interrupt
32
27
IFS1
IEC1
IPC6
IPC6
No
CMP2 – Comparator Interrupt
33
28
IFS1
IEC1
IPC7
IPC7
No
CMP3 – Comparator Interrupt
34
29
IFS1
IEC1
IPC7
IPC7
No
USB – USB Interrupts
35
30
IFS1
IEC1
IPC7
IPC7
Yes
IPC5
IPC6
SPI1E – SPI1 Fault
36
31
IFS1
IEC1
IPC7
IPC7
Yes
SPI1RX – SPI1 Receive Done
37
31
IFS1
IEC1
IPC7
IPC7
Yes
SPI1TX – SPI1 Transfer Done
38
31
IFS1
IEC1
IPC7
IPC7
Yes
Note 1:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX1XX 28/36/44-Pin General
Purpose Family Features” and TABLE 2: “PIC32MX2XX 28/36/44-pin USB Family Features” for the
lists of available peripherals.
DS60001168L-page 68
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
IRQ Vector
#
#
32
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
IFS1
IEC1
IPC8
IPC8
Yes
U1E – UART1 Fault
39
U1RX – UART1 Receive Done
40
32
IFS1
IEC1
IPC8
IPC8
Yes
U1TX – UART1 Transfer Done
41
32
IFS1
IEC1
IPC8
IPC8
Yes
I2C1B – I2C1 Bus Collision Event
42
33
IFS1 IEC1 IPC8
IPC8
Yes
I2C1S – I2C1 Slave Event
43
33
IFS1 IEC1 IPC8
IPC8
Yes
I2C1M – I2C1 Master Event
44
33
IFS1 IEC1 IPC8
IPC8
Yes
CNA – PORTA Input Change
Interrupt
45
34
IFS1 IEC1 IPC8
IPC8
Yes
CNB – PORTB Input Change
Interrupt
46
34
IFS1 IEC1 IPC8
IPC8
Yes
CNC – PORTC Input Change
Interrupt
47
34
IFS1 IEC1 IPC8
IPC8
Yes
PMP – Parallel Master Port
48
35
IFS1 IEC1 IPC8
IPC8
Yes
PMPE – Parallel Master Port Error
49
35
IFS1 IEC1 IPC8
IPC8
Yes
SPI2E – SPI2 Fault
50
36
IFS1 IEC1
IPC9
IPC9
Yes
SPI2RX – SPI2 Receive Done
51
36
IFS1 IEC1
IPC9
IPC9
Yes
SPI2TX – SPI2 Transfer Done
52
36
IFS1 IEC1
IPC9
IPC9
Yes
U2E – UART2 Error
53
37
IFS1 IEC1 IPC9
IPC9
Yes
U2RX – UART2 Receiver
54
37
IFS1 IEC1 IPC9
IPC9
Yes
U2TX – UART2 Transmitter
55
37
IFS1 IEC1 IPC9
IPC9
Yes
I2C2B – I2C2 Bus Collision Event
56
38
IFS1 IEC1 IPC9
IPC9
Yes
I2C2S – I2C2 Slave Event
57
38
IFS1 IEC1 IPC9
IPC9
Yes
I2C2M – I2C2 Master Event
58
38
IFS1 IEC1 IPC9
IPC9
Yes
CTMU – CTMU Event
59
39
IFS1 IEC1 IPC9
IPC9
Yes
DMA0 – DMA Channel 0
60
40
IFS1 IEC1
IPC10
No
DMA1 – DMA Channel 1
61
41
IFS1 IEC1 IPC10
IPC10
No
DMA2 – DMA Channel 2
62
42
IFS1 IEC1 IPC10 IPC10
No
DMA3 – DMA Channel 3
63
43
IFS1 IEC1 IPC10 IPC10
No
IPC10
Lowest Natural Order Priority
Note 1:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX1XX 28/36/44-Pin General
Purpose Family Features” and TABLE 2: “PIC32MX2XX 28/36/44-pin USB Family Features” for the
lists of available peripherals.
2011-2019 Microchip Technology Inc.
DS60001168L-page 69
Interrupt Control Registers
Virtual Address
(BF88_#)
Register
Name(1)
TABLE 7-2:
1000
INTCON
INTERRUPT REGISTER MAP
1010 INTSTAT(3)
1020
IPTMR
1030
IFS0
1040
IFS1
1060
IEC0
1070
IEC1
1090
IPC0
10A0
IPC1
10B0
IPC2
2011-2019 Microchip Technology Inc.
10C0
IPC3
10D0
IPC4
10E0
IPC5
10F0
IPC6
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
—
15:0
—
—
—
—
—
—
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
—
INT4EP
INT3EP
—
—
—
—
—
—
—
TPC
—
—
—
SRIPL
31:16
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Bits
—
—
—
0000
INT2EP INT1EP INT0EP
—
—
—
VEC
0000
0000
IPTMR
15:0
0000
0000
0000
31:16
FCEIF
RTCCIF
FSCMIF
AD1IF
OC5IF
IC5IF
IC5EIF
T5IF
INT4IF
OC4IF
IC4IF
IC4EIF
T4IF
INT3IF
OC3IF
IC3IF
0000
15:0
IC3EIF
T3IF
INT2IF
OC2IF
IC2IF
IC2EIF
T2IF
INT1IF
OC1IF
IC1IF
IC1EIF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
DMA2IF
DMA1IF
DMA0IF
CTMUIF
I2C2MIF
I2C2SIF
I2C2BIF
U2TXIF
U2RXIF
U2EIF
CNCIF
CNBIF
CNAIF
I2C1MIF
I2C1SIF
I2C1BIF
U1TXIF
U1RXIF
U1EIF
SPI1TXIF
SPI1RXIF
SPI1EIF
31:16
FCEIE
RTCCIE
FSCMIE
AD1IE
OC5IE
IC5IE
IC5EIE
T5IE
INT4IE
OC4IE
IC4IE
IC4EIE
T4IE
INT3IE
OC3IE
IC3IE
0000
15:0
IC3EIE
T3IE
INT2IE
OC2IE
IC2IE
IC2EIE
T2IE
INT1IE
OC1IE
IC1IE
IC1EIE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
0000
31:16 DMA3IF
15:0
31:16 DMA3IE
DMA2IE
DMA1IE
DMA0IE
CTMUIE
I2C2MIE
I2C2SIE
I2C2BIE
U2TXIE
U2RXIE
U2EIE
15:0
CNCIE
CNBIE
CNAIE
I2C1MIE
I2C1SIE
I2C1BIE
U1TXIE
U1RXIE
U1EIE
SPI1TXIE
SPI1RXIE
31:16
—
—
—
INT0IS
—
—
—
INT0IP
SPI2TXIF SPI2RXIF SPI2EIF PMPEIF PMPIF
USBIF(2) CMP3IF CMP2IF CMP1IF
SPI2TXIE SPI2RXIE SPI2EIE PMPEIE PMPIE
SPI1EIE
USBIE(2) CMP3IE CMP2IE CMP1IE
CS1IP
0000
0000
0000
0000
CS1IS
0000
15:0
—
—
—
CS0IP
CS0IS
—
—
—
CTIP
CTIS
0000
31:16
—
—
—
INT1IP
INT1IS
—
—
—
OC1IP
OC1IS
0000
15:0
—
—
—
IC1IP
IC1IS
—
—
—
T1IP
T1IS
0000
31:16
—
—
—
INT2IP
INT2IS
—
—
—
OC2IP
OC2IS
0000
15:0
—
—
—
IC2IP
IC2IS
—
—
—
T2IP
T2IS
0000
31:16
—
—
—
INT3IP
INT3IS
—
—
—
OC3IP
OC3IS
0000
15:0
—
—
—
IC3IP
IC3IS
—
—
—
T3IP
T3IS
0000
31:16
—
—
—
INT4IP
INT4IS
—
—
—
OC4IP
OC4IS
0000
15:0
—
—
—
IC4IP
IC4IS
—
—
—
T4IP
T4IS
0000
31:16
—
—
—
AD1IP
AD1IS
—
—
—
OC5IP
OC5IS
0000
15:0
—
—
—
IC5IP
IC5IS
—
—
—
T5IP
T5IS
0000
31:16
—
—
—
CMP1IP
CMP1IS
—
—
—
FCEIP
FCEIS
0000
15:0
—
—
—
RTCCIP
RTCCIS
—
—
—
FSCMIP
FSCMIS
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 11.2 “CLR,
SET and INV Registers” for more information.
These bits are not available on PIC32MX1XX devices.
This register does not have associated CLR, SET, INV registers.
2:
3:
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 70
7.1
Virtual Address
(BF88_#)
Register
Name(1)
1100
IPC7
1110
IPC8
INTERRUPT REGISTER MAP (CONTINUED)
1120
IPC9
1130
IPC10
31/15
30/14
29/13
28/12
27/11
31:16
—
—
—
SPI1IP
15:0
—
—
—
CMP3IP
31:16
—
—
—
PMPIP
15:0
—
—
—
I2C1IP
31:16
—
—
—
15:0
—
—
31:16
—
15:0
—
26/10
25/9
24/8
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
Bits
23/7
22/6
21/5
SPI1IS
—
—
—
USBIP(2)
USBIS(2)
0000
CMP3IS
—
—
—
CMP2IP
CMP2IS
0000
PMPIS
—
—
—
CNIP
CNIS
0000
I2C1IS
—
—
—
U1IP
U1IS
0000
CTMUIP
CTMUIS
—
—
—
I2C2IP
I2C2IS
0000
—
U2IP
U2IS
—
—
—
SPI2IP
SPI2IS
0000
—
—
DMA3IP
DMA3IS
—
—
—
DMA2IP
DMA2IS
0000
—
—
DMA1IP
DMA1IS
—
—
—
DMA0IP
DMA0IS
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 11.2 “CLR,
SET and INV Registers” for more information.
These bits are not available on PIC32MX1XX devices.
This register does not have associated CLR, SET, INV registers.
2:
3:
DS60001168L-page 71
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2011-2019 Microchip Technology Inc.
TABLE 7-2:
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 7-1:
Bit
Range
31:24
23:16
15:8
7:0
INTCON: INTERRUPT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
MVEC
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
TPC
R/W-0
R/W-0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-13 Unimplemented: Read as ‘0’
bit 12
bit 11
bit 10-8
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
MVEC: Multi Vector Configuration bit
1 = Interrupt controller configured for Multi-vectored mode
0 = Interrupt controller configured for Single-vectored mode
Unimplemented: Read as ‘0’
TPC: Interrupt Proximity Timer Control bits
111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer
110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer
101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer
100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer
011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer
010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer
001 = Interrupts of group priority 1 start the Interrupt Proximity timer
000 = Disables Interrupt Proximity timer
Unimplemented: Read as ‘0’
INT4EP: External Interrupt 4 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
INT3EP: External Interrupt 3 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
INT2EP: External Interrupt 2 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
INT1EP: External Interrupt 1 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
INT0EP: External Interrupt 0 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
DS60001168L-page 72
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 7-2:
Bit
Range
31:24
23:16
15:8
7:0
INTSTAT: INTERRUPT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
SRIPL(1)
R/W-0
R/W-0
R/W-0
VEC(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10-8 SRIPL: Requested Priority Level bits(1)
111-000 = The priority level of the latest interrupt presented to the CPU
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
VEC: Interrupt Vector bits(1)
11111-00000 = The interrupt vector that is presented to the CPU
Note 1:
This value should only be used when the interrupt controller is configured for Single Vector mode.
REGISTER 7-3:
Bit
Range
31:24
23:16
15:8
7:0
IPTMR: INTERRUPT PROXIMITY TIMER REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR
R/W-0
IPTMR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
IPTMR: Interrupt Proximity Timer Reload bits
Used by the Interrupt Proximity Timer as a reload value when the Interrupt Proximity timer is triggered by
an interrupt event.
2011-2019 Microchip Technology Inc.
DS60001168L-page 73
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 7-4:
Bit
Range
31:24
23:16
15:8
7:0
IFSx: INTERRUPT FLAG STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS31
IFS30
IFS29
R/W-0
R/W-0
R/W-0
IFS28
IFS27
IFS26
IFS25
IFS24
R/W-0
R/W-0
R/W-0
R/W-0
IFS23
IFS22
IFS21
R/W-0
IFS20
IFS19
IFS18
IFS17
IFS16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS15
IFS14
IFS13
IFS12
IFS11
IFS10
IFS09
IFS08
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS07
IFS06
IFS05
IFS04
IFS03
IFS02
IFS01
IFS00
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
Note:
31:24
23:16
15:8
7:0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
IFS31-IFS00: Interrupt Flag Status bits
1 = Interrupt request has occurred
0 = No interrupt request has occurred
This register represents a generic definition of the IFSx register. Refer to Table 7-1 for the exact bit
definitions.
REGISTER 7-5:
Bit
Range
W = Writable bit
‘1’ = Bit is set
Bit
31/23/15/7
IECx: INTERRUPT ENABLE CONTROL REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC31
IEC30
IEC29
IEC28
IEC27
IEC26
IEC25
IEC24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC23
IEC22
IEC21
IEC20
IEC19
IEC18
IEC17
IEC16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC15
IEC14
IEC13
IEC12
IEC11
IEC10
IEC09
IEC08
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC07
IEC06
IEC05
IEC04
IEC03
IEC02
IEC01
IEC00
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
Note:
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
IEC31-IEC00: Interrupt Enable bits
1 = Interrupt is enabled
0 = Interrupt is disabled
This register represents a generic definition of the IECx register. Refer to Table 7-1 for the exact bit
definitions.
DS60001168L-page 74
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 7-6:
Bit
Range
IPCx: INTERRUPT PRIORITY CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
31:24
23:16
15:8
7:0
Legend:
R = Readable bit
-n = Value at POR
Bit
Bit
28/20/12/4 27/19/11/3
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
IP03
R/W-0
R/W-0
IS03
R/W-0
IP02
R/W-0
R/W-0
R/W-0
IP00
R/W-0
IS02
R/W-0
IP01
R/W-0
R/W-0
R/W-0
R/W-0
IS01
R/W-0
R/W-0
R/W-0
IS00
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-26 IP03: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 25-24 IS03: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
bit 23-21 Unimplemented: Read as ‘0’
bit 20-18 IP02: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 17-16 IS02: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
bit 15-13 Unimplemented: Read as ‘0’
bit 12-10 IP01: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
Note:
This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit
definitions.
2011-2019 Microchip Technology Inc.
DS60001168L-page 75
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 7-6:
bit 9-8
bit 7-5
bit 4-2
IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED)
IS01: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
Unimplemented: Read as ‘0’
IP00: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
bit 1-0
Note:
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
IS00: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit
definitions.
DS60001168L-page 76
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
8.0
Note:
OSCILLATOR
CONFIGURATION
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 6. “Oscillator
Configuration” (DS60001112), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The PIC32MX1XX/2XX 28/36/44-pin Family oscillator
system has the following modules and features:
• Four external and internal oscillator options as
clock sources
• On-Chip PLL with user-selectable input divider,
multiplier and output divider to boost operating
frequency on select internal and external
oscillator sources
• On-Chip user-selectable divisor postscaler on
select oscillator sources
• Software-controllable switching between
various clock sources
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and permits safe application recovery
or shutdown
• Dedicated On-Chip PLL for USB peripheral
A block diagram of the oscillator system is provided in
Figure 8-1.
2011-2019 Microchip Technology Inc.
DS60001168L-page 77
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 8-1:
OSCILLATOR DIAGRAM
USB PLL(4)
USB Clock (48 MHz)
div x
UFIN
div 2
PLL x24
UFRCEN
UPLLEN
UFIN 4 MHz
UPLLIDIV
ROTRIM
(M)
REFCLKI
POSC
FRC
LPRC
SOSC
PBCLK
SYSCLK
System PLL
4 MHz FIN 5 MHz
FIN
div x
PLL
REFCLKO
M
2 N + --------512
To SPI
RODIV
(N)
ROSEL
FPLLIDIV
COSC
OE
PLLMULT
div y
XTPLL, HSPLL,
ECPLL, FRCPLL
PLLODIV
Primary Oscillator (POSC)
C1(2)
OSC1
XTAL
RP(1)
C2(2)
POSC (XT, HS, EC)
To Internal
Logic
HS
3x
1x
XT
FRC
RS(1) OSC2(3)
div 16
div 2
PBDIV
FRC/16
To ADC
Secondary Oscillator (SOSC)
SOSCO
Postscaler Peripherals
div x
PBCLK (TPB)
CPU and Select Peripherals
FRC
Oscillator
8 MHz typical
Postscaler
TUN
FRCDIV
SYSCLK
FRCDIV
32.768 kHz
SOSC
SOSCEN and FSOSCEN
LPRC
Oscillator
SOSCI
31.25 kHz typical
LPRC
Clock Control Logic
Fail-Safe
Clock
Monitor
FSCM INT
FSCM Event
NOSC
COSC
OSWEN
FSCMEN
WDT, PWRT
Timer1, RTCC
Notes:
1.
2.
3.
4.
A series resistor, RS, may be required for AT strip cut crystals or eliminate clipping. Alternately, to increase oscillator circuit gain,
add a parallel resistor, RP, with a value of 1 M
Refer to Section 6. “Oscillator Configuration” (DS60001112) in the “PIC32 Family Reference Manual” for help in determining the
best oscillator components.
The PBCLK out is only available on the OSC2 pin in certain clock modes.
The USB PLL is only available on PIC32MX2XX devices.
DS60001168L-page 78
2011-2019 Microchip Technology Inc.
Oscillator Control Regiters
Virtual Address
(BF80_#)
TABLE 8-1:
OSCILLATOR CONTROL REGISTER MAP
F000 OSCCON
F010 OSCTUN
F020 REFOCON
F030 REFOTRIM
Legend:
Note 1:
2:
3:
31/15
30/14
31:16
—
—
15:0
—
—
29/13
28/12
27/11
26/10
PLLODIV
—
—
NOSC
—
—
—
—
—
—
—
31:16
—
—
15:0
ON
—
SIDL
OE
RSLP
—
15:0
—
31:16
15:0
24/8
FRCDIV
—
—
31:16
COSC
—
25/9
23/7
—
—
—
DIVSWEN ACTIVE
—
—
—
—
—
—
—
21/5
SOSCRDY PBDIVRDY
CLKLOCK ULOCK(3)
—
—
SLOCK
—
20/4
19/3
—
—
18/2
PBDIV
SLPEN
—
17/1
16/0
x1xx(2)
PLLMULT
CF
—
—
—
RODIV
ROTRIM
—
22/6
UFRCEN(3) SOSCEN
—
—
All Resets
Bit Range
Register
Name(1)
Bits
OSWEN
—
TUN
xxxx(2)
0000
0000
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
ROSEL
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
This bit is only available on PIC32MX2XX devices.
DS60001168L-page 79
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2011-2019 Microchip Technology Inc.
8.1
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 8-1:
Bit
Range
31:24
23:16
15:8
7:0
OSCCON: OSCILLATOR CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
R/W-y
—
—
U-0
R-0
—
U-0
R/W-y
R-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-y
R/W-0
R/W-0
R/W-1
R/W-y
R/W-y
PLLODIV
R-1
SOSCRDY PBDIVRDY
—
Bit
Bit
28/20/12/4 27/19/11/3
R-0
R/W-y
FRCDIV
PBDIV
R-0
U-0
COSC
R/W-y
R/W-y
PLLMULT
R/W-y
—
R/W-y
R/W-y
NOSC
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-y
R/W-0
CLKLOCK
ULOCK(1)
SLOCK
SLPEN
CF
UFRCEN(1)
SOSCEN
OSWEN
Legend:
R = Readable bit
y = Value set from Configuration bits on POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-27 PLLODIV: Output Divider for PLL
111 = PLL output divided by 256
110 = PLL output divided by 64
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 1
bit 26-24 FRCDIV: Internal Fast RC (FRC) Oscillator Clock Divider bits
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2 (default setting)
000 = FRC divided by 1
bit 23
Unimplemented: Read as ‘0’
bit 22
bit 21
SOSCRDY: Secondary Oscillator (SOSC) Ready Indicator bit
1 = The Secondary Oscillator is running and is stable
0 = The Secondary Oscillator is still warming up or is turned off
PBDIVRDY: Peripheral Bus Clock (PBCLK) Divisor Ready bit
1 = PBDIV bits can be written
0 = PBDIV bits cannot be written
bit 20-19 PBDIV: Peripheral Bus Clock (PBCLK) Divisor bits
11 = PBCLK is SYSCLK divided by 8 (default)
10 = PBCLK is SYSCLK divided by 4
01 = PBCLK is SYSCLK divided by 2
00 = PBCLK is SYSCLK divided by 1
Note 1:
Note:
This bit is only available on PIC32MX2XX devices.
Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
DS60001168L-page 80
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 8-1:
OSCCON: OSCILLATOR CONTROL REGISTER
bit 18-16 PLLMULT: Phase-Locked Loop (PLL) Multiplier bits
111 = Clock is multiplied by 24
110 = Clock is multiplied by 21
101 = Clock is multiplied by 20
100 = Clock is multiplied by 19
011 = Clock is multiplied by 18
010 = Clock is multiplied by 17
001 = Clock is multiplied by 16
000 = Clock is multiplied by 15
bit 15
Unimplemented: Read as ‘0’
bit 14-12 COSC: Current Oscillator Selection bits
111 = Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (OSCCON)
110 = Internal Fast RC (FRC) Oscillator divided by 16
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator (POSC) with PLL module (XTPLL, HSPLL or ECPLL)
010 = Primary Oscillator (POSC) (XT, HS or EC)
001 = Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL)
000 = Internal Fast RC (FRC) Oscillator
bit 11
bit 10-8
Unimplemented: Read as ‘0’
NOSC: New Oscillator Selection bits
111 = Internal Fast RC Oscillator (FRC) divided by OSCCON bits
110 = Internal Fast RC Oscillator (FRC) divided by 16
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL)
010 = Primary Oscillator (XT, HS or EC)
001 = Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL)
000 = Internal Fast Internal RC Oscillator (FRC)
On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1).
bit 7
CLKLOCK: Clock Selection Lock Enable bit
If clock switching and monitoring is disabled (FCKSM = 1x):
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified
If clock switching and monitoring is enabled (FCKSM = 0x):
Clock and PLL selections are never locked and may be modified.
bit 6
ULOCK: USB PLL Lock Status bit(1)
1 = The USB PLL module is in lock or USB PLL module start-up timer is satisfied
0 =The USB PLL module is out of lock or USB PLL module start-up timer is in progress or the USB PLL is
disabled
bit 5
SLOCK: PLL Lock Status bit
1 = The PLL module is in lock or PLL module start-up timer is satisfied
0 = The PLL module is out of lock, the PLL start-up timer is running, or the PLL is disabled
SLPEN: Sleep Mode Enable bit
1 = The device will enter Sleep mode when a WAIT instruction is executed
0 = The device will enter Idle mode when a WAIT instruction is executed
bit 4
Note 1:
Note:
This bit is only available on PIC32MX2XX devices.
Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
2011-2019 Microchip Technology Inc.
DS60001168L-page 81
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 8-1:
OSCCON: OSCILLATOR CONTROL REGISTER
bit 3
CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
bit 2
UFRCEN: USB FRC Clock Enable bit(1)
1 = Enable the FRC as the clock source for the USB clock source
0 = Use the Primary Oscillator or USB PLL as the USB clock source
SOSCEN: Secondary Oscillator (SOSC) Enable bit
1 = Enable the Secondary Oscillator
0 = Disable the Secondary Oscillator
bit 1
bit 0
OSWEN: Oscillator Switch Enable bit
1 = Initiate an oscillator switch to selection specified by NOSC bits
0 = Oscillator switch is complete
Note 1:
This bit is only available on PIC32MX2XX devices.
Note:
Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
DS60001168L-page 82
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 8-2:
Bit
Range
31:24
23:16
15:8
7:0
OSCTUN: FRC TUNING REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
TUN(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-6
Unimplemented: Read as ‘0’
bit 5-0
TUN: FRC Oscillator Tuning bits(1)
100000 = Center frequency -12.5%
100001 =
•
•
•
111111 =
000000 = Center frequency. Oscillator runs at minimal frequency (8 MHz)
000001 =
•
•
•
011110 =
011111 = Center frequency +12.5%
x = Bit is unknown
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither
characterized, nor tested.
Note:
Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
2011-2019 Microchip Technology Inc.
DS60001168L-page 83
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 8-3:
Bit
Range
31:24
23:16
15:8
7:0
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RODIV(1,3)
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RODIV
(1,3)
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0, HC
R-0, HS, HC
ON
—
SIDL
OE
RSLP(2)
—
DIVSWEN
ACTIVE
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
ROSEL(1)
Legend:
R = Readable bit
HC = Hardware Clearable HS = Hardware Settable
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Unimplemented: Read as ‘0’
bit 30-16 RODIV Reference Clock Divider bits(1,3)
The value selects the reference clock divider bits. See Figure 8-1 for information.
bit 15
ON: Output Enable bit
1 = Reference Oscillator module is enabled
0 = Reference Oscillator module is disabled
Unimplemented: Read as ‘0’
bit 14
bit 13
SIDL: Peripheral Stop in Idle Mode bit
1 = Discontinue module operation when the device enters Idle mode
0 = Continue module operation when the device enters Idle mode
bit 12
OE: Reference Clock Output Enable bit
1 = Reference clock is driven out on REFCLKO pin
0 = Reference clock is not driven out on REFCLKO pin
RSLP: Reference Oscillator Module Run in Sleep bit(2)
1 = Reference Oscillator module output continues to run in Sleep
0 = Reference Oscillator module output is disabled in Sleep
bit 11
bit 10
bit 9
Unimplemented: Read as ‘0’
DIVSWEN: Divider Switch Enable bit
1 = Divider switch is in progress
0 = Divider switch is complete
bit 8
ACTIVE: Reference Clock Request Status bit
1 = Reference clock request is active
0 = Reference clock request is not active
Unimplemented: Read as ‘0’
bit 7-4
Note 1:
2:
3:
The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may
result.
This bit is ignored when the ROSEL bits = 0000 or 0001.
While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to ’1’.
DS60001168L-page 84
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 8-3:
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
bit 3-0
ROSEL: Reference Clock Source Select bits(1)
1111 = Reserved; do not use
•
•
•
1001 = Reserved; do not use
1000 = REFCLKI
0111 = System PLL output
0110 = USB PLL output
0101 = SOSC
0100 = LPRC
0011 = FRC
0010 = POSC
0001 = PBCLK
0000 = SYSCLK
Note 1:
The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may
result.
This bit is ignored when the ROSEL bits = 0000 or 0001.
While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to ’1’.
2:
3:
2011-2019 Microchip Technology Inc.
DS60001168L-page 85
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 8-4:
Bit
Range
31:24
23:16
15:8
7:0
REFOTRIM: REFERENCE OSCILLATOR TRIM REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
ROTRIM
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
ROTRIM
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-23 ROTRIM: Reference Oscillator Trim bits
111111111 = 511/512 divisor added to RODIV value
111111110 = 510/512 divisor added to RODIV value
•
•
•
100000000 = 256/512 divisor added to RODIV value
•
•
•
000000010 = 2/512 divisor added to RODIV value
000000001 = 1/512 divisor added to RODIV value
000000000 = 0/512 divisor added to RODIV value
bit 22-0
Note:
Unimplemented: Read as ‘0’
While the ON (REFOCON) bit is ‘1’, writes to this register do not take effect until the DIVSWEN bit is
also set to ‘1’.
DS60001168L-page 86
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
9.0
Note:
DIRECT MEMORY ACCESS
(DMA) CONTROLLER
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 31. “Direct Memory
Access
(DMA)
Controller”
(DS60001117), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The PIC32 Direct Memory Access (DMA) controller is a
bus master module useful for data transfers between
different devices without CPU intervention. The source
and destination of a DMA transfer can be any of the
memory mapped modules existent in the PIC32, such
as Peripheral Bus devices: SPI, UART, PMP, etc., or
memory itself. Figure 9-1 show a block diagram of the
DMA Controller module.
The DMA Controller module has the following key
features:
• Four identical channels, each featuring:
- Auto-increment source and destination
address registers
- Source and destination pointers
- Memory to memory and memory to
peripheral transfers
• Automatic word-size detection:
- Transfer granularity, down to byte level
- Bytes need not be word-aligned at source
and destination
FIGURE 9-1:
DMA BLOCK DIAGRAM
Interrupt
Controller
System IRQ
Peripheral Bus
Address
Decoder
• Fixed priority channel arbitration
• Flexible DMA channel operating modes:
- Manual (software) or automatic (interrupt)
DMA requests
- One-Shot or Auto-Repeat Block Transfer
modes
- Channel-to-channel chaining
• Flexible DMA requests:
- A DMA request can be selected from any of
the peripheral interrupt sources
- Each channel can select any (appropriate)
observable interrupt as its DMA request
source
- A DMA transfer abort can be selected from
any of the peripheral interrupt sources
- Pattern (data) match transfer termination
• Multiple DMA channel status interrupts:
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half full
- DMA transfer aborted due to an external
event
- Invalid DMA address generated
• DMA debug support features:
- Most recent address accessed by a DMA
channel
- Most recent DMA channel to transfer data
• CRC Generation module:
- CRC module can be assigned to any of the
available channels
- CRC module is highly configurable
Channel 0
Control
SE
I0 L
Channel 1
Control
I1
Y
Bus
Interface
Device Bus and
Bus Arbitration
I2
Global Control
(DMACON)
Channel n
Control
In
L
SE
Channel Priority
Arbitration
2011-2019 Microchip Technology Inc.
DS60001168L-page 87
DMA Control Registers
DMA GLOBAL REGISTER MAP
3000 DMACON
3010 DMASTAT
3020 DMAADDR
31/15
30/14
29/13
31:16
—
—
—
15:0
ON
31:16
—
—
—
—
—
15:0
—
—
—
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF88_#)
TABLE 9-1:
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
RDWR
SUSPEND DMABUSY
—
—
—
—
31:16
DMACH(2)
0000
0000
DMAADDR
15:0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more
information.
DMA CRC REGISTER MAP
31/15
30/14
—
—
—
—
29/13
28/12
BYTO
—
27/11
26/10
25/9
24/8
23/7
WBO
—
PLEN
—
BITO
—
CRCEN
22/6
21/5
—
—
CRCAPP CRCTYP
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
CRCCH
—
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF88_#)
TABLE 9-2:
2011-2019 Microchip Technology Inc.
3030 DCRCCON
31:16
15:0
3040 DCRCDATA
31:16
15:0
DCRCDATA
0000
0000
3050 DCRCXOR
31:16
15:0
DCRCXOR
0000
0000
Legend:
Note 1:
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 88
9.1
Virtual Address
(BF88_#)
3070 DCH0ECON
DCH0INT
3090 DCH0SSA
30A0 DCH0DSA
30B0 DCH0SSIZ
30C0 DCH0DSIZ
30D0 DCH0SPTR
30E0 DCH0DPTR
30F0 DCH0CSIZ
3100 DCH0CPTR
3110 DCH0DAT
3120 DCH1CON
3130 DCH1ECON
3140
DCH1INT
DS60001168L-page 89
3150 DCH1SSA
3160 DCH1DSA
Legend:
Note 1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCHNS
—
CHEN
CHAED
CHCHN
CHAEN
—
CHAIRQ
CHEDET
—
—
—
31:16
—
—
—
CHSIRQ
—
—
—
—
—
CFORCE CABORT
CHSDIE CHSHIE
PATEN
CHDDIE
SIRQEN
CHDHIE
AIRQEN
CHBCIE
—
CHCCIE
—
CHTAIE
—
FF00
CHERIE 0000
15:0
—
—
—
—
—
—
—
CHSDIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
0000
31:16
15:0 CHBUSY
31:16
15:0
—
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
17/1
16/0
—
—
—
0000
CHPRI
0000
00FF
0000
0000
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
CHPDAT
—
—
—
0000
0000
0000
—
0000
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCHNS
—
31:16
—
—
—
CHSIRQ
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
0000
CHCPTR
15:0
—
—
0000
0000
CHCSIZ
15:0 CHBUSY
15:0
31:16
—
18/2
CHDPTR
—
31:16
19/3
CHSPTR
—
31:16
20/4
CHDSIZ
—
31:16
CHSHIF
21/5
CHSSIZ
15:0
31:16
15:0
22/6
CHDSA
15:0
31:16
15:0
31:16
23/7
CHSSA
15:0
15:0
31:16
24/8
All Resets
Bit Range
Register
Name(1)
Bits
3060 DCH0CON
3080
DMA CHANNELS 0-3 REGISTER MAP
0000
—
—
—
CHEN
CHAED
CHCHN
CHAEN
—
CHAIRQ
CHEDET
CFORCE CABORT
CHSDIE CHSHIE
PATEN
CHDDIE
SIRQEN
CHDHIE
AIRQEN
CHBCIE
—
CHCCIE
—
CHTAIE
—
FF00
CHERIE 0000
CHSDIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
0000
CHSSA
CHDSA
15:0
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
CHSHIF
—
—
CHPRI
0000
00FF
0000
0000
0000
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2011-2019 Microchip Technology Inc.
TABLE 9-3:
Virtual Address
(BF88_#)
3180 DCH1DSIZ
3190 DCH1SPTR
31A0 DCH1DPTR
31B0 DCH1CSIZ
31C0 DCH1CPTR
31D0 DCH1DAT
31E0 DCH2CON
31F0 DCH2ECON
DCH2INT
3210 DCH2SSA
3220 DCH2DSA
2011-2019 Microchip Technology Inc.
3230 DCH2SSIZ
3240 DCH2DSIZ
3250 DCH2SPTR
3260 DCH2DPTR
3270 DCH2CSIZ
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
15:0
31:16
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
15:0
31:16
15:0
31:16
24/8
—
—
CHSSIZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCHNS
—
31:16
—
—
—
CHSIRQ
—
—
—
—
—
15:0
—
—
—
—
—
—
—
15:0
18/2
17/1
16/0
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
CHPDAT
—
—
—
0000
0000
0000
—
0000
—
—
—
15:0
—
31:16
—
0000
0000
—
—
—
CHEN
CHAED
CHCHN
CHAEN
—
CHAIRQ
CHEDET
CFORCE CABORT
CHSDIE CHSHIE
PATEN
CHDDIE
SIRQEN
CHDHIE
AIRQEN
CHBCIE
—
CHCCIE
—
CHTAIE
—
FF00
CHERIE 0000
CHSDIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
0000
CHSHIF
—
—
CHPRI
CHSSA
15:0
31:16
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSSIZ
—
—
0000
CHDSIZ
—
—
0000
CHSPTR
—
—
0000
CHDPTR
—
—
—
—
—
—
—
—
—
CHCSIZ
0000
00FF
0000
0000
CHDSA
—
0000
0000
CHCPTR
15:0 CHBUSY
15:0
19/3
CHCSIZ
—
15:0
31:16
20/4
CHDPTR
—
15:0
31:16
21/5
CHSPTR
—
31:16
—
22/6
CHDSIZ
—
31:16
23/7
All Resets
Bit Range
Register
Name(1)
Bits
3170 DCH1SSIZ
3200
DMA CHANNELS 0-3 REGISTER MAP (CONTINUED)
0000
0000
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 90
TABLE 9-3:
Virtual Address
(BF88_#)
3290 DCH2DAT
32A0 DCH3CON
32B0 DCH3ECON
DCH3INT
32D0 DCH3SSA
32E0 DCH3DSA
32F0 DCH3SSIZ
3300 DCH3DSIZ
3310 DCH3SPTR
3320 DCH3DPTR
3330 DCH3CSIZ
3340 DCH3CPTR
3350 DCH3DAT
Legend:
DS60001168L-page 91
Note 1:
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCPTR
All Resets
Bit Range
Register
Name(1)
Bits
3280 DCH2CPTR
32C0
DMA CHANNELS 0-3 REGISTER MAP (CONTINUED)
0000
0000
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCHNS
—
CHEN
CHAED
CHCHN
CHAEN
—
CHAIRQ
CHEDET
—
—
—
31:16
—
—
—
CHSIRQ
—
—
—
—
—
CFORCE CABORT
CHSDIE CHSHIE
PATEN
CHDDIE
SIRQEN
CHDHIE
AIRQEN
CHBCIE
—
CHCCIE
—
CHTAIE
—
FF00
CHERIE 0000
15:0
—
—
—
—
—
—
—
CHSDIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
0000
15:0 CHBUSY
31:16
15:0
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
0000
CHPRI
0000
00FF
0000
0000
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
CHSSIZ
—
—
0000
CHDSIZ
—
—
0000
CHSPTR
—
—
0000
CHDPTR
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
15:0
CHSHIF
—
—
—
—
0000
CHCPTR
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
0000
0000
CHCSIZ
—
0000
0000
CHDSA
15:0
31:16
15:0
31:16
CHPDAT
CHSSA
15:0
31:16
15:0
31:16
—
0000
CHPDAT
0000
0000
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2011-2019 Microchip Technology Inc.
TABLE 9-3:
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 9-1:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
U-0
DMACON: DMA CONTROLLER CONTROL REGISTER
Bit
Bit
30/22/14/6 29/21/13/5
U-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
(1)
U-0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
—
—
SUSPEND
DMABUSY
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
ON
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: DMA On bit(1)
1 = DMA module is enabled
0 = DMA module is disabled
bit 14-13 Unimplemented: Read as ‘0’
bit 12
SUSPEND: DMA Suspend bit
1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus
0 = DMA operates normally
bit 11
DMABUSY: DMA Module Busy bit
1 = DMA module is active
0 = DMA module is disabled and not actively transferring data
bit 10-0
Unimplemented: Read as ‘0’
Note 1:
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS60001168L-page 92
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 9-2:
Bit
Range
31:24
23:16
15:8
7:0
DMASTAT: DMA STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
—
—
—
—
RDWR
DMACH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3
RDWR: Read/Write Status bit
1 = Last DMA bus access was a read
0 = Last DMA bus access was a write
bit 2-0
DMACH: DMA Channel bits
These bits contain the value of the most recent active DMA channel.
REGISTER 9-3:
Bit
Range
31:24
23:16
15:8
7:0
DMAADDR: DMA ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R-0
R-0
R-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DMAADDR
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DMAADDR
R-0
R-0
DMAADDR
R-0
R-0
R-0
R-0
R-0
DMAADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DMAADDR: DMA Module Address bits
These bits contain the address of the most recent DMA access.
2011-2019 Microchip Technology Inc.
DS60001168L-page 93
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 9-4:
Bit
Range
31:24
23:16
15:8
7:0
DCRCCON: DMA CRC CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
R/W-0
R/W-0
BYTO
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
R/W-0
R/W-0
(1)
—
—
WBO
—
—
BITO
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
R/W-0
U-0
U-0
PLEN
CRCEN
CRCAPP(1)
CRCTYP
—
—
R/W-0
CRCCH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 BYTO: CRC Byte Order Selection bits
11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order
per half-word)
10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per
half-word)
01 = Endian byte swap on word boundaries (i.e., reverse source byte order)
00 = No swapping (i.e., source byte order)
bit 27
WBO: CRC Write Byte Order Selection bit(1)
1 = Source data is written to the destination re-ordered as defined by BYTO
0 = Source data is written to the destination unaltered
bit 26-25 Unimplemented: Read as ‘0’
bit 24
BITO: CRC Bit Order Selection bit
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected)
0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected)
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected)
0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected)
bit 23-13 Unimplemented: Read as ‘0’
bit 12-8
PLEN: Polynomial Length bits
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
These bits are unused.
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
Denotes the length of the polynomial – 1.
bit 7
CRCEN: CRC Enable bit
1 = CRC module is enabled and channel transfers are routed through the CRC module
0 = CRC module is disabled and channel transfers proceed normally
Note 1:
When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
DS60001168L-page 94
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 9-4:
DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED)
bit 6
CRCAPP: CRC Append Mode bit(1)
1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer
completes the DMA writes the calculated CRC value to the location given by CHxDSA
0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the
destination
bit 5
CRCTYP: CRC Type Selection bit
1 = The CRC module will calculate an IP header checksum
0 = The CRC module will calculate a LFSR CRC
bit 4-3
Unimplemented: Read as ‘0’
bit 2-0
CRCCH: CRC Channel Select bits
111 = CRC is assigned to Channel 7
110 = CRC is assigned to Channel 6
101 = CRC is assigned to Channel 5
100 = CRC is assigned to Channel 4
011 = CRC is assigned to Channel 3
010 = CRC is assigned to Channel 2
001 = CRC is assigned to Channel 1
000 = CRC is assigned to Channel 0
Note 1:
When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
2011-2019 Microchip Technology Inc.
DS60001168L-page 95
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 9-5:
Bit
Range
31:24
23:16
15:8
7:0
DCRCDATA: DMA CRC DATA REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DCRCDATA: CRC Data Register bits
Writing to this register will seed the CRC generator. Reading from this register will return the current value of
the CRC. Bits greater than PLEN will return ‘0’ on any read.
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written
to this register is converted and read back in 1’s complement form (i.e., current IP header checksum value).
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
Bits greater than PLEN will return ‘0’ on any read.
REGISTER 9-6:
Bit
Range
31:24
23:16
15:8
7:0
DCRCXOR: DMA CRCXOR ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR
R/W-0
R/W-0
DCRCXOR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DCRCXOR: CRC XOR Register bits
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
This register is unused.
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
1 = Enable the XOR input to the Shift register
0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in
the register
DS60001168L-page 96
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 9-7:
Bit
Range
31:24
23:16
15:8
7:0
DCHxCON: DMA CHANNEL ‘x’ CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
CHBUSY
—
—
—
—
—
—
CHCHNS(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R-0
CHEN(2)
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
CHBUSY: Channel Busy bit
1 = Channel is active or has been enabled
0 = Channel is inactive or has been disabled
bit 14-9
Unimplemented: Read as ‘0’
bit 8
CHCHNS: Chain Channel Selection bit(1)
1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
bit 7
CHEN: Channel Enable bit(2)
1 = Channel is enabled
0 = Channel is disabled
bit 6
CHAED: Channel Allow Events If Disabled bit
1 = Channel start/abort events will be registered, even if the channel is disabled
0 = Channel start/abort events will be ignored if the channel is disabled
bit
CHCHN: Channel Chain Enable bit
1 = Allow channel to be chained
0 = Do not allow channel to be chained
bit 4
CHAEN: Channel Automatic Enable bit
1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete
0 = Channel is disabled on block transfer complete
bit 3
Unimplemented: Read as ‘0’
bit 2
CHEDET: Channel Event Detected bit
1 = An event has been detected
0 = No events have been detected
bit 1-0
CHPRI: Channel Priority bits
11 = Channel has priority 3 (highest)
10 = Channel has priority 2
01 = Channel has priority 1
00 = Channel has priority 0
Note 1:
2:
The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).
When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.
2011-2019 Microchip Technology Inc.
DS60001168L-page 97
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 9-8:
Bit
Range
31:24
23:16
DCHxECON: DMA CHANNEL ‘x’ EVENT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
(1)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CHAIRQ
15:8
R/W-1
CHSIRQ(1)
7:0
S-0
S-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
Legend:
R = Readable bit
-n = Value at POR
S = Settable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 CHAIRQ: Channel Transfer Abort IRQ bits(1)
11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag
•
•
•
bit 15-8
00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag
00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag
CHSIRQ: Channel Transfer Start IRQ bits(1)
11111111 = Interrupt 255 will initiate a DMA transfer
•
•
•
bit 2-0
00000001 = Interrupt 1 will initiate a DMA transfer
00000000 = Interrupt 0 will initiate a DMA transfer
CFORCE: DMA Forced Transfer bit
1 = A DMA transfer is forced to begin when this bit is written to a ‘1’
0 = This bit always reads ‘0’
CABORT: DMA Abort Transfer bit
1 = A DMA transfer is aborted when this bit is written to a ‘1’
0 = This bit always reads ‘0’
PATEN: Channel Pattern Match Abort Enable bit
1 = Abort transfer and clear CHEN on pattern match
0 = Pattern match is disabled
SIRQEN: Channel Start IRQ Enable bit
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer
AIRQEN: Channel Abort IRQ Enable bit
1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs
0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer
Unimplemented: Read as ‘0’
Note 1:
See Table 7-1: “Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources.
bit 7
bit 6
bit 5
bit 4
bit 3
DS60001168L-page 98
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 9-9:
Bit
Range
31:24
23:16
15:8
7:0
DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23
CHSDIE: Channel Source Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 22
CHSHIE: Channel Source Half Empty Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 21
CHDDIE: Channel Destination Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 20
CHDHIE: Channel Destination Half Full Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 19
CHBCIE: Channel Block Transfer Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 18
CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 17
CHTAIE: Channel Transfer Abort Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 16
CHERIE: Channel Address Error Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 15-8
Unimplemented: Read as ‘0’
bit 7
CHSDIF: Channel Source Done Interrupt Flag bit
1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
0 = No interrupt is pending
bit 6
CHSHIF: Channel Source Half Empty Interrupt Flag bit
1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
0 = No interrupt is pending
bit 5
CHDDIF: Channel Destination Done Interrupt Flag bit
1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
0 = No interrupt is pending
2011-2019 Microchip Technology Inc.
DS60001168L-page 99
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 9-9:
DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER (CONTINUED)
bit 4
CHDHIF: Channel Destination Half Full Interrupt Flag bit
1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
0 = No interrupt is pending
bit 3
CHBCIF: Channel Block Transfer Complete Interrupt Flag bit
1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a
pattern match event occurs
0 = No interrupt is pending
bit 2
CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit
1 = A cell transfer has been completed (CHCSIZ bytes have been transferred)
0 = No interrupt is pending
bit 1
CHTAIF: Channel Transfer Abort Interrupt Flag bit
1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
0 = No interrupt is pending
bit 0
CHERIF: Channel Address Error Interrupt Flag bit
1 = A channel address error has been detected (either the source or the destination address is invalid)
0 = No interrupt is pending
DS60001168L-page 100
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 9-10:
Bit Range
DCHxSSA: DMA CHANNEL ‘x’ SOURCE START ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
R/W-0
R/W-0
31:24
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
R/W-0
R/W-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA
R/W-0
23:16
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA
R/W-0
15:8
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA
R/W-0
7:0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
CHSSA Channel Source Start Address bits
Channel source start address.
Note: This must be the physical address of the source.
REGISTER 9-11:
Bit
Range
31:24
23:16
15:8
7:0
DCHxDSA: DMA CHANNEL ‘x’ DESTINATION START ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSA
R/W-0
R/W-0
CHDSA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSA
R/W-0
CHDSA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 CHDSA: Channel Destination Start Address bits
Channel destination start address.
Note: This must be the physical address of the destination.
2011-2019 Microchip Technology Inc.
DS60001168L-page 101
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 9-12:
Bit
Range
31:24
23:16
15:8
DCHxSSIZ: DMA CHANNEL ‘x’ SOURCE SIZE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSIZ
7:0
R/W-0
CHSSIZ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CHSSIZ: Channel Source Size bits
1111111111111111 = 65,535 byte source size
•
•
•
0000000000000010 = 2 byte source size
0000000000000001 = 1 byte source size
0000000000000000 = 65,536 byte source size
REGISTER 9-13:
Bit
Range
31:24
23:16
15:8
DCHxDSIZ: DMA CHANNEL ‘x’ DESTINATION SIZE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSIZ
7:0
R/W-0
CHDSIZ
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHDSIZ: Channel Destination Size bits
1111111111111111 = 65,535 byte destination size
•
•
•
0000000000000010 = 2 byte destination size
0000000000000001 = 1 byte destination size
0000000000000000 = 65,536 byte destination size
DS60001168L-page 102
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 9-14:
Bit
Range
31:24
23:16
15:8
DCHxSPTR: DMA CHANNEL ‘x’ SOURCE POINTER REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHSPTR
7:0
R-0
R-0
CHSPTR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CHSPTR: Channel Source Pointer bits
1111111111111111 = Points to byte 65,535 of the source
•
•
•
0000000000000001 = Points to byte 1 of the source
0000000000000000 = Points to byte 0 of the source
Note:
When in Pattern Detect mode, this register is reset on a pattern detect.
REGISTER 9-15:
Bit
Range
31:24
23:16
15:8
DCHxDPTR: DMA CHANNEL ‘x’ DESTINATION POINTER REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHDPTR
7:0
R-0
R-0
CHDPTR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CHDPTR: Channel Destination Pointer bits
1111111111111111 = Points to byte 65,535 of the destination
•
•
•
0000000000000001 = Points to byte 1 of the destination
0000000000000000 = Points to byte 0 of the destination
2011-2019 Microchip Technology Inc.
DS60001168L-page 103
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 9-16:
Bit
Range
31:24
23:16
15:8
DCHxCSIZ: DMA CHANNEL ‘x’ CELL-SIZE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHCSIZ
7:0
R/W-0
CHCSIZ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CHCSIZ: Channel Cell Size bits
1111111111111111 = 65,535 bytes transferred on an event
•
•
•
0000000000000010 = 2 bytes transferred on an event
0000000000000001= 1 byte transferred on an event
0000000000000000 = 65,536 bytes transferred on an event
REGISTER 9-17:
Bit
Range
31:24
23:16
15:8
DCHxCPTR: DMA CHANNEL ‘x’ CELL POINTER REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHCPTR
7:0
R-0
R-0
CHCPTR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCPTR: Channel Cell Progress Pointer bits
1111111111111111 = 65,535 bytes have been transferred since the last event
•
•
•
0000000000000001 = 1 byte has been transferred since the last event
0000000000000000 = 0 bytes have been transferred since the last event
Note:
When in Pattern Detect mode, this register is reset on a pattern detect.
DS60001168L-page 104
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 9-18:
Bit
Range
31:24
23:16
15:8
7:0
DCHxDAT: DMA CHANNEL ‘x’ PATTERN DATA REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHPDAT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0
CHPDAT: Channel Data Register bits
Pattern Terminate mode:
Data to be matched must be stored in this register to allow a “terminate on match”.
All other modes:
Unused.
2011-2019 Microchip Technology Inc.
DS60001168L-page 105
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
NOTES:
DS60001168L-page 106
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
10.0
Note:
USB ON-THE-GO (OTG)
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 27. “USB On-TheGo (OTG)” (DS60001126), which is available from the Documentation > Reference
Manual section of the Microchip PIC32
web site (www.microchip.com/pic32).
The Universal Serial Bus (USB) module contains
analog and digital components to provide a USB 2.0
Full-Speed and Low-Speed embedded host, FullSpeed device or OTG implementation with a minimum
of external components. This module in Host mode is
intended for use as an embedded host and therefore
does not implement a UHCI or OHCI controller.
The USB module consists of the clock generator, the
USB voltage comparators, the transceiver, the Serial
Interface Engine (SIE), a dedicated USB DMA controller, pull-up and pull-down resistors, and the register
interface. A block diagram of the PIC32 USB OTG
module is presented in Figure 10-1.
The PIC32 USB module includes the following
features:
•
•
•
•
•
•
•
•
•
USB Full-Speed support for Host and Device
Low-Speed Host support
USB OTG support
Integrated signaling resistors
Integrated analog comparators for VBUS
monitoring
Integrated USB transceiver
Transaction handshaking performed by hardware
Endpoint buffering anywhere in system RAM
Integrated DMA to access system RAM and Flash
Note:
The implementation and use of the USB
specifications, as well as other third party
specifications or technologies, may
require licensing; including, but not limited
to, USB Implementers Forum, Inc., also
referred to as USB-IF (www.usb.org). The
user is fully responsible for investigating
and satisfying any applicable licensing
obligations.
The clock generator provides the 48 MHz clock
required for USB Full-Speed and Low-Speed communication. The voltage comparators monitor the voltage on
the VBUS pin to determine the state of the bus. The
transceiver provides the analog translation between
the USB bus and the digital logic. The SIE is a state
machine that transfers data to and from the endpoint
buffers and generates the hardware protocol for data
transfers. The USB DMA controller transfers data
between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the
need for external signaling components. The register
interface allows the CPU to configure and
communicate with the module.
2011-2019 Microchip Technology Inc.
DS60001168L-page 107
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 10-1:
PIC32MX1XX/2XX 28/36/44-PIN FAMILY FAMILY USB INTERFACE DIAGRAM
FRC
Oscillator
8 MHz Typical
TUN(3)
Primary Oscillator
(POSC)
Div x
OSC1
UPLLIDIV
UFIN(4)
(5)
PLL
Div 2
UPLLEN(5)
UFRCEN(2)
OSC2
USB Module
SRP Charge
Bus
SRP Discharge
USB
Voltage
Comparators
48 MHz USB Clock(6)
Full Speed Pull-up
D+(1)
Registers
and
Control
Interface
Host Pull-down
SIE
Transceiver
Low Speed Pull-up
D-(1)
DMA
System
RAM
Host Pull-down
ID Pull-up
ID(1)
VBUSON(1)
Transceiver Power 3.3V
VUSB3V3
Note 1:
2:
3:
4:
5:
6:
Pins can be used as digital input/output when USB is not enabled.
This bit field is contained in the OSCCON register.
This bit field is contained in the OSCTRM register.
USB PLL UFIN requirements: 4 MHz.
This bit field is contained in the DEVCFG2 register.
A 48 MHz clock is required for proper USB operation.
DS60001168L-page 108
2011-2019 Microchip Technology Inc.
USB Control Registers
Virtual Address
(BF88_#)
Register
Name(1)
TABLE 10-1:
5040
U1OTGIR(2)
5050
U1OTGIE
5060
U1OTGSTAT(3)
5070
5080
U1OTGCON
U1PWRC
U1IR(2)
5210
U1IE
5220
U1EIR(2)
5230
U1EIE
U1STAT(3)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IDIF
—
T1MSECIF LSTATEIF
—
—
ACTVIF
—
SESVDIF SESENDIF
—
—
—
—
VBUSVDIF 0000
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IDIE
—
T1MSECIE LSTATEIE
—
—
ACTVIE
—
SESVDIE SESENDIE
—
—
—
—
VBUSVDIE 0000
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ID
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UACTPND(4)
—
15:0
—
—
—
—
—
—
—
—
STALLIF
31:16
—
—
—
—
—
—
—
—
—
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
23/7
22/6
21/5
—
—
—
—
—
—
19/3
18/2
17/1
—
—
—
SESVD
—
DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
STALLIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ATTACHIE RESUMEIE
—
—
0000
0000
OTGEN
—
VBUSCHG
—
VBUSDIS
—
0000
0000
USUSPEND USBPWR
—
—
0000
0000
—
—
SOFIF
UERRIF
—
—
—
—
IDLEIE
TRNIE
SOFIE
—
—
—
—
—
—
—
—
—
—
BTSEF
BMXEF
DMAEF
BTOEF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
0000
VBUSVD
—
TRNIF
—
—
—
—
IDLEIF
15:0
16/0
SESEND
—
USLPGRD USBBUSY
—
—
ATTACHIF RESUMEIF
DFN8EF CRC16EF
—
—
UERRIE
—
URSTIF 0000
DETACHIF 0000
—
0000
URSTIE
0000
DETACHIE 0000
—
0000
CRC5EF
EOFEF
PIDEF
0000
0000
—
—
0000
PIDEE
0000
CRC5EE
DS60001168L-page 109
15:0
—
—
—
—
—
—
—
—
BTSEE
BMXEE
DMAEE
BTOEE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ENDPT
—
—
—
DIR
—
PPBI
—
—
—
—
—
0000
0000
15:0
—
—
—
—
—
—
—
—
JSTATE
SE0
PKTDIS
TOKBUSY
USBRST
PPBRST
USBEN
SOFEN
0000
0000
—
—
—
—
0000
0000
—
—
—
—
0000
0000
U1CON
5260
U1ADDR
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LSPDEN
—
—
5270
U1BDTP1
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2:
3:
4:
—
LSTATE
—
5250
Legend:
Note 1:
20/4
All Resets
Bit Range
Bits
5200
5240
USB REGISTER MAP
DFN8EE CRC16EE
HOSTEN RESUME
—
DEVADDR
—
BDTPTRL
—
EOFEE
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8, and 0xC respectively.
See Section 11.2 “CLR, SET and INV Registers” for more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET and INV registers.
Reset value for this bit is undefined.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2011-2019 Microchip Technology Inc.
10.1
Virtual Address
(BF88_#)
Register
Name(1)
Bit Range
USB REGISTER MAP (CONTINUED)
5280
U1FRML(3)
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FRML
—
—
—
0000
0000
5290
U1FRMH(3)
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FRMH
—
0000
0000
52A0
U1TOK
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PID
—
—
—
—
EP
—
15:0
0000
0000
52B0
U1SOF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNT
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BDTPTRH
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BDTPTRU
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTEYE
—
UOEMON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LSPD
—
RETRYDIS
—
—
—
EPCONDIS EPRXEN
—
—
EPTXEN
—
EPSTALL
—
EPHSHK
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS EPRXEN
—
—
EPTXEN
—
EPSTALL
—
EPHSHK
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS EPRXEN
—
—
EPTXEN
—
EPSTALL
—
EPHSHK
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS EPRXEN
—
—
EPTXEN
—
EPSTALL
—
EPHSHK
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS EPRXEN
—
—
EPTXEN
—
EPSTALL
—
EPHSHK
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS EPRXEN
—
—
EPTXEN
—
EPSTALL
—
EPHSHK
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS EPRXEN
—
—
EPTXEN
—
EPSTALL
—
EPHSHK
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS EPRXEN
—
—
EPTXEN
—
EPSTALL
—
EPHSHK
—
0000
0000
52C0
52D0
52E0
U1BDTP2
U1BDTP3
U1CNFG1
5300
U1EP0
5310
U1EP1
5320
U1EP2
5330
U1EP3
5340
U1EP4
2011-2019 Microchip Technology Inc.
5350
U1EP5
5360
U1EP6
5370
U1EP7
5380
U1EP8
Legend:
Note 1:
2:
3:
4:
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
USBSIDL
—
19/3
—
—
18/2
17/1
16/0
All Resets
Bits
UASUSPND 0001
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
EPHSHK 0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8, and 0xC respectively.
See Section 11.2 “CLR, SET and INV Registers” for more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET and INV registers.
Reset value for this bit is undefined.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 110
TABLE 10-1:
Virtual Address
(BF88_#)
Register
Name(1)
5390
U1EP9
53A0
U1EP10
53B0
U1EP11
53C0
U1EP12
53D0
U1EP13
53E0
U1EP14
USB REGISTER MAP (CONTINUED)
53F0
U1EP15
Legend:
Note 1:
2:
3:
4:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
20/4
18/2
17/1
16/0
—
—
EPCONDIS EPRXEN
—
EPTXEN
—
EPSTALL
—
EPHSHK
0000
0000
—
—
—
—
EPCONDIS EPRXEN
—
EPTXEN
—
EPSTALL
—
EPHSHK
0000
0000
—
—
—
—
—
—
EPCONDIS EPRXEN
—
EPTXEN
—
EPSTALL
—
EPHSHK
0000
0000
—
—
—
—
—
—
—
—
EPCONDIS EPRXEN
—
EPTXEN
—
EPSTALL
—
EPHSHK
0000
0000
—
—
—
—
—
—
—
—
—
—
EPCONDIS EPRXEN
—
EPTXEN
—
EPSTALL
—
EPHSHK
0000
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
EPCONDIS EPRXEN
—
—
EPTXEN
—
EPSTALL
—
EPHSHK
—
0000
0000
—
—
—
—
—
EPCONDIS EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
—
19/3
All Resets
Bit Range
Bits
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8, and 0xC respectively.
See Section 11.2 “CLR, SET and INV Registers” for more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET and INV registers.
Reset value for this bit is undefined.
DS60001168L-page 111
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2011-2019 Microchip Technology Inc.
TABLE 10-1:
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-1:
Bit
Range
31:24
23:16
15:8
7:0
U1OTGIR: USB OTG INTERRUPT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
U-0
R/WC-0, HS
IDIF
T1MSECIF
LSTATEIF
ACTVIF
SESVDIF
SESENDIF
—
VBUSVDIF
Legend:
WC = Write ‘1’ to clear
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
IDIF: ID State Change Indicator bit
1 = A change in the ID state was detected
0 = No change in the ID state was detected
bit 6
T1MSECIF: 1 Millisecond Timer bit
1 = 1 millisecond timer has expired
0 = 1 millisecond timer has not expired
bit 5
LSTATEIF: Line State Stable Indicator bit
1 = USB line state has been stable for 1 ms, but different from last time
0 = USB line state has not been stable for 1 ms
bit 4
ACTVIF: Bus Activity Indicator bit
1 = Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up
0 = Activity has not been detected
bit 3
SESVDIF: Session Valid Change Indicator bit
1 = VBUS voltage has dropped below the session end level
0 = VBUS voltage has not dropped below the session end level
bit 2
SESENDIF: B-Device VBUS Change Indicator bit
1 = A change on the session end input was detected
0 = No change on the session end input was detected
bit 1
Unimplemented: Read as ‘0’
bit 0
VBUSVDIF: A-Device VBUS Change Indicator bit
1 = A change on the session valid input was detected
0 = No change on the session valid input was detected
DS60001168L-page 112
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-2:
Bit
Range
31:24
23:16
15:8
7:0
U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
IDIE
T1MSECIE
LSTATEIE
ACTVIE
SESVDIE
SESENDIE
—
VBUSVDIE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
IDIE: ID Interrupt Enable bit
1 = ID interrupt is enabled
0 = ID interrupt is disabled
bit 6
T1MSECIE: 1 Millisecond Timer Interrupt Enable bit
1 = 1 millisecond timer interrupt is enabled
0 = 1 millisecond timer interrupt is disabled
bit 5
LSTATEIE: Line State Interrupt Enable bit
1 = Line state interrupt is enabled
0 = Line state interrupt is disabled
bit 4
ACTVIE: Bus Activity Interrupt Enable bit
1 = Activity interrupt is enabled
0 = Activity interrupt is disabled
bit 3
SESVDIE: Session Valid Interrupt Enable bit
1 = Session valid interrupt is enabled
0 = Session valid interrupt is disabled
bit 2
SESENDIE: B-Device Session End Interrupt Enable bit
1 = B-Device session end interrupt is enabled
0 = B-Device session end interrupt is disabled
bit 1
Unimplemented: Read as ‘0’
bit 0
VBUSVDIE: A-Device VBUS Valid Interrupt Enable bit
1 = A-Device VBUS valid interrupt is enabled
0 = A-Device VBUS valid interrupt is disabled
2011-2019 Microchip Technology Inc.
DS60001168L-page 113
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-3:
Bit
Range
31:24
23:16
15:8
7:0
U1OTGSTAT: USB OTG STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
U-0
R-0
U-0
R-0
R-0
U-0
R-0
ID
—
LSTATE
—
SESVD
SESEND
—
VBUSVD
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
ID: ID Pin State Indicator bit
1 = No cable is attached or a “type B” cable has been inserted into the USB receptacle
0 = A “type A” OTG cable has been inserted into the USB receptacle
bit 6
Unimplemented: Read as ‘0’
bit 5
LSTATE: Line State Stable Indicator bit
1 = USB line state (SE0 (U1CON) bit and JSTATE (U1CON)) bit has been stable for previous 1 ms
0 = USB line state (SE0 and JSTATE) has not been stable for previous 1 ms
bit 4
Unimplemented: Read as ‘0’
bit 3
SESVD: Session Valid Indicator bit
1 = VBUS voltage is above Session Valid on the A or B device
0 = VBUS voltage is below Session Valid on the A or B device
bit 2
SESEND: B-Device Session End Indicator bit
1 = VBUS voltage is below Session Valid on the B device
0 = VBUS voltage is above Session Valid on the B device
bit 1
Unimplemented: Read as ‘0’
bit 0
VBUSVD: A-Device VBUS Valid Indicator bit
1 = VBUS voltage is above Session Valid on the A device
0 = VBUS voltage is below Session Valid on the A device
DS60001168L-page 114
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-4:
Bit
Range
31:24
23:16
15:8
7:0
U1OTGCON: USB OTG CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VBUSON
OTGEN
VBUSCHG
VBUSDIS
DPPULUP DMPULUP DPPULDWN DMPULDWN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
DPPULUP: D+ Pull-Up Enable bit
1 = D+ data line pull-up resistor is enabled
0 = D+ data line pull-up resistor is disabled
bit 6
DMPULUP: D- Pull-Up Enable bit
1 = D- data line pull-up resistor is enabled
0 = D- data line pull-up resistor is disabled
bit 5
DPPULDWN: D+ Pull-Down Enable bit
1 = D+ data line pull-down resistor is enabled
0 = D+ data line pull-down resistor is disabled
bit 4
DMPULDWN: D- Pull-Down Enable bit
1 = D- data line pull-down resistor is enabled
0 = D- data line pull-down resistor is disabled
bit 3
VBUSON: VBUS Power-on bit
1 = VBUS line is powered
0 = VBUS line is not powered
bit 2
OTGEN: OTG Functionality Enable bit
1 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control
0 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control
bit 1
VBUSCHG: VBUS Charge Enable bit
1 = VBUS line is charged through a pull-up resistor
0 = VBUS line is not charged through a resistor
bit 0
VBUSDIS: VBUS Discharge Enable bit
1 = VBUS line is discharged through a pull-down resistor
0 = VBUS line is not discharged through a resistor
2011-2019 Microchip Technology Inc.
DS60001168L-page 115
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-5:
Bit
Bit
Range 31/23/15/7
31:24
23:16
15:8
7:0
U-0
U1PWRC: USB POWER CONTROL REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
U-0
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
UACTPND
—
—
USLPGRD USBBUSY(1)
—
USUSPEND USBPWR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
UACTPND: USB Activity Pending bit
1 = USB bus activity has been detected; however, an interrupt is pending, which has yet to be generated
0 = An interrupt is not pending
bit 6-5
Unimplemented: Read as ‘0’
bit 4
USLPGRD: USB Sleep Entry Guard bit
1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending
0 = USB module does not block Sleep entry
bit 3
USBBUSY: USB Module Busy bit(1)
1 = USB module is active or disabled, but not ready to be enabled
0 = USB module is not active and is ready to be enabled
bit 2
Unimplemented: Read as ‘0’
bit 1
USUSPEND: USB Suspend Mode bit
1 = USB module is placed in Suspend mode
(The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.)
0 = USB module operates normally
bit 0
USBPWR: USB Operation Enable bit
1 = USB module is turned on
0 = USB module is disabled
(Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power
consumption.)
Note 1:
When USBPWR = 0 and USBBUSY = 1, status from all other registers is invalid and writes to all USB
module registers produce undefined results.
DS60001168L-page 116
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-6:
Bit
Bit
Range 31/23/15/7
31:24
23:16
15:8
7:0
U1IR: USB INTERRUPT REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R-0
IDLEIF
TRNIF(3)
SOFIF
UERRIF(4)
R/WC-0, HS
(5)
STALLIF
ATTACHIF(1) RESUMEIF(2)
Legend:
R = Readable bit
-n = Value at POR
WC = Write ‘1’ to clear
W = Writable bit
‘1’ = Bit is set
URSTIF
DETACHIF(6)
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
STALLIF: STALL Handshake Interrupt bit
1 = In Host mode a STALL handshake was received during the handshake phase of the transaction
In Device mode a STALL handshake was transmitted during the handshake phase of the transaction
0 = STALL handshake has not been sent
bit 6
ATTACHIF: Peripheral Attach Interrupt bit(1)
1 = Peripheral attachment was detected by the USB module
0 = Peripheral attachment was not detected
bit 5
RESUMEIF: Resume Interrupt bit(2)
1 = K-State is observed on the D+ or D- pin for 2.5 µs
0 = K-State is not observed
bit 4
IDLEIF: Idle Detect Interrupt bit
1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
bit 3
TRNIF: Token Processing Complete Interrupt bit(3)
1 = Processing of current token is complete; a read of the U1STAT register will provide endpoint information
0 = Processing of current token not complete
bit 2
SOFIF: SOF Token Interrupt bit
1 = SOF token received by the peripheral or the SOF threshold reached by the host
0 = SOF token was not received nor threshold reached
bit 1
UERRIF: USB Error Condition Interrupt bit(4)
1 = Unmasked error condition has occurred
0 = Unmasked error condition has not occurred
bit 0
URSTIF: USB Reset Interrupt bit (Device mode)(5)
1 = Valid USB Reset has occurred
0 = No USB Reset has occurred
DETACHIF: USB Detach Interrupt bit (Host mode)(6)
1 = Peripheral detachment was detected by the USB module
0 = Peripheral detachment was not detected
Note 1:
2:
3:
4:
5:
6:
This bit is valid only if the HOSTEN bit is set (see Register 10-11), there is no activity on the USB for
2.5 µs, and the current bus state is not SE0.
When not in Suspend mode, this interrupt should be disabled.
Clearing this bit will cause the STAT FIFO to advance.
Only error conditions enabled through the U1EIE register will set this bit.
Device mode.
Host mode.
2011-2019 Microchip Technology Inc.
DS60001168L-page 117
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-7:
Bit
Range
31:24
23:16
15:8
7:0
U1IE: USB INTERRUPT ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STALLIE
ATTACHIE RESUMEIE
IDLEIE
TRNIE
SOFIE
R/W-0
(1)
UERRIE
URSTIE(2)
DETACHIE(3)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
STALLIE: STALL Handshake Interrupt Enable bit
1 = STALL interrupt is enabled
0 = STALL interrupt is disabled
bit 6
ATTACHIE: ATTACH Interrupt Enable bit
1 = ATTACH interrupt is enabled
0 = ATTACH interrupt is disabled
bit 5
RESUMEIE: RESUME Interrupt Enable bit
1 = RESUME interrupt is enabled
0 = RESUME interrupt is disabled
bit 4
IDLEIE: Idle Detect Interrupt Enable bit
1 = Idle interrupt is enabled
0 = Idle interrupt is disabled
bit 3
TRNIE: Token Processing Complete Interrupt Enable bit
1 = TRNIF interrupt is enabled
0 = TRNIF interrupt is disabled
bit 2
SOFIE: SOF Token Interrupt Enable bit
1 = SOFIF interrupt is enabled
0 = SOFIF interrupt is disabled
bit 1
UERRIE: USB Error Interrupt Enable bit(1)
1 = USB Error interrupt is enabled
0 = USB Error interrupt is disabled
bit 0
URSTIE: USB Reset Interrupt Enable bit(2)
1 = URSTIF interrupt is enabled
0 = URSTIF interrupt is disabled
DETACHIE: USB Detach Interrupt Enable bit(3)
1 = DATTCHIF interrupt is enabled
0 = DATTCHIF interrupt is disabled
Note 1:
2:
3:
For an interrupt to propagate USBIF, the UERRIE (U1IE) bit must be set.
Device mode.
Host mode.
DS60001168L-page 118
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-8:
Bit
Range
31:24
23:16
15:8
7:0
U1EIR: USB ERROR INTERRUPT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
BTSEF
BMXEF
DMAEF(1)
BTOEF(2)
DFN8EF
CRC16EF
CRC5EF(4)
EOFEF(3,5)
Legend:
WC = Write ‘1’ to clear
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
PIDEF
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
BTSEF: Bit Stuff Error Flag bit
1 = Packet rejected due to bit stuff error
0 = Packet accepted
bit 6
BMXEF: Bus Matrix Error Flag bit
1 = The base address, of the Buffer Descriptor Table, or the address of an individual buffer pointed to by a
Buffer Descriptor Table entry, is invalid.
0 = No address error
bit 5
DMAEF: DMA Error Flag bit(1)
1 = USB DMA error condition detected
0 = No DMA error
bit 4
BTOEF: Bus Turnaround Time-Out Error Flag bit(2)
1 = Bus turnaround time-out has occurred
0 = No bus turnaround time-out
bit 3
DFN8EF: Data Field Size Error Flag bit
1 = Data field received is not an integral number of bytes
0 = Data field received is an integral number of bytes
bit 2
CRC16EF: CRC16 Failure Flag bit
1 = Data packet rejected due to CRC16 error
0 = Data packet accepted
Note 1:
2:
3:
4:
5:
This type of error occurs when the module’s request for the DMA bus is not granted in time to service the
module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer
size is not sufficient to store the received data packet causing it to be truncated.
This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)
has elapsed.
This type of error occurs when the module is transmitting or receiving data and the SOF counter has
reached zero.
Device mode.
Host mode.
2011-2019 Microchip Technology Inc.
DS60001168L-page 119
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-8:
U1EIR: USB ERROR INTERRUPT STATUS REGISTER (CONTINUED)
bit 1
CRC5EF: CRC5 Host Error Flag bit(4)
1 = Token packet rejected due to CRC5 error
0 = Token packet accepted
EOFEF: EOF Error Flag bit(3,5)
1 = An EOF error condition was detected
0 = No EOF error condition was detected
bit 0
PIDEF: PID Check Failure Flag bit
1 = PID check failed
0 = PID check passed
Note 1:
2:
3:
4:
5:
This type of error occurs when the module’s request for the DMA bus is not granted in time to service the
module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer
size is not sufficient to store the received data packet causing it to be truncated.
This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)
has elapsed.
This type of error occurs when the module is transmitting or receiving data and the SOF counter has
reached zero.
Device mode.
Host mode.
DS60001168L-page 120
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-9:
Bit
Range
31:24
23:16
15:8
7:0
U1EIE: USB ERROR INTERRUPT ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BTSEE
BMXEE
DMAEE
BTOEE
DFN8EE
CRC16EE
CRC5EE(1)
EOFEE(2)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
PIDEE
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
BTSEE: Bit Stuff Error Interrupt Enable bit
1 = BTSEF interrupt is enabled
0 = BTSEF interrupt is disabled
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
Note:
BMXEE: Bus Matrix Error Interrupt Enable bit
1 = BMXEF interrupt is enabled
0 = BMXEF interrupt is disabled
DMAEE: DMA Error Interrupt Enable bit
1 = DMAEF interrupt is enabled
0 = DMAEF interrupt is disabled
BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1 = BTOEF interrupt is enabled
0 = BTOEF interrupt is disabled
DFN8EE: Data Field Size Error Interrupt Enable bit
1 = DFN8EF interrupt is enabled
0 = DFN8EF interrupt is disabled
CRC16EE: CRC16 Failure Interrupt Enable bit
1 = CRC16EF interrupt is enabled
0 = CRC16EF interrupt is disabled
CRC5EE: CRC5 Host Error Interrupt Enable bit(1)
1 = CRC5EF interrupt is enabled
0 = CRC5EF interrupt is disabled
EOFEE: EOF Error Interrupt Enable bit(2)
1 = EOF interrupt is enabled
0 = EOF interrupt is disabled
PIDEE: PID Check Failure Interrupt Enable bit
1 = PIDEF interrupt is enabled
0 = PIDEF interrupt is disabled
Device mode.
Host mode.
For an interrupt to propagate the USBIF register, the UERRIE (U1IE) bit must be set.
2011-2019 Microchip Technology Inc.
DS60001168L-page 121
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-10: U1STAT: USB STATUS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-x
R-x
R-x
R-x
R-x
R-x
U-0
U-0
DIR
PPBI
—
—
ENDPT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-4
ENDPT: Encoded Number of Last Endpoint Activity bits
(Represents the number of the Buffer Descriptor Table, updated by the last USB transfer.)
1111 = Endpoint 15
1110 = Endpoint 14
•
•
•
0001 = Endpoint 1
0000 = Endpoint 0
bit 3
DIR: Last Buffer Descriptor Direction Indicator bit
1 = Last transaction was a transmit (TX) transfer
0 = Last transaction was a receive (RX) transfer
bit 2
PPBI: Ping-Pong Buffer Descriptor Pointer Indicator bit
1 = The last transaction was to the ODD Buffer Descriptor bank
0 = The last transaction was to the EVEN Buffer Descriptor bank
bit 1-0
Unimplemented: Read as ‘0’
Note:
The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. U1STAT value is only
valid when the TRNIF (U1IR) bit is active. Clearing the TRNIF bit advances the FIFO. Data in register
is invalid when the TRNIF bit = 0.
DS60001168L-page 122
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-11: U1CON: USB CONTROL REGISTER
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6
31:24
23:16
15:8
7:0
U-0
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-x
R-x
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
JSTATE
SE0
PKTDIS(4)
TOKBUSY(1,5)
USBRST
HOSTEN(2) RESUME(3)
PPBRST
USBEN(4)
SOFEN(5)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
JSTATE: Live Differential Receiver JSTATE flag bit
1 = JSTATE was detected on the USB
0 = No JSTATE was detected
bit 6
SE0: Live Single-Ended Zero flag bit
1 = Single-Ended Zero was detected on the USB
0 = No Single-Ended Zero was detected
bit 5
PKTDIS: Packet Transfer Disable bit(4)
1 = Token and packet processing is disabled (set upon SETUP token received)
0 = Token and packet processing is enabled
TOKBUSY: Token Busy Indicator bit(1,5)
1 = Token is being executed by the USB module
0 = No token is being executed
bit 4
USBRST: Module Reset bit(5)
1 = USB reset generated
0 = USB reset terminated
bit 3
HOSTEN: Host Mode Enable bit(2)
1 = USB host capability is enabled
0 = USB host capability is disabled
bit 2
RESUME: RESUME Signaling Enable bit(3)
1 = RESUME signaling is activated
0 = RESUME signaling is disabled
Note 1:
2:
3:
4:
5:
Software is required to check this bit before issuing another token command to the U1TOK register (see
Register 10-15).
All host control logic is reset any time that the value of this bit is toggled.
Software must set RESUME for 10 ms if the part is a function, or for 25 ms if the part is a host, and then
clear it to enable remote wake-up. In Host mode, the USB module will append a Low-Speed EOP to the
RESUME signaling when this bit is cleared.
Device mode.
Host mode.
2011-2019 Microchip Technology Inc.
DS60001168L-page 123
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-11: U1CON: USB CONTROL REGISTER (CONTINUED)
bit 1
PPBRST: Ping-Pong Buffers Reset bit
1 = Reset all Even/Odd buffer pointers to the EVEN Buffer Descriptor banks
0 = Even/Odd buffer pointers are not Reset
bit 0
USBEN: USB Module Enable bit(4)
1 = USB module and supporting circuitry is enabled
0 = USB module and supporting circuitry is disabled
SOFEN: SOF Enable bit(5)
1 = SOF token is sent every 1 ms
0 = SOF token is disabled
Note 1:
2:
3:
4:
5:
Software is required to check this bit before issuing another token command to the U1TOK register (see
Register 10-15).
All host control logic is reset any time that the value of this bit is toggled.
Software must set RESUME for 10 ms if the part is a function, or for 25 ms if the part is a host, and then
clear it to enable remote wake-up. In Host mode, the USB module will append a Low-Speed EOP to the
RESUME signaling when this bit is cleared.
Device mode.
Host mode.
DS60001168L-page 124
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-12: U1ADDR: USB ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LSPDEN
DEVADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
LSPDEN: Low-Speed Enable Indicator bit
1 = Next token command to be executed at Low-Speed
0 = Next token command to be executed at Full-Speed
bit 6-0
DEVADDR: 7-bit USB Device Address bits
REGISTER 10-13: U1FRML: USB FRAME NUMBER LOW REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FRML
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0
FRML: The 11-bit Frame Number Lower bits
The register bits are updated with the current frame number whenever a SOF TOKEN is received.
2011-2019 Microchip Technology Inc.
DS60001168L-page 125
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
—
—
—
—
—
FRMH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-3 Unimplemented: Read as ‘0’
bit 2-0
FRMH: The Upper 3 bits of the Frame Numbers bits
The register bits are updated with the current frame number whenever a SOF TOKEN is received.
REGISTER 10-15: U1TOK: USB TOKEN REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PID
EP
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-4
PID: Token Type Indicator bits(1)
1101 = SETUP (TX) token type transaction
1001 = IN (RX) token type transaction
0001 = OUT (TX) token type transaction
Note: All other values are reserved and must not be used.
bit 3-0
EP: Token Command Endpoint Address bits
The four bit value must specify a valid endpoint.
Note 1:
All other values are reserved and must not be used.
DS60001168L-page 126
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-16: U1SOF: USB SOF THRESHOLD REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0
CNT: SOF Threshold Value bits
Typical values of the threshold are:
01001010 = 64-byte packet
00101010 = 32-byte packet
00011010 = 16-byte packet
00010010 = 8-byte packet
REGISTER 10-17: U1BDTP1: USB BUFFER DESCRIPTOR TABLE PAGE 1 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
BDTPTRL
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-1
BDTPTRL: Buffer Descriptor Table Base Address bits
This 7-bit value provides address bits 15 through 9 of the Buffer Descriptor Table base address, which
defines the starting location of the Buffer Descriptor Table in system memory.
The 32-bit Buffer Descriptor Table base address is 512-byte aligned.
bit 0
Unimplemented: Read as ‘0’
2011-2019 Microchip Technology Inc.
DS60001168L-page 127
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-18: U1BDTP2: USB BUFFER DESCRIPTOR TABLE PAGE 2 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BDTPTRH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0
BDTPTRH: Buffer Descriptor Table Base Address bits
This 8-bit value provides address bits 23 through 16 of the Buffer Descriptor Table base address, which
defines the starting location of the Buffer Descriptor Table in system memory.
The 32-bit Buffer Descriptor Table base address is 512-byte aligned.
REGISTER 10-19: U1BDTP3: USB BUFFER DESCRIPTOR TABLE PAGE 3 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BDTPTRU
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8
Unimplemented: Read as ‘0’
bit 7-0
BDTPTRU: Buffer Descriptor Table Base Address bits
This 8-bit value provides address bits 31 through 24 of the Buffer Descriptor Table base address, defines the
starting location of the Buffer Descriptor Table in system memory.
The 32-bit Buffer Descriptor Table base address is 512-byte aligned.
DS60001168L-page 128
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-20: U1CNFG1: USB CONFIGURATION 1 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
UTEYE
UOEMON
—
USBSIDL
—
—
—
UASUSPND
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8
Unimplemented: Read as ‘0’
bit 7
UTEYE: USB Eye-Pattern Test Enable bit
1 = Eye-Pattern Test is enabled
0 = Eye-Pattern Test is disabled
bit 6
UOEMON: USB OE Monitor Enable bit
1 = OE signal is active; it indicates intervals during which the D+/D- lines are driving
0 = OE signal is inactive
bit 5
Unimplemented: Read as ‘0’
bit 4
USBSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when the device enters Idle mode
0 = Continue module operation when the device enters Idle mode
bit 3-1
Unimplemented: Read as ‘0’
bit 0
UASUSPND: Automatic Suspend Enable bit
1 = USB module automatically suspends upon entry to Sleep mode. See the USUSPEND bit
(U1PWRC) in Register 10-5.
0 = USB module does not automatically suspend upon entry to Sleep mode. Software must use the
USUSPEND bit (U1PWRC) to suspend the module, including the USB 48 MHz clock.
2011-2019 Microchip Technology Inc.
DS60001168L-page 129
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 10-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LSPD
RETRYDIS
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only)
1 = Direct connection to a Low-Speed device enabled
0 = Direct connection to a Low-Speed device disabled; hub required with PRE_PID
bit 6
RETRYDIS: Retry Disable bit (Host mode and U1EP0 only)
1 = Retry NAKed transactions disabled
0 = Retry NAKed transactions enabled; retry done in hardware
bit 5
Unimplemented: Read as ‘0’
bit 4
EPCONDIS: Bidirectional Endpoint Control bit
If EPTXEN = 1 and EPRXEN = 1:
1 = Disable Endpoint n from Control transfers; only TX and RX transfers allowed
0 = Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
Otherwise, this bit is ignored.
bit 3
EPRXEN: Endpoint Receive Enable bit
1 = Endpoint n receive is enabled
0 = Endpoint n receive is disabled
bit 2
EPTXEN: Endpoint Transmit Enable bit
1 = Endpoint n transmit is enabled
0 = Endpoint n transmit is disabled
bit 1
EPSTALL: Endpoint Stall Status bit
1 = Endpoint n was stalled
0 = Endpoint n was not stalled
bit 0
EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint Handshake is enabled
0 = Endpoint Handshake is disabled (typically used for isochronous endpoints)
DS60001168L-page 130
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
11.0
I/O PORTS
Note:
These functions depend on which peripheral features
are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose
I/O pin.
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS60001120), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
Key features of this module include:
• Individual output pin open-drain enable/disable
• Individual input pin weak pull-up and pull-down
• Monitor selective inputs and generate interrupt
when change in pin state is detected
• Operation during Sleep and Idle modes
• Fast bit manipulation using CLR, SET, and INV
registers
Figure 11-1 illustrates a block diagram of a typical
multiplexed I/O port.
General purpose I/O pins are the simplest of peripherals. They allow the PIC® MCU to monitor and control
other devices. To add flexibility and functionality, some
pins are multiplexed with alternate functions.
FIGURE 11-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Peripheral Module
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
PIO Module
RD ODC
Data Bus
D
SYSCLK
Q
ODC
CK
EN Q
WR ODC
1
RD TRIS
0
I/O Cell
0
1
D
Q
1
TRIS
CK
EN Q
WR TRIS
0
Output Multiplexers
D
Q
I/O Pin
LAT
CK
EN Q
WR LAT
WR PORT
RD LAT
1
RD PORT
0
Sleep
Q
Q
D
CK
Q
Q
D
CK
PBCLK
Synchronization
Peripheral Input
Legend:
Note:
R
Peripheral Input Buffer
R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
This block diagram is a general representation of a shared port/peripheral structure and is only provided for illustration purposes. The
actual structure for any specific port/peripheral combination may be different than it is shown here.
2011-2019 Microchip Technology Inc.
DS60001168L-page 131
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
11.1
Parallel I/O (PIO) Ports
All port pins have 10 registers directly associated with
their operation as digital I/O. The data direction register
(TRISx) determines whether the pin is an input or an
output. If the data direction bit is a ‘1’, then the pin is an
input. All port pins are defined as inputs after a Reset.
Reads from the latch (LATx) read the latch. Writes to
the latch write the latch. Reads from the port (PORTx)
read the port pins, while writes to the port pins write the
latch.
11.1.1
OPEN-DRAIN CONFIGURATION
In addition to the PORTx, LATx, and TRISx registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any desired 5Vtolerant pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
See the “Pin Diagrams” section for the available pins
and their functionality.
11.1.2
CONFIGURING ANALOG AND
DIGITAL PORT PINS
The ANSELx register controls the operation of the
analog port pins. The port pins that are to function as
analog inputs must have their corresponding ANSEL
and TRIS bits set. In order to use port pins for I/O
functionality with digital modules, such as Timers,
UARTs, etc., the corresponding ANSELx bit must be
cleared.
The ANSELx register has a default value of 0xFFFF;
therefore, all pins that share analog functions are
analog (not digital) by default.
If the TRIS bit is cleared (output) while the ANSELx bit
is set, the digital output level (VOH or VOL) is converted
by an analog peripheral, such as the ADC module or
Comparator module.
When the PORT register is read, all pins configured as
analog input channels are read as cleared (a low level).
Pins configured as digital inputs do not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
11.1.3
11.1.4
INPUT CHANGE NOTIFICATION
The input change notification function of the I/O ports
allows the PIC32MX1XX/2XX 28/36/44-pin Family
devices to generate interrupt requests to the processor
in response to a change-of-state on selected input pins.
This feature can detect input change-of-states even in
Sleep mode, when the clocks are disabled. Every I/O
port pin can be selected (enabled) for generating an
interrupt request on a change-of-state.
Five control registers are associated with the CN functionality of each I/O port. The CNENx registers contain
the CN interrupt enable control bits for each of the input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
The CNSTATx register indicates whether a change
occurred on the corresponding pin since the last read
of the PORTx bit.
Each I/O pin also has a weak pull-up and a weak
pull-down connected to it. The pull-ups act as a
current source or sink source connected to the pin,
and eliminate the need for external resistors when
push-button or keypad devices are connected. The
pull-ups and pull-downs are enabled separately using
the CNPUx and the CNPDx registers, which contain
the control bits for each of the pins. Setting any of
the control bits enables the weak pull-ups and/or
pull-downs for the corresponding pins.
Note:
Pull-ups and pull-downs on change notification pins should always be disabled
when the port pin is configured as a digital
output.
An additional control register (CNCONx) is shown in
Register 11-3.
11.2
CLR, SET and INV Registers
Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR, or INV register, the base register must be read.
I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP.
DS60001168L-page 132
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
11.3
Peripheral Pin Select
A major challenge in general purpose devices is providing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. The challenge is even greater on low pin-count devices. In an
application where more than one peripheral needs to
be assigned to a single pin, inconvenient workarounds
in application code or a complete redesign may be the
only option.
The Peripheral Pin Select (PPS) configuration provides
an alternative to these choices by enabling peripheral
set selection and their placement on a wide range of
I/O pins. By increasing the pinout options available on
a particular device, users can better tailor the device to
their entire application, rather than trimming the
application to fit the device.
The PPS configuration feature operates over a fixed
subset of digital I/O pins. Users may independently
map the input and/or output of most digital peripherals
to these I/O pins. PPS is performed in software and
generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral
mapping once it has been established.
11.3.1
AVAILABLE PINS
The number of available pins is dependent on the
particular device and its pin count. Pins that support the
PPS feature include the designation “RPn” in their full
pin designation, where “RP” designates a remappable
peripheral and “n” is the remappable port number.
11.3.2
Priority is given regardless of the type of peripheral that
is mapped. Remappable peripherals never take priority
over any analog functions associated with the pin.
11.3.3
PPS features are controlled through two sets of SFRs:
one to map peripheral inputs, and one to map outputs.
Because they are separately controlled, a particular
peripheral’s input and output (if the peripheral has both)
can be placed on any selectable function pin without
constraint.
The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on
whether an input or output is being mapped.
11.3.4
INPUT MAPPING
The inputs of the PPS options are mapped on the basis
of the peripheral. That is, a control register associated
with a peripheral dictates the pin it will be mapped to.
The [pin name]R registers, where [pin name] refers to the
peripheral pins listed in Table 11-1, are used to configure peripheral input mapping (see Register 11-1). Each
register contains sets of 4 bit fields. Programming these
bit fields with an appropriate value maps the RPn pin
with the corresponding value to that peripheral. For any
given device, the valid range of values for any bit field is
shown in Table 11-1.
For example, Figure 11-2 illustrates the remappable
pin selection for the U1RX input.
FIGURE 11-2:
AVAILABLE PERIPHERALS
The peripherals managed by the PPS are all digitalonly peripherals. These include general serial communications (UART and SPI), general purpose timer clock
inputs, timer-related peripherals (input capture and output compare) and interrupt-on-change inputs.
CONTROLLING PERIPHERAL PIN
SELECT
REMAPPABLE INPUT
EXAMPLE FOR U1RX
U1RXR
0
RPA2
1
In comparison, some digital-only peripheral modules
are never included in the PPS feature. This is because
the peripheral’s function requires special I/O circuitry
on a specific port and cannot be easily connected to
multiple pins. These modules include I2C among others. A similar requirement excludes all modules with
analog inputs, such as the Analog-to-Digital Converter
(ADC).
RPB6
A key difference between remappable and non-remappable peripherals is that remappable peripherals are
not associated with a default I/O pin. The peripheral
must always be assigned to a specific I/O pin before it
can be used. In contrast, non-remappable peripherals
are always available on a default pin, assuming that the
peripheral is active and not conflicting with another
peripheral.
RPn
2
RPA4
U1RX input
to peripheral
n
Note:
For input only, PPS functionality does not have
priority over TRISx settings. Therefore, when
configuring RPn pin for input, the corresponding
bit in the TRISx register must also be configured
for input (set to ‘1’).
When a remappable peripheral is active on a given I/O
pin, it takes priority over all other digital I/O and digital
communication peripherals associated with the pin.
2011-2019 Microchip Technology Inc.
DS60001168L-page 133
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 11-1:
INPUT PIN SELECTION
[pin name]R Value to
RPn Pin Selection
Peripheral Pin
[pin name]R SFR
[pin name]R bits
INT4
INT4R
INT4R
T2CK
T2CKR
T2CKR
IC4
IC4R
IC4R
SS1
SS1R
SS1R
REFCLKI
REFCLKIR
REFCLKIR
INT3
INT3R
INT3R
T3CK
T3CKR
T3CKR
IC3
IC3R
IC3R
U1CTS
U1CTSR
U1CTSR
U2RX
U2RXR
U2RXR
SDI1
SDI1R
SDI1R
INT2
INT2R
INT2R
T4CK
T4CKR
T4CKR
IC1
IC1R
IC1R
IC5
IC5R
IC5R
U1RX
U1RXR
U1RXR
U2CTS
U2CTSR
U2CTSR
SDI2
SDI2R
SDI2R
OCFB
OCFBR
OCFBR
INT1
INT1R
INT1R
T5CK
T5CKR
T5CKR
IC2
IC2R
IC2R
SS2
SS2R
SS2R
OCFA
OCFAR
OCFAR
Note 1:
2:
0000 = RPA0
0001 = RPB3
0010 = RPB4
0011 = RPB15
0100 = RPB7
0101 = RPC7(2)
0110 = RPC0(1)
0111 = RPC5(2)
1000 = Reserved
•
•
•
1111 = Reserved
0000 = RPA1
0001 = RPB5
0010 = RPB1
0011 = RPB11
0100 = RPB8
0101 = RPA8(2)
0110 = RPC8(2)
0111 = RPA9(2)
1000 = Reserved
•
•
•
1111 = Reserved
0000 = RPA2
0001 = RPB6
0010 = RPA4
0011 = RPB13
0100 = RPB2
0101 = RPC6(2)
0110 = RPC1(1)
0111 = RPC3(1)
1000 = Reserved
•
•
•
1111 = Reserved
0000 = RPA3
0001 = RPB14
0010 = RPB0
0011 = RPB10
0100 = RPB9
0101 = RPC9(1)
0110 = RPC2(2)
0111 = RPC4(2)
1000 = Reserved
•
•
•
1111 = Reserved
This pin is not available on 28-pin devices.
This pin is only available on 44-pin devices.
DS60001168L-page 134
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
11.3.5
OUTPUT MAPPING
11.3.6.1
In contrast to inputs, the outputs of the PPS options
are mapped on the basis of the pin. In this case, a
control register associated with a particular pin
dictates the peripheral output to be mapped. The
RPnR registers (Register 11-2) are used to control
output mapping. Like the [pin name]R registers, each
register contains sets of 4 bit fields. The value of the
bit field corresponds to one of the peripherals, and
that peripheral’s output is mapped to the pin (see
Table 11-2 and Figure 11-3).
A null output is associated with the output register reset
value of ‘0’. This is done to ensure that remappable
outputs remain disconnected from all output pins by
default.
FIGURE 11-3:
EXAMPLE OF
MULTIPLEXING OF
REMAPPABLE OUTPUT
FOR RPA0
RPA0R
Default
U1TX Output
U1RTS Output
0
1
2
RPA0
Output Data
Control Register Lock Sequence
Under normal operation, writes to the RPnR and [pin
name]R registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the Configuration bit,
IOLOCK (CFGCON). Setting IOLOCK prevents
writes to the control registers; clearing IOLOCK
allows writes.
To set or clear the IOLOCK bit, an unlock sequence
must be executed. Refer to Section 6. “Oscillator”
(DS60001112) in the “PIC32 Family Reference
Manual” for details.
11.3.6.2
Configuration Bit Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPnR and [pin name]R registers. The Configuration
bit, IOL1WAY (DEVCFG3), blocks the IOLOCK bit
from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure
does not execute, and the PPS control registers cannot
be written to. The only way to clear the bit and reenable peripheral remapping is to perform a device
Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session.
14
15
11.3.6
CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC32 devices include two features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Configuration bit select lock
2011-2019 Microchip Technology Inc.
DS60001168L-page 135
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 11-2:
OUTPUT PIN SELECTION
RPnR Value to Peripheral
Selection
RPn Port Pin
RPnR SFR
RPnR bits
RPA0
RPA0R
RPA0R
RPB3
RPB3R
RPB3R
RPB4
RPB4R
RPB4R
RPB15
RPB15R
RPB15R
RPB7
RPB7R
RPB7R
RPC7
RPC7R
RPC7R
RPC0
RPC0R
RPC0R
RPC5
RPC5R
RPC5R
RPA1
RPA1R
RPA1R
RPB5
RPB5R
RPB5R
RPB1
RPB1R
RPB1R
RPB11
RPB11R
RPB11R
RPB8
RPB8R
RPB8R
RPA8
RPA8R
RPA8R
RPC8
RPC8R
RPC8R
RPA9
RPA9R
RPA9R
1111 = Reserved
RPA2
RPA2R
RPA2R
RPB6
RPB6R
RPB6R
RPA4
RPA4R
RPA4R
RPB13
RPB13R
RPB13R
RPB2
RPB2R
RPB2R
RPC6
RPC6R
RPC6R
0000 = No Connect
0001 = Reserved
0010 = Reserved
0011 = SDO1
0100 = SDO2
0101 = OC4
0110 = OC5
0111 = REFCLKO
1000 = Reserved
RPC1
RPC1R
RPC1R
•
•
•
RPC3
RPC3R
RPC3R
1111 = Reserved
RPA3
RPA3R
RPA3R
RPB14
RPB14R
RPB14R
RPB0
RPB0R
RPB0R
RPB10
RPB10R
RPB10R
RPB9
RPB9R
RPB9R
RPC9
RPC9R
RPC9R
0000 = No Connect
0001 = U1RTS
0010 = U2TX
0011 = Reserved
0100 = SS2
0101 = OC3
0110 = Reserved
0111 = C1OUT
1000 = Reserved
RPC2
RPC2R
RPC2R
•
•
•
RPC4
RPC4R
RPC4R
1111 = Reserved
DS60001168L-page 136
0000 = No Connect
0001 = U1TX
0010 = U2RTS
0011 = SS1
0100 = Reserved
0101 = OC1
0110 = Reserved
0111 = C2OUT
1000 = Reserved
•
•
•
1111 = Reserved
0000 = No Connect
0001 = Reserved
0010 = Reserved
0011 = SDO1
0100 = SDO2
0101 = OC2
0110 = Reserved
0111 = C3OUT
•
•
•
2011-2019 Microchip Technology Inc.
Ports Control Registers
Virtual Address
(BF88_#)
TABLE 11-3:
6010
TRISA
PORTA
6030
LATA
6040
6050
6060
ODCA
CNPUA
CNPDA
6070 CNCONA
6080
CNENA
6090 CNSTATA
Legend:
Note
1:
2:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSA1
—
ANSA0
—
0003
0000
—
—
—
—
—
—
—
—
—
—
TRISA10(2)
—
TRISA9(2)
—
TRISA8(2)
—
TRISA7(2)
—
—
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
079F
0000
—
—
—
—
—
—
—
—
—
—
RA10(2)
—
RA9(2)
—
RA8(2)
—
RA7(2)
—
—
—
—
—
RA4
—
RA3
—
RA2
—
RA1
—
RA0
—
xxxx
0000
—
—
—
—
—
—
—
—
—
—
LATA10(2)
—
LATA9(2)
—
LATA8(2)
—
LATA7(2)
—
—
—
—
—
LATA4
—
LATA3
—
LATA2
—
LATA1
—
LATA0
—
xxxx
0000
—
—
—
—
—
—
—
—
—
—
ODCA10(2)
—
ODCA9(2)
—
ODCA8(2)
—
ODCA7(2)
—
—
—
—
—
ODCA4
—
ODCA3
—
ODCA2
—
ODCA1
—
ODCA0
—
0000
0000
—
—
—
—
—
—
—
—
—
—
CNPUA10(2)
—
CNPUA9(2)
—
CNPUA8(2)
—
CNPUA7(2)
—
—
—
—
—
CNPUA4
—
CNPUA3
—
CNPUA2
—
CNPUA1
—
CNPUA0 0000
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
CNPDA10(2)
—
CNPDA9(2)
—
CNPDA8(2)
—
CNPDA7(2)
—
—
—
—
—
CNPDA4
—
CNPDA3
—
CNPDA2
—
CNPDA1
—
CNPDA0 0000
—
0000
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Bits
6000 ANSELA
6020
PORTA REGISTER MAP
15:0
ON
31:16
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
—
—
—
—
—
—
—
—
—
—
CNIEA10(2)
—
CNIEA9(2)
—
CNIEA8(2)
—
CNIEA7(2)
—
—
—
—
—
CNIEA4
—
CNIEA3
—
CNIEA2
—
CNIEA1
—
CNIEA0
—
0000
0000
—
—
31:16
15:0
—
—
—
—
—
CNSTATA10(2) CNSTATA9(2) CNSTATA8(2) CNSTATA7(2)
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
CNSTATA4 CNSTATA3 CNSTATA2 CNSTATA1 CNSTATA0 0000
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
This bit is only available on 44-pin devices.
DS60001168L-page 137
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2011-2019 Microchip Technology Inc.
11.4
Virtual Address
(BF88_#)
6110
TRISB
6120
PORTB
6130
LATB
6140
ODCB
6150
CNPUB
6160
CNPDB
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
—
ANSB15
—
ANSB14
—
ANSB13
—
ANSB12(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSB3
—
ANSB2
—
—
0000
ANSB1
ANSB0
E00F
—
15:0 TRISB15
—
TRISB14
—
TRISB13
—
TRISB12(2)
—
TRISB11
—
TRISB10
—
TRISB9
—
TRISB8
—
TRISB7
—
TRISB6(2)
—
TRISB5
—
TRISB4
—
TRISB3
—
TRISB2
—
TRISB1
—
TRISB0
0000
FFFF
—
RB15
—
RB14
—
RB13
—
RB12(2)
—
RB11
—
RB10
—
RB9
—
RB8
—
RB7
—
RC6(2)
—
RB5
RB4
RB3
RB2
RB1
RB0
0000
xxxx
—
LATB15
—
LATB14
—
LATB13
—
LATB12(2)
—
LATB11
—
LATB10
—
LATB9
—
LATB8
—
LATB7
—
LATB6(2)
—
LATB5
—
LATB4
—
LATB3
—
LATB2
—
LATB1
—
LATB0
0000
xxxx
—
15:0 ODCB15
—
ODCB14
—
ODCB13
—
ODCB12(2)
—
ODCB11
—
ODCB10
—
ODCB9
—
ODCB8
—
ODCB7
—
ODCB6
—
ODCB5
—
ODCB4
—
ODCB3
—
ODCB2
—
ODCB1
—
ODCB0
0000
0000
31:16
15:0
31:16
31:16
15:0
31:16
15:0
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0 CNPUB15 CNPUB14 CNPUB13 CNPUB12(2) CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6(2) CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0 CNPDB15 CNPDB14 CNPDB13 CNPDB12(2) CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6(2) CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000
31:16
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
CNIEB14
—
CNIEB13
—
CNIEB11(2)
—
CNIEB11
—
CNIEB10
—
CNIEB9
—
CNIEB8
—
CNIEB7
—
CNIEB6(2)
—
CNIEB5
—
CNIEB4
—
CNIEB3
—
CNIEB2
—
CNIEB1
—
CNIEB0
0000
0000
—
—
—
—
—
—
—
—
CN
CN
CN
CN
CN
CN
CN
CN
STATB15 STATB14 STATB13 STATB12(2) STATB11 STATB10 STATB9 STATB8
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
CN
STATB7
—
CN
STATB6(2)
—
CN
STATB5
—
CN
STATB4
—
CN
STATB3
—
CN
STATB2
—
CN
STATB1
—
CN
STATB0
6170 CNCONB
CNENB
15:0
31:16
Note 1:
2:
—
ON
—
15:0 CNIEB15
31:16
6190 CNSTATB
Legend:
16/0
All Resets
Bit Range
Register
Name
Bits
6100 ANSELB
6180
PORTB REGISTER MAP
15:0
0000
0000
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
This bit is not available on PIC32MX2XX devices. The reset value for the TRISB register when this bit is not available is 0x0000EFBF.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 138
TABLE 11-4:
6210
TRISC
6220
PORTC
6230
LATC
6240
ODCC
6250
CNPUC
6260
CNPDC
6270 CNCONC
CNENC
6290 CNSTATC
Legend:
Note 1:
2:
3:
4:
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31/15 30/14 29/13 28/12 27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Register
Name(1,2)
Virtual Address
(BF88_#)
Bits
6200 ANSELC
6280
PORTC REGISTER MAP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSC3(4)
—
ANSC2(3)
—
—
ANSC1
ANSC0
0000
000F
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISC9
—
TRISC8(3)
—
TRISC7(3)
—
TRISC6(3)
—
TRISC5(3)
—
TRISC4(3)
—
TRISC3
—
TRISC2(3)
—
TRISC1
—
TRISC0
0000
03FF
—
—
—
—
—
—
—
—
—
—
—
—
—
RC9
—
RC8(3)
—
RC7(3)
—
RC6(3)
—
RC5(3)
RC4(3)
RC3
RC2(3)
RC1
RC0
0000
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
LATC9
—
LATC8(3)
—
LATC7(3)
—
LATC6(3)
—
LATC5(3)
—
LATC4(3)
—
LATC3
—
LATC2(3)
—
LATC1
—
LATC0
0000
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
ODCC9
—
ODCC8(3)
—
ODCC7(3)
—
ODCC6(3)
—
ODCC5(3)
—
ODCC4(3)
—
ODCC3
—
ODCC2(3)
—
ODCC1
—
ODCC0
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPUC9
—
CNPUC8(3)
—
CNPUC7(3)
—
CNPUC6(3)
—
CNPUC5(3)
—
CNPUC4(3)
—
CNPUC3
—
CNPUC2(3)
—
CNPUC1
—
0000
CNPUC0 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPDC9
—
CNPDC8(3)
—
CNPDC7(3)
—
CNPDC6(3)
—
CNPDC5(3)
—
CNPDC4(3)
—
CNPDC3
—
CNPDC2(3)
—
CNPDC1
—
0000
CNPDC0 0000
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIEC9
—
CNIEC8(3)
—
CNIEC7(3)
—
CNIEC6(3)
—
CNIEC5(3)
—
CNIEC4(3)
—
CNIEC3
—
CNIEC2(3)
—
CNIEC1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
0000
CNIEC0 0000
—
—
—
—
—
—
—
—
—
—
0000
CNSTATC9 CNSTATC8(3) CNSTATC7(3) CNSTATC6(3) CNSTATC5(3) CNSTATC4(3) CNSTATC3 CNSTATC2(3) CNSTATC1 CNSTATC0 0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
PORTC is not available on 28-pin devices.
This bit is only available on 44-pin devices.
This bit is only available on USB-enabled devices with 36 or 44 pins.
DS60001168L-page 139
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2011-2019 Microchip Technology Inc.
TABLE 11-5:
PERIPHERAL PIN SELECT INPUT REGISTER MAP
INT1R
FA08
INT2R
FA0C
INT3R
FA10
INT4R
FA18
T2CKR
FA1C
T3CKR
FA20
T4CKR
FA24
T5CKR
FA28
IC1R
FA2C
IC2R
FA30
IC3R
FA34
IC4R
FA38
IC5R
FA48
OCFAR
FA4C
OCFBR
FA50
U1RXR
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
INT1R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U1RXR
0000
0000
—
OCFBR
—
0000
0000
OCFAR
—
0000
0000
IC5R
—
0000
0000
IC4R
—
0000
0000
IC3R
—
0000
0000
IC2R
—
0000
0000
IC1R
—
0000
0000
T5CKR
—
0000
0000
T4CKR
—
0000
0000
T3CKR
—
0000
0000
T2CKR
—
0000
0000
INT4R
—
0000
0000
INT3R
—
0000
0000
INT2R
—
All Resets
FA04
Bit Range
Register
Name
2011-2019 Microchip Technology Inc.
Virtual Address
(BF80_#)
Bits
0000
0000
—
0000
0000
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 140
TABLE 11-6:
PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
U1CTSR
FA58
U2RXR
FA5C
U2CTSR
FA84
SDI1R
FA88
SS1R
FA90
SDI2R
FA94
SS2R
FAB8 REFCLKIR
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
18/2
17/1
16/0
—
—
—
U1CTSR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
REFCLKIR
0000
0000
—
SS2R
—
0000
0000
SDI2R
—
0000
0000
SS1R
—
0000
0000
SDI1R
—
0000
0000
U2CTSR
—
0000
0000
U2RXR
—
All Resets
Register
Name
FA54
Bit Range
Virtual Address
(BF80_#)
Bits
0000
0000
—
0000
0000
DS60001168L-page 141
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2011-2019 Microchip Technology Inc.
TABLE 11-6:
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP
2011-2019 Microchip Technology Inc.
FB00
RPA0R
FB04
RPA1R
FB08
RPA2R
FB0C
RPA3R
FB10
RPA4R
FB20
RPA8R(1)
FB24
RPA9R(1)
FB2C
RPB0R
FB30
RPB1R
FB34
RPB2R
FB38
RPB3R
FB3C
RPB4R
FB40
RPB5R
FB44
RPB6R(2)
FB48
RPB7R
Legend:
Note 1:
2:
3:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register is only available on 44-pin devices.
This register is only available on PIC32MX1XX devices.
This register is only available on 36-pin and 44-pin devices.
RPA0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RPB7
0000
0000
—
RPB6
—
0000
0000
RPB5
—
0000
0000
RPB4
—
0000
0000
RPB3
—
0000
0000
RPB2
—
0000
0000
RPB1
—
0000
0000
RPB0
—
0000
0000
RPA9
—
0000
0000
RPA8
—
0000
0000
RPA4
—
0000
0000
RPA3
—
0000
0000
RPA2
—
0000
0000
RPA1
—
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000
0000
—
0000
0000
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 142
TABLE 11-7:
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)
DS60001168L-page 143
FB4C
RPB8R
FB50
RPB9R
FB54
RPB10R
FB58
RPB11R
FB60
RPB13R
FB64
RPB14R
FB68
RPB15R
FB6C
RPC0R(3)
FB70
RPC1R(3)
FB74
RPC2R(1)
FB78
RPC3R(3)
FB7C
RPC4R(1)
FB80
RPC5R(1)
FB84
RPC6R(1)
FB88
RPC7R(1)
Legend:
Note 1:
2:
3:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register is only available on 44-pin devices.
This register is only available on PIC32MX1XX devices.
This register is only available on 36-pin and 44-pin devices.
RPB8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RPC7
0000
0000
—
RPC6
—
0000
0000
RPC5
—
0000
0000
RPC4
—
0000
0000
RPC3
—
0000
0000
RPC2
—
0000
0000
RPC1
—
0000
0000
RPC0
—
0000
0000
RPB15
—
0000
0000
RPB14
—
0000
0000
RPB13
—
0000
0000
RPB11
—
0000
0000
RPB10
—
0000
0000
RPB9
—
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000
0000
—
0000
0000
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2011-2019 Microchip Technology Inc.
TABLE 11-7:
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)
FB8C
RPC8R(1)
FB90
RPC9R(3)
Legend:
Note 1:
2:
3:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register is only available on 44-pin devices.
This register is only available on PIC32MX1XX devices.
This register is only available on 36-pin and 44-pin devices.
RPC8
—
—
—
RPC9
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000
0000
—
0000
0000
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 144
TABLE 11-7:
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 11-1:
Bit
Range
31:24
23:16
15:8
7:0
[pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
[pin name]R
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4
Unimplemented: Read as ‘0’
bit 3-0
[pin name]R: Peripheral Pin Select Input bits
Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Table 11-1 for
input pin selection values.
Note:
Register values can only be changed if the Configuration bit, IOLOCK (CFGCON), = 0.
REGISTER 11-2:
Bit
Range
31:24
23:16
15:8
7:0
RPnR: PERIPHERAL PIN SELECT OUTPUT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
RPnR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-4
Unimplemented: Read as ‘0’
bit 3-0
RPnR: Peripheral Pin Select Output bits
See Table 11-2 for output pin selection values.
Note:
x = Bit is unknown
Register values can only be changed if the Configuration bit, IOLOCK (CFGCON), = 0.
2011-2019 Microchip Technology Inc.
DS60001168L-page 145
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 11-3:
Bit
Range
31:24
23:16
15:8
7:0
CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (x = A, B, C)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ON
—
SIDL
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Change Notice (CN) Control ON bit
1 = CN is enabled
0 = CN is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Control bit
1 = Idle mode halts CN operation
0 = Idle does not affect CN operation
bit 12-0
Unimplemented: Read as ‘0’
DS60001168L-page 146
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
12.0
TIMER1
Note:
The following modes are supported:
•
•
•
•
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS60001105), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
12.1
Additional Supported Features
• Selectable clock prescaler
• Timer operation during CPU Idle and Sleep mode
• Fast bit manipulation using CLR, SET and INV
registers
• Asynchronous mode can be used with the SOSC
to function as a Real-Time Clock (RTC)
This family of PIC32 devices features one
synchronous/asynchronous 16-bit timer that can operate
as a free-running interval timer for various timing applications and counting external events. This timer can also
be used with the Low-Power Secondary Oscillator
(SOSC) for Real-Time Clock (RTC) applications.
FIGURE 12-1:
Synchronous Internal Timer
Synchronous Internal Gated Timer
Synchronous External Timer
Asynchronous External Timer
Figure 12-1 illustrates a general block diagram of
Timer1.
TIMER1 BLOCK DIAGRAM
Data Bus
TSYNC
1
Reset
Sync
TMR1
0
Equal
16-bit Comparator
PR1
T1IF
Event Flag
0
Q
1
TGATE
D
Q
TGATE
TCS
ON
SOSCO/T1CK
x1
SOSCEN
SOSCI
Gate
Sync
PBCLK
10
00
Prescaler
1, 8, 64, 256
2
TCKPS
Note:
The default state of the SOSCEN (OSCCON) bit during a device Reset is controlled by the
FSOSCEN bit in Configuration Word, DEVCFG1.
2011-2019 Microchip Technology Inc.
DS60001168L-page 147
Timer1 Control Registers
Virtual Address
(BF80_#)
TABLE 12-1:
TMR1
0620
Legend:
Note 1:
PR1
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
15:0
ON
31:16
—
—
—
SIDL
—
15:0
31:16
—
—
—
—
23/7
22/6
21/5
20/4
19/3
—
—
—
—
TWDIS
—
TWIP
—
—
—
—
—
—
—
—
—
18/2
—
—
—
—
—
—
—
—
TGATE
—
—
—
TCKPS
—
—
—
—
17/1
16/0
—
—
—
0000
TSYNC
—
TCS
—
—
—
0000
0000
—
—
—
—
—
—
TMR1
—
15:0
PR1
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All Resets
Bit Range
Register
Name(1)
Bits
0600 T1CON
0610
TIMER1 REGISTER MAP
0000
—
0000
FFFF
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 148
12.2
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 12-1:
Bit
Range
31:24
23:16
15:8
7:0
T1CON: TYPE A TIMER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
R/W-0
R-0
U-0
U-0
U-0
ON(1)
—
SIDL
TWDIS
TWIP
—
—
—
R/W-0
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
TGATE
—
—
TSYNC
TCS
—
TCKPS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Timer On bit(1)
1 = Timer is enabled
0 = Timer is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when the device enters Idle mode
0 = Continue module operation when the device enters Idle mode
bit 12
TWDIS: Asynchronous Timer Write Disable bit
1 = Writes to Timer1 are ignored until pending write operation completes
0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
bit 11
TWIP: Asynchronous Timer Write in Progress bit
In Asynchronous Timer mode:
1 = Asynchronous write to the Timer1 register in progress
0 = Asynchronous write to Timer1 register is complete
In Synchronous Timer mode:
This bit is read as ‘0’.
bit 10-8
Unimplemented: Read as ‘0’
bit 7
TGATE: Timer Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5-4
TCKPS: Timer Input Clock Prescale Select bits
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
Note 1:
When using 1:1 PBCmLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2011-2019 Microchip Technology Inc.
DS60001168L-page 149
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 12-1:
T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED)
bit 3
Unimplemented: Read as ‘0’
bit 2
TSYNC: Timer External Clock Input Synchronization Selection bit
When TCS = 1:
1 = External clock input is synchronized
0 = External clock input is not synchronized
When TCS = 0:
This bit is ignored.
bit 1
TCS: Timer Clock Source Select bit
1 = External clock from TxCKI pin
0 = Internal peripheral clock
bit 0
Unimplemented: Read as ‘0’
Note 1:
When using 1:1 PBCmLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS60001168L-page 150
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
13.0
Note:
TIMER2/3, TIMER4/5
• Synchronous internal 32-bit timer
• Synchronous internal 32-bit gated timer
• Synchronous external 32-bit timer
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS60001105), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
Note:
13.1
This family of PIC32 devices features four synchronous
16-bit timers (default) that can operate as a freerunning interval timer for various timing applications
and counting external events. The following modes are
supported:
Additional Supported Features
• Selectable clock prescaler
• Timers operational during CPU idle
• Time base for Input Capture and Output Compare
modules (Timer2 and Timer3 only)
• ADC event trigger (Timer3 in 16-bit mode,
Timer2/3 in 32-bit mode)
• Fast bit manipulation using CLR, SET and INV
registers
• Synchronous internal 16-bit timer
• Synchronous internal 16-bit gated timer
• Synchronous external 16-bit timer
Figure 13-1 and Figure 13-2 illustrate block diagrams
of Timer2/3 and Timer4/5.
Two 32-bit synchronous timers are available by
combining Timer2 with Timer3 and Timer4 with Timer5.
The 32-bit timers can operate in three modes:
FIGURE 13-1:
In this chapter, references to registers,
TxCON, TMRx and PRx, use ‘x’ to
represent Timer2 through Timer5 in 16-bit
modes. In 32-bit modes, ‘x’ represents
Timer2 or Timer4 and ‘y’ represents
Timer3 or Timer5.
TIMER2-TIMER5 BLOCK DIAGRAM (16-BIT)
Data Bus
Reset
Sync
TMRx
ADC Event
Trigger(1)
Equal
Comparator x 16
PRx
TxIF
Event Flag
0
1
TGATE
Q
TGATE
D
Q
TCS
ON
TxCK
x1
Gate
Sync
PBCLK
Note
1:
ADC event trigger is available on Timer3 only.
2011-2019 Microchip Technology Inc.
10
00
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
3
TCKPS
DS60001168L-page 151
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 13-2:
TIMER2/3, TIMER4/5 BLOCK DIAGRAM (32-BIT)
Data Bus
Reset
TMRy(1)
MS Half Word
ADC Event
Trigger(2)
Equal
Sync
LS Half Word
32-bit Comparator
PRy
TyIF Event
Flag
TMRx(1)
PRx
0
1
TGATE
Q
D
TGATE
Q
TCS
ON
TxCK
x1
Gate
Sync
PBCLK
10
00
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
3
TCKPS
Note 1:
2:
In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the
use of ‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5.
ADC event trigger is available only on the Timer2/3 pair.
DS60001168L-page 152
2011-2019 Microchip Technology Inc.
Timer Control Registers
Virtual Address
(BF80_#)
TABLE 13-1:
TMR2
0820
PR2
0A00 T3CON
0A10 TMR3
0A20
PR3
0C00 T4CON
0C10 TMR4
0C20
PR4
0E00 T5CON
0E10 TMR5
0E20
Legend:
Note 1:
PR5
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
15:0
ON
31:16
15:0
31:16
23/7
22/6
—
—
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21/5
20/4
19/3
18/2
—
—
—
—
TGATE
—
—
—
—
TCKPS
—
—
—
—
T32
—
17/1
16/0
—
—
—
0000
—
—
TCS
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
TCKPS
—
—
—
—
—
—
TCS
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
TCKPS
—
—
T32
—
—
—
TCS
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
TCKPS
—
—
—
—
—
—
TCS
—
—
—
0000
0000
—
—
—
—
—
—
—
TMR2
—
15:0
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
31:16
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
TGATE
—
15:0
31:16
—
—
—
—
—
—
—
—
0000
PR2
15:0
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
31:16
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
TGATE
—
15:0
31:16
—
—
—
—
—
—
—
—
0000
PR3
15:0
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
31:16
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
TGATE
—
15:0
31:16
—
—
—
—
—
—
—
—
0000
PR4
15:0
PR5
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
FFFF
TMR5
—
0000
FFFF
TMR4
—
0000
FFFF
TMR3
—
All Resets
Bit Range
Register
Name(1)
Bits
0800 T2CON
0810
TIMER2-TIMER5 REGISTER MAP
0000
0000
FFFF
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
DS60001168L-page 153
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2011-2019 Microchip Technology Inc.
13.2
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 13-1:
Bit
Range
31:24
23:16
15:8
7:0
TXCON: TYPE B TIMER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ON(1,3)
—
SIDL(4)
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
T32(2)
—
TCS(3)
—
TGATE(3)
TCKPS(3)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15
ON: Timer On bit(1,3)
1 = Module is enabled
0 = Module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit(4)
1 = Discontinue module operation when the device enters Idle mode
0 = Continue module operation when the device enters Idle mode
bit 12-8
Unimplemented: Read as ‘0’
bit 7
TGATE: Timer Gated Time Accumulation Enable bit(3)
When TCS = 1:
This bit is ignored and is read as ‘0’.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6-4
TCKPS: Timer Input Clock Prescale Select bits(3)
111 = 1:256 prescale value
110 = 1:64 prescale value
101 = 1:32 prescale value
100 = 1:16 prescale value
011 = 1:8 prescale value
010 = 1:4 prescale value
001 = 1:2 prescale value
000 = 1:1 prescale value
Note 1:
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
This bit is available only on even numbered timers (Timer2 and Timer4).
While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer3, and Timer5). All
timer functions are set through the even numbered timers.
While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
2:
3:
4:
DS60001168L-page 154
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 13-1:
TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED)
bit 3
T32: 32-Bit Timer Mode Select bit(2)
1 = Odd numbered and even numbered timers form a 32-bit timer
0 = Odd numbered and even numbered timers form a separate 16-bit timer
bit 2
Unimplemented: Read as ‘0’
bit 1
TCS: Timer Clock Source Select bit(3)
1 = External clock from TxCK pin
0 = Internal peripheral clock
bit 0
Unimplemented: Read as ‘0’
Note 1:
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
This bit is available only on even numbered timers (Timer2 and Timer4).
While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer3, and Timer5). All
timer functions are set through the even numbered timers.
While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
2:
3:
4:
2011-2019 Microchip Technology Inc.
DS60001168L-page 155
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
NOTES:
DS60001168L-page 156
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
14.0
WATCHDOG TIMER (WDT)
Note:
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 9. “Watchdog,
Deadman, and Power-up Timers”
(DS60001114), which are available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
FIGURE 14-1:
The WDT, when enabled, operates from the internal
Low-Power Oscillator (LPRC) clock source and can be
used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in
software. Various WDT time-out periods can be
selected using the WDT postscaler. The WDT can also
be used to wake the device from Sleep or Idle mode.
The following are some of the key features of the WDT
module:
• Configuration or software controlled
• User-configurable time-out period
• Can wake the device from Sleep or Idle mode
Figure 14-1 illustrates a block diagram of the WDT and
Power-up timer.
WATCHDOG TIMER AND POWER-UP TIMER BLOCK DIAGRAM
PWRT Enable
WDT Enable
LPRC
Control
PWRT Enable
1:64 Output
LPRC
Oscillator
PWRT
1
Clock
25-bit Counter
WDTCLR = 1
WDT Enable
Wake
WDT Enable
Reset Event
25
WDT Counter Reset
0
Device Reset
1
NMI (Wake-up)
Power Save
Decoder
FWDTPS (DEVCFG1)
2011-2019 Microchip Technology Inc.
DS60001168L-page 157
Watchdog Timer Control Registers
Virtual Address
(BF80_#)
TABLE 14-1:
Legend:
1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
20/4
19/3
18/2
—
—
—
SWDTPS
17/1
16/0
—
—
WDTWINEN WDTCLR
All Resets
Bit Range
Register
Name(1)
Bits
0000 WDTCON
Note
WATCHDOG TIMER CONTROL REGISTER MAP
0000
0000
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 158
14.1
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 14-1:
Bit
Range
31:24
23:16
15:8
7:0
WDTCON: WATCHDOG TIMER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
R/W-0
(1,2)
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
R-y
R-y
R-y
R-y
R-y
R/W-0
R/W-0
ON
—
Legend:
SWDTPS
WDTWINEN WDTCLR
y = Values set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Watchdog Timer Enable bit(1,2)
1 = Enables the WDT if it is not enabled by the device configuration
0 = Disable the WDT if it was enabled in software
bit 14-7
Unimplemented: Read as ‘0’
bit 6-2
SWDTPS: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits
On reset, these bits are set to the values of the WDTPS of Configuration bits.
bit 1
WDTWINEN: Watchdog Timer Window Enable bit
1 = Enable windowed Watchdog Timer
0 = Disable windowed Watchdog Timer
bit 0
WDTCLR: Watchdog Timer Reset bit
1 = Writing a ‘1’ will clear the WDT
0 = Software cannot force this bit to a ‘0’
Note 1:
2:
A read of this bit results in a ‘1’ if the Watchdog Timer is enabled by the device configuration or software.
When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2011-2019 Microchip Technology Inc.
DS60001168L-page 159
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
NOTES:
DS60001168L-page 160
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
15.0
Note:
INPUT CAPTURE
• Prescaler capture event modes:
- Capture timer value on every 4th rising edge of
input at ICx pin
- Capture timer value on every 16th rising edge of
input at ICx pin
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 15. “Input Capture” (DS60001122), which is available
from the Documentation > Reference
Manual section of the Microchip PIC32
web site (www.microchip.com/pic32).
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base,
or two 16-bit timers (Timer2 and Timer3) together to
form a 32-bit timer. The selected timer can use either
an internal or external clock.
Other operational features include:
• Device wake-up from capture pin during Sleep
and Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values (interrupt
optionally generated after 1, 2, 3, or 4 buffer
locations are filled)
• Input capture can also be used to provide
additional sources of external interrupts
The Input Capture module is useful in applications
requiring frequency (period) and pulse measurement.
The Input Capture module captures the 16-bit or 32-bit
value of the selected Time Base registers when an
event occurs at the ICx pin. The following events cause
capture events:
• Simple capture event modes:
- Capture timer value on every rising and falling
edge of input at ICx pin
- Capture timer value on every edge (rising
and falling)
- Capture timer value on every edge (rising
and falling), specified edge first.
FIGURE 15-1:
Figure 15-1 illustrates a general block diagram of the
Input Capture module.
INPUT CAPTURE BLOCK DIAGRAM
FEDGE
Specified/Every
Edge Mode
ICM
110
Prescaler Mode
(16th Rising Edge)
101
Prescaler Mode
(4th Rising Edge)
100
Rising Edge Mode
011
TMR2 TMR3
C32 || ICTMR
Capture Event
ICx pin
To CPU
FIFO CONTROL
ICxBUF
Falling Edge Mode
FIFO
010
ICI
Edge Detection
Mode
001
ICM
Set Flag ICxIF
(In IFSx Register)
/N
Sleep/Idle
Wake-up Mode
001
111
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
2011-2019 Microchip Technology Inc.
DS60001168L-page 161
Input Capture Control Registers
Virtual Address
(BF80_#)
TABLE 15-1:
IC1BUF
31/15
30/14
31:16
—
15:0
ON
31:16
15:0
2210
31:16
15:0
2400 IC3CON(1)
31:16
15:0
2410
31:16
15:0
IC3BUF
2600 IC4CON(1)
31:16
15:0
2610
31:16
15:0
IC4BUF
2800 IC5CON(1)
31:16
15:0
2810
31:16
15:0
IC5BUF
Legend:
Note 1:
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
SIDL
—
—
—
FEDGE
31:16
15:0
2200 IC2CON(1)
IC2BUF
29/13
24/8
23/7
22/6
21/5
—
—
—
—
C32
ICTMR
ICI
20/4
19/3
18/2
—
—
—
ICOV
ICBNE
17/1
16/0
—
—
ICM
—
—
—
SIDL
—
—
—
—
—
—
—
FEDGE
—
C32
—
ICTMR
xxxx
xxxx
—
—
ICI
—
ICOV
—
ICBNE
—
—
ICM
—
—
—
—
SIDL
—
—
—
—
—
—
—
FEDGE
—
C32
—
ICTMR
—
—
ICI
—
ICOV
—
ICBNE
—
—
ICM
—
—
—
—
SIDL
—
—
—
—
—
—
—
FEDGE
—
C32
—
ICTMR
—
—
ICI
—
ICOV
—
ICBNE
—
—
ICM
—
—
—
—
SIDL
—
—
—
—
—
—
—
FEDGE
—
C32
—
ICTMR
IC5BUF
0000
0000
xxxx
xxxx
IC4BUF
—
ON
0000
0000
xxxx
xxxx
IC3BUF
—
ON
0000
0000
xxxx
xxxx
IC2BUF
—
ON
0000
0000
IC1BUF
—
ON
All Resets
Bit Range
Register
Name
Bits
2000 IC1CON(1)
2010
INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP
—
—
ICI
—
ICOV
—
ICBNE
—
—
ICM
—
0000
0000
xxxx
xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 162
15.1
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 15-1:
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
(1)
U-0
R/W-0
—
SIDL
R/W-0
R/W-0
31:24
23:16
15:8
7:0
ICXCON: INPUT CAPTURE ‘x’ CONTROL REGISTER
ON
ICTMR
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
FEDGE
C32
R-0
R-0
R/W-0
R/W-0
R/W-0
ICOV
ICBNE
R/W-0
ICI
ICM
Legend:
R = Readable bit
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = unknown)
U = Unimplemented bit
P = Programmable bit
r = Reserved bit
bit 31-16
Unimplemented: Read as ‘0’
bit 15
ON: Input Capture Module Enable bit(1)
1 = Module is enabled
0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Control bit
1 = Halt in Idle mode
0 = Continue to operate in Idle mode
bit 12-10
Unimplemented: Read as ‘0’
bit 9
FEDGE: First Capture Edge Select bit (only used in mode 6, ICM = 110)
1 = Capture rising edge first
0 = Capture falling edge first
bit 8
C32: 32-bit Capture Select bit
1 = 32-bit timer resource capture
0 = 16-bit timer resource capture
bit 7
ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON) is ‘1’)
0 = Timer3 is the counter source for capture
1 = Timer2 is the counter source for capture
bit 6-5
ICI: Interrupt Control bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4
ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture overflow has occurred
0 = No input capture overflow has occurred
bit 3
ICBNE: Input Capture Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty; at least one more capture value can be read
0 = Input capture buffer is empty
Note 1:
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2011-2019 Microchip Technology Inc.
DS60001168L-page 163
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 15-1:
bit 2-0
Note 1:
ICXCON: INPUT CAPTURE ‘x’ CONTROL REGISTER (CONTINUED)
ICM: Input Capture Mode Select bits
111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter
101 = Prescaled Capture Event mode – every sixteenth rising edge
100 = Prescaled Capture Event mode – every fourth rising edge
011 = Simple Capture Event mode – every rising edge
010 = Simple Capture Event mode – every falling edge
001 = Edge Detect mode – every edge (rising and falling)
000 = Input Capture module is disabled
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS60001168L-page 164
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
16.0
Note:
OUTPUT COMPARE
The following are some of the key features:
• Multiple Output Compare Modules in a device
• Programmable interrupt generation on compare
event
• Single and Dual Compare modes
• Single and continuous output pulse generation
• Pulse-Width Modulation (PWM) mode
• Hardware-based PWM Fault detection and
automatic output disable
• Can operate from either of two available 16-bit
time bases or a single 32-bit time base
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 16. “Output Compare” (DS60001111), which is available
from the Documentation > Reference
Manual section of the Microchip PIC32
web site (www.microchip.com/pic32).
The Output Compare module is used to generate a single pulse or a train of pulses in response to selected
time base events. For all modes of operation, the Output Compare module compares the values stored in
the OCxR and/or the OCxRS registers to the value in
the selected timer. When a match occurs, the Output
Compare module generates an event based on the
selected mode of operation.
FIGURE 16-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit
OCxIF(1)
OCxRS(1)
Output
Logic
OCxR(1)
3
OCM
Mode Select
Comparator
0
16
Timer2
OCTSEL
1
0
S
R
Output
Enable
Q
OCx(1)
Output Enable
Logic
OCFA or OCFB(2)
1
16
Timer3
Timer2
Rollover
Timer3
Rollover
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels,
1 through 5.
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.
2011-2019 Microchip Technology Inc.
DS60001168L-page 165
Output Compare Control Registers
Virtual Address
(BF80_#)
TABLE 16-1:
OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP
3000 OC1CON
31:16
15:0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OC32
—
OCFLT
—
OCTSEL
—
—
OCM
—
All Resets
Bit Range
Register
Name(1)
Bits
0000
0000
3010
OC1R
31:16
15:0
OC1R
xxxx
xxxx
3020
OC1RS
31:16
15:0
OC1RS
xxxx
xxxx
3200 OC2CON
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OC32
—
OCFLT
—
OCTSEL
—
—
OCM
—
0000
0000
3210
OC2R
31:16
15:0
OC2R
xxxx
xxxx
3220
OC2RS
31:16
15:0
OC2RS
xxxx
xxxx
3400 OC3CON
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OC32
—
OCFLT
—
OCTSEL
—
—
OCM
—
0000
0000
3410
OC3R
31:16
15:0
OC3R
xxxx
xxxx
3420
OC3RS
31:16
15:0
OC3RS
xxxx
xxxx
3600 OC4CON
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OC32
—
OCFLT
—
OCTSEL
—
—
OCM
—
0000
0000
2011-2019 Microchip Technology Inc.
3610
OC4R
31:16
15:0
OC4R
xxxx
xxxx
3620
OC4RS
31:16
15:0
OC4RS
xxxx
xxxx
3800 OC5CON
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OC32
—
OCFLT
—
OCTSEL
—
—
OCM
—
0000
0000
3810
OC5R
31:16
15:0
OC5R
xxxx
xxxx
3820
OC5RS
31:16
15:0
OC5RS
xxxx
xxxx
Legend:
Note 1:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 166
16.1
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 16-1:
Bit
Range
31:24
23:16
15:8
7:0
OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
(1)
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
SIDL
—
—
—
—
—
U-0
U-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
OC32
OCFLT(2)
OCTSEL
ON
OCM
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Output Compare Peripheral On bit(1)
1 = Output Compare peripheral is enabled
0 = Output Compare peripheral is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when the device enters Idle mode
0 = Continue module operation when the device enters Idle mode
bit 12-6
Unimplemented: Read as ‘0’
bit 5
OC32: 32-bit Compare Mode bit
1 = OCxR and/or OCxRS are used for comparisons to the 32-bit timer source
0 = OCxR and OCxRS are used for comparisons to the 16-bit timer source
bit 4
OCFLT: PWM Fault Condition Status bit(2)
1 = PWM Fault condition has occurred (cleared in hardware only)
0 = No PWM Fault condition has occurred
bit 3
OCTSEL: Output Compare Timer Select bit
1 = Timer3 is the clock source for this Output Compare module
0 = Timer2 is the clock source for this Output Compare module
bit 2-0
OCM: Output Compare Mode Select bits
111 = PWM mode on OCx; Fault pin enabled
110 = PWM mode on OCx; Fault pin disabled
101 = Initialize OCx pin low; generate continuous output pulses on OCx pin
100 = Initialize OCx pin low; generate single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initialize OCx pin high; compare event forces OCx pin low
001 = Initialize OCx pin low; compare event forces OCx pin high
000 = Output compare peripheral is disabled but continues to draw current
Note 1:
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
This bit is only used when OCM = ‘111’. It is read as ‘0’ in all other modes.
2:
2011-2019 Microchip Technology Inc.
DS60001168L-page 167
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
NOTES:
DS60001168L-page 168
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
17.0
Note:
SERIAL PERIPHERAL
INTERFACE (SPI)
Some of the key features of the SPI module are:
•
•
•
•
•
Master mode and Slave mode support
Four clock formats
Enhanced Framed SPI protocol support
User-configurable 8-bit, 16-bit and 32-bit data width
Separate SPI FIFO buffers for receive and transmit
- FIFO buffers act as 4/8/16-level deep FIFOs
based on 32/16/8-bit data width
• Programmable interrupt event on every 8-bit,
16-bit and 32-bit data transfer
• Operation during Sleep and Idle modes
• Audio Codec Support:
- I2S protocol
- Left-justified
- Right-justified
- PCM
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 23. “Serial
Peripheral
Interface
(SPI)”
(DS60001106), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The SPI module is a synchronous serial interface that
is useful for communicating with external peripherals
and other microcontrollers. These peripheral devices
may be Serial EEPROMs, Shift registers, display drivers, Analog-to-Digital Converters (ADC), etc. The
PIC32 SPI module is compatible with Motorola® SPI
and SIOP interfaces.
FIGURE 17-1:
SPI MODULE BLOCK DIAGRAM
Internal
Data Bus
SPIxBUF
Read
Write
SPIxRXB FIFO
FIFOs Share Address SPIxBUF
SPIxTXB FIFO
Transmit
Receive
SPIxSR
SDIx
bit 0
SDOx
SSx/FSYNC
Slave Select
and Frame
Sync Control
Shift
Control
Clock
Control
MCLKSEL
Edge
Select
SCKx
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.
2011-2019 Microchip Technology Inc.
1
REFCLK
0
PBCLK
Baud Rate
Generator
MSTEN
DS60001168L-page 169
SPI Control Registers
SPI1 AND SPI2 REGISTER MAP
5800 SPI1CON
5810 SPI1STAT
5820 SPI1BUF
5830 SPI1BRG
31:16
FRMEN
15:0
ON
31:16
15:0
5A00 SPI2CON
5A10 SPI2STAT
5A20 SPI2BUF
5A30 SPI2BRG
5A40 SPI2CON2
2011-2019 Microchip Technology Inc.
Legend:
Note 1:
30/14
29/13
FRMSYNC FRMPOL
28/12
27/11
MSSEN
FRMSYPW
26/10
25/9
24/8
DISSDO
—
SIDL
—
MODE32 MODE16
SMP
RXBUFELM
—
—
—
FRMERR
SPIBUSY
—
—
23/7
22/6
21/5
20/4
MCLKSEL
—
—
—
CKE
SSEN
—
CKP
—
MSTEN
—
DISSDI
SPITUR
SRMT
SPIROV
SPIRBE
—
FRMCNT
—
—
31:16
19/3
18/2
17/1
—
—
SPIFE
16/0
ENHBUF 0000
STXISEL
SRXISEL
TXBUFELM
SPITBE
—
SPITBF
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
15:0
SPI
SGNEXT
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
IGNROV
IGNTUR
AUDEN
31:16
FRMEN
MSSEN
FRMSYPW
15:0
ON
31:16
15:0
FRMSYNC FRMPOL
0000
DISSDO
—
SIDL
—
MODE32 MODE16
SMP
RXBUFELM
—
—
—
FRMERR
SPIBUSY
—
—
31:16
—
BRG
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
0000
0000
—
—
AUD
MONO
—
—
—
AUDMOD
MCLKSEL
—
—
—
CKE
SSEN
—
CKP
—
MSTEN
—
DISSDI
SPITUR
SRMT
SPIROV
SPIRBE
—
SPITBE
—
SPITBF
—
—
—
—
—
—
FRMCNT
—
—
SPIFE
31:16
—
—
—
15:0
31:16
—
—
—
—
—
—
15:0
SPI
SGNEXT
—
—
—
—
—
—
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
—
—
IGNROV
—
—
IGNTUR
—
—
AUDEN
0000
ENHBUF 0000
STXISEL
SRXISEL
TXBUFELM
DATA
15:0
0000
0000
SPIRBF 0008
DATA
15:0
31:16
5840 SPI1CON2
31/15
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF80_#)
TABLE 17-1:
0000
0000
SPIRBF 0008
0000
0000
BRG
—
—
—
—
—
—
—
—
AUD
MONO
—
—
—
0000
—
0000
0000
AUDMOD
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV
Registers” for more information.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 170
17.1
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 17-1:
Bit
Range
31:24
SPIxCON: SPI CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMEN
FRMSYNC
FRMPOL
MSSEN
FRMSYPW
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
FRMCNT
23:16
R/W-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
MCLKSEL(2)
—
—
—
—
—
SPIFE
ENHBUF(2)
15:8
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ON(1)
—
SIDL
DISSDO
MODE32
MODE16
SMP
CKE(3)
R/W-0
R/W-0
R/W-0
R/W-0
7:0
R/W-0
R/W-0
R/W-0
R/W-0
SSEN
CKP(4)
MSTEN
DISSDI
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
STXISEL
SRXISEL
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
FRMEN: Framed SPI Support bit
1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)
0 = Framed SPI support is disabled
bit 30
FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only)
1 = Frame sync pulse input (Slave mode)
0 = Frame sync pulse output (Master mode)
bit 29
FRMPOL: Frame Sync / Slave Select Polarity bit (Framed SPI or Master Transmit modes only)
1 = Frame pulse or SSx pin is active-high
0 = Frame pulse or SSx pin is active-low
bit 28
MSSEN: Master Mode Slave Select Enable bit
1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in
Master mode. Polarity is determined by the FRMPOL bit.
0 = Slave select SPI support is disabled.
bit 27
FRMSYPW: Frame Sync Pulse Width bit
1 = Frame sync pulse is one character wide
0 = Frame sync pulse is one clock wide
bit 26-24 FRMCNT: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per
pulse. This bit is only valid in FRAMED_SYNC mode.
111 = Reserved; do not use
110 = Reserved; do not use
101 = Generate a frame sync pulse on every 32 data characters
100 = Generate a frame sync pulse on every 16 data characters
011 = Generate a frame sync pulse on every 8 data characters
010 = Generate a frame sync pulse on every 4 data characters
001 = Generate a frame sync pulse on every 2 data characters
000 = Generate a frame sync pulse on every data character
bit 23
MCLKSEL: Master Clock Enable bit(2)
1 = REFCLK is used by the Baud Rate Generator
0 = PBCLK is used by the Baud Rate Generator
bit 22-18 Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
This bit can only be written when the ON bit = 0.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
When AUDEN = 1, the SPI module functions as if the CKP bit is equal to ‘1’, regardless of the actual value
of CKP.
2011-2019 Microchip Technology Inc.
DS60001168L-page 171
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 17-1:
SPIxCON: SPI CONTROL REGISTER (CONTINUED)
bit 17
SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only)
1 = Frame synchronization pulse coincides with the first bit clock
0 = Frame synchronization pulse precedes the first bit clock
bit 16
ENHBUF: Enhanced Buffer Enable bit(2)
1 = Enhanced Buffer mode is enabled
0 = Enhanced Buffer mode is disabled
bit 15
ON: SPI Peripheral On bit(1)
1 = SPI Peripheral is enabled
0 = SPI Peripheral is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when the device enters Idle mode
0 = Continue module operation when the device enters Idle mode
bit 12
DISSDO: Disable SDOx pin bit
1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register
0 = SDOx pin is controlled by the module
bit 11-10 MODE: 32/16-Bit Communication Select bits
When AUDEN = 1:
MODE32
MODE16
Communication
1
1
24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
1
0
32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
0
1
16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame
0
0
16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame
When AUDEN = 0:
MODE32
MODE16
Communication
1
x
32-bit
0
1
16-bit
0
0
8-bit
SMP: SPI Data Input Sample Phase bit
Master mode (MSTEN = 1):
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode (MSTEN = 0):
SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.
bit 9
To write a '1' to this bit, the MSTEN value = 1 must first be written.
CKE: SPI Clock Edge Select bit(3)
1 = Serial output data changes on transition from active clock state to Idle clock state (see the CKP bit)
0 = Serial output data changes on transition from Idle clock state to active clock state (see the CKP bit)
SSEN: Slave Select Enable (Slave mode) bit
1 = SSx pin used for Slave mode
0 = SSx pin not used for Slave mode, pin controlled by port function.
CKP: Clock Polarity Select bit(4)
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 8
bit 7
bit 6
Note 1:
2:
3:
4:
When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
This bit can only be written when the ON bit = 0.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
When AUDEN = 1, the SPI module functions as if the CKP bit is equal to ‘1’, regardless of the actual value
of CKP.
DS60001168L-page 172
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 17-1:
bit 5
SPIxCON: SPI CONTROL REGISTER (CONTINUED)
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
DISSDI: Disable SDI bit
1 = SDI pin is not used by the SPI module (pin is controlled by PORT function)
0 = SDI pin is controlled by the SPI module
STXISEL: SPI Transmit Buffer Empty Interrupt Mode bits
11 = Interrupt is generated when the buffer is not full (has one or more empty elements)
10 = Interrupt is generated when the buffer is empty by one-half or more
01 = Interrupt is generated when the buffer is completely empty
00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are
complete
SRXISEL: SPI Receive Buffer Full Interrupt Mode bits
11 = Interrupt is generated when the buffer is full
10 = Interrupt is generated when the buffer is full by one-half or more
01 = Interrupt is generated when the buffer is not empty
00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)
bit 4
bit 3-2
bit 1-0
Note 1:
2:
3:
4:
When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
This bit can only be written when the ON bit = 0.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
When AUDEN = 1, the SPI module functions as if the CKP bit is equal to ‘1’, regardless of the actual value
of CKP.
2011-2019 Microchip Technology Inc.
DS60001168L-page 173
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 17-2:
Bit
Range
31:24
23:16
15:8
7:0
SPIxCON2: SPI CONTROL REGISTER 2
Bit
31/23/15/7
Bit
Bit
30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
Bit
Bit
26/18/10/2 25/17/9/1 24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SPISGNEXT
—
—
FRMERREN
SPIROVEN
R/W-0
U-0
U-0
U-0
R/W-0
U-0
AUDEN(1)
—
—
—
AUDMONO(1,2)
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
SPITUREN IGNROV
R/W-0
IGNTUR
R/W-0
AUDMOD(1,2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
SPISGNEXT: Sign Extend Read Data from the RX FIFO bit
1 = Data from RX FIFO is sign extended
0 = Data from RX FIFO is not sign extended
bit 14-13 Unimplemented: Read as ‘0’
bit 12
FRMERREN: Enable Interrupt Events via FRMERR bit
1 = Frame Error overflow generates error events
0 = Frame Error does not generate error events
bit 11
SPIROVEN: Enable Interrupt Events via SPIROV bit
1 = Receive overflow generates error events
0 = Receive overflow does not generate error events
bit 10
SPITUREN: Enable Interrupt Events via SPITUR bit
1 = Transmit underrun generates error events
0 = Transmit underrun does not generate error events
bit 9
IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions)
1 = A ROV is not a critical error; during ROV data in the FIFO is not overwritten by receive data
0 = A ROV is a critical error that stops SPI operation
bit 8
IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions)
1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty
0 = A TUR is a critical error that stops SPI operation
bit 7
AUDEN: Enable Audio CODEC Support bit(1)
1 = Audio protocol enabled
0 = Audio protocol disabled
bit 6-5
Unimplemented: Read as ‘0’
bit 3
AUDMONO: Transmit Audio Data Format bit(1,2)
1 = Audio data is mono (Each data word is transmitted on both left and right channels)
0 = Audio data is stereo
bit 2
Unimplemented: Read as ‘0’
bit 1-0
AUDMOD: Audio Protocol Mode bit(1,2)
11 = PCM/DSP mode
10 = Right-Justified mode
01 = Left-Justified mode
00 = I2S mode
Note 1:
2:
This bit can only be written when the ON bit = 0.
This bit is only valid for AUDEN = 1.
DS60001168L-page 174
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 17-3:
Bit
Range
31:24
23:16
15:8
7:0
SPIxSTAT: SPI STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
R-0
—
—
—
U-0
U-0
U-0
R-0
R-0
—
—
—
U-0
U-0
U-0
R/C-0, HS
R-0
U-0
U-0
R-0
—
—
—
FRMERR
SPIBUSY
—
—
SPITUR
RXBUFELM
R-0
R-0
R-0
TXBUFELM
R-0
R/W-0
R-0
U-0
R-1
U-0
R-0
R-0
SRMT
SPIROV
SPIRBE
—
SPITBE
—
SPITBF
SPIRBF
Legend:
C = Clearable bit
HS = Set in hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 RXBUFELM: Receive Buffer Element Count bits (valid only when ENHBUF = 1)
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFELM: Transmit Buffer Element Count bits (valid only when ENHBUF = 1)
bit 15-13 Unimplemented: Read as ‘0’
bit 12
FRMERR: SPI Frame Error status bit
1 = Frame error detected
0 = No Frame error detected
This bit is only valid when FRMEN = 1.
bit 11
SPIBUSY: SPI Activity Status bit
1 = SPI peripheral is currently busy with some transactions
0 = SPI peripheral is currently idle
bit 10-9
Unimplemented: Read as ‘0’
bit 8
SPITUR: Transmit Under Run bit
1 = Transmit buffer has encountered an underrun condition
0 = Transmit buffer has no underrun condition
This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling (ON bit = 0)
and re-enabling (ON bit = 1) the module, or writing a ‘0’ to SPITUR.
bit 7
SRMT: Shift Register Empty bit (valid only when ENHBUF = 1)
1 = When SPI module shift register is empty
0 = When SPI module shift register is not empty
bit 6
SPIROV: Receive Overflow Flag bit
1 = A new data is completely received and discarded. The user software has not read the previous data in
the SPIxBUF register.
0 = No overflow has occurred
This bit is set in hardware; can bit only be cleared by disabling (ON bit = 0) and re-enabling (ON bit = 1) the
module, or by writing a ‘0’ to SPIROV.
bit 5
SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1)
1 = RX FIFO is empty (CRPTR = SWPTR)
0 = RX FIFO is not empty (CRPTR SWPTR)
bit 4
Unimplemented: Read as ‘0’
2011-2019 Microchip Technology Inc.
DS60001168L-page 175
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 17-3:
SPIxSTAT: SPI STATUS REGISTER
bit 3
SPITBE: SPI Transmit Buffer Empty Status bit
1 = Transmit buffer, SPIxTXB is empty
0 = Transmit buffer, SPIxTXB is not empty
Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR.
Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.
bit 2
Unimplemented: Read as ‘0’
bit 1
SPITBF: SPI Transmit Buffer Full Status bit
1 = Transmit not yet started, SPITXB is full
0 = Transmit buffer is not full
Standard Buffer Mode:
Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB.
Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR.
Enhanced Buffer Mode:
Set when CWPTR + 1 = SRPTR; cleared otherwise
bit 0
SPIRBF: SPI Receive Buffer Full Status bit
1 = Receive buffer, SPIxRXB is full
0 = Receive buffer, SPIxRXB is not full
Standard Buffer Mode:
Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer Mode:
Set when SWPTR + 1 = CRPTR; cleared otherwise
DS60001168L-page 176
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
18.0
Note:
INTER-INTEGRATED CIRCUIT
(I2C)
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 24. “InterIntegrated Circuit (I2C)” (DS60001116),
which is available from the Documentation
> Reference Manual section of the Microchip
PIC32
web
site
(www.microchip.com/pic32).
2011-2019 Microchip Technology Inc.
The I2C module provides complete hardware support
for both Slave and Multi-Master modes of the I2C serial
communication standard. Figure 18-1 illustrates the
I2C module block diagram.
Each I2C module has a 2-pin interface: the SCLx pin is
clock and the SDAx pin is data.
Each I2C module offers the following key features:
• I2C interface supporting both master and slave
operation
• I2C Slave mode supports 7-bit and 10-bit addressing
• I2C Master mode supports 7-bit and 10-bit
addressing
• I2C port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for the I2C port can
be used as a handshake mechanism to suspend
and resume serial transfer (SCLREL control)
• I2C supports multi-master operation; detects bus
collision and arbitrates accordingly
• Provides support for address bit masking
DS60001168L-page 177
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 18-1:
I2C BLOCK DIAGRAM
Internal
Data Bus
I2CxRCV
Read
SCLx
Shift
Clock
I2CxRSR
LSB
SDAx
Address Match
Match Detect
Write
I2CxMSK
Write
Read
I2CxADD
Read
Start and Stop
bit Detect
Write
Start and Stop
bit Generation
Control Logic
I2CxSTAT
Collision
Detect
Read
Write
I2CxCON
Acknowledge
Generation
Read
Clock
Stretching
Write
I2CxTRN
LSB
Read
Shift Clock
Reload
Control
BRG Down Counter
Write
I2CxBRG
Read
PBCLK
DS60001168L-page 178
2011-2019 Microchip Technology Inc.
I2C Control Registers
Virtual Address
(BF80_#)
TABLE 18-1:
5010 I2C1STAT
5020 I2C1ADD
5030 I2C1MSK
5040 I2C1BRG
I2C1TRN
5060 I2C1RCV
5100 I2C2CON
5110 I2C2STAT
5120 I2C2ADD
5130 I2C2MSK
5140 I2C2BRG
5150
I2C2TRN
5160 I2C2RCV
DS60001168L-page 179
Legend:
Note 1:
31/15
30/14
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
31:16
—
—
—
SIDL
—
SCLREL
—
STRICT
—
A10M
—
DISSLW
—
SMEN
—
GCEN
—
STREN
—
ACKDT
—
ACKEN
—
RCEN
—
PEN
—
RSEN
—
SEN
—
1000
0000
D_A
—
P
—
S
—
R_W
—
RBF
—
TBF
—
0000
0000
15:0 ACKSTAT TRSTAT
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Bits
5000 I2C1CON
5050
I2C1 AND I2C2 REGISTER MAP
31:16
—
—
—
—
—
—
—
—
BCL
—
GCSTAT
—
ADD10
—
IWCOL
—
I2COV
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Address Register
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Address Mask Register
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Transmit Register
—
—
—
—
—
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Register
—
—
—
—
—
0000
0000
15:0
ON
31:16
—
—
—
SIDL
—
SCLREL
—
STRICT
—
A10M
—
DISSLW
—
SMEN
—
GCEN
—
STREN
—
ACKDT
—
ACKEN
—
RCEN
—
PEN
—
RSEN
—
SEN
—
1000
0000
D_A
—
P
—
S
—
R_W
—
RBF
—
TBF
—
0000
0000
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
15:0 ACKSTAT TRSTAT
Baud Rate Generator Register
—
—
—
31:16
—
—
—
—
—
—
—
—
BCL
—
GCSTAT
—
ADD10
—
IWCOL
—
I2COV
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Address Register
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Address Mask Register
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Baud Rate Generator Register
—
—
—
—
—
Transmit Register
—
—
Receive Register
0000
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV
Registers” for more information.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2011-2019 Microchip Technology Inc.
18.1
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 18-1:
Bit
Range
31:24
23:16
15:8
7:0
I2CXCON: I2C CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
(1)
U-0
R/W-0
R/W-1, HC
R/W-0
R/W-0
R/W-0
R/W-0
—
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
ON
R/W-0
R/W-0
R/W-0
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
Legend:
HC = Cleared in Hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: I2C Enable bit(1)
1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins
0 = Disables the I2C module; all I2C pins are controlled by PORT functions
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when the device enters Idle mode
0 = Continue module operation when the device enters Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1 = Release SCLx clock
0 = Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at
beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
bit 11
STRICT: Strict I2C Reserved Address Rule Enable bit
1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate
addresses in reserved address space.
0 = Strict I2C Reserved Address Rule not enabled
bit 10
A10M: 10-bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control disabled
0 = Slew rate control enabled
bit 8
SMEN: SMBus Input Levels bit
1 = Enable I/O pin thresholds compliant with SMBus specification
0 = Disable SMBus input thresholds
Note 1:
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS60001168L-page 180
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 18-1:
I2CXCON: I2C CONTROL REGISTER (CONTINUED)
bit 7
GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enable interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0 = General call address is disabled
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
bit 5
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1 = Send a NACK during an Acknowledge sequence
0 = Send an ACK during an Acknowledge sequence
bit 4
ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master
receive)
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Hardware clear at end of master Acknowledge sequence.
0 = Acknowledge sequence not in progress
bit 3
RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.
0 = Receive sequence not in progress
bit 2
PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0 = Stop condition not in progress
bit 1
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
master Repeated Start sequence.
0 = Repeated Start condition not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0 = Start condition not in progress
Note 1:
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2011-2019 Microchip Technology Inc.
DS60001168L-page 181
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 18-2:
Bit
Range
31:24
23:16
15:8
7:0
I2CXSTAT: I2C STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0, HSC
R-0, HSC
U-0
U-0
U-0
R/C-0, HS
R-0, HSC
R-0, HSC
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
R/C-0, HS
R/C-0, HS
R-0, HSC
R/C-0, HSC
R/C-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
Legend:
HS = Set in hardware
HSC = Hardware set/cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
C = Clearable bit
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
Hardware set or clear at end of slave Acknowledge.
bit 14
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.
bit 13-11 Unimplemented: Read as ‘0’
bit 10
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware set at detection of bus collision. This condition can only be cleared by disabling (ON bit = 0) and
re-enabling (ON bit = 1) the module.
bit 9
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware set when address matches general call address. Hardware clear at Stop detection.
bit 8
ADD10: 10-bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
bit 7
IWCOL: Write Collision Detect bit
1 = An attempt to write the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
bit 6
I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
bit 5
D_A: Data/Address bit (when operating as I2C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of slave byte.
DS60001168L-page 182
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 18-2:
I2CXSTAT: I2C STATUS REGISTER (CONTINUED)
bit 4
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
bit 3
S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
bit 2
R_W: Read/Write Information bit (when operating as I2C slave)
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
Hardware set or clear after reception of I 2C device address byte.
bit 1
RBF: Receive Buffer Full Status bit
1 = Receive complete, I2CxRCV is full
0 = Receive not complete, I2CxRCV is empty
Hardware set when I2CxRCV is written with received byte. Hardware clear when software
reads I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.
2011-2019 Microchip Technology Inc.
DS60001168L-page 183
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
NOTES:
DS60001168L-page 184
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
19.0
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Note:
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 21. “Universal
Asynchronous Receiver Transmitter
(UART)” (DS60001107), which is available from the Documentation > Reference
Manual section of the Microchip PIC32
web site (www.microchip.com/pic32).
The UART module is one of the serial I/O modules
available in PIC32MX1XX/2XX 28/36/44-pin Family
devices. The UART is a full-duplex, asynchronous
communication channel that communicates with
peripheral devices and personal computers through
protocols, such as RS-232, RS-485, LIN, and IrDA®.
The UART module also supports the hardware flow
control option, with UxCTS and UxRTS pins, and also
includes an IrDA encoder and decoder.
FIGURE 19-1:
Key features of the UART module include:
•
•
•
•
•
•
•
•
•
•
•
•
•
Full-duplex, 8-bit or 9-bit data transmission
Even, Odd or No Parity options (for 8-bit data)
One or two Stop bits
Hardware auto-baud feature
Hardware flow control option
Fully integrated Baud Rate Generator (BRG) with
16-bit prescaler
Baud rates ranging from 38 bps to 12.5 Mbps at
50 MHz
8-level deep First In First Out (FIFO) transmit data
buffer
8-level deep FIFO receive data buffer
Parity, framing and buffer overrun error detection
Support for interrupt-only on address detect
(9th bit = 1)
Separate transmit and receive interrupts
Loopback mode for diagnostic support
• LIN protocol support
• IrDA encoder and decoder with 16x baud clock
output for external IrDA encoder/decoder support
Figure 19-1 illustrates a simplified block diagram of the
UART module.
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
Hardware Flow Control
Note:
UxRTS/BCLKx
UxCTS
UARTx Receiver
UxRX
UARTx Transmitter
UxTX
Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information.
2011-2019 Microchip Technology Inc.
DS60001168L-page 185
UART Control Registers
Virtual Address
(BF80_#)
TABLE 19-1:
U1STA(1)
6020 U1TXREG
6030 U1RXREG
6040
U1BRG(1)
6200 U2MODE(1)
6210
U2STA(1)
6220 U2TXREG
6230 U2RXREG
6240
U2BRG(1)
31/15
30/14
31:16
—
—
—
15:0
ON
31:16
—
—
—
SIDL
—
15:0
31:16
15:0
31:16
15:0
31:16
UTXISEL
29/13
28/12
27/11
26/10
25/9
24/8
—
—
—
—
—
IREN
—
RTSMD
—
—
—
UEN
—
ADM_EN
18/2
17/1
—
—
—
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
ADDR
URXISEL
PDSEL
16/0
—
0000
STSEL
0000
0000
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Transmit Register
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Register
—
—
—
—
—
0000
0000
—
—
—
—
—
—
0000
WAKE
LPBACK
ABAUD
RXINV
BRGH
ADDR
STSEL
0000
0000
Baud Rate Generator Prescaler
—
—
—
—
—
ON
31:16
—
—
—
SIDL
—
IREN
—
RTSMD
—
—
—
UEN
—
ADM_EN
15:0
19/3
—
—
31:16
20/4
UTXINV
—
15:0
21/5
—
15:0
31:16
22/6
—
31:16
15:0
15:0
31:16
23/7
All Resets
Bit Range
Register
Name
Bits
6000 U1MODE(1)
6010
UART1 AND UART2 REGISTER MAP
UTXISEL
—
0000
URXISEL
—
—
PDSEL
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Transmit Register
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Register
—
—
—
—
—
0000
0000
Legend:
15:0
Baud Rate Generator Prescaler
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information.
0000
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 186
19.1
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 19-1:
Bit
Range
31:24
23:16
15:8
7:0
UxMODE: UARTx MODE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
(1)
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
—
SIDL
IREN
RTSMD
—
R/W-0
ON
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAKE
LPBACK
ABAUD
RXINV
BRGH
UEN
R/W-0
PDSEL
R/W-0
STSEL
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: UARTx Enable bit(1)
1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by the UEN and UTXEN
control bits.
0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx
registers; UARTx power consumption is minimal.
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when the device enters Idle mode
0 = Continue module operation when the device enters Idle mode
bit 12
IREN: IrDA Encoder and Decoder Enable bit
1 = IrDA is enabled
0 = IrDA is disabled
bit 11
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
bit 9-8
UEN: UARTx Enable bits
11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by
corresponding bits in the PORTx register
bit 7
WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit
1 = Wake-up enabled
0 = Wake-up disabled
bit 6
LPBACK: UARTx Loopback Mode Select bit
1 = Loopback mode is enabled
0 = Loopback mode is disabled
Note 1:
When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2011-2019 Microchip Technology Inc.
DS60001168L-page 187
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 19-1:
UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 5
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of Sync character (0x55);
cleared by hardware upon completion
0 = Baud rate measurement disabled or completed
bit 4
RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1 = High-Speed mode – 4x baud clock enabled
0 = Standard Speed mode – 16x baud clock enabled
bit 2-1
PDSEL: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0
STSEL: Stop Selection bit
1 = 2 Stop bits
0 = 1 Stop bit
Note 1:
When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS60001168L-page 188
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 19-2:
Bit
Range
31:24
23:16
15:8
7:0
UxSTA: UARTx STATUS AND CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
ADM_EN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR
R/W-0
R/W-0
UTXISEL
R/W-0
R/W-0
URXISEL
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-1
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
R/W-0
R-1
R-0
R-0
R/W-0
R-0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-25 Unimplemented: Read as ‘0’
bit 24
ADM_EN: Automatic Address Detect Mode Enable bit
1 = Automatic Address Detect mode is enabled
0 = Automatic Address Detect mode is disabled
bit 23-16 ADDR: Automatic Address Mask bits
When the ADM_EN bit is ‘1’, this value defines the address character to use for automatic address
detection.
bit 15-14 UTXISEL: TX Interrupt Mode Selection bits
11 = Reserved, do not use
10 = Interrupt is generated and asserted while the transmit buffer is empty
01 = Interrupt is generated and asserted when all characters have been transmitted
00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space
bit 13
UTXINV: Transmit Polarity Inversion bit
If IrDA mode is disabled (i.e., IREN (UxMODE) is ‘0’):
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IrDA mode is enabled (i.e., IREN (UxMODE) is ‘1’):
1 = IrDA encoded UxTX Idle state is ‘1’
0 = IrDA encoded UxTX Idle state is ‘0’
bit 12
URXEN: Receiver Enable bit
1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)
0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module. UxRX pin is controlled by port.
bit 11
UTXBRK: Transmit Break bit
1 = Send Break on next transmission. Start bit followed by twelve ‘0’ bits, followed by Stop bit; cleared by
hardware upon completion
0 = Break transmission is disabled or completed
bit 10
UTXEN: Transmit Enable bit
1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1).
0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is
controlled by port.
bit 9
UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register is Empty bit (read-only)
1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
2011-2019 Microchip Technology Inc.
DS60001168L-page 189
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 19-2:
UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 7-6
URXISEL: Receive Interrupt Mode Selection bit
11 = Reserved; do not use
10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full (i.e., has 6 or more data characters)
01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full (i.e., has 4 or more data characters)
00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character)
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect.
0 = Address Detect mode is disabled
bit 4
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Data is being received
bit 3
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character
0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character
0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit.
This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit
resets the receiver buffer and the RSR to an empty state.
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed
bit 0
URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
DS60001168L-page 190
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
Figure 19-2 and Figure 19-3 illustrate typical receive
and transmit timing for the UART module.
FIGURE 19-2:
UART RECEPTION
Char 1
Char 2-4
Char 5-10
Char 11-13
Read to
UxRXREG
Start 1
Stop Start 2
Stop 4
Start 5
Stop 10 Start 11
Stop 13
UxRX
RIDLE
Cleared by
Software
OERR
Cleared by
Software
UxRXIF
URXISEL = 00
Cleared by
Software
UxRXIF
URXISEL = 01
UxRXIF
URXISEL = 10
FIGURE 19-3:
TRANSMISSION (8-BIT OR 9-BIT DATA)
8 into TxBUF
Write to
UxTXREG
TSR
Pull from Buffer
BCLK/16
(Shift Clock)
UxTX
Start
Bit 0
Bit 1
Stop
Start
Bit 1
UxTXIF
UTXISEL = 00
UxTXIF
UTXISEL = 01
UxTXIF
UTXISEL = 10
2011-2019 Microchip Technology Inc.
DS60001168L-page 191
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
NOTES:
DS60001168L-page 192
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
20.0
Note:
PARALLEL MASTER PORT
(PMP)
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 13. “Parallel
Master Port (PMP)” (DS60001128),
which is available from the Documentation
> Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The PMP is a parallel 8-bit input/output module
specifically designed to communicate with a wide
variety of parallel devices, such as communications
peripherals, LCDs, external memory devices and
microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP module is
highly configurable.
Key features of the PMP module include:
• Fully multiplexed address/data mode
• Demultiplexed or partially multiplexed address/
data mode
- up to 11 address lines with single Chip Select
- up to 12 address lines without Chip Select
• One Chip Select line
• Programmable strobe options
- Individual read and write strobes or;
- Read/write strobe with enable strobe
• Address auto-increment/auto-decrement
• Programmable address/data multiplexing
• Programmable polarity on control signals
• Legacy parallel slave port support
• Enhanced parallel slave support
- Address support
- 4-byte deep auto-incrementing buffer
• Programmable Wait states
• Selectable input voltage levels
Figure 20-1 illustrates the PMP module block diagram.
FIGURE 20-1:
PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
Address Bus
Data Bus
Control Lines
PIC32MX1XX/2XX
Parallel
Master Port
PMA
PMALL
PMA
PMALH
Flash
EEPROM
SRAM
Up to 12-bit Address
PMA
PMA
PMCS1
PMRD
PMRD/PMWR
PMWR
PMENB
Microcontroller
LCD
FIFO
Buffer
PMD
8-bit Data (with or without multiplexed addressing)
2011-2019 Microchip Technology Inc.
DS60001168L-page 193
PMP Control Registers
Virtual Address
(BF80_#)
Register
Name(1)
TABLE 20-1:
7000
PMCON
PARALLEL MASTER PORT REGISTER MAP
7010 PMMODE
7020 PMADDR
31/15
30/14
29/13
31:16
—
—
—
15:0
ON
31:16
—
—
—
SIDL
—
IRQM
28/12
27/11
—
—
ADRMUX
—
—
15:0
BUSY
31:16
—
—
—
—
INCM
—
15:0
—
CS1
ADDR14
—
—
—
26/10
25/9
24/8
23/7
22/6
—
—
—
—
—
PMPTTL PTWREN PTRDEN
—
—
—
—
—
MODE
—
—
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Bits
—
—
—
—
—
—
0000
CSF
—
—
ALP
—
—
—
CS1P
—
—
—
WRSP
—
RDSP
—
0000
0000
WAITB
—
—
—
WAITM
—
—
—
WAITE
—
—
0000
0000
0000
ADDR
7030 PMDOUT
31:16
15:0
DATAOUT
0000
0000
7040
PMDIN
31:16
15:0
DATAIN
0000
0000
7050
PMAEN
7060
PMSTAT
Legend:
Note 1:
31:16
—
—
—
—
—
15:0
—
PTEN14
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
PTEN
—
—
—
—
15:0
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
OBE
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
—
—
—
—
—
—
—
0000
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
008F
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 194
20.1
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 20-1:
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
(1)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SIDL
ADRMUX
PMPTTL
PTWREN
PTRDEN
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
R/W-0
R/W-0
ALP(2)
—
CS1P(2)
—
WRSP
RDSP
ON
7:0
PMCON: PARALLEL PORT CONTROL REGISTER
CSF(2)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Parallel Master Port Enable bit(1)
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when the device enters Idle mode
0 = Continue module operation when the device enters Idle mode
bit 12-11 ADRMUX: Address/Data Multiplexing Selection bits
11 = Lower 8 bits of address are multiplexed on PMD pins; upper 8 bits are not used
10 = All 16 bits of address are multiplexed on PMD pins
01 = Lower 8 bits of address are multiplexed on PMD pins, upper bits are on PMA and
PMA
00 = Address and data appear on separate pins
bit 10
PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffer
bit 9
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled
bit 8
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port enabled
0 = PMRD/PMWR port disabled
bit 7-6
CSF: Chip Select Function bits(2)
11 = Reserved
10 = PMCS1 functions as Chip Select
01 = PMCS1 functions as PMA
00 = PMCS1 functions as PMA
bit 5
ALP: Address Latch Polarity bit(2)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
2011-2019 Microchip Technology Inc.
DS60001168L-page 195
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 20-1:
PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
bit 4
Unimplemented: Read as ‘0’
bit 3
CS1P: Chip Select 0 Polarity bit(2)
1 = Active-high (PMCS1)
0 = Active-low (PMCS1)
bit 2
Unimplemented: Read as ‘0’
bit 1
WRSP: Write Strobe Polarity bit
For Slave Modes and Master mode 2 (MODE = 00,01,10):
1 = Write strobe active-high (PMWR)
0 = Write strobe active-low (PMWR)
For Master mode 1 (MODE = 11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB)
bit 0
RDSP: Read Strobe Polarity bit
For Slave modes and Master mode 2 (MODE = 00,01,10):
1 = Read Strobe active-high (PMRD)
0 = Read Strobe active-low (PMRD)
For Master mode 1 (MODE = 11):
1 = Read/write strobe active-high (PMRD/PMWR)
0 = Read/write strobe active-low (PMRD/PMWR)
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
DS60001168L-page 196
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 20-2:
Bit
Range
31:24
23:16
15:8
PMMODE: PARALLEL PORT MODE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
BUSY
R/W-0
7:0
IRQM
R/W-0
R/W-0
WAITB(1)
INCM
R/W-0
R/W-0
—
R/W-0
WAITM(1)
MODE
R/W-0
R/W-0
WAITE(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
BUSY: Busy bit (Master mode only)
1 = Port is busy
0 = Port is not busy
bit 14-13 IRQM: Interrupt Request Mode bits (3)
11 = Reserved, do not use
10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA =11 (Addressable Slave mode only)
01 = Interrupt generated at the end of the read/write cycle
00 = No Interrupt generated
bit 12-11 INCM: Increment Mode bits
11 = Slave mode read and write buffers auto-increment (MODE = 00 only)
10 = Decrement ADDR and ADDR by 1 every read/write cycle(2)
01 = Increment ADDR and ADDR by 1 every read/write cycle(2)
00 = No increment or decrement of address
bit 10
Unimplemented: Read as ‘0’
bit 9-8
MODE: Parallel Port Mode Select bits
11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMA, and PMD)
10 = Master mode 2 (PMCS1, PMRD, PMWR, PMA, and PMD)
01 = Enhanced Slave mode, control signals (PMRD, PMWR, PMCS1, PMD, and PMA)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1, and PMD)
bit 7-6
WAITB: Data Setup to Read/Write Strobe Wait States bits(1)
11 = Data wait of 4 TPB; multiplexed address phase of 4 TPB
10 = Data wait of 3 TPB; multiplexed address phase of 3 TPB
01 = Data wait of 2 TPB; multiplexed address phase of 2 TPB
00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (default)
Note 1: Whenever WAITM = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a
write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1.
3: These bits only control generating the Parallel Master Port (PMP) interrupt. The Parallel Master Port Error
(PMPE) is always generated.
2011-2019 Microchip Technology Inc.
DS60001168L-page 197
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 20-2:
bit 5-2
PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED)
WAITM: Data Read/Write Strobe Wait States bits(1)
1111 = Wait of 16 TPB
•
•
•
0001 = Wait of 2 TPB
0000 = Wait of 1 TPB (default)
bit 1-0
WAITE: Data Hold After Read/Write Strobe Wait States bits(1)
11 = Wait of 4 TPB
10 = Wait of 3 TPB
01 = Wait of 2 TPB
00 = Wait of 1 TPB (default)
For Read operations:
11 = Wait of 3 TPB
10 = Wait of 2 TPB
01 = Wait of 1 TPB
00 = Wait of 0 TPB (default)
Note 1: Whenever WAITM = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a
write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1.
3: These bits only control generating the Parallel Master Port (PMP) interrupt. The Parallel Master Port Error
(PMPE) is always generated.
DS60001168L-page 198
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 20-3:
Bit
Range
31:24
23:16
15:8
7:0
PMADDR: PARALLEL PORT ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
(1)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
R/W-0
—
R/W-0
CS1
ADDR14(2)
R/W-0
ADDR
R/W-0
R/W-0
R/W-0
ADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14
CS1: Chip Select 1 bit(1)
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive
bit 14
ADDR: Destination Address bit 14(2)
bit 13-11 Unimplemented: Read as ‘0’
bit 10-0
ADDR: Destination Address bits
Note 1:
2:
When the CSF bits (PMCON) = 10.
When the CSF bits (PMCON) = 00 or 01.
2011-2019 Microchip Technology Inc.
DS60001168L-page 199
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 20-4:
Bit
Range
31:24
23:16
15:8
7:0
PMAEN: PARALLEL PORT PIN ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
PTEN14
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN
R/W-0
R/W-0
R/W-0
PTEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 15-14 PTEN14: PMCS1 Address Port Enable bits
1 = PMA14 functions as either PMA14 or PMCS1(1)
0 = PMA14 functions as port I/O
bit 13-11 Unimplemented: Read as ‘0’
bit 10-2
PTEN: PMP Address Port Enable bits
1 = PMA function as PMP address lines
0 = PMA function as port I/O
bit 1-0
PTEN: PMALH/PMALL Address Port Enable bits
1 = PMA1 and PMA0 function as either PMA or PMALH and PMALL(2)
0 = PMA1 and PMA0 pads functions as port I/O
Note 1: The use of this pin as PMA14 or CS1 is selected by the CSF bits in the PMCON register.
2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode
selected by bits ADRMUX in the PMCON register.
DS60001168L-page 200
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 20-5:
Bit
Range
31:24
23:16
15:8
7:0
PMSTAT: PARALLEL PORT STATUS REGISTER (SLAVE MODES ONLY)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R/W-0, HS, SC
U-0
U-0
R-0
R-0
R-0
R-0
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
R-1
R/W-0, HS, SC
U-0
U-0
R-1
R-1
R-1
R-1
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
Legend:
HS = Hardware Set
SC = Cleared by Software
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
IBF: Input Buffer Full Status bit
1 = All writable input buffer registers are full
0 = Some or all of the writable input buffer registers are empty
bit 14
IBOV: Input Buffer Overflow Status bit (1)
1 = A write attempt to a full input byte buffer occurred (must be cleared in software)
0 = No overflow occurred
bit 13-12 Unimplemented: Read as ‘0’
bit 11-8
IBxF: Input Buffer ‘x’ Status Full bits
1 = Input Buffer contains data that has not been read (reading buffer will clear this bit)
0 = Input Buffer does not contain any unread data
bit 7
OBE: Output Buffer Empty Status bit
1 = All readable output buffer registers are empty
0 = Some or all of the readable output buffer registers are full
bit 6
OBUF: Output Buffer Underflow Status bit (1)
1 = A read occurred from an empty output byte buffer (must be cleared in software)
0 = No underflow occurred
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
OBxE: Output Buffer ‘x’ Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains data that has not been transmitted
Note 1: This will generate a PMPE - Parallel Master Port Error interrupt.
2011-2019 Microchip Technology Inc.
DS60001168L-page 201
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
NOTES:
DS60001168L-page 202
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
21.0
Note:
REAL-TIME CLOCK AND
CALENDAR (RTCC)
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 29. “Real-Time
Clock
and
Calendar
(RTCC)”
(DS60001125), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The PIC32 RTCC module is intended for applications in
which accurate time must be maintained for extended
periods of time with minimal or no CPU intervention.
Low-power optimization provides extended battery
lifetime while keeping track of time.
Following are some of the key features of this module:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
FIGURE 21-1:
Time: hours, minutes and seconds
24-hour format (military time)
Visibility of one-half second period
Provides calendar: day, date, month and year
Alarm intervals are configurable for half of a
second, one second, 10 seconds, one minute, 10
minutes, one hour, one day, one week, one month
and one year
Alarm repeat with decrementing counter
Alarm with indefinite repeat: Chime
Year range: 2000 to 2099
Leap year correction
BCD format for smaller firmware overhead
Optimized for long-term battery operation
Fractional second synchronization
User calibration of the clock crystal frequency with
auto-adjust
Calibration range: 0.66 seconds error per month
Calibrates up to 260 ppm of crystal error
Requirements: External 32.768 kHz clock crystal
Alarm pulse or seconds clock output on
RTCC pin
RTCC BLOCK DIAGRAM
CAL
32.768 kHz Input
from Secondary
Oscillator (SOSC)
RTCC Prescalers
RTCTIME
0.5s
HR, MIN, SEC
RTCC Timer
Alarm
Event
RTCVAL
RTCDATE
YEAR, MONTH, DAY, WDAY
Comparator
ALRMTIME
Compare Registers
with Masks
HR, MIN, SEC
ALRMVAL
ALRMDATE
MONTH, DAY, WDAY
Repeat Counter
Set RTCC Flag
RTCC Interrupt Logic
Alarm Pulse
Seconds Pulse
0
1
RTCC
RTSECSEL
RTCOE
2011-2019 Microchip Technology Inc.
DS60001168L-page 203
RTCC Control Registers
Virtual Address
(BF80_#)
Register
Name(1)
TABLE 21-1:
0200
RTCCON
RTCC REGISTER MAP
0210 RTCALRM
0220 RTCTIME
0230 RTCDATE
0240 ALRMTIME
0250 ALRMDATE
Legend:
Note 1:
31/15
30/14
31:16
—
15:0
ON
31:16
—
15:0 ALRMEN
—
31:16
15:0
29/13
28/12
27/11
26/10
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
CHIME
—
—
31:16
PIV
ALRMSYNC
HR10
SEC10
YEAR10
25/9
24/8
—
—
—
—
23/7
22/6
21/5
20/4
AMASK
HR01
—
—
—
—
—
SEC01
—
—
—
—
YEAR01
—
—
—
—
MONTH10
—
—
DAY10
DAY01
—
—
15:0
HR10
SEC10
HR01
SEC01
—
—
—
31:16
—
—
—
—
—
MONTH10
—
—
—
—
—
—
—
DAY01
0000
—
—
MIN10
—
—
—
—
—
—
MONTH01
—
—
MONTH01
—
WDAY01
xx00
xxxx
WDAY01
MIN01
—
—
0000
0000
0000
xxxx
MIN01
—
—
—
16/0
ARPT
—
—
17/1
RTCWREN RTCSYNC HALFSEC RTCOE
—
—
—
—
MIN10
15:0
DAY10
18/2
CAL
RTSECSEL RTCCLKON
—
—
31:16
15:0
19/3
All Resets
Bit Range
Bits
xx00
—
xxxx
xx00
00xx
xx0x
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more
information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 204
21.1
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 21-1:
Bit
Range
31:24
23:16
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
29/21/13/5 28/20/12/4
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CAL
CAL
15:8
7:0
RTCCON: RTC CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ON(1,2)
—
SIDL
—
—
—
—
—
R/W-0
R-0
U-0
U-0
R/W-0
R-0
R-0
—
—
RTSECSEL(3) RTCCLKON
RTCWREN(4) RTCSYNC HALFSEC(5)
R/W-0
RTCOE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25-16 CAL: RTC Drift Calibration bits, which contain a signed 10-bit integer value
0111111111 = Maximum positive adjustment, adds 511 RTC clock pulses every one minute
•
•
•
0000000001 = Minimum positive adjustment, adds 1 RTC clock pulse every one minute
0000000000 = No adjustment
1111111111 = Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute
•
•
•
1000000000 = Maximum negative adjustment, subtracts 512 clock pulses every one minute
bit 15
ON: RTCC On bit(1,2)
1 = RTCC module is enabled
0 = RTCC module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Disables the PBCLK to the RTCC when the device enters Idle mode
0 = Continue normal operation when the device enters Idle mode
bit 12-8
Unimplemented: Read as ‘0’
bit 7
RTSECSEL: RTCC Seconds Clock Output Select bit(3)
1 = RTCC Seconds Clock is selected for the RTCC pin
0 = RTCC Alarm Pulse is selected for the RTCC pin
bit 6
RTCCLKON: RTCC Clock Enable Status bit
1 = RTCC Clock is actively running
0 = RTCC Clock is not running
Note 1:
2:
The ON bit is only writable when RTCWREN = 1.
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Requires RTCOE = 1 (RTCCON) for the output to be active.
The RTCWREN bit can be set only when the write sequence is enabled.
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME).
3:
4:
5:
Note:
This register is reset only on a Power-on Reset (POR).
2011-2019 Microchip Technology Inc.
DS60001168L-page 205
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 21-1:
RTCCON: RTC CONTROL REGISTER (CONTINUED)
bit 5-4
Unimplemented: Read as ‘0’
bit 3
RTCWREN: RTC Value Registers Write Enable bit(4)
1 = RTC Value registers can be written to by the user
0 = RTC Value registers are locked out from being written to by the user
bit 2
RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data read
If the register is read twice and results in the same data, the data can be assumed to be valid
0 = RTC Value registers can be read without concern about a rollover ripple
bit 1
HALFSEC: Half-Second Status bit(5)
1 = Second half period of a second
0 = First half period of a second
bit 0
RTCOE: RTCC Output Enable bit
1 = RTCC clock output enabled – clock presented onto an I/O
0 = RTCC clock output disabled
Note 1:
2:
The ON bit is only writable when RTCWREN = 1.
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Requires RTCOE = 1 (RTCCON) for the output to be active.
The RTCWREN bit can be set only when the write sequence is enabled.
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME).
3:
4:
5:
Note:
This register is reset only on a Power-on Reset (POR).
DS60001168L-page 206
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 21-2:
Bit
Range
31:24
23:16
15:8
7:0
RTCALRM: RTC ALARM CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
Bit
27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R-0
R/W-0
R/W-0
CHIME(2)
R/W-0
(2)
R/W-0
ALRMEN(1,2)
R/W-0
(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PIV
ALRMSYNC(3)
R/W-0
AMASK
R/W-0
ARPT(2)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ALRMEN: Alarm Enable bit(1,2)
1 = Alarm is enabled
0 = Alarm is disabled
bit 14
CHIME: Chime Enable bit(2)
1 = Chime is enabled – ARPT is allowed to rollover from 0x00 to 0xFF
0 = Chime is disabled – ARPT stops once it reaches 0x00
bit 13
PIV: Alarm Pulse Initial Value bit(2)
When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse.
When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.
bit 12
ALRMSYNC: Alarm Sync bit(3)
1 = ARPT and ALRMEN may change as a result of a half second rollover during a read.
The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple
bits may be changing, which are then synchronized to the PB clock domain
0 = ARPT and ALRMEN can be read without concerns of rollover because the prescaler is > 32 RTC
clocks away from a half-second rollover
bit 11-8 AMASK: Alarm Mask Configuration bits(2)
0000 = Every half-second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29, once every four years)
1010 = Reserved; do not use
1011 = Reserved; do not use
11xx = Reserved; do not use
Note 1:
2:
3:
Note:
Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT = 00 and
CHIME = 0.
This field should not be written when the RTCC ON bit = ‘1’ (RTCCON) and ALRMSYNC = 1.
This assumes a CPU read will execute in less than 32 PBCLKs.
This register is reset only on a Power-on Reset (POR).
2011-2019 Microchip Technology Inc.
DS60001168L-page 207
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 21-2:
RTCALRM: RTC ALARM CONTROL REGISTER (CONTINUED)
ARPT: Alarm Repeat Counter Value bits(2)
11111111 = Alarm will trigger 256 times
bit 7-0
•
•
•
00000000 = Alarm will trigger one time
The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.
Note 1:
2:
3:
Note:
Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT = 00 and
CHIME = 0.
This field should not be written when the RTCC ON bit = ‘1’ (RTCCON) and ALRMSYNC = 1.
This assumes a CPU read will execute in less than 32 PBCLKs.
This register is reset only on a Power-on Reset (POR).
DS60001168L-page 208
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 21-3:
Bit
Range
31:24
23:16
15:8
7:0
RTCTIME: RTC TIME VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
U-0
R/W-x
—
U-0
HR10
R/W-x
R/W-x
HR01
R/W-x
R/W-x
MIN10
R/W-x
—
R/W-x
R/W-x
R/W-x
MIN01
R/W-x
R/W-x
R/W-x
SEC10
R/W-x
R/W-x
SEC01
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 HR10: Binary-Coded Decimal Value of Hours bits, 10s place digit; contains a value from 0 to 2
bit 27-24 HR01: Binary-Coded Decimal Value of Hours bits, 1s place digit; contains a value from 0 to 9
bit 23
Unimplemented: Read as ‘0’
bit 22-20 MIN10: Binary-Coded Decimal Value of Minutes bits, 10s place digit; contains a value from 0 to 5
bit 19-16 MIN01: Binary-Coded Decimal Value of Minutes bits, 1s place digit; contains a value from 0 to 9
bit 15
Unimplemented: Read as ‘0’
bit 14-12 SEC10: Binary-Coded Decimal Value of Seconds bits, 10s place digit; contains a value from 0 to 5
bit 11-8
SEC01: Binary-Coded Decimal Value of Seconds bits, 1s place digit; contains a value from 0 to 9
bit 7-0
Unimplemented: Read as ‘0’
Note:
This register is only writable when RTCWREN = 1 (RTCCON).
2011-2019 Microchip Technology Inc.
DS60001168L-page 209
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 21-4:
Bit
Range
31:24
23:16
15:8
7:0
RTCDATE: RTC DATE VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
—
—
—
MONTH10
U-0
U-0
R/W-x
R/W-x
YEAR10
YEAR01
R/W-x
R/W-x
MONTH01
R/W-x
R/W-x
R/W-x
—
—
U-0
U-0
U-0
DAY10
U-0
U-0
—
—
—
—
—
R/W-x
R/W-x
DAY01
R/W-x
R/W-x
WDAY01
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 YEAR10: Binary-Coded Decimal Value of Years bits, 10s place digit; contains a value from 0 to 9
bit 27-24 YEAR01: Binary-Coded Decimal Value of Years bits, 1s place digit; contains a value from 0 to 9
bit 23-21 Unimplemented: Read as ‘0’
bit 20
MONTH10: Binary-Coded Decimal Value of Months bits, 10s place digit; contains a value of 0 or 1
bit 19-16 MONTH01: Binary-Coded Decimal Value of Months bits, 1s place digit; contains a value from 0 to 9
bit 15-14 Unimplemented: Read as ‘0’
bit 13-12 DAY10: Binary-Coded Decimal Value of Days bits, 10s place digit; contains a value of 0 to 3
bit 11-8
DAY01: Binary-Coded Decimal Value of Days bits, 1s place digit; contains a value from 0 to 9
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
WDAY01: Binary-Coded Decimal Value of Weekdays bits; contains a value from 0 to 6
Note:
This register is only writable when RTCWREN = 1 (RTCCON).
DS60001168L-page 210
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 21-5:
Bit
Range
31:24
23:16
15:8
7:0
ALRMTIME: ALARM TIME VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
U-0
R/W-x
—
U-0
HR10
R/W-x
R/W-x
HR01
R/W-x
R/W-x
MIN10
R/W-x
—
R/W-x
R/W-x
R/W-x
MIN01
R/W-x
R/W-x
R/W-x
SEC10
R/W-x
R/W-x
SEC01
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 HR10: Binary Coded Decimal value of hours bits, 10s place digit; contains a value from 0 to 2
bit 27-24 HR01: Binary Coded Decimal value of hours bits, 1s place digit; contains a value from 0 to 9
bit 23
Unimplemented: Read as ‘0’
bit 22-20 MIN10: Binary Coded Decimal value of minutes bits, 10s place digit; contains a value from 0 to 5
bit 19-16 MIN01: Binary Coded Decimal value of minutes bits, 1s place digit; contains a value from 0 to 9
bit 15
Unimplemented: Read as ‘0’
bit 14-12 SEC10: Binary Coded Decimal value of seconds bits, 10s place digit; contains a value from 0 to 5
bit 11-8
SEC01: Binary Coded Decimal value of seconds bits, 1s place digit; contains a value from 0 to 9
bit 7-0
Unimplemented: Read as ‘0’
2011-2019 Microchip Technology Inc.
DS60001168L-page 211
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 21-6:
Bit
Range
31:24
23:16
15:8
7:0
ALRMDATE: ALARM DATE VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
MONTH10
U-0
U-0
R/W-x
R/W-x
MONTH01
—
—
U-0
U-0
U-0
DAY10
U-0
U-0
—
—
—
—
—
R/W-x
R/W-x
DAY01
R/W-x
R/W-x
WDAY01
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-21 Unimplemented: Read as ‘0’
bit 20
MONTH10: Binary Coded Decimal value of months bits, 10s place digit; contains a value of 0 or 1
bit 19-16 MONTH01: Binary Coded Decimal value of months bits, 1s place digit; contains a value from 0 to 9
bit 15-14 Unimplemented: Read as ‘0’
bit 13-12 DAY10: Binary Coded Decimal value of days bits, 10s place digit; contains a value from 0 to 3
bit 11-8
DAY01: Binary Coded Decimal value of days bits, 1s place digit; contains a value from 0 to 9
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
WDAY01: Binary Coded Decimal value of weekdays bits; contains a value from 0 to 6
DS60001168L-page 212
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
22.0
Note:
10-BIT ANALOG-TO-DIGITAL
CONVERTER (ADC)
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 17. “10-bit Analog-to-Digital
Converter
(ADC)”
(DS60001104), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The 10-bit Analog-to-Digital Converter (ADC) includes
the following features:
• Successive Approximation Register (SAR)
conversion
• Up to 1 Msps conversion speed
FIGURE 22-1:
• Up to 13 analog input pins
• External voltage reference input pins
• One unipolar, differential Sample and Hold
Amplifier (SHA)
• Automatic Channel Scan mode
• Selectable conversion trigger source
• 16-word conversion result buffer
• Selectable buffer fill modes
• Eight conversion result format options
• Operation during Sleep and Idle modes
A block diagram of the 10-bit ADC is illustrated in
Figure 22-1. Figure 22-2 illustrates a block diagram of
the ADC conversion clock period. The 10-bit ADC has
up to 13 analog input pins, designated AN0-AN12. In
addition, there are two analog input pins for external
voltage reference connections. These voltage
reference inputs may be shared with other analog input
pins and may be common to other analog module
references.
ADC1 MODULE BLOCK DIAGRAM
CTMUI(3)
VREF+(1)
AVDD
VREF-(1)
AVSS
AN0
AN12(2)
VCFG
CTMUT(3)
ADC1BUF0
IVREF(4)
ADC1BUF1
Open(5)
S&H
Channel
Scan
VREFH
VREFL
ADC1BUF2
+
CH0SB
CH0SA
-
SAR ADC
CSCNA
AN1
ADC1BUFE
VREFL
ADC1BUFF
CH0NA CH0NB
Alternate
Input Selection
Note 1: VREF+ and VREF- inputs can be multiplexed with other analog inputs.
2:
The AN8 pin is only available on 44-pin devices. The AN6 and AN7pins are not available on 28-pin devices. The
AN12 pin is available on all General Purpose Devices as well as 36 and 44 pin USB Devices.
3:
Connected to the CTMU module. See Section 25.0 “Charge Time Measurement Unit (CTMU)” for more
information.
4:
Internal precision voltage reference (1.2V).
2011-2019 Microchip Technology Inc.
DS60001168L-page 213
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 22-2:
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
ADRC
FRC(1)
Div 2
1
TAD
ADCS
0
8
ADC Conversion
Clock Multiplier
TPB(2)
2, 4,..., 512
Note 1:
2:
See Section 30.0 “Electrical Characteristics” for the exact FRC clock value.
Refer to Figure 8-1 in Section 8.0 “Oscillator Configuration” for more information.
DS60001168L-page 214
2011-2019 Microchip Technology Inc.
ADC Control Registers
Register
Name
9010 AD1CON2(1)
AD1CON3(1)
9040 AD1CHS(1)
9050 AD1CSSL(1)
9070 ADC1BUF0
9080 ADC1BUF1
9090 ADC1BUF2
90A0 ADC1BUF3
90B0 ADC1BUF4
90C0 ADC1BUF5
90D0 ADC1BUF6
90E0 ADC1BUF7
DS60001168L-page 215
90F0 ADC1BUF8
9100 ADC1BUF9
9110 ADC1BUFA
31/15
30/14
31:16
—
15:0
ON
31:16
—
15:0
31:16
29/13
28/12
27/11
26/10
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
OFFCAL
—
CSCNA
—
—
BUFS
—
—
—
—
—
—
—
VCFG
—
—
—
15:0
ADRC
—
—
31:16
CH0NB
—
—
—
15:0
—
—
—
—
25/9
24/8
23/7
—
—
—
22/6
21/5
—
—
18/2
17/1
16/0
—
—
—
—
—
—
ASAM
SAMP
DONE
0000
—
—
—
—
—
—
0000
BUFM
ALTS
0000
—
—
—
—
—
0000
CH0NA
—
—
—
—
—
—
—
SSRC
SMPI
—
—
ADCS
CH0SB
—
19/3
CLRASAM
FORM
SAMC
—
20/4
—
—
All Resets
Bits
9000 AD1CON1(1)
9020
ADC REGISTER MAP
Bit Range
Virtual Address
(BF80_#)
TABLE 22-1:
0000
CH0SA
—
0000
—
—
0000
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CSSL15
CSSL14
CSSL13
CSSL12
CSSL11
CSSL10
CSSL9
CSSL8
CSSL7
CSSL6
CSSL5
CSSL4
CSSL3
CSSL2
CSSL1
CSSL0
0000
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
ADC Result Word 0 (ADC1BUF0)
ADC Result Word 1 (ADC1BUF1)
ADC Result Word 2 (ADC1BUF2)
ADC Result Word 3 (ADC1BUF3)
ADC Result Word 4 (ADC1BUF4)
ADC Result Word 5 (ADC1BUF5)
ADC Result Word 6 (ADC1BUF6)
ADC Result Word 7 (ADC1BUF7)
ADC Result Word 8 (ADC1BUF8)
ADC Result Word 9 (ADC1BUF9)
ADC Result Word A (ADC1BUFA)
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for details.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2011-2019 Microchip Technology Inc.
22.1
Register
Name
9120 ADC1BUFB
9130 ADC1BUFC
9140 ADC1BUFD
9150 ADC1BUFE
9160 ADC1BUFF
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
ADC Result Word B (ADC1BUFB)
ADC Result Word C (ADC1BUFC)
ADC Result Word D (ADC1BUFD)
ADC Result Word E (ADC1BUFE)
ADC Result Word F (ADC1BUFF)
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for details.
All Resets
Bits
Bit Range
Virtual Address
(BF80_#)
ADC REGISTER MAP (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 216
TABLE 22-1:
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 22-1:
Bit
Range
31:24
23:16
15:8
7:0
AD1CON1: ADC CONTROL REGISTER 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
(1)
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
SIDL
—
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
CLRASAM
—
ASAM
ON
SSRC
FORM
R/W-0, HSC
(2)
SAMP
R/C-0, HSC
(3)
DONE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: ADC Operating Mode bit(1)
1 = ADC module is operating
0 = ADC module is not operating
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation when the device enters Idle mode
bit 12-11 Unimplemented: Read as ‘0’
bit 10-8
FORM: Data Output Format bits
111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000)
110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000)
101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd)
100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)
011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000)
010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000)
001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd)
000 =Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)
bit 7-5
SSRC: Conversion Trigger Source Select bits
111 = Internal counter ends sampling and starts conversion (auto convert)
110 = Reserved
101 = Reserved
100 = Reserved
011 = CTMU ends sampling and starts conversion
010 = Timer 3 period match ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing SAMP bit ends sampling and starts conversion
Note 1:
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if
ASAM = 1. If SSRC = 0, software can write a ‘0’ to end sampling and start conversion. If SSRC ‘0’, this
bit is automatically cleared by hardware to end sampling and start conversion.
This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can
write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation
already in progress. This bit is automatically cleared by hardware at the start of a new conversion.
2:
3:
2011-2019 Microchip Technology Inc.
DS60001168L-page 217
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 22-1:
AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED)
bit 4
CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated)
1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the
ADC interrupt is generated.
0 = Normal operation, buffer contents will be overwritten by the next conversion sequence
bit 3
Unimplemented: Read as ‘0’
bit 2
ASAM: ADC Sample Auto-Start bit
1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set.
0 = Sampling begins when SAMP bit is set
bit 1
SAMP: ADC Sample Enable bit(2)
1 = The ADC sample and hold amplifier is sampling
0 = The ADC sample/hold amplifier is holding
When ASAM = 0, writing ‘1’ to this bit starts sampling.
When SSRC = 000, writing ‘0’ to this bit will end sampling and start conversion.
bit 0
DONE: Analog-to-Digital Conversion Status bit(3)
1 = Analog-to-digital conversion is done
0 = Analog-to-digital conversion is not done or has not started
Clearing this bit will not affect any operation in progress.
Note 1:
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if
ASAM = 1. If SSRC = 0, software can write a ‘0’ to end sampling and start conversion. If SSRC ‘0’, this
bit is automatically cleared by hardware to end sampling and start conversion.
This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can
write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation
already in progress. This bit is automatically cleared by hardware at the start of a new conversion.
2:
3:
DS60001168L-page 218
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 22-2:
Bit
Range
31:24
23:16
15:8
AD1CON2: ADC CONTROL REGISTER 2
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
OFFCAL
—
CSCNA
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUFM
ALTS
VCFG
7:0
Bit
Bit
28/20/12/4 27/19/11/3
R-0
U-0
BUFS
—
R/W-0
SMPI
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-13 VCFG: Voltage Reference Configuration bits
000
001
010
011
1xx
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5-2
VREFH
VREFL
AVDD
External VREF+ pin
AVDD
External VREF+ pin
AVDD
AVss
AVSS
External VREF- pin
External VREF- pin
AVSS
OFFCAL: Input Offset Calibration Mode Select bit
1 = Enable Offset Calibration mode
Positive and negative inputs of the sample and hold amplifier are connected to VREFL
0 = Disable Offset Calibration mode
The inputs to the sample and hold amplifier are controlled by AD1CHS or AD1CSSL
Unimplemented: Read as ‘0’
CSCNA: Input Scan Select bit
1 = Scan inputs
0 = Do not scan inputs
Unimplemented: Read as ‘0’
BUFS: Buffer Fill Status bit
Only valid when BUFM = 1.
1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7
0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF
Unimplemented: Read as ‘0’
SMPI: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
•
•
•
bit 1
bit 0
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
BUFM: ADC Result Buffer Mode Select bit
1 = Buffer configured as two 8-word buffers, ADC1BUF7-ADC1BUF0, ADC1BUFF-ADCBUF8
0 = Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0
ALTS: Alternate Input Sample Mode Select bit
1 = Uses Sample A input multiplexer settings for first sample, then alternates between Sample B and
Sample A input multiplexer settings for all subsequent samples
0 = Always use Sample A input multiplexer settings
2011-2019 Microchip Technology Inc.
DS60001168L-page 219
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 22-3:
Bit
Range
31:24
23:16
15:8
7:0
AD1CON3: ADC CONTROL REGISTER 3
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
U-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADRC
—
—
R/W-0
R/W-0
R/W-0
R/W
R/W-0
SAMC(1)
R/W-0
R/W-0
R/W-0
ADCS(2)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ADRC: ADC Conversion Clock Source bit
1 = Clock derived from FRC
0 = Clock derived from Peripheral Bus Clock (PBCLK)
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8
SAMC: Auto-Sample Time bits(1)
11111 = 31 TAD
•
•
•
00001 = 1 TAD
00000 = 0 TAD (Not allowed)
bit 7-0
ADCS: ADC Conversion Clock Select bits(2)
11111111 =TPB • 2 • (ADCS + 1) = 512 • TPB = TAD
•
•
•
00000001 =TPB • 2 • (ADCS + 1) = 4 • TPB = TAD
00000000 =TPB • 2 • (ADCS + 1) = 2 • TPB = TAD
Note 1:
2:
This bit is only used if the SSRC bits (AD1CON1) = 111.
This bit is not used if the ADRC (AD1CON3) bit = 1.
DS60001168L-page 220
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 22-4:
Bit
Range
31:24
23:16
15:8
7:0
AD1CHS: ADC INPUT SELECT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
U-0
U-0
U-0
CH0NB
—
—
—
R/W-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
CH0SB
R/W-0
R/W-0
R/W-0
R/W-0
CH0NA
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
CH0SA
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
CH0NB: Negative Input Select bit for Sample B
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VREFL
bit 30-28
Unimplemented: Read as ‘0’
bit 27-24
CH0SB: Positive Input Select bits for Sample B
1111 = Channel 0 positive input is Open(1)
1110 = Channel 0 positive input is IVREF(2)
1101 = Channel 0 positive input is CTMU temperature sensor (CTMUT)(3)
1100 = Channel 0 positive input is AN12(4)
•
•
•
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
bit 23
CH0NA: Negative Input Select bit for Sample A Multiplexer Setting(2)
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VREFL
bit 22-20
Unimplemented: Read as ‘0’
bit 19-16
CH0SA: Positive Input Select bits for Sample A Multiplexer Setting
1111 = Channel 0 positive input is Open(1)
1110 = Channel 0 positive input is IVREF(2)
1101 = Channel 0 positive input is CTMU temperature (CTMUT)(3)
1100 = Channel 0 positive input is AN12(4)
•
•
•
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
bit 15-0
Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
This selection is only used with CTMU capacitive and time measurement.
See Section 24.0 “Comparator Voltage Reference (CVREF)” for more information.
See Section 25.0 “Charge Time Measurement Unit (CTMU)” for more information.
The AN8 pin is only available on the 44-pin devices. The AN6 and AN7 pins are not available on the 28-pin
devices. The AN12 pin is available on all General Purpose Devices as well as 36 and 44 pin USB Devices.
2011-2019 Microchip Technology Inc.
DS60001168L-page 221
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 22-5:
Bit
Range
31:24
23:16
15:8
7:0
AD1CSSL: ADC INPUT SCAN SELECT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSSL15
CSSL14
CSSL13
CSSL12
CSSL11
CSSL10
CSSL9
CSSL8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSSL7
CSSL6
CSSL5
CSSL4
CSSL3
CSSL2
CSSL1
CSSL0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CSSL: ADC Input Pin Scan Selection bits(1,2)
1 = Select ANx for input scan
0 = Skip ANx for input scan
Note 1:
CSSL = ANx, where ‘x’ = 0-12; CSSL13 selects CTMU input for scan; CSSL14 selects IVREF for scan;
CSSL15 selects VSS for scan.
On devices with less than 13 analog inputs, all CSSLx bits can be selected; however, inputs selected for
scan without a corresponding input on the device will convert to VREFL.
2:
DS60001168L-page 222
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
23.0
Note:
COMPARATOR
Following are some of the key features of this module:
• Selectable inputs available include:
- Analog inputs multiplexed with I/O pins
- On-chip internal absolute voltage reference
(IVREF)
- Comparator voltage reference (CVREF)
• Outputs can be Inverted
• Selectable interrupt generation
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet,
refer
to
Section
19.
“Comparator” (DS60001110), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
A block diagram of the comparator module is provided
in Figure 23-1.
The Analog Comparator module contains three
comparators that can be configured in a variety of
ways.
FIGURE 23-1:
COMPARATOR BLOCK DIAGRAM
CCH
C1INB
C1INC
COE
C1IND
CMP1
C1OUT
CREF
CMSTAT
CM1CON
CPOL
C1INA
CCH
C2INB
To CTMU module
(Pulse Generator)
C2INC
COE
C2IND
CMP2
C2OUT
CREF
CMSTAT
CM2CON
CPOL
C2INA
CCH
C3INB
C3INC
COE
C3IND
CREF
C3INA
CMP3
CPOL
CVREF(1)
IVREF(2)
2011-2019 Microchip Technology Inc.
Note 1:
2:
C3OUT
CMSTAT
CM3CON
Internally connected. See Section 24.0 “Comparator Voltage Reference
(CVREF)” for more information.
Internal precision voltage reference (1.2V).
DS60001168L-page 223
Comparator Control Registers
Virtual Address
(BF80_#)
TABLE 23-1:
A010 CM2CON
A020 CM3CON
CMSTAT
Legend:
Note 1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
—
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Bits
A000 CM1CON
A060
COMPARATOR REGISTER MAP
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
COE
CPOL
31:16
—
—
—
—
—
—
—
—
—
—
—
COUT
—
EVPOL
—
—
—
—
CREF
—
—
—
—
—
CCH
—
—
00C3
0000
—
—
—
—
—
—
—
—
COUT
—
EVPOL
—
—
—
—
CREF
—
—
—
—
—
CCH
—
—
00C3
0000
—
—
—
—
—
—
—
—
COUT
—
EVPOL
—
—
—
—
CREF
—
—
—
—
—
CCH
—
—
00C3
0000
—
—
—
—
C3OUT
15:0
ON
COE
CPOL
31:16
—
—
—
15:0
ON
COE
CPOL
31:16
—
—
—
15:0
—
—
SIDL
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
C2OUT
C1OUT
0000
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 224
23.1
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 23-1:
Bit
Range
31:24
23:16
15:8
7:0
CMXCON: COMPARATOR CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
R/W-0
(1)
R/W-0
ON
COE
R/W-1
R/W-1
Bit
Bit
28/20/12/4 27/19/11/3
—
R/W-0
(2)
CPOL
EVPOL
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
R-0
—
—
—
—
COUT
U-0
R/W-0
U-0
U-0
R/W-1
R/W-1
—
CREF
—
—
CCH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Comparator ON bit(1)
1 = Module is enabled. Setting this bit does not affect the other bits in this register
0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this
register
bit 14
COE: Comparator Output Enable bit
1 = Comparator output is driven on the output CxOUT pin
0 = Comparator output is not driven on the output CxOUT pin
bit 13
CPOL: Comparator Output Inversion bit(2)
1 = Output is inverted
0 = Output is not inverted
bit 12-9
Unimplemented: Read as ‘0’
bit 8
COUT: Comparator Output bit
1 = Output of the Comparator is a ‘1’
0 = Output of the Comparator is a ‘0’
bit 7-6
EVPOL: Interrupt Event Polarity Select bits
11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
10 = Comparator interrupt is generated on a high-to-low transition of the comparator output
01 = Comparator interrupt is generated on a low-to-high transition of the comparator output
00 = Comparator interrupt generation is disabled
bit 5
Unimplemented: Read as ‘0’
bit 4
CREF: Comparator Positive Input Configure bit
1 = Comparator non-inverting input is connected to the internal CVREF
0 = Comparator non-inverting input is connected to the CXINA pin
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
CCH: Comparator Negative Input Select bits for Comparator
11 = Comparator inverting input is connected to the IVREF
10 = Comparator inverting input is connected to the CxIND pin
01 = Comparator inverting input is connected to the CxINC pin
00 = Comparator inverting input is connected to the CxINB pin
Note 1:
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an
interrupt being generated on the opposite edge from the one selected by EVPOL.
2:
2011-2019 Microchip Technology Inc.
DS60001168L-page 225
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 23-2:
Bit
Range
31:24
23:16
15:8
7:0
CMSTAT: COMPARATOR STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
—
—
R/W-0
U-0
U-0
U-0
U-0
U-0
SIDL
—
—
—
—
—
U-0
U-0
—
—
U-0
U-0
U-0
R-0
R-0
R-0
—
—
—
C3OUT
C2OUT
C1OUT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Control bit
1 = All Comparator modules are disabled when the device enters Idle mode
0 = All Comparator modules continue to operate when the device enters Idle mode
bit 12-3
Unimplemented: Read as ‘0’
bit 2
C3OUT: Comparator Output bit
1 = Output of Comparator 3 is a ‘1’
0 = Output of Comparator 3 is a ‘0’
bit 1
C2OUT: Comparator Output bit
1 = Output of Comparator 2 is a ‘1’
0 = Output of Comparator 2 is a ‘0’
bit 0
C1OUT: Comparator Output bit
1 = Output of Comparator 1 is a ‘1’
0 = Output of Comparator 1 is a ‘0’
DS60001168L-page 226
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
24.0
Note:
COMPARATOR VOLTAGE
REFERENCE (CVREF)
The resistor ladder is segmented to provide two ranges
of voltage reference values and has a power-down
function to conserve power when the reference is not
being used. The module’s supply reference can be provided from either device VDD/VSS or an external
voltage reference. The CVREF output is available for
the comparators and typically available for pin output.
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 20. “Comparator
Voltage
Reference
(CVREF)”
(DS60001109), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The comparator voltage reference has the following
features:
• High and low range selection
• Sixteen output levels available for each range
• Internally connected to comparators to conserve
device pins
• Output can be connected to a pin
The CVREF module is a 16-tap, resistor ladder network
that provides a selectable reference voltage. Although
its primary purpose is to provide a reference for the
analog comparators, it also may be used independently
of them.
FIGURE 24-1:
VREF+
AVDD
A block diagram of the module is shown in Figure 24-1.
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
CVRSRC
8R
CVRSS = 0
CVR
CVREF
R
CVREN
R
R
16-to-1 MUX
R
16 Steps
R
CVREFOUT
CVRCON
R
R
CVRR
VREFAVSS
2011-2019 Microchip Technology Inc.
8R
CVRSS = 1
CVRSS = 0
DS60001168L-page 227
Comparator Voltage Reference Control Register
Virtual Address
(BF80_#)
TABLE 24-1:
Legend:
1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
31:16
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
CVROE
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
CVRR
CVRSS
CVR
All Resets
Register
Name(1)
Bit Range
Bits
9800 CVRCON
Note
COMPARATOR VOLTAGE REFERENCE REGISTER MAP
0000
0000
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 228
24.1
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 24-1:
Bit
Range
31:24
23:16
15:8
7:0
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CVROE
CVRR
CVRSS
ON
CVR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Comparator Voltage Reference On bit(1)
1 = Module is enabled
Setting this bit does not affect other bits in the register.
0 = Module is disabled and does not consume current.
Clearing this bit does not affect the other bits in the register.
bit 14-7
Unimplemented: Read as ‘0’
bit 6
CVROE: CVREFOUT Enable bit
1 = Voltage level is output on CVREFOUT pin
0 = Voltage level is disconnected from CVREFOUT pin
bit 5
CVRR: CVREF Range Selection bit
1 = 0 to 0.67 CVRSRC, with CVRSRC/24 step size
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size
bit 4
CVRSS: CVREF Source Selection bit
1 = Comparator voltage reference source, CVRSRC = (VREF+) – (VREF-)
0 = Comparator voltage reference source, CVRSRC = AVDD – AVSS
bit 3-0
CVR: CVREF Value Selection 0 CVR 15 bits
When CVRR = 1:
CVREF = (CVR/24) (CVRSRC)
When CVRR = 0:
CVREF = 1/4 (CVRSRC) + (CVR/32) (CVRSRC)
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2011-2019 Microchip Technology Inc.
DS60001168L-page 229
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
NOTES:
DS60001168L-page 230
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
25.0
CHARGE TIME
MEASUREMENT UNIT (CTMU)
Note:
The CTMU module includes the following key features:
• Up to 13 channels available for capacitive or time
measurement input
• On-chip precision current source
• 16-edge input trigger sources
• Selection of edge or level-sensitive inputs
• Polarity control for each edge source
• Control of edge sequence
• Control of response to edges
• High precision time measurement
• Time delay of external or internal signal asynchronous to system clock
• Integrated temperature sensing diode
• Control of current source during auto-sampling
• Four current source ranges
• Time measurement resolution of one nanosecond
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 37. “Charge Time
Measurement
Unit
(CTMU)”
(DS60001167), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The Charge Time Measurement Unit (CTMU) is a flexible analog module that has a configurable current
source with a digital configuration circuit built around it.
The CTMU can be used for differential time measurement between pulse sources and can be used for generating an asynchronous pulse. By working with other
on-chip analog modules, the CTMU can be used for
high resolution time measurement, measure capacitance, measure relative changes in capacitance or
generate output pulses with a specific time delay. The
CTMU is ideal for interfacing with capacitive-based
sensors.
FIGURE 25-1:
A block diagram of the CTMU is shown in Figure 25-1.
CTMU BLOCK DIAGRAM
CTMUCON1 or CTMUCON2
CTMUCON
ITRIM
IRNG
Current Source
CTED1
•
•
•
Edge
Control
Logic
CTED13
Timer1
OC1
IC1-IC3
CMP1-CMP3
PBCLK
EDG1STAT
EDG2STAT
TGEN
Current
Control
CTMUP
CTMUT
(To ADC)
Temperature
Sensor
CTMU
Control
Logic
ADC
Trigger
Pulse
Generator
CTPLS
CTMUI
(To ADC S&H capacitor)
C2INB
CDelay
Comparator 2
External capacitor
for pulse generation
Current Control Selection
TGEN
EDG1STAT, EDG2STAT
CTMUT
0
EDG1STAT = EDG2STAT
CTMUI
0
EDG1STAT EDG2STAT
CTMUP
1
EDG1STAT EDG2STAT
No Connect
1
EDG1STAT = EDG2STAT
2011-2019 Microchip Technology Inc.
DS60001168L-page 231
CTMU Control Registers
A200 CTMUCON
Legend:
Note 1:
CTMU REGISTER MAP
31/15
30/14
29/13
31:16 EDG1MOD EDG1POL
15:0
ON
—
CTMUSIDL
28/12
27/11
26/10
25/9
24/8
23/7
22/6
EDG2STAT EDG1STAT EDG2MOD EDG2POL
EDG1SEL
TGEN
EDGEN EDGSEQEN IDISSEN
CTTRIG
21/5
20/4
19/3
EDG2SEL
ITRIM
18/2
17/1
16/0
—
—
IRNG
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF80_#)
TABLE 25-1:
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 232
25.1
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 25-1:
Bit
Range
31:24
23:16
15:8
7:0
CTMUCON: CTMU CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
EDG1MOD EDG1POL
R/W-0
R/W-0
R/W-0
Bit
26/18/10/2
R/W-0
EDG1SEL
R/W-0
R/W-0
EDG2MOD EDG2POL
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
EDG2STAT EDG1STAT
R/W-0
U-0
EDG2SEL
U-0
—
—
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ON
—
CTMUSIDL
TGEN(1)
EDGEN
EDGSEQEN
IDISSEN(2)
CTTRIG
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ITRIM
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
IRNG
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
EDG1MOD: Edge1 Edge Sampling Select bit
1 = Input is edge-sensitive
0 = Input is level-sensitive
bit 30
EDG1POL: Edge 1 Polarity Select bit
1 = Edge1 programmed for a positive edge response
0 = Edge1 programmed for a negative edge response
bit 29-26 EDG1SEL: Edge 1 Source Select bits
1111 = C3OUT pin is selected
1110 = C2OUT pin is selected
1101 = C1OUT pin is selected
1100 = IC3 Capture Event is selected
1011 = IC2 Capture Event is selected
1010 = IC1 Capture Event is selected
1001 = CTED8 pin is selected
1000 = CTED7 pin is selected
0111 = CTED6 pin is selected
0110 = CTED5 pin is selected
0101 = CTED4 pin is selected
0100 = CTED3 pin is selected
0011 = CTED1 pin is selected
0010 = CTED2 pin is selected
0001 = OC1 Compare Event is selected
0000 = Timer1 Event is selected
bit 25
EDG2STAT: Edge2 Status bit
Indicates the status of Edge2 and can be written to control edge source
1 = Edge2 has occurred
0 = Edge2 has not occurred
Note 1:
2:
3:
4:
When this bit is set for Pulse Delay Generation, the EDG2SEL bits must be set to ‘1110’ to select
C2OUT.
The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
Refer to the CTMU Current Source Specifications (Table 30-41) in Section 30.0 “Electrical
Characteristics” for current values.
This bit setting is not available for the CTMU temperature diode.
2011-2019 Microchip Technology Inc.
DS60001168L-page 233
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 25-1:
CTMUCON: CTMU CONTROL REGISTER (CONTINUED)
bit 24
EDG1STAT: Edge1 Status bit
Indicates the status of Edge1 and can be written to control edge source
1 = Edge1 has occurred
0 = Edge1 has not occurred
bit 23
EDG2MOD: Edge2 Edge Sampling Select bit
1 = Input is edge-sensitive
0 = Input is level-sensitive
bit 22
EDG2POL: Edge 2 Polarity Select bit
1 = Edge2 programmed for a positive edge response
0 = Edge2 programmed for a negative edge response
bit 21-18 EDG2SEL: Edge 2 Source Select bits
1111 = C3OUT pin is selected
1110 = C2OUT pin is selected
1101 = C1OUT pin is selected
1100 = PBCLK clock is selected
1011 = IC3 Capture Event is selected
1010 = IC2 Capture Event is selected
1001 = IC1 Capture Event is selected
1000 = CTED13 pin is selected
0111 = CTED12 pin is selected
0110 = CTED11 pin is selected
0101 = CTED10 pin is selected
0100 = CTED9 pin is selected
0011 = CTED1 pin is selected
0010 = CTED2 pin is selected
0001 = OC1 Compare Event is selected
0000 = Timer1 Event is selected
bit 17-16 Unimplemented: Read as ‘0’
bit 15
ON: ON Enable bit
1 = Module is enabled
0 = Module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
CTMUSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when the device enters Idle mode
0 = Continue module operation when the device enters Idle mode
bit 12
TGEN: Time Generation Enable bit(1)
1 = Enables edge delay generation
0 = Disables edge delay generation
bit 11
EDGEN: Edge Enable bit
1 = Edges are not blocked
0 = Edges are blocked
Note 1:
2:
3:
4:
When this bit is set for Pulse Delay Generation, the EDG2SEL bits must be set to ‘1110’ to select
C2OUT.
The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
Refer to the CTMU Current Source Specifications (Table 30-41) in Section 30.0 “Electrical
Characteristics” for current values.
This bit setting is not available for the CTMU temperature diode.
DS60001168L-page 234
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 25-1:
bit 10
CTMUCON: CTMU CONTROL REGISTER (CONTINUED)
EDGSEQEN: Edge Sequence Enable bit
1 = Edge1 must occur before Edge2 can occur
0 = No edge sequence is needed
IDISSEN: Analog Current Source Control bit(2)
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
CTTRIG: Trigger Control bit
1 = Trigger output is enabled
0 = Trigger output is disabled
ITRIM: Current Source Trim bits
011111 = Maximum positive change from nominal current
011110
bit 9
bit 8
bit 7-2
•
•
•
000001 = Minimum positive change from nominal current
000000 = Nominal current output specified by IRNG
111111 = Minimum negative change from nominal current
•
•
•
100010
100001 = Maximum negative change from nominal current
IRNG: Current Range Select bits(3)
11 = 100 times base current
10 = 10 times base current
01 = Base current level
00 = 1000 times base current(4)
bit 1-0
Note 1:
2:
3:
4:
When this bit is set for Pulse Delay Generation, the EDG2SEL bits must be set to ‘1110’ to select
C2OUT.
The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
Refer to the CTMU Current Source Specifications (Table 30-41) in Section 30.0 “Electrical
Characteristics” for current values.
This bit setting is not available for the CTMU temperature diode.
2011-2019 Microchip Technology Inc.
DS60001168L-page 235
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
NOTES:
DS60001168L-page 236
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
26.0
Note:
POWER-SAVING FEATURES
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 10. “PowerSaving Features” (DS60001130), which
is available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
This section describes power-saving features for the
PIC32MX1XX/2XX 28/36/44-pin Family. The PIC32
devices offer a total of nine methods and modes,
organized into two categories, that allow the user to
balance power consumption with device performance. In
all of the methods and modes described in this section,
power-saving is controlled by software.
26.1
Power Saving with CPU Running
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency,
lowering the PBCLK and by individually disabling
modules. These methods are grouped into the
following categories:
• FRC Run mode: the CPU is clocked from the FRC
clock source with or without postscalers
• LPRC Run mode: the CPU is clocked from the
LPRC clock source
• SOSC Run mode: the CPU is clocked from the
SOSC clock source
In addition, the Peripheral Bus Scaling mode is available
where peripherals are clocked at the programmable
fraction of the CPU clock (SYSCLK).
26.2
CPU Halted Methods
The device supports two power-saving modes, Sleep
and Idle, both of which Halt the clock to the CPU. These
modes operate with all clock sources, as follows:
• POSC Idle mode: the system clock is derived from
the POSC. The system clock source continues to
operate. Peripherals continue to operate, but can
optionally be individually disabled.
• FRC Idle mode: the system clock is derived from
the FRC with or without postscalers. Peripherals
continue to operate, but can optionally be
individually disabled.
• SOSC Idle mode: the system clock is derived from
the SOSC. Peripherals continue to operate, but
can optionally be individually disabled.
2011-2019 Microchip Technology Inc.
• LPRC Idle mode: the system clock is derived from
the LPRC. Peripherals continue to operate, but
can optionally be individually disabled. This is the
lowest power mode for the device with a clock
running.
• Sleep mode: the CPU, the system clock source
and any peripherals that operate from the system
clock source are Halted. Some peripherals can
operate in Sleep using specific clock sources.
This is the lowest power mode for the device.
26.3
Power-Saving Operation
Peripherals and the CPU can be Halted or disabled to
further reduce power consumption.
26.3.1
SLEEP MODE
Sleep mode has the lowest power consumption of the
device power-saving operating modes. The CPU and
most peripherals are Halted. Select peripherals can
continue to operate in Sleep mode and can be used to
wake the device from Sleep. See the individual
peripheral module sections for descriptions of
behavior in Sleep.
Sleep mode includes the following characteristics:
• The CPU is halted
• The system clock source is typically shutdown.
See Section 26.3.3 “Peripheral Bus Scaling
Method” for specific information.
• There can be a wake-up delay based on the
oscillator selection
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode
• The BOR circuit remains operative during Sleep
mode
• The WDT, if enabled, is not automatically cleared
prior to entering Sleep mode
• Some peripherals can continue to operate at
limited functionality in Sleep mode. These
peripherals include I/O pins that detect a change
in the input signal, WDT, ADC, UART and
peripherals that use an external clock input or the
internal LPRC oscillator (e.g., RTCC, Timer1 and
Input Capture).
• I/O pins continue to sink or source current in the
same manner as they do when the device is not in
Sleep
• The USB module can override the disabling of the
Posc or FRC. Refer to the USB section for
specific details.
• Modules can be individually disabled by software
prior to entering Sleep in order to further reduce
consumption
DS60001168L-page 237
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
The processor will exit, or ‘wake-up’, from Sleep on one
of the following events:
• On any interrupt from an enabled source that is
operating in Sleep. The interrupt priority must be
greater than the current CPU priority.
• On any form of device Reset
• On a WDT time-out
If the interrupt priority is lower than or equal to the
current priority, the CPU will remain Halted, but the
PBCLK will start running and the device will enter into
Idle mode.
26.3.2
IDLE MODE
In Idle mode, the CPU is Halted but the System Clock
(SYSCLK) source is still enabled. This allows peripherals to continue operation when the CPU is Halted.
Peripherals can be individually configured to Halt when
entering Idle by setting their respective SIDL bit.
Latency, when exiting Idle mode, is very low due to the
CPU oscillator source remaining active.
Note 1: Changing the PBCLK divider ratio
requires recalculation of peripheral timing. For example, assume the UART is
configured for 9600 baud with a PB clock
ratio of 1:1 and a POSC of 8 MHz. When
the PB clock divisor of 1:2 is used, the
input frequency to the baud clock is cut in
half; therefore, the baud rate is reduced
to 1/2 its former value. Due to numeric
truncation in calculations (such as the
baud rate divisor), the actual baud rate
may be a tiny percentage different than
expected. For this reason, any timing calculation required for a peripheral should
be performed with the new PB clock frequency instead of scaling the previous
value based on a change in the PB divisor
ratio.
2: Oscillator start-up and PLL lock delays
are applied when switching to a clock
source that was disabled and that uses a
crystal and/or the PLL. For example,
assume the clock source is switched from
POSC to LPRC just prior to entering Sleep
in order to save power. No oscillator startup delay would be applied when exiting
Idle. However, when switching back to
POSC, the appropriate PLL and/or
oscillator start-up/lock delays would be
applied.
DS60001168L-page 238
The device enters Idle mode when the SLPEN
(OSCCON) bit is clear and a WAIT instruction is
executed.
The processor will wake or exit from Idle mode on the
following events:
• On any interrupt event for which the interrupt
source is enabled. The priority of the interrupt
event must be greater than the current priority of
the CPU. If the priority of the interrupt event is
lower than or equal to current priority of the CPU,
the CPU will remain Halted and the device will
remain in Idle mode.
• On any form of device Reset
• On a WDT time-out interrupt
26.3.3
PERIPHERAL BUS SCALING
METHOD
Most of the peripherals on the device are clocked using
the PBCLK. The Peripheral Bus can be scaled relative to
the SYSCLK to minimize the dynamic power consumed
by the peripherals. The PBCLK divisor is controlled by
PBDIV (OSCCON), allowing SYSCLK to
PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals
using PBCLK are affected when the divisor is changed.
Peripherals such as the USB, Interrupt Controller, DMA,
and the bus matrix are clocked directly from SYSCLK.
As a result, they are not affected by PBCLK divisor
changes.
Changing the PBCLK divisor affects:
• The CPU to peripheral access latency. The CPU
has to wait for next PBCLK edge for a read to
complete. In 1:8 mode, this results in a latency of
one to seven SYSCLKs.
• The power consumption of the peripherals. Power
consumption is directly proportional to the frequency at which the peripherals are clocked. The
greater the divisor, the lower the power consumed
by the peripherals.
To minimize dynamic power, the PB divisor should be
chosen to run the peripherals at the lowest frequency
that provides acceptable system performance. When
selecting a PBCLK divider, peripheral clock requirements, such as baud rate accuracy, should be taken
into account. For example, the UART peripheral may
not be able to achieve all baud rate values at some
PBCLK divider depending on the SYSCLK value.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
26.4
Peripheral Module Disable
To disable a peripheral, the associated PMDx bit must
be set to ‘1’. To enable a peripheral, the associated
PMDx bit must be cleared (default). See Table 26-1 for
more information.
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers do not have effect and read
values are invalid.
TABLE 26-1:
Note:
Disabling a peripheral module while it’s
ON bit is set, may result in undefined
behavior. The ON bit for the associated
peripheral module must be cleared prior to
disable a module via the PMDx bits.
PERIPHERAL MODULE DISABLE BITS AND LOCATIONS
Peripheral(1)
PMDx bit Name(1)
Register Name and Bit Location
ADC1
AD1MD
PMD1
CTMU
CTMUMD
PMD1
Comparator Voltage Reference
CVRMD
PMD1
Comparator 1
CMP1MD
PMD2
Comparator 2
CMP2MD
PMD2
Comparator 3
CMP3MD
PMD2
Input Capture 1
IC1MD
PMD3
Input Capture 2
IC2MD
PMD3
Input Capture 3
IC3MD
PMD3
Input Capture 4
IC4MD
PMD3
Input Capture 5
IC5MD
PMD3
Output Compare 1
OC1MD
PMD3
Output Compare 2
OC2MD
PMD3
Output Compare 3
OC3MD
PMD3
Output Compare 4
OC4MD
PMD3
Output Compare 5
OC5MD
PMD3
Timer1
T1MD
PMD4
Timer2
T2MD
PMD4
Timer3
T3MD
PMD4
Timer4
T4MD
PMD4
Timer5
T5MD
PMD4
UART1
U1MD
PMD5
UART2
U2MD
PMD5
SPI1
SPI1MD
PMD5
SPI2
SPI2MD
PMD5
I2C1
I2C1MD
PMD5
I2C2
I2C2MD
PMD5
USB(2)
USBMD
PMD5
RTCC
RTCCMD
PMD6
Reference Clock Output
REFOMD
PMD6
PMPMD
PMD6
PMP
Note 1:
2:
Not all modules and associated PMDx bits are available on all devices. See TABLE 1: “PIC32MX1XX
28/36/44-Pin General Purpose Family Features” and TABLE 2: “PIC32MX2XX 28/36/44-pin USB
Family Features” for the lists of available peripherals.
The module must not be busy after clearing the associated ON bit and prior to setting the USBMD bit.
2011-2019 Microchip Technology Inc.
DS60001168L-page 239
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
26.4.1
CONTROLLING CONFIGURATION
CHANGES
Because peripherals can be disabled during run time,
some restrictions on disabling peripherals are needed
to prevent accidental configuration changes. PIC32
devices include two features to prevent alterations to
enabled or disabled peripherals:
• Control register lock sequence
• Configuration bit select lock
26.4.1.1
Control Register Lock
Under normal operation, writes to the PMDx registers
are not allowed. Attempted writes appear to execute
normally, but the contents of the registers remain
unchanged. To change these registers, they must be
unlocked in hardware. The register lock is controlled by
the Configuration bit, PMDLOCK (CFGCON).
Setting PMDLOCK prevents writes to the control
registers; clearing PMDLOCK allows writes.
To set or clear PMDLOCK, an unlock sequence must
be executed. Refer to Section 6. “Oscillator”
(DS60001112) in the “PIC32 Family Reference
Manual” for details.
26.4.1.2
Configuration Bit Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the PMDx registers. The Configuration bit, PMDL1WAY
(DEVCFG3), blocks the PMDLOCK bit from being
cleared after it has been set once. If PMDLOCK
remains set, the register unlock procedure does not
execute, and the peripheral pin select control registers
cannot be written to. The only way to clear the bit and
re-enable PMD functionality is to perform a device
Reset.
DS60001168L-page 240
2011-2019 Microchip Technology Inc.
Virtual Address
(BF80_#)
Register
Name(1)
F240
PMD1
23/7
22/6
21/5
20/4
19/3
18/2
17/1
—
—
—
—
—
—
—
—
—
—
0000
—
—
CTMUMD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AD1MD
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
OC5MD
—
OC4MD
CMP3MD
OC3MD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IC5MD
—
IC4MD
—
IC3MD
—
IC2MD
—
IC1MD
—
0000
0000
—
—
—
—
—
—
—
—
—
USB1MD
—
—
—
—
—
—
T5MD
—
T4MD
—
T3MD
—
T2MD
I2C1MD
T1MD
I2C1MD
0000
0000
—
—
—
—
—
—
SPI2MD
—
SPI1MD
—
—
—
—
—
—
—
—
—
—
—
—
—
U2MD
—
U1MD
PMPMD
0000
0000
15:0
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
—
—
REFOMD RTCCMD
0000
PMD3
PMD4
F270
PMD5
F280
PMD6
F290
Legend:
1:
31/15
30/14
29/13
31:16
—
—
15:0
—
—
—
—
—
—
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
28/12
27/11
26/10
25/9
—
—
—
—
—
—
CVRMD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16/0
All Resets
24/8
PMD2
F260
Bit Range
Bits
F250
Note
PERIPHERAL MODULE DISABLE REGISTER MAP
CMP2MD CMP1MD 0000
OC2MD
OC1MD 0000
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
DS60001168L-page 241
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
2011-2019 Microchip Technology Inc.
TABLE 26-2:
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
NOTES:
DS60001168L-page 242
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
27.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features
of the PIC32MX1XX/2XX 28/36/44-pin
Family of devices. However, it is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section
32.
“Configuration”
(DS60001124)
and
Section
33.
“Programming
and
Diagnostics”
(DS60001129), which are available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
27.1
Configuration Bits
The Configuration bits can be programmed using the
following registers to select various device
configurations.
•
•
•
•
•
DEVCFG0: Device Configuration Word 0
DEVCFG1: Device Configuration Word 1
DEVCFG2: Device Configuration Word 2
DEVCFG3: Device Configuration Word 3
CFGCON: Configuration Control Register
In addition, the DEVID register (Register 27-6)
provides device and revision information.
PIC32MX1XX/2XX 28/36/44-pin Family devices
include the following features intended to maximize
application flexibility, reliability and minimize cost
through elimination of external components.
• Flexible device configuration
• Joint Test Action Group (JTAG) interface
• In-Circuit Serial Programming™ (ICSP™)
2011-2019 Microchip Technology Inc.
DS60001168L-page 243
Configuration Registers
DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
0BF4 DEVCFG2
0BF8 DEVCFG1
0BFC DEVCFG0
Legend:
Note 1:
2:
30/14
29/13
28/12
31:16 FVBUSONIO FUSBIDIO IOL1WAY PMDL1WAY
15:0
31:16
15:0
31:16
27/11
26/10
25/9
—
—
—
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
USERID
—
—
—
—
—
—
UPLLEN(1)
—
—
—
—
—
—
—
—
—
UPLLIDIV(1)
—
FPLLMUL
—
FWDTWINSZ FWDTEN WINDIS
—
—
—
15:0
FCKSM
FPBDIV
31:16
—
—
—
CP
OSCIOFNC
—
—
—
—
POSCMOD
—
BWP
15:0
PWP
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This bit is only available on PIC32MX2XX devices.
PWP are only available on devices with 256 KB of Flash.
Virtual Address
(BF80_#)
Register
Name
TABLE 27-2:
F220
DEVID
—
—
IESO
—
—
—
FSOSCEN
—
—
—
—
23/7
22/6
21/5
—
—
—
—
FPLLODIV
xxxx
—
FPLLIDIV
WDTPS
xxxx
xxxx
—
—
ICESEL
FNOSC
PWP(2)
JTAGEN
xxxx
xxxx
DEBUG
2011-2019 Microchip Technology Inc.
F230 SYSKEY(3)
Legend:
Note 1:
xxxx
DEVICE ID, REVISION, AND CONFIGURATION SUMMARY
Bit Range
Bits
F200 CFGCON
xxxx
xxxx
31/15
31:16
30/14
29/13
28/12
27/11
26/10
25/9
VER
20/4
19/3
18/2
17/1
16/0
xxxx(1)
DEVID
15:0
DEVID
31:16
—
—
15:0
—
—
31:16
24/8
—
—
IOLOCK PMDLOCK
xxxx(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
JTAGEN
—
—
SYSKEY
15:0
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset values are dependent on the device variant.
All Resets(1)
0BF0 DEVCFG3
31/15
All Resets
Bit Range
Bits
Register
Name
Virtual Address
(BFC0_#)
TABLE 27-1:
—
0000
TDOEN 000B
0000
0000
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
DS60001168L-page 244
27.2
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 27-1:
Bit
Range
31:24
23:16
15:8
7:0
DEVCFG0: DEVICE CONFIGURATION WORD 0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-0
r-1
r-1
R/P
r-1
r-1
r-1
R/P
—
—
—
CP
—
—
—
BWP
R/P
R/P
R/P
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
R/P
R/P
R/P
R/P
R/P
PWP(3)
R/P
PWP
r-1
r-1
r-1
R/P
—
—
—
ICESEL(2)
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R/P
R/P
JTAGEN(1)
r-1
r-1
—
—
R/P
R/P
DEBUG
P = Programmable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Reserved: Write ‘0’
bit 30-29 Reserved: Write ‘1’
bit 28
CP: Code-Protect bit
Prevents boot and program Flash memory from being read or modified by an external programming device.
1 = Protection is disabled
0 = Protection is enabled
bit 27-25 Reserved: Write ‘1’
bit 24
BWP: Boot Flash Write-Protect bit
Prevents boot Flash memory from being modified during code execution.
1 = Boot Flash is writable
0 = Boot Flash is not writable
bit 23-19 Reserved: Write ‘1’
Note 1:
2:
3:
This bit sets the value for the JTAGEN bit in the CFGCON register.
The PGEC4/PGED4 pin pair is not available on all devices. Refer to the “Pin Diagrams” section for
availability.
The PWP bits are only available on devices with 256 KB Flash.
2011-2019 Microchip Technology Inc.
DS60001168L-page 245
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 27-1:
DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)
bit 18-10 PWP: Program Flash Write-Protect bits(3)
Prevents selected program Flash memory pages from being modified during code execution.
111111111 = Disabled
111111110 = Memory below 0x0400 address is write-protected
111111101 = Memory below 0x0800 address is write-protected
111111100 = Memory below 0x0C00 address is write-protected
111111011 = Memory below 0x1000 (4K) address is write-protected
111111010 = Memory below 0x1400 address is write-protected
111111001 = Memory below 0x1800 address is write-protected
111111000 = Memory below 0x1C00 address is write-protected
111110111 = Memory below 0x2000 (8K) address is write-protected
111110110 = Memory below 0x2400 address is write-protected
111110101 = Memory below 0x2800 address is write-protected
111110100 = Memory below 0x2C00 address is write-protected
111110011 = Memory below 0x3000 address is write-protected
111110010 = Memory below 0x3400 address is write-protected
111110001 = Memory below 0x3800 address is write-protected
111110000 = Memory below 0x3C00 address is write-protected
111101111 = Memory below 0x4000 (16K) address is write-protected
•
•
•
110111111 = Memory below 0x10000 (64K) address is write-protected
•
•
•
101111111 = Memory below 0x20000 (128K) address is write-protected
•
•
•
011111111 = Memory below 0x40000 (256K) address is write-protected
•
•
•
000000000 = All possible memory is write-protected
bit 9-5
bit 4-3
Reserved: Write ‘1’
ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bits(2)
11 = PGEC1/PGED1 pair is used
10 = PGEC2/PGED2 pair is used
01 = PGEC3/PGED3 pair is used
00 = PGEC4/PGED4 pair is used(2)
JTAGEN: JTAG Enable bit(1)
1 = JTAG is enabled
0 = JTAG is disabled
DEBUG: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)
11 = Debugger is disabled
0x = Debugger is enabled
bit 2
bit 1-0
Note 1:
2:
3:
This bit sets the value for the JTAGEN bit in the CFGCON register.
The PGEC4/PGED4 pin pair is not available on all devices. Refer to the “Pin Diagrams” section for
availability.
The PWP bits are only available on devices with 256 KB Flash.
DS60001168L-page 246
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 27-2:
Bit
Range
31:24
23:16
15:8
7:0
DEVCFG1: DEVICE CONFIGURATION WORD 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
R/P
R/P
R/P
R/P
r-1
FWDTEN
WINDIS
—
R/P
R/P
R/P
FCKSM
Bit
25/17/9/1
Bit
24/16/8/0
R/P
R/P
FWDTWINSZ
R/P
R/P
R/P
R/P
R/P
WDTPS
R/P
FPBDIV
r-1
R/P
—
OSCIOFNC
R/P
R/P
r-1
R/P
r-1
r-1
IESO
—
FSOSCEN
—
—
POSCMOD
R/P
R/P
FNOSC
Legend:
r = Reserved bit
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Reserved: Write ‘1’
bit 25-24 FWDTWINSZ: Watchdog Timer Window Size bits
11 = Window size is 25%
10 = Window size is 37.5%
01 = Window size is 50%
00 = Window size is 75%
bit 23
FWDTEN: Watchdog Timer Enable bit
1 = Watchdog Timer is enabled and cannot be disabled by software
0 = Watchdog Timer is not enabled; it can be enabled in software
bit 22
WINDIS: Watchdog Timer Window Enable bit
1 = Watchdog Timer is in non-Window mode
0 = Watchdog Timer is in Window mode
bit 21
Reserved: Write ‘1’
bit 20-16 WDTPS: Watchdog Timer Postscale Select bits
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
All other combinations not shown result in operation = 10100
Note 1:
Do not disable the POSC (POSCMOD = 11) when using this oscillator source.
2011-2019 Microchip Technology Inc.
DS60001168L-page 247
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 27-2:
DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED)
bit 15-14 FCKSM: Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 13-12 FPBDIV: Peripheral Bus Clock Divisor Default Value bits
11 = PBCLK is SYSCLK divided by 8
10 = PBCLK is SYSCLK divided by 4
01 = PBCLK is SYSCLK divided by 2
00 = PBCLK is SYSCLK divided by 1
bit 11
Reserved: Write ‘1’
bit 10
OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output disabled
0 = CLKO output signal active on the OSCO pin; Primary Oscillator must be disabled or configured for the
External Clock mode (EC) for the CLKO to be active (POSCMOD = 11 or 00)
bit 9-8
POSCMOD: Primary Oscillator Configuration bits
11 = Primary Oscillator is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = External Clock mode is selected
bit 7
IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled)
0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled)
bit 6
Reserved: Write ‘1’
bit 5
FSOSCEN: Secondary Oscillator Enable bit
1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator
bit 4-3
Reserved: Write ‘1’
bit 2-0
FNOSC: Oscillator Selection bits
111 = Fast RC Oscillator with divide-by-N (FRCDIV)
110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator (POSC) with PLL module (XT+PLL, HS+PLL, EC+PLL)
010 = Primary Oscillator (XT, HS, EC)(1)
001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)
000 = Fast RC Oscillator (FRC)
Note 1:
Do not disable the POSC (POSCMOD = 11) when using this oscillator source.
DS60001168L-page 248
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 27-3:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
DEVCFG2: DEVICE CONFIGURATION WORD 2
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
R/P
R/P
R/P
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
R/P
r-1
r-1
r-1
r-1
UPLLEN(1)
—
—
—
—
r-1
R/P-1
R/P
R/P-1
—
FPLLMUL
r-1
FPLLODIV
R/P
R/P
R/P
UPLLIDIV(1)
R/P
—
R/P
R/P
FPLLIDIV
Legend:
r = Reserved bit
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-19 Reserved: Write ‘1’
bit 18-16 FPLLODIV: Default PLL Output Divisor bits
111 = PLL output divided by 256
110 = PLL output divided by 64
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 1
bit 15
UPLLEN: USB PLL Enable bit(1)
1 = Disable and bypass USB PLL
0 = Enable USB PLL
bit 14-11 Reserved: Write ‘1’
bit 10-8
UPLLIDIV: USB PLL Input Divider bits(1)
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
bit 7
Reserved: Write ‘1’
bit 6-4
FPLLMUL: PLL Multiplier bits
111 = 24x multiplier
110 = 21x multiplier
101 = 20x multiplier
100 = 19x multiplier
011 = 18x multiplier
010 = 17x multiplier
001 = 16x multiplier
000 = 15x multiplier
bit 3
Reserved: Write ‘1’
Note 1:
This bit is only available on PIC32MX2XX devices.
2011-2019 Microchip Technology Inc.
DS60001168L-page 249
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 27-3:
DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED)
bit 2-0
FPLLIDIV: PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
Note 1:
This bit is only available on PIC32MX2XX devices.
DS60001168L-page 250
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 27-4:
Bit
Range
31:24
23:16
15:8
7:0
DEVCFG3: DEVICE CONFIGURATION WORD 3
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
Bit
27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/P
R/P
R/P
R/P
r-1
r-1
r-1
r-1
FVBUSONIO
FUSBIDIO
IOL1WAY
PMDL1WAY
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
USERID
R/P
R/P
Legend:
R = Readable bit
-n = Value at POR
R/P
R/P
R/P
USERID
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
P = Programmable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
FVBUSONIO: USB VBUSON Selection bit
1 = VBUSON pin is controlled by the USB module
0 = VBUSON pin is controlled by the port function
bit 30
FUSBIDIO: USB USBID Selection bit
1 = USBID pin is controlled by the USB module
0 = USBID pin is controlled by the port function
bit 29
IOL1WAY: Peripheral Pin Select Configuration bit
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
bit 28
PMDl1WAY: Peripheral Module Disable Configuration bit
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
bit 27-16 Reserved: Write ‘1’
bit 15-0 USERID: User ID bits
This is a 16-bit value that is user-defined and is readable via ICSP™ and JTAG.
2011-2019 Microchip Technology Inc.
DS60001168L-page 251
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 27-5:
Bit
Range
31:24
23:16
15:8
7:0
CFGCON: CONFIGURATION CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-1
U-0
U-1
R/W-1
—
—
—
—
JTAGEN
—
—
TDOEN
IOLOCK(1) PMDLOCK(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13
IOLOCK: Peripheral Pin Select Lock bit(1)
1 = Peripheral Pin Select is locked. Writes to PPS registers is not allowed.
0 = Peripheral Pin Select is not locked. Writes to PPS registers is allowed.
bit 12
PMDLOCK: Peripheral Module Disable bit(1)
1 = Peripheral module is locked. Writes to PMD registers is not allowed.
0 = Peripheral module is not locked. Writes to PMD registers is allowed.
bit 11-4
Unimplemented: Read as ‘0’
bit 3
JTAGEN: JTAG Port Enable bit
1 = Enable the JTAG port
0 = Disable the JTAG port
bit 2-1
Unimplemented: Read as ‘1’
bit 0
TDOEN: TDO Enable for 2-Wire JTAG bit
1 = 2-wire JTAG protocol uses TDO
0 = 2-wire JTAG protocol does not use TDO
Note 1:
To change this bit, the unlock sequence must be performed. Refer to Section 6. “Oscillator”
(DS60001112) in the “PIC32 Family Reference Manual” for details.
DS60001168L-page 252
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 27-6:
Bit
Range
31:24
23:16
15:8
7:0
DEVID: DEVICE AND REVISION ID REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R
R
R
R
R
VER(1)
R
R
R
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R
R
R
DEVID(1)
R
R
R
R
R
R
R
R
R
R
R
DEVID(1)
R
R
R
R
R
DEVID(1)
R
R
R
R
R
DEVID(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 VER: Revision Identifier bits(1)
bit 27-0
DEVID: Device ID bits(1)
Note 1:
See the “PIC32 Flash Programming Specification” (DS60001145) for a list of Revision and Device ID
values.
2011-2019 Microchip Technology Inc.
DS60001168L-page 253
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
27.3
On-Chip Voltage Regulator
All PIC32MX1XX/2XX 28/36/44-pin Family devices’
core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in
the PIC32MX1XX/2XX 28/36/44-pin Family family
incorporate an on-chip regulator providing the required
core logic voltage from VDD.
A low-ESR capacitor (such as tantalum) must be
connected to the VCAP pin (see Figure 27-1). This
helps to maintain the stability of the regulator. The
recommended value for the filter capacitor is provided
in Section 30.1 “DC Characteristics”.
Note:
It is important that the low-ESR capacitor
is placed as close as possible to the VCAP
pin.
27.3.1
ON-CHIP REGULATOR AND POR
It takes a fixed delay for the on-chip regulator to generate an output. During this time, designated as TPU,
code execution is disabled. TPU is applied every time
the device resumes operation after any power-down,
including Sleep mode.
27.3.2
27.4
Programming and Diagnostics
PIC32MX1XX/2XX 28/36/44-pin Family devices provide a complete range of programming and diagnostic
features that can increase the flexibility of any application using them. These features allow system designers to include:
• Simplified field programmability using two-wire
In-Circuit Serial Programming™ (ICSP™)
interfaces
• Debugging using ICSP
• Programming and debugging capabilities using
the EJTAG extension of JTAG
• JTAG boundary scan testing for device and board
diagnostics
PIC32 devices incorporate two programming and diagnostic modules, and a trace controller, that provide a
range of functions to the application developer.
Figure 27-2 illustrates a block diagram of
programming, debugging, and trace ports.
FIGURE 27-2:
BLOCK DIAGRAM OF
PROGRAMMING,
DEBUGGING AND TRACE
PORTS
ON-CHIP REGULATOR AND BOR
PIC32MX1XX/2XX 28/36/44-pin Family devices also
have a simple brown-out capability. If the voltage
supplied to the regulator is inadequate to maintain a
regulated level, the regulator Reset circuitry will
generate a Brown-out Reset. This event is captured by
the BOR flag bit (RCON). The brown-out voltage
levels
are
specific
in
Section 30.1
“DC
Characteristics”.
FIGURE 27-1:
the
PGEC1
PGED1
ICSP™
Controller
PGEC4
PGED4
Core
CONNECTIONS FOR THE
ON-CHIP REGULATOR
ICESEL
TDI
3.3V(1)
TDO
PIC32
VDD
TCK
JTAG
Controller
TMS
VCAP
CEFC(2,3)
(10 F typ)
Note 1:
2:
3:
JTAGEN
DEBUG
VSS
These are typical operating voltages. Refer to
Section 30.1 “DC Characteristics” for the full
operating ranges of VDD.
It is important that the low-ESR capacitor is
placed as close as possible to the VCAP pin.
The typical voltage on the VCAP pin is 1.8V.
DS60001168L-page 254
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
28.0
INSTRUCTION SET
The PIC32MX1XX/2XX family instruction set
complies with the MIPS32® Release 2 instruction set
architecture. The PIC32 device family does not
support the following features:
• Core extend instructions
• Coprocessor 1 instructions
• Coprocessor 2 instructions
Note:
Refer to “MIPS32® Architecture for
Programmers Volume II: The MIPS32®
Instruction Set” at www.imgtec.com for
more information.
2011-2019 Microchip Technology Inc.
DS60001168L-page 255
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
NOTES:
DS60001168L-page 256
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
29.0
DEVELOPMENT SUPPORT
®
29.1
®
The PIC microcontrollers (MCU) and dsPIC digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2011-2019 Microchip Technology Inc.
DS60001168L-page 257
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
29.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
29.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
29.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
29.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS60001168L-page 258
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
29.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
29.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2011-2019 Microchip Technology Inc.
29.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
29.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
29.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
DS60001168L-page 259
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
29.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
29.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS60001168L-page 260
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
30.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC32MX1XX/2XX 28/36/44-pin Family electrical characteristics for
devices that operate at 40 MHz. Refer to Section 31.0 “50 MHz Electrical Characteristics” for additional
specifications for operations at higher frequency. Additional information will be provided in future revisions of this
document as it becomes available.
Absolute maximum ratings for the PIC32MX1XX/2XX 28/36/44-pin Family devices are listed below. Exposure to these
maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these
or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings
(See Note 1)
Ambient temperature under bias............................................................................................................ .-40°C to +105°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)......................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 2.3V (Note 3)........................................ -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)........................................ -0.3V to +3.6V
Voltage on D+ or D- pin with respect to VUSB3V3 .................................................................... -0.3V to (VUSB3V3 + 0.3V)
Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V
Maximum current out of VSS pin(s) .......................................................................................................................300 mA
Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA
Maximum output current sunk by any I/O pin..........................................................................................................15 mA
Maximum output current sourced by any I/O pin ....................................................................................................15 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 2)....................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions,
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 30-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.
2011-2019 Microchip Technology Inc.
DS60001168L-page 261
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
30.1
DC Characteristics
TABLE 30-1:
OPERATING MIPS VS. VOLTAGE
Max. Frequency
VDD Range
(in Volts)(1)
Temp. Range
(in °C)
PIC32MX1XX/2XX 28/36/44-pin Family
DC5
2.3-3.6V
-40°C to +85°C
40 MHz
DC5b
2.3-3.6V
-40°C to +105°C
40 MHz
Characteristic
Note 1:
Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device
Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to
parameter BO10 in Table 30-11 for BOR values.
TABLE 30-2:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min.
Typical
Max.
Unit
TJ
TA
-40
-40
—
—
+125
+85
°C
°C
TJ
-40
—
+140
°C
TA
-40
—
+105
°C
Industrial Temperature Devices
Operating Junction Temperature Range
Operating Ambient Temperature Range
V-temp Temperature Devices
Operating Junction Temperature Range
Operating Ambient Temperature Range
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – S IOH)
I/O Pin Power Dissipation:
I/O = S (({VDD – VOH} x IOH) + S (VOL x IOL))
Maximum Allowed Power Dissipation
TABLE 30-3:
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
THERMAL PACKAGING CHARACTERISTICS
Characteristics
Symbol Typical
Max.
Unit
Notes
Package Thermal Resistance, 28-pin SSOP
JA
71
—
°C/W
1
Package Thermal Resistance, 28-pin SOIC
JA
50
—
°C/W
1
Package Thermal Resistance, 28-pin SPDIP
JA
42
—
°C/W
1
Package Thermal Resistance, 28-pin QFN
JA
35
—
°C/W
1
Package Thermal Resistance, 36-pin VTLA
JA
31
—
°C/W
1
Package Thermal Resistance, 44-pin QFN
JA
32
—
°C/W
1
Package Thermal Resistance, 44-pin TQFP
JA
45
—
°C/W
1
Package Thermal Resistance, 44-pin VTLA
JA
30
—
°C/W
1
Note 1:
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
DS60001168L-page 262
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typ.
Max.
Units
Conditions
Operating Voltage
DC10
VDD
Supply Voltage (Note 2)
2.3
—
3.6
V
—
DC12
VDR
RAM Data Retention Voltage
(Note 1)
1.75
—
—
V
—
DC16
VPOR
VDD Start Voltage
to Ensure Internal Power-on Reset
Signal
1.75
—
2.1
V
—
DC17
SVDD
VDD Rise Rate
to Ensure Internal Power-on Reset
Signal
0.00005
—
0.115
V/s
—
Note 1:
2:
This is the limit to which VDD can be lowered without losing RAM data.
Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device
Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to
parameter BO10 in Table 30-11 for BOR values.
2011-2019 Microchip Technology Inc.
DS60001168L-page 263
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
DC CHARACTERISTICS
Parameter
No.
Typical(3)
Max.
Units
Conditions
Operating Current (IDD) (Notes 1, 2, 5)
DC20
2
3
mA
4 MHz (Note 4)
DC21
7
10.5
mA
10 MHz
DC22
10
15
mA
20 MHz (Note 4)
DC23
15
23
mA
30 MHz (Note 4)
DC24
20
30
mA
DC25
100
150
µA
Note 1:
2:
3:
4:
5:
40 MHz
+25ºC, 3.3V
LPRC (31 kHz) (Note 4)
A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
The test conditions for IDD measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU, Program Flash, and SRAM data memory are operational, SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• CPU executing while(1) statement from Flash
• RTCC and JTAG are disabled
Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
This parameter is characterized, but not tested in manufacturing.
IPD electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information.
DS60001168L-page 264
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-6:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
DC CHARACTERISTICS
Parameter
No.
Typical(2)
Max.
Units
Conditions
Idle Current (IIDLE): Core Off, Clock on Base Current (Notes 1, 4)
DC30a
1
1.5
mA
4 MHz (Note 3)
DC31a
2
3
mA
10 MHz
DC32a
4
6
mA
20 MHz (Note 3)
DC33a
5.5
8
mA
30 MHz (Note 3)
DC34a
7.5
11
mA
DC37a
100
—
µA
-40°C
DC37b
250
—
µA
+25°C
DC37c
380
—
µA
+85°C
Note 1:
2:
3:
4:
40 MHz
3.3V
LPRC (31 kHz)
(Note 3)
The test conditions for IIDLE current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Idle mode (CPU core Halted), and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
This parameter is characterized, but not tested in manufacturing.
IIDLE electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information.
2011-2019 Microchip Technology Inc.
DS60001168L-page 265
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-7:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC CHARACTERISTICS
Param.
Typical(2)
No.
Max.
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Units
Conditions
Power-Down Current (IPD) (Notes 1, 5)
DC40k
44
70
A
-40°C
DC40l
44
70
A
+25°C
DC40n
168
259
A
+85°C
DC40m
335
536
µA
+105ºC
Base Power-Down Current
Module Differential Current
DC41e
5
20
A
3.6V
Watchdog Timer Current: IWDT (Note 3)
DC42e
23
50
A
3.6V
RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3)
1000
1100
A
3.6V
ADC: IADC (Notes 3,4)
DC43d
Note 1:
2:
3:
4:
5:
The test conditions for IPD current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is set
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
IPD electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information.
DS60001168L-page 266
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-8:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Param.
Symbol
No.
VIL
DI10
Characteristics
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise
stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Min.
Typical(1)
Max.
Units
Conditions
Input Low Voltage
I/O Pins with PMP
VSS
—
0.15 VDD
V
I/O Pins
VSS
—
0.2 VDD
V
DI18
SDAx, SCLx
VSS
—
0.3 VDD
V
SMBus disabled
(Note 4)
DI19
SDAx, SCLx
VSS
—
0.8
V
SMBus enabled
(Note 4)
VIH
Input High Voltage
I/O Pins not 5V-tolerant(5)
DI20
0.65 VDD
—
VDD
V
(Note 4,6)
0.25 VDD + 0.8V
—
5.5
V
(Note 4,6)
I/O Pins 5V-tolerant(5)
0.65 VDD
—
5.5
V
DI28
SDAx, SCLx
0.65 VDD
—
5.5
V
SMBus disabled
(Note 4,6)
DI29
SDAx, SCLx
2.1
—
5.5
V
SMBus enabled,
2.3V VPIN 5.5
(Note 4,6)
I/O Pins 5V-tolerant with
PMP(5)
DI30
ICNPU
Change Notification
Pull-up Current
—
—
-50
A
VDD = 3.3V, VPIN = VSS
(Note 3,6)
DI31
ICNPD
Change Notification
Pull-down Current(4)
—
—
-50
µA
VDD = 3.3V, VPIN = VDD
IIL
Input Leakage Current
(Note 3)
DI50
I/O Ports
—
—
+1
A
VSS VPIN VDD,
Pin at high-impedance
DI51
Analog Input Pins
—
—
+1
A
VSS VPIN VDD,
Pin at high-impedance
DI55
MCLR(2)
—
—
+1
A
VSS VPIN VDD
DI56
OSC1
—
—
+1
A
VSS VPIN VDD,
XT and HS modes
Note 1:
2:
3:
4:
5:
6:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
This parameter is characterized, but not tested in manufacturing.
See the “Pin Diagrams” section for the 5V-tolerant pins.
The VIH specifications are only in relation to externally applied inputs, and not with respect to the userselectable internal pull-ups. External open drain input signals utilizing the internal pull-ups of the PIC32
device are guaranteed to be recognized only as a logic “high” internally to the PIC32 device, provided that
the external load does not exceed the minimum value of ICNPU. For External “input” logic inputs that require
a pull-up source, to guarantee the minimum VIH of those components, it is recommended to use an
external pull-up resistor rather than the internal pull-ups of the PIC32 device.
2011-2019 Microchip Technology Inc.
DS60001168L-page 267
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-9:
DC CHARACTERISTICS: I/O PIN INPUT INJECTION CURRENT SPECIFICATIONS
DC CHARACTERISTICS
Param.
Symbol
No.
DI60a
IICL
DI60b
IICH
DI60c
Note 1:
2:
3:
4:
5:
6:
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Min.
Typ.(1)
Max.
Units
Input Low Injection
Current
0
—
-5(2,5)
mA
Input High Injection
Current
0
—
+5(3,4,5)
mA
Characteristics
Conditions
This parameter applies to all pins,
with the exception of the power
pins.
This parameter applies to all pins,
with the exception of all 5V tolerant
pins, and the SOSCI, SOSCO,
OSC1, D+, and D- pins.
(6)
(6)
Total Input Injection
—
+20
mA
Absolute instantaneous sum of all ±
IICT
-20
Current (sum of all I/O
input injection currents from all I/O
and Control pins)
pins ( | IICL + | IICH | ) IICT )
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
VIL source < (VSS - 0.3). Characterized but not tested.
VIH source > (VDD + 0.3) for non-5V tolerant pins only.
Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any
“positive” input injection current.
Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD
+ 0.3) or VIL source < (VSS - 0.3)).
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. If Note 2, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 3, IICH = ((IICH source - (VDD + 0.3)) /
RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3) VSOURCE (VDD +
0.3), injection current = 0.
DS60001168L-page 268
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
DC CHARACTERISTICS
Param. Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
—
—
0.4
V
IOL 10 mA, VDD = 3.3V
Output High Voltage
1.5(1)
—
—
I/O Pins
2.0(1)
—
—
2.4
—
—
3.0(1)
—
—
Output Low Voltage
DO10
VOL
I/O Pins
DO20
Note 1:
VOH
IOH -14 mA, VDD = 3.3V
V
IOH -12 mA, VDD = 3.3V
IOH -10 mA, VDD = 3.3V
IOH -7 mA, VDD = 3.3V
Parameters are characterized, but not tested.
TABLE 30-11: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
DC CHARACTERISTICS
Param.
Symbol
No.
BO10
Note 1:
2:
VBOR
Characteristics
BOR Event on VDD transition
high-to-low(2)
Min.(1) Typical
2.0
—
Max.
Units
Conditions
2.3
V
—
Parameters are for design guidance only and are not tested in manufacturing.
Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device
Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN.
2011-2019 Microchip Technology Inc.
DS60001168L-page 269
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-12: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Min.
Typical(1)
Max.
Units
Conditions
Program Flash Memory(3)
EP
Cell Endurance
20,000
—
—
E/W
—
D131
VPR
VDD for Read
2.3
—
3.6
V
—
D132
VPEW
VDD for Erase or Write
2.3
—
3.6
V
—
D134
TRETD
Characteristic Retention
20
—
—
Year Provided no other specifications
are violated
D135
IDDP
Supply Current during
Programming
—
10
—
mA
TWW
Word Write Cycle Time
—
411
—
D136
TRW
Row Write Cycle Time
—
6675
—
D137
TPE
Page Erase Cycle Time
—
20011
—
TCE
Chip Erase Cycle Time
—
80180
—
Note 1:
2:
3:
4:
FRC Cycles
D130
—
See Note 4
See Note 2,4
See Note 4
See Note 4
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities
during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus
loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The
default Arbitration mode is mode 1 (CPU has lowest priority).
Refer to the “PIC32 Flash Programming Specification” (DS60001145) for operating conditions during
programming and erase cycles.
Translating this value to seconds depends on the FRC accuracy (See Table 30-19) and FRC tuning values
(See Register 8-2).
DS60001168L-page 270
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-13: COMPARATOR SPECIFICATIONS
Standard Operating Conditions (see Note 4): 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typical
Max.
Units
Comments
D300
VIOFF
Input Offset Voltage
—
±7.5
±25
mV
AVDD = VDD,
AVSS = VSS
D301
VICM
Input Common Mode Voltage
0
—
VDD
V
AVDD = VDD,
AVSS = VSS
(Note 2)
D302
CMRR
Common Mode Rejection Ratio
55
—
—
dB
Max VICM = (VDD - 1)V
(Note 2)
D303A TRESP
Large Signal Response Time
—
150
400
ns
AVDD = VDD, AVSS = VSS
(Note 1,2)
D303B TSRESP
Small Signal Response Time
—
1
—
s
This is defined as an input
step of 50 mV with 15 mV
of overdrive (Note 2)
D304
ON2OV
Comparator Enabled to Output
Valid
—
—
10
s
Comparator module is
configured before setting
the comparator ON bit
(Note 2)
D305
IVREF
Internal Voltage Reference
1.14
1.2
1.26
V
D312
TSET
Internal Comparator Voltage
DRC Reference Setting time
—
—
10
µs
Note 1:
2:
3:
4:
—
(Note 3)
Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
These parameters are characterized but not tested.
Settling time measured while CVRR = 1 and CVR transitions from ‘0000’ to ‘1111’. This parameter is
characterized, but not tested in manufacturing.
The Comparator module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.
2011-2019 Microchip Technology Inc.
DS60001168L-page 271
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-14: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
D312
TSET
D313
DACREFH CVREF Input Voltage
Reference Range
D314
DVREF
D315
DACRES
D316
DACACC
Note 1:
2:
Min.
Typ.
Max.
Units
—
—
10
µs
See Note 1
Internal 4-bit DAC
Comparator Reference
Settling time
Comments
AVSS
—
AVDD
V
CVRSRC with CVRSS = 0
VREF-
—
VREF+
V
CVRSRC with CVRSS = 1
0
—
0.625 x
DACREFH
V
0 to 0.625 DACREFH with
DACREFH/24 step size
0.25 x
DACREFH
—
0.719 x
DACREFH
V
0.25 x DACREFH to 0.719
DACREFH with
DACREFH/32 step size
—
—
DACREFH/24
—
CVRCON = 1
—
—
DACREFH/32
—
CVRCON = 0
—
—
1/4
LSB
DACREFH/24,
CVRCON = 1
—
—
1/2
LSB
DACREFH/32,
CVRCON = 0
CVREF Programmable
Output Range
Resolution
Absolute Accuracy(2)
Settling time was measured while CVRR = 1 and CVR transitions from ‘0000’ to ‘1111’. This
parameter is characterized, but is not tested in manufacturing.
These parameters are characterized but not tested.
TABLE 30-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
DC CHARACTERISTICS
Param.
No.
D321
Symbol
CEFC
Characteristics
Min.
Typical
Max.
Units
Comments
External Filter Capacitor Value
8
10
—
F
Capacitor must be low series
resistance (1 ohm). Typical
voltage on the VCAP pin is
1.8V.
DS60001168L-page 272
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
30.2
AC Characteristics and Timing
Parameters
The information contained in this section defines
PIC32MX1XX/2XX 28/36/44-pin Family AC characteristics and timing parameters.
FIGURE 30-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins
50 pF for OSC2 pin (EC mode)
VSS
TABLE 30-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Param.
Symbol
No.
Min.
Typical(1)
Max.
Units
Conditions
15
pF
In XT ans HS modes, when external crystal is used to drive OSC1
DO50
Characteristics
Cosco
OSC2 Pin
—
—
DO56
CIO
All I/O pins and OSC2
—
—
50
pF
EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C mode
Note 1:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 30-2:
EXTERNAL CLOCK TIMING
OS20
OS30
OS31
OSC1
OS30
2011-2019 Microchip Technology Inc.
OS31
DS60001168L-page 273
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Min.
Typical(1)
Max.
Units
Conditions
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
4
—
—
40
40
MHz
MHz
EC (Note 4)
ECPLL (Note 3)
Oscillator Crystal Frequency
3
—
10
MHz
XT (Note 4)
OS12
4
—
10
MHz
XTPLL
(Notes 3,4)
OS13
10
—
25
MHz
HS (Note 5)
OS14
10
—
25
MHz
HSPLL
(Notes 3,4)
32
32.768
100
kHz
SOSC (Note 4)
—
—
—
—
See parameter
OS10 for FOSC
value
OS10
FOSC
OS11
Characteristics
OS15
OS20
TOSC
TOSC = 1/FOSC = TCY (Note 2)
OS30
TOSL,
TOSH
External Clock In (OSC1)
High or Low Time
0.45 x TOSC
—
—
ns
EC (Note 4)
OS31
TOSR,
TOSF
External Clock In (OSC1)
Rise or Fall Time
—
—
0.05 x TOSC
ns
EC (Note 4)
OS40
TOST
Oscillator Start-up Timer Period
(Only applies to HS, HSPLL,
XT, XTPLL and SOSC Clock
Oscillator modes)
—
1024
—
OS41
TFSCM
Primary Clock Fail Safe
Time-out Period
—
2
—
OS42
GM
External Oscillator
Transconductance (Primary
Oscillator only)
—
12
—
Note 1:
2:
3:
4:
TOSC (Note 4)
ms
(Note 4)
mA/V VDD = 3.3V,
TA = +25°C
(Note 4)
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are not
tested.
Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device
executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min.” values with an
external clock applied to the OSC1/CLKI pin.
PLL input requirements: 4 MHZ FPLLIN 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is
characterized, but tested at 10 MHz only at manufacturing.
This parameter is characterized, but not tested in manufacturing.
DS60001168L-page 274
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-18: PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical
Max.
Units
Conditions
OS50
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
3.92
—
5
MHz
OS51
FSYS
On-Chip VCO System
Frequency
60
—
120
MHz
—
OS52
TLOCK
PLL Start-up Time (Lock Time)
—
—
2
ms
—
-0.25
—
+0.25
%
OS53
Note 1:
2:
DCLK
Stability(2)
CLKO
(Period Jitter or Cumulative)
ECPLL, HSPLL, XTPLL,
FRCPLL modes
Measured over 100 ms
period
These parameters are characterized, but not tested in manufacturing.
This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for
individual time-bases on communication clocks, use the following formula:
D CLK
EffectiveJitter = -------------------------------------------------------------SYSCLK
---------------------------------------------------------CommunicationClock
For example, if SYSCLK = 40 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows:
D CLK
D CLK
EffectiveJitter = -------------- = -------------1.41
40
-----20
TABLE 30-19:
INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Param.
No.
Characteristics
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Min.
Typical
Max.
Units
Conditions
—
+0.9
%
—
Internal FRC Accuracy @ 8.00 MHz(1)
F20b
Note 1:
FRC
-0.9
Frequency calibrated at 25°C and 3.3V. The TUN bits can be used to compensate for temperature drift.
TABLE 30-20: INTERNAL LPRC ACCURACY
AC CHARACTERISTICS
Param.
No.
Characteristics
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Min.
Typical
Max.
Units
Conditions
-15
—
+15
%
—
LPRC @ 31.25 kHz(1)
F21
Note 1:
LPRC
Change of LPRC frequency as VDD changes.
2011-2019 Microchip Technology Inc.
DS60001168L-page 275
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 30-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
Note: Refer to Figure 30-1 for load conditions.
DO31
DO32
TABLE 30-21: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
No.
Characteristics(2)
Symbol
Min.
Typical(1)
Max.
Units
—
5
15
ns
VDD < 2.5V
Conditions
DO31
TIOR
Port Output Rise Time
—
5
10
ns
VDD > 2.5V
DO32
TIOF
Port Output Fall Time
—
5
15
ns
VDD < 2.5V
—
5
10
ns
VDD > 2.5V
DI35
TINP
INTx Pin High or Low Time
10
—
—
ns
—
DI40
TRBP
CNx High or Low Time (input)
2
—
—
TSYSCLK
—
Note 1:
2:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
This parameter is characterized, but not tested in manufacturing.
DS60001168L-page 276
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 30-4:
POWER-ON RESET TIMING CHARACTERISTICS
Internal Voltage Regulator Enabled
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
CPU Starts Fetching Code
SY00
(TPU)
(Note 1)
Internal Voltage Regulator Enabled
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
VDD
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
SY00
(TPU)
(Note 1)
Note 1:
2:
OS40
(TOST)
CPU Starts Fetching Code
The power-up period will be extended if the power-up sequence completes before the device exits from BOR
(VDD < VDDMIN).
Includes interval voltage regulator stabilization delay.
2011-2019 Microchip Technology Inc.
DS60001168L-page 277
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 30-5:
EXTERNAL RESET TIMING CHARACTERISTICS
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
MCLR
TMCLR
(SY20)
BOR
TBOR
(SY30)
(TSYSDLY)
SY02
Reset Sequence
CPU Starts Fetching Code
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
(TSYSDLY)
SY02
Reset Sequence
CPU Starts Fetching Code
TOST
(OS40)
TABLE 30-22: RESETS TIMING
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
SY00
TPU
Power-up Period
Internal Voltage Regulator Enabled
—
400
600
s
—
SY02
TSYSDLY System Delay Period:
Time Required to Reload Device
Configuration Fuses plus SYSCLK
Delay before First instruction is
Fetched.
—
s +
8 SYSCLK
cycles
—
—
—
SY20
TMCLR
MCLR Pulse Width (low)
2
—
—
s
—
SY30
TBOR
BOR Pulse Width (low)
—
1
—
s
—
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.
DS60001168L-page 278
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 30-6:
TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRx
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS(1)
Param.
No.
TA10
TA11
TA15
Symbol
TTXH
TTXL
TTXP
Characteristics(2)
TxCK
High Time
TxCK
Low Time
Typical Max. Units
Conditions
Synchronous,
with prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
—
ns
Must also meet
parameter TA15
Asynchronous,
with prescaler
10
—
—
ns
—
Synchronous,
with prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
—
ns
Must also meet
parameter TA15
Asynchronous,
with prescaler
10
—
—
ns
—
[(Greater of 25 ns or
2 TPB)/N] + 30 ns
—
—
ns
VDD > 2.7V
[(Greater of 25 ns or
2 TPB)/N] + 50 ns
—
—
ns
VDD < 2.7V
20
—
—
ns
VDD > 2.7V
(Note 3)
50
—
—
ns
VDD < 2.7V
(Note 3)
32
—
100
kHz
—
—
—
1
TPB
—
TxCK
Synchronous,
Input Period with prescaler
Asynchronous,
with prescaler
OS60
FT1
TA20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
Note 1:
2:
3:
Min.
SOSC1/T1CK Oscillator
Input Frequency Range
(oscillator enabled by setting
the TCS (T1CON) bit)
Timer1 is a Type A timer.
This parameter is characterized, but not tested in manufacturing.
N = Prescale Value (1, 8, 64, 256).
2011-2019 Microchip Technology Inc.
DS60001168L-page 279
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Max. Units
TB10
TTXH
TxCK
Synchronous, with
High Time prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns
TB11
TTXL
TxCK
Synchronous, with
Low Time prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns
Conditions
Must also meet N = prescale
parameter
value
TB15
(1, 2, 4, 8,
Must also meet 16, 32, 64,
256)
parameter
TB15
TB15
TB20
TTXP
TxCK
Input
Period
Synchronous, with
prescaler
[(Greater of [(25 ns or
2 TPB)/N] + 30 ns
—
ns
VDD > 2.7V
[(Greater of [(25 ns or
2 TPB)/N] + 50 ns
—
ns
VDD < 2.7V
—
1
TPB
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer Increment
Note 1:
—
These parameters are characterized, but not tested in manufacturing.
FIGURE 30-7:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param.
Symbol
No.
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Characteristics(1)
Min.
Max.
Units
Conditions
IC10
TCCL
ICx Input Low Time
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns
Must also
meet
parameter
IC15.
IC11
TCCH
ICx Input High Time
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns
Must also
meet
parameter
IC15.
IC15
TCCP
ICx Input Period
[(25 ns or 2 TPB)/N]
+ 50 ns
—
ns
Note 1:
These parameters are characterized, but not tested in manufacturing.
DS60001168L-page 280
N = prescale
value (1, 4, 16)
—
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 30-8:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM mode)
OC10
OC11
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
OC10
TCCF
OCx Output Fall Time
—
—
—
ns
See parameter DO32
OC11
TCCR
OCx Output Rise Time
—
—
—
ns
See parameter DO31
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 30-9:
OCx/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCx
OCx is tri-stated
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param
No.
Symbol
Characteristics(1)
Min
Typical(2)
Max
Units
Conditions
OC15
TFD
Fault Input to PWM I/O Change
—
—
50
ns
—
OC20
TFLT
Fault Input Pulse Width
50
—
—
ns
—
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2011-2019 Microchip Technology Inc.
DS60001168L-page 281
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 30-10:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
SP31
SDIx
MSb In
LSb
SP30
LSb In
Bit 14 - - - -1
SP40 SP41
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2) Max.
Units
Conditions
SP10
TSCL
SCKx Output Low Time
(Note 3)
TSCK/2
—
—
ns
—
SP11
TSCH
SCKx Output High Time
(Note 3)
TSCK/2
—
—
ns
—
SP20
TSCF
SCKx Output Fall Time
(Note 4)
—
—
—
ns
See parameter DO32
SP21
TSCR
SCKx Output Rise Time
(Note 4)
—
—
—
ns
See parameter DO31
SP30
TDOF
SDOx Data Output Fall Time
(Note 4)
—
—
—
ns
See parameter DO32
SP31
TDOR
SDOx Data Output Rise Time
(Note 4)
—
—
—
ns
See parameter DO31
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
15
ns
VDD > 2.7V
—
—
20
ns
VDD < 2.7V
SP40
TDIV2SCH,
TDIV2SCL
Setup Time of SDIx Data Input
to SCKx Edge
10
—
—
ns
—
SP41
TSCH2DIL,
TSCL2DIL
Hold Time of SDIx Data Input
to SCKx Edge
10
—
—
ns
—
Note 1:
2:
3:
4:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The minimum clock period for SCKx is 50 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
DS60001168L-page 282
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 30-11:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11
SCKX
(CKP = 1)
SP10
SP21
SP20
SP20
SP21
SP35
LSb
Bit 14 - - - - - -1
MSb
SDOX
SP30,SP31
SDIX
MSb In
SP40
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
TSCL
SCKx Output Low Time (Note 3)
TSCK/2
—
—
ns
—
SP11
TSCH
SCKx Output High Time (Note 3)
TSCK/2
—
—
ns
—
SP20
TSCF
SCKx Output Fall Time (Note 4)
—
—
—
ns
See parameter DO32
SP21
TSCR
SCKx Output Rise Time (Note 4)
—
—
—
ns
See parameter DO31
SP30
TDOF
SDOx Data Output Fall Time
(Note 4)
—
—
—
ns
See parameter DO32
SP31
TDOR
SDOx Data Output Rise Time
(Note 4)
—
—
—
ns
See parameter DO31
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
15
ns
VDD > 2.7V
—
—
20
ns
VDD < 2.7V
SP36
TDOV2SC, SDOx Data Output Setup to
TDOV2SCL First SCKx Edge
15
—
—
ns
SP40
TDIV2SCH, Setup Time of SDIx Data Input to
TDIV2SCL SCKx Edge
SP41
TSCH2DIL,
TSCL2DIL
Note 1:
2:
3:
4:
Hold Time of SDIx Data Input
to SCKx Edge
—
15
—
—
ns
VDD > 2.7V
20
—
—
ns
VDD < 2.7V
15
—
—
ns
VDD > 2.7V
20
—
—
ns
VDD < 2.7V
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 50 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
2011-2019 Microchip Technology Inc.
DS60001168L-page 283
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 30-12:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
LSb
Bit 14 - - - - - -1
SP51
SP30,SP31
SDIX
MSb In
SP40
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
SP71
SP72
SP73
SP30
SP31
SP35
TSCL
TSCH
TSCF
TSCR
TDOF
TDOR
TSCH2DOV,
TSCL2DOV
SCKx Input Low Time (Note 3)
SCKx Input High Time (Note 3)
SCKx Input Fall Time
SCKx Input Rise Time
SDOx Data Output Fall Time (Note 4)
SDOx Data Output Rise Time (Note 4)
SDOx Data Output Valid after
SCKx Edge
SP40
TDIV2SCH,
TDIV2SCL
TSCH2DIL,
TSCL2DIL
Setup Time of SDIx Data Input
to SCKx Edge
Hold Time of SDIx Data Input
to SCKx Edge
TSCK/2
TSCK/2
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
20
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
See parameter DO32
See parameter DO31
See parameter DO32
See parameter DO31
VDD > 2.7V
VDD < 2.7V
—
10
—
—
ns
—
175
—
—
ns
—
5
—
25
ns
—
SP41
SP50
TSSL2SCH, SSx to SCKx or SCKx Input
TSSL2SCL
SP51
TSSH2DOZ SSx to SDOx Output
High-Impedance (Note 3)
SP52
TSCK + 20
—
—
ns
—
TSCH2SSH SSx after SCKx Edge
TSCL2SSH
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 50 ns.
Assumes 50 pF load on all SPIx pins.
Note 1:
2:
3:
4:
DS60001168L-page 284
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 30-13:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30,SP31
SDI
SDIx
MSb In
SP40
SP51
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
SP70
TSCL
SCKx Input Low Time (Note 3)
TSCK/2
—
—
ns
—
SP71
TSCH
SCKx Input High Time (Note 3)
TSCK/2
—
—
ns
—
SP72
TSCF
SCKx Input Fall Time
—
5
10
ns
—
SP73
TSCR
SCKx Input Rise Time
—
5
10
ns
—
SP30
TDOF
SDOx Data Output Fall Time
(Note 4)
—
—
—
ns
See parameter DO32
SP31
TDOR
SDOx Data Output Rise Time
(Note 4)
—
—
—
ns
See parameter DO31
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
20
ns
VDD > 2.7V
—
—
30
ns
VDD < 2.7V
SP40
TDIV2SCH, Setup Time of SDIx Data Input
TDIV2SCL to SCKx Edge
10
—
—
ns
—
SP41
TSCH2DIL, Hold Time of SDIx Data Input
TSCL2DIL to SCKx Edge
10
—
—
ns
—
SP50
TSSL2SCH, SSx to SCKx or SCKx Input
TSSL2SCL
175
—
—
ns
—
Note 1:
2:
3:
4:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 50 ns.
Assumes 50 pF load on all SPIx pins.
2011-2019 Microchip Technology Inc.
DS60001168L-page 285
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
SP51
TSSH2DOZ SSx to SDOX Output
High-Impedance
(Note 4)
5
—
25
ns
—
SP52
TSCH2SSH SSx after SCKx Edge
TSCL2SSH
TSCK +
20
—
—
ns
—
SP60
TSSL2DOV SDOx Data Output Valid after
SSx Edge
—
—
25
ns
—
Note 1:
2:
3:
4:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 50 ns.
Assumes 50 pF load on all SPIx pins.
DS60001168L-page 286
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 30-14:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 30-1 for load conditions.
FIGURE 30-15:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM25
IM33
SDAx
In
IM40
IM40
IM45
SDAx
Out
Note: Refer to Figure 30-1 for load conditions.
2011-2019 Microchip Technology Inc.
DS60001168L-page 287
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
IM10
IM11
IM20
Min.(1)
Max.
Units
Conditions
TLO:SCL Clock Low Time 100 kHz mode
TPB * (BRG + 2)
—
s
—
400 kHz mode
TPB * (BRG + 2)
—
s
—
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
s
—
Clock High Time 100 kHz mode
TPB * (BRG + 2)
—
s
—
400 kHz mode
TPB * (BRG + 2)
—
s
—
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
s
—
—
300
ns
20 + 0.1 CB
300
ns
—
100
ns
—
1000
ns
20 + 0.1 CB
300
ns
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode
(Note 2)
100
—
ns
THI:SCL
TF:SCL
Characteristics
SDAx and SCLx 100 kHz mode
Fall Time
400 kHz mode
1 MHz mode
(Note 2)
IM21
TR:SCL
SDAx and SCLx 100 kHz mode
Rise Time
400 kHz mode
1 MHz mode
(Note 2)
IM25
IM26
IM30
IM31
IM33
IM34
TSU:DAT Data Input
Setup Time
THD:DAT Data Input
Hold Time
TSU:STA Start Condition
Setup Time
THD:STA Start Condition
Hold Time
TSU:STO Stop Condition
Setup Time
THD:STO Stop Condition
Hold Time
Note 1:
2:
3:
100 kHz mode
0
—
s
400 kHz mode
0
0.9
s
1 MHz mode
(Note 2)
0
0.3
s
100 kHz mode
TPB * (BRG + 2)
—
s
400 kHz mode
TPB * (BRG + 2)
—
s
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
s
100 kHz mode
TPB * (BRG + 2)
—
s
400 kHz mode
TPB * (BRG + 2)
—
s
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
s
100 kHz mode
TPB * (BRG + 2)
—
s
400 kHz mode
TPB * (BRG + 2)
—
s
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
s
100 kHz mode
TPB * (BRG + 2)
—
ns
400 kHz mode
TPB * (BRG + 2)
—
ns
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
ns
CB is specified to be
from 10 to 400 pF
CB is specified to be
from 10 to 400 pF
—
—
Only relevant for
Repeated Start
condition
After this period, the
first clock pulse is
generated
—
—
BRG is the value of the I2C Baud Rate Generator.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
The typical value for this parameter is 104 ns.
DS60001168L-page 288
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
IM40
IM45
Min.(1)
Max.
Units
Conditions
100 kHz mode
—
3500
ns
—
400 kHz mode
—
1000
ns
—
1 MHz mode
(Note 2)
—
350
ns
—
The amount of time the
bus must be free
before a new
transmission can start
Characteristics
TAA:SCL Output Valid
from Clock
TBF:SDA Bus Free Time
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode
(Note 2)
0.5
—
s
IM50
CB
Bus Capacitive Loading
—
400
pF
—
IM51
TPGD
Pulse Gobbler Delay
52
312
ns
See Note 3
Note 1:
2:
3:
BRG is the value of the I2C Baud Rate Generator.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
The typical value for this parameter is 104 ns.
2011-2019 Microchip Technology Inc.
DS60001168L-page 289
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
FIGURE 30-16:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 30-1 for load conditions.
FIGURE 30-17:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS25
IS33
SDAx
In
IS40
IS40
IS45
SDAx
Out
Note: Refer to Figure 30-1 for load conditions.
DS60001168L-page 290
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
No.
IS10
IS11
IS20
Symbol
TLO:SCL
THI:SCL
TF:SCL
Characteristics
Clock Low Time
Clock High Time
SDAx and SCLx
Fall Time
Min.
Max.
Units
100 kHz mode
4.7
—
s
PBCLK must operate at a
minimum of 800 kHz
400 kHz mode
1.3
—
s
PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode
(Note 1)
0.5
—
s
100 kHz mode
4.0
—
s
PBCLK must operate at a
minimum of 800 kHz
400 kHz mode
0.6
—
s
PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode
(Note 1)
0.5
—
s
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
—
300
ns
250
—
ns
1 MHz mode
(Note 1)
IS21
TR:SCL
SDAx and SCLx
Rise Time
1 MHz mode
(Note 1)
IS25
IS26
IS30
IS31
IS33
Note 1:
TSU:DAT
THD:DAT
TSU:STA
THD:STA
TSU:STO
Data Input
Setup Time
Data Input
Hold Time
Start Condition
Setup Time
Start Condition
Hold Time
Stop Condition
Setup Time
100 kHz mode
400 kHz mode
100
—
ns
1 MHz mode
(Note 1)
100
—
ns
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
1 MHz mode
(Note 1)
0
0.3
s
100 kHz mode
4700
—
ns
400 kHz mode
600
—
ns
1 MHz mode
(Note 1)
250
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode
(Note 1)
250
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode
(Note 1)
600
—
ns
Conditions
—
—
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
—
—
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
—
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2011-2019 Microchip Technology Inc.
DS60001168L-page 291
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
No.
IS34
IS40
Symbol
THD:STO
TAA:SCL
Characteristics
Stop Condition
Hold Time
Min.
Max.
Units
Conditions
100 kHz mode
4000
—
ns
—
400 kHz mode
600
—
ns
1 MHz mode
(Note 1)
250
Output Valid from 100 kHz mode
Clock
400 kHz mode
0
3500
0
1000
ns
0
350
ns
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode
(Note 1)
0.5
—
s
—
400
pF
1 MHz mode
(Note 1)
IS45
IS50
Note 1:
TBF:SDA
CB
Bus Free Time
ns
Bus Capacitive Loading
ns
—
The amount of time the bus
must be free before a new
transmission can start
—
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS60001168L-page 292
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
TABLE 30-34: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param.
Symbol
No.
Standard Operating Conditions (see Note 5): 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Characteristics
Min.
Typical
Max.
Units
Conditions
—
Device Supply
AD01
AVDD
Module VDD Supply
Greater of
VDD – 0.3
or 2.5
—
Lesser of
VDD + 0.3 or
3.6
V
AD02
AVSS
Module VSS Supply
VSS
—
AVDD
V
(Note 1)
—
—
AVDD
3.6
V
V
(Note 1)
VREFH = AVDD (Note 3)
Reference Inputs
AD05 VREFH
AD05a
Reference Voltage High AVSS + 2.0
2.5
AD06
VREFL
Reference Voltage Low
AVSS
—
VREFH – 2.0
V
(Note 1)
AD07
VREF
Absolute Reference
Voltage (VREFH – VREFL)
2.0
—
AVDD
V
(Note 3)
Current Drain
—
—
250
—
400
3
µA
µA
ADC operating
ADC off
VREFL
—
VREFH
V
—
AD08 IREF
AD08a
Analog Input
AD12
VINH-VINL Full-Scale Input Span
AD13
VINL
Absolute VINL Input
Voltage
AVSS – 0.3
—
AVDD/2
V
—
AD14
VIN
Absolute Input Voltage
AVSS – 0.3
—
AVDD + 0.3
V
—
Leakage Current
—
±0.001
±0.610
µA
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
Source Impedance = 10 k
Recommended
Impedance of Analog
Voltage Source
—
—
5k
(Note 1)
AD15
AD17
—
RIN
ADC Accuracy – Measurements with External VREF+/VREFAD20c Nr
Resolution
AD21c INL
Integral Non-linearity
> -1
—
-1
—
-1
—
-1
—
-1
—
-1
—
-4
—
-2
—
6623@
1RWH
)RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWS ZZZPLFURFKLSFRPSDFNDJLQJ
D
N
E
E1
1 2
NOTE 1
b
e
c
A2
A
φ
A1
L
L1
8QLWV
'LPHQVLRQ/LPLWV
1XPEHURI3LQV
0,//,0(7(56
0,1
1
120
0$;
3LWFK
H
2YHUDOO+HLJKW
$
±
%6&
±
0ROGHG3DFNDJH7KLFNQHVV
$
6WDQGRII
$
±
±
2YHUDOO:LGWK
(
0ROGHG3DFNDJH:LGWK
(
2YHUDOO/HQJWK
'
)RRW/HQJWK
/
)RRWSULQW
/
5()
/HDG7KLFNQHVV
F
±
)RRW$QJOH
/HDG:LGWK
E
±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(63',3@
1RWH
)RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWS ZZZPLFURFKLSFRPSDFNDJLQJ
N
NOTE 1
E1
1
2 3
D
E
A2
A
L
c
b1
A1
b
e
eB
8QLWV
'LPHQVLRQ/LPLWV
1XPEHURI3LQV
,1&+(6
0,1
1
120
0$;
3LWFK
H
7RSWR6HDWLQJ3ODQH
$
±
±
0ROGHG3DFNDJH7KLFNQHVV
$
%DVHWR6HDWLQJ3ODQH
$
±
±
6KRXOGHUWR6KRXOGHU:LGWK
(
0ROGHG3DFNDJH:LGWK
(
2YHUDOO/HQJWK
'
7LSWR6HDWLQJ3ODQH
/
/HDG7KLFNQHVV
F
E
E
H%
±
±
8SSHU/HDG:LGWK
/RZHU/HDG:LGWK
2YHUDOO5RZ6SDFLQJ
%6&
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
6LJQLILFDQW&KDUDFWHULVWLF
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(4)1@
ZLWKPP&RQWDFW/HQJWK
1RWH
)RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWS ZZZPLFURFKLSFRPSDFNDJLQJ
D
D2
EXPOSED
PAD
e
E
b
E2
2
2
1
1
N
K
N
NOTE 1
L
BOTTOM VIEW
TOP VIEW
A
A3
A1
8QLWV
'LPHQVLRQ/LPLWV
1XPEHURI3LQV
0,//,0(7(56
0,1
1
120
0$;
3LWFK
H
2YHUDOO+HLJKW
$
6WDQGRII
$
&RQWDFW7KLFNQHVV
$
2YHUDOO:LGWK
(
([SRVHG3DG:LGWK
(
2YHUDOO/HQJWK
'
([SRVHG3DG/HQJWK
%6&
5()
%6&
%6&
'
&RQWDFW:LGWK
E
&RQWDFW/HQJWK
/
&RQWDFWWR([SRVHG3DG
.
±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
3DFNDJHLVVDZVLQJXODWHG
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(4)1@
1RWH
)RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWS ZZZPLFURFKLSFRPSDFNDJLQJ
DS60001168L-page 330
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
/HDG3ODVWLF7KLQ4XDG)ODWSDFN 37 ±[[PP%RG\PP>74)3@
1RWH
)RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWS ZZZPLFURFKLSFRPSDFNDJLQJ
D
D1
E
e
E1
N
b
NOTE 1
1 2 3
NOTE 2
α
A
φ
c
β
A2
A1
L
L1
8QLWV
'LPHQVLRQ/LPLWV
1XPEHURI/HDGV
0,//,0(7(56
0,1
1
120
0$;
/HDG3LWFK
H
2YHUDOO+HLJKW
$
±
%6&
±
0ROGHG3DFNDJH7KLFNQHVV
$
6WDQGRII
$
±
)RRW/HQJWK
/
)RRWSULQW
/
5()
)RRW$QJOH
2YHUDOO:LGWK
(
%6&
2YHUDOO/HQJWK
'
%6&
0ROGHG3DFNDJH:LGWK
(
%6&
0ROGHG3DFNDJH/HQJWK
'
%6&
/HDG7KLFNQHVV
F
±
/HDG:LGWK
E
0ROG'UDIW$QJOH7RS
0ROG'UDIW$QJOH%RWWRP
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
&KDPIHUVDWFRUQHUVDUHRSWLRQDO VL]HPD\YDU\
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(
工商网监
湘ICP备2023018690号
