PIC32MX5XX/6XX/7XX
32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM)
with Graphics Interface, USB, CAN, and Ethernet
Operating Conditions
Timers/Output Compare/Input Capture
• 2.3V to 3.6V, -40ºC to +105ºC, DC to 80 MHz
®
Core: 80 MHz/105 DMIPS MIPS32 M4K
• Five General Purpose Timers:
- Five 16-bit and up to two 32-bit Timers/Counters
• Five Output Compare (OC) modules
• Five Input Capture (IC) modules
• Real-Time Clock and Calendar (RTCC) module
®
• MIPS16e® mode for up to 40% smaller code size
• Code-efficient (C and Assembly) architecture
• Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply
Communication Interfaces
Clock Management
•
•
•
•
•
• USB 2.0-compliant Full-Speed OTG controller
• 10/100 Mbps Ethernet MAC with MII and RMII interface
• CAN module:
- 2.0B Active with DeviceNet™ addressing support
• Six UART modules (20 Mbps):
- Supports LIN 2.1 protocols and IrDA® support
• Up to four 4-wire SPI modules (25 Mbps)
• Up to five I2C modules (up to 1 Mbaud) with SMBus
support
• Parallel Master Port (PMP)
0.9% internal oscillator (on some variants)
Programmable PLLs and oscillator clock sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer
Fast wake-up and start-up
Power Management
•
•
•
•
Low-power management modes (Sleep and Idle)
Integrated Power-on Reset, Brown-out Reset
0.5 mA/MHz dynamic current (typical)
41 µA IPD current (typical)
Direct Memory Access (DMA)
• Up to eight channels of hardware DMA with automatic
data size detection
• 32-bit Programmable Cyclic Redundancy Check (CRC)
• Six additional channels dedicated to USB, Ethernet and
CAN modules
Graphics Features
• External graphics interface with up to 34 Parallel Master
Port (PMP) pins:
- Interface to external graphics controller
- Capable of driving LCD directly with DMA and
internal or external memory
Input/Output
• 15 mA or 10 mA source/sink for standard VOH/VOL and
up to 22 mA for non-standard VOH1
• 5V-tolerant pins
• Selectable open drain and pull-ups
• External interrupts
Analog Features
• ADC Module:
- 10-bit 1 Msps rate with one Sample and Hold (S&H)
- 16 analog inputs
- Can operate during Sleep mode
• Flexible and independent ADC trigger sources
• Comparators:
- Two dual-input Comparator modules
- Programmable references with 32 voltage points
Class B Support
• Class B Safety Library, IEC 60730
Debugger Development Support
•
•
•
•
In-circuit and in-application programming
4-wire MIPS® Enhanced JTAG interface
Unlimited program and six complex data breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Packages
Type
QFN
TFBGA
VTLA
Pin Count
64
64
100
100
121
124
I/O Pins (up to)
Contact/Lead Pitch
51
0.50
51
0.50
83
0.40
83
0.50
83
0.80
83
0.50
12x12x1
14x14x1
10x10x1.1
9x9x0.9
Note:
TQFP
Dimensions
9x9x0.9
10x10x1
All dimensions are in millimeters (mm) unless specified.
2009-2019 Microchip Technology Inc.
DS60001156K-page 1
PIC32MX5XX/6XX/7XX
TABLE 1:
PIC32MX5XX USB AND CAN FEATURES
Device
Pins
Program Memory (KB)
Data Memory (KB)
USB
CAN
Timers/Capture/Compare
DMA Channels
(Programmable/Dedicated)
UART(2,3)
SPI(3)
I2C(3)
10-bit 1 Msps ADC (Channels)
Comparators
PMP/PSP
JTAG
Trace
Packages(4)
USB and CAN
PIC32MX534F064H
64
64 + 12(1)
16
1
1
5/5/5
4/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX564F064H
64
64 + 12(1)
32
1
1
5/5/5
4/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX564F128H
64
128 + 12(1)
32
1
1
5/5/5
4/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX575F256H
64
256 + 12(1)
64
1
1
5/5/5
8/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX575F512H
64
512 + 12(1)
64
1
1
5/5/5
8/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX534F064L
100
64 + 12(1)
16
1
1
5/5/5
4/4
6
4
5
16
2
Yes
Yes
Yes
PT,
PF,
BG
PIC32MX564F064L
100
64 + 12(1)
32
1
1
5/5/5
4/4
6
4
5
16
2
Yes
Yes
Yes
PT,
PF,
BG
PIC32MX564F128L
100 128 + 12(1)
32
1
1
5/5/5
4/4
6
4
5
16
2
Yes
Yes
Yes
PT,
PF,
BG
PIC32MX575F256L
100 256 + 12(1)
64
1
1
5/5/5
8/4
6
4
5
16
2
Yes
Yes
Yes
PT,
PF,
BG
PIC32MX575F512L
100 512 + 12(1)
64
1
1
5/5/5
8/4
6
4
5
16
2
Yes
Yes
Yes
PT,
PF,
BG
Legend:
Note 1:
2:
3:
4:
5:
PF, PT = TQFP
MR = QFN
BG = TFBGA
TL = VTLA(5)
This device features 12 KB boot Flash memory.
CTS and RTS pins may not be available for all UART modules. Refer to the “Device Pin Tables” section for more
information.
Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Device Pin Tables” section for more
information.
Refer to 34.0 “Packaging Information” for more information.
100-pin devices in the VTLA package are available upon request. Please contact your local Microchip Sales Office for
details.
DS60001156K-page 2
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 2:
PIC32MX6XX USB AND ETHERNET FEATURES
Device
Pins
Program Memory (KB)
Data Memory (KB)
USB
Ethernet
Timers/Capture/Compare
DMA Channels
(Programmable/Dedicated)
UART(2,3)
SPI(3)
I2C(3)
10-bit 1 Msps ADC (Channels)
Comparators
PMP/PSP
JTAG
Trace
Packages(4)
USB and Ethernet
PIC32MX664F064H
64
64 + 12(1)
32
1
1
5/5/5
4/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX664F128H
64
128 + 12(1)
32
1
1
5/5/5
4/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX675F256H
64
256 + 12(1)
64
1
1
5/5/5
8/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX675F512H
64
512 + 12(1)
64
1
1
5/5/5
8/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX695F512H
64
512 + 12(1)
128
1
1
5/5/5
8/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX664F064L
100
64 + 12(1)
32
1
1
5/5/5
4/4
6
4
5
16
2
Yes
Yes
Yes
PT, PF,
BG
PIC32MX664F128L
100
128 + 12(1)
32
1
1
5/5/5
4/4
6
4
5
16
2
Yes
Yes
Yes
PT, PF,
BG
PIC32MX675F256L
100
256 + 12(1)
64
1
1
5/5/5
8/4
6
4
5
16
2
Yes
Yes
Yes
PT, PF,
BG
PIC32MX675F512L
100
512 + 12(1)
64
1
1
5/5/5
8/4
6
4
5
16
2
Yes
Yes
Yes
PT, PF,
BG, TL
PIC32MX695F512L
100
512 + 12(1)
128
1
1
5/5/5
8/4
6
4
5
16
2
Yes
Yes
Yes
PT, PF,
BG, TL
Legend:
Note 1:
2:
3:
4:
5:
PF, PT = TQFP
MR = QFN
BG = TFBGA
TL = VTLA(5)
This device features 12 KB boot Flash memory.
CTS and RTS pins may not be available for all UART modules. Refer to the “Device Pin Tables” section for more
information.
Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Device Pin Tables” section for
more information.
Refer to 34.0 “Packaging Information” for more information.
100-pin devices other than those listed here are available in the VTLA package upon request. Please contact your local
Microchip Sales Office for details.
2009-2019 Microchip Technology Inc.
DS60001156K-page 3
PIC32MX5XX/6XX/7XX
TABLE 3:
PIC32MX7XX USB, ETHERNET, AND CAN FEATURES
Device
Pins
Program Memory (KB)
Data Memory (KB)
USB
Ethernet
CAN
Timers/Capture/Compare
DMA Channels
(Programmable/Dedicated)
UART(2,3)
SPI(3)
I2C(3)
10-bit 1 Msps ADC (Channels)
Comparators
PMP/PSP
JTAG
Trace
Packages(4)
USB, Ethernet, and CAN
PIC32MX764F128H
64
128 + 12(1)
32
1
1
1
5/5/5
4/8
6
3
4
16
2
Yes Yes
No
PT,
MR
PIC32MX775F256H
64
256 + 12(1)
64
1
1
2
5/5/5
8/8
6
3
4
16
2
Yes Yes
No
PT,
MR
PIC32MX775F512H
64
512 + 12(1)
64
1
1
2
5/5/5
8/8
6
3
4
16
2
Yes Yes
No
PT,
MR
PIC32MX795F512H
64
512 + 12(1) 128
1
1
2
5/5/5
8/8
6
3
4
16
2
Yes Yes
No
PT,
MR
PIC32MX764F128L
100 128 + 12(1)
32
1
1
1
5/5/5
4/6
6
4
5
16
2
Yes Yes Yes
PT, PF,
BG
PIC32MX775F256L
100 256 + 12(1)
64
1
1
2
5/5/5
8/8
6
4
5
16
2
Yes Yes Yes
PT, PF,
BG
PIC32MX775F512L
100 512 + 12(1)
64
1
1
2
5/5/5
8/8
6
4
5
16
2
Yes Yes Yes
PT, PF,
BG
PIC32MX795F512L
100 512 + 12(1) 128
1
1
2
5/5/5
8/8
6
4
5
16
2
Yes Yes Yes
PT, PF,
BG, TL
Legend:
Note 1:
2:
3:
4:
5:
PF, PT = TQFP
MR = QFN
BG = TFBGA
TL = VTLA(5)
This device features 12 KB boot Flash memory.
CTS and RTS pins may not be available for all UART modules. Refer to the “Device Pin Tables” section for more
information.
Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Device Pin Tables” section for
more information.
Refer to Section 34.0 “Packaging Information” for more information.
100-pin devices other than those listed here are available in the VTLA package upon request. Please contact your local
Microchip Sales Office for details.
DS60001156K-page 4
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Device Pin Tables
TABLE 4:
PIN NAMES FOR 64-PIN USB AND CAN DEVICES
64-PIN QFN(2) AND TQFP (TOP VIEW)
PIC32MX534F064H
PIC32MX564F064H
PIC32MX564F128H
PIC32MX575F256H
PIC32MX575F512H
64
1
QFN(2)
Pin #
Full Pin Name
64
TQFP
Pin #
Full Pin Name
1
PMD5/RE5
33
USBID/RF3
2
PMD6/RE6
34
VBUS
3
PMD7/RE7
35
VUSB3V3
4
SCK2/U6TX/U3RTS/PMA5/CN8/RG6
36
D-/RG3
5
SDA4/SDI2/U3RX/PMA4/CN9/RG7
37
D+/RG2
6
SCL4/SDO2/U3TX/PMA3/CN10/RG8
38
VDD
7
MCLR
39
OSC1/CLKI/RC12
8
SS2/U6RX/U3CTS/PMA2/CN11/RG9
40
OSC2/CLKO/RC15
9
VSS
41
Vss
10
VDD
42
RTCC/IC1/INT1/RD8
11
AN5/C1IN+/VBUSON/CN7/RB5
43
SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
12
AN4/C1IN-/CN6/RB4
44
SCL1/IC3/PMCS2/PMA15/INT3/RD10
13
AN3/C2IN+/CN5/RB3
45
IC4/PMCS1/PMA14/INT4/RD11
14
AN2/C2IN-/CN4/RB2
46
OC1/INT0/RD0
15
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
47
SOSCI/CN1/RC13
16
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
48
SOSCO/T1CK/CN0/RC14
17
PGEC2/AN6/OCFA/RB6
49
SCK3/U4TX/U1RTS/OC2/RD1
18
PGED2/AN7/RB7
50
SDA3/SDI3/U1RX/OC3/RD2
19
AVDD
51
SCL3/SDO3/U1TX/OC4/RD3
20
AVSS
52
OC5/IC5/PMWR/CN13/RD4
21
AN8/SS4/U5RX/U2CTS/C1OUT/RB8
53
PMRD/CN14/RD5
22
AN9/C2OUT/PMA7/RB9
54
CN15/RD6
23
TMS/AN10/CVREFOUT/PMA13/RB10
55
CN16/RD7
24
TDO/AN11/PMA12/RB11
56
VCAP
25
VSS
57
VDD
26
VDD
58
C1RX/RF0
27
TCK/AN12/PMA11/RB12
59
C1TX/RF1
28
TDI/AN13/PMA10/RB13
60
PMD0/RE0
29
AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14
61
PMD1/RE1
30
AN15/OCFB/PMALL/PMA0/CN12/RB15
62
PMD2/RE2
31
AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4
63
PMD3/RE3
32
AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5
64
PMD4/RE4
Note
1:
2:
1
Shaded pins are 5V tolerant.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
2009-2019 Microchip Technology Inc.
DS60001156K-page 5
PIC32MX5XX/6XX/7XX
TABLE 5:
PIN NAMES FOR 64-PIN USB AND ETHERNET DEVICES
64-PIN QFN(2) AND TQFP (TOP VIEW)
PIC32MX664F064H
PIC32MX664F128H
PIC32MX675F256H
PIC32MX675F512H
PIC32MX695F512H
64
1
QFN(2)
Pin #
Full Pin Name
64
TQFP
Pin #
1
Full Pin Name
1
ETXEN/PMD5/RE5
33
USBID/RF3
2
ETXD0/PMD6/RE6
34
VBUS
3
ETXD1/PMD7/RE7
35
VUSB3V3
4
SCK2/U6TX/U3RTS/PMA5/CN8/RG6
36
D-/RG3
5
SDA4/SDI2/U3RX/PMA4/CN9/RG7
37
D+/RG2
6
SCL4/SDO2/U3TX/PMA3/CN10/RG8
38
VDD
7
MCLR
39
OSC1/CLKI/RC12
8
SS2/U6RX/U3CTS/PMA2/CN11/RG9
40
OSC2/CLKO/RC15
9
VSS
41
Vss
10
VDD
42
RTCC/AERXD1/ETXD3/IC1/INT1/RD8
11
AN5/C1IN+/VBUSON/CN7/RB5
43
AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
12
AN4/C1IN-/CN6/RB4
44
ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
13
AN3/C2IN+/CN5/RB3
45
ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
14
AN2/C2IN-/CN4/RB2
46
OC1/INT0/RD0
15
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
47
SOSCI/CN1/RC13
16
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
48
SOSCO/T1CK/CN0/RC14
17
PGEC2/AN6/OCFA/RB6
49
EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1
18
PGED2/AN7/RB7
50
SDA3/SDI3/U1RX/OC3/RD2
19
AVDD
51
SCL3/SDO3/U1TX/OC4/RD3
20
AVSS
52
OC5/IC5/PMWR/CN13/RD4
21
AN8/SS4/U5RX/U2CTS/C1OUT/RB8
53
PMRD/CN14/RD5
22
AN9/C2OUT/PMA7/RB9
54
AETXEN/ETXERR/CN15/RD6
23
TMS/AN10/CVREFOUT/PMA13/RB10
55
ETXCLK/AERXERR/CN16/RD7
24
TDO/AN11/PMA12/RB11
56
VCAP
25
VSS
57
VDD
26
VDD
58
AETXD1/ERXD3/RF0
27
TCK/AN12/PMA11/RB12
59
AETXD0/ERXD2/RF1
28
TDI/AN13/PMA10/RB13
60
ERXD1/PMD0/RE0
29
AN14/SCK4/U5TX/U2RTSU2RTS/PMALH/PMA1/RB14
61
ERXD0/PMD1/RE1
30
AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15
62
ERXDV/ECRSDV/PMD2/RE2
31
SDA5/SDI4/U2RX/PMA9/CN17/RF4
63
ERXCLK/EREFCLK/PMD3/RE3
32
SCL5/SDO4/U2TX/PMA8/CN18/RF5
64
ERXERR/PMD4/RE4
Note
1:
2:
Shaded pins are 5V tolerant.
The metal plane at the bottom of the QFN device is not connected to any pins and is recommended to be connected to VSS externally.
DS60001156K-page 6
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 6:
PIN NAMES FOR 64-PIN USB, ETHERNET, AND CAN DEVICES
64-PIN QFN(3) AND TQFP (TOP VIEW)
PIC32MX764F128H
PIC32MX775F256H
PIC32MX775F512H
PIC32MX795F512H
64
1
QFN(3)
Pin #
Full Pin Name
1
ETXEN/PMD5/RE5
2
3
4
64
TQFP
Pin #
1
Full Pin Name
33
USBID/RF3
ETXD0/PMD6/RE6
34
VBUS
ETXD1/PMD7/RE7
35
VUSB3V3
SCK2/U6TX/U3RTS/PMA5/CN8/RG6
36
D-/RG3
5
SDA4/SDI2/U3RX/PMA4/CN9/RG7
37
D+/RG2
6
SCL4/SDO2/U3TX/PMA3/CN10/RG8
38
VDD
7
MCLR
39
OSC1/CLKI/RC12
8
SS2/U6RX/U3CTS/PMA2/CN11/RG9
40
OSC2/CLKO/RC15
9
VSS
41
Vss
10
VDD
42
RTCC/AERXD1/ETXD3/IC1/INT1/RD8
11
AN5/C1IN+/VBUSON/CN7/RB5
43
AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
12
AN4/C1IN-/CN6/RB4
44
ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
13
AN3/C2IN+/CN5/RB3
45
ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
14
AN2/C2IN-/CN4/RB2
46
OC1/INT0/RD0
15
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
47
SOSCI/CN1/RC13
16
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
48
SOSCO/T1CK/CN0/RC14
17
PGEC2/AN6/OCFA/RB6
49
EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1
18
PGED2/AN7/RB7
50
SDA3/SDI3/U1RX/OC3/RD2
19
AVDD
51
SCL3/SDO3/U1TX/OC4/RD3
20
AVSS
52
OC5/IC5/PMWR/CN13/RD4
21
AN8/C2TX(2)/SS4/U5RX/U2CTS/C1OUT/RB8
53
PMRD/CN14/RD5
22
AN9/C2OUT/PMA7/RB9
54
AETXEN/ETXERR/CN15/RD6
23
TMS/AN10/CVREFOUT/PMA13/RB10
55
ETXCLK/AERXERR/CN16/RD7
24
TDO/AN11/PMA12/RB11
56
VCAP
25
VSS
57
VDD
26
VDD
58
C1RX/AETXD1/ERXD3/RF0
27
TCK/AN12/PMA11/RB12
59
C1TX/AETXD0/ERXD2/RF1
28
TDI/AN13/PMA10/RB13
60
ERXD1/PMD0/RE0
29
AN14/C2RX(2)/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14
61
ERXD0/PMD1/RE1
30
AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15
62
ERXDV/ECRSDV/PMD2/RE2
31
AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4
63
ERXCLK/EREFCLKPMD3/RE3
32
AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5
64
ERXERR/PMD4/RE4
Note
1:
2:
3:
Shaded pins are 5V tolerant.
This pin is not available on PIC32MX765F128H devices.
The metal plane at the bottom of the QFN device is not connected to any pins and is recommended to be connected to VSS externally.
2009-2019 Microchip Technology Inc.
DS60001156K-page 7
PIC32MX5XX/6XX/7XX
TABLE 7:
PIN NAMES FOR 100-PIN USB AND CAN DEVICES
100-PIN TQFP (TOP VIEW)
PIC32MX534F064L
PIC32MX564F064L
PIC32MX564F128L
PIC32MX575F512L
PIC32MX575F256L
100
1
Pin #
Full Pin Name
Pin #
Full Pin Name
1
RG15
36
VSS
2
VDD
37
VDD
3
PMD5/RE5
38
TCK/RA1
4
PMD6/RE6
39
AC1TX/SCK4/U5TX/U2RTS/RF13
5
PMD7/RE7
40
AC1RX/SS4/U5RX/U2CTS/RF12
6
T2CK/RC1
41
AN12/PMA11/RB12
7
T3CK/RC2
42
AN13/PMA10/RB13
8
T4CK/RC3
43
AN14/PMALH/PMA1/RB14
9
T5CK/SDI1/RC4
44
AN15/OCFB/PMALL/PMA0/CN12/RB15
10
SCK2/U6TX/U3RTS/PMA5/CN8/RG6
45
VSS
11
SDA4/SDI2/U3RX/PMA4/CN9/RG7
46
VDD
12
SCL4/SDO2/U3TX/PMA3/CN10/RG8
47
SS3/U4RX/U1CTS/CN20/RD14
13
MCLR
48
SCK3/U4TX/U1RTS/CN21/RD15
14
SS2/U6RX/U3CTS/PMA2/CN11/RG9
49
SDA5/SDI4/U2RX/PMA9/CN17/RF4
15
VSS
50
SCL5/SDO4/U2TX/PMA8/CN18/RF5
16
VDD
51
USBID/RF3
17
TMS/RA0
52
SDA3/SDI3/U1RX/RF2
18
INT1/RE8
53
SCL3/SDO3/U1TX/RF8
19
INT2/RE9
54
VBUS
20
AN5/C1IN+/VBUSON/CN7/RB5
55
VUSB3V3
21
AN4/C1IN-/CN6/RB4
56
D-/RG3
22
AN3/C2IN+/CN5/RB3
57
D+/RG2
23
AN2/C2IN-/CN4/RB2
58
SCL2/RA2
24
PGEC1/AN1/CN3/RB1
59
SDA2/RA3
25
PGED1/AN0/CN2/RB0
60
TDI/RA4
26
PGEC2/AN6/OCFA/RB6
61
TDO/RA5
27
PGED2/AN7/RB7
62
VDD
28
VREF-/CVREF-/PMA7/RA9
63
OSC1/CLKI/RC12
OSC2/CLKO/RC15
29
VREF+/CVREF+/PMA6/RA10
64
30
AVDD
65
VSS
31
AVSS
66
SCL1/INT3/RA14
32
AN8/C1OUT/RB8
67
SDA1/INT4/RA15
33
AN9/C2OUT/RB9
68
RTCC/IC1/RD8
34
AN10/CVREFOUT/PMA13/RB10
69
SS1/IC2/RD9
35
AN11/PMA12/RB11
70
SCK1/IC3/PMCS2/PMA15/RD10
Note
1:
Shaded pins are 5V tolerant.
DS60001156K-page 8
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 7:
PIN NAMES FOR 100-PIN USB AND CAN DEVICES (CONTINUED)
100-PIN TQFP (TOP VIEW)
PIC32MX534F064L
PIC32MX564F064L
PIC32MX564F128L
PIC32MX575F512L
PIC32MX575F256L
100
1
Pin #
Full Pin Name
Pin #
Full Pin Name
71
IC4/PMCS1/PMA14/RD11
86
VDD
72
SDO1/OC1/INT0/RD0
87
C1RX/PMD11/RF0
73
SOSCI/CN1/RC13
88
C1TX/PMD10/RF1
74
SOSCO/T1CK/CN0/RC14
89
PMD9/RG1
75
VSS
90
PMD8/RG0
76
OC2/RD1
91
TRCLK/RA6
77
OC3/RD2
92
TRD3/RA7
78
OC4/RD3
93
PMD0/RE0
79
IC5/PMD12/RD12
94
PMD1/RE1
80
PMD13/CN19/RD13
95
TRD2/RG14
81
OC5/PMWR/CN13/RD4
96
TRD1/RG12
82
PMRD/CN14/RD5
97
TRD0/RG13
83
PMD14/CN15/RD6
98
PMD2/RE2
84
PMD15/CN16/RD7
99
PMD3/RE3
85
VCAP
100
PMD4/RE4
Note
1:
Shaded pins are 5V tolerant.
2009-2019 Microchip Technology Inc.
DS60001156K-page 9
PIC32MX5XX/6XX/7XX
TABLE 8:
PIN NAMES FOR 100-PIN USB AND ETHERNET DEVICES
100-PIN TQFP (TOP VIEW)
PIC32MX664F064L
PIC32MX664F128L
PIC32MX675F256L
PIC32MX675F512L
PIC32MX695F512L
100
1
Pin #
Full Pin Name
Pin #
Full Pin Name
1
AERXERR/RG15
36
VSS
2
VDD
37
VDD
3
PMD5/RE5
38
TCK/RA1
4
PMD6/RE6
39
SCK4/U5TX/U2RTS/RF13
5
PMD7/RE7
40
SS4/U5RX/U2CTS/RF12
6
T2CK/RC1
41
AN12/ERXD0/AECRS/PMA11/RB12
7
T3CK/RC2
42
AN13/ERXD1/AECOL/PMA10/RB13
8
T4CK/RC3
43
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
9
T5CK/SDI1/RC4
44
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
10
ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6
45
VSS
VDD
11
ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
46
12
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8
47
AETXD0/SS3/U4RX/U1CTS/CN20/RD14
13
MCLR
48
AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
14
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9
49
SDA5/SDI4/U2RX/PMA9/CN17/RF4
15
VSS
50
SCL5/SDO4/U2TX/PMA8/CN18/RF5
16
VDD
51
USBID/RF3
17
TMS/RA0
52
SDA3/SDI3/U1RX/RF2
18
AERXD0/INT1/RE8
53
SCL3/SDO3/U1TX/RF8
19
AERXD1/INT2/RE9
54
VBUS
20
AN5/C1IN+/VBUSON/CN7/RB5
55
VUSB3V3
21
AN4/C1IN-/CN6/RB4
56
D-/RG3
22
AN3/C2IN+/CN5/RB3
57
D+/RG2
23
AN2/C2IN-/CN4/RB2
58
SCL2/RA2
24
PGEC1/AN1/CN3/RB1
59
SDA2/RA3
25
PGED1/AN0/CN2/RB0
60
TDI/RA4
26
PGEC2/AN6/OCFA/RB6
61
TDO/RA5
27
PGED2/AN7/RB7
62
VDD
28
VREF-/CVREF-/AERXD2/PMA7/RA9
63
OSC1/CLKI/RC12
29
VREF+/CVREF+/AERXD3/PMA6/RA10
64
OSC2/CLKO/RC15
30
AVDD
65
VSS
31
AVSS
66
AETXCLK/SCL1/INT3/RA14
32
AN8/C1OUT/RB8
67
AETXEN/SDA1/INT4/RA15
33
AN9/C2OUT/RB9
68
RTCC/EMDIO/AEMDIO/IC1/RD8
34
AN10/CVREFOUT/PMA13/RB10
69
SS1/IC2/RD9
35
AN11/ERXERR/AETXERR/PMA12/RB11
70
SCK1/IC3/PMCS2/PMA15/RD10
Note
1:
Shaded pins are 5V tolerant.
DS60001156K-page 10
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 8:
PIN NAMES FOR 100-PIN USB AND ETHERNET DEVICES (CONTINUED)
100-PIN TQFP (TOP VIEW)
PIC32MX664F064L
PIC32MX664F128L
PIC32MX675F256L
PIC32MX675F512L
PIC32MX695F512L
100
1
Pin #
Full Pin Name
Pin #
Full Pin Name
71
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
86
VDD
72
SDO1/OC1/INT0/RD0
87
ETXD1/PMD11/RF0
73
SOSCI/CN1/RC13
88
ETXD0/PMD10/RF1
74
SOSCO/T1CK/CN0/RC14
89
ETXERR/PMD9/RG1
75
VSS
90
PMD8/RG0
76
OC2/RD1
91
TRCLK/RA6
77
OC3/RD2
92
TRD3/RA7
78
OC4/RD3
93
PMD0/RE0
79
ETXD2/IC5/PMD12/RD12
94
PMD1/RE1
80
ETXD3/PMD13/CN19/RD13
95
TRD2/RG14
81
OC5/PMWR/CN13/RD4
96
TRD1/RG12
82
PMRD/CN14/RD5
97
TRD0/RG13
83
ETXEN/PMD14/CN15/RD6
98
PMD2/RE2
84
ETXCLK/PMD15/CN16/RD7
99
PMD3/RE3
85
VCAP/VDDCORE
100
PMD4/RE4
Note
1:
Shaded pins are 5V tolerant.
2009-2019 Microchip Technology Inc.
DS60001156K-page 11
PIC32MX5XX/6XX/7XX
TABLE 9:
PIN NAMES FOR 100-PIN USB, ETHERNET, AND CAN DEVICES
100-PIN TQFP (TOP VIEW)
PIC32MX764F128L
PIC32MX775F256L
PIC32MX775F512L
PIC32MX795F512L
100
1
Pin #
Full Pin Name
Pin #
Full Pin Name
1
AERXERR/RG15
36
VSS
2
VDD
37
VDD
3
PMD5/RE5
38
TCK/RA1
4
PMD6/RE6
39
AC1TX/SCK4/U5TX/U2RTS/RF13
5
PMD7/RE7
40
AC1RX/SS4/U5RX/U2CTS/RF12
6
T2CK/RC1
41
AN12/ERXD0/AECRS/PMA11/RB12
7
T3CK/AC2TX(1)/RC2
42
AN13/ERXD1/AECOL/PMA10/RB13
8
T4CK/AC2RX(1)/RC3
43
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
9
T5CK/SDI1/RC4
44
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
10
ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6
45
VSS
VDD
11
ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
46
12
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8
47
AETXD0/SS3/U4RX/U1CTS/CN20/RD14
13
MCLR
48
AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
14
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9
49
SDA5/SDI4/U2RX/PMA9/CN17/RF4
15
VSS
50
SCL5/SDO4/U2TX/PMA8/CN18/RF5
16
VDD
51
USBID/RF3
17
TMS/RA0
52
SDA3/SDI3/U1RX/RF2
18
AERXD0/INT1/RE8
53
SCL3/SDO3/U1TX/RF8
19
AERXD1/INT2/RE9
54
VBUS
20
AN5/C1IN+/VBUSON/CN7/RB5
55
VUSB3V3
21
AN4/C1IN-/CN6/RB4
56
D-/RG3
22
AN3/C2IN+/CN5/RB3
57
D+/RG2
23
AN2/C2IN-/CN4/RB2
58
SCL2/RA2
24
PGEC1/AN1/CN3/RB1
59
SDA2/RA3
25
PGED1/AN0/CN2/RB0
60
TDI/RA4
26
PGEC2/AN6/OCFA/RB6
61
TDO/RA5
27
PGED2/AN7/RB7
62
VDD
28
VREF-/CVREF-/AERXD2/PMA7/RA9
63
OSC1/CLKI/RC12
29
VREF+/CVREF+/AERXD3/PMA6/RA10
64
OSC2/CLKO/RC15
30
AVDD
65
VSS
31
AVSS
66
AETXCLK/SCL1/INT3/RA14
32
AN8/C1OUT/RB8
67
AETXEN/SDA1/INT4/RA15
33
AN9/C2OUT/RB9
68
RTCC/EMDIO/AEMDIO/IC1/RD8
34
AN10/CVREFOUT/PMA13/RB10
69
SS1/IC2/RD9
AN11/ERXERR/AETXERR/PMA12/RB11
1:
This pin is not available on PIC32MX764F128L devices.
2:
Shaded pins are 5V tolerant.
70
SCK1/IC3/PMCS2/PMA15/RD10
35
Note
DS60001156K-page 12
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 9:
PIN NAMES FOR 100-PIN USB, ETHERNET, AND CAN DEVICES (CONTINUED)
100-PIN TQFP (TOP VIEW)
PIC32MX764F128L
PIC32MX775F256L
PIC32MX775F512L
PIC32MX795F512L
100
1
Pin #
71
72
Full Pin Name
Pin #
Full Pin Name
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
SDO1/OC1/INT0/RD0
86
87
73
SOSCI/CN1/RC13
88
C1TX/ETXD0/PMD10/RF1
74
89
75
SOSCO/T1CK/CN0/RC14
VSS
90
C2TX(1)/ETXERR/PMD9/RG1
C2RX(1)/PMD8/RG0
76
OC2/RD1
91
TRCLK/RA6
77
OC3/RD2
92
TRD3/RA7
78
OC4/RD3
93
PMD0/RE0
79
ETXD2/IC5/PMD12/RD12
94
PMD1/RE1
80
ETXD3/PMD13/CN19/RD13
95
TRD2/RG14
81
OC5/PMWR/CN13/RD4
96
TRD1/RG12
82
PMRD/CN14/RD5
97
TRD0/RG13
83
ETXEN/PMD14/CN15/RD6
98
PMD2/RE2
84
ETXCLK/PMD15/CN16/RD7
99
PMD3/RE3
85
VCAP/VDDCORE
100
PMD4/RE4
Note
1:
2:
VDD
C1RX/ETXD1/PMD11/RF0
This pin is not available on PIC32MX764F128L devices.
Shaded pins are 5V tolerant.
2009-2019 Microchip Technology Inc.
DS60001156K-page 13
PIC32MX5XX/6XX/7XX
TABLE 10:
PIN NAMES FOR USB AND CAN DEVICES
121-PIN TFBGA (BOTTOM VIEW)
PIC32MX534F064L
PIC32MX564F064L
PIC32MX564F128L
PIC32MX575F256L
PIC32MX575F512L
Note:
L11
L1
A11
The TFBGA package skips from row “H” to row “J” and has no “I” row. A1
Pin #
Full Pin Name
Pin #
Full Pin Name
A1
PMD4/RE4
E2
T4CK/RC3
A2
PMD3/RE3
E3
SCK2/U6TXU6TX/U3RTS/PMA5/CN8/RG6
A3
TRD0/RG13
E4
T3CK/RC2
A4
PMD0/RE0
E5
VDD
A5
PMD8/RG0
E6
PMD9/RG1
A6
C1TX/PMD10/RF1
E7
VSS
A7
VDD
E8
SDA1/INT4/RA15
RTCC/IC1/RD8
A8
VSS
E9
A9
IC5/PMD12/RD12
E10
SS1/IC2/RD9
A10
OC3/RD2
E11
SCL1/INT3/RA14
A11
OC2/RD1
F1
MCLR
B1
No Connect (NC)
F2
SCL4/SDO2/U3TX/PMA3/CN10/RG8
B2
RG15
F3
SS2/U6RX/U3CTS/PMA2/CN11/RG9
B3
PMD2/RE2
F4
SDA4/SDI2/U3RX/PMA4/CN9/RG7
B4
PMD1/RE1
F5
VSS
B5
TRD3/RA7
F6
No Connect (NC)
B6
C1RX/PMD11/RF0
F7
No Connect (NC)
B7
VCAP
F8
VDD
B8
PMRD/CN14/RD5
F9
OSC1/CLKI/RC12
B9
OC4/RD3
F10
VSS
B10
VSS
F11
OSC2/CLKO/RC15
B11
SOSCO/T1CK/CN0/RC14
G1
INT1/RE8
C1
PMD6/RE6
G2
INT2/RE9
C2
VDD
G3
TMS/RA0
C3
TRD1/RG12
G4
No Connect (NC)
C4
TRD2/RG14
G5
VDD
C5
TRCLK/RA6
G6
VSS
C6
No Connect (NC)
G7
VSS
C7
PMD15/CN16/RD7
G8
No Connect (NC)
C8
OC5/PMWR/CN13/RD4
G9
TDO/RA5
C9
VDD
G10
SDA2/RA3
C10
SOSCI/CN1/RC13
G11
TDI/RA4
C11
IC4/PMCS1/PMA14/RD11
H1
AN5/C1IN+/VBUSON/CN7/RB5
D1
T2CK/RC1
H2
AN4/C1IN-/CN6/RB4
D2
PMD7/RE7
H3
VSS
D3
PMD5/RE5
H4
VDD
D4
VSS
H5
No Connect (NC)
D5
VSS
H6
VDD
D6
No Connect (NC)
H7
No Connect (NC)
D7
PMD14/CN15/RD6
H8
VBUS
D8
PMD13/CN19/RD13
H9
VUSB3V3
D9
SDO1/OC1/INT0/RD0
H10
D+/RG2
D10
No Connect (NC)
H11
SCL2/RA2
D11
SCK1/IC3/PMCS2/PMA15/RD10
J1
AN3/C2IN+/CN5/RB3
E1
T5CK/SDI1/RC4
J2
AN2/C2IN-/CN4/RB2
Note
1:
Shaded pins are 5V tolerant.
DS60001156K-page 14
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 10:
PIN NAMES (CONTINUED)FOR USB AND CAN DEVICES
121-PIN TFBGA (BOTTOM VIEW)
PIC32MX534F064L
PIC32MX564F064L
PIC32MX564F128L
PIC32MX575F256L
PIC32MX575F512L
Note:
L11
L1
A11
The TFBGA package skips from row “H” to row “J” and has no “I” row. A1
Pin #
Full Pin Name
Pin #
K8
Full Pin Name
J3
PGED2/AN7/RB7
VDD
J4
AVDD
K9
SCK3/U4TX/U1RTS/CN21/RD15
J5
AN11/PMA12/RB11
K10
USBID/RF3
SDA3/SDI3/U1RX/RF2
J6
TCK/RA1
K11
J7
AN12/PMA11/RB12
L1
PGEC2/AN6/OCFA/RB6
J8
No Connect (NC)
L2
VREF-/CVREF-/PMA7/RA9
J9
No Connect (NC)
L3
AVSS
J10
SCL3/SDO3/U1TX/RF8
L4
AN9/C2OUT/RB9
J11
D-/RG3
L5
AN10/CVREFOUT/PMA13/RB10
K1
PGEC1/AN1/CN3/RB1
L6
AC1TX/SCK4/U5TX/U2RTS/RF13
K2
PGED1/AN0/CN2/RB0
L7
AN13/PMA10/RB13
K3
VREF+/CVREF+/PMA6/RA10
L8
AN15/OCFB/PMALL/PMA0/CN12/RB15
K4
AN8/C1OUT/RB8
L9
SS3/U4RX/U1CTS/CN20/RD14
K5
No Connect (NC)
L10
SDA5/SDI4/U2RX/PMA9/CN17/RF4
K6
AC1RX/SS4/U5RX/U2CTS/RF12
L11
SCL5/SDO4/U2TX/PMA8/CN18/RF5
K7
AN14/PMALH/PMA1/RB14
Note
1:
Shaded pins are 5V tolerant.
2009-2019 Microchip Technology Inc.
DS60001156K-page 15
PIC32MX5XX/6XX/7XX
TABLE 11:
PIN NAMES FOR USB AND ETHERNET DEVICES
121-PIN TFBGA (BOTTOM VIEW)
L11
PIC32MX664F064L
PIC32MX664F128L
PIC32MX675F256L
PIC32MX675F512L
PIC32MX695F512L
Note:
L1
A11
The TFBGA package skips from row “H” to row “J” and has no “I” row.
Pin #
Full Pin Name
A1
Pin #
Full Pin Name
PMD4/RE4
E2
A2
PMD3/RE3
E3
ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6
A3
TRD0/RG13
E4
T3CK/RC2
A4
PMD0/RE0
E5
VDD
A5
PMD8/RG0
E6
ETXERR/PMD9/RG1
A6
ETXD0/PMD10/RF1
E7
VSS
A7
VDD
E8
AETXEN/SDA1/INT4/RA15
A8
VSS
E9
RTCC/EMDIO/AEMDIO/IC1/RD8
A1
T4CK/RC3
A9
ETXD2/IC5/PMD12/RD12
E10
SS1/IC2/RD9
A10
OC3/RD2
E11
AETXCLK/SCL1/INT3/RA14
A11
OC2/RD1
F1
MCLR
B1
No Connect (NC)
F2
ERXDV/AERXDV/ECRSDV/AECRSDV//SCL4/SDO2/U3TX/PMA3/CN10/RG8
B2
AERXERR/RG15
F3
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9
B3
PMD2/RE2
F4
ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
B4
PMD1/RE1
F5
VSS
B5
TRD3/RA7
F6
No Connect (NC)
B6
ETXD1/PMD11/RF0
F7
No Connect (NC)
B7
VCAP
F8
VDD
B8
PMRD/CN14/RD5
F9
OSC1/CLKI/RC12
B9
OC4/RD3
F10
VSS
B10
VSS
F11
OSC2/CLKO/RC15
B11
SOSCO/T1CK/CN0/RC14
G1
AERXD0/INT1/RE8
C1
PMD6/RE6
G2
AERXD1/INT2/RE9
C2
VDD
G3
TMS/RA0
C3
TRD1/RG12
G4
No Connect (NC)
C4
TRD2/RG14
G5
VDD
C5
TRCLK/RA6
G6
VSS
C6
No Connect (NC)
G7
VSS
C7
ETXCLK/PMD15/CN16/RD7
G8
No Connect (NC)
C8
OC5/PMWR/CN13/RD4
G9
TDO/RA5
C9
VDD
G10
SDA2/RA3
C10
SOSCI/CN1/RC13
G11
TDI/RA4
C11
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
H1
AN5/C1IN+/VBUSON/CN7/RB5
D1
T2CK/RC1
H2
AN4/C1IN-/CN6/RB4
D2
PMD7/RE7
H3
VSS
D3
PMD5/RE5
H4
VDD
D4
VSS
H5
No Connect (NC)
VDD
D5
VSS
H6
D6
No Connect (NC)
H7
No Connect (NC)
D7
ETXEN/PMD14/CN15/RD6
H8
VBUS
D8
ETXD3/PMD13/CN19/RD13
H9
VUSB3V3
D9
SDO1/OC1/INT0/RD0
H10
D+/RG2
D10
No Connect (NC)
H11
SCL2/RA2
D11
SCK1/IC3/PMCS2/PMA15/RD10
J1
AN3/C2IN+/CN5/RB3
E1
T5CK/SDI1/RC4
J2
AN2/C2IN-/CN4/RB2
Note
1:
Shaded pins are 5V tolerant.
DS60001156K-page 16
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 11:
PIN NAMES FOR USB AND ETHERNET DEVICES (CONTINUED)
121-PIN TFBGA (BOTTOM VIEW)
L11
PIC32MX664F064L
PIC32MX664F128L
PIC32MX675F256L
PIC32MX675F512L
PIC32MX695F512L
Note:
L1
A11
The TFBGA package skips from row “H” to row “J” and has no “I” row.
Pin #
Full Pin Name
Pin #
K8
A1
Full Pin Name
J3
PGED2/AN7/RB7
VDD
J4
AVDD
K9
AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
J5
AN11/ERXERR/AETXERR/PMA12/RB11
K10
USBID/RF3
J6
TCK/RA1
K11
SDA3/SDI3/U1RX/RF2
J7
AN12/ERXD0/AECRS/PMA11/RB12
L1
PGEC2/AN6/OCFA/RB6
J8
No Connect (NC)
L2
VREF-/CVREF-/AERXD2/PMA7/RA9
J9
No Connect (NC)
L3
AVSS
J10
SCL3/SDO3/U1TX/RF8
L4
AN9/C2OUT/RB9
J11
D-/RG3
L5
AN10/CVREFOUT/PMA13/RB10
K1
PGEC1/AN1/CN3/RB1
L6
SCK4/U5TX/U2RTS/RF13
K2
PGED1/AN0/CN2/RB0
L7
AN13/ERXD1/AECOL/PMA10/RB13
K3
VREF+/CVREF+/AERXD3/PMA6/RA10
L8
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
K4
AN8/C1OUT/RB8
L9
AETXD0/SS3/U4RX/U1CTS/CN20/RD14
K5
No Connect (NC)
L10
SDA5/SDI4/U2RX/PMA9/CN17/RF4
K6
SS4/U5RX/U2CTS/RF12
L11
SCL5/SDO4/U2TX/PMA8/CN18/RF5
K7
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
Note
1:
Shaded pins are 5V tolerant.
2009-2019 Microchip Technology Inc.
DS60001156K-page 17
PIC32MX5XX/6XX/7XX
TABLE 12:
PIN NAMES FOR USB, ETHERNET, AND CAN DEVICES
121-PIN TFBGA (BOTTOM VIEW)
L11
L1
PIC32MX764F128L
PIC32MX775F256L
PIC32MX775F512L
PIC32MX795F512L
Note:
A11
The TFBGA package skips from row “H” to row “J” and has no “I” row.
Pin #
Full Pin Name
A1
Pin #
Full Pin Name
(1)
A1
PMD4/RE4
E2
T4CK/AC2RX /RC3
A2
PMD3/RE3
E3
ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6
A3
TRD0/RG13
E4
T3CK/AC2TX(1)/RC2
A4
PMD0/RE0
E5
VDD
A5
C2RX(1)/PMD8/RG0
E6
C2TX(1)/ETXERR/PMD9/RG1
A6
C1TX/ETXD0/PMD10/RF1
E7
VSS
A7
VDD
E8
AETXEN/SDA1/INT4/RA15
A8
VSS
E9
RTCC/EMDIO/AEMDIO/IC1/RD8
A9
ETXD2/IC5/PMD12/RD12
E10
SS1/IC2/RD9
A10
OC3/RD2
E11
AETXCLK/SCL1/INT3/RA14
A11
OC2/RD1
F1
MCLR
B1
No Connect (NC)
F2
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8
B2
AERXERR/RG15
F3
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9
B3
PMD2/RE2
F4
ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
B4
PMD1/RE1
F5
VSS
B5
TRD3/RA7
F6
No Connect (NC)
B6
C1RX/ETXD1/PMD11/RF0
F7
No Connect (NC)
B7
VCAP
F8
VDD
B8
PMRD/CN14/RD5
F9
OSC1/CLKI/RC12
B9
OC4/RD3
F10
VSS
B10
VSS
F11
OSC2/CLKO/RC15
B11
SOSCO/T1CK/CN0/RC14
G1
AERXD0/INT1/RE8
C1
PMD6/RE6
G2
AERXD1/INT2/RE9
C2
VDD
G3
TMS/RA0
C3
TRD1/RG12
G4
No Connect (NC)
C4
TRD2/RG14
G5
VDD
C5
TRCLK/RA6
G6
VSS
C6
No Connect (NC)
G7
VSS
C7
ETXCLK/PMD15/CN16/RD7
G8
No Connect (NC)
C8
OC5/PMWR/CN13/RD4
G9
TDO/RA5
C9
VDD
G10
SDA2/RA3
C10
SOSCI/CN1/RC13
G11
TDI/RA4
C11
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
H1
AN5/C1IN+/VBUSON/CN7/RB5
D1
T2CK/RC1
H2
AN4/C1IN-/CN6/RB4
D2
PMD7/RE7
H3
VSS
D3
PMD5/RE5
H4
VDD
D4
VSS
H5
No Connect (NC)
D5
VSS
H6
VDD
D6
No Connect (NC)
H7
No Connect (NC)
D7
ETXEN/PMD14/CN15/RD6
H8
VBUS
D8
ETXD3/PMD13/CN19/RD13
H9
VUSB3V3
D9
SDO1/OC1/INT0/RD0
H10
D+/RG2
D10
No Connect (NC)
H11
SCL2/RA2
D11
SCK1/IC3/PMCS2/PMA15/RD10
J1
AN3/C2IN+/CN5/RB3
E1
T5CK/SDI1/RC4
J2
AN2/C2IN-/CN4/RB2
Note
1:
2:
This pin is not available on PIC32MX764F128L devices.
Shaded pins are 5V tolerant.
DS60001156K-page 18
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 12:
PIN NAMES FOR USB, ETHERNET, AND CAN DEVICES (CONTINUED)
121-PIN TFBGA (BOTTOM VIEW)
L11
L1
PIC32MX764F128L
PIC32MX775F256L
PIC32MX775F512L
PIC32MX795F512L
Note:
A11
The TFBGA package skips from row “H” to row “J” and has no “I” row.
Pin #
Full Pin Name
A1
Pin #
K8
Full Pin Name
J3
PGED2/AN7/RB7
VDD
J4
AVDD
K9
AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
J5
AN11/ERXERR/AETXERR/PMA12/RB11
K10
USBID/RF3
J6
TCK/RA1
K11
SDA3/SDI3/U1RX/RF2
J7
AN12/ERXD0/AECRS/PMA11/RB12
L1
PGEC2/AN6/OCFA/RB6
J8
No Connect (NC)
L2
VREF-/CVREF-/AERXD2/PMA7/RA9
J9
No Connect (NC)
L3
AVSS
J10
SCL3/SDO3/U1TX/RF8
L4
AN9/C2OUT/RB9
J11
D-/RG3
L5
AN10/CVREFOUT/PMA13/RB10
K1
PGEC1/AN1/CN3/RB1
L6
AC1TX/SCK4/U5TX/U2RTS/RF13
K2
PGED1/AN0/CN2/RB0
L7
AN13/ERXD1/AECOL/PMA10/RB13
K3
VREF+/CVREF+/AERXD3/PMA6/RA10
L8
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
AETXD0/SS3/U4RX/U1CTS/CN20/RD14
K4
AN8/C1OUT/RB8
L9
K5
No Connect (NC)
L10
SDA5/SDI4/U2RX/PMA9/CN17/RF4
K6
AC1RX/SS4/U5RX/U2CTS/RF12
L11
SCL5/SDO4/U2TX/PMA8/CN18/RF5
K7
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
Note
1:
2:
This pin is not available on PIC32MX764F128L devices.
Shaded pins are 5V tolerant.
2009-2019 Microchip Technology Inc.
DS60001156K-page 19
PIC32MX5XX/6XX/7XX
TABLE 13:
PIN NAMES FOR 124-PIN USB, ETHERNET, AND CAN DEVICES
124-PIN VTLA (BOTTOM VIEW)(2,3)
A34
A17
B13
PIC32MX675F512L
PIC32MX695F512L
PIC32MX795F512L
B1
B29
Conductive
Thermal Pad
B41
B56
A51
A1
Polarity Indicator
Package
Bump #
Full Pin Name
A68
Package
Bump #
Full Pin Name
A1
No Connect (NC)
A38
A2
AERXERR/RG15
A39
SCL2/RA2
A3
VSS
A40
TDI/RA4
A4
PMD6/RE6
A41
VDD
A5
T2CK/RC1
A42
OSC2/CLKO/RC15
A6
T4CK/AC2RX(1)/RC3
A43
VSS
A7
ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6
A44
AETXEN/SDA1/INT4/RA15
A8
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8
A45
SS1/IC2/RD9
A9
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9
A46
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
A10
VDD
A47
SOSCI/CN1/RC13
A11
AERXD0/INT1/RE8
A48
VDD
A12
AN5/C1IN+/VBUSON/CN7/RB5
A49
No Connect (NC)
A13
AN3/C2IN+/CN5/RB3
A50
No Connect (NC)
A14
VDD
A51
No Connect (NC)
A15
PGEC1/AN1/CN3/RB1
A52
OC2/RD1
A16
No Connect (NC)
A53
OC4/RD3
A17
No Connect (NC)
A54
ETXD3/PMD13/CN19/RD13
A18
No Connect (NC)
A55
PMRD/CN14/RD5
A19
No Connect (NC)
A56
ETXCLK/PMD15/CN16/RD7
A20
PGEC2/AN6/OCFA/RB6
A57
No Connect (NC)
A21
VREF-/CVREF-/AERXD2/PMA7/RA9
A58
No Connect (NC)
A22
AVDD
A59
VDD
A23
AN8/C1OUT/RB8
A60
C1TX/ETXD0/PMD10/RF1
A24
AN10/CVREFOUT/PMA13/RB10
A61
C2RX(1)/PMD8/RG0
TRD3/RA7
D-/RG3
A25
VSS
A62
A26
TCK/RA1
A63
VSS
A27
AC1RX(1)/SS4/U5RX/U2CTS/RF12
A64
PMD1/RE1
A28
AN13/ERXD1/AECOL/PMA10/RB13
A65
TRD1/RG12
A29
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
A66
PMD2/RE2
A30
VDD
A67
PMD4/RE4
A31
AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
A68
No Connect (NC)
A32
SCL5/SDO4/U2TX/PMA8/CN18/RF5
B1
VDD
A33
No Connect (NC)
B2
PMD5/RE5
A34
No Connect (NC)
B3
PMD7/RE7
A35
USBID/RF3
B4
T3CK/AC2TX(1)/RC2
A36
SDA3/SDI3/U1RX/RF2
B5
T5CK/SDI1/RC4
A37
VBUS
B6
ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
MCLR
B32
SDA2/RA3
B7
Note
1:
2:
3:
This pin is only available on PIC32MX795F512L devices.
Shaded package bumps are 5V tolerant.
It is recommended that the user connect the printed circuit board (PCB) ground to the conductive thermal pad on the bottom of the
package. And to not run non-Vss PCB traces under the conductive thermal pad on the same side of the PCB layout.
DS60001156K-page 20
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 13:
PIN NAMES FOR 124-PIN USB, ETHERNET, AND CAN DEVICES (CONTINUED)
124-PIN VTLA (BOTTOM VIEW)(2,3)
A34
A17
B13
PIC32MX675F512L
PIC32MX695F512L
PIC32MX795F512L
B1
B29
Conductive
Thermal Pad
B41
B56
A51
A1
Polarity Indicator
Package
Bump #
Full Pin Name
A68
Package
Bump #
Full Pin Name
B8
VSS
B33
TDO/RA5
B9
TMS/RA0
B34
OSC1/CLKI/RC12
B10
AERXD1/INT2/RE9
B35
No Connect (NC)
B11
AN4/C1IN-/CN6/RB4
B36
AETXCLK/SCL1/INT3/RA14
B12
VSS
B37
RTCC/EMDIO/AEMDIO/IC1/RD8
B13
AN2/C2IN-/CN4/RB2
B38
SCK1/IC3/PMCS2/PMA15/RD10
B14
PGED1/AN0/CN2/RB0
B39
SDO1/OC1/INT0/RD0
B15
No Connect (NC)
B40
SOSCO/T1CK/CN0/RC14
B16
PGED2/AN7/RB7
B41
VSS
B17
VREF+/CVREF+/AERXD3/PMA6/RA10
B42
OC3/RD2
B18
AVSS
B43
ETXD2/IC5/PMD12/RD12
B19
AN9/C2OUT/RB9
B44
OC5/PMWR/CN13/RD4
B20
AN11/ERXERR/AETXERR/PMA12/RB11
B45
ETXEN/PMD14/CN15/RD6
B21
VDD
B46
VSS
B22
AC1TX/SCK4/U5TX/U2RTS/RF13
B47
No Connect (NC)
B23
AN12/ERXD0/AECRS/PMA11/RB12
B48
VCAP
B24
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
B49
C1RX(1)/ETXD1/PMD11/RF0
B25
VSS
B50
C2TX(1)/ETXERR/PMD9/RG1
B26
AETXD0/SS3/U4RX/U1CTS/CN20/RD14
B51
TRCLK/RA6
B27
SDA5/SDI4/U2RX/PMA9/CN17/RF4
B52
PMD0/RE0
B28
No Connect (NC)
B53
VDD
B29
SCL3/SDO3/U1TX/RF8
B54
TRD2/RG14
B30
VUSB3V3
B55
TRD0/RG13
B31
D+/RG2
B56
PMD3/RE3
Note
1:
2:
3:
This pin is only available on PIC32MX795F512L devices.
Shaded package bumps are 5V tolerant.
It is recommended that the user connect the printed circuit board (PCB) ground to the conductive thermal pad on the bottom of the
package. And to not run non-Vss PCB traces under the conductive thermal pad on the same side of the PCB layout.
2009-2019 Microchip Technology Inc.
DS60001156K-page 21
PIC32MX5XX/6XX/7XX
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 25
2.0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................ 37
3.0 CPU ............................................................................................................................................................................................ 45
4.0 Memory Organization ................................................................................................................................................................. 51
5.0 Flash Program Memory .............................................................................................................................................................. 67
6.0 Resets ........................................................................................................................................................................................ 73
7.0 Interrupt Controller ..................................................................................................................................................................... 77
8.0 Oscillator Configuration .............................................................................................................................................................. 99
9.0 Prefetch Cache......................................................................................................................................................................... 105
10.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 115
11.0 USB On-The-Go (OTG)............................................................................................................................................................ 137
12.0 I/O Ports ................................................................................................................................................................................... 161
13.0 Timer1 ...................................................................................................................................................................................... 171
14.0 Timer2/3, Timer4/5 ................................................................................................................................................................... 175
15.0 Watchdog Timer (WDT) ........................................................................................................................................................... 181
16.0 Input Capture............................................................................................................................................................................ 185
17.0 Output Compare ....................................................................................................................................................................... 189
18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 193
19.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 199
20.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 207
21.0 Parallel Master Port (PMP)....................................................................................................................................................... 215
22.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 225
23.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 235
24.0 Controller Area Network (CAN) ................................................................................................................................................ 245
25.0 Ethernet Controller ................................................................................................................................................................... 283
26.0 Comparator .............................................................................................................................................................................. 327
27.0 Comparator Voltage Reference (CVREF).................................................................................................................................. 331
28.0 Power-Saving Features ........................................................................................................................................................... 335
29.0 Special Features ...................................................................................................................................................................... 337
30.0 Instruction Set .......................................................................................................................................................................... 349
31.0 Development Support............................................................................................................................................................... 351
32.0 Electrical Characteristics .......................................................................................................................................................... 355
33.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 403
34.0 Packaging Information.............................................................................................................................................................. 405
The Microchip Web Site ..................................................................................................................................................................... 443
Customer Change Notification Service .............................................................................................................................................. 443
Customer Support .............................................................................................................................................................................. 443
Product Identification System............................................................................................................................................................. 444
DS60001156K-page 22
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of
your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications
Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data
sheet to (480) 792-4150. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner
of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of
document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may
exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The
errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature
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Register on our web site at www.microchip.com to receive the most current information on all of our products.
2009-2019 Microchip Technology Inc.
DS60001156K-page 23
PIC32MX5XX/6XX/7XX
Referenced Sources
This device data sheet is based on the following
individual chapters of the “PIC32 Family Reference
Manual”. These documents should be considered as
the general reference for the operation of a particular
module or device feature.
Note 1: To access the documents listed below,
browse to the documentation section of
the PIC32MX795F512L product page on
the
Microchip
web
site
(www.microchip.com) or select a family
reference manual section from the
following list.
In addition to parameters, features, and
other documentation, the resulting page
provides links to the related family
reference manual sections.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Section 1. “Introduction” (DS60001127)
Section 2. “CPU” (DS60001113)
Section 4. “Prefetch Cache” (DS60001119)
Section 3. “Memory Organization” (DS60001115)
Section 5. “Flash Program Memory” (DS60001121)
Section 6. “Oscillator Configuration” (DS60001112)
Section 7. “Resets” (DS60001118)
Section 8. “Interrupt Controller” (DS60001108)
Section 9. “Watchdog Timer and Power-up Timer (DS60001114)
Section 10. “Power-Saving Features” (DS60001130)
Section 12. “I/O Ports” (DS60001120)
Section 13. “Parallel Master Port (PMP)” (DS60001128)
Section 14. “Timers” (DS60001105)
Section 15. “Input Capture” (DS60001122)
Section 16. “Output Capture” (DS60001111)
Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS60001104)
Section 19. “Comparator” (DS60001110)
Section 20. “Comparator Voltage Reference (CVREF)” (DS60001109)
Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107)
Section 23. “Serial Peripheral Interface (SPI)” (DS60001106)
Section 24. “Inter-Integrated Circuit (I2C)” (DS60001116)
Section 27. “USB On-The-Go (OTG)” (DS60001126)
Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125)
Section 31. “Direct Memory Access (DMA) Controller” (DS60001117)
Section 32. “Configuration” (DS60001124)
Section 33. “Programming and Diagnostics” (DS60001129)
Section 34. “Controller Area Network (CAN)” (DS60001154)
Section 35. “Ethernet Controller” (DS60001155)
DS60001156K-page 24
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
1.0
Note:
DEVICE OVERVIEW
This document contains device-specific information for
PIC32MX5XX/6XX/7XX devices.
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the documents listed in the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
Figure 1-1 illustrates a general block diagram of the
core and peripheral modules in the PIC32MX5XX/6XX/
7XX family of devices.
Table 1-1 lists the functions of the various pins shown
in the pinout diagrams.
BLOCK DIAGRAM(1,2)
FIGURE 1-1:
OSC2/CLKO
OSC1/CLKI
VCAP
OSC/SOSC
Oscillators
Power-up
Timer
FRC/LPRC
Oscillators
Voltage
Regulator
PLL
Oscillator
Start-up Timer
PLL-USB
Watchdog
Timer
USBCLK
SYSCLK
PBCLK
Timing
Generation
Brown-out
Reset
Peripheral Bus Clocked by SYSCLK
CN1-22
PORTA
PORTC
IS
32
DS
32
32
32
32
32
32
32
32
PORTD
Bus Matrix
32
32
IC1-5
SPI1-4
I2C1-5
32
PORTE
Prefetch
Module
PWM
OC1-5
Peripheral Bus Clocked by PBCLK
USB
MIPS32® M4K®
CPU Core
ICD
INT
PORTB
DMAC
EJTAG
Timer1-5
ETHERNET
Priority
Interrupt
Controller
CAN1, CAN2
JTAG
BSCAN
MCLR
Power-on
Reset
Precision
Band Gap
Reference
Dividers
VDD, VSS
32
Data RAM
Peripheral Bridge
PMP
10-bit ADC
PORTF
PORTG
128-bit Wide
Program Flash Memory
Flash
Controller
128
UART1-6
RTCC
Comparators
Note
1:
2:
Some features are not available on all devices.
BOR functionality is provided when the on-board voltage regulator is enabled.
2009-2019 Microchip Technology Inc.
DS60001156K-page 25
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin Number(1)
Pin Name
Pin
Type
Buffer
Type
Description
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
TFBGA
124-pin
VTLA
AN0
16
25
K2
B14
I
Analog Analog input channels
AN1
AN2
15
14
24
23
K1
J2
A15
B13
I
I
Analog
Analog
AN3
AN4
13
12
22
21
J1
H2
A13
B11
I
I
Analog
Analog
AN5
AN6
11
17
20
26
H1
L1
A12
A20
I
I
Analog
Analog
AN7
AN8
18
21
27
32
J3
K4
B16
A23
I
I
Analog
Analog
AN9
AN10
22
23
33
34
L4
L5
B19
A24
I
I
Analog
Analog
AN11
AN12
24
27
35
41
J5
J7
B20
B23
I
I
Analog
Analog
AN13
AN14
28
29
42
43
L7
K7
A28
B24
I
I
Analog
Analog
AN15
30
44
L8
A29
I
CLKI
39
63
F9
B34
I
Analog
ST/ External clock source input. Always
CMOS associated with OSC1 pin function.
CLKO
40
64
F11
A42
O
OSC1
39
63
F9
B34
I
OSC2
40
64
F11
A42
I/O
SOSCI
47
73
C10
A47
I
SOSCO
48
74
B11
B40
O
—
Oscillator crystal output. Connects to
crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in
RC and EC modes. Always associated
with OSC2 pin function.
Oscillator crystal input. ST buffer when
ST/
configured in RC mode; CMOS
CMOS
otherwise.
Oscillator crystal output. Connects to
crystal or resonator in Crystal Oscillator
—
mode. Optionally functions as CLKO in
RC and EC modes.
ST/ 32.768 kHz low-power oscillator crystal
CMOS input; CMOS otherwise
32.768 kHz low-power oscillator crystal
—
output
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
DS60001156K-page 26
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
B40
I
ST
C10
K2
A47
B14
I
I
ST
ST
24
23
K1
J2
A15
B13
I
I
ST
ST
13
12
22
21
J1
H2
A13
B11
I
I
ST
ST
CN7
CN8
11
4
20
10
H1
E3
A12
A7
I
I
ST
ST
CN9
CN10
5
6
11
12
F4
F2
B6
A8
I
I
ST
ST
CN11
CN12
8
30
14
44
F3
L8
A9
A29
I
I
ST
ST
CN13
CN14
52
53
81
82
C8
B8
B44
A55
I
I
ST
ST
CN15
CN16
54
55
83
84
D7
C7
B45
A56
I
I
ST
ST
CN17
CN18
31
32
49
50
L10
L11
B27
A32
I
I
ST
ST
CN19
CN20
—
—
80
47
D8
L9
A54
B26
I
I
ST
ST
CN21
IC1
—
42
48
68
K9
E9
A31
B37
I
I
ST
ST
IC2
IC3
43
44
69
70
E10
D11
A45
B38
I
I
ST
ST
IC4
IC5
45
52
71
79
C11
A9
A46
A60
I
I
ST
ST
OCFA
OC1
17
46
26
72
L1
D9
A20
B39
I
O
ST
—
Output Compare Fault A Input
Output Compare Output 1
OC2
OC3
49
50
76
77
A11
A10
A52
B42
O
O
—
—
Output Compare Output 2
Output Compare Output 3
OC4
OC5
51
52
78
81
B9
C8
A53
B44
O
O
—
—
Output Compare Output 4
Output Compare Output 5
OCFB
INT0
30
46
44
72
L8
D9
A29
B39
I
I
ST
ST
Output Compare Fault B Input
External Interrupt 0
INT1
INT2
42
43
18
19
G1
G2
A11
B10
I
I
ST
ST
External Interrupt 1
External Interrupt 2
INT3
INT4
44
45
66
67
E11
E8
B36
A44
I
I
ST
ST
External Interrupt 3
External Interrupt 4
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
TFBGA
124-pin
VTLA
CN0
48
74
B11
CN1
CN2
47
16
73
25
CN3
CN4
15
14
CN5
CN6
Description
Change notification inputs. Can be
software programmed for internal weak
pull-ups on all inputs.
Capture Inputs 1-5
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
2009-2019 Microchip Technology Inc.
DS60001156K-page 27
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
B9
I/O
ST
J6
H11
A26
A39
I/O
I/O
ST
ST
59
60
G10
G11
B32
A40
I/O
I/O
ST
ST
—
—
61
91
G9
C5
B33
B51
I/O
I/O
ST
ST
RA7
RA9
—
—
92
28
B5
L2
A62
A21
I/O
I/O
ST
ST
RA10
RA14
—
—
29
66
K3
E11
B17
B36
I/O
I/O
ST
ST
RA15
RB0
—
16
67
25
E8
K2
A44
B14
I/O
I/O
ST
ST
RB1
RB2
15
14
24
23
K1
J2
A15
B13
I/O
I/O
ST
ST
RB3
RB4
13
12
22
21
J1
H2
A13
B11
I/O
I/O
ST
ST
RB5
RB6
11
17
20
26
H1
L1
A12
A20
I/O
I/O
ST
ST
RB7
RB8
18
21
27
32
J3
K4
B16
A23
I/O
I/O
ST
ST
RB9
RB10
22
23
33
34
L4
L5
B19
A24
I/O
I/O
ST
ST
RB11
RB12
24
27
35
41
J5
J7
B20
B23
I/O
I/O
ST
ST
RB13
RB14
28
29
42
43
L7
K7
A28
B24
I/O
I/O
ST
ST
RB15
RC1
30
—
44
6
L8
D1
A29
A5
I/O
I/O
ST
ST
RC2
RC3
—
—
7
8
E4
E2
B4
A6
I/O
I/O
ST
ST
RC4
RC12
—
39
9
63
E1
F9
B5
B34
I/O
I/O
ST
ST
RC13
RC14
47
48
73
74
C10
B11
A47
B40
I/O
I/O
ST
ST
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
TFBGA
124-pin
VTLA
RA0
—
17
G3
RA1
RA2
—
—
38
58
RA3
RA4
—
—
RA5
RA6
Description
PORTA is a bidirectional I/O port
PORTB is a bidirectional I/O port
PORTC is a bidirectional I/O port
RC15
40
64
F11
A42
I/O
ST
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
DS60001156K-page 28
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
B39
I/O
ST
A11
A10
A52
B42
I/O
I/O
ST
ST
78
81
B9
C8
A53
B44
I/O
I/O
ST
ST
53
54
82
83
B8
D7
A55
B45
I/O
I/O
ST
ST
RD7
RD8
55
42
84
68
C7
E9
A56
B37
I/O
I/O
ST
ST
RD9
RD10
43
44
69
70
E10
D11
A45
B38
I/O
I/O
ST
ST
RD11
RD12
45
—
71
79
C11
A9
A46
B43
I/O
I/O
ST
ST
RD13
RD14
—
—
80
47
D8
L9
A54
B26
I/O
I/O
ST
ST
RD15
RE0
—
60
48
93
K9
A4
A31
B52
I/O
I/O
ST
ST
RE1
RE2
61
62
94
98
B4
B3
A64
A66
I/O
I/O
ST
ST
RE3
RE4
63
64
99
100
A2
A1
B56
A67
I/O
I/O
ST
ST
RE5
RE6
1
2
3
4
D3
C1
B2
A4
I/O
I/O
ST
ST
RE7
RE8
3
—
5
18
D2
G1
B3
A11
I/O
I/O
ST
ST
RE9
RF0
—
58
19
87
G2
B6
B10
B49
I/O
I/O
ST
ST
RF1
RF2
59
—
88
52
A6
K11
A60
A36
I/O
I/O
ST
ST
RF3
RF4
33
31
51
49
K10
L10
A35
B27
I/O
I/O
ST
ST
RF5
RF8
32
—
50
53
L11
J10
A32
B29
I/O
I/O
ST
ST
RF12
RF13
—
—
40
39
K6
L6
A27
B22
I/O
I/O
ST
ST
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
TFBGA
124-pin
VTLA
RD0
46
72
D9
RD1
RD2
49
50
76
77
RD3
RD4
51
52
RD5
RD6
Description
PORTD is a bidirectional I/O port
PORTE is a bidirectional I/O port
PORTF is a bidirectional I/O port
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
2009-2019 Microchip Technology Inc.
DS60001156K-page 29
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
A61
I/O
ST
E6
E3
B50
A7
I/O
I/O
ST
ST
11
12
F4
F2
B6
A8
I/O
I/O
ST
ST
8
—
14
96
F3
C3
A9
A65
I/O
I/O
ST
ST
RG13
RG14
—
—
97
95
A3
C4
B55
B54
I/O
I/O
ST
ST
RG15
RG2
—
37
1
57
B2
H10
A2
B31
I/O
I
ST
ST
RG3
T1CK
36
48
56
74
J11
B11
A38
B40
I
I
ST
ST
Timer1 external clock input
T2CK
T3CK
—
—
6
7
D1
E4
A5
B4
I
I
ST
ST
Timer2 external clock input
Timer3 external clock input
T4CK
T5CK
—
—
8
9
E2
E1
A6
B5
I
I
ST
ST
Timer4 external clock input
Timer5 external clock input
U1CTS
43
47
L9
B26
I
ST
UART1 clear to send
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
TFBGA
124-pin
VTLA
RG0
—
90
A5
RG1
RG6
—
4
89
10
RG7
RG8
5
6
RG9
RG12
Description
PORTG is a bidirectional I/O port
PORTG input pins
U1RTS
49
48
K9
A31
O
—
UART1 ready to send
U1RX
50
52
K11
A36
I
ST
UART1 receive
U1TX
51
53
J10
B29
O
—
UART1 transmit
U3CTS
8
14
F3
A9
I
ST
UART3 clear to send
U3RTS
4
10
E3
A7
O
—
UART3 ready to send
U3RX
5
11
F4
B6
I
ST
UART3 receive
U3TX
6
12
F2
A8
O
—
UART3 transmit
U2CTS
21
40
K6
A27
I
ST
UART2 clear to send
U2RTS
29
39
L6
B22
O
—
UART2 ready to send
U2RX
31
49
L10
B27
I
ST
UART2 receive
U2TX
32
50
L11
A32
O
—
UART2 transmit
U4RX
43
47
L9
B26
I
ST
UART4 receive
U4TX
49
48
K9
A31
O
—
UART4 transmit
U6RX
8
14
F3
A9
I
ST
UART6 receive
U6TX
4
10
E3
A7
O
—
UART6 transmit
UART5 receive
U5RX
21
40
K6
A27
I
ST
U5TX
29
39
L6
B22
O
—
SCK1
—
70
D11
B38
UART5 transmit
Synchronous serial clock input/output
I/O
ST
for SPI1
Analog = Analog input
P = Power
O = Output
I = Input
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
DS60001156K-page 30
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
Pin
Type
Buffer
Type
B5
I
ST
B39
O
—
SPI1 data out
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
TFBGA
124-pin
VTLA
SDI1
—
9
E1
SDO1
—
72
D9
Description
SPI1 data in
SS1
—
69
E10
A45
I/O
ST
SPI1 slave synchronization or frame
pulse I/O
SCK3
49
48
K9
A31
I/O
ST
Synchronous serial clock input/output
for SPI3
SDI3
SDO3
50
51
52
53
K11
J10
A36
B29
I
O
ST
—
SPI3 data in
SPI3 data out
SS3
43
47
L9
B26
I/O
ST
SCK2
4
10
E3
A7
I/O
ST
SDI2
5
11
F4
B6
I
ST
SPI3 slave synchronization or frame
pulse I/O
Synchronous serial clock input/output
for SPI2
SPI2 data in
SDO2
6
12
F2
A8
O
—
SPI2 data out
SS2
8
14
F3
A9
I/O
ST
SPI2 slave synchronization or frame
pulse I/O
SCK4
29
39
L6
B22
I/O
ST
SDI4
31
49
L10
B27
I
ST
Synchronous serial clock input/output
for SPI4
SPI4 data in
SDO4
32
50
L11
A32
O
—
SPI4 data out
SS4
21
40
K6
A27
I/O
ST
SPI4 slave synchronization or frame
pulse I/O
SCL1
44
66
E11
B36
I/O
ST
Synchronous serial clock input/output
for I2C1
SDA1
43
67
E8
A44
I/O
ST
SCL3
51
53
J10
B29
I/O
ST
SDA3
50
52
K11
A36
I/O
ST
SCL2
—
58
H11
A39
I/O
ST
SDA2
—
59
G10
B32
I/O
ST
Synchronous serial data input/output
for I2C2
SCL4
6
12
F2
A8
I/O
ST
Synchronous serial clock input/output
for I2C4
SDA4
5
11
F4
B6
SCL5
32
50
L11
A32
SDA5
31
49
L10
B27
Synchronous serial data input/output
for I2C1
Synchronous serial clock input/output
for I2C3
Synchronous serial data input/output
for I2C3
Synchronous serial clock input/output
for I2C2
Synchronous serial data input/output
for I2C4
Synchronous serial clock input/output
I/O
ST
for I2C5
Synchronous serial data input/output
I/O
ST
for I2C5
Analog = Analog input
P = Power
O = Output
I = Input
I/O
ST
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
2009-2019 Microchip Technology Inc.
DS60001156K-page 31
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
B9
A26
I
I
ST
ST
JTAG Test mode select pin
JTAG test clock input pin
A40
B33
I
O
ST
—
JTAG test data input pin
JTAG test data output pin
E9
B37
O
—
Real-Time Clock alarm output
L2
K3
A21
B17
I
I
Analog Comparator Voltage Reference (low)
Analog Comparator Voltage Reference (high)
34
21
L5
H2
A24
B11
O
I
Analog Comparator Voltage Reference output
Analog Comparator 1 negative input
11
21
20
32
H1
K4
A12
A23
I
O
Analog Comparator 1 positive input
—
Comparator 1 output
C2INC2IN+
14
13
23
22
J2
J1
B13
A13
I
I
Analog Comparator 2 negative input
Analog Comparator 2 positive input
C2OUT
22
33
L4
B19
O
PMA0
30
44
L8
A29
I/O
PMA1
29
43
K7
B24
I/O
PMA2
PMA3
8
6
14
12
F3
F2
A9
A8
O
O
—
—
PMA4
PMA5
5
4
11
10
F4
E3
B6
A7
O
O
—
—
PMA6
PMA7
16
22
29
28
K3
L2
B17
A21
O
O
—
—
PMA8
PMA9
32
31
50
49
L11
L10
A32
B27
O
O
—
—
PMA10
PMA11
28
27
42
41
L7
J7
A28
B23
O
O
—
—
PMA12
PMA13
24
23
35
34
J5
L5
B20
A24
O
O
—
—
PMA14
PMA15
45
44
71
70
C11
D11
A46
B38
O
O
—
—
PMCS1
45
71
C11
A46
O
PMCS2
44
70
D11
B38
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
TFBGA
124-pin
VTLA
TMS
TCK
23
27
17
38
G3
J6
TDI
TDO
28
24
60
61
G11
G9
RTCC
42
68
CVREFCVREF+
15
16
28
29
CVREFOUT
C1IN-
23
12
C1IN+
C1OUT
Description
—
Comparator 2 output
Parallel Master Port Address bit 0 input
TTL/ST (Buffered Slave modes) and output
(Master modes)
Parallel Master Port Address bit 1 input
TTL/ST (Buffered Slave modes) and output
(Master modes)
Parallel Master Port address
(Demultiplexed Master modes)
Parallel Master Port Chip Select 1
strobe
Parallel Master Port Chip Select 2
O
—
strobe
Analog = Analog input
P = Power
O = Output
I = Input
—
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
DS60001156K-page 32
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
Pin
Type
Buffer
Type
Description
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
TFBGA
124-pin
VTLA
PMD0
60
93
A4
B52
I/O
PMD1
PMD2
61
62
94
98
B4
B3
A64
A66
I/O
I/O
PMD3
PMD4
63
64
99
100
A2
A1
B56
A67
I/O
I/O
TTL/ST Parallel Master Port data
TTL/ST (Demultiplexed Master mode) or
address/data (Multiplexed Master
TTL/ST
modes)
TTL/ST
TTL/ST
PMD5
PMD6
1
2
3
4
D3
C1
B2
A4
I/O
I/O
TTL/ST
TTL/ST
PMD7
PMD8
3
—
5
90
D2
A5
B3
A61
I/O
I/O
TTL/ST
TTL/ST
PMD9
PMD10
—
—
89
88
E6
A6
B50
A60
I/O
I/O
TTL/ST
TTL/ST
PMD11
PMD12
—
—
87
79
B6
A9
B49
B43
I/O
I/O
TTL/ST
TTL/ST
PMD13
PMD14
—
—
80
83
D8
D7
A54
B45
I/O
I/O
TTL/ST
TTL/ST
PMD15
—
84
C7
A56
I/O
TTL/ST
PMALL
30
44
L8
A29
O
—
Parallel Master Port address latch
enable low byte (Multiplexed Master
modes)
PMALH
29
43
K7
B24
O
—
Parallel Master Port address latch
enable high byte (Multiplexed Master
modes)
PMRD
PMWR
53
52
82
81
B8
C8
A55
B44
O
O
—
—
Parallel Master Port read strobe
Parallel Master Port write strobe
VBUS
34
54
H8
A37
I
VUSB3V3
35
55
H9
B30
P
VBUSON
11
20
H1
A12
O
D+
37
57
H10
B31
I/O
Analog USB bus power monitor
USB internal transceiver supply. If the
—
USB module is not used, this pin must
be connected to VDD.
USB Host and OTG bus power control
—
output
Analog USB D+
DUSBID
36
33
56
51
J11
K10
A38
A35
I/O
I
Analog USB DST
USB OTG ID detect
C1RX
C1TX
58
59
87
88
B6
A6
B49
A60
I
O
ST
—
CAN1 bus receive pin
CAN1 bus transmit pin
AC1RX
AC1TX
32
31
40
39
K6
L6
A27
B22
I
O
ST
—
Alternate CAN1 bus receive pin
Alternate CAN1 bus transmit pin
C2RX
C2TX
29
21
90
89
A5
E6
A61
B50
I
O
ST
—
CAN2 bus receive pin
CAN2 bus transmit pin
AC2RX
—
8
E2
A6
1
ST
Alternate CAN2 bus receive pin
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
2009-2019 Microchip Technology Inc.
DS60001156K-page 33
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
B4
B23
O
I
—
ST
Alternate CAN2 bus transmit pin
Ethernet Receive Data 0(2)
L7
K7
A28
B24
I
I
ST
ST
Ethernet Receive Data 1(2)
Ethernet Receive Data 2(2)
44
L8
A29
I
ST
Ethernet Receive Data 3(2)
64
62
35
12
J5
F2
B20
A8
I
I
ST
ST
Ethernet receive error input(2)
Ethernet receive data valid(2)
ECRSDV
ERXCLK
62
63
12
14
F2
F3
A8
A9
I
I
ST
ST
Ethernet carrier sense data valid(2)
Ethernet receive clock(2)
EREFCLK
ETXD0
63
2
14
88
F3
A6
A9
A60
I
O
ST
—
Ethernet reference clock(2)
Ethernet Transmit Data 0(2)
ETXD1
ETXD2
3
43
87
79
B6
A9
B49
B43
O
O
—
—
Ethernet Transmit Data 1(2)
Ethernet Transmit Data 2(2)
ETXD3
ETXERR
42
54
80
89
D8
E6
A54
B50
O
O
—
—
Ethernet Transmit Data 3(2)
Ethernet transmit error(2)
ETXEN
ETXCLK
1
55
83
84
D7
C7
B45
A56
O
I
—
ST
Ethernet transmit enable(2)
Ethernet transmit clock(2)
ECOL
ECRS
44
45
10
11
E3
F4
A7
B6
I
I
ST
ST
Ethernet collision detect(2)
Ethernet carrier sense(2)
EMDC
EMDIO
30
49
71
68
C11
E9
A46
B37
O
I/O
—
—
Ethernet management data clock(2)
Ethernet management data(2)
AERXD0
AERXD1
43
42
18
19
G1
G2
A11
B10
I
I
ST
ST
Alternate Ethernet Receive Data 0(2)
Alternate Ethernet Receive Data 1(2)
AERXD2
AERXD3
—
—
28
29
L2
K3
A21
B17
I
I
ST
ST
Alternate Ethernet Receive Data 2(2)
Alternate Ethernet Receive Data 3(2)
AERXERR
AERXDV
55
—
1
12
B2
F2
A2
A8
I
I
ST
ST
Alternate Ethernet receive error input(2)
Alternate Ethernet receive data valid(2)
AECRSDV
44
12
F2
A8
I
ST
Alternate Ethernet carrier sense data
valid(2)
AERXCLK
AEREFCLK
—
45
14
14
F3
F3
A9
A9
I
I
ST
ST
Alternate Ethernet receive clock(2)
Alternate Ethernet reference clock(2)
AETXD0
AETXD1
59
58
47
48
L9
K9
B26
A31
O
O
—
—
Alternate Ethernet Transmit Data 0(2)
Alternate Ethernet Transmit Data 1(2)
AETXD2
AETXD3
—
—
44
43
L8
K7
A29
B24
O
O
—
—
Alternate Ethernet Transmit Data 2(2)
Alternate Ethernet Transmit Data 3(2)
AETXERR
AETXEN
—
54
35
67
J5
E8
B20
A44
O
O
—
—
Alternate Ethernet transmit error(2)
Alternate Ethernet transmit enable(2)
AETXCLK
AECOL
—
—
66
42
E11
L7
B36
A28
I
I
ST
ST
Alternate Ethernet transmit clock(2)
Alternate Ethernet collision detect(2)
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
TFBGA
124-pin
VTLA
AC2TX
ERXD0
—
61
7
41
E4
J7
ERXD1
ERXD2
60
59
42
43
ERXD3
58
ERXERR
ERXDV
Description
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
DS60001156K-page 34
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
B23
I
ST
A46
O
—
E9
B37
I/O
—
Alternate Ethernet carrier sense(2)
Alternate Ethernet Management Data
clock(2)
Alternate Ethernet Management Data(2)
C5
B51
O
—
Trace clock
B55
O
O
—
—
Trace Data bits 0-3
A65
C4
B5
B54
A62
O
O
—
—
25
K2
B14
I/O
ST
15
24
K1
A15
I
ST
PGED2
18
27
J3
B16
I/O
ST
PGEC2
17
26
L1
A20
I
ST
MCLR
7
13
F1
B7
I/P
ST
AVDD
19
30
J4
A22
P
P
AVSS
20
31
L3
B18
P
P
A7, C2,
C9, E5,
K8, F8,
G5, H4,
H6
A10, A14,
A30, A41,
A48, A59,
B1, B21,
B53
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
TFBGA
124-pin
VTLA
AECRS
—
41
J7
AEMDC
30
71
C11
AEMDIO
49
68
TRCLK
—
91
TRD0
TRD1
—
—
97
96
A3
C3
TRD2
TRD3
—
—
95
92
PGED1
16
PGEC1
VDD
10, 26, 38, 2, 16, 37,
57
46, 62, 86
VCAP
56
VSS
9, 25, 41
VREF+
VREF-
16
15
85
B7
B48
A8, B10, A3, A25,
D4, D5, A43, A63,
15, 36, 45,
E7, F5, B8, B12,
65, 75
F10, G6, B25, B41,
G7, H3
B46
29
28
K3
L2
B17
A21
Description
Data I/O pin for Programming/
Debugging Communication Channel 1
Clock input pin for Programming/
Debugging Communication Channel 1
Data I/O pin for Programming/
Debugging Communication Channel 2
Clock input pin for Programming/
Debugging Communication Channel 2
Master Clear (Reset) input. This pin is
an active-low Reset to the device.
Positive supply for analog modules.
This pin must be connected at all times.
Ground reference for analog modules
Positive supply for peripheral logic and
I/O pins
P
—
P
—
P
—
I
I
Capacitor for Internal Voltage Regulator
Ground reference for logic and I/O pins.
This pin must be connected at all times.
Analog Analog voltage reference (high) input
Analog Analog voltage reference (low) input
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
2009-2019 Microchip Technology Inc.
DS60001156K-page 35
PIC32MX5XX/6XX/7XX
NOTES:
DS60001156K-page 36
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
2.0
Note:
2.1
GUIDELINES FOR GETTING
STARTED WITH 32-BIT MCUS
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
Basic Connection Requirements
Getting started with the PIC32MX5XX/6XX/7XX family
of 32-bit Microcontrollers (MCUs) requires attention to
a minimal set of device pin connections before proceeding with development. The following is a list of pin
names, which must always be connected:
• All VDD and VSS pins (see 2.2 “Decoupling
Capacitors”)
• All AVDD and AVSS pins even if the ADC module is
not used (see 2.2 “Decoupling Capacitors”)
• VCAP pin (see 2.3 “Capacitor on Internal Voltage
Regulator (VCAP)”)
• MCLR pin (see 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used (see 2.8 “External Oscillator Pins”)
The following pin may be required, as well: VREF+/
VREF- pins used when external voltage reference for
ADC module is implemented.
Note:
The AVDD and AVSS pins must be
connected, regardless of the ADC use
and the ADC voltage reference source.
2009-2019 Microchip Technology Inc.
2.2
Decoupling Capacitors
The use of decoupling capacitors on power supply
pins, such as VDD, VSS, AVDD and AVSS is required.
See Figure 2-1.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A value of 0.1 µF
(100 nF), 10-20V is recommended. The capacitor
should be a low Equivalent Series Resistance
(low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is
further recommended to use ceramic capacitors.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended that
the capacitors be placed on the same side of
the board as the device. If space is constricted,
the capacitor can be placed on another layer on
the PCB using a via; however, ensure that the
trace length from the pin to the capacitor is
within one-quarter inch (6 mm) in length.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track
inductance.
DS60001156K-page 37
PIC32MX5XX/6XX/7XX
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
Tantalum or
ceramic 10 µF
ESR 3(3)
R1
MCLR
C
VSS
VCAP
R
VDD
VDD
0.1 µF
Ceramic
VUSB3V3(1)
PIC32
VDD
VSS
Connect(2)
0.1 µF
Ceramic
0.1 µF
Ceramic
VSS
VDD
AVSS
0.1 µF
Ceramic
AVDD
VDD
VSS
0.1 µF
Ceramic
L1(2)
Note
1:
If the USB module is not used, this pin must be
connected to VDD.
2:
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 3 and the inductor
capacity greater than 10 mA.
2.4
Master Clear (MCLR) Pin
The MCLR
functions:
2.2.1
2.3.1
specific
device
For example, as illustrated in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components illustrated in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
10k
R1(1)
MCLR
Aluminum or electrolytic capacitors should not be
used. ESR 3 from -40ºC to 125ºC @ SYSCLK
frequency (i.e., MIPS).
0.1 µF(2)
ICSP™
(i.e., ADC conversion rate/2)
Note
1
5
4
2
3
6
Capacitor on Internal Voltage
Regulator (VCAP)
VDD
VSS
NC
C
1 k
PIC32
PGECx(3)
PGEDx(3)
1:
470 R1 1k will limit any current flowing into
MCLR from the external capacitor C, in the event of
MCLR pin breakdown, due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS). Ensure that the
MCLR pin VIH and VIL specifications are met without
interfering with the Debug/Programmer tools.
2:
The capacitor can be sized to prevent unintentional
Resets from brief glitches or to extend the device
Reset period during POR.
3:
No pull-ups or bypass capacitors are allowed on
active debug/program PGECx/PGEDx pins.
BULK CAPACITORS
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.
2.3
two
Pulling The MCLR pin low generates a device Reset.
Figure 2-2 illustrates a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
R
1 - 2
L = -------------------- 2f C
3:
provides
• Device Reset
• Device Programming and Debugging
Where:
F CNV
f = -------------2
1
f = ---------------------- 2 LC
pin
INTERNAL REGULATOR MODE
A low-ESR (1 ohm) capacitor is required on the VCAP
pin, which is used to stabilize the internal voltage regulator output. The VCAP pin must not be connected to
VDD, and must have a CEFC capacitor, with at least a
6V rating, connected to ground. The type can be
ceramic or tantalum. Refer to Section 32.0 “Electrical
Characteristics” for additional information on CEFC
specifications.
DS60001156K-page 38
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
2.5
ICSP Pins
2.7
Trace
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging. It is
recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is
recommended, with the value in the range of a few tens
of Ohms, not to exceed 100 Ohms.
The trace pins can be connected to a hardware-traceenabled programmer to provide a compress real time
instruction trace. When used for trace the TRD3,
TRD2, TRD1, TRD0 and TRCLK pins should be
dedicated for this use. The trace hardware requires
a 22 series resistor between the trace pins and the
trace connector.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
2.8
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 3 or MPLAB® REAL ICE™.
For more information on ICD 3 and REAL ICE connection requirements, refer to the following documents that
are available on the Microchip web site.
• “Using MPLAB® ICD 3” (poster) (DS50001765)
• “MPLAB® ICD 3 Design Advisory” (DS50001764)
• “MPLAB® REAL ICE™ In-Circuit Emulator User’s
Guide” (DS50001616)
• “Using MPLAB® REAL ICE™ Emulator” (poster)
(DS50001749)
2.6
JTAG
The TMS, TDO, TDI and TCK pins are used for testing
and debugging according to the Joint Test Action
Group (JTAG) standard. It is recommended to keep the
trace length between the JTAG connector and the
JTAG pins on the device as short as possible. If the
JTAG connector is expected to experience an ESD
event, a series resistor is recommended, with the value
in the range of a few tens of Ohms, not to exceed 100
Ohms.
External Oscillator Pins
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator. Refer to Section 8.0 “Oscillator
Configuration” for details.
The oscillator circuit should be placed on the same side
of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The
load capacitors should be placed next to the oscillator
itself, on the same side of the board. Use a grounded
copper pour around the oscillator circuit to isolate them
from surrounding circuits. The grounded copper pour
should be routed directly to the MCU ground. Do not
run any signal traces or power traces inside the ground
pour. Also, if using a two-sided board, avoid any traces
on the other side of the board where the crystal is
placed. A suggested layout is illustrated in Figure 2-3.
FIGURE 2-3:
SUGGESTED OSCILLATOR
CIRCUIT PLACEMENT
Oscillator
Secondary
Guard Trace
Guard Ring
Main Oscillator
Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended
as they will interfere with the programmer/debugger
communications to the device. If such discrete components are an application requirement, they should be
removed from the circuit during programming and
debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the
respective device Flash programming specification for
information on capacitive loading limits and pin input
voltage high (VIH) and input low (VIL) requirements.
2009-2019 Microchip Technology Inc.
DS60001156K-page 39
PIC32MX5XX/6XX/7XX
2.9
Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 3 or REAL ICE is selected as a
debugger, it automatically initializes all of the Analogto-Digital input pins (ANx) as “digital” pins by setting
all bits in the AD1PCFG register.
The bits in this register that correspond to the Analogto-Digital pins that are initialized by MPLAB ICD 3 or
REAL ICE, must not be cleared by the user application
firmware; otherwise, communication errors will result
between the debugger and the device.
If your application needs to use certain ADC pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFG register during initialization of the ADC
module.
When MPLAB ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly
configure the AD1PCFG register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will
result in all ADC pins being recognized as analog input
pins, resulting in the port value being read as a logic ‘0’,
which may affect user application functionality.
2.10
Unused I/Os
Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
to a logic-low state.
Alternatively, inputs can be reserved by connecting the
pin to VSS through a 1k to 10k resistor and configuring
the pin as an input.
DS60001156K-page 40
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
2.11
2.11.1
Considerations When Interfacing
to Remotely Powered Circuits
the respective injection current specifications defined
by parameters DI60a, DI60b, and DI60c in TABLE 3610: “DC Characteristics: I/O Pin Input Injection current Specifications”. Figure 2-4 shows an example of
a remote circuit using an independent power source,
which is powered while connected to a PIC32 non-5V
tolerant circuit that is not powered.
NON-5V TOLERANT INPUT PINS
A quick review of the absolute maximum rating section
in 36.0 “Electrical Characteristics” will indicate that
the voltage on any non-5v tolerant pin may not exceed
VDD + 0.3V unless the input current is limited to meet
FIGURE 2-4:
Note:
PIC32 NON-5V TOLERANT CIRCUIT EXAMPLE
PIC32
When VDD power is OFF.
Non-5V Tolerant
Pin Architecture
On/Off
VDD
ANSEL
I/O IN
AN2/RB0
I/O OUT
Remote
GND
TRIS
CPU LOGIC
Remote
0.3V dVIH d 3.6V
PIC32
POWER
SUPPLY
Current Flow
VSS
2009-2019 Microchip Technology Inc.
Opto Coupling
Analog/Digital Switch
EXAMPLES OF DIGITAL/
ANALOG ISOLATORS WITH
OPTIONAL LEVEL
TRANSLATION
Capacitive Coupling
TABLE 2-1:
Inductive Coupling
Without proper signal isolation, on non-5V tolerant
pins, the remote signal can power the PIC32 device
through the high side ESD protection diodes.
Besides violating the absolute maximum rating
specification when VDD of the PIC32 device is
restored and ramping up or ramping down, it can
also negatively affect the internal Power-on Reset
(POR) and Brown-out Reset (BOR) circuits, which
can lead to improper initialization of internal PIC32
logic circuits. In these cases, it is recommended to
implement digital or analog signal isolation as
depicted in Figure 2-5, as appropriate. This is
indicative of all industry microcontrollers and not just
Microchip products.
ADuM7241 / 40 ARZ (1 Mbps)
X
—
—
—
ADuM7241 / 40 CRZ (25 Mbps)
X
—
—
—
ISO721
—
X
—
—
LTV-829S (2 Channel)
—
—
X
—
LTV-849S (4 Channel)
—
—
X
—
FSA266 / NC7WB66
—
—
—
X
Example Digital/Analog
Signal Isolation Circuits
DS60001156K-page 41
PIC32MX5XX/6XX/7XX
FIGURE 2-5:
EXAMPLE DIGITAL/ANALOG SIGNAL ISOLATION CIRCUITS
Conn
PIC32 VDD
Digital Isolator
External VDD
IN
REMOTE_IN
PIC32
PIC32 VDD
Digital Isolator
External VDD
REMOTE_IN
IN1
REMOTE_OUT
OUT1
PIC32
VSS
VSS
PIC32 VDD
Opto Digital
ISOLATOR
PIC32 VDD
Analog / Digital Isolator
Conn
IN1
External VDD
ENB
Analog_OUT2
PIC32
External_VDD1
ENB
PIC32
S
Analog_IN1
REMOTE_IN
Analog_IN2
Analog Switch
VSS
VSS
2.11.2
5V TOLERANT INPUT PINS
The internal high side diode on 5v tolerant pins are
bussed to an internal floating node, rather than being
connected to VDD, as shown in Figure 2-6. Voltages
on these pins, if VDD < 2.3V, should not exceed
roughly 3.2V relative to VSS of the PIC32 device.
Voltage of 3.6V or higher will violate the absolute
maximum specification, and will stress the oxide
layer separating the high side floating node, which
impacts device reliability. If a remotely powered
“digital-only” signal can be guaranteed to always be
3.2V relative to Vss on the PIC32 device side, a
5V tolerant pin could be used without the need for a
digital isolator. This is assuming there is not a
ground loop issue, logic ground of the two circuits
not at the same absolute level, and a remote logic
low input is not less than VSS - 0.3V.
DS60001156K-page 42
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 2-6:
PIC32 5V TOLERANT PIN ARCHITECTURE EXAMPLE
PIC32
Floating Bus
Oxide BV = 3.6V
if VDD < 2.3V
OXIDE
On/Off
VDD
5V Tolerant Pin
Architecture
ANSEL
I/O IN
Remote
VIH = 2.5V
RG10
Remote
GND
PIC32
POWER
SUPPLY
CPU LOGIC
I/O OUT
TRIS
VSS
FIGURE 2-7:
EMI/EMC/EFT (IEC 61000-4-4 and
IEC 61000-4-2) Suppression
Considerations
VDD
0.01 µF
Ferrite
Chips
0.1 µF
0.1 µF
VSS
VDD
VSS
VDD
VSS
0.1 µF
PIC32
VSS
0.1 µF
0.1 µF
VDD
VSS
VUSB3V3
VDD
AVDD
AVSS
0.1 µF
VSS
VDD
VSS
VDD
The use of LDO regulators is preferred to reduce
overall system noise and provide a cleaner power
source. However, when utilizing switching Buck/
Boost regulators as the local power source for PIC32
devices, as well as in electrically noisy environments or test conditions required for IEC 61000-4-4
and IEC 61000-4-2, users should evaluate the use of
T-Filters (i.e., L-C-L) on the power pins, as shown in
Figure 2-7. In addition to a more stable power
source, use of this type of T-Filter can greatly reduce
susceptibility to EMI sources and events.
Ferrite Chip SMD
DCR = 0.15ȍ (max)
600 ma ISAT
300ȍ @ 100 MHz
PN#: 1-1624117-3
VDD
VSS
2.12
EMI/EMC/EFT
SUPPRESSION CIRCUIT
0.1 µF
0.1 µF
0.1 µF
Ferrite
Chips
VDD
0.01 µF
2009-2019 Microchip Technology Inc.
DS60001156K-page 43
PIC32MX5XX/6XX/7XX
NOTES:
DS60001156K-page 44
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
3.0
Note:
CPU
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS60001113) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site (www.microchip.com/PIC32). Resources for the
MIPS32® M4K® Processor Core are
available at http://www.imgtec.com.
The MIPS32® M4K® Processor core is the heart of the
PIC32MX5XX/6XX/7XX family processor. The CPU
fetches instructions, decodes each instruction, fetches
source operands, executes each instruction and writes
the results of instruction execution to the proper
destinations.
3.1
Features
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32 Enhanced Architecture (Release 2)
- Multiply-accumulate and multiply-subtract
instructions
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
for interrupt handlers
- Bit field manipulation instructions
FIGURE 3-1:
• MIPS16e® code compression
- 16-bit encoding of 32-bit instructions to
improve code density
- Special PC-relative instructions for efficient
loading of addresses and constants
- SAVE and RESTORE macro instructions for
setting up and tearing down stack frames
within subroutines
- Improved support for handling 8-bit and 16-bit
data types
• Simple Fixed Mapping Translation (FMT)
mechanism
• Simple dual bus interface
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
interrupt latency
• Autonomous multiply/divide unit
- Maximum issue rate of one 32x16 multiply
per clock
- Maximum issue rate of one 32x32 multiply
every other clock
- Early-in iterative divide. Minimum 11 and
maximum 33 clock latency (dividend (rs) sign
extension-dependent)
• Power control
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
instruction)
- Extensive use of local gated clocks
• EJTAG debug and instruction trace
- Support for single stepping
- Virtual instruction and data address/value
- Breakpoints
- PC tracing with trace compression
MIPS32® M4K® PROCESSOR CORE BLOCK DIAGRAM
CPU
EJTAG
MDU
TAP
Execution Core
(RF/ALU/Shift)
System
Co-processor
2009-2019 Microchip Technology Inc.
FMT
Bus Interface
Off-chip Debug Interface
Dual Bus Interface
Bus Matrix
Power
Management
DS60001156K-page 45
PIC32MX5XX/6XX/7XX
3.2
Architecture Overview
3.2.2
The MIPS32 M4K processor core contains several
logic blocks working together in parallel, providing an
efficient high-performance computing engine. The
following blocks are included with the core:
•
•
•
•
•
•
•
•
Execution Unit
Multiply/Divide Unit (MDU)
System Control Coprocessor (CP0)
Fixed Mapping Translation (FMT)
Dual Internal Bus interfaces
Power Management
MIPS16e® Support
Enhanced JTAG (EJTAG) Controller
3.2.1
EXECUTION UNIT
The MIPS32 M4K processor core execution unit implements a load/store architecture with single-cycle ALU
operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two
32-bit General Purpose Registers (GPRs) used for
integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead
during interrupt/exception processing. The register file
consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline.
The execution unit includes:
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
address
• Logic for branch determination and branch target
address calculation
• Load aligner
• Bypass multiplexers used to avoid stalls when
executing instruction streams where data
producing instructions are followed closely by
consumers of their results
• Leading Zero/One detect unit for implementing
the CLZ and CLO instructions
• Arithmetic Logic Unit (ALU) for performing bit-wise
logical operations
• Shifter and store aligner
TABLE 3-1:
MULTIPLY/DIVIDE UNIT (MDU)
MIPS32 M4K processor core includes a Multiply/Divide
Unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline operates in parallel with the Integer Unit (IU) pipeline and does not stall
when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or
other integer unit instructions.
The high-performance MDU consists of a 32x16 booth
recoded multiplier, result/accumulation registers (HI
and LO), a divide state machine, and the necessary
multiplexers and control logic. The first number shown
(‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
PIC32 core only checks the value of the latter (rt)
operand to determine how many times the operation
must pass through the multiplier. The 16x16 and 32x16
operations pass through the multiplier once. A 32x32
operation passes through the multiplier twice.
The MDU supports execution of one 16x16 or 32x16
multiply operation every clock cycle; 32x32 multiply
operations can be issued every other clock cycle.
Appropriate interlocks are implemented to stall the
issuance of back-to-back 32x32 multiply operations.
The multiply operand size is automatically determined
by logic built into the MDU.
Divide operations are implemented with a simple 1 bit
per clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand.
If rs is 8 bits wide, 23 iterations are skipped. For a 16 bit
wide rs, 15 iterations are skipped and for a 24 bit wide rs,
7 iterations are skipped. Any attempt to issue a
subsequent MDU instruction while a divide is still active
causes an IU pipeline stall until the divide operation is
completed.
Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
MIPS32® M4K® CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT
LATENCIES AND REPEAT RATES
Opcode
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU
MUL
DIV/DIVU
DS60001156K-page 46
Operand Size (mul rt) (div rs)
Latency
Repeat Rate
16 bits
32 bits
16 bits
32 bits
8 bits
16 bits
24 bits
32 bits
1
2
2
3
12
19
26
33
1
2
1
2
11
18
25
32
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
The MIPS architecture defines that the result of a
multiply or divide operation be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be
transferred to the General Purpose Register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction,
MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By
avoiding the explicit MFLO instruction required when
using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive
operations is increased.
3.2.3
SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (Kernel, User and Debug) and
whether interrupts are enabled or disabled. Configuration information, such as presence of options like
MIPS16e, is also available by accessing the CP0
registers, listed in Table 3-2.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
TABLE 3-2:
Register
Number
0-6
COPROCESSOR 0 REGISTERS
Register
Name
Function
Reserved
Reserved.
7
8
HWREna
BadVAddr(1)
Enables access via the RDHWR instruction to selected hardware registers.
Reports the address for the most recent address-related exception.
9
10
Count(1)
Reserved
Processor cycle count.
Reserved.
11
12
Compare(1)
Status(1)
Timer interrupt control.
Processor status and control.
12
12
IntCtl(1)
SRSCtl(1)
Interrupt system status and control.
Shadow register set status and control.
12
13
SRSMap(1)
Cause(1)
Provides mapping from vectored interrupt to a shadow set.
Cause of last general exception.
14
15
EPC(1)
PRId
Program counter at last exception.
Processor identification and revision.
15
16
Ebase
Config
Exception vector base register.
Configuration register.
16
16
Config1
Config2
Configuration Register 1.
Configuration Register 2.
16
17-22
Config3
Reserved
Configuration Register 3.
Reserved.
23
24
Debug(2)
DEPC(2)
Debug control and exception status.
Program counter at last debug exception.
Reserved
ErrorEPC(1)
Reserved.
Program counter at last error.
25-29
30
31
Note 1:
2:
Debug handler scratchpad register.
DESAVE(2)
Registers used in exception processing.
Registers used during debug.
2009-2019 Microchip Technology Inc.
DS60001156K-page 47
PIC32MX5XX/6XX/7XX
Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events or program errors. Table 3-3 lists
the exception types in order of priority.
TABLE 3-3:
PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES
Exception
Description
Reset
Assertion MCLR or a Power-on Reset (POR).
DSS
EJTAG debug single step.
DINT
EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
NMI
Assertion of NMI signal.
Interrupt
Assertion of unmasked hardware or software interrupt signal.
DIB
EJTAG debug hardware instruction break matched.
AdEL
Fetch address alignment error.
Fetch reference to protected address.
IBE
Instruction fetch bus error.
DBp
EJTAG breakpoint (execution of SDBBP instruction).
Sys
Execution of SYSCALL instruction.
Bp
Execution of BREAK instruction.
RI
Execution of a reserved instruction.
CpU
Execution of a coprocessor instruction for a coprocessor that is not enabled.
CEU
Execution of a CorExtend instruction when CorExtend is not enabled.
Ov
Execution of an arithmetic instruction that overflowed.
Tr
Execution of a trap (when trap condition is true).
DDBL/DDBS
EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).
AdEL
Load address alignment error.
Load reference to protected address.
AdES
Store address alignment error.
Store to protected address.
DBE
Load or store bus error.
DDBL
EJTAG data hardware breakpoint matched in load data compare.
DS60001156K-page 48
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
3.3
Power Management
The MIPS32 M4K Processor core offers a number of
power management features, including low-power
design, active power management and power-down
modes of operation. The core is a static design that
supports slowing or halting the clocks, which reduces
system power consumption during idle periods.
3.3.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 28.0
“Power-Saving Features”.
3.3.2
LOCAL CLOCK GATING
The majority of the power consumed by the PIC32MX5XX/6XX/7XX family core is in the clock tree and clocking registers. The PIC32 family uses extensive use of
local gated clocks to reduce this dynamic power consumption.
2009-2019 Microchip Technology Inc.
3.4
EJTAG Debug Support
The MIPS32 M4K Processor core provides for an
Enhanced JTAG (EJTAG) interface for use in the
software debug of application and kernel code. In
addition to standard User mode and Kernel modes of
operation, the MIPS M4K core provides a Debug mode
that is entered after a debug exception (derived from a
hardware breakpoint, single-step exception, etc.) is
taken and continues until a Debug Exception Return
(DERET) instruction is executed. During this time, the
processor executes the debug exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for
transferring test data in and out of the MIPS32 M4K
processor core. In addition to the standard JTAG
instructions, special instructions defined in the EJTAG
specification define which registers are selected and
how they are used.
DS60001156K-page 49
PIC32MX5XX/6XX/7XX
NOTES:
DS60001156K-page 50
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
4.0
Note:
MEMORY ORGANIZATION
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. For
detailed information, refer to Section 3.
“Memory Organization” (DS60001115)
in the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB
of unified virtual memory address space. All memory
regions, including program, data memory, SFRs and
Configuration registers, reside in this address space at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, the data memory can
be made executable, allowing PIC32MX5XX/6XX/7XX
devices to execute from data memory.
4.1
Memory Layout
PIC32MX5XX/6XX/7XX microcontrollers implement
two address schemes: virtual and physical. All
hardware resources, such as program memory, data
memory and peripherals, are located at their respective
physical addresses. Virtual addresses are exclusively
used by the CPU to fetch and execute instructions as
well as access peripherals. Physical addresses are
used by bus master peripherals, such as DMA and the
Flash controller, that access memory independently of
the CPU.
The memory maps for the PIC32MX5XX/6XX/7XX
devices are illustrated in Figure 4-1 through Figure 4-6.
Table 4-1 provides memory map information for the
Special Function Registers (SFRs).
Key features include:
• 32-bit native data width
• Separate User (KUSEG) and Kernel (KSEG0/
KSEG1) mode address space
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
program space
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
runaway code
• Simple memory mapping with Fixed Mapping
Translation (FMT) unit
• Cacheable (KSEG0) and non-cacheable (KSEG1)
address regions
2009-2019 Microchip Technology Inc.
DS60001156K-page 51
PIC32MX5XX/6XX/7XX
FIGURE 4-1:
MEMORY MAP ON RESET FOR PIC32MX564F064H, PIC32MX564F064L,
PIC32MX664F064H AND PIC32MX664F064L DEVICES
Virtual
Memory Map(1)
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map(1)
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD010000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD00FFFF
Program Flash(2)
0xBD000000
0xA0008000
Reserved
0xA0007FFF
RAM(2)
0xA0000000
0x9FC03000
0x9FC02FFF
0x9FC02FF0
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x1FC00000
0x9FC02FEF
Boot Flash
Reserved
0x9FC00000
0x1F900000
Reserved
0x9D010000
0x9D00FFFF
Program Flash(2)
KSEG0
0x1F8FFFFF
SFRs
0x1F800000
Reserved
0x9D000000
0x80008000
0x1D010000
Reserved
0x1D00FFFF
Program Flash(2)
0x1D000000
0x80007FFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
DS60001156K-page 52
Reserved
Reserved
RAM(2)
0x00008000
0x00007FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentation for information).
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 4-2:
MEMORY MAP ON RESET FOR PIC32MX534F064H AND PIC32MX534F064L
DEVICES
Virtual
Memory Map(1)
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map(1)
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD010000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD00FFFF
Program Flash(2)
0xBD000000
0xA0004000
Reserved
0xA0003FFF
RAM(2)
0xA0000000
0x9FC03000
0x9FC02FFF
0x9FC02FF0
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
Reserved
0x9D010000
0x9D00FFFF
Program Flash(2)
KSEG0
0x1F8FFFFF
SFRs
0x1F800000
Reserved
0x9D000000
0x80004000
0x1D010000
Reserved
0x1D00FFFF
Program Flash(2)
0x1D000000
0x80003FFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
Reserved
Reserved
RAM(2)
0x00004000
0x00003FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentation for information).
2009-2019 Microchip Technology Inc.
DS60001156K-page 53
PIC32MX5XX/6XX/7XX
FIGURE 4-3:
MEMORY MAP ON RESET FOR PIC32MX564F128H, PIC32MX564F128L,
PIC32MX664F128H, PIC32MX664F128L, PIC32MX764F128H AND
PIC32MX764F128L DEVICES
Virtual
Memory Map(1)
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map(1)
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD020000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD01FFFF
Program Flash(2)
0xBD000000
0xA0008000
Reserved
0xA0007FFF
RAM(2)
0xA0000000
0x9FC03000
0x9FC02FFF
0x9FC02FF0
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
Reserved
0x9D020000
0x9D01FFFF
Program Flash(2)
KSEG0
0x1F8FFFFF
SFRs
0x1F800000
Reserved
0x9D000000
0x80008000
0x1D020000
Reserved
0x1D01FFFF
Program Flash(2)
0x1D000000
0x80007FFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
DS60001156K-page 54
Reserved
Reserved
RAM(2)
0x00008000
0x00007FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentation for information).
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 4-4:
MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L,
PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND
PIC32MX775F256L DEVICES
Virtual
Memory Map(1)
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map(1)
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD040000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD03FFFF
Program Flash(2)
0xBD000000
0xA0010000
Reserved
0xA000FFFF
RAM(2)
0xA0000000
0x9FC03000
0x9FC02FFF
0x9FC02FF0
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
Reserved
0x9D040000
0x9D03FFFF
Program Flash(2)
KSEG0
0x1F8FFFFF
SFRs
0x1F800000
Reserved
0x9D000000
0x80008000
0x1D040000
Reserved
0x1D03FFFF
Program Flash(2)
0x1D000000
0x8000FFFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
Reserved
Reserved
RAM(2)
0x00010000
0x0000FFFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentation for information).
2009-2019 Microchip Technology Inc.
DS60001156K-page 55
PIC32MX5XX/6XX/7XX
FIGURE 4-5:
MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L,
PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND
PIC32MX775F512L DEVICES
Virtual
Memory Map(1)
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map(1)
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD080000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD07FFFF
Program Flash(2)
0xBD000000
0xA0010000
Reserved
0xA000FFFF
RAM(2)
0xA0000000
0x9FC03000
0x9FC02FFF
0x9FC02FF0
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
Reserved
0x9D080000
0x9D07FFFF
KSEG0
0x1F8FFFFF
Program Flash(2)
SFRs
0x1F800000
Reserved
0x9D000000
0x80010000
0x1D080000
Reserved
0x1D07FFFF
Program Flash(2)
0x1D000000
0x8000FFFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
DS60001156K-page 56
Reserved
Reserved
RAM(2)
0x00010000
0x0000FFFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentation for information).
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 4-6:
MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L,
PIC32MX795F512H AND PIC32MX795F512L DEVICES
Virtual
Memory Map(1)
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map(1)
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD080000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD07FFFF
Program Flash(2)
0xBD000000
0xA0020000
Reserved
0xA001FFFF
RAM(2)
0xA0000000
0x9FC03000
0x9FC02FFF
0x9FC02FF0
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
Reserved
0x9D080000
0x9D07FFFF
KSEG0
0x1F8FFFFF
Program Flash(2)
SFRs
0x1F800000
Reserved
0x9D000000
0x80020000
0x1D080000
Reserved
0x1D07FFFF
Program Flash(2)
0x1D000000
0x8001FFFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
Reserved
Reserved
RAM(2)
0x00020000
0x0001FFFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentation for information).
2009-2019 Microchip Technology Inc.
DS60001156K-page 57
PIC32MX5XX/6XX/7XX
TABLE 4-1:
SFR MEMORY MAP
Virtual Address
Peripheral
Base
Offset
Start
Watchdog Timer
0x0000
RTCC
0x0200
Timer1-Timer5
0x0600
Input Capture 1-5
0x2000
Output Compare 1-5
0x3000
I2C1-I2C5
0x5000
SPI1-SPI4
0x5800
UART1-UART6
PMP
0xBF80
0x6000
0x7000
ADC
0x9000
CVREF
0x9800
Comparator
0xA000
Oscillator
0xF000
Device and Revision ID
0xF200
Flash Controller
0xF400
Reset
0xF600
Interrupts
0x1000
Bus Matrix
0x2000
DMA
0x3000
Prefetch
0xBF88
USB
0x4000
0x5040
PORTA-PORTG
0x6000
Ethernet
0x9000
Configuration
DS60001156K-page 58
0xBFC0
0x2FF0
2009-2019 Microchip Technology Inc.
Control Registers
Register 4-1 through Register 4-8 are used for setting the RAM and Flash memory partitions for data and code.
BMXCON(1)
2010 BMXDKPBA(1)
2020 BMXDUDBA(1)
2030 BMXDUPBA(1)
2040 BMXDRMSZ
2050 BMXPUPBA(1)
BMXPFMSZ
2070 BMXBOOTSZ
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
31:16
—
—
—
—
—
BMXCHEDMA
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
15:0
—
—
—
—
BMXWSDRM
—
—
—
—
—
—
—
—
18/2
17/1
16/0
BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F
BMXARB
—
—
0041
—
—
—
—
—
0000
0000
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
0000
0000
xxxx
BMXDRMSZ
15:0
31:16
19/3
BMXDUPBA
31:16
15:0
20/4
BMXDUDBA
15:0
31:16
21/5
BMXDKPBA
15:0
31:16
22/6
xxxx
—
—
—
—
—
—
—
—
—
—
BMXPUPBA
BMXPFMSZ
—
—
BMXPUPBA
0000
0000
xxxx
xxxx
BMXBOOTSZ
0000
3000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
DS60001156K-page 59
PIC32MX5XX/6XX/7XX
2060
Bits
All
Resets
2000
BUS MATRIX REGISTER MAP
Bit Range
Register
Name
TABLE 4-2:
Virtual Address
(BF88_#)
2009-2019 Microchip Technology Inc.
4.2
PIC32MX5XX/6XX/7XX
REGISTER 4-1:
Bit
Range
BMXCON: BUS MATRIX CONFIGURATION REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
BMX
ERRIXI
BMX
ERRICD
BMX
ERRDMA
BMX
ERRDS
BMX
ERRIS
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-1
U-0
U-0
U-0
R/W-0
R/W-0
R/W-1
—
BMX
WSDRM
—
—
—
BMXARB
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-21 Unimplemented: Read as ‘0’
bit 20
BMXERRIXI: Enable Bus Error from IXI bit
1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus
0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus
bit 19
BMXERRICD: Enable Bus Error from ICD Debug Unit bit
1 = Enable bus error exceptions for unmapped address accesses initiated from ICD
0 = Disable bus error exceptions for unmapped address accesses initiated from ICD
bit 18
BMXERRDMA: Bus Error from DMA bit
1 = Enable bus error exceptions for unmapped address accesses initiated from DMA
0 = Disable bus error exceptions for unmapped address accesses initiated from DMA
bit 17
BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode)
1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access
0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access
bit 16
BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in Debug mode)
1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access
0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access
bit 15-7
Unimplemented: Read as ‘0’
bit 6
BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit
1 = Data RAM accesses from CPU have one wait state for address setup
0 = Data RAM accesses from CPU have zero wait states for address setup
bit 5-3
Unimplemented: Read as ‘0’
bit 2-0
BMXARB: Bus Matrix Arbitration Mode bits
111 = Reserved (using these Configuration modes will produce undefined behavior)
•
•
•
011 = Reserved (using these Configuration modes will produce undefined behavior)
010 = Arbitration Mode 2
001 = Arbitration Mode 1 (default)
000 = Arbitration Mode 0
DS60001156K-page 60
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 4-2:
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
BMXDKPBA
R-0
7:0
BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER
R-0
R-0
R-0
R-0
BMXDKPBA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDKPBA: DRM Kernel Program Base Address bits
When non-zero, this value selects the relative base address for kernel program space in RAM
bit 9-0
BMXDKPBA: DRM Kernel Program Base Address Read-Only bits
Value is always ‘0’, which forces 1 KB increments
Note 1:
At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
The value in this register must be less than or equal to BMXDRMSZ.
2:
2009-2019 Microchip Technology Inc.
DS60001156K-page 61
PIC32MX5XX/6XX/7XX
REGISTER 4-3:
Bit
Range
31:24
23:16
15:8
7:0
BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
BMXDUDBA
R-0
R-0
BMXDUDBA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDUDBA: DRM User Data Base Address bits
When non-zero, the value selects the relative base address for User mode data space in RAM, the value
must be greater than BMXDKPBA.
bit 9-0
BMXDUDBA: DRM User Data Base Address Read-Only bits
Value is always ‘0’, which forces 1 KB increments
Note 1:
At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
The value in this register must be less than or equal to BMXDRMSZ.
2:
DS60001156K-page 62
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 4-4:
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
BMXDUPBA
R-0
7:0
BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER
R-0
R-0
R-0
R-0
BMXDUPBA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDUPBA: DRM User Program Base Address bits
When non-zero, the value selects the relative base address for User mode program space in RAM,
BMXDUPBA must be greater than BMXDUDBA.
bit 9-0
BMXDUPBA: DRM User Program Base Address Read-Only bits
Value is always ‘0’, which forces 1 KB increments
Note 1:
At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
The value in this register must be less than or equal to BMXDRMSZ.
2:
2009-2019 Microchip Technology Inc.
DS60001156K-page 63
PIC32MX5XX/6XX/7XX
REGISTER 4-5:
Bit
Range
31:24
23:16
15:8
7:0
BMXDRMSZ: DATA RAM SIZE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R
R
R
R
R
R
Bit
Bit
28/20/12/4 27/19/11/3
R
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R
R
R
R
R
R
R
R
R
R
R
R
R
BMXDRMSZ
R
R
BMXDRMSZ
R
R
R
R
R
R
R
R
BMXDRMSZ
R
R
BMXDRMSZ
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
BMXDRMSZ: Data RAM Memory (DRM) Size bits
Static value that indicates the size of the Data RAM in bytes:
0x00004000 = device has 16 KB RAM
0x00008000 = device has 32 KB RAM
0x00010000 = device has 64 KB RAM
REGISTER 4-6:
Bit
Range
31:24
23:16
15:8
BMXPUPBA: PROGRAM FLASH (PFM) USER PROGRAM BASE ADDRESS
REGISTER(1,2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
BMXPUPBA
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
BMXPUPBA
R-0
7:0
x = Bit is unknown
R-0
R-0
R-0
R-0
BMXPUPBA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-20 Unimplemented: Read as ‘0’
bit 19-11 BMXPUPBA: Program Flash (PFM) User Program Base Address bits
bit 10-0
BMXPUPBA: Program Flash (PFM) User Program Base Address Read-Only bits
Value is always ‘0’, which forces 2 KB increments
Note 1:
At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
The value in this register must be less than or equal to BMXPFMSZ.
2:
DS60001156K-page 64
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 4-7:
Bit
Range
31:24
23:16
15:8
7:0
BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R
R
R
Bit
Bit
28/20/12/4 27/19/11/3
R
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R
R
R
R
R
R
R
R
R
R
R
R
R
BMXPFMSZ
R
R
R
R
R
BMXPFMSZ
R
R
R
R
R
BMXPFMSZ
R
R
R
R
R
BMXPFMSZ
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
BMXPFMSZ: Program Flash Memory (PFM) Size bits
Static value that indicates the size of the PFM in bytes:
0x00010000 = device has 64 KB Flash
0x00020000 = device has 128 KB Flash
0x00040000 = device has 256 KB Flash
0x00080000 = device has 512 KB Flash
REGISTER 4-8:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
BMXBOOTSZ: BOOT FLASH (IFM) SIZE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R
R
R
Bit
Bit
28/20/12/4 27/19/11/3
R
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R
R
R
R
R
R
R
R
R
R
R
R
R
BMXBOOTSZ
R
R
R
R
R
R
R
R
BMXBOOTSZ
R
R
BMXBOOTSZ
R
R
R
R
R
BMXBOOTSZ
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
BMXBOOTSZ: Boot Flash Memory (BFM) Size bits
Static value that indicates the size of the Boot PFM in bytes:
0x00003000 = device has 12 KB boot Flash
2009-2019 Microchip Technology Inc.
DS60001156K-page 65
PIC32MX5XX/6XX/7XX
NOTES:
DS60001156K-page 66
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
5.0
Note:
FLASH PROGRAM MEMORY
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 5. “Flash
Program Memory” (DS60001121) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX devices contain an internal
Flash program memory for executing user code. There
are three methods by which the user can program this
memory:
• Run-Time Self-Programming (RTSP)
• EJTAG Programming
• In-Circuit Serial Programming™ (ICSP™)
RTSP is performed by software executing from either
Flash or RAM memory. Information about RTSP
techniques is available in Section 5. “Flash Program
Memory” (DS60001121) in the “PIC32 Family
Reference Manual”.
EJTAG is performed using the EJTAG port of the
device and an EJTAG capable programmer.
ICSP is performed using a serial data connection to the
device and allows much faster programming times than
RTSP.
The EJTAG and ICSP methods are described in the
“PIC32
Flash
Programming
Specification”
(DS60001145), which can be downloaded from the
Microchip web site.
Note:
2009-2019 Microchip Technology Inc.
For PIC32MX5XX/6XX/7XX devices, the
Flash page size is 4 KB and the row size
is 512 bytes (1024 IW and 128 IW,
respectively).
DS60001156K-page 67
Control Registers
Virtual Address
(BF80_#)
TABLE 5-1:
FLASH CONTROLLER REGISTER MAP
F400 NVMCON(1)
F410
NVMKEY
(1)
F420 NVMADDR
F430
NVMDATA
F440
NVMSRC
ADDR
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
WR
WREN
WRERR
LVDERR
LVDSTAT
—
—
—
—
—
—
—
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
NVMOP
NVMKEY
NVMADDR
NVMDATA
NVMSRCADDR
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
1:
All Resets
Register
Name
Bit Range
Bits
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MX5XX/6XX/7XX
DS60001156K-page 68
5.1
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 5-1:
Bit
Range
NVMCON: PROGRAMMING CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
—
—
—
—
R/W-0, HC
R/W-0
R-0, HS
R-0, HS
WR
WREN
WRERR(1)
U-0
U-0
U-0
U-0
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
—
R-0, HSC
(1)
LVDERR(1) LVDSTAT
R/W-0
U = Unimplemented bit, read as ‘0’
W = Writable bit
HS = Set by hardware
‘1’ = Bit is set
‘0’ = Bit is cleared
—
—
—
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
NVMOP
HSC = Set and Cleared by hardware
HC = Cleared by hardware
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
WR: Write Control bit
This bit is writable when WREN = 1 and the unlock sequence is followed.
1 = Initiate a Flash operation. Hardware clears this bit when the operation completes
0 = Flash operation complete or inactive
bit 14
WREN: Write Enable bit
1 = Enable writes to WR bit and enables LVD circuit
0 = Disable writes to WR bit and disables LVD circuit
bit 13
bit 12
bit 11
bit 10-4
bit 3-0
Note:
This is the only bit in this register that is reset by a device Reset.
WRERR: Write Error bit(1)
This bit is read-only and is automatically set by hardware.
1 = Program or erase sequence did not complete successfully
0 = Program or erase sequence completed normally
LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)(1)
This bit is read-only and is automatically set by hardware.
1 = Low-voltage detected (possible data corruption, if WRERR is set)
0 = Voltage level is acceptable for programming
LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled)(1)
This bit is read-only and is automatically set, and cleared, by hardware.
1 = Low-voltage event is active
0 = Low-voltage event is not active
Unimplemented: Read as ‘0’
NVMOP: NVM Operation bits
These bits are writable when WREN = 0.
1111 = Reserved
•
•
•
0111 = Reserved
0110 = No operation
0101 = Program Flash (PFM) erase operation: erases PFM if all pages are not write-protected
0100 = Page erase operation: erases page selected by NVMADDR if it is not write-protected
0011 = Row program operation: programs row selected by NVMADDR if it is not write-protected
0010 = No operation
0001 = Word program operation: programs word selected by NVMADDR if it is not write-protected
0000 = No operation
Note 1:
This bit is cleared by setting NVMOP == 0000b, and initiating a Flash operation (i.e., WR).
2009-2019 Microchip Technology Inc.
DS60001156K-page 69
PIC32MX5XX/6XX/7XX
REGISTER 5-2:
Bit
Range
31:24
23:16
15:8
7:0
NVMKEY: PROGRAMMING UNLOCK REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
W-0
W-0
W-0
Bit
Bit
28/20/12/4 27/19/11/3
W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY
W-0
NVMKEY
W-0
W-0
W-0
W-0
W-0
NVMKEY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
NVMKEY: Unlock Register bits
These bits are write-only, and read as ‘0’ on any read.
This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.
REGISTER 5-3:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
NVMADDR: FLASH ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR
R/W-0
NVMADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR
R/W-0
NVMADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
NVMADDR: Flash Address bits
Bulk/Chip/PFM Erase: Address is ignored.
Page Erase: Address identifies the page to erase.
Row Program: Address identifies the row to program.
Word Program: Address identifies the word to program.
DS60001156K-page 70
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 5-4:
Bit
Range
31:24
23:16
15:8
7:0
NVMDATA: FLASH PROGRAM DATA REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
R/W-0
NVMDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
NVMDATA: Flash Programming Data bits
The bits in this register are only reset by a Power-on Reset (POR).
REGISTER 5-5:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
NVMSRCADDR: SOURCE DATA ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR
R/W-0
R/W-0
NVMSRCADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
NVMSRCADDR: Source Data Address bits
The system physical address of the data to be programmed into the Flash when the NVMOP bits
(NVMCON) are set to perform row programming.
2009-2019 Microchip Technology Inc.
DS60001156K-page 71
PIC32MX5XX/6XX/7XX
NOTES:
DS60001156K-page 72
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
6.0
Note:
RESETS
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 7. “Resets”
(DS60001118) in the “PIC32 Family Reference Manual”, which is available from
the
Microchip
web
site
(www.microchip.com/PIC32).
•
•
•
•
•
•
Power-on Reset (POR)
Master Clear Reset pin (MCLR)
Software Reset (SWR)
Watchdog Timer Reset (WDTR)
Brown-out Reset (BOR)
Configuration Mismatch Reset (CMR)
A simplified block diagram of the Reset module is
illustrated in Figure 6-1.
The Reset module combines all Reset sources and
controls the device Master Reset signal, SYSRST. The
following is a list of device Reset sources:
FIGURE 6-1:
SYSTEM RESET BLOCK DIAGRAM
MCLR
Glitch Filter
Sleep or Idle
WDTR
WDT
Time-out
Voltage
Regulator
Enabled
VDD
MCLR
Power-up
Timer
POR
Brown-out
Reset
BOR
SYSRST
VDD Rise
Detect
Configuration
Mismatch
Reset
Software Reset
2009-2019 Microchip Technology Inc.
CMR
SWR
DS60001156K-page 73
Control Registers
Register
Name(1)
F600
RCON
RESETS REGISTER MAP
F610 RSWRST
Bit Range
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
CMR
VREGS
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
23/7
20/4
19/3
18/2
17/1
16/0
22/6
21/5
—
—
—
—
—
—
—
—
EXTR
SWR
—
WDTO
SLEEP
IDLE
BOR
POR
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
SWRST
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
1:
2:
All Resets(2)
Virtual Address
(BF80_#)
TABLE 6-1:
0000
PIC32MX5XX/6XX/7XX
DS60001156K-page 74
6.1
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 6-1:
Bit
Range
31:24
23:16
15:8
7:0
RCON: RESET CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
—
U-0
U-0
U-0
U-0
R/W-0, HS
R/W-0
—
—
—
—
—
—
CMR
VREGS
R/W-0, HS
R/W-0, HS
U-0
R/W-0, HS
R/W-0, HS
R/W-0, HS
EXTR
SWR
—
WDTO
SLEEP
IDLE
R/W-1, HS
(1)
R/W-1, HS
(1)
BOR
Legend:
HS = Set by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
POR
x = Bit is unknown
bit 31-10 Unimplemented: Read as ‘0’
bit 9
CMR: Configuration Mismatch Reset Flag bit
1 = Configuration mismatch Reset has occurred
0 = Configuration mismatch Reset has not occurred
bit 8
VREGS: Voltage Regulator Standby Enable bit
1 = Regulator is enabled and is on during Sleep mode
0 = Regulator is set to Stand-by Tracking mode
bit 7
EXTR: External Reset (MCLR) Pin Flag bit
1 = Master Clear (pin) Reset has occurred
0 = Master Clear (pin) Reset has not occurred
bit 6
SWR: Software Reset Flag bit
1 = Software Reset was executed
0 = Software Reset was not executed
bit 5
Unimplemented: Read as ‘0’
bit 4
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT Time-out has occurred
0 = WDT Time-out has not occurred
bit 3
SLEEP: Wake From Sleep Flag bit
1 = Device was in Sleep mode
0 = Device was not in Sleep mode
bit 2
IDLE: Wake From Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
bit 1
BOR: Brown-out Reset Flag bit(1)
1 = Brown-out Reset has occurred
0 = Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit(1)
1 = Power-on Reset has occurred
0 = Power-on Reset has not occurred
Note 1:
User software must clear this bit to view the next detection.
2009-2019 Microchip Technology Inc.
DS60001156K-page 75
PIC32MX5XX/6XX/7XX
REGISTER 6-2:
Bit
Range
31:24
23:16
15:8
7:0
RSWRST: SOFTWARE RESET REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
W-0, HC
—
—
—
—
—
—
—
SWRST(1)
Legend:
HC = Cleared by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-1
Unimplemented: Read as ‘0’
bit 0
SWRST: Software Reset Trigger bit(1)
1 = Enable software Reset event
0 = No effect
Note 1:
The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section
6. “Oscillator” (DS60001112) in the “PIC32 Family Reference Manual” for details.
DS60001156K-page 76
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
7.0
INTERRUPT CONTROLLER
Note:
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Interrupts”
(DS60001108) in the “PIC32 Family Reference Manual”, which is available from
the
Microchip
web
site
(www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX devices generate interrupt
requests in response to interrupt events from peripheral
modules. The interrupt control module exists externally
to the CPU logic and prioritizes the interrupt events
before presenting them to the CPU.
FIGURE 7-1:
The Interrupt Controller module includes the following
features:
•
•
•
•
•
•
•
•
•
•
•
Up to 96 interrupt sources
Up to 64 interrupt vectors
Single and multi-vector mode operations
Five external interrupts with edge polarity control
Interrupt proximity timer
Seven user-selectable priority levels for each vector
Four user-selectable sub-priority levels within each
priority
Dedicated shadow set for user-selectable priority
level
Software can generate any interrupt
User-configurable interrupt vector table location
User-configurable interrupt vector spacing
A simplified block diagram of the Interrupt Controller
module is illustrated in Figure 7-1.
INTERRUPT CONTROLLER MODULE
Vector Number
Interrupt Requests
Interrupt Controller
Priority Level
CPU Core
Shadow Set Number
2009-2019 Microchip Technology Inc.
DS60001156K-page 77
PIC32MX5XX/6XX/7XX
TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION
Interrupt Source(1)
IRQ
Number
Vector
Number
Interrupt Bit Location
Flag
Enable
Priority
Sub-Priority
Highest Natural Order Priority
CT – Core Timer Interrupt
0
0
IFS0
IEC0
IPC0
IPC0
CS0 – Core Software Interrupt 0
1
1
IFS0
IEC0
IPC0
IPC0
CS1 – Core Software Interrupt 1
2
2
IFS0
IEC0
IPC0
IPC0
INT0 – External Interrupt 0
3
3
IFS0
IEC0
IPC0
IPC0
T1 – Timer1
4
4
IFS0
IEC0
IPC1
IPC1
IC1 – Input Capture 1
5
5
IFS0
IEC0
IPC1
IPC1
OC1 – Output Compare 1
6
6
IFS0
IEC0
IPC1
IPC1
INT1 – External Interrupt 1
7
7
IFS0
IEC0
IPC1
IPC1
T2 – Timer2
8
8
IFS0
IEC0
IPC2
IPC2
IC2 – Input Capture 2
9
9
IFS0
IEC0
IPC2
IPC2
OC2 – Output Compare 2
10
10
IFS0
IEC0
IPC2
IPC2
INT2 – External Interrupt 2
11
11
IFS0
IEC0
IPC2
IPC2
T3 – Timer3
12
12
IFS0
IEC0
IPC3
IPC3
IC3 – Input Capture 3
13
13
IFS0
IEC0
IPC3
IPC3
OC3 – Output Compare 3
14
14
IFS0
IEC0
IPC3
IPC3
INT3 – External Interrupt 3
15
15
IFS0
IEC0
IPC3
IPC3
T4 – Timer4
16
16
IFS0
IEC0
IPC4
IPC4
IC4 – Input Capture 4
17
17
IFS0
IEC0
IPC4
IPC4
OC4 – Output Compare 4
18
18
IFS0
IEC0
IPC4
IPC4
INT4 – External Interrupt 4
19
19
IFS0
IEC0
IPC4
IPC4
T5 – Timer5
20
20
IFS0
IEC0
IPC5
IPC5
IC5 – Input Capture 5
21
21
IFS0
IEC0
IPC5
IPC5
OC5 – Output Compare 5
22
22
IFS0
IEC0
IPC5
IPC5
SPI1E – SPI1 Fault
23
23
IFS0
IEC0
IPC5
IPC5
SPI1RX – SPI1 Receive Done
24
23
IFS0
IEC0
IPC5
IPC5
SPI1TX – SPI1 Transfer Done
25
23
IFS0
IEC0
IPC5
IPC5
26
24
IFS0
IEC0
IPC6
IPC6
27
24
IFS0
IEC0
IPC6
IPC6
28
24
IFS0
IEC0
IPC6
IPC6
U1E – UART1 Error
SPI3E – SPI3 Fault
I2C3B – I2C3 Bus Collision Event
U1RX – UART1 Receiver
SPI3RX – SPI3 Receive Done
I2C3S – I2C3 Slave Event
U1TX – UART1 Transmitter
SPI3TX – SPI3 Transfer Done
I2C3M – I2C3 Master Event
I2C1B – I2C1 Bus Collision Event
29
25
IFS0
IEC0
IPC6
IPC6
I2C1S – I2C1 Slave Event
30
25
IFS0
IEC0
IPC6
IPC6
I2C1M – I2C1 Master Event
31
25
IFS0
IEC0
IPC6
IPC6
CN – Input Change Interrupt
32
26
IFS1
IEC1
IPC6
IPC6
Note 1:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX5XX USB and CAN
Features”, TABLE 2: “PIC32MX6XX USB and Ethernet Features” and TABLE 3: “PIC32MX7XX USB,
Ethernet, and CAN Features” for the list of available peripherals.
DS60001156K-page 78
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
IRQ
Number
Vector
Number
Interrupt Bit Location
Flag
Enable
Priority
Sub-Priority
AD1 – ADC1 Convert Done
33
27
IFS1
IEC1
IPC6
IPC6
PMP – Parallel Master Port
34
28
IFS1
IEC1
IPC7
IPC7
CMP1 – Comparator Interrupt
35
29
IFS1
IEC1
IPC7
IPC7
CMP2 – Comparator Interrupt
36
30
IFS1
IEC1
IPC7
IPC7
U2E – UART2 Error
SPI2E – SPI2 Fault
I2C4B – I2C4 Bus Collision Event
37
31
IFS1
IEC1
IPC7
IPC7
U2RX – UART2 Receiver
SPI2RX – SPI2 Receive Done
I2C4S – I2C4 Slave Event
38
31
IFS1
IEC1
IPC7
IPC7
U2TX – UART2 Transmitter
SPI2TX – SPI2 Transfer Done
IC4M – I2C4 Master Event
39
31
IFS1
IEC1
IPC7
IPC7
U3E – UART3 Error
SPI4E – SPI4 Fault
I2C5B – I2C5 Bus Collision Event
40
32
IFS1
IEC1
IPC8
IPC8
U3RX – UART3 Receiver
SPI4RX – SPI4 Receive Done
I2C5S – I2C5 Slave Event
41
32
IFS1
IEC1
IPC8
IPC8
U3TX – UART3 Transmitter
SPI4TX – SPI4 Transfer Done
IC5M – I2C5 Master Event
42
32
IFS1
IEC1
IPC8
IPC8
I2C2B – I2C2 Bus Collision Event
43
33
IFS1
IEC1
IPC8
IPC8
I2C2S – I2C2 Slave Event
44
33
IFS1
IEC1
IPC8
IPC8
I2C2M – I2C2 Master Event
45
33
IFS1
IEC1
IPC8
IPC8
FSCM – Fail-Safe Clock Monitor
46
34
IFS1
IEC1
IPC8
IPC8
RTCC – Real-Time Clock and
Calendar
47
35
IFS1
IEC1
IPC8
IPC8
DMA0 – DMA Channel 0
48
36
IFS1
IEC1
IPC9
IPC9
DMA1 – DMA Channel 1
49
37
IFS1
IEC1
IPC9
IPC9
DMA2 – DMA Channel 2
50
38
IFS1
IEC1
IPC9
IPC9
DMA3 – DMA Channel 3
51
39
IFS1
IEC1
IPC9
IPC9
DMA4 – DMA Channel 4
52
40
IFS1
IEC1
IPC10
IPC10
DMA5 – DMA Channel 5
53
41
IFS1
IEC1
IPC10 IPC10
DMA6 – DMA Channel 6
54
42
IFS1
IEC1
IPC10 IPC10
DMA7 – DMA Channel 7
55
43
IFS1
IEC1
IPC10 IPC10
FCE – Flash Control Event
56
44
IFS1
IEC1
IPC11
IPC11
USB – USB Interrupt
57
45
IFS1
IEC1
IPC11 IPC11
CAN1 – Control Area Network 1
58
46
IFS1
IEC1
IPC11 IPC11
CAN2 – Control Area Network 2
59
47
IFS1
IEC1
IPC11 IPC11
ETH – Ethernet Interrupt
60
48
IFS1
IEC1
IPC12
IPC12
IC1E – Input Capture 1 Error
61
5
IFS1
IEC1
IPC1
IPC1
IC2E – Input Capture 2 Error
62
9
IFS1
IEC1
IPC2
IPC2
Note 1:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX5XX USB and CAN
Features”, TABLE 2: “PIC32MX6XX USB and Ethernet Features” and TABLE 3: “PIC32MX7XX USB,
Ethernet, and CAN Features” for the list of available peripherals.
2009-2019 Microchip Technology Inc.
DS60001156K-page 79
PIC32MX5XX/6XX/7XX
TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
IRQ
Number
Vector
Number
Interrupt Bit Location
Flag
Enable
Priority
Sub-Priority
IC3E – Input Capture 3 Error
63
13
IFS1
IEC1
IPC3
IPC3
IC4E – Input Capture 4 Error
64
17
IFS2
IEC2
IPC4
IPC4
IC5E – Input Capture 5 Error
65
21
IFS2
IEC2
IPC5
IPC5
PMPE – Parallel Master Port Error
66
28
IFS2
IEC2
IPC7
IPC7
U4E – UART4 Error
67
49
IFS2
IEC2
IPC12 IPC12
U4RX – UART4 Receiver
68
49
IFS2
IEC2
IPC12 IPC12
U4TX – UART4 Transmitter
69
49
IFS2
IEC2
IPC12 IPC12
U6E – UART6 Error
70
50
IFS2
IEC2
IPC12 IPC12
U6RX – UART6 Receiver
71
50
IFS2
IEC2
IPC12 IPC12
U6TX – UART6 Transmitter
72
50
IFS2
IEC2
IPC12 IPC12
U5E – UART5 Error
73
51
IFS2
IEC2
IPC12 IPC12
U5RX – UART5 Receiver
74
51
IFS2
IEC2
IPC12 IPC12
U5TX – UART5 Transmitter
75
51
IFS2
IEC2
IPC12 IPC12
(Reserved)
—
—
—
—
—
—
Lowest Natural Order Priority
Note 1:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX5XX USB and CAN
Features”, TABLE 2: “PIC32MX6XX USB and Ethernet Features” and TABLE 3: “PIC32MX7XX USB,
Ethernet, and CAN Features” for the list of available peripherals.
DS60001156K-page 80
2009-2019 Microchip Technology Inc.
Control Registers
TABLE 7-2:
INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND
PIC32MX575F512H DEVICES
INTCON
1010 INTSTAT(3)
1020
IPTMR
1030
IFS0
IFS1
1050
IFS2
1060
IEC0
1070
IEC1
DS60001156K-page 81
1080
IEC2
1090
IPC0
30/14
29/13
28/12
27/11
26/10
31:16
—
—
15:0
—
—
—
—
—
—
—
MVEC
—
31:16
—
15:0
—
—
—
—
—
—
—
—
—
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
INT4EP
—
—
—
—
—
—
TPC
—
—
—
SRIPL
31:16
19/3
18/2
17/1
16/0
—
—
—
SS0
0000
INT3EP INT2EP INT1EP INT0EP 0000
—
—
—
—
VEC
31:16 I2C1MIF
I2C1SIF
I2C1BIF
U1TXIF
U1RXIF
U1EIF
SPI3TXIF
SPI3RXIF
SPI3EIF
I2C3MIF
I2C3SIF
I2C3BIF
—
—
0000
0000
—
OC5IF
IC5IF
T5IF
INT4IF
OC4IF
IC4IF
T4IF
0000
INT1IF
OC1IF
IC1IF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
31:16
IC3EIF
IC2EIF
IC1EIF
—
—
CAN1IF
USBIF
FCEIF
U3TXIF
U3RXIF
U3EIF
15:0
RTCCIF
FSCMIF
—
—
—
SPI4TXIF
SPI4RXIF
SPI4EIF
SPI2TXIF SPI2RXIF
SPI2EIF
I2C5MIF
I2C5SIF
I2C5BIF
I2C4MIF
I2C4BIF
DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) DMA3IF DMA2IF DMA1IF DMA0IF 0000
U2TXIF
U2RXIF
I2C4SIF
U2EIF
CMP2IF
CMP1IF
PMPIF
AD1IF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U5TXIF
U5RXIF
U5EIF
U6TXIF
U6RXIF
U6EIF
U4TXIF
U4RXIF
U4EIF
U1TXIE
U1RXIE
U1EIE
SPI3TXIE
SPI3RXIE
SPI3EIE
—
—
—
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
I2C3MIE
I2C3SIE
I2C3BIE
INT1IE
OC1IE
IC1IE
T1IE
INT0IE
CS1IE
31:16 I2C1MIE I2C1SIE
I2C1BIE
0000
0000
IPTMR
15:0
31:16
15:0
20/4
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
31:16
IC3EIE
IC2EIE
IC1EIE
—
—
CAN1IE
USBIE
FCEIE
U3TXIE
U3RXIE
U3EIE
15:0
RTCCIE
FSCMIE
—
—
—
SPI4TXIE
SPI4RXIE
SPI4EIE
SPI2TXIE SPI2RXIE
SPI2EIE
I2C5MIE
I2C5SIE
I2C5BIE
I2C4MIE
I2C4BIE
CNIF
0000
—
0000
IC4EIF
0000
IC4IE
T4IE
0000
CS0IE
CTIE
0000
PMPEIF IC5EIF
DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) DMA3IE DMA2IE DMA1IE DMA0IE 0000
U2TXIE
U2RXIE
I2C4SIE
U2EIE
CMP2IE
CMP1IE
PMPIE
AD1IE
—
—
CNIE
0000
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
U5TXIE
U5RXIE
U5EIE
U6TXIE
U6RXIE
U6EIE
U4TXIE
U4RXIE
U4EIE
31:16
—
—
—
INT0IP
INT0IS
—
—
—
CS1IP
CS1IS
0000
15:0
—
—
—
CS0IP
CS0IS
—
—
—
CTIP
CTIS
0000
PMPEIE IC5EIE
IC4EIE 0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET
and INV Registers” for more information.
These bits are not available on PIC32MX534/564/664/764 devices.
This register does not have associated CLR, SET, and INV registers.
1:
2:
3:
PIC32MX5XX/6XX/7XX
1040
31/15
All
Resets
1000
Bit Range
Register
Name(1)
Bits
Virtual Address
(BF88_#)
2009-2019 Microchip Technology Inc.
7.1
INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND
PIC32MX575F512H DEVICES (CONTINUED)
IPC1
10B0
IPC2
10C0
IPC3
10D0
IPC4
10E0
IPC5
10F0
IPC6
1100
IPC7
1110
IPC8
2009-2019 Microchip Technology Inc.
1120
IPC9
1130
IPC10
1140
IPC11
1150
IPC12
16/0
OC1IP
OC1IS
0000
T1IP
T1IS
0000
—
OC2IP
OC2IS
0000
—
—
T2IP
T2IS
0000
—
—
—
OC3IP
OC3IS
0000
IC3IS
—
—
—
T3IP
T3IS
0000
INT4IP
INT4IS
—
—
—
OC4IP
OC4IS
0000
IC4IP
IC4IS
—
—
—
T4IP
T4IS
0000
—
—
—
OC5IP
OC5IS
0000
IC5IS
—
—
—
T5IP
T5IS
0000
AD1IS
—
—
—
CNIP
CNIS
0000
U1IP
U1IS
SPI3IP
SPI3IS
I2C3IP
I2C3IS
CMP2IP
CMP2IS
0000
31/15
30/14
29/13
23/7
22/6
21/5
31:16
—
—
—
INT1IP
15:0
—
—
—
IC1IP
INT1IS
—
—
—
IC1IS
—
—
—
31:16
—
—
—
INT2IP
INT2IS
—
—
15:0
—
—
—
IC2IP
IC2IS
—
31:16
—
—
—
INT3IP
INT3IS
15:0
—
—
—
IC3IP
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
IC5IP
31:16
—
—
—
AD1IP
15:0
31:16
—
—
—
—
28/12
All
Resets
Register
Name(1)
10A0
Bit Range
Virtual Address
(BF88_#)
Bits
—
—
27/11
—
26/10
—
I2C1IP
—
25/9
—
24/8
—
I2C1IS
U2IP
U2IS
SPI2IP
SPI2IS
I2C4IP
I2C4IS
—
—
20/4
—
—
—
—
19/3
18/2
17/1
0000
15:0
—
—
—
CMP1IP
CMP1IS
—
—
—
PMPIP
PMPIS
0000
31:16
—
—
—
RTCCIP
RTCCIS
—
—
—
FSCMIP
FSCMIS
0000
U3IP
U3IS
SPI4IP
SPI4IS
I2C5IP
I2C5IS
15:0
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
DMA3IP
DMA3IS
—
—
—
DMA2IP
DMA2IS
0000
15:0
—
—
—
DMA1IP
DMA1IS
—
—
—
DMA0IP
DMA0IS
0000
31:16
—
—
—
DMA7IP(2)
DMA7IS(2)
—
—
—
DMA6IP(2)
DMA6IS(2)
0000
15:0
—
—
—
DMA5IP(2)
DMA5IS(2)
—
—
—
DMA4IP(2)
DMA4IS(2)
0000
31:16
—
—
—
—
—
—
CAN1IP
CAN1IS
0000
0000
—
—
—
—
—
15:0
—
—
—
USBIP
USBIS
—
—
—
FCEIP
FCEIS
31:16
—
—
—
U5IP
U5IS
—
—
—
U6IP
U6IS
0000
15:0
—
—
—
U4IP
U4IS
—
—
—
—
0000
—
—
—
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET
and INV Registers” for more information.
These bits are not available on PIC32MX534/564/664/764 devices.
This register does not have associated CLR, SET, and INV registers.
1:
2:
3:
PIC32MX5XX/6XX/7XX
DS60001156K-page 82
TABLE 7-2:
Virtual Address
(BF88_#)
Register
Name(1)
1000
INTCON
INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND
PIC32MX695F512H DEVICES
1010 INTSTAT(3)
1020
IPTMR
1030
IFS0
1040
IFS1
1050
IFS2
IEC0
1070
IEC1
1080
IEC2
1090
IPC0
10A0
IPC1
DS60001156K-page 83
10B0
IPC2
10C0
IPC3
30/14
29/13
28/12
27/11
26/10
31:16
—
—
15:0
—
—
—
—
—
—
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
SS0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
—
—
—
—
—
—
—
—
0000
—
—
TPC
—
—
SRIPL
31:16
18/2
17/1
16/0
VEC
I2C1MIF
I2C1SIF
I2C1BIF
U1TXIF
U1RXIF
U1EIF
SPI3TXIF
SPI3RXIF
SPI3EIF
I2C3MIF
I2C3SIF
I2C3BIF
—
—
0000
0000
—
OC5IF
IC5IF
T5IF
INT1IF
OC1IF
IC1IF
T1IF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
IC3EIF
IC2EIF
IC1EIF
ETHIF
—
—
USBIF
FCEIF
U3TXIF
U3RXIF
U3EIF
U2TXIF
U2RXIF
U2EIF
15:0
RTCCIF
FSCMIF
—
—
—
SPI4TXIF
SPI4RXIF
SPI4EIF
SPI2TXIF
SPI2RXIF
SPI2EIF
I2C5MIF
I2C5SIF
I2C5BIF
I2C4MIF
I2C4SIF
I2C4BIF
31:16
—
—
15:0
—
—
31:16 I2C1MIE
I2C1SIE
—
I2C1BIE
IC4IF
T4IF
INT0IF
CS1IF
CS0IF
CTIF
0000
DMA3IF
DMA2IF
DMA1IF
DMA0IF
0000
CMP1IF
PMPIF
AD1IF
CNIF
0000
—
—
—
—
—
—
—
—
—
—
—
0000
U5RXIF
U5EIF
U6TXIF
U6RXIF
U6EIF
U4TXIF
U4RXIF
U4EIF
PMPEIF
IC5EIF
IC4EIF
0000
U1TXIE
U1RXIE
U1EIE
—
—
—
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
INT1IE
OC1IE
IC1IE
T1IE
SPI3TXIE SPI3RXIE
SPI3EIE
I2C3MIE
I2C3SIE
I2C3BIE
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
IC2EIE
IC1EIE
ETHIE
—
—
USBIE
FCEIE
U3TXIE
U3RXIE
U3EIE
—
—
DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2)
U2TXIE
U2RXIE
SPI4EIE
SPI2TXIE SPI2RXIE
SPI2EIE
I2C5MIE
I2C5BIE
I2C4MIE
I2C4BIE
I2C4SIE
CS1IE
CS0IE
CTIE
0000
DMA2IE
DMA1IE
DMA0IE
0000
CMP1IE
PMPIE
AD1IE
CNIE
0000
0000
U2EIE
SPI4TXIE SPI4RXIE
I2C5SIE
INT0IE
DMA3IE
CMP2IE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
U5TXIE
U5RXIE
U5EIE
U6TXIE
U6RXIE
U6EIE
U4TXIE
U4RXIE
U4EIE
PMPEIE
IC5EIE
IC4EIE
31:16
—
—
—
INT0IS
—
—
—
INT0IP
CS1IP
0000
15:0
—
—
—
CS0IP
CS0IS
—
—
—
CTIP
CTIS
0000
31:16
—
—
—
INT1IP
INT1IS
—
—
—
OC1IP
OC1IS
0000
15:0
—
—
—
IC1IP
IC1IS
—
—
—
T1IP
T1IS
0000
31:16
—
—
—
INT2IP
INT2IS
—
—
—
OC2IP
OC2IS
0000
15:0
—
—
—
IC2IP
IC2IS
—
—
—
T2IP
T2IS
0000
31:16
—
—
—
INT3IP
INT3IS
—
—
—
OC3IP
OC3IS
0000
15:0
—
—
—
IC3IP
IC3IS
—
—
—
T3IP
T3IS
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
These bits are not available on PIC32MX664 devices.
This register does not have associated CLR, SET, and INV registers.
2:
3:
0000
CS1IS
Legend:
1:
0000
—
IC3EIE
—
CMP2IF
OC4IF
U5TXIF
15:0
FSCMIE
DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2)
INT4IF
—
31:16
RTCCIE
0000
0000
31:16
15:0
19/3
IPTMR
15:0
31:16
—
20/4
PIC32MX5XX/6XX/7XX
1060
31/15
All Resets
Bits
Bit Range
2009-2019 Microchip Technology Inc.
TABLE 7-3:
Virtual Address
(BF88_#)
Register
Name(1)
10D0
IPC4
10E0
IPC5
INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND
PIC32MX695F512H DEVICES (CONTINUED)
10F0
IPC6
1100
IPC7
1110
IPC8
1120
IPC9
1130
IPC10
1140
IPC11
1150
IPC12
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
INT4IP
INT4IS
—
—
—
OC4IP
OC4IS
0000
15:0
—
—
—
IC4IP
IC4IS
—
—
—
T4IP
T4IS
0000
31:16
—
—
—
—
—
—
OC5IP
OC5IS
0000
15:0
—
—
—
IC5IP
IC5IS
—
—
—
T5IP
T5IS
0000
31:16
—
—
—
AD1IP
AD1IS
—
—
—
CNIP
CNIS
0000
U1IP
U1IS
SPI3IP
SPI3IS
I2C3IP
I2C3IS
CMP2IP
CMP2IS
0000
15:0
31:16
—
—
—
—
—
—
—
—
I2C1IP
—
—
—
I2C1IS
U2IP
U2IS
SPI2IP
SPI2IS
I2C4IP
I2C4IS
—
—
—
—
—
—
15:0
—
—
—
CMP1IP
CMP1IS
—
—
—
PMPIP
PMPIS
0000
—
—
—
RTCCIP
RTCCIS
—
—
—
FSCMIP
FSCMIS
0000
U3IP
U3IS
SPI4IP
SPI4IS
I2C5IP
I2C5IS
15:0
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
DMA3IP
DMA3IS
—
—
—
DMA2IP
DMA2IS
15:0
—
—
—
DMA1IP
DMA1IS
—
—
—
DMA0IP
DMA0IS
0000
31:16
—
—
—
DMA7IP(2)
DMA7IS(2)
—
—
—
DMA6IP(2)
DMA6IS(2)
0000
DMA5IS(2)
—
—
—
DMA4IS(2)
0000
—
—
—
DMA5IP(2)
DMA4IP(2)
0000
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
USBIP
USBIS
—
—
—
FCEIP
FCEIS
0000
31:16
—
—
—
U5IP
U5IS
—
—
—
U6IP
U6IS
0000
15:0
—
—
—
U4IP
U4IS
—
—
—
ETHIP
ETHIS
0000
—
—
—
—
—
—
—
—
—
—
2009-2019 Microchip Technology Inc.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
These bits are not available on PIC32MX664 devices.
This register does not have associated CLR, SET, and INV registers.
2:
3:
0000
31:16
Legend:
1:
All Resets
Bit Range
Bits
0000
PIC32MX5XX/6XX/7XX
DS60001156K-page 84
TABLE 7-3:
Virtual Address
(BF88_#)
Register
Name(1)
1000
INTCON
INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND
PIC32MX795F512H DEVICES
1010 INTSTAT
1020
(3)
IPTMR
1030
IFS0
1040
IFS1
1050
IFS2
IEC0
1070
IEC1
1080
IEC2
1090
IPC0
10A0
IPC1
DS60001156K-page 85
10B0
IPC2
IPC3
10C0
30/14
29/13
28/12
27/11
26/10
31:16
—
—
15:0
—
—
—
—
—
—
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
SS0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
—
—
—
—
—
—
—
—
0000
—
—
TPC
—
—
SRIPL
31:16
19/3
18/2
17/1
16/0
VEC
I2C1MIF
I2C1SIF
I2C1BIF
U1TXIF
U1RXIF
U1EIF
SPI3TXIF
SPI3RXIF
SPI3EIF
I2C3MIF
I2C3SIF
I2C3BIF
—
—
0000
0000
—
OC5IF
IC5IF
T5IF
INT1IF
OC1IF
IC1IF
T1IF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
31:16
IC3EIF
IC2EIF
IC1EIF
ETHIF
CAN2IF(2)
CAN1IF
USBIF
FCEIF
U3TXIF
U3RXIF
U3EIF
U2TXIF
U2RXIF
U2EIF
15:0
RTCCIF
FSCMIF
—
—
—
SPI4TXIF
SPI4RXIF
SPI4EIF
SPI2TXIF
SPI2RXIF
SPI2EIF
I2C5MIF
I2C5SIF
I2C5BIF
I2C4MIF
I2C4SIF
I2C4BIF
DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2)
CMP2IF
INT4IF
OC4IF
IC4IF
T4IF
INT0IF
CS1IF
CS0IF
CTIF
0000
DMA2IF
DMA1IF
DMA0IF
0000
CMP1IF
PMPIF
AD1IF
CNIF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U5TXIF
U5RXIF
U5EIF
U6TXIF
U6RXIF
U6EIF
U4TXIF
U4RXIF
U4EIF
PMPEIF
IC5EIF
IC4EIF
0000
U1TXIE
U1RXIE
U1EIE
—
—
—
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
INT1IE
OC1IE
IC1IE
T1IE
31:16
I2C1MIE
I2C1SIE
I2C1BIE
SPI3TXIE SPI3RXIE
SPI3EIE
I2C3MIE
I2C3BIE
I2C3SIE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
31:16
IC3EIE
IC2EIE
IC1EIE
ETHIE
CAN2IE(2)
CAN1IE
USBIE
FCEIE
U3TXIE
U3RXIE
U3EIE
15:0
RTCCIE
FSCMIE
—
—
—
DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2)
U2TXIE
U2RXIE
SPI4EIE
SPI2TXIE SPI2RXIE
SPI2EIE
I2C5MIE
I2C5BIE
I2C4MIE
I2C4BIE
I2C4SIE
CS1IE
CS0IE
CTIE
0000
DMA2IE
DMA1IE
DMA0IE
0000
CMP1IE
PMPIE
AD1IE
CNIE
0000
0000
U2EIE
SPI4TXIE SPI4RXIE
I2C5SIE
INT0IE
DMA3IE
CMP2IE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
U5TXIE
U5RXIE
U5EIE
U6TXIE
U6RXIE
U6EIE
U4TXIE
U4RXIE
U4EIE
PMPEIE
IC5EIE
IC4EIE
31:16
—
—
—
INT0IS
—
—
—
INT0IP
CS1IP
0000
CS1IS
0000
15:0
—
—
—
CS0IP
CS0IS
—
—
—
CTIP
CTIS
0000
31:16
—
—
—
INT1IP
INT1IS
—
—
—
OC1IP
OC1IS
0000
15:0
—
—
—
IC1IP
IC1IS
—
—
—
T1IP
T1IS
0000
31:16
—
—
—
INT2IP
INT2IS
—
—
—
OC2IP
OC2IS
0000
15:0
—
—
—
IC2IP
IC2IS
—
—
—
T2IP
T2IS
0000
31:16
—
—
—
INT3IP
INT3IS
—
—
—
OC3IP
OC3IS
0000
15:0
—
—
—
IC3IP
IC3IS
—
—
—
T3IP
T3IS
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
This bit is unimplemented on PIC32MX764F128H device.
This register does not have associated CLR, SET, and INV registers.
2:
3:
0000
DMA3IF
Legend:
1:
0000
0000
IPTMR
15:0
31:16
—
20/4
PIC32MX5XX/6XX/7XX
1060
31/15
All Resets
Bits
Bit Range
2009-2019 Microchip Technology Inc.
TABLE 7-4:
Virtual Address
(BF88_#)
Register
Name(1)
10D0
IPC4
10E0
IPC5
IPC6
1100
IPC7
1110
IPC8
1120
IPC9
1130
IPC10
1140
IPC11
1150
IPC12
2009-2019 Microchip Technology Inc.
Legend:
31/15
30/14
29/13
31:16
—
—
—
INT4IP
15:0
—
—
—
IC4IP
31:16
—
—
—
15:0
—
—
—
IC5IP
31:16
—
—
—
AD1IP
15:0
31:16
—
—
—
—
28/12
—
—
27/11
—
26/10
—
I2C1IP
—
25/9
23/7
22/6
21/5
INT4IS
—
—
—
OC4IP
OC4IS
0000
IC4IS
—
—
—
T4IP
T4IS
0000
—
—
—
OC5IP
OC5IS
0000
IC5IS
—
—
—
T5IP
T5IS
0000
AD1IS
—
—
—
CNIP
CNIS
0000
U1IP
U1IS
SPI3IP
SPI3IS
I2C3IP
I2C3IS
CMP2IP
CMP2IS
0000
—
24/8
—
I2C1IS
U2IP
U2IS
SPI2IP
SPI2IS
I2C4IP
I2C4IS
—
—
—
—
—
—
20/4
19/3
18/2
17/1
16/0
2:
3:
0000
15:0
—
—
—
CMP1IP
CMP1IS
—
—
—
PMPIP
PMPIS
0000
31:16
—
—
—
RTCCIP
RTCCIS
—
—
—
FSCMIP
FSCMIS
0000
U3IP
U3IS
SPI4IP
SPI4IS
I2C5IP
I2C5IS
15:0
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
DMA3IP
DMA3IS
—
—
—
DMA2IP
DMA2IS
15:0
—
—
—
DMA1IP
DMA1IS
—
—
—
DMA0IP
DMA0IS
0000
31:16
—
—
—
DMA7IP(2)
DMA7IS(2)
—
—
—
DMA6IP(2)
DMA6IS(2)
0000
0000
15:0
—
—
—
DMA5IP(2)
DMA5IS(2)
—
—
—
DMA4IP(2)
DMA4IS(2)
0000
31:16
—
—
—
CAN2IP(2)
CAN2IS(2)
—
—
—
CAN1IP
CAN1IS
0000
15:0
—
—
—
USBIP
USBIS
—
—
—
FCEIP
FCEIS
0000
31:16
—
—
—
U5IP
U5IS
—
—
—
U6IP
U6IS
0000
15:0
—
—
—
U4IP
U4IS
—
—
—
ETHIP
ETHIS
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
All Resets
Bit Range
Bits
10F0
Note
INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND
PIC32MX795F512H DEVICES (CONTINUED)
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
This bit is unimplemented on PIC32MX764F128H device.
This register does not have associated CLR, SET, and INV registers.
PIC32MX5XX/6XX/7XX
DS60001156K-page 86
TABLE 7-4:
Virtual Address
(BF88_#)
Register
Name(1)
1000
INTCON
INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND
PIC32MX575F256L DEVICES
(3)
1010 INTSTAT
1020
IPTMR
1030
IFS0
1040
IFS1
1050
IFS2
IEC0
1070
IEC1
1080
IEC2
DS60001156K-page 87
1090
IPC0
10A0
IPC1
10B0
IPC2
10C0
IPC3
30/14
29/13
28/12
27/11
26/10
31:16
—
—
15:0
—
—
—
—
—
—
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
SS0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
—
—
—
—
—
—
—
—
0000
—
—
TPC
—
—
—
SRIPL
31:16
19/3
18/2
17/1
16/0
VEC
I2C1MIF
I2C1SIF
I2C1BIF
U1TXIF
U1RXIF
U1EIF
SPI3TXIF
SPI3RXIF
SPI3EIF
I2C3MIF
I2C3SIF
I2C3BIF
SPI1TXIF
SPI1RXIF
0000
0000
SPI1EIF
OC5IF
IC5IF
T5IF
INT1IF
OC1IF
IC1IF
T1IF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
31:16
IC3EIF
IC2EIF
IC1EIF
—
—
CAN1IF
USBIF
FCEIF
U3TXIF
U3RXIF
U3EIF
U2TXIF
U2RXIF
U2EIF
15:0
RTCCIF
FSCMIF
I2C2MIF
I2C2SIF
I2C2BIF
SPI4TXIF
SPI4RXIF
SPI4EIF
SPI2TXIF
SPI2RXIF
SPI2EIF
I2C5MIF
I2C5SIF
I2C5BIF
I2C4MIF
I2C4SIF
I2C4BIF
DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2)
CMP2IF
INT4IF
OC4IF
IC4IF
INT0IF
CS1IF
CS0IF
DMA3IF
DMA2IF
DMA1IF
CMP1IF
PMPIF
AD1IF
T4IF
0000
CTIF
0000
DMA0IF 0000
CNIF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U5TXIF
U5RXIF
U5EIF
U6TXIF
U6RXIF
U6EIF
U4TXIF
U4RXIF
U4EIF
PMPEIF
IC5EIF
IC4EIF
0000
U1TXIE
U1RXIE
U1EIE
SPI1EIE
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
INT1IE
OC1IE
IC1IE
T1IE
CTIE
0000
31:16
I2C1MIE
I2C1SIE
I2C1BIE
SPI3TXIE SPI3RXIE
SPI3EIE
I2C3MIE
I2C3SIE
I2C3BIE
SPI1TXIE SPI1RXIE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
31:16
IC3EIE
IC2EIE
IC1EIE
—
—
CAN1IE
USBIE
FCEIE
U3TXIE
U3RXIE
15:0
RTCCIE
FSCMIE
I2C2MIE
I2C2SIE
I2C2BIE
U3EIE
DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2)
U2TXIE
U2RXIE
SPI4EIE
SPI2TXIE SPI2RXIE
SPI2EIE
I2C5MIE
I2C5BIE
I2C4MIE
I2C4BIE
I2C4SIE
CS1IE
CS0IE
DMA2IE
DMA1IE
CMP1IE
PMPIE
AD1IE
DMA0IE 0000
U2EIE
SPI4TXIE SPI4RXIE
I2C5SIE
INT0IE
DMA3IE
CMP2IE
CNIE
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
U5TXIE
U5RXIE
U5EIE
U6TXIE
U6RXIE
U6EIE
U4TXIE
U4RXIE
U4EIE
PMPEIE
IC5EIE
IC4EIE
31:16
—
—
—
INT0IS
—
—
—
INT0IP
CS1IP
0000
15:0
—
—
—
CS0IP
CS0IS
—
—
—
CTIP
CTIS
0000
31:16
—
—
—
INT1IP
INT1IS
—
—
—
OC1IP
OC1IS
0000
15:0
—
—
—
IC1IP
IC1IS
—
—
—
T1IP
T1IS
0000
31:16
—
—
—
INT2IP
INT2IS
—
—
—
OC2IP
OC2IS
0000
15:0
—
—
—
IC2IP
IC2IS
—
—
—
T2IP
T2IS
0000
31:16
—
—
—
INT3IP
INT3IS
—
—
—
OC3IP
OC3IS
0000
15:0
—
—
—
IC3IP
IC3IS
—
—
—
T3IP
T3IS
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
These bits are not available on PIC32MX534/564 devices.
This register does not have associated CLR, SET, and INV registers.
2:
3:
0000
CS1IS
Legend:
1:
0000
0000
IPTMR
15:0
31:16
20/4
PIC32MX5XX/6XX/7XX
1060
31/15
All Resets
Bits
Bit Range
2009-2019 Microchip Technology Inc.
TABLE 7-5:
Virtual Address
(BF88_#)
Register
Name(1)
10D0
IPC4
INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND
PIC32MX575F256L DEVICES (CONTINUED)
10E0
IPC5
10F0
IPC6
1100
IPC7
1110
IPC8
1120
IPC9
1130
IPC10
1140
IPC11
1150
IPC12
31/15
30/14
29/13
31:16
—
—
—
INT4IP
15:0
—
—
—
IC4IP
31:16
—
—
—
15:0
—
—
31:16
—
—
15:0
31:16
—
—
—
—
28/12
23/7
22/6
21/5
INT4IS
—
—
—
OC4IP
OC4IS
0000
IC4IS
—
—
—
T4IP
T4IS
0000
SPI1IP
SPI1IS
—
—
—
OC5IP
OC5IS
0000
—
IC5IP
IC5IS
—
—
—
T5IP
T5IS
0000
—
AD1IP
AD1IS
—
—
—
CNIP
CNIS
0000
U1IP
U1IS
SPI3IP
SPI3IS
I2C3IP
I2C3IS
CMP2IP
CMP2IS
0000
—
27/11
26/10
I2C1IP
—
25/9
24/8
I2C1IS
U2IP
U2IS
SPI2IP
SPI2IS
I2C4IP
I2C4IS
—
—
20/4
—
—
—
—
19/3
18/2
17/1
16/0
15:0
—
—
—
CMP1IP
CMP1IS
—
—
—
PMPIP
PMPIS
0000
—
—
—
RTCCIP
RTCCIS
—
—
—
FSCMIP
FSCMIS
0000
U3IP
U3IS
SPI4IP
SPI4IS
I2C5IP
I2C5IS
15:0
—
—
—
I2C2IP
I2C2IS
—
—
—
0000
31:16
—
—
—
DMA3IP
DMA3IS
—
—
—
DMA2IP
DMA2IS
15:0
—
—
—
DMA1IP
DMA1IS
—
—
—
DMA0IP
DMA0IS
0000
31:16
—
—
—
DMA7IP(2)
DMA7IS(2)
—
—
—
DMA6IP(2)
DMA6IS(2)
0000
DMA5IS(2)
—
—
—
DMA4IP(2)
DMA4IS(2)
0000
—
—
—
CAN1IP
CAN1IS
0000
0000
DMA5IP(2)
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
USBIP
USBIS
—
—
—
FCEIP
FCEIS
31:16
—
—
—
U5IP
U5IS
—
—
—
U6IP
U6IS
15:0
—
—
—
U4IP
U4IS
—
—
—
—
—
—
—
—
—
—
—
—
—
2009-2019 Microchip Technology Inc.
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
These bits are not available on PIC32MX534/564 devices.
This register does not have associated CLR, SET, and INV registers.
2:
3:
0000
31:16
Note
1:
All Resets
Bit Range
Bits
0000
0000
0000
PIC32MX5XX/6XX/7XX
DS60001156K-page 88
TABLE 7-5:
Virtual Address
(BF88_#)
Register
Name(1)
1000
INTCON
INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND
PIC32MX695F512L DEVICES
1010 INTSTAT
1020
(3)
IPTMR
1030
IFS0
1040
IFS1
1050
IFS2
IEC0
1070
IEC1
1080
IEC2
DS60001156K-page 89
1090
IPC0
10A0
IPC1
10B0
IPC2
10C0
IPC3
30/14
29/13
28/12
27/11
26/10
31:16
—
—
15:0
—
—
—
—
—
—
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
SS0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
—
—
—
—
—
—
—
—
0000
—
—
TPC
—
—
SRIPL
31:16
19/3
18/2
17/1
16/0
VEC
I2C1MIF
I2C1SIF
I2C1BIF
U1TXIF
U1RXIF
U1EIF
SPI3TXIF
SPI3RXIF
SPI3EIF
I2C3MIF
I2C3SIF
I2C3BIF
SPI1TXIF
SPI1RXIF
0000
0000
SPI1EIF
OC5IF
IC5IF
T5IF
INT1IF
OC1IF
IC1IF
T1IF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
31:16
IC3EIF
IC2EIF
IC1EIF
ETHIF
—
—
USBIF
FCEIF
U3TXIF
U3RXIF
U3EIF
U2TXIF
U2RXIF
U2EIF
15:0
RTCCIF
FSCMIF
I2C2MIF
I2C2SIF
I2C2BIF
SPI4TXIF
SPI4RXIF
SPI4EIF
SPI2TXIF
SPI2RXIF
SPI2EIF
I2C5MIF
I2C5SIF
I2C5BIF
I2C4MIF
I2C4SIF
I2C4BIF
DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2)
CMP2IF
INT4IF
OC4IF
IC4IF
T4IF
INT0IF
CS1IF
CS0IF
CTIF
0000
DMA2IF
DMA1IF
DMA0IF
0000
CMP1IF
PMPIF
AD1IF
CNIF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U5TXIF
U5RXIF
U5EIF
U6TXIF
U6RXIF
U6EIF
U4TXIF
U4RXIF
U4EIF
PMPEIF
IC5EIF
IC4EIF
0000
U1TXIE
U1RXIE
U1EIE
SPI1EIE
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
INT1IE
OC1IE
IC1IE
T1IE
31:16
I2C1MIE
I2C1SIE
I2C1BIE
SPI3TXIE SPI3RXIE
SPI3EIE
I2C3MIE
I2C3SIE
I2C3BIE
SPI1TXIE SPI1RXIE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
31:16
IC3EIE
IC2EIE
IC1EIE
ETHIE
—
—
USBIE
FCEIE
U3TXIE
U3RXIE
15:0
RTCCIE
FSCMIE
I2C2MIE
I2C2SIE
I2C2BIE
U3EIE
DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2)
U2TXIE
U2RXIE
SPI4EIE
SPI2TXIE SPI2RXIE
SPI2EIE
I2C5MIE
I2C5BIE
I2C4MIE
I2C4BIE
I2C4SIE
CS1IE
CS0IE
CTIE
0000
DMA2IE
DMA1IE
DMA0IE
0000
CMP1IE
PMPIE
AD1IE
CNIE
0000
0000
U2EIE
SPI4TXIE SPI4RXIE
I2C5SIE
INT0IE
DMA3IE
CMP2IE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
U5TXIE
U5RXIE
U5EIE
U6TXIE
U6RXIE
U6EIE
U4TXIE
U4RXIE
U4EIE
PMPEIE
IC5EIE
IC4EIE
31:16
—
—
—
INT0IS
—
—
—
INT0IP
CS1IP
0000
CS1IS
0000
15:0
—
—
—
CS0IP
CS0IS
—
—
—
CTIP
CTIS
0000
31:16
—
—
—
INT1IP
INT1IS
—
—
—
OC1IP
OC1IS
0000
15:0
—
—
—
IC1IP
IC1IS
—
—
—
T1IP
T1IS
0000
31:16
—
—
—
INT2IP
INT2IS
—
—
—
OC2IP
OC2IS
0000
15:0
—
—
—
IC2IP
IC2IS
—
—
—
T2IP
T2IS
0000
31:16
—
—
—
INT3IP
INT3IS
—
—
—
OC3IP
OC3IS
0000
15:0
—
—
—
IC3IP
IC3IS
—
—
—
T3IP
T3IS
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
These bits are not available on PIC32MX664 devices.
This register does note have associated CLR, SET, and INV registers.
2:
3:
0000
DMA3IF
Legend:
1:
0000
0000
IPTMR
15:0
31:16
—
20/4
PIC32MX5XX/6XX/7XX
1060
31/15
All Resets
Bits
Bit Range
2009-2019 Microchip Technology Inc.
TABLE 7-6:
Virtual Address
(BF88_#)
Register
Name(1)
10D0
IPC4
10E0
IPC5
INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND
PIC32MX695F512L DEVICES (CONTINUED)
10F0
IPC6
1100
IPC7
1110
IPC8
1120
IPC9
1130
IPC10
1140
IPC11
1150
IPC12
31/15
30/14
29/13
31:16
—
—
—
INT4IP
15:0
—
—
—
IC4IP
31:16
—
—
—
15:0
—
—
31:16
—
—
15:0
31:16
—
—
—
—
28/12
23/7
22/6
21/5
INT4IS
—
—
—
OC4IP
OC4IS
0000
IC4IS
—
—
—
T4IP
T4IS
0000
SPI1IP
SPI1IS
—
—
—
OC5IP
OC5IS
0000
—
IC5IP
IC5IS
—
—
—
T5IP
T5IS
0000
—
AD1IP
AD1IS
—
—
—
CNIP
CNIS
0000
U1IP
U1IS
SPI3IP
SPI3IS
I2C3IP
I2C3IS
CMP2IP
CMP2IS
0000
—
27/11
26/10
I2C1IP
—
25/9
24/8
I2C1IS
U2IP
U2IS
SPI2IP
SPI2IS
I2C4IP
I2C4IS
—
—
20/4
—
—
—
—
19/3
18/2
17/1
16/0
15:0
—
—
—
CMP1IP
CMP1IS
—
—
—
PMPIP
PMPIS
0000
—
—
—
RTCCIP
RTCCIS
—
—
—
FSCMIP
FSCMIS
0000
U3IP
U3IS
SPI4IP
SPI4IS
I2C5IP
I2C5IS
15:0
—
—
—
I2C2IP
I2C2IS
—
—
—
0000
31:16
—
—
—
DMA3IP
DMA3IS
—
—
—
DMA2IP
DMA2IS
15:0
—
—
—
DMA1IP
DMA1IS
—
—
—
DMA0IP
DMA0IS
0000
31:16
—
—
—
DMA7IP(2)
DMA7IS(2)
—
—
—
DMA6IP(2)
DMA6IS(2)
0000
DMA5IS(2)
—
—
—
DMA4IS(2)
0000
—
—
—
DMA5IP(2)
DMA4IP(2)
0000
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
USBIP
USBIS
—
—
—
FCEIP
FCEIS
0000
31:16
—
—
—
U5IP
U5IS
—
—
—
U6IP
U6IS
0000
15:0
—
—
—
U4IP
U4IS
—
—
—
ETHIP
ETHIS
0000
—
—
—
—
—
—
—
—
—
—
2009-2019 Microchip Technology Inc.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
These bits are not available on PIC32MX664 devices.
This register does note have associated CLR, SET, and INV registers.
2:
3:
0000
31:16
Legend:
1:
All Resets
Bit Range
Bits
0000
PIC32MX5XX/6XX/7XX
DS60001156K-page 90
TABLE 7-6:
Virtual Address
(BF88_#)
Register
Name(1)
1000
INTCON
INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND
PIC32MX795F512L DEVICES
1010 INTSTAT
1020
(3)
IPTMR
1030
IFS0
1040
IFS1
1050
IFS2
IEC0
1070
IEC1
1080
IEC2
DS60001156K-page 91
1090
IPC0
10A0
IPC1
10B0
IPC2
10C0
IPC3
30/14
29/13
28/12
27/11
26/10
31:16
—
—
15:0
—
—
—
—
—
—
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
SS0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
—
—
—
—
—
—
—
—
0000
—
—
TPC
—
—
SRIPL
31:16
19/3
18/2
17/1
16/0
VEC
I2C1MIF
I2C1SIF
I2C1BIF
U1TXIF
U1RXIF
U1EIF
SPI3TXIF
SPI3RXIF
SPI3EIF
I2C3MIF
I2C3SIF
I2C3BIF
SPI1TXIF
SPI1RXIF
0000
0000
SPI1EIF
OC5IF
IC5IF
T5IF
INT1IF
OC1IF
IC1IF
T1IF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
31:16
IC3EIF
IC2EIF
IC1EIF
ETHIF
CAN2IF(2)
CAN1IF
USBIF
FCEIF
U3TXIF
U3RXIF
U3EIF
U2TXIF
U2RXIF
U2EIF
15:0
RTCCIF
FSCMIF
I2C2MIF
I2C2SIF
I2C2BIF
SPI4TXIF
SPI4RXIF
SPI4EIF
SPI2TXIF
SPI2RXIF
SPI2EIF
I2C5MIF
I2C5SIF
I2C5BIF
I2C4MIF
I2C4SIF
I2C4BIF
DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2)
CMP2IF
INT4IF
OC4IF
IC4IF
T4IF
INT0IF
CS1IF
CS0IF
CTIF
0000
DMA2IF
DMA1IF
DMA0IF
0000
CMP1IF
PMPIF
AD1IF
CNIF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U5TXIF
U5RXIF
U5EIF
U6TXIF
U6RXIF
U6EIF
U4TXIF
U4RXIF
U4EIF
PMPEIF
IC5EIF
IC4EIF
0000
U1TXIE
U1RXIE
U1EIE
SPI1EIE
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
INT1IE
OC1IE
IC1IE
T1IE
31:16
I2C1MIE
I2C1SIE
I2C1BIE
SPI3TXIE SPI3RXIE
SPI3EIE
I2C3MIE
I2C3BIE
I2C3SIE
SPI1TXIE SPI1RXIE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
31:16
IC3EIE
IC2EIE
IC1EIE
ETHIE
CAN2IE(2)
CAN1IE
USBIE
FCEIE
U3TXIE
U3RXIE
15:0
RTCCIE
FSCMIE
I2C2MIE
I2C2SIE
I2C2BIE
U3EIE
DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2)
U2TXIE
U2RXIE
SPI4EIE
SPI2TXIE SPI2RXIE
SPI2EIE
I2C5MIE
I2C5BIE
I2C4MIE
I2C4BIE
I2C4SIE
CS1IE
CS0IE
CTIE
0000
DMA2IE
DMA1IE
DMA0IE
0000
CMP1IE
PMPIE
AD1IE
CNIE
0000
0000
U2EIE
SPI4TXIE SPI4RXIE
I2C5SIE
INT0IE
DMA3IE
CMP2IE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
U5TXIE
U5RXIE
U5EIE
U6TXIE
U6RXIE
U6EIE
U4TXIE
U4RXIE
U4EIE
PMPEIE
IC5EIE
IC4EIE
31:16
—
—
—
INT0IS
—
—
—
INT0IP
CS1IP
0000
CS1IS
0000
15:0
—
—
—
CS0IP
CS0IS
—
—
—
CTIP
CTIS
0000
31:16
—
—
—
INT1IP
INT1IS
—
—
—
OC1IP
OC1IS
0000
15:0
—
—
—
IC1IP
IC1IS
—
—
—
T1IP
T1IS
0000
31:16
—
—
—
INT2IP
INT2IS
—
—
—
OC2IP
OC2IS
0000
15:0
—
—
—
IC2IP
IC2IS
—
—
—
T2IP
T2IS
0000
31:16
—
—
—
INT3IP
INT3IS
—
—
—
OC3IP
OC3IS
0000
15:0
—
—
—
IC3IP
IC3IS
—
—
—
T3IP
T3IS
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
This bit is unimplemented on PIC32MX764F128L device.
This register does not have associated CLR, SET, and INV registers.
2:
3:
0000
DMA3IF
Legend:
1:
0000
0000
IPTMR
15:0
31:16
—
20/4
PIC32MX5XX/6XX/7XX
1060
31/15
All Resets
Bits
Bit Range
2009-2019 Microchip Technology Inc.
TABLE 7-7:
Virtual Address
(BF88_#)
Register
Name(1)
10D0
IPC4
10E0
IPC5
INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND
PIC32MX795F512L DEVICES (CONTINUED)
10F0
IPC6
1100
IPC7
1110
IPC8
1120
IPC9
1130
IPC10
1140
IPC11
1150
IPC12
31/15
30/14
29/13
31:16
—
—
—
INT4IP
15:0
—
—
—
IC4IP
31:16
—
—
—
15:0
—
—
31:16
—
—
15:0
31:16
—
—
—
—
23/7
22/6
21/5
INT4IS
—
—
—
OC4IP
OC4IS
0000
IC4IS
—
—
—
T4IP
T4IS
0000
SPI1IP
SPI1IS
—
—
—
OC5IP
OC5IS
0000
—
IC5IP
IC5IS
—
—
—
T5IP
T5IS
0000
—
AD1IP
AD1IS
—
—
—
CNIP
CNIS
0000
U1IP
U1IS
SPI3IP
SPI3IS
I2C3IP
I2C3IS
CMP2IP
CMP2IS
0000
—
—
28/12
27/11
I2C1IP
26/10
25/9
24/8
I2C1IS
U2IP
U2IS
SPI2IP
SPI2IS
I2C4IP
I2C4IS
—
—
—
—
—
—
20/4
19/3
18/2
17/1
16/0
15:0
—
—
—
CMP1IP
CMP1IS
—
—
—
PMPIP
PMPIS
0000
—
—
—
RTCCIP
RTCCIS
—
—
—
FSCMIP
FSCMIS
0000
U3IP
U3IS
SPI4IP
SPI4IS
I2C5IP
I2C5IS
15:0
—
—
—
I2C2IP
I2C2IS
—
—
—
0000
31:16
—
—
—
DMA3IP
DMA3IS
—
—
—
DMA2IP
DMA2IS
15:0
—
—
—
DMA1IP
DMA1IS
—
—
—
DMA0IP
DMA0IS
0000
31:16
—
—
—
DMA7IP(2)
DMA7IS(2)
—
—
—
DMA6IP(2)
DMA6IS(2)
0000
0000
15:0
—
—
—
DMA5IP(2)
DMA5IS(2)
—
—
—
DMA4IP(2)
DMA4IS(2)
0000
31:16
—
—
—
CAN2IP(2)
CAN2IS(2)
—
—
—
CAN1IP
CAN1IS
0000
15:0
—
—
—
USBIP
USBIS
—
—
—
FCEIP
FCEIS
0000
31:16
—
—
—
U5IP
U5IS
—
—
—
U6IP
U6IS
0000
15:0
—
—
—
U4IP
U4IS
—
—
—
ETHIP
ETHIS
0000
2009-2019 Microchip Technology Inc.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
This bit is unimplemented on PIC32MX764F128L device.
This register does not have associated CLR, SET, and INV registers.
2:
3:
0000
31:16
Legend:
1:
All Resets
Bit Range
Bits
PIC32MX5XX/6XX/7XX
DS60001156K-page 92
TABLE 7-7:
PIC32MX5XX/6XX/7XX
REGISTER 7-1:
Bit
Range
31:24
23:16
15:8
7:0
INTCON: INTERRUPT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
SS0
U-0
U-0
—
—
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
—
MVEC
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
TPC
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-17 Unimplemented: Read as ‘0’
bit 16
SS0: Single Vector Shadow Register Set bit
1 = Single vector is presented with a shadow register set
0 = Single vector is not presented with a shadow register set
bit 15-13 Unimplemented: Read as ‘0’
bit 12
MVEC: Multiple Vector Configuration bit
1 = Interrupt controller configured for Multi-vector mode
0 = Interrupt controller configured for Single-vector mode
bit 11
bit 10-8
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
TPC: Interrupt Proximity Timer Control bits
111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer
110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer
101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer
100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer
011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer
010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer
001 = Interrupts of group priority 1 start the Interrupt Proximity timer
000 = Disables Interrupt Proximity timer
Unimplemented: Read as ‘0’
INT4EP: External Interrupt 4 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
INT3EP: External Interrupt 3 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
INT2EP: External Interrupt 2 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
INT1EP: External Interrupt 1 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
INT0EP: External Interrupt 0 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
2009-2019 Microchip Technology Inc.
DS60001156K-page 93
PIC32MX5XX/6XX/7XX
REGISTER 7-2:
Bit
Range
31:24
23:16
15:8
7:0
INTSTAT: INTERRUPT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
RIPL(1)
R/W-0
R/W-0
R/W-0
VEC(1)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10-8
RIPL: Requested Priority Level bits(1)
111-000 = The priority level of the latest interrupt presented to the CPU
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
VEC: Interrupt Vector bits(1)
11111-00000 = The interrupt vector that is presented to the CPU
Note 1:
This value should only be used when the interrupt controller is configured for Single-vector mode.
REGISTER 7-3:
Bit
Range
31:24
23:16
15:8
7:0
TPTMR: TEMPORAL PROXIMITY TIMER REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TPTMR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TPTMR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TPTMR
R/W-0
TPTMR
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
TPTMR: Temporal Proximity Timer Reload bits
Used by the Temporal Proximity Timer as a reload value when the Temporal Proximity timer is triggered by
an interrupt event.
DS60001156K-page 94
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 7-4:
Bit
Range
31:24
23:16
15:8
7:0
IFSx: INTERRUPT FLAG STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS31
IFS30
IFS29
R/W-0
R/W-0
R/W-0
IFS28
IFS27
IFS26
IFS25
IFS24
R/W-0
R/W-0
R/W-0
R/W-0
IFS23
IFS22
IFS21
R/W-0
IFS20
IFS19
IFS18
IFS17
IFS16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS15
IFS14
IFS13
IFS12
IFS11
IFS10
IFS09
IFS08
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS07
IFS06
IFS05
IFS04
IFS03
IFS02
IFS01
IFS00
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
IFS31-IFS00: Interrupt Flag Status bits
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
This register represents a generic definition of the IFSx register. Refer to Table 7-1 for the exact bit
definitions.
REGISTER 7-5:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
Bit
31/23/15/7
IECx: INTERRUPT ENABLE CONTROL REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC31
IEC30
IEC29
IEC28
IEC27
IEC26
IEC25
IEC24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC23
IEC22
IEC21
IEC20
IEC19
IEC18
IEC17
IEC16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC15
IEC14
IEC13
IEC12
IEC11
IEC10
IEC09
IEC08
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC07
IEC06
IEC05
IEC04
IEC03
IEC02
IEC01
IEC00
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
Bit
24/16/8/0
x = Bit is unknown
IEC31-IEC00: Interrupt Enable bits
1 = Interrupt is enabled
0 = Interrupt is disabled
This register represents a generic definition of the IECx register. Refer to Table 7-1 for the exact bit
definitions.
2009-2019 Microchip Technology Inc.
DS60001156K-page 95
PIC32MX5XX/6XX/7XX
REGISTER 7-6:
Bit
Range
IPCx: INTERRUPT PRIORITY CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
31:24
23:16
15:8
7:0
Legend:
R = Readable bit
-n = Value at POR
Bit
Bit
28/20/12/4 27/19/11/3
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
IP03
R/W-0
R/W-0
IS03
R/W-0
IP02
R/W-0
R/W-0
R/W-0
IP00
R/W-0
IS02
R/W-0
IP01
R/W-0
R/W-0
R/W-0
R/W-0
IS01
R/W-0
R/W-0
R/W-0
IS00
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-26 IP03: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 25-24 IS03: Interrupt Sub-priority bits
11 = Interrupt sub-priority is 3
10 = Interrupt sub-priority is 2
01 = Interrupt sub-priority is 1
00 = Interrupt sub-priority is 0
bit 23-21 Unimplemented: Read as ‘0’
bit 20-18 IP02: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 17-16 IS02: Interrupt Sub-priority bits
11 = Interrupt sub-priority is 3
10 = Interrupt sub-priority is 2
01 = Interrupt sub-priority is 1
00 = Interrupt sub-priority is 0
bit 15-13 Unimplemented: Read as ‘0’
Note:
This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit
definitions.
DS60001156K-page 96
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 7-6:
IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED)
bit 12-10 IP01: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
bit 9-8
bit 7-5
bit 4-2
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
IS01: Interrupt Sub-priority bits
11 = Interrupt sub-priority is 3
10 = Interrupt sub-priority is 2
01 = Interrupt sub-priority is 1
00 = Interrupt sub-priority is 0
Unimplemented: Read as ‘0’
IP00: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
bit 1-0
Note:
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
IS00: Interrupt Sub-priority bits
11 = Interrupt sub-priority is 3
10 = Interrupt sub-priority is 2
01 = Interrupt sub-priority is 1
00 = Interrupt sub-priority is 0
This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit
definitions.
2009-2019 Microchip Technology Inc.
DS60001156K-page 97
PIC32MX5XX/6XX/7XX
NOTES:
DS60001156K-page 98
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
8.0
OSCILLATOR
CONFIGURATION
Note:
The Oscillator module has the following features:
• A total of four external and internal oscillator
options as clock sources
• On-chip PLL with user-selectable input divider,
multiplier and output divider to boost operating
frequency on select internal and external
oscillator sources
• On-chip user-selectable divisor postscaler on
select oscillator sources
• Software-controllable switching between
various clock sources
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and permits safe application recovery
or shutdown
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 6. “Oscillator”
(DS60001112) in the “PIC32 Family Reference Manual”, which is available from
the Microchip web site (www.microchip.com/PIC32).
• Dedicated On-Chip PLL for USB peripheral
Figure 8-1shows the Oscillator module block diagram.
FIGURE 8-1:
OSCILLATOR BLOCK DIAGRAM
USB PLL
UFIN
div x
RP(1)
C2(3)
4 MHz FIN 5 MHz
XTPLL, HSPLL,
FIN
ECPLL, FRCPLL
div x
div y
PLL
Enable
RS(1)
PLL Input Divider
FPLLIDIV
OSC2(4)
FRC
Oscillator
8 MHz typical
UFRCEN
UPLLEN
XT, HS, EC
RF(2)
XTAL
div 2
UFIN 4 MHz
UPLLIDIV
Primary Oscillator
To Internal
(POSC)
Logic
OSC1
C1(3)
USB Clock (48 MHz)
PLL x24
COSC
(001 = FRC,
011 = POSC)
PLL Output Divider
PLLODIV
PLL Multiplier
PLLMULT
div 16
TUN
Postscaler Peripherals
div x
PBCLK
Postscaler
PBDIV
FRC
FRC/16
CPU and Select Peripherals
FRCDIV
SYSCLK
FRCDIV
LPRC
LPRC
Oscillator
31.25 kHz typical
Secondary Oscillator (SOSC)
SOSCO
32.768 kHz
SOSC
COSC
SOSCEN and FSOSCEN
Clock Control Logic
Notes:
1.
2.
3.
4.
FSCM INT
Fail-Safe
Clock
Monitor
SOSCI
A series resistor, RS, may be required for AT strip cut crystals or eliminate
clipping. Alternately, to increase oscillator circuit gain, add a parallel
resistor, RP, with a value of 1 M
The internal feedback resistor, RF, is typically in the range of 2 to 10 M
Refer to the “PIC32 Family Reference Manual” Section 6. “Oscillator
Configuration” (DS60001112) for help determining the best oscillator
components.
PBCLK out is available on the OSC2 pin in certain clock modes.
2009-2019 Microchip Technology Inc.
FSCM Event
NOSC
COSC
FSCMEN
OSWEN
WDT, PWRT
Timer1, RTCC
DS60001156K-page 99
Control Registers
OSCTUN
Bit Range
Register
Name(1)
Bits
F000 OSCCON
F010
OSCILLATOR REGISTER MAP
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
—
15:0
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
PLLODIV
COSC
—
25/9
24/8
21/5
20/4
19/3
18/2
23/7
22/6
FRCDIV
—
SOSCRDY
—
NOSC
CLKLOCK
ULOCK
SLOCK
SLPEN
CF
UFRCEN
SOSCEN
OSWEN
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
PBDIV
17/1
16/0
PLLMULT
0000
TUN
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
1:
2:
All Resets(2)
Virtual Address
(BF80_#)
TABLE 8-1:
0000
PIC32MX5XX/6XX/7XX
DS60001156K-page 100
8.1
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 8-1:
Bit
Range
31:24
23:16
15:8
7:0
OSCCON: OSCILLATOR CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
R/W-y
—
—
U-0
R-0
—
U-0
R/W-y
—
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-y
R/W-0
R/W-0
R/W-1
R/W-y
R/W-y
PLLODIV
R-1
SOSCRDY PBDIVRDY
R-0
Bit
Bit
28/20/12/4 27/19/11/3
R-0
R/W-y
FRCDIV
PBDIV
R-0
U-0
COSC
R/W-y
R/W-y
PLLMULT
R/W-y
—
R/W-y
R/W-y
NOSC
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-y
R/W-0
CLKLOCK
ULOCK
SLOCK
SLPEN
CF
UFRCEN
SOSCEN
OSWEN
Legend:
R = Readable bit
-n = Value at POR
y = Value set from Configuration bits on POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-27 PLLODIV: Output Divider for PLL
111 = PLL output divided by 256
110 = PLL output divided by 64
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 1
bit 26-24 FRCDIV: Internal Fast RC (FRC) Oscillator Clock Divider bits
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2 (default setting)
000 = FRC divided by 1
bit 23
Unimplemented: Read as ‘0’
bit 22
SOSCRDY: Secondary Oscillator (SOSC) Ready Indicator bit
1 = Indicates that the Secondary Oscillator is running and is stable
0 = Secondary Oscillator is still warming up or is turned off
bit 21
PBDIVRDY: Peripheral Bus Clock (PBCLK) Divisor Ready bit
1 = PBDIV bits can be written
0 = PBDIV bits cannot be written
bit 20-19 PBDIV: Peripheral Bus Clock (PBCLK) Divisor bits
11 = PBCLK is SYSCLK divided by 8 (default)
10 = PBCLK is SYSCLK divided by 4
01 = PBCLK is SYSCLK divided by 2
00 = PBCLK is SYSCLK divided by 1
Note:
Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
2009-2019 Microchip Technology Inc.
DS60001156K-page 101
PIC32MX5XX/6XX/7XX
REGISTER 8-1:
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 18-16 PLLMULT: Phase-Locked Loop (PLL) Multiplier bits
111 = Clock is multiplied by 24
110 = Clock is multiplied by 21
101 = Clock is multiplied by 20
100 = Clock is multiplied by 19
011 = Clock is multiplied by 18
010 = Clock is multiplied by 17
001 = Clock is multiplied by 16
000 = Clock is multiplied by 15
bit 15
Unimplemented: Read as ‘0’
bit 14-12 COSC: Current Oscillator Selection bits
111 = Internal Fast RC (FRC) Oscillator divided by OSCCON bits
110 = Internal Fast RC (FRC) Oscillator divided by 16
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator (POSC) with PLL module (XTPLL, HSPLL or ECPLL)
010 = Primary Oscillator (POSC) (XT, HS or EC)
001 = Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL)
000 = Internal Fast RC (FRC) Oscillator
bit 11
Unimplemented: Read as ‘0’
bit 10-8 NOSC: New Oscillator Selection bits
111 = Internal Fast RC Oscillator (FRC) divided by OSCCON bits
110 = Internal Fast RC Oscillator (FRC) divided by 16
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL)
010 = Primary Oscillator (XT, HS or EC)
001 = Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL)
000 = Internal Fast Internal RC Oscillator (FRC)
bit 7
bit 6
bit 5
bit 4
bit 3
Note:
On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1).
CLKLOCK: Clock Selection Lock Enable bit
If clock switching and monitoring is disabled (FCKSM = 1x):
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified
If clock switching and monitoring is enabled (FCKSM = 0x):
Clock and PLL selections are never locked and may be modified.
ULOCK: USB PLL Lock Status bit
1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied
0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or
USB PLL is disabled
SLOCK: PLL Lock Status bit
1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
SLPEN: Sleep Mode Enable bit
1 = Device will enter Sleep mode when a WAIT instruction is executed
0 = Device will enter Idle mode when a WAIT instruction is executed
CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
DS60001156K-page 102
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 8-1:
bit 2
bit 1
bit 0
Note:
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
UFRCEN: USB FRC Clock Enable bit
1 = Enable FRC as the clock source for the USB clock source
0 = Use the Primary Oscillator or USB PLL as the USB clock source
SOSCEN: Secondary Oscillator (SOSC) Enable bit
1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator
OSWEN: Oscillator Switch Enable bit
1 = Initiate an oscillator switch to selection specified by NOSC bits
0 = Oscillator switch is complete
Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
2009-2019 Microchip Technology Inc.
DS60001156K-page 103
PIC32MX5XX/6XX/7XX
REGISTER 8-2:
Bit
Range
31:24
23:16
15:8
7:0
OSCTUN: FRC TUNING REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
R/W-0
(1)
TUN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-6
Unimplemented: Read as ‘0’
bit 5-0
TUN: FRC Oscillator Tuning bits(1)
100000 = Center frequency -12.5% for PIC32MX575/595/675/695/775/795 devices
100000 = Center frequency -1.5% for PIC32MX534/564/664/764 devices
100001 =
•
•
•
111111 =
000000 = Center frequency; Oscillator runs at nominal frequency (8 MHz)
000001 =
•
•
•
011110 =
011111 = Center frequency +12.5% for PIC32MX575/595/675/695/775/795 devices
011111 = Center frequency +1.5% for PIC32MX534/564/664/764 devices
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither
characterized nor tested.
Note:
Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
DS60001156K-page 104
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
9.0
PREFETCH CACHE
Note:
9.1
•
•
•
•
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
Cache” (DS60001119) in the “PIC32
Family Reference Manual”, which is available from the Microchip web site
(www.microchip.com/PIC32).
•
•
•
•
Prefetch cache increases performance for applications
executing out of the cacheable program Flash memory
regions by implementing instruction caching, constant
data caching and instruction prefetching.
FIGURE 9-1:
16 fully-associative lockable cache lines
16-byte cache lines
Up to four cache lines allocated to data
Two cache lines with address mask to hold
repeated instructions
Pseudo-LRU replacement policy
All cache lines are software writable
16-byte parallel memory fetch
Predictive instruction prefetch
A simplified block diagram of the Prefetch Cache
module is illustrated in Figure 9-1.
PREFETCH CACHE MODULE BLOCK DIAGRAM
CTRL
FSM
Cache Line
Tag Logic
CTRL
BMX/CPU
BMX/CPU
Features
Bus Control
Cache Control
Prefetch Control
Cache
Line
Address
Encode
Hit LRU
Miss LRU
RDATA
Hit Logic
Prefetch
Prefetch
CTRL
RDATA
PFM
2009-2019 Microchip Technology Inc.
DS60001156K-page 105
Control Registers
Virtual Address
(BF88_#)
TABLE 9-1:
4010 CHEACC
(1)
CHETAG(1)
4030 CHEMSK(1)
4040
CHEW0
4050
CHEW1
4060
CHEW2
4070
CHEW3
4080
CHELRU
4090
CHEHIT
40A0
CHEMIS
2009-2019 Microchip Technology Inc.
40C0 CHEPFABT
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16 CHEWEN
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16 LTAGBOOT
15:0
31:16
DCSZ
—
—
—
—
—
—
—
31:16
31:16
31:16
31:16
15:0
—
—
—
PREFEN
—
—
—
—
—
—
—
—
—
—
—
—
CHECOH 0000
PFMWS
—
—
0007
—
CHEIDX
—
—
—
—
—
—
—
—
—
—
00xx
LVALID
LLOCK
LTYPE
—
xxx2
—
—
—
—
—
0000
—
—
—
—
—
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
CHELRU
CHELRU
CHEHIT
CHEMIS
CHEPFABT
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
Reset value is dependent on DEVCFGx configuration.
1:
2:
0000
0000
LTAG
CHEW3
15:0
15:0
—
—
16/0
CHEW2
15:0
31:16
—
17/1
CHEW1
15:0
15:0
18/2
CHEW0
15:0
15:0
19/3
LMASK
31:16
31:16
20/4
LTAG
15:0
31:16
21/5
All Resets
Register
Name
Bit Range
Bits
4000 CHECON(1,2)
4020
PREFETCH REGISTER MAP
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
PIC32MX5XX/6XX/7XX
DS60001156K-page 106
9.2
PIC32MX5XX/6XX/7XX
REGISTER 9-1:
Bit
Range
31:24
23:16
15:8
7:0
CHECON: CACHE CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
CHECOH
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
U-0
R/W-1
—
—
PREFEN
—
DCSZ
R/W-1
R/W-1
PFMWS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-17 Unimplemented: Write ‘0’; ignore read
bit 16
CHECOH: Cache Coherency Setting on a PFM Program Cycle bit
1 = Invalidate all data and instruction lines
0 = Invalidate all data lnes and instruction lines that are not locked
bit 15-10 Unimplemented: Write ‘0’; ignore read
bit 9-8
DCSZ: Data Cache Size in Lines bits
Changing these bits causes all lines to be reinitialized to the “invalid” state.
11 = Enable data caching with a size of 4 lines
10 = Enable data caching with a size of 2 lines
01 = Enable data caching with a size of 1 line
00 = Disable data caching
bit 7-6
Unimplemented: Write ‘0’; ignore read
bit 5-4
PREFEN: Predictive Prefetch Enable bits
11 = Enable predictive prefetch for both cacheable and non-cacheable regions
10 = Enable predictive prefetch only for non-cacheable regions
01 = Enable predictive prefetch only for cacheable regions
00 = Disable predictive prefetch
bit 3
Unimplemented: Write ‘0’; ignore read
bit 2-0
PFMWS: PFM Access Time Defined in Terms of SYSLK Wait States bits
111 = Seven Wait states
110 = Six Wait states
101 = Five Wait states
100 = Four Wait states
011 = Three Wait states
010 = Two Wait states
001 = One Wait state
000 = Zero Wait state
2009-2019 Microchip Technology Inc.
DS60001156K-page 107
PIC32MX5XX/6XX/7XX
REGISTER 9-2:
Bit
Range
31:24
23:16
15:8
7:0
CHEACC: CACHE ACCESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
CHEWEN
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
CHEIDX
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
CHEWEN: Cache Access Enable bits
These bits apply to registers CHETAG, CHEMSK, CHEW0, CHEW1, CHEW2, and CHEW3.
1 = The cache line selected by CHEIDX is writeable
0 = The cache line selected by CHEIDX is not writeable
bit 30-4 Unimplemented: Write ‘0’; ignore read
bit 3-0
CHEIDX: Cache Line Index bits
The value selects the cache line for reading or writing.
DS60001156K-page 108
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 9-3:
Bit
Range
31:24
23:16
15:8
7:0
CHETAG: CACHE TAG REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
LTAGBOOT
—
—
—
—
—
—
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
LTAG
R/W-x
LTAG
R/W-x
R/W-x
R/W-x
R/W-x
LTAG
R/W-0
R/W-0
R/W-1
U-0
LVALID
LLOCK
LTYPE
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
LTAGBOOT: Line Tag Address Boot bit
1 = The line is in the 0x1D000000 (physical) area of memory
0 = The line is in the 0x1FC00000 (physical) area of memory
bit 30-24 Unimplemented: Write ‘0’; ignore read
bit 23-4
LTAG: Line Tag Address bits
LTAG bits are compared against physical address to determine a hit. Because its address range and
position of PFM in kernel space and user space, the LTAG PFM address is identical for virtual addresses,
(system) physical addresses, and PFM physical addresses.
bit 3
LVALID: Line Valid bit
1 = The line is valid and is compared to the physical address for hit detection
0 = The line is not valid and is not compared to the physical address for hit detection
bit 2
LLOCK: Line Lock bit
1 = The line is locked and will not be replaced
0 = The line is not locked and can be replaced
bit 1
LTYPE: Line Type bit
1 = The line caches instruction words
0 = The line caches data words
bit 0
Unimplemented: Write ‘0’; ignore read
2009-2019 Microchip Technology Inc.
DS60001156K-page 109
PIC32MX5XX/6XX/7XX
REGISTER 9-4:
Bit
Range
31:24
23:16
15:8
7:0
CHEMSK: CACHE TAG MASK REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LMASK
R/W-0
R/W-0
R/W-0
LMASK
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Write ‘0’; ignore read
bit 15-5
LMASK: Line Mask bits
1 = Enables mask logic to force a match on the corresponding bit position in LTAG bits
(CHETAG) and the physical address
0 = Only writeable for values of CHEIDX bits (CHEACC) equal to 0x0A and 0x0B
(disables mask logic)
bit 4-0
Unimplemented: Write ‘0’; ignore read
REGISTER 9-5:
Bit
Range
31:24
23:16
15:8
7:0
CHEW0: CACHE WORD 0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEW0
R/W-x
R/W-x
CHEW0
R/W-x
CHEW0
R/W-x
CHEW0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 CHEW0: Word 0 of the cache line selected by CHEIDX bits (CHEACC)
Readable only if the device is not code-protected.
DS60001156K-page 110
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 9-6:
Bit
Range
31:24
23:16
15:8
7:0
CHEW1: CACHE WORD 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-x
R/W-x
R/W-x
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEW1
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEW1
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEW1
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEW1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 CHEW1: Word 1 of the cache line selected by CHEIDX bits (CHEACC)
Readable only if the device is not code-protected.
REGISTER 9-7:
Bit
Range
31:24
23:16
15:8
7:0
CHEW2: CACHE WORD 2
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEW2
R/W-x
R/W-x
CHEW2
R/W-x
CHEW2
R/W-x
CHEW2
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 CHEW2: Word 2 of the cache line selected by CHEIDX bits (CHEACC)
Readable only if the device is not code-protected.
2009-2019 Microchip Technology Inc.
DS60001156K-page 111
PIC32MX5XX/6XX/7XX
REGISTER 9-8:
Bit
Range
31:24
23:16
15:8
7:0
CHEW3: CACHE WORD 3
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-x
R/W-x
R/W-x
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEW3
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEW3
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEW3
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEW3
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 CHEW3: Word 3 of the cache line selected by CHEIDX bits (CHEACC)
Readable only if the device is not code-protected.
Note:
This register is a window into the cache data array and is only readable if the device is not code-protected.
REGISTER 9-9:
Bit
Range
31:24
23:16
15:8
7:0
CHELRU: CACHE LRU REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
CHELRU
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHELRU
R-0
R-0
R-0
R-0
R-0
CHELRU
R-0
R-0
R-0
R-0
R-0
CHELRU
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-25 Unimplemented: Write ‘0’; ignore read
bit 24-0
CHELRU: Cache Least Recently Used State Encoding bits
Indicates the pseudo-LRU state of the cache.
DS60001156K-page 112
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 9-10:
Bit
Range
31:24
23:16
15:8
7:0
CHEHIT: CACHE HIT STATISTICS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-x
R/W-x
R/W-x
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEHIT
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEHIT
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEHIT
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEHIT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 CHEHIT: Cache Hit Count bits
Incremented each time the processor issues an instruction fetch or load that hits the prefetch cache from a
cacheable region. Non-cacheable accesses do not modify this value.
REGISTER 9-11:
Bit
Range
31:24
23:16
15:8
7:0
CHEMIS: CACHE MISS STATISTICS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEMIS
R/W-x
R/W-x
CHEMIS
R/W-x
CHEMIS
R/W-x
CHEMIS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 CHEMIS: Cache Miss Count bits
Incremented each time the processor issues an instruction fetch from a cacheable region that misses the
prefetch cache. Non-cacheable accesses do not modify this value.
2009-2019 Microchip Technology Inc.
DS60001156K-page 113
PIC32MX5XX/6XX/7XX
REGISTER 9-12:
Bit
Range
31:24
23:16
15:8
7:0
CHEPFABT: PREFETCH CACHE ABORT STATISTICS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-x
R/W-x
R/W-x
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEPFABT
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEPFABT
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEPFABT
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
CHEPFABT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 CHEPFABT: Prefab Abort Count bits
Incremented each time an automatic prefetch cache is aborted due to a non-sequential instruction fetch, load
or store.
DS60001156K-page 114
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
10.0
Note:
DIRECT MEMORY ACCESS
(DMA) CONTROLLER
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 31. “Direct Memory
Access
(DMA)
Controller”
(DS60001117) in the “PIC32 Family Reference Manual”, which is available from
the
Microchip
web
site
(www.microchip.com/PIC32).
The Direct Memory Access (DMA) controller is a bus
master module useful for data transfers between
different devices without CPU intervention. The source
and destination of a DMA transfer can be any of the
memory mapped modules existent in the PIC32 (such
as SPI, UART, PMP, etc.) or memory itself.
Following are some of the key features of the DMA
controller module:
• Four identical channels, each featuring:
- Auto-increment source and destination address
registers
- Source and destination pointers
- Memory to memory and memory to
peripheral transfers
FIGURE 10-1:
INT Controller
Peripheral Bus
• Automatic word-size detection:
- Transfer granularity, down to byte level
- Bytes need not be word-aligned at source and
destination
• Fixed priority channel arbitration
• Flexible DMA channel operating modes:
- Manual (software) or automatic (interrupt) DMA
requests
- One-Shot or Auto-Repeat Block Transfer modes
- Channel-to-channel chaining
• Flexible DMA requests:
- A DMA request can be selected from any of the
peripheral interrupt sources
- Each channel can select any (appropriate)
observable interrupt as its DMA request source
- A DMA transfer abort can be selected from any of
the peripheral interrupt sources
- Pattern (data) match transfer termination
• Multiple DMA channel status interrupts:
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half full
- DMA transfer aborted due to an external event
- Invalid DMA address generated
• DMA debug support features:
- Most recent address accessed by a DMA channel
- Most recent DMA channel to transfer data
• CRC Generation module:
- CRC module can be assigned to any of the
available channels
- CRC module is highly configurable
DMA BLOCK DIAGRAM
System IRQ
Address Decoder
SE
Channel 0 Control
I0
Channel 1 Control
I1
L
Y
Bus Interface
Device Bus + Bus Arbitration
I2
Global Control
(DMACON)
Channel ‘n’ Control
In
L
SE
Channel Priority
Arbitration
2009-2019 Microchip Technology Inc.
DS60001156K-page 115
Control Registers
Virtual Address
(BF88_#)
TABLE 10-1:
DMASTAT
3020 DMAADDR
31/15
30/14
29/13
31:16
—
—
—
15:0
ON
—
—
31:16
—
—
—
—
15:0
—
—
—
—
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RDWR
SUSPEND DMABUSY
31:16
DMACH(2)
0000
DMAADDR
15:0
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
DMACH bit is not available on PIC32MX534/564/664/764 devices.
Virtual Address
(BF88_#)
TABLE 10-2:
0000
0000
Legend:
1:
2:
All Resets
Bit Range
Register
Name
Bits
3000 DMACON(1)
DMA CRC REGISTER MAP(1)
3030 DCRCCON
3040 DCRCDATA
3050 DCRCXOR
Bit Range
Register
Name(1)
Bits
31/15
30/14
31:16
—
—
15:0
—
—
31:16
15:0
31:16
2009-2019 Microchip Technology Inc.
15:0
29/13
28/12
BYTO
—
27/11
WBO
26/10
25/9
24/8
—
—
BITO
PLEN
23/7
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
—
CRCEN
CRCAPP
CRCTYP
—
—
17/1
16/0
—
—
CRCCH
DCRCDATA
DCRCXOR
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
3010
DMA GLOBAL REGISTER MAP
0000
0000
0000
0000
0000
0000
PIC32MX5XX/6XX/7XX
DS60001156K-page 116
10.1
Virtual Address
(BF88_#)
3060 DCH0CON
3070 DCH0ECON
3080
3090
DCH0INT
DCH0SSA
30A0 DCH0DSA
30B0 DCH0SSIZ
30C0 DCH0DSIZ
30D0 DCH0SPTR
30F0 DCH0CSIZ
3100 DCH0CPTR
DCH0DAT
3120 DCH1CON
3130 DCH1ECON
3140
DS60001156K-page 117
3150
DCH1INT
DCH1SSA
3160 DCH1DSA
3170 DCH1SSIZ
30/14
29/13
28/12
27/11
26/10
25/9
31:16
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
CHSIRQ
15:0
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
18/2
17/1
16/0
—
—
CHCHN
CHAEN
—
—
—
—
—
CHEDET
CHPRI
CHAIRQ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
0000
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
CHSIRQ
15:0
31:16
31:16
CHPRI
CHAIRQ
—
—
—
—
—
—
—
—
—
0000
00FF
0000
0000
0000
CHDSA
15:0
15:0
0000
CHSSA
15:0
31:16
CHPDAT
0000
—
—
—
—
—
—
—
CHSSIZ
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
2:
0000
0000
Legend:
1:
0000
0000
CHCPTR
31:16
0000
0000
CHCSIZ
—
0000
00FF
CHDPTR
15:0
31:16
19/3
CHSPTR
15:0
31:16
20/4
CHDSIZ
15:0
31:16
21/5
CHSSIZ
15:0
31:16
22/6
CHDSA
15:0
31:16
23/7
CHSSA
15:0
31:16
24/8
All Resets
Bit Range
31/15
0000
0000
PIC32MX5XX/6XX/7XX
30E0 DCH0DPTR
3110
DMA CHANNELS 0-7 REGISTER MAP
Bits
Register
Name(1)
2009-2019 Microchip Technology Inc.
TABLE 10-3:
Virtual Address
(BF88_#)
DMA CHANNELS 0-7 REGISTER MAP (CONTINUED)
3180 DCH1DSIZ
3190 DCH1SPTR
31A0 DCH1DPTR
31B0 DCH1CSIZ
31C0 DCH1CPTR
31D0 DCH1DAT
31E0 DCH2CON
31F0 DCH2ECON
3200
DCH2INT
3210
DCH2SSA
3220 DCH2DSA
3230 DCH2SSIZ
3240 DCH2DSIZ
2009-2019 Microchip Technology Inc.
3250 DCH2SPTR
3260 DCH2DPTR
3270 DCH2CSIZ
3280 DCH2CPTR
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
0000
0000
CHCPTR
31:16
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
15:0
CHSIRQ
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
0000
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
0000
0000
0000
CHCPTR
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
2:
0000
0000
CHCSIZ
—
0000
0000
CHDPTR
15:0
31:16
0000
CHSPTR
15:0
31:16
0000
CHDSIZ
15:0
31:16
—
0000
00FF
CHSSIZ
15:0
31:16
CHPRI
CHAIRQ
CHDSA
15:0
31:16
0000
CHSSA
15:0
31:16
CHPDAT
Legend:
1:
0000
0000
CHCSIZ
—
0000
0000
CHDPTR
15:0
31:16
23/7
CHSPTR
15:0
31:16
24/8
CHDSIZ
—
All Resets
Bit Range
Register
Name(1)
Bits
0000
0000
PIC32MX5XX/6XX/7XX
DS60001156K-page 118
TABLE 10-3:
Virtual Address
(BF88_#)
Register
Name(1)
3290
DCH2DAT
32B0 DCH3ECON
DCH3INT
32D0 DCH3SSA
32E0 DCH3DSA
32F0 DCH3SSIZ
3300 DCH3DSIZ
3320 DCH3DPTR
3330 DCH3CSIZ
3340 DCH3CPTR
3350
DCH3DAT
3360 DCH4CON
3370 DCH4ECON
DS60001156K-page 119
3380
3390
DCH4INT
DCH4SSA
33A0 DCH4DSA
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
15:0
CHSIRQ
31:16
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
0000
—
CHEDET
0000
CHPRI
CHAIRQ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
15:0
31:16
15:0
31:16
15:0
CHSIRQ
CHPDAT
0000
CHPRI
CHAIRQ
0000
00FF
CHSSA
CHDSA
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
2:
0000
0000
Legend:
1:
0000
0000
CHCPTR
31:16
0000
0000
CHCSIZ
—
0000
00FF
CHDPTR
15:0
31:16
—
CHPDAT
CHSPTR
15:0
31:16
16/0
CHDSIZ
15:0
31:16
17/1
CHSSIZ
15:0
31:16
18/2
CHDSA
15:0
31:16
19/3
CHSSA
15:0
31:16
20/4
0000
0000
0000
0000
PIC32MX5XX/6XX/7XX
3310 DCH3SPTR
All Resets
Bits
32A0 DCH3CON
32C0
DMA CHANNELS 0-7 REGISTER MAP (CONTINUED)
Bit Range
2009-2019 Microchip Technology Inc.
TABLE 10-3:
Virtual Address
(BF88_#)
33C0 DCH4DSIZ
33D0 DCH4SPTR
33E0 DCH4DPTR
33F0 DCH4CSIZ
3400 DCH4CPTR
DCH4DAT
3420 DCH5CON
3430 DCH5ECON
3440
DCH5INT
3450
DCH5SSA
3460
DCH5DSA
3470 DCH5SSIZ
2009-2019 Microchip Technology Inc.
3480 DCH5DSIZ
3490 DCH5SPTR
34A0 DCH5DPTR
34B0 DCH5CSIZ
34C0 DCH5CPTR
Legend:
Note
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
0000
15:0
31:16
CHSSIZ15:0>
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
0000
0000
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
15:0
CHSIRQ
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
2:
0000
0000
0000
0000
0000
CHCSIZ
—
0000
0000
CHDPTR
15:0
31:16
0000
CHSPTR
15:0
31:16
0000
0000
CHDSIZ
15:0
31:16
—
0000
00FF
CHSSIZ
15:0
31:16
CHPRI
CHAIRQ
CHDSA
15:0
31:16
0000
CHSSA
15:0
31:16
CHPDAT
0000
CHCPTR
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
0000
0000
CHCPTR
31:16
0000
0000
CHCSIZ
—
0000
0000
CHDPTR
15:0
31:16
—
CHSPTR
15:0
31:16
—
CHDSIZ
15:0
31:16
All Resets
Bit Range
Register
Name(1)
Bits
33B0 DCH4SSIZ
3410
DMA CHANNELS 0-7 REGISTER MAP (CONTINUED)
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
0000
0000
PIC32MX5XX/6XX/7XX
DS60001156K-page 120
TABLE 10-3:
Virtual Address
(BF88_#)
34D0 DCH5DAT
34E0 DCH6CON
34F0 DCH6ECON
3500
3510
DCH6INT
DCH6SSA
3520 DCH6DSA
3530 DCH6SSIZ
3540 DCH6DSIZ
3560 DCH6DPTR
3570 DCH6CSIZ
3580 DCH6CPTR
DCH6DAT
35A0 DCH7CON
35B0 DCH7ECON
DS60001156K-page 121
35C0
DCH7INT
35D0 DCH7SSA
35E0 DCH7DSA
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
15:0
CHSIRQ
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
0000
—
CHEDET
0000
CHPRI
CHAIRQ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
0000
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
15:0
31:16
15:0
31:16
15:0
CHSIRQ
CHPDAT
0000
CHPRI
CHAIRQ
0000
00FF
CHSSA
CHDSA
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
2:
0000
0000
CHCPTR
31:16
0000
0000
CHCSIZ
—
0000
00FF
CHDPTR
15:0
31:16
—
CHPDAT
CHSPTR
15:0
31:16
16/0
CHDSIZ
15:0
31:16
17/1
CHSSIZ
15:0
31:16
18/2
CHDSA
15:0
31:16
19/3
CHSSA
15:0
31:16
20/4
Note
1:
All Resets
Bit Range
31/15
0000
0000
0000
0000
PIC32MX5XX/6XX/7XX
3550 DCH6SPTR
3590
DMA CHANNELS 0-7 REGISTER MAP (CONTINUED)
Bits
Register
Name(1)
2009-2019 Microchip Technology Inc.
TABLE 10-3:
Virtual Address
(BF88_#)
3600 DCH7DSIZ
3610 DCH7SPTR
3620 DCH7DPTR
3630 DCH7CSIZ
3640 DCH7CPTR
DCH7DAT
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
CHPDAT
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
1:
2:
0000
0000
CHCPTR
31:16
0000
0000
CHCSIZ
—
0000
0000
CHDPTR
15:0
31:16
21/5
CHSPTR
15:0
31:16
22/6
CHDSIZ
15:0
31:16
23/7
CHSSIZ
15:0
31:16
24/8
All Resets
Bit Range
Register
Name(1)
Bits
35F0 DCH7SSIZ
3650
DMA CHANNELS 0-7 REGISTER MAP (CONTINUED)
0000
PIC32MX5XX/6XX/7XX
DS60001156K-page 122
TABLE 10-3:
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 10-1:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
DMACON: DMA CONTROLLER CONTROL REGISTER
Bit
Bit
30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
U-0
U-0
ON(1)
—
—
SUSPEND
DMABUSY
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: DMA On bit(1)
1 = DMA module is enabled
0 = DMA module is disabled
bit 14-13 Unimplemented: Read as ‘0’
bit 12
SUSPEND: DMA Suspend bit
1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus
0 = DMA operates normally
bit 11
DMABUSY: DMA Module Busy bit
1 = DMA module is active
0 = DMA module is disabled and not actively transferring data
bit 10-0
Unimplemented: Read as ‘0’
Note 1:
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2009-2019 Microchip Technology Inc.
DS60001156K-page 123
PIC32MX5XX/6XX/7XX
REGISTER 10-2:
Bit
Range
31:24
23:16
15:8
7:0
DMASTAT: DMA STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
—
—
—
—
RDWR
DMACH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3
RDWR: Read/Write Status bit
1 = Last DMA bus access was a read
0 = Last DMA bus access was a write
bit 2-0
DMACH: DMA Channel bits
These bits contain the value of the most recent active DMA channel.
REGISTER 10-3:
Bit
Range
31:24
23:16
15:8
7:0
DMAADDR: DMA ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DMAADDR
R-0
R-0
DMAADDR
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DMAADDR
R-0
R-0
DMAADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DMAADDR: DMA Module Address bits
These bits contain the address of the most recent DMA access.
DS60001156K-page 124
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 10-4:
Bit
Range
31:24
23:16
15:8
7:0
DCRCCON: DMA CRC CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
R/W-0
R/W-0
BYTO
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
R/W-0
R/W-0
(1)
—
—
WBO
—
—
BITO
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
R/W-0
U-0
U-0
PLEN
CRCEN
CRCAPP(1)
CRCTYP
—
—
R/W-0
CRCCH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 BYTO: CRC Byte Order Selection bits
11 = Endian byte swap on half-word boundaries (source half-word order with reverse source byte order
per half-word)
10 = Swap half-words on word boundaries (reverse source half-word order with source byte order
per half-word)
01 = Endian byte swap on word boundaries (reverse source byte order)
00 = No swapping (source byte order)
bit 27
WBO: CRC Write Byte Order Selection bit(1)
1 = Source data is written to the destination re-ordered as defined by BYTO
0 = Source data is written to the destination unaltered
bit 26-25 Unimplemented: Read as ‘0’
bit 24
BITO: CRC Bit Order Selection bit
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
1 = The IP header checksum is calculated Least Significant bit (LSb) first (reflected)
0 = The IP header checksum is calculated Most Significant bit (MSb) first (not reflected)
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
1 = The LFSR CRC is calculated Least Significant bit first (reflected)
0 = The LFSR CRC is calculated Most Significant bit first (not reflected)
bit 23-13 Unimplemented: Read as ‘0’
bit 12-8
PLEN: Polynomial Length bits(1)
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
These bits are unused.
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
Denotes the length of the polynomial – 1.
bit 7
CRCEN: CRC Enable bit
1 = CRC module is enabled and channel transfers are routed through the CRC module
0 = CRC module is disabled and channel transfers proceed normally
Note 1:
When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
2009-2019 Microchip Technology Inc.
DS60001156K-page 125
PIC32MX5XX/6XX/7XX
REGISTER 10-4:
DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED)
bit 6
CRCAPP: CRC Append Mode bit(1)
1 = The DMA transfers data from the source into the CRC but not to the destination. When a block transfer
completes the DMA writes the calculated CRC value to the location given by CHxDSA
0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the
destination
bit 5
CRCTYP: CRC Type Selection bit
1 = The CRC module will calculate an IP header checksum
0 = The CRC module will calculate a LFSR CRC
bit 4-3
Unimplemented: Read as ‘0’
bit 2-0
CRCCH: CRC Channel Select bits
111 = CRC is assigned to Channel 7
110 = CRC is assigned to Channel 6
101 = CRC is assigned to Channel 5
100 = CRC is assigned to Channel 4
011 = CRC is assigned to Channel 3
010 = CRC is assigned to Channel 2
001 = CRC is assigned to Channel 1
000 = CRC is assigned to Channel 0
Note 1:
When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
DS60001156K-page 126
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 10-5:
Bit
Range
31:24
23:16
15:8
7:0
DCRCDATA: DMA CRC DATA REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA
R/W-0
R/W-0
DCRCDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DCRCDATA: CRC Data Register bits
Writing to this register will seed the CRC generator. Reading from this register will return the current value of
the CRC. Bits greater than PLEN will return ‘0’ on any read.
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written
to this register is converted and read back in 1’s complement form (current IP header checksum value).
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
Bits greater than PLEN will return ‘0’ on any read.
REGISTER 10-6:
Bit
Range
31:24
23:16
15:8
7:0
DCRCXOR: DMA CRCXOR ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR
R/W-0
R/W-0
DCRCXOR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DCRCXOR: CRC XOR Register bits
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
This register is unused.
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
1 = Enable the XOR input to the Shift register
0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in
the register
2009-2019 Microchip Technology Inc.
DS60001156K-page 127
PIC32MX5XX/6XX/7XX
REGISTER 10-7:
Bit
Range
31:24
23:16
15:8
7:0
DCHxCON: DMA CHANNEL ‘x’ CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
CHBUSY
—
—
—
—
—
—
CHCHNS(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R-0
CHEN(2)
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
CHBUSY: Channel Busy bit
1 = Channel is active or has been enabled
0 = Channel is inactive or has been disabled
bit 14-9
Unimplemented: Read as ‘0’
bit 8
CHCHNS: Chain Channel Selection bit(1)
1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
bit 7
CHEN: Channel Enable bit(2)
1 = Channel is enabled
0 = Channel is disabled
bit 6
CHAED: Channel Allow Events If Disabled bit
1 = Channel start/abort events will be registered, even if the channel is disabled
0 = Channel start/abort events will be ignored if the channel is disabled
bit
CHCHN: Channel Chain Enable bit
1 = Allow channel to be chained
0 = Do not allow channel to be chained
bit 4
CHAEN: Channel Automatic Enable bit
1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete
0 = Channel is disabled on block transfer complete
bit 3
Unimplemented: Read as ‘0’
bit 2
CHEDET: Channel Event Detected bit
1 = An event has been detected
0 = No events have been detected
bit 1-0
CHPRI: Channel Priority bits
11 = Channel has priority 3 (highest)
10 = Channel has priority 2
01 = Channel has priority 1
00 = Channel has priority 0
Note 1:
2:
The chain selection bit takes effect when chaining is enabled (CHCHN = 1).
When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.
DS60001156K-page 128
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 10-8:
Bit
Range
31:24
23:16
DCHxECON: DMA CHANNEL ‘x’ EVENT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
(1)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CHAIRQ
15:8
R/W-1
CHSIRQ(1)
7:0
S-0
S-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
Legend:
R = Readable bit
-n = Value at POR
S = Settable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 CHAIRQ: Channel Transfer Abort IRQ bits(1)
11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag
•
•
•
bit 15-8
00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag
00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag
CHSIRQ: Channel Transfer Start IRQ bits(1)
11111111 = Interrupt 255 will initiate a DMA transfer
•
•
•
bit 2-0
00000001 = Interrupt 1 will initiate a DMA transfer
00000000 = Interrupt 0 will initiate a DMA transfer
CFORCE: DMA Forced Transfer bit
1 = A DMA transfer is forced to begin when this bit is written to a ‘1’
0 = This bit always reads ‘0’
CABORT: DMA Abort Transfer bit
1 = A DMA transfer is aborted when this bit is written to a ‘1’
0 = This bit always reads ‘0’
PATEN: Channel Pattern Match Abort Enable bit
1 = Abort transfer and clear CHEN on pattern match
0 = Pattern match is disabled
SIRQEN: Channel Start IRQ Enable bit
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer
AIRQEN: Channel Abort IRQ Enable bit
1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs
0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer
Unimplemented: Read as ‘0’
Note 1:
See Table 7-1: “Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources.
bit 7
bit 6
bit 5
bit 4
bit 3
2009-2019 Microchip Technology Inc.
DS60001156K-page 129
PIC32MX5XX/6XX/7XX
REGISTER 10-9:
Bit
Range
31:24
23:16
15:8
7:0
DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23
CHSDIE: Channel Source Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 22
CHSHIE: Channel Source Half Empty Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 21
CHDDIE: Channel Destination Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 20
CHDHIE: Channel Destination Half Full Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 19
CHBCIE: Channel Block Transfer Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 18
CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 17
CHTAIE: Channel Transfer Abort Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 16
CHERIE: Channel Address Error Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 15-8
Unimplemented: Read as ‘0’
bit 7
CHSDIF: Channel Source Done Interrupt Flag bit
1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
0 = No interrupt is pending
bit 6
CHSHIF: Channel Source Half Empty Interrupt Flag bit
1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
0 = No interrupt is pending
DS60001156K-page 130
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 10-9:
DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER (CONTINUED)
bit 5
CHDDIF: Channel Destination Done Interrupt Flag bit
1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
0 = No interrupt is pending
bit 4
CHDHIF: Channel Destination Half Full Interrupt Flag bit
1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
0 = No interrupt is pending
bit 3
CHBCIF: Channel Block Transfer Complete Interrupt Flag bit
1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a
pattern match event occurs
0 = No interrupt is pending
bit 2
CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit
1 = A cell transfer has been completed (CHCSIZ bytes have been transferred)
0 = No interrupt is pending
bit 1
CHTAIF: Channel Transfer Abort Interrupt Flag bit
1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
0 = No interrupt is pending
bit 0
CHERIF: Channel Address Error Interrupt Flag bit
1 = A channel address error has been detected (either the source or the destination address is invalid)
0 = No interrupt is pending
2009-2019 Microchip Technology Inc.
DS60001156K-page 131
PIC32MX5XX/6XX/7XX
REGISTER 10-10: DCHxSSA: DMA CHANNEL ‘x’ SOURCE START ADDRESS REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
R/W-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA
23:16
R/W-0
R/W-0
CHSSA
15:8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA
7:0
R/W-0
CHSSA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
CHSSA Channel Source Start Address bits
Channel source start address.
Note: This must be the physical address of the source.
REGISTER 10-11: DCHxDSA: DMA CHANNEL ‘x’ DESTINATION START ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSA
R/W-0
R/W-0
CHDSA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 CHDSA: Channel Destination Start Address bits
Channel destination start address.
Note: This must be the physical address of the destination.
DS60001156K-page 132
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 10-12: DCHxSSIZ: DMA CHANNEL ‘x’ SOURCE SIZE REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSIZ
7:0
R/W-0
CHSSIZ
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHSSIZ: Channel Source Size bits
1111111111111111 = 65,535 byte source size
•
•
•
0000000000000010 = 2 byte source size
0000000000000001 = 1 byte source size
0000000000000000 = 65,536 byte source size
REGISTER 10-13: DCHxDSIZ: DMA CHANNEL ‘x’ DESTINATION SIZE REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSIZ
7:0
R/W-0
CHDSIZ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CHDSIZ: Channel Destination Size bits
1111111111111111 = 65,535 byte destination size
•
•
•
0000000000000010 = 2 byte destination size
0000000000000001 = 1 byte destination size
0000000000000000 = 65,536 byte destination size
2009-2019 Microchip Technology Inc.
DS60001156K-page 133
PIC32MX5XX/6XX/7XX
REGISTER 10-14: DCHxSPTR: DMA CHANNEL ‘x’ SOURCE POINTER REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHSPTR
7:0
R-0
R-0
CHSPTR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHSPTR: Channel Source Pointer bits
1111111111111111 = Points to byte 65,535 of the source
•
•
•
0000000000000001 = Points to byte 1 of the source
0000000000000000 = Points to byte 0 of the source
Note:
When in Pattern Detect mode, this register is reset on a pattern detect.
REGISTER 10-15: DCHxDPTR: DMA CHANNEL ‘x’ DESTINATION POINTER REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHDPTR
7:0
R-0
R-0
CHDPTR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CHDPTR: Channel Destination Pointer bits
1111111111111111 = Points to byte 65,535 of the destination
•
•
•
0000000000000001 = Points to byte 1 of the destination
0000000000000000 = Points to byte 0 of the destination
DS60001156K-page 134
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 10-16: DCHxCSIZ: DMA CHANNEL ‘x’ CELL-SIZE REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHCSIZ
7:0
R/W-0
CHCSIZ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCSIZ: Channel Cell-Size bits
1111111111111111 = 65,535 bytes transferred on an event
•
•
•
0000000000000010 = 2 bytes transferred on an event
0000000000000001 = 1 byte transferred on an event
0000000000000000 = 65,536 bytes transferred on an event
REGISTER 10-17: DCHxCPTR: DMA CHANNEL ‘x’ CELL POINTER REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHCPTR
7:0
R-0
R-0
CHCPTR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCPTR: Channel Cell Progress Pointer bits
1111111111111111 = 65,535 bytes have been transferred since the last event
•
•
•
0000000000000001 = 1 byte has been transferred since the last event
0000000000000000 = 0 bytes have been transferred since the last event
Note:
When in Pattern Detect mode, this register is reset on a pattern detect.
2009-2019 Microchip Technology Inc.
DS60001156K-page 135
PIC32MX5XX/6XX/7XX
REGISTER 10-18: DCHxDAT: DMA CHANNEL ‘x’ PATTERN DATA REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHPDAT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0
CHPDAT: Channel Data Register bits
Pattern Terminate mode:
Data to be matched must be stored in this register to allow terminate on match.
All other modes:
Unused.
DS60001156K-page 136
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
11.0
Note:
USB ON-THE-GO (OTG)
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 27. “USB On-TheGo (OTG)” (DS60001126) in the “PIC32
Family Reference Manual”, which is available from the Microchip web site
(www.microchip.com/PIC32).
The Universal Serial Bus (USB) module contains
analog and digital components to provide a USB 2.0
full-speed and low-speed embedded Host, full-speed
Device or OTG implementation with a minimum of
external components. This module in Host mode is
intended for use as an embedded host and therefore
does not implement a UHCI or OHCI controller.
The USB module consists of the clock generator, the
USB voltage comparators, the transceiver, the Serial
Interface Engine (SIE), a dedicated USB DMA controller, pull-up and pull-down resistors, and the register
interface. A block diagram of the PIC32 USB OTG
module is presented in Figure 11-1.
The clock generator provides the 48 MHz clock
required for USB full-speed and low-speed communication. The voltage comparators monitor the voltage on
the VBUS pin to determine the state of the bus. The
transceiver provides the analog translation between
the USB bus and the digital logic. The SIE is a state
machine that transfers data to and from the endpoint
buffers and generates the hardware protocol for data
transfers. The USB DMA controller transfers data
between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the
need for external signaling components. The register
interface allows the CPU to configure and
communicate with the module.
The USB module includes the following features:
•
•
•
•
•
•
•
•
•
USB Full-speed support for host and device
Low-speed host support
USB OTG support
Integrated signaling resistors
Integrated analog comparators for VBUS
monitoring
Integrated USB transceiver
Transaction handshaking performed by hardware
Endpoint buffering anywhere in system RAM
Integrated DMA to access system RAM and Flash
Note:
2009-2019 Microchip Technology Inc.
The implementation and use of the USB
specifications, as well as other third party
specifications or technologies, may
require licensing; including, but not limited
to, USB Implementers Forum, Inc. (also
referred to as USB-IF). The user is fully
responsible
for
investigating
and
satisfying any applicable licensing
obligations.
DS60001156K-page 137
PIC32MX5XX/6XX/7XX
FIGURE 11-1:
PIC32MX5XX/6XX/7XX FAMILY USB INTERFACE DIAGRAM
USBEN
FRC
Oscillator
8 MHz Typical
USB Suspend
CPU Clock Not POSC
Sleep
TUN(4)
Primary Oscillator
(POSC)
Div x
OSC1
UFIN(5)
PLL
UPLLEN(6)
UPLLIDIV(6)
USB Suspend
OSC2
Div 2
UFRCEN(3)
To Clock Generator for Core and Peripherals
Sleep or Idle
(PB Out)(1)
USB Module
SRP Charge
Bus
SRP Discharge
USB
Voltage
Comparators
48 MHz USB Clock(7)
Full-Speed Pull-up
D+(2)
Registers
and
Control
Interface
Host Pull-down
SIE
Transceiver
Low-Speed Pull-up
D-(2)
DMA
System
RAM
Host Pull-down
ID Pull-up
ID(8)
VBUSON(8)
Transceiver Power 3.3V
VUSB3V3
Note 1:
2:
3:
4:
5:
6:
7:
8:
PB clock is only available on this pin for select EC modes.
Pins can be used as digital inputs when USB is not enabled.
This bit field is contained in the OSCCON register.
This bit field is contained in the OSCTRM register.
USB PLL UFIN requirements: 4 MHz.
This bit field is contained in the DEVCFG2 register.
A 48 MHz clock is required for proper USB operation.
Pins can be used as GPIO when the USB module is disabled.
DS60001156K-page 138
2009-2019 Microchip Technology Inc.
Control Registers
Register
Name(1)
TABLE 11-1:
Virtual Address
(BF88_#)
5040
U1OTGIR(2)
5050
U1OTGIE
5070
U1OTGCON
5080
U1PWRC
U1IR(2)
5200
U1IE
U1EIR(2)
5230
5240
U1EIE
U1STAT(3)
5250
5260
DS60001156K-page 139
5270
U1CON
U1ADDR
U1BDTP1
Legend:
Note
1:
2:
3:
4:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
22/6
21/5
—
—
20/4
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
IDIF
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
IDIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
ID
—
LSTATE
—
SESVD
SESEND
—
VBUSVD
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
OTGEN
VBUSCHG
VBUSDIS
0000
—
—
—
0000
—
T1MSECIF LSTATEIF
—
—
15:0
—
—
—
—
—
—
—
—
DPPULUP
—
—
—
—
—
—
—
—
—
—
—
18/2
17/1
—
—
—
SESVDIF SESENDIF
—
T1MSECIE LSTATEIE
31:16
ACTVIF
19/3
—
ACTVIE
—
SESVDIE SESENDIE
DMPULUP DPPULDWN DMPULDWN VBUSON
15:0
—
—
—
—
—
—
—
—
UACTPND(4)
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
STALLIF
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
STALLIE
31:16
—
—
—
—
—
—
—
—
—
—
USLPGRD USBBUSY
ATTACHIF RESUMEIF
—
—
ATTACHIE RESUMEIE
—
—
—
—
—
—
—
16/0
—
—
—
—
—
IDLEIF
TRNIF
SOFIF
UERRIF
—
—
—
—
IDLEIE
TRNIE
SOFIE
UERRIE
—
—
—
—
CRC5EF
0000
VBUSVDIE 0000
USUSPEND USBPWR
—
0000
VBUSVDIF 0000
0000
0000
—
0000
URSTIF
0000
DETACHIF 0000
—
0000
URSTIE
0000
DETACHIE 0000
—
0000
PIDEF
0000
—
0000
PIDEE
0000
15:0
—
—
—
—
—
—
—
—
BTSEF
BMXEF
DMAEF
BTOEF
DFN8EF
CRC16EF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
BTSEE
BMXEE
DMAEE
BTOEE
DFN8EE
CRC16EE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
DIR
PPBI
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
0000
USBEN
0000
ENDPT(4)
—
—
(4)
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
JSTATE
15:0
—
—
—
—
—
—
—
—
LSPDEN
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
(4)
SE0
—
—
PKTDIS
TOKBUSY
EOFEF
—
CRC5EE
EOFEE
USBRST
HOSTEN
RESUME
PPBRST
—
—
—
—
—
—
—
—
—
BDTPTRL
0000
SOFEN
0000
—
—
0000
—
—
0000
—
0000
DEVADDR
—
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET and INV registers.
Reset value for this bit is undefined.
PIC32MX5XX/6XX/7XX
5210
23/7
All Resets
Bits
5060 U1OTGSTAT(3)
5220
USB REGISTER MAP
Bit Range
2009-2019 Microchip Technology Inc.
11.1
Virtual Address
(BF88_#)
Register
Name(1)
5280
U1FRML(3)
5290
U1FRMH(3)
U1TOK
52B0
U1SOF
52C0
U1BDTP2
U1BDTP3
52E0
U1CNFG1
5300
U1EP0
5310
U1EP1
5320
U1EP2
5330
U1EP3
5340
U1EP4
2009-2019 Microchip Technology Inc.
5350
U1EP5
5360
U1EP6
5370
U1EP7
5380
U1EP8
5390
U1EP9
Legend:
Note
1:
2:
3:
4:
All Resets
Bit Range
Bits
52A0
52D0
USB REGISTER MAP (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
0000
FRML
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
0000
—
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
FRMH
PID
0000
EP
0000
CNT
0000
BDTPTRH
—
—
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BDTPTRU
0000
15:0
—
—
—
—
—
—
—
—
UTEYE
UOEMON
—
USBSIDL
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UASUSPND 0001
—
15:0
—
—
—
—
—
—
—
—
LSPD
RETRYDIS
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET and INV registers.
Reset value for this bit is undefined.
PIC32MX5XX/6XX/7XX
DS60001156K-page 140
TABLE 11-1:
Virtual Address
(BF88_#)
Register
Name(1)
53A0
U1EP10
53B0
U1EP11
53C0
U1EP12
53D0
USB REGISTER MAP (CONTINUED)
U1EP13
53E0
U1EP14
53F0
U1EP15
Legend:
Note
1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET and INV registers.
Reset value for this bit is undefined.
DS60001156K-page 141
PIC32MX5XX/6XX/7XX
2:
3:
4:
20/4
All Resets
Bits
Bit Range
2009-2019 Microchip Technology Inc.
TABLE 11-1:
PIC32MX5XX/6XX/7XX
REGISTER 11-1:
Bit
Range
31:24
23:16
15:8
7:0
U1OTGIR: USB OTG INTERRUPT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
U-0
R/WC-0, HS
IDIF
T1MSECIF
LSTATEIF
ACTVIF
SESVDIF
SESENDIF
—
VBUSVDIF
Legend:
WC = Write ‘1’ to clear
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
IDIF: ID State Change Indicator bit
1 = Change in ID state detected
0 = No change in ID state detected
bit 6
T1MSECIF: 1 Millisecond Timer bit
1 = 1 millisecond timer has expired
0 = 1 millisecond timer has not expired
bit 5
LSTATEIF: Line State Stable Indicator bit
1 = USB line state has been stable for 1 ms, but different from last time
0 = USB line state has not been stable for 1 ms
bit 4
ACTVIF: Bus Activity Indicator bit
1 = Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up
0 = Activity has not been detected
bit 3
SESVDIF: Session Valid Change Indicator bit
1 = VBUS voltage has dropped below the session end level
0 = VBUS voltage has not dropped below the session end level
bit 2
SESENDIF: B-Device VBUS Change Indicator bit
1 = A change on the session end input was detected
0 = No change on the session end input was detected
bit 1
Unimplemented: Read as ‘0’
bit 0
VBUSVDIF: A-Device VBUS Change Indicator bit
1 = Change on the session valid input detected
0 = No change on the session valid input detected
DS60001156K-page 142
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 11-2:
Bit
Range
31:24
23:16
15:8
7:0
U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
IDIE
T1MSECIE
LSTATEIE
ACTVIE
SESVDIE
SESENDIE
—
VBUSVDIE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
IDIE: ID Interrupt Enable bit
1 = ID interrupt enabled
0 = ID interrupt disabled
bit 6
T1MSECIE: 1 Millisecond Timer Interrupt Enable bit
1 = 1 millisecond timer interrupt enabled
0 = 1 millisecond timer interrupt disabled
bit 5
LSTATEIE: Line State Interrupt Enable bit
1 = Line state interrupt enabled
0 = Line state interrupt disabled
bit 4
ACTVIE: Bus ACTIVITY Interrupt Enable bit
1 = ACTIVITY interrupt enabled
0 = ACTIVITY interrupt disabled
bit 3
SESVDIE: Session Valid Interrupt Enable bit
1 = Session valid interrupt enabled
0 = Session valid interrupt disabled
bit 2
SESENDIE: B-Session End Interrupt Enable bit
1 = B-session end interrupt enabled
0 = B-session end interrupt disabled
bit 1
Unimplemented: Read as ‘0’
bit 0
VBUSVDIE: A-VBUS Valid Interrupt Enable bit
1 = A-VBUS valid interrupt enabled
0 = A-VBUS valid interrupt disabled
2009-2019 Microchip Technology Inc.
DS60001156K-page 143
PIC32MX5XX/6XX/7XX
REGISTER 11-3:
Bit
Range
31:24
23:16
15:8
7:0
U1OTGSTAT: USB OTG STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
U-0
R-0
U-0
R-0
R-0
U-0
R-0
ID
—
LSTATE
—
SESVD
SESEND
—
VBUSVD
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
ID: ID Pin State Indicator bit
1 = No cable is attached or a “type B” cable has been inserted into the USB receptacle
0 = A “type A” OTG cable has been inserted into the USB receptacle
bit 6
Unimplemented: Read as ‘0’
bit 5
LSTATE: Line State Stable Indicator bit
1 = USB line state (SE0 (U1CON and JSTATE (U1CON) has been stable for the previous 1 ms
0 = USB line state (SE0 (U1CON and JSTATE (U1CON) has not been stable for the previous 1 ms
bit 4
Unimplemented: Read as ‘0’
bit 3
SESVD: Session Valid Indicator bit
1 = VBUS voltage is above Session Valid on the A or B device
0 = VBUS voltage is below Session Valid on the A or B device
bit 2
SESEND: B-Device Session End Indicator bit
1 = VBUS voltage is below Session Valid on the B device
0 = VBUS voltage is above Session Valid on the B device
bit 1
Unimplemented: Read as ‘0’
bit 0
VBUSVD: A-Device VBUS Valid Indicator bit
1 = VBUS voltage is above Session Valid on the A device
0 = VBUS voltage is below Session Valid on the A device
DS60001156K-page 144
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 11-4:
Bit
Range
31:24
23:16
15:8
7:0
U1OTGCON: USB OTG CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
DPPULUP DMPULUP DPPULDWN DMPULDWN
R/W-0
R/W-0
R/W-0
R/W-0
VBUSON
OTGEN
VBUSCHG
VBUSDIS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
DPPULUP: D+ Pull-Up Enable bit
1 = D+ data line pull-up resistor is enabled
0 = D+ data line pull-up resistor is disabled
bit 6
DMPULUP: D- Pull-Up Enable bit
1 = D- data line pull-up resistor is enabled
0 = D- data line pull-up resistor is disabled
bit 5
DPPULDWN: D+ Pull-Down Enable bit
1 = D+ data line pull-down resistor is enabled
0 = D+ data line pull-down resistor is disabled
bit 4
DMPULDWN: D- Pull-Down Enable bit
1 = D- data line pull-down resistor is enabled
0 = D- data line pull-down resistor is disabled
bit 3
VBUSON: VBUS Power-on bit
1 = VBUS line is powered
0 = VBUS line is not powered
bit 2
OTGEN: OTG Functionality Enable bit
1 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control
0 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control
bit 1
VBUSCHG: VBUS Charge Enable bit
1 = VBUS line is charged through a pull-up resistor
0 = VBUS line is not charged through a resistor
bit 0
VBUSDIS: VBUS Discharge Enable bit
1 = VBUS line is discharged through a pull-down resistor
0 = VBUS line is not discharged through a resistor
2009-2019 Microchip Technology Inc.
DS60001156K-page 145
PIC32MX5XX/6XX/7XX
REGISTER 11-5:
U1PWRC: USB POWER CONTROL REGISTER
Bit
Bit
Range 31/23/15/7
31:24
23:16
15:8
7:0
U-0
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
U-0
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
UACTPND
—
—
USLPGRD
USBBUSY
—
USUSPEND USBPWR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
UACTPND: USB Activity Pending bit
1 = USB bus activity has been detected; but an interrupt is pending, it has not been generated yet
0 = An interrupt is not pending
bit 6-5
Unimplemented: Read as ‘0’
bit 4
USLPGRD: USB Sleep Entry Guard bit
1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending
0 = USB module does not block Sleep entry
bit 3
USBBUSY: USB Module Busy bit
1 = USB module is active or disabled, but not ready to be enabled
0 = USB module is not active and is ready to be enabled
Note:
When USBPWR = 0 and USBBUSY = 1, status from all other registers is invalid and writes to all
USB module registers produce undefined results.
bit 2
Unimplemented: Read as ‘0’
bit 1
USUSPEND: USB Suspend Mode bit
1 = USB module is placed in Suspend mode
(The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.)
0 = USB module operates normally
bit 0
USBPWR: USB Operation Enable bit
1 = USB module is turned on
0 = USB module is disabled
(Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power
consumption.)
DS60001156K-page 146
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 11-6:
Bit
Bit
Range 31/23/15/7
31:24
23:16
15:8
7:0
U1IR: USB INTERRUPT REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R-0
IDLEIF
TRNIF(3)
SOFIF
UERRIF(4)
R/WC-0, HS
(5)
STALLIF
ATTACHIF(1) RESUMEIF(2)
Legend:
R = Readable bit
-n = Value at POR
WC = Write ‘1’ to clear
W = Writable bit
‘1’ = Bit is set
URSTIF
DETACHIF(6)
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
STALLIF: STALL Handshake Interrupt bit
1 = In Host mode a STALL handshake was received during the handshake phase of the transaction. In
Device mode, a STALL handshake was transmitted during the handshake phase of the transaction.
0 = STALL handshake has not been sent
bit 6
ATTACHIF: Peripheral Attach Interrupt bit(1)
1 = Peripheral attachment was detected by the USB module
0 = Peripheral attachment was not detected
bit 5
RESUMEIF: Resume Interrupt bit(2)
1 = K-State is observed on the D+ or D- pin for 2.5 µs
0 = K-State is not observed
bit 4
IDLEIF: Idle Detect Interrupt bit
1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
bit 3
TRNIF: Token Processing Complete Interrupt bit(3)
1 = Processing of current token is complete; a read of the U1STAT register will provide endpoint information
0 = Processing of current token not complete
bit 2
SOFIF: SOF Token Interrupt bit
1 = SOF token received by the peripheral or the SOF threshold reached by the host
0 = SOF token was not received nor threshold reached
bit 1
UERRIF: USB Error Condition Interrupt bit(4)
1 = Unmasked error condition has occurred
0 = Unmasked error condition has not occurred
bit 0
URSTIF: USB Reset Interrupt bit (Device mode)(5)
1 = Valid USB Reset has occurred
0 = No USB Reset has occurred
DETACHIF: USB Detach Interrupt bit (Host mode)(6)
1 = Peripheral detachment was detected by the USB module
0 = Peripheral detachment was not detected
Note 1:
2:
3:
4:
5:
6:
This bit is only valid if the HOSTEN bit is set (see Register 11-11), there is no activity on the USB for
2.5 µs, and the current bus state is not SE0.
When not in Suspend mode, this interrupt should be disabled.
Clearing this bit will cause the STAT FIFO to advance.
Only error conditions enabled through the U1EIE register will set this bit.
Device mode.
Host mode.
2009-2019 Microchip Technology Inc.
DS60001156K-page 147
PIC32MX5XX/6XX/7XX
REGISTER 11-7:
Bit
Range
31:24
23:16
15:8
7:0
U1IE: USB INTERRUPT ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STALLIE
ATTACHIE RESUMEIE
IDLEIE
TRNIE
SOFIE
UERRIE(1)
R/W-0
URSTIE(2)
DETACHIE(3)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
STALLIE: STALL Handshake Interrupt Enable bit
1 = STALL interrupt is enabled
0 = STALL interrupt is disabled
bit 6
ATTACHIE: ATTACH Interrupt Enable bit
1 = ATTACH interrupt is enabled
0 = ATTACH interrupt is disabled
bit 5
RESUMEIE: RESUME Interrupt Enable bit
1 = RESUME interrupt is enabled
0 = RESUME interrupt is disabled
bit 4
IDLEIE: Idle Detect Interrupt Enable bit
1 = Idle interrupt is enabled
0 = Idle interrupt is disabled
bit 3
TRNIE: Token Processing Complete Interrupt Enable bit
1 = TRNIF interrupt is enabled
0 = TRNIF interrupt is disabled
bit 2
SOFIE: SOF Token Interrupt Enable bit
1 = SOFIF interrupt is enabled
0 = SOFIF interrupt is disabled
bit 1
UERRIE: USB Error Interrupt Enable bit(1)
1 = USB Error interrupt is enabled
0 = USB Error interrupt is disabled
bit 0
URSTIE: USB Reset Interrupt Enable bit(2)
1 = URSTIF interrupt is enabled
0 = URSTIF interrupt is disabled
DETACHIE: USB Detach Interrupt Enable bit(3)
1 = DATTCHIF interrupt is enabled
0 = DATTCHIF interrupt is disabled
Note 1:
2:
3:
For an interrupt to propagate USBIF, the UERRIE bit (U1IE) must be set.
Device mode.
Host mode.
DS60001156K-page 148
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 11-8:
Bit
Range
31:24
23:16
15:8
7:0
U1EIR: USB ERROR INTERRUPT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
BTSEF
BMXEF
DMAEF(1)
BTOEF(2)
R/WC-0, HS
(4)
DFN8EF
CRC16EF
Legend:
R = Readable bit
-n = Value at POR
WC = Write ‘1’ to clear
W = Writable bit
‘1’ = Bit is set
CRC5EF
EOFEF(3,5)
PIDEF
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
BTSEF: Bit Stuff Error Flag bit
1 = Packet is rejected due to bit stuff error
0 = Packet is accepted
bit 6
BMXEF: Bus Matrix Error Flag bit
1 = Invalid base address of the BDT, or the address of an individual buffer pointed to by a BDT entry
0 = No address error
bit 5
DMAEF: DMA Error Flag bit(1)
1 = USB DMA error condition detected
0 = No DMA error
bit 4
BTOEF: Bus Turnaround Time-Out Error Flag bit(2)
1 = Bus turnaround time-out has occurred
0 = No bus turnaround time-out
bit 3
DFN8EF: Data Field Size Error Flag bit
1 = Data field received is not an integral number of bytes
0 = Data field received is an integral number of bytes
bit 2
CRC16EF: CRC16 Failure Flag bit
1 = Data packet is rejected due to CRC16 error
0 = Data packet is accepted
bit 1
CRC5EF: CRC5 Host Error Flag bit(4)
1 = Token packet is rejected due to CRC5 error
0 = Token packet is accepted
EOFEF: EOF Error Flag bit(3,5)
1 = EOF error condition is detected
0 = No EOF error condition
bit 0
PIDEF: PID Check Failure Flag bit
1 = PID check is failed
0 = PID check is passed
Note 1:
2:
3:
4:
5:
This type of error occurs when the module’s request for the DMA bus is not granted in time to service the
module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer
size is not sufficient to store the received data packet causing it to be truncated.
This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)
has elapsed.
This type of error occurs when the module is transmitting or receiving data and the SOF counter has
reached zero.
Device mode.
Host mode.
2009-2019 Microchip Technology Inc.
DS60001156K-page 149
PIC32MX5XX/6XX/7XX
REGISTER 11-9:
Bit
Range
31:24
23:16
15:8
7:0
U1EIE: USB ERROR INTERRUPT ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BTSEE
BMXEE
DMAEE
BTOEE
DFN8EE
CRC16EE
CRC5EE(1)
EOFEE(2)
PIDEE
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
Note:
BTSEE: Bit Stuff Error Interrupt Enable bit
1 = BTSEF interrupt is enabled
0 = BTSEF interrupt is disabled
BMXEE: Bus Matrix Error Interrupt Enable bit
1 = BMXEF interrupt is enabled
0 = BMXEF interrupt is disabled
DMAEE: DMA Error Interrupt Enable bit
1 = DMAEF interrupt is enabled
0 = DMAEF interrupt is disabled
BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1 = BTOEF interrupt is enabled
0 = BTOEF interrupt is disabled
DFN8EE: Data Field Size Error Interrupt Enable bit
1 = DFN8EF interrupt is enabled
0 = DFN8EF interrupt is disabled
CRC16EE: CRC16 Failure Interrupt Enable bit
1 = CRC16EF interrupt is enabled
0 = CRC16EF interrupt is disabled
CRC5EE: CRC5 Host Error Interrupt Enable bit(1)
1 = CRC5EF interrupt is enabled
0 = CRC5EF interrupt is disabled
EOFEE: EOF Error Interrupt Enable bit(2)
1 = EOF interrupt is enabled
0 = EOF interrupt is disabled
PIDEE: PID Check Failure Interrupt Enable bit
1 = PIDEF interrupt is enabled
0 = PIDEF interrupt is disabled
Device mode.
Host mode.
For an interrupt to propagate USBIF, the UERRIE bit (U1IE) must be set.
DS60001156K-page 150
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 11-10: U1STAT: USB STATUS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-x
R-x
R-x
R-x
R-x
R-x
U-0
U-0
DIR
PPBI
—
—
ENDPT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-4
ENDPT: Encoded Number of Last Endpoint Activity bits
(Represents the number of the BDT, updated by the last USB transfer.)
1111 = Endpoint 15
1110 = Endpoint 14
•
•
•
0001 = Endpoint 1
0000 = Endpoint 0
bit 3
DIR: Last Buffer Descriptor Direction Indicator bit
1 = Last transaction was a transmit transfer (TX)
0 = Last transaction was a receive transfer (RX)
bit 2
PPBI: Ping-Pong Buffer Descriptor Pointer Indicator bit
1 = The last transaction was to the Odd buffer descriptor bank
0 = The last transaction was to the Even buffer descriptor bank
bit 1-0
Unimplemented: Read as ‘0’
Note:
The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. U1STAT value is only
valid when U1IR is active. Clearing the U1IR bit advances the FIFO. Data in register is
invalid when U1IR = 0.
2009-2019 Microchip Technology Inc.
DS60001156K-page 151
PIC32MX5XX/6XX/7XX
REGISTER 11-11: U1CON: USB CONTROL REGISTER
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6
31:24
23:16
15:8
7:0
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-x
R-x
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
JSTATE
SE0
PKTDIS(4)
TOKBUSY(1,5)
USBRST
HOSTEN(2) RESUME(3)
PPBRST
R/W-0
USBEN(4)
SOFEN(5)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
JSTATE: Live Differential Receiver JSTATE flag bit
1 = JSTATE was detected on the USB
0 = JSTATE was not detected
bit 6
SE0: Live Single-Ended Zero flag bit
1 = Single-ended zero was detected on the USB
0 = Single-ended zero was not detected
bit 5
PKTDIS: Packet Transfer Disable bit(4)
1 = Token and packet processing disabled (set upon SETUP token received)
0 = Token and packet processing enabled
TOKBUSY: Token Busy Indicator bit(1,5)
1 = Token being executed by the USB module
0 = No token being executed
bit 4
USBRST: Module Reset bit(5)
1 = USB reset is generated
0 = USB reset is terminated
bit 3
HOSTEN: Host Mode Enable bit(2)
1 = USB host capability is enabled
0 = USB host capability is disabled
bit 2
RESUME: RESUME Signaling Enable bit(3)
1 = RESUME signaling is activated
0 = RESUME signaling is disabled
Note 1:
2:
3:
4:
5:
Software is required to check this bit before issuing another token command to the U1TOK register (see
Register 11-15).
All host control logic is reset any time that the value of this bit is toggled.
Software must set RESUME for 10 ms in Device mode, or for 25 ms in Host mode, and then clear it to
enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME
signaling when this bit is cleared.
Device mode.
Host mode.
DS60001156K-page 152
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PIC32MX5XX/6XX/7XX
REGISTER 11-11: U1CON: USB CONTROL REGISTER (CONTINUED)
bit 1
PPBRST: Ping-Pong Buffers Reset bit
1 = Reset all Even/Odd buffer pointers to the Even buffer descriptor banks
0 = Even/Odd buffer pointers are not reset
bit 0
USBEN: USB Module Enable bit(4)
1 = USB module and supporting circuitry is enabled
0 = USB module and supporting circuitry is disabled
SOFEN: SOF Enable bit(5)
1 = SOF token is sent every 1 ms
0 = SOF token is disabled
Note 1:
2:
3:
4:
5:
Software is required to check this bit before issuing another token command to the U1TOK register (see
Register 11-15).
All host control logic is reset any time that the value of this bit is toggled.
Software must set RESUME for 10 ms in Device mode, or for 25 ms in Host mode, and then clear it to
enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME
signaling when this bit is cleared.
Device mode.
Host mode.
2009-2019 Microchip Technology Inc.
DS60001156K-page 153
PIC32MX5XX/6XX/7XX
REGISTER 11-12: U1ADDR: USB ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LSPDEN
DEVADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
LSPDEN: Low-Speed Enable Indicator bit
1 = Next token command to be executed at low-speed
0 = Next token command to be executed at full-speed
bit 6-0
DEVADDR: 7-bit USB Device Address bits
REGISTER 11-13: U1FRML: USB FRAME NUMBER LOW REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FRML
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0
FRML: 11-bit Frame Number Lower bits
The register bits are updated with the current frame number whenever a SOF TOKEN is received.
DS60001156K-page 154
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 11-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
—
—
—
—
—
FRMH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-3 Unimplemented: Read as ‘0’
bit 2-0
FRMH: Upper 3 bits of the Frame Numbers bits
These register bits are updated with the current frame number whenever a SOF TOKEN is received.
REGISTER 11-15: U1TOK: USB TOKEN REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PID
EP
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-4
PID: Token Type Indicator bits(1)
1101 = SETUP (TX) token type transaction
1001 = IN (RX) token type transaction
0001 = OUT (TX) token type transaction
Note: All other values not listed, are Reserved and must not be used.
bit 3-0
EP: Token Command Endpoint Address bits
The four bit value must specify a valid endpoint.
2009-2019 Microchip Technology Inc.
DS60001156K-page 155
PIC32MX5XX/6XX/7XX
REGISTER 11-16: U1SOF: USB SOF THRESHOLD REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0
CNT: SOF Threshold Value bits
Typical values of the threshold are:
01001010 = 64-byte packet
00101010 = 32-byte packet
00011010 = 16-byte packet
00010010 = 8-byte packet
REGISTER 11-17: U1BDTP1: USB BUFFER DESCRIPTOR TABLE PAGE 1 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
BDTPTRL
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-1
BDTPTRL: BDT Base Address bits
This 7-bit value provides address bits 15 through 9 of the BDT base address, which defines the starting
location of the BDT in system memory.
The 32-bit BDT base address is 512-byte aligned.
bit 0
Unimplemented: Read as ‘0’
DS60001156K-page 156
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 11-18: U1BDTP2: USB BUFFER DESCRIPTOR TABLE PAGE 2 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BDTPTRH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0
BDTPTRH: BDT Base Address bits
This 8-bit value provides address bits 23 through 16 of the BDT base address, which defines the starting
location of the BDT in system memory.
The 32-bit BDT base address is 512-byte aligned.
REGISTER 11-19: U1BDTP3: USB BUFFER DESCRIPTOR TABLE PAGE 3 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BDTPTRU
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8
Unimplemented: Read as ‘0’
bit 7-0
BDTPTRU: BDT Base Address bits
This 8-bit value provides address bits 31 through 24 of the BDT base address, defines the starting location
of the BDT in system memory.
The 32-bit BDT base address is 512-byte aligned.
2009-2019 Microchip Technology Inc.
DS60001156K-page 157
PIC32MX5XX/6XX/7XX
REGISTER 11-20: U1CNFG1: USB CONFIGURATION 1 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
UTEYE
UOEMON
—
USBSIDL
—
—
—
UASUSPND
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8
Unimplemented: Read as ‘0’
bit 7
UTEYE: USB Eye-Pattern Test Enable bit
1 = Eye-Pattern Test is enabled
0 = Eye-Pattern Test is disabled
bit 6
UOEMON: USB OE Monitor Enable bit
1 = OE signal is active; it indicates intervals during which the D+/D- lines are driving
0 = OE signal is inactive
bit 5
Unimplemented: Read as ‘0’
bit 4
USBSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 3-1
Unimplemented: Read as ‘0’
bit 0
UASUSPND: Automatic Suspend Enable bit
1 = USB module automatically suspends upon entry to Sleep mode. See the USUSPEND bit
(U1PWRC) in Register 11-5.
0 = USB module does not automatically suspend upon entry to Sleep mode. Software must use the
USUSPEND bit (U1PWRC) to suspend the module, including the USB 48 MHz clock.
DS60001156K-page 158
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 11-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LSPD
RETRYDIS
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only)
1 = Direct connection to a low-speed device enabled
0 = Direct connection to a low-speed device disabled; hub required with PRE_PID
bit 6
RETRYDIS: Retry Disable bit (Host mode and U1EP0 only)
1 = Retry NACK’d transactions disabled
0 = Retry NACK’d transactions enabled; retry done in hardware
bit 5
Unimplemented: Read as ‘0’
bit 4
EPCONDIS: Bidirectional Endpoint Control bit
If EPTXEN = 1 and EPRXEN = 1:
1 = Disable Endpoint ‘n’ from control transfers; only TX and RX transfers are allowed
0 = Enable Endpoint ‘n’ for control (SETUP) transfers; TX and RX transfers are also allowed
Otherwise, this bit is ignored.
bit 3
EPRXEN: Endpoint Receive Enable bit
1 = Endpoint ’n’ receive is enabled
0 = Endpoint ’n’ receive is disabled
bit 2
EPTXEN: Endpoint Transmit Enable bit
1 = Endpoint ’n’ transmit is enabled
0 = Endpoint ’n’ transmit is disabled
bit 1
EPSTALL: Endpoint Stall Status bit
1 = Endpoint ’n’ was stalled
0 = Endpoint ’n’ was not stalled
bit 0
EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint Handshake is enabled
0 = Endpoint Handshake is disabled (typically used for isochronous endpoints)
2009-2019 Microchip Technology Inc.
DS60001156K-page 159
PIC32MX5XX/6XX/7XX
NOTES:
DS60001156K-page 160
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
12.0
I/O PORTS
Note:
Following are some of the key features of this module:
• Individual output pin open-drain enable/disable
• Individual input pin weak pull-up enable/disable
• Monitor selective inputs and generate interrupt
when change in pin state is detected
• Operation during Sleep and Idle modes
• Fast bit manipulation using CLR, SET and INV
registers
Figure 12-1 illustrates a block diagram of a typical
multiplexed I/O port.
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS60001120) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
General purpose I/O pins are the simplest of peripherals. They allow the PIC32 MCU to monitor and control
other devices. To add flexibility and functionality, some
pins are multiplexed with alternate function(s). These
functions depend on which peripheral features are on
the device. In general, when a peripheral is functioning,
that pin may not be used as a general purpose I/O pin.
FIGURE 12-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Peripheral Module
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
PIO Module
RD ODC
Data Bus
D
PBCLK
Q
ODC
CK
EN Q
WR ODC
1
RD TRIS
0
I/O Cell
0
1
D
Q
1
TRIS
CK
EN Q
WR TRIS
0
Output Multiplexers
D
Q
I/O Pin
LAT
CK
EN Q
WR LAT
WR PORT
RD LAT
1
RD PORT
0
Sleep
Q
Q
D
CK
Q
Q
D
CK
PBCLK
Synchronization
Peripheral Input
Legend:
Note:
R
Peripheral Input Buffer
R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
This block diagram is a general representation of a shared port/peripheral structure is only for illustration purposes. The actual structure
for any specific port/peripheral combination may be different than it is shown here.
2009-2019 Microchip Technology Inc.
DS60001156K-page 161
PIC32MX5XX/6XX/7XX
12.1
Parallel I/O (PIO) Ports
All port pins have three registers (TRIS, LAT and
PORT) that are directly associated with their operation.
TRIS is a Data Direction or Tri-State Control register
that determines whether a digital pin is an input or an
output. Setting a TRISx register bit = 1, configures the
corresponding I/O pin as an input; setting a TRISx
register bit = 0, configures the corresponding I/O pin as
an output. All port I/O pins are defined as inputs after a
device Reset. Certain I/O pins are shared with analog
peripherals and default to analog inputs after a device
Reset.
PORT is a register used to read the current state of the
signal applied to the port I/O pins. Writing to a PORTx
register performs a write to the port’s latch, LATx
register, latching the data to the port’s I/O pins.
LAT is a register used to write data to the port I/O pins.
The LATx Latch register holds the data written to either
the LATx or PORTx registers. Reading the LATx Latch
register reads the last value written to the
corresponding PORT or Latch register.
Not all port I/O pins are implemented on some devices,
therefore, the corresponding PORTx, LATx and TRISx
register bits will read as zeros.
12.1.1
CLR, SET AND INV REGISTERS
Every I/O module register has a corresponding Clear
(CLR), Set (SET) and Invert (INV) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
Note:
12.1.2
The maximum input voltage allowed on the input pins
is the same as the maximum VIH specification. Refer to
Section 32.0 “Electrical Characteristics” for VIH
specification details.
Note:
12.1.3
12.1.4
DIGITAL OUTPUTS
Pins are configured as digital outputs by setting the
corresponding TRIS register bits = 0. When configured
as digital outputs, these pins are CMOS drivers or can
be configured as open-drain outputs by setting the
corresponding bits in the Open-Drain Configuration
(ODCx) register.
The open-drain feature allows generation of outputs
higher than VDD (e.g., 5V) on any desired 5V tolerant
pins by using external pull-up resistors. The maximum
open-drain voltage allowed is the same as the
maximum VIH specification.
See the “Device Pin Tables” section for the available
pins and their functionality.
12.1.5
DIGITAL INPUTS
12.1.6
DS60001156K-page 162
ANALOG INPUTS
Certain pins can be configured as analog inputs used
by the ADC and comparator modules. Setting the
corresponding bits in the AD1PCFG register = 0
enables the pin as an analog input pin and must have
the corresponding TRIS bit set = 1 (input). If the TRIS
bit is cleared = 0 (output), the digital output level (VOH
or VOL) will be converted. Any time a port I/O pin is
configured as analog, its digital input is disabled and
the corresponding PORTx register bit will read ‘0’. The
AD1PCFG register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
Using a PORTxINV register to toggle a bit
is recommended because the operation is
performed in hardware atomically, using
fewer instructions, as compared to the
traditional read-modify-write method, as
follows:
PORTC ^ = 0x0001;
Pins are configured as digital inputs by setting the
corresponding TRIS register bits = 1. When configured
as inputs, they are either TTL buffers or Schmitt
Triggers. Several digital pins share functionality with
analog inputs and default to the analog inputs at POR.
Setting the corresponding bit in the AD1PCFG
register = 1 enables the pin as a digital pin.
Analog levels on any pin that is defined as
a digital input (including the ANx pins)
may cause the input buffer to consume
current that exceeds the device
specifications.
ANALOG OUTPUTS
Certain pins can be configured as analog outputs, such
as the CVREF output voltage used by the comparator
module. Configuring the comparator reference module
to provide this output will present the analog output
voltage on the pin, independent of the TRIS register
setting for the corresponding pin.
INPUT CHANGE NOTIFICATION
The input change notification function of the I/O ports
(CNx) allows devices to generate interrupt requests in
response to change-of-state on selected pin.
Each CNx pin also has a weak pull-up, which acts as a
current source connected to the pin. The pull-ups are
enabled by setting the corresponding bit in the CNPUE
register.
2009-2019 Microchip Technology Inc.
Control Registers
Register
Name(1)
TABLE 12-1:
Virtual Address
(BF88_#)
6000
TRISA
6010
PORTA
6020
LATA
PORTA REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
6030
ODCA
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
TRISA15
TRISA14
—
—
—
TRISA10
TRISA9
—
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
C6FF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RA15
RA14
—
—
—
RA10
RA9
—
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATA15
LATA14
—
—
—
LATA10
LATA9
—
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCA15
ODCA14
—
—
—
ODCA10
ODCA9
—
ODCA7
ODCA6
ODCA5
ODCA4
ODCA3
ODCA2
ODCA1
ODCA0
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
Virtual Address
(BF88_#)
Register
Name(1)
DS60001156K-page 163
TRISB
6050
PORTB
6060
LATB
6070
ODCB
PORTB REGISTER MAP
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
TRISB15
TRISB14
TRISB13
TRISB12
TRISB11
TRISB10
TRISB9
TRISB8
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
FFFF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATB15
LATB14
LATB13
LATB12
LATB11
LATB10
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCB15
ODCB14
ODCB13
ODCB12
ODCB11
ODCB10
ODCB9
ODCB8
ODCB7
ODCB6
ODCB5
ODCB4
ODCB3
ODCB2
ODCB1
ODCB0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
Bit Range
Bits
PIC32MX5XX/6XX/7XX
TABLE 12-2:
6040
0000
31:16
Legend:
1:
All Resets
Bits
Bit Range
2009-2019 Microchip Technology Inc.
12.2
Virtual Address
(BF88_#)
Register
Name(1)
6080
TRISC
PORTC
60A0
LATC
60B0
ODCC
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
TRISC15
TRISC14
TRISC13
TRISC12
—
—
—
—
—
—
—
—
—
—
—
—
F000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RC15
RC14
RC13
RC12
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATC15
LATC14
LATC13
LATC12
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCC15
ODCC14
ODCC13
ODCC12
—
—
—
—
—
—
—
—
—
—
—
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
Register
Name(1)
2009-2019 Microchip Technology Inc.
Virtual Address
(BF88_#)
TABLE 12-4:
6080
TRISC
PORTC REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
Bit Range
Bits
6090 PORTC
60A0
60B0
All Resets
Bit Range
Bits
LATC
ODCC
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
TRISC15
TRISC14
TRISC13
TRISC12
—
—
—
—
—
—
—
TRISC4
TRISC3
TRISC2
TRISC1
—
F00F
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RC15
RC14
RC13
RC12
—
—
—
—
—
—
—
RC4
RC3
RC2
RC1
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATC15
LATC14
LATC13
LATC12
—
—
—
—
—
—
—
LATC4
LATC3
LATC2
LATC1
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCC15
ODCC14
ODCC13
ODCC12
—
—
—
—
—
—
—
ODCC4
ODCC3
ODCC2
ODCC1
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
6090
PORTC REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
PIC32MX5XX/6XX/7XX
DS60001156K-page 164
TABLE 12-3:
Virtual Address
(BF88_#)
Register
Name(1)
60C0
TRISD
PORTD REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
60D0
PORTD
60E0
LATD
60F0
ODCD
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31/15
30/14
29/13
28/12
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
TRISD11
TRISD10
TRISD9
TRISD8
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
0FFF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
RD11
RD10
RD9
RD8
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
LATD11
LATD10
LATD9
LATD8
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
ODCD11
ODCD10
ODCD9
ODCD8
ODCD7
ODCD6
ODCD5
ODCD4
ODCD3
ODCD2
ODCD1
ODCD0
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
Register
Name(1)
TRISD
PORTD REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
60D0 PORTD
DS60001156K-page 165
60E0
LATD
60F0
ODCD
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
TRISD15
TRISD14
TRISD13
TRISD12
TRISD11
TRISD10
TRISD9
TRISD8
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
FFFF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RD15
RD14
RD13
RD12
RD11
RD10
RD9
RD8
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LAT15
LAT14
LAT13
LAT12
LATD11
LATD10
LATD9
LATD8
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCD15
ODCD14
ODCD13
ODCD12
ODCD11
ODCD10
ODCD9
ODCD8
ODCD7
ODCD6
ODCD5
ODCD4
ODCD3
ODCD2
ODCD1
ODCD0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
Bit Range
Bits
PIC32MX5XX/6XX/7XX
Virtual Address
(BF88_#)
TABLE 12-6:
60C0
0000
31:16
Legend:
1:
All Resets
Bits
Bit Range
2009-2019 Microchip Technology Inc.
TABLE 12-5:
Virtual Address
(BF88_#)
Register
Name(1)
6100
TRISE
PORTE REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
6110
PORTE
6120
LATE
6130
ODCE
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
00FF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
ODCE7
0DCE6
ODCE5
ODCE4
ODCE3
ODCE2
ODCE1
ODCE0
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
Register
Name(1)
2009-2019 Microchip Technology Inc.
Virtual Address
(BF88_#)
TABLE 12-8:
6100
TRISE
0000
31:16
Legend:
1:
All Resets
Bit Range
Bits
PORTE REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
6110
PORTE
6120
LATE
6130
ODCE
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
TRISE9
TRISE8
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
03FF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
—
—
—
—
—
—
RE9
RE8
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
LATE9
LATE8
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
ODCE9
ODCE8
ODCE7
0DCE6
ODCE5
ODCE4
ODCE3
ODCE2
ODCE1
ODCE0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
Bit Range
Bits
PIC32MX5XX/6XX/7XX
DS60001156K-page 166
TABLE 12-7:
Virtual Address
(BF88_#)
Register
Name(1)
6140
TRISF
PORTF REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
6150 PORTF
6160
LATF
6170
ODCF
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
TRISF5
31:16
—
—
—
—
—
—
—
—
—
—
—
20/4
17/1
16/0
19/3
18/2
—
—
—
—
—
TRISF4
TRISF3
—
TRISF1
TRISF0
003B
—
—
—
—
—
0000
0000
15:0
—
—
—
—
—
—
—
—
—
—
RF5
RF4
RF3
—
RF1
RF0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
LATF5
LATF4
LATF3
—
LATF1
LATF0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
ODCF5
ODCF4
ODCF3
—
ODCF1
ODCF0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
Bits
Bit Range
2009-2019 Microchip Technology Inc.
TABLE 12-9:
Virtual Address
(BF88_#)
Register
Name(1)
DS60001156K-page 167
6140
TRISF
6150
PORTF
6160
LATF
6170
ODCF
31/15
30/14
31:16
—
—
15:0
—
—
31:16
—
—
29/13
28/12
27/11
26/10
25/9
—
—
—
—
TRISF13
TRISF12
—
—
—
—
—
21/5
20/4
19/3
18/2
17/1
16/0
24/8
23/7
22/6
—
—
—
—
—
—
—
—
—
—
—
TRISF8
—
—
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0
313F
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
—
—
RF13
RF12
—
—
—
RF8
—
—
RF5
RF4
RF3
RF2
RF1
RF0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
LATF13
LATF12
—
—
—
LATF8
—
—
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
ODCF13
ODCF12
—
—
—
ODCF8
—
—
ODCF5
ODCF4
ODCF3
ODCF2
ODCF1
ODCF0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
Bit Range
Bits
PIC32MX5XX/6XX/7XX
TABLE 12-10: PORTF REGISTER MAP PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L,
PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L,
PIC32MX764F128L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address
(BF88_#)
Register
Name(1)
6180
TRISG
6190 PORTG
61A0
61B0
LATG
ODCG
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
TRISG9
TRISG8
—
—
—
—
TRISG7
TRISG6
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
RG9
RG8
RG7
RG6
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
LATG9
LATG8
LATG7
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
ODCG9
ODCG8
19/3
18/2
17/1
16/0
—
—
—
—
0000
TRISG3
TRISG2
—
—
03CC
—
—
—
—
0000
—
RG3
RG2
—
—
xxxx
—
—
—
—
—
—
0000
LATG6
—
—
LATG3
LATG2
—
—
xxxx
—
—
—
—
—
—
—
—
0000
ODCG7
ODCG6
—
—
ODCG3
ODCG2
—
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
Bit Range
Bits
Register
Name(1)
2009-2019 Microchip Technology Inc.
Virtual Address
(BF88_#)
TABLE 12-12: PORTG REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
6180
TRISG
6190 PORTG
61A0
LATG
61B0
ODCG
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
TRISG15
TRISG14
TRISG13
TRISG12
—
—
TRISG9
TRISG8
TRISG7
TRISG6
—
—
TRISG3
TRISG2
TRISG1
TRISG0
F3CF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
RG15
RG14
RG13
RG12
—
—
RG9
RG8
RG7
RG6
—
—
RG3
RG2
RG1
RG0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATG15
LATG14
LATG13
LATG12
—
—
LATG9
LATG8
LATG7
LATG6
—
—
LATG3
LATG2
LATG1
LATG0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCG15
ODCG14
ODCG13
ODCG12
—
—
ODCG9
ODCG8
ODCG7
ODCG6
—
—
ODCG3
ODCG2
ODCG1
ODCG0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
Bit Range
Bits
PIC32MX5XX/6XX/7XX
DS60001156K-page 168
TABLE 12-11: PORTG REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
Virtual Address
(BF88_#)
61C0 CNCON
61D0
CNEN
61E0
CNPUE
31/15
30/14
31:16
—
15:0
ON
31:16
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
CNEN21
CNEN20
CNEN19
CNEN18
CNEN17
CNEN16
0000
15:0
CNEN15
CNEN14
CNEN13
CNEN12
CNEN11
CNEN10
CNEN9
CNEN8
CNEN7
CNEN6
CNEN5
CNEN4
CNEN3
CNEN2
CNEN1
CNEN0
0000
31:16
—
—
—
—
—
—
—
—
—
—
CNPUE21
CNPUE20
CNPUE19 CNPUE18 CNPUE17 CNPUE16 0000
CNPUE9
CNPUE8
CNPUE7
CNPUE6
CNPUE5
CNPUE4
CNPUE3
15:0
CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10
CNPUE2
CNPUE1
CNPUE0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
Bit Range
Bits
Register
Name(1)
2009-2019 Microchip Technology Inc.
TABLE 12-13: CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L,
PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512 AND PIC32MX795F512L DEVICES
0000
61C0 CNCON
61D0
CNEN
61E0
CNPUE
31/15
30/14
31:16
—
15:0
ON
31:16
15:0
31:16
15:0
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
CNEN18
CNEN17
CNEN16
0000
CNEN15
CNEN14
CNEN13
CNEN12
CNEN11
CNEN10
CNEN9
CNEN8
CNEN7
CNEN6
CNEN5
CNEN4
CNEN3
CNEN2
CNEN1
CNEN0
0000
—
—
—
—
—
—
CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10
—
—
—
—
—
—
—
CNPUE9
CNPUE8
CNPUE7
CNPUE6
CNPUE5
CNPUE4
CNPUE3
CNPUE18 CNPUE17 CNPUE16 0000
CNPUE2
CNPUE1
CNPUE0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
Bit Range
Register
Name(1)
Bits
0000
DS60001156K-page 169
PIC32MX5XX/6XX/7XX
Virtual Address
(BF88_#)
TABLE 12-14: CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H,
PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
PIC32MX5XX/6XX/7XX
REGISTER 12-1:
Bit
Range
31:24
23:16
15:8
7:0
CNCON: CHANGE NOTICE CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ON
—
SIDL
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Change Notice (CN) Control ON bit
1 = CN is enabled
0 = CN is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Control bit
1 = Idle mode halts CN operation
0 = Idle mode does not affect CN operation
bit 12-0
Unimplemented: Read as ‘0’
DS60001156K-page 170
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
13.0
Note:
TIMER1
13.1
Additional Supported Features
• Selectable clock prescaler
• Timer operation during Idle and Sleep mode
• Fast bit manipulation using CLR, SET and INV
registers
• Asynchronous mode can be used with the SOSC
to function as a Real-Time Clock (RTC)
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS60001105) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
A simplified block diagram of the Timer1 module is
illustrated in Figure 13-1.
This family of PIC32 devices features one synchronous/
asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and
counting external events. This timer can also be used
with the low-power Secondary Oscillator (SOSC) for
Real-Time Clock (RTC) applications. The following
modes are supported:
•
•
•
•
Synchronous Internal Timer
Synchronous Internal Gated Timer
Synchronous External Timer
Asynchronous External Timer
FIGURE 13-1:
TIMER1 BLOCK DIAGRAM
PR1
Equal
16-bit Comparator
TSYNC (T1CON)
1
Reset
Sync
TMR1
0
T1IF
Event Flag
0
Q
1
TGATE (T1CON)
D
Q
TGATE (T1CON)
TCS (T1CON)
ON (T1CON)
SOSCO/T1CK
x1
SOSCEN(1)
SOSCI
Gate
Sync
PBCLK
10
00
Prescaler
1, 8, 64, 256
2
TCKPS
(T1CON)
Note 1: The default state of the SOSCEN (OSCCON) during a device Reset is controlled by the FSOSCEN bit in
Configuration Word, DEVCFG1.
2009-2019 Microchip Technology Inc.
DS60001156K-page 171
Control Registers
Virtual Address
(BF80_#)
TABLE 13-1:
TIMER1 REGISTER MAP
0600 T1CON
0610
TMR1
0620
PR1
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
15:0
ON
—
SIDL
31:16
—
—
—
—
—
—
—
—
TWDIS
TWIP
—
—
—
—
—
15:0
31:16
15:0
23/7
22/6
21/5
20/4
19/3
—
—
—
—
—
—
—
TGATE
—
TCKPS
—
—
—
—
—
—
—
—
—
—
—
18/2
17/1
16/0
—
—
—
0000
TSYNC
TCS
—
0000
—
—
—
0000
—
—
—
TMR1
—
—
—
—
—
—
—
—
—
0000
PR1
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
Register
Name(1)
Bit Range
Bits
0000
FFFF
PIC32MX5XX/6XX/7XX
DS60001156K-page 172
13.2
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 13-1:
Bit
Range
31:24
23:16
15:8
7:0
T1CON: TYPE A TIMER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
R/W-0
R-0
U-0
U-0
U-0
ON(1)
—
SIDL
TWDIS
TWIP
—
—
—
R/W-0
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
TGATE
—
—
TSYNC
TCS
—
TCKPS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Timer On bit(1)
1 = Timer is enabled
0 = Timer is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation when device is in Idle mode
bit 12
TWDIS: Asynchronous Timer Write Disable bit
1 = Writes to TMR1 are ignored until pending write operation completes
0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
bit 11
TWIP: Asynchronous Timer Write in Progress bit
In Asynchronous Timer mode:
1 = Asynchronous write to TMR1 register in progress
0 = Asynchronous write to TMR1 register complete
In Synchronous Timer mode:
This bit is read as ‘0’.
bit 10-8
Unimplemented: Read as ‘0’
bit 7
TGATE: Timer Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5-4
TCKPS: Timer Input Clock Prescale Select bits
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
Note 1:
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2009-2019 Microchip Technology Inc.
DS60001156K-page 173
PIC32MX5XX/6XX/7XX
REGISTER 13-1:
T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED)
bit 3
Unimplemented: Read as ‘0’
bit 2
TSYNC: Timer External Clock Input Synchronization Selection bit
When TCS = 1:
1 = External clock input is synchronized
0 = External clock input is not synchronized
When TCS = 0:
This bit is ignored.
bit 1
TCS: Timer Clock Source Select bit
1 = External clock from TxCKI pin
0 = Internal peripheral clock
bit 0
Unimplemented: Read as ‘0’
Note 1:
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS60001156K-page 174
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
14.0
TIMER2/3, TIMER4/5
Note:
Two 32-bit synchronous timers are available by
combining Timer2 with Timer3 and Timer4 with Timer5.
The 32-bit timers can operate in three modes:
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS60001105) of the “PIC32 Family Reference Manual”, which is available from
the Microchip web site (www.microchip.com/PIC32).
• Synchronous Internal 32-bit Timer
• Synchronous Internal 32-bit Gated Timer
• Synchronous External 32-bit Timer
Note:
This family of PIC32 devices features four synchronous
16-bit timers (default) that can operate as a freerunning interval timer for various timing applications
and counting external events. The following modes are
supported:
14.1
Additional Supported Features
• Selectable clock prescaler
• Timers operational during CPU idle
• Time base for Input Capture and Output Compare
modules (only Timer2 and Timer3)
• ADC event trigger (only Timer3)
• Fast bit manipulation using CLR, SET and INV
registers
• Synchronous Internal 16-bit Timer
• Synchronous Internal 16-bit Gated Timer
• Synchronous External 16-bit Timer
FIGURE 14-1:
In this chapter, references to registers,
TxCON, TMRx and PRx, use ‘x’ to
represent Timer2 through Timer5 in 16-bit
modes. In 32-bit modes, ‘x’ represents
Timer2 or Timer4; ‘y’ represents Timer3 or
Timer5.
TIMER2/3 AND TIMER4/5 BLOCK DIAGRAM (16-BIT)
Sync
TMRx
ADC Event
Trigger(1)
Equal
Comparator x 16
PRx
Reset
TxIF
Event Flag
0
1
TGATE (TxCON)
Q
TGATE (TxCON)
D
Q
TCS (TxCON)
ON (TxCON)
TxCK(2)
x1
Gate
Sync
PBCLK
10
00
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
3
TCKPS (TxCON)
Note 1: ADC event trigger is only available on Timer3.
2: TxCK pins are not available on 64-pin devices.
2009-2019 Microchip Technology Inc.
DS60001156K-page 175
PIC32MX5XX/6XX/7XX
FIGURE 14-2:
TIMER2/3 AND TIMER4/5 BLOCK DIAGRAM (32-BIT)
Reset
TMRy
MS Half Word
ADC Event
Trigger(3)
Equal
Sync
LS Half Word
32-bit Comparator
PRy
TyIF Event
Flag
TMRx
PRx
0
1
TGATE (TxCON)
Q
D
TGATE (TxCON)
Q
TCS (TxCON)
ON (TxCON)
TxCK(2)
x1
Gate
Sync
PBCLK
10
00
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
3
TCKPS (TxCON)
Note 1: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use
of ‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5.
2: TxCK pins are not available on 64-pin devices.
3: ADC event trigger is only available on the Timer2/3 pair.
DS60001156K-page 176
2009-2019 Microchip Technology Inc.
Control Registers
TABLE 14-1:
Virtual Address
(BF80_#)
TIMER2 THROUGH TIMER5 REGISTER MAP
0800 T2CON
0810
TMR2
0820
PR2
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
15:0
ON
31:16
—
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
15:0
31:16
0A10
TMR3
0A20
PR3
—
—
—
—
—
—
—
0C20
PR4
TMR5
0E20
PR5
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
15:0
17/1
16/0
—
—
—
—
0000
T32
—
TCS(2)
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
0000
FFFF
—
—
TCS(2)
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
TCKPS
0000
FFFF
T32
—
TCS(2)
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
TCKPS
TMR4
—
—
—
—
—
—
—
—
—
0000
PR4
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
15:0
15:0
—
18/2
PR3
31:16
31:16
—
TCKPS
19/3
TMR3
15:0
0E10
—
—
31:16
0E00 T5CON
—
TGATE
20/4
FFFF
—
—
TCS(2)
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
TCKPS
TMR5
—
—
—
—
—
—
—
—
—
0000
PR5
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
These bits are not available on 64-pin devices.
1:
2:
0000
FFFF
DS60001156K-page 177
PIC32MX5XX/6XX/7XX
TMR4
—
—
21/5
PR2
15:0
0C10
—
31:16
31:16
0C00 T4CON
22/6
TMR2
15:0
0A00 T3CON
23/7
All Resets
Bit Range
Bits
Register
Name(1)
2009-2019 Microchip Technology Inc.
14.2
PIC32MX5XX/6XX/7XX
REGISTER 14-1:
Bit
Range
31:24
23:16
15:8
7:0
TXCON: TYPE B TIMER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ON(1,3)
—
SIDL(4)
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
T32(2)
—
TCS(3)
—
TGATE(3)
TCKPS(3)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15
ON: Timer On bit(1,3)
1 = Module is enabled
0 = Module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit(4)
1 = Discontinue operation when device enters Idle mode
0 = Continue operation when device is in Idle mode
bit 12-8
Unimplemented: Read as ‘0’
bit 7
TGATE: Timer Gated Time Accumulation Enable bit(3)
When TCS = 1:
This bit is ignored and is read as ‘0’.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6-4
TCKPS: Timer Input Clock Prescale Select bits(3)
111 = 1:256 prescale value
110 = 1:64 prescale value
101 = 1:32 prescale value
100 = 1:16 prescale value
011 = 1:8 prescale value
010 = 1:4 prescale value
001 = 1:2 prescale value
000 = 1:1 prescale value
Note 1:
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
This bit is only available on even numbered timers (Timer2 and Timer4).
While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and Timer5). All timer functions are set through the even numbered timers.
While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
2:
3:
4:
DS60001156K-page 178
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 14-1:
TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED)
bit 3
T32: 32-Bit Timer Mode Select bit(2)
1 = Odd numbered and even numbered timers form a 32-bit timer
0 = Odd numbered and even numbered timers form a separate 16-bit timer
bit 2
Unimplemented: Read as ‘0’
bit 1
TCS: Timer Clock Source Select bit(3)
1 = External clock from TxCK pin
0 = Internal peripheral clock
bit 0
Unimplemented: Read as ‘0’
Note 1:
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
This bit is only available on even numbered timers (Timer2 and Timer4).
While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and Timer5). All timer functions are set through the even numbered timers.
While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
2:
3:
4:
2009-2019 Microchip Technology Inc.
DS60001156K-page 179
PIC32MX5XX/6XX/7XX
NOTES:
DS60001156K-page 180
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
15.0
WATCHDOG TIMER (WDT)
Note:
This section describes the operation of the WDT and
Power-up Timer of the PIC32MX5XX/6XX/7XX.
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Watchdog
Timer
and
Power-up
Timer”
(DS60001114) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
FIGURE 15-1:
The WDT, when enabled, operates from the internal
Low-Power Oscillator (LPRC) clock source and can be
used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in
software. Various WDT time-out periods can be
selected using the WDT postscaler. The WDT can also
be used to wake the device from Sleep or Idle mode.
The following are key features of the WDT module:
• Configuration or software controlled
• User-configurable time-out period
• Can wake the device from Sleep or Idle mode
WATCHDOG TIMER AND POWER-UP TIMER BLOCK DIAGRAM
PWRT Enable
WDT Enable
LPRC
Control
PWRT Enable
1:64 Output
LPRC
Oscillator
PWRT
1
Clock
25-bit Counter
WDTCLR = 1
WDT Enable
Wake
WDT Enable
Reset Event
25
WDT Counter Reset
0
Device Reset
1
NMI (Wake-up)
Power Save
Decoder
FWDTPS (DEVCFG1)
2009-2019 Microchip Technology Inc.
DS60001156K-page 181
Control Registers
WATCHDOG TIMER REGISTER MAP
0000 WDTCON
Bit Range
Register
Name(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
—
—
—
—
—
—
—
20/4
19/3
18/2
17/1
—
—
—
—
—
0000
—
WDTCLR
0000
SWDTPS
16/0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
1:
2:
All Resets(2)
Virtual Address
(BF80_#)
TABLE 15-1:
PIC32MX5XX/6XX/7XX
DS60001156K-page 182
15.1
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 15-1:
Bit
Range
31:24
23:16
15:8
7:0
WDTCON: WATCHDOG TIMER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
ON(1,2)
—
—
—
—
—
—
—
U-0
R-y
R-y
R-y
R-y
R-y
R/W-0
R/W-0
—
Legend:
SWDTPS
WDTWINEN WDTCLR
y = Values set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Watchdog Timer Enable bit(1,2)
1 = Enables the WDT if it is not enabled by the device configuration
0 = Disable the WDT if it was enabled in software
bit 14-7
Unimplemented: Read as ‘0’
bit 6-2
SWDTPS: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits
On reset, these bits are set to the values of the WDTPS Configuration bits.
bit 1
WDTWINEN: Watchdog Timer Window Enable bit
1 = Enable windowed Watchdog Timer
0 = Disable windowed Watchdog Timer
bit 0
WDTCLR: Watchdog Timer Reset bit
1 = Writing a ‘1’ will clear the WDT
0 = Software cannot force this bit to a ‘0’
Note 1:
2:
A read of this bit results in a ‘1’ if the Watchdog Timer is enabled by the device configuration or software.
When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2009-2019 Microchip Technology Inc.
DS60001156K-page 183
PIC32MX5XX/6XX/7XX
NOTES:
DS60001156K-page 184
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
16.0
Note:
INPUT CAPTURE
• Capture timer value on every edge (rising and
falling)
• Capture timer value on every edge (rising and
falling), specified edge first.
• Prescaler capture event modes:
- Capture timer value on every 4th rising edge of
input at ICx pin
- Capture timer value on every 16th rising edge of
input at ICx pin
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 15. “Input Capture” (DS60001122) of the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
The Input Capture module is useful in applications
requiring frequency (period) and pulse measurement.
The Input Capture module captures the 16-bit or 32-bit
value of the selected Time Base registers when an
event occurs at the ICx pin. The following events cause
capture events:
• Simple capture event modes:
- Capture timer value on every falling edge of input
at ICx pin
- Capture timer value on every rising edge of input
at ICx pin
FIGURE 16-1:
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base,
or two 16-bit timers (Timer2 and Timer3) together to
form a 32-bit timer. The selected timer can use either
an internal or external clock.
Other operational features include:
• Device wake-up from capture pin during Sleep and
Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
Interrupt optionally generated after 1, 2, 3 or 4 buffer
locations are filled
• Input Capture module can also be used to provide
additional sources of external interrupts
INPUT CAPTURE BLOCK DIAGRAM
ICx Input
Timer3 Timer2
ICTMR
0
1
C32
FIFO Control
ICxBUF
Prescaler
1, 4, 16
ICM
ICxBUF
Edge Detect
ICM
FEDGE
ICBNE
ICOV
ICxCON
ICI
Interrupt
Event
Generation
Data Space Interface
Interrupt
2009-2019 Microchip Technology Inc.
Peripheral Data Bus
DS60001156K-page 185
Control Registers
Virtual Address
(BF80_#)
Register
Name
TABLE 16-1:
2000
IC1CON(1)
2010
IC1BUF
2200
IC2CON(1)
2210
IC2BUF
2400
IC3CON(1)
2410
IC3BUF
2600
IC4CON(1)
2610
IC4BUF
2800
IC5CON(1)
2810
IC5BUF
INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
15:0
ON
25/9
—
—
—
—
—
—
—
SIDL
—
—
—
FEDGE
31:16
31:16
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
FEDGE
31:16
22/6
21/5
—
—
—
—
C32
ICTMR
ICI
20/4
19/3
18/2
—
—
—
ICOV
ICBNE
17/1
16/0
—
—
ICM
—
—
C32
ICTMR
31:16
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
FEDGE
31:16
—
—
C32
ICTMR
xxxx
xxxx
—
—
ICI
—
—
ICOV
ICBNE
—
—
—
ICM
31:16
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
FEDGE
31:16
—
—
C32
ICTMR
xxxx
xxxx
—
—
ICI
—
—
ICOV
ICBNE
—
—
—
ICM
31:16
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
FEDGE
—
—
C32
ICTMR
xxxx
xxxx
—
—
ICI
—
—
ICOV
ICBNE
—
—
—
ICM
0000
0000
xxxx
xxxx
—
—
ICI
—
—
ICOV
ICBNE
—
—
—
ICM
IC5BUF
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
1:
0000
0000
IC4BUF
15:0
0000
0000
IC3BUF
15:0
0000
0000
IC2BUF
15:0
15:0
23/7
IC1BUF
15:0
31:16
24/8
All Resets
Bit Range
Bits
0000
0000
xxxx
xxxx
PIC32MX5XX/6XX/7XX
DS60001156K-page 186
16.1
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 16-1:
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
31:24
23:16
15:8
7:0
ICXCON: INPUT CAPTURE ‘X’ CONTROL REGISTER
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
ON(1)
—
SIDL
—
—
—
FEDGE
C32
R/W-0
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
ICOV
ICBNE
ICTMR
ICI
ICM
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15
ON: Input Capture Module Enable bit(1)
1 = Module is enabled
0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Control bit
1 = Halt in Idle mode
0 = Continue to operate in Idle mode
bit 12-10
Unimplemented: Read as ‘0’
bit 9
FEDGE: First Capture Edge Select bit (only used in mode 6, ICM = 110)
1 = Capture rising edge first
0 = Capture falling edge first
bit 8
C32: 32-bit Capture Select bit
1 = 32-bit timer resource capture
0 = 16-bit timer resource capture
bit 7
ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON) is ‘1’)
1 = Timer2 is the counter source for capture
0 = Timer3 is the counter source for capture
bit 6-5
ICI: Interrupt Control bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4
ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture overflow is occurred
0 = No input capture overflow is occurred
bit 3
ICBNE: Input Capture Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty; at least one more capture value can be read
0 = Input capture buffer is empty
Note 1:
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2009-2019 Microchip Technology Inc.
DS60001156K-page 187
PIC32MX5XX/6XX/7XX
REGISTER 16-1:
bit 2-0
Note 1:
ICXCON: INPUT CAPTURE ‘X’ CONTROL REGISTER (CONTINUED)
ICM: Input Capture Mode Select bits
111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter
101 = Prescaled Capture Event mode – every sixteenth rising edge
100 = Prescaled Capture Event mode – every fourth rising edge
011 = Simple Capture Event mode – every rising edge
010 = Simple Capture Event mode – every falling edge
001 = Edge Detect mode – every edge (rising and falling)
000 = Input Capture module is disabled
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS60001156K-page 188
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
17.0
Note:
OUTPUT COMPARE
The following are key features of the Output Compare
module:
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 16. “Output Compare” (DS60001111) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
• Multiple Output Compare modules in a device
• Programmable interrupt generation on compare
event
• Single and Dual Compare modes
• Single and continuous output pulse generation
• Pulse-Width Modulation (PWM) mode
• Hardware-based PWM Fault detection and
automatic output disable
• Programmable selection of 16-bit or 32-bit time
bases
• Can operate from either of two available 16-bit
time bases or a single 32-bit time base
The Output Compare module is used to generate a
single pulse or a series of pulses in response to
selected time base events. For all modes of operation,
the Output Compare module compares the values
stored in the OCxR and/or the OCxRS registers to the
value in the selected timer. When a match occurs, the
Output Compare module generates an event based on
the selected mode of operation.
FIGURE 17-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit
OCxIF(1)
OCxRS(1)
Output
Logic
OCxR(1)
3
OCM
Mode Select
Comparator
0
16
OCTSEL
1
0
S
R
Output
Enable
Q
OCx(1)
Output Enable
Logic
OCFA or OCFB(2)
1
16
TMR Register Inputs
from Time Bases(3)
Period Match Signals
from Time Bases(3)
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels,
1 through 5.
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.
3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base.
2009-2019 Microchip Technology Inc.
DS60001156K-page 189
Control Registers
Virtual Address
(BF80_#)
TABLE 17-1:
OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP
3000 OC1CON
3010
OC1R
3020
OC1RS
3200 OC2CON
3210
OC2R
3220
OC2RS
3400 OC3CON
3410
OC3R
3420
OC3RS
3600 OC4CON
3610
OC4R
3620
OC4RS
2009-2019 Microchip Technology Inc.
3800 OC5CON
3810
OC5R
3820
OC5RS
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
15:0
ON
—
—
—
—
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
OC32
31:16
21/5
20/4
19/3
18/2
—
—
—
OCFLT
OCTSEL
31:16
0000
xxxx
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM
31:16
0000
xxxx
xxxx
OC2RS
15:0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM
31:16
15:0
0000
xxxx
xxxx
OC3RS
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM
31:16
15:0
0000
xxxx
xxxx
OC4RS
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
—
—
—
OCM
OC5R
OC5RS
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
0000
xxxx
OC4R
15:0
0000
xxxx
OC3R
15:0
0000
xxxx
OC2R
15:0
0000
xxxx
—
15:0
—
xxxx
31:16
31:16
—
OCM
OC1RS
15:0
15:0
16/0
OC1R
15:0
31:16
17/1
All Resets
Bit Range
Register
Name(1)
Bits
0000
0000
xxxx
xxxx
xxxx
xxxx
PIC32MX5XX/6XX/7XX
DS60001156K-page 190
17.1
PIC32MX5XX/6XX/7XX
REGISTER 17-1:
Bit
Range
31:24
23:16
15:8
7:0
OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
ON(1)
—
SIDL
—
—
—
—
—
U-0
U-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
OC32
OCFLT(2)
OCTSEL
OCM
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Output Compare Module On bit(1)
1 = Output Compare module is enabled
0 = Output Compare module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters Idle mode
0 = Continue operation when CPU is in Idle mode
bit 12-6
Unimplemented: Read as ‘0’
bit 5
OC32: 32-bit Compare Mode bit
1 = OCxR and/or OCxRS are used for comparisons to the 32-bit timer source
0 = OCxR and OCxRS are used for comparisons to the 16-bit timer source
bit 4
OCFLT: PWM Fault Condition Status bit(2)
1 = PWM Fault condition has occurred (only cleared in hardware)
0 = PWM Fault condition has not occurred
bit 3
OCTSEL: Output Compare Timer Select bit
1 = Timer3 is the clock source for this Output Compare module
0 = Timer2 is the clock source for this Output Compare module
bit 2-0
OCM: Output Compare Mode Select bits
111 = PWM mode on OCx; Fault pin enabled
110 = PWM mode on OCx; Fault pin disabled
101 = Initialize OCx pin low; generate continuous output pulses on OCx pin
100 = Initialize OCx pin low; generate single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initialize OCx pin high; compare event forces OCx pin low
001 = Initialize OCx pin low; compare event forces OCx pin high
000 = Output compare peripheral is disabled but continues to draw current
Note 1:
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
This bit is only used when OCM = 111. It is read as ‘0’ in all other modes.
2:
2009-2019 Microchip Technology Inc.
DS60001156K-page 191
PIC32MX5XX/6XX/7XX
NOTES:
DS60001156K-page 192
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
18.0
Note:
SERIAL PERIPHERAL
INTERFACE (SPI)
The following are some of the key features of the SPI
module:
•
•
•
•
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To complement the information in this data sheet,
refer to Section 23. “Serial Peripheral
Interface (SPI)” (DS60001106) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
•
•
•
•
The SPI module is a synchronous serial interface that
is useful for communicating with external peripherals
and other microcontroller devices. These peripheral
devices may be Serial EEPROMs, Shift registers, display drivers, Analog-to-Digital Converters, etc. The
PIC32 SPI module is compatible with Motorola® SPI
and SIOP interfaces.
FIGURE 18-1:
Master mode and Slave mode support
Four different clock formats
Enhanced Framed SPI protocol support
User-configurable 8-bit, 16-bit and 32-bit data
width
Separate SPI FIFO buffers for receive and transmit
- FIFO buffers act as 4/8/16-level deep FIFOs
based on 32/16/8-bit data width
Programmable interrupt event on every 8-bit,
16-bit and 32-bit data transfer
Operation during Sleep and Idle modes
Fast bit manipulation using CLR, SET and INV
registers
SPI MODULE BLOCK DIAGRAM
Internal
Data Bus
SPIxBUF
Read
Write
SPIxRXB FIFO
FIFOs Share Address SPIxBUF
SPIxTXB FIFO
Transmit
Receive
SPIxSR
SDIx
bit 0
SDOx
SSx/FSYNC
Slave Select
and Frame
Sync Control
Shift
Control
Clock
Control
Edge
Select
SCKx
Baud Rate
Generator
PBCLK
Enable Master Clock
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.
2009-2019 Microchip Technology Inc.
DS60001156K-page 193
Control Registers
Virtual Address
(BF80_#)
TABLE 18-1:
5E10 SPI1STAT(2)
5E20 SPI1BUF(2)
5E30 SPI1BRG(2)
5800
SPI3CON
5810
SPI3STAT
5820
SPI3BUF
5830
SPI3BRG
5A00
SPI2CON
2009-2019 Microchip Technology Inc.
5A10
SPI2STAT
5A20
SPI2BUF
5A30
SPI2BRG
5C00
SPI4CON
5C10
SPI4STAT
5C20
SPI4BUF
SPI4BRG
31/15
30/14
29/13
31:16
FRMEN
15:0
ON
FRMSYNC FRMPOL
—
SIDL
31:16
—
—
—
15:0
—
—
—
28/12
27/11
26/10
MSSEN
FRMSYPW
DISSDO
MODE32
25/9
SMP
—
SPIBUSY
—
—
SSEN
—
—
—
SRMT
SPIROV
SPIRBE
SPITUR
22/6
21/5
20/4
19/3
18/2
17/1
—
—
CKP
MSTEN
—
—
—
SPIFE
—
STXISEL
16/0
ENHBUF 0000
SRXISEL
TXBUFELM
—
SPITBE
—
—
15:0
—
FRMEN
—
—
—
—
FRMSYNC FRMPOL
15:0
ON
—
SIDL
31:16
—
—
—
15:0
—
—
—
—
—
—
—
—
—
MSSEN
FRMSYPW
DISSDO
MODE32
—
—
SPITBF
SPIRBF
—
SPIBUSY
0000
—
—
—
—
—
—
MODE16
SMP
SSEN
CKP
MSTEN
—
—
—
—
—
31:16
SRMT
SPIROV
SPIRBE
—
—
—
—
—
—
—
SPIFE
—
STXISEL
—
BRG
CKE
RXBUFELM
SPITUR
0000
SRXISEL
TXBUFELM
—
—
15:0
—
31:16
FRMEN
—
—
—
—
FRMSYNC FRMPOL
15:0
ON
—
SIDL
31:16
—
—
—
15:0
—
—
—
—
—
—
—
—
—
MSSEN
FRMSYPW
DISSDO
MODE32
—
—
SPITBE
—
SPITBF
SPIRBF
MODE16
SMP
CKE
—
SPIBUSY
—
—
31:16
SPITUR
—
—
—
—
—
SSEN
CKP
MSTEN
—
—
—
SRMT
SPIROV
SPIRBE
—
—
—
—
—
—
—
SPIFE
—
STXISEL
—
0000
SRXISEL
TXBUFELM
—
—
15:0
—
31:16
FRMEN
—
—
—
—
FRMSYNC FRMPOL
15:0
ON
—
SIDL
31:16
—
—
—
15:0
—
—
—
—
—
—
—
—
—
MSSEN
FRMSYPW
DISSDO
MODE32
—
—
SPITBE
—
SPITBF
SPIRBF
MODE16
SMP
CKE
—
SPIBUSY
—
—
31:16
SPITUR
—
—
—
—
—
SSEN
CKP
MSTEN
—
—
—
SRMT
SPIROV
SPIRBE
—
—
—
—
—
—
—
SPIFE
—
STXISEL
—
0000
SRXISEL
TXBUFELM
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
0000
ENHBUF 0000
SPITBE
—
0000
0000
SPITBF
SPIRBF
0008
0000
DATA
15:0
0008
0000
—
BRG
RXBUFELM
0000
0000
0000
—
FRMCNT
0000
ENHBUF 0000
DATA
15:0
0008
0000
—
BRG
RXBUFELM
0000
0000
0000
—
FRMCNT
0000
ENHBUF 0000
DATA
15:0
0008
0000
—
FRMCNT
0000
0000
DATA
31:16
31:16
—
CKE
RXBUFELM
15:0
31:16
23/7
FRMCNT
MODE16
31:16
31:16
24/8
All Resets
Bit Range
Register
Name(1)
Bits
5E00 SPI1CON(2)
5C30
SPI1 THROUGH SPI4 REGISTER MAP
0000
—
—
—
BRG
—
—
—
—
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
This register is not available on 64-pin devices.
1:
2:
PIC32MX5XX/6XX/7XX
DS60001156K-page 194
18.1
PIC32MX5XX/6XX/7XX
REGISTER 18-1:
Bit
Range
31:24
23:16
15:8
7:0
SPIxCON: SPI CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMEN
FRMSYNC
FRMPOL
MSSEN
FRMSYPW
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
SPIFE
ENHBUF(2)
FRMCNT
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ON(1)
—
SIDL
DISSDO
MODE32
MODE16
SMP
CKE(3)
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEN
CKP
MSTEN
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
STXISEL
SRXISEL
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
FRMEN: Framed SPI Support bit
1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)
0 = Framed SPI support is disabled
bit 30
FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (only Framed SPI mode)
1 = Frame sync pulse input (Slave mode)
0 = Frame sync pulse output (Master mode)
bit 29
FRMPOL: Frame Sync/Slave Select Polarity bit (Framed SPI or Master Transmit modes only)
1 = Frame pulse or SSx pin is active-high
0 = Frame pulse or SSx pin is active-low
bit 28
MSSEN: Master Mode Slave Select Enable bit
1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in
Master mode. Polarity is determined by the FRMPOL bit.
0 = Slave select SPI support is disabled.
bit 27
FRMSYPW: Frame Sync Pulse Width bit
1 = Frame sync pulse is one character wide
0 = Frame sync pulse is one clock wide
bit 26-24 FRMCNT: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per
pulse. This bit is only valid in Framed Sync mode.
111 = Reserved
110 = Reserved
101 = Generate a frame sync pulse on every 32 data characters
100 = Generate a frame sync pulse on every 16 data characters
011 = Generate a frame sync pulse on every 8 data characters
010 = Generate a frame sync pulse on every 4 data characters
001 = Generate a frame sync pulse on every 2 data characters
000 = Generate a frame sync pulse on every data character
bit 23-18 Unimplemented: Read as ‘0’
bit 17
SPIFE: Frame Sync Pulse Edge Select bit (only Framed SPI mode)
1 = Frame synchronization pulse coincides with the first bit clock
0 = Frame synchronization pulse precedes the first bit clock
ENHBUF: Enhanced Buffer Enable bit(2)
1 = Enhanced Buffer mode is enabled
0 = Enhanced Buffer mode is disabled
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit can only be written when the ON bit = 0.
3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
bit 16
2009-2019 Microchip Technology Inc.
DS60001156K-page 195
PIC32MX5XX/6XX/7XX
REGISTER 18-1:
SPIxCON: SPI CONTROL REGISTER (CONTINUED)
ON: SPI Peripheral On bit(1)
1 = SPI Peripheral is enabled
0 = SPI Peripheral is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters in Idle mode
0 = Continue operation in Idle mode
bit 12
DISSDO: Disable SDOx pin bit
1 = SDOx pin is not used by the module (pin is controlled by associated PORT register)
0 = SDOx pin is controlled by the module
bit 11-10 MODE: 32/16-Bit Communication Select bits
MODE16
Communication
MODE32
1
x
32-bit
0
1
16-bit
0
0
8-bit
bit 9
SMP: SPI Data Input Sample Phase bit
Master mode (MSTEN = 1):
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
bit 15
Slave mode (MSTEN = 0):
SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.
CKE: SPI Clock Edge Select bit(3)
1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
SSEN: Slave Select Enable (Slave mode) bit
1 = SSx pin used for Slave mode
0 = SSx pin not used for Slave mode (pin is controlled by port function)
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
Unimplemented: Read as ‘0’
STXISEL: SPI Transmit Buffer Empty Interrupt Mode bits
11 = Interrupt is generated when the buffer is not full (has one or more empty elements)
10 = Interrupt is generated when the buffer is empty by one-half or more
01 = Interrupt is generated when the buffer is completely empty
00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are
complete
SRXISEL: SPI Receive Buffer Full Interrupt Mode bits
11 = Interrupt is generated when the buffer is full
10 = Interrupt is generated when the buffer is full by one-half or more
01 = Interrupt is generated when the buffer is not empty
00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3-2
bit 1-0
Note 1:
2:
3:
When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
This bit can only be written when the ON bit = 0.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
DS60001156K-page 196
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 18-2:
Bit
Range
31:24
23:16
15:8
7:0
SPIxSTAT: SPI STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
U-0
R-0
SPITUR
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
RXBUFELM
R-0
TXBUFELM
U-0
R-0
U-0
—
—
—
—
SPIBUSY
—
—
R-0
R/W-0
R-0
U-0
R-1
U-0
R-0
R-0
SRMT
SPIROV
SPIRBE
—
SPITBE
—
SPITBF
SPIRBF
Legend:
C = Clearable bit
HS = Set in hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 RXBUFELM: Receive Buffer Element Count bits (only valid when ENHBUF = 1)
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFELM: Transmit Buffer Element Count bits (only valid when ENHBUF = 1)
bit 15-12 Unimplemented: Read as ‘0’
bit 11
SPIBUSY: SPI Activity Status bit
1 = SPI peripheral is currently busy with some transactions
0 = SPI peripheral is currently idle
bit 10-9
Unimplemented: Read as ‘0’
bit 8
SPITUR: Transmit Under Run bit
1 = Transmit buffer has encountered an underrun condition
0 = Transmit buffer has no underrun condition
This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling
the module.
bit 7
SRMT: Shift Register Empty bit (only valid when ENHBUF = 1)
1 = When SPI module shift register is empty
0 = When SPI module shift register is not empty
bit 6
SPIROV: Receive Overflow Flag bit
1 = A new data is completely received and discarded. The user software has not read the previous data in
the SPIxBUF register.
0 = No overflow has occurred
This bit is set in hardware; can only be cleared (= 0) in software.
bit 5
SPIRBE: RX FIFO Empty bit (only valid when ENHBUF = 1)
1 = RX FIFO is empty (CRPTR = SWPTR)
0 = RX FIFO is not empty (CRPTR SWPTR)
bit 4
Unimplemented: Read as ‘0’
bit 3
SPITBE: SPI Transmit Buffer Empty Status bit
1 = Transmit buffer, SPIxTXB is empty
0 = Transmit buffer, SPIxTXB is not empty
Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR.
Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.
bit 2
Unimplemented: Read as ‘0’
2009-2019 Microchip Technology Inc.
DS60001156K-page 197
PIC32MX5XX/6XX/7XX
REGISTER 18-2:
bit 1
SPIxSTAT: SPI STATUS REGISTER
SPITBF: SPI Transmit Buffer Full Status bit
1 = Transmit not yet started, SPITXB is full
0 = Transmit buffer is not full
Standard Buffer Mode:
Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB.
Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR.
Enhanced Buffer Mode:
Set when CWPTR + 1 = SRPTR; cleared otherwise
bit 0
SPIRBF: SPI Receive Buffer Full Status bit
1 = Receive buffer, SPIxRXB is full
0 = Receive buffer, SPIxRXB is not full
Standard Buffer Mode:
Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer Mode:
Set when SWPTR + 1 = CRPTR; cleared otherwise
DS60001156K-page 198
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
19.0
Note:
INTER-INTEGRATED CIRCUIT
(I2C)
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 24. “InterIntegrated Circuit (I2C)” (DS60001116)
in the “PIC32 Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
2009-2019 Microchip Technology Inc.
The I2C module provides complete hardware support
for both Slave and Multi-Master modes of the I2C serial
communication standard. Figure 19-1 illustrates the
I2C module block diagram.
Each I2C module has a 2-pin interface: the SCLx pin is
clock and the SDAx pin is data.
Each I2C module offers the following key features:
• I2C interface supporting both master and slave
operation
• I2C Slave mode supports 7-bit and 10-bit addressing
• I2C Master mode supports 7-bit and 10-bit
addressing
• I2C port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for the I2C port can
be used as a handshake mechanism to suspend
and resume serial transfer (SCLREL control)
• I2C supports multi-master operation; detects bus
collision and arbitrates accordingly
• Provides support for address bit masking
DS60001156K-page 199
PIC32MX5XX/6XX/7XX
FIGURE 19-1:
I2C BLOCK DIAGRAM
Internal
Data Bus
I2CxRCV
SCLx
Read
Shift
Clock
I2CxRSR
LSB
SDAx
Address Match
Match Detect
Write
I2CxMSK
Write
Read
I2CxADD
Read
Start and Stop
bit Detect
Write
Start and Stop
bit Generation
Control Logic
I2CxSTAT
Collision
Detect
Read
Write
I2CxCON
Acknowledge
Generation
Read
Clock
Stretching
Write
I2CxTRN
LSB
Read
Shift Clock
Reload
Control
BRG Down Counter
Write
I2CxBRG
Read
PBCLK
DS60001156K-page 200
2009-2019 Microchip Technology Inc.
Control Registers
Register
Name(1)
TABLE 19-1:
Virtual Address
(BF80_#)
5000
I2C3CON
5010
I2C3STAT
5020
I2C3ADD
I2C3MSK
5040
I2C3BRG
5050
I2C3TRN
I2C3RCV
5100
I2C4CON
5110
I2C4STAT
5120
I2C4ADD
5130
I2C4MSK
5140
I2C4BRG
DS60001156K-page 201
5150
I2C4TRN
5160
I2C4RCV
5200
I2C5CON
I2C5STAT
5220
I2C5ADD
31/15
30/14
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
0000
—
—
—
0000
0000
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
ADD
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
MSK
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
0000
Baud Rate Generator Register
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
0000
Transmit Register
—
—
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Register
0000
15:0
ON
—
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
0000
—
—
—
0000
0000
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
ADD
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
MSK
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
0000
Baud Rate Generator Register
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
0000
Transmit Register
—
—
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Register
0000
15:0
ON
—
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
ADD
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
This register is not available on 64-pin devices.
1:
2:
PIC32MX5XX/6XX/7XX
5060
29/13
All Resets
Bits
5030
5210
I2C1THROUGH I2C5 REGISTER MAP
Bit Range
2009-2019 Microchip Technology Inc.
19.1
Virtual Address
(BF80_#)
Register
Name(1)
5230
I2C5MSK
I2C5BRG
5250
I2C5TRN
5260
I2C5RCV
5300
I2C1CON
I2C1STAT
5320
I2C1ADD
5330
I2C1MSK
5340
I2C1BRG
5350
I2C1TRN
5360
I2C1RCV
5400 I2C2CON(2)
5410 I2C2STAT(2)
2009-2019 Microchip Technology Inc.
5420 I2C2ADD(2)
5430 I2C2MSK(2)
5440 I2C2BRG(2)
5450 I2C2TRN(2)
5460 I2C2RCV(2)
Legend:
Note
All Resets
Bit Range
Bits
5240
5310
I2C1THROUGH I2C5 REGISTER MAP (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
0000
0000
MSK
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
0000
Baud Rate Generator Register
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
0000
Transmit Register
—
—
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Register
0000
15:0
ON
—
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
0000
—
—
—
0000
0000
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
ADD
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
MSK
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
0000
Baud Rate Generator Register
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
0000
Transmit Register
—
—
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Register
0000
15:0
ON
—
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
0000
—
—
—
0000
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
ADD
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
MSK
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
0000
Baud Rate Generator Register
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
0000
Transmit Register
—
—
Receive Register
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
This register is not available on 64-pin devices.
PIC32MX5XX/6XX/7XX
DS60001156K-page 202
TABLE 19-1:
PIC32MX5XX/6XX/7XX
REGISTER 19-1:
Bit
Range
31:24
23:16
15:8
7:0
I2CXCON: I2C CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
R/W-1, HC
R/W-0
R/W-0
R/W-0
R/W-0
ON(1)
—
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
R/W-0
R/W-0
R/W-0
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
Legend:
HC = Cleared by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: I2C Enable bit(1)
1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins
0 = Disables the I2C module; all I2C pins are controlled by PORT functions
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation when device enters Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1 = Release SCLx clock
0 = Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Cleared by hardware at
the beginning of a slave transmission and at the end of slave reception.
If STREN = 0:
Bit is R/S (software can only write ‘1’ to release clock). Cleared by hardware at the beginning of slave
transmission.
bit 11
STRICT: Strict I2C Reserved Address Rule Enable bit
1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate
addresses in reserved address space.
0 = Strict I2C reserved address rule is not enabled
bit 10
A10M: 10-bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
bit 8
SMEN: SMBus Input Levels bit
1 = Enable I/O pin thresholds compliant with SMBus specification
0 = Disable SMBus input thresholds
Note 1:
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2009-2019 Microchip Technology Inc.
DS60001156K-page 203
PIC32MX5XX/6XX/7XX
REGISTER 19-1:
I2CXCON: I2C CONTROL REGISTER (CONTINUED)
bit 7
GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enable interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0 = General call address is disabled
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
bit 5
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an acknowledge sequence.
1 = Send NACK during an acknowledge
0 = Send ACK during an acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master
receive)
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Hardware clear at end of master Acknowledge sequence.
0 = Acknowledge sequence not in progress
bit 3
RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.
0 = Receive sequence is not in progress
bit 2
PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0 = Stop condition is not in progress
bit 1
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated
Start sequence.
0 = Repeated Start condition is not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0 = Start condition is not in progress
Note 1:
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS60001156K-page 204
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 19-2:
Bit
Range
31:24
23:16
15:8
7:0
I2CXSTAT: I2C STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0, HSC
R-0, HSC
U-0
U-0
U-0
R/C-0, HS
R-0, HSC
R-0, HSC
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
R/C-0, HS
R/C-0, HS
R-0, HSC
R/C-0, HSC
R/C-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
Legend:
HS = Set by hardware
HSC = Hardware set/cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
C = Clearable bit
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation)
This bit is set or cleared by hardware at the end of a slave Acknowledge.
1 = NACK received from slave
0 = ACK received from slave
bit 14
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
This bit is set by hardware at the beginning of a master transmission, and is cleared by hardware at the end
of a slave Acknowledge.
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
bit 13-11 Unimplemented: Read as ‘0’
bit 10
BCL: Master Bus Collision Detect bit
This bit is set by hardware at the detection of a bus collision.
1 = A bus collision has been detected during a master operation
0 = No collision
bit 9
GCSTAT: General Call Status bit
This bit is set by hardware when the address matches the general call address, and is cleared by hardware
clear at a Stop detection.
1 = General call address was received
0 = General call address was not received
bit 8
ADD10: 10-bit Address Status bit
This bit is set by hardware upon a match of the 2nd byte of the matched 10-bit address, and is cleared by
hardware at a Stop detection.
1 = 10-bit address was matched
0 = 10-bit address was not matched
bit 7
IWCOL: Write Collision Detect bit
This bit is set by hardware at the occurrence of a write to I2CxTRN while busy (cleared by software).
1 = An attempt to write the I2CxTRN register failed because the I2C module is busy
0 = No collision
bit 6
I2COV: Receive Overflow Flag bit
This bit is set by hardware at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
2009-2019 Microchip Technology Inc.
DS60001156K-page 205
PIC32MX5XX/6XX/7XX
REGISTER 19-2:
I2CXSTAT: I2C STATUS REGISTER (CONTINUED)
bit 5
D_A: Data/Address bit (when operating as I2C slave)
This bit is cleared by hardware upon a device address match, and is set by hardware by reception of the
slave byte.
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
bit 4
P: Stop bit
This bit is set or cleared by hardware when a Start, Repeated Start, or Stop condition is detected.
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
bit 3
S: Start bit
This bit is set or cleared by hardware when a Start, Repeated Start, or Stop condition is detected.
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
bit 2
R_W: Read/Write Information bit (when operating as I2C slave)
This bit is set or cleared by hardware after reception of an I 2C device address byte.
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
bit 1
RBF: Receive Buffer Full Status bit
This bit is set by hardware when the I2CxRCV register is written with a received byte, and is cleared by
hardware when software reads I2CxRCV.
1 = Receive complete, I2CxRCV is full
0 = Receive not complete, I2CxRCV is empty
bit 0
TBF: Transmit Buffer Full Status bit
This bit is set by hardware when software writes to the I2CxTRN register, and is cleared by hardware upon
completion of data transmission.
1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty
DS60001156K-page 206
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
20.0
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Note:
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 21. “Universal
Asynchronous Receiver Transmitter
(UART)” (DS60001107) in the “PIC32
Family Reference Manual”, which is available from the Microchip web site
(www.microchip.com/PIC32).
The UART module is one of the serial I/O modules
available in the PIC32MX5XX/6XX/7XX family of
devices. The UART is a full-duplex, asynchronous
communication channel that communicates with
peripheral devices and personal computers through
protocols, such as RS-232, RS-485, LIN 1.2 and IrDA®.
The module also supports the hardware flow control
option, with UxCTS and UxRTS pins, and also includes
an IrDA encoder and decoder.
The following are primary features of the UART
module:
•
•
•
•
•
•
•
•
•
•
•
•
•
Full-duplex, 8-bit or 9-bit data transmission
Even, Odd or No Parity options (for 8-bit data)
One or two Stop bits
Hardware auto-baud feature
Hardware flow control option
Fully integrated Baud Rate Generator (BRG) with
16-bit prescaler
Baud rates ranging from 76 bps to 20 Mbps at
80 MHz
8-level deep First-In-First-Out (FIFO) transmit
data buffer
8-level deep FIFO receive data buffer
Parity, framing and buffer overrun error detection
Support for interrupt-only on address detect
(ninth bit = 1)
Separate transmit and receive interrupts
Loopback mode for diagnostic support
• LIN 2.1 Protocol support
• IrDA encoder and decoder with 16x baud clock
output for external IrDA encoder/decoder support
Figure 20-1 illustrates a simplified block diagram of the
UART module.
FIGURE 20-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
Hardware Flow Control
Note:
BCLKx
UxRTS
UxCTS
UARTx Receiver
UxRX
UARTx Transmitter
UxTX
Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information
(see “Device Pin Tables”).
2009-2019 Microchip Technology Inc.
DS60001156K-page 207
PIC32MX5XX/6XX/7XX
Figure 20-2 and Figure 20-3 illustrate typical receive
and transmit timing for the UART module.
FIGURE 20-2:
UART RECEPTION
Char 1
Char 2-4
Char 5-10
Char 11-13
Read to
UxRXREG
UxRX
Start 1
Stop
Start 2
Start 5
Stop 4
Stop 10 Start 11
Stop 13
RIDLE
Cleared by
Software
OERR
Cleared by
Software
UxRXIF
URXISEL = 00
Cleared by
Software
UxRXIF
URXISEL = 01
UxRXIF
URXISEL = 10
FIGURE 20-3:
TRANSMISSION (8-BIT OR 9-BIT DATA)
8 into TxBUF
Write to
UxTXREG
TSR
Pull from Buffer
BCLK/16
(Shift Clock)
UxTX
Start
Bit 0
Bit 1
Stop
Start
Bit 1
UxTXIF
UTXISEL = 00
UxTXIF
UTXISEL = 01
UxTXIF
UTXISEL = 10
DS60001156K-page 208
2009-2019 Microchip Technology Inc.
Control Registers
TABLE 20-1:
Virtual Address
(BF80_#)
UART1 THROUGH UART6 REGISTER MAP
6000 U1MODE(1)
6010
U1STA(1)
6020
U1TXREG
6030
U1RXREG
6040
U1BRG(1)
6200 U4MODE(1)
(1)
U4STA
6220
U4TXREG
6230
U4RXREG
6240
(1)
U4BRG
U3STA(1)
DS60001156K-page 209
6420
U3TXREG
6430
U3RXREG
6440
U3BRG(1)
6600 U6MODE
(1)
U6STA(1)
6610
29/13
31:16
—
—
—
15:0
ON
—
SIDL
31:16
—
—
—
28/12
27/11
26/10
25/9
24/8
—
—
—
—
—
IREN
RTSMD
—
—
—
—
—
ADM_EN
UEN
15:0
UTXISEL
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
23/7
22/6
21/5
20/4
19/3
18/2
17/1
—
—
—
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL
16/0
—
STSEL
ADDR
URXISEL
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
—
0000
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
0000
STSEL
0000
Transmit Register
—
—
0000
Receive Register
0000
BRG
0000
—
—
—
—
—
—
—
—
—
—
—
—
ON
—
SIDL
IREN
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
31:16
—
—
—
—
—
—
—
ADM_EN
15:0
UTXISEL
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
IREN
RTSMD
—
31:16
—
—
—
—
—
—
—
ADM_EN
PDSEL
ADDR
URXISEL
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
0000
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
Transmit Register
—
—
0000
Receive Register
0000
BRG
UEN
15:0
UTXISEL
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
31:16
—
—
—
—
—
—
—
—
0000
PDSEL
STSEL
ADDR
URXISEL
0000
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
0000
STSEL
0000
15:0
—
—
—
—
—
—
—
TX8
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
IREN
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
31:16
—
—
—
—
—
—
—
ADM_EN
15:0
UTXISEL
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
Transmit Register
—
—
0000
Receive Register
0000
BRG
0000
PDSEL
ADDR
URXISEL
ADDEN
RIDLE
PERR
0000
FERR
OERR
URXDA
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
1:
0000
—
31:16
15:0
0000
0000
—
—
31:16
0000
—
31:16
15:0
15:0
6400 U3MODE(1)
6410
30/14
0110
PIC32MX5XX/6XX/7XX
6210
31/15
All Resets
Bit Range
Bits
Register
Name
2009-2019 Microchip Technology Inc.
20.1
Virtual Address
(BF80_#)
Register
Name
6620
U6TXREG
6630
U6RXREG
U6BRG(1)
6800 U2MODE(1)
U2STA(1)
6810
U2TXREG
6830
U2RXREG
6840
U2BRG(1)
6A00 U5MODE(1)
6A10
U5STA(1)
6A20
U5TXREG
6A30
U5RXREG
U5BRG(1)
6A40
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
RX8
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
IREN
RTSMD
—
31:16
—
—
—
—
—
—
—
ADM_EN
15:0
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
0000
—
—
—
0000
0000
Transmit Register
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
Receive Register
0000
BRG
UEN
15:0
UTXISEL
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
31:16
—
—
—
—
—
—
—
—
0000
PDSEL
STSEL
ADDR
URXISEL
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
—
0000
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
0000
STSEL
0000
—
—
—
—
—
—
—
TX8
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
IREN
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
31:16
—
—
—
—
—
—
—
ADM_EN
15:0
UTXISEL
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
31:16
—
—
—
—
—
—
—
—
Transmit Register
—
—
0000
Receive Register
0000
BRG
15:0
—
—
—
—
—
—
—
TX8
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
2009-2019 Microchip Technology Inc.
15:0
0000
PDSEL
ADDR
URXISEL
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
0000
—
—
—
0000
—
—
—
0000
—
—
—
—
—
—
—
—
—
Transmit Register
—
—
0000
Receive Register
—
—
0000
BRG
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
1:
0000
0000
—
15:0
31:16
0000
—
31:16
15:0
All Resets
Bit Range
Bits
6640
6820
UART1 THROUGH UART6 REGISTER MAP (CONTINUED)
0000
PIC32MX5XX/6XX/7XX
DS60001156K-page 210
TABLE 20-1:
PIC32MX5XX/6XX/7XX
REGISTER 20-1:
Bit
Range
31:24
23:16
15:8
7:0
UxMODE: UARTx MODE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
ON(1)
—
SIDL
IREN
RTSMD
—
R/W-0
R/W-0
R/W-0, HC
R/W-0
R/W-0
R/W-0
WAKE
LPBACK
ABAUD
RXINV
BRGH
Legend:
R/W-0
UEN
R/W-0
PDSEL
R/W-0
STSEL
HC = Cleared by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: UARTx Enable bit(1)
1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN and UTXEN
control bits.
0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx
registers; UARTx power consumption is minimal.
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation when device enters Idle mode
bit 12
IREN: IrDA Encoder and Decoder Enable bit
1 = IrDA is enabled
0 = IrDA is disabled
bit 11
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
bit 9-8
UEN: UARTx Enable bits
11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by
corresponding bits in the PORTx register
bit 7
WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit
1 = Wake-up is enabled
0 = Wake-up is disabled
bit 6
LPBACK: UARTx Loopback Mode Select bit
1 = Loopback mode is enabled
0 = Loopback mode is disabled
Note 1:
When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2009-2019 Microchip Technology Inc.
DS60001156K-page 211
PIC32MX5XX/6XX/7XX
REGISTER 20-1:
UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 5
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of Sync character (0x55);
cleared by hardware upon completion
0 = Baud rate measurement disabled or completed
bit 4
RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1 = High-Speed mode – 4x baud clock enabled
0 = Standard Speed mode – 16x baud clock enabled
bit 2-1
PDSEL: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0
STSEL: Stop Selection bit
1 = 2 Stop bits
0 = 1 Stop bit
Note 1:
When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS60001156K-page 212
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 20-2:
Bit
Range
31:24
23:16
15:8
7:0
UxSTA: UARTx STATUS AND CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
ADM_EN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-1
TRMT
ADDR
R/W-0
R/W-0
UTXISEL
R/W-0
R/W-0
URXISEL
R/W-0
R/W-0
R/W-0, HC
R/W-0
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
R/W-0
R-1
R-0
R-0
R/W-0, HS
R-0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
Legend:
HS = Set by hardware
HC = Cleared by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-25 Unimplemented: Read as ‘0’
bit 24
ADM_EN: Automatic Address Detect Mode Enable bit
1 = Automatic Address Detect mode is enabled
0 = Automatic Address Detect mode is disabled
bit 23-16 ADDR: Automatic Address Mask bits
When the ADM_EN bit is ‘1’, this value defines the address character to use for automatic address
detection.
bit 15-14 UTXISEL: TX Interrupt Mode Selection bits
11 = Reserved, do not use
10 = Interrupt is generated and asserted while the transmit buffer is empty
01 = Interrupt is generated and asserted when all characters have been transmitted
00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space
bit 13
UTXINV: Transmit Polarity Inversion bit
If IrDA mode is disabled (i.e., IREN (UxMODE) is ‘0’):
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IrDA mode is enabled (i.e., IREN (UxMODE) is ‘1’):
1 = IrDA encoded UxTX Idle state is ‘1’
0 = IrDA encoded UxTX Idle state is ‘0’
bit 12
URXEN: Receiver Enable bit
1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)
0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module. UxRX pin is controlled by port.
bit 11
UTXBRK: Transmit Break bit
1 = Send Break on next transmission. Start bit followed by twelve ‘0’ bits, followed by Stop bit; cleared by
hardware upon completion.
0 = Break transmission is disabled or completed
bit 10
UTXEN: Transmit Enable bit
1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)
0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is
controlled by port.
bit 9
UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
2009-2019 Microchip Technology Inc.
DS60001156K-page 213
PIC32MX5XX/6XX/7XX
REGISTER 20-2:
UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 8
TRMT: Transmit Shift Register is Empty bit (read-only)
1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
bit 7-6
URXISEL: Receive Interrupt Mode Selection bit
11 = Reserved
10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full (has 6 or more data characters)
01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full (has 4 or more data characters)
00 = Interrupt flag bit is asserted while receive buffer is not empty (has at least 1 data character)
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect.
0 = Address Detect mode is disabled
bit 4
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is idle
0 = Data is being received
bit 3
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character
0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character
0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit.
This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit
resets the receiver buffer and RSR to an empty state.
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed
bit 0
URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
DS60001156K-page 214
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
21.0
PARALLEL MASTER PORT
(PMP)
Note:
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 13. “Parallel Master Port (PMP)”
(DS60001128) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
The PMP is a parallel 8-bit/16-bit input/output module
specifically designed to communicate with a wide
variety of parallel devices, such as communications
peripherals, LCDs, external memory devices and
microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP module is
highly configurable. Figure 21-1 shows the PMP
module pinout and its connections to external devices.
The following are key features of the PMP module:
•
•
•
•
•
•
•
•
•
•
•
8-bit and 16-bit interface
Up to 16 programmable address lines
Up to two Chip Select lines
Programmable strobe options
- Individual read and write strobes, or
- Read/Write strobe with enable strobe
Address auto-increment/auto-decrement
Programmable address/data multiplexing
Programmable polarity on control signals
Parallel Slave Port support
- Legacy addressable
- Address support
- 4-byte deep auto-incrementing buffer
Programmable wait states
Operates during Sleep and Idle modes
Fast bit manipulation using CLR, SET and INV
registers
Note:
FIGURE 21-1:
On 64-pin devices, the PMD data
pins are not available.
PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
Address Bus
Data Bus
PIC32MX5XX/6XX/7XX
Parallel
Master Port
Control Lines
PMA
PMALL
PMA
PMALH
Flash
EEPROM
SRAM
Up to 16-bit Address
PMA
PMA
PMCS1
PMA
PMCS2
PMRD
PMRD/PMWR
PMWR
PMENB
PMD
PMD(1)
Note 1:
Microcontroller
LCD
FIFO
Buffer
16/8-bit Data (with or without multiplexed addressing)
On 64-pin devices, data pins, PMD, are not available in 16-bit Master modes.
2009-2019 Microchip Technology Inc.
DS60001156K-page 215
Control Registers
Virtual Address
(BF80_#)
Register
Name(1)
TABLE 21-1:
7000
PMCON
PARALLEL MASTER PORT REGISTER MAP
7010 PMMODE
7020 PMADDR
7030 PMDOUT
7040
PMDIN
7050
PMAEN
7060
PMSTAT
31/15
30/14
29/13
31:16
—
—
—
15:0
ON
—
SIDL
31:16
—
—
—
15:0
BUSY
31:16
—
IRQM
—
—
28/12
27/11
—
—
ADRMUX
—
—
INCM
—
—
26/10
25/9
24/8
23/7
22/6
—
—
—
—
—
PMPTTL
PTWREN
PTRDEN
—
—
—
MODE16
—
MODE
—
—
15:0 CS2EN/A15 CS1EN/A14
—
—
—
19/3
18/2
17/1
16/0
—
—
—
—
—
—
ALP
CS2P
CS1P
—
WRSP
RDSP
0000
—
—
—
—
—
—
0000
—
—
—
—
WAITB
—
20/4
WAITM
—
WAITE
—
ADDR
31:16
31:16
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
15:0
—
0000
0000
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
008F
PTEN
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
0000
0000
DATAIN
15:0
0000
0000
DATAOUT
15:0
31:16
CSF
21/5
All Resets
Bit Range
Bits
PIC32MX5XX/6XX/7XX
DS60001156K-page 216
21.1
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 21-1:
Bit
Range
31:24
23:16
15:8
7:0
PMCON: PARALLEL PORT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
U-0
R/W-0
ON(1)
—
SIDL
ADRMUX
R/W-0
R/W-0
(2)
R/W-0
(2)
U-0
CSF
ALP
—
R/W-0
R/W-0
R/W-0
PMPTTL
PTWREN
PTRDEN
U-0
R/W-0
R/W-0
—
WRSP
RDSP
R/W-0
(2)
CS1P
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Parallel Master Port Enable bit(1)
1 = PMP is enabled
0 = PMP is disabled, no off-chip access performed
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation when device enters Idle mode
bit 12-11 ADRMUX: Address/Data Multiplexing Selection bits
11 = All 16 bits of address are multiplexed on PMD pins
10 = All 16 bits of address are multiplexed on PMD pins
01 = Lower 8 bits of address are multiplexed on PMD pins, upper bits are on PMA
00 = Address and data appear on separate pins
bit 10
PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffer
bit 9
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
bit 8
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port is enabled
0 = PMRD/PMWR port is disabled
bit 7-6
CSF: Chip Select Function bits(2)
11 = Reserved
10 = PMCS2 and PMCS1 function as Chip Select
01 = PMCS2 functions as Chip Select, PMCS1 functions as address bit 14
00 = PMCS2 and PMCS1 function as address bits 15 and 14(2)
bit 5
ALP: Address Latch Polarity bit(2)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
bit 4
Unimplemented: Read as ‘0’
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
2009-2019 Microchip Technology Inc.
DS60001156K-page 217
PIC32MX5XX/6XX/7XX
REGISTER 21-1:
PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
bit 3
CS1P: Chip Select 0 Polarity bit(2)
1 = Active-high (PMCS1)
0 = Active-low (PMCS1)
bit 2
Unimplemented: Read as ‘0’
bit 1
WRSP: Write Strobe Polarity bit
For Slave Modes and Master mode 2 (PMMODE = 00,01,10):
1 = Write strobe active-high (PMWR)
0 = Write strobe active-low (PMWR)
For Master mode 1 (PMMODE = 11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB)
bit 0
RDSP: Read Strobe Polarity bit
For Slave modes and Master mode 2 (PMMODE = 00,01,10):
1 = Read Strobe active-high (PMRD)
0 = Read Strobe active-low (PMRD)
For Master mode 1 (PMMODE = 11):
1 = Read/write strobe active-high (PMRD/PMWR)
0 = Read/write strobe active-low (PMRD/PMWR)
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
DS60001156K-page 218
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 21-2:
Bit
Range
31:24
23:16
15:8
PMMODE: PARALLEL PORT MODE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUSY
R/W-0
7:0
IRQM
R/W-0
(1)
R/W-0
WAITB
INCM
R/W-0
MODE16
R/W-0
(1)
MODE
R/W-0
R/W-0
R/W-0
WAITE(1)
WAITM
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
BUSY: Busy bit (only Master mode)
1 = Port is busy
0 = Port is not busy
bit 14-13 IRQM: Interrupt Request Mode bits (4)
11 = Reserved
10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA =11 (only Addressable Slave mode)
01 = Interrupt generated at the end of the read/write cycle
00 = Interrupt is not generated
bit 12-11 INCM: Increment Mode bits
11 = Slave mode read and write buffers auto-increment (only PMMODE = 00)
10 = Decrement ADDR and ADDR by 1 every read/write cycle(2)
01 = Increment ADDR and ADDR by 1 every read/write cycle(2)
00 = No increment or decrement of address
bit 10
MODE16: 8/16-bit Mode bit
1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer
0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer
bit 9-8
MODE: Parallel Port Mode Select bits
11 = Master mode 1 PMCSx, PMRD/PMWR, PMENB, PMA, PMD and PMD(3))
10 = Master mode 2 (PMCSx, PMRD, PMWR, PMA, PMD and PMD(3))
01 = Enhanced Slave mode, control signals (PMRD, PMWR, PMCS1, PMD, and PMA)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1, and PMD)
bit 7-6
WAITB: Data Setup to Read/Write Strobe Wait States bits(1)
11 = Data wait of 4 TPB; multiplexed address phase of 4 TPB
10 = Data wait of 3 TPB; multiplexed address phase of 3 TPB
01 = Data wait of 2 TPB; multiplexed address phase of 2 TPB
00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (default)
Note 1: Whenever WAITM = 0000, the WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for
a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: Address bit A14 is not subject to auto-increment or auto-decrement if configured as Chip Select CS1.
3: These pins are active when MODE16 = 1 (16-bit mode).
4: These bits only control generating the Parallel Master Port (PMP) interrupt. The Parallel Master Port Error
(PMPE) is always generated.
2009-2019 Microchip Technology Inc.
DS60001156K-page 219
PIC32MX5XX/6XX/7XX
REGISTER 21-2:
PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED)
bit 5-2
WAITM: Data Read/Write Strobe Wait States bits(1)
1111 = Wait of 16 TPB
•
•
•
0001 = Wait of 2 TPB
0000 = Wait of 1 TPB (default)
bit 1-0
WAITE: Data Hold After Read/Write Strobe Wait States bits(1)
11 = Wait of 4 TPB
10 = Wait of 3 TPB
01 = Wait of 2 TPB
00 = Wait of 1 TPB (default)
For Read operations:
11 = Wait of 3 TPB
10 = Wait of 2 TPB
01 = Wait of 1 TPB
00 = Wait of 0 TPB (default)
Note 1: Whenever WAITM = 0000, the WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for
a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: Address bit A14 is not subject to auto-increment or auto-decrement if configured as Chip Select CS1.
3: These pins are active when MODE16 = 1 (16-bit mode).
4: These bits only control generating the Parallel Master Port (PMP) interrupt. The Parallel Master Port Error
(PMPE) is always generated.
DS60001156K-page 220
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 21-3:
Bit
Range
31:24
23:16
15:8
7:0
PMADDR: PARALLEL PORT ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
(1)
R/W-0
(3)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CS2
CS1
ADDR15(2)
ADDR14(4)
R/W-0
R/W-0
ADDR
R/W-0
R/W-0
R/W-0
R/W-0
ADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
CS2: Chip Select 2 bit(1)
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive
bit 15
ADDR: Destination Address bit 15(2)
bit 14
CS1: Chip Select 1 bit(3)
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive
bit 14
ADDR: Destination Address bit 14(4)
bit 13-0
ADDR: Address bits
Note 1:
2:
3:
4:
When the CSF bits (PMCON) = 10 or 01.
When the CSF bits (PMCON) = 00.
When the CSF bits (PMCON) = 10.
When the CSF bits (PMCON) = 00 or 01.
2009-2019 Microchip Technology Inc.
DS60001156K-page 221
PIC32MX5XX/6XX/7XX
REGISTER 21-4:
Bit
Range
31:24
23:16
15:8
7:0
PMAEN: PARALLEL PORT PIN ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
(1)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
PTEN
R/W-0
PTEN
R/W-0
R/W-0
R/W-0
PTEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-14 PTEN: PMCSx Address Port Enable bits
1 = PMA15 and PMA14 function as either PMA or PMCS2 and PMCS1(1)
0 = PMA15 and PMA14 function as port I/O
bit 13-11 Unimplemented: Read as ‘0’
bit 10-2
PTEN: PMP Address Port Enable bits
1 = PMA function as PMP address lines
0 = PMA function as port I/O
bit 1-0
PTEN: PMALH/PMALL Strobe Enable bits
1 = PMA1 and PMA0 function as either PMA or PMALH and PMALL(2)
0 = PMA1 and PMA0 pads function as port I/O
Note 1:
2:
The use of these pins as PMA15/PMA14 or CS2/CS1 is selected by the CSF bits (PMCON).
The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode
selected by bits ADRMUX in the PMCON register.
DS60001156K-page 222
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 21-5:
Bit
Range
31:24
23:16
15:8
7:0
PMSTAT: PARALLEL PORT STATUS REGISTER (ONLY SLAVE MODES)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R/W-0, HS, SC
U-0
U-0
R-0
R-0
R-0
R-0
IB0F
IBF
IBOV
—
—
IB3F
IB2F
IB1F
R-1
R/W-0, HS, SC
U-0
U-0
R-1
R-1
R-1
R-1
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
Legend:
HS = Set by Hardware
SC = Cleared by software
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
IBF: Input Buffer Full Status bit
1 = All writable input buffer registers are full
0 = Some or all of the writable input buffer registers are empty
bit 14
IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full input byte buffer occurred (must be cleared in software)(1)
0 = An overflow has not occurred
bit 13-12 Unimplemented: Read as ‘0’
bit 11-8
IBxF: Input Buffer ‘x’ Status Full bits
1 = Input buffer contains data that has not been read (reading buffer will clear this bit)
0 = Input buffer does not contain any unread data
bit 7
OBE: Output Buffer Empty Status bit
1 = All readable output buffer registers are empty
0 = Some or all of the readable output buffer registers are full
bit 6
OBUF: Output Buffer Underflow Status bit
1 = A read occurred from an empty output byte buffer (must be cleared in software)(1)
0 = An underflow has not occurred
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
OBxE: Output Buffer ‘x’ Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains data that has not been transmitted
Note 1: This will generate a PMPE – Parallel Master Port Error interrupt.
2009-2019 Microchip Technology Inc.
DS60001156K-page 223
PIC32MX5XX/6XX/7XX
NOTES:
DS60001156K-page 224
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
22.0
Note:
REAL-TIME CLOCK AND
CALENDAR (RTCC)
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 29. “Real-Time
Clock
and
Calendar
(RTCC)”
(DS60001125) in the “PIC32 Family Reference Manual”, which is available from
the Microchip web site (www.microchip.com/PIC32).
The PIC32 RTCC module is intended for applications
in which accurate time must be maintained for
extended periods of time with minimal or no CPU
intervention.
Low-power
optimization
provides
extended battery lifetime while keeping track of time.
A simplified block diagram of the RTCC module is
illustrated in Figure 22-1.
FIGURE 22-1:
Key features of the RTCC module include:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Time: hours, minutes and seconds
24-hour format (military time)
Visibility of one-half second period
Provides calendar: Weekday, date, month and year
Alarm intervals are configurable for half of a
second, one second, 10 seconds, one minute, 10
minutes, one hour, one day, one week, one month
and one year
Alarm repeat with decrementing counter
Alarm with indefinite repeat: Chime
Year range: 2000 to 2099
Leap year correction
BCD format for smaller firmware overhead
Optimized for long-term battery operation
Fractional second synchronization
User calibration of the clock crystal frequency with
auto-adjust
Calibration range: 0.66 seconds error per month
Calibrates up to 260 ppm of crystal error
Requirements: External 32.768 kHz clock crystal
Alarm pulse or seconds clock output on RTCC pin
RTCC BLOCK DIAGRAM
32.768 kHz Input
from Secondary
Oscillator (SOSC)
RTCC Prescalers
0.5s
YEAR, MTH, DAY
RTCC Timer
Alarm
Event
RTCVAL
WKDAY
HR, MIN, SEC
Comparator
MTH, DAY
Compare Registers
with Masks
ALRMVAL
WKDAY
HR, MIN, SEC
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
Seconds Pulse
RTCC Pin
RTCOE
2009-2019 Microchip Technology Inc.
DS60001156K-page 225
Control Registers
Virtual Address
(BF80_#)
Register
Name(1)
TABLE 22-1:
0200
RTCCON
RTCTIME
0230 RTCDATE
0240 ALRMTIME
0250 ALRMDATE
Legend:
Note
1:
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
15:0
ON
—
—
—
—
—
—
SIDL
—
—
—
31:16
—
—
—
—
15:0
ALRMEN
CHIME
PIV
ALRMSYNC
31:16
25/9
24/8
—
—
—
—
—
—
SEC10
SEC01
YEAR10
YEAR01
15:0
DAY10
DAY01
31:16
HR10
HR01
15:0
SEC10
—
—
DAY10
RTSECSEL RTCCLKON
—
—
—
19/3
18/2
17/1
16/0
—
—
DAY01
0000
—
—
—
—
RTCWREN RTCSYNC HALFSEC
—
MIN10
—
—
—
RTCOE
0000
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
MONTH10
—
—
—
—
—
xxxx
—
MONTH01
MIN10
—
0000
MIN01
MONTH10
SEC01
—
20/4
ARPT
HR01
15:0
—
21/5
AMASK
HR10
15:0
22/6
CAL
31:16
31:16
23/7
All Resets
Bit Range
Bits
0210 RTCALRM
0220
RTCC REGISTER MAP
—
—
xx00
xxxx
WDAY01
xx00
MIN01
xxxx
—
—
—
xx00
MONTH01
00xx
WDAY01
xx0x
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
PIC32MX5XX/6XX/7XX
DS60001156K-page 226
22.1
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 22-1:
Bit
Range
31:24
23:16
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
29/21/13/5 28/20/12/4
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
CAL
CAL
15:8
7:0
RTCCON: RTC CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
ON(1,2)
—
SIDL
—
—
—
—
—
R/W-0
R-0
U-0
U-0
R/W-0
R-0
R-0
R/W-0
—
—
RTSECSEL(3) RTCCLKON
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
RTCWREN(4) RTCSYNC HALFSEC(5)
RTCOE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25-16 CAL: RTC Drift Calibration bits, which contain a signed 10-bit integer value
1111111111 = Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute
•
•
•
1000000000 = Maximum negative adjustment, subtracts 512 clock pulses every one minute
0111111111 = Maximum positive adjustment, adds 511 RTC clock pulses every one minute
•
•
•
bit 15
bit 14
bit 13
bit 12-8
bit 7
bit 6
bit 5-4
Note 1:
2:
3:
4:
5:
Note:
0000000001 = Minimum positive adjustment, adds 1 RTC clock pulse every one minute
0000000000 = No adjustment
ON: RTCC On bit(1,2)
1 = RTCC module is enabled
0 = RTCC module is disabled
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1 = Disables the PBCLK to the RTCC when CPU enters in Idle mode
0 = Continue normal operation in Idle mode
Unimplemented: Read as ‘0’
RTSECSEL: RTCC Seconds Clock Output Select bit(3)
1 = RTCC Seconds Clock is selected for the RTCC pin
0 = RTCC Alarm Pulse is selected for the RTCC pin
RTCCLKON: RTCC Clock Enable Status bit
1 = RTCC Clock is actively running
0 = RTCC Clock is not running
Unimplemented: Read as ‘0’
The ON bit is only writable when RTCWREN = 1.
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Requires RTCOE = 1 (RTCCON) for the output to be active.
The RTCWREN bit can only be set when the write sequence is enabled.
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME).
This register is only reset on a Power-on Reset (POR).
2009-2019 Microchip Technology Inc.
DS60001156K-page 227
PIC32MX5XX/6XX/7XX
REGISTER 22-1:
RTCCON: RTC CONTROL REGISTER (CONTINUED)
RTCWREN: RTC Value Registers Write Enable bit(4)
1 = RTC Value registers can be written to by the user
0 = RTC Value registers are locked out from being written to by the user
RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data
read. If the register is read twice and results in the same data, the data can be assumed to be valid.
0 = RTC Value registers can be read without concern about a rollover ripple
HALFSEC: Half-Second Status bit(5)
1 = Second half period of a second
0 = First half period of a second
RTCOE: RTCC Output Enable bit
1 = RTCC clock output is enabled (clock presented onto an I/O)
0 = RTCC clock output is disabled
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
3:
4:
5:
Note:
The ON bit is only writable when RTCWREN = 1.
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Requires RTCOE = 1 (RTCCON) for the output to be active.
The RTCWREN bit can only be set when the write sequence is enabled.
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME).
This register is only reset on a Power-on Reset (POR).
DS60001156K-page 228
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 22-2:
Bit
Range
31:24
23:16
15:8
RTCALRM: RTC ALARM CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
Bit
27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R-0
R/W-0
R/W-0
CHIME(2)
R/W-0
(2)
R/W-0
ALRMEN(1,2)
R/W-0
(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7:0
PIV
ALRMSYNC(3)
R/W-0
AMASK
R/W-0
ARPT(2)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ALRMEN: Alarm Enable bit(1,2)
1 = Alarm is enabled
0 = Alarm is disabled
bit 14
CHIME: Chime Enable bit(2)
1 = Chime is enabled – ARPT is allowed to rollover from 0x00 to 0xFF
0 = Chime is disabled – ARPT stops once it reaches 0x00
bit 13
PIV: Alarm Pulse Initial Value bit(3)
When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse.
When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.
bit 12
ALRMSYNC: Alarm Sync bit(3)
1 = ARPT and ALRMEN may change as a result of a half second rollover during a read.
The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple
bits may be changing, which are then synchronized to the PB clock domain.
0 = ARPT and ALRMEN can be read without concerns of rollover because the prescaler is > 32 RTC
clocks away from a half-second rollover
bit 11-8 AMASK: Alarm Mask Configuration bits(2)
1111 = Reserved
•
•
•
1010 =
1001 =
1000 =
0111 =
0110 =
0101 =
0100 =
0011 =
0010 =
0001 =
0000 =
Note 1:
2:
3:
Note:
Reserved
Once a year (except when configured for February 29, once every four years)
Once a month
Once a week
Once a day
Every hour
Every 10 minutes
Every minute
Every 10 seconds
Every second
Every half-second
Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT = 00 and
CHIME = 0.
This field should not be written when the RTCC ON bit = ‘1’ (RTCCON) and ALRMSYNC = 1.
This assumes a CPU read will execute in less than 32 PBCLKs.
This register is only reset on a Power-on Reset (POR).
2009-2019 Microchip Technology Inc.
DS60001156K-page 229
PIC32MX5XX/6XX/7XX
REGISTER 22-2:
RTCALRM: RTC ALARM CONTROL REGISTER (CONTINUED)
ARPT: Alarm Repeat Counter Value bits(2)
11111111 = Alarm will trigger 256 times
bit 7-0
•
•
•
00000000 = Alarm will trigger one time
The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.
Note 1:
2:
3:
Note:
Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT = 00 and
CHIME = 0.
This field should not be written when the RTCC ON bit = ‘1’ (RTCCON) and ALRMSYNC = 1.
This assumes a CPU read will execute in less than 32 PBCLKs.
This register is only reset on a Power-on Reset (POR).
DS60001156K-page 230
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 22-3:
Bit
Range
31:24
23:16
15:8
7:0
RTCTIME: RTC TIME VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
HR10
HR01
R/W-x
MIN10
R/W-x
R/W-x
U-0
U-0
—
—
R/W-x
R/W-x
R/W-x
MIN01
R/W-x
R/W-x
R/W-x
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
SEC10
R/W-x
R/W-x
SEC01
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 HR10: Binary-Coded Decimal Value of Hours bits, 10 digits; contains a value from 0 to 2
bit 27-24 HR01: Binary-Coded Decimal Value of Hours bits, 1 digit; contains a value from 0 to 9
bit 23-20 MIN10: Binary-Coded Decimal Value of Minutes bits, 10 digits; contains a value from 0 to 5
bit 19-16 MIN01: Binary-Coded Decimal Value of Minutes bits, 1 digit; contains a value from 0 to 9
bit 15-12 SEC10: Binary-Coded Decimal Value of Seconds bits, 10 digits; contains a value from 0 to 5
bit 11-8
SEC01: Binary-Coded Decimal Value of Seconds bits, 1 digit; contains a value from 0 to 9
bit 7-0
Unimplemented: Read as ‘0’
Note:
This register is only writable when RTCWREN = 1 (RTCCON).
2009-2019 Microchip Technology Inc.
DS60001156K-page 231
PIC32MX5XX/6XX/7XX
REGISTER 22-4:
Bit
Range
31:24
23:16
15:8
7:0
RTCDATE: RTC DATE VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
YEAR10
R/W-x
YEAR01
MONTH10
R/W-x
R/W-x
U-0
U-0
—
—
R/W-x
R/W-x
R/W-x
MONTH01
R/W-x
R/W-x
R/W-x
U-0
U-0
R/W-x
R/W-x
—
—
DAY10
R/W-x
R/W-x
DAY01
R/W-x
R/W-x
WDAY01
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 YEAR10: Binary-Coded Decimal Value of Years bits, 10 digits
bit 27-24 YEAR01: Binary-Coded Decimal Value of Years bits, 1 digit
bit 23-20 MONTH10: Binary-Coded Decimal Value of Months bits, 10 digits; contains a value from 0 to 1
bit 19-16 MONTH01: Binary-Coded Decimal Value of Months bits, 1 digit; contains a value from 0 to 9
bit 15-12 DAY10: Binary-Coded Decimal Value of Days bits, 10 digits; contains a value from 0 to 3
bit 11-8
DAY01: Binary-Coded Decimal Value of Days bits, 1 digit; contains a value from 0 to 9
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
WDAY01: Binary-Coded Decimal Value of Weekdays bits,1 digit; contains a value from 0 to 6
Note:
This register is only writable when RTCWREN = 1 (RTCCON).
DS60001156K-page 232
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 22-5:
Bit
Range
31:24
23:16
15:8
7:0
ALRMTIME: ALARM TIME VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
HR10
HR01
R/W-x
MIN10
R/W-x
R/W-x
U-0
U-0
—
—
R/W-x
R/W-x
R/W-x
MIN01
R/W-x
R/W-x
R/W-x
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
SEC10
R/W-x
R/W-x
SEC01
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 HR10: Binary Coded Decimal value of hours bits, 10 digits; contains a value from 0 to 2
bit 27-24 HR01: Binary Coded Decimal value of hours bits, 1 digit; contains a value from 0 to 9
bit 23-20 MIN10: Binary Coded Decimal value of minutes bits, 10 digits; contains a value from 0 to 5
bit 19-16 MIN01: Binary Coded Decimal value of minutes bits, 1 digit; contains a value from 0 to 9
bit 15-12 SEC10: Binary Coded Decimal value of seconds bits, 10 digits; contains a value from 0 to 5
bit 11-8
SEC01: Binary Coded Decimal value of seconds bits, 1 digit; contains a value from 0 to 9
bit 7-0
Unimplemented: Read as ‘0’
2009-2019 Microchip Technology Inc.
DS60001156K-page 233
PIC32MX5XX/6XX/7XX
REGISTER 22-6:
Bit
Range
31:24
23:16
15:8
7:0
ALRMDATE: ALARM DATE VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
U-0
U-0
Bit
Bit
27/19/11/3 26/18/10/2
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
U-0
U-0
U-0
U-0
R/W-x
R/W-x
—
—
—
—
MONTH10
R/W-x
MONTH01
DAY10
R/W-x
R/W-x
DAY01
R/W-x
R/W-x
WDAY01
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-20 MONTH10: Binary Coded Decimal value of months bits, 10 digits; contains a value from 0 to 1
bit 19-16 MONTH01: Binary Coded Decimal value of months bits, 1 digit; contains a value from 0 to 9
bit 15-12 DAY10: Binary Coded Decimal value of days bits, 10 digits; contains a value from 0 to 3
bit 11-8
DAY01: Binary Coded Decimal value of days bits, 1 digit; contains a value from 0 to 9
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
WDAY01: Binary Coded Decimal value of weekdays bits, 1 digit; contains a value from 0 to 6
DS60001156K-page 234
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
23.0
10-BIT ANALOG-TO-DIGITAL
CONVERTER (ADC)
Note:
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 17. “10-bit Analog-to-Digital
Converter
(ADC)”
(DS60001104) in the “PIC32 Family Reference Manual”, which is available from
the
Microchip
web
site
(www.microchip.com/PIC32).
The PIC32MX5XX/6XX/7XX 10-bit Analog-to-Digital
Converter (ADC) includes the following features:
• Successive Approximation Register (SAR)
conversion
• Up to 1 Msps conversion speed
• Up to 16 analog input pins
• External voltage reference input pins
• One unipolar, differential Sample and Hold (S&H)
circuit
• Automatic Channel Scan mode
• Selectable conversion trigger source
FIGURE 23-1:
•
•
•
•
16-word conversion result buffer
Selectable buffer fill modes
Eight conversion result format options
Operation during Sleep and Idle modes
A block diagram of the 10-bit ADC is illustrated in
Figure 23-1. The 10-bit ADC has up to 16 analog input
pins, designated AN0-AN15. In addition, there are two
analog input pins for external voltage reference
connections. These voltage reference inputs may be
shared with other analog input pins and may be
common to other analog module references.
The analog inputs are connected through two multiplexers to one S&H. The analog input multiplexers can
be switched between two sets of analog inputs
between conversions. Unipolar differential conversions
are possible on all channels, other than the pin used as
the reference, using a reference input pin (see
Figure 23-1).
The Analog Input Scan mode sequentially converts
user-specified channels. A control register specifies
which analog input channels will be included in the
scanning sequence.
The 10-bit ADC is connected to a 16-word result buffer.
Each 10-bit result is converted to one of eight 32-bit
output formats when it is read from the result buffer.
ADC1 MODULE BLOCK DIAGRAM
VREF+(1)
AVDD
VREF-(1)
AVSS
VCFG
AN0
ADC1BUF0
ADC1BUF1
AN15
S&H
Channel
Scan
VREFH
VREFL
ADC1BUF2
+
CH0SB
CH0SA
-
SAR ADC
CSCNA
AN1
ADC1BUFE
VREFL
ADC1BUFF
CH0NA CH0NB
Alternate
Input Selection
Note
1:
VREF+ and VREF- inputs can be multiplexed with other analog inputs.
2009-2019 Microchip Technology Inc.
DS60001156K-page 235
PIC32MX5XX/6XX/7XX
FIGURE 23-2:
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
ADRC
FRC
2
1
TAD
ADCS
0
8
TPB
ADC Conversion
Clock Multiplier
2, 4,..., 512
DS60001156K-page 236
2009-2019 Microchip Technology Inc.
Control Registers
TABLE 23-1:
Virtual Address
(BF80_#)
ADC REGISTER MAP
9000 AD1CON1(1)
9010 AD1CON2(1)
9020 AD1CON3(1)
9040 AD1CHS
(1)
9060 AD1PCFG(1)
9050 AD1CSSL(1)
9070 ADC1BUF0
9090 ADC1BUF2
90A0 ADC1BUF3
90B0 ADC1BUF4
90C0 ADC1BUF5
90D0 ADC1BUF6
90E0 ADC1BUF7
DS60001156K-page 237
90F0 ADC1BUF8
9100 ADC1BUF9
9110 ADC1BUFA
30/14
29/13
28/12
27/11
26/10
31:16
—
15:0
ON
31:16
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
15:0
VCFG2
VCFG1
VCFG0
OFFCAL
—
CSCNA
—
—
BUFS
—
31:16
—
—
—
—
—
—
—
—
—
15:0
ADRC
—
—
31:16
CH0NB
—
—
—
25/9
24/8
23/7
—
—
—
22/6
21/5
—
—
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
CLRASAM
—
ASAM
SAMP
DONE
0000
—
—
—
—
—
—
0000
BUFM
ALTS
0000
—
—
—
—
—
0000
CH0NA
—
—
—
FORM
SSRC
SMPI
SAMC
—
—
ADCS
CH0SB
0000
CH0SA
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
PCFG15
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CSSL15
CSSL14
CSSL13
CSSL12
CSSL11
CSSL10
CSSL9
CSSL8
CSSL7
CSSL6
CSSL5
CSSL4
CSSL3
CSSL2
CSSL1
CSSL0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
ADC Result Word 0 (ADC1BUF0)
ADC Result Word 1 (ADC1BUF1)
ADC Result Word 2 (ADC1BUF2)
ADC Result Word 3 (ADC1BUF3)
ADC Result Word 4 (ADC1BUF4)
ADC Result Word 5 (ADC1BUF5)
ADC Result Word 6 (ADC1BUF6)
ADC Result Word 7 (ADC1BUF7)
ADC Result Word 8 (ADC1BUF8)
ADC Result Word 9 (ADC1BUF9)
ADC Result Word A (ADC1BUFA)
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
1:
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MX5XX/6XX/7XX
9080 ADC1BUF1
31/15
All Resets
Bit Range
Bits
Register
Name
2009-2019 Microchip Technology Inc.
23.1
Virtual Address
(BF80_#)
ADC REGISTER MAP (CONTINUED)
9120 ADC1BUFB
9130 ADC1BUFC
9140 ADC1BUFD
9150 ADC1BUFE
9160 ADC1BUFF
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
ADC Result Word B (ADC1BUFB)
ADC Result Word C (ADC1BUFC)
ADC Result Word D (ADC1BUFD)
ADC Result Word E (ADC1BUFE)
ADC Result Word F (ADC1BUFF)
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
1:
All Resets
Bit Range
Register
Name
Bits
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MX5XX/6XX/7XX
DS60001156K-page 238
TABLE 23-1:
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 23-1:
Bit
Range
31:24
23:16
15:8
7:0
AD1CON1: ADC CONTROL REGISTER 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
ON(1)
—
SIDL
—
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
CLRASAM
—
ASAM
SSRC
FORM
R/W-0, HSC
(2)
SAMP
R/C-0, HSC
(3)
DONE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: ADC Operating Mode bit(1)
1 = ADC module is operating
0 = ADC module is not operating
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-11 Unimplemented: Read as ‘0’
bit 10-8
FORM: Data Output Format bits
111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000)
110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000)
101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd)
100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)
011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000)
010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000)
001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd)
000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)
bit 7-5
SSRC: Conversion Trigger Source Select bits
111 = Internal counter ends sampling and starts conversion (auto convert)
110 = Reserved
101 = Reserved
100 = Reserved
011 = CTMU ends sampling and starts conversion
010 = Timer 3 period match ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing the SAMP bit ends sampling and starts conversion
Note 1:
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if
ASAM = 1. If SSRC = 000, software can write a ‘0’ to end sampling and start conversion. If
SSRC ‘000’, this bit is automatically cleared by hardware to end sampling and start conversion.
This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can
write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation
already in progress. This bit is automatically cleared by hardware at the start of a new conversion.
2:
3:
2009-2019 Microchip Technology Inc.
DS60001156K-page 239
PIC32MX5XX/6XX/7XX
REGISTER 23-1:
AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED)
bit 4
CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated)
1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the
ADC interrupt is generated.
0 = Normal operation, buffer contents will be overwritten by the next conversion sequence
bit 3
Unimplemented: Read as ‘0’
bit 2
ASAM: ADC Sample Auto-Start bit
1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set
0 = Sampling begins when SAMP bit is set
bit 1
SAMP: ADC Sample Enable bit(2)
1 = The ADC S&H circuit is sampling
0 = The ADC S&H circuit is holding
When ASAM = 0, writing ‘1’ to this bit starts sampling.
When SSRC = 000, writing ‘0’ to this bit will end sampling and start conversion.
bit 0
DONE: Analog-to-Digital Conversion Status bit(3)
Clearing this bit will not affect any operation in progress.
1 = Analog-to-digital conversion is done
0 = Analog-to-digital conversion is not done or has not started
Note 1:
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if
ASAM = 1. If SSRC = 000, software can write a ‘0’ to end sampling and start conversion. If
SSRC ‘000’, this bit is automatically cleared by hardware to end sampling and start conversion.
This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can
write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation
already in progress. This bit is automatically cleared by hardware at the start of a new conversion.
2:
3:
DS60001156K-page 240
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 23-2:
Bit
Range
31:24
23:16
15:8
AD1CON2: ADC CONTROL REGISTER 2
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
OFFCAL
—
CSCNA
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUFM
ALTS
VCFG
7:0
Bit
Bit
28/20/12/4 27/19/11/3
R-0
U-0
BUFS
—
R/W-0
SMPI
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-13 VCFG: Voltage Reference Configuration bits
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5-2
Bit Value
VREFH
VREFL
1xx
011
010
001
AVDD
External VREF+ pin
AVDD
External VREF+ pin
AVss
External VREF- pin
External VREF- pin
AVSS
000
AVDD
AVss
OFFCAL: Input Offset Calibration Mode Select bit
1 = Enable Offset Calibration mode
Positive and negative inputs of the S&H circuit are connected to VREFL.
0 = Disable Offset Calibration mode
The inputs to the S&H circuit are controlled by AD1CHS or AD1CSSL.
Unimplemented: Read as ‘0’
CSCNA: Input Scan Select bit
1 = Scan inputs
0 = Do not scan inputs
Unimplemented: Read as ‘0’
BUFS: Buffer Fill Status bit
Only valid when BUFM = 1.
1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7
0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF
Unimplemented: Read as ‘0’
SMPI: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
•
•
•
bit 1
bit 0
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
BUFM: ADC Result Buffer Mode Select bit
1 = Buffer configured as two 8-word buffers, ADC1BUF7-ADC1BUF0, ADC1BUFF-ADCBUF8
0 = Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0
ALTS: Alternate Input Sample Mode Select bit
1 = Uses Sample A input multiplexer settings for first sample, and then alternates between Sample B and
Sample A input multiplexer settings for all subsequent samples
0 = Always use Sample A input multiplexer settings
2009-2019 Microchip Technology Inc.
DS60001156K-page 241
PIC32MX5XX/6XX/7XX
REGISTER 23-3:
Bit
Range
31:24
23:16
15:8
7:0
AD1CON3: ADC CONTROL REGISTER 3
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADRC
—
—
R/W-0
R/W-0
R/W-0
R/W
R/W-0
SAMC(1)
R/W-0
R/W-0
R/W-0
ADCS(2)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ADRC: ADC Conversion Clock Source bit
1 = Clock derived from FRC
0 = Clock derived from Peripheral Bus Clock (PBCLK)
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8
SAMC: Auto-Sample Time bits(1)
11111 = 31 TAD
•
•
•
00001 = 1 TAD
00000 = 0 TAD (Not allowed)
bit 7-0
ADCS: ADC Conversion Clock Select bits(2)
11111111 =TPB • 2 • (ADCS + 1) = 512 • TPB = TAD
•
•
•
00000001 =TPB • 2 • (ADCS + 1) = 4 • TPB = TAD
00000000 =TPB • 2 • (ADCS + 1) = 2 • TPB = TAD
Note 1:
2:
This bit is only used if the SSRC bits (AD1CON1) = 111.
This bit is not used if the ADRC bit (AD1CON3) = 1.
DS60001156K-page 242
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 23-4:
Bit
Range
31:24
23:16
15:8
7:0
AD1CHS: ADC INPUT SELECT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0NB
—
—
—
R/W-0
U-0
U-0
U-0
CH0SB
CH0NA
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
CH0SA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
CH0NB: Negative Input Select bit for Sample B
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VREFL
bit 30-28
Unimplemented: Read as ‘0’
bit 27-24
CH0SB: Positive Input Select bits for Sample B
1111 = Channel 0 positive input is AN15
•
•
•
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
bit 23
CH0NA: Negative Input Select bit for Sample A Multiplexer Setting
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VREFL
bit 22-20
Unimplemented: Read as ‘0’
bit 19-16
CH0SA: Positive Input Select bits for Sample A Multiplexer Setting
1111 = Channel 0 positive input is AN15
•
•
•
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
bit 15-0
Unimplemented: Read as ‘0’
2009-2019 Microchip Technology Inc.
x = Bit is unknown
DS60001156K-page 243
PIC32MX5XX/6XX/7XX
REGISTER 23-5:
Bit
Range
31:24
23:16
15:8
7:0
AD1CSSL: ADC INPUT SCAN SELECT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSSL15
CSSL14
CSSL13
CSSL12
CSSL11
CSSL10
CSSL9
CSSL8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSSL7
CSSL6
CSSL5
CSSL4
CSSL3
CSSL2
CSSL1
CSSL0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CSSL: ADC Input Pin Scan Selection bits(1)
1 = Select ANx for input scan
0 = Skip ANx for input scan
Note 1:
CSSL = ANx, where ‘x’ = 0-15.
DS60001156K-page 244
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
24.0
Note:
CONTROLLER AREA
NETWORK (CAN)
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 34. “Controller
Area Network (CAN)” (DS60001154) in
the “PIC32 Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
The Controller Area Network (CAN) module supports
the following key features:
• Standards Compliance:
- Full CAN 2.0B compliance
- Programmable bit rate up to 1 Mbps
• Message Reception and Transmission:
- 32 message FIFOs
- Each FIFO can have up to 32 messages for a
total of 1024 messages
FIGURE 24-1:
- FIFO can be a transmit message FIFO or a
receive message FIFO
- User-defined priority levels for message
FIFOs used for transmission
- 32 acceptance filters for message filtering
- Four acceptance filter mask registers for
message filtering
- Automatic response to remote transmit request
- DeviceNet™ addressing support
• Additional Features:
- Loopback, Listen All Messages, and Listen
Only modes for self-test, system diagnostics
and bus monitoring
- Low-power operating modes
- CAN module is a bus master on the PIC32
system bus
- Use of DMA is not required
- Dedicated time-stamp timer
- Dedicated DMA channels
- Data-only Message Reception mode
Figure 24-1 illustrates the general structure of the CAN
module.
PIC32 CAN MODULE BLOCK DIAGRAM
CxTX
32 Filters
4 Masks
CPU
CxRX
CAN Module
Up to 32 Message Buffers
System Bus
Message
Buffer Size
2 or 4 Words
System RAM
Message Buffer 31
Message Buffer 31
Message Buffer 31
Message Buffer 1
Message Buffer 0
Message Buffer 1
Message Buffer 0
Message Buffer 1
Message Buffer 0
FIFO1
FIFO31
FIFO0
CAN Message FIFO (up to 32 FIFOs)
2009-2019 Microchip Technology Inc.
DS60001156K-page 245
Control Registers
Virtual Address
(BF88_#)
Register
Name(1)
TABLE 24-1:
B000
C1CON
C1CFG
B020
C1INT
B030
B050
B060
C1VEC
C1TREC
C1FSTAT
C1RXOVF
B070
B080
C1TMR
C1RXM0
2009-2019 Microchip Technology Inc.
B090
C1RXM1
B0A0
C1RXM2
B0B0
C1RXM3
B0C0 C1FLTCON0
B0D0 C1FLTCON1
B0E0 C1FLTCON2
Legend:
Note
1:
31/15
30/14
31:16
—
15:0
ON
31:16
—
15:0 SEG2PHTS
29/13
28/12
—
—
—
ABAT
—
SIDLE
—
CANBUSY
—
—
—
—
—
—
SAM
27/11
26/10
25/9
24/8
23/7
—
—
—
—
—
—
—
—
WAKFIL
—
—
—
REQOP
SEG1PH
22/6
21/5
OPMOD
PRSEG
20/4
19/3
CANCAP
—
18/2
17/1
16/0
—
—
—
DNCNT
SJW
All Resets
Bit Range
Bits
B010
B040
CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L,
PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES
0480
0000
SEG2PH
0000
BRP
0000
31:16
IVRIE
WAKIE
CERRIE
SERRIE
RBOVIE
—
—
—
—
—
—
—
MODIE
CTMRIE
RBIE
TBIE
0000
15:0
IVRIF
WAKIF
CERRIF
SERRIF
RBOVIF
—
—
—
—
—
—
—
MODIF
CTMRIF
RBIF
TBIF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
TXBO
TXBP
TXWARN
RXWARN
FIFOIP24
FIFOIP23
FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18
FIFOIP17 FIFOIP16 0000
FIFOIP7
FIFOIP6
FIFOIP1
15:0
FILHIT
—
ICODE
TERRCNT
0040
EWARN 0000
RERRCNT
31:16 FIFOIP31
FIFOIP30
FIFOIP29 FIFOIP28 FIFOIP27
FIFOIP26
FIFOIP25
15:0
FIFOIP14
FIFOIP13 FIFOIP12 FIFOIP11
FIFOIP10
FIFOIP9
FIFOIP15
RXBP
FIFOIP8
FIFOIP5
FIFOIP4
0000
FIFOIP3
FIFOIP2
FIFOIP0 0000
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25
RXOVF24
RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10
RXOVF8
RXOVF7
31:16
RXOVF9
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0 0000
CANTS
15:0
0000
CANTSPRE
31:16
0000
SID
15:0
-—
MIDE
—
EID
-—
MIDE
—
EID
xxxx
xxxx
-—
MIDE
—
EID
xxxx
xxxx
-—
MIDE
—
EID
xxxx
EID
31:16
xxxx
SID
15:0
EID
31:16
SID
15:0
EID
31:16
SID
15:0
EID
31:16
FLTEN3
MSEL3
FSEL3
FLTEN2
xxxx
xxxx
MSEL2
FSEL2
0000
15:0
FLTEN1
MSEL1
FSEL1
FLTEN0
MSEL0
FSEL0
0000
31:16
FLTEN7
MSEL7
FSEL7
FLTEN6
MSEL6
FSEL6
0000
15:0
FLTEN5
MSEL5
FSEL5
FLTEN4
MSEL4
FSEL4
0000
31:16 FLTEN11
MSEL11
FSEL11
FLTEN10
MSEL10
FSEL10
0000
15:0
MSEL9
FSEL9
FLTEN8
MSEL8
FSEL8
0000
FLTEN9
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
PIC32MX5XX/6XX/7XX
DS60001156K-page 246
24.1
Virtual Address
(BF88_#)
B0F0 C1FLTCON3
B100 C1FLTCON4
B110 C1FLTCON5
B120 C1FLTCON6
B130 C1FLTCON7
B140
C1RXFn
(n = 0-31)
C1FIFOBA
C1FIFOINTn
(n = 0-31)
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
29/13
MSEL15
FSEL15
FLTEN14
MSEL14
FSEL14
0000
15:0
FLTEN13
MSEL13
FSEL13
FLTEN12
MSEL12
FSEL12
0000
31:16 FLTEN19
MSEL19
FSEL19
FLTEN18
MSEL18
FSEL18
0000
15:0
FLTEN17
MSEL17
FSEL17
FLTEN16
MSEL16
FSEL16
0000
31:16 FLTEN23
MSEL23
FSEL23
FLTEN22
MSEL22
FSEL22
0000
FLTEN21
MSEL21
FSEL21
FLTEN20
MSEL20
FSEL20
0000
31:16 FLTEN27
15:0
MSEL27
FSEL27
FLTEN26
MSEL26
FSEL26
0000
15:0
FLTEN25
MSEL25
FSEL25
FLTEN24
MSEL24
FSEL24
0000
31:16 FLTEN31
MSEL31
FSEL31
FLTEN30
MSEL30
FSEL30
0000
15:0
MSEL29
FSEL29
FLTEN28
MSEL28
FSEL28
FLTEN29
31:16
SID
-—
15:0
EXID
—
0000
EID
EID
31:16
xxxx
xxxx
0000
C1FIFOBA
15:0
0000
—
—
—
—
—
—
—
—
—
—
—
—
FRESET
UINC
DONLY
—
—
—
—
TXEN
TXABAT
TXLARB
FSIZE
TXERR
TXREQ
RTREN
0000
TXPRI
0000
31:16
—
—
—
—
—
TXNFULLIE TXHALFIE TXEMPTYIE
—
—
—
—
RXN
0000
RXOVFLIE RXFULLIE RXHALFIE
EMPTYIE
15:0
—
—
—
—
—
TXNFULLIF TXHALFIF TXEMPTYIF
—
—
—
—
RXOVFLIF RXFULLIF RXHALFIF
B370
C1FIFOUAn 31:16
(n = 0-31)
15:0
B380
C1FIFOCIn 31:16
(n = 0-31)
15:0
Legend:
Note
1:
30/14
31:16 FLTEN15
C1FIFOCONn 31:16
B350
(n = 0-31)
15:0
B360
31/15
RXN
0000
EMPTYIF
0000
C1FIFOUA
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C1FIFOCI
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
0000
0000
DS60001156K-page 247
PIC32MX5XX/6XX/7XX
B340
CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L,
PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED)
Bits
Register
Name(1)
2009-2019 Microchip Technology Inc.
TABLE 24-1:
Virtual Address
(BF88_#)
Register
Name(1)
C000
C2CON
C010
C2CFG
C040
C050
C060
C070
C2INT
C2VEC
C2TREC
C2FSTAT
C2RXOVF
C2TMR
C080
C2RXM0
C0A0
C2RXM1
C0B0
2009-2019 Microchip Technology Inc.
C0B0
C2RXM2
C2RXM3
C0C0 C2FLTCON0
C0D0 C2FLTCON1
C0E0 C2FLTCON2
C0F0 C2FLTCON3
Legend:
Note
1:
31/15
30/14
31:16
—
15:0
ON
31:16
—
15:0 SEG2PHTS
29/13
28/12
—
—
—
ABAT
—
SIDLE
—
CANBUSY
—
—
—
—
—
—
SAM
27/11
26/10
25/9
24/8
23/7
—
—
—
—
—
—
—
—
WAKFIL
—
—
—
REQOP
SEG1PH
22/6
21/5
OPMOD
PRSEG
20/4
19/3
CANCAP
—
18/2
17/1
16/0
—
—
—
DNCNT
SJW
All Resets
Bit Range
Bits
C020
C030
CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES
0480
0000
SEG2PH
0000
BRP
0000
31:16
IVRIE
WAKIE
CERRIE
SERRIE
RBOVIE
—
—
—
—
—
—
—
MODIE
CTMRIE
RBIE
TBIE
0000
15:0
IVRIF
WAKIF
CERRIF
SERRIF
RBOVIF
—
—
—
—
—
—
—
MODIF
CTMRIF
RBIF
TBIF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
TXBO
TXBP
TXWARN
RXWARN
EWARN
0000
FIFOIP24
FIFOIP23
FIFOIP22
FIFOIP21
FIFOIP20
FIFOIP19
FIFOIP18
FIFOIP17 FIFOIP16 0000
FIFOIP7
FIFOIP6
FIFOIP5
FIFOIP4
FIFOIP3
FIFOIP2
FIFOIP1
15:0
FILHIT
—
ICODE
TERRCNT
0040
RERRCNT
31:16 FIFOIP31
FIFOIP30 FIFOIP29 FIFOIP28
FIFOIP27
FIFOIP26
FIFOIP25
15:0
FIFOIP14 FIFOIP13 FIFOIP12
FIFOIP11
FIFOIP10
FIFOIP9
FIFOIP15
RXBP
FIFOIP8
0000
FIFOIP0
0000
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25
RXOVF24
RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10
RXOVF8
RXOVF7
31:16
RXOVF9
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0
CANTS
15:0
0000
CANTSPRE
31:16
0000
SID
15:0
-—
MIDE
—
EID
xxxx
-—
MIDE
—
EID
xxxx
-—
MIDE
—
EID
xxxx
-—
MIDE
—
EID
xxxx
EID
31:16
xxxx
SID
15:0
EID
31:16
xxxx
SID
15:0
EID
31:16
xxxx
SID
15:0
0000
EID
xxxx
31:16
FLTEN3
MSEL3
FSEL3
FLTEN2
MSEL2
FSEL2
0000
15:0
FLTEN1
MSEL1
FSEL1
FLTEN0
MSEL0
FSEL0
0000
31:16
FLTEN7
MSEL7
FSEL7
FLTEN6
MSEL6
FSEL6
0000
15:0
FLTEN5
MSEL5
FSEL5
FLTEN4
MSEL4
FSEL4
0000
31:16 FLTEN11
MSEL11
FSEL11
FLTEN10
MSEL10
FSEL10
0000
15:0
FLTEN9
MSEL9
FSEL9
FLTEN8
MSEL8
FSEL8
0000
31:16 FLTEN15
MSEL15
FSEL15
FLTEN14
MSEL14
FSEL14
0000
15:0
MSEL13
FSEL13
FLTEN12
MSEL12
FSEL12
0000
FLTEN13
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
PIC32MX5XX/6XX/7XX
DS60001156K-page 248
TABLE 24-2:
Virtual Address
(BF88_#)
C100 C2FLTCON4
C110 C2FLTCON5
C120 C2FLTCON6
C130 C2FLTCON7
C140
C340
CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED)
C2RXFn
(n = 0-31)
C2FIFOBA
C380
29/13
28/12
27/11
26/10
25/9
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
MSEL19
FSEL19
FLTEN18
MSEL18
FSEL18
0000
15:0
FLTEN17
MSEL17
FSEL17
FLTEN16
MSEL16
FSEL16 7).
This register can only be modified when the CAN module is in Configuration mode (OPMOD
(CiCON) = 100).
DS60001156K-page 252
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 24-2:
CiCFG: CAN BAUD RATE CONFIGURATION REGISTER (CONTINUED)
bit 10-8
PRSEG: Propagation Time Segment bits(4)
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
bit 7-6
SJW: Synchronization Jump Width bits(3)
11 = Length is 4 x TQ
10 = Length is 3 x TQ
01 = Length is 2 x TQ
00 = Length is 1 x TQ
bit 5-0
BRP: Baud Rate Prescaler bits
111111 = TQ = (2 x 64)/FSYS
111110 = TQ = (2 x 63)/FSYS
•
•
•
000001 = TQ = (2 x 2)/FSYS
000000 = TQ = (2 x 1)/FSYS
Note 1:
2:
3:
4:
SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.
3 Time bit sampling is not allowed for BRP < 2.
SJW SEG2PH.
The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7).
Note:
This register can only be modified when the CAN module is in Configuration mode (OPMOD
(CiCON) = 100).
2009-2019 Microchip Technology Inc.
DS60001156K-page 253
PIC32MX5XX/6XX/7XX
REGISTER 24-3:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
CiINT: CAN INTERRUPT REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
IVRIE
WAKIE
CERRIE
SERRIE
RBOVIE
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
MODIE
CTMRIE
RBIE
TBIE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
(1)
IVRIF
WAKIF
CERRIF
RBOVIF
—
—
—
U-0
U-0
U-0
SERRIF
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
MODIF
CTMRIF
RBIF
TBIF
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
IVRIE: Invalid Message Received Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 30
WAKIE: CAN Bus Activity Wake-up Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 29
CERRIE: CAN Bus Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 28
SERRIE: System Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 27
RBOVIE: Receive Buffer Overflow Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
x = Bit is unknown
bit 26-20 Unimplemented: Read as ‘0’
bit 19
MODIE: Mode Change Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 18
CTMRIE: CAN Timestamp Timer Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 17
RBIE: Receive Buffer Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 16
TBIE: Transmit Buffer Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 15
IVRIF: Invalid Message Received Interrupt Flag bit
1 = An invalid messages interrupt has occurred
0 = An invalid message interrupt has not occurred
Note 1:
This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit
(CiCON).
DS60001156K-page 254
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 24-3:
CiINT: CAN INTERRUPT REGISTER (CONTINUED)
bit 14
WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit
1 = A bus wake-up activity interrupt has occurred
0 = A bus wake-up activity interrupt has not occurred
bit 13
CERRIF: CAN Bus Error Interrupt Flag bit
1 = A CAN bus error has occurred
0 = A CAN bus error has not occurred
bit 12
SERRIF: System Error Interrupt Flag bit
1 = A system error occurred (typically an illegal address was presented to the system bus)
0 = A system error has not occurred
bit 11
RBOVIF: Receive Buffer Overflow Interrupt Flag bit
1 = A receive buffer overflow has occurred
0 = A receive buffer overflow has not occurred
bit 10-4
Unimplemented: Read as ‘0’
bit 3
MODIF: CAN Mode Change Interrupt Flag bit
1 = A CAN module mode change has occurred (OPMOD has changed to reflect REQOP)
0 = A CAN module mode change has not occurred
bit 2
CTMRIF: CAN Timer Overflow Interrupt Flag bit
1 = A CAN timer (CANTMR) overflow has occurred
0 = A CAN timer (CANTMR) overflow has not occurred
bit 1
RBIF: Receive Buffer Interrupt Flag bit
1 = A receive buffer interrupt is pending
0 = A receive buffer interrupt is not pending
bit 0
TBIF: Transmit Buffer Interrupt Flag bit
1 = A transmit buffer interrupt is pending
0 = A transmit buffer interrupt is not pending
Note 1:
This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit
(CiCON).
2009-2019 Microchip Technology Inc.
DS60001156K-page 255
PIC32MX5XX/6XX/7XX
REGISTER 24-4:
Bit
Range
CiVEC: CAN INTERRUPT CODE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
31:24
23:16
15:8
7:0
—
—
—
U-0
R-1
R-0
FILHIT
R-0
(1)
—
ICODE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12-8
FILHIT: Filter Hit Number bit
11111 = Filter 31
11110 = Filter 30
•
•
•
00001 = Filter 1
00000 = Filter 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
ICODE: Interrupt Flag Code bits(1)
1111111 = Reserved
•
•
•
1001001 = Reserved
1001000 = Invalid message received (IVRIF)
1000111 = CAN module mode change (MODIF)
1000110 = CAN timestamp timer (CTMRIF)
1000101 = Bus bandwidth error (SERRIF)
1000100 = Address error interrupt (SERRIF)
1000011 = Receive FIFO overflow interrupt (RBOVIF)
1000010 = Wake-up interrupt (WAKIF)
1000001 = Error Interrupt (CERRIF)
1000000 = No interrupt
0111111 = Reserved
•
•
•
0100000 = Reserved
0011111 = FIFO31 Interrupt (CiFSTAT set)
0011110 = FIFO30 Interrupt (CiFSTAT set)
•
•
•
0000001 = FIFO1 Interrupt (CiFSTAT set)
0000000 = FIFO0 Interrupt (CiFSTAT set)
Note 1:
These bits are only updated for enabled interrupts.
DS60001156K-page 256
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 24-5:
Bit
Range
31:24
23:16
15:8
7:0
CiTREC: CAN TRANSMIT/RECEIVE ERROR COUNT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R-0
R-0
R-0
R-0
R-0
R-0
—
—
TXBO
TXBP
RXBP
TXWARN
RXWARN
EWARN
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
TERRCNT
R-0
RERRCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-22 Unimplemented: Read as ‘0’
bit 21
TXBO: Transmitter in Error State Bus OFF (TERRCNT 256)
bit 20
TXBP: Transmitter in Error State Bus Passive (TERRCNT 128)
bit 19
RXBP: Receiver in Error State Bus Passive (RERRCNT 128)
bit 18
TXWARN: Transmitter in Error State Warning (128 > TERRCNT 96)
bit 17
RXWARN: Receiver in Error State Warning (128 > RERRCNT 96)
bit 16
EWARN: Transmitter or Receiver is in Error State Warning
bit 15-8
TERRCNT: Transmit Error Counter
bit 7-0
RERRCNT: Receive Error Counter
REGISTER 24-6:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
CiFSTAT: CAN FIFO STATUS REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FIFOIP31
FIFOIP30
FIFOIP29
FIFOIP28
FIFOIP27
FIFOIP26
FIFOIP25
FIFOIP24
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FIFOIP23
FIFOIP22
FIFOIP21
FIFOIP20
FIFOIP19
FIFOIP18
FIFOIP17
FIFOIP16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FIFOIP15
FIFOIP14
FIFOIP13
FIFOIP12
FIFOIP11
FIFOIP10
FIFOIP9
FIFOIP8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FIFOIP7
FIFOIP6
FIFOIP5
FIFOIP4
FIFOIP3
FIFOIP2
FIFOIP1
FIFOIP0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 FIFOIP: FIFOn Interrupt Pending bits
1 = One or more enabled FIFO interrupts are pending
0 = No FIFO interrupts are pending
2009-2019 Microchip Technology Inc.
DS60001156K-page 257
PIC32MX5XX/6XX/7XX
REGISTER 24-7:
Bit
Range
CiRXOVF: CAN RECEIVE FIFO OVERFLOW STATUS REGISTER
Bit
31/23/15/7
31:24
23:16
15:8
7:0
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R-0
R-0
R-0
R-0
R-0
RXOVF31
RXOVF30
RXOVF29
RXOVF28
RXOVF27
Bit
26/18/10/2
Bit
25/17/9/1
R-0
R-0
RXOVF26 RXOVF25
R-0
Bit
24/16/8/0
R-0
RXOVF24
R-0
R-0
R-0
R-0
R-0
RXOVF23
RXOVF22
RXOVF21
RXOVF20
RXOVF19
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RXOVF15
RXOVF14
RXOVF13
RXOVF12
RXOVF11
RXOVF10
RXOVF9
RXOVF8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RXOVF7
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0
RXOVF18 RXOVF17
R-0
RXOVF16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
RXOVF: FIFOn Receive Overflow Interrupt Pending bit
1 = FIFO has overflowed
0 = FIFO has not overflowed
REGISTER 24-8:
Bit
Range
31:24
CiTMR: CAN TIMER REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CANTS
R/W-0
23:16
R/W-0
R/W-0
R/W-0
R/W-0
CANTS
15:8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CANTSPRE
7:0
R/W-0
R/W-0
CANTSPRE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0
CANTS: CAN Time Stamp Timer bits
This is a free-running timer that increments every CANTSPRE system clocks when the CANCAP bit
(CiCON) is set.
bit 15-0
CANTSPRE: CAN Time Stamp Timer Prescaler bits
1111 1111 1111 1111 = CAN time stamp timer (CANTS) increments every 65,535 system clocks
•
•
•
0000 0000 0000 0000 = CAN time stamp timer (CANTS) increments every system clock
Note 1:
2:
CiTMR will be paused when CANCAP = 0.
The CiTMR prescaler count will be reset on any write to CiTMR (CANTSPRE will be unaffected).
DS60001156K-page 258
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 24-9:
Bit
Range
31:24
23:16
15:8
7:0
CiRXMn: CAN ACCEPTANCE FILTER MASK ‘n’ REGISTER (n = 0, 1, 2 OR 3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SID
R/W-0
R/W-0
R/W-0
SID
U-0
R/W-0
U-0
—
MIDE
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EID
EID
R/W-0
EID
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-21
SID: Standard Identifier bits
1 = Include the SIDx bit in filter comparison
0 = The SIDx bit is a ‘don’t care’ in filter operation
bit 20
Unimplemented: Read as ‘0’
bit 19
MIDE: Identifier Receive Mode bit
1 = Match only message types (standard/extended address) that correspond to the EXID bit in filter
0 = Match either standard or extended address message if filters match (that is, if (Filter SID) = (Message
SID) or if (FILTER SID/EID) = (Message SID/EID))
bit 18
Unimplemented: Read as ‘0’
bit 17-0
EID: Extended Identifier bits
1 = Include the EIDx bit in filter comparison
0 = The EIDx bit is a ‘don’t care’ in filter operation
Note:
This register can only be modified when the CAN module is in Configuration mode (OPMOD
(CiCON) = 100).
2009-2019 Microchip Technology Inc.
DS60001156K-page 259
PIC32MX5XX/6XX/7XX
REGISTER 24-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0
Bit Range
31:24
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN3
R/W-0
23:16
FLTEN2
R/W-0
15:8
FLTEN1
R/W-0
7:0
FLTEN0
MSEL3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL2
R/W-0
R/W-0
R/W-0
R/W-0
MSEL1
R/W-0
Bit
25/17/9/1
FSEL3
MSEL2
R/W-0
Bit
26/18/10/2
R/W-0
FSEL1
MSEL0
R/W-0
FSEL0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
FLTEN3: Filter 3 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29
MSEL3: Filter 3 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24
FSEL3: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
x = Bit is unknown
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN2: Filter 2 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21
MSEL2: Filter 2 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16
FSEL2: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001156K-page 260
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 24-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0 (CONTINUED)
bit 15
FLTEN1: Filter 1 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13
MSEL1: Filter 1 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL1: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN0: Filter 0 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL0: Filter 0 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL0: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2009-2019 Microchip Technology Inc.
DS60001156K-page 261
PIC32MX5XX/6XX/7XX
REGISTER 24-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1
Bit
Range
31:24
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN7
R/W-0
23:16
FLTEN6
R/W-0
15:8
FLTEN5
R/W-0
7:0
FLTEN4
MSEL7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL6
R/W-0
R/W-0
R/W-0
R/W-0
MSEL5
R/W-0
Bit
25/17/9/1
FSEL7
MSEL6
R/W-0
Bit
26/18/10/2
R/W-0
FSEL5
MSEL4
R/W-0
FSEL4
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
FLTEN7: Filter 7 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL7: Filter 7 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL7: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN6: Filter 6 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL6: Filter 6 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL6: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001156K-page 262
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 24-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1 (CONTINUED)
bit 15
FLTEN5: Filter 17 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL5: Filter 5 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL5: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN4: Filter 4 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL4: Filter 4 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL4: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2009-2019 Microchip Technology Inc.
DS60001156K-page 263
PIC32MX5XX/6XX/7XX
REGISTER 24-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2
Bit
Range
31:24
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN11
R/W-0
23:16
FLTEN10
R/W-0
15:8
FLTEN9
R/W-0
7:0
FLTEN8
MSEL11
R/W-0
FSEL11
R/W-0
R/W-0
R/W-0
MSEL10
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSEL9
R/W-0
R/W-0
FSEL10
R/W-0
FSEL9
R/W-0
MSEL8
R/W-0
FSEL8
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
FLTEN11: Filter 11 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29
MSEL11: Filter 11 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24
FSEL11: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
x = Bit is unknown
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN10: Filter 10 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21
MSEL10: Filter 10 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16
FSEL10: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001156K-page 264
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 24-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2 (CONTINUED)
bit 15
FLTEN9: Filter 9 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13
MSEL9: Filter 9 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL9: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN8: Filter 8 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL8: Filter 8 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL8: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2009-2019 Microchip Technology Inc.
DS60001156K-page 265
PIC32MX5XX/6XX/7XX
REGISTER 24-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3
Bit
Range
31:24
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN15
R/W-0
23:16
FLTEN14
R/W-0
15:8
FLTEN13
R/W-0
7:0
FLTEN12
MSEL15
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL14
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSEL13
R/W-0
Bit
25/17/9/1
FSEL15
MSEL14
R/W-0
Bit
26/18/10/2
R/W-0
FSEL13
R/W-0
MSEL12
R/W-0
FSEL12
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
FLTEN15: Filter 15 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29
MSEL15: Filter 15 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24
FSEL15: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
x = Bit is unknown
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN14: Filter 14 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21
MSEL14: Filter 14 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16
FSEL14: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001156K-page 266
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 24-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3 (CONTINUED)
bit 15
FLTEN13: Filter 13 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13
MSEL13: Filter 13 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL13: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN12: Filter 12 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL12: Filter 12 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL12: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2009-2019 Microchip Technology Inc.
DS60001156K-page 267
PIC32MX5XX/6XX/7XX
,4
REGISTER 24-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
FLTEN19
R/W-0
23:16
FLTEN18
R/W-0
15:8
FLTEN17
R/W-0
7:0
FLTEN16
MSEL19
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL18
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSEL17
R/W-0
Bit
25/17/9/1
FSEL19
MSEL18
R/W-0
Bit
26/18/10/2
R/W-0
FSEL17
R/W-0
MSEL16
R/W-0
FSEL16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
FLTEN19: Filter 19 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29
MSEL19: Filter 19 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24
FSEL19: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
x = Bit is unknown
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN18: Filter 18 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21
MSEL18: Filter 18 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16
FSEL18: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001156K-page 268
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 24-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4 (CONTINUED)
bit 15
FLTEN17: Filter 13 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13
MSEL17: Filter 17 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL17: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN16: Filter 16 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL16: Filter 16 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL16: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2009-2019 Microchip Technology Inc.
DS60001156K-page 269
PIC32MX5XX/6XX/7XX
REGISTER 24-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5
Bit
Range
31:24
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN23
R/W-0
23:16
FLTEN22
R/W-0
15:8
FLTEN21
R/W-0
7:0
FLTEN20
MSEL23
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL22
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSEL21
R/W-0
Bit
25/17/9/1
FSEL23
MSEL22
R/W-0
Bit
26/18/10/2
R/W-0
FSEL21
R/W-0
MSEL20
R/W-0
FSEL20
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
FLTEN23: Filter 23 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29
MSEL23: Filter 23 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24
FSEL23: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
x = Bit is unknown
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN22: Filter 22 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21
MSEL22: Filter 22 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16
FSEL22: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001156K-page 270
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 24-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5 (CONTINUED)
bit 15
FLTEN21: Filter 21 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13
MSEL21: Filter 21 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL21: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN20: Filter 20 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL20: Filter 20 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL20: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2009-2019 Microchip Technology Inc.
DS60001156K-page 271
PIC32MX5XX/6XX/7XX
REGISTER 24-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6
Bit
Range
31:24
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN27
R/W-0
23:16
FLTEN26
R/W-0
15:8
FLTEN25
R/W-0
7:0
FLTEN24
MSEL27
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL26
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSEL25
R/W-0
Bit
25/17/9/1
FSEL27
MSEL26
R/W-0
Bit
26/18/10/2
R/W-0
FSEL25
R/W-0
MSEL24
R/W-0
FSEL24
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
FLTEN27: Filter 27 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL27: Filter 27 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL27: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN26: Filter 26 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL26: Filter 26 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL26: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001156K-page 272
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 24-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6 (CONTINUED)
bit 15
FLTEN25: Filter 25 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL25: Filter 25 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL25: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN24: Filter 24 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL24: Filter 24 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL24: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2009-2019 Microchip Technology Inc.
DS60001156K-page 273
PIC32MX5XX/6XX/7XX
REGISTER 24-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7
Bit
Range
31:24
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN31
R/W-0
23:16
FLTEN30
R/W-0
15:8
FLTEN29
R/W-0
7:0
FLTEN28
MSEL31
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL30
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSEL29
R/W-0
Bit
25/17/9/1
FSEL31
MSEL30
R/W-0
Bit
26/18/10/2
R/W-0
FSEL29
R/W-0
MSEL28
R/W-0
FSEL28
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
FLTEN31: Filter 31 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL31: Filter 31 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL31: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN30: Filter 30Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL30: Filter 30Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL30: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001156K-page 274
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 24-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7 (CONTINUED)
bit 15
FLTEN29: Filter 29 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL29: Filter 29 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL29: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN28: Filter 28 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL28: Filter 28 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL28: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2009-2019 Microchip Technology Inc.
DS60001156K-page 275
PIC32MX5XX/6XX/7XX
REGISTER 24-18: CiRXFn: CAN ACCEPTANCE FILTER ‘n’ REGISTER 7 (n = 0 THROUGH 31)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID
R/W-x
R/W-x
R/W-x
SID
U-0
R/W-0
U-0
—
EXID
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID
EID
R/W-x
EID
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-21 SID: Standard Identifier bits
1 = Message address bit SIDx must be ‘1’ to match filter
0 = Message address bit SIDx must be ‘0’ to match filter
bit 20
Unimplemented: Read as ‘0’
bit 19
EXID: Extended Identifier Enable bits
1 = Match only messages with extended identifier addresses
0 = Match only messages with standard identifier addresses
bit 18
Unimplemented: Read as ‘0’
bit 17-0
EID: Extended Identifier bits
1 = Message address bit EIDx must be ‘1’ to match filter
0 = Message address bit EIDx must be ‘0’ to match filter
Note:
This register can only be modified when the filter is disabled (FLTENn = 0).
DS60001156K-page 276
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 24-19: CiFIFOBA: CAN MESSAGE BUFFER BASE ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0(1)
R-0(1)
CiFIFOBA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CiFIFOBA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CiFIFOBA
R/W-0
CiFIFOBA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0
CiFIFOBA: CAN FIFO Base Address bits
These bits define the base address of all message buffers. Individual message buffers are located based
on the size of the previous message buffers. This address is a physical address. Bits are read-only
and read as ‘0’, forcing the messages to be 32-bit word-aligned in device RAM.
Note 1:
This bit is unimplemented and will always read ‘0’, which forces word-alignment of messages.
Note:
This register can only be modified when the CAN module is in Configuration mode (OPMOD
(CiCON) = 100).
2009-2019 Microchip Technology Inc.
DS60001156K-page 277
PIC32MX5XX/6XX/7XX
REGISTER 24-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER ‘n’ (n = 0 THROUGH 31)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
U-0
S/HC-0
S/HC-0
U-0
U-0
FSIZE(1)
R/W-0
DONLY
U-0
(1)
U-0
—
FRESET
UINC
—
—
—
—
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXEN
TXABAT(2)
TXLARB(3)
TXERR(3)
TXREQ
RTREN
TXPR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-21 Unimplemented: Read as ‘0’
bit 20-16 FSIZE: FIFO Size bits(1)
11111 = FIFO is 32 messages deep
•
•
•
00010 = FIFO is 3 messages deep
00001 = FIFO is 2 messages deep
00000 = FIFO is 1 message deep
bit 15
Unimplemented: Read as ‘0’
bit 14
FRESET: FIFO Reset bits
1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user should
poll whether this bit is clear before taking any action.
0 = No effect
bit 13
UINC: Increment Head/Tail bit
TXEN = 1: (FIFO configured as a Transmit FIFO)
When this bit is set the FIFO head will increment by a single message
TXEN = 0: (FIFO configured as a Receive FIFO)
When this bit is set the FIFO tail will increment by a single message
bit 12
DONLY: Store Message Data Only bit(1)
TXEN = 1: (FIFO configured as a Transmit FIFO)
This bit is not used and has no effect.
TXEN = 0: (FIFO configured as a Receive FIFO)
1 = Only data bytes will be stored in the FIFO
0 = Full message is stored, including identifier
bit 11-8
Unimplemented: Read as ‘0’
bit 7
TXEN: TX/RX Buffer Selection bit
1 = FIFO is a Transmit FIFO
0 = FIFO is a Receive FIFO
Note 1:
These bits can only be modified when the CAN module is in Configuration mode (OPMOD bits
(CiCON) = 100).
This bit is updated when a message completes (or aborts) or when the FIFO is reset.
This bit is reset on any read of this register or when the FIFO is reset.
2:
3:
DS60001156K-page 278
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 24-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER ‘n’ (n = 0 THROUGH 31)
bit 6
TXABAT: Message Aborted bit(2)
1 = Message was aborted
0 = Message completed successfully
bit 5
TXLARB: Message Lost Arbitration bit(3)
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 4
TXERR: Error Detected During Transmission bit(3)
1 = A bus error occured while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 3
TXREQ: Message Send Request
TXEN = 1: (FIFO configured as a Transmit FIFO)
Setting this bit to ‘1’ requests sending a message.
The bit will automatically clear when all the messages queued in the FIFO are successfully sent.
Clearing the bit to ‘0’ while set (‘1’) will request a message abort.
TXEN = 0: (FIFO configured as a receive FIFO)
This bit has no effect.
bit 2
RTREN: Auto RTR Enable bit
1 = When a remote transmit is received, TXREQ will be set
0 = When a remote transmit is received, TXREQ will be unaffected
bit 1-0
TXPR: Message Transmit Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority
Note 1:
These bits can only be modified when the CAN module is in Configuration mode (OPMOD bits
(CiCON) = 100).
This bit is updated when a message completes (or aborts) or when the FIFO is reset.
This bit is reset on any read of this register or when the FIFO is reset.
2:
3:
2009-2019 Microchip Technology Inc.
DS60001156K-page 279
PIC32MX5XX/6XX/7XX
REGISTER 24-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (n = 0 THROUGH 31)
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
31:24
23:16
15:8
7:0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
TXNFULLIE
TXHALFIE
TXEMPTYIE
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
RXOVFLIE
RXFULLIE
RXHALFIE
RXNEMPTYIE
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
—
—
—
—
—
TXNFULLIF(1)
TXHALFIF
TXEMPTYIF(1)
U-0
U-0
U-0
U-0
R/W-0
R-0
R-0
R-0
—
—
—
—
(1)
RXOVFLIF RXFULLIF
(1)
RXHALFIF
RXNEMPTYIF(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26
TXNFULLIE: Transmit FIFO Not Full Interrupt Enable bit
1 = Interrupt enabled for FIFO not full
0 = Interrupt disabled for FIFO not full
bit 25
TXHALFIE: Transmit FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 24
TXEMPTYIE: Transmit FIFO Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO empty
0 = Interrupt disabled for FIFO empty
bit 23-20 Unimplemented: Read as ‘0’
bit 19
RXOVFLIE: Overflow Interrupt Enable bit
1 = Interrupt enabled for overflow event
0 = Interrupt disabled for overflow event
bit 18
RXFULLIE: Full Interrupt Enable bit
1 = Interrupt enabled for FIFO full
0 = Interrupt disabled for FIFO full
bit 17
RXHALFIE: FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 16
RXNEMPTYIE: Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO not empty
0 = Interrupt disabled for FIFO not empty
bit 15-11 Unimplemented: Read as ‘0’
bit 10
TXNFULLIF: Transmit FIFO Not Full Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)
1 = FIFO is not full
0 = FIFO is full
TXEN = 0: (FIFO configured as a receive buffer)
Unused, reads ‘0’
Note 1:
This bit is read-only and reflects the status of the FIFO.
DS60001156K-page 280
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 24-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (n = 0 THROUGH 31)
bit 9
TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)
1 = FIFO is half full
0 = FIFO is > half full
TXEN = 0: (FIFO configured as a receive buffer)
Unused, reads ‘0’
bit 8
TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)
1 = FIFO is empty
0 = FIFO is not empty, at least 1 message queued to be transmitted
TXEN = 0: (FIFO configured as a receive buffer)
Unused, reads ‘0’
bit 7-4
Unimplemented: Read as ‘0’
bit 3
RXOVFLIF: Receive FIFO Overflow Interrupt Flag bit
TXEN = 1: (FIFO configured as a transmit buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a receive buffer)
1 = Overflow event has occurred
0 = No overflow event occured
bit 2
RXFULLIF: Receive FIFO Full Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a receive buffer)
1 = FIFO is full
0 = FIFO is not full
bit 1
RXHALFIF: Receive FIFO Half Full Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a receive buffer)
1 = FIFO is half full
0 = FIFO is < half full
bit 0
RXNEMPTYIF: Receive Buffer Not Empty Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a receive buffer)
1 = FIFO is not empty, has at least 1 message
0 = FIFO is empty
Note 1:
This bit is read-only and reflects the status of the FIFO.
2009-2019 Microchip Technology Inc.
DS60001156K-page 281
PIC32MX5XX/6XX/7XX
REGISTER 24-22: CiFIFOUAn: CAN FIFO USER ADDRESS REGISTER ‘n’ (n = 0 THROUGH 31)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-0(1)
R-0(1)
CiFIFOUAn
R-x
R-x
R-x
R-x
R-x
R-x
CiFIFOUAn
R-x
R-x
R-x
R-x
R-x
CiFIFOUAn
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
R-x
CiFIFOUAn
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
CiFIFOUAn: CAN FIFO User Address bits
TXEN = 1: (FIFO configured as a transmit buffer)
A read of this register will return the address where the next message is to be written (FIFO head).
TXEN = 0: (FIFO configured as a receive buffer)
A read of this register will return the address where the next message is to be read (FIFO tail).
Note 1:
Note:
This bit will always read ‘0’, which forces byte-alignment of messages.
This register is not guaranteed to read correctly in Configuration mode, and should only be accessed when
the module is not in Configuration mode.
REGISTER 24-23: CiFIFOCIN: CAN MODULE MESSAGE INDEX REGISTER ‘n’ (n = 0 THROUGH 31)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R-0
R-0
R-0
R-0
R-0
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
CiFIFOCI
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-5 Unimplemented: Read as ‘0’
bit 4-0
CiFIFOCIn: CAN Side FIFO Message Index bits
TXEN = 1: (FIFO configured as a transmit buffer)
A read of this register will return an index to the message that the FIFO will next attempt to transmit.
TXEN = 0: (FIFO configured as a receive buffer)
A read of this register will return an index to the message that the FIFO will use to save the next message.
DS60001156K-page 282
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
25.0
Note:
ETHERNET CONTROLLER
Key features of the Ethernet Controller include:
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 35. “Ethernet
Controller” (DS60001155) in the “PIC32
Family Reference Manual”, which is available from the Microchip web site
(www.microchip.com/PIC32).
•
•
•
•
•
•
•
•
The Ethernet controller is a bus master module that
interfaces with an off-chip Physical Layer (PHY) to
implement a complete Ethernet node in a system.
•
•
Supports 10/100 Mbps data transfer rates
Supports full-duplex and half-duplex operation
Supports RMII and MII PHY interface
Supports MIIM PHY management interface
Supports both manual and automatic Flow Control
RAM descriptor-based DMA operation for both
receive and transmit path
Fully configurable interrupts
Configurable receive packet filtering
- CRC check
- 64-byte pattern match
- Broadcast, multicast and unicast packets
- Magic Packet™
- 64-bit hash table
- Runt packet
Supports packet payload checksum calculation
Supports various hardware statistics counters
Figure 25-1 illustrates a block diagram of the Ethernet
controller.
ETHERNET CONTROLLER BLOCK DIAGRAM
TX
FIFO
FIGURE 25-1:
TX DMA
TX BM
TX Bus
Master
TX Function
TX Flow Control
System Bus
RX DMA
RX
FIFO
MII/RMII
IF
RX Flow
Control
RX BM
External
PHY
MAC
RX Bus
Master
RX Filter
RX Function
Checksum
Fast Peripheral
Bus
DMA
Control
Registers
Ethernet DMA
MIIM
IF
MAC Control
and
Configuration
Registers
Host IF
Ethernet Controller
2009-2019 Microchip Technology Inc.
DS60001156K-page 283
PIC32MX5XX/6XX/7XX
Table 25-1, Table 25-2, Table 25-3 and Table 25-4
show four interfaces and the associated pins that can
be used with the Ethernet Controller.
TABLE 25-1:
MII MODE DEFAULT
INTERFACE SIGNALS
(FMIIEN = 1, FETHIO = 1)
TABLE 25-3:
Pin Name
AEMDC
MII MODE ALTERNATE
INTERFACE SIGNALS
(FMIIEN = 1, FETHIO = 0)
Description
Management Clock
AEMDIO
Management I/O
AETXCLK
Transmit Clock
Management Clock
AETXEN
Transmit Enable
EMDIO
Management I/O
AETXD0
Transmit Data
ETXCLK
Transmit Clock
AETXD1
Transmit Data
ETXEN
Transmit Enable
AETXD2
Transmit Data
ETXD0
Transmit Data
AETXD3
Transmit Data
ETXD1
Transmit Data
AETXERR
Transmit Error
ETXD2
Transmit Data
AERXCLK
Receive Clock
ETXD3
Transmit Data
AERXDV
Receive Data Valid
ETXERR
Transmit Error
AERXD0
Receive Data
ERXCLK
Receive Clock
AERXD1
Receive Data
ERXDV
Receive Data Valid
AERXD2
Receive Data
ERXD0
Receive Data
AERXD3
Receive Data
ERXD1
Receive Data
AERXERR
Receive Error
ERXD2
Receive Data
AECRS
Carrier Sense
ERXD3
Receive Data
AECOL
Collision Indication
Pin Name
EMDC
Description
ERXERR
Receive Error
ECRS
Carrier Sense
ECOL
Collision Indication
TABLE 25-2:
RMII MODE DEFAULT
INTERFACE SIGNALS
(FMIIEN = 0, FETHIO = 1)
Pin Name
Description
EMDC
Management Clock
EMDIO
Management I/O
ETXEN
Transmit Enable
ETXD0
Transmit Data
ETXD1
Transmit Data
EREFCLK
Reference Clock
ECRSDV
Carrier Sense – Receive Data Valid
ERXD0
Receive Data
ERXD1
Receive Data
ERXERR
Receive Error
Note:
Note:
The MII mode Alternate Interface is not
available on 64-pin devices.
TABLE 25-4:
Pin Name
RMII MODE ALTERNATE
INTERFACE SIGNALS
(FMIIEN = 0, FETHIO = 0)
Description
AEMDC
Management Clock
AEMDIO
Management I/O
AETXEN
Transmit Enable
AETXD0
Transmit Data
AETXD1
Transmit Data
AEREFCLK
Reference Clock
AECRSDV
Carrier Sense – Receive Data Valid
AERXD0
Receive Data
AERXD1
Receive Data
AERXERR
Receive Error
Ethernet controller pins that are not used
by selected interface can be used by
other peripherals.
DS60001156K-page 284
2009-2019 Microchip Technology Inc.
Control Registers
Register
Name(1)
TABLE 25-5:
Virtual Address
(BF88_#)
9000
ETHCON1
9010
ETHCON2
9020
ETHTXST
9030
ETHRXST
9040
ETHHT0
9050
ETHHT1
9060
ETHPMM0
9070
ETHPMM1
9080
ETHPMCS
9090
ETHPMO
ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L,
PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
15:0
ON
—
SIDL
—
—
—
TXRTS
RXEN
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
31:16
ETHRXFC
90B0 ETHRXWM
DS60001156K-page 285
90C0
ETHIEN
90D0
ETHIRQ
Legend:
Note
19/3
18/2
17/1
16/0
AUTOFC
—
—
MANFC
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
0000
—
—
—
—
0000
BUFCDEC 0000
0000
TXSTADDR
RXSTADDR
15:0
0000
RXSTADDR
31:16
31:16
0000
0000
HT
15:0
31:16
0000
0000
PMM
15:0
31:16
0000
0000
PMM
15:0
—
—
—
—
—
—
—
15:0
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CRC
ERREN
CRC
OKEN
RUNT
ERREN
UCEN
NOT
MEEN
MCEN
BCEN
0000
PMCS
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
PMMODE
0000
0000
PMO
—
0000
0000
HT
15:0
0000
0000
0000
15:0
HTEN
MPEN
—
NOTPM
31:16
—
—
—
—
—
—
—
—
RUNTEN
RXFWM
15:0
—
—
—
—
—
—
—
—
RXEWM
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
TX
BUSEIE
RX
BUSEIE
—
—
—
EW
MARKIE
FW
MARKIE
RX
DONEIE
PK
TPENDIE
RX
ACTIE
—
TX
DONEIE
TX
ABORTIE
RX
BUFNAIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
TXBUSE
RXBUSE
—
—
—
EWMARK
FWMARK
RXDONE
PKTPEND
RXACT
—
TXDONE
TXABORT
RXBUFNA
0000
0000
—
0000
RX
0000
OVFLWIE
—
0000
RXOVFLW 0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
Reset values default to the factory programmed value.
PIC32MX5XX/6XX/7XX
90A0
20/4
TXSTADDR
31:16
31:16
21/5
RXBUFSZ
15:0
31:16
22/6
PTV
31:16
31:16
23/7
All Resets
Bits
Bit Range
2009-2019 Microchip Technology Inc.
25.1
Virtual Address
(BF88_#)
Register
Name(1)
90E0
ETHSTAT
ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L,
PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
9100
31:16
ETH
RXOVFLOW 15:0
—
—
—
—
—
—
—
9110
31:16
ETH
FRMTXOK 15:0
—
9120
31:16
ETH
SCOLFRM 15:0
—
9130
31:16
ETH
MCOLFRM 15:0
—
9140
31:16
ETH
FRMRXOK 15:0
—
31:16
—
9150
9160
ETH
FCSERR
23/7
22/6
21/5
20/4
—
BUSY
TXBUSY
RXBUSY
—
—
—
—
—
—
18/2
17/1
16/0
—
—
—
—
0000
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RXPAUSE
PASSALL
—
—
BUFCNT
—
—
—
—
—
—
—
—
0000
FRMTXOKCNT
—
—
—
—
—
—
—
—
SCOLFRMCNT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
SOFT
RESET
SIM
RESET
—
—
RESET
RMCS
RESET
RFUN
RESET
TMCS
RESET
TFUN
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
EXCESS
DFR
BP
NOBKOFF
NOBKOFF
—
—
LONGPRE
PUREPRE
AUTOPAD
VLANPAD
PAD
ENABLE
CRC
ENABLE
—
—
—
—
—
—
—
—
—
ALGNERRCNT
2009-2019 Microchip Technology Inc.
EMAC1
CFG1
9210
EMAC1
CFG2
9220
EMAC1
IPGT
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
9230
EMAC1
IPGR
31:16
—
—
—
—
—
—
—
—
—
15:0
—
9240
EMAC1
CLRT
31:16
—
—
15:0
—
—
9250
EMAC1
MAXF
31:16
—
—
NB2BIPKTGP1
—
—
—
—
—
CWINDOW
—
—
—
—
—
15:0
—
LOOPBACK TXPAUSE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
DELAYCRC HUGEFRM LENGTHCK FULLDPLX 4082
—
—
—
—
—
—
—
—
—
—
—
—
0000
0C12
RETX
—
0000
0012
NB2BIPKTGP2
—
0000
RXENABLE 800D
B2BIPKTGP
—
MACMAXF
0000
0000
—
—
0000
0000
—
—
0000
0000
FCSERRCNT
—
0000
0000
FRMRXOKCNT
—
0000
0000
MCOLFRMCNT
—
0000
0000
31:16
ETH
ALGNERR 15:0
Legend:
0000
RXOVFLWCNT
9200
Note
19/3
All Resets
Bit Range
Bits
—
—
0000
370F
—
0000
05EE
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
Reset values default to the factory programmed value.
PIC32MX5XX/6XX/7XX
DS60001156K-page 286
TABLE 25-5:
Virtual Address
(BF88_#)
Register
Name(1)
9260
EMAC1
SUPP
ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L,
PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED)
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
All Resets
Bits
Bit Range
2009-2019 Microchip Technology Inc.
TABLE 25-5:
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
RESET
RMII
—
—
SPEED
RMII
—
—
—
—
—
—
—
—
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
TESTBP
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9270
EMAC1
TEST
9280
EMAC1
MCFG
15:0
RESET
MGMT
—
—
—
—
—
—
—
—
—
9290
EMAC1
MCMD
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCAN
READ
0000
92A0
EMAC1
MADR
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
92B0
EMAC1
MWTD
31:16
—
—
—
—
—
—
—
—
—
—
—
92C0
EMAC1
MRDD
31:16
—
—
—
—
—
—
—
92D0
EMAC1
MIND
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
LINKFAIL
NOTVALID
SCAN
9300
EMAC1
SA0(2)
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9310
EMAC1
SA1(2)
31:16
—
—
—
9320
EMAC1
SA2(2)
31:16
—
—
—
Note
—
—
—
—
15:0
NOPRE
—
—
—
—
—
—
—
—
—
—
REGADDR
0100
—
—
15:0
—
—
—
—
—
—
—
STNADDR4
—
—
—
—
—
—
—
—
STNADDR2
—
—
—
—
—
—
STNADDR1
xxxx
xxxx
STNADDR3
—
0000
MIIMBUSY 0000
STNADDR5
—
0000
0000
STNADDR6
—
0000
0000
MRDD
15:0
0000
SCANINC 0020
MWTD
15:0
15:0
—
CLKSEL
—
xxxx
xxxx
xxxx
xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
Reset values default to the factory programmed value.
DS60001156K-page 287
PIC32MX5XX/6XX/7XX
Legend:
PHYADDR
TESTPAUSE SHRTQNTA 0000
PIC32MX5XX/6XX/7XX
REGISTER 25-1:
Bit Range
31:24
23:16
15:8
7:0
ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1
Bit
31/23/15/7
R/W-0
Bit
Bit
30/22/14/6 29/21/13/5
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTV
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTV
R/W-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
ON
—
SIDL
—
—
—
TXRTS
RXEN(1)
R/W-0
U-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
AUTOFC
—
—
MANFC
—
—
—
BUFCDEC
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-16
x = Bit is unknown
PTV: PAUSE Timer Value bits
PAUSE Timer Value used for Flow Control.
This register should only be written when RXEN (ETHCON1) is not set.
These bits are only used for Flow Control operations.
bit 15
ON: Ethernet ON bit
1 = Ethernet module is enabled
0 = Ethernet module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Ethernet Stop in Idle Mode bit
1 = Ethernet module transfers are paused during Idle mode
0 = Ethernet module transfers continue during Idle mode
bit 12-10
Unimplemented: Read as ‘0’
bit 9
TXRTS: Transmit Request to Send bit
1 = Activate the TX logic and send the packet(s) defined in the TX EDT
0 = Stop transmit (when cleared by software) or transmit done (when cleared by hardware)
After the bit is written with a ‘1’, it will clear to a ‘0’ whenever the transmit logic has finished transmitting
the requested packets in the Ethernet Descriptor Table (EDT). If a ‘0’ is written by the CPU, the transmit
logic finishes the current packet’s transmission and then stops any further.
This bit only affects TX operations.
bit 8
RXEN: Receive Enable bit(1)
1 = Enable RX logic, packets are received and stored in the RX buffer as controlled by the filter
configuration
0 = Disable RX logic, no packets are received in the RX buffer
This bit only affects RX operations.
Note 1:
It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The
Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.
DS60001156K-page 288
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 25-1:
bit 7
ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1 (CONTINUED)
AUTOFC: Automatic Flow Control bit
1 = Automatic Flow Control is enabled
0 = Automatic Flow Control is disabled
Setting this bit will enable automatic Flow Control. If set, the full and empty watermarks are used to
automatically enable and disable the Flow Control, respectively. When the number of received buffers
BUFCNT (ETHSTAT) rises to the full watermark, Flow Control is automatically enabled. When
the BUFCNT falls to the empty watermark, Flow Control is automatically disabled.
This bit is only used for Flow Control operations and affects both TX and RX operations.
bit 6-5
Unimplemented: Read as ‘0’
bit 4
MANFC: Manual Flow Control bit
1 = Manual Flow Control is enabled
0 = Manual Flow Control is disabled
Setting this bit will enable manual Flow Control. If set, the Flow Control logic will send a PAUSE frame
using the PAUSE timer value in the PTV register. It will then resend a PAUSE frame every 128 *
PTV/2 TX clock cycles until the bit is cleared.
Note:
For 10 Mbps operation, TX clock runs at 2.5 MHz. For 100 Mbps operation, TX clock runs at
25 MHz.
When this bit is cleared, the Flow Control logic will automatically send a PAUSE frame with a 0x0000
PAUSE timer value to disable Flow Control.
This bit is only used for Flow Control operations and affects both TX and RX operations.
bit 3-1
Unimplemented: Read as ‘0’
bit 0
BUFCDEC: Descriptor Buffer Count Decrement bit
The BUFCDEC bit is a write-1 bit that reads as ‘0’. When written with a ‘1’, the Descriptor Buffer Counter,
BUFCNT, will decrement by one. If BUFCNT is incremented by the RX logic at the same time that this bit
is written, the BUFCNT value will remain unchanged. Writing a ‘0’ will have no effect.
This bit is only used for RX operations.
Note 1:
It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The
Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.
2009-2019 Microchip Technology Inc.
DS60001156K-page 289
PIC32MX5XX/6XX/7XX
REGISTER 25-2:
Bit Range
ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2
Bit
31/23/15/7
31:24
23:16
15:8
7:0
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
—
RXBUFSZ
RXBUFSZ
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-11
Unimplemented: Read as ‘0’
bit 10-4
RXBUFSZ: RX Data Buffer Size for All RX Descriptors (in 16-byte increments) bits
1111111 = RX data Buffer size for descriptors is 2032 bytes
•
•
•
1100000 = RX data Buffer size for descriptors is 1536 bytes
•
•
•
0000011 = RX data Buffer size for descriptors is 48 bytes
0000010 = RX data Buffer size for descriptors is 32 bytes
0000001 = RX data Buffer size for descriptors is 16 bytes
0000000 = Reserved
bit 3-0
Note 1:
2:
Unimplemented: Read as ‘0’
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0.
DS60001156K-page 290
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 25-3:
Bit
Range
31:24
23:16
15:8
7:0
ETHTXST: ETHERNET CONTROLLER TX PACKET DESCRIPTOR START
ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
—
—
TXSTADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXSTADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXSTADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXSTADDR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-2 TXSTADDR: Starting Address of First Transmit Descriptor bits
This register should not be written while any transmit, receive or DMA operations are in progress.
This address must be 4-byte aligned (bits 1-0 must be ‘00’).
bit 1-0 Unimplemented: Read as ‘0’
Note 1:
2:
This register is only used for TX operations.
This register will be updated by hardware with the last descriptor used by the last successfully transmitted
packet.
REGISTER 25-4:
Bit
Range
31:24
23:16
15:8
7:0
ETHRXST: ETHERNET CONTROLLER RX PACKET DESCRIPTOR START
ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
—
—
RXSTADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXSTADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXSTADDR
R/W-0
R/W-0
R/W-0
R/W-0
RXSTADDR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-2 RXSTADDR: Starting Address of First Receive Descriptor bits
This register should not be written while any transmit, receive or DMA operations are in progress.
This address must be 4-byte aligned (bits 1-0 must be ‘00’).
bit 1-0 Unimplemented: Read as ‘0’
Note 1:
2:
This register is only used for RX operations.
This register will be updated by hardware with the last descriptor used by the last successfully transmitted
packet.
2009-2019 Microchip Technology Inc.
DS60001156K-page 291
PIC32MX5XX/6XX/7XX
REGISTER 25-5:
Bit
Range
ETHHT0: ETHERNET CONTROLLER HASH TABLE 0 REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
HT
R/W-0
23:16
R/W-0
R/W-0
R/W-0
R/W-0
HT
15:8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HT
7:0
R/W-0
HT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note 1:
2:
HT: Hash Table Bytes 0-3 bits
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0 or the HTEN bit
(ETHRXFC) = 0.
REGISTER 25-6:
Bit Range
31:24
23:16
15:8
7:0
x = Bit is unknown
ETHHT1: ETHERNET CONTROLLER HASH TABLE 1 REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HT
R/W-0
HT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note 1:
2:
x = Bit is unknown
HT: Hash Table Bytes 4-7 bits
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0 or the HTEN bit
(ETHRXFC) = 0.
DS60001156K-page 292
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 25-7:
Bit Range
31:24
ETHPMM0: ETHERNET CONTROLLER PATTERN MATCH MASK 0 REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMM
R/W-0
23:16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 31-24
bit 23-16
bit 15-8
bit 7-0
Note 1:
2:
R/W-0
R/W-0
W = Writable bit
‘1’ = Bit is set
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
ETHPMM1: ETHERNET CONTROLLER PATTERN MATCH MASK 1 REGISTER
Bit
24/16/8/0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMM
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMM
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMM
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMM
Legend:
R = Readable bit
-n = Value at POR
bit 31-24
bit 23-16
bit 15-8
bit 7-0
R/W-0
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0 or the PMMODE bit
(ETHRXFC) = 0.
Bit Range
7:0
R/W-0
PMM: Pattern Match Mask 3 bits
PMM: Pattern Match Mask 2 bits
PMM: Pattern Match Mask 1 bits
PMM: Pattern Match Mask 0 bits
REGISTER 25-8:
15:8
R/W-0
PMM
Legend:
R = Readable bit
-n = Value at POR
23:16
R/W-0
PMM
7:0
31:24
R/W-0
PMM
15:8
Note 1:
2:
R/W-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
PMM: Pattern Match Mask 7 bits
PMM: Pattern Match Mask 6 bits
PMM: Pattern Match Mask 5 bits
PMM: Pattern Match Mask 4 bits
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0 or the PMMODE bit
(ETHRXFC) = 0.
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PIC32MX5XX/6XX/7XX
REGISTER 25-9:
Bit Range
31:24
23:16
15:8
7:0
ETHPMCS: ETHERNET CONTROLLER PATTERN MATCH CHECKSUM
REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
Note 1:
2:
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMCS
R/W-0
PMCS
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-8
bit 7-0
Bit
24/16/8/0
Bit
31/23/15/7
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
PMCS: Pattern Match Checksum 1 bits
PMCS: Pattern Match Checksum 0 bits
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0 or the PMMODE bit
(ETHRXFC) = 0.
REGISTER 25-10: ETHPMO: ETHERNET CONTROLLER PATTERN MATCH OFFSET REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMO
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
Note 1:
2:
R/W-0
PMO
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
PMO: Pattern Match Offset 1 bits
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0 or the PMMODE bit
(ETHRXFC) = 0.
DS60001156K-page 294
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PIC32MX5XX/6XX/7XX
REGISTER 25-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
Bit
25/17/9/1 24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HTEN
MPEN
—
NOTPM
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CRCERREN
CRCOKEN
RUNTERREN
RUNTEN
UCEN
NOTMEEN
MCEN
BCEN
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
PMMODE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
HTEN: Enable Hash Table Filtering bit
1 = Enable Hash Table Filtering
0 = Disable Hash Table Filtering
bit 14
MPEN: Magic Packet™ Enable bit
1 = Enable Magic Packet Filtering
0 = Disable Magic Packet Filtering
bit 13
Unimplemented: Read as ‘0’
bit 12
NOTPM: Pattern Match Inversion bit
1 = The Pattern Match Checksum must not match for a successful Pattern Match to occur
0 = The Pattern Match Checksum must match for a successful Pattern Match to occur
This bit determines whether Pattern Match Checksum must match in order for a successful Pattern Match
to occur.
bit 11-8 PMMODE: Pattern Match Mode bits
1001 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Packet = Magic Packet)(1,3)
1000 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Hash Table Filter match)(1,2)
0111 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Broadcast Address)(1)
0110 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Broadcast Address)(1)
0101 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Unicast Address)(1)
0100 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Unicast Address)(1)
0011 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Station Address)(1)
0010 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Station Address)(1)
0001 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches)(1)
0000 = Pattern Match is disabled; pattern match is always unsuccessful
Note 1:
2:
3:
XOR = True when either one or the other conditions are true, but not both.
This Hash Table Filter match is active regardless of the value of the HTEN bit.
This Magic Packet Filter match is active regardless of the value of the MPEN bit.
Note 1:
2:
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0.
2009-2019 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX
REGISTER 25-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION
REGISTER (CONTINUED)
bit 7
bit 6
bit 5
bit 4
CRCERREN: CRC Error Collection Enable bit
1 = The received packet CRC must be invalid for the packet to be accepted
0 = Disable CRC Error Collection filtering
This bit allows the user to collect all packets that have an invalid CRC.
CRCOKEN: CRC OK Enable bit
1 = The received packet CRC must be valid for the packet to be accepted
0 = Disable CRC filtering
This bit allows the user to reject all packets that have an invalid CRC.
RUNTERREN: Runt Error Collection Enable bit
1 = The received packet must be a runt packet for the packet to be accepted
0 = Disable Runt Error Collection filtering
This bit allows the user to collect all packets that are runt packets. For this filter, a runt packet is defined as
any packet with a size of less than 64 bytes (when CRCOKEN = 0) or any packet with a size of less than
64 bytes that has a valid CRC (when CRCOKEN = 1).
RUNTEN: Runt Enable bit
1 = The received packet must not be a runt packet for the packet to be accepted
0 = Disable Runt filtering
bit 3
This bit allows the user to reject all runt packets. For this filter, a runt packet is defined as any packet with a
size of less than 64 bytes.
UCEN: Unicast Enable bit
1 = Enable Unicast Filtering
0 = Disable Unicast Filtering
bit 2
This bit allows the user to accept all unicast packets whose Destination Address matches the Station
Address.
NOTMEEN: Not Me Unicast Enable bit
1 = Enable Not Me Unicast Filtering
0 = Disable Not Me Unicast Filtering
bit 1
This bit allows the user to accept all unicast packets whose Destination Address does not match the Station
Address.
MCEN: Multicast Enable bit
1 = Enable Multicast Filtering
0 = Disable Multicast Filtering
bit 0
This bit allows the user to accept all Multicast Address packets.
BCEN: Broadcast Enable bit
1 = Enable Broadcast Filtering
0 = Disable Broadcast Filtering
This bit allows the user to accept all Broadcast Address packets.
Note 1:
2:
3:
XOR = True when either one or the other conditions are true, but not both.
This Hash Table Filter match is active regardless of the value of the HTEN bit.
This Magic Packet Filter match is active regardless of the value of the MPEN bit.
Note 1:
2:
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0.
DS60001156K-page 296
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PIC32MX5XX/6XX/7XX
REGISTER 25-12: ETHRXWM: ETHERNET CONTROLLER RECEIVE WATERMARKS REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
31:24
23:16
RXFWM
U-0
15:8
7:0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXEWM
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-24
Unimplemented: Read as ‘0’
bit 23-16
RXFWM: Receive Full Watermark bits
x = Bit is unknown
The software controlled RX Buffer Full Watermark Pointer is compared against the RX BUFCNT to
determine the full watermark condition for the FWMARK interrupt and for enabling Flow Control when
automatic Flow Control is enabled. The Full Watermark Pointer should always be greater than the Empty
Watermark Pointer.
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
RXEWM: Receive Empty Watermark bits
The software controlled RX Buffer Empty Watermark Pointer is compared against the RX BUFCNT to
determine the empty watermark condition for the EWMARK interrupt and for disabling Flow Control when
automatic Flow Control is enabled. The Empty Watermark Pointer should always be less than the Full
Watermark Pointer.
Note:
This register is only used for RX operations.
2009-2019 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX
REGISTER 25-13: ETHIEN: ETHERNET CONTROLLER INTERRUPT ENABLE REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
—
R/W-0
TXBUSEIE(1) RXBUSEIE(2)
R/W-0
R/W-0
RXDONEIE(2) PKTPENDIE(2) RXACTIE(2)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U-0
—
EWMARKIE(2) FWMARKIE(2)
R/W-0
R/W-0
TXDONEIE(1) TXABORTIE(1) RXBUFNAIE(2) RXOVFLWIE(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14
TXBUSEIE: Transmit BVCI Bus Error Interrupt Enable bit(1)
1 = Enable TXBUS Error Interrupt
0 = Disable TXBUS Error Interrupt
bit 13
RXBUSEIE: Receive BVCI Bus Error Interrupt Enable bit(2)
1 = Enable RXBUS Error Interrupt
0 = Disable RXBUS Error Interrupt
bit 12-10 Unimplemented: Read as ‘0’
bit 9
EWMARKIE: Empty Watermark Interrupt Enable bit(2)
1 = Enable EWMARK Interrupt
0 = Disable EWMARK Interrupt
bit 8
FWMARKIE: Full Watermark Interrupt Enable bit(2)
1 = Enable FWMARK Interrupt
0 = Disable FWMARK Interrupt
bit 7
RXDONEIE: Receiver Done Interrupt Enable bit(2)
1 = Enable RXDONE Interrupt
0 = Disable RXDONE Interrupt
bit 6
PKTPENDIE: Packet Pending Interrupt Enable bit(2)
1 = Enable PKTPEND Interrupt
0 = Disable PKTPEND Interrupt
bit 5
RXACTIE: RX Activity Interrupt Enable bit
1 = Enable RXACT Interrupt
0 = Disable RXACT Interrupt
bit 4
Unimplemented: Read as ‘0’
bit 3
TXDONEIE: Transmitter Done Interrupt Enable bit(1)
1 = Enable TXDONE Interrupt
0 = Disable TXDONE Interrupt
bit 2
TXABORTIE: Transmitter Abort Interrupt Enable bit(1)
1 = Enable TXABORT Interrupt
0 = Disable TXABORT Interrupt
bit 1
RXBUFNAIE: Receive Buffer Not Available Interrupt Enable bit(2)
1 = Enable RXBUFNA Interrupt
0 = Disable RXBUFNA Interrupt
bit 0
RXOVFLWIE: Receive FIFO Overflow Interrupt Enable bit(2)
1 = Enable RXOVFLW Interrupt
0 = Disable RXOVFLW Interrupt
Note 1:
2:
This bit is only used for TX operations.
This bit is only used for RX operations.
DS60001156K-page 298
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PIC32MX5XX/6XX/7XX
REGISTER 25-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
—
TXBUSE
RXBUSE
—
—
—
EWMARK
FWMARK
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
RXDONE
PKTPEND
RXACT
—
TXDONE
TXABORT
RXBUFNA RXOVFLW
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-15
Unimplemented: Read as ‘0’
bit 14
TXBUSE: Transmit BVCI Bus Error Interrupt bit
1 = BVCI Bus Error has occurred
0 = BVCI Bus Error has not occurred
x = Bit is unknown
This bit is set when the TX DMA encounters a BVCI Bus error during a memory access. It is cleared by
either a Reset or CPU write of a ‘1’ to the CLR register.
bit 13
RXBUSE: Receive BVCI Bus Error Interrupt bit
1 = BVCI Bus Error has occurred
0 = BVCI Bus Error has not occurred
This bit is set when the RX DMA encounters a BVCI Bus error during a memory access. It is cleared by
either a Reset or CPU write of a ‘1’ to the CLR register.
bit 12-10
Unimplemented: Read as ‘0’
bit 9
EWMARK: Empty Watermark Interrupt bit
1 = Empty Watermark pointer reached
0 = No interrupt pending
This bit is set when the RX Descriptor Buffer Count is less than or equal to the value in the
RXEWM bit (ETHRXWM) value. It is cleared by BUFCNT bit (ETHSTAT)
being incremented by hardware. Writing a ‘0’ or a ‘1’ has no effect.
bit 8
FWMARK: Full Watermark Interrupt bit
1 = Full Watermark pointer reached
0 = No interrupt pending
This bit is set when the RX Descriptor Buffer Count is greater than or equal to the value in the RXFWM
bit (ETHRXWM) field. It is cleared by writing the BUFCDEC (ETHCON1) bit to decrement
the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.
bit 7
RXDONE: Receive Done Interrupt bit
1 = RX packet was successfully received
0 = No interrupt pending
This bit is set whenever an RX packet is successfully received. It is cleared by either a Reset or CPU
write of a ‘1’ to the CLR register.
Note:
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
2009-2019 Microchip Technology Inc.
DS60001156K-page 299
PIC32MX5XX/6XX/7XX
REGISTER 25-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER
bit 6
PKTPEND: Packet Pending Interrupt bit
1 = RX packet pending in memory
0 = RX packet is not pending in memory
This bit is set when the BUFCNT counter has a value other than ‘0’. It is cleared by either a Reset or by
writing the BUFCDEC bit to decrement the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.
bit 5
RXACT: Receive Activity Interrupt bit
1 = RX packet data was successfully received
0 = No interrupt pending
This bit is set whenever RX packet data is stored in the RXBM FIFO. It is cleared by either a Reset or
CPU write of a ‘1’ to the CLR register.
bit 4
Unimplemented: Read as ‘0’
bit 3
TXDONE: Transmit Done Interrupt bit
1 = TX packet was successfully sent
0 = No interrupt pending
This bit is set when the currently transmitted TX packet completes transmission, and the Transmit Status
Vector is loaded into the first descriptor used for the packet. It is cleared by either a Reset or CPU write
of a ‘1’ to the CLR register.
bit 2
TXABORT: Transmit Abort Condition Interrupt bit
1 = TX abort condition occurred on the last TX packet
0 = No interrupt pending
This bit is set when the MAC aborts the transmission of a TX packet for one of the following reasons:
•
•
•
•
•
Jumbo TX packet abort
Underrun abort
Excessive defer abort
Late collision abort
Excessive collisions abort
This bit is cleared by either a Reset or CPU write of a ‘1’ to the CLR register.
bit 1
RXBUFNA: Receive Buffer Not Available Interrupt bit
1 = RX Buffer Descriptor Not Available condition has occurred
0 = No interrupt pending
This bit is set by a RX Buffer Descriptor Overrun condition. It is cleared by either a Reset or a CPU write
of a ‘1’ to the CLR register.
bit 0
RXOVFLW: Receive FIFO Over Flow Error bit
1 = RX FIFO Overflow Error condition has occurred
0 = No interrupt pending
RXOVFLW is set by the RXBM Logic for an RX FIFO Overflow condition. It is cleared by either a Reset
or CPU write of a ‘1’ to the CLR register.
Note:
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
DS60001156K-page 300
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 25-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
BUFCNT
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ETHBUSY(1)
TXBUSY(2)
RXBUSY(2)
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 BUFCNT: Packet Buffer Count bits
Number of packet buffers received in memory. Once a packet has been successfully received, this register
is incremented by hardware based on the number of descriptors used by the packet. Software decrements
the counter (by writing to the BUFCDEC bit (ETHCON1) for each descriptor used) after a packet has
been read out of the buffer. The register does not roll over (0xFF to 0x00) when hardware tries to increment
the register and the register is already at 0xFF. Conversely, the register does not roll under (0x00 to 0xFF)
when software tries to decrement the register and the register is already at 0x0000. When software attempts
to decrement the counter at the same time that the hardware attempts to increment the counter, the counter
value will remain unchanged.
When this register value reaches 0xFF, the RX logic will halt (only if automatic Flow Control is enabled)
awaiting software to write the BUFCDEC bit in order to decrement the register below 0xFF.
If automatic Flow Control is disabled, the RXDMA will continue processing and the BUFCNT will saturate at
a value of 0xFF.
When this register is non-zero, the PKTPEND status bit will be set and an interrupt may be generated,
depending on the value of the ETHIEN bit register.
When the ETHRXST register is written, the BUFCNT counter is automatically cleared to 0x00.
Note:
BUFCNT will not be cleared when ON is set to ‘0’. This enables software to continue to utilize
and decrement this count.
bit 15-8
Unimplemented: Read as ‘0’
bit 7
ETHBUSY: Ethernet Module busy bit(1)
1 = Ethernet logic has been turned on (ON (ETHCON1) = 1) or is completing a transaction
0 = Ethernet logic is idle
This bit indicates that the module has been turned on or is completing a transaction after being turned off.
bit 6
TXBUSY: Transmit Busy bit(2)
1 = TX logic is receiving data
0 = TX logic is idle
This bit indicates that a packet is currently being transmitted. A change in this status bit is not necessarily
reflected by the TXDONE interrupt, as TX packets may be aborted or rejected by the MAC.
Note 1:
2:
This bit will be set when the ON bit (ETHCON1) = 1.
This bit will be cleared when the ON bit (ETHCON1) = 0.
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REGISTER 25-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER (CONTINUED)
bit 5
RXBUSY: Receive Busy bit(2)
1 = RX logic is receiving data
0 = RX logic is idle
This bit indicates that a packet is currently being received. A change in this status bit is not necessarily
reflected by the RXDONE interrupt, as RX packets may be aborted or rejected by the RX filter.
bit 4-0
Unimplemented: Read as ‘0’
Note 1:
2:
This bit will be set when the ON bit (ETHCON1) = 1.
This bit will be cleared when the ON bit (ETHCON1) = 0.
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REGISTER 25-16: ETHRXOVFLOW: ETHERNET CONTROLLER RECEIVE OVERFLOW STATISTICS
REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
RXOVFLWCNT
R/W-0
R/W-0
RXOVFLWCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15-0
RXOVFLWCNT: Dropped Receive Frames Count bits
Increment counter for frames accepted by the RX filter and subsequently dropped due to internal receive
error (RXFIFO overrun). This event also sets the RXOVFLW bit (ETHIRQ) interrupt flag.
Note 1:
2:
3:
This register is only used for RX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for
bytes 0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
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REGISTER 25-17: ETHFRMTXOK: ETHERNET CONTROLLER FRAMES TRANSMITTED OK
STATISTICS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMTXOKCNT
R/W-0
R/W-0
FRMTXOKCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15-0
FRMTXOKCNT: Frame Transmitted OK Count bits
Increment counter for frames successfully transmitted.
Note 1:
2:
This register is only used for TX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
3:
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PIC32MX5XX/6XX/7XX
REGISTER 25-18: ETHSCOLFRM: ETHERNET CONTROLLER SINGLE COLLISION FRAMES
STATISTICS REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
SCOLFRMCNT
R/W-0
R/W-0
SCOLFRMCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15-0
SCOLFRMCNT: Single Collision Frame Count bits
Increment count for frames that were successfully transmitted on the second try.
Note 1:
2:
3:
This register is only used for TX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for
bytes 0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
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REGISTER 25-19: ETHMCOLFRM: ETHERNET CONTROLLER MULTIPLE COLLISION FRAMES
STATISTICS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
24/16/8/0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MCOLFRMCNT
R/W-0
R/W-0
MCOLFRMCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
MCOLFRMCNT: Multiple Collision Frame Count bits
Increment count for frames that were successfully transmitted after there was more than one collision.
Note 1:
2:
This register is only used for TX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
3:
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PIC32MX5XX/6XX/7XX
REGISTER 25-20: ETHFRMRXOK: ETHERNET CONTROLLER FRAMES RECEIVED OK
STATISTICS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMRXOKCNT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMRXOKCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15-0
FRMRXOKCNT: Frames Received OK Count bits
Increment count for frames received successfully by the RX Filter. This count will not be incremented if
there is a Frame Check Sequence (FCS) or Alignment error.
Note 1:
2:
This register is only used for RX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for
bytes 0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
3:
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REGISTER 25-21: ETHFCSERR: ETHERNET CONTROLLER FRAME CHECK SEQUENCE ERROR
STATISTICS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FCSERRCNT
R/W-0
R/W-0
FCSERRCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
FCSERRCNT: FCS Error Count bits
Increment count for frames received with FCS error and the frame length in bits is an integral multiple of
8 bits.
Note 1:
2:
This register is only used for RX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should be only done for debug/test purposes.
3:
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PIC32MX5XX/6XX/7XX
REGISTER 25-22: ETHALGNERR: ETHERNET CONTROLLER ALIGNMENT ERRORS STATISTICS
REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALGNERRCNT
R/W-0
7:0
R/W-0
R/W-0
R/W-0
R/W-0
ALGNERRCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
ALGNERRCNT: Alignment Error Count bits
Increment count for frames with alignment errors. Note that an alignment error is a frame that has an FCS
error and the frame length in bits is not an integral multiple of 8 bits (a.k.a., dribble nibble)
Note 1:
2:
This register is only used for RX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should be only done for debug/test purposes.
3:
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PIC32MX5XX/6XX/7XX
REGISTER 25-23: EMAC1CFG1: ETHERNET CONTROLLER MAC CONFIGURATION 1 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
Bit
30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
SOFT
RESET
SIM
RESET
—
—
RESET
RMCS
RESET
RFUN
RESET
TMCS
RESET
TFUN
U-0
U-0
U-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-1
LOOPBACK
TX
PAUSE
RX
PAUSE
PASSALL
RX
ENABLE
—
Legend:
R = Readable bit
-n = Value at POR
—
—
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
SOFTRESET: Soft Reset bit
Setting this bit will put the MACMII in reset. Its default value is ‘1’.
bit 14
SIMRESET: Simulation Reset bit
Setting this bit will cause a reset to the random number generator within the Transmit Function.
bit 13-12 Unimplemented: Read as ‘0’
bit 11
RESETRMCS: Reset MCS/RX bit
Setting this bit will put the MAC Control Sub-layer/Receive domain logic in reset.
bit 10
RESETRFUN: Reset RX Function bit
Setting this bit will put the MAC Receive function logic in reset.
bit 9
RESETTMCS: Reset MCS/TX bit
Setting this bit will put the MAC Control Sub-layer/TX domain logic in reset.
bit 8
RESETTFUN: Reset TX Function bit
Setting this bit will put the MAC Transmit function logic in reset.
bit 7-5
Unimplemented: Read as ‘0’
bit 4
LOOPBACK: MAC Loopback mode bit
1 = MAC Transmit interface is loop backed to the MAC Receive interface
0 = MAC normal operation
bit 3
TXPAUSE: MAC TX Flow Control bit
1 = PAUSE Flow Control frames are allowed to be transmitted
0 = PAUSE Flow Control frames are blocked
bit 2
RXPAUSE: MAC RX Flow Control bit
1 = The MAC acts upon received PAUSE Flow Control frames
0 = Received PAUSE Flow Control frames are ignored
bit 1
PASSALL: MAC Pass all Receive Frames bit
1 = The MAC will accept all frames regardless of type (Normal vs. Control)
0 = The received Control frames are ignored
bit 0
RXENABLE: MAC Receive Enable bit
1 = Enable the MAC receiving of frames
0 = Disable the MAC receiving of frames
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
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PIC32MX5XX/6XX/7XX
REGISTER 25-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
25/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
—
EXCESS
DFR
BPNOBK
OFF
NOBK
OFF
—
—
LONGPRE
PUREPRE
R/W-1
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
AUTO
PAD(1,2)
VLAN
PAD(1,2)
PAD
ENABLE(1,3)
CRC
ENABLE
DELAYCRC HUGEFRM LENGTHCK FULLDPLX
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14
EXCESSDER: Excess Defer bit
1 = The MAC will defer to carrier indefinitely as per the Standard
0 = The MAC will abort when the excessive deferral limit is reached
bit 13
BPNOBKOFF: Backpressure/No Backoff bit
1 = The MAC after incidentally causing a collision during backpressure will immediately retransmit without
backoff reducing the chance of further collisions and ensuring transmit packets get sent
0 = The MAC will not remove the backoff
bit 12
NOBKOFF: No Backoff bit
1 = Following a collision, the MAC will immediately retransmit rather than using the Binary Exponential Backoff algorithm as specified in the Standard
0 = Following a collision, the MAC will use the Binary Exponential Backoff algorithm
bit 11-10 Unimplemented: Read as ‘0’
bit 9
LONGPRE: Long Preamble Enforcement bit
1 = The MAC only allows receive packets which contain preamble fields less than 12 bytes in length
0 = The MAC allows any length preamble as per the Standard
bit 8
PUREPRE: Pure Preamble Enforcement bit
1 = The MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with
errors in its preamble is discarded
0 = The MAC does not perform any preamble checking
bit 7
AUTOPAD: Automatic Detect Pad Enable bit(1,2)
1 = The MAC will automatically detect the type of frame, either tagged or untagged, by comparing the two
octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly
0 = The MAC does not perform automatic detection
Note 1:
2:
3:
Note:
Table 25-6 provides a description of the pad function based on the configuration of this register.
This bit is ignored if the PADENABLE bit is cleared.
This bit is used in conjunction with the AUTOPAD and VLANPAD bits.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware
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PIC32MX5XX/6XX/7XX
REGISTER 25-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER
bit 6
VLANPAD: VLAN Pad Enable bit(1,2)
1 = The MAC will pad all short frames to 64 bytes and append a valid CRC
0 = The MAC does not perform padding of short frames
bit 5
PADENABLE: Pad/CRC Enable bit(1,3)
1 = The MAC will pad all short frames
0 = The frames presented to the MAC have a valid length
bit 4
CRCENABLE: CRC Enable1 bit
1 = The MAC will append a CRC to every frame whether padding was required or not. Must be set if the
PADENABLE bit is set.
0 = The frames presented to the MAC have a valid CRC
bit 3
DELAYCRC: Delayed CRC bit
This bit determines the number of bytes, if any, of proprietary header information that exist on the front of the
IEEE 802.3 frames.
1 = Four bytes of header (ignored by the CRC function)
0 = No proprietary header
bit 2
HUGEFRM: Huge Frame enable bit
1 = Frames of any length are transmitted and received
0 = Huge frames are not allowed for receive or transmit
bit 1
LENGTHCK: Frame Length checking bit
1 = Both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field
represents a length then the check is performed. Mismatches are reported on the transmit/receive
statistics vector.
0 = Length/Type field check is not performed
bit 0
FULLDPLX: Full-Duplex Operation bit
1 = The MAC operates in Full-Duplex mode
0 = The MAC operates in Half-Duplex mode
Note 1:
2:
3:
Note:
Table 25-6 provides a description of the pad function based on the configuration of this register.
This bit is ignored if the PADENABLE bit is cleared.
This bit is used in conjunction with the AUTOPAD and VLANPAD bits.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware
TABLE 25-6:
PAD OPERATION
Type
AUTOPAD
VLANPAD
PADENABLE
Any
x
x
0
No pad, check CRC
Any
0
0
1
Pad to 60 Bytes, append CRC
Any
x
1
1
Pad to 64 Bytes, append CRC
Any
1
0
1
If untagged: Pad to 60 Bytes, append CRC
If VLAN tagged: Pad to 64 Bytes, append CRC
DS60001156K-page 312
Action
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 25-25: EMAC1IPGT: ETHERNET CONTROLLER MAC BACK-TO-BACK INTERPACKET
GAP REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
—
B2BIPKTGP
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-7
Unimplemented: Read as ‘0’
bit 6-0
B2BIPKTGP: Back-to-Back Interpacket Gap bits
This is a programmable field representing the nibble time offset of the minimum possible period between
the end of any transmitted packet, to the beginning of the next. In Full-Duplex mode, the register value
should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the
desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6 µs (in 10 Mbps). In Half-Duplex mode, the recommended setting is 0x12 (18d), which also represents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6
µs (in 10 Mbps).
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
2009-2019 Microchip Technology Inc.
DS60001156K-page 313
PIC32MX5XX/6XX/7XX
REGISTER 25-26: EMAC1IPGR: ETHERNET CONTROLLER MAC NON-BACK-TO-BACK
INTERPACKET GAP REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-0
—
U-0
NB2BIPKTGP1
—
R/W-0
NB2BIPKTGP2
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-15
Unimplemented: Read as ‘0’
bit 14-8
NB2BIPKTGP1: Non-Back-to-Back Interpacket Gap Part 1 bits
This is a programmable field representing the optional carrierSense window referenced in section
4.2.3.2.1 “Deference” of the IEEE 80.23 Specification. If the carrier is detected during the timing of IPGR1,
the MAC defers to the carrier. If, however, the carrier comes after IPGR1, the MAC continues timing IPGR2
and transmits, knowingly causing a collision, thus ensuring fair access to the medium. Its range of values
is 0x0 to IPGR2. Its recommend value is 0xC (12d).
bit 7
Unimplemented: Read as ‘0’
bit 6-0
NB2BIPKTGP2: Non-Back-to-Back Interpacket Gap Part 2 bits
This is a programmable field representing the non-back-to-back Inter-Packet-Gap. Its recommended value
is 0x12 (18d), which represents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6 µs (in 10 Mbps).
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
DS60001156K-page 314
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 25-27: EMAC1CLRT: ETHERNET CONTROLLER MAC COLLISION WINDOW/RETRY
LIMIT REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-1
R/W-1
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U-0
U-0
U-0
U-0
CWINDOW
—
—
—
—
R/W-1
R/W-1
RETX
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13-8
CWINDOW: Collision Window bits
This is a programmable field representing the slot time or collision window during which collisions occur in
properly configured networks. Since the collision window starts at the beginning of transmission, the preamble and SFD is included. Its default of 0x37 (55d) corresponds to the count of frame bytes at the end of
the window.
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
RETX: Retransmission Maximum bits
This is a programmable field specifying the number of retransmission attempts following a collision before
aborting the packet due to excessive collisions. The Standard specifies the maximum number of attempts
(attemptLimit) to be 0xF (15d). Its default is ‘0xF’.
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
2009-2019 Microchip Technology Inc.
DS60001156K-page 315
PIC32MX5XX/6XX/7XX
REGISTER 25-28: EMAC1MAXF: ETHERNET CONTROLLER MAC MAXIMUM FRAME LENGTH
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
MACMAXF(1)
R/W-1
R/W-1
R/W-1
R/W-0
R/W-1
MACMAXF(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
MACMAXF: Maximum Frame Length bits(1)
These bits reset to 0x05EE, which represents a maximum receive frame of 1518 octets. An untagged
maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If
a shorter/longer maximum length restriction is desired, program this 16-bit field.
Note 1:
If a proprietary header is allowed, this bit should be adjusted accordingly. For example, if 4-byte headers
are prepended to frames, MACMAXF could be set to 1527 octets. This would allow the maximum VLAN
tagged frame plus the 4-byte header.
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
DS60001156K-page 316
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 25-29: EMAC1SUPP: ETHERNET CONTROLLER MAC PHY SUPPORT REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4
Bit
27/19/11/3
Bit
Bit
26/18/10/2 25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
U-0
U-0
R/W-0
—
—
—
—
RESETRMII(1)
—
—
SPEEDRMII(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-12
Unimplemented: Read as ‘0’
bit 11
RESETRMII: Reset RMII Logic bit(1)
1 = Reset the MAC RMII module
0 = Normal operation.
bit 10-9
Unimplemented: Read as ‘0’
bit 8
SPEEDRMII: RMII Speed bit(1)
This bit configures the Reduced MII logic for the current operating speed.
1 = RMII is running at 100 Mbps
0 = RMII is running at 10 Mbps
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
Note:
x = Bit is unknown
This bit is only used for the RMII module.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
2009-2019 Microchip Technology Inc.
DS60001156K-page 317
PIC32MX5XX/6XX/7XX
REGISTER 25-30: EMAC1TEST: ETHERNET CONTROLLER MAC TEST REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
TESTBP
TESTPAUSE(1) SHRTQNTA(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-3 Unimplemented: Read as ‘0’
bit 2
TESTBP: Test Backpressure bit
1 = The MAC will assert backpressure on the link. Backpressure causes preamble to be transmitted, raising
carrier sense. A transmit packet from the system will be sent during backpressure.
0 = Normal operation
bit 1
TESTPAUSE: Test PAUSE bit(1)
1 = The MAC Control sub-layer will inhibit transmissions, just as if a PAUSE Receive Control frame with a
non-zero pause time parameter was received
0 = Normal operation
bit 0
SHRTQNTA: Shortcut PAUSE Quanta bit(1)
1 = The MAC reduces the effective PAUSE Quanta from 64 byte-times to 1 byte-time
0 = Normal operation
Note 1:
Note:
This bit is only for testing purposes.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
DS60001156K-page 318
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 25-31: EMAC1MCFG: ETHERNET CONTROLLER MAC MII MANAGEMENT
CONFIGURATION REGISTER
Bit
Range
Bit
31/23/15/7
U-0
31:24
23:16
15:8
Bit
Bit
30/22/14/6 29/21/13/5
U-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
RESETMGMT
—
—
—
—
—
—
—
U-0
U-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
NOPRE
SCANINC
7:0
Legend:
R = Readable bit
-n = Value at POR
CLKSEL(1)
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
RESETMGMT: Test Reset MII Management bit
1 = Reset the MII Management module
0 = Normal Operation
bit 14-6 Unimplemented: Read as ‘0’
bit 5-2
CLKSEL: MII Management Clock Select 1 bits(1)
These bits are used by the clock divide logic in creating the MII Management Clock (MDC), which the IEEE
802.3 Specification defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz.
bit 1
NOPRE: Suppress Preamble bit
1 = The MII Management will perform read/write cycles without the 32-bit preamble field. Some PHYs
support suppressed preamble
0 = Normal read/write cycles are performed
bit 0
SCANINC: Scan Increment bit
1 = The MII Management module will perform read cycles across a range of PHYs. The read cycles will start
from address 1 through the value set in EMAC1MADR
0 = Continuous reads of the same PHY
Note 1:
Note:
Table 25-7 provides a description of the clock divider encoding.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
TABLE 25-7:
MIIM CLOCK SELECTION
MIIM Clock Select
EMAC1MCFG
SYSCLK divided by 4
000x
SYSCLK divided by 6
0010
SYSCLK divided by 8
0011
SYSCLK divided by 10
0100
SYSCLK divided by 14
0101
SYSCLK divided by 20
0110
SYSCLK divided by 28
0111
SYSCLK divided by 40
1000
Undefined
Any other combination
2009-2019 Microchip Technology Inc.
DS60001156K-page 319
PIC32MX5XX/6XX/7XX
REGISTER 25-32: EMAC1MCMD: ETHERNET CONTROLLER MAC MII MANAGEMENT COMMAND
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
Bit
Bit
26/18/10/2 25/17/9/1 24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
SCAN
READ
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-2
Unimplemented: Read as ‘0’
bit 1
SCAN: MII Management Scan Mode bit
1 = The MII Management module will perform read cycles continuously (for example, useful for monitoring
the Link Fail)
0 = Normal Operation
bit 0
READ: MII Management Read Command bit
1 = The MII Management module will perform a single read cycle. The read data is returned in the
EMAC1MRDD register
0 = The MII Management module will perform a write cycle. The write data is taken from the EMAC1MWTD
register
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
DS60001156K-page 320
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 25-33: EMAC1MADR: ETHERNET CONTROLLER MAC MII MANAGEMENT ADDRESS
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
PHYADDR
R/W-0
REGADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ’0’
bit 12-8
PHYADDR: MII Management PHY Address bits
This field represents the 5-bit PHY Address field of Management cycles. Up to 31 PHYs can be addressed
(0 is reserved).
bit 7-5
Unimplemented: Read as ’0’
bit 4-0
REGADDR: MII Management Register Address bits
This field represents the 5-bit Register Address field of Management cycles. Up to 32 registers can be
accessed.
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
2009-2019 Microchip Technology Inc.
DS60001156K-page 321
PIC32MX5XX/6XX/7XX
REGISTER 25-34: EMAC1MWTD: ETHERNET CONTROLLER MAC MII MANAGEMENT WRITE
DATA REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MWTD
R/W-0
R/W-0
MWTD
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ’0’
bit 15-0
MWTD: MII Management Write Data bits
When written, a MII Management write cycle is performed using the 16-bit data and the pre-configured PHY
and Register addresses from the EMAC1MADR register.
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
REGISTER 25-35: EMAC1MRDD: ETHERNET CONTROLLER MAC MII MANAGEMENT READ DATA
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MRDD
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MRDD
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
Note:
MRDD: MII Management Read Data bits
Following a MII Management Read Cycle, the 16-bit data can be read from this location.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
DS60001156K-page 322
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 25-36: EMAC1MIND: ETHERNET CONTROLLER MAC MII MANAGEMENT INDICATORS
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
LINKFAIL
NOTVALID
SCAN
MIIMBUSY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3
LINKFAIL: Link Fail bit
When ‘1’ is returned - indicates link fail has occurred. This bit reflects the value last read from the PHY status
register.
bit 2
NOTVALID: MII Management Read Data Not Valid bit
When ‘1’ is returned - indicates an MII management read cycle has not completed and the Read Data is not
yet valid.
bit 1
SCAN: MII Management Scanning bit
When ‘1’ is returned - indicates a scan operation (continuous MII Management Read cycles) is in progress.
bit 0
MIIMBUSY: MII Management Busy bit
When ‘1’ is returned - indicates MII Management module is currently performing an MII Management Read
or Write cycle.
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
2009-2019 Microchip Technology Inc.
DS60001156K-page 323
PIC32MX5XX/6XX/7XX
REGISTER 25-37: EMAC1SA0: ETHERNET CONTROLLER MAC STATION ADDRESS 0 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
Bit
27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
R/W-P
R/W-P
R/W-P
R/W-P
—
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
STNADDR6
R/W-P
R/W-P
STNADDR5
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-8
STNADDR6: Station Address Octet 6 bits
These bits hold the sixth transmitted octet of the station address.
bit 7-0
STNADDR5: Station Address Octet 5 bits
These bits hold the fifth transmitted octet of the station address.
Note 1:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
This register is loaded at reset from the factory preprogrammed station address.
2:
DS60001156K-page 324
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 25-38: EMAC1SA1: ETHERNET CONTROLLER MAC STATION ADDRESS 1 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
STNADDR4
R/W-P
R/W-P
STNADDR3
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-8
STNADDR4: Station Address Octet 4 bits
These bits hold the fourth transmitted octet of the station address.
bit 7-0
STNADDR3: Station Address Octet 3 bits
These bits hold the third transmitted octet of the station address.
Note 1:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
This register is loaded at reset from the factory preprogrammed station address.
2:
2009-2019 Microchip Technology Inc.
DS60001156K-page 325
PIC32MX5XX/6XX/7XX
REGISTER 25-39: EMAC1SA2: ETHERNET CONTROLLER MAC STATION ADDRESS 2 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
R/W-P
R/W-P
R/W-P
R/W-P
—
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
STNADDR2
R/W-P
R/W-P
STNADDR1
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Reserved: Maintain as ‘0’; ignore read
bit 15-8
STNADDR2: Station Address Octet 2 bits
These bits hold the second transmitted octet of the station address.
bit 7-0
STNADDR1: Station Address Octet 1 bits
These bits hold the most significant (first transmitted) octet of the station address.
Note 1:
2:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
This register is loaded at reset from the factory preprogrammed station address.
DS60001156K-page 326
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
26.0
Note:
COMPARATOR
The Comparator module contains two comparators that
can be configured in a variety of ways.
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet,
refer
to
Section
19.
“Comparator” (DS60001110) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
Key features of the Comparator module include:
FIGURE 26-1:
• Selectable inputs available include:
- Analog inputs multiplexed with I/O pins
- On-chip internal absolute voltage reference (IVREF)
- Comparator voltage reference (CVREF)
• Outputs can be inverted
• Selectable interrupt generation
A block diagram of the Comparator module is
illustrated in Figure 26-1.
COMPARATOR MODULE BLOCK DIAGRAM
Comparator 1
CREF
ON
C1IN+(1)
CPOL
COUT (CM1CON)
C1OUT (CMSTAT)
CVREF(2)
C1OUT
CCH
C1
C1IN-
COE
C1IN+
C2IN+
IVREF(2)
Comparator 2
CREF
ON
C2IN+
CPOL
COUT (CM2CON)
C2OUT (CMSTAT)
CVREF(2)
C2OUT
CCH
C2
C2IN-
COE
C2IN+
C1IN+
IVREF(2)
Note 1:
2:
On devices with a USB module, and when the module is enabled, this pin is controlled by the USB module,
and therefore, is not available as a comparator input.
Internally connected. See Section 27.0 “Comparator Voltage Reference (CVREF)”.
2009-2019 Microchip Technology Inc.
DS60001156K-page 327
Control Registers
A000 CM1CON
A010 CM2CON
A060 CMSTAT
Legend:
Note 1:
COMPARATOR REGISTER MAP
31:16
15:0
31:16
15:0
31:16
15:0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
—
ON
—
COE
—
CPOL
—
—
—
—
—
—
—
—
—
COUT
—
ON
—
COE
—
CPOL
—
—
—
—
—
—
—
—
—
COUT
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
23/7
22/6
21/5
20/4
19/3
18/2
—
—
EVPOL
—
—
—
CREF
—
—
—
—
—
—
CCH
0000
00C3
—
—
EVPOL
—
—
—
CREF
—
—
—
—
—
—
CCH
0000
00C3
—
—
—
—
—
—
—
—
—
—
—
—
17/1
—
C2OUT
16/0
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF80_#)
TABLE 26-1:
—
C1OUT
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
PIC32MX5XX/6XX/7XX
DS60001156K-page 328
26.1
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 26-1:
Bit
Range
31:24
23:16
15:8
7:0
CMxCON: COMPARATOR ‘x’ CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
R/W-0
(1)
R/W-0
ON
COE
R/W-1
R/W-1
EVPOL
Legend:
R = Readable bit
-n = Value at POR
Bit
Bit
28/20/12/4 27/19/11/3
—
R/W-0
(2)
CPOL
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
R-0
COUT
—
—
—
—
U-0
R/W-0
U-0
U-0
R/W-1
—
CREF
—
—
W = Writable bit
‘1’ = Bit is set
R/W-1
CCH
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Comparator ON bit(1)
Clearing this bit does not affect the other bits in this register.
1 = Module is enabled. Setting this bit does not affect the other bits in this register
0 = Module is disabled and does not consume current.
bit 14
COE: Comparator Output Enable bit
1 = Comparator output is driven on the output CxOUT pin
0 = Comparator output is not driven on the output CxOUT pin
bit 13
CPOL: Comparator Output Inversion bit(2)
1 = Output is inverted
0 = Output is not inverted
bit 12-9 Unimplemented: Read as ‘0’
bit 8
COUT: Comparator Output bit
1 = Output of the Comparator is a ‘1’
0 = Output of the Comparator is a ‘0’
bit 7-6
EVPOL: Interrupt Event Polarity Select bits
11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
10 = Comparator interrupt is generated on a high-to-low transition of the comparator output
01 = Comparator interrupt is generated on a low-to-high transition of the comparator output
00 = Comparator interrupt generation is disabled
bit 5
Unimplemented: Read as ‘0’
bit 4
CREF: Comparator Positive Input Configure bit
1 = Comparator non-inverting input is connected to the internal CVREF
0 = Comparator non-inverting input is connected to the CXIN+ pin
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
CCH: Comparator Negative Input Select bits for Comparator
11 = Comparator inverting input is connected to the IVREF
10 = Comparator inverting input is connected to the C2IN+ pin for C1 and C1IN+ pin for C2
01 = Comparator inverting input is connected to the C1IN+ pin for C1 and C2IN+ pin for C2
00 = Comparator inverting input is connected to the C1IN- pin for C1 and C2IN- pin for C2
Note 1:
2:
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an
interrupt being generated on the opposite edge from the one selected by EVPOL.
2009-2019 Microchip Technology Inc.
DS60001156K-page 329
PIC32MX5XX/6XX/7XX
REGISTER 26-2:
Bit
Range
31:24
23:16
15:8
7:0
CMSTAT: COMPARATOR STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
—
—
R/W-0
U-0
U-0
U-0
U-0
U-0
SIDL
—
—
—
—
—
U-0
U-0
—
—
U-0
U-0
U-0
U-0
R-0
R-0
—
—
—
—
C2OUT
C1OUT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Control bit
1 = All Comparator modules are disabled while in Idle mode
0 = All Comparator modules continue to operate while in Idle mode
bit 12-2
Unimplemented: Read as ‘0’
bit 1
C2OUT: Comparator Output bit
1 = Output of Comparator 2 is a ‘1’
0 = Output of Comparator 2 is a ‘0’
bit 0
C1OUT: Comparator Output bit
1 = Output of Comparator 1 is a ‘1’
0 = Output of Comparator 1 is a ‘0’
DS60001156K-page 330
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
27.0
Note:
COMPARATOR VOLTAGE
REFERENCE (CVREF)
A block diagram of the module is illustrated in
Figure 27-1. The resistor ladder is segmented to
provide two ranges of voltage reference values and has
a power-down function to conserve power when the
reference is not being used. The module’s supply reference can be provided from either device VDD/VSS or an
external voltage reference. The CVREF output is available for the comparators and typically available for pin
output.
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To complement the information in this data sheet,
refer to Section 20. “Comparator Voltage
Reference (CVREF)” (DS60001109) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
Key features of the CVREF module include:
• High and low range selection
• Sixteen output levels available for each range
• Internally connected to comparators to conserve
device pins
• Output can be connected to a pin
The CVREF module is a 16-tap, resistor ladder network
that provides a selectable reference voltage. Although
its primary purpose is to provide a reference for the
analog comparators, it also may be used independently
of them.
FIGURE 27-1:
COMPARATOR VOLTAGE REFERENCE MODULE BLOCK DIAGRAM
BGSEL(1)
1.2V
IVREF
0.6V
VREFSEL(1)
VREF+
AVDD
CVRSS = 1
CVRSRC
CVREF
8R
CVRSS = 0
CVR
R
CVREN
R
R
16-to-1 MUX
R
16 Steps
R
CVREFOUT
CVROE (CVRCON)
R
R
CVRR
VREFAVSS
Note 1:
8R
CVRSS = 1
CVRSS = 0
This bit is not available on PIC32MX575/675/695/775/795 devices. On these devices CVREF is generated by the
Register network and IVREF is connected to 0.6V.
2009-2019 Microchip Technology Inc.
DS60001156K-page 331
Control Register
Virtual Address
(BF80_#)
TABLE 27-1:
Legend:
1:
2:
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
—
—
—
—
—
—
—
—
—
—
—
CVROE
—
—
—
—
VREFSEL(2)
BGSEL(2)
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
15:0
ON
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
CVRR
CVRSS
CVR
All Resets
Register
Name(1)
Bit Range
Bits
9800 CVRCON
Note
COMPARATOR VOLTAGE REFERENCE REGISTER MAP
0000
0100
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
These bits are not available on PIC32MX575/675/695/775/795 devices. On these devices, reset value for CVRCON is ‘0000’.
PIC32MX5XX/6XX/7XX
DS60001156K-page 332
27.1
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 27-1:
Bit
Range
31:24
23:16
15:8
7:0
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
(1)
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
VREFSEL(2)
R/W-1
(2)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CVROE
CVRR
CVRSS
ON
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
BGSEL
R/W-0
R/W-0
CVR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Comparator Voltage Reference On bit(1)
Setting or clearing this bit does not affect the other bits in this register.
1 = Module is enabled
0 = Module is disabled and does not consume current
bit 14-11 Unimplemented: Read as ‘0’
bit 10
VREFSEL: Voltage Reference Select bit(2)
1 = CVREF = VREF+
0 = CVREF is generated by the resistor network
bit 9-8
BGSEL: Band Gap Reference Source bits(2)
11 = IVREF = VREF+
10 = Reserved
01 = IVREF = 0.6V (nominal, default)
00 = IVREF = 1.2V (nominal)
bit 7
Unimplemented: Read as ‘0’
bit 6
CVROE: CVREFOUT Enable bit
1 = Voltage level is output on CVREFOUT pin
0 = Voltage level is disconnected from CVREFOUT pin
bit 5
CVRR: CVREF Range Selection bit
1 = 0 to 0.625 CVRSRC, with CVRSRC/24 step size
0 = 0.25 CVRSRC to 0.719 CVRSRC, with CVRSRC/32 step size
bit 4
CVRSS: CVREF Source Selection bit
1 = Comparator voltage reference source, CVRSRC = (VREF+) – (VREF-)
0 = Comparator voltage reference source, CVRSRC = AVDD – AVSS
bit 3-0
CVR: CVREF Value Selection 0 CVR 15 bits
When CVRR = 1:
CVREF = (CVR/24) (CVRSRC)
When CVRR = 0:
CVREF = 1/4 (CVRSRC) + (CVR/32) (CVRSRC)
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: These bits are not available on PIC32MX575/675/775/795 devices. On these devices, the reset value for
CVRON is ‘0000’.
2009-2019 Microchip Technology Inc.
DS60001156K-page 333
PIC32MX5XX/6XX/7XX
NOTES:
DS60001156K-page 334
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
28.0
Note:
POWER-SAVING FEATURES
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To complement the information in this data
sheet, refer to Section 10. “Power-Saving Features” (DS60001130) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
This section describes power-saving features for the
PIC32MX5XX/6XX/7XX family of devices. These
devices offer a total of nine methods and modes,
organized into two categories, that allow the user to
balance power consumption with device performance.
In all of the methods and modes described in this
section, power-saving is controlled by software.
28.1
Power-Saving with CPU Running
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency,
lowering the Peripheral Bus Clock (PBCLK) and by
individually disabling modules. These methods are
grouped into the following categories:
• FRC Run mode: the CPU is clocked from the FRC
clock source with or without postscalers.
• LPRC Run mode: the CPU is clocked from the
LPRC clock source.
• SOSC Run mode: the CPU is clocked from the
SOSC clock source.
In addition, the Peripheral Bus Scaling mode is available
where peripherals are clocked at the programmable
fraction of the CPU clock (SYSCLK).
28.2
CPU Halted Methods
The device supports two power-saving modes, Sleep
and Idle, both of which Halt the clock to the CPU. These
modes operate with all clock sources, as listed below:
• POSC Idle mode: the system clock is derived from
the POSC. The system clock source continues to
operate. Peripherals continue to operate, but can
optionally be individually disabled.
• FRC Idle mode: the system clock is derived from
the FRC with or without postscalers. Peripherals
continue to operate, but can optionally be
individually disabled.
2009-2019 Microchip Technology Inc.
• SOSC Idle mode: the system clock is derived from
the SOSC. Peripherals continue to operate, but
can optionally be individually disabled.
• LPRC Idle mode: the system clock is derived
from the LPRC. Peripherals continue to operate,
but can optionally be individually disabled. This is
the lowest power mode for the device with a clock
running.
• Sleep mode: the CPU, the system clock source
and any peripherals that operate from the system
clock source are Halted. Some peripherals can
operate in Sleep using specific clock sources.
This is the lowest power mode for the device.
28.3
Power-Saving Operation
Peripherals and the CPU can be halted or disabled to
further reduce power consumption.
28.3.1
SLEEP MODE
Sleep mode has the lowest power consumption of the
device power-saving operating modes. The CPU and
most peripherals are halted. Select peripherals can
continue to operate in Sleep mode and can be used to
wake the device from Sleep. See the individual
peripheral module sections for descriptions of
behavior in Sleep.
Sleep mode includes the following characteristics:
• The CPU is halted
• The system clock source is typically shutdown.
See Section 28.3.3 “Peripheral Bus Scaling
Method” for specific information.
• There can be a wake-up delay based on the
oscillator selection
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode
• The BOR circuit, if enabled, remains operative
during Sleep mode
• The WDT, if enabled, is not automatically cleared
prior to entering Sleep mode
• Some peripherals can continue to operate at
limited functionality in Sleep mode. These
peripherals include I/O pins that detect a change
in the input signal, WDT, ADC, UART and
peripherals that use an external clock input or the
internal LPRC oscillator (e.g., RTCC, Timer1 and
Input Capture).
• I/O pins continue to sink or source current in the
same manner as they do when the device is not in
Sleep
• Modules can be individually disabled by software
prior to entering Sleep in order to further reduce
consumption
DS60001156K-page 335
PIC32MX5XX/6XX/7XX
The processor will exit, or ‘wake-up’, from Sleep mode
on one of the following events:
• On any interrupt from an enabled source that is
operating in Sleep mode. The interrupt priority
must be greater than the current CPU priority.
• On any form of device Reset
• On a WDT time-out
If the interrupt priority is lower than or equal to the
current priority, the CPU will remain Halted, but the
PBCLK will start running and the device will enter into
Idle mode.
28.3.2
IDLE MODE
In Idle mode, the CPU is Halted but the System Clock
(SYSCLK) source is still enabled. This allows peripherals to continue operation when the CPU is Halted.
Peripherals can be individually configured to Halt when
entering Idle by setting their respective SIDL bit.
Latency, when exiting Idle mode, is very low due to the
CPU oscillator source remaining active.
Note 1: Changing the PBCLK divider ratio
requires recalculation of peripheral timing. For example, assume the UART is
configured for 9600 baud with a PB clock
ratio of 1:1 and a POSC of 8 MHz. When
the PB clock divisor of 1:2 is used, the
input frequency to the baud clock is cut in
half; therefore, the baud rate is reduced
to 1/2 its former value. Due to numeric
truncation in calculations (such as the
baud rate divisor), the actual baud rate
may be a tiny percentage different than
expected. For this reason, any timing calculation required for a peripheral should
be performed with the new PB clock frequency instead of scaling the previous
value based on a change in the PB divisor
ratio.
2: Oscillator start-up and PLL lock delays
are applied when switching to a clock
source that was disabled and that uses a
crystal and/or the PLL. For example,
assume the clock source is switched from
POSC to LPRC just prior to entering Sleep
in order to save power. No oscillator startup delay would be applied when exiting
Idle. However, when switching back to
POSC, the appropriate PLL and/or
oscillator start-up/lock delays would be
applied.
DS60001156K-page 336
The device enters Idle mode when the SLPEN bit
(OSCCON) is clear and a WAIT instruction is
executed.
The processor will wake or exit from Idle mode on the
following events:
• On any interrupt event for which the interrupt
source is enabled. The priority of the interrupt
event must be greater than the current priority of
the CPU. If the priority of the interrupt event is
lower than or equal to current priority of the CPU,
the CPU will remain Halted and the device will
remain in Idle mode.
• On any form of device Reset
• On a WDT time-out interrupt
28.3.3
PERIPHERAL BUS SCALING
METHOD
Most of the peripherals on the device are clocked using
the PBCLK. The Peripheral Bus (PB) can be scaled relative to the SYSCLK to minimize the dynamic power
consumed by the peripherals. The PBCLK divisor is controlled by PBDIV (OSCCON), allowing
SYSCLK to PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All
peripherals using PBCLK are affected when the divisor
is changed. Peripherals such as USB, interrupt controller, DMA, bus matrix and prefetch cache are clocked
directly from SYSCLK. As a result, they are not affected
by PBCLK divisor changes.
Changing the PBCLK divisor affects:
• The CPU to peripheral access latency. The CPU
has to wait for next PBCLK edge for a read to
complete. In 1:8 mode, this results in a latency of
one to seven SYSCLKs.
• The power consumption of the peripherals. Power
consumption is directly proportional to the frequency at which the peripherals are clocked. The
greater the divisor, the lower the power consumed
by the peripherals.
To minimize dynamic power, the PB divisor should be
chosen to run the peripherals at the lowest frequency
that provides acceptable system performance. When
selecting a PBCLK divider, peripheral clock requirements, such as baud rate accuracy, should be taken
into account. For example, the UART peripheral may
not be able to achieve all baud rate values at some
PBCLK divider depending on the SYSCLK value.
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
29.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 33. “Programming
and Diagnostics” (DS60001129) in the
“PIC32 Family Reference Manual”, which
are available from the Microchip web site
(www.microchip.com/PIC32).
The PIC32MX5XX/6XX/7XX family of devices include
several features intended to maximize application
flexibility and reliability and minimize cost through
elimination of external components. Key features
include:
•
•
•
•
Flexible device configuration
Watchdog Timer (WDT)
Joint Test Action Group (JTAG) interface
In-Circuit Serial Programming™ (ICSP™)
29.1
Configuration Bits
The Configuration bits can be programmed using the
following registers to select various device
configurations.
•
•
•
•
•
DEVCFG0: Device Configuration Word 0
DEVCFG1: Device Configuration Word 1
DEVCFG2: Device Configuration Word 2
DEVCFG3: Device Configuration Word 3
DEVID: Device and Revision ID Register
2009-2019 Microchip Technology Inc.
DS60001156K-page 337
2FF4 DEVCFG2
2FF8 DEVCFG1
2FFC DEVCFG0
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
—
—
—
FCANIO
FETHIO
FMIIEN
—
—
—
—
—
FSRSSEL
—
—
—
—
FPLLODIV
xxxx
—
FPLLIDIV
xxxx
31:16 FVBUSONIO FUSBIDIO
15:0
18/2
17/1
16/0
xxxx
USERID
31:16
—
—
—
—
—
15:0
UPLLEN
—
—
—
—
31:16
—
—
—
—
—
—
15:0
FCKSM
FPBDIV
—
OSCIOFNC
31:16
—
—
—
—
—
—
—
—
15:0
—
CP
PWP
—
—
—
—
UPLLIDIV
—
xxxx
—
—
FPLLMUL
FWDTEN
—
—
IESO
—
FSOSCEN
—
BWP
—
—
—
—
—
—
—
—
—
ICESEL
—
19/3
18/2
17/1
POSCMOD
WDTPS
—
xxxx
FNOSC
xxxx
PWP
xxxx
DEBUG
xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Virtual Address
(BF80_#)
Register
Name
TABLE 29-2:
F200
DDPCON
F220
DEVID
DEVICE ID, REVISION, AND CONFIGURATION SUMMARY
SYSKEY
2009-2019 Microchip Technology Inc.
Legend:
Note
1:
Bit Range
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
JTAGEN
TROEN
—
TDOEN
0008
31:16
15:0
31:16
15:0
VER
DEVID
16/0
All Resets(1)
Legend:
31/15
All Resets
Bit Range
Register
Name
Virtual Address
(BFC0_#)
Bits
2FF0 DEVCFG3
F230
DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
xxxx
DEVID
xxxx
SYSKEY
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset values are dependent on the device variant. Refer to “PIC32MX5XX/6XX/7XX Family Silicon Errata and Data Sheet Clarification” (DS80000480) for more information.
0000
PIC32MX5XX/6XX/7XX
DS60001156K-page 338
TABLE 29-1:
PIC32MX5XX/6XX/7XX
REGISTER 29-1:
Bit
Range
DEVCFG0: DEVICE CONFIGURATION WORD 0
Bit
31/23/15/7
31:24
23:16
15:8
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
26/18/10/2
Bit
25/17/9/1
r-0
r-1
r-1
R/P
r-1
r-1
r-1
R/P
—
—
CP
—
—
—
BWP
r-1
r-1
r-1
r-1
R/P
R/P
R/P
R/P
r-1
r-1
r-1
r-1
—
—
—
—
R/P
R/P
—
—
—
—
R/P
R/P
R/P
R/P
PWP
r-1
r-1
r-1
r-1
R/P
r-1
—
—
—
—
ICESEL
—
DEBUG
Legend:
r = Reserved bit
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
Bit
24/16/8/0
—
PWP
7:0
Bit
27/19/11/3
x = Bit is unknown
Reserved: Write ‘0’
bit 30-29 Reserved: Write ‘1’
bit 28
CP: Code-Protect bit
Prevents boot and program Flash memory from being read or modified by an external programming device.
1 = Protection is disabled
0 = Protection is enabled
bit 27-25 Reserved: Write ‘1’
bit 24
BWP: Boot Flash Write-Protect bit
Prevents boot Flash memory from being modified during code execution.
1 = Boot Flash is writable
0 = Boot Flash is not writable
bit 23-20 Reserved: Write ‘1’
bit 19-12 PWP: Program Flash Write-Protect bits
Prevents selected program Flash memory pages from being modified during code execution. The PWP bits
represent the 1’s complement of the number of write-protected program Flash memory pages.
11111111 = Disabled
11111110 = 0xBD00_0FFF
11111101 = 0xBD00_1FFF
11111100 = 0xBD00_2FFF
11111011 = 0xBD00_3FFF
11111010 = 0xBD00_4FFF
11111001 = 0xBD00_5FFF
11111000 = 0xBD00_6FFF
11110111 = 0xBD00_7FFF
11110110 = 0xBD00_8FFF
11110101 = 0xBD00_9FFF
11110100 = 0xBD00_AFFF
11110011 = 0xBD00_BFFF
11110010 = 0xBD00_CFFF
11110001 = 0xBD00_DFFF
11110000 = 0xBD00_EFFF
11101111 = 0xBD00_FFFF
•
•
•
01111111 = 0xBD07_FFFF
bit 11-4
Reserved: Write ‘1’
2009-2019 Microchip Technology Inc.
DS60001156K-page 339
PIC32MX5XX/6XX/7XX
REGISTER 29-1:
DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)
bit 3
ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit
1 = PGEC2/PGED2 pair is used
0 = PGEC1/PGED1 pair is used
bit 2
Reserved: Write ‘1’
bit 1-0
DEBUG: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)
11 = Debugger is disabled
10 = Debugger is enabled
01 = Reserved (same as ‘11’ setting)
00 = Reserved (same as ‘11’ setting)
DS60001156K-page 340
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 29-2:
Bit
Range
31:24
23:16
15:8
7:0
DEVCFG1: DEVICE CONFIGURATION WORD 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
R/P
r-1
r-1
R/P
R/P
R/P
R/P
R/P
R/P
r-1
R/P
R/P
R/P
FWDTEN
—
—
R/P
R/P
R/P
FCKSM
WDTPS
—
OSCIOFNC
R/P
r-1
R/P
r-1
r-1
R/P
IESO
—
FSOSCEN
—
—
Legend:
FPBDIV
r = Reserved bit
POSCMOD
R/P
R/P
FNOSC
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Reserved: Write ‘1’
bit 23
FWDTEN: Watchdog Timer Enable bit
1 = The WDT is enabled and cannot be disabled by software
0 = The WDT is not enabled; it can be enabled in software
bit 22-21 Reserved: Write ‘1’
bit 20-16 WDTPS: Watchdog Timer Postscale Select bits
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
All other combinations not shown result in operation = 10100
bit 15-14 FCKSM: Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
Note 1:
Do not disable the POSC (POSCMOD = 11) when using this oscillator source.
2009-2019 Microchip Technology Inc.
DS60001156K-page 341
PIC32MX5XX/6XX/7XX
REGISTER 29-2:
DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED)
bit 13-12 FPBDIV: Peripheral Bus Clock Divisor Default Value bits
11 = PBCLK is SYSCLK divided by 8
10 = PBCLK is SYSCLK divided by 4
01 = PBCLK is SYSCLK divided by 2
00 = PBCLK is SYSCLK divided by 1
bit 11
Reserved: Write ‘1’
bit 10
OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output is disabled
0 = CLKO output signal is active on the OSCO pin; the Primary Oscillator must be disabled or configured
for External Clock mode (EC) for the CLKO to be active (POSCMOD = 11 or 00)
bit 9-8
POSCMOD: Primary Oscillator Configuration bits
11 = Primary Oscillator is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = External Clock mode is selected
bit 7
IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled)
0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled)
bit 6
Reserved: Write ‘1’
bit 5
FSOSCEN: Secondary Oscillator Enable bit
1 = Enable the Secondary Oscillator
0 = Disable the Secondary Oscillator
bit 4-3
Reserved: Write ‘1’
bit 2-0
FNOSC: Oscillator Selection bits
111 = Fast RC Oscillator with divide-by-N (FRCDIV)
110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator (POSC) with PLL module (XT+PLL, HS+PLL, EC+PLL)
010 = Primary Oscillator (XT, HS, EC)(1)
001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)
000 = Fast RC Oscillator (FRC)
Note 1:
Do not disable the POSC (POSCMOD = 11) when using this oscillator source.
DS60001156K-page 342
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 29-3:
Bit
Range
31:24
23:16
15:8
7:0
DEVCFG2: DEVICE CONFIGURATION WORD 2
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
R/P
R/P
R/P
—
—
—
—
—
R/P
r-1
r-1
r-1
r-1
UPLLEN
—
—
—
—
r-1
R/P-1
R/P
R/P-1
r-1
—
FPLLMUL
FPLLODIV
R/P
R/P
R/P
UPLLIDIV
R/P
—
R/P
R/P
FPLLIDIV
Legend:
r = Reserved bit
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-19 Reserved: Write ‘1’
bit 18-16 FPLLODIV: PLL Output Divider bits
111 = PLL output divided by 256
110 = PLL output divided by 64
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 1
bit 15
UPLLEN: USB PLL Enable bit
1 = Disable and bypass USB PLL
0 = Enable USB PLL
bit 14-11 Reserved: Write ‘1’
bit 10-8
UPLLIDIV: USB PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
bit 7
Reserved: Write ‘1’
bit 6-4
FPLLMUL: PLL Multiplier bits
111 = 24x multiplier
110 = 21x multiplier
101 = 20x multiplier
100 = 19x multiplier
011 = 18x multiplier
010 = 17x multiplier
001 = 16x multiplier
000 = 15x multiplier
bit 3
Reserved: Write ‘1’
2009-2019 Microchip Technology Inc.
DS60001156K-page 343
PIC32MX5XX/6XX/7XX
REGISTER 29-3:
bit 2-0
DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED)
FPLLIDIV: PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
DS60001156K-page 344
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 29-4:
Bit
Range
31:24
DEVCFG3: DEVICE CONFIGURATION WORD 3
Bit
31/23/15/7
Bit
30/22/14/6
R/P
R/P
FVBUSONIO FUSBIDIO
23:16
15:8
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
r-1
r-1
R/P
R/P
R/P
—
—
—
FCANIO(1)
FETHIO(2)
FMIIEN(2)
R/P
R/P
R/P
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
R/P
R/P
R/P
R/P
R/P
FSRSSEL
R/P
R/P
R/P
R/P
R/P
R/P
USERID
R/P
7:0
R/P
R/P
R/P
R/P
USERID
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
P = Programmable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
FVBUSONIO: USB VBUSON Selection bit
1 = VBUSON pin is controlled by the USB module
0 = VBUSON pin is controlled by the port function
bit 30
FUSBIDIO: USB USBID Selection bit
1 = USBID pin is controlled by the USB module
0 = USBID pin is controlled by the port function
bit 29-27 Reserved: Write ‘1’
bit 26
FCANIO: CAN I/O Pin Selection bit(1)
1 = Default CAN I/O Pins
0 = Alternate CAN I/O Pins
bit 25
FETHIO: Ethernet I/O Pin Selection bit(2)
1 = Default Ethernet I/O Pins
0 = Alternate Ethernet I/O Pins
bit 24
FMIIEN: Ethernet MII Enable bit(2)
1 = MII is enabled
0 = RMII is enabled
bit 23-19 Reserved: Write ‘1’
bit 18-16 FSRSSEL: SRS Select bits
111 = Assign Interrupt Priority 7 to a shadow register set
110 = Assign Interrupt Priority 6 to a shadow register set
•
•
•
bit 15-0
Note 1:
2:
001 = Assign Interrupt Priority 1 to a shadow register set
000 = All interrupt priorities are assigned to a shadow register set
USERID: User ID bits
This is a 16-bit value that is user-defined and is readable via ICSP™ and JTAG.
This bit is Reserved and reads ‘1’ on PIC32MX664/675/695 devices.
This bit is Reserved and reads ‘1’ on PIC32MX534/564/575 devices.
2009-2019 Microchip Technology Inc.
DS60001156K-page 345
PIC32MX5XX/6XX/7XX
REGISTER 29-5:
Bit
Range
31:24
23:16
15:8
7:0
DEVID: DEVICE AND REVISION ID REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
R
R
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
R
R
R
R
R
R
R
(1)
VER
R
Bit
24/16/8/0
R
(1)
R
R
R
R
R
(1)
R
R
R
R
R
R
R
(1)
R
Bit
25/17/9/1
DEVID
DEVID
R
R
R
R
R
R
R
DEVID
R
DEVID(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 VER: Revision Identifier bits(1)
bit 27-0
DEVID: Device ID bits(1)
Note 1:
See the “PIC32 Flash Programming Specification” (DS60001145) for a list of Revision and Device ID values.
REGISTER 29-6:
Bit
Range
31:24
23:16
15:8
7:0
DDPCON: DEBUG DATA PORT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-1
R/W-0
U-0
R/W-0
—
—
—
—
JTAGEN
TROEN
—
TDOEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3
JTAGEN: JTAG Port Enable bit
1 = Enable the JTAG port
0 = Disable the JTAG port
bit 2
TROEN: Trace Output Enable bit
1 = Enable the trace port
0 = Disable the trace port
bit 1
Unimplemented: Read as ‘0’
bit 0
TDOEN: TDO Enable for 2-Wire JTAG
1 = 2-wire JTAG protocol uses TDO
0 = 2-wire JTAG protocol does not use TDO
DS60001156K-page 346
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
29.2
On-Chip Voltage Regulator
All PIC32MX5XX/6XX/7XX devices’ core and digital
logic are designed to operate at a nominal 1.8V. To
simplify system designs, most devices in the PIC32MX5XX/6XX/7XX family incorporate an on-chip regulator
providing the required core logic voltage from VDD.
A low-ESR capacitor (such as tantalum) must be
connected to the VCAP pin (see Figure 29-1). This
helps to maintain the stability of the regulator. The
recommended value for the filter capacitor is provided
in Section 32.1 “DC Characteristics”.
Note:
It is important that the low-ESR capacitor
is placed as close as possible to the VCAP
pin.
29.2.1
ON-CHIP REGULATOR AND POR
It takes a fixed delay for the on-chip regulator to generate
an output. During this time, designated as TPU, code
execution is disabled. TPU is applied every time the
device resumes operation after any power-down,
including Sleep mode.
29.2.2
ON-CHIP REGULATOR AND BOR
PIC32MX5XX/6XX/7XX devices also have a simple
brown-out capability. If the voltage supplied to the
regulator is inadequate to maintain a regulated level,
the regulator Reset circuitry will generate a Brown-out
Reset (BOR). This event is captured by the BOR flag
bit (RCON). The brown-out voltage levels are
specified in Section 32.1 “DC Characteristics”.
FIGURE 29-1:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
29.3
Programming and Diagnostics
PIC32MX5XX/6XX/7XX devices provide a complete
range of programming and diagnostic features that can
increase the flexibility of any application using them.
These features allow system designers to include:
• Simplified field programmability using two-wire
In-Circuit Serial Programming™ (ICSP™)
interfaces
• Debugging using ICSP
• Programming and debugging capabilities using
the EJTAG extension of JTAG
• JTAG boundary scan testing for device and board
diagnostics
PIC32 devices incorporate two programming and diagnostic modules, and a trace controller, that provide a
range of functions to the application developer.
FIGURE 29-2:
PGEC1
PGED1
ICSP™
Controller
PGEC2
PGED2
ICESEL
TDI
TDO
TCK
3.3V(1)
PIC32
VCAP
VSS
2:
These are typical operating voltages. Refer to
Section 32.1 “DC Characteristics” for the full
operating ranges of VDD.
It is important that the low-ESR capacitor is
placed as close as possible to the VCAP pin.
2009-2019 Microchip Technology Inc.
Core
JTAGEN DEBUG
TRCLK
TRD0
TRD1
TRD2
Note 1:
JTAG
Controller
TMS
VDD
CEFC(2)
(10 F typical)
PROGRAMMING,
DEBUGGING, AND TRACE
PORTS BLOCK DIAGRAM
Instruction Trace
Controller
(see Note 1)
TRD3
DEBUG
Note 1:
Trace is not available on 64-pin devices.
DS60001156K-page 347
PIC32MX5XX/6XX/7XX
NOTES:
DS60001156K-page 348
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
30.0
INSTRUCTION SET
The PIC32MX5XX/6XX/7XX family instruction set
complies with the MIPS32 Release 2 instruction set
architecture. The PIC32 device family does not support
the following features:
• Core Extend instructions
• Coprocessor 1 instructions
• Coprocessor 2 instructions
Note:
Refer to “MIPS32® Architecture for
Programmers Volume II: The MIPS32®
Instruction Set” at www.imgtec.com for
more information.
2009-2019 Microchip Technology Inc.
DS60001156K-page 349
PIC32MX5XX/6XX/7XX
NOTES:
DS60001156K-page 350
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
31.0
DEVELOPMENT SUPPORT
®
31.1
®
The PIC microcontrollers (MCU) and dsPIC digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2009-2019 Microchip Technology Inc.
DS60001156K-page 351
PIC32MX5XX/6XX/7XX
31.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
31.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
31.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
31.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS60001156K-page 352
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
31.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
31.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2009-2019 Microchip Technology Inc.
31.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
31.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
31.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
DS60001156K-page 353
PIC32MX5XX/6XX/7XX
31.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
31.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS60001156K-page 354
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
32.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC32MX5XX/6XX/7XX electrical characteristics. Additional information will be
provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC32MX5XX/6XX/7XX devices are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these or any other
conditions, above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings
(See Note 1)
Ambient temperature under bias............................................................................................................ .-40°C to +105°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)......................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 2.3V (Note 3)........................................ -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)........................................ -0.3V to +3.6V
Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V
Maximum current out of VSS pin(s) .......................................................................................................................300 mA
Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 2)....................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions,
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 32-2).
3: See the “Device Pin Tables” section for the 5V tolerant pins.
2009-2019 Microchip Technology Inc.
DS60001156K-page 355
PIC32MX5XX/6XX/7XX
32.1
DC Characteristics
TABLE 32-1:
OPERATING MIPS VS. VOLTAGE
Characteristic
DC5
DC5b
Note 1:
Max. Frequency
VDD Range
(in Volts)(1)
Temp. Range
(in °C)
PIC32MX5XX/6XX/7XX
2.3-3.6V
-40°C to +85°C
80 MHz
2.3-3.6V
-40°C to +105°C
80 MHz
Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device
Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to
parameter BO10 in Table 32-10 for BOR values.
TABLE 32-2:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min.
Typical
Max.
Unit
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
Operating Junction Temperature Range
TJ
-40
—
+140
°C
Operating Ambient Temperature Range
TA
-40
—
+105
°C
Industrial Temperature Devices
V-Temp Temperature Devices
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – S IOH)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
I/O Pin Power Dissipation:
I/O = S (({VDD – VOH} x IOH) + S (VOL x IOL))
Maximum Allowed Power Dissipation
TABLE 32-3:
THERMAL PACKAGING CHARACTERISTICS
Characteristics
Symbol Typical
Max.
Unit
See
Note
Package Thermal Resistance, 121-Pin TFBGA (10x10x1.1 mm)
JA
40
—
°C/W
1
Package Thermal Resistance, 100-Pin TQFP (14x14x1 mm)
JA
43
—
°C/W
1
Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm)
JA
43
—
°C/W
1
Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm)
JA
47
—
°C/W
1
Package Thermal Resistance, 64-Pin QFN (9x9x0.9 mm)
JA
28
—
°C/W
1
Package Thermal Resistance, 124-Pin VTLA (9x9x0.9 mm)
JA
21
—
°C/W
1
Note 1:
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
DS60001156K-page 356
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 32-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typical
Max.
Units
Conditions
Operating Voltage
Supply Voltage
2.3
—
3.6
V
—
DC10 VDD
DC12 VDR
RAM Data Retention Voltage(1)
1.75
—
—
V
—
DC16 VPOR
VDD Start Voltage to Ensure
1.75
—
2.1
V
—
Internal Power-on Reset Signal
VDD Rise Rate to Ensure
0.00005
—
0.115 V/s
—
DC17 SVDD
Internal Power-on Reset Signal
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device
Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to
parameter BO10 in Table 32-10 for BOR values.
2009-2019 Microchip Technology Inc.
DS60001156K-page 357
PIC32MX5XX/6XX/7XX
TABLE 32-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
DC CHARACTERISTICS
Param.
No.
Typical(3)
Max.
Units
Conditions
Operating Current (IDD)(1,2,4) for PIC32MX575/675/695/775/795 Family Devices
DC20
6
9
mA
DC20b
7
10
DC20a
4
—
DC21
37
40
DC21a
25
—
DC22
64
70
DC22a
61
—
DC23
85
98
90
120
DC23a
85
—
125
150
DC25a
Note 1:
2:
3:
4:
—
4 MHz
—
—
25 MHz
—
—
60 MHz
-40ºC,
+25ºC,
+85ºC
—
80 MHz
3.3V
LPRC (31 kHz)
+105ºC
Code executing from SRAM
mA
mA
mA
DC23b
Code executing from Flash
-40ºC,
+25ºC,
+85ºC
Code executing from Flash
Code executing from SRAM
Code executing from Flash
Code executing from SRAM
Code executing from Flash
—
+105ºC
µA
Code executing from SRAM
—
—
+25°C
A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
The test conditions for IDD measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU, program Flash, and SRAM data memory are operational, program Flash memory Wait
states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• CPU executing while(1) statement from Flash
• RTCC and JTAG are disabled
Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
All parameters are characterized, but only those parameters listed for 4 MHz and 80 MHz are tested at
3.3V in manufacturing.
DS60001156K-page 358
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 32-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
DC CHARACTERISTICS
Param.
No.
Typical(3)
Max.
Units
Conditions
Operating Current (IDD)(1,2) for PIC32MX534/564/664/764 Family Devices
DC20c
6
9
mA
DC20d
7
Code executing from Flash
10
2
—
Code executing from SRAM
DC21b
19
32
Code executing from Flash
DC21c
14
—
DC22b
31
50
29
—
DC23c
39
65
mA
mA
mA
DC23d
49
70
DC23e
39
—
DC25b
100
150
Note 1:
2:
3:
4:
—
4 MHz
—
—
25 MHz
(Note 4)
—
—
60 MHz
(Note 4)
-40ºC,
+25ºC,
+85ºC
—
80 MHz
3.3V
LPRC (31 kHz)
(Note 4)
+105ºC
DC20e
DC22c
-40ºC,
+25ºC,
+85ºC
Code executing from SRAM
Code executing from Flash
Code executing from SRAM
Code executing from Flash
—
+105ºC
µA
Code executing from SRAM
—
—
+25°C
A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
The test conditions for IDD measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU, program Flash, and SRAM data memory are operational, program Flash memory Wait
states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• CPU executing while(1) statement from Flash
• RTCC and JTAG are disabled
Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
All parameters are characterized, but only those parameters listed for 4 MHz and 80 MHz are tested at
3.3V in manufacturing.
2009-2019 Microchip Technology Inc.
DS60001156K-page 359
PIC32MX5XX/6XX/7XX
TABLE 32-6:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
DC CHARACTERISTICS
Parameter
No.
Typical(2)
Max.
Units
Conditions
Idle Current (IIDLE)(1,3) for PIC32MX575/675/695/775/795 Family Devices
DC30
4.5
6.5
DC30b
5
7
DC31
13
15
mA
DC32
28
30
mA
mA
-40ºC, +25ºC, +85ºC
—
4 MHz
-40ºC, +25ºC, +85ºC
—
25 MHz
-40ºC, +25ºC, +85ºC
—
60 MHz
—
80 MHz
+105°C
DC33
36
42
mA
-40ºC, +25ºC, +85ºC
DC33b
39
45
mA
+105°C
DC34
40
-40°C
DC34a
75
+25°C
DC34b
—
DC34c
800
µA
1000
+85°C
+105°C
DC35
35
-40°C
DC35a
65
+25°C
DC35b
600
DC35c
800
—
µA
+85°C
43
-40°C
DC36a
106
+25°C
—
DC36c
Note 1:
2:
3:
4:
3.3V
LPRC (31 kHz)
+105°C
DC36
DC36b
2.3V
800
1000
µA
+85°C
3.6V
+105°C
The test conditions for IIDLE current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Idle mode, program Flash memory Wait states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
This parameter is characterized, but not tested in manufacturing.
All parameters are characterized, but only those parameters listed for 4 MHz and 80 MHz are tested at
3.3V in manufacturing.
DS60001156K-page 360
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 32-6:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
DC CHARACTERISTICS
Parameter
No.
Typical(2)
Max.
Units
Conditions
Idle Current (IIDLE)(1) for PIC32MX534/564/664/764 Family Devices
DC30a
1.5
5
DC30c
3.5
6
DC31a
7
11
DC32a
13
20
DC33a
17
25
DC33c
20
27
-40ºC, +25ºC, +85ºC
mA
mA
mA
—
4 MHz
-40ºC, +25ºC, +85ºC
—
25 MHz (Note 3)
-40ºC, +25ºC, +85ºC
—
60 MHz (Note 3)
—
80 MHz
+105ºC
-40ºC, +25ºC, +85ºC
+105ºC
DC34c
40
-40°C
DC34d
75
+25°C
DC34e
—
DC34f
800
µA
1000
+85°C
+105ºC
DC35c
30
-40°C
DC35d
55
+25°C
DC35e
230
DC35f
800
DC36c
DC36d
DC36e
DC36f
Note 1:
2:
3:
4:
—
µA
+85°C
3.3V
LPRC (31 kHz)
(Note 3)
+105ºC
43
—
2.3V
106
800
1000
-40°C
µA
+25°C
+85°C
3.6V
+105ºC
The test conditions for IIDLE current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Idle mode, program Flash memory Wait states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
This parameter is characterized, but not tested in manufacturing.
All parameters are characterized, but only those parameters listed for 4 MHz and 80 MHz are tested at
3.3V in manufacturing.
2009-2019 Microchip Technology Inc.
DS60001156K-page 361
PIC32MX5XX/6XX/7XX
TABLE 32-7:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC CHARACTERISTICS
Param.
Typical(2)
No.
Max.
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Units
Conditions
Power-Down Current (IPD)(1) for PIC32MX575/675/695/775/795 Family Devices
DC40
10
40
-40°C
DC40a
36
100
+25°C
DC40b
400
720
+85°C
DC40h
900
1800
+105°C
DC40c
41
120
DC40d
22
80
A
+25°C
2.3V
Base Power-Down Current (Note 6)
3.3V
Base Power-Down Current
3.6V
Base Power-Down Current (Note 6)
-40°C
DC40e
42
120
+25°C
DC40g
315
400(5)
+70°C
DC40f
410
800
+85°C
DC40i
1000
2000
+105°C
Module Differential Current for PIC32MX575/675/695/775/795 Family Devices
DC41
—
10
DC41a
5
—
DC41b
—
20
DC42
—
40
DC42a
23
—
A
A
—
—
2.3V
Watchdog Timer Current: IWDT (Notes 3,6)
3.3V
Watchdog Timer Current: IWDT (Note 3)
3.6V
Watchdog Timer Current: IWDT (Note 3,6)
2.3V
RTCC + Timer1 w/32 kHz Crystal: IRTCC (Notes 3,6)
3.3V
RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3)
DC42b
—
50
3.6V
RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3,6)
DC43
—
1300
2.5V
ADC: IADC (Notes 3,4,6)
DC43a
1100
—
DC43b
—
1300
Note 1:
2:
3:
4:
5:
6:
A
—
3.3V
ADC: IADC (Notes 3,4)
3.6V
ADC: IADC (Notes 3,4,6)
The test conditions for IPD current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, program Flash memory Wait states = 111, Program Cache and Prefetch are
disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
Data is characterized at +70°C and not tested. Parameter is for design guidance only.
This parameter is characterized, but not tested in manufacturing.
DS60001156K-page 362
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 32-7:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)
DC CHARACTERISTICS
Param.
Typical(2)
No.
Max.
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Units
Conditions
Power-Down Current (IPD)(1) for PIC32MX534/564/664/764 Family Devices
DC40g
12
40
-40°C
DC40h
20
120
+25°C
DC40i
210
600
+85°C
DC40o
400
1000
+105°C
DC40j
20
120
DC40k
15
80
A
+25°C
2.3V
Base Power-Down Current (Note 6)
3.3V
Base Power-Down Current
3.6V
Base Power-Down Current
-40°C
DC40l
20
120
DC40m
113
350(5)
+25°C
+70°C
DC40n
220
650
+85°C
DC40p
500
1000
+105°C
Module Differential Current for PIC32MX534/564/664/764 Family Devices
DC41c
—
10
2.5V
Watchdog Timer Current: IWDT (Notes 3,6)
DC41d
5
—
3.3V
Watchdog Timer Current: IWDT (Note 3)
DC41e
—
20
3.6V
Watchdog Timer Current: IWDT (Note 3)
DC42c
—
40
2.5V
RTCC + Timer1 w/32 kHz Crystal: IRTCC (Notes 3,6)
DC42d
23
—
3.3V
RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3)
A
A
—
—
DC42e
—
50
3.6V
RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3)
DC43c
—
1300
2.5V
ADC: IADC (Notes 3,4,6)
DC43d
1100
—
DC43e
—
1300
Note 1:
2:
3:
4:
5:
6:
A
—
3.3V
ADC: IADC (Notes 3,4)
3.6V
ADC: IADC (Notes 3,4)
The test conditions for IPD current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, program Flash memory Wait states = 111, Program Cache and Prefetch are
disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
Data is characterized at +70°C and not tested. Parameter is for design guidance only.
This parameter is characterized, but not tested in manufacturing.
2009-2019 Microchip Technology Inc.
DS60001156K-page 363
PIC32MX5XX/6XX/7XX
TABLE 32-8:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Param.
Symbol
No.
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Characteristics
Min.
Typical(1)
Max.
Units
DI15
DI16
DI17
DI18
Input Low Voltage
I/O Pins:
with TTL Buffer
with Schmitt Trigger Buffer
MCLR(2)
OSC1 (XT mode)
OSC1 (HS mode)
SDAx, SCLx
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
0.15 VDD
0.2 VDD
0.2 VDD
0.2 VDD
0.2 VDD
0.3 VDD
V
V
V
V
V
V
DI19
SDAx, SCLx
VSS
—
0.8
V
0.65 VDD
0.25 VDD + 0.8V
—
—
VDD
5.5
V
V
0.65 VDD
0.65 VDD
—
—
5.5
5.5
V
V
2.1
—
5.5
V
VIL
DI10
VIH
DI28
Input High Voltage
I/O Pins not 5V-tolerant(5)
I/O Pins 5V-tolerant with
PMP(5)
I/O Pins 5V-tolerant(5)
SDAx, SCLx
DI29
SDAx, SCLx
DI20
Conditions
(Note 4)
(Note 4)
SMBus disabled
(Note 4)
SMBus enabled
(Note 4)
(Note 4,6)
(Note 4,6)
SMBus disabled
(Note 4,6)
SMBus enabled,
2.3V VPIN 5.5
(Note 4,6)
VDD = 3.3V, VPIN = VSS
(Note 3,6)
VDD = 3.3V, VPIN = VDD
Change Notification
—
—
-50
A
Pull-up Current
DI31
ICNPD
Change Notification
—
50
—
µA
Pull-down Current(4)
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: This parameter is characterized, but not tested in manufacturing.
5: See the “Device Pin Tables” section for the 5V-tolerant pins.
6: The VIH specification is only in relation to externally applied inputs and not with respect to the user-selectable pull-ups. Externally applied high impedance or open drain input signals utilizing the PIC32 internal pullups are guaranteed to be recognized as a logic “high” internally to the PIC32 device, provided that the
external load does not exceed the maximum value of ICNPU.
7: VIL source < (VSS - 0.3). Characterized but not tested.
8: VIH source > (VDD + 0.3) for non-5V tolerant pins only.
9: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any
“positive” input injection current.
10: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD +
0.3) or VIL source < (VSS - 0.3)).
11: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. If Note 7, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 8, IICH = ((IICH source - (VDD + 0.3)) / RS).
RS = Resistance between input source voltage and device pin. If (VSS - 0.3) VSOURCE (VDD + 0.3), injection current = 0.
DI30
ICNPU
DS60001156K-page 364
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 32-8:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
DC CHARACTERISTICS
Param.
Symbol
No.
IIL
Characteristics
Min.
Typical(1)
Max.
Units
Conditions
(3)
Input Leakage Current
I/O Ports
VSS VPIN VDD,
Pin at high-impedance
DI51
Analog Input Pins
—
—
+1
A VSS VPIN VDD,
Pin at high-impedance
DI55
MCLR(2)
—
—
+1
A VSS VPIN VDD
DI56
OSC1
—
—
+1
A VSS VPIN VDD,
XT and HS modes
This parameter applies
to all pins, with the
Input Low Injection
exception of RB10.
(7,10)
0
—
-5
DI60a IICL
mA
Current
Maximum IICH current
for this exception is
0 mA.
This parameter applies
to all pins, with the
exception of all 5V tolerInput High Injection
DI60b IICH
0
—
+5(8,9,10) mA ant pins, SOSCI, and
Current
RB10. Maximum IICH
current for these
exceptions is 0 mA.
Total Input Injection
-20(11)
—
+20(11)
mA Absolute instantaneous
DI60c IICT
Current (sum of all I/O
sum of all ± input
and control pins)
injection currents from
all I/O pins
( | IICL + | IICH | ) IICT
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: This parameter is characterized, but not tested in manufacturing.
5: See the “Device Pin Tables” section for the 5V-tolerant pins.
6: The VIH specification is only in relation to externally applied inputs and not with respect to the user-selectable pull-ups. Externally applied high impedance or open drain input signals utilizing the PIC32 internal pullups are guaranteed to be recognized as a logic “high” internally to the PIC32 device, provided that the
external load does not exceed the maximum value of ICNPU.
7: VIL source < (VSS - 0.3). Characterized but not tested.
8: VIH source > (VDD + 0.3) for non-5V tolerant pins only.
9: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any
“positive” input injection current.
10: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD +
0.3) or VIL source < (VSS - 0.3)).
11: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. If Note 7, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 8, IICH = ((IICH source - (VDD + 0.3)) / RS).
RS = Resistance between input source voltage and device pin. If (VSS - 0.3) VSOURCE (VDD + 0.3), injection current = 0.
DI50
2009-2019 Microchip Technology Inc.
—
—
+1
A
DS60001156K-page 365
PIC32MX5XX/6XX/7XX
TABLE 32-9:
DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
DC CHARACTERISTICS
Param. Symbol
DO10
DO20
VOL
VOH
DO20A VOH1
Note 1:
2:
3:
Characteristic
Output Low Voltage
I/O Pins:
4x Sink Driver Pins - All I/O
output pins not defined as 8x
Sink Driver pins
Output Low Voltage
I/O Pins:
8x Sink Driver Pins - RC15
Output High Voltage
I/O Pins:
4x Source Driver Pins - All I/O
output pins not defined as 8x
Source Driver pins
Output High Voltage
I/O Pins:
8x Source Driver Pins - RC15
Output High Voltage
I/O Pins:
4x Source Driver Pins - All I/O
output pins not defined as 8x
Sink Driver pins
Output High Voltage
I/O Pins:
8x Source Driver Pins - RC15
Min.
Typ.
Max.
Units
Conditions
—
—
0.4
V
IOL 10 mA, VDD = 3.3V
—
—
0.4
V
IOL 15 mA, VDD = 3.3V
2.4
—
—
V
IOH -10 mA, VDD = 3.3V
2.4
—
—
V
IOH -15 mA, VDD = 3.3V
1.5(1)
—
—
2.0(1)
—
—
3.0(1)
—
—
IOH -7 mA, VDD = 3.3V
(1)
1.5
—
—
IOH -22 mA, VDD = 3.3V
2.0(1)
—
—
3.0(1)
—
—
IOH -14 mA, VDD = 3.3V
IOH -12 mA, VDD = 3.3V
V
IOH -18 mA, VDD = 3.3V
V
IOH -10 mA, VDD = 3.3V
Parameters are characterized, but not tested.
This driver pin only applies to devices with less than 64 pins.
This driver pin only applies to devices with 64 pins.
TABLE 32-10: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
DC CHARACTERISTICS
Param.
No.
Characteristics
Min.(1)
Typical
Max.
Units
Conditions
BOR Event on VDD transition
high-to-low (Note 2)
2.0
—
2.3
V
—
Symbol
BO10
VBOR
Note 1:
2:
Parameters are for design guidance only and are not tested in manufacturing.
Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device
Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN.
DS60001156K-page 366
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PIC32MX5XX/6XX/7XX
TABLE 32-11: DC CHARACTERISTICS: PROGRAM MEMORY(3)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param.
Symbol
No.
Min.
Typ.(1)
Max.
Units
Conditions
—
E/W
—
D130
Characteristics
EP
Cell Endurance
1000
—
D130a EP
Cell Endurance
20,000
—
—
E/W
D131
VPR
VDD for Read
2.3
—
3.6
V
D132
See Note 5
—
VPEW
VDD for Erase or Write
3.0
—
3.6
V
D132a VPEW
VDD for Erase or Write
2.3
—
3.6
V
D134
TRETD
Characteristic Retention
20
—
—
Year
Provided no other specifications
are violated
D135
IDDP
Supply Current during
Programming
—
10
—
mA
—
D138
TWW
Word Write Cycle Time(4)
—
411
—
FRC Cycles
—
Time(2,4)
—
See Note 5
D136
TRW
Row Write Cycle
—
26067
—
FRC Cycles
—
D137
TPE
Page Erase Cycle Time(4)
—
201060
—
FRC Cycles
—
D139
TCE
Chip Erase Cycle Time(4)
—
804652
—
FRC Cycles
—
Note 1:
2:
3:
4:
5:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities
during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads
are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default
Arbitration mode is mode 1 (CPU has lowest priority).
Refer to “PIC32 Flash Programming Specification” (DS60001145) for operating conditions during
programming and erase cycles.
Translating this value to seconds depends on the FRC accuracy (see Table 32-19) and the FRC tuning values (see Register 8-2).
This parameter only applies to PIC32MX534/564/664/764 devices.
TABLE 32-12: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS
DC CHARACTERISTICS
Required Flash Wait States
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
SYSCLK
Units
Comments
0 Wait State
0 to 30
MHz
—
1 Wait State
31 to 60
2 Wait States
61 to 80
2009-2019 Microchip Technology Inc.
DS60001156K-page 367
PIC32MX5XX/6XX/7XX
TABLE 32-13: COMPARATOR SPECIFICATIONS
Standard Operating Conditions (see Note 3): 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typical
Max.
Units
Comments
D300
VIOFF
Input Offset Voltage
—
±7.5
±25
mV
AVDD = VDD,
AVSS = VSS
D301
VICM
Input Common Mode Voltage
0
—
VDD
V
AVDD = VDD,
AVSS = VSS
(Note 2)
D302
CMRR
Common Mode Rejection Ratio
55
—
—
dB
Max VICM = (VDD - 1)V
(Note 2)
D303
TRESP
Response Time
—
150
400
ns
AVDD = VDD,
AVSS = VSS
(Notes 1, 2)
D304
ON2OV
Comparator Enabled to Output
Valid
—
—
10
s
Comparator module is
configured before setting
the comparator ON bit
(Note 2)
D305
IVREF
Internal Voltage Reference
0.57
0.6
0.63
V
For devices without
BGSEL
1.14
1.2
1.26
V
BGSEL = 00
0.57
0.6
0.63
V
BGSEL = 01
Note 1:
2:
3:
Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
These parameters are characterized but not tested.
The Comparator module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.
DS60001156K-page 368
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 32-14: VOLTAGE REFERENCE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
D312
TSET
D313
DACREFH CVREF Input Voltage
Reference Range
D314
DVREF
D315
Internal 4-bit DAC
Comparator Reference
Settling time.
DACACC Absolute Accuracy(2)
Note 1:
2:
Typical
Max.
Units
—
—
10
µs
See Note 1
Comments
AVSS
—
AVDD
V
CVRSRC with CVRSS = 0
VREF-
—
VREF+
V
CVRSRC with CVRSS = 1
0
—
0.625 x
DACREFH
V
0 to 0.625 DACREFH with
DACREFH/24 step size
0.25 x
DACREFH
—
0.719 x
DACREFH
V
0.25 x DACREFH to 0.719
DACREFH with DACREFH/32
step size
—
—
DACREFH/
24
CVRCON = 1
—
—
DACREFH/
32
CVRCON = 0
—
—
1/4
LSB
DACREFH/24,
CVRCON = 1
—
—
1/2
LSB
DACREFH/32,
CVRCON = 0
CVREF Programmable
Output Range
DACRES Resolution
D316
Min.
Settling time measured while CVRR = 1 and CVR transitions from ‘0000’ to ‘1111’. This parameter
is characterized, but not tested in manufacturing.
These parameters are characterized but not tested.
TABLE 32-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
DC CHARACTERISTICS
Param.
No.
Symbol
Characteristics
Min.
Typical
Max.
Units
Comments
D321
CEFC
External Filter Capacitor Value
8
10
—
F
Capacitor must be low series
resistance (1 ohm)
D322
TPWRT
Power-up Timer Period
—
64
—
ms
—
2009-2019 Microchip Technology Inc.
DS60001156K-page 369
PIC32MX5XX/6XX/7XX
32.2
AC Characteristics and Timing
Parameters
The information contained in this section defines
PIC32MX5XX/6XX/7XX AC characteristics and timing
parameters.
FIGURE 32-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins
50 pF for OSC2 pin (EC mode)
VSS
TABLE 32-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Param.
Symbol
No.
Min.
Typical(1)
Max.
Units
15
pF
In XT and HS modes when an
external crystal is used to drive
OSC1
DO50
Characteristics
Conditions
Cosco
OSC2 pin
—
—
DO56
CIO
All I/O pins and OSC2
—
—
50
pF
In EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C mode
Note 1:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 32-2:
EXTERNAL CLOCK TIMING
OS20
OS30
OS31
OSC1
OS30
DS60001156K-page 370
OS31
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 32-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param.
Symbol
No.
OS10
FOSC
OS11
Min.
Typical(1)
Max.
Units
Conditions
External CLKI Frequency
(External clocks only allowed
in EC and ECPLL modes)
DC
4
—
—
50
50
MHz
MHz
EC (Note 4)
ECPLL (Note 3)
Oscillator Crystal Frequency
Characteristics
3
—
10
MHz
XT (Note 4)
OS12
4
—
10
MHz
XTPLL
(Notes 3,4)
OS13
10
—
25
MHz
HS (Note 4)
OS14
10
—
25
MHz
HSPLL
(Notes 3,4)
32
32.768
100
kHz
SOSC (Note 4)
—
—
—
—
See parameter
OS10 for FOSC
value
OS15
TCY(2)
OS20
TOSC
TOSC = 1/FOSC =
OS30
TOSL,
TOSH
External Clock In (OSC1)
High or Low Time
0.45 x TOSC
—
—
ns
EC (Note 4)
OS31
TOSR,
TOSF
External Clock In (OSC1)
Rise or Fall Time
—
—
0.05 x TOSC
ns
EC (Note 4)
OS40
TOST
Oscillator Start-up Timer Period
(Only applies to HS, HSPLL,
XT, XTPLL and SOSC Clock
Oscillator modes)
—
1024
—
OS41
TFSCM
Primary Clock Fail Safe
Time-out Period
—
2
—
OS42
GM
External Oscillator
Transconductance (Primary
Oscillator only)
—
12
—
Note 1:
2:
3:
4:
TOSC (Note 4)
ms
(Note 4)
mA/V VDD = 3.3V,
TA = +25°C
(Note 4)
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are not
tested.
Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device
executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min.” values with an
external clock applied to the OSC1/CLKI pin.
PLL input requirements: 4 MHZ FPLLIN 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is
characterized, but is only tested at 10 MHz at manufacturing.
This parameter is characterized, but not tested in manufacturing.
2009-2019 Microchip Technology Inc.
DS60001156K-page 371
PIC32MX5XX/6XX/7XX
TABLE 32-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical
Max.
Units
OS50
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
3.92
—
5
MHz
OS51
FSYS
On-Chip VCO System
Frequency
60
—
120
MHz
OS52
TLOCK
PLL Start-up Time (Lock Time)
—
—
2
ms
OS53
DCLK
CLKO Stability(2)
(Period Jitter or Cumulative)
-0.25
—
+0.25
%
Note 1:
2:
Conditions
ECPLL, HSPLL, XTPLL,
FRCPLL modes
—
—
Measured over 100 ms
period
These parameters are characterized, but not tested in manufacturing.
This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for
individual time-bases on communication clocks, use the following formula:
D CLK
EffectiveJitter = -------------------------------------------------------------SYSCLK
--------------------------------------------------------CommunicationClock
For example, if SYSCLK = 80 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows:
D CLK
D CLK
EffectiveJitter = -------------- = -------------2
80
-----20
TABLE 32-19:
INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Param.
No.
Characteristics
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Min.
Typical
Max.
Units
Conditions
Internal FRC Accuracy @ 8.00 MHz(1) for PIC32MX575/675/695/775/795 Family Devices
F20a
FRC
-2
—
+2
%
—
Internal FRC Accuracy @ 8.00 MHz(1) for PIC32MX534/564/664/764 Family Devices
F20b
Note 1:
FRC
-0.9
—
+0.9
%
—
Frequency calibrated at 25°C and 3.3V. The TUN bits can be used to compensate for temperature drift.
DS60001156K-page 372
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PIC32MX5XX/6XX/7XX
TABLE 32-20: INTERNAL RC ACCURACY
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Characteristics
Min.
Typical
Max.
Units
Conditions
-15
—
+15
%
—
LPRC @ 31.25 kHz(1)
F21
LPRC
Note 1:
Change of LPRC frequency as VDD changes.
FIGURE 32-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
Note: Refer to Figure 32-1 for load conditions.
DO31
DO32
TABLE 32-21: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(2)
Min.
Typical(1)
Max.
Units
—
5
15
ns
VDD < 2.5V
Conditions
DO31
TIOR
Port Output Rise Time
—
5
10
ns
VDD > 2.5V
DO32
TIOF
Port Output Fall Time
—
5
15
ns
VDD < 2.5V
—
5
10
ns
VDD > 2.5V
DI35
TINP
INTx Pin High or Low Time
10
—
—
ns
—
DI40
TRBP
CNx High or Low Time (input)
2
—
—
TSYSCLK
—
Note 1:
2:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
This parameter is characterized, but not tested in manufacturing.
2009-2019 Microchip Technology Inc.
DS60001156K-page 373
PIC32MX5XX/6XX/7XX
FIGURE 32-4:
POWER-ON RESET TIMING CHARACTERISTICS
Internal Voltage Regulator Enabled
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
CPU Starts Fetching Code
SY00
(TPU)
(Note 1)
Internal Voltage Regulator Enabled
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
VDD
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
SY00
(TPU)
(Note 1)
Note 1:
2:
OS40
(TOST)
CPU Starts Fetching Code
The power-up period will be extended if the power-up sequence completes before the device exits from BOR
(VDD < VDDMIN).
Includes interval voltage regulator stabilization delay.
DS60001156K-page 374
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 32-5:
EXTERNAL RESET TIMING CHARACTERISTICS
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
MCLR
TMCLR
(SY20)
BOR
TBOR
(SY30)
(TSYSDLY)
SY02
Reset Sequence
CPU Starts Fetching Code
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
(TSYSDLY)
SY02
Reset Sequence
CPU Starts Fetching Code
TOST
(OS40)
TABLE 32-22: RESETS TIMING
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
SY00
TPU
Power-up Period
Internal Voltage Regulator Enabled
—
400
600
s
-40°C to +85°C
SY02
TSYSDLY System Delay Period:
Time Required to Reload Device
Configuration Fuses plus SYSCLK
Delay before First instruction is
Fetched.
—
1 µs +
8 SYSCLK
cycles
—
—
-40°C to +85°C
SY20
TMCLR
MCLR Pulse Width (low)
—
2
—
s
-40°C to +85°C
SY30
TBOR
BOR Pulse Width (low)
—
1
—
s
-40°C to +85°C
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.
2009-2019 Microchip Technology Inc.
DS60001156K-page 375
PIC32MX5XX/6XX/7XX
FIGURE 32-6:
TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRx
Note: Refer to Figure 32-1 for load conditions.
TABLE 32-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
TA10
TA11
TA15
Characteristics(2)
Symbol
TTXH
TTXL
TTXP
TxCK
High Time
TxCK
Low Time
Typical Max. Units
Conditions
Synchronous,
with prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
—
ns
Must also meet
parameter TA15
Asynchronous,
with prescaler
10
—
—
ns
—
Synchronous,
with prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
—
ns
Must also meet
parameter TA15
Asynchronous,
with prescaler
10
—
—
ns
—
[(Greater of 25 ns or
2 TPB)/N] + 30 ns
—
—
ns
VDD > 2.7V
[(Greater of 25 ns or
2 TPB)/N] + 50 ns
—
—
ns
VDD < 2.7V
20
—
—
ns
VDD > 2.7V
(Note 3)
50
—
—
ns
VDD < 2.7V
(Note 3)
32
—
100
kHz
—
—
—
1
TPB
—
TxCK
Synchronous,
Input Period with prescaler
Asynchronous,
with prescaler
OS60
FT1
TA20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
Note 1:
2:
3:
Min.
SOSC1/T1CK Oscillator
Input Frequency Range
(oscillator enabled by setting
TCS bit (T1CON))
Timer1 is a Type A.
This parameter is characterized, but not tested in manufacturing.
N = Prescale Value (1, 8, 64, 256).
DS60001156K-page 376
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 32-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Max. Units
TB10
TTXH
TxCK
Synchronous, with
High Time prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns
TB11
TTXL
TxCK
Synchronous, with
Low Time prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns
Conditions
Must also meet N = prescale
parameter
value
TB15
(1, 2, 4, 8,
Must also meet 16, 32, 64,
256)
parameter
TB15
TB15
TB20
TTXP
TxCK
Input
Period
Synchronous, with
prescaler
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer Increment
Note 1:
[(Greater of [(25 ns or
2 TPB)/N] + 30 ns
—
ns
VDD > 2.7V
[(Greater of [(25 ns or
2 TPB)/N] + 50 ns
—
ns
VDD < 2.7V
—
1
TPB
—
These parameters are characterized, but not tested in manufacturing.
2009-2019 Microchip Technology Inc.
DS60001156K-page 377
PIC32MX5XX/6XX/7XX
FIGURE 32-7:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 32-1 for load conditions.
TABLE 32-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param.
Symbol
No.
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Characteristics(1)
Min.
Max.
Units
Conditions
IC10
TCCL
ICx Input Low Time
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns
Must also
meet
parameter
IC15.
IC11
TCCH
ICx Input High Time
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns
Must also
meet
parameter
IC15.
IC15
TCCP
ICx Input Period
[(25 ns or 2 TPB)/N]
+ 50 ns
—
ns
Note 1:
These parameters are characterized, but not tested in manufacturing.
FIGURE 32-8:
N = prescale
value (1, 4, 16)
—
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM mode)
OC10
OC11
Note: Refer to Figure 32-1 for load conditions.
TABLE 32-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Min.
Typical(2)
Max.
Units
Conditions
OC10
TCCF
OCx Output Fall Time
—
—
—
ns
See parameter DO32
OC11
TCCR
OCx Output Rise Time
—
—
—
ns
See parameter DO31
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
DS60001156K-page 378
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 32-9:
OCx/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCx
OCx is tri-stated
Note: Refer to Figure 32-1 for load conditions.
TABLE 32-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param
No.
Symbol
Characteristics(1)
Min
Typical(2)
Max
Units
Conditions
OC15
TFD
Fault Input to PWM I/O Change
—
—
50
ns
—
OC20
TFLT
Fault Input Pulse Width
50
—
—
ns
—
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2009-2019 Microchip Technology Inc.
DS60001156K-page 379
PIC32MX5XX/6XX/7XX
FIGURE 32-10:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDOx
SP31
SDIx
LSb
SP30
MSb In
LSb In
Bit 14 - - - -1
SP40 SP41
Note: Refer to Figure 32-1 for load conditions.
TABLE 32-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2) Max.
Units
Conditions
ns
—
—
TSCL
SCKx Output Low Time(3)
TSCK/2
SP11
TSCH
SCKx Output High
Time(3)
TSCK/2
—
—
ns
SP20
TSCF
SCKx Output Fall Time(4)
—
—
—
ns
See parameter DO32
SP21
TSCR
SCKx Output Rise Time(4)
—
—
—
ns
See parameter DO31
—
—
—
ns
See parameter DO32
—
—
—
ns
See parameter DO31
—
—
15
ns
VDD > 2.7V
VDD < 2.7V
SP10
Time(4)
—
—
SP30
TDOF
SDOx Data Output Fall
SP31
TDOR
SDOx Data Output Rise
Time(4)
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
20
ns
SP40
TDIV2SCH,
TDIV2SCL
Setup Time of SDIx Data Input
to SCKx Edge
10
—
—
ns
—
SP41
TSCH2DIL,
TSCL2DIL
Hold Time of SDIx Data Input
to SCKx Edge
10
—
—
ns
—
Note 1:
2:
3:
4:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
DS60001156K-page 380
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 32-11:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11
SCKX
(CKP = 1)
SP10
SP21
SP20
SP20
SP21
SP35
LSb
Bit 14 - - - - - -1
MSb
SDOX
SP30,SP31
SDIX
Bit 14 - - - -1
MSb In
SP40
LSb In
SP41
Note: Refer to Figure 32-1 for load conditions.
TABLE 32-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typ.(2)
Max.
Units
Conditions
—
—
ns
—
TSCL
SCKx Output Low Time(3)
TSCK/2
SP11
TSCH
SCKx Output High
Time(3)
TSCK/2
—
—
ns
—
SP20
TSCF
SCKx Output Fall Time(4)
—
—
—
ns
See parameter DO32
SP21
TSCR
SCKx Output Rise Time(4)
—
—
—
ns
See parameter DO31
SP30
TDOF
SDOx Data Output Fall Time(4)
—
—
—
ns
See parameter DO32
—
—
—
ns
See parameter DO31
—
—
15
ns
VDD > 2.7V
VDD < 2.7V
SP10
SP31
TDOR
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
20
ns
SP36
TDOV2SC, SDOx Data Output Setup to
TDOV2SCL First SCKx Edge
15
—
—
ns
SP40
TDIV2SCH, Setup Time of SDIx Data Input to
TDIV2SCL SCKx Edge
15
—
—
ns
VDD > 2.7V
20
—
—
ns
VDD < 2.7V
SP41
TSCH2DIL,
TSCL2DIL
15
—
—
ns
VDD > 2.7V
20
—
—
ns
VDD < 2.7V
Note 1:
2:
3:
4:
SDOx Data Output Rise
Time(4)
Hold Time of SDIx Data Input
to SCKx Edge
—
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
2009-2019 Microchip Technology Inc.
DS60001156K-page 381
PIC32MX5XX/6XX/7XX
FIGURE 32-12:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
LSb
Bit 14 - - - - - -1
SP51
SP30,SP31
SDIX
MSb In
SP40
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 32-1 for load conditions.
TABLE 32-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Characteristics(1)
Symbol
SP70
SP71
SP72
SP73
SP30
SP31
SP35
TSCL
TSCH
TSCF
TSCR
TDOF
TDOR
TSCH2DOV,
TSCL2DOV
SCKx Input Low Time(3)
SCKx Input High Time(3)
SCKx Input Fall Time
SCKx Input Rise Time
SDOx Data Output Fall Time(4)
SDOx Data Output Rise Time(4)
SDOx Data Output Valid after
SCKx Edge
SP40
TDIV2SCH,
TDIV2SCL
TSCH2DIL,
TSCL2DIL
Setup Time of SDIx Data Input
to SCKx Edge
Hold Time of SDIx Data Input
to SCKx Edge
SP41
SP50
TSSL2SCH, SSx to SCKx or SCKx Input
TSSL2SCL
SP51
TSSH2DOZ SSx to SDOx Output
High-Impedance(3)
Min.
Typ.(2)
Max.
Units
Conditions
TSCK/2
TSCK/2
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
20
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
See parameter DO32
See parameter DO31
See parameter DO32
See parameter DO31
VDD > 2.7V
VDD < 2.7V
—
10
—
—
ns
—
175
—
—
ns
—
5
—
25
ns
—
TSCK + 20
—
—
ns
—
TSCH2SSH SSx after SCKx Edge
TSCL2SSH
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The minimum clock period for SCKx is 40 ns.
4: Assumes 50 pF load on all SPIx pins.
SP52
DS60001156K-page 382
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 32-13:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30,SP31
SDIx
SDI
MSb In
SP40
SP51
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 32-1 for load conditions.
TABLE 32-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
—
ns
—
—
TSCL
SCKx Input Low Time(3)
TSCK/2
—
SP71
TSCH
SCKx Input High
Time(3)
TSCK/2
—
—
ns
SP72
TSCF
SCKx Input Fall Time
—
5
10
ns
—
SP73
TSCR
SCKx Input Rise Time
—
5
10
ns
—
SP30
TDOF
SDOx Data Output Fall Time(4)
—
—
—
ns
See parameter DO32
SP70
(4)
SP31
TDOR
SDOx Data Output Rise Time
—
—
—
ns
See parameter DO31
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
20
ns
VDD > 2.7V
—
—
30
ns
VDD < 2.7V
SP40
TDIV2SCH, Setup Time of SDIx Data Input
TDIV2SCL to SCKx Edge
10
—
—
ns
—
SP41
TSCH2DIL, Hold Time of SDIx Data Input
TSCL2DIL to SCKx Edge
10
—
—
ns
—
SP50
TSSL2SCH, SSx to SCKx or SCKx Input
TSSL2SCL
175
—
—
ns
—
Note 1:
2:
3:
4:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 40 ns.
Assumes 50 pF load on all SPIx pins.
2009-2019 Microchip Technology Inc.
DS60001156K-page 383
PIC32MX5XX/6XX/7XX
TABLE 32-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
SP51
TSSH2DOZ SSx to SDOX Output
High-Impedance(4)
5
—
25
ns
—
SP52
TSCH2SSH SSx after SCKx Edge
TSCL2SSH
TSCK +
20
—
—
ns
—
SP60
TSSL2DOV SDOx Data Output Valid after
SSx Edge
—
—
25
ns
—
Note 1:
2:
3:
4:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 40 ns.
Assumes 50 pF load on all SPIx pins.
DS60001156K-page 384
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 32-14:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 32-1 for load conditions.
FIGURE 32-15:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM25
IM33
SDAx
In
IM40
IM40
IM45
SDAx
Out
Note: Refer to Figure 32-1 for load conditions.
2009-2019 Microchip Technology Inc.
DS60001156K-page 385
PIC32MX5XX/6XX/7XX
TABLE 32-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
IM10
Symbol
TLO:SCL
THI:SCL
IM11
Min.(1)
Max.
Units
Conditions
100 kHz mode
TPB * (BRG + 2)
—
s
—
400 kHz mode
TPB * (BRG + 2)
—
s
—
1 MHz mode(2)
TPB * (BRG + 2)
—
s
—
100 kHz mode
TPB * (BRG + 2)
—
s
—
400 kHz mode
TPB * (BRG + 2)
—
s
—
(2)
Characteristics
Clock Low Time
Clock High Time
TPB * (BRG + 2)
—
s
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode
IM20
TF:SCL
SDAx and SCLx
Fall Time
mode(2)
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(2)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode(2)
100
—
ns
100 kHz mode
0
—
s
400 kHz mode
0
0.9
s
1 MHz mode(2)
0
0.3
s
100 kHz mode
TPB * (BRG + 2)
—
ns
400 kHz mode
TPB * (BRG + 2)
—
ns
1 MHz mode(2)
TPB * (BRG + 2)
—
ns
100 kHz mode
TPB * (BRG + 2)
—
ns
400 kHz mode
TPB * (BRG + 2)
—
ns
1 MHz mode(2)
TPB * (BRG + 2)
—
ns
100 kHz mode
TPB * (BRG + 2)
—
ns
400 kHz mode
TPB * (BRG + 2)
—
ns
1 MHz mode(2)
TPB * (BRG + 2)
—
ns
1 MHz
TR:SCL
IM21
IM25
TSU:DAT
THD:DAT
IM26
IM30
TSU:STA
IM31
THD:STA
TSU:STO
IM33
THD:STO
IM34
TAA:SCL
IM40
SDAx and SCLx
Rise Time
Data Input
Setup Time
Data Input
Hold Time
Start Condition
Setup Time
Start Condition
Hold Time
Stop Condition
Setup Time
TBF:SDA
CB
IM51
TPGD
Note 1:
2:
3:
—
—
Only relevant for
Repeated Start
condition
After this period, the
first clock pulse is
generated
—
Stop Condition
100 kHz mode
TPB * (BRG + 2)
—
ns
400 kHz mode
TPB * (BRG + 2)
—
ns
1 MHz mode(2)
TPB * (BRG + 2)
—
ns
—
3500
ns
—
—
1000
ns
—
(2)
—
350
ns
—
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
mode(2)
0.5
—
s
The amount of time the
bus must be free before
a new
transmission can start
—
400
pF
—
52
312
ns
—
Output Valid from 100 kHz mode
Clock
400 kHz mode
Bus Free Time
1 MHz
IM50
CB is specified to be
from 10 to 400 pF
Hold Time
1 MHz mode
IM45
—
CB is specified to be
from 10 to 400 pF
Bus Capacitive Loading
Pulse Gobbler Delay
(3)
—
BRG is the value of the I2C Baud Rate Generator.
Maximum pin capacitance = 10 pF for all I2Cx pins (only for 1 MHz mode).
The typical value for this parameter is 104 ns.
DS60001156K-page 386
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 32-16:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 32-1 for load conditions.
FIGURE 32-17:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS25
IS33
SDAx
In
IS40
IS40
IS45
SDAx
Out
Note: Refer to Figure 32-1 for load conditions.
2009-2019 Microchip Technology Inc.
DS60001156K-page 387
PIC32MX5XX/6XX/7XX
TABLE 32-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
IS10
IS11
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
Note 1:
Symbol
TLO:SCL
THI:SCL
TF:SCL
TR:SCL
TSU:DAT
THD:DAT
TSU:STA
THD:STA
TSU:STO
THD:STO
TAA:SCL
TBF:SDA
CB
Characteristics
Clock Low Time
Clock High Time
SDAx and SCLx
Fall Time
SDAx and SCLx
Rise Time
Data Input
Setup Time
Data Input
Hold Time
Start Condition
Setup Time
Start Condition
Hold Time
Stop Condition
Setup Time
Stop Condition
Hold Time
Min.
Max.
Units
100 kHz mode
4.7
—
s
PBCLK must operate at a
minimum of 800 kHz
400 kHz mode
1.3
—
s
PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode(1)
0.5
—
s
100 kHz mode
4.0
—
s
PBCLK must operate at a
minimum of 800 kHz
400 kHz mode
0.6
—
s
PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode(1)
0.5
—
s
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode(1)
100
—
ns
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
1 MHz mode(1)
0
0.3
s
100 kHz mode
4700
—
ns
400 kHz mode
600
—
ns
1 MHz mode(1)
250
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode(1)
250
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode(1)
600
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
1 MHz mode(1)
250
Output Valid from 100 kHz mode
Clock
400 kHz mode
Bus Free Time
Conditions
—
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
—
—
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
—
—
ns
ns
0
3500
ns
0
1000
ns
1 MHz mode(1)
0
350
ns
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode(1)
0.5
—
s
—
400
pF
Bus Capacitive Loading
—
—
The amount of time the bus
must be free before a new
transmission can start
—
Maximum pin capacitance = 10 pF for all I2Cx pins (only for 1 MHz mode).
DS60001156K-page 388
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 32-18:
CiTx Pin
(output)
CAN MODULE I/O TIMING CHARACTERISTICS
New Value
Old Value
CA10 CA11
CiRx Pin
(input)
CA20
TABLE 32-34: CAN MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
CA10
TioF
Port Output Fall Time
—
—
—
ns
See parameter DO32
CA11
TioR
Port Output Rise Time
—
—
—
ns
See parameter DO31
CA20
Tcwf
Pulse Width to Trigger
CAN Wake-up Filter
700
—
—
ns
Note 1:
2:
—
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2009-2019 Microchip Technology Inc.
DS60001156K-page 389
PIC32MX5XX/6XX/7XX
TABLE 32-35: ETHERNET MODULE SPECIFICATIONS
Standard Operating Conditions (see Note 1): 2.9V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Characteristic
Min.
Typical
Max.
Units
Conditions
MIIM Timing Requirements
ET1
MDC Duty Cycle
40
—
60
%
—
ET2
MDC Period
400
—
—
ns
—
ET3
MDIO Output Setup and Hold
10
—
10
ns
See Figure 32-19
ET4
MDIO Input Setup and Hold
0
—
300
ns
See Figure 32-20
MII Timing Requirements
ET5
TX Clock Frequency
—
25
—
MHz
—
ET6
TX Clock Duty Cycle
35
—
65
%
—
ET7
ETXDx, ETEN, ETXERR Output Delay
0
—
25
ns
See Figure 32-21
ET8
RX Clock Frequency
—
25
—
MHz
—
ET9
RX Clock Duty Cycle
35
—
65
%
—
ET10
ERXDx, ERXDV, ERXERR Setup and Hold
10
—
30
ns
See Figure 32-22
RMII Timing Requirements
ET11
Reference Clock Frequency
—
50
—
MHz
—
ET12
Reference Clock Duty Cycle
35
—
65
%
—
ET13
ETXDx, ETEN, Setup and Hold
2
—
4
ns
—
ET14
ERXDx, ERXDV, ERXERR Setup and Hold
2
—
4
ns
—
Note 1: The Ethernet module is functional at VBORMIN < VDD < 2.9V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized.
FIGURE 32-19:
MDIO SOURCED BY THE PIC32 DEVICE
VIHMIN
MDC
VILMAX
VIHMIN
MDIO
VILMAX
ET3 (Hold)
(Setup) ET3
FIGURE 32-20:
MDIO SOURCED BY THE PHY
VIHMIN
MDC
VILMAX
VIHMIN
MDIO
VILMAX
ET4
DS60001156K-page 390
2009-2019 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 32-21:
TRANSMIT SIGNAL TIMING RELATIONSHIPS AT THE MII
VIHMIN
VILMAX
TX Clock
VIHMIN
ETXD,
ETEN,
ETXERR
FIGURE 32-22:
VILMAX
ET7
RECEIVE SIGNAL TIMING RELATIONSHIPS AT THE MII
VIHMIN
RX Clock
VILMAX
VIHMIN
ERXD,
ERXDV,
ERXERR
VILMAX
(Setup) ET10
ET10 (Hold)
2009-2019 Microchip Technology Inc.
DS60001156K-page 391
PIC32MX5XX/6XX/7XX
TABLE 32-36: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics
Standard Operating Conditions (see Note 5): 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-Temp
Min.
Typical
Max.
Units
Greater of
VDD – 0.3
or 2.5
—
Lesser of
VDD + 0.3
or 3.6
V
VSS
—
VSS + 0.3
V
Conditions
Device Supply
AD01
AD02
AVDD
AVSS
Module VDD Supply
Module VSS Supply
—
—
Reference Inputs
AD05 VREFH
AD05a
Reference Voltage High AVSS + 2.0
2.5
—
—
AVDD
3.6
V
V
(Note 1)
VREFH = AVDD (Note 3)
AD06
VREFL
Reference Voltage Low
AVSS
—
VREFH – 2.0
V
(Note 1)
AD07
VREF
Absolute Reference
Voltage (VREFH – VREFL)
2.0
—
AVDD
V
(Note 3)
Current Drain
—
—
250
—
400
3
A
A
ADC operating
ADC off
AD08 IREF
AD08a
Analog Input
AD12
VINH-VINL Full-Scale Input Span
VREFL
—
VREFH
V
—
AD13
VINL
Absolute VINL Input
Voltage
AVSS – 0.3
—
AVDD/2
V
—
AD14
VIN
Absolute Input Voltage
AVSS – 0.3
—
AVDD + 0.3
V
—
Leakage Current
—
±0.001
±0.610
A
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
Source Impedance = 10 k
Recommended
Impedance of Analog
Voltage Source
—
—
5K
(Note 1)
AD15
AD17
RIN
ADC Accuracy – Measurements with External VREF+/VREFAD20c Nr
Resolution
AD21c INL
Integral Nonlinearity
> -1
—
-1
—
-1
—
-1
—
-1
—
-1
—
-4
—
-2
—
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