PIC32MZ Embedded Connectivity
with Floating Point Unit (EF) Family
32-bit MCUs (up to 2 MB Live-Update Flash and 512 KB SRAM) with FPU,
Audio and Graphics Interfaces, HS USB, Ethernet, and Advanced Analog
Operating Conditions
Advanced Analog Features
• 2.1V to 3.6V, -40ºC to +85ºC, DC to 252 MHz
• 2.1V to 3.6V, -40ºC to +125ºC, DC to 180 MHz
• 12-bit ADC module:
- 18 Msps with up to six Sample and Hold (S&H) circuits
(five dedicated and one shared)
- Up to 48 analog inputs
- Can operate during Sleep and Idle modes
- Multiple trigger sources
- Six Digital Comparators and six Digital Filters
• Two comparators with 32 programmable voltage
references
• Temperature sensor with ±2ºC accuracy
Core: 252 MHz (up to 415 DMIPS) M-Class
•
•
•
•
•
16 KB I-Cache, 4 KB D-Cache
FPU for 32-bit and 64-bit floating point math
MMU for optimum embedded OS execution
microMIPS™ mode for up to 35% smaller code size
DSP-enhanced core:
- Four 64-bit accumulators
- Single-cycle MAC, saturating, and fractional math
- IEEE 754-compliant
• Code-efficient (C and Assembly) architecture
Clock Management
• Programmable PLLs and oscillator clock sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timers (WDT) and Deadman
Timer (DMT)
• Fast wake-up and start-up
Power Management
• Low-power modes (Sleep and Idle)
• Integrated Power-on Reset (POR) and Brown-out Reset
(BOR)
Communication Interfaces
• Two CAN modules (with dedicated DMA channels):
- 2.0B Active with DeviceNet™ addressing support
• Six UART modules (25 Mbps):
- Supports up to LIN 2.1 and IrDA® protocols
• Six 4-wire SPI modules (up to 50 MHz)
• SQI configurable as an additional SPI module (50 MHz)
• Five I2C modules (up to 1 Mbaud) with SMBus support
• Parallel Master Port (PMP)
• Peripheral Pin Select (PPS) to enable function remap
Timers/Output Compare/Input Capture
Memory Interfaces
•
•
•
•
• 50 MHz External Bus Interface (EBI)
• 50 MHz Serial Quad Interface (SQI)
Input/Output
Audio and Graphics Interfaces
•
•
•
•
Graphics interfaces: EBI or PMP
Audio data communication: I2S, LJ, and RJ
Audio control interfaces: SPI and I2C
Audio master clock: Fractional clock frequencies with USB
synchronization
Nine 16-bit or up to four 32-bit timers/counters
Nine Output Compare (OC) modules
Nine Input Capture (IC) modules
Real-Time Clock and Calendar (RTCC) module
• 5V-tolerant pins with up to 32 mA source/sink
• Selectable open drain, pull-ups, pull-downs, and slew rate
controls
• External interrupts on all I/O pins
• PPS to enable function remap
Qualification and Class B Support
High-Speed (HS) Communication Interfaces
(with Dedicated DMA)
• AEC-Q100 REVH (Grade 1 -40ºC to +125ºC)
• Class B Safety Library, IEC 60730 (planned)
• Back-up internal oscillator
• USB 2.0-compliant Hi-Speed On-The-Go (OTG) controller
• 10/100 Mbps Ethernet MAC with MII and RMII interface
Debugger Development Support
Security Features
• Crypto Engine with RNG for data encryption/decryption and
authentication (AES, 3DES, SHA, MD5, and HMAC)
• Advanced memory protection:
- Peripheral and memory region access control
•
•
•
•
•
Software and Tools Support
•
•
•
•
•
Direct Memory Access (DMA)
• Eight channels with automatic data size detection
• Programmable Cyclic Redundancy Check (CRC)
In-circuit and in-application programming
4-wire MIPS® Enhanced JTAG interface
Unlimited software and 12 complex breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Non-intrusive hardware-based instruction trace
C/C++ compiler with native DSP/fractional and FPU support
MPLAB® Harmony Integrated Software Framework
TCP/IP, USB, Graphics, and mTouch™ middleware
MFi, Android™, and Bluetooth® audio frameworks
RTOS Kernels: Express Logic ThreadX, FreeRTOS™,
OPENRTOS®, Micriµm® µC/OS™, and SEGGER embOS®
Packages
Type
QFN
TQFP
TFBGA(1)
VTLA
LQFP
Pin Count
64
64
100
144
100
144
124
144
I/O Pins (up to)
53
53
78
120
78
120
98
120
Contact/Lead Pitch 0.50 mm
0.50 mm
0.40 mm
0.50 mm
0.40 mm
0.65 mm
0.50 mm
0.50 mm
0.50 mm
Dimensions
9x9x0.9 mm 10x10x1 mm 12x12x1 mm 14x14x1 mm 16x16x1 mm 7x7x1.2 mm 7x7x1.2 mm 9x9x0.9 mm 20x20x1.40 mm
Note 1: Contact your local Microchip Sales Office for information on the availability of devices in the 100-pin and 144-pin TFBGA packages
2015-2016 Microchip Technology Inc.
DS60001320D-page 1
PIC32MZ EF FAMILY FEATURES
Y
Y
Y
8/18
PIC32MZ0512EFE100
0
N
Y
8/12
2
N
Y
8/16
2
Y
Y
8/18
0
N
Y
8/12
8/16
128
PIC32MZ0512EFK100
100
PIC32MZ1024EFE100
PIC32MZ1024EFF100
160
51
9/9/9
6
6
5
2
N
Y
PIC32MZ1024EFK100
2
Y
Y
8/18
PIC32MZ0512EFE124
0
N
Y
8/12
2
N
Y
8/16
2
Y
Y
8/18
0
N
Y
8/12
8/16
PIC32MZ0512EFF124
1024
TQFP
512
256
128
PIC32MZ0512EFK124
124
PIC32MZ1024EFE124
PIC32MZ1024EFF124
160
53
9/9/9
6
6
5
2015-2016 Microchip Technology Inc.
2
N
Y
PIC32MZ1024EFK124
2
Y
Y
8/18
PIC32MZ0512EFE144
0
N
Y
8/12
2
N
Y
8/16
2
Y
Y
8/18
0
N
Y
8/12
2
N
Y
8/16
2
Y
Y
8/18
PIC32MZ0512EFF144
1024
VTLA
512
256
128
PIC32MZ0512EFK144
144
PIC32MZ1024EFE144
PIC32MZ1024EFF144
1024
LQFP,
TQFP
160
256
PIC32MZ1024EFK144
Note
1:
2:
3:
Eight out of nine timers are remappable.
Four out of five external interrupts are remappable.
This device is available with a 252 MHz speed rating.
53
9/9/9
6
6
5
Trace
N
JTAG
8/16
2
I/O Pins
8/12
Ethernet
Y
RTCC
N
SQI
8/18
0
2
512
256
Y
EBI
5
Y
PMP
4
8/16
2
I2C
6
8/12
Y
USB 2.0 HS OTG
9/9/9
Y
N
PIC32MZ1024EFK064
PIC32MZ0512EFF100
1024
34
N
2
Analog Comparators
PIC32MZ1024EFF064
160
0
ADC (Channels)
64
PIC32MZ1024EFE064
TQFP,
QFN
DMA Channels
(Programmable/
Dedicated)
PIC32MZ0512EFK064
RNG
PIC32MZ0512EFF064
Crypto
PIC32MZ0512EFE064
CAN 2.0B
External
Interrupts(2)
SPI/I2S
UART
Timers/
Capture/
Compare(1)
Remappable Pins
Boot Flash
Memory (KB)
128
Packages
Data
Memory (KB)
512
Pins
Program
Memory (KB)
Device
Remappable Peripherals
24
2
Y
4
Y
N
Y
Y
Y
46
Y
Y
40
2
Y
5
Y
Y
Y
Y
Y
78
Y
Y
48
2
Y
5
Y
Y
Y
Y
Y
97
Y
Y
48
2
Y
5
Y
Y
Y
Y
Y
120
Y
Y
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 2
TABLE 1:
PIC32MZ EF FAMILY FEATURES (CONTINUED)
8/12
8/16
2
N
Y
PIC32MZ2048EFM064
2
Y
Y
8/18
PIC32MZ1024EFG100
0
N
Y
8/12
2
N
Y
8/16
2
Y
Y
8/18
0
N
Y
8/12
8/16
PIC32MZ1024EFH100
1024
PIC32MZ1024EFM100
512
PIC32MZ2048EFG100
PIC32MZ2048EFH100(3)
100
TQFP
160
51
9/9/9
6
6
5
2048
2
N
Y
PIC32MZ2048EFM100
2
Y
Y
8/18
PIC32MZ1024EFG124
0
N
Y
8/12
2
N
Y
8/16
2
Y
Y
8/18
0
N
Y
8/12
8/16
PIC32MZ1024EFH124
1024
PIC32MZ1024EFM124
512
PIC32MZ2048EFG124
PIC32MZ2048EFH124
124
VTLA
160
53
9/9/9
6
6
5
2
N
Y
PIC32MZ2048EFM124
2
Y
Y
8/18
PIC32MZ1024EFG144
0
N
Y
8/12
2
N
Y
8/16
2
Y
Y
8/18
0
N
Y
8/12
2
N
Y
8/16
2
Y
Y
8/18
PIC32MZ1024EFH144
2048
1024
PIC32MZ1024EFM144
512
PIC32MZ2048EFG144
PIC32MZ2048EFH144(3)
144
LQFP,
TQFP
160
2048
PIC32MZ2048EFM144
DS60001320D-page 3
Note
1:
2:
3:
Eight out of nine timers are remappable.
Four out of five external interrupts are remappable.
This device is available with a 252 MHz speed rating.
53
9/9/9
6
6
5
Trace
Y
JTAG
N
I/O Pins
2048
8/18
0
Ethernet
5
RTCC
4
Y
SQI
6
Y
EBI
9/9/9
8/16
2
PMP
34
8/12
Y
I2C
160
Y
N
USB 2.0 HS OTG
PIC32MZ2048EFH064(3)
64
N
2
Analog Comparators
512
PIC32MZ2048EFG064
TQFP,
QFN
0
ADC (Channels)
PIC32MZ1024EFM064
DMA Channels
(Programmable/
Dedicated)
1024
RNG
PIC32MZ1024EFH064
Crypto
PIC32MZ1024EFG064
CAN 2.0B
External
Interrupts(2)
SPI/I2S
UART
Timers/
Capture/
Compare(1)
Remappable Pins
Boot Flash
Memory (KB)
Packages
Pins
Data
Memory (KB)
Program
Memory (KB)
Device
Remappable Peripherals
24
2
Y
4
Y
N
Y
Y
Y
46
Y
Y
40
2
Y
5
Y
Y
Y
Y
Y
78
Y
Y
48
2
Y
5
Y
Y
Y
Y
Y
97
Y
Y
48
2
Y
5
Y
Y
Y
Y
Y
120
Y
Y
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2015-2016 Microchip Technology Inc.
TABLE 1:
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
Device Pin Tables
TABLE 2:
PIN NAMES FOR 64-PIN DEVICES
64-PIN QFN(4) AND TQFP (TOP VIEW)
PIC32MZ0512EF(E/F/K)064
PIC32MZ1024EF(G/H/M)064
PIC32MZ1024EF(E/F/K)064
PIC32MZ2048EF(G/H/M)064
64
QFN
Pin #
Full Pin Name
64
1
(4)
1
TQFP
Pin #
Full Pin Name
1
AN17/ETXEN/RPE5/PMD5/RE5
33
VBUS
2
AN16/ETXD0/PMD6/RE6
34
VUSB3V3
3
AN15/ETXD1/PMD7/RE7
35
VSS
4
AN14/C1IND/RPG6/SCK2/PMA5/RG6
36
D-
5
AN13/C1INC/RPG7/SDA4/PMA4/RG7
37
D+
6
AN12/C2IND/RPG8/SCL4/PMA3/RG8
38
RPF3/USBID/RF3
7
VSS
39
VDD
8
VDD
40
VSS
9
MCLR
41
RPF4/SDA5/PMA9/RF4
10
AN11/C2INC/RPG9/PMA2/RG9
42
RPF5/SCL5/PMA8/RF5
11
AN45/C1INA/RPB5/RB5
43
AERXD0/ETXD2/RPD9/SDA1/PMCS2/PMA15/RD9
12
AN4/C1INB/RB4
44
ECOL/RPD10/SCL1/SCK4/RD10
13
AN3/C2INA/RPB3/RB3
45
AERXCLK/AEREFCLK/ECRS/RPD11/PMCS1/PMA14/RD11
14
AN2/C2INB/RPB2/RB2
46
AERXD1/ETXD3/RPD0/RTCC/INT0/RD0
15
PGEC1/VREF-/CVREF-/AN1/RPB1/RB1
47
SOSCI/RPC13/RC13
16
PGED1/VREF+/CVREF+/AN0/RPB0/PMA6/RB0
48
SOSCO/RPC14/T1CK/RC14
17
PGEC2/AN46/RPB6/RB6
49
EMDIO/AEMDIO/RPD1/SCK1/RD1
18
PGED2/AN47/RPB7/RB7
50
ETXERR/AETXEN/RPD2/SDA3/RD2
19
AVDD
51
AERXERR/ETXCLK/RPD3/SCL3/RD3
20
AVss
52
SQICS0/RPD4/PMWR/RD4
21
AN48/RPB8/PMA10/RB8
53
SQICS1/RPD5/PMRD/RD5
22
AN49/RPB9/PMA7/RB9
54
VDD
23
TMS/CVREFOUT/AN5/RPB10/PMA13/RB10
55
VSS
24
TDO/AN6/PMA12/RB11
56
ERXD3/AETXD1/RPF0/RF0
25
VSS
57
TRCLK/SQICLK/ERXD2/AETXD0/RPF1/RF1
26
VDD
58
TRD0/SQID0/ERXD1/PMD0/RE0
27
TCK/AN7/PMA11/RB12
59
VSS
28
TDI/AN8/RB13
60
VDD
29
AN9/RPB14/SCK3/PMA1/RB14
61
TRD1/SQID1/ERXD0/PMD1/RE1
30
AN10/EMDC/AEMDC/RPB15/OCFB/PMA0/RB15
62
TRD2/SQID2/ERXDV/ECRSDV/AECRSDV/PMD2/RE2
31
OSC1/CLKI/RC12
63
TRD3/SQID3/ERXCLK/EREFCLK/RPE3/PMD3/RE3
OSC2/CLKO/RC15
64
AN18/ERXERR/PMD4/RE4
32
Note
1:
2:
3:
4:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RBx-RGx) can be used as a change notification pin (CNBx-CNGx). See Section 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
DS60001320D-page 4
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 3:
PIN NAMES FOR 100-PIN DEVICES
100-PIN TQFP (TOP VIEW)
PIC32MZ0512EF(E/F/K)100
PIC32MZ1024EF(G/H/M)100
PIC32MZ1024EF(E/F/K)100
PIC32MZ2048EF(G/H/M)100
100
1
Pin #
Full Pin Name
Pin #
Full Pin Name
1
AN23/AERXERR/RG15
36
VSS
2
EBIA5/AN34/PMA5/RA5
37
VDD
3
EBID5/AN17/RPE5/PMD5/RE5
38
TCK/EBIA19/AN29/RA1
4
EBID6/AN16/PMD6/RE6
39
TDI/EBIA18/AN30/RPF13/SCK5/RF13
5
EBID7/AN15/PMD7/RE7
40
TDO/EBIA17/AN31/RPF12/RF12
6
EBIA6/AN22/RPC1/PMA6/RC1
41
EBIA11/AN7/ERXD0/AECRS/PMA11/RB12
7
EBIA12/AN21/RPC2/PMA12/RC2
42
AN8/ERXD1/AECOL/RB13
8
EBIWE/AN20/RPC3/PMWR/RC3
43
EBIA1/AN9/ERXD2/AETXD3/RPB14/SCK3/PMA1/RB14
9
EBIOE/AN19/RPC4/PMRD/RC4
44
EBIA0/AN10/ERXD3/AETXD2/RPB15/OCFB/PMA0/RB15
10
AN14/C1IND/ECOL/RPG6/SCK2/RG6
45
VSS
11
EBIA4/AN13/C1INC/ECRS/RPG7/SDA4/PMA4/RG7
46
VDD
12
EBIA3/AN12/C2IND/ERXDV/ECRSDV/AERXDV/
AECRSDV/RPG8/SCL4/PMA3/RG8
47
AN32/AETXD0/RPD14/RD14
13
VSS
48
AN33/AETXD1/RPD15/SCK6/RD15
14
VDD
49
OSC1/CLKI/RC12
15
MCLR
50
OSC2/CLKO/RC15
16
EBIA2/AN11/C2INC/ERXCLK/EREFCLK/AERXCLK/
AEREFCLK/RPG9/PMA2/RG9
51
VBUS
17
TMS/EBIA16/AN24/RA0
52
VUSB3V3
18
AN25/AERXD0/RPE8/RE8
53
VSS
19
AN26/AERXD1/RPE9/RE9
54
D-
20
AN45/C1INA/RPB5/RB5
55
D+
21
AN4/C1INB/RB4
56
RPF3/USBID/RF3
22
AN3/C2INA/RPB3/RB3
57
EBIRDY3/RPF2/SDA3/RF2
23
AN2/C2INB/RPB2/RB2
58
EBIRDY2/RPF8/SCL3/RF8
24
PGEC1/AN1/RPB1/RB1
59
EBICS0/SCL2/RA2
25
PGED1/AN0/RPB0/RB0
60
EBIRDY1/SDA2/RA3
26
PGEC2/AN46/RPB6/RB6
61
EBIA14/PMCS1/PMA14/RA4
27
PGED2/AN47/RPB7/RB7
62
VDD
28
VREF-/CVREF-/AN27/AERXD2/RA9
63
VSS
29
VREF+/CVREF+/AN28/AERXD3/RA10
64
EBIA9/RPF4/SDA5/PMA9/RF4
30
AVDD
65
EBIA8/RPF5/SCL5/PMA8/RF5
31
AVSS
66
AETXCLK/RPA14/SCL1/RA14
32
EBIA10/AN48/RPB8/PMA10/RB8
67
AETXEN/RPA15/SDA1/RA15
33
EBIA7/AN49/RPB9/PMA7/RB9
68
EBIA15/RPD9/PMCS2/PMA15/RD9
34
EBIA13/CVREFOUT/AN5/RPB10/PMA13/RB10
69
RPD10/SCK4/RD10
35
AN6/ERXERR/AETXERR/RB11
70
EMDC/AEMDC/RPD11/RD11
Note
1:
2:
3:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 12.0 “I/O Ports” for more
information.
Shaded pins are 5V tolerant.
2015-2016 Microchip Technology Inc.
DS60001320D-page 5
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 3:
PIN NAMES FOR 100-PIN DEVICES (CONTINUED)
100-PIN TQFP (TOP VIEW)
PIC32MZ0512EF(E/F/K)100
PIC32MZ1024EF(G/H/M)100
PIC32MZ1024EF(E/F/K)100
PIC32MZ2048EF(G/H/M)100
100
1
Pin #
Full Pin Name
Pin #
Full Pin Name
71
EMDIO/AEMDIO/RPD0/RTCC/INT0/RD0
86
EBID10/ETXD0/RPF1/PMD10/RF1
72
SOSCI/RPC13/RC13
87
EBID9/ETXERR/RPG1/PMD9/RG1
73
SOSCO/RPC14/T1CK/RC14
88
EBID8/RPG0/PMD8/RG0
74
VDD
89
TRCLK/SQICLK/RA6
75
VSS
90
TRD3/SQID3/RA7
76
RPD1/SCK1/RD1
91
EBID0/PMD0/RE0
77
EBID14/ETXEN/RPD2/PMD14/RD2
92
VSS
78
EBID15/ETXCLK/RPD3/PMD15/RD3
93
VDD
79
EBID12/ETXD2/RPD12/PMD12/RD12
94
EBID1/PMD1/RE1
80
EBID13/ETXD3/PMD13/RD13
95
TRD2/SQID2/RG14
81
SQICS0/RPD4/RD4
96
TRD1/SQID1/RG12
82
SQICS1/RPD5/RD5
97
TRD0/SQID0/RG13
83
VDD
98
EBID2/PMD2/RE2
84
VSS
99
EBID3/RPE3/PMD3/RE3
85
EBID11/ETXD1/RPF0/PMD11/RF0
100
EBID4/AN18/PMD4/RE4
Note
1:
2:
3:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 12.0 “I/O Ports” for more
information.
Shaded pins are 5V tolerant.
DS60001320D-page 6
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 4:
PIN NAMES FOR 124-PIN DEVICES
A34
124-PIN VTLA (BOTTOM VIEW)
A17
B29
B13
PIC32MZ0512EF(E/F/K)124
PIC32MZ1024EF(G/H/M)124
PIC32MZ1024EF(E/F/K)124
PIC32MZ2048EF(G/H/M)124
B56
Full Pin Name
A51
A1
A68
Polarity Indicator
Package
Pin #
B41
B1
Package
Pin #
Full Pin Name
A1
No Connect
A35
VBUS
A2
AN23/RG15
A36
VUSB3V3
A3
EBID5/AN17/RPE5/PMD5/RE5
A37
D-
A4
EBID7/AN15/PMD7/RE7
A38
RPF3/USBID/RF3
A5
AN35/ETXD0/RJ8
A39
EBIRDY2/RPF8/SCL3/RF8
A6
EBIA12/AN21/RPC2/PMA12/RC2
A40
ERXD3/RH9
A7
EBIOE/AN19/RPC4/PMRD/RC4
A41
EBICS0/SCL2/RA2
A8
EBIA4/AN13/C1INC/RPG7/SDA4/PMA4/RG7
A42
EBIA14/PMCS1/PMA14/RA4
A9
VSS
A43
VSS
A10
MCLR
A44
EBIA8/RPF5/SCL5/PMA8/RF5
A11
TMS/EBIA16/AN24/RA0
A45
RPA15/SDA1/RA15
A12
AN26/RPE9/RE9
A46
RPD10/SCK4/RD10
A13
AN4/C1INB/RB4
A47
ECRS/RH12
A14
AN3/C2INA/RPB3/RB3
A48
RPD0/RTCC/INT0/RD0
A15
VDD
A49
SOSCO/RPC14/T1CK/RC14
A16
AN2/C2INB/RPB2/RB2
A50
VDD
A17
PGEC1/AN1/RPB1/RB1
A51
VSS
A18
PGED1/AN0/RPB0/RB0
A52
RPD1/SCK1/RD1
A19
PGED2/AN47/RPB7/RB7
A53
EBID15/RPD3/PMD15/RD3
A20
VREF+/CVREF+/AN28/RA10
A54
EBID13/PMD13/RD13
A21
AVSS
A55
EMDIO/RJ1
A22
AN39/ETXD3/RH1
A56
SQICS0/RPD4/RD4
A23
EBIA7/AN49/RPB9/PMA7/RB9
A57
ETXEN/RPD6/RD6
A24
AN6/RB11
A58
VDD
A25
VDD
A59
EBID11/RPF0/PMD11/RF0
A26
TDI/EBIA18/AN30/RPF13/SCK5/RF13
A60
EBID9/RPG1/PMD9/RG1
A27
EBIA11/AN7/PMA11/RB12
A61
TRCLK/SQICLK/RA6
A28
EBIA1/AN9/RPB14/SCK3/PMA1/RB14
A62
RJ4
A29
VSS
A63
VSS
A30
AN40/ERXERR/RH4
A64
EBID1/PMD1/RE1
A31
AN42/ERXD2/RH6
A65
TRD1/SQID1/RG12
A32
AN33/RPD15/SCK6/RD15
A66
EBID2/SQID2/PMD2/RE2
A33
OSC2/CLKO/RC15
A67
EBID4/AN18/PMD4/RE4
A34
No Connect
A68
No Connect
Note
1:
2:
3:
4:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RJx) can be used as a change notification pin (CNAx-CNJx). See Section 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
2015-2016 Microchip Technology Inc.
DS60001320D-page 7
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 4:
PIN NAMES FOR 124-PIN DEVICES (CONTINUED)
A34
124-PIN VTLA (BOTTOM VIEW)
A17
B13
PIC32MZ0512EF(E/F/K)124
PIC32MZ1024EF(G/H/M)124
PIC32MZ1024EF(E/F/K)124
PIC32MZ2048EF(G/H/M)124
Full Pin Name
B41
B1
B56
A51
A1
A68
Polarity Indicator
Package
Pin #
B29
Package
Pin #
Full Pin Name
B1
EBIA5/AN34/PMA5/RA5
B29
VSS
B2
EBID6/AN16/PMD6/RE6
B30
D+
B3
EBIA6/AN22/RPC1/PMA6/RC1
B31
RPF2/SDA3/RF2
B4
AN36/ETXD1/RJ9
B32
ERXD0/RH8
B5
EBIWE/AN20/RPC3/PMWR/RC3
B33
ECOL/RH10
B6
AN14/C1IND/RPG6/SCK2/RG6
B34
EBIRDY1/SDA2/RA3
B7
EBIA3/AN12/C2IND/RPG8/SCL4/PMA3/RG8
B35
VDD
B8
VDD
B36
EBIA9/RPF4/SDA5/PMA9/RF4
RPA14/SCL1/RA14
B9
EBIA2/AN11/C2INC/RPG9/PMA2/RG9
B37
B10
AN25/RPE8/RE8
B38
EBIA15/RPD9/PMCS2/PMA15/RD9
B11
AN45/C1INA/RPB5/RB5
B39
EMDC/RPD11/RD11
B12
AN37/ERXCLK/EREFCLK/RJ11
B40
ERXDV/ECRSDV/RH13
B13
VSS
B41
SOSCI/RPC13/RC13
B14
PGEC2/AN46/RPB6/RB6
B42
EBID14/RPD2/PMD14/RD2
B15
VREF-/CVREF-/AN27/RA9
B43
EBID12/RPD12/PMD12/RD12
B16
AVDD
B44
ETXERR/RJ0
B17
AN38/ETXD2/RH0
B45
EBIRDY3/RJ2
B18
EBIA10/AN48/RPB8/PMA10/RB8
B46
SQICS1/RPD5/RD5
ETXCLK/RPD7/RD7
B19
EBIA13/CVREFOUT/AN5/RPB10/PMA13/RB10
B47
B20
VSS
B48
VSS
B21
TCK/EBIA19/AN29/RA1
B49
EBID10/RPF1/PMD10/RF1
B22
TDO/EBIA17/AN31/RPF12/RF12
B50
EBID8/RPG0/PMD8/RG0
B23
AN8/RB13
B51
TRD3/SQID3/RA7
B24
EBIA0/AN10/RPB15/OCFB/PMA0/RB15
B52
EBID0/PMD0/RE0
B25
VDD
B53
VDD
B26
AN41/ERXD1/RH5
B54
TRD2/SQID2/RG14
B27
AN32/AETXD0/RPD14/RD14
B55
TRD0/SQID0/RG13
B28
OSC1/CLKI/RC12
B56
EBID3/RPE3/PMD3/RE3
Note
1:
2:
3:
4:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RJx) can be used as a change notification pin (CNAx-CNJx). See Section 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
DS60001320D-page 8
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 5:
PIN NAMES FOR 144-PIN DEVICES
144-PIN LQFP AND TQFP (TOP VIEW)
PIC32MZ0512EF(E/F/K)144
PIC32MZ1024EF(G/H/M)144
PIC32MZ1024EF(E/F/K)144
PIC32MZ2048EF(G/H/M)144
144
1
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
1
AN23/RG15
37
PGEC2/AN46/RPB6/RB6
2
EBIA5/AN34/PMA5/RA5
38
PGED2/AN47/RPB7/RB7
3
EBID5/AN17/RPE5/PMD5/RE5
39
VREF-/CVREF-/AN27/RA9
4
EBID6/AN16/PMD6/RE6
40
VREF+/CVREF+/AN28/RA10
5
6
EBID7/AN15/PMD7/RE7
EBIA6/AN22/RPC1/PMA6/RC1
41
42
AVDD
AVSS
7
AN35/ETXD0/RJ8
43
AN38/ETXD2/RH0
8
AN36/ETXD1/RJ9
44
AN39/ETXD3/RH1
9
EBIBS0/RJ12
45
EBIRP/RH2
10
EBIBS1/RJ10
46
RH3
11
12
EBIA12/AN21/RPC2/PMA12/RC2
EBIWE/AN20/RPC3/PMWR/RC3
47
EBIA10/AN48/RPB8/PMA10/RB8
48
EBIA7/AN49/RPB9/PMA7/RB9
13
EBIOE/AN19/RPC4/PMRD/RC4
49
CVREFOUT/AN5/RPB10/RB10
14
15
AN14/C1IND/RPG6/SCK2/RG6
AN13/C1INC/RPG7/SDA4/RG7
50
51
AN6/RB11
EBIA1/PMA1/RK1
16
AN12/C2IND/RPG8/SCL4/RG8
52
EBIA3/PMA3/RK2
17
VSS
53
EBIA17/RK3
18
VDD
54
VSS
19
EBIA16/RK0
55
VDD
20
21
MCLR
EBIA2/AN11/C2INC/RPG9/PMA2/RG9
56
57
TCK/AN29/RA1
TDI/AN30/RPF13/SCK5/RF13
22
23
TMS/AN24/RA0
AN25/RPE8/RE8
58
59
TDO/AN31/RPF12/RF12
AN7/RB12
24
25
AN26/RPE9/RE9
AN45/C1INA/RPB5/RB5
60
61
AN8/RB13
AN9/RPB14/SCK3/RB14
26
27
AN4/C1INB/RB4
AN37/ERXCLK/EREFCLK/RJ11
62
63
AN10/RPB15/OCFB/RB15
VSS
28
29
EBIA13/PMA13/RJ13
EBIA11/PMA11/RJ14
64
65
VDD
AN40/ERXERR/RH4
30
31
EBIA0/PMA0/RJ15
AN3/C2INA/RPB3/RB3
66
67
AN41/ERXD1/RH5
AN42/ERXD2/RH6
32
VSS
68
EBIA4/PMA4/RH7
33
34
VDD
AN2/C2INB/RPB2/RB2
69
70
AN32/RPD14/RD14
AN33/RPD15/SCK6/RD15
35
36
PGEC1/AN1/RPB1/RB1
PGED1/AN0/RPB0/RB0
71
72
OSC1/CLKI/RC12
OSC2/CLKO/RC15
Note
1:
2:
3:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See Section 12.0 “I/O Ports” for more
information.
Shaded pins are 5V tolerant.
2015-2016 Microchip Technology Inc.
DS60001320D-page 9
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 5:
PIN NAMES FOR 144-PIN DEVICES (CONTINUED)
144-PIN LQFP AND TQFP (TOP VIEW)
PIC32MZ0512EF(E/F/K)144
PIC32MZ1024EF(G/H/M)144
PIC32MZ1024EF(E/F/K)144
PIC32MZ2048EF(G/H/M)144
144
1
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
73
VBUS
109
RPD1/SCK1/RD1
74
VUSB3V3
75
VSS
110
111
EBID14/RPD2/PMD14/RD2
EBID15/RPD3/PMD15/RD3
76
D-
77
D+
112
113
EBID12/RPD12/PMD12/RD12
EBID13/PMD13/RD13
78
RPF3/USBID/RF3
79
SDA3/RPF2/RF2
114
115
ETXERR/RJ0
EMDIO/RJ1
80
81
SCL3/RPF8/RF8
ERXD0/RH8
116
117
EBIRDY3/RJ2
EBIA22/RJ3
82
ERXD3/RH9
118
SQICS0/RPD4/RD4
83
84
ECOL/RH10
EBIRDY2/RH11
119
120
SQICS1/RPD5/RD5
ETXEN/RPD6/RD6
85
86
SCL2/RA2
EBIRDY1/SDA2/RA3
121
122
ETXCLK/RPD7/RD7
VDD
87
EBIA14/PMCS1/PMA14/RA4
123
VSS
88
89
VDD
VSS
124
125
EBID11/RPF0/PMD11/RF0
EBID10/RPF1/PMD10/RF1
90
EBIA9/RPF4/SDA5/PMA9/RF4
126
EBIA21/RK7
91
92
EBIA8/RPF5/SCL5/PMA8/RF5
EBIA18/RK4
127
128
EBID9/RPG1/PMD9/RG1
EBID8/RPG0/PMD8/RG0
93
EBIA19/RK5
129
TRCLK/SQICLK/RA6
94
95
EBIA20/RK6
RPA14/SCL1/RA14
130
131
TRD3/SQID3/RA7
EBICS0/RJ4
96
97
RPA15/SDA1/RA15
EBIA15/RPD9/PMCS2/PMA15/RD9
132
133
EBICS1/RJ5
EBICS2/RJ6
98
99
RPD10/SCK4/RD10
EMDC/RPD11/RD11
134
135
EBICS3/RJ7
EBID0/PMD0/RE0
100
ECRS/RH12
136
VSS
101
ERXDV/ECRSDV/RH13
137
VDD
102
RH14
138
EBID1/PMD1/RE1
103
104
EBIA23/RH15
RPD0/RTCC/INT0/RD0
139
140
TRD2/SQID2/RG14
TRD1/SQID1/RG12
105
SOSCI/RPC13/RC13
106
SOSCO/RPC14/T1CK/RC14
141
142
TRD0/SQID0/RG13
EBID2/PMD2/RE2
107
VDD
108
VSS
143
144
EBID3/RPE3/PMD3/RE3
EBID4/AN18/PMD4/RE4
Note
1:
2:
3:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See Section 12.0 “I/O Ports” for more
information.
Shaded pins are 5V tolerant.
DS60001320D-page 10
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 15
2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 37
3.0 CPU............................................................................................................................................................................................ 43
4.0 Memory Organization ................................................................................................................................................................. 61
5.0 Flash Program Memory.............................................................................................................................................................. 99
6.0 Resets ...................................................................................................................................................................................... 109
7.0 CPU Exceptions and Interrupt Controller ................................................................................................................................. 115
8.0 Oscillator Configuration ............................................................................................................................................................ 153
9.0 Prefetch Module ....................................................................................................................................................................... 169
10.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 173
11.0 Hi-Speed USB with On-The-Go (OTG) .................................................................................................................................... 197
12.0 I/O Ports ................................................................................................................................................................................... 247
13.0 Timer1 ...................................................................................................................................................................................... 283
14.0 Timer2/3, Timer4/5, Timer6/7, and Timer8/9............................................................................................................................ 287
15.0 Deadman Timer (DMT) ............................................................................................................................................................ 293
16.0 Watchdog Timer (WDT) ........................................................................................................................................................... 301
17.0 Input Capture............................................................................................................................................................................ 305
18.0 Output Compare....................................................................................................................................................................... 309
19.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I2S)....................................................................................................... 315
20.0 Serial Quad Interface (SQI)...................................................................................................................................................... 325
21.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 353
22.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 361
23.0 Parallel Master Port (PMP)....................................................................................................................................................... 369
24.0 External Bus Interface (EBI)..................................................................................................................................................... 383
25.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 391
26.0 Crypto Engine........................................................................................................................................................................... 401
27.0 Random Number Generator (RNG) ......................................................................................................................................... 421
28.0 12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC)......................................... 427
29.0 Controller Area Network (CAN) ................................................................................................................................................ 485
30.0 Ethernet Controller ................................................................................................................................................................... 523
31.0 Comparator .............................................................................................................................................................................. 567
32.0 Comparator Voltage Reference (CVREF) ................................................................................................................................. 571
33.0 Power-Saving Features ........................................................................................................................................................... 575
34.0 Special Features ...................................................................................................................................................................... 581
35.0 Instruction Set .......................................................................................................................................................................... 605
36.0 Development Support............................................................................................................................................................... 607
37.0 Electrical Characteristics .......................................................................................................................................................... 611
38.0 Extended Temperature Electrical Characteristics .................................................................................................................... 663
39.0 252 MHz Electrical Characteristics........................................................................................................................................... 669
40.0 AC and DC Characteristics Graphs.......................................................................................................................................... 675
41.0 Packaging Information.............................................................................................................................................................. 677
The Microchip Web Site ..................................................................................................................................................................... 733
Customer Change Notification Service .............................................................................................................................................. 733
Customer Support .............................................................................................................................................................................. 733
Product Identification System ............................................................................................................................................................ 734
2015-2016 Microchip Technology Inc.
DS60001320D-page 11
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS60001320D-page 12
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
Referenced Sources
This device data sheet is based on the following
individual sections of the “PIC32 Family Reference
Manual”. These documents should be considered as
the general reference for the operation of a particular
module or device feature.
Note:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
To access the following documents,
browse the documentation section of the
Microchip
web
site
(www.microchip.com).
Section 1. “Introduction” (DS60001127)
Section 7. “Resets” (DS60001118)
Section 8. “Interrupt Controller” (DS60001108)
Section 9. “Watchdog, Deadman, and Power-up Timers” (DS60001114)
Section 10. “Power-Saving Features” (DS60001130)
Section 12. “I/O Ports” (DS60001120)
Section 13. “Parallel Master Port (PMP)” (DS60001128)
Section 14. “Timers” (DS60001105)
Section 15. “Input Capture” (DS60001122)
Section 16. “Output Compare” (DS60001111)
Section 19. “Comparator” (DS60001110)
Section 20. “Comparator Voltage Reference (CVREF)” (DS60001109)
Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107)
Section 22. “12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter
(ADC)” (DS60001344)
Section 23. “Serial Peripheral Interface (SPI)” (DS60001106)
Section 24. “Inter-Integrated Circuit (I2C)” (DS60001116)
Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125)
Section 31. “Direct Memory Access (DMA) Controller” (DS60001117)
Section 32. “Configuration” (DS60001124)
Section 33. “Programming and Diagnostics” (DS60001129)
Section 34. “Controller Area Network (CAN)” (DS60001154)
Section 35. “Ethernet Controller” (DS60001155)
Section 41. “Prefetch Module for Devices with L1 CPU Cache” (DS60001183)
Section 42. “Oscillators with Enhanced PLL” (DS60001250)
Section 46. “Serial Quad Interface (SQI)” (DS60001244)
Section 47. “External Bus Interface (EBI)” (DS60001245)
Section 48. “Memory Organization and Permissions” (DS60001214)
Section 49. “Crypto Engine (CE) and Random Number Generator (RNG)” (DS60001246)
Section 50. “CPU for Devices with MIPS32® microAptiv™ and M-Class Cores” (DS60001192)
Section 51. “Hi-Speed USB with On-The-Go (OTG)” (DS60001326)
Section 52. “Flash Program Memory with Support for Live Update” (DS60001193)
2015-2016 Microchip Technology Inc.
DS60001320D-page 13
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
NOTES:
DS60001320D-page 14
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
1.0
DEVICE OVERVIEW
Note:
This data sheet contains device-specific information for
PIC32MZ EF devices.
This data sheet summarizes the features
of the PIC32MZ EF family of devices. It is
not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC32
Family Reference Manual”, which is available from the Microchip web site
(www.microchip.com/PIC32).
FIGURE 1-1:
Figure 1-1 illustrates a general block diagram of the
core and peripheral modules in the PIC32MZ EF family
of devices.
Table 1-21 through Table 1-22 list the pinout I/O
descriptions for the pins shown in the device pin tables
(see Table 2 through Table 5).
PIC32MZ EF FAMILY BLOCK DIAGRAM
OSC2/CLKO
OSC1/CLKI
POSC/SOSC
Oscillators
FRC/LPRC
Oscillators
DIVIDERS
PLL-USB
Power-on
Reset
PBCLKx
Timing
Generation
PORTA
Watchdog
Timer
SYSCLK
6
MCLR
Oscillator
Start-up Timer
Precision
Band Gap
Reference
PLL
VDD, VSS
Power-up
Timer
Voltage
Regulator
PORTB
PORTC
Brown-out
Reset
PORTD
PORTE
PORTF
EVIC
PORTH
PORTJ
Ethernet
Controller
CAN1
CAN2
I-Cache D-Cache
SQI
DMAC
MIPS32®
M-Class Core
HS USB
INT
CRYPTO
EJTAG
PORTG
PORTK
Peripheral
Bus 5
System Bus I/F
I1,
I2
I3, I5, I14 T12 I12, T11 I7 T10
I4 I6
I11
I10
I8
I9
T9
Peripheral
Bus 4
T8
System Bus
Peripheral Bus 1
CFG
PPS
ICD
WDT
DMT
RTCC
Note:
Flash
Controller
T1
Flash
Prefetch
Cache
T2
T3
Data
Ram
Bank 1
Data
Ram
Bank 2
T4
T13
T6
Peripheral
Bus 2
RNG
I13
EBI
T5
T7
Peripheral
Bus 3
Timer1-9
128
128
PFM Flash Wrapper
and ECC
140-bit wide
Dual Panel
Flash Memory
CVREF
JTAG
BSCAN
SPI1-6
OC1-9
I2C1-5
IC1-9
UART1-6
Comparator
1-2
PMP
6 S&H
SAR ADC
Not all features are available on all devices. Refer to TABLE 1: “PIC32MZ EF Family Features” for the list of features by device.
2015-2016 Microchip Technology Inc.
DS60001320D-page 15
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-1:
ADC PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
AN0
16
25
A18
36
I
Analog
AN1
15
24
A17
35
I
Analog
AN2
14
23
A16
34
I
Analog
AN3
13
22
A14
31
I
Analog
AN4
12
21
A13
26
I
Analog
AN5
23
34
B19
49
I
Analog
AN6
24
35
A24
50
I
Analog
AN7
27
41
A27
59
I
Analog
AN8
28
42
B23
60
I
Analog
Pin Name
AN9
29
43
A28
61
I
Analog
AN10
30
44
B24
62
I
Analog
AN11
10
16
B9
21
I
Analog
AN12
6
12
B7
16
I
Analog
AN13
5
11
A8
15
I
Analog
AN14
4
10
B6
14
I
Analog
AN15
3
5
A4
5
I
Analog
AN16
2
4
B2
4
I
Analog
AN17
1
3
A3
3
I
Analog
AN18
64
100
A67
144
I
Analog
AN19
—
9
A7
13
I
Analog
AN20
—
8
B5
12
I
Analog
AN21
—
7
A6
11
I
Analog
AN22
—
6
B3
6
I
Analog
AN23
—
1
A2
1
I
Analog
AN24
—
17
A11
22
I
Analog
AN25
—
18
B10
23
I
Analog
AN26
—
19
A12
24
I
Analog
AN27
—
28
B15
39
I
Analog
AN28
—
29
A20
40
I
Analog
AN29
—
38
B21
56
I
Analog
AN30
—
39
A26
57
I
Analog
AN31
—
40
B22
58
I
Analog
AN32
—
47
B27
69
I
Analog
AN33
—
48
A32
70
I
Analog
AN34
—
2
B1
2
I
Analog
AN35
—
—
A5
7
I
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001320D-page 16
Description
Analog Input Channels
Analog
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-1:
ADC PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
AN36
—
—
B4
8
I
Analog
AN37
—
—
B12
27
I
Analog
AN38
—
—
B17
43
I
Analog
AN39
—
—
A22
44
I
Analog
AN40
—
—
A30
65
I
Analog
AN41
—
—
B26
66
I
Analog
AN42
—
—
A31
67
I
Analog
AN45
11
20
B11
25
I
Analog
AN46
17
26
B14
37
I
Analog
AN47
18
27
A19
38
I
Analog
AN48
21
32
B18
47
I
Analog
AN49
22
33
A23
48
I
Pin Name
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2016 Microchip Technology Inc.
Description
Analog Input Channels
Analog
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001320D-page 17
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-2:
OSCILLATOR PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
CLKI
31
49
B28
71
I
CLKO
32
50
A33
72
O
OSC1
31
49
B28
71
I
OSC2
32
50
A33
72
O
SOSCI
47
72
B41
105
I
Pin Name
SOSCO
48
73
A49
106
REFCLKI1
PPS
PPS
PPS
PPS
REFCLKI3
PPS
PPS
PPS
PPS
REFCLKI4
PPS
PPS
PPS
PPS
REFCLKO1
PPS
PPS
PPS
PPS
REFCLKO3
PPS
PPS
PPS
PPS
REFCLKO4
PPS
PPS
PPS
PPS
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-3:
O
I
I
I
O
O
O
Buffer
Type
Description
ST/CMOS External clock source input. Always associated with
OSC1 pin function.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions
as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
ST/CMOS Oscillator crystal input. ST buffer when configured in
RC mode; CMOS otherwise.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions
as CLKO in RC and EC modes.
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS
otherwise.
—
32.768 low-power oscillator crystal output.
—
Reference Clock Generator Inputs 1-4
—
—
—
Reference Clock Generator Outputs 1-4
—
—
Analog = Analog input
P = Power
O = Output
I = Input
PPS = Peripheral Pin Select
IC1 THROUGH IC9 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
IC1
PPS
PPS
PPS
PPS
I
ST
IC2
PPS
PPS
PPS
PPS
I
ST
IC3
PPS
PPS
PPS
PPS
I
ST
IC4
PPS
PPS
PPS
PPS
I
ST
IC5
PPS
PPS
PPS
PPS
I
ST
IC6
PPS
PPS
PPS
PPS
I
ST
IC7
PPS
PPS
PPS
PPS
I
ST
IC8
PPS
PPS
PPS
PPS
I
ST
IC9
PPS
PPS
PPS
PPS
I
Pin Name
Description
Input Capture
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001320D-page 18
Input Capture Inputs 1-9
ST
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-4:
OC1 THROUGH OC9 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
OC1
PPS
PPS
PPS
PPS
O
—
OC2
PPS
PPS
PPS
PPS
O
—
OC3
PPS
PPS
PPS
PPS
O
—
OC4
PPS
PPS
PPS
PPS
O
—
OC5
PPS
PPS
PPS
PPS
O
—
OC6
PPS
PPS
PPS
PPS
O
—
OC7
PPS
PPS
PPS
PPS
O
—
OC8
PPS
PPS
PPS
PPS
O
—
OC9
PPS
PPS
PPS
PPS
O
—
OCFA
PPS
PPS
PPS
PPS
I
ST
Output Compare Fault A Input
OCFB
30
44
B24
62
I
ST
Output Compare Fault B Input
Pin Name
Description
Output Compare
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-5:
Output Compare Outputs 1-9
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
EXTERNAL INTERRUPTS PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
INT0
46
71
A48
104
I
ST
External Interrupt 0
INT1
PPS
PPS
PPS
PPS
I
ST
External Interrupt 1
INT2
PPS
PPS
PPS
PPS
I
ST
External Interrupt 2
INT3
PPS
PPS
PPS
PPS
I
ST
External Interrupt 3
INT4
PPS
PPS
PPS
PPS
I
ST
External Interrupt 4
Pin Name
Description
External Interrupts
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2016 Microchip Technology Inc.
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001320D-page 19
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-6:
PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
RA0
—
17
A11
22
I/O
ST
RA1
—
38
B21
56
I/O
ST
RA2
—
59
A41
85
I/O
ST
RA3
—
60
B34
86
I/O
ST
RA4
—
61
A42
87
I/O
ST
RA5
—
2
B1
2
I/O
ST
RA6
—
89
A61
129
I/O
ST
Pin Name
Buffer
Type
Description
PORTA
RA7
—
90
B51
130
I/O
ST
RA9
—
28
B15
39
I/O
ST
RA10
—
29
A20
40
I/O
ST
RA14
—
66
B37
95
I/O
ST
RA15
—
67
A45
96
I/O
ST
PORTA is a bidirectional I/O port
PORTB
RB0
16
25
A18
36
I/O
ST
RB1
15
24
A17
35
I/O
ST
RB2
14
23
A16
34
I/O
ST
RB3
13
22
A14
31
I/O
ST
RB4
12
21
A13
26
I/O
ST
RB5
11
20
B11
25
I/O
ST
RB6
17
26
B14
37
I/O
ST
RB7
18
27
A19
38
I/O
ST
RB8
21
32
B18
47
I/O
ST
RB9
22
33
A23
48
I/O
ST
RB10
23
34
B19
49
I/O
ST
RB11
24
35
A24
50
I/O
ST
RB12
27
41
A27
59
I/O
ST
RB13
28
42
B23
60
I/O
ST
RB14
29
43
A28
61
I/O
ST
RB15
30
44
B24
62
I/O
ST
PORTB is a bidirectional I/O port
PORTC
RC1
—
6
B3
6
I/O
ST
RC2
—
7
A6
11
I/O
ST
RC3
—
8
B5
12
I/O
ST
RC4
—
9
A7
13
I/O
ST
RC12
31
49
B28
71
I/O
ST
RC13
47
72
B41
105
I/O
ST
RC14
48
73
A49
106
I/O
ST
RC15
32
50
A33
72
I/O
ST
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001320D-page 20
PORTC is a bidirectional I/O port
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-6:
PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
RD0
46
71
A48
104
I/O
ST
RD1
49
76
A52
109
I/O
ST
Pin Name
Buffer
Type
Description
PORTD
RD2
50
77
B42
110
I/O
ST
RD3
51
78
A53
111
I/O
ST
RD4
52
81
A56
118
I/O
ST
RD5
53
82
B46
119
I/O
ST
RD6
—
—
A57
120
I/O
ST
ST
RD7
—
—
B47
121
I/O
RD9
43
68
B38
97
I/O
ST
RD10
44
69
A46
98
I/O
ST
RD11
45
70
B39
99
I/O
ST
RD12
—
79
B43
112
I/O
ST
RD13
—
80
A54
113
I/O
ST
RD14
—
47
B27
69
I/O
ST
RD15
—
48
A32
70
I/O
ST
PORTD is a bidirectional I/O port
PORTE
RE0
58
91
B52
135
I/O
ST
RE1
61
94
A64
138
I/O
ST
RE2
62
98
A66
142
I/O
ST
RE3
63
99
B56
143
I/O
ST
RE4
64
100
A67
144
I/O
ST
RE5
1
3
A3
3
I/O
ST
RE6
2
4
B2
4
I/O
ST
RE7
3
5
A4
5
I/O
ST
RE8
—
18
B10
23
I/O
ST
RE9
—
19
A12
24
I/O
PORTE is a bidirectional I/O port
ST
PORTF
RF0
56
85
A59
124
I/O
ST
RF1
57
86
B49
125
I/O
ST
RF2
—
57
B31
79
I/O
ST
RF3
38
56
A38
78
I/O
ST
RF4
41
64
B36
90
I/O
ST
RF5
42
65
A44
91
I/O
ST
RF8
—
58
A39
80
I/O
ST
RF12
—
40
B22
58
I/O
ST
—
39
A26
57
I/O
RF13
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2016 Microchip Technology Inc.
PORTF is a bidirectional I/O port
ST
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001320D-page 21
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-6:
PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
RG0
—
88
B50
128
I/O
ST
RG1
—
87
A60
127
I/O
ST
RG6
4
10
B6
14
I/O
ST
RG7
5
11
A8
15
I/O
ST
RG8
6
12
B7
16
I/O
ST
RG9
10
16
B9
21
I/O
ST
RG12
—
96
A65
140
I/O
ST
RG13
—
97
B55
141
I/O
ST
RG14
—
95
B54
139
I/O
ST
RG15
—
1
A2
1
I/O
ST
RH0
—
—
B17
43
I/O
ST
RH1
—
—
A22
44
I/O
ST
RH2
—
—
—
45
I/O
ST
RH3
—
—
—
46
I/O
ST
RH4
—
—
A30
65
I/O
ST
RH5
—
—
B26
66
I/O
ST
RH6
—
—
A31
67
I/O
ST
RH7
—
—
—
68
I/O
ST
RH8
—
—
B32
81
I/O
ST
Pin Name
Buffer
Type
Description
PORTG
PORTG is a bidirectional I/O port
PORTH
RH9
—
—
A40
82
I/O
ST
RH10
—
—
B33
83
I/O
ST
RH11
—
—
—
84
I/O
ST
RH12
—
—
A47
100
I/O
ST
RH13
—
—
B40
101
I/O
ST
RH14
—
—
—
102
I/O
ST
RH15
—
—
—
103
I/O
PORTH is a bidirectional I/O port
ST
PORTJ
RJ0
—
—
B44
114
I/O
ST
RJ1
—
—
A55
115
I/O
ST
RJ2
—
—
B45
116
I/O
ST
RJ3
—
—
—
117
I/O
ST
RJ4
—
—
A62
131
I/O
ST
RJ5
—
—
—
132
I/O
ST
RJ6
—
—
—
133
I/O
ST
RJ7
—
—
—
134
I/O
ST
RJ8
—
—
A5
7
I/O
ST
RJ9
—
—
B4
8
I/O
ST
RJ10
—
—
—
10
I/O
ST
RJ11
—
—
B12
27
I/O
ST
RJ12
—
—
—
9
I/O
ST
RJ13
—
—
—
28
I/O
ST
RJ14
—
—
—
29
I/O
ST
RJ15
—
—
—
30
I/O
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001320D-page 22
PORTJ is a bidirectional I/O port
ST
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-6:
PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
RK0
—
—
—
19
I/O
ST
RK1
—
—
—
51
I/O
ST
RK2
—
—
—
52
I/O
ST
RK3
—
—
—
53
I/O
ST
RK4
—
—
—
92
I/O
ST
RK5
—
—
—
93
I/O
ST
RK6
—
—
—
94
I/O
ST
RK7
—
—
—
126
I/O
Pin Name
Buffer
Type
Description
PORTK
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2016 Microchip Technology Inc.
PORTK is a bidirectional I/O port
ST
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001320D-page 23
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-7:
TIMER1 THROUGH TIMER9 AND RTCC PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
T1CK
48
73
A49
106
I
ST
Timer1 External Clock Input
T2CK
PPS
PPS
PPS
PPS
I
ST
Timer2 External Clock Input
T3CK
PPS
PPS
PPS
PPS
I
ST
Timer3 External Clock Input
T4CK
PPS
PPS
PPS
PPS
I
ST
Timer4 External Clock Input
T5CK
PPS
PPS
PPS
PPS
I
ST
Timer5 External Clock Input
T6CK
PPS
PPS
PPS
PPS
I
ST
Timer6 External Clock Input
T7CK
PPS
PPS
PPS
PPS
I
ST
Timer7 External Clock Input
T8CK
PPS
PPS
PPS
PPS
I
ST
Timer8 External Clock Input
T9CK
PPS
PPS
PPS
PPS
I
ST
Timer9 External Clock Input
Pin Name
Description
Timer1 through Timer9
Real-Time Clock and Calendar
RTCC
Legend:
46
71
A48
104
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001320D-page 24
O
—
Real-Time Clock Alarm/Seconds Output
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-8:
UART1 THROUGH UART6 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
U1RX
PPS
PPS
PPS
PPS
I
ST
U1TX
PPS
PPS
PPS
PPS
O
—
UART1 Transmit
U1CTS
PPS
PPS
PPS
PPS
I
ST
UART1 Clear to Send
U1RTS
PPS
PPS
PPS
PPS
O
—
UART1 Ready to Send
Pin Name
144-pin
TQFP/
LQFP
Description
Universal Asynchronous Receiver Transmitter 1
UART1 Receive
Universal Asynchronous Receiver Transmitter 2
U2RX
PPS
PPS
PPS
PPS
I
ST
U2TX
PPS
PPS
PPS
PPS
O
—
UART2 Receive
UART2 Transmit
U2CTS
PPS
PPS
PPS
PPS
I
ST
UART2 Clear To Send
U2RTS
PPS
PPS
PPS
PPS
O
—
UART2 Ready To Send
Universal Asynchronous Receiver Transmitter 3
U3RX
PPS
PPS
PPS
PPS
I
ST
U3TX
PPS
PPS
PPS
PPS
O
—
UART3 Receive
UART3 Transmit
U3CTS
PPS
PPS
PPS
PPS
I
ST
UART3 Clear to Send
U3RTS
PPS
PPS
PPS
PPS
O
—
UART3 Ready to Send
Universal Asynchronous Receiver Transmitter 4
U4RX
PPS
PPS
PPS
PPS
I
ST
U4TX
PPS
PPS
PPS
PPS
O
—
UART4 Receive
UART4 Transmit
U4CTS
PPS
PPS
PPS
PPS
I
ST
UART4 Clear to Send
U4RTS
PPS
PPS
PPS
PPS
O
—
UART4 Ready to Send
Universal Asynchronous Receiver Transmitter 5
U5RX
PPS
PPS
PPS
PPS
I
ST
U5TX
PPS
PPS
PPS
PPS
O
—
UART5 Receive
UART5 Transmit
U5CTS
PPS
PPS
PPS
PPS
I
ST
UART5 Clear to Send
U5RTS
PPS
PPS
PPS
PPS
O
—
UART5 Ready to Send
Universal Asynchronous Receiver Transmitter 6
U6RX
PPS
PPS
PPS
PPS
I
ST
U6TX
PPS
PPS
PPS
PPS
O
—
UART6 Transmit
U6CTS
PPS
PPS
PPS
PPS
I
ST
UART6 Clear to Send
PPS
PPS
PPS
PPS
O
—
UART6 Ready to Send
U6RTS
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2016 Microchip Technology Inc.
UART6 Receive
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001320D-page 25
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-9:
SPI1 THROUGH SPI 6 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
SCK1
49
76
A52
109
I/O
ST
SPI1 Synchronous Serial Clock Input/Output
SDI1
PPS
PPS
PPS
PPS
I
ST
SPI1 Data In
SDO1
PPS
PPS
PPS
PPS
O
—
SPI1 Data Out
SS1
PPS
PPS
PPS
PPS
I/O
ST
SPI1 Slave Synchronization Or Frame Pulse I/O
Pin Name
Description
Serial Peripheral Interface 1
Serial Peripheral Interface 2
SCK2
4
10
B6
14
I/O
ST
SPI2 Synchronous Serial Clock Input/output
SDI2
PPS
PPS
PPS
PPS
I
ST
SPI2 Data In
SDO2
PPS
PPS
PPS
PPS
O
—
SPI2 Data Out
SS2
PPS
PPS
PPS
PPS
I/O
ST
SPI2 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 3
SCK3
29
43
A28
61
I/O
ST
SPI3 Synchronous Serial Clock Input/Output
SDI3
PPS
PPS
PPS
PPS
I
ST
SPI3 Data In
SDO3
PPS
PPS
PPS
PPS
O
—
SPI3 Data Out
SS3
PPS
PPS
PPS
PPS
I/O
ST
SPI3 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 4
SCK4
44
69
A46
98
I/O
ST
SPI4 Synchronous Serial Clock Input/Output
SDI4
PPS
PPS
PPS
PPS
I
ST
SPI4 Data In
SDO4
PPS
PPS
PPS
PPS
O
—
SPI4 Data Out
SS4
PPS
PPS
PPS
PPS
I/O
ST
SPI4 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 5
SCK5
—
39
A26
57
I/O
ST
SPI5 Synchronous Serial Clock Input/Output
SDI5
—
PPS
PPS
PPS
I
ST
SPI5 Data In
SDO5
—
PPS
PPS
PPS
O
—
SPI5 Data Out
SS5
—
PPS
PPS
PPS
I/O
ST
SPI5 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 6
SCK6
—
48
A32
70
I/O
ST
SPI6 Synchronous Serial Clock Input/Output
SDI6
—
PPS
PPS
PPS
I
ST
SPI6 Data In
SDO6
—
PPS
PPS
PPS
O
—
SPI6 Data Out
SS6
—
PPS
PPS
PPS
I/O
ST
SPI6 Slave Synchronization Or Frame Pulse I/O
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001320D-page 26
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-10:
I2C1 THROUGH I2C5 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
SCL1
44
66
B37
95
I/O
ST
I2C1 Synchronous Serial Clock Input/Output
SDA1
43
67
A45
96
I/O
ST
I2C1 Synchronous Serial Data Input/Output
Pin Name
Description
Inter-Integrated Circuit 1
Inter-Integrated Circuit 2
SCL2
—
59
A41
85
I/O
ST
I2C2 Synchronous Serial Clock Input/Output
SDA2
—
60
B34
86
I/O
ST
I2C2 Synchronous Serial Data Input/Output
Inter-Integrated Circuit 3
SCL3
51
58
A39
80
I/O
ST
I2C3 Synchronous Serial Clock Input/Output
SDA3
50
57
B31
79
I/O
ST
I2C3 Synchronous Serial Data Input/Output
Inter-Integrated Circuit 4
SCL4
6
12
B7
16
I/O
ST
I2C4 Synchronous Serial Clock Input/Output
SDA4
5
11
A8
15
I/O
ST
I2C4 Synchronous Serial Data Input/Output
Inter-Integrated Circuit 5
SCL5
42
65
A44
91
I/O
ST
I2C5 Synchronous Serial Clock Input/Output
SDA5
41
64
B36
90
I/O
ST
I2C5 Synchronous Serial Data Input/Output
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-11:
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
COMPARATOR 1, COMPARATOR 2 AND CVREF PINOUT I/O DESCRIPTIONS
Pin Number
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
CVREF+
16
29
A20
40
I
Analog
Comparator Voltage Reference (High) Input
CVREF-
15
28
B15
39
I
Analog
Comparator Voltage Reference (Low) Input
CVREFOUT
23
34
B19
49
O
Analog
Comparator Voltage Reference Output
Pin Name
Description
Comparator Voltage Reference
Comparator 1
C1INA
11
20
B11
25
I
Analog
Comparator 1 Positive Input
C1INB
12
21
A13
26
I
Analog
Comparator 1 Selectable Negative Input
C1INC
5
11
A8
15
I
Analog
C1IND
4
10
B6
14
I
Analog
C1OUT
PPS
PPS
PPS
PPS
O
—
Comparator 1 Output
Comparator 2
C2INA
13
22
A14
31
I
Analog
Comparator 2 Positive Input
C2INB
14
23
A16
34
I
Analog
Comparator 2 Selectable Negative Input
C2INC
10
16
B9
21
I
Analog
Analog
C2IND
6
12
B7
16
I
C2OUT
PPS
PPS
PPS
PPS
O
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2016 Microchip Technology Inc.
—
Comparator 2 Output
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001320D-page 27
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-12:
PMP PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
PMA0
30
44
B24
30
I/O
TTL/ST
Parallel Master Port Address bit 0 Input (Buffered
Slave modes) and Output (Master modes)
PMA1
29
43
A28
51
I/O
TTL/ST
Parallel Master Port Address bit 1 Input (Buffered
Slave modes) and Output (Master modes)
PMA2
10
16
B9
21
O
—
PMA3
6
12
B7
52
O
—
PMA4
5
11
A8
68
O
—
PMA5
4
2
B1
2
O
—
PMA6
16
6
B3
6
O
—
PMA7
22
33
A23
48
O
—
PMA8
42
65
A44
91
O
—
PMA9
41
64
B36
90
O
—
PMA10
21
32
B18
47
O
—
PMA11
27
41
A27
29
O
—
PMA12
24
7
A6
11
O
—
PMA13
23
34
B19
28
O
—
PMA14
45
61
A42
87
O
—
PMA15
43
68
B38
97
O
—
PMCS1
45
61
A42
87
O
—
PMCS2
43
68
B38
97
O
—
PMD0
58
91
B52
135
I/O
TTL/ST
PMD1
61
94
A64
138
I/O
TTL/ST
PMD2
62
98
A66
142
I/O
TTL/ST
PMD3
63
99
B56
143
I/O
TTL/ST
PMD4
64
100
A67
144
I/O
TTL/ST
PMD5
1
3
A3
3
I/O
TTL/ST
PMD6
2
4
B2
4
I/O
TTL/ST
PMD7
3
5
A4
5
I/O
TTL/ST
PMD8
—
88
B50
128
I/O
TTL/ST
Pin Name
Description
Parallel Master Port Address (Demultiplexed Master
modes)
Parallel Master Port Chip Select 1 Strobe
Parallel Master Port Chip Select 2 Strobe
Parallel Master Port Data (Demultiplexed Master
mode) or Address/Data (Multiplexed Master modes)
PMD9
—
87
A60
127
I/O
TTL/ST
PMD10
—
86
B49
125
I/O
TTL/ST
PMD11
—
85
A59
124
I/O
TTL/ST
PMD12
—
79
B43
112
I/O
TTL/ST
PMD13
—
80
A54
113
I/O
TTL/ST
PMD14
—
77
B42
110
I/O
TTL/ST
PMD15
—
78
A53
111
I/O
TTL/ST
PMALL
30
44
B24
30
O
—
Parallel Master Port Address Latch Enable Low Byte
(Multiplexed Master modes)
PMALH
29
43
A28
51
O
—
Parallel Master Port Address Latch Enable High Byte
(Multiplexed Master modes)
PMRD
53
9
A7
13
O
—
Parallel Master Port Read Strobe
PMWR
52
8
B5
12
O
—
Parallel Master Port Write Strobe
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001320D-page 28
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-13:
EBI PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
EBIA0
—
44
B24
30
O
—
EBIA1
—
43
A28
51
O
—
EBIA2
—
16
B9
21
O
—
EBIA3
—
12
B7
52
O
—
EBIA4
—
11
A8
68
O
—
EBIA5
—
2
B1
2
O
—
EBIA6
—
6
B3
6
O
—
EBIA7
—
33
A23
48
O
—
EBIA8
—
65
A44
91
O
—
EBIA9
—
64
B36
90
O
—
EBIA10
—
32
B18
47
O
—
EBIA11
—
41
A27
29
O
—
EBIA12
—
7
A6
11
O
—
EBIA13
—
34
B19
28
O
—
EBIA14
—
61
A42
87
O
—
EBIA15
—
68
B38
97
O
—
EBIA16
—
17
A11
19
O
—
EBIA17
—
40
B22
53
O
—
EBIA18
—
39
A26
92
O
—
EBIA19
—
38
B21
93
O
—
EBIA20
—
—
—
94
O
—
EBIA21
—
—
—
126
O
—
EBIA22
—
—
—
117
O
—
EBIA23
—
—
—
103
O
—
EBID0
—
91
B52
135
I/O
ST
EBID1
—
94
A64
138
I/O
ST
EBID2
—
98
A66
142
I/O
ST
EBID3
—
99
B56
143
I/O
ST
EBID4
—
100
A67
144
I/O
ST
EBID5
—
3
A3
3
I/O
ST
EBID6
—
4
B2
4
I/O
ST
EBID7
—
5
A4
5
I/O
ST
EBID8
—
88
B50
128
I/O
ST
Pin Name
EBID9
—
87
A60
127
I/O
ST
EBID10
—
86
B49
125
I/O
ST
EBID11
—
85
A59
124
I/O
ST
EBID12
—
79
B43
112
I/O
ST
EBID13
—
80
A54
113
I/O
ST
EBID14
—
77
B42
110
I/O
ST
EBID15
—
78
A53
111
I/O
ST
EBIBS0
—
—
—
9
O
—
EBIBS1
—
—
—
10
O
—
EBICS0
—
59
A41
131
O
—
EBICS1
—
—
—
132
O
—
EBICS2
—
—
—
133
O
—
EBICS3
—
—
—
134
O
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2016 Microchip Technology Inc.
Description
External Bus Interface Address Bus
External Bus Interface Data I/O Bus
External Bus Interface Byte Select
External Bus Interface Chip Select
—
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001320D-page 29
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-13:
EBI PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
Description
EBIOE
—
9
A7
13
O
—
External Bus Interface Output Enable
EBIRDY1
—
60
B34
86
I
ST
External Bus Interface Ready Input
EBIRDY2
—
58
A39
84
I
ST
EBIRDY3
—
57
B45
116
I
ST
EBIRP
—
—
—
45
O
—
External Bus Interface Flash Reset Pin
EBIWE
—
8
B5
12
O
—
External Bus Interface Write Enable
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001320D-page 30
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-14:
USB PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
73
I
Analog
74
P
—
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
VBUS
33
51
A35
VUSB3V3
34
52
A36
Pin Name
Description
USB bus power monitor
USB internal transceiver supply. If the USB module is
not used, this pin must be connected to VSS. When
connected, the shared pin functions on USBID will not
be available.
D+
37
55
B30
77
I/O
Analog
USB D+
D-
36
54
A37
76
I/O
Analog
USB D-
38
56
A38
78
I
USBID
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-15:
ST
USB OTG ID detect
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
CAN1 AND CAN2 PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
C1TX
PPS
PPS
PPS
PPS
O
—
CAN1 Bus Transmit Pin
C1RX
PPS
PPS
PPS
PPS
I
ST
CAN1 Bus Receive Pin
C2TX
PPS
PPS
PPS
PPS
O
—
CAN2 Bus Transmit Pin
C2RX
PPS
PPS
PPS
PPS
I
ST
CAN2 Bus Receive Pin
Pin Name
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2016 Microchip Technology Inc.
Buffer
Type
Description
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001320D-page 31
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-16:
ETHERNET MII I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
ERXD0
61
41
B32
81
I
ST
Ethernet Receive Data 0
ERXD1
58
42
B26
66
I
ST
Ethernet Receive Data 1
ERXD2
57
43
A31
67
I
ST
Ethernet Receive Data 2
ERXD3
56
44
A40
82
I
ST
Ethernet Receive Data 3
ERXERR
64
35
A30
65
I
ST
Ethernet Receive Error Input
Pin Name
Description
ERXDV
62
12
B40
101
I
ST
Ethernet Receive Data Valid
ERXCLK
63
16
B12
27
I
ST
Ethernet Receive Clock
ETXD0
2
86
A5
7
O
—
Ethernet Transmit Data 0
ETXD1
3
85
B4
8
O
—
Ethernet Transmit Data 1
ETXD2
43
79
B17
43
O
—
Ethernet Transmit Data 2
ETXD3
46
80
A22
44
O
—
Ethernet Transmit Data 3
ETXERR
50
87
B44
114
O
—
Ethernet Transmit Error
ETXEN
1
77
A57
120
O
—
Ethernet Transmit Enable
ETXCLK
51
78
B47
121
I
ST
Ethernet Transmit Clock
ECOL
44
10
B33
83
I
ST
Ethernet Collision Detect
ECRS
45
11
A47
100
I
ST
Ethernet Carrier Sense
EMDC
30
70
B39
99
O
—
Ethernet Management Data Clock
EMDIO
49
71
A55
115
I/O
—
Ethernet Management Data
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-17:
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
ETHERNET RMII PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
ERXD0
61
41
B32
81
I
ST
Ethernet Receive Data 0
ERXD1
58
42
B26
66
I
ST
Ethernet Receive Data 1
ERXERR
64
35
A30
65
I
ST
Ethernet Receive Error Input
ETXD0
2
86
A5
7
O
—
Ethernet Transmit Data 0
ETXD1
3
85
B4
8
O
—
Ethernet Transmit Data 1
ETXEN
1
77
A57
120
O
—
Ethernet Transmit Enable
EMDC
30
70
B39
99
O
—
Ethernet Management Data Clock
EMDIO
49
71
A55
115
I/O
—
Ethernet Management Data
EREFCLK
63
16
B12
27
I
ST
Ethernet Reference Clock
ECRSDV
62
12
B40
101
I
ST
Ethernet Carrier Sense Data Valid
Pin Name
Description
Ethernet MII Interface
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001320D-page 32
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-18:
ALTERNATE ETHERNET MII PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
AERXD0
—
18
—
—
I
ST
Alternate Ethernet Receive Data 0
AERXD1
—
19
—
—
I
ST
Alternate Ethernet Receive Data 1
AERXD2
—
28
—
—
I
ST
Alternate Ethernet Receive Data 2
AERXD3
—
29
—
—
I
ST
Alternate Ethernet Receive Data 3
AERXERR
—
1
—
—
I
ST
Alternate Ethernet Receive Error Input
AERXDV
—
12
—
—
I
ST
Alternate Ethernet Receive Data Valid
AERXCLK
—
16
—
—
I
ST
Alternate Ethernet Receive Clock
AETXD0
—
47
—
—
O
—
Alternate Ethernet Transmit Data 0
AETXD1
—
48
—
—
O
—
Alternate Ethernet Transmit Data 1
AETXD2
—
44
—
—
O
—
Alternate Ethernet Transmit Data 2
AETXD3
—
43
—
—
O
—
Alternate Ethernet Transmit Data 3
AETXERR
—
35
—
—
O
—
Alternate Ethernet Transmit Error
Pin Name
Description
AECOL
—
42
—
—
I
ST
Alternate Ethernet Collision Detect
AECRS
—
41
—
—
I
ST
Alternate Ethernet Carrier Sense
AETXCLK
—
66
—
—
I
ST
Alternate Ethernet Transmit Clock
AEMDC
—
70
—
—
O
—
Alternate Ethernet Management Data Clock
AEMDIO
—
71
—
—
I/O
—
Alternate Ethernet Management Data
AETXEN
—
67
—
—
O
—
Alternate Ethernet Transmit Enable
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-19:
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
ALTERNATE ETHERNET RMII PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
AERXD0
43
18
—
—
I
ST
Alternate Ethernet Receive Data 0
AERXD1
46
19
—
—
I
ST
Alternate Ethernet Receive Data 1
AERXERR
51
1
—
—
I
ST
Alternate Ethernet Receive Error Input
AETXD0
57
47
—
—
O
—
Alternate Ethernet Transmit Data 0
AETXD1
56
48
—
—
O
—
Alternate Ethernet Transmit Data 1
AEMDC
30
70
—
—
O
—
Alternate Ethernet Management Data Clock
AEMDIO
49
71
—
—
I/O
—
Alternate Ethernet Management Data
AETXEN
50
67
—
—
O
—
Alternate Ethernet Transmit Enable
AEREFCLK
45
16
—
—
I
ST
Alternate Ethernet Reference Clock
AECRSDV
62
12
—
—
I
ST
Alternate Ethernet Carrier Sense Data Valid
Pin Name
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2016 Microchip Technology Inc.
Description
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001320D-page 33
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-20:
SQI1 PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
SQICLK
57
89
A61
129
O
—
Serial Quad Interface Clock
SQICS0
52
81
A56
118
O
—
Serial Quad Interface Chip Select 0
SQICS1
53
82
B46
119
O
—
Serial Quad Interface Chip Select 1
SQID0
58
97
B55
141
I/O
ST
Serial Quad Interface Data 0
SQID1
61
96
A65
140
I/O
ST
Serial Quad Interface Data 1
SQID2
62
95
B54
139
I/O
ST
Serial Quad Interface Data 2
SQID3
63
90
B51
130
I/O
ST
Serial Quad Interface Data 3
Pin Name
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-21:
Description
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
POWER, GROUND, AND VOLTAGE REFERENCE PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
AVDD
AVSS
VDD
VSS
VREF+
VREFLegend:
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
Buffer
Type
Description
Power and Ground
P
P
Positive supply for analog modules. This pin must be
connected at all times.
20
31
A21
42
P
P
Ground reference for analog modules. This pin must
be connected at all times
8, 26, 39, 14, 37, B8, A15, 18, 33,
P
—
Positive supply for peripheral logic and I/O pins. This
pin must be connected at all times.
54, 60
46, 62,
A25,
55, 64,
74, 83, 93
B25,
88, 107,
B35,
122, 137
A50,
A58, B53
7, 25, 35, 13, 36, A9, B13, 17, 32,
P
—
Ground reference for logic, I/O pins, and USB. This pin
must be connected at all times.
40, 55, 59 45, 53,
B20,
54, 63,
63, 75,
B29,
75, 89,
84, 92
A29,
108,
A43,
123, 136
A51,
B48, A63
Voltage Reference
16
29
A20
40
I
Analog Analog Voltage Reference (High) Input
15
28
B15
39
I
Analog Analog Voltage Reference (Low) Input
CMOS = CMOS-compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = Transistor-transistor Logic input buffer
PPS = Peripheral Pin Select
19
DS60001320D-page 34
30
B16
41
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 1-22:
JTAG, TRACE, AND PROGRAMMING/DEBUGGING PINOUT I/O DESCRIPTIONS
Pin Number
64-pin
QFN/
TQFP
100-pin
TQFP
124-pin
VTLA
144-pin
TQFP/
LQFP
Pin
Type
TCK
27
38
B21
56
I
ST
TDI
28
39
A26
57
I
ST
JTAG Test Data Input Pin
TDO
24
40
B22
58
O
—
JTAG Test Data Output Pin
TMS
23
17
A11
22
I
ST
JTAG Test Mode Select Pin
Pin Name
Buffer
Type
Description
JTAG
JTAG Test Clock Input Pin
Trace
TRCLK
57
89
A61
129
O
—
Trace Clock
TRD0
58
97
B55
141
O
—
Trace Data bits 0-3
TRD1
61
96
A65
140
O
—
TRD2
62
95
B54
139
O
—
TRD3
63
90
B51
130
O
—
Programming/Debugging
PGED1
16
25
A18
36
I/O
ST
Data I/O pin for Programming/Debugging
Communication Channel 1
PGEC1
15
24
A17
35
I
ST
Clock input pin for Programming/Debugging
Communication Channel 1
PGED2
18
27
A19
38
I/O
ST
Data I/O pin for Programming/Debugging
Communication Channel 2
PGEC2
17
26
B14
37
I
ST
Clock input pin for Programming/Debugging
Communication Channel 2
MCLR
9
15
A10
20
I/P
ST
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2016 Microchip Technology Inc.
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001320D-page 35
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
NOTES:
DS60001320D-page 36
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2.0
GUIDELINES FOR GETTING
STARTED WITH 32-BIT
MICROCONTROLLERS
Note 1: This data sheet summarizes the
features of the PIC32MZ EF family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web site
(www.microchip.com/PIC32).
2.1
Basic Connection Requirements
Getting started with the PIC32MZ EF family of 32-bit
Microcontrollers (MCUs) requires attention to a minimal
set of device pin connections before proceeding with
development. The following is a list of pin names, which
must always be connected:
• All VDD and VSS pins (see 2.2 “Decoupling
Capacitors”)
• All AVDD and AVSS pins, even if the ADC module
is not used (see 2.2 “Decoupling Capacitors”)
• MCLR pin (see 2.3 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins, used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes (see 2.4 “ICSP Pins”)
• OSC1 and OSC2 pins, when external oscillator
source is used (see 2.7 “External Oscillator
Pins”)
The following pin(s) may be required as well:
VREF+/VREF- pins, used when external voltage
reference for the ADC module is implemented.
Note:
The AVDD and AVSS pins must be
connected, regardless of ADC use and
the ADC voltage reference source.
2015-2016 Microchip Technology Inc.
2.2
Decoupling Capacitors
The use of decoupling capacitors on power supply
pins, such as VDD, VSS, AVDD and AVSS is required.
See Figure 2-1.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A value of 0.1 µF
(100 nF), 10-20V is recommended. The capacitor
should be a low Equivalent Series Resistance (lowESR) capacitor and have resonance frequency in
the range of 20 MHz and higher. It is further
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close to
the pins as possible. It is recommended that the
capacitors be placed on the same side of the board
as the device. If space is constricted, the capacitor
can be placed on another layer on the PCB using a
via; however, ensure that the trace length from the
pin to the capacitor is within one-quarter inch
(6 mm) in length.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of tens
of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor.
The value of the second capacitor can be in the
range of 0.01 µF to 0.001 µF. Place this second
capacitor next to the primary decoupling capacitor.
In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the
power and ground pins as possible. For example,
0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first, and
then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally
important is to keep the trace length between the
capacitor and the power pins to a minimum thereby
reducing PCB track inductance.
DS60001320D-page 37
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
RECOMMENDED
MINIMUM CONNECTION
VDD
0.1 µF
Ceramic
VSS
VDD
VDD
VSS
MCLR
VDD
VSS
VDD
C
PIC32
VSS
VSS
VUSB3V3(1)
VDD
VSS
VDD
Connect(2)
VDD
0.1 µF
Ceramic
VSS
VSS
AVSS
AVDD
VDD
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
L1(2)
Note
1:
If the USB module is not used, this pin must be
connected to VSS.
2:
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
Where:
F CNVf = ------------2
1
f = ---------------------- 2 LC
The MCLR pin provides for two specific device
functions:
Pulling The MCLR pin low generates either a device
Reset or a POR, depending on the setting of the
SMCLR bit (DEVCFG0). Figure 2-2 illustrates a
typical MCLR circuit. During device programming
and debugging, the resistance and capacitance that
can be added to the pin must be considered. Device
programmers and debuggers drive the MCLR pin.
Consequently, specific voltage levels (VIH and VIL)
and fast signal transitions must not be adversely
affected. Therefore, specific values of R and C will
need to be adjusted based on the application and
PCB requirements.
For example, as illustrated in Figure 2-2, it is
recommended that the capacitor C be isolated from the
MCLR pin during programming and debugging
operations.
Place the components illustrated in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
R
DS60001320D-page 38
10k
R1(1)
MCLR
0.1 µF(2)
C
1 k
PIC32
BULK CAPACITORS
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
(i.e., ADC conversion rate/2)
2
1
L = ----------------------
2f C
2.2.1
Master Clear (MCLR) Pin
• Device Reset
• Device programming and debugging
R
R1
2.3
ICSP™
FIGURE 2-1:
Note
1
5
4
2
3
6
VDD
VSS
NC
PGECx(3)
PGEDx(3)
1:
470 R1 1k will limit any current flowing into
MCLR from the external capacitor C, in the event of
MCLR pin breakdown, due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS). Ensure that the
MCLR pin VIH and VIL specifications are met without
interfering with the Debug/Programmer tools.
2:
The capacitor can be sized to prevent unintentional
Resets from brief glitches or to extend the device
Reset period during POR.
3:
No pull-ups or bypass capacitors are allowed on
active debug/program PGECx/PGEDx pins.
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2.4
ICSP Pins
2.6
Trace
The PGECx and PGEDx pins are used for ICSP and
debugging purposes. It is recommended to keep the
trace length between the ICSP connector and the
ICSP pins on the device as short as possible. If the
ICSP connector is expected to experience an ESD
event, a series resistor is recommended, with the
value in the range of a few tens of Ohms, not to
exceed 100 Ohms.
The trace pins can be connected to a hardware
trace-enabled programmer to provide a compressed
real-time instruction trace. When used for trace, the
TRD3, TRD2, TRD1, TRD0 and TRCLK pins should
be dedicated for this use. The trace hardware
requires a 22 Ohm series resistor between the trace
pins and the trace connector.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
2.7
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 3 or MPLAB REAL ICE™.
For more information on ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available from the Microchip web
site.
• “Using MPLAB® ICD 3” (poster) (DS50001765)
• “MPLAB® ICD 3 Design Advisory” (DS50001764)
• “MPLAB® REAL ICE™ In-Circuit Debugger
User’s Guide” (DS50001616)
• “Using MPLAB® REAL ICE™ Emulator” (poster)
(DS50001749)
2.5
External Oscillator Pins
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same side
of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The
load capacitors should be placed next to the oscillator
itself, on the same side of the board. Use a grounded
copper pour around the oscillator circuit to isolate them
from surrounding circuits. The grounded copper pour
should be routed directly to the MCU ground. Do not
run any signal traces or power traces inside the ground
pour. Also, if using a two-sided board, avoid any traces
on the other side of the board where the crystal is
placed. A suggested layout is illustrated in Figure 2-3.
FIGURE 2-3:
SUGGESTED OSCILLATOR
CIRCUIT PLACEMENT
JTAG
Oscillator
Secondary
The TMS, TDO, TDI and TCK pins are used for testing
and debugging according to the Joint Test Action
Group (JTAG) standard. It is recommended to keep the
trace length between the JTAG connector and the
JTAG pins on the device as short as possible. If the
JTAG connector is expected to experience an ESD
event, a series resistor is recommended, with the value
in the range of a few tens of Ohms, not to exceed 100
Ohms.
Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended
as they will interfere with the programmer/debugger
communications to the device. If such discrete
components are an application requirement, they
should be removed from the circuit during
programming and debugging. Alternatively, refer to the
AC/DC characteristics and timing requirements
information in the respective device Flash
programming specification for information on
capacitive loading limits and pin input voltage high (VIH)
and input voltage low (VIL) requirements.
2015-2016 Microchip Technology Inc.
Guard Trace
Guard Ring
Main Oscillator
2.8
Unused I/Os
Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
to a logic-low state.
Alternatively, inputs can be reserved by connecting the
pin to VSS through a 1k to 10k resistor and configuring
the pin as an input.
DS60001320D-page 39
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2.9
Designing for High-Speed
Peripherals
The PIC32MZ EF family devices have peripherals that
operate at frequencies much higher than typical for an
embedded environment. Table 2-1 lists the peripherals
that produce high-speed signals on their external pins:
TABLE 2-1:
PERIPHERALS THAT
PRODUCE HS SIGNALS ON
EXTERNAL PINS
Peripheral
High-Speed
Signal Pins
Maximum
Speed on
Signal Pin
EBI
EBIAx,
EBIDx
50 MHz
SQI1
SQICLK,
SQICSx,
SQIDx
50 MHz
HS USB
D+, D-
480 MHz
Due to these high-speed signals, it is important to
consider several factors when designing a product that
uses these peripherals, as well as the PCB on which
these components will be placed. Adhering to these
recommendations will help achieve the following goals:
• Minimize the effects of electromagnetic interference
to the proper operation of the product
• Ensure signals arrive at their intended destination at
the same time
• Minimize crosstalk
• Maintain signal integrity
• Reduce system noise
• Minimize ground bounce and power sag
2.9.1
2.9.1.1
SYSTEM DESIGN
Impedance Matching
When selecting parts to place on high-speed buses,
particularly the SQI bus, if the impedance of the peripheral device does not match the impedance of the pins
on the PIC32MZ EF device to which it is connected,
signal reflections could result, thereby degrading the
quality of the signal.
If it is not possible to select a product that matches
impedance, place a series resistor at the load to create
the matching impedance. See Figure 2-4 for an
example.
FIGURE 2-4:
SERIES RESISTOR
PIC32MZ
50
DS60001320D-page 40
2.9.1.2
PCB Layout Recommendations
The following list contains recommendations that will
help ensure the PCB layout will promote the goals
previously listed.
• Component Placement
- Place bypass capacitors as close to their
component power and ground pins as possible,
and place them on the same side of the PCB
- Devices on the same bus that have larger setup
times should be placed closer to the PIC32MZ EF
device
• Power and Ground
- Multi-layer PCBs will allow separate power and
ground planes
- Each ground pin should be connected to the
ground plane individually
- Place bypass capacitor vias as close to the pad
as possible (preferably inside the pad)
- If power and ground planes are not used,
maximize width for power and ground traces
- Use low-ESR, surface-mount bypass capacitors
• Clocks and Oscillators
- Place crystals as close as possible to the
PIC32MZ EF device OSC/SOSC pins
- Do not route high-speed signals near the clock or
oscillator
- Avoid via usage and branches in clock lines
(SQICLK)
- Place termination resistors at the end of clock
lines
• Traces
- Higher-priority signals should have the shortest
traces
- Match trace lengths for parallel buses (EBIAx,
EBIDx, SQIDx)
- Avoid long run lengths on parallel traces to reduce
coupling
- Make the clock traces as straight as possible
- Use rounded turns rather than right-angle turns
- Have traces on different layers intersect on right
angles to minimize crosstalk
- Maximize the distance between traces, preferably
no less than three times the trace width
- Power traces should be as short and as wide as
possible
- High-speed traces should be placed close to the
ground plane
SQI
Flash
Device
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2.9.1.3
EMI/EMC/EFT (IEC 61000-4-4 and
IEC 61000-4-2) Suppression
Considerations
The use of LDO regulators is preferred to reduce
overall system noise and provide a cleaner power
source. However, when utilizing switching Buck/Boost
regulators as the local power source for PIC32MZ EF
devices, as well as in electrically noisy environments or
test conditions required for IEC 61000-4-4 and IEC
61000-4-2, users should evaluate the use of T-Filters
(i.e., L-C-L) on the power pins, as shown in Figure 2-5.
In addition to a more stable power source, use of this
type of T-Filter can greatly reduce susceptibility to EMI
sources and events.
FIGURE 2-5:
EMI/EMC/EFT
SUPPRESSION CIRCUIT
Ferrite Chip SMD
DCR = 0.15ȍ(max)
600 ma ISAT
300ȍ@ 100 MHz
PN#:
VDD
0.01 μF
Ferrite
Chips
0.1 μF
VSS
VDD
VDD
VSS
0.1 μF
VSS
VDD
VSS
VDD
VSS
0.1 μF
PIC32MZ
VSS
0.1 μF
VSS
VDD
AVDD
AVSS
0.1 μF
VSS
VUSB3V3
VDD
0.1 μF
VDD
0.1 μF
0.1 μF
0.1 μF
Ferrite
Chips
VDD
0.01 μF
2015-2016 Microchip Technology Inc.
DS60001320D-page 41
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2.10
Typical Application Connection
Examples
Examples of typical application connections are shown
in Figure 2-6 and Figure 2-7.
FIGURE 2-6:
AUDIO PLAYBACK APPLICATION
PMD
USB
Host
PMP
USB
Display
PMWR
PIC32
I2S
SPI
Stereo Headphones
3
REFCLKO
3
Audio
Codec
Speaker
3
MMC SD
SDI
FIGURE 2-7:
LOW-COST CONTROLLERLESS (LCC) GRAPHICS APPLICATION WITH
PROJECTED CAPACITIVE TOUCH
PIC32
Microchip
mTouch™
Library
Microchip
GFX Library
ANx
ADC
Render
LCD Display
Refresh
DMA
Projected Capacitive
Touch Overlay
EBI
SRAM
DS60001320D-page 42
External Frame Buffer
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
3.0
CPU
Note 1: This data sheet summarizes the features of the PIC32MZ EF family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 50. “CPU for
Devices with MIPS32® microAptiv™
and M-Class Cores” (DS60001192) of
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
2: The Series 5 Warrior M-class CPU core
resources
are
available
at:
www.imgtec.com.
The MIPS32® M-Class Core is the heart of the
PIC32MZ EF family device processor. The CPU
fetches instructions, decodes each instruction, fetches
source operands, executes each instruction and writes
the results of instruction execution to the proper
destinations.
Key features include:
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32 Enhanced Architecture (Release 5):
- Multiply-accumulate and multiply-subtract
instructions
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency for
interrupt handlers
- Bit field manipulation instructions
- Virtual memory support
• microMIPS™ compatible instruction set:
- Improves code size density over MIPS32, while
maintaining MIPS32 performance.
- Supports all MIPS32 instructions (except branchlikely instructions)
- Fifteen additional 32-bit instructions and 39 16-bit
instructions corresponding to commonly-used
MIPS32 instructions
- Stack pointer implicit in instruction
- MIPS32 assembly and ABI compatible
• MMU with Translation Lookaside Buffer (TLB)
mechanism:
- 16 dual-entry fully associative Joint TLB
- 4-entry fully associative Instruction and Data TLB
- 4 KB pages
2015-2016 Microchip Technology Inc.
• Separate L1 data and instruction caches:
- 16 KB 4-way Instruction Cache (I-Cache)
- 4 KB 4-way Data Cache (D-Cache)
• Autonomous Multiply/Divide Unit (MDU):
- Maximum issue rate of one 32x32 multiply per clock
- Early-in iterative divide. Minimum 12 and
maximum 38 clock latency (dividend (rs) sign
extension-dependent)
• Power Control:
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT instruction)
- Extensive use of local gated clocks
• EJTAG Debug and Instruction Trace:
- Support for single stepping
- Virtual instruction and data address/value
breakpoints
- Hardware breakpoint supports both address
match and address range triggering.
- Eight instruction and four data complex
breakpoints
• iFlowtrace® version 2.0 support:
- Real-time instruction program counter
- Special events trace capability
- Two performance counters with 34 userselectable countable events
- Disabled if the processor enters Debug mode
- Program Counter sampling
• Four Watch registers:
- Instruction, Data Read, Data Write options
- Address match masking options
• DSP ASE Extension:
- Native fractional format data type operations
- Register Single Instruction Multiple Data (SIMD)
operations (add, subtract, multiply, shift)
- GPR-based shift
- Bit manipulation
- Compare-Pick
- DSP Control Access
- Indexed-Load
- Branch
- Multiplication of complex operands
- Variable bit insertion and extraction
- Virtual circular buffers
- Arithmetic saturation and overflow handling
- Zero-cycle overhead saturation and rounding
operations
• Floating Point Unit (FPU):
- 1985 IEEE-754 compliant Floating Point Unit
- Supports single and double precision datatypes
- 2008 IEEE-754 compatibility control of NaN
handling and Abs/Neg instructions
- Runs at 1:1 core/FPU clock ratio
DS60001320D-page 43
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
A block diagram of the PIC32MZ EF family processor
core is shown in Figure 3-1.
FIGURE 3-1:
PIC32MZ EF FAMILY MICROPROCESSOR CORE BLOCK DIAGRAM
M-Class Microprocessor Core
PBCLK7
Decode
(MIPS32®/microMIPS™)
microMIPS™
I-Cache
Controller
I-Cache
GPR
(8 sets)
Execution Unit
ALU/Shift
Atomic/LdSt
DSP ASE
Enhanced MDU
(with DSP ASE)
MMU
(TLB)
BIU
System Bus
FPU
(Single & Double)
D-Cache
Controller
D-Cache
Debug/Profiling
System
Interface
System
Coprocessor
Interrupt
Interface
2-wire Debug
DS60001320D-page 44
Break Points
iFlowtrace®
Fast Debug Channel
Performance Counters
Sampling
Secure Debug
Power
Management
EJTAG
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
3.1
Architecture Overview
The MIPS32 M-Class Microprocessor core in PIC32MZ
EF family devices contains several logic blocks working
together in parallel, providing an efficient high-performance computing engine. The following blocks are
included with the core:
•
•
•
•
•
•
•
•
•
•
•
Execution unit
General Purpose Register (GPR)
Multiply/Divide Unit (MDU)
System control coprocessor (CP0)
Floating Point Unit (FPU)
Memory Management Unit (MMU)
Instruction/Data cache controllers
Power Management
Instructions and data caches
microMIPS support
Enhanced JTAG (EJTAG) controller
3.1.1
3.1.2
MULTIPLY/DIVIDE UNIT (MDU)
The processor core includes a Multiply/Divide Unit
(MDU) that contains a separate pipeline for multiply
and divide operations, and DSP ASE multiply instructions. This pipeline operates in parallel with the Integer
Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially
masked by system stalls and/or other integer unit
instructions.
EXECUTION UNIT
The processor core execution unit implements a load/
store architecture with single-cycle ALU operations
(logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer
operations and address calculation. Seven additional
register file shadow sets (containing thirty-two registers) are added to minimize context switching overhead
during interrupt/exception processing. The register file
consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline.
The execution unit includes:
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
address
• Logic for branch determination and branch target
address calculation
• Load aligner
• Trap condition comparator
• Bypass multiplexers used to avoid stalls when
executing instruction streams where data
producing instructions are followed closely by
consumers of their results
TABLE 3-1:
• Leading Zero/One detect unit for implementing
the CLZ and CLO instructions
• Arithmetic Logic Unit (ALU) for performing arithmetic
and bitwise logical operations
• Shifter and store aligner
• DSP ALU and logic block for performing DSP
instructions, such as arithmetic/shift/compare
operations
The high-performance MDU consists of a 32x32 booth
recoded multiplier, four pairs of result/accumulation
registers (HI and LO), a divide state machine, and the
necessary multiplexers and control logic. The first number shown (‘32’ of 32x32) represents the rs operand.
The second number (‘32’ of 32x32) represents the rt
operand.
The MDU supports execution of one multiply or
multiply-accumulate operation every clock cycle.
Divide operations are implemented with a simple 1-bitper-clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For
a 16-bit wide rs, 15 iterations are skipped and for a
24-bit wide rs, 7 iterations are skipped. Any attempt to
issue a subsequent MDU instruction while a divide is
still active causes an IU pipeline stall until the divide
operation has completed.
Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency (number of cycles until a result is available) for the processor
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
MIPS32® M-CLASS MICROPROCESSOR CORE HIGH-PERFORMANCE INTEGER
MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU (HI/LO destination)
MUL (GPR destination)
DIV/DIVU
2015-2016 Microchip Technology Inc.
Operand Size (mul rt) (div rs)
Latency
Repeat Rate
16 bits
32 bits
16 bits
32 bits
8 bits
16 bits
24 bits
32 bits
5
5
5
5
12/14
20/22
28/30
36/38
1
1
1
1
12/14
20/22
28/30
36/38
DS60001320D-page 45
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
The MIPS architecture defines that the result of a
multiply or divide operation be placed in one of four
pairs of HI and LO registers. Using the Move-From-HI
(MFHI) and Move-From-LO (MFLO) instructions, these
values can be transferred to the General Purpose
Register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in
the primary register file instead of the HI/LO register
pair. By avoiding the explicit MFLO instruction
required when using the LO register, and by supporting multiple destination registers, the throughput of
multiply-intensive operations is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
The MDU also implements various shift instructions
operating on the HI/LO register and multiply instructions as defined in the DSP ASE. The MDU supports all
of the data types required for this purpose and includes
three extra HI/LO registers as defined by the ASE.
TABLE 3-3:
Register
Number
Register
Name
Index
Random
EntryLo0
EntryLo1
Context/
UserLocal
5
PageMask/
PageGrain
Wired
HWREna
8
9
10
11
TABLE 3-2:
DSP-RELATED LATENCIES
AND REPEAT RATES
Op code
Latency
Repeat
Rate
Multiply and dot-product without
saturation after accumulation
5
1
Multiply and dot-product with
saturation after accumulation
5
1
Multiply without accumulation
5
1
3.1.3
SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation and cache protocols, the exception control system, the processor’s
diagnostics capability, the operating modes (Kernel,
User and Debug) and whether interrupts are enabled or
disabled. Configuration information, such as cache
size and set associativity, and the presence of options
like microMIPS is also available by accessing the CP0
registers, listed in Table 3-3.
COPROCESSOR 0 REGISTERS
0
1
2
3
4
6
7
Table 3-2 lists the latencies and repeat rates for the
DSP multiply and dot-product operations. The approximate latencies and repeat rates are listed in terms of
pipeline clocks.
BadVAddr
BadInstr
BadInstrP
Count
EntryHi
Compare
DS60001320D-page 46
Function
Index into the TLB array (MPU only).
Randomly generated index into the TLB array (MPU only).
Low-order portion of the TLB entry for even-numbered virtual pages (MPU only).
Low-order portion of the TLB entry for odd-numbered virtual pages (MPU only).
Pointer to the page table entry in memory (MPU only).
User information that can be written by privileged software and read via the RDHWR
instruction.
PageMask controls the variable page sizes in TLB entries. PageGrain enables support
of 1 KB pages in the TLB (MPU only).
Controls the number of fixed (i.e., wired) TLB entries (MPU only).
Enables access via the RDHWR instruction to selected hardware registers in
Non-privileged mode.
Reports the address for the most recent address-related exception.
Reports the instruction that caused the most recent exception.
Reports the branch instruction if a delay slot caused the most recent exception.
Processor cycle count.
High-order portion of the TLB entry (MPU only).
Core timer interrupt control.
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 3-3:
Register
Number
12
13
14
15
16
17
18
19
20-22
23
24
25
26
27
28
29
30
31
COPROCESSOR 0 REGISTERS (CONTINUED)
Register
Name
Function
Status
IntCtl
SRSCtl
SRSMap
View_IPL
Processor status and control.
Interrupt control of vector spacing.
Shadow register set control.
Shadow register mapping control.
Allows the Priority Level to be read/written without
extracting or inserting that bit from/to the Status register.
SRSMAP2
Contains two 4-bit fields that provide the mapping from a vector number to the shadow
set number to use when servicing such an interrupt.
Cause
Describes the cause of the last exception.
NestedExc
Contains the error and exception level status bit values that existed prior to the current
exception.
View_RIPL
Enables read access to the RIPL bit that is available in the Cause register.
EPC
Program counter at last exception.
NestedEPC
Contains the exception program counter that existed prior to the current exception.
PRID
Processor identification and revision
Ebase
Exception base address of exception vectors.
CDMMBase
Common device memory map base.
Config
Configuration register.
Config1
Configuration register 1.
Config2
Configuration register 2.
Config3
Configuration register 3.
Config4
Configuration register 4.
Config5
Configuration register 5.
Config7
Configuration register 7.
LLAddr
Load link address (MPU only).
WatchLo
Low-order watchpoint address (MPU only).
WatchHi
High-order watchpoint address (MPU only).
Reserved
Reserved in the PIC32 core.
Debug
EJTAG debug register.
TraceControl
EJTAG trace control.
TraceControl2
EJTAG trace control 2.
UserTraceData1 EJTAG user trace data 1 register.
TraceBPC
EJTAG trace breakpoint register.
Debug2
Debug control/exception status 1.
DEPC
Program counter at last debug exception.
UserTraceData2 EJTAG user trace data 2 register.
PerfCtl0
Performance counter 0 control.
PerfCnt0
Performance counter 0.
PerfCtl1
Performance counter 1 control.
PerfCnt1
Performance counter 1.
ErrCtl
Software test enable of way-select and data RAM arrays for I-Cache and D-Cache
(MPU only).
Reserved
Reserved in the PIC32 core.
TagLo/DataLo
Low-order portion of cache tag interface (MPU only).
Reserved
Reserved in the PIC32 core.
ErrorEPC
Program counter at last error exception.
DeSave
Debug exception save.
2015-2016 Microchip Technology Inc.
DS60001320D-page 47
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
3.1.4
FLOATING POINT UNIT (FPU)
The Floating Point Unit (FPU), Coprocessor (CP1),
implements the MIPS Instruction Set Architecture for
floating point computation. The implementation supports the ANSI/IEEE Standard 754 (IEEE for Binary
Floating Point Arithmetic) for 32-bit and 64-bit floating
point data formats. The FPU can be programmed to
have thirty-two 32-bit or 64-bit floating point registers
used for floating point operations.
The performance is optimized for 32-bit formats. Most
instructions have one FPU cycle throughput and four
FPU cycle latency. The FPU implements the multiplyadd (MADD) and multiply-sub (MSUB) instructions with
intermediate rounding after the multiply function. The
result is guaranteed to be the same as executing a
MUL and an ADD instruction separately, but the
instruction latency, instruction fetch, dispatch bandwidth, and the total number of register accesses are
improved.
IEEE denormalized input operands and results are
supported by hardware for some instructions. IEEE
denormalized results are not supported by hardware in
general, but a fast flush-to-zero mode is provided to
optimize performance. The fast flush-to-zero mode is
enabled through the FCCR register, and use of this
mode is recommended for best performance when
denormalized results are generated.
The FPU has a separate pipeline for floating point
instruction execution. This pipeline operates in parallel
with the integer core pipeline and does not stall when
the integer pipeline stalls. This allows long-running
FPU operations, such as divide or square root, to be
partially masked by system stalls and/or other integer
unit instructions. Arithmetic instructions are always
dispatched and completed in order, but loads and
stores can complete out of order. The exception model
is “precise” at all times.
Table 3-4 contains the floating point instruction latencies and repeat rates for the processor core. In this
table, 'Latency' refers to the number of FPU cycles necessary for the first instruction to produce the result
needed by the second instruction. The “Repeat Rate”
refers to the maximum rate at which an instruction can
be executed per FPU cycle.
DS60001320D-page 48
TABLE 3-4:
FPU INSTRUCTION
LATENCIES AND REPEAT
RATES
Latency
(FPU
Cycles)
Repeat
Rate
(FPU
Cycles)
ABS.[S,D], NEG.[S,D],
ADD.[S,D], SUB.[S,D],
C.cond.[S,D], MUL.S
4
1
MADD.S, MSUB.S,
NMADD.S, NMSUB.S,
CABS.cond.[S,D]
4
1
CVT.D.S, CVT.PS.PW,
CVT.[S,D].[W,L]
4
1
CVT.S.D,
CVT.[W,L].[S,D],
CEIL.[W,L].[S,D],
FLOOR.[W,L].[S,D],
ROUND.[W,L].[S,D],
TRUNC.[W,L].[S,D]
4
1
MOV.[S,D], MOVF.[S,D],
MOVN.[S,D],
MOVT.[S,D], MOVZ.[S,D]
4
1
MUL.D
5
2
MADD.D, MSUB.D,
NMADD.D, NMSUB.D
5
2
RECIP.S
13
10
RECIP.D
26
21
RSQRT.S
17
14
RSQRT.D
36
31
DIV.S, SQRT.S
17
14
DIV.D, SQRT.D
32
29
MTC1, DMTC1, LWC1,
LDC1, LDXC1, LUXC1,
LWXC1
4
1
MFC1, DMFC1, SWC1,
SDC1, SDXC1, SUXC1,
SWXC1
1
1
Op code
Legend: S = Single (32-bit) D = Double (64-bit)
W = Word (32-bit) L = Long word (64-bit)
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
The FPU implements a high-performance 7-stage
pipeline:
• Decode, register read and unpack (FR stage)
• Multiply tree, double pumped for double (M1
stage)
• Multiply complete (M2 stage)
• Addition first step (A1 stage)
• Addition second and final step (A2 stage)
• Packing to IEEE format (FP stage)
• Register writeback (FW stage)
The FPU implements a bypass mechanism that allows
the result of an operation to be forwarded directly to the
instruction that needs it without having to write the
result to the FPU register and then read it back.
Table 3-5 lists the Coprocessor 1 Registers for the
FPU.
TABLE 3-5:
FPU (CP1) REGISTERS
Register Register
Number
Name
Function
0
FIR
Floating Point implementation
register. Contains information
that identifies the FPU.
25
FCCR
Floating Point condition codes
register.
26
FEXR
Floating Point exceptions
register.
28
FENR
Floating Point enables register.
31
FCSR
Floating Point Control and
Status register.
3.2
Power Management
The processor core offers a number of power management features, including low-power design, active power
management and power-down modes of operation. The
core is a static design that supports slowing or halting
the clocks, which reduces system power consumption
during Idle periods.
3.2.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 33.0
“Power-Saving Features”.
3.2.2
LOCAL CLOCK GATING
The majority of the power consumed by the processor
core is in the clock tree and clocking registers. The
PIC32MZ family makes extensive use of local gatedclocks to reduce this dynamic power consumption.
2015-2016 Microchip Technology Inc.
3.3
3.3.1
L1 Instruction and Data Caches
INSTRUCTION CACHE (I-CACHE)
The I-Cache is an on-core memory block of 16 Kbytes.
Because the I-Cache is virtually indexed, the virtual-tophysical address translation occurs in parallel with the
cache access rather than having to wait for the physical
address translation. The tag holds 22 bits of physical
address, a valid bit, and a lock bit. The LRU
replacement bits are stored in a separate array.
The I-Cache block also contains and manages the
instruction line fill buffer. Besides accumulating data to
be written to the cache, instruction fetches that reference data in the line fill buffer are serviced either by a
bypass of that data, or data coming from the external
interface. The I-Cache control logic controls the bypass
function.
The processor core supports I-Cache locking. Cache
locking allows critical code or data segments to be
locked into the cache on a per-line basis, enabling the
system programmer to maximize the efficiency of the
system cache.
The cache locking function is always available on all
I-Cache entries. Entries can then be marked as
locked or unlocked on a per entry basis using the
CACHE instruction.
3.3.2
DATA CACHE (D-CACHE)
The D-Cache is an on-core memory block of 4 Kbytes.
This virtually indexed, physically tagged cache is protected. Because the D-Cache is virtually indexed, the
virtual-to-physical address translation occurs in parallel
with the cache access. The tag holds 22 bits of physical
address, a valid bit, and a lock bit. There is an additional array holding dirty bits and LRU replacement
algorithm bits for each set of the cache.
In addition to I-Cache locking, the processor core also
supports a D-Cache locking mechanism identical to the
I-Cache. Critical data segments are locked into the
cache on a per-line basis. The locked contents can be
updated on a store hit, but cannot be selected for
replacement on a cache miss.
The D-Cache locking function is always available on
all D-Cache entries. Entries can then be marked as
locked or unlocked on a per-entry basis using the
CACHE instruction.
3.3.3
ATTRIBUTES
The processor core I-Cache and D-Cache attributes
are listed in the Configuration registers (see
Register 3-1 through Register 3-4).
DS60001320D-page 49
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
3.4
EJTAG Debug Support
The processor core provides for an Enhanced JTAG
(EJTAG) interface for use in the software debug of
application and kernel code. In addition to standard
User mode and Kernel modes of operation, the processor core provides a Debug mode that is entered after a
debug exception (derived from a hardware breakpoint,
single-step exception, etc.) is taken and continues until
a Debug Exception Return (DERET) instruction is
executed. During this time, the processor executes the
debug exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for transferring test data in and out of the core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification specify which
registers are selected and how they are used.
3.5
3.6
microMIPS ISA
The processor core supports the microMIPS ISA,
which contains all MIPS32 ISA instructions (except for
branch-likely instructions) in a new 32-bit encoding
scheme, with some of the commonly used instructions
also available in 16-bit encoded format. This ISA
improves code density through the additional 16-bit
instructions while maintaining a performance similar to
MIPS32 mode. In microMIPS mode, 16-bit or 32-bit
instructions will be fetched and recoded to legacy
MIPS32 instruction opcodes in the pipeline’s I stage, so
that the processor core can have the same microAptiv
UP microarchitecture. Because the microMIPS instruction stream can be intermixed with 16-bit halfword or
32-bit word size instructions on halfword or word
boundaries, additional logic is in place to address the
word
misalignment
issues,
thus
minimizing
performance loss.
MIPS DSP ASE Extension
The MIPS DSP Application-Specific Extension
Revision 2 is an extension to the MIPS32 architecture.
This extension comprises new integer instructions and
states that include new HI/LO accumulator register
pairs and a DSP control register. This extension is
crucial in a wide range of DSP, multimedia, and DSPlike algorithms covering Audio and Video processing
applications. The extension supports native fractional
format data type operations, register Single Instruction
Multiple Data (SIMD) operations, such as add,
subtract, multiply, and shift. In addition, the extension
includes the following features that are essential in
making DSP algorithms computationally efficient:
•
•
•
•
Support for multiplication of complex operands
Variable bit insertion and extraction
Implementation and use of virtual circular buffers
Arithmetic saturation and overflow handling
support
• Zero cycle overhead saturation and rounding
operations
DS60001320D-page 50
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
3.7
M-Class Core Configuration
Register 3-1 through Register 3-4 show the default
configuration of the M-Class core, which is included on
the PIC32MZ EF family of devices.
REGISTER 3-1:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG: CONFIGURATION REGISTER; CP0 REGISTER 16, SELECT 0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
r-1
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
ISP
R-1
R-0
R-0
R-1
R-0
U-0
DSP
UDI
SB
MDU
—
R-0
R-0
R-0
R-0
BE
AT
R-0
R-1
U-0
U-0
U-0
U-0
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
R-0
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R-0
MM
R-1
AR
MT
Bit
24/16/8/0
BM
R-0
R-0
MT
R/W-0
R/W-1
R/W-0
K0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Reserved: This bit is hardwired to ‘1’ to indicate the presence of the Config1 register.
bit 30-25 Unimplemented: Read as ‘0’
bit 24
ISP: Instruction Scratch Pad RAM bit
0 = Instruction Scratch Pad RAM is not implemented
bit 23
DSP: Data Scratch Pad RAM bit
0 = Data Scratch Pad RAM is not implemented
bit 22
UDI: User-defined bit
0 = CorExtend User-Defined Instructions are not implemented
bit 21
SB: SimpleBE bit
1 = Only Simple Byte Enables are allowed on the internal bus interface
bit 20
MDU: Multiply/Divide Unit bit
0 = Fast, high-performance MDU
bit 19
Unimplemented: Read as ‘0’
bit 18-17 MM: Merge Mode bits
10 = Merging is allowed
bit 16
BM: Burst Mode bit
0 = Burst order is sequential
bit 15
BE: Endian Mode bit
0 = Little-endian
bit 14-13 AT: Architecture Type bits
00 = MIPS32
bit 12-10 AR: Architecture Revision Level bits
001 = MIPS32 Release 2
bit 9-7
MT: MMU Type bits
001 = M-Class MPU Microprocessor core uses a TLB-based MMU
bit 6-3
Unimplemented: Read as ‘0’
bit 2-0
K0: Kseg0 Coherency Algorithm bits
011 = Cacheable, non-coherent, write-back, write allocate
010 = Uncached
001 = Cacheable, non-coherent, write-through, write allocate
000 = Cacheable, non-coherent, write-through, no write allocate
All other values are not used and mapped to other values. 100, 101, and 110 are mapped to 010. 111 is
mapped to 010.
2015-2016 Microchip Technology Inc.
DS60001320D-page 51
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 3-2:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG1: CONFIGURATION REGISTER 1; CP0 REGISTER 16, SELECT 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
r-1
R-0
R-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
R-1
R-1
R-1
R-1
—
R-0
MMU Size
R-1
R-0
R-0
R-0
R-0
IS
R-0
R-1
IS
R-1
R-0
R-1
R-1
IL
R-1
R-1
IA
R-0
DS
R-0
DL
R-1
DA
R-1
U-0
U-0
R-1
R-1
R-0
R-1
R-1
DA
—
—
PC
WR
CA
EP
FP
Legend:
R = Readable bit
r = Reserved bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
Bit
24/16/8/0
x = Bit is unknown
Reserved: This bit is hardwired to a ‘1’ to indicate the presence of the Config2 register.
bit 30-25 MMU Size: Contains the number of TLB entries minus 1
001111 = 16 TLB entries
bit 24-22 IS: Instruction Cache Sets bits
010 = Contains 256 instruction cache sets per way
bit 21-19 IL: Instruction-Cache Line bits
011 = Contains instruction cache line size of 16 bytes
bit 18-16 IA!(K|DM)
EBASE+0x180
transition).
EJTAG debug hardware instruction break matched.
0xBFC0_0480
A reference to an address that is in one of the
EBASE+0x180
Watch registers (fetch).
Fetch address alignment error. Fetch reference to
EBASE+0x180
protected address.
Fetch TLB miss or fetch TLB hit to page with V = 0. EBASE if Status.EXL = 0
EBASE+0x180 if
Status.EXL == 1
An instruction fetch matched a valid TLB entry that
EBASE+0x180
had the XI bit set.
Instruction fetch bus error.
EBASE+0x180
BEV, NMI,
ERL
MCHECK,
EXL
IPL
—
0x00
See Table 7-2.
WP, EXL
—
0x17
_general_exception_handler
—
EXL
DIB
—
—
0x17
—
_general_exception_handler
EXL
—
0x04
_general_exception_handler
—
—
—
—
0x02
0x02
—
_general_exception_handler
EXL
—
0x14
_general_exception_handler
EXL
—
0x06
_general_exception_handler
Deferred Watch
2015-2016 Microchip Technology Inc.
DIB
WATCH
AdEL
TLBL
TLBL Execute
Inhibit
IBE
0xBFC0_0000
—
—
_nmi_handler
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 116
7.1
Exception Type
(In Order of
Priority)
Instruction
Validity
Exceptions
Execute
Exception
Tr
DDBL/DDBS
WATCH
AdEL
AdES
TLBL
TLBS
DBE
DDBL
CBrk
MIPS32® M-CLASS MICROPROCESSOR CORE EXCEPTION TYPES (CONTINUED)
Description
Branches to
Status
Bits Set
Debug Bits
Set
An instruction could not be completed because it
was not allowed to access the required resources
(Coprocessor Unusable) or was illegal (Reserved
Instruction). If both exceptions occur on the same
instruction, the Coprocessor Unusable Exception
takes priority over the Reserved Instruction
Exception.
An instruction-based exception occurred: Integer
overflow, trap, system call, breakpoint, floating
point, or DSP ASE state disabled exception.
Execution of a trap (when trap condition is true).
EJTAG Data Address Break (address only) or
EJTAG data value break on store (address +
value).
A reference to an address that is in one of the
Watch registers (data).
Load address alignment error. User mode load
reference to kernel address.
Store address alignment error. User mode store to
kernel address.
Load TLB miss or load TLB hit to page with V = 0.
Store TLB miss or store TLB hit to page with V = 0.
Load or store bus error.
EJTAG data hardware breakpoint matched in load
data compare.
EJTAG complex breakpoint.
EBASE+0x180
EXL
—
EBASE+0x180
EXL
—
EBASE+0x180
0xBFC0_0480
EXL
—
—
DDBL or
DDBS
0x0D
—
_general_exception_handler
—
EBASE+0x180
EXL
—
0x17
_general_exception_handler
EBASE+0x180
EXL
—
0x04
_general_exception_handler
EBASE+0x180
EXL
—
0x05
_general_exception_handler
EBASE+0x180
EBASE+0x180
EBASE+0x180
0xBFC0_0480
EXL
EXL
EXL
—
—
—
—
DDBL
0x02
0x03
0x07
—
_general_exception_handler
_general_exception_handler
_general_exception_handler
—
0xBFC0_0480
—
DIBIMPR,
DDBLIMPR,
and/or
DDBSIMPR
—
—
DS60001320D-page 117
Lowest Priority
EXCCODE
XC32 Function Name
0x0A or
0x0B
_general_exception_handler
0x08-0x0C _general_exception_handler
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2015-2016 Microchip Technology Inc.
TABLE 7-1:
For details on the Variable Offset feature, refer to 8.5.2 “Variable Offset” in
Section 8. “Interrupt Controller” (DS60001108) of the “PIC32 Family
Reference Manual”.
Interrupts
The PIC32MZ EF family uses variable offsets for vector spacing. This allows the
interrupt vector spacing to be configured according to application needs. A
unique interrupt vector offset can be set for each vector using its associated
OFFx register.
TABLE 7-2:
Table 7-2 provides the Interrupt IRQ, vector and bit location information.
INTERRUPT IRQ, VECTOR, AND BIT LOCATION
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Interrupt Bit Location
Persistent
Sub-priority Interrupt
Vector #
Flag
Enable
Priority
Highest Natural Order Priority
2015-2016 Microchip Technology Inc.
Core Timer Interrupt
_CORE_TIMER_VECTOR
0
OFF000 IFS0 IEC0 IPC0
IPC0
No
Core Software Interrupt 0
_CORE_SOFTWARE_0_VECTOR
1
OFF001 IFS0 IEC0 IPC0
IPC0
No
Core Software Interrupt 1
_CORE_SOFTWARE_1_VECTOR
2
OFF002 IFS0 IEC0 IPC0
IPC0
No
External Interrupt 0
_EXTERNAL_0_VECTOR
3
OFF003 IFS0 IEC0 IPC0
IPC0
No
Timer1
_TIMER_1_VECTOR
4
OFF004 IFS0 IEC0 IPC1
IPC1
No
Input Capture 1 Error
_INPUT_CAPTURE_1_ERROR_VECTOR
5
OFF005 IFS0 IEC0 IPC1
IPC1
Yes
Input Capture 1
_INPUT_CAPTURE_1_VECTOR
6
OFF006 IFS0 IEC0 IPC1
IPC1
Yes
Output Compare 1
_OUTPUT_COMPARE_1_VECTOR
7
OFF007 IFS0 IEC0 IPC1
IPC1
No
External Interrupt 1
_EXTERNAL_1_VECTOR
8
OFF008 IFS0 IEC0 IPC2
IPC2
No
Timer2
_TIMER_2_VECTOR
9
OFF009 IFS0 IEC0 IPC2
IPC2
No
Input Capture 2 Error
_INPUT_CAPTURE_2_ERROR_VECTOR
10 OFF010 IFS0 IEC0 IPC2
IPC2
Yes
Input Capture 2
_INPUT_CAPTURE_2_VECTOR
11
IPC2
Yes
Output Compare 2
_OUTPUT_COMPARE_2_VECTOR
12 OFF012 IFS0 IEC0 IPC3
IPC3
No
External Interrupt 2
_EXTERNAL_2_VECTOR
13 OFF013 IFS0 IEC0 IPC3
IPC3
No
Timer3
_TIMER_3_VECTOR
14 OFF014 IFS0 IEC0 IPC3
IPC3
No
Input Capture 3 Error
_INPUT_CAPTURE_3_ERROR_VECTOR
15 OFF015 IFS0 IEC0 IPC3
IPC3
Yes
Input Capture 3
_INPUT_CAPTURE_3_VECTOR
16 OFF016 IFS0 IEC0 IPC4
IPC4
Yes
Output Compare 3
_OUTPUT_COMPARE_3_VECTOR
17 OFF017 IFS0 IEC0 IPC4
IPC4
No
External Interrupt 3
_EXTERNAL_3_VECTOR
18 OFF018 IFS0 IEC0 IPC4
IPC4
No
Timer4
_TIMER_4_VECTOR
19 OFF019 IFS0 IEC0 IPC4
IPC4
No
Input Capture 4 Error
_INPUT_CAPTURE_4_ERROR_VECTOR
20 OFF020 IFS0 IEC0 IPC5
IPC5
Yes
Input Capture 4
_INPUT_CAPTURE_4_VECTOR
21 OFF021 IFS0 IEC0 IPC5
IPC5
Yes
Note 1:
2:
3:
4:
OFF011 IFS0 IEC0 IPC2
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EF Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
This interrupt source is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 118
7.2
INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Interrupt Bit Location
Sub-priority
Persistent
Interrupt
Vector #
Flag
Enable
Priority
DS60001320D-page 119
Output Compare 4
_OUTPUT_COMPARE_4_VECTOR
22 OFF022 IFS0 IEC0 IPC5
IPC5
No
External Interrupt 4
_EXTERNAL_4_VECTOR
23 OFF023 IFS0 IEC0 IPC5
IPC5
No
Timer5
_TIMER_5_VECTOR
24 OFF024 IFS0 IEC0 IPC6
IPC6
No
Input Capture 5 Error
_INPUT_CAPTURE_5_ERROR_VECTOR
25 OFF025 IFS0 IEC0 IPC6
IPC6
Yes
Input Capture 5
_INPUT_CAPTURE_5_VECTOR
26 OFF026 IFS0 IEC0 IPC6
IPC6
Yes
Output Compare 5
_OUTPUT_COMPARE_5_VECTOR
27 OFF027 IFS0 IEC0 IPC6
IPC6
No
Timer6
_TIMER_6_VECTOR
28 OFF028 IFS0 IEC0 IPC7
IPC7
No
Input Capture 6 Error
_INPUT_CAPTURE_6_ERROR_VECTOR
29 OFF029 IFS0 IEC0 IPC7
IPC7
Yes
Input Capture 6
_INPUT_CAPTURE_6_VECTOR
30 OFF030 IFS0 IEC0 IPC7
IPC7
Yes
Output Compare 6
_OUTPUT_COMPARE_6_VECTOR
31 OFF031 IFS0 IEC0 IPC7
IPC7
No
Timer7
_TIMER_7_VECTOR
32 OFF032 IFS1 IEC1 IPC8
IPC8
No
Input Capture 7 Error
_INPUT_CAPTURE_7_ERROR_VECTOR
33 OFF033 IFS1 IEC1 IPC8
IPC8
Yes
Input Capture 7
_INPUT_CAPTURE_7_VECTOR
34 OFF034 IFS1 IEC1 IPC8
IPC8
Yes
Output Compare 7
_OUTPUT_COMPARE_7_VECTOR
35 OFF035 IFS1 IEC1 IPC8
IPC8
No
Timer8
_TIMER_8_VECTOR
36 OFF036 IFS1 IEC1 IPC9
IPC9
No
Input Capture 8 Error
_INPUT_CAPTURE_8_ERROR_VECTOR
37 OFF037 IFS1 IEC1 IPC9
IPC9
Yes
Input Capture 8
_INPUT_CAPTURE_8_VECTOR
38 OFF038 IFS1 IEC1 IPC9
IPC9
Yes
Output Compare 8
_OUTPUT_COMPARE_8_VECTOR
39 OFF039 IFS1 IEC1 IPC9
IPC9
No
Timer9
_TIMER_9_VECTOR
40 OFF040 IFS1 IEC1 IPC10
IPC10
No
Input Capture 9 Error
_INPUT_CAPTURE_9_ERROR_VECTOR
41 OFF041 IFS1 IEC1 IPC10 IPC10
Yes
Input Capture 9
_INPUT_CAPTURE_9_VECTOR
42 OFF042 IFS1 IEC1 IPC10 IPC10
Yes
Output Compare 9
_OUTPUT_COMPARE_9_VECTOR
43 OFF043 IFS1 IEC1 IPC10 IPC10
No
ADC Global Interrupt
_ADC_VECTOR
44 OFF044 IFS1 IEC1 IPC11
IPC11
Yes
ADC FIFO Data Ready Interrupt
_ADC_FIFO_VECTOR
45 OFF045 IFS1 IEC1 IPC11 IPC11
Yes
ADC Digital Comparator 1
_ADC_DC1_VECTOR
46 OFF046 IFS1 IEC1 IPC11 IPC11
Yes
ADC Digital Comparator 2
_ADC_DC2_VECTOR
47 OFF047 IFS1 IEC1 IPC11 IPC11
Yes
ADC Digital Comparator 3
_ADC_DC3_VECTOR
48 OFF048 IFS1 IEC1 IPC12
IPC12
Yes
ADC Digital Comparator 4
_ADC_DC4_VECTOR
49 OFF049 IFS1 IEC1 IPC12 IPC12
Yes
Note 1:
2:
3:
4:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EF Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
This interrupt source is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2015-2016 Microchip Technology Inc.
TABLE 7-2:
INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Interrupt Bit Location
Persistent
Sub-priority Interrupt
Vector #
Flag
Enable
Priority
2015-2016 Microchip Technology Inc.
ADC Digital Comparator 5
_ADC_DC5_VECTOR
50 OFF050 IFS1 IEC1 IPC12 IPC12
Yes
ADC Digital Comparator 6
_ADC_DC6_VECTOR
51 OFF051 IFS1 IEC1 IPC12 IPC12
Yes
ADC Digital Filter 1
_ADC_DF1_VECTOR
52 OFF052 IFS1 IEC1 IPC13
IPC13
Yes
ADC Digital Filter 2
_ADC_DF2_VECTOR
53 OFF053 IFS1 IEC1 IPC13 IPC13
Yes
ADC Digital Filter 3
_ADC_DF3_VECTOR
54 OFF054 IFS1 IEC1 IPC13 IPC13
Yes
ADC Digital Filter 4
_ADC_DF4_VECTOR
55 OFF055 IFS1 IEC1 IPC13 IPC13
Yes
ADC Digital Filter 5
_ADC_DF5_VECTOR
56 OFF056 IFS1 IEC1 IPC14
IPC14
Yes
ADC Digital Filter 6
_ADC_DF6_VECTOR
57 OFF057 IFS1 IEC1 IPC14 IPC14
Yes
ADC Fault
_ADC_FAULT_VECTOR
58 OFF058 IFS1 IEC1 IPC14 IPC14
No
ADC Data 0
_ADC_DATA0_VECTOR
59 OFF059 IFS1 IEC1 IPC14 IPC14
Yes
ADC Data 1
_ADC_DATA1_VECTOR
60 OFF060 IFS1 IEC1 IPC15
IPC15
Yes
ADC Data 2
_ADC_DATA2_VECTOR
61 OFF061 IFS1 IEC1 IPC15 IPC15
Yes
ADC Data 3
_ADC_DATA3_VECTOR
62 OFF062 IFS1 IEC1 IPC15 IPC15
Yes
ADC Data 4
_ADC_DATA4_VECTOR
63 OFF063 IFS1 IEC1 IPC15 IPC15
Yes
ADC Data 5
_ADC_DATA5_VECTOR
64 OFF064 IFS2 IEC2 IPC16
IPC16
Yes
ADC Data 6
_ADC_DATA6_VECTOR
65 OFF065 IFS2 IEC2 IPC16 IPC16
Yes
ADC Data 7
_ADC_DATA7_VECTOR
66 OFF066 IFS2 IEC2 IPC16 IPC16
Yes
ADC Data 8
_ADC_DATA8_VECTOR
67 OFF067 IFS2 IEC2 IPC16 IPC16
Yes
ADC Data 9
_ADC_DATA9_VECTOR
68 OFF068 IFS2 IEC2 IPC17
IPC17
Yes
ADC Data 10
_ADC_DATA10_VECTOR
69 OFF069 IFS2 IEC2 IPC17 IPC17
Yes
ADC Data 11
_ADC_DATA11_VECTOR
70 OFF070 IFS2 IEC2 IPC17 IPC17
Yes
ADC Data 12
_ADC_DATA12_VECTOR
71 OFF071 IFS2 IEC2 IPC17 IPC17
Yes
ADC Data 13
_ADC_DATA13_VECTOR
72 OFF072 IFS2 IEC2 IPC18
IPC18
Yes
ADC Data 14
_ADC_DATA14_VECTOR
73 OFF073 IFS2 IEC2 IPC18 IPC18
Yes
ADC Data 15
_ADC_DATA15_VECTOR
74 OFF074 IFS2 IEC2 IPC18 IPC18
Yes
ADC Data 16
_ADC_DATA16_VECTOR
75 OFF075 IFS2 IEC2 IPC18 IPC18
Yes
ADC Data 17
_ADC_DATA17_VECTOR
76 OFF076 IFS2 IEC2 IPC19
IPC19
Yes
ADC Data 18
_ADC_DATA18_VECTOR
77 OFF077 IFS2 IEC2 IPC19 IPC19
Yes
Note 1:
2:
3:
4:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EF Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
This interrupt source is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 120
TABLE 7-2:
INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Interrupt Bit Location
Vector #
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
ADC Data 19(2)
_ADC_DATA19_VECTOR
78 OFF078 IFS2 IEC2 IPC19 IPC19
Yes
ADC Data 20(2)
_ADC_DATA20_VECTOR
79 OFF079 IFS2 IEC2 IPC19 IPC19
Yes
21(2)
_ADC_DATA21_VECTOR
80 OFF080 IFS2 IEC2 IPC20
IPC20
Yes
ADC Data 22(2)
_ADC_DATA22_VECTOR
81 OFF081 IFS2 IEC2 IPC20 IPC20
Yes
ADC Data 23(2)
_ADC_DATA23_VECTOR
82 OFF082 IFS2 IEC2 IPC20 IPC20
Yes
ADC Data 24(2)
_ADC_DATA24_VECTOR
83 OFF083 IFS2 IEC2 IPC20 IPC20
Yes
(2)
_ADC_DATA25_VECTOR
84 OFF084 IFS2 IEC2 IPC21
IPC21
Yes
ADC Data 26(2)
_ADC_DATA26_VECTOR
85 OFF085 IFS2 IEC2 IPC21 IPC21
Yes
ADC Data 27(2)
_ADC_DATA27_VECTOR
86 OFF086 IFS2 IEC2 IPC21 IPC21
Yes
ADC Data 28(2)
_ADC_DATA28_VECTOR
87 OFF087 IFS2 IEC2 IPC21 IPC21
Yes
29(2)
_ADC_DATA29_VECTOR
88 OFF088 IFS2 IEC2 IPC22
IPC22
Yes
ADC Data 30(2)
_ADC_DATA30_VECTOR
89 OFF089 IFS2 IEC2 IPC22 IPC22
Yes
ADC Data 31(2)
_ADC_DATA31_VECTOR
90 OFF090 IFS2 IEC2 IPC22 IPC22
Yes
ADC Data 32(2)
_ADC_DATA32_VECTOR
91 OFF091 IFS2 IEC2 IPC22 IPC22
Yes
33(2)
_ADC_DATA33_VECTOR
92 OFF092 IFS2 IEC2 IPC23
IPC23
Yes
ADC Data 34(2)
_ADC_DATA34_VECTOR
93 OFF093 IFS2 IEC2 IPC23 IPC23
Yes
ADC Data 35(2,3)
_ADC_DATA35_VECTOR
94 OFF094 IFS2 IEC2 IPC23 IPC23
Yes
ADC Data 36(2,3)
_ADC_DATA36_VECTOR
95 OFF095 IFS2 IEC2 IPC23 IPC23
Yes
(2,3)
_ADC_DATA37_VECTOR
96 OFF096 IFS3 IEC3 IPC24
IPC24
Yes
ADC Data 38(2,3)
_ADC_DATA38_VECTOR
97 OFF097 IFS3 IEC3 IPC24 IPC24
Yes
ADC Data 39(2,3)
_ADC_DATA39_VECTOR
98 OFF098 IFS3 IEC3 IPC24 IPC24
Yes
ADC Data 40(2,3)
_ADC_DATA40_VECTOR
99 OFF099 IFS3 IEC3 IPC24 IPC24
Yes
41(2,3)
_ADC_DATA41_VECTOR
100 OFF100 IFS3 IEC3 IPC25
IPC25
Yes
ADC Data 42(2,3)
_ADC_DATA42_VECTOR
101 OFF101 IFS3 IEC3 IPC25 IPC25
Yes
ADC Data 43
_ADC_DATA43_VECTOR
102 OFF102 IFS3 IEC3 IPC25 IPC25
Yes
ADC Data 44
_ADC_DATA44_VECTOR
103 OFF103 IFS3 IEC3 IPC25 IPC25
Yes
Core Performance Counter Interrupt
_CORE_PERF_COUNT_VECTOR
104 OFF104 IFS3 IEC3 IPC26
IPC26
No
Core Fast Debug Channel Interrupt
_CORE_FAST_DEBUG_CHAN_VECTOR
105 OFF105 IFS3 IEC3 IPC26 IPC26
Yes
ADC Data
ADC Data 25
ADC Data
ADC Data
ADC Data 37
ADC Data
DS60001320D-page 121
Note 1:
2:
3:
4:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EF Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
This interrupt source is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2015-2016 Microchip Technology Inc.
TABLE 7-2:
INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Interrupt Bit Location
Persistent
Sub-priority Interrupt
Vector #
Flag
Enable
Priority
System Bus Protection Violation
_SYSTEM_BUS_PROTECTION_VECTOR 106 OFF106 IFS3 IEC3 IPC26 IPC26
Yes
Crypto Engine Event
_CRYPTO_VECTOR
Yes
Reserved
—
107 OFF107 IFS3 IEC3 IPC26 IPC26
108
—
—
—
—
—
—
SPI1 Fault
_SPI1_FAULT_VECTOR
109 OFF109 IFS3 IEC3 IPC27 IPC27
Yes
SPI1 Receive Done
_SPI1_RX_VECTOR
110 OFF110 IFS3 IEC3 IPC27 IPC27
Yes
SPI1 Transfer Done
_SPI1_TX_VECTOR
111 OFF111 IFS3 IEC3 IPC27 IPC27
Yes
UART1 Fault
_UART1_FAULT_VECTOR
112 OFF112 IFS3 IEC3 IPC28
IPC28
Yes
UART1 Receive Done
_UART1_RX_VECTOR
113 OFF113 IFS3 IEC3 IPC28 IPC28
Yes
UART1 Transfer Done
_UART1_TX_VECTOR
114 OFF114 IFS3 IEC3 IPC28 IPC28
Yes
I2C1 Bus Collision Event
_I2C1_BUS_VECTOR
115 OFF115 IFS3 IEC3 IPC28 IPC28
Yes
I2C1 Slave Event
_I2C1_SLAVE_VECTOR
116 OFF116 IFS3 IEC3 IPC29
IPC29
Yes
I2C1 Master Event
_I2C1_MASTER_VECTOR
117 OFF117 IFS3 IEC3 IPC29 IPC29
Yes
PORTA Input Change Interrupt
(2)
_CHANGE_NOTICE_A_VECTOR
118 OFF118 IFS3 IEC3 IPC29 IPC29
Yes
PORTB Input Change Interrupt
_CHANGE_NOTICE_B_VECTOR
119 OFF119 IFS3 IEC3 IPC29 IPC29
Yes
PORTC Input Change Interrupt
_CHANGE_NOTICE_C_VECTOR
120 OFF120 IFS3 IEC3 IPC30
IPC30
Yes
PORTD Input Change Interrupt
_CHANGE_NOTICE_D_VECTOR
121 OFF121 IFS3 IEC3 IPC30 IPC30
Yes
PORTE Input Change Interrupt
_CHANGE_NOTICE_E_VECTOR
122 OFF122 IFS3 IEC3 IPC30 IPC30
Yes
PORTF Input Change Interrupt
_CHANGE_NOTICE_F_VECTOR
123 OFF123 IFS3 IEC3 IPC30 IPC30
Yes
PORTG Input Change Interrupt
_CHANGE_NOTICE_G_VECTOR
124 OFF124 IFS3 IEC3 IPC31
IPC31
Yes
PORTH Input Change Interrupt(2,3)
_CHANGE_NOTICE_H_VECTOR
125 OFF125 IFS3 IEC3 IPC31 IPC31
Yes
Interrupt(2,3)
PORTJ Input Change
2015-2016 Microchip Technology Inc.
_CHANGE_NOTICE_J_VECTOR
126 OFF126 IFS3 IEC3 IPC31 IPC31
Yes
PORTK Input Change Interrupt(2,3,4)
_CHANGE_NOTICE_K_VECTOR
127 OFF127 IFS3 IEC3 IPC31 IPC31
Yes
Parallel Master Port
_PMP_VECTOR
128 OFF128 IFS4 IEC4 IPC32
IPC32
Yes
Parallel Master Port Error
_PMP_ERROR_VECTOR
129 OFF129 IFS4 IEC4 IPC32 IPC32
Yes
Comparator 1 Interrupt
_COMPARATOR_1_VECTOR
130 OFF130 IFS4 IEC4 IPC32 IPC32
No
Comparator 2 Interrupt
_COMPARATOR_2_VECTOR
131 OFF131 IFS4 IEC4 IPC32 IPC32
No
USB General Event
_USB1_VECTOR
132 OFF132 IFS4 IEC4 IPC33
IPC33
Yes
USB DMA Event
_USB1_DMA_VECTOR
133 OFF133 IFS4 IEC4 IPC33 IPC33
Yes
Note 1:
2:
3:
4:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EF Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
This interrupt source is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 122
TABLE 7-2:
INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Interrupt Bit Location
Vector #
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
DMA Channel 0
_DMA0_VECTOR
134 OFF134 IFS4 IEC4 IPC33 IPC33
No
DMA Channel 1
_DMA1_VECTOR
135 OFF135 IFS4 IEC4 IPC33 IPC33
No
DMA Channel 2
_DMA2_VECTOR
136 OFF136 IFS4 IEC4 IPC34
IPC34
No
DMA Channel 3
_DMA3_VECTOR
137 OFF137 IFS4 IEC4 IPC34 IPC34
No
DMA Channel 4
_DMA4_VECTOR
138 OFF138 IFS4 IEC4 IPC34 IPC34
No
DMA Channel 5
_DMA5_VECTOR
139 OFF139 IFS4 IEC4 IPC34 IPC34
No
DMA Channel 6
_DMA6_VECTOR
140 OFF140 IFS4 IEC4 IPC35
No
DMA Channel 7
_DMA7_VECTOR
141 OFF141 IFS4 IEC4 IPC35 IPC35
No
SPI2 Fault
_SPI2_FAULT_VECTOR
142 OFF142 IFS4 IEC4 IPC35 IPC35
Yes
SPI2 Receive Done
_SPI2_RX_VECTOR
143 OFF143 IFS4 IEC4 IPC35 IPC35
Yes
SPI2 Transfer Done
_SPI2_TX_VECTOR
144 OFF144 IFS4 IEC4 IPC36
IPC36
Yes
UART2 Fault
_UART2_FAULT_VECTOR
145 OFF145 IFS4 IEC4 IPC36 IPC36
Yes
UART2 Receive Done
_UART2_RX_VECTOR
146 OFF146 IFS4 IEC4 IPC36 IPC36
Yes
UART2 Transfer Done
_UART2_TX_VECTOR
147 OFF147 IFS4 IEC4 IPC36 IPC36
Yes
I2C2 Bus Collision
Event(2)
IPC35
DS60001320D-page 123
_I2C2_BUS_VECTOR
148 OFF148 IFS4 IEC4 IPC37
IPC37
Yes
I2C2 Slave Event(2)
_I2C2_SLAVE_VECTOR
149 OFF149 IFS4 IEC4 IPC37 IPC37
Yes
I2C2 Master Event(2)
_I2C2_MASTER_VECTOR
150 OFF150 IFS4 IEC4 IPC37 IPC37
Yes
Control Area Network 1
_CAN1_VECTOR
151 OFF151 IFS4 IEC4 IPC37 IPC37
Yes
Control Area Network 2
_CAN2_VECTOR
152 OFF152 IFS4 IEC4 IPC38
IPC38
Yes
Ethernet Interrupt
_ETHERNET_VECTOR
153 OFF153 IFS4 IEC4 IPC38 IPC38
Yes
SPI3 Fault
_SPI3_FAULT_VECTOR
154 OFF154 IFS4 IEC4 IPC38 IPC38
Yes
SPI3 Receive Done
_SPI3_RX_VECTOR
155 OFF155 IFS4 IEC4 IPC38 IPC38
Yes
SPI3 Transfer Done
_SPI3_TX_VECTOR
156 OFF156 IFS4 IEC4 IPC39
IPC39
Yes
UART3 Fault
_UART3_FAULT_VECTOR
157 OFF157 IFS4 IEC4 IPC39 IPC39
Yes
UART3 Receive Done
_UART3_RX_VECTOR
158 OFF158 IFS4 IEC4 IPC39 IPC39
Yes
UART3 Transfer Done
_UART3_TX_VECTOR
159 OFF159 IFS4 IEC4 IPC39 IPC39
Yes
I2C3 Bus Collision Event
_I2C3_BUS_VECTOR
160 OFF160 IFS5 IEC5 IPC40
IPC40
Yes
I2C3 Slave Event
_I2C3_SLAVE_VECTOR
161 OFF161 IFS5 IEC5 IPC40 IPC40
Yes
Note 1:
2:
3:
4:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EF Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
This interrupt source is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2015-2016 Microchip Technology Inc.
TABLE 7-2:
INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Interrupt Bit Location
Persistent
Sub-priority Interrupt
Vector #
Flag
Enable
Priority
I2C3 Master Event
_I2C3_MASTER_VECTOR
162 OFF162 IFS5 IEC5 IPC40 IPC40
Yes
SPI4 Fault
_SPI4_FAULT_VECTOR
163 OFF163 IFS5 IEC5 IPC40 IPC40
Yes
SPI4 Receive Done
_SPI4_RX_VECTOR
164 OFF164 IFS5 IEC5 IPC41
IPC41
Yes
SPI4 Transfer Done
_SPI4_TX_VECTOR
165 OFF165 IFS5 IEC5 IPC41 IPC41
Yes
Real Time Clock
_RTCC_VECTOR
166 OFF166 IFS5 IEC5 IPC41 IPC41
No
Flash Control Event
_FLASH_CONTROL_VECTOR
167 OFF167 IFS5 IEC5 IPC41 IPC41
No
Prefetch Module SEC Event
_PREFETCH_VECTOR
168 OFF168 IFS5 IEC5 IPC42
IPC42
Yes
SQI1 Event
_SQI1_VECTOR
169 OFF169 IFS5 IEC5 IPC42 IPC42
Yes
UART4 Fault
_UART4_FAULT_VECTOR
170 OFF170 IFS5 IEC5 IPC42 IPC42
Yes
UART4 Receive Done
_UART4_RX_VECTOR
171 OFF171 IFS5 IEC5 IPC42 IPC42
Yes
UART4 Transfer Done
_UART4_TX_VECTOR
172 OFF172 IFS5 IEC5 IPC43
IPC43
Yes
I2C4 Bus Collision Event
_I2C4_BUS_VECTOR
173 OFF173 IFS5 IEC5 IPC43 IPC43
Yes
I2C4 Slave Event
_I2C4_SLAVE_VECTOR
174 OFF174 IFS5 IEC5 IPC43 IPC43
Yes
I2C4 Master Event
_I2C4_MASTER_VECTOR
175 OFF175 IFS5 IEC5 IPC43 IPC43
Yes
SPI5 Fault(2)
_SPI5_FAULT_VECTOR
176 OFF176 IFS5 IEC5 IPC44
IPC44
Yes
SPI5 Receive Done(2)
_SPI5_RX_VECTOR
177 OFF177 IFS5 IEC5 IPC44 IPC44
Yes
Done(2)
SPI5 Transfer
2015-2016 Microchip Technology Inc.
_SPI5_TX_VECTOR
178 OFF178 IFS5 IEC5 IPC44 IPC44
Yes
UART5 Fault
_UART5_FAULT_VECTOR
179 OFF179 IFS5 IEC5 IPC44 IPC44
Yes
UART5 Receive Done
_UART5_RX_VECTOR
180 OFF180 IFS5 IEC5 IPC45
IPC45
Yes
UART5 Transfer Done
_UART5_TX_VECTOR
181 OFF181 IFS5 IEC5 IPC45 IPC45
Yes
I2C5 Bus Collision Event
_I2C5_BUS_VECTOR
182 OFF182 IFS5 IEC5 IPC45 IPC45
Yes
I2C5 Slave Event
_I2C5_SLAVE_VECTOR
183 OFF183 IFS5 IEC5 IPC45 IPC45
Yes
I2C5 Master Event
_I2C5_MASTER_VECTOR
184 OFF184 IFS5 IEC5 IPC46
IPC46
Yes
SPI6 Fault(2)
_SPI6_FAULT_VECTOR
185 OFF185 IFS5 IEC5 IPC46 IPC46
Yes
(2)
_SPI6_RX_VECTOR
186 OFF186 IFS5 IEC5 IPC46 IPC46
Yes
SPI6 Transfer Done(2)
_SPI6_TX_VECTOR
187 OFF187 IFS5 IEC5 IPC46 IPC46
Yes
UART6 Fault
_UART6_FAULT_VECTOR
188 OFF188 IFS5 IEC5 IPC47
IPC47
Yes
UART6 Receive Done
_UART6_RX_VECTOR
189 OFF189 IFS5 IEC5 IPC47 IPC47
Yes
SPI6 Receive Done
Note 1:
2:
3:
4:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EF Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
This interrupt source is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 124
TABLE 7-2:
INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
UART6 Transfer Done
Reserved
XC32 Vector Name
_UART6_TX_VECTOR
—
IRQ
#
Interrupt Bit Location
Vector #
Flag
Enable
Priority
Sub-priority
190 OFF190 IFS5 IEC5 IPC47 IPC47
191
—
—
—
—
—
IPC48
IPC48
Yes
IPC48
Yes
_ADC_EOS_VECTOR
192 OFF192 IFS6 IEC6
ADC Analog Circuits Ready
_ADC_ARDY_VECTOR
193 OFF193 IFS6 IEC6 IPC48
ADC Update Ready
_ADC_URDY_VECTOR
194 OFF194 IFS6 IEC6 IPC48 IPC48
—
ADC Group Early Interrupt Request
Reserved
_ADC_EARLY_VECTOR
—
195
—
—
—
196 OFF196 IFS6 IEC6
197
—
—
—
Yes
—
ADC End of Scan Ready
Reserved
Persistent
Interrupt
Yes
—
—
—
IPC49
IPC49
Yes
—
—
—
ADC0 Early Interrupt
_ADC0_EARLY_VECTOR
198 OFF198 IFS6 IEC6 IPC49 IPC49
Yes
ADC1 Early Interrupt
_ADC1_EARLY_VECTOR
199 OFF199 IFS6 IEC6 IPC49 IPC49
Yes
ADC2 Early Interrupt
_ADC2_EARLY_VECTOR
200 OFF200 IFS6 IEC6
IPC50
Yes
ADC3 Early Interrupt
_ADC2_EARLY_VECTOR
201 OFF201 IFS6 IEC6 IPC50
IPC50
Yes
ADC4 Early Interrupt
_ADC4_EARLY_VECTOR
202 OFF202 IFS6 IEC6 IPC50 IPC50
Reserved
Reserved
IPC50
—
203
—
—
—
—
—
204
—
—
—
—
—
Yes
—
—
—
IPC51
Yes
ADC7 Early Interrupt
_ADC7_EARLY_VECTOR
205 OFF205 IFS6 IEC6 IPC51
ADC0 Warm Interrupt
_ADC0_WARM_VECTOR
206 OFF206 IFS6 IEC6 IPC51 IPC51
Yes
ADC1 Warm Interrupt
_ADC1_WARM_VECTOR
207 OFF207 IFS6 IEC6 IPC51 IPC51
Yes
ADC2 Warm Interrupt
_ADC2_WARM_VECTOR
208 OFF208 IFS6 IEC6
IPC52
Yes
ADC3 Warm Interrupt
_ADC3_WARM_VECTOR
209 OFF209 IFS6 IEC6 IPC52
IPC52
Yes
ADC4 Warm Interrupt
_ADC4_WARM_VECTOR
210 OFF210 IFS6 IEC6 IPC52 IPC52
Reserved
Reserved
ADC7 Warm Interrupt
IPC52
—
211
—
—
—
—
—
212
—
—
—
—
_ADC7_WARM_VECTOR
213 OFF213 IFS6 IEC6 IPC53
Lowest Natural Order Priority
DS60001320D-page 125
Note 1:
2:
3:
4:
Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EF Family Features” for the list of available peripherals.
This interrupt source is not available on 64-pin devices.
This interrupt source is not available on 100-pin devices.
This interrupt source is not available on 124-pin devices.
—
Yes
—
—
—
IPC53
Yes
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2015-2016 Microchip Technology Inc.
TABLE 7-2:
Interrupt Control Registers
0000 INTCON
0010 PRISS
0020 INTSTAT
0030 IPTMR
0040 IFS0
(6)
0080 IFS4
0090 IFS5
00A0 IFS6
29/13
28/12
—
—
—
MVEC
31:16
15:0
2015-2016 Microchip Technology Inc.
00E0 IEC2
25/9
24/8
—
TPC
23/7
22/6
21/5
—
—
—
—
—
—
—
—
0000
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
31:16
PRI7SS
PRI6SS
PRI5SS
15:0
PRI3SS
PRI2SS
PRI1SS
31:16
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
20/4
19/3
18/2
17/1
16/0
PRI4SS
—
SRIPL
0000
—
—
—
SS0
0000
—
—
—
—
0000
SIRQ
31:16
0000
0000
IPTMR
15:0
0000
31:16
OC6IF
IC6IF
IC6EIF
T6IF
OC5IF
IC5IF
IC5EIF
T5IF
INT4IF
OC4IF
IC4IF
IC4EIF
T4IF
INT3IF
OC3IF
IC3IF
0000
15:0
IC3EIF
T3IF
INT2IF
OC2IF
IC2IF
IC2EIF
T2IF
INT1IF
OC1IF
IC1IF
IC1EIF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
ADCD3IF
ADCD2IF
ADCD1IF
ADCD0IF
ADCFLTIF
ADCIF
OC9IF
ADCDF6IF ADCDF5IF ADCDF4IF ADCDF3IF ADCDF2IF ADCDF1IF ADCDC6IF ADCDC5IF
IC9IF
IC9EIF
T9IF
IC7IF
IC7EIF
ADCD31IF
ADCD30IF
ADCD29IF
ADCD28IF ADCD27IF ADCD26IF ADCD25IF ADCD24IF
ADCD23IF
ADCD22IF
ADCD21IF 0000
15:0 ADCD20IF ADCD19IF ADCD18IF ADCD17IF ADCD16IF
ADCD12IF ADCD11IF ADCD10IF
ADCD5IF 0000
31:16 CNKIF(8)
ADCD15IF
ADCD14IF
ADCD13IF
CNJIF
CNHIF
CNGIF
CNFIF
CNEIF
CNDIF
CNCIF
OC8IF
CNBIF
IC8IF
CNAIF
IC8EIF
I2C1MIF
T8IF
OC7IF
ADCDC4IF ADCDC3IF 0000
31:16 ADCD36IF ADCD35IF ADCD34IF ADCD33IF ADCD32IF
T7IF
0000
ADCD9IF
ADCD8IF
ADCD7IF
ADCD6IF
I2C1SIF
I2C1BIF
U1TXIF
U1RXIF
ADCD39IF
ADCD38IF
ADCD37IF 0000
SPI2TXIF 0000
15:0
SPI1TXIF
SPI1RXIF
SPI1EIF
—
CRPTIF(7)
SBIF
CFDCIF
CPCIF
31:16
U3TXIF
U3RXIF
U3EIF
SPI3TXIF
SPI3RXIF
SPI3EIF
ETHIF
CAN2IF(3)
CAN1IF(3)
U2TXIF
U2RXIF
U2EIF
15:0
SPI2RXIF
SPI2EIF
DMA7IF
DMA6IF
DMA5IF
DMA4IF
DMA3IF
DMA2IF
DMA1IF
DMA0IF
USBDMAIF
USBIF
CMP2IF
CMP1IF
PMPEIF
31:16
—
U6TXIF
U6RXIF
U6EIF
SPI6TX(2)
SPI6RXIF(2)
SPI6IF(2)
I2C5MIF
I2C5SIF
I2C5BIF
U5TXIF
U5RXIF
U5EIF
15:0
I2C4MIF
I2C4SIF
I2C4BIF
U4TXIF
U4RXIF
U4EIF
SQI1IF
PREIF
FCEIF
RTCCIF
SPI4TXIF
SPI4RXIF
SPI4EIF
I2C3MIF
I2C3SIF
31:16
—
—
—
—
—
—
—
—
—
—
ADC7WIF
—
—
ADC4WIF
ADC3WIF
ADCD44IF ADCD43IF ADCD42IF ADCD41IF ADCD40IF
I2C2MIF(2) I2C2SIF(2) I2C2BIF(2)
U1EIF
PMPIF
0000
0000
SPI5TXIF(2) SPI5RXIF(2) SPI5EIF(2) 0000
I2C3BIF
0000
ADC2WIF 0000
ADC0WIF
ADC7EIF
—
—
ADC4EIF
ADC3EIF
ADC2EIF
ADC1EIF
ADC0EIF
—
ADCGRPIF
—
31:16
OC6IE
IC6IE
IC6EIE
T6IE
OC5IE
IC5IE
IC5EIE
T5IE
INT4IE
OC4IE
IC4IE
IC4EIE
T4IE
INT3IE
OC3IE
IC3IE
0000
15:0
IC3EIE
T3IE
INT2IE
OC2IE
IC2IE
IC2EIE
T2IE
INT1IE
OC1IE
IC1IE
IC1EIE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
0000
ADCD3IE
ADCD2IE
ADCD1IE
ADCD0IE
ADCFLTIE
ADCIE
OC9IE
15:0 ADCDC2IE ADCDC1IE ADCFIFOIE
(5)
26/10
NMIKEY
31:16 ADCD4IE
00D0 IEC1
27/11
All Resets
30/14
15:0 ADC1WIF
00C0 IEC0
Note
31/15
15:0 ADCDC2IF ADCDC1IF ADCFIFOIF
0060 IFS2(5)
Legend:
Bits
31:16 ADCD4IF
0050 IFS1
0070 IFS3
INTERRUPT REGISTER MAP
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
TABLE 7-3:
IC9IE
ADCURDYIF ADCARDYIF ADCEOSIF 0000
ADCDF6IE ADCDF5IE ADCDF4IE ADCDF3IE ADCDF2IE ADCDF1IE ADCDC6IE ADCDC5IE
IC9EIE
T9IE
OC8IE
IC8IE
IC8EIE
T8IE
OC7IE
IC7IE
ADCDC4IE ADCDC3IE 0000
IC7EIE
T7IE
0000
31:16 ADCD36IE ADCD35IE ADCD34IE ADCD33IE ADCD32IE
ADCD31IE
ADCD30IE ADCD29IE ADCD28IE ADCD27IE ADCD26IE ADCD25IE ADCD24IE
ADCD23IE
ADCD22IE ADCD21IE 0000
15:0 ADCD20IE ADCD19IE ADCD18IE ADCD17IE ADCD16IE
ADCD15IE
ADCD14IE ADCD13IE ADCD12IE ADCD11IE ADCD10IE ADCD9IE
ADCD7IE
ADCD6IE
ADCD8IE
ADCD5IE 0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 126
7.3
0100 IEC4
0110 IEC5
0120 IEC6
0140 IPC0
0150 IPC1
0160 IPC2
0170 IPC3
0180 IPC4
0190 IPC5
01A0 IPC6
01B0 IPC7
01C0 IPC8
01D0 IPC9
01E0 IPC10
DS60001320D-page 127
Legend:
Note
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
CNBIE
CNAIE
I2C1MIE
I2C1SIE
I2C1BIE
18/2
16/0
U1RXIE
U1EIE
31:16
CNKIE
CNJIE
CNHIE
CNGIE
CNFIE
CNEIE
CNDIE
CNCIE
15:0
SPI1TXIE
SPI1RXIE
SPI1EIE
—
CRPTIE(7)
SBIE
CFDCIE
CPCIE
31:16
U3TXIE
U3RXIE
U3EIE
SPI3TXIE
SPI3RXIE
SPI3EIE
ETHIE
CAN2IE(3)
U2TXIE
U2RXIE
U2EIE
15:0 SPI2RXIE
SPI2EIE
DMA7IE
DMA6IE
DMA5IE
DMA4IE
DMA3IE
DMA2IE
DMA1IE
DMA0IE
USBDMAIE
USBIE
CMP2IE
CMP1IE
PMPEIE
31:16
—
U6TXIE
U6RXIE
U6EIE
SPI6IE(2)
I2C5MIE
I2C5SIE
I2C5BIE
U5TXIE
U5RXIE
U5EIE
15:0
I2C4MIE
I2C4SIE
I2C4BIE
U4TXIE
U4RXIE
U4EIE
SQI1IE
PREIE
FCEIE
RTCCIE
SPI4TXIE
SPI4RXIE
SPI4EIE
I2C3MIE
I2C3SIE
31:16
—
—
—
—
—
—
—
—
—
—
ADC7WIE
—
—
ADC4WIE
ADC3WIE
—
—
ADC4EIE
ADC3EIF
ADC2EIE
ADCGRPIE
15:0 ADC1WIE
SPI6TXIE(2) SPI6RXIE(2)
U1TXIE
17/1
ADCD44IE ADCD43IE ADCD42IE ADCD41IE ADCD40IE
CAN1IE(3) I2C2MIE(2) I2C2SIE(2) I2C2BIE(2)
—
ADCD39IE
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
00F0 IEC3(6)
INTERRUPT REGISTER MAP (CONTINUED)
0000
ADCD38IE ADCD37IE 0000
SPI2TXIE 0000
PMPIE
0000
SPI5TXIE(2) SPI5RXIE(2) SPI5EIE(2) 0000
I2C3BIE
0000
ADC2WIE 0000
ADC0WIE
ADC7EIE
ADC1EIE
ADC0EIE
—
31:16
—
—
—
INT0IP
INT0IS
—
—
—
CS1IP
ADCURDYIE ADCARDYIE ADCEOSIE 0000
CS1IS
0000
15:0
—
—
—
CS0IP
CS0IS
—
—
—
CTIP
CTIS
0000
31:16
—
—
—
OC1IP
OC1IS
—
—
—
IC1IP
IC1IS
0000
15:0
—
—
—
IC1EIP
IC1EIS
—
—
—
T1IP
T1IS
0000
31:16
—
—
—
IC2IP
IC2IS
—
—
—
IC2EIP
IC2EIS
0000
15:0
—
—
—
T2IP
T2IS
—
—
—
INT1IP
INT1IS
0000
31:16
—
—
—
IC3EIP
IC3EIS
—
—
—
T3IP
T3IS
0000
15:0
—
—
—
INT2IP
INT2IS
—
—
—
OC2IP
OC2IS
0000
31:16
—
—
—
T4IP
T4IS
—
—
—
INT3IP
INT3IS
0000
15:0
—
—
—
OC3IP
OC3IS
—
—
—
IC3IP
IC3IS
0000
31:16
—
—
—
INT4IP
INT4IS
—
—
—
OC4IP
OC4IS
0000
15:0
—
—
—
IC4IP
IC4IS
—
—
—
IC4EIP
IC4EIS
0000
31:16
—
—
—
OC5IP
OC5IS
—
—
—
IC5IP
IC5IS
0000
15:0
—
—
—
IC5EIP
IC5EIS
—
—
—
T5IP
T5IS
0000
31:16
—
—
—
OC6IP
OC6IS
—
—
—
IC6IP
IC6IS
0000
15:0
—
—
—
IC6EIP
IC6EIS
—
—
—
T6IP
T6IS
0000
31:16
—
—
—
OC7IP
OC7IS
—
—
—
IC7IP
IC7IS
0000
15:0
—
—
—
IC7EIP
IC7EIS
—
—
—
T7IP
T7IS
0000
31:16
—
—
—
OC8IP
OC8IS
—
—
—
IC8IP
IC8IS
0000
15:0
—
—
—
IC8EIP
IC8EIS
—
—
—
T8IP
T8IS
0000
31:16
—
—
—
OC9IP
OC9IS
—
—
—
IC9IP
IC9IS
0000
15:0
—
—
—
IC9EIP
IC9EIS
—
—
—
T9IP
T9IS
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2015-2016 Microchip Technology Inc.
TABLE 7-3:
0200 IPC12
0210 IPC13
0220 IPC14
0230 IPC15
0240 IPC16
0250 IPC17
0260 IPC18
0270 IPC19
0280 IPC20
0290 IPC21
02A0 IPC22
2015-2016 Microchip Technology Inc.
02B0 IPC23
02C0 IPC24
02D0 IPC25
Legend:
Note
Bits
31/15
30/14
29/13
28/12
27/11
31:16
—
—
—
ADCDC2IP
15:0
—
—
—
ADCFIFOIP
31:16
—
—
—
ADCDC6IP
15:0
—
—
—
31:16
—
—
15:0
—
31:16
26/10
25/9
24/8
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
01F0 IPC11
INTERRUPT REGISTER MAP (CONTINUED)
23/7
22/6
21/5
ADCDC2IS
—
—
—
ADCDC1IP
ADCDC1IS
0000
ADCFIFOIS
—
—
—
ADCIP
ADCIS
0000
ADCDC6IS
—
—
—
ADCDC5IP
ADCDC5IS
0000
ADCDC4IP
ADCDC4IS
—
—
—
ADCDC3IP
ADCDC3IS
0000
—
ADCDF4IP
ADCDF4IS
—
—
—
ADCDF3IP
ADCDF3IS
0000
—
—
ADCDF2IP
ADCDF2IS
—
—
—
ADCDF1IP
ADCDF1IS
0000
—
—
—
ADCD0IP
ADCD0IS
—
—
—
ADCDFLTIP
ADCDFLTIS
0000
15:0
—
—
—
ADCDF6IP
ADCDF6IS
—
—
—
ADCDF5IP
ADCDF5IS
0000
31:16
—
—
—
ADCD4IP
ADCD4IS
—
—
—
ADCD3IP
ADCD3IS
0000
15:0
—
—
—
ADCD2IP
ADCD2IS
—
—
—
ADCD1IP
ADCD1IS
0000
31:16
—
—
—
ADCD8IP
ADCD8IS
—
—
—
ADCD7IP
ADCD7IS
0000
15:0
—
—
—
ADCD6IP
ADCD6IS
—
—
—
ADCD5IP
ADCD5IS
0000
31:16
—
—
—
ADCD12IP
ADCD12IS
—
—
—
ADCD11IP
ADCD11IS
0000
15:0
—
—
—
ADCD10IP
ADCD10IS
—
—
—
ADCD9IP
ADCD9IS
0000
31:16
—
—
—
ADCD16IP
ADCD16IS
—
—
—
ADCD15IP
ADCD15IS
0000
15:0
—
—
—
ADCD14IP
ADCD14IS
—
—
—
ADCD13IP
ADCD13IS
0000
31:16
—
—
—
ADCD20IP(2)
ADCD20IS(2)
—
—
—
ADCD19IP(2)
ADCD19IS(2)
0000
15:0
—
—
—
ADCD18IP
ADCD18IS
—
—
—
ADCD17IP
ADCD17IS
0000
31:16
—
—
—
ADCD24IP(2)
ADCD24IS(2)
—
—
—
ADCD23IP(2)
ADCD23IS(2)
0000
15:0
—
—
—
ADCD22IP(2)
ADCD22IS(2)
—
—
—
ADCD21IP(2)
ADCD21IS(2)
0000
31:16
—
—
—
ADCD28IP(2)
ADCD28IS(2)
—
—
—
ADCD27IP(2)
ADCD27IS(2)
0000
15:0
—
—
—
ADCD26IP(2)
ADCD26IS(2)
—
—
—
ADCD25IP(2)
ADCD25IS(2)
0000
31:16
—
—
—
ADCD32IP(2)
ADCD32IS(2)
—
—
—
ADCD31IP(2)
ADCD31IS(2)
0000
15:0
—
—
—
ADCD30IP(2)
ADCD30IS(2)
—
—
—
ADCD29IP(2)
ADCD29IS(2)
0000
31:16
—
—
—
ADCD36IP(2,4)
ADCD36IS(2,4)
—
—
—
ADCD35IP(2,4)
ADCD35IS(2,4)
0000
15:0
—
—
—
ADCD34IP(2)
ADCD34IS(2)
—
—
—
ADCD33IP(2)
ADCD33IS(2)
0000
31:16
—
—
—
ADCD40IP(2,4)
ADCD40IS(2,4)
—
—
—
ADCD39IP(2,4)
ADCD39IS(2,4)
0000
15:0
—
—
—
ADCD38IP(2,4)
ADCD38IS(2,4)
—
—
—
ADCD37IP(2,4)
ADCD37IS(2,4)
0000
31:16
—
—
—
ADCD44IP
ADCD44IS
—
—
—
ADCD43IP
ADCD43IS
0000
15:0
—
—
—
ADCD42IP(2,4)
ADCD42IS(2,4)
—
—
—
ADCD41IP(2,4)
ADCD41IS(2,4)
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 128
TABLE 7-3:
02F0 IPC27
0300 IPC28
0310 IPC29
0320 IPC30
0330 IPC31
0340 IPC32
0350 IPC33
0360 IPC34
0370 IPC35
0380 IPC36
0390 IPC37
03A0 IPC38
03B0 IPC39
03C0 IPC40
DS60001320D-page 129
Legend:
Note
Bits
31/15
30/14
29/13
28/12
27/11
31:16
—
—
—
CRPTIP(7)
15:0
—
—
—
CFDCIP
31:16
—
—
—
15:0
—
—
31:16
—
15:0
26/10
25/9
24/8
20/4
23/7
22/6
21/5
CRPTIS(7)
—
—
—
SBIP
SBIS
0000
CFDCIS
—
—
—
CPCIP
CPCIS
0000
SPI1TXIP
SPI1TXIS
—
—
—
SPI1RXIP
SPI1RXIS
0000
—
SPI1EIP
SPI1EIS
—
—
—
—
0000
—
—
I2C1BIP
I2C1BIS
—
—
—
U1TXIP
U1TXIS
0000
—
—
—
U1RXIP
U1RXIS
—
—
—
U1EIP
U1EIS
0000
31:16
—
—
—
CNBIP
CNBIS
—
—
—
CNAIP(2)
CNAIS(2)
0000
15:0
—
—
—
I2C1MIP
I2C1MIS
—
—
—
I2C1SIP
I2C1SIS
0000
31:16
—
—
—
CNFIP
CNFIS
—
—
—
CNEIP
CNEIS
0000
15:0
—
—
—
CNDIP
CNDIS
—
—
—
CNCIP
CNCIS
0000
31:16
—
—
—
CNKIP(2,4,8)
CNKIS(2,4,8)
—
—
—
CNJIP(2,4)
CNJIS(2,4)
0000
15:0
—
—
—
CNHIP(2,4)
CNHIS(2,4)
—
—
—
CNGIP
CNGIS
0000
31:16
—
—
—
CMP2IP
CMP2IS
—
—
—
CMP1IP
CMP1IS
0000
15:0
—
—
—
PMPEIP
PMPEIS
—
—
—
PMPIP
PMPIS
0000
31:16
—
—
—
DMA1IP
DMA1IS
—
—
—
DMA0IP
DMA0IS
0000
15:0
—
—
—
USBDMAIP
USBDMAIS
—
—
—
USBIP
USBIS
0000
31:16
—
—
—
DMA5IP
DMA5IS
—
—
—
DMA4IP
DMA4IS
0000
15:0
—
—
—
DMA3IP
DMA3IS
—
—
—
DMA2IP
DMA2IS
0000
31:16
—
—
—
SPI2RXIP
SPI2RXIS
—
—
—
SPI2EIP
SPI2EIS
0000
15:0
—
—
—
DMA7IP
DMA7IS
—
—
—
DMA6IP
DMA6IS
0000
31:16
—
—
—
U2TXIP
U2TXIS
—
—
—
U2RXIP
U2RXIS
0000
15:0
—
—
—
U2EIP
U2EIS
—
—
—
SPI2TXIP
SPI2TXIS
0000
31:16
—
—
—
CAN1IP(3)
CAN1IS(3)
—
—
—
I2C2MIP(2)
I2C2MIS(2)
0000
15:0
—
—
—
I2C2SIP(2)
I2C2SIS(2)
—
—
—
I2C2BIP(2)
I2C2BIS(2)
0000
31:16
—
—
—
SPI3RXIP
SPI3RXIS
—
—
—
SPI3EIP
SPI3EIS
0000
15:0
—
—
—
ETHIP
ETHIS
—
—
—
CAN2IP(3)
CAN2IS(3)
0000
31:16
—
—
—
U3TXIP
U3TXIS
—
—
—
U3RXIP
U3RXIS
0000
15:0
—
—
—
U3EIP
U3EIS
—
—
—
SPI3TXIP
SPI3TXIS
0000
31:16
—
—
—
SPI4EIP
SPI4EIS
—
—
—
I2C3MIP
I2C3MIS
0000
15:0
—
—
—
I2C3SIP
I2C3SIS
—
—
—
I2C3BIP
I2C3BIS
0000
—
19/3
—
18/2
—
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
02E0 IPC26
INTERRUPT REGISTER MAP (CONTINUED)
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2015-2016 Microchip Technology Inc.
TABLE 7-3:
03E0 IPC42
03F0 IPC43
0400 IPC44
0410 IPC45
0420 IPC46
0430 IPC47
0440 IPC48
0450 IPC49
0460 IPC50
0470 IPC51
0480 IPC52
2015-2016 Microchip Technology Inc.
0490 IPC53
0540 OFF000
0544 OFF001
Legend:
Note
Bits
31/15
30/14
29/13
28/12
23/7
22/6
21/5
31:16
—
—
—
FCEIP
15:0
—
—
—
SPI4TXIP
FCEIS
—
—
—
RTCCIP
RTCCIS
0000
SPI4TXIS
—
—
—
SPI4RXIP
SPI4RXIS
31:16
—
—
—
U4RXIP
0000
U4RXIS
—
—
—
U4EIP
U4EIS
15:0
—
—
—
0000
SQI1IP
SQI1IS
—
—
—
PREIP
PREIS
31:16
—
—
0000
—
I2C4MIP
I2C4MIS
—
—
—
I2C4SIP
I2C4SIS
15:0
—
0000
—
—
I2C4BIP
I2C4BIS
—
—
—
U4TXIP
U4TXIS
31:16
0000
—
—
—
U5EIP
U5EIS
—
—
—
SPI5TXIP(2)
SPI5TXIS(2)
0000
15:0
—
—
—
SPI5RXIP(2)
SPI5RXIS(2)
—
—
—
SPI5EIP(2)
SPI5EIS(2)
0000
31:16
—
—
—
I2C5SIP
I2C5SIS
—
—
—
I2C5BIP
I2C5BIS
0000
15:0
—
—
—
U5TXIP
U5TXIS
—
—
—
U5RXIP
U5RXIS
0000
31:16
—
—
—
SPI6TXIP(2)
SPI6TXIS(2)
—
—
—
SPI6RXIP(2)
SPI6RXIS(2)
0000
15:0
—
—
—
SPI6EIP(2)
SPI6EIS(2)
—
—
—
I2C5MIP
I2C5MIS
0000
31:16
—
—
—
—
—
—
U6TXIP
U6TXIS
0000
15:0
—
—
—
U6RXIS
—
—
—
U6EIP
U6EIS
0000
31:16
—
—
—
—
—
—
—
ADCURDYIP
ADCURDYIS
0000
15:0
—
—
—
ADCARDYIP
ADCARDYIS
—
—
—
ADCEOSIP
ADCEOSIS
0000
31:16
—
—
—
ADC1EIP
ADC1EIS
ADC0EIP
ADC0EIS
0000
15:0
—
—
—
—
—
—
—
—
ADCGRPIP
ADCGRPIS
0000
31:16
—
—
—
—
—
—
—
—
ADC4EIP
ADC4EIS
0000
15:0
—
—
—
ADC3EIP
ADC3EIS
ADC2EIP
ADC2EIS
0000
31:16
—
—
—
ADC1WIP
ADC1WIS
ADC0WIP
ADC0WIS
0000
15:0
—
—
—
ADC7EIP
ADC7EIS
—
—
0000
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
—
27/11
—
26/10
—
U6RXIP
—
—
—
—
—
—
ADC3WIP
—
—
—
ADC7WIP
—
—
—
25/9
—
15:0
—
—
—
20/4
—
19/3
—
18/2
—
—
—
—
—
—
16/0
ADC4WIP
ADC4WIS
0000
ADC3WIS
ADC2WIP
ADC2WIS
0000
—
—
—
—
—
—
—
0000
ADC7WIS
—
—
—
—
—
0000
—
—
—
VOFF
—
—
—
—
—
VOFF
—
17/1
—
15:0
31:16
24/8
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
03D0 IPC41
INTERRUPT REGISTER MAP (CONTINUED)
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
0000
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 130
TABLE 7-3:
054C OFF003
0550 OFF004
0554 OFF005
0558 OFF006
055C OFF007
0560 OFF008
0564 OFF009
0568 OFF010
056C OFF011
0570 OFF012
0574 OFF013
0578 OFF014
057C OFF015
0580 OFF016
DS60001320D-page 131
Legend:
Note
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
VOFF
VOFF
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
16/0
—
VOFF
—
17/1
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
VOFF
—
—
—
—
—
—
—
VOFF
—
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
0548 OFF002
INTERRUPT REGISTER MAP (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2015-2016 Microchip Technology Inc.
TABLE 7-3:
0588 OFF018
058C OFF019
0590 OFF020
0594 OFF021
0598 OFF022
059C OFF023
05A0 OFF024
05A4 OFF025
05A8 OFF026
05AC OFF027
05B0 OFF028
2015-2016 Microchip Technology Inc.
05B4 OFF029
05B8 OFF030
05BC OFF031
Legend:
Note
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
VOFF
VOFF
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
16/0
—
VOFF
—
17/1
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
VOFF
—
—
—
—
—
—
—
VOFF
—
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
0584 OFF017
INTERRUPT REGISTER MAP (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 132
TABLE 7-3:
05C4 OFF033
05C8 OFF034
05CC OFF035
05D0 OFF036
05D4 OFF037
05D8 OFF038
05DC OFF039
05E0 OFF040
05E4 OFF041
05E8 OFF042
05EC OFF043
05F0 OFF044
05F4 OFF045
05F8 OFF046
DS60001320D-page 133
Legend:
Note
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
VOFF
VOFF
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
16/0
—
VOFF
—
17/1
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
VOFF
—
—
—
—
—
—
—
VOFF
—
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
05C0 OFF032
INTERRUPT REGISTER MAP (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2015-2016 Microchip Technology Inc.
TABLE 7-3:
0600 OFF048
0604 OFF049
0608 OFF050
060C OFF051
0610 OFF052
0614 OFF053
0618 OFF054
061C OFF055
0620 OFF056
0624 OFF057
0628 OFF058
2015-2016 Microchip Technology Inc.
062C OFF059
0630 OFF060
0634 OFF061
Legend:
Note
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
VOFF
VOFF
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
16/0
—
VOFF
—
17/1
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
VOFF
—
—
—
—
—
—
—
VOFF
—
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
05FC OFF047
INTERRUPT REGISTER MAP (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 134
TABLE 7-3:
063C OFF063
0640 OFF064
0644 OFF065
0648 OFF066
064C OFF067
0650 OFF068
0654 OFF069
0658 OFF070
065C OFF071
0660 OFF072
0664 OFF073
0668 OFF074
066C OFF075
0670 OFF076
DS60001320D-page 135
Legend:
Note
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
VOFF
VOFF
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
16/0
—
VOFF
—
17/1
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
VOFF
—
—
—
—
—
—
—
VOFF
—
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
0638 OFF062
INTERRUPT REGISTER MAP (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2015-2016 Microchip Technology Inc.
TABLE 7-3:
0678 OFF078
(2)
0680 OFF080
(2)
0684 OFF081
(2)
(2)
(2)
2015-2016 Microchip Technology Inc.
06A0 OFF088
(2)
06A4 OFF089
(2)
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
31:16
31:16
31:16
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
31:16
—
—
—
—
—
—
31:16
(2)
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
VOFF
VOFF
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
16/0
—
VOFF
—
17/1
—
VOFF
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
VOFF
—
—
—
—
—
—
—
VOFF
—
All Resets
27/11
15:0
06A8 OFF090(2)
Note
28/12
15:0
069C OFF087(2)
Legend:
29/13
15:0
0694 OFF085(2)
06AC OFF091
30/14
15:0
OFF084(2)
0698 OFF086
31/15
15:0
0688 OFF082(2)
0690
31:16
Bits
15:0
067C OFF079(2)
068C OFF083
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
0674 OFF077(2)
INTERRUPT REGISTER MAP (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 136
TABLE 7-3:
06B4 OFF093(2)
06B8
OFF094(2,4)
06BC OFF095
(2,4)
(2,4)
06CC OFF099(2,4)
(2,4)
06DC OFF103
06E0 OFF104
06E4 OFF105
06E8 OFF106
DS60001320D-page 137
Legend:
Note
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
31:16
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
VOFF
VOFF
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
16/0
—
VOFF
—
17/1
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
VOFF
—
—
—
—
—
—
—
VOFF
—
All Resets
30/14
15:0
06D4 OFF101(2,4)
06D8 OFF102
31/15
15:0
06C8 OFF098(2,4)
06D0 OFF100
31:16
Bits
15:0
06C0 OFF096(2,4)
06C4 OFF097
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
06B0 OFF092(2)
INTERRUPT REGISTER MAP (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2015-2016 Microchip Technology Inc.
TABLE 7-3:
31:16
31:16
27/11
26/10
25/9
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
070C OFF115
—
—
—
—
—
—
0710 OFF116
0714 OFF117
—
—
—
—
—
—
0718 OFF118(2)
—
—
—
—
—
—
—
—
—
—
—
—
2015-2016 Microchip Technology Inc.
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
VOFF
VOFF
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
16/0
—
VOFF
—
17/1
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
VOFF
—
—
—
—
—
—
—
VOFF
—
All Resets
28/12
15:0
0708 OFF114
Note
29/13
15:0
0704 OFF113
Legend:
30/14
15:0
0700 OFF112
0728 OFF122
31/15
15:0
31:16
06FC OFF111
0724 OFF121
Bits
15:0
06F8 OFF110
0720 OFF120
31:16
31:16
06F4 OFF109
071C OFF119
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
06EC OFF107(7)
INTERRUPT REGISTER MAP (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 138
TABLE 7-3:
31:16
(2,4)
0748 OFF130
074C OFF131
0750 OFF132
0754 OFF133
0758 OFF134
075C OFF135
0760 OFF136
0764 OFF137
DS60001320D-page 139
Legend:
Note
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
VOFF
VOFF
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
16/0
—
VOFF
—
17/1
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
VOFF
—
—
—
—
—
—
—
VOFF
—
All Resets
30/14
15:0
073C OFF127(2,4,8)
0744 OFF129
31/15
15:0
OFF125(2,4)
0740 OFF128
Bits
15:0
0730 OFF124
0738 OFF126
Bit Range
Virtual Address
(BF81_#)
Register
Name(1)
31:16
072C OFF123
0734
INTERRUPT REGISTER MAP (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2015-2016 Microchip Technology Inc.
TABLE 7-3:
31:16
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
31:16
0774 OFF141
—
—
—
—
—
—
—
0778 OFF142
—
—
—
—
—
—
077C OFF143
0780 OFF144
—
—
—
—
—
—
0784 OFF145
0788 OFF146
—
—
—
—
—
—
078C OFF147
0790 OFF148(2)
2015-2016 Microchip Technology Inc.
0794 OFF149
(2)
—
—
—
—
—
—
0798 OFF150
(2)
—
—
—
—
—
—
079C OFF151(3)
(3)
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
VOFF
VOFF
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
16/0
—
VOFF
—
17/1
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
VOFF
—
—
—
—
—
—
—
VOFF
—
All Resets
31/15
15:0
0770 OFF140
Note
Bits
15:0
076C OFF139
Legend:
Bit Range
Virtual Address
(BF81_#)
Register
Name(1)
31:16
0768 OFF138
07A0 OFF152
INTERRUPT REGISTER MAP (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 140
TABLE 7-3:
07A8 OFF154
07AC OFF155
07B0 OFF156
07B4 OFF157
07B8 OFF158
07BC OFF159
07C0 OFF160
07C4 OFF161
07C8 OFF162
07CC OFF163
07D0 OFF164
07D4 OFF165
07D8 OFF166
07DC OFF167
DS60001320D-page 141
Legend:
Note
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
VOFF
VOFF
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
16/0
—
VOFF
—
17/1
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
VOFF
—
—
—
—
—
—
—
VOFF
—
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
07A4 OFF153
INTERRUPT REGISTER MAP (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2015-2016 Microchip Technology Inc.
TABLE 7-3:
31:16
31:16
31:16
31:16
31:16
26/10
25/9
—
—
—
—
—
—
—
31:16
07FC OFF175
—
—
—
—
—
—
—
0800 OFF176(2)
(2)
—
—
—
—
—
—
0808 OFF178(2)
—
—
—
—
—
—
—
—
—
—
—
—
2015-2016 Microchip Technology Inc.
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
VOFF
VOFF
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
16/0
—
VOFF
—
17/1
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
VOFF
—
—
—
—
—
—
—
VOFF
—
All Resets
27/11
15:0
07F8 OFF174
Note
28/12
15:0
07F4 OFF173
Legend:
29/13
15:0
07F0 OFF172
0818 OFF182
30/14
15:0
07EC OFF171
0814 OFF181
31/15
15:0
07E8 OFF170
0810 OFF180
Bits
15:0
07E4 OFF169
080C OFF179
Bit Range
Virtual Address
(BF81_#)
Register
Name(1)
31:16
07E0 OFF168
0804 OFF177
INTERRUPT REGISTER MAP (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 142
TABLE 7-3:
31:16
(2)
0838 OFF190
0840 OFF192
0844 OFF193
0848 OFF194
0850 OFF196
0858 OFF198
085C OFF199
0860 OFF200
DS60001320D-page 143
Legend:
Note
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
VOFF
VOFF
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
VOFF
—
16/0
—
VOFF
—
17/1
—
VOFF
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
—
VOFF
15:0
31:16
—
—
—
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
VOFF
—
—
—
—
—
—
—
VOFF
—
All Resets
30/14
15:0
082C OFF187(2)
0834 OFF189
31/15
15:0
OFF185(2)
0830 OFF188
Bits
15:0
0820 OFF184
0828 OFF186
Bit Range
Virtual Address
(BF81_#)
Register
Name(1)
31:16
081C OFF183
0824
INTERRUPT REGISTER MAP (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2015-2016 Microchip Technology Inc.
TABLE 7-3:
0868 OFF202
0874 OFF205
0878 OFF206
087C OFF207
0880 OFF208
0884 OFF209
0888 OFF210
0894 OFF213
Legend:
Note
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
VOFF
VOFF
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
VOFF
—
VOFF
—
VOFF
—
16/0
—
VOFF
—
17/1
—
VOFF
15:0
31:16
18/2
VOFF
15:0
31:16
19/3
—
—
15:0
31:16
20/4
VOFF
15:0
31:16
21/5
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
VOFF
—
—
—
—
—
—
—
VOFF
—
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
0864 OFF201
INTERRUPT REGISTER MAP (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2015-2016 Microchip Technology Inc.
2:
3:
4:
5:
6:
7:
8:
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV
Registers” for more information.
This bit or register is not available on 64-pin devices.
This bit or register is not available on devices without a CAN module.
This bit or register is not available on 100-pin devices.
Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
This bit or register is not available on devices without a Crypto module.
This bit or register is not available on 124-pin devices.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 144
TABLE 7-3:
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 7-1:
Bit
Range
31:24
23:16
15:8
7:0
INTCON: INTERRUPT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
U-0
NMIKEY
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
MVEC
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
TPC
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 NMIKEY: Non-Maskable Interrupt Key bits
When the correct key (0x4E) is written, a software NMI will be generated. The status is indicated by the
GNMI bit (RNMICON).
bit 23-13 Unimplemented: Read as ‘0’
bit 12
MVEC: Multi Vector Configuration bit
1 = Interrupt controller configured for multi vectored mode
0 = Interrupt controller configured for single vectored mode
bit 11
Unimplemented: Read as ‘0’
bit 10-8 TPC: Interrupt Proximity Timer Control bits
111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer
110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer
101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer
100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer
011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer
010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer
001 = Interrupts of group priority 1 start the Interrupt Proximity timer
000 = Disables Interrupt Proximity timer
bit 7-5
Unimplemented: Read as ‘0’
bit 4
INT4EP: External Interrupt 4 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 3
INT3EP: External Interrupt 3 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 2
INT2EP: External Interrupt 2 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 1
INT1EP: External Interrupt 1 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 0
INT0EP: External Interrupt 0 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
2015-2016 Microchip Technology Inc.
DS60001320D-page 145
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 7-2:
Bit
Range
PRISS: PRIORITY SHADOW SELECT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
31:24
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
PRI7SS(1)
R/W-0
23:16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRI1SS(1)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRI4SS(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRI2SS(1)
PRI3SS
7:0
Bit
25/17/9/1
PRI6SS(1)
PRI5SS(1)
15:8
Bit
26/18/10/2
R/W-0
U-0
U-0
U-0
R/W-0
—
—
—
SS0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 PRI7SS: Interrupt with Priority Level 7 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 7 uses Shadow Set 0)
0111 = Interrupt with a priority level of 7 uses Shadow Set 7
0110 = Interrupt with a priority level of 7 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 7 uses Shadow Set 1
0000 = Interrupt with a priority level of 7 uses Shadow Set 0
bit 27-24 PRI6SS: Interrupt with Priority Level 6 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 6 uses Shadow Set 0)
0111 = Interrupt with a priority level of 6 uses Shadow Set 7
0110 = Interrupt with a priority level of 6 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 6 uses Shadow Set 1
0000 = Interrupt with a priority level of 6 uses Shadow Set 0
bit 23-20 PRI5SS: Interrupt with Priority Level 5 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 5 uses Shadow Set 0)
0111 = Interrupt with a priority level of 5 uses Shadow Set 7
0110 = Interrupt with a priority level of 5 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 5 uses Shadow Set 1
0000 = Interrupt with a priority level of 5 uses Shadow Set 0
bit 19-16 PRI4SS: Interrupt with Priority Level 4 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 4 uses Shadow Set 0)
0111 = Interrupt with a priority level of 4 uses Shadow Set 7
0110 = Interrupt with a priority level of 4 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 4 uses Shadow Set 1
0000 = Interrupt with a priority level of 4 uses Shadow Set 0
Note 1:
These bits are ignored if the MVEC bit (INTCON) = 0.
DS60001320D-page 146
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 7-2:
PRISS: PRIORITY SHADOW SELECT REGISTER (CONTINUED)
bit 15-12 PRI3SS: Interrupt with Priority Level 3 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 3 uses Shadow Set 0)
0111 = Interrupt with a priority level of 3 uses Shadow Set 7
0110 = Interrupt with a priority level of 3 uses Shadow Set 6
•
•
•
bit 11-8
0001 = Interrupt with a priority level of 3 uses Shadow Set 1
0000 = Interrupt with a priority level of 3 uses Shadow Set 0
PRI2SS: Interrupt with Priority Level 2 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 2 uses Shadow Set 0)
0111 = Interrupt with a priority level of 2 uses Shadow Set 7
0110 = Interrupt with a priority level of 2 uses Shadow Set 6
•
•
•
bit 7-4
0001 = Interrupt with a priority level of 2 uses Shadow Set 1
0000 = Interrupt with a priority level of 2 uses Shadow Set 0
PRI1SS: Interrupt with Priority Level 1 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 1 uses Shadow Set 0)
0111 = Interrupt with a priority level of 1 uses Shadow Set 7
0110 = Interrupt with a priority level of 1 uses Shadow Set 6
•
•
•
bit 3-1
bit 0
0001 = Interrupt with a priority level of 1 uses Shadow Set 1
0000 = Interrupt with a priority level of 1 uses Shadow Set 0
Unimplemented: Read as ‘0’
SS0: Single Vector Shadow Register Set bit
1 = Single vector is presented with a shadow set
0 = Single vector is not presented with a shadow set
Note 1:
These bits are ignored if the MVEC bit (INTCON) = 0.
2015-2016 Microchip Technology Inc.
DS60001320D-page 147
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 7-3:
Bit
Range
31:24
23:16
15:8
7:0
INTSTAT: INTERRUPT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
—
—
—
—
—
R-0
R-0
R-0
R-0
SRIPL(1)
R-0
R-0
R-0
R-0
SIRQ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10-8
bit 7-6
SRIPL: Requested Priority Level bits for Single Vector Mode bits(1)
111-000 = The priority level of the latest interrupt presented to the CPU
Unimplemented: Read as ‘0’
bit 7-0
SIRQ: Last Interrupt Request Serviced Status bits
11111111-00000000 = The last interrupt request number serviced by the CPU
Note 1:
This value should only be used when the interrupt controller is configured for Single Vector mode.
REGISTER 7-4:
Bit
Range
31:24
23:16
15:8
7:0
IPTMR: INTERRUPT PROXIMITY TIMER REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
IPTMR: Interrupt Proximity Timer Reload bits
Used by the Interrupt Proximity Timer as a reload value when the Interrupt Proximity timer is triggered by
an interrupt event.
DS60001320D-page 148
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 7-5:
Bit
Range
31:24
23:16
15:8
7:0
IFSx: INTERRUPT FLAG STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS31
IFS30
IFS29
R/W-0
R/W-0
R/W-0
IFS28
IFS27
IFS26
IFS25
IFS24
R/W-0
R/W-0
R/W-0
R/W-0
IFS23
IFS22
IFS21
R/W-0
IFS20
IFS19
IFS18
IFS17
IFS16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS15
IFS14
IFS13
IFS12
IFS11
IFS10
IFS9
IFS8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS7
IFS6
IFS5
IFS4
IFS3
IFS2
IFS1
IFS0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
IFS31-IFS0: Interrupt Flag Status bits
1 = Interrupt request has occurred
0 = No interrupt request has occurred
This register represents a generic definition of the IFSx register. Refer to Table 7-2 for the exact bit
definitions.
REGISTER 7-6:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
Bit
31/23/15/7
IECx: INTERRUPT ENABLE CONTROL REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC31
IEC30
IEC29
IEC28
IEC27
IEC26
IEC25
IEC24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC23
IEC22
IEC21
IEC20
IEC19
IEC18
IEC17
IEC16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC15
IEC14
IEC13
IEC12
IEC11
IEC10
IEC9
IEC8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC7
IEC6
IEC5
IEC4
IEC3
IEC2
IEC1
IEC0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
Bit
24/16/8/0
x = Bit is unknown
IEC31-IEC0: Interrupt Enable bits
1 = Interrupt is enabled
0 = Interrupt is disabled
This register represents a generic definition of the IECx register. Refer to Table 7-2 for the exact bit
definitions.
2015-2016 Microchip Technology Inc.
DS60001320D-page 149
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 7-7:
Bit
Range
IPCx: INTERRUPT PRIORITY CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
31:24
23:16
15:8
7:0
Legend:
R = Readable bit
-n = Value at POR
Bit
Bit
28/20/12/4 27/19/11/3
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
IP3
R/W-0
R/W-0
IS3
R/W-0
IP2
R/W-0
R/W-0
R/W-0
IP0
R/W-0
IS2
R/W-0
IP1
R/W-0
R/W-0
R/W-0
R/W-0
IS1
R/W-0
R/W-0
R/W-0
IS0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-26 IP3: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 25-24 IS3: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
bit 23-21 Unimplemented: Read as ‘0’
bit 20-18 IP2: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 17-16 IS2: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
bit 15-13 Unimplemented: Read as ‘0’
Note:
This register represents a generic definition of the IPCx register. Refer to Table 7-2 for the exact bit
definitions.
DS60001320D-page 150
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 7-7:
IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED)
bit 12-10 IP1: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
bit 9-8
bit 7-5
bit 4-2
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
IS1: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
Unimplemented: Read as ‘0’
IP0: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
bit 1-0
Note:
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
IS0: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
This register represents a generic definition of the IPCx register. Refer to Table 7-2 for the exact bit
definitions.
2015-2016 Microchip Technology Inc.
DS60001320D-page 151
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 7-8:
Bit
Range
31:24
23:16
15:8
7:0
OFFx: INTERRUPT VECTOR ADDRESS OFFSET REGISTER (x = 0-190)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VOFF
R/W-0
R/W-0
R/W-0
U-0
VOFF
R/W-0
Legend:
R = Readable bit
-n = Value at POR
R/W-0
R/W-0
R/W-0
R/W-0
VOFF
W = Writable bit
‘1’ = Bit is set
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 17-1 VOFF: Interrupt Vector ‘x’ Address Offset bits
bit 0
Unimplemented: Read as ‘0’
DS60001320D-page 152
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
8.0
Note:
OSCILLATOR
CONFIGURATION
This data sheet summarizes the
features of the PIC32MZ EF family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 42. “Oscillators
with Enhanced PLL” (DS60001250) in
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
The PIC32MZ EF oscillator system has the following
modules and features:
• A total of five external and internal oscillator options
as clock sources
• On-Chip PLL with user-selectable input divider,
multiplier and output divider to boost operating
frequency on select internal and external oscillator
sources
• On-Chip user-selectable divisor postscaler on select
oscillator sources
• Software-controllable switching between
various clock sources
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and permits safe application recovery
or shutdown with dedicated Back-up FRC (BFRC)
• Dedicated On-Chip PLL for USB peripheral
• Flexible reference clock output
• Multiple clock branches for peripherals for better
performance flexibility
• Clock switch/slew control with output divider
A block diagram of the oscillator system is shown in
Figure 8-1. The clock distribution is provided in
Table 8-1.
Note:
2015-2016 Microchip Technology Inc.
Devices that support 252 MHz operation should
be configured for SYSCLK Host), this field is filled by the Hardware to indicate whether the
packet goes across multiple buffer descriptors. In case of transmit packets (from Host -> H/W), this field
indicates whether this BD is the last in the frame.
bit 31
bit 17
bit 16
bit 15-0
PKT_INT_EN: Packet Interrupt Enable
Generate an interrupt after processing the current buffer descriptor, if it is the end of the packet.
CBD_INT_EN: CBD Interrupt Enable
Generate an interrupt after processing the current buffer descriptor.
BD_BUFLEN: Buffer Descriptor Length
This field contains the length of the buffer and is updated with the actual length filled by the receiver.
FIGURE 26-3:
Bit
Range
FORMAT OF BD_SADDR
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
31-24
BD_SAADDR
23-16
BD_SAADDR
15-8
BD_SAADDR
7-0
BD_SAADDR
bit 31-0
Bit
25/17/9/1
Bit
24/16/8/0
BD_SAADDR: Security Association IP Session Address
The sessions’ SA pointer has the keys and IV values.
2015-2016 Microchip Technology Inc.
DS60001320D-page 413
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
FIGURE 26-4:
Bit
Range
FORMAT OF BD_SRCADDR
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31-24
BD_SCRADDR
23-16
BD_SCRADDR
15-8
BD_SCRADDR
7-0
BD_SCRADDR
bit 31-0
BD_SCRADDR: Buffer Source Address
The source address of the buffer that needs to be passed through the PE-CRDMA for encryption or
authentication. This address must be on a 32-bit boundary.
FIGURE 26-5:
Bit
Range
FORMAT OF BD_DSTADDR
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31-24
BD_DSTADDR
23-16
BD_DSTADDR
15-8
BD_DSTADDR
7-0
BD_DSTADDR
bit 31-0
BD_DSTADDR: Buffer Destination Address
The destination address of the buffer that needs to be passed through the PE-CRDMA for encryption
or authentication. This address must be on a 32-bit boundary.
FIGURE 26-6:
Bit
Range
FORMAT OF BD_NXTADDR
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
31-24
BD_NXTADDR
23-16
BD_NXTADDR
15-8
BD_NXTADDR
7-0
BD_NXTADDR
bit 31-0
Bit
25/17/9/1
Bit
24/16/8/0
BD_NXTADDR: Next BD Pointer Address Has Next Buffer Descriptor
The next buffer can be a next segment of the previous buffer or a new packet.
DS60001320D-page 414
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
FIGURE 26-7:
Bit
Range
FORMAT OF BD_UPDPTR
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31-24
BD_UPDADDR
23-16
BD_UPDADDR
15-8
BD_UPDADDR
7-0
BD_UPDADDR
bit 31-0
BD_UPDADDR: UPD Address Location
The update address has the location where the CRDMA results are posted. The updated results are
the ICV values, key output values as needed.
FIGURE 26-8:
Bit
Range
FORMAT OF BD_MSG_LEN
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
31-24
MSG_LENGTH
23-16
MSG_LENGTH
15-8
MSG_LENGTH
7-0
MSG_LENGTH
bit 31-0
Bit
24/16/8/0
MSG_LENGTH: Total Message Length
Total message length for the hash and HMAC algorithms in bytes. Total number of crypto bytes in
case of GCM algorithm (LEN-C).
FIGURE 26-9:
Bit
Range
Bit
25/17/9/1
FORMAT OF BD_ENC_OFF
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31-24
ENCR_OFFSET
23-16
ENCR_OFFSET
15-8
ENCR_OFFSET
7-0
ENCR_OFFSET
bit 31-0
ENCR_OFFSET: Encryption Offset
Encryption offset for the multi-task test cases (both encryption and authentication). The number of
AAD bytes in the case of GCM algorithm (LEN-A).
2015-2016 Microchip Technology Inc.
DS60001320D-page 415
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
26.3
Security Association Structure
Table 26-4 shows the Security Association Structure.
The Crypto Engine uses the Security Association to
determine the settings for processing a Buffer Descriptor Processor. The Security Association contains:
• Which algorithm to use
• Whether to use engines in parallel (for both
authentication and encryption/decryption)
• The size of the key
• Authentication key
• Encryption/decryption key
• Authentication Initialization Vector (IV)
• Encryption IV
TABLE 26-4:
CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE
Bit
31/23/15/7
Name
SA_CTRL
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
31:24
—
—
VERIFY
—
NO_RX
OR_EN
ICVONLY
IRFLAG
23:16
LNC
LOADIV
FB
FLAGS
—
—
—
ALGO
ENCTYPE
KEYSIZE
15:8
7:0
ALGO
KEYSIZE
MULTITASK
CRYPTOALGO
SA_AUTHKEY1 31:24
23:16
AUTHKEY
AUTHKEY
15:8
7:0
AUTHKEY
AUTHKEY
SA_AUTHKEY2 31:24
23:16
AUTHKEY
AUTHKEY
15:8
AUTHKEY
7:0
AUTHKEY
SA_AUTHKEY3 31:24
23:16
AUTHKEY
AUTHKEY
15:8
AUTHKEY
7:0
AUTHKEY
SA_AUTHKEY4 31:24
23:16
AUTHKEY
AUTHKEY
15:8
7:0
AUTHKEY
AUTHKEY
SA_AUTHKEY5 31:24
23:16
AUTHKEY
AUTHKEY
15:8
7:0
AUTHKEY
AUTHKEY
SA_AUTHKEY6 31:24
23:16
AUTHKEY
AUTHKEY
15:8
7:0
AUTHKEY
AUTHKEY
SA_AUTHKEY7 31:24
23:16
AUTHKEY
AUTHKEY
15:8
7:0
AUTHKEY
AUTHKEY
SA_AUTHKEY8 31:24
23:16
AUTHKEY
AUTHKEY
15:8
7:0
AUTHKEY
AUTHKEY
31:24
23:16
ENCKEY
ENCKEY
15:8
7:0
ENCKEY
ENCKEY
31:24
23:16
ENCKEY
ENCKEY
SA_ENCKEY1
SA_ENCKEY2
Bit
24/16/8/0
DS60001320D-page 416
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 26-4:
CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE (CONTINUED)
Bit
31/23/15/7
Name
Bit
30/22/14/6
15:8
SA_ENCKEY3
SA_ENCKEY4
SA_ENCKEY5
SA_ENCKEY6
SA_ENCKEY7
SA_ENCKEY8
SA_AUTHIV1
SA_AUTHIV2
SA_AUTHIV3
SA_AUTHIV4
SA_AUTHIV5
SA_AUTHIV6
SA_AUTHIV7
SA_AUTHIV8
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
25/17/9/1
Bit
24/16/8/0
ENCKEY
7:0
ENCKEY
31:24
23:16
ENCKEY
ENCKEY
15:8
ENCKEY
7:0
ENCKEY
31:24
ENCKEY
23:16
ENCKEY
15:8
ENCKEY
7:0
ENCKEY
31:24
ENCKEY
23:16
ENCKEY
15:8
7:0
ENCKEY
ENCKEY
31:24
ENCKEY
23:16
ENCKEY
15:8
7:0
ENCKEY
ENCKEY
31:24
ENCKEY
23:16
ENCKEY
15:8
7:0
ENCKEY
ENCKEY
31:24
23:16
ENCKEY
ENCKEY
15:8
ENCKEY
7:0
ENCKEY
31:24
23:16
AUTHIV
AUTHIV
15:8
7:0
AUTHIV
AUTHIV
31:24
23:16
AUTHIV
AUTHIV
15:8
7:0
AUTHIV
AUTHIV
31:24
23:16
AUTHIV
AUTHIV
15:8
7:0
AUTHIV
AUTHIV
31:24
23:16
AUTHIV
AUTHIV
15:8
7:0
AUTHIV
AUTHIV
31:24
23:16
AUTHIV
AUTHIV
15:8
7:0
AUTHIV
AUTHIV
31:24
23:16
AUTHIV
AUTHIV
15:8
7:0
AUTHIV
AUTHIV
31:24
23:16
AUTHIV
AUTHIV
15:8
7:0
AUTHIV
AUTHIV
31:24
23:16
AUTHIV
AUTHIV
15:8
7:0
AUTHIV
AUTHIV
2015-2016 Microchip Technology Inc.
Bit
26/18/10/2
DS60001320D-page 417
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE 26-4:
CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE (CONTINUED)
Bit
31/23/15/7
Name
SA_ENCIV1
SA_ENCIV2
SA_ENCIV3
SA_ENCIV4
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
31:24
ENCIV
23:16
ENCIV
15:8
7:0
ENCIV
ENCIV
31:24
ENCIV
23:16
ENCIV
15:8
ENCIV
7:0
ENCIV
31:24
ENCIV
23:16
ENCIV
15:8
ENCIV
7:0
ENCIV
31:24
23:16
ENCIV
ENCIV
15:8
ENCIV
7:0
ENCIV
DS60001320D-page 418
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
Figure 26-10 shows the Security Association control
word structure.
The Crypto Engine fetches different structures for different flows and ensures that hardware fetches minimum words from SA required for processing. The
structure is ready for hardware optimal data fetches.
FIGURE 26-10:
Bit
Range
FORMAT OF SA_CTRL
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31-24
—
—
VERIFY
—
NO_RX
OR_EN
ICVONLY
IRFLAG
23-16
LNC
LOADIV
FB
FLAGS
—
—
—
ALGO
ENC
KEY
SIZE
15-8
7-0
ALGO
KEY
SIZE
MULTITASK
CRYPTOALGO
bit 31-30 Reserved: Do not use
bit 29
VERIFY: NIST Procedure Verification Setting
1 = NIST procedures are to be used
0 = Do not use NIST procedures
bit 28
Reserved: Do not use
bit 27
NO_RX: Receive DMA Control Setting
1 = Only calculate ICV for authentication calculations
0 = Normal processing
bit 26
OR_EN: OR Register Bits Enable Setting
1 = OR the register bits with the internal value of the CSR register
0 = Normal processing
bit 25
ICVONLY: Incomplete Check Value Only Flag
This affects the SHA-1 algorithm only. It has no effect on the AES algorithm.
1 = Only three words of the HMAC result are available
0 = All results from the HMAC result are available
bit 24
IRFLAG: Immediate Result of Hash Setting
This bit is set when the immediate result for hashing is requested.
1 = Save the immediate result for hashing
0 = Do not save the immediate result
bit 23
LNC: Load New Keys Setting
1 = Load a new set of keys for encryption and authentication
0 = Do not load new keys
bit 22
LOADIV: Load IV Setting
1 = Load the IV from this Security Association
0 = Use the next IV
bit 21
FB: First Block Setting
This bit indicates that this is the first block of data to feed the IV value.
1 = Indicates this is the first block of data
0 = Indicates this is not the first block of data
bit 20
FLAGS: Incoming/Outgoing Flow Setting
1 = Security Association is associated with an outgoing flow
0 = Security Association is associated with an incoming flow
bit 19-17 Reserved: Do not use
2015-2016 Microchip Technology Inc.
DS60001320D-page 419
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
Figure 26-10: Format of SA_CTRL (Continued)
bit 16-10 ALGO: Type of Algorithm to Use
1xxxxxx = HMAC 1
x1xxxxx = SHA-256
xx1xxxx = SHA1
xxx1xxx = MD5
xxxx1xx = AES
xxxxx1x = TDES
xxxxxx1 = DES
bit 9
ENC: Type of Encryption Setting
1 = Encryption
0 = Decryption
bit 8-7
KEYSIZE: Size of Keys in SA_AUTHKEYx or SA_ENCKEYx
11 = Reserved; do not use
10 = 256 bits
01 = 192 bits
00 = 128 bits(1)
bit 6-4
MULTITASK: How to Combine Parallel Operations in the Crypto Engine
111 = Parallel pass (decrypt and authenticate incoming data in parallel)
101 = Pipe pass (encrypt the incoming data, and then perform authentication on the encrypted data)
011 = Reserved
010 = Reserved
001 = Reserved
000 = Encryption or authentication or decryption (no pass)
bit 3-0
CRYPTOALGO: Mode of operation for the Crypto Algorithm
1111 = Reserved
1110 = AES_GCM
(for AES processing)
1101 = RCTR
(for AES processing)
1100 = RCBC_MAC (for AES processing)
1011 = ROFB
(for AES processing)
1010 = RCFB
(for AES processing)
1001 = RCBC
(for AES processing)
1000 = RECB
(for AES processing)
0111 = TOFB
(for Triple-DES processing)
0110 = TCFB
(for Triple-DES processing)
0101 = TCBC
(for Triple-DES processing)
0100 = TECB
(for Triple-DES processing)
0011 = OFB
(for DES processing)
0010 = CFB
(for DES processing)
0001 = CBC
(for DES processing)
0000 = ECB
(for DES processing)
Note 1:
This setting does not alter the size of SA_AUTHKEYx or SA_ENCKEYx in the Security Association,
only the number of bits of SA_AUTHKEYx and SA_ENCKEYx that are used.
DS60001320D-page 420
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
27.0
Note:
RANDOM NUMBER
GENERATOR (RNG)
This data sheet summarizes the features
of the PIC32MZ EF family of devices. It is
not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 49.
“Crypto Engine (CE) and Random
Number
Generator
(RNG)”
(DS60001246) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
TABLE 27-1:
RANDOM NUMBER
GENERATOR BLOCK
DIAGRAM
System Bus
PRNG
SFR
PBCLK5
The Random Number Generator (RNG) core implements a thermal noise-based, True Random Number
Generator (TRNG) and a cryptographically secure
Pseudo-Random Number Generator (PRNG).
The TRNG uses multiple ring oscillators and the inherent thermal noise of integrated circuits to generate true
random numbers that can initialize the PRNG.
TRNG
BIAS Corrector
The PRNG is a flexible LSFR, which is capable of
manifesting a maximal length LFSR of up to 64-bits.
The following are some of the key features of the
Random Number Generator:
• TRNG:
- Up to 25 Mbps of random bits
- Multi-Ring Oscillator based design
- Built-in Bias Corrector
• PRNG:
- LSFR-based
- Up to 64-bit polynomial length
- Programmable polynomial
- TRNG can be seed value
2015-2016 Microchip Technology Inc.
Edge Comparator
Ring
Oscillator
Ring
Oscillator
DS60001320D-page 421
RNG Control Registers
Virtual Address
(BF8E_#)
Register
Name
TABLE 27-2:
6000
RNGVER
6004
6008
600C
RANDOM NUMBER GENERATOR (RNG) REGISTER MAP
RNGCON
RNGPOLY1
RNGPOLY2
6010 RNGNUMGEN1
6014 RNGNUMGEN2
6018
601C
6020
Legend:
RNGSEED1
RNGSEED2
RNGCNT
31/15
30/14
29/13
28/12
27/11
26/10
25/9
31:16
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
ID
15:0
xxxx
VERSION
REVISION
31:16
—
—
—
—
—
—
15:0
—
—
—
LOAD
TRNGMODE
CONT
—
—
—
—
—
PRNGEN TRNGEN
31:16
—
—
xxxx
—
—
—
PLEN
31:16
FFFF
0000
FFFF
POLY
15:0
31:16
0000
FFFF
RNG
15:0
31:16
FFFF
FFFF
RNG
15:0
31:16
FFFF
0000
SEED
15:0
31:16
0000
0000
SEED
15:0
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
0064
POLY
15:0
All Resets
Bit Range
Bits
0000
—
—
—
—
RCNT
—
—
—
0000
0000
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 422
27.1
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 27-1:
Bit
Range
31:24
23:16
15:8
7:0
RNGVER: RANDOM NUMBER GENERATOR VERSION REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
ID
ID
R-0
R-0
R-0
R-0
R-0
R-0
R-0
VERSION
R-0
R-0
REVISION
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 ID: Block Identification bits
bit 15-8
VERSION: Block Version bits
bit 7-0
REVISION: Block Revision bits
2015-2016 Microchip Technology Inc.
DS60001320D-page 423
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 27-2:
Bit
Range
31:24
23:16
15:8
7:0
RNGCON: RANDOM NUMBER GENERATOR CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
LOAD
TRNGMODE
CONT
PRNGEN
TRNGEN
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
PLEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12
LOAD: Device Select bit
This bit is self-clearing and is used to load the seed from the TRNG (i.e., the random value) as a seed to
the PRNG.
bit 11
TRNGMODE: TRNG Mode Selection bit
1 = Use ring oscillators with bias corrector
0 = Use ring oscillators with XOR tree
bit 10
CONT: PRNG Number Shift Enable bit
1 = The PRNG random number is shifted every cycle
0 = The PRNG random number is shifted when the previous value is removed
bit 9
PRNGEN: PRNG Operation Enable bit
1 = PRNG operation is enabled
0 = PRNG operation is not enabled
bit 8
TRNGEN: TRNG Operation Enable bit
1 = TRNG operation is enabled
0 = TRNG operation is not enabled
bit 7-0
PLEN: PRNG Polynomial Length bits
These bits contain the length of the polynomial used for the PRNG.
Note:
DS60001320D-page 424
Enabling this bit will generate numbers with a more even distribution of randomness.
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 27-3:
Bit
Range
31:24
23:16
15:8
7:0
RNGPOLYx: RANDOM NUMBER GENERATOR POLYNOMIAL REGISTER ‘x’
(‘x’ = 1 OR 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POLY
R/W-1
POLY
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POLY
R/W-0
POLY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
POLY: PRNG LFSR Polynomial MSb/LSb bits (RNGPOLY1 = LSb, RNGPOLY2 = MSb)
REGISTER 27-4:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
RNGNUMGENx: RANDOM NUMBER GENERATOR REGISTER ‘x’ (‘x’ = 1 OR 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RNG
R/W-1
RNG
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RNG
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RNG
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
RNG: Current PRNG MSb/LSb Value bits (RNGNUMGEN1 = LSb, RNGNUMGEN2 = MSb)
2015-2016 Microchip Technology Inc.
DS60001320D-page 425
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
REGISTER 27-5:
Bit
Range
31:24
23:16
15:8
7:0
RNGSEEDx: TRUE RANDOM NUMBER GENERATOR SEED REGISTER ‘x’
(‘x’ = 1 OR 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
SEED
R-0
R-0
SEED
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
SEED
R-0
SEED
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
SEED: TRNG MSb/LSb Value bits (RNGSEED1 = LSb, RNGSEED2 = MSb)
REGISTER 27-6:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
RNGCNT: TRUE RANDOM NUMBER GENERATOR COUNT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
RCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-7
Unimplemented: Read as ‘0’
bit 6-0
RCNT: Number of Valid TRNG MSB 32 bits
DS60001320D-page 426
x = Bit is unknown
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
28.0
Note:
12-BIT HIGH-SPEED
SUCCESSIVE APPROXIMATION
REGISTER (SAR) ANALOG-TODIGITAL CONVERTER (ADC)
This data sheet summarizes the features
of the PIC32MZ EF family of devices. It is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section
22.
“12-bit
High-Speed
Successive Approximation Register
(SAR) Analog-to-Digital Converter
(ADC)” (DS60001344) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
The 12-bit High-Speed Successive Approximation
Register (SAR) Analog-to-Digital Converter (ADC)
includes the following key features:
• 12-bit resolution
• Six ADC modules with dedicated Sample and
Hold (S&H) circuits
• Two dedicated ADC modules can be combined in
Turbo mode to provide double conversion rate
(clock sources for combined ADC modules must
be synchronous)
• Single-ended and/or differential inputs
• Can operate during Sleep mode
• Supports touch sense applications
• Six digital comparators
• Six digital filters supporting two modes:
- Oversampling mode
- Averaging mode
• Early interrupt generation resulting in faster
processing of converted data
• Designed for motor control, power conversion,
and general purpose applications
A simplified block diagram of the ADC module is
illustrated in Figure 28-1.
The 12-bit HS SAR ADC has up to five dedicated
ADC modules (ADC0-ADC4) and one shared ADC
module (ADC7). The dedicated ADC modules use a
single input (or its alternate) and are intended for
high-speed and precise sampling of time-sensitive or
transient inputs. The the shared ADC module
incorporates a multiplexer on the input to facilitate a
larger group of inputs, with slower sampling, and
provides flexible automated scanning option through
the input scan logic.
For each ADC module, the analog inputs are
connected to the S&H capacitor. The clock, sampling
time, and output data resolution for each ADC
module can be set independently. The ADC module
performs the conversion of the input analog signal
based on the configurations set in the registers.
When conversion is complete, the final result is
stored in the result buffer for the specific analog
input and is passed to the digital filter and digital
comparator if configured to use data from this
particular sample. Input to ADCx mapping is
illustrated in Figure 28-2.
The
throughput
rate
(see
Table 37-39
in
37.0 “Electrical Characteristics”) is calculated, as
shown in Equation 28-1.
EQUATION 28-1:
ADC THROUGHPUT RATE
T AD
FTP = ------------------------------------------- T SAMP + T CONV
Where,
TAD = the frequency of the individual ADC module
Note 1: Prior to enabling the ADC module, the
user application must copy the ADC calibration data (DEVADC0-DEVADC4,
DEVADC7; see Register 34-13) from the
Configuration memory into the ADC Configuration
registers
(ADC0CFGADC4CFG, ADC7CFG).
2: Configure the AICPMPEN (ADCCON1) and IOANCPEN (CFGCON) bits to ‘0’ if VDD >= 2.5V. Set
the AICPMPEN and IOANCPEN bits to
‘1’ if VDD < 2.5V.
2015-2016 Microchip Technology Inc.
DS60001320D-page 427
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
FIGURE 28-1:
AN0
AN45
N/C
N/C
ADC BLOCK DIAGRAM
00
01
10
11
AVDD
VREF+
VREFADCSEL
00
10
11
CONCLKDIV
VREFSEL
0
1
VREFH
DIFF0
(ADCIMCON1)
VREFL
TAD0-TAD4
ADCDIV
(ADCxTIME)
TQ
ADC0
TAD7
AN4
AN49
N/C
N/C
01
TCLK
SH0ALT
(ADCTRGMODE)
AN5
VREFL
AVSS
ADCDIV
(ADCCON2)
00
01
10
11
SH4ALT
(ADCTRGMODE)
AN9
VREFL
0
1
ADC4
DIFF4
(ADCIMCON1)
AN5
AN41
IVREF (AN43)
AN42
IVTEMP (AN44)
ADC7
AN10
VREFL
0
1
CVD
Capacitor
DIFFx
x = 5 to 44
(ADCIMCONy)
y = 1 to 3,
z = 1 to 31 (Odd numbers)
ADCDATA0
…...
FIFO
Digital Filter
Digital Comparator
Data
Interrupt/Event
Triggers,
Turbo Channel,
Scan Control Logic
Trigger
Capacitive Voltage
Divider (CVD)
Status and Control
Registers
DS60001320D-page 428
SYSTEMBUS
ADCDATA44
Interrupt/Event
Interrupt
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
FIGURE 28-2:
S&H BLOCK DIAGRAM
ADC3
ADC0
AN0
00
AN3
00
AN45
01
AN48
01
N/C
10
N/C
10
N/C
11
N/C
11
SAR
SAR
SH3ALT
(ADCTRGMODE
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2015-2016 Microchip Technology Inc.
DS60001320D-page 685
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS60001320D-page 686
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
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2015-2016 Microchip Technology Inc.
DS60001320D-page 687
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS60001320D-page 688
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
2015-2016 Microchip Technology Inc.
DS60001320D-page 689
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320D-page 690
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
124-Very Thin Leadless Array Package (TL) – 9x9x0.9 mm Body [VTLA]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E/2
G4
X1
X2
G3
E
T2 C2
G1
G5
X4
G2
SILK SCREEN
W3
W2
C1
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Pad Clearance
G1
Pad Clearance
G2
Pad Clearance
G3
Pad Clearance
G4
Contact to Center Pad Clearance (X4)
G5
Optional Center Pad Width
T2
Optional Center Pad Length
W2
W3
Optional Center Pad Chamfer (X4)
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X124)
X1
Contact Pad Length (X124)
X2
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
0.20
0.20
0.20
0.20
0.30
6.60
6.60
0.10
8.50
8.50
0.30
0.30
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2193A
2015-2016 Microchip Technology Inc.
DS60001320D-page 691
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS60001320D-page 692
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2015-2016 Microchip Technology Inc.
DS60001320D-page 693
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS60001320D-page 694
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
144-Lead Plastic Low Profile Quad Flatpack (PL) – 20x20x1.40 mm Body, with 2.00 mm
Footprint [LQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2015-2016 Microchip Technology Inc.
DS60001320D-page 695
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
144-Lead Plastic Low Profile Quad Flatpack (PL) – 20x20x1.40 mm Body, with 2.00 mm
Footprint [LQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS60001320D-page 696
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2015-2016 Microchip Technology Inc.
DS60001320D-page 697
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
NOTES:
DS60001320D-page 698
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
APPENDIX A:
MIGRATING FROM
PIC32MX5XX/6XX/7XX
TO PIC32MZ EF
This appendix provides an overview of considerations
for migrating from PIC32MX5XX/6XX/7XX devices to
the PIC32MZ EF family of devices. The code developed for PIC32MX5XX/6XX/7XX devices can be
ported to PIC32MZ EF devices after making the
appropriate changes outlined in the following sections.
A.1
Oscillator and PLL Configuration
Because the maximum speed of the PIC32MZ EF
family is greater, the configuration of the oscillator is
different from prior PIC32MX5XX/6XX/7XX devices.
Table A-1 summarizes the differences (indicated by
Bold type) between the family devices for the oscillator.
The PIC32MZ EF devices are based on a new
architecture, and feature many improvements and new
capabilities over PIC32MX5XX/6XX/7XX devices.
TABLE A-1:
OSCILLATOR CONFIGURATION DIFFERENCES
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
Primary Oscillator Configuration
On PIC32MX devices, XT mode had to be selected if the input fre- On PIC32MZ EF devices, HS mode has a wider input frequency
quency was in the 3 MHz to 10 MHz range (4-10 for PLL), and HS range (4 MHz to 12 MHz). The bit setting of ‘01’ is Reserved.
mode had to be selected if the input frequency was in the 10 MHz
to 20 MHz range.
POSCMOD (DEVCFG1)
11 = Primary Oscillator disabled
10 = HS Oscillator mode selected
01 = XT Oscillator mode selected
00 = External Clock mode selected
POSCMOD (DEVCFG1)
11 = Primary Oscillator disabled
10 = HS Oscillator mode selected
01 = Reserved
00 = External Clock mode selected
On PIC32MX devices, crystal mode could be selected with the
HS or XT POSC setting, but an external oscillator could be fed
into the OSC1/CLKI pin and the part would operate normally.
On PIC32MZ devices, this option is not available. External oscillator signals should only be fed into the OSC1/CLKI pin with the
POSC set to EC mode.
Oscillator Selection
On PIC32MX devices, clock selection choices are as follows:
On PIC32MZ EF devices, clock selection choices are as follows:
FNOSC (DEVCFG1)
NOSC (OSCCON)
111 = FRCDIV
110 = FRCDIV16
101 = LPRC
100 = SOSC
011 = POSC with PLL module
010 = POSC (XT, HS, EC)
001 = FRCDIV+PLL
000 = FRC
FNOSC (DEVCFG1)
NOSC (OSCCON)
111 = FRCDIV
110 = Reserved
101 = LPRC
100 = SOSC
011 = Reserved
010 = POSC (HS or EC)
001 = System PLL (SPLL)
000 = FRCDIV
COSC (OSCCON)
111 = FRC divided by FRCDIV
110 = FRC divided by 16
101 = LPRC
100 = SOSC
011 = POSC + PLL module
010 = POSC
001 = FRCPLL
000 = FRC
COSC (OSCCON)
111 = FRC divided by FRCDIV
110 = BFRC
101 = LPRC
100 = SOSC
011 = Reserved
010 = POSC
001 = System PLL
000 = FRC divided by FRCDIV
2015-2016 Microchip Technology Inc.
DS60001320D-page 699
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE A-1:
OSCILLATOR CONFIGURATION DIFFERENCES (CONTINUED)
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
Secondary Oscillator Enable
The location of the SOSCEN bit in the Flash Configuration Words
has moved.
FSOSCEN (DEVCFG1)
FSOSCEN (DEVCFG1)
PLL Configuration
The FNOSC and NOSC bits select between POSC
and FRC.
Selection of which input clock (POSC or FRC) is now done
through the FPLLICLK/PLLICLK bits.
FNOSC (DEVCFG1)
NOSC (OSCCON)
FPLLICLK (DEVCFG2)
PLLICLK (SPLLCON)
On PIC32MX devices, the input frequency to the PLL had to be On PIC32MZ EF devices, the input range for the PLL is wider (5
between 4 MHz and 5 MHz. FPLLIDIV selected how to divide the MHz to 64 MHz). The input divider values have changed, and new
input frequency to give it the appropriate range.
FPLLRNG/PLLRNG bits have been added to indicate under what
range the input frequency falls.
FPLLIDIV (DEVCFG2)
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
FPLLIDIV (DEVCFG2)
PLLIDIV (SPLLCON)
111 = Divide by 8
110 = Divide by 7
101 = Divide by 6
100 = Divide by 5
011 = Divide by 4
010 = Divide by 3
001 = Divide by 2
000 = Divide by 1
FPLLRNG (DEVCFG2)
PLLRNG (SPLLCON)
111 = Reserved
110 = Reserved
101 = 34-64 MHz
100 = 21-42 MHz
011 = 13-26 MHz
010 = 8-16 MHz
001 = 5-10 MHz
000 = Bypass
On PIC32MX devices, the output frequency of PLL is between
60 MHz and 120 MHz. The PLL multiplier and divider bits
configure the PLL for this range.
The PLL multiplier and divider on PIC32MZ EF devices have a
wider range to accommodate the wider PLL specification range.
FPLLMUL (DEVCFG2)
PLLMULT (OSCCON)
111 = 24x multiplier
110 = 21x multiplier
101 = 20x multiplier
100 = 19x multiplier
011 = 18x multiplier
010 = 17x multiplier
001 = 16x multiplier
000 = 15x multiplier
FPLLMULT (DEVCFG2)
PLLMULT (SPLLCON)
1111111 = Multiply by 128
1111110 = Multiply by 127
1111101 = Multiply by 126
1111100 = Multiply by 125
•
•
•
0000000 = Multiply by 1
FPLLODIV (DEVCFG2)
PLLODIV (OSCCON)
111 = 24x multiplier
110 = 21x multiplier
101 = 20x multiplier
100 = 19x multiplier
011 = 18x multiplier
010 = 17x multiplier
001 = 16x multiplier
000 = 15x multiplier
FPLLODIV (DEVCFG2)
PLLODIV (SPLLCON)
111 = PLL Divide by 32
110 = PLL Divide by 32
101 = PLL Divide by 32
100 = PLL Divide by 16
011 = PLL Divide by 8
010 = PLL Divide by 4
001 = PLL Divide by 2
000 = PLL Divide by 2
DS60001320D-page 700
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE A-1:
OSCILLATOR CONFIGURATION DIFFERENCES (CONTINUED)
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
Crystal/Oscillator Selection for USB
Any frequency that can be divided down to 4 MHz using
UPLLIDIV, including 4, 8, 12, 16, 20, 40, and 48 MHz.
If the USB module is used, the Primary Oscillator is limited to
either 12 MHz or 24 MHz. Which frequency is used is selected
using the UPLLFSEL (DEVCFG2) bit.
USB PLL Configuration
On PIC32MX devices, the PLL for the USB requires an input fre- On PIC32MZ EF devices, the HS USB PHY requires an input
frequency of 12 MHz or 24 MHz. UPLLIDIV has been replaced
quency of 4 MHz.
with UPLLFSEL.
UPLLIDIV (DEVCFG2)
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
UPLLFSEL (DEVCFG2)
1 = UPLL input clock is 24 MHz
0 = UPLL input clock is 12 MHz
Peripheral Bus Clock Configuration
On PIC32MX devices, there is one peripheral bus, and the clock
for that bus is divided from the SYSCLK using FPBDIV/PBDIV. In
addition, the maximum PBCLK frequency is the same as
SYSCLK.
On PIC32MZ EF devices, there are eight peripheral buses with
their own clocks. FPBDIV is removed, and each PBDIV is in its
own register for each PBCLK. The initial PBCLK speed is fixed at
reset, and the maximum PBCLK speed is limited to100 MHz for
all buses, with the exception of PBCLK7, which is 200 MHz.
FPBDIV (DEVCFG1)
PBDIV (OSCCON)
11 = PBCLK is SYSCLK divided by 8
10 = PBCLK is SYSCLK divided by 4
01 = PBCLK is SYSCLK divided by 2
00 = PBCLK is SYSCLK divided by 1
PBDIV (PBxDIV)
1111111 = PBCLKx is SYSCLK divided by 128
1111110 = PBCLKx is SYSCLK divided by 127
•
•
•
0000011 = PBCLKx is SYSCLK divided by 4
0000010 = PBCLKx is SYSCLK divided by 3
0000001 = PBCLKx is SYSCLK divided by 2
(default value for x < 7)
0000000 = PBCLKx is SYSCLK divided by 1
(default value for x 7)
CPU Clock Configuration
On PIC32MX devices, the CPU clock is derived from SYSCLK.
On PIC32MZ EF devices, the CPU clock is derived from PBCLK7.
FRCDIV Default
On PIC32MX devices, the default value for FRCDIV was to divide On PIC32MZ EF devices, the default has been changed to divide
the FRC clock by two.
by one.
FRCDIV (OSCCON)
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2 (default)
000 = FRC divided by 1
2015-2016 Microchip Technology Inc.
FRCDIV (OSCCON)
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2
000 = FRC divided by 1 (default)
DS60001320D-page 701
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE A-1:
OSCILLATOR CONFIGURATION DIFFERENCES (CONTINUED)
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
Fail-Safe Clock Monitor (FSCM)
On PIC32MX devices, the internal FRC became the clock source On PIC32MZ EF devices, a separate internal Backup FRC
on a failure of the clock source.
(BFRC) becomes the clock source upon a failure at the clock
source.
On PIC32MX devices, a clock failure resulted in the triggering of On PIC32MZ EF devices, a NMI is triggered instead, and must be
a specific interrupt when the switchover was complete.
handled by the NMI routine.
FSCM generates an interrupt.
FSCM generates a NMI.
The definitions of the FCKSM bits has changed on
PIC32MZ EF devices.
FCKSM (DEVCFG1)
1x = Clock switching is disabled, FSCM is disabled
01 = Clock switching is enabled, FSCM is disabled
00 = Clock switching is enabled, FSCM is enabled
FCKSM (DEVCFG1)
11 = Clock switching is enabled and clock monitoring
is enabled
10 = Clock switching is disabled and clock monitoring
is enabled
01 = Clock switching is enabled and clock monitoring is disabled
00 = Clock switching is disabled and clock monitoring
is disabled
On PIC32MX devices, the CF (OSCCON) bit indicates a
clock failure. Writing to this bit initiates a FSCM event.
On PIC32MZ EF devices, the CF (OSCCON) bit has the
same functionality as that of PIC32MX device; however, an additional CF(RNMICON) bit is available to indicate a NMI event.
Writing to this bit causes a NMI event, but not a FSCM event.
On PIC32MX devices, the CLKLOCK (OSCCON) bit is
controlled by the FSCM.
On PIC32MZ EF devices, the CLKLOCK (OSCCON) bit is
not impacted by the FSCM.
CLKLOCK (OSCCON)
CLKLOCK (OSCCON)
If clock switching and monitoring is disabled (FCKSM = 1x): 1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified
If clock switching and monitoring is enabled (FCKSM = 0x):
Clock and PLL selections are never locked and may be modified.
Table A-2 illustrates the difference in code setup of the
respective parts for maximum speed using an external
24 MHz crystal.
TABLE A-2:
CODE DIFFERENCES FOR MAXIMUM SPEED USING AN EXTERNAL 24 MHz
CRYSTAL
PIC32MX5XX/6XX/7XX @ 80 Hz
PIC32MZ EF @ 200 MHz
#include
#include
#pragma config POSCMOD = HS
#pragma config FNOSC = PRIPLL
#pragma config FPLLMUL = MUL_20
#pragma config FPLLODIV = DIV_1
#pragma
#pragma
#pragma
#pragma
#pragma
#pragma
#pragma
#define SYSFREQ (80000000L)
#define SYSFREQ (200000000L)
#pragma config FPLLIDIV = DIV_6
DS60001320D-page 702
config
config
config
config
config
config
config
POSCMOD = HS
FNOSC = SPLL
FPLLICLK = PLL_POSC
FPLLIDIV = DIV_3
FPLLRNG = RANGE_5_10_MHZ
FPLLMULT = MUL_50
FPLLODIV = DIV_2
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
A.2
Analog-to-Digital Converter (ADC)
The PIC32MZ EF family of devices has a new 12-bit
High-Speed Successive Approximation Register (SAR)
ADC module that replaces the 10-bit ADC module in
PIC32MX5XX/6XX/7XX devices; therefore, the use of
Bold type to show differences is not used in the following table. Note that not all register differences are
described in this section; however, the key feature
differences are listed in Table A-3.
TABLE A-3:
ADC DIFFERENCES
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
Clock Selection and Operating Frequency (TAD)
On PIC32MX devices, the ADC clock was derived from either the On PIC32MZ EF devices, the three possible sources of the ADC
FRC or from the PBCLK.
clock are FRC, REFCLKO3, and SYSCLK.
ADRC (AD1CON3)
1 = FRC clock
0 = Clock derived from Peripheral Bus Clock (PBCLK)
ADCSEL (ADCCON3)
11 = FRC
10 = REFCLKO3
01 = SYSCLK
00 = Reserved
On PIC32MX devices, if the ADC clock was derived from the On PIC32MZ EF devices, any ADC clock source can be divided
PBCLK, that frequency was divided further down, with a maxi- down separately for each dedicated ADC and the shared ADC,
mum divisor of 512, and a minimum divisor of two.
with a maximum divisor of 254. The input clock can also be fed
directly to the ADC.
ADCS (AD1CON3)
11111111 = 512 * TPB = TAD
•
•
•
00000001 = 4 * TPB = TAD
00000000 = 2 * TPB = TAD
2015-2016 Microchip Technology Inc.
ADCDIV (ADCTIMEx)
ADCDIV (ADCCON2)
1111111 = 254 * TQ = TAD
•
•
•
0000011 = 6 * TQ = TAD
0000010 = 4 * TQ = TAD
0000001 = 2 * TQ = TAD
0000000 = TQ = TAD
DS60001320D-page 703
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE A-3:
ADC DIFFERENCES (CONTINUED)
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
Scan Trigger Source
On PIC32MX devices, there are four sources that can trigger a On PIC32MZ EF devices, the list of sources for triggering a scan
scan conversion in the ADC module: Auto, Timer3, INT0, and conversion has been expanded to include the comparators,
clearing the SAMP bit.
Output Compare, and two additional Timers. In addition, trigger
sources can be simulated by setting the RQCNVRT
(ADCCON3) bit.
SSRC (AD1CON1)
111 = Auto convert
110 = Reserved
101 = Reserved
100 = Reserved
011 = Reserved
010 = Timer3 period match
001 = Active transition on INT0 pin
000 = Clearing SAMP bit
STRGSRC (ADCCON1)
11111 = Reserved
•
•
•
01101 = Reserved
01100 = Comparator 2 COUT
01011 = Comparator 1 COUT
01010 = OCMP5
01001 = OCMP3
01000 = OCMP1
00111 = TMR5 match
00110 = TMR3 match
00101 = TMR1 match
00100 = INT0
00011 = Reserved
00010 = Global level software trigger (GLSWTRG)
00001 = Global software trigger (GSWTRG)
00000 = No trigger
Output Format
On PIC32MX devices, the output format was decided for all ADC On PIC32MZ EF devices, the FRACT bit determines whether
channels based on the setting of the FORM bits.
fractional or integer format is used. Then, each input can have its
own setting for input (differential or single-ended) and sign
(signed or unsigned) using the DIFFx and SIGNx bits in the
ADCIMODx registers.
FORM (AD1CON1)
011 = Signed Fractional 16-bit
010 = Fractional 16-bit
001 = Signed Integer 16-bit
000 = Integer 16-bit
111 = Signed Fractional 32-bit
110 = Fractional 32-bit
101 = Signed Integer 32-bit
100 = Integer 32-bit
FRACT (ADCCON1)
1 = Fractional
0 = Integer
DIFFx (ADCIMODy)
1 = Channel x is using Differential mode
0 = Channel x is using Single-ended mode
SIGNx (ADCMODy)
1 = Channel x is using Signed Data mode
0 = Channel x is using Unsigned Data mode
Interrupts
On PIC32MX devices, an interrupt is triggered from the ADC On PIC32MZ EF devices, the ADC module can trigger an intermodule when a certain number of conversions have taken place, rupt for each channel when it is converted. Use the Interrupt Controller bits, IEC1, IEC2, and IEC3, to enable/
irrespective of which channel was converted.
disable them.
In addition, the ADC support one global interrupt to indicate
conversion on any number of channels.
SMPI (AD1CON2)
1111 = Interrupt for each 16th sample/convert sequence
1110 = Interrupt for each 15th sample/convert sequence
•
•
•
0001 = Interrupt for each 2nd sample/convert sequence
0000 = Interrupt for each sample/convert sequence
DS60001320D-page 704
AGIENxx (ADCGIRQENx)
1 = Data ready event will generate a Global ADC interrupt
0 = No global interrupt
In addition, interrupts can be generated for filter and comparator
events.
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE A-3:
ADC DIFFERENCES (CONTINUED)
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
ADC Calibration
On PIC32MX devices, the ADC module can be used immediately, PIC32MZ devices require a calibration step prior to operation.
once it is enabled.
This is done by copying the calibration data from DEVADCx to the
corresponding ADCxCFG register.
I/O Pin Analog Function Selection
On PIC32MX devices, the analog function of an I/O pin was deter- On PIC32MZ EF devices, the analog selection function has been
mined by the PCFGx bit in the AD1PCFG register.
moved into a separate register on each I/O port. Note that the
sense of the bit is different.
PCFGx (AD1PCFG)
1 = Analog input pin in Digital mode
0 = Analog input pin in Analog mode
ANSxy (ANSELx)
1 = Analog input pin in Analog mode
0 = Analog input pin in Digital mode
Electrical Specifications and Timing Requirements
Refer to “Section 31. Electrical Characteristics” in the On PIC32MZ EF devices, the ADC module sampling and converPIC32MX5XX/6XX/7XX Data Sheet for ADC module sion time and other specifications have changed. Refer to
specifications and timing requirements.
37.0 “Electrical Characteristics” for more information.
2015-2016 Microchip Technology Inc.
DS60001320D-page 705
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
A.3
CPU
The CPU in the PIC32MZ EF family of devices has
been changed to the MIPS32 M-Class MPU architecture. This CPU includes DSP ASE, internal data and
instruction L1 caches, and a TLB-based MMU.
TABLE A-4:
Table A-4 summarizes some of the key differences
(indicated by Bold type) in the internal CPU registers.
CPU DIFFERENCES
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
L1 Data and Instruction Cache and Prefetch Wait States
On PIC32MX devices, the cache was included in the prefetch On PIC32MZ EF devices, the CPU has a separate L1 instruction
module outside the CPU.
and data cache in the core. The PREFEN bits still enable
the prefetch module; however, the K0 bits in the CP0 registers controls the internal L1 cache for the designated regions.
PREFEN (CHECON)
11 = Enable predictive prefetch for both cacheable and
non-cacheable regions
10 = Enable predictive prefetch for non-cacheable regions only
01 = Enable predictive prefetch for cacheable regions only
00 = Disable predictive prefetch
PREFEN (PRECON)
11 = Enable predictive prefetch for any address
10 = Enable predictive prefetch for CPU instructions and CPU
data
01 = Enable predictive prefetch for CPU instructions only
00 = Disable predictive prefetch
DCSZ (CHECON)
K0 (CP0 Reg 16, Select 0)
Changing these bits causes all lines to be reinitialized to the 011 = Cacheable, non-coherent, write-back, write allocate
010 = Uncached
“invalid” state.
001 = Cacheable, non-coherent, write-through, write allocate
11 = Enable data caching with a size of 4 lines
000 = Cacheable, non-coherent, write-through, no write allocate
10 = Enable data caching with a size of 2 lines
01 = Enable data caching with a size of 1 line
00 = Disable data caching
CHECOH (CHECON)
1 = Invalidate all data and instruction lines
0 = Invalidate all data and instruction lines that are not locked
The Program Flash Memory read wait state frequency points
have changed in PIC32MZ EF devices. The register for accessing
the PFMWS field has changed from CHECON to PRECON.
PFMWS (CHECON)
111 = Seven Wait states
110 = Six Wait states
101 = Five Wait states
100 = Four Wait states
011 = Three Wait states
010 = Two Wait states (61-80 MHz)
001 = One Wait state (31-60 MHz)
000 = Zero Wait state (0-30 MHz)
PFMWS (PRECON)
111 = Seven Wait states
•
•
•
100 = Four Wait states (200-252 MHz)
011 = Reserved
010 = Two Wait states (133-200 MHz)
001 = One Wait state (66-133 MHz)
000 = Zero Wait states (0-66 MHz)
Note:
Wait states listed are for ECC enabled.
Core Instruction Execution
On PIC32MX devices, the CPU can execute MIPS16e On PIC32MZ EF devices, the CPU can operate a mode called
instructions and uses a 16-bit instruction set, which reduces microMIPS. microMIPS mode is an enhanced MIPS32®
memory size.
instruction set that uses both 16-bit and 32-bit opcodes. This
mode of operation reduces memory size with minimum
performance impact.
microMIPS™
MIPS16e®
The BOOTISA (DEVCFG0) Configuration bit controls the
MIPS32 and microMIPS modes for boot and exception code.
1 = Boot code and Exception code is MIPS32® (ISAONEXC bit is
set to ‘0’ and the ISA bits are set to ‘10’ in the CP0 Config3
register)
0 = Boot code and Exception code is microMIPS™ (ISAONEXC
bit is set to ‘1’ and the ISA bits are set to ‘11’ in the CP0
Config3 register)
DS60001320D-page 706
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
A.4
Resets
The PIC32MZ EF family of devices has updated the
resets modules to incorporate the new handling of NMI
resets from the WDT, DMT, and the FSCM. In addition,
some bits have been moved, as summarized in
Table A-5.
TABLE A-5:
RESET DIFFERENCES
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
Power Reset
The VREGS bit, which controls whether the internal regulator is
enabled in Sleep mode, has been moved from RCON in
PIC32MX5XX/6XX/7XX devices to a new PWRCON register in
PIC32MZ EF devices.
VREGS (RCON)
1 = Regulator is enabled and is on during Sleep mode
0 = Regulator is disabled and is off during Sleep mode
VREGS (PWRCON)
1 = Voltage regulator will remain active during Sleep
0 = Voltage regulator will go to Stand-by mode during Sleep
Watchdog Timer Reset
On PIC32MX devices, a WDT expiration immediately triggers a On PIC32MZ EF devices, the WDT expiration now causes a NMI.
device reset.
The WDTO bit in RNMICON indicates that the WDT caused the
NMI. A new timer, NMICNT, runs when the WDT NMI is triggered,
and if it expires, the device is reset.
WDT expiration immediately causes a device reset.
WDT expiration causes a NMI, which can then trigger the
device reset.
WDTO (RNMICON)
1 = WDT time-out has occurred and caused a NMI
0 = WDT time-out has not occurred
NMICNT (RNMICON)
A.5
USB
The PIC32MZ EF family of devices has a new HiSpeed USB module, which requires the updated
USB stack from Microchip. In addition, the USB PLL
was also updated. See A.1 “Oscillator and PLL
Configuration” for more information and Table A-6
for a list of additional differences.
TABLE A-6:
USB DIFFERENCES
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
Debug Mode
On PIC32MX devices, when stopping on a breakpoint during On PIC32MZ EF devices, the USB module continues operating
debugging, the USB module can be configured to stop or when stopping on a breakpoint during debugging.
continue execution from the Freeze Peripherals dialog in MPLAB
X IDE.
VBUSON Pin
PIC32MX devices feature a VBUSON pin for controlling the On PIC32MZ EF devices, the VBUSON pin is not available. A port
external transceiver power supply.
pin can be used to achieve the same functionality.
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DS60001320D-page 707
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
A.6
DMA
The DMA controller in PIC32MZ EF devices is similar
to the DMA controller in PIC32MX5XX/6XX/7XX
devices. New features include the extension of pattern
matching to two by bytes and the addition of the
optional Pattern Ignore mode. Table A-7 lists differences (indicated by Bold type) that will affect software
migration.
TABLE A-7:
DMA DIFFERENCES
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
Read/Write Status on Error
The RDWR bit has moved from DMASTAT in PIC32MX5XX/
6XX/7XX devices to DMASTAT in PIC32MZ EF devices.
RDWR (DMASTAT)
RDWR (DMASTAT)
1 = Last DMA bus access when an error was detected was a read 1 = Last DMA bus access when an error was detected was a read
0 = Last DMA bus access when an error was detected was a write 0 = Last DMA bus access when an error was detected was a write
Source-to-Destination Transfer
On PIC32MX devices, a DMA channel performs a read of the
source data and completes the transfer of this data into the destination address before it is ready to read the next data from the
source.
DS60001320D-page 708
On PIC32MZ EF devices, the DMA implements a 4-deep queue
for data transfers. A DMA channel reads the source data and
places it into the queue, regardless of whether previous data in
the queue has been delivered to the destination address.
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PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
A.7
Interrupts and Exceptions
In addition, the IFSx, IECx, and IPCx registers for old
peripherals have shifted to different registers due to
new peripherals. Please refer to 7.0 “CPU Exceptions
and Interrupt Controller” to determine where the
interrupts are now located.
The key difference between Interrupt Controllers in
PIC32MX5XX/6XX/7XX devices and PIC32MZ EF
devices concerns vector spacing. Previous PIC32MX
devices had fixed vector spacing, which is adjustable in
set increments, and every interrupt had the same
amount of space. PIC32MZ EF devices replace this
with a variable offset spacing, where each interrupt has
an offset register to determine where to begin
execution.
TABLE A-8:
Table A-8 lists differences (indicated by Bold type) in
the registers that will affect software migration.
INTERRUPT DIFFERENCES
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
Vector Spacing
On PIC32MX devices, the vector spacing was determined by the On PIC32MZ EF devices, the vector spacing is variable and
VS field in the CPU core.
determined by the Interrupt controller. The VOFFx bits in
the OFFx register are set to the offset from EBASE where the
interrupt service routine is located.
VS (IntCtl: CP0 Register 12, Select 1)
10000 = 512-byte vector spacing
01000 = 256-byte vector spacing
00100 = 128-byte vector spacing
00010 = 64-byte vector spacing
00001 = 32-byte vector spacing
00000 = 0-byte vector spacing
VOFFx (OFFx)
Interrupt Vector ‘x’ Address Offset bits
Shadow Register Sets
On PIC32MX devices, there was one shadow register set which
could be used during interrupt processing. Which interrupt priority
could use the shadow register set was determined by the FSRSSEL field in DEVCFG3 and SS0 on INTCON.
On PIC32MZ EF devices, there are seven shadow register sets,
and each priority level can be assigned a shadow register set to
use via the PRIxSS bits in the PRISS register. The SS0 bit
is also moved to PRISS.
FSRSSEL (DEVCFG3)
111 = Assign Interrupt Priority 7 to a shadow register set
110 = Assign Interrupt Priority 6 to a shadow register set
PRIxSS PRISS
1xxx = Reserved (by default, an interrupt with a priority
level of x uses Shadow Set 0)
0111 = Interrupt with a priority level of x uses Shadow Set 7
0110 = Interrupt with a priority level of x uses Shadow Set 6
•
•
•
001 = Assign Interrupt Priority 1 to a shadow register set
000 = All interrupt priorities are assigned to a shadow
register set
SS0 (INTCON)
1 = Single vector is presented with a shadow register set
0 = Single vector is not presented with a shadow register set
•
•
•
0001 = Interrupt with a priority level of x uses Shadow Set 1
0000 = Interrupt with a priority level of x uses Shadow Set 0
SS0 (PRISS)
1 = Single vector is presented with a shadow register set
0 = Single vector is not presented with a shadow register set
Status
PIC32MX devices, the VEC bits show which interrupt is
being serviced.
On PIC32MZ EF devices, the SIRQ bits show the IRQ
number of the interrupt last serviced.
VEC (INTSTAT)
11111-00000 = The interrupt vector that is presented to the
CPU
SIRQ (INTSTAT)
11111111-00000000 = The last interrupt request number
serviced by the CPU
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DS60001320D-page 709
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
A.8
Flash Programming
The PIC32MZ EF family of devices incorporates a new
Flash memory technology. Applications ported from
PIC32MX5XX/6XX/7XX devices that take advantage of
Run-time Self Programming will need to adjust the
Flash programming steps to incorporate these
changes.
TABLE A-9:
Table A-9 lists the differences (indicated by Bold type)
that will affect software migration.
FLASH PROGRAMMING DIFFERENCES
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
Program Flash Write Protection
On PIC32MX devices, the Program Flash write-protect bits are On PIC32MZ EF devices, the write-protect register is contained
part of the Flash Configuration words (DEVCFG0).
separately as the NVMPWP register. It has been expanded to 24
bits, and now represents the address below, which all Flash memory is protected. Note that the lower 14 bits are forced to zero, so
that all memory locations in the page are protected.
PWP (NVMPWP)
PWP (DEVCFG0)
11111111 = Disabled
11111110 = 0xBD000FFF
11111101 = 0xBD001FFF
11111100 = 0xBD002FFF
11111011 = 0xBD003FFF
11111010 = 0xBD004FFF
11111001 = 0xBD005FFF
11111000 = 0xBD006FFF
11110111 = 0xBD007FFF
11110110 = 0xBD008FFF
11110101 = 0xBD009FFF
11110100 = 0xBD00AFFF
11110011 = 0xBD00BFFF
11110010 = 0xBD00CFFF
11110001 = 0xBD00DFFF
11110000 = 0xBD00EFFF
11101111 = 0xBD00FFFF
Physical memory below address 0x1Dxxxxxx is write protected,
where ‘xxxxxx’ is specified by PWP. When PWP
has a value of ‘0’, write protection is disabled for the entire program Flash. If the specified address falls within the page, the
entire page and all pages below the current page will be protected.
•
•
•
01111111 = 0xBD07FFFF
Code Protection
On PIC32MX devices, code protection is enabled by the CP
(DEVCFG) bit.
On PIC32MZ EF devices, code protection is enabled by the CP
(DEVCP0) bit.
Boot Flash Write Protection
On PIC32MX devices, Boot Flash write protection is enable by
the BWP (DEVCFG) bit and protects the entire Boot Flash
memory.
On PIC32MZ EF devices, Boot Flash write protection is divided
into pages and is enable by the LBWPx and UBWPx bits in the
NVMBWP register.
Low-Voltage Detect Status
LVDSTAT (NVMCON)
1 = Low-voltage event is active
0 = Low-voltage event is not active
DS60001320D-page 710
The LVDSTAT bit is not available in PIC32MZ EF devices.
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PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE A-9:
FLASH PROGRAMMING DIFFERENCES (CONTINUED)
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
Flash Programming
The op codes for programming the Flash memory have been
changed to accommodate the new quad-word programming and
dual-panel features. The row size has changed to 2 KB (512 IW)
from 128 IW. The page size has changed to 16 KB (4K IW) from
4 KB (1K IW). Note that the NVMOP register is now protected,
and requires the WREN bit be set to enable modification.
NVMOP (NVMCON)
1111 = Reserved
NVMOP (NVMCON)
1111 = Reserved
•
•
•
•
•
•
0111
0110
0101
0100
0011
0010
0001
0000
= Reserved
= No operation
= Program Flash (PFM) erase operation
= Page erase operation
= Row program operation
= No operation
= Word program operation
= No operation
1000 = Reserved
0111 = Program erase operation
0110 = Upper program Flash memory erase operation
0101 = Lower program Flash memory erase operation
0100 = Page erase operation
0011 = Row program operation
0010 = Quad Word (128-bit) program operation
0001 = Word program operation
0000 = No operation
PIC32MX devices feature a single NVMDATA register for word
programming.
On PIC32MZ EF devices, to support quad word programming,
the NVMDATA register has been expanded to four words.
NVMDATA
NVMDATAx, where ‘x’ = 0 through 3
Flash Endurance and Retention
PIC32MX devices support Flash endurance and retention of up
to 20K E/W cycles and 20 years.
On PIC32MZ EF devices, ECC must be enabled to support the
same endurance and retention as PIC32MX devices.
Configuration Words
On PIC32MX devices, Configuration Words can be programmed
with Word or Row program operation.
On PIC32MZ EF devices, all Configuration Words must be
programmed with Quad Word or Row Program operations.
Configuration Words Reserved Bit
On PIC32MX devices, the DEVCFG0 bit is Reserved and
must be programmed to ‘0’.
2015-2016 Microchip Technology Inc.
On PIC32MZ EF devices, this bit is DEVSIGN0.
DS60001320D-page 711
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
A.9
Other Peripherals and Features
Table A-10 lists the differences (indicated by Bold
type) that will affect software and hardware migration.
Most of the remaining peripherals on PIC32MZ EF
devices act identical to their counterparts on PIC32MX5XX/6XX/7XX devices. The main differences have to
do with handling the increased peripheral bus clock
speed and additional clock sources.
TABLE A-10:
PERIPHERAL DIFFERENCES
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
2
I C
On PIC32MX devices, all pins are 5V-tolerant.
On PIC32MZ EF devices, the I2C4 port uses non-5V tolerant
pins, and will have different VOL/VOH specifications.
The Baud Rate Generator register has been expanded from 12
bits to 16 bits.
I2CxBRG
I2CxBRG
Watchdog Timer
Clearing the Watchdog Timer on PIC32MX5XX/6XX/7XX
devices required writing a ‘1’ to the WDTCLR bit.
On PIC32MZ EF devices, the WDTCLR bit has been replaced
with the 16-bit WDTCLRKEY, which must be written with a specific value (0x5743) to clear the Watchdog Timer. In addition, the
WDTSPGM (DEVCFG1) bit is used to control operation of
the Watchdog Timer during Flash programming.
WDTCLR (WDTCON)
WDTCLRKEY (WDTCON)
RTCC
On PIC32MX devices, the output of the RTCC pin was selected
between the Seconds Clock or the Alarm Pulse.
On PIC32MZ EF devices, the RTCC Clock is added as an
option. RTCSECSEL has been renamed RTCOUTSEL and
expanded to two bits.
RTCSECSEL (RTCCON)
1 = RTCC Seconds Clock is selected for the RTCC pin
0 = RTCC Alarm Pulse is selected for the RTCC pin
RTCOUTSEL (RTCCON)
11 = Reserved
10 = RTCC Clock is presented on the RTCC pin
01 = Seconds Clock is presented on the RTCC pin
00 = Alarm Pulse is presented on the RTCC pin when the alarm
interrupt is triggered
On PIC32MX devices, the Secondary Oscillator (SOSC) serves
as the input clock for the RTCC module.
On PIC32MZ EF devices, an additional clock source, LPRC, is
available as a choice for the input clock.
RTCCLKSEL (RTCCON)
11 = Reserved
10 = Reserved
01 = RTCC uses the external 32.768 kHz SOSC
00 = RTCC uses the internal 32 kHz oscillator (LPRC)
DS60001320D-page 712
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PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
TABLE A-10:
PERIPHERAL DIFFERENCES (CONTINUED)
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
Ethernet
On PIC32MZ EF devices, the input clock divider for the Ethernet
module has expanded options to accommodate the faster
peripheral bus clock.
CLKSEL (EMAC1MCFG)
1000 = SYSCLK divided by 40
0111 = SYSCLK divided by 28
0110 = SYSCLK divided by 20
0101 = SYSCLK divided by 14
0100 = SYSCLK divided by 10
0011 = SYSCLK divided by 8
0010 = SYSCLK divided by 6
000x = SYSCLK divided by 4
CLKSEL (EMAC1MCFG)
1010 = PBCLK5 divided by 50
1001 = PBCLK5 divided by 48
1000 = PBCLK5 divided by 40
0111 = PBCLK5 divided by 28
0110 = PBCLK5 divided by 20
0101 = PBCLK5 divided by 14
0100 = PBCLK5 divided by 10
0011 = PBCLK5 divided by 8
0010 = PBCLK5 divided by 6
000x = PBCLK5 divided by 4
Comparator/Comparator Voltage Reference
On PIC32MX devices, it was possible to select the VREF+ pin as
the output to the CVREFOUT pin.
On PIC32MZ EF devices, the CVREFOUT pin must come from the
resistor network.
VREFSEL (CVRCON)
1 = CVREF = VREF+
0 = CVREF is generated by the resistor network
This bit is not available.
On PIC32MX devices, the internal voltage reference (IVREF)
could be chosen by the BGSEL bits.
On PIC32MZ EF devices, IVREF is fixed and cannot be changed.
BGSEL (CVRCON)
11 = IVREF = VREF+
10 = Reserved
01 = IVREF = 0.6V (nominal, default)
00 = IVREF = 1.2V (nominal)
These bits are not available.
Change Notification
On PIC32MX devices, Change Notification is controlled by the
CNCON, CNEN, and CNPUE registers.
On PIC32MZ EF devices, Change Notification functionality has
been relocated into each I/O port and is controlled by the
CNPUx, CNPDx, CNCONx, CNENx, and CNSTATx registers.
System Bus
On PIC32MX devices, the System Bus registers can be used to
configure RAM memory for data and program memory partitions,
cacheability of Flash memory, and RAM Wait states. These registers are: BMXCON, BMXDKPBA, BMXDUDBA, BMXDUPBA,
BMXPUPBA, BMXDRMSZ, BMXPFMSZ, and BMXBOOTSZ.
On PIC32MZ EF devices, a new System Bus is utilized that supports using RAM memory for program or data without the need
for special configuration. Therefore, no special registers are
associated with the System Bus to configure these features.
On PIC32MX devices, various arbitration modes are used as ini- On PIC32MZ EF devices, a new arbitration scheme has been
tiators on the System Bus. These modes can be selected by the implemented on the System Bus. All initiators use the Least
BMXARB (BMXCON) bits.
Recently Serviced (LRS) scheme, with the exception of the
DMA, CPU, and the Flash Controller.
The Flash Controller always has High priority over LRS initiators.
The DMA and CPU (when servicing an interrupt) can be selected
to have LRS or High priority using the DMAPRI (CFGCON)
and CPUPRI (CFGCON) bits.
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DS60001320D-page 713
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
A.10
Package Differences
In general, PIC32MZ EF devices are mostly pin compatible with PIC32MX5XX/6XX/7XX devices; however, some pins are not. In particular, the VDD and
VSS pins have been added and moved to different
pins. In addition, I/O functions that were on fixed
pins now will largely be on remappable pins.
TABLE A-11:
PACKAGE DIFFERENCES
PIC32MX5XX/6XX/7XX Feature
PIC32MZ EF Feature
VCAP Pin
On PIC32MX devices, an external capacitor is required between
a VCAP pin and GND, which provides a filtering capacitor for the
internal voltage regulator.
On PIC32MZ EF devices, this requirement has been removed.
A low-ESR capacitor (typically 10 µF) is required on the VCAP
pin.
No VCAP pin.
VDD and VSS Pins
There are more VDD pins on PIC32MZ EF devices, and many
are located on different pins.
VDD on 64-pin packages: 8, 26, 39, 54, 60
VDD on 100-pin packages: 14, 37, 46, 62, 74, 83, 93
VDD on 64-pin packages: 10, 26, 38, 57
VDD on 100-pin packages: 2, 16, 37, 46, 62, 86
There are more VSS pins on PIC32MZ EF devices, and many are
located on different pins.
VSS on 64-pin packages: 7, 25, 35, 40, 55, 59
VSS on 100-pin packages: 13, 36, 45, 53, 63, 75, 84, 92
VSS on 64-pin packages: 9, 25, 41
VSS on 100-pin packages: 15, 36, 45, 65, 75
PPS I/O Pins
Peripheral functions on PIC32MZ EF devices are now routed
through a PPS module, which routes the signals to the desired
pins. When migrating software, it is necessary to initialize the
PPS I/O functions in order to get the signal to and from the correct pin.
All peripheral functions are fixed as to what pin upon which they
operate.
DS60001320D-page 714
PPS functionality for the following peripherals:
• CAN
• UART
• SPI (except SCK)
• Input Capture
• Output Compare
• External Interrupt (except INT0)
• Timer Clocks (except Timer1)
• Reference Clocks (except REFCLK2)
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
APPENDIX B:
MIGRATING FROM
PIC32MZ EC TO
PIC32MZ EF
The PIC32MZ EF devices are similar to PIC32MZ EC
devices, with many feature improvements and new
capabilities.
This appendix provides an overview of considerations
for migrating from PIC32MZ EC devices to the
PIC32MZ EF family of devices. The code developed for
PIC32MZ EC devices can be ported to PIC32MZ EF
devices after making the appropriate changes outlined
in the following sections.
TABLE B-1:
B.1
Oscillator and PLL Configuration
A number of new features have been added to the
oscillator and PLL to enhance their ability to work with
crystals and to change frequencies.
Table B-1 summarizes the differences (indicated by
Bold type) between the family differences for the
oscillator.
OSCILLATOR DIFFERENCES
PIC32MZ EC Feature
PIC32MZ EF Feature
Primary Oscillator Crystal Power
On PIC32MZ EC devices, the crystal HS POSC mode is only
functional with crystals that have certain characteristics, such as
very low ESR.
On PIC32MZ EF devices, some DEVCFG0 bits have been
added to allow control over the strength of the oscillator and to
add a kick start boost.
POSCBOOST (DEVCFG0)
1 = Boost the kick start of the oscillator
0 = Normal start of the oscillator
POSCGAIN (DEVCFG0)
11 = 2x gain setting
10 = 1.5x gain setting
01 = 0.5x gain setting
00 = 1x gain setting
Note that the default for POSCGAIN (2x gain setting) may overdrive crystals and shorten their life. It is the responsibility of the
designer to ensure crystals are operated properly.
Secondary Oscillator Crystal Power
On PIC32MZ EC devices, the Secondary Oscillator (SOSC) is not
functional.
On PIC32MZ EF devices, the Secondary Oscillator is now
functional, and provides similar strength and kick start boost
features as the POSC.
SOSCBOOST (DEVCFG0)
1 = Boost the kick start of the oscillator
0 = Normal start of the oscillator
SOSCGAIN (DEVCFG0)
11 = 2x gain setting
10 = 1.5x gain setting
01 = 0.5x gain setting
00 = 1x gain setting
Note that the default for SOSCGAIN (2x gain setting) may overdrive crystals and shorten their life. It is the responsibility of the
designer to ensure crystals are operated properly.
Clock Status Bits
On PIC32MZ EC devices, the SOSCRDY bit (OSCCON)
indicates when the Secondary Oscillator is ready. There are no
indications of other oscillator status.
A new register, CLKSTAT, has been added, which includes the
SOSCRDY bit (CLKSTAT). In addition, new status bits are
available:
• LPRCRDY (CLKSTAT)
• POSCRDY (CLKSTAT)
• DIVSPLLRDY (CLKSTAT)
• FRCRDY (CLKSTAT)
Clock Switching
On PIC32MZ EC devices, clock switches occur as soon as the
switch command is issued. Also, the only clock sources that can
be divided are the output of the PLL, and the FRC.
2015-2016 Microchip Technology Inc.
To reduce power spikes during clock switches, PIC32MZ EF
devices add a clock slewing feature, so that clock switches can
be controlled in their rate and size. The SLEWCON register
controls this feature. The SLEWCON register also features a
SYSCLK divider, so that all of the possible clock sources may be
divided further as needed.
DS60001320D-page 715
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
B.2
Analog-to-Digital Converter (ADC)
The PIC32MZ EC family features a Pipelined ADC
module, while the PIC32MZ EF family of devices has
an entirely new 12-bit High-Speed SAR ADC module.
Nearly all registers in this new ADC module differ from
the registers in PIC32MZ EC devices. Due to this difference, code will not port from PIC32MZ EC devices to
PIC32MZ EF devices. Table B-2 lists some of the differences in registers to note to adapt code as quickly as
possible.
TABLE B-2:
ADC DIFFERENCES
PIC32MZ EC Feature
PIC32MZ EF Feature
Clock Selection and Operating Frequency (TAD)
On PIC32MZ EC devices, there are three possible sources of the On PIC32MZ EF devices, there are four sources for the ADC
ADC clock: FRC, REFCLKO3, and SYSCLK.
clock. In addition to the ones for PIC32MZ EC, PBCLK4 is added
as a source. Also, the clock source selection is in a different
register.
ADCSEL (AD1CON1)
11 = FRC
10 = REFCLKO3
01 = SYSCLK
00 = Reserved
ADCSEL (ADCCON3)
11 = FRC
10 = REFCLKO3
01 = SYSCLK
00 = PBCLK4
Scan Trigger Sources
On PIC32MZ EC devices, there are 10 available trigger sources
for starting ADC sampling and conversion.
On PIC32MZ EF devices, two new sources have been added.
One is a shared trigger source (STRIG). The other is a Global
Level Software Trigger (GLSWTRG). With the GLSWTRG, the
conversions continue until the bit is cleared in software.
STRGSRC (AD1CON1)
11111 = Reserved
TRGSRC (ADCTRGx)
11111 = Reserved
•
•
•
•
•
•
01101 = Reserved
01100 = Comparator 2 COUT
01011 = Comparator 1 COUT
01010 = OCMP5
01001 = OCMP3
01000 = OCMP1
00111 = TMR5 match
00110 = TMR3 match
00101 = TMR1 match
00100 = INT0
00011 = Reserved
00010 = Reserved
00001 = Global Software Trigger (GSWTRG)
00000 = No trigger
01101 = Reserved
01100 = Comparator 2 COUT
01011 = Comparator 1 COUT
01010 = OCMP5
01001 = OCMP3
01000 = OCMP1
00111 = TMR5 match
00110 = TMR3 match
00101 = TMR1 match
00100 = INT0
00011 = STRIG
00010 = Global Level Software Trigger (GLSWTRG)
00001 = Global Software Trigger (GSWTRG)
00000 = No trigger
Debug Mode
On PIC32MZ EC devices, the ADC module continues operating
when stopping on a breakpoint during debugging.
On PIC32MZ EF devices, the ADC module will stop during
debugging when stopping on a breakpoint.
Electrical Specifications and Timing Requirements
Refer to the “Electrical Characteristics” chapter in the
PIC32MZ EC data sheet for ADC module specifications and
timing requirements.
On PIC32MZ EF devices, the ADC module sampling and
conversion time and other specifications have changed. Refer to
37.0 “Electrical Characteristics” for more information.
ADC Calibration
PIC32MZ EC devices require calibration values be copied into the PIC32MZ EF devices also require ADC calibration values, but the
AD1CALx registers before turning on the ADC. These values destination registers are named ADCxCAL.
come from the DEVADCx registers.
DS60001320D-page 716
2015-2016 Microchip Technology Inc.
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
B.3
CPU
B.4
The CPU in PIC32MZ EC devices is the microAptiv™
MPU architecture. The CPU in the PIC32MZ EF
devices is the Series 5 Warrior M-Class M5150 MPU
architecture. Most PIC32MZ EF M-Class core features
are identical to the microAptiv™ core in PIC32MZ EC
devices. The main differences are that in PIC32MZ EF
devices, a floating-point unit (FPU) is included for
improved math performance, and PC Sampling for
performance measurement.
TABLE B-3:
System Bus
The system bus on PIC32MZ EF devices is similar to
the system bus on PIC32MZ EC devices. There are
two key differences listed in Table B-3.
SYSTEM BUS DIFFERENCES
PIC32MZ EC Feature
PIC32MZ EF Feature
Permission Groups during NMI
On PIC32MZ EC devices, the permission group in which the
CPU is part of is lost during NMI handling, and must be manually
restored.
On PIC32MZ EF devices, the prior permission group is
preserved, and is restored when the CPU returns from the NMI
handler.
DMA Access
The DMA can access the peripheral registers on Peripheral
Bus 1.
B.5
On PIC32MZ EF devices, the DMA no longer has access to
registers on Peripheral Bus 1. Refer to Table 4-4 for details on
which peripherals are now excluded.
Flash Controller
The Flash controller on PIC32MZ EF devices adds the
ability both to control boot Flash aliasing, and for locking the current swap settings. Table B-4 lists theses
differences.
TABLE B-4:
FLASH CONTROLLER DIFFERENCES
PIC32MZ EC Feature
PIC32MZ EF Feature
Boot Flash Aliasing
On PIC32MZ EC devices, Boot Flash aliasing is done through
the DEVSEQ0 register, but no further changes are possible
without rebooting the processor.
On PIC32MZ EF devices, the initial Boot Flash aliasing is
determined by the DEVSEQ3 register, but the BFSWAP bit
(NVMCON) reflects the state of the aliasing, and can be
modified to change it during run-time.
BFSWAP (NVMCON)
1 = Boot Flash Bank 2 is mapped to the lower boot alias, and Boot
Flash bank 1 is mapped to the upper boot alias
0 = Boot Flash Bank 1 is mapped to the lower boot alias, and Boot
Flash Bank 2 is mapped to the upper boot alias
PFM and BFM Swap Locking
On PIC32MZ EC devices, the swapping of PFM is always
available.
On PIC32MZ EF devices, a new control, SWAPLOCK
(NVMCON2) allows the locking of PFSWAP and BFSWAP
bits, and can restrict any further changes.
SWAPLOCK (NVMCON2)
11 = PFSWAP and BFSWAP are not writable and SWAPLOCK is
not writable
10 = PFSWAP and BFSWAP are not writable and SWAPLOCK is
writable
01 = PFSWAP and BFSWAP are not writable and SWAPLOCK is
writable
00 = PFSWAP and BFSWAP are writable and SWAPLOCK is
writable
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B.6
Resets
On PIC32MZ EF devices, the Reset module adds eight
bits to the NMICNT field to make the time-out period
before device Reset longer, as described in Table B-5.
TABLE B-5:
RESETS DIFFERENCES
PIC32MZ EC Feature
PIC32MZ EF Feature
Countdown to Reset During NMIs
On PIC32MZ EC devices, the NMICNT field is eight bits
long, giving a maximum of 256 instructions before the device
Reset.
B.7
On PIC32MZ EF devices, the NMICNT field is now 16 bits
long, giving a longer period of time (up to 65,536 instructions)
prior to a device Reset.
USB
On PIC32MZ EF devices, a new USBCRCON register
has been added to assist in controlling the reset of the
USB module, and triggering interrupts based on VBUS
voltage levels. This register also overcomes an errata
on PIC32MZ EC devices that requires a three second
start-up on the USB module.
B.8
I/O Ports
On PIC32MZ EF devices, many of the I/O pins now
feature slew rate control bits to control how fast the pin
makes a low-to-high or high-to-low transition. The
Change Notification feature has also been enhanced to
allow detection of level events in addition to edge
detection. However, the SIDL bit is not present in the
CNCONx registers on PIC32MZ EF devices, as it is on
PIC32MZ EC devices.
B.9
Watchdog Timer
PIC32MZ EF devices use a new Watchdog Timer,
although the overall control through the DEVCFGx
words remains identical to that of PIC32MZ EC
devices. Table B-6 lists two more changes, as well.
TABLE B-6:
WATCHDOG TIMER DIFFERENCES
PIC32MZ EC Feature
PIC32MZ EF Feature
Watchdog Timer Postscaler
On PIC32MZ EC devices, the SWDTPS bits
(WDTCON) reflect the postscaler setting for the Watchdog
Timer.
On PIC32MZ EF devices, the field has been changed to the
RUNDIV bits (WDTCON).
Watchdog Windowed Mode
On PIC32MZ EC devices, WDTWINEN is at bit position 1
(WDTCON).
DS60001320D-page 718
On PIC32MZ EF devices, WDTWINEN is now at bit position 0
(WDTCON).
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PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
B.10
Serial Quad Interface (SQI)
On PIC32MZ EF devices, the SQI module has been
updated with the following features:
• FIFOs can be reset through the CONFIFORST
(SQI1CFG), RXFIFORST (SQI1CFG),
and TXFIFORST (SQI1CFG) bits in
Register 20-3
• A new Flash Status check is available, which will
allow the SQI to automatically query the status of
the external device during write/erase operations
without software intervention. See the SCHECK bit
(SQI1CON) and the SQI1MEMSTAT register
(Register 20-4 and Register 20-24, respectively).
• The SQI clock divider bits have been expanded,
and can use an undivided clock. See the
CLKDIV bits (SQI1CLKCON) in
Register 20-5.
• A new DMA Bus Error Interrupt is available through
the DMAEIE (SQI1INTEN), DMAEIF
(SQI1INTSTAT), and DMAEISE
(SQI1INTSIGEN) bits in Register 20-8,
Register 20-9, and Register 20-22, respectively
• The SQI1STAT2 register (see Register 20-13) has
two new fields:
- CMDSTAT (SQI1STAT2) indicates
the current command status
- CONAVAIL (SQI1STAT) indicates
how many spaces are available in the Control
FIFO.
• The TAP Controller within the SQI can be
configured for various timing requirements via the
SQI1TAPCON register (Register 20-23)
• Two new XIP mode registers (SQI1XCON3 and
SQI1XCON4) have been added for additional
command sequencing (see Register 20-25 and
Register 20-26, respectively)
B.11
PMP
On PIC32MZ EF devices, the PMP features the ability
to buffer reads and writes in both directions, and can
read and write from different addresses. Refer to
23.0 “Parallel Master Port (PMP)” and Section 43.
“Parallel Master Port” (DS60001346) for information.
Refer to 20.0 “Serial Quad Interface (SQI)” and
Section 46. “Serial Quad Interface (SQI)”
(DS60001128) for more information.
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B.12
Crypto Engine
Table B-7 lists the changes available for the Crypto
Engine.
TABLE B-7:
CRYPTO DIFFERENCES
PIC32MZ EC Feature
PIC32MZ EF Feature
Output Data Format
On PIC32MZ EC devices, the output of the Crypto Engine is
always in big-endian format, usually requiring a software (or
DMA) solution to put the data into little-endian format, which the
core handles natively.
B.13
On PIC32MZ EF devices, the SWAPOEN bit (CECON) has
been added to control output byte swapping. This bit, when
enabled, will byte-swap the output.
Device Configuration and Control
A number of enhancements have been added to the
PIC32MZ EF devices that allow greater control and
flexibility on the device. Some bit fields have also
changed location. Table B-8 lists these changes.
TABLE B-8:
DEVICE CONFIGURATION AND CONTROL DIFFERENCES
PIC32MZ EC Feature
PIC32MZ EF Feature
MCLR Pin Configuration
On PIC32MZ EC devices, the MCLR pin always generate a
system reset.
On PIC32MZ EF devices, the MCLR pin can now be configured
to generate either a system Reset or an emulated POR Reset.
SMCLR (DEVCFG0)
1 = MCLR pin generates a normal system Reset
0 = MCLR pin generates an emulated POR Reset
I/O Analog Charge Pump
Low VDD environments cause attenuation of analog inputs.
A new bit enables an I/O charge pump, which improves analog
performance when operating at lower VDD.
IOANCPEN (CFGCON)
1 = Charge pump is enabled
0 = Charge pump is disabled
EBI Ready Pin Control
The EBIRDY control bits have been moved.
EBIRDYINV (CFGEBIC)
EBIRDYEN (CFGEBIC)
EBIRDYINV (CFGEBIC)
EBIRDYEN (CFGEBIC)
Boot Flash Sequence Control
On PIC32MZ EC devices, the Boot Flash Sequence (specifying
which boot memory was mapped to the lower boot alias) was
determined with the BFxSEQ0 registers.
DS60001320D-page 720
On PIC32MZ EF devices, the Boot Flash Sequence has been
moved to the BFxSEQ3 register.
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PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
APPENDIX C:
REVISION HISTORY
Revision A (January 2015)
This is the initial released version of the document.
Revision B (July 2015)
The document status was updated from Advance
Information to Preliminary.
The revision includes the following major changes,
which are referenced by their respective chapter in
Table C-1.
In addition, minor updates to text and formatting were
incorporated throughout the document.
TABLE C-1:
MAJOR SECTION UPDATES
Section Name
Update Description
32-bit MCUs (up to 2 MB LiveThe Operating Conditions were updated to: 2.1V to 3.6V.
Update Flash and 512 KB SRAM)
with FPU, Audio and Graphics
Interfaces, HS USB, Ethernet,
and Advanced Analog
4.0 “Memory Organization”
Legal information on the System Bus was added (see 4.2 “System Bus
Arbitration”).
5.0 “Flash Program Memory”
The BOOTSWAP bit in the NVMCON register was changed to: BFSWAP (see
Register 5-1).
6.0 “Resets”
The NVMLTA bit was removed from the RCON register (see Register 6-1).
The GNMI bit was added to the RNMICON register (see Register 6-3).
7.0 “CPU Exceptions and
Interrupt Controller”
The ADC FIFO Data Ready Interrupt, IRQ 45, was added (see Table 7-2).
ADC FIFO bits were added, and Note 7 regarding devices without a Crypto
module was added to the Interrupt Register Map (see Table 7-3).
The NMIKEY bits were added to the INTCON register (see Register 7-1).
8.0 “Oscillator Configuration”
The SPLLRDY bit was removed and the SPLLDIVRDY bit was added to the
CLKSTAT register (see Register 8-8
11.0 “Hi-Speed USB with On-The- The VBUSIE and VBUSIF bits were changed to: VBUSERRIE and
Go (OTG)”
VBUSERRIF, respectively in the USBCSR2 register (see Register 11-3).
15.0 “Deadman Timer (DMT)”
The POR values were updated for the PSCNT bits in the Post Status
Configure DMT Count Status register (see Register 15-6).
The POR values were updated for the PSINTV bits in the Post Status
Configure DMT Interval Status register (see Register 15-7).
16.0 “Watchdog Timer (WDT)”
The WDTCON register was updated (see Register 16-1).
23.0 “Parallel Master Port (PMP)” The PMDOUT, PMDIN, and PMRDIN registers were added (see Register 23-4,
Register 23-4, and Register 23-10).
The PMADDR, PMWADDR, and PMRADDR registers were updated (see
Register 23-3, Register 23-8, and Register 23-9).
The PMRDATA register was removed.
24.0 “External Bus Interface
(EBI)”
Reset values for the EBIMSK2, EBIMSK3, EBISMT0-EBISMT2, and
EBIFTRPD registers were updated in the EBI Register Map (see Table 24-2).
POR value changes were implemented to the EBI Static Memory Timing
Register (see Register 24-3).
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TABLE C-1:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
27.0 “Random Number Generator The TRNGMODE bit was added to the RNGCON register (see Register 27-2).
(RNG)”
28.0 “12-bit High-Speed
Successive Approximation
Register (SAR) Analog-to-Digital
Converter (ADC)”
The S&H Block Diagram was updated (see Figure 28-2).
The registers, ADCTRG4 through ADCTRG8, were removed.
The bit value definitions for the ADCSEL and CONCLKDIV bits in
the ADCCON3 register were updated (see Register 28-3).
The bit names in the ADC Status registers (Register 28-12 and Register 28-13)
were updated to match the names in the SFR summary table.
The ADCTRGSNS register was updated (see Register 28-26).
The POR values were changed in the ADC System Configuration registers (see
Register 28-34 and Register 28-35).
34.0 “Special Features”
The FDBGWP bit was removed from the DEVCFG0/ADEVCFG0 registers (see
Register 34-3).
37.0 “Electrical Characteristics”
V-Temp (-40°C TA +105°C) information was removed from all tables.
The operating conditions voltage range was updated in the Absolute Maximum
Ratings and in all tables to: 2.1V to 3.6V.
Notes on Maximum value operating conditions were added to the Operating,
Idle, and Power-Down Current tables (see Table 37-6, Table 37-7, and
Table 37-8, respectively).
The conditions for System Timing Requirement parameters OS55a and OS55b
were updated (see Table 37-18).
The Internal FRC Accuracy specifications were updated (see Table 37-20).
The Internal LPRC Accuracy specifications were updated (see Table 37-21).
The ADC Module Specifications were updated (see Table 37-38).
The Analog-to-Digital Conversion Timing Requirements were updated (see
Table 37-39).
Appendix B: “Migrating from
PIC32MZ EC to PIC32MZ EF”
This appendix was added, which provides an overview of considerations for
migrating from PIC32MZ EC devices to the PIC32MZ EF family of devices.
Product Identification System
V-Temp (-40°C TA +105°C) information was removed.
DS60001320D-page 722
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PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
Revision C (March 2016)
In this revision, the Preliminary status was removed
from the document footer.
The revision also includes the following major changes,
which are referenced by their respective chapter in
Table C-2. In addition, minor updates to text and
formatting were incorporated throughout the
document.
TABLE C-2:
MAJOR SECTION UPDATES
Section Name
Update Description
2.0 “Guidelines for Getting
Started with 32-bit
Microcontrollers”
2.9.1.3 “EMI/EMC/EFT (IEC 61000-4-4 and IEC 61000-4-2) Suppression
Considerations” and Figure 2-5 were updated.
4.0 “Memory Organization”
The names of the Boot Flash Words were updated from BFxSEQ0 to BFxSEQ3
(see 4.1.1 “Boot Flash Sequence and Configuration Spaces”).
The ABFxSEQx registers were removed from the Boot Flash Sequence and
Configuration tables (see Table 4-2 and Table 4-3).
7.0 “CPU Exceptions and
Interrupt Controller”
The Cache Error exception type was removed from the MIPS32 M-Class
Microprocessor Core Exception Types (see Table 7-1).
8.0 “Oscillator Configuration”
The PLLODIV bit value settings were updated in the SPLLCON register
(see Register 8-3).
12.0 “I/O Ports”
The SIDL bit was removed from the CNCONx registers (see Table 12-4 through
Table 12-21 and Register 12-3).
20.0 “Serial Quad Interface
(SQI)”
The following bits were removed from the SQI1XCON1 register (see Table 20-1
and Register 20-1): DDRDATA, DDRDUMMY, DDRMODE, DDRADDR, and
DDRCMD.
The DDRMODE bit was removed from the SQI1CON register (see Table 20-1
and Register 20-4).
28.0 “12-bit High-Speed
Successive Approximation
Register (SAR) Analog-to-Digital
Converter (ADC)”
A note was added to the SELRES bits in the ADCCON1 and ADCxTIME
registers (see Register 28-1 and Register 28-27).
34.0 “Special Features”
The bit value definitions for the POSCGAIN and SOSCGAIN bits
were updated (see Register 34-3).
The ADCID
