PIC32MZ Graphics (DA) Family
32-bit Graphics Applications MCUs (up to 2 MB Live Update Flash,
640 KB SRAM, and 32 MB DDR2 SDRAM) with XLP Technology
Operating Conditions
Advanced Analog Features
• -40ºC to +85ºC, DC to 200 MHz
- VDDIO = 2.2V to 3.6V
- VDDCORE = 1.7V to 1.9V
• 12-bit ADC modules:
- 18 Msps with up to six ADC circuits (five dedicated and one
shared)
- Up to 45 analog input
- Can operate during Sleep and Idle modes
- Multiple trigger sources
- Six Digital Comparators and six Digital Filters
• Two Comparators with 32 programmable voltage references
• Temperature sensor with ±2ºC accuracy
• Charge Time Measurement Unit (CTMU)
Core: 200 MHz / 330 DMIPS MIPS32® microAptiv™
•
•
•
•
32 KB I-Cache, 32 KB D-Cache
MMU for optimum embedded OS execution
microMIPS™ mode for up to 35% smaller code size
DSP-enhanced core:
- Four 64-bit accumulators
- Single-cycle MAC, saturating and fractional math
• Code-efficient (C and Assembly) architecture
Communication Interfaces
• Two CAN modules (with dedicated DMA channels):
- 2.0B Active with DeviceNet™ addressing support
• Six UART modules (25 Mbps):
- Supports up to LIN 2.1 and IrDA® protocols
• Six 4-wire SPI modules (up to 50 MHz)
• SQI configurable as additional SPI module (up to 80 MHz)
• Five I2C modules (up to 1 Mbaud) with SMBus support
• Parallel Host Port (PMP)
• Peripheral Pin Select (PPS) to enable function remap
Clock Management
•
•
•
•
•
Programmable PLLs and oscillator clock sources
Dedicated PLL for DDR2
Fail-Safe Clock Monitor
Independent Watchdog and Deadman Timers
Fast wake-up and start-up
Power Management
• Various power management options for extreme power
reduction (VBAT, Deep Sleep, Sleep and Idle)
• Deep Sleep current: < 1 µA (typical)
• Integrated POR and BOR
• Programmable High/Low-Voltage Detect (HLVD) on VDDIO
and High-Voltage Detect (HVD) on VDDR1V8
Timers/Output Compare/Input Capture
•
•
•
•
Memory Interfaces
•
•
•
•
DDR2 SDRAM interface (up to DDR2-400)
SD/SDIO/eMMC bus interface (up to 50 MHz)
Serial Quad Interface (up to 80 MHz)
External Bus Interface (up to 50 MHz)
Nine 16-bit and up to four 32-bit timers/counters
Nine Output Compare (OC) modules
Nine Input Capture (IC) modules
Real-Time Clock and Calendar (RTCC) module
Input/Output
•
•
•
•
•
Graphics Features
• 3-layer Graphics Controller with up to 24-bit color support
• High-performance 2D Graphics Processing Unit (GPU)
5V-tolerant pins with up to 32 mA source/sink
Selectable open drain, pull-ups, and pull-downs
Selectable slew rate control
External interrupts on all I/O pins
PPS to enable function remap
Qualification and Class B Support
Audio Interfaces
• Class B Safety Library, IEC 60730
• Back-up internal oscillator
• Audio data communication: I2S, LJ, and RJ
• Audio control interfaces: SPI and I2C
• Audio host clock: Fractional clock frequencies with USB synchronization
Debugger Development Support
• USB 2.0-compliant High-Speed On-The-Go (OTG) controller
• 10/100 Mbps Ethernet MAC with MII and RMII interface
•
•
•
•
•
Security Features
Integrated Software Libraries and Tools
High-Speed Communication Interfaces (with
Dedicated DMA)
• Crypto Engine with a RNG for data encryption/decryption and
authentication (AES, 3DES, SHA, MD5, and HMAC)
• Advanced memory protection:
- Peripheral and memory region access control
•
•
•
•
Direct Memory Access (DMA)
In-circuit and in-application programming
4-wire MIPS® Enhanced JTAG interface
Unlimited software and 12 complex breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Non-intrusive hardware-based instruction trace
C/C++ compiler with native DSP/fractional support
MPLAB® Harmony Integrated Software Framework
TCP/IP, USB, Graphics, and mTouch™ middleware
MFi, Android™, and Bluetooth® audio frameworks
• RTOS Kernels: Express Logic ThreadX, FreeRTOS™,
OPENRTOS®, Micriµm® µC/OS™, and SEGGER embOS®
• Eight channels with automatic data size detection
• Programmable Cyclic Redundancy Check (CRC)
Packages
Type
LFBGA
LQFP
Pin Count
169
288
I/O Pins (up to)
120
120
120
0.8 mm
0.8 mm
0.4 mm
11x11 mm
15x15 mm
20x20 mm
Contact/Lead Pitch
Dimensions
2015-2021 Microchip Technology Inc.
176
DS60001361J-page 1
PIC32MZ Graphics (DA) Family
EBI
PMP
SQI
SDHC
RTCC
Ethernet
I/O Pins
JTAG
Trace
5
GPU
2
GLCD
External Interrupts(2)
6
I2C
CAN 2.0B
6
USB 2.0 HS OTG
SPI/I2S
9/9/9
1:
2:
CTMU
UART
47
Analog Comparators
Timers(1)/Capture/
Compare
160
Note
12-bit ADC Channels
PIC32MZ DA FEATURES COMMON TO ALL DEVICES
Remappable Peripherals
Remappable Pins
45
2
Y
Y
5
Y
Y
Y
Y
Y
Y
Y
Y
120
Y
Y
Eight out of nine timers are remappable.
Four out of five external interrupts are remappable.
PIC32MZ1025DAH169
PIC32MZ1064DAG169
256
1024
640
PIC32MZ1064DAH169
PIC32MZ2025DAG169
PIC32MZ2025DAH169
PIC32MZ2064DAG169
PIC32MZ2064DAH169
256
2048
640
Yes
(INT)
32
Y
8/26
N
8/24
Y
8/26
PIC32MZ2025DAB176
N
8/24
PIC32MZ2064DAA176
Y
8/26
PIC32MZ2064DAB176
N
8/24
PIC32MZ1025DAG176
Y
8/26
PIC32MZ1025DAH176
N
8/24
PIC32MZ1064DAG176
Y
8/26
PIC32MZ1064DAH176
N
8/24
Y
8/26
PIC32MZ2025DAH176
N
8/24
PIC32MZ2064DAG176
Y
8/26
PIC32MZ2064DAH176
HF
6J
No
PIC32MZ2025DAA176
—
256
2048
640
256
1024
640
PIC32MZ2025DAG176
256
Yes
(INT)
32
2048
640
DMA Channels
(Programmable/
Dedicated)
8/24
Y
8/26
N
8/24
Y
8/26
N
8/24
Y
8/26
N
8/24
Y
8/26
N
8/24
Y
8/26
N
8/24
Y
8/26
N
8/24
Y
8/26
N
8/24
Y
8/26
Package
Crypto/RNG
DDR2 SDRAM
Size (MB)
640
2J
Devices
288-PIN LFBGA PIC32MZ DA
FEATURES
PIC32MZ1025DAA288
PIC32MZ1025DAB288
PIC32MZ1064DAA288
1024
PIC32MZ1064DAB288
PIC32MZ2025DAA288
PIC32MZ2025DAB288
PIC32MZ2064DAA288
PIC32MZ2064DAB288
DS60001361J-page 2
DDR2 Controller
Interface (Internal/External)
1024
PIC32MZ1064DAB176
TABLE 4:
Data Memory (KB
Program Memory (KB
Devices
PIC32MZ1064DAA176
Package
8/24
N
2048
25
6
N
8/24
Y
8/26
64
0
N
8/24
25
6
64
0
Yes
(EXT)
Y
8/26
N
8/24
Y
8/26
N
8/24
Y
8/26
Package
PIC32MZ1025DAG169
N
256
DMA Channels
(Programmable/Dedicated)
640
PIC32MZ2064DAB169
PIC32MZ1025DAB176
Crypto/RNG
256
2048
PIC32MZ1025DAA176
8/26
DDR2 Controller
Interface (Internal/External)
PIC32MZ2064DAA169
—
8/24
Y
Data Memory (KB)
No
PIC32MZ2025DAA169
N
Program Memory (KB)
640
PIC32MZ1064DAB169
PIC32MZ2025DAB169
DDR2 Controller
Interface (Internal/External)
1024
176-PIN LQFP PIC32MZ DA
FEATURES
DMA Channels
(Programmable/
Dedicated)
PIC32MZ1064DAA169
256
TABLE 3:
Crypto/RNG
PIC32MZ1025DAA169
PIC32MZ1025DAB169
Data
Memory (KB)
Program Memory (KB)
169-PIN LFBGA PIC32MZ DA
FEATURES
Devices
TABLE 2:
DDR2 SDRAM
Size (MB)
Boot Flash Memory (KB)
TABLE 1:
4J
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
Device Pin Tables
TABLE 5:
PIN NAMES FOR 169-PIN DEVICES
169-PIN LFBGA (BOTTOM VIEW)
PIC32MZ1025DAA169
PIC32MZ1025DAB169
PIC32MZ1064DAA169
PIC32MZ1064DAB169
PIC32MZ2025DAA169
PIC32MZ2025DAB169
PIC32MZ2064DAA169
PIC32MZ2064DAB169
PIC32MZ1025DAG169
PIC32MZ1025DAH169
PIC32MZ1064DAG169
PIC32MZ1064DAH169
PIC32MZ2025DAG169
PIC32MZ2025DAH169
PIC32MZ2064DAG169
PIC32MZ2064DAH169
Ball/Pin
Number
N1
A1
N13
A13
Polarity Indicator
Full Pin Name
Ball/Pin
Number
Full Pin Name
A1
No Connect
C5
EBIA2/AN23/C2INC/RPG9/PMA2/RG9
A2
VBUS
C6
TDO/AN31/RPF12/RF12
A3
RPF2/SDA3/RF2
C7
EBID7/AN15/PMD7/RE7
A4
EBID1/AN39/PMD1/RE1
C8
AVSS
A5
AN21/RG15
C9
VDDCORE
A6
TDI/AN17/SCK5/RF13
C10
VREF+/CVREF+/AN28/RA10
A7
EBIWE/AN34/RPC3/PMWR/RC3
C11
CVREFOUT/AN5/RPB10/RB10
A8
EBID12/AN10/RPC2/PMD12/RC2
C12
PGED1/AN0/RPB0/CTED2/RB0
A9
EBID10/AN4/RPB8/PMD10/RB8
C13
SOSCI/RPC13(6)/RC13(6)
A10
AN8/RPB3/RB3
D1
TRD3/SDDATA3/SQID3/RA7
A11
EBIA5/AN7/PMA5/RA5
D2
TMS/SDCD/RA0
A12
AN2/C1INB/RB4
D3
USBID
A13
AN1/C2INB/RPB2/RB2
D4
AN20/RH4
B1
D-
D5
AN13/C1INC/RPG7/SDA4/RG7
B2
VUSB3V3
D6
AN26/RPE9/RE9
B3
EBID4/AN18/PMD4/RE4
D7
PGEC2/RPB6/RB6
B4
VDDCORE
D8
AVSS
B5
AN30/C2IND/RPG8/SCL4/RG8
D9
AVDD
B6
VDDIO
D10
VBAT
B7
EBID5/AN12/RPC1/PMD5/RC1
D11
AN45/RPB5/RB5
B8
EBIOE/AN19/RPC4/PMRD/RC4
D12
PGED2/C1INA/AN46/RPB7/RB7
B9
PGEC1/AN9/RPB1/CTED1/RB1
D13
SOSCO/RPC14(6)/T1CK/RC14(6)
B10
AN3/C2INA/RPB15/OCFB/RB15
E1
TRD2/SDDATA2/SQID2/RG14
B11
VREF-/CVREF-/AN27/RA9
E2
TRD0/SDDATA0/SQID0/RG13
B12
EBIA7/AN47/HLVDIN/RPB9/PMA7/RB9
E3
TRD1/SDDATA1/SQID1/RG12
B13
AN6/RB12
E4
TRCLK/SDCK/SQICLK/RA6
C1
D+
E5
AN14/C1IND/SCK2/RG6
C2
VSS
E6
AN25/RPE8/RE8
C3
INT0/RH14
E7
AN49/RB11
C4
Note 1:
2:
3:
4:
5:
6:
EBID0/PMD0/RE0
E8
GD20/EBIA22/RJ3
The RPn pins can be used by remappable peripherals. See Table 1 and Table 2 for the available peripherals and 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
This pin must be tied to Vss through a 20k resistor in devices without DDR.
This pin is a No Connect in devices without DDR.
These pins are restricted to input functions only.
2015-2021 Microchip Technology Inc.
DS60001361J-page 3
PIC32MZ Graphics (DA) Family
TABLE 5:
PIN NAMES FOR 169-PIN DEVICES (CONTINUED)
169-PIN LFBGA (BOTTOM VIEW)
PIC32MZ1025DAA169
PIC32MZ1025DAB169
PIC32MZ1064DAA169
PIC32MZ1064DAB169
PIC32MZ2025DAA169
PIC32MZ2025DAB169
PIC32MZ2064DAA169
PIC32MZ2064DAB169
PIC32MZ1025DAG169
PIC32MZ1025DAH169
PIC32MZ1064DAG169
PIC32MZ1064DAH169
PIC32MZ2025DAG169
PIC32MZ2025DAH169
PIC32MZ2064DAG169
PIC32MZ2064DAH169
Ball/Pin
Number
N1
A1
N13
A13
Polarity Indicator
Full Pin Name
Ball/Pin
Number
Full Pin Name
E9
AN22/RPD14/RD14
H2
SCK4/RD10
E10
AN29/SCK3/RB14
H3
RTCC/RPD0/RD0
E11
TCK/AN24/RA1
H4
VSS1V8
E12
OSC1/CLKI/RC12
H5
E13
OSC2/CLKO/RC15
H6
VDDR1V8(4)
VDDR1V8(4)
F1
SDCMD/SQICS0/RPD4/RD4
H7
VSS
F2
SQICS1/RPD5/RD5
H8
VSS
F3
EBIA6/RPE5/PMA6/RE5
H9
VDDIO
F4
DDRVREF(5)
H10
GD13/EBIA18/RK4
F5
VSS
H11
EBIA3/AN11/PMA3/RK2
F6
EBID6/AN16/PMD6/RE6
H12
SDWP/EBIRP/RH2
F7
AN48/CTPLS/RB13
H13
F8
GD18/EBIBS1/RJ10
J1
EBIA0/PMA0/RJ15
GD7/EBIA12/RPD12/PMA12/RD12
F9
GD9/EBIBS0/RJ12
J2
GD22/EBIA13/PMA13/RD13
F10
EBIRDY3/AN32/RJ2
J3
RPF8/SCL3/RF8
F11
AN33/SCK6/RD15
J4
VSS1V8
F12
HSYNC/EBICS1/RJ5
J5
F13
VSYNC/EBICS0/RJ4
J6
VDDR1V8(4)
VDDR1V8(4)
G1
SCK1/RD1
J7
VSS
G2
GD10/EBIA14/RPD2/PMA14/PMCS1/RD2
J8
VSS
G3
GD11/EBIA15/RPD3/PMA15/PMCS2/RD3
J9
VDDIO
G4
VSS1V8
J10
GD14/EBIA19/RK5
G5
VSS
J11
EBIA1/AN38/PMA1/RK1
G6
VSS
J12
EBIA4/AN36/PMA4/RH7
G7
VSS
J13
AN35/RH3
G8
VSS
K1
MCLR
G9
VDDIO
K2
GD16/EBID8/RPF5/SCL5/PMD8/RF5
G10
GD8/EBID11/PMD11/RJ14
K3
GD5/EBIA10/RPF1/PMA10/RF1
G11
GCLK/EBICS2/RJ6
K4
VSS1V8
G12
GD0/EBID13/PMD13/RJ13
K5
G13
GEN/EBICS3/RJ7
K6
VDDR1V8(4)
VDDR1V8(4)
H1
Note
1:
2:
3:
4:
5:
6:
GD2/EBID15/RPD9/PMD15/RD9
K7
Vss
The RPn pins can be used by remappable peripherals. See Table 1 and Table 2 for the available peripherals and 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
This pin must be tied to Vss through a 20k resistor in devices without DDR.
This pin is a No Connect in devices without DDR.
These pins are restricted to input functions only.
DS60001361J-page 4
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 5:
PIN NAMES FOR 169-PIN DEVICES (CONTINUED)
169-PIN LFBGA (BOTTOM VIEW)
PIC32MZ1025DAA169
PIC32MZ1025DAB169
PIC32MZ1064DAA169
PIC32MZ1064DAB169
PIC32MZ2025DAA169
PIC32MZ2025DAB169
PIC32MZ2064DAA169
PIC32MZ2064DAB169
PIC32MZ1025DAG169
PIC32MZ1025DAH169
PIC32MZ1064DAG169
PIC32MZ1064DAH169
PIC32MZ2025DAG169
PIC32MZ2025DAH169
PIC32MZ2064DAG169
PIC32MZ2064DAH169
Ball/Pin
Number
K8
K9
K10
K11
K12
K13
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
M1
M2
M3
M4
Note
N13
A13
Polarity Indicator
Full Pin Name
VSS
VDDIO
EMDIO/RJ1
ETXEN/RPD6/RD6
GD23/EBIA16/RK0
EBIRDY2/AN37/RH11
GD6/EBIA11/RPF0/PMA11/RF0
GD21/EBIA23/RH15
GD17/EBID9/RPF4/SDA5/PMD9/RF4
VSS1V8
VSS1V8
VDDIO
VDDIO
VDDCORE
VDDIO
ETXERR/RJ0
GD1/EBID14/PMD14/RA4
SCL2/RA2
GD12/EBIA17/RK3
ERXERR/RPF3/RF3
GD4/EBIA9/RPG1/PMA9/RG1
EBID3/RPE3/PMD3/RE3
ERXD1/RH5
1:
2:
3:
4:
5:
6:
N1
A1
Ball/Pin
Number
M5
M6
M7
M8
M9
M10
M11
M12
M13
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
Full Pin Name
ERXDV/ECRSDV/RH13
ECOL/RH10
ETXD3/RH1
ETXD2/RH0
ETXD1/RJ9
ETXCLK/RPD7/RD7
RPA14/SCL1/RA14
GD19/EBIA21/RK7
GD15/EBIA20/RK6
VDDCORE
GD3/EBIA8/RPG0/PMA8/RG0
EBID2/PMD2/RE2
ERXD2/RH6
ECRS/RH12
ERXD3/RH9
ERXD0/RH8
ERXCLK/EREFCLK/RJ11
ETXD0/RJ8
EMDC/RPD11/RD11
RPA15/SDA1/RA15
EBIRDY1/SDA2/RA3
No Connect
The RPn pins can be used by remappable peripherals. See Table 1 and Table 2 for the available peripherals and 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
This pin must be tied to Vss through a 20k resistor in devices without DDR.
This pin is a No Connect in devices without DDR.
These pins are restricted to input functions only.
2015-2021 Microchip Technology Inc.
DS60001361J-page 5
PIC32MZ Graphics (DA) Family
TABLE 6:
PIN NAMES FOR 176-PIN DEVICES
176-PIN LQFP (TOP VIEW)
PIC32MZ1025DAA176
PIC32MZ1025DAB176
PIC32MZ1064DAA176
PIC32MZ1064DAB176
PIC32MZ2025DAA176
PIC32MZ2025DAB176
PIC32MZ2064DAA176
PIC32MZ2064DAB176
PIC32MZ1025DAG176
PIC32MZ1025DAH176
PIC32MZ1064DAG176
PIC32MZ1064DAH176
PIC32MZ2025DAG176
PIC32MZ2025DAH176
PIC32MZ2064DAG176
PIC32MZ2064DAH176
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Full Pin Name
VREF-/CVREF-/AN27/RA9
VREF+/CVREF+/AN28/RA10
AVDD
AVDD
AVSS
AVSS
AN3/C2INA/RPB15/OCFB/RB15
AN8/RPB3/RB3
AN48/CTPLS/RB13
EBID10/AN4/RPB8/PMD10/RB8
PGEC1/AN9/RPB1/CTED1/RB1
AN49/RB11
PGEC2/RPB6/RB6
EBID12/AN10/RPC2/PMD12/RC2
EBIWE/AN34/RPC3/PMWR/RC3
EBIOE/AN19/RPC4/PMRD/RC4
EBID5/AN12/RPC1/PMD5/RC1
VDDCORE
VDDIO
No Connect
VSS
VSS
EBID6/AN16/PMD6/RE6
EBID7/AN15/PMD7/RE7
AN25/RPE8/RE8
AN26/RPE9/RE9
TDO/AN31/RPF12/RF12
TDI/AN17/SCK5/RF13
VSS
AN14/C1IND/SCK2/RG6
31
32
33
34
35
36
Note 1:
2:
3:
4:
5:
6:
7:
176
1
Pin
Number
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Full Pin Name
VSS
VDDIO
VDDCORE
EBID0/PMD0/RE0
RPF2/SDA3/RF2
INT0/RH14
EBID4/AN18/PMD4/RE4
No Connect
VBUS
VUSB3V3
VUSB3V3
VSS
VSS
DD+
USBID
TMS/SDCD/RA0
TRCLK/SDCK/SQICLK/RA6
TRD3/SDDATA3/SQID3/RA7
TRD1/SDDATA1/SQID1/RG12
VDDR1V8(5)
VDDR1V8(5)
VDDR1V8(5)
VDDR1V8(5)
VDDR1V8(5)
VDDR1V8(5)
VDDR1V8(5)
TRD0/SDDATA0/SQID0/RG13
TRD2/SDDATA2/SQID2/RG14
DDRVREF(6)
AN13/C1INC/RPG7/SDA4/RG7
67
VDDR1V8(5)
AN30/C2IND/RPG8/SCL4/RG8
68
VDDR1V8(5)
EBIA2/AN23/C2INC/RPG9/PMA2/RG9
69
EBIA6/RPE5/PMA6/RE5
70
SDCMD/SQICS0/RPD4/RD4
AN21/RG15
71
SQICS1/RPD5/RD5
AN20/RH4
EBID1/AN39/PMD1/RE1
72
VDDR1V8(5)
The RPn pins can be used by remappable peripherals. See Table 1 and Table 3 for the available peripherals and 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
The metal plane at the bottom of the device is internally tied to VSS1V8 and should be connected to 1.8V ground externally.
This pin must be tied to Vss through a 20k resistor in devices without DDR.
This pin is a No Connect in devices without DDR.
These pins are restricted to input functions only.
DS60001361J-page 6
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 6:
PIN NAMES FOR 176-PIN DEVICES (CONTINUED)
176-PIN LQFP (TOP VIEW)
PIC32MZ1025DAA176
PIC32MZ1025DAB176
PIC32MZ1064DAA176
PIC32MZ1064DAB176
PIC32MZ2025DAA176
PIC32MZ2025DAB176
PIC32MZ2064DAA176
PIC32MZ2064DAB176
PIC32MZ1025DAG176
PIC32MZ1025DAH176
PIC32MZ1064DAG176
PIC32MZ1064DAH176
PIC32MZ2025DAG176
PIC32MZ2025DAH176
PIC32MZ2064DAG176
PIC32MZ2064DAH176
Pin
Number
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
Note 1:
2:
3:
4:
5:
6:
7:
Full Pin Name
176
Pin
Number
1
Full Pin Name
SCK1/RD1
GD10/EBIA14/RPD2/PMA14/PMCS1/RD2
GD11/EBIA15/RPD3/PMA15/PMCS2/RD3
GD2/EBID15/RPD9/PMD15/RD9
SCK4/RD10
109
ETXD3/RH1
110
ETXD2/RH0
111
ERXCLK/EREFCLK/RJ11
112
ETXD1/RJ9
113
ETXD0/RJ8
114
EMDIO/RJ1
VDDR1V8(5)
RTCC/RPD0/RD0
115
VSS
GD7/EBIA12/RPD12/PMA12/RD12
116
VDDCORE
GD22/EBIA13/PMA13/RD13
117
VDDIO
RPF8/SCL3/RF8
118
ETXERR/RJ0
119
EMDC/RPD11/RD11
VSS
120
ETXCLK/RPD7/RD7
VDDCORE
121
ETXEN/RPD6/RD6
MCLR
122
VSS
VDDIO
VSS
123
VSS
No Connect
124
VDDIO
GD16/EBID8/RPF5/SCL5/PMD8/RF5
125
RPA15/SDA1/RA15
GD5/EBIA10/RPF1/PMA10/RF1
126
RPA14/SCL1/RA14
GD6/EBIA11/RPF0/PMA11/RF0
127
GD1/EBID14/PMD14/RA4
GD21/EBIA23/RH15
128
EBIRDY1/SDA2/RA3
ERXERR/RPF3/RF3
129
SCL2/RA2
VSS
130
GD19/EBIA21/RK7
GD4/EBIA9/RPG1/PMA9/RG1
131
GD15/EBIA20/RK6
GD3/EBIA8/RPG0/PMA8/RG0
132
GD14/EBIA19/RK5
GD17/EBID9/RPF4/SDA5/PMD9/RF4
133
GD13/EBIA18/RK4
EBID3/RPE3/PMD3/RE3
134
GD12/EBIA17/RK3
EBID2/PMD2/RE2
135
EBIA3/AN11/PMA3/RK2
ERXD1/RH5
136
EBIA1/AN38/PMA1/RK1
ERXD2/RH6
137
GD23/EBIA16/RK0
138
EBIRDY2/AN37/RH11
VDDIO
139
EBIA4/AN36/PMA4/RH7
VSS
ERXDV/ECRSDV/RH13
140
AN35/RH3
ECRS/RH12
141
SDWP/EBIRP/RH2
ECOL/RH10
142
EBIA0/PMA0/RJ15
ERXD3/RH9
143
GD8/EBID11/PMD11/RJ14
ERXD0/RH8
144
GD0/EBID13/PMD13/RJ13
The RPn pins can be used by remappable peripherals. See Table 1 and Table 3 for the available peripherals and 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
The metal plane at the bottom of the device is internally tied to VSS1V8 and should be connected to 1.8V ground externally.
This pin must be tied to Vss through a 20k resistor in devices without DDR.
This pin is a No Connect in devices without DDR.
These pins are restricted to input functions only.
2015-2021 Microchip Technology Inc.
DS60001361J-page 7
PIC32MZ Graphics (DA) Family
TABLE 6:
PIN NAMES FOR 176-PIN DEVICES (CONTINUED)
176-PIN LQFP (TOP VIEW)
PIC32MZ1025DAA176
PIC32MZ1025DAB176
PIC32MZ1064DAA176
PIC32MZ1064DAB176
PIC32MZ2025DAA176
PIC32MZ2025DAB176
PIC32MZ2064DAA176
PIC32MZ2064DAB176
PIC32MZ1025DAG176
PIC32MZ1025DAH176
PIC32MZ1064DAG176
PIC32MZ1064DAH176
PIC32MZ2025DAG176
PIC32MZ2025DAH176
PIC32MZ2064DAG176
PIC32MZ2064DAH176
Pin
Number
Full Pin Name
176
Pin
Number
Full Pin Name
SOSCO/RPC14(7)/T1CK/RC14(7)
145
GD9/EBIBS0/RJ12
146
SOSCI/RPC13(7)/RC13(7)
GEN/EBICS3/RJ7
163
OSC2/CLKO/RC15
GCLK/EBICS2/RJ6
164
OSC1/CLKI/RC12
HSYNC/EBICS1/RJ5
165
VDDIO
VSYNC/EBICS0/RJ4
166
VBAT
GD20/EBIA22/RJ3
167
AN45/RPB5/RB5
EBIRDY3/AN32/RJ2
168
AN5/RPB10/RB10
169
PGED1/AN0/RPB0/CTED2/RB0
VSS
170
PGED2/C1INA/AN46/RPB7/RB7
VSS
171
AN6/RB12
VDDIO
172
AN1/C2INB/RPB2/RB2
VDDIO
AN33/SCK6/RD15
173
EBIA7/AN47/HLVDIN/RPB9/PMA7/RB9
AN22/RPD14/RD14
174
EBIA5/AN7/PMA5/RA5
AN29/SCK3/RB14
175
AN2/C1INB/RB4
TCK/AN24/RA1
176
No Connect
The RPn pins can be used by remappable peripherals. See Table 1 and Table 3 for the available peripherals and 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
The metal plane at the bottom of the device is internally tied to VSS1V8 and should be connected to 1.8V ground externally.
This pin must be tied to Vss through a 20k resistor in devices without DDR.
This pin is a No Connect in devices without DDR.
These pins are restricted to input functions only.
GD18/EBIBS1/RJ10
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Note 1:
2:
3:
4:
5:
6:
7:
DS60001361J-page 8
161
1
162
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 7:
PIN NAMES FOR 288-PIN DEVICES
288-PIN LFBGA (BOTTOM VIEW)
V1
A1
PIC32MZ1025DAA288
PIC32MZ1025DAB288
PIC32MZ1064DAA288
PIC32MZ1064DAB288
PIC32MZ2025DAA288
PIC32MZ2025DAB288
PIC32MZ2064DAA288
PIC32MZ2064DAB288
N6
F6
N13
F13
V18
A18
Polarity Indicator
Ball/Pin
Number
Full Pin Name
Ball/Pin
Number
Full Pin Name
A1
No Connect
B17
AN2/C1INB/RB4
A2
DDRUDQS
B18
EBIA5/AN7/PMA5/RA5
A3
DDRDM1
C1
DDRDQ8
A4
D-
C2
DDRDQ15
A5
VSS
C3
DDRDQ9
A6
INT0/RH14
C4
VUSB3V3
A7
RPF2/SDA3/RF2
C5
VBUS
A8
AN21/RG15
C6
USBID
A9
AN14/C1IND/SCK2/RG6
C7
VSS
A10
TDI/AN17/SCK5/RF13
C8
No Connect
A11
TDO/AN31/RPF12/RF12
C9
AN30/C2IND/RPG8/SCL4/RG8
A12
EBID5/AN12/RPC1/PMD5/RC1
C10
AN25/RPE8/RE8
A13
EBIOE/AN19/RPC4/PMRD/RC4
C11
EBID6/AN16/PMD6/RE6
A14
PGEC1/AN9/RPB1/CTED1/RB1
C12
No Connect
A15
EBID10/AN4/RPB8/PMD10/RB8
C13
EBID12/AN10/RPC2/PMD12/RC2
A16
AN8/RPB3/RB3
C14
AN49/RB11
A17
VREF-/CVREF-/AN27/RA9
C15
VREF+/CVREF+/AN28/RA10
A18
No Connect
C16
VDDIO
B1
No Connect
C17
AN1/C2INB/RPB2/RB2
B2
DDRUDQS
C18
AN6/RB12
B3
DDRDQ14
D1
DDRDQ13
B4
D+
D2
DDRDQ10
B5
VSS
D3
VSS1V8
B6
EBID4/AN18/PMD4/RE4
D4
TMS/SDCD/RA0
B7
EBID0/PMD0/RE0
D5
VUSB3V3
B8
AN20/RH4
D6
No Connect
B9
EBIA2/AN23/C2INC/RPG9/PMA2/RG9
D7
VDDCORE
B10
AN26/RPE9/RE9
D8
EBID1/AN39/PMD1/RE1
B11
EBID7/AN15/PMD7/RE7
D9
AN13/C1INC/RPG7/SDA4/RG7
B12
No Connect
D10
VSS
B13
EBIWE/AN34/RPC3/PMWR/RC3
D11
VSS
B14
PGEC2/RPB6/RB6
D12
VSS
B15
AN48/CTPLS/RB13
D13
VSS
B16
AN3/C2INA/RPB15/OCFB/RB15
D14
VDDCORE
The RPn pins can be used by remappable peripherals. See Table 1 and Table 4 for the available peripherals and 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
This pin must be tied to Vss through a 20k resistor when DDR is not connected in the system.
This pin is a No Connect when DDR is not connected in the system.
These pins are restricted to input functions only.
Note
1:
2:
3:
4:
5:
6:
2015-2021 Microchip Technology Inc.
DS60001361J-page 9
PIC32MZ Graphics (DA) Family
TABLE 7:
PIN NAMES FOR 288-PIN DEVICES (CONTINUED)
288-PIN LFBGA (BOTTOM VIEW)
V1
A1
PIC32MZ1025DAA288
PIC32MZ1025DAB288
PIC32MZ1064DAA288
PIC32MZ1064DAB288
PIC32MZ2025DAA288
PIC32MZ2025DAB288
PIC32MZ2064DAA288
PIC32MZ2064DAB288
N6
F6
N13
F13
V18
A18
Polarity Indicator
Ball/Pin
Number
Full Pin Name
Ball/Pin
Number
Full Pin Name
D15
VDDIO
G8
D16
VDDIO
G9
VSS1V8
D17
PGED2/C1INA/AN46/RPB7/RB7
G10
VSS
VDDIO
D18
VSS1V8
PGED1/AN0/RPB0/CTED2/RB0
G11
E1
DDRLDQS
G12
AVSS
E2
DDRLDQS
G13
AVDD
E3
DDRDQ12
G15
VDDIO
E4
TRCLK/SDCK/SQICLK/RA6
G16
No Connect
E15
VDDIO
G17
OSC1/CLKI/RC12
E16
EBIA7/AN47/HLVDIN/RPB9/PMA7/RB9
G18
OSC2/CLKO/RC15
E17
AN45/RPB5/RB5
H1
DDRDQ2
E18
CVREFOUT/AN5/RPB10/RB10
H2
DDRDQ5
F1
DDRDQ0
H3
DDRDQ6
F2
DDRDQ7
H4
TRD0/SDDATA0/SQID0/RG13
F3
DDRDQ11
H6
F4
TRD3/SDDATA3/SQID3/RA7
H7
F6
VSS1V8
H8
VDDR1V8(4)
VDDR1V8(4)
VDDR1V8(4)
F7
VSS1V8
H9
VSS1V8
F8
VSS1V8
VSS
F9
VSS
H10
H11
F10
VSS
H12
VDDIO
F11
VDDIO
H13
VDDIO
F12
AVSS
H15
VDDIO
F13
AVDD
H16
TCK/AN24/RA1
F15
VDDIO
H17
SOSCI/RPC13(6)/RC13(6)
F16
VBAT
H18
SOSCO/RPC14(6)/T1CK/RC14(6)
F17
No Connect
J1
DDRVREF(5)
F18
No Connect
J2
No Connect
G1
DDRDQ3
J3
DDRDQ1
G2
DDRDQ4
J4
TRD2/SDDATA2/SQID2/RG14
G3
DDRDM0
J6
G4
TRD1/SDDATA1/SQID1/RG12
J7
G6
VSS1V8
J8
VDDR1V8(4)
VDDR1V8(4)
VDDR1V8(4)
G7
Note 1:
2:
3:
4:
5:
6:
VDDIO
J9
VSS1V8
VSS1V8
The RPn pins can be used by remappable peripherals. See Table 1 and Table 4 for the available peripherals and 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
This pin must be tied to Vss through a 20k resistor when DDR is not connected in the system.
This pin is a No Connect when DDR is not connected in the system.
These pins are restricted to input functions only.
DS60001361J-page 10
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 7:
PIN NAMES FOR 288-PIN DEVICES (CONTINUED)
288-PIN LFBGA (BOTTOM VIEW)
V1
A1
PIC32MZ1025DAA288
PIC32MZ1025DAB288
PIC32MZ1064DAA288
PIC32MZ1064DAB288
PIC32MZ2025DAA288
PIC32MZ2025DAB288
PIC32MZ2064DAA288
PIC32MZ2064DAB288
N6
F6
N13
F13
V18
A18
Polarity Indicator
Ball/Pin
Number
Full Pin Name
Ball/Pin
Number
Full Pin Name
J10
VDDIO
L12
VDDIO
J11
VSS
L13
VSS
J12
VSS
L15
VSS
J13
VSS
L16
GEN/EBICS3/RJ7
J15
VDDIO
L17
GCLK/EBICS2/RJ6
J16
AN33/SCK6/RD15
L18
HSYNC/EBICS1/RJ5
J17
AN29/SCK3/RB14
M1
DDRRAS
J18
AN22/RPD14/RD14
M2
DDRBA0
K1
DDRCK
M3
DDRBA1
K2
DDRCK
M4
SCK1/RD1
K3
EBIA6/RPE5/PMA6/RE5
M6
VSS1V8
K4
SDCMD/SQICS0/RPD4/RD4
M7
VSS1V8
K6
VDDR1V8(4)
VDDR1V8(4)
VDDR1V8(4)
M8
VSS1V8
K7
K8
M9
VSS1V8
M10
VSS
K9
VSS1V8
M11
VSS
K10
VDDIO
M12
VDDIO
K11
VSS
M13
VDDIO
K12
VSS
M15
VDDIO
K13
VSS
M16
GD0/EBID13/PMD13/RJ13
K15
VSS
M17
GD9/EBIBS0/RJ12
K16
EBIRDY3/AN32/RJ2
M18
K17
GD20/EBIA22/RJ3
N1
DDRODT
K18
GD18/EBIBS1/RJ10
VSYNC/EBICS0/RJ4
N2
DDRCS0
L1
DDRWE
N3
DDRA2
L2
DDRCKE
N4
GD22/EBIA13/PMA13/RD13
L3
DDRA1
N6
VSS1V8
L4
SQICS1/RPD5/RD5
N7
VSS1V8
L6
VDDR1V8(4)
VDDR1V8(4)
VDDR1V8(4)
N8
VSS1V8
L7
L8
N9
VSS1V8
N10
VSS
L9
VSS1V8
N11
VSS
L10
VSS
N12
VDDIO
L11
Note 1:
2:
3:
4:
5:
6:
VDDIO
N13
VDDIO
The RPn pins can be used by remappable peripherals. See Table 1 and Table 4 for the available peripherals and 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
This pin must be tied to Vss through a 20k resistor when DDR is not connected in the system.
This pin is a No Connect when DDR is not connected in the system.
These pins are restricted to input functions only.
2015-2021 Microchip Technology Inc.
DS60001361J-page 11
PIC32MZ Graphics (DA) Family
TABLE 7:
PIN NAMES FOR 288-PIN DEVICES (CONTINUED)
288-PIN LFBGA (BOTTOM VIEW)
V1
A1
PIC32MZ1025DAA288
PIC32MZ1025DAB288
PIC32MZ1064DAA288
PIC32MZ1064DAB288
PIC32MZ2025DAA288
PIC32MZ2025DAB288
PIC32MZ2064DAA288
PIC32MZ2064DAB288
N6
F6
N13
F13
V18
A18
Polarity Indicator
Ball/Pin
Number
Full Pin Name
Ball/Pin
Number
Full Pin Name
N15
EBIA4/AN36/PMA4/RH7
T5
No Connect
N16
SDWP/EBIRP/RH2
T6
GD11/EBIA15/RPD3/PMA15/PMCS2/RD3
N17
EBIA0/PMA0/RJ15
T7
GD16/EBID8/RPF5/SCL5/PMD8/RF5
N18
GD8/EBID11/PMD11/RJ14
T8
GD4/EBIA9/RPG1/PMA9/RG1
P1
DDRA10
T9
EBID3/RPE3/PMD3/RE3
P2
DDRCAS
T10
ERXD2/RH6
P3
DDRA4
T11
ECOL/RH10
P4
RPF8/SCL3/RF8
T12
ETXD3/RH1
P15
GD13/EBIA18/RK4
T13
ETXD1/RJ9
P16
GD23/EBIA16/RK0
T14
No Connect
P17
EBIRDY2/AN37/RH11
T15
ETXCLK/RPD7/RD7
P18
AN35/RH3
T16
RPA14/SCL1/RA14
R1
DDRA0
T17
GD19/EBIA21/RK7
R2
DDRA3
T18
GD15/EBIA20/RK6
R3
DDRA9
U1
DDRA6
R4
VSS1V8
U2
DDRA8
R5
MCLR
U3
DDRA13
R6
GD10/EBIA14/RPD2/PMA14/PMCS1/RD2
U4
DDRBA2
R7
VSS
U5
GD7/EBIA12/RPD12/PMA12/RD12
R8
VSS
U6
GD2/EBID15/RPD9/PMD15/RD9
R9
VDDIO
U7
GD5/EBIA10/RPF1/PMA10/RF1
R10
VDDIO
U8
ERXERR/RPF3/RF3
R11
VDDCORE
U9
GD17/EBID9/RPF4/SDA5/PMD9/RF4
R12
VDDIO
U10
ERXD1/RH5
R13
VDDIO
U11
ECRS/RH12
R14
VDDIO
U12
ERXD0/RH8
R15
GD14/EBIA19/RK5
U13
ERXCLK/EREFCLK/RJ11
R16
GD12/EBIA17/RK3
U14
EMDIO/RJ1
R17
EBIA3/AN11/PMA3/RK2
U15
EMDC/RPD11/RD11
RPA15/SDA1/RA15
EBIA1/AN38/PMA1/RK1
U16
T1
DDRA5
U17
EBIRDY1/SDA2/RA3
T2
T3
DDRA7
DDRA12
U18
SCL2/RA2
V1
No Connect
T4
DDRA14
V2
DDRA11
R18
Note
1:
2:
3:
4:
5:
6:
The RPn pins can be used by remappable peripherals. See Table 1 and Table 4 for the available peripherals and 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
This pin must be tied to Vss through a 20k resistor when DDR is not connected in the system.
This pin is a No Connect when DDR is not connected in the system.
These pins are restricted to input functions only.
DS60001361J-page 12
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 7:
PIN NAMES FOR 288-PIN DEVICES (CONTINUED)
288-PIN LFBGA (BOTTOM VIEW)
V1
A1
PIC32MZ1025DAA288
PIC32MZ1025DAB288
PIC32MZ1064DAA288
PIC32MZ1064DAB288
PIC32MZ2025DAA288
PIC32MZ2025DAB288
PIC32MZ2064DAA288
PIC32MZ2064DAB288
N6
F6
N13
F13
V18
A18
Polarity Indicator
Ball/Pin
Number
V3
V4
V5
V6
V7
V8
V9
V10
Note 1:
2:
3:
4:
5:
6:
Full Pin Name
Ball/Pin
Number
Full Pin Name
DDRA15
V11
ERXDV/ECRSDV/RH13
V12
ERXD3/RH9
VDDCORE
RTCC/RPD0/RD0
V13
ETXD2/RH0
SCK4/RD10
V14
ETXD0/RJ8
GD6/EBIA11/RPF0/PMA11/RF0
V15
ETXERR/RJ0
GD21/EBIA23/RH15
V16
ETXEN/RPD6/RD6
GD3/EBIA8/RPG0/PMA8/RG0
V17
GD1/EBID14/PMD14/RA4
EBID2/PMD2/RE2
V18
No Connect
The RPn pins can be used by remappable peripherals. See Table 1 and Table 4 for the available peripherals and 12.4 “Peripheral Pin
Select (PPS)” for restrictions.
Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See 12.0 “I/O Ports” for more information.
Shaded pins are 5V tolerant.
This pin must be tied to Vss through a 20k resistor when DDR is not connected in the system.
This pin is a No Connect when DDR is not connected in the system.
These pins are restricted to input functions only.
2015-2021 Microchip Technology Inc.
DS60001361J-page 13
PIC32MZ Graphics (DA) Family
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 17
2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 39
3.0 CPU............................................................................................................................................................................................ 51
4.0 Memory Organization ................................................................................................................................................................. 61
5.0 Flash Program Memory ............................................................................................................................................................ 111
6.0 Resets ...................................................................................................................................................................................... 121
7.0 CPU Exceptions and Interrupt Controller ................................................................................................................................. 129
8.0 Oscillator Configuration ............................................................................................................................................................ 163
9.0 Prefetch Module ....................................................................................................................................................................... 181
10.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 185
11.0 Hi-Speed USB with On-The-Go (OTG) .................................................................................................................................... 209
12.0 I/O Ports ................................................................................................................................................................................... 259
13.0 Timer1 ...................................................................................................................................................................................... 287
14.0 Timer2/3, Timer4/5, Timer6/7, and Timer8/9............................................................................................................................ 291
15.0 Input Capture............................................................................................................................................................................ 297
16.0 Output Compare....................................................................................................................................................................... 301
17.0 Deadman Timer (DMT) ............................................................................................................................................................ 307
18.0 Watchdog Timer (WDT) ........................................................................................................................................................... 315
19.0 Deep Sleep Watchdog Timer (DSWDT)................................................................................................................................... 319
20.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 321
21.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I2S) ....................................................................................................... 331
22.0 Serial Quad Interface (SQI) ...................................................................................................................................................... 341
23.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 369
24.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 377
25.0 Parallel Master Port (PMP)....................................................................................................................................................... 385
26.0 External Bus Interface (EBI) ..................................................................................................................................................... 399
27.0 Crypto Engine........................................................................................................................................................................... 407
28.0 Random Number Generator (RNG) ......................................................................................................................................... 429
29.0 12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC)......................................... 435
30.0 Controller Area Network (CAN) ................................................................................................................................................ 493
31.0 Ethernet Controller ................................................................................................................................................................... 531
32.0 Comparator .............................................................................................................................................................................. 575
33.0 Comparator Voltage Reference (CVREF).................................................................................................................................. 579
34.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 583
35.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 587
36.0 Graphics LCD (GLCD) Controller ............................................................................................................................................. 593
37.0 2-D Graphics Processing Unit (GPU) ....................................................................................................................................... 613
38.0 DDR2 SDRAM Controller ......................................................................................................................................................... 615
39.0 Secure Digital Host Controller (SDHC) .................................................................................................................................... 655
40.0 Power-Saving Features ........................................................................................................................................................... 683
41.0 Special Features ...................................................................................................................................................................... 697
42.0 Instruction Set .......................................................................................................................................................................... 727
43.0 Development Support............................................................................................................................................................... 729
44.0 Electrical Characteristics .......................................................................................................................................................... 733
45.0 AC and DC Characteristics Graphs.......................................................................................................................................... 793
46.0 Packaging Information.............................................................................................................................................................. 795
Index ................................................................................................................................................................................................. 821
DS60001361J-page 14
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
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2015-2021 Microchip Technology Inc.
DS60001361J-page 15
PIC32MZ Graphics (DA) Family
Referenced Sources
This device data sheet is based on the following
individual sections of the “PIC32 Family Reference
Manual”. These documents should be considered as
the general reference for the operation of a particular
module or device feature.
Note:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
To access the following documents, refer
to the Documentation > Reference
Manuals section of the Microchip PIC32
website: http://www.microchip.com/pic32.
Section 1. “Introduction” (DS60001127)
Section 7. “Resets” (DS60001118)
Section 8. “Interrupt Controller” (DS60001108)
Section 9. “Watchdog, Deadman, and Power-up Timers” (DS60001114)
Section 10. “Power-Saving Features” (DS60001130)
Section 12. “I/O Ports” (DS60001120)
Section 13. “Parallel Master Port (PMP)” (DS60001128)
Section 14. “Timers” (DS60001105)
Section 15. “Input Capture” (DS60001122)
Section 16. “Output Compare” (DS60001111)
Section 19. “Comparator” (DS60001110)
Section 20. “Comparator Voltage Reference (CVREF)” (DS60001109)
Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107)
Section 22. “12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter
(ADC)” (DS60001344)
Section 23. “Serial Peripheral Interface (SPI)” (DS60001106)
Section 24. “Inter-Integrated Circuit (I2C)” (DS60001116)
Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125)
Section 31. “Direct Memory Access (DMA) Controller” (DS60001117)
Section 32. “Configuration” (DS60001124)
Section 33. “Programming and Diagnostics” (DS60001129)
Section 34. “Controller Area Network (CAN)” (DS60001154)
Section 35. “Ethernet Controller” (DS60001155)
Section 37. “Charge Time Measurement Unit (CTMU)” (DS60001167)
Section 38. “High/Low Voltage Detect (HLVD) (DS60001408)
Section 41. “Prefetch Module for Devices with L1 CPU Cache” (DS60001183)
Section 42. “Oscillators with Enhanced PLL” (DS60001250)
Section 46. “Serial Quad Interface (SQI)” (DS60001244)
Section 47. “External Bus Interface (EBI)” (DS60001245)
Section 48. “Memory Organization and Permissions” (DS60001214)
Section 49. “Crypto Engine (CE) and Random Number Generator (RNG)” (DS60001246)
Section 50. “CPU for Devices with MIPS32® microAptiv™ and M-Class Cores” (DS60001192)
Section 51. “High-Speed USB with On-The-Go (OTG)” (DS60001326)
Section 52. “Flash Program Memory with Support for Live Update” (DS60001193)
Section 54. “Graphics LCD (GLCD) Controller” (DS60001379)
Section 55. “DDR SDRAM Controller” (DS60001321)
Section 57. “Secure Digital Host Controller (SDHC)” (DS60001334)
DS60001361J-page 16
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
1.0
DEVICE OVERVIEW
Note:
This data sheet contains device-specific information for
the PIC32MZ DA family of devices.
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the documents listed in the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
FIGURE 1-1:
Figure 1-1 illustrates a general block diagram of the
core and peripheral modules in the PIC32MZ DA family
of devices.
Table 1-1 through Table 1-24 list the pinout I/O
descriptions for the pins shown in the device pin tables
(see Table 5 through Table 7).
PIC32MZ DA FAMILY BLOCK DIAGRAM
OSC2/CLKO
OSC1/CLKI
POSC/SOSC
Oscillators
SOSC
SOSC
Oscillator
FRC
Oscillator
VBAT
Power
Switch
SPLL
UPLL
MPLL
VDDIO
INT0
Voltage
Regulator
Precision
Band Gap
Reference
DIVIDERS
DSWDT
Timing
Generation
Power-on
Reset
SYSCLK
6
MCLR
Oscillator
Start-up Timer
USBCLK
LPRC
Oscillator
VDDIOV
, SS
Power-up
Timer
PORTA
Brown-out
Reset
PBCLKx
PORTB
PORTC
Deep Sleep
PORTD
RTCC
EVIC
Deep Sleep
PORTG
PORTH
SDHC
I1
I3
I2
CAN1
CAN2
EBI
SQI
T11 I4 T10 T23
I11 T12 I9
T22
I8
PORTJ
Ethernet
Controller
Peripheral
Bridge 6
System Bus
HS USB
I-Cache D-Cache
CRYPTO
microAptiv™ Core
T19
PORTF
INT
MIPS32®
DMAC
EJTAG
PORTE
DSCTRL
I7
I5
PORTK
Peripheral
Bridge 5
I6
Peripheral
Bridge 4
T9
T8
T6
T7
I14
System Bus
T15,
T16,
T20,
T21
T18 I13
GPU
DDR2
Controller
I12 T14
LCD
Controller
T13
RNG
T3
SRAM2
T2
SRAM1
CFG
Flash
Prefetch
Cache
Peripheral Bridge 1
T1
I10
Flash
Controller
T5
Peripheral
Bridge 2
Peripheral
Bridge 3
Timer1-9
PPS
128
128
CVREF
WDT
DMT
HLVD
Note:
PFM Flash
Wrapper
140-bit Wide
Dual Panel
Flash Memory
I12
T17
I13
OC1-9
SPI1-6
IC1-9
I2C1-5
Comparator
1-2
UART1-6
6 S&H
12-bit ADC
PMP
CTMU
Not all features are available on all devices. Refer to Table 1 through Table 4 for the list of features by device.
2015-2021 Microchip Technology Inc.
DS60001361J-page 17
PIC32MZ Graphics (DA) Family
TABLE 1-1:
Pin
Name
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AN39
AN45
AN46
AN47
AN48
AN49
Legend:
ADC PINOUT I/O DESCRIPTIONS
Pin Number
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
Pin
Type
Buffer
Type
Description
Analog-to-Digital Converter
169
I
Analog
Analog Input Channels
C12
D18
172
I
Analog
A13
C17
175
I
Analog
A12
B17
7
I
Analog
B10
B16
10
I
Analog
A9
A15
168
I
Analog
C11
E18
171
I
Analog
B13
C18
174
I
Analog
A11
B18
8
I
Analog
A10
A16
11
I
Analog
B9
A14
14
I
Analog
A8
C13
135
I
Analog
H11
R17
17
I
Analog
B7
A12
31
I
Analog
D5
D9
30
I
Analog
E5
A9
24
I
Analog
C7
B11
23
I
Analog
F6
C11
28
I
Analog
A6
A10
43
I
Analog
B3
B6
16
I
Analog
B8
A13
35
I
Analog
D4
B8
34
I
Analog
A5
A8
158
I
Analog
E9
J18
33
I
Analog
C5
B9
160
I
Analog
E11
H16
25
I
Analog
E6
C10
26
I
Analog
D6
B10
1
I
Analog
B11
A17
2
I
Analog
C10
C15
159
I
Analog
E10
J17
32
I
Analog
B5
C9
27
I
Analog
C6
A11
152
I
Analog
F10
K16
157
I
Analog
F11
J16
15
I
Analog
A7
B13
140
I
Analog
J13
P18
139
I
Analog
J12
N15
138
I
Analog
K13
P17
136
I
Analog
J11
R18
36
I
Analog
A4
D8
167
I
Analog
D11
E17
170
I
Analog
D12
D17
173
I
Analog
B12
E16
9
I
Analog
F7
B15
12
I
Analog
E7
C14
CMOS = CMOS-compatible input or output
Analog = Analog input
ST = Schmitt Trigger input with CMOS levels
O = Output
TTL = Transistor-transistor Logic input buffer
PPS = Peripheral Pin Select
DS60001361J-page 18
P = Power
I = Input
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 1-2:
OSCILLATOR PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
169-pin 176-pin 288-pin
LFBGA LQFP LFBGA
Pin
Type
Buffer
Type
Description
Oscillators
CLKI
E12
164
G17
I
CLKO
E13
163
G18
O
OSC1
E12
164
G17
I
OSC2
E13
163
G18
O
ST/CMOS External clock source input. Always associated with OSC1 pin
function.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKO in RC and
EC modes. Always associated with OSC2 pin function.
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode;
CMOS otherwise.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKO in RC and
EC modes.
SOSCI
C13
162
H17
I
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
SOSCO
D13
161
H18
O
ST/CMOS 32.768 low-power oscillator crystal output. In external clock mode,
SOSCO is the input. The secondary oscillator must be disabled in
order to use the SOSCO as an input.
REFCLKI1
PPS
PPS
PPS
I
—
REFCLKI3
PPS
PPS
PPS
I
—
REFCLKI4
PPS
PPS
PPS
I
—
REFCLKO1
PPS
PPS
PPS
O
—
REFCLKO3
PPS
PPS
PPS
O
—
PPS
PPS
PPS
O
—
REFCLKO4
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-3:
Reference Clock Generator Outputs 1-4
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
IC1 THROUGH IC9 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
Reference Clock Generator Inputs 1-4
169-pin 176-pin 288-pin
LFBGA LQFP LFBGA
Pin
Type
Buffer
Type
Description
Input Capture
IC1
PPS
PPS
PPS
I
ST
IC2
PPS
PPS
PPS
I
ST
IC3
PPS
PPS
PPS
I
ST
IC4
PPS
PPS
PPS
I
ST
IC5
PPS
PPS
PPS
I
ST
IC6
PPS
PPS
PPS
I
ST
IC7
PPS
PPS
PPS
I
ST
IC8
PPS
PPS
PPS
I
ST
IC9
Legend:
PPS
PPS
PPS
I
ST
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2021 Microchip Technology Inc.
Input Capture Inputs 1-9
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001361J-page 19
PIC32MZ Graphics (DA) Family
TABLE 1-4:
Pin
Name
OC1 THROUGH OC9 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
OC1
PPS
PPS
PPS
O
—
OC2
PPS
PPS
PPS
O
—
OC3
PPS
PPS
PPS
O
—
OC4
PPS
PPS
PPS
O
—
OC5
PPS
PPS
PPS
O
—
OC6
PPS
PPS
PPS
O
—
OC7
PPS
PPS
PPS
O
—
OC8
PPS
PPS
PPS
O
—
OC9
PPS
PPS
PPS
O
—
OCFA
PPS
PPS
PPS
I
ST
OCFB
PPS
PPS
PPS
I
ST
Description
Output Compare
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-5:
Pin
Name
Output Compare Outputs 1-9
Output Compare Fault A Input
Output Compare Fault B Input
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
EXTERNAL INTERRUPTS PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
Description
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
INT0
C3
42
A6
I
ST
External Interrupt 0
INT1
PPS
PPS
PPS
I
ST
External Interrupt 1
INT2
PPS
PPS
PPS
I
ST
External Interrupt 2
INT3
PPS
PPS
PPS
I
ST
External Interrupt 3
INT4
PPS
PPS
PPS
I
ST
External Interrupts
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001361J-page 20
External Interrupt 4
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 1-6:
Pin
Name
PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
D4
H16
U18
U17
V17
B18
E4
F4
A17
C15
T16
U16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
D18
A14
C17
A16
B17
E17
B14
D17
A15
E16
E18
C14
C18
B15
J17
B16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA9
RA10
RA14
RA15
D2
E11
L12
N12
L11
A11
E4
D1
B11
C10
M11
N11
53
160
129
128
127
174
54
55
1
2
126
125
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RB8
RB9
RB10
RB11
RB12
RB13
RB14
RB15
C12
B9
A13
A10
A12
D11
D7
D12
A9
B12
C11
E7
B13
F7
E10
B10
169
11
172
8
175
167
13
170
10
173
168
12
171
9
159
7
RC1
RC2
RC3
RC4
RC12
RC13
RC14
RC15
Legend:
B7
17
A12
I/O
ST
A8
14
C13
I/O
ST
A7
15
B13
I/O
ST
B8
16
A13
I/O
ST
E12
164
G17
I/O
ST
C13
162
H17
I
ST
D13
161
H18
I
ST
E13
163
G18
I/O
ST
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2021 Microchip Technology Inc.
Description
PORTA
PORTA is a bidirectional I/O port
PORTB
PORTB is a bidirectional I/O port
PORTC
PORTC is a bidirectional I/O port
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001361J-page 21
PIC32MZ Graphics (DA) Family
TABLE 1-6:
Pin
Name
PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
V5
M4
R6
T6
K4
L4
V16
T15
U6
V6
U15
U5
N4
J18
J16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
B7
D8
V10
T9
B6
K3
C11
B11
C10
B10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RD9
RD10
RD11
RD12
RD13
RD14
RD15
H3
G1
G2
G3
F1
F2
K11
M10
H1
H2
N10
J1
J2
E9
F11
79
73
74
75
70
71
121
120
76
77
119
80
81
158
157
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
RE8
RE9
C4
A4
N3
M3
B3
F3
F6
C7
E6
D6
40
36
99
98
43
69
23
24
25
26
RF0
RF1
RF2
RF3
RF4
RF5
RF8
RF12
RF13
Legend:
L1
91
V7
I/O
ST
K3
90
U7
I/O
ST
A3
41
A7
I/O
ST
M1
93
U8
I/O
ST
L3
97
U9
I/O
ST
K2
89
T7
I/O
ST
J3
82
P4
I/O
ST
C6
27
A11
I/O
ST
A6
28
A10
I/O
ST
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001361J-page 22
Description
PORTD
PORTD is a bidirectional I/O port
PORTE
PORTE is a bidirectional I/O port
PORTF
PORTF is a bidirectional I/O port
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 1-6:
Pin
Name
PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
V9
T8
A9
D9
C9
B9
G4
H4
J4
A8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
V13
T12
N16
P18
B8
U10
T10
N15
U12
V12
T11
P17
U11
V11
A6
V8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
RG0
RG1
RG6
RG7
RG8
RG9
RG12
RG13
RG14
RG15
N2
M2
E5
D5
B5
C5
E3
E2
E1
A5
96
95
30
31
32
33
56
64
65
34
RH0
RH1
RH2
RH3
RH4
RH5
RH6
RH7
RH8
RH9
RH10
RH11
RH12
RH13
RH14
RH15
M8
M7
H12
J13
D4
M4
N4
J12
N7
N6
M6
K13
N5
M5
C3
L2
110
109
141
140
35
100
101
139
108
107
106
138
105
104
42
92
RJ0
RJ1
RJ2
RJ3
RJ4
RJ5
RJ6
RJ7
RJ8
RJ9
RJ10
RJ11
RJ12
RJ13
RJ14
RJ15
Legend:
L10
118
V15
I/O
ST
K10
114
U14
I/O
ST
F10
152
K16
I/O
ST
E8
151
K17
I/O
ST
F13
150
K18
I/O
ST
F12
149
L18
I/O
ST
G11
148
L17
I/O
ST
G13
147
L16
I/O
ST
N9
113
V14
I/O
ST
M9
112
T13
I/O
ST
F8
146
M18
I/O
ST
N8
111
U13
I/O
ST
F9
145
M17
I/O
ST
G12
144
M16
I/O
ST
G10
143
N18
I/O
ST
H13
142
N17
I/O
ST
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2021 Microchip Technology Inc.
Description
PORTG
PORTG is a bidirectional I/O port
PORTH
PORTH is a bidirectional I/O port
PORTJ
PORTJ is a bidirectional I/O port
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001361J-page 23
PIC32MZ Graphics (DA) Family
TABLE 1-6:
Pin
Name
RK0
RK1
RK2
RK3
RK4
RK5
RK6
RK7
Legend:
PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
Buffer
Type
K12
137
P16
I/O
ST
J11
136
R18
I/O
ST
H11
135
R17
I/O
ST
L13
134
R16
I/O
ST
H10
133
P15
I/O
ST
J10
132
R15
I/O
ST
M13
131
T18
I/O
ST
M12
130
T17
I/O
ST
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-7:
Description
PORTK
PORTK is a bidirectional I/O port
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
TIMER1 THROUGH TIMER9 AND RTCC PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
Pin
Type
Pin
Type
Buffer
Type
Description
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
T1CK
D13
161
H18
I
ST
Timer1 External Clock Input
T2CK
PPS
PPS
PPS
I
ST
Timer2 External Clock Input
T3CK
PPS
PPS
PPS
I
ST
Timer3 External Clock Input
T4CK
PPS
PPS
PPS
I
ST
Timer4 External Clock Input
T5CK
PPS
PPS
PPS
I
ST
Timer5 External Clock Input
T6CK
PPS
PPS
PPS
I
ST
Timer6 External Clock Input
T7CK
PPS
PPS
PPS
I
ST
Timer7 External Clock Input
T8CK
PPS
PPS
PPS
I
ST
Timer8 External Clock Input
T9CK
PPS
PPS
PPS
I
ST
Timer9 External Clock Input
Timer1 through Timer9
Real-Time Clock and Calendar
RTCC(1)
H3
79
V5
O
—
Real-Time Clock Alarm/Seconds Output
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
Note 1:
RTCC pin function in not available during VBAT operation.
DS60001361J-page 24
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 1-8:
Pin
Name
UART1 THROUGH UART6 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
Description
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
U1RX
PPS
PPS
PPS
I
ST
UART1 Receive
U1TX
PPS
PPS
PPS
O
—
UART1 Transmit
U1CTS
PPS
PPS
PPS
I
ST
UART1 Clear to Send
U1RTS
PPS
PPS
PPS
O
—
UART1 Ready to Send
Universal Asynchronous Receiver Transmitter 1
Universal Asynchronous Receiver Transmitter 2
U2RX
PPS
PPS
PPS
I
ST
UART2 Receive
U2TX
PPS
PPS
PPS
O
—
UART2 Transmit
U2CTS
PPS
PPS
PPS
I
ST
UART2 Clear To Send
U2RTS
PPS
PPS
PPS
O
—
UART2 Ready To Send
Universal Asynchronous Receiver Transmitter 3
U3RX
PPS
PPS
PPS
I
U3TX
PPS
U3CTS
PPS
U3RTS
PPS
ST
UART3 Receive
PPS
PPS
O
—
UART3 Transmit
PPS
PPS
I
ST
UART3 Clear to Send
PPS
PPS
O
—
UART3 Ready to Send
Universal Asynchronous Receiver Transmitter 4
U4RX
PPS
PPS
PPS
I
ST
UART4 Receive
U4TX
PPS
PPS
PPS
O
—
UART4 Transmit
U4CTS
PPS
PPS
PPS
I
ST
UART4 Clear to Send
U4RTS
PPS
PPS
PPS
O
—
UART4 Ready to Send
U5RX
PPS
PPS
PPS
I
ST
UART5 Receive
U5TX
PPS
PPS
PPS
O
—
UART5 Transmit
U5CTS
PPS
PPS
PPS
I
ST
UART5 Clear to Send
U5RTS
PPS
PPS
PPS
O
—
UART5 Ready to Send
Universal Asynchronous Receiver Transmitter 5
Universal Asynchronous Receiver Transmitter 6
U6RX
PPS
PPS
PPS
I
ST
UART6 Receive
U6TX
PPS
PPS
PPS
O
—
UART6 Transmit
U6CTS
PPS
PPS
PPS
I
ST
UART6 Clear to Send
U6RTS
PPS
PPS
PPS
O
—
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2021 Microchip Technology Inc.
UART6 Ready to Send
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001361J-page 25
PIC32MZ Graphics (DA) Family
TABLE 1-9:
SPI1 THROUGH SPI 6 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
Pin
Type
Buffer
Type
Description
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
SCK1
G1
73
M4
I/O
ST
SPI1 Synchronous Serial Clock Input/Output
SDI1
PPS
PPS
PPS
I
ST
SPI1 Data In
SDO1
PPS
PPS
PPS
O
—
SPI1 Data Out
SS1
PPS
PPS
PPS
I/O
ST
SPI1 Select Or Frame Pulse I/O
Serial Peripheral Interface 1
Serial Peripheral Interface 2
SCK2
E5
30
A9
I/O
ST
SPI2 Synchronous Serial Clock Input/output
SDI2
PPS
PPS
PPS
I
ST
SPI2 Data In
SDO2
PPS
PPS
PPS
O
—
SPI2 Data Out
SS2
PPS
PPS
PPS
I/O
ST
SPI2 Select Or Frame Pulse I/O
Serial Peripheral Interface 3
SCK3
E10
159
J17
I/O
ST
SPI3 Synchronous Serial Clock Input/Output
SDI3
PPS
PPS
PPS
I
ST
SPI3 Data In
SDO3
PPS
PPS
PPS
O
—
SPI3 Data Out
SS3
PPS
PPS
PPS
I/O
ST
SPI3 Select Or Frame Pulse I/O
Serial Peripheral Interface 4
SCK4
H2
77
V6
I/O
ST
SDI4
PPS
PPS
PPS
I
ST
SPI4 Synchronous Serial Clock Input/Output
SPI4 Data In
SDO4
PPS
PPS
PPS
O
—
SPI4 Data Out
SS4
PPS
PPS
PPS
I/O
ST
SPI4 Select Or Frame Pulse I/O
SCK5
A6
28
A10
I/O
ST
SDI5
PPS
PPS
PPS
I
ST
SPI5 Data In
SDO5
PPS
PPS
PPS
O
—
SPI5 Data Out
SS5
PPS
PPS
PPS
I/O
ST
SPI5 Select Or Frame Pulse I/O
Serial Peripheral Interface 5
SPI5 Synchronous Serial Clock Input/Output
Serial Peripheral Interface 6
SCK6
F11
157
J16
I/O
ST
SPI6 Synchronous Serial Clock Input/Output
SDI6
PPS
PPS
PPS
I
ST
SPI6 Data In
SDO6
PPS
PPS
PPS
O
—
SPI6 Data Out
SS6
PPS
PPS
PPS
I/O
ST
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001361J-page 26
SPI6 Select Or Frame Pulse I/O
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 1-10:
I2C1 THROUGH I2C5 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
Pin
Type
Buffer
Type
Description
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
SCL1
M11
126
T16
I/O
ST
I2C1 Synchronous Serial Clock Input/Output
SDA1
N11
125
U16
I/O
ST
I2C1 Synchronous Serial Data Input/Output
SCL2
L12
129
U18
I/O
ST
I2C2 Synchronous Serial Clock Input/Output
SDA2
N12
128
U17
I/O
ST
I2C2 Synchronous Serial Data Input/Output
SCL3
J3
82
P4
I/O
ST
I2C3 Synchronous Serial Clock Input/Output
SDA3
A3
41
A7
I/O
ST
I2C3 Synchronous Serial Data Input/Output
SCL4
B5
32
C9
I/O
ST
I2C4 Synchronous Serial Clock Input/Output
SDA4
D5
31
D9
I/O
ST
I2C4 Synchronous Serial Data Input/Output
SCL5
K2
89
T7
I/O
Inter-Integrated Circuit 1
Inter-Integrated Circuit 2
Inter-Integrated Circuit 3
Inter-Integrated Circuit 4
Inter-Integrated Circuit 5
SDA5
Legend:
L3
97
I/O
U9
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-11:
I2C5 Synchronous Serial Clock Input/Output
ST
I2C5 Synchronous Serial Data Input/Output
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
COMPARATOR 1, COMPARATOR 2 AND CVREF PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
ST
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
Pin
Type
Buffer
Type
Description
Comparator Voltage Reference
CVREF+
C10
CVREF-
B11
CVREFOUT
C11
C15
I
Analog
Comparator Voltage Reference (High) Input
1
A17
I
Analog
Comparator Voltage Reference (Low) Input
168
E18
O
Analog
Comparator Voltage Reference Output
2
Comparator 1
C1INA
C1INB
D12
A12
170
176
D17
I
Analog
Comparator 1 Positive Input
B17
I
Analog
Comparator 1 Selectable Negative Input
Analog
I
Analog
C1INC
D5
31
D9
I
C1IND
E5
PPS
30
PPS
A9
PPS
O
C1OUT
—
Comparator 1 Output
Comparator 2
C2INA
B10
7
B16
I
Analog
Comparator 2 Positive Input
C2INB
A13
172
C17
I
Analog
Comparator 2 Selectable Negative Input
Analog
C2INC
C5
33
B9
I
C2IND
B5
PPS
32
PPS
C9
PPS
I
Analog
O
—
C2OUT
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2021 Microchip Technology Inc.
Comparator 2 Output
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001361J-page 27
PIC32MZ Graphics (DA) Family
TABLE 1-12:
PMP PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
Pin
Type
Buffer
Type
Description
PMP
PMA0
H13
142
N17
I/O
TTL/ST
PMP Address bit 0 Input (Buffered Client modes) and Output
(Host modes)
PMA1
J11
136
R18
I/O
TTL/ST
PMP Address bit 1 Input (Buffered Client modes) and Output
(Host modes)
PMA2
C5
33
B9
O
—
PMA3
H11
135
R17
O
—
PMA4
J12
139
N15
O
—
B18
O
—
PMA5
A11
174
PMA6
F3
69
K3
O
—
PMA7
B12
173
E16
O
—
PMA8
N2
96
V9
O
—
95
T8
O
—
PMA9
M2
PMA10
K3
90
U7
O
—
PMA11
L1
91
V7
O
—
PMA12
J1
80
U5
O
—
N4
O
—
R6
O
—
PMA13
J2
81
PMP Address (Demultiplexed Host modes)
PMA14
G2
74
PMA15
G3
75
T6
O
—
PMCS1
G2
74
R6
O
—
T6
O
—
TTL/ST
PMCS2
G3
75
PMP Chip Select 1 Strobe
PMP Chip Select 2 Strobe
PMD0
C4
40
B7
I/O
PMD1
A4
36
D8
I/O
TTL/ST
PMD2
N3
99
V10
I/O
TTL/ST
PMD3
M3
98
T9
I/O
TTL/ST
TTL/ST
PMD4
B3
43
B6
I/O
PMD5
B7
17
A12
I/O
TTL/ST
PMD6
F6
23
C11
I/O
TTL/ST
PMD7
C7
24
B11
I/O
TTL/ST
T7
I/O
TTL/ST
PMD8
K2
89
PMD9
L3
97
U9
I/O
TTL/ST
PMD10
A9
10
A15
I/O
TTL/ST
PMD11
G10
143
N18
I/O
TTL/ST
C13
I/O
TTL/ST
TTL/ST
PMD12
A8
14
PMP Data (Demultiplexed Host mode) or Address/Data (Multiplexed Host modes)
PMD13
G12
144
M16
I/O
PMD14
L11
127
V17
I/O
TTL/ST
PMD15
H1
76
U6
I/O
TTL/ST
PMALL
H13
142
N17
O
—
PMP Address Latch Enable Low Byte (Multiplexed Host
modes)
PMALH
J11
136
R18
O
—
PMP Address Latch Enable High Byte (Multiplexed Host
modes)
PMRD
B8
16
A13
O
—
PMP Read Strobe
O
—
PMP Write Strobe
PMWR
Legend:
A7
15
B13
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001361J-page 28
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 1-13:
EBI PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
Pin
Type
Buffer
Type
Description
External Bus Interface
EBIA0
H13
142
N17
O
—
—
EBIA1
J11
136
R18
O
EBIA2
C5
33
B9
O
—
—
EBIA3
H11
135
R17
O
EBIA4
J12
139
N15
O
—
EBIA5
A11
174
B18
O
—
—
EBIA6
F3
69
K3
O
EBIA7
B12
173
E16
O
—
EBIA8
N2
96
V9
O
—
95
T8
O
—
EBIA9
M2
EBIA10
K3
90
U7
O
—
EBIA11
L1
91
V7
O
—
—
EBIA12
J1
80
U5
O
EBIA13
J2
81
N4
O
—
R6
O
—
—
EBIA14
G2
74
EBIA15
G3
75
T6
O
EBIA16
K12
137
P16
O
—
R16
O
—
EBIA17
L13
EBIA18
H10
133
P15
O
—
EBIA19
J10
132
R15
O
—
T18
O
—
134
EBIA20
M13
131
EBIA21
M12
130
T17
O
—
EBIA22
E8
151
K17
O
—
V8
O
—
B7
I/O
ST
ST
ST
EBIA23
L2
EBID0
C4
92
40
EBID1
A4
36
D8
I/O
EBID2
N3
99
V10
I/O
EBID3
M3
98
T9
I/O
ST
ST
ST
EBID4
B3
43
B6
I/O
EBID5
B7
17
A12
I/O
EBID6
F6
23
C11
I/O
ST
ST
EBID7
C7
24
B11
I/O
EBID8
K2
89
T7
I/O
ST
EBID9
L3
97
U9
I/O
ST
ST
EBID10
A9
10
A15
I/O
EBID11
G10
143
N18
I/O
ST
EBID12
A8
14
C13
I/O
ST
ST
EBID13
G12
144
M16
I/O
EBID14
L11
127
V17
I/O
ST
I/O
ST
EBID15
Legend:
H1
76
U6
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2021 Microchip Technology Inc.
External Bus Interface Address Bus
External Bus Interface Data I/O Bus
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001361J-page 29
PIC32MZ Graphics (DA) Family
TABLE 1-13:
EBI PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin
Type
Buffer
Type
M17
O
—
146
M18
O
—
150
K18
O
—
—
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
EBIBS0
J11
145
EBIBS1
J12
EBICS0
G10
EBICS1
H12
149
L18
O
EBICS2
H11
148
L17
O
—
EBICS3
H10
147
L16
O
—
EBIOE
B8
16
A13
O
—
M10
128
U17
I
ST
I
ST
EBIRDY1
EBIRDY2
C5
138
P17
EBIRDY3
C4
152
K16
I
ST
N16
O
—
EBIRP
EBIWE
Legend:
F1
O
A7
15
B13
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-14:
Pin
Name
141
—
Description
External Bus Interface Byte Select
External Bus Interface Chip Select
External Bus Interface Output Enable
External Bus Interface Ready Input
External Bus Interface Flash Reset Pin
External Bus Interface Write Enable
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
USB PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
VBUS
A2
45
C5
I
Analog
VUSB3V3
B2
46, 47
C4, D5
P
—
D+
C1
51
B4
I/O
Analog
Description
Universal Serial Bus
DUSBID
Legend:
USB internal transceiver supply. If the USB module is not used,
this pin must be connected to VSS.
USB D+
I/O
Analog USB DB1
50
A4
I
ST
USB OTG ID detect
D3
52
C6
CMOS = CMOS-compatible input or output
Analog = Analog input
ST = Schmitt Trigger input with CMOS levels
O = Output
TTL = Transistor-transistor Logic input buffer
PPS = Peripheral Pin Select
TABLE 1-15:
Pin
Name
USB bus power monitor
P = Power
I = Input
CAN1 AND CAN2 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
Description
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
C1TX
PPS
PPS
PPS
O
—
CAN1 Bus Transmit Pin
C1RX
PPS
PPS
PPS
I
ST
CAN1 Bus Receive Pin
C2TX
PPS
PPS
PPS
O
—
CAN2 Bus Transmit Pin
C2RX
PPS
PPS
PPS
I
ST
Controller Area Network
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001361J-page 30
CAN2 Bus Receive Pin
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 1-16:
ETHERNET MII I/O DESCRIPTIONS
Pin Number
Pin Name
Pin
Type
Buffer
Type
Description
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
ERXD0
N7
108
U12
I
ST
Ethernet Receive Data 0
ERXD1
M4
100
U10
I
ST
Ethernet Receive Data 1
T10
I
ST
Ethernet Receive Data 2
ST
Ethernet Receive Data 3
Ethernet Receive Error Input
Ethernet
ERXD2
N4
101
ERXD3
N6
107
V12
I
ERXERR
M1
93
U8
I
ST
ERXDV
M5
104
V11
I
ST
Ethernet Receive Data Valid
ERXCLK
N8
111
U13
I
ST
Ethernet Receive Clock
ETXD0
N9
113
V14
O
—
Ethernet Transmit Data 0
112
T13
O
—
Ethernet Transmit Data 1
ETXD1
M9
ETXD2
M8
110
V13
O
—
Ethernet Transmit Data 2
ETXD3
M7
109
T12
O
—
Ethernet Transmit Data 3
V15
O
—
Ethernet Transmit Error
121
V16
O
—
Ethernet Transmit Enable
ETXERR
L10
118
ETXEN
K11
ETXCLK
M10
120
T15
I
ST
Ethernet Transmit Clock
ECOL
M6
106
T11
I
ST
Ethernet Collision Detect
U11
I
ST
Ethernet Carrier Sense
O
—
Ethernet Management Data Clock
ECRS
EMDC
EMDIO
Legend:
N5
105
N10
119
U15
I/O
K10
114
U14
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-17:
Ethernet Management Data
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
ETHERNET RMII PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
—
Pin
Type
Buffer
Type
Description
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
N7
108
U12
I
ST
Ethernet Receive Data 0
U10
I
ST
Ethernet Receive Data 1
ST
Ethernet Receive Error Input
Ethernet MII Interface
ERXD0
ERXD1
ERXERR
M4
100
M1
93
U8
I
ETXD0
N9
113
V14
O
—
Ethernet Transmit Data 0
ETXD1
M9
112
T13
O
—
Ethernet Transmit Data 1
V16
O
—
Ethernet Transmit Enable
—
Ethernet Management Data Clock
ETXEN
K11
121
EMDC
N10
119
U15
O
EMDIO
K10
114
U14
I/O
—
Ethernet Management Data
EREFCLK
N8
111
U13
I
ST
Ethernet Reference Clock
I
ST
ECRSDV
Legend:
M5
104
V11
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2021 Microchip Technology Inc.
Ethernet Carrier Sense Data Valid
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001361J-page 31
PIC32MZ Graphics (DA) Family
TABLE 1-18:
SQI1 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
Pin
Type
Buffer
Type
Description
Serial Quad Interface
SQICLK
E4
O
E4
54
—
Serial Quad Interface Clock
SQICS0
F1
70
K4
O
—
Serial Quad Interface Chip Select 0
SQICS1
F2
71
L4
O
—
Serial Quad Interface Chip Select 1
ST
Serial Quad Interface Data 0
SQID0
E2
64
H4
I/O
SQID1
E3
56
G4
I/O
ST
Serial Quad Interface Data 1
J4
I/O
ST
Serial Quad Interface Data 2
SQID2
SQID3
Legend:
E1
65
I/O
D1
55
F4
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-19:
Serial Quad Interface Data 3
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
SDHC PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
ST
Pin
Type
Buffer
Type
Description
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
E4
54
E4
O
—
SD Serial Clock
—
SD Command/Response
SDHC
SDCK
SDCMD
F1
70
K4
O
SDDATA0
E2
64
H4
I/O
ST
SD Serial Data 0
ST
SD Serial Data 1
SDDATA1
E3
56
G4
I/O
SDDATA2
E1
65
J4
I/O
ST
SD Serial Data 2
ST
SD Serial Data 3/Card Detect
SD Mechanical Card Detect
SDDATA3
D1
55
F4
I/O
SDCD
D2
53
D4
I
ST
I
ST
SDWP
Legend:
H12
141
N16
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
TABLE 1-20:
P = Power
I = Input
CTMU PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
SD Write Protect
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
Pin
Type
Buffer
Type
Description
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
CTED1
B9
11
A14
I
ST
CTMU External Edge Input 1
CTED2
C12
169
D18
I
ST
CTMU External Edge Input 2
Charge Time Measurement Unit
CTPLS
Legend:
F7
9
B15
O
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001361J-page 32
—
CTMU Output Pulse
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 1-21:
GRAPHICS LCD (GLCD) CONTROLLER PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
Pin
Type
Buffer
Type
Description
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
GCLK
G11
148
L17
O
—
Graphics Display Pixel Clock
HSYNC
F12
149
L18
O
—
Graphics Display Horizontal Sync Pulse
K18
O
—
Graphics Display Vertical Sync Pulse
—
Graphics Display Enable Output
Graphics Controller Data Output
GLCD Controller
VSYNC
F13
150
GEN
G13
147
L16
O
GD0
G12
144
M16
O
—
GD1
L11
127
V17
O
—
GD2
H1
76
U6
O
—
V9
O
—
—
GD3
N2
96
GD4
M2
95
T8
O
GD5
K3
90
U7
O
—
GD6
L1
91
V7
O
—
U5
O
—
—
GD7
GD8
J1
80
G10
143
N18
O
GD9
F9
145
M17
O
—
GD10
G2
74
R6
O
—
T6
O
—
R16
O
—
GD11
G3
75
GD12
L13
GD13
H10
133
P15
O
—
GD14
J10
132
R15
O
—
GD15
M13
131
T18
O
—
T7
O
—
97
U9
O
—
GD16
GD17
K2
L3
134
89
GD18
F8
146
M18
O
—
GD19
M12
130
T17
O
—
K17
O
—
V8
O
—
GD20
GD21
GD22
GD23
Legend:
E8
L2
151
92
O
J2
81
N4
O
K12
137
P16
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2021 Microchip Technology Inc.
—
—
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS60001361J-page 33
PIC32MZ Graphics (DA) Family
TABLE 1-22:
DDR2 SDRAM CONTROLLER PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
Pin
Type
Buffer
Type
Description
DDR2 SDRAM Controller
DDRCK
DDRCK
DDR Internal
DDR Internal
to the Package to the Package
DDRCKE
K2
O
SSTL
K1
O
SSTL
Differential Clocks
L2
O
SSTL
Clock Enable
DDRCS0
N2
O
SSTL
Chip Select 0
DDRRAS
M1
O
SSTL
Row Address Strobe
SSTL
Column Address Strobe
Write Enable Strobe
P2
O
DDRWE
L1
O
SSTL
DDRLDM
G3
O
SSTL
Lower Data Byte Mask
DDRUDM
A3
O
SSTL
Upper Data Byte Mask
DDRODT
DDRCAS
N1
O
SSTL
On-Die Termination
DDRLDQS
E1
I/O
SSTL
Lower Data Byte Qualifier Strobes (Differential)
SSTL
DDRLDQS
E2
I/O
DDRUDQS
B2
I/O
SSTL
DDRUDQS
A2
I/O
SSTL
DDRBA0
Upper Data Byte Qualifier Strobes (Differential)
M2
O
SSTL
Bank Address Select 0
DDRBA1
M3
O
SSTL
Bank Address Select 1
DDRBA2
U4
O
SSTL
Bank Address Select 2
DDRA0
R1
O
SSTL
DDR2 Address Bus
DDRA1
L3
O
SSTL
DDRA2
N3
O
SSTL
DDRA3
R2
O
SSTL
DDRA4
P3
O
SSTL
DDRA5
T1
O
SSTL
DDRA6
U1
O
SSTL
DDRA7
T2
O
SSTL
DDRA8
U2
O
SSTL
DDRA9
R3
O
SSTL
P1
O
SSTL
V2
O
SSTL
DDRA12
T3
O
SSTL
DDRA13
U3
O
SSTL
T4
O
SSTL
O
SSTL
DDRA10
DDRA11
DDRA14
DDRA15
Legend:
V3
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001361J-page 34
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
SSTL = Stub Series Terminated Logic
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 1-22:
DDR2 SDRAM CONTROLLER PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
DDRDQ0
DDRDQ1
169-pin
LFBGA
176-pin
LQFP
DDR Internal
DDR Internal
to the Package to the Package
Pin
Type
Buffer
Type
F1
I/O
SSTL
SSTL
288-pin
LFBGA
J3
I/O
DDRDQ2
H1
I/O
SSTL
DDRDQ3
G1
I/O
SSTL
DDRDQ4
G2
I/O
SSTL
H2
I/O
SSTL
H3
I/O
SSTL
DDRDQ7
F2
I/O
SSTL
DDRDQ8
C1
I/O
SSTL
DDRDQ9
C3
I/O
SSTL
DDRDQ10
D2
I/O
SSTL
DDRDQ11
F3
I/O
SSTL
DDRDQ12
E3
I/O
SSTL
DDRDQ13
D1
I/O
SSTL
B3
I/O
SSTL
I/O
SSTL
DDRDQ5
DDRDQ6
DDRDQ14
DDRDQ15
Legend:
C2
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
2015-2021 Microchip Technology Inc.
Description
DDR2 Data Bus
DDR2 Data Bus
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
SSTL = Stub Series Terminated Logic
DS60001361J-page 35
PIC32MZ Graphics (DA) Family
POWER, GROUND, AND VOLTAGE REFERENCE PINOUT I/O
DESCRIPTIONS
TABLE 1-23:
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
AVDD
D9
3, 4
F13, G13
AVSS
C8, D8
5, 6
F12, G12
VDDIO
B6, G9,
H9, J9,
K9, L6,
L7, L9
19, 38, 86,
102, 117,
124, 155,
156, 165
C16, D15,
D16, E15,
F11, F15,
G11, G15,
H11, H12,
H13, H15,
J10, J15,
K10, L11,
L12, M12,
M13, M15,
N12, N13,
R9, R10,
R12, R13,
R14
VDDCORE
B4, C9,
L8, N1
18, 39, 84,
116
D7, D14,
R11, V4
P
—
1.8V positive supply for core logic. This pin must be connected at all times.
21, 22, 29, A5, B5,
37, 48, 49, C7, D10,
83, 87, 94, D11, D12,
103, 115, D13, F9,
122, 123, F10, G10,
153, 154 H10, J11,
J12, J13,
K11, K12,
K13, K15,
L10, L13,
L15, M10,
M11, N10,
N11, R7,
R8
P
—
Ground reference for logic, I/O pins, and USB. This pin
must be connected at all times.
VSS
C2, F5,
G5, G6,
G7, G8,
H7, H8,
J7, J8, K7,
K8
Power and Ground
P
Positive supply for analog modules. This pin must be
connected at all times.
P
P
Ground reference for analog modules. This pin must be
connected at all times.
P
—
Positive supply for peripheral logic and I/O pins. This pin
must be connected at all times.
P
HLVDIN
B12
173
E16
P
—
Low-voltage detect pin.
VBAT
D10
166
F16
P
—
Positive supply for the battery backed section. It is
recommended to connect this pin to VDDIO if VBAT mode is
not used (i.e., not connected to the battery).
Positive supply for the DDR2 SDRAM memory.
VDDR1V8
Legend:
Note 1:
2:
3:
P
—
H5, H6, 57, 58, 59, H6, H7,
J5, J6, K5, 60, 61, 62, H8, J6, J7,
J8, K6,
63, 67, 68,
K6
K7, K8,
72, 78
(Note 2)
(Note 2) L6, L7, L8
(Note 2)
CMOS = CMOS-compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = Transistor-transistor Logic input buffer
PPS = Peripheral Pin Select
The metal plane at the bottom of the device is internally tied to VSS1V8 and must be connected to 1.8V ground externally.
This pin must be tied to Vss through a 20k resistor in devices without DDR.
This pin is a No Connect in devices without DDR.
DS60001361J-page 36
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 1-23:
POWER, GROUND, AND VOLTAGE REFERENCE PINOUT I/O
DESCRIPTIONS (CONTINUED)
Pin Name
VSS1V8
DDRVREF
VREF+
VREFLegend:
Note 1:
2:
3:
Pin Number
Pin
Type
Buffer
Type
—
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
G4, H4,
J4, K4, L4,
L5
See
Note 1
D3, F6,
F7, F8,
G6, G7,
G8, G9,
H9, J9,
K9, L9,
M6, M7,
M8, M9,
N6, N7,
N8, N9,
R4
P
F4
(Note 3)
66
(Note 3)
J11
P
Description
Ground reference for DDR2 SDRAM memory.
Voltage Reference
—
1.8V Voltage Reference to DDR2 SDRAM memory.
I
Analog Analog Voltage Reference (High) Input
2
C15
I
Analog Analog Voltage Reference (Low) Input
B11
1
A17
CMOS = CMOS-compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = Transistor-transistor Logic input buffer
PPS = Peripheral Pin Select
The metal plane at the bottom of the device is internally tied to VSS1V8 and must be connected to 1.8V ground externally.
This pin must be tied to Vss through a 20k resistor in devices without DDR.
This pin is a No Connect in devices without DDR.
C10
2015-2021 Microchip Technology Inc.
DS60001361J-page 37
PIC32MZ Graphics (DA) Family
TABLE 1-24:
JTAG, TRACE, AND PROGRAMMING/DEBUGGING PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
169-pin
LFBGA
176-pin
LQFP
288-pin
LFBGA
TCK
E11
160
H16
I
ST
JTAG Test Clock Input Pin
TDI
A6
28
A10
I
ST
JTAG Test Data Input Pin
TDO
C6
27
A11
O
—
JTAG Test Data Output Pin
TMS
D2
53
D4
I
TRCLK
E4
54
E4
O
—
Trace Clock
TRD0
E2
64
H4
O
—
Trace Data bits 0-3
TRD1
E3
56
G4
O
—
TRD2
E1
65
J4
O
—
TRD3
D1
55
F4
O
—
Programming/Debugging
PGED1
C12
169
D18
I/O
ST
Data I/O pin for Programming/Debugging Communication
Channel 1
PGEC1
B9
11
A14
I
ST
Clock input pin for Programming/Debugging Communication
Channel 1
PGED2
D12
170
D17
I/O
ST
Data I/O pin for Programming/Debugging Communication
Channel 2
PGEC2
D7
13
B14
I
ST
Clock input pin for Programming/Debugging Communication
Channel 2
MCLR
K1
85
R5
I/P
ST
Master Clear (Reset) input. This pin is an active-low Reset to
the device.
JTAG
Legend:
CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
DS60001361J-page 38
ST
Trace
JTAG Test Mode Select Pin
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
2.0
Note:
2.1
GUIDELINES FOR GETTING
STARTED WITH 32-BIT
MICROCONTROLLERS
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the documents listed in the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
Basic Connection Requirements
Getting started with the PIC32MZ DA family of 32-bit
Microcontrollers (MCUs) requires attention to a minimal
set of device pin connections before proceeding with
development. The following is a list of pin names, which
must always be connected:
• All VDDIO, VDDCORE, and VSS pins (see
2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins, even if the ADC module
is not used (see 2.2 “Decoupling Capacitors”)
• VBAT pin (see 2.2 “Decoupling Capacitors”)
• All VDDR1V8 and VSS1V8 pins (see
2.2 “Decoupling Capacitors”)
• MCLR pin (see 2.3 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins, used for In-Circuit Serial
Programming (ICSP™) and debugging purposes
(see 2.4 “ICSP Pins”)
• OSC1 and OSC2 pins, when external oscillator
source is used (see 2.7 “External Oscillator
Pins”)
2.2
Decoupling Capacitors
The use of decoupling capacitors on power supply
pins, such as VDDIO, VSS, AVDD and AVSS is
required. See Figure 2-1.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: It is recommended
that two parallel capacitors with a value of 0.1 µF
(100 nF, 10-20V) and a value of 0.01 µF be used.
The 0.1 µF capacitor should be a low Equivalent
Series Resistance (low-ESR) capacitor and have
resonance frequency in the range of 20 MHz and
higher. Place both capacitors in close proximity and
consider implementing the pair of capacitances as
close to the power and ground pins as possible. It is
further recommended that ceramic capacitors be
used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close to
the pins as possible. It is recommended that the
capacitors be placed on the same side of the board
as the device. If space is constricted, the capacitor
can be placed on another layer on the PCB using a
via; however, ensure that the trace length from the
pin to the capacitor is within one-quarter inch
(6 mm) in length.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first, and
then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally
important is to keep the trace length between the
capacitor and the power pins to a minimum thereby
reducing PCB track inductance.
The following pin(s) may be required as well:
VREF+/VREF- pins, used when external voltage
reference for the ADC module is implemented.
Note:
The AVDD and AVSS pins must be
connected, regardless of ADC use and
the ADC voltage reference source.
2015-2021 Microchip Technology Inc.
DS60001361J-page 39
PIC32MZ Graphics (DA) Family
FIGURE 2-1:
RECOMMENDED MINIMUM CONNECTION
VDDIO(1,2)
VDDIO(1)
VDDCORE (1,2)
AVDD(1)
VUSB3V3(3)
L1(4)
0.01 μF
0.1 μF
0.01 μF
0.1 μF
VSS(1)
0.01 μF
VSS(1)
VSS(1)
VBAT(1)
VDDR1V8(1)
0.01 μF
0.01 μF
0.1 μF
0.1 μF
VSS1V8(1)
VSS(1)
Note
1:
2:
3:
4:
5:
0.1 μF
0.1μF
0.1 μF
0.01 μF
0.01 μF
VSS(1)
AVSS(1)
( )
DDRVREF 5
0.01 μF
0.1 μF
VSS1V8
There are multiple power and ground pairs and minimum connection rules which apply for each power pin (i.e., VDDIO, VDDCORE,
AVDD, VUSB3V3, VBAT, VDDR1V8) and each ground pin (VSS, AVSS, VSS1V8).
Voltage on VDDIO must always be greater than or equal to VDDCORE during power-up.
If the USB module is not used, this pin must be connected to VSS.
As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDDIO and AVDD to improve ADC
noise rejection. The inductor impedance should be less than 1Ω and the inductor capacity greater than 10 mA.
This pin is a no connect in devices without DDR.
Where:
F CNV
f = -------------2
(i.e., ADC conversion rate/2)
1
f = ----------------------- 2 LC
2
1
L = ----------------------
2f C
2.2.1
BULK CAPACITORS
The use of a bulk capacitor on VDDIO and VDDCORE
is recommended to improve power supply stability.
Typical values range from 4.7 µF to 47 µF. This
capacitor should be located as close to the device as
possible.
DS60001361J-page 40
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
2.3
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
• Device Reset
• Device programming and debugging
Pulling The MCLR pin low generates a device Reset.
Figure 2-2 illustrates a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
For example, as illustrated in Figure 2-2, it is
recommended that the capacitor C be isolated from the
MCLR pin during programming and debugging
operations.
Place the components illustrated in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDDIO
R
10k
ICSP™
0.1 µF(2)
Note
1
5
4
2
3
6
VDDIO
VSS
NC
C
R1(1)
1 k
MCLR
PIC32
PGECx(3)
PGEDx(3)
1:
470W ≤ R1 ≤ 1KΩ will limit any current flowing into
MCLR from the external capacitor C, in the event of
MCLR pin breakdown, due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS). Ensure that the
MCLR pin VIH and VIL specifications are met without
interfering with the Debug/Programmer tools.
2:
The capacitor can be sized to prevent unintentional
Resets from brief glitches or to extend the device
Reset period during POR.
3:
No pull-ups or bypass capacitors are allowed on
active debug/program PGECx/PGEDx pins.
2015-2021 Microchip Technology Inc.
2.4
ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on
the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series
resistor is recommended, with the value in the range
of a few tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 3 or MPLAB REAL ICE™.
For additional information on ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available for download from the
Microchip web site, www.microchip.com:
• “Using MPLAB® ICD 3” (poster) (DS50001765)
• “MPLAB® ICD 3 Design Advisory” (DS50001764)
• “MPLAB® REAL ICE™ In-Circuit Debugger
User’s Guide” (DS50001616)
• “Using MPLAB® REAL ICE™ Emulator” (poster)
(DS50001749)
2.5
JTAG
The TMS, TDO, TDI and TCK pins are used for testing
and debugging according to the Joint Test Action
Group (JTAG) standard. It is recommended to keep the
trace length between the JTAG connector and the
JTAG pins on the device as short as possible. If the
JTAG connector is expected to experience an ESD
event, a series resistor is recommended, with the value
in the range of a few tens of Ohms, not to exceed 100
Ohms.
Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended
as they will interfere with the programmer or debugger
communications to the device. If such discrete components are an application requirement, they should be
removed from the circuit during programming and
debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the
respective device Flash programming specification for
information on capacitive loading limits and pin input
voltage high (VIH) and input low (VIL) requirements.
DS60001361J-page 41
PIC32MZ Graphics (DA) Family
2.6
Trace
2.7.1
The trace pins can be connected to a hardware
trace-enabled programmer to provide a compressed
real-time instruction trace. When used for trace, the
TRD3, TRD2, TRD1, TRD0 and TRCLK pins should
be dedicated for this use. The trace hardware
requires a 22 Ohm series resistor between the trace
pins and the trace connector.
2.7
External Oscillator Pins
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same side
of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The
load capacitors should be placed next to the oscillator
itself, on the same side of the board. Use a grounded
copper pour around the oscillator circuit to isolate them
from surrounding circuits. The grounded copper pour
should be routed directly to the MCU ground. Do not
run any signal traces or power traces inside the ground
pour. Also, if using a two-sided board, avoid any traces
on the other side of the board where the crystal is
placed. A suggested layout is illustrated in Figure 2-3.
CRYSTAL OSCILLATOR DESIGN
CONSIDERATION
The following example assumptions are used to
calculate the Primary Oscillator loading capacitor
values:
•
•
•
•
CIN = PIC32_OSC2_pin capacitance = 4 pF
COUT = PIC32_OSC1_pin capacitance = 4 pF
PCB stray capacitance (i.e., 12 mm length) = 2.5 pF
C1 and C2 are the loading capacitors to use on
your Crystal circuit design to guarantee that the
effective capacitance as seen by the crystal in circuit meets the crystal manufacturer specification.
From the Crystal manufacturer CLOAD spec:
CLOAD = {( [Cin + C1] * [COUT + C2] ) / [Cin + C1 + C2
+ COUT] } + oscillator PCB stray capacitance
EXAMPLE 2-1: CRYSTAL LOAD CAPACITOR
CALCULATION
Crystal manufacturer data sheet spec example: CLOAD = 15 pF
Therefore:
MFG CLOAD = {( [CIN + C1] * [COUT + C2] ) / [CIN + C1 + C2 +
COUT] }
+ estimated oscillator PCB stray capacitance
Assuming C1 = C2 and PIC32 Cin = Cout, the formula can be further
simplified and restated to solve for C1 and C2 by:
C1 = C2 = ((2 * MFG Cload spec) - Cin - (2 * PCB capacitance))
= ((2 * 15) - 4 - (2 * 2.5 pF))
= (30 - 4 - 5)
FIGURE 2-3:
SUGGESTED OSCILLATOR
CIRCUIT PLACEMENT
Oscillator
Secondary
Guard Trace
= 21 pF
Therefore:
C1 = C2 = 21 pF is the correct loading capacitors to use on your crystal circuit design to guarantee that the effective capacitance as seen
by the crystal in circuit in this example is 15 pF to meet the crystal.
Note:
Guard Ring
Main Oscillator
2.7.1.1
Do not add excessive gain such that the
oscillator signal is clipped flat on top of the
sine wave. If your oscillator signal is
clipped, reduce the gain or add a series
resistor (RS) as shown in the “Circuit A” of
the Figure 2-4. Failure to do so will stress
and reduce the lifetime of the crystal,
which might result in a premature failure.
When measuring the oscillator signal, the
user must use an active-powered scope
probe with 1 pF or the scope probe itself
will unduly change the gain and Peak-toPeak oscillator signal levels.
Additional Microchip References
• AN588 “PICmicro® Microcontroller Oscillator
Design Guide”
• AN826 “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
• AN849 “Basic PICmicro® Oscillator Design”
DS60001361J-page 42
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
FIGURE 2-4:
PRIMARY CRYSTAL
OSCILLATOR CIRCUIT
RECOMMENDATIONS
C2
C1
Circuit A
Rs
OSC2
OSC1
Circuit B
Not Recommended
RSHUNT
Rs
OSC2
OSC1
Circuit C
Not Recommended
Rs
RSHUNT
OSC2
Note:
2.8
OSC1
For recommended resistor values versus
crystal/frequency, Refer to the “PIC32MK
GP/MC Family Silicon Errata and Data
Sheet Clarification” (DS80000737), which
is available for download from the Microchip web site (www.microchip.com).
Unused I/Os
Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
to a logic-low state.
Alternatively, inputs can be reserved by connecting the
pin to VSS through a 1k to 10k resistor and configuring
the pin as an input.
2015-2021 Microchip Technology Inc.
DS60001361J-page 43
PIC32MZ Graphics (DA) Family
2.9
Considerations When Interfacing
to Remotely Powered Circuits
2.9.1
Without a proper signal isolation on non-5V tolerant
pins, the remote signal can power the PIC32 device
through the high side ESD protection diodes.
Besides violating the absolute maximum rating
specification when VDD of the PIC32 device is
restored and ramping up or ramping down, it can
also negatively affect the internal Power-on Reset
(POR) and Brown-out Reset (BOR) circuits, which
can lead to improper initialization of internal PIC32
logic circuits. In these cases, it is recommended to
implement digital or analog signal isolation as shown
in Figure 2-6. This is indicative of all industry
microcontrollers and not just Microchip products.
NON-5V TOLERANT INPUT PINS
A quick review of the absolute maximum rating section
in 44.0 “Electrical Characteristics” indicates that the
voltage on any non-5v tolerant pin should not exceed
VDD + 0.3V, unless the input current is limited to meet
the respective injection current specifications defined
by the parameters DI60a, DI60b, and DI60c as shown
in Table 44-12.
Figure 2-5 illustrates a remote circuit using an independent power source, which is powered while connected
to a PIC32 non-5V tolerant circuit that is not powered.
FIGURE 2-5:
Note:
PIC32 NON-5V TOLERANT CIRCUIT EXAMPLE
When VDD power is OFF.
PIC32
Non-5V Tolerant
Pin Architecture
On/Off
VDD
ANSEL
I/O IN
AN2/RB0
I/O OUT
Remote
GND
TRIS
CPU LOGIC
Remote
0.3V dVIH d 3.6V
PIC32
POWER
SUPPLY
Current Flow
VSS
DS60001361J-page 44
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
Capacitive Coupling
Opto Coupling
Analog/Digital Switch
EXAMPLES OF DIGITAL/
ANALOG ISOLATORS WITH
OPTIONAL LEVEL
TRANSLATION
Inductive Coupling
TABLE 2-1:
ADuM7241 / 40 ARZ (1 Mbps)
X
—
—
—
ADuM7241 / 40 CRZ (25 Mbps)
X
—
—
—
ISO721
—
X
—
—
LTV-829S (2-Channel)
—
—
X
—
LTV-849S (4-Channel)
—
—
X
—
FSA266 / NC7WB66
—
—
—
X
Example Digital/Analog
Signal Isolation Circuits
FIGURE 2-6:
EXAMPLE DIGITAL/ANALOG SIGNAL ISOLATION CIRCUITS
Conn
PIC32 VDD
Digital Isolator
External VDD
IN
REMOTE_IN
PIC32
PIC32 VDD
Digital Isolator
External VDD
REMOTE_IN
IN1
REMOTE_OUT
OUT1
PIC32
VSS
VSS
PIC32 VDD
Opto Digital
ISOLATOR
External VDD
PIC32 VDD
Analog / Digital Isolator
Conn
IN1
ENB
Analog_OUT2
PIC32
External_VDD1
ENB
PIC32
S
Analog_IN1
REMOTE_IN
Analog_IN2
Analog Switch
VSS
VSS
2015-2021 Microchip Technology Inc.
DS60001361J-page 45
PIC32MZ Graphics (DA) Family
2.9.2
5V TOLERANT INPUT PINS
The internal high side diode on 5V tolerant pins are
bussed to an internal floating node, rather than being
connected to VDDIO, as shown in Figure 2-7. The
voltage on these pins, if VDDIO < 2.2V (usually
during power up or power down), should not exceed
3.2V relative to VSS of the PIC32 device. The
voltage of 3.6V or higher will (when VDDIO < 2.2V)
violate the absolute maximum specification and will
stress the oxide layer separating the high side
floating node, which impacts device reliability.
assuming there is no ground loop issue, that is, the
logic ground of the two circuits are not at the same
absolute level, and remote logic low input is not less
than VSS - 0.3V. Once VDDIO is >2.2V, the pin can
be operated up to 5.5V.
If a remotely powered “digital-only” signal can be
guaranteed to be 3.2V relative to Vss on the
PIC32 device side, a 5V tolerant pin can be used
without the need for a digital isolator. This is
FIGURE 2-7:
PIC32 5V TOLERANT PIN ARCHITECTURE EXAMPLE
PIC32
5V Tolerant Pin
Architecture
Floating Bus
Oxide BV = 3.6V
if VDD < 2.V
OXIDE
On/Off
VDD
ANSEL
I/O IN
RG10
I/O OUT
Remote
GND
TRIS
CPU LOGIC
Remote
VIH = 2.5V
PIC32
POWER
SUPPLY
VSS
DS60001361J-page 46
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
2.10
Designing for High-Speed
Peripherals
The PIC32MZ DA family devices have peripherals that
operate at frequencies much higher than typical for an
embedded environment. Table 2-2 lists the peripherals
that produce high-speed signals on their external pins:
TABLE 2-2:
PERIPHERALS THAT
PRODUCE HS SIGNALS ON
EXTERNAL PINS
Peripheral
DDR2 SDRAM
Controller
High-Speed
Signal Pins
Maximum
Speed on
Signal Pin
DDRCLK,
DDRCLK,
DDRUDQS,
DDRUDQS,
DDRLDQS,
DDRLDQS,
DDRAx
200 MHz
DDRDx
400 MHz
EBIAx,
EBIDx
50 MHz
HS USB
D+, D-
480 MHz
SDHC
SDCK, DATAx
50 MHz
SQI
SQICLK, SQIDx
80 MHz
EBI
Due to these high-speed signals, it is important to
consider several factors when designing a product that
uses these peripherals, as well as the PCB on which
these components will be placed. Adhering to these
recommendations will help achieve the following goals:
• Minimize the effects of electromagnetic interference
to the proper operation of the product
• Ensure signals arrive at their intended destination at
the same time
• Minimize crosstalk
• Maintain signal integrity
• Reduce system noise
• Minimize ground bounce and power sag
2.10.1
2.10.1.1
SYSTEM DESIGN
Impedance Matching
When selecting parts to place on high-speed buses,
particularly the SQI bus, if the impedance of the peripheral device does not match the impedance of the pins
on the PIC32MZ DA device to which it is connected,
signal reflections could result, thereby degrading the
quality of the signal.
If it is not possible to select a product that matches
impedance, place a series resistor at the load to create
the matching impedance, see Figure 2-8 for an
example.
2015-2021 Microchip Technology Inc.
FIGURE 2-8:
SERIES RESISTOR
PIC32MZ
50
2.10.1.2
SQI
Flash
Device
PCB Layout Recommendations
The following list contains recommendations that will
help ensure the PCB layout will promote the goals
previously listed.
• Component Placement
- Place bypass capacitors as close to their
component power and ground pins as possible,
and place them on the same side of the PCB
- Devices on the same bus that have larger setup
times should be placed closer to the PIC32MZ DA
device
• Power and Ground
- Multi-layer PCBs will allow separate power and
ground planes
- Each ground pin should be connected to the
ground plane individually
- Place bypass capacitor vias as close to the pad
as possible (preferably inside the pad)
- If power and ground planes are not used,
maximize width for power and ground traces
- Use low-ESR, surface-mount bypass capacitors
• Clocks and Oscillators
- Place crystals as close as possible to the
PIC32MZ DA device OSC/SOSC pins
- Do not route high-speed signals near the clock or
oscillator
- Avoid via usage and branches in clock lines
(SQICLK)
- Place termination resistors at the end of clock
lines
• Traces
- Higher-priority signals should have the shortest
traces
- Follow vendor-recommended layout guidelines for
the DDR2 interface
- Match trace lengths for parallel buses (EBIAx,
EBIDx, SQIDx)
- Avoid long run lengths on parallel traces to reduce
coupling
- Make the clock traces as straight as possible
- Use rounded turns rather than right-angle turns
- Have traces on different layers intersect on right
angles to minimize crosstalk
- Maximize the distance between traces, preferably
no less than three times the trace width
- Power traces should be as short and as wide as
possible
- High-speed traces should be placed close to the
ground plane
DS60001361J-page 47
PIC32MZ Graphics (DA) Family
2.10.1.3
EMI/EMC/EFT (IEC 61000-4-4 and
IEC 61000-4-2) Suppression
Considerations
The use of LDO regulators is preferred to reduce
overall system noise and provide a cleaner power
source. However, when utilizing switching Buck/Boost
regulators as the local power source for PIC32MZ DA
devices, as well as in electrically noisy environments or
test conditions required for IEC 61000-4-4 and IEC
61000-4-2, users should evaluate the use of T-Filters
(i.e., L-C-L) on the power pins, as shown in Figure 2-9.
In addition to a more stable power source, using
T-Filters can greatly reduce susceptibility to EMI
sources and events.
Note:
The EMI/EMC/EFT Suppression Circuit
represents only a few supply/ground
pairs. However, the number of pairs on a
given package may vary. The number of
T-Filters in the system depends on the ferrite chip current limitation and the number
of supply/ground pairs. For example, with
600 mA current limitation per T-Filter for
the 288-LFBGA package, the system
should use three T-Filters.
FIGURE 2-9:
EMI/EMC/EFT
SUPPRESSION CIRCUIT
Ferrite Chip SMD
DCR = 0.15ȍ(max)
600 ma ISAT
300ȍ@ 100 MHz
PN#:
VDD
0.01 µF
Ferrite
Chips
0.1 µF
VSS
VDD
VDD
VSS
0.1 µF
VSS
VDD
VSS
0.1 µF
PIC32MZ
VSS
0.1 µF
0.1 µF
VDD
VSS
VDD
VSS
VUSB3V3
VDD
AVDD
AVSS
0.1 µF
VSS
VDD
0.1 µF
0.1 µF
0.1 µF
Ferrite
Chips
VDD
0.01 µF
DS60001361J-page 48
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
2.11
Typical Application Connection
Example
An example of a typical application connection is
shown in Figure 2-10.
FIGURE 2-10:
GRAPHICS APPLICATION
PIC32
GLCD I/F
GD(1)
GLCD
System Bus
GCLK
HSYNC
DISPLAY
VSYNC
GEN
RAM(2)
GPU
DDRCS0
DDR2
SDRAM
Controller
DDR2 SDRAM Controller I/F
DDRCK, DDRCK
DDRUDQS, DDRUDQS
DDRLDQS, DDRLDQS
DDRA
DDR2 SDRAM(2.3)
DDRDQ
DDRCAS, DDRRAS, DDRWE
ODT
Note 1:
R = GD; G = GD; B = GD.
2:
Frame buffers are either in system RAM or in the DDR2 SDRAM (maximum resolution supported depends on
the memory size).
3:
Stacked die version (169-pin LFBGA and 176-pin LQFP) supports 32 MB DDR2 SDRAM devices.
2015-2021 Microchip Technology Inc.
DS60001361J-page 49
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 50
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
3.0
CPU
Note 1: This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 50. “CPU for
Devices with MIPS32® microAptiv™
and M-Class Cores” (DS60001192),
which
is
available
from
the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
2: MIPS32® microAptiv™ Microprocessor
Core resources are available at:
http://www.imgtec.com.
The MIPS32 microAptiv Microprocessor Core is the
heart of the PIC32MZ DA family device processor. The
CPU fetches instructions, decodes each instruction,
fetches source operands, executes each instruction
and writes the results of instruction execution to the
proper destinations.
3.1
Features
PIC32MZ DA family processor core key features:
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32 Enhanced Architecture (Release 2):
- Multiply-accumulate and multiply-subtract
instructions
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency for
interrupt handlers
- Bit field manipulation instructions
- Virtual memory support
• microMIPS compatible instruction set:
- Improves code size density over MIPS32, while
maintaining MIPS32 performance.
- Supports all MIPS32 instructions (except branchlikely instructions)
- Fifteen additional 32-bit instructions and 39 16-bit
instructions corresponding to commonly-used
MIPS32 instructions
- Stack pointer implicit in instruction
- MIPS32 assembly and ABI compatible
2015-2021 Microchip Technology Inc.
• MMU with Translation Lookaside Buffer (TLB)
mechanism:
- 32 dual-entry fully associative Joint TLB
- 4-entry fully associative Instruction TLB
- 4-entry fully associative Data TLB
- 4 KB pages
• Separate L1 data and instruction caches:
- 32 KB 4-way Instruction Cache (I-Cache)
- 32 KB 4-way Data Cache (D-Cache)
• Autonomous Multiply/Divide Unit (MDU):
- Maximum issue rate of one 32x32 multiply per
clock
- Early-in iterative divide. Minimum 12 and
maximum 38 clock latency (dividend (rs) sign
extension-dependent)
• Power Control:
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT instruction)
- Extensive use of local gated clocks
• EJTAG Debug and Instruction Trace:
- Support for single stepping
- Virtual instruction and data address/value
breakpoints
- Hardware breakpoint supports both address
match and address range triggering.
- Eight instruction and four data complex
breakpoints
• iFlowtrace® version 2.0 support:
- Real-time instruction program counter
- Special events trace capability
- Two performance counters with 34 userselectable countable events
- Disabled if the processor enters Debug mode
• Four Watch registers:
- Instruction, Data Read, Data Write options
- Address match masking options
• DSP ASE Extension:
- Native fractional format data type operations
- Register Single Instruction Multiple Data
(SIMD) operations (add, subtract, multiply,
shift)
- GPR-based shift
- Bit manipulation
- Compare-Pick
- DSP Control Access
- Indexed-Load
- Branch
- Multiplication of complex operands
- Variable bit insertion and extraction
- Virtual circular buffers
- Arithmetic saturation and overflow handling
- Zero-cycle overhead saturation and rounding
operations
DS60001361J-page 51
PIC32MZ Graphics (DA) Family
A block diagram of the PIC32MZ DA family processor
core is shown in Figure 3-1.
FIGURE 3-1:
PIC32MZ DA FAMILY MICROPROCESSOR CORE BLOCK DIAGRAM
microAptiv™ Microprocessor Core
PBCLK7
Decode
(MIPS32®/microMIPS™)
microMIPS™
GPR
(8 sets)
Execution Unit
ALU/Shift
Atomic/LdSt
DSP ASE
Enhanced MDU
(with DSP ASE)
Debug/Profiling
System
Interface
System
Coprocessor
Interrupt
Interface
2-wire Debug
DS60001361J-page 52
Break Points
iFlowtrace®
Fast Debug Channel
Performance Counters
Sampling
Secure Debug
I-Cache
Controller
MMU
(TLB)
I-Cache
BIU
System Bus
D-Cache
Controller
D-Cache
Power
Management
EJTAG
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
3.2
Architecture Overview
The MIPS32 microAptiv Microprocessor core in
PIC32MZ DA family devices contains several logic
blocks working together in parallel, providing an
efficient high-performance computing engine. The
following blocks are included with the core:
•
•
•
•
•
•
•
•
•
•
Execution unit
General Purpose Register (GPR)
Multiply/Divide Unit (MDU)
System control coprocessor (CP0)
Memory Management Unit (MMU)
Instruction/Data cache controllers
Power Management
Instructions and data caches
microMIPS support
Enhanced JTAG (EJTAG) controller
3.2.1
3.2.2
MULTIPLY/DIVIDE UNIT (MDU)
The processor core includes a Multiply/Divide Unit
(MDU) that contains a separate pipeline for multiply
and divide operations, and DSP ASE multiply instructions. This pipeline operates in parallel with the Integer
Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially
masked by system stalls and/or other integer unit
instructions.
EXECUTION UNIT
The processor core execution unit implements a load/
store architecture with single-cycle ALU operations
(logical, shift, add, subtract) and an autonomous
multiply/divide unit. The core contains thirty-two 32-bit
General Purpose Registers (GPRs) used for integer
operations and address calculation. Seven additional
register file shadow sets (containing thirty-two
registers) are added to minimize context switching
overhead during interrupt/exception processing. The
register file consists of two read ports and one write
port and is fully bypassed to minimize operation latency
in the pipeline.
The execution unit includes:
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
address
• Logic for branch determination and branch target
address calculation
• Load aligner
• Trap condition comparator
• Bypass multiplexers used to avoid stalls when
executing instruction streams where data producing
instructions are followed closely by consumers of
their results
TABLE 3-1:
• Leading Zero/One detect unit for implementing the
CLZ and CLO instructions
• Arithmetic Logic Unit (ALU) for performing arithmetic
and bitwise logical operations
• Shifter and store aligner
• DSP ALU and logic block for performing DSP
instructions, such as arithmetic/shift/compare operations
The high-performance MDU consists of a 32x32 booth
recoded multiplier, four pairs of result/accumulation
registers (HI and LO), a divide state machine, and the
necessary multiplexers and control logic. The first number shown (‘32’ of 32x32) represents the rs operand.
The second number (‘32’ of 32x32) represents the rt
operand.
The MDU supports execution of one multiply or
multiply-accumulate operation every clock cycle.
Divide operations are implemented with a simple 1-bitper-clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For
a 16-bit wide rs, 15 iterations are skipped and for a
24-bit wide rs, 7 iterations are skipped. Any attempt to
issue a subsequent MDU instruction while a divide is
still active causes an IU pipeline stall until the divide
operation has completed.
Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency (number of cycles until a result is available) for the processor
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
MIPS32 microAptiv MICROPROCESSOR CORE HIGH-PERFORMANCE INTEGER
MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU (HI/LO destination)
MUL (GPR destination)
DIV/DIVU
2015-2021 Microchip Technology Inc.
Operand Size (mul rt) (div rs)
Latency
Repeat Rate
16 bits
32 bits
16 bits
32 bits
8 bits
16 bits
24 bits
32 bits
5
5
5
5
12/14
20/22
28/30
36/38
1
1
1
1
12/14
20/22
28/30
36/38
DS60001361J-page 53
PIC32MZ Graphics (DA) Family
The MIPS architecture defines that the result of a
multiply or divide operation be placed in one of four
pairs of HI and LO registers. Using the Move-From-HI
(MFHI) and Move-From-LO (MFLO) instructions, these
values can be transferred to the General Purpose
Register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in
the primary register file instead of the HI/LO register
pair. By avoiding the explicit MFLO instruction
required when using the LO register, and by supporting multiple destination registers, the throughput of
multiply-intensive operations is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
The MDU also implements various shift instructions
operating on the HI/LO register and multiply instructions as defined in the DSP ASE. The MDU supports all
of the data types required for this purpose and includes
three extra HI/LO registers as defined by the ASE.
TABLE 3-3:
Register
Number
Table 3-2 lists the latencies and repeat rates for the
DSP multiply and dot-product operations. The approximate latencies and repeat rates are listed in terms of
pipeline clocks.
TABLE 3-2:
DSP-RELATED LATENCIES
AND REPEAT RATES
Op code
Latency
Repeat
Rate
Multiply and dot-product without
saturation after accumulation
5
1
Multiply and dot-product with
saturation after accumulation
5
1
Multiply without accumulation
5
1
3.2.3
SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation and cache protocols, the exception control system, the processor’s
diagnostics capability, the operating modes (Kernel,
User and Debug) and whether interrupts are enabled or
disabled. Configuration information, such as cache
size and set associativity, and the presence of options
like microMIPS, is also available by accessing the CP0
registers, listed in Table 3-3.
COPROCESSOR 0 REGISTERS
Register
Name
Function
0
1
2
Index
Random
EntryLo0
3
EntryLo1
4
Context/
UserLocal
5
6
7
PageMask/
PageGrain
Wired
HWREna
8
9
BadVAddr
Count
Index into the TLB array (microAptiv MPU only).
Randomly generated index into the TLB array (microAptiv MPU only).
Low-order portion of the TLB entry for even-numbered virtual pages (microAptiv MPU
only).
Low-order portion of the TLB entry for odd-numbered virtual pages (microAptiv MPU
only).
Pointer to the page table entry in memory (microAptiv MPU only).
User information that can be written by privileged software and read via the RDHWR
instruction.
PageMask controls the variable page sizes in TLB entries. PageGrain enables support
of 1 KB pages in the TLB (microAptiv MPU only).
Controls the number of fixed (i.e., wired) TLB entries (microAptiv MPU only).
Enables access via the RDHWR instruction to selected hardware registers in
Non-privileged mode.
Reports the address for the most recent address-related exception.
Processor cycle count.
10
11
EntryHi
Compare
High-order portion of the TLB entry (microAptiv MPU only).
Core timer interrupt control.
DS60001361J-page 54
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 3-3:
Register
Number
12
COPROCESSOR 0 REGISTERS (CONTINUED)
Register
Name
Status
IntCtl
SRSCtl
Processor status and control.
Interrupt control of vector spacing.
Shadow register set control.
SRSMap
View_IPL
Shadow register mapping control.
Allows the Priority Level to be read/written without
extracting or inserting that bit from/to the Status register.
Contains two 4-bit fields that provide the mapping from a vector number to the shadow
set number to use when servicing such an interrupt.
Describes the cause of the last exception.
Contains the error and exception level status bit values that existed prior to the current
exception.
Enables read access to the RIPL bit that is available in the Cause register.
Program counter at last exception.
SRSMAP2
13
14
Cause
NestedExc
View_RIPL
EPC
26
NestedEPC
PRID
Ebase
CDMMBase
Config
Config1
Config2
Config3
Config4
Config5
Config7
LLAddr
WatchLo
WatchHi
Reserved
Debug
TraceControl
TraceControl2
UserTraceData1
TraceBPC
Debug2
DEPC
UserTraceData2
PerfCtl0
PerfCnt0
PerfCtl1
PerfCnt1
ErrCtl
27
28
Reserved
TagLo/DataLo
15
16
17
18
19
20-22
23
24
25
Function
Contains the exception program counter that existed prior to the current exception.
Processor identification and revision
Exception base address of exception vectors.
Common device memory map base.
Configuration register.
Configuration register 1.
Configuration register 2.
Configuration register 3.
Configuration register 4.
Configuration register 5.
Configuration register 7.
Load link address (microAptiv MPU only).
Low-order watchpoint address (microAptiv MPU only).
High-order watchpoint address (microAptiv MPU only).
Reserved in the PIC32 core.
EJTAG debug register.
EJTAG trace control.
EJTAG trace control 2.
EJTAG user trace data 1 register.
EJTAG trace breakpoint register.
Debug control/exception status 1.
Program counter at last debug exception.
EJTAG user trace data 2 register.
Performance counter 0 control.
Performance counter 0.
Performance counter 1 control.
Performance counter 1.
Software test enable of way-select and data RAM arrays for I-Cache and D-Cache
(microAptiv MPU only).
Reserved in the PIC32 core.
Low-order portion of cache tag interface (microAptiv MPU only).
2015-2021 Microchip Technology Inc.
DS60001361J-page 55
PIC32MZ Graphics (DA) Family
3.3
Power Management
The processor core offers a number of power management features, including low-power design, active power
management and power-down modes of operation. The
core is a static design that supports slowing or halting
the clocks, which reduces system power consumption
during Idle periods.
3.3.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 40.0
“Power-Saving Features”.
3.3.2
LOCAL CLOCK GATING
The majority of the power consumed by the processor
core is in the clock tree and clocking registers. The
PIC32MZ family makes extensive use of local gatedclocks to reduce this dynamic power consumption.
3.4
3.4.1
L1 Instruction and Data Caches
INSTRUCTION CACHE (I-CACHE)
The I-Cache is an on-core memory block of 32 Kbytes.
Because the I-Cache is virtually indexed, the virtual-tophysical address translation occurs in parallel with the
cache access rather than having to wait for the physical
address translation. The tag holds 23 bits of physical
address, a valid bit, and a lock bit. The LRU replacement bits are stored in a separate array.
The I-Cache block also contains and manages the
instruction line fill buffer. Besides accumulating data to
be written to the cache, instruction fetches that reference data in the line fill buffer are serviced either by a
bypass of that data, or data coming from the external
interface. The I-Cache control logic controls the bypass
function.
The processor core supports I-Cache locking. Cache
locking allows critical code or data segments to be
locked into the cache on a per-line basis, enabling the
system programmer to maximize the efficiency of the
system cache.
The cache locking function is always available on all
I-Cache entries. Entries can then be marked as
locked or unlocked on a per entry basis using the
CACHE instruction.
3.4.2
DATA CACHE (D-CACHE)
The D-Cache is an on-core memory block of
32 Kbytes. This virtually indexed, physically tagged
cache is protected. Because the D-Cache is virtually
indexed, the virtual-to-physical address translation
occurs in parallel with the cache access. The tag holds
23 bits of physical address, a valid bit, and a lock bit.
There is an additional array holding dirty bits and LRU
replacement algorithm bits for each set of the cache.
DS60001361J-page 56
In addition to I-Cache locking, the processor core also
supports a D-Cache locking mechanism identical to the
I-Cache. Critical data segments are locked into the
cache on a per-line basis. The locked contents can be
updated on a store hit, but cannot be selected for
replacement on a cache miss.
The D-Cache locking function is always available on
all D-Cache entries. Entries can then be marked as
locked or unlocked on a per-entry basis using the
CACHE instruction.
3.4.3
ATTRIBUTES
The processor core I-Cache and D-Cache attributes
are listed in the Configuration registers (see
Register 3-1 through Register 3-4).
3.5
EJTAG Debug Support
The processor core provides for an Enhanced JTAG
(EJTAG) interface for use in the software debug of
application and kernel code. In addition to standard
User mode and Kernel modes of operation, the processor core provides a Debug mode that is entered after a
debug exception (derived from a hardware breakpoint,
single-step exception, etc.) is taken and continues until
a Debug Exception Return (DERET) instruction is
executed. During this time, the processor executes the
debug exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for transferring test data in and out of the core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification specify which
registers are selected and how they are used.
3.6
MIPS® DSP ASE Extension
The MIPS DSP Application-Specific Extension
Revision 2 is an extension to the MIPS32 architecture.
This extension comprises new integer instructions and
states that include new HI/LO accumulator register
pairs and a DSP control register. This extension is
crucial in a wide range of DSP, multimedia, and DSPlike algorithms covering Audio and Video processing
applications. The extension supports native fractional
format data type operations, register Single Instruction
Multiple Data (SIMD) operations, such as add,
subtract, multiply, and shift. In addition, the extension
includes the following features that are essential in
making DSP algorithms computationally efficient:
•
•
•
•
Support for multiplication of complex operands
Variable bit insertion and extraction
Implementation and use of virtual circular buffers
Arithmetic saturation and overflow handling
support
• Zero cycle overhead saturation and rounding
operations
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
3.7
microAptiv Core Configuration
Register 3-1 through Register 3-4 show the default
configuration of the microAptiv core, which is included
on PIC32MZ DA family devices.
REGISTER 3-1:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG: CONFIGURATION REGISTER; CP0 REGISTER 16, SELECT 0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
r-1
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
ISP
R-1
R-0
R-0
R-1
R-0
U-0
DSP
UDI
SB
MDU
—
R-0
R-0
R-0
R-0
BE
AT
R-0
R-1
U-0
U-0
U-0
U-0
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
R-0
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R-0
MM
R-1
BM
R-0
AR
MT
Bit
24/16/8/0
R-0
MT
R/W-0
R/W-1
R/W-0
K0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Reserved: This bit is hardwired to ‘1’ to indicate the presence of the Config1 register.
bit 30-25 Unimplemented: Read as ‘0’
bit 24
ISP: Instruction Scratch Pad RAM bit
0 = Instruction Scratch Pad RAM is not implemented
bit 23
DSP: Data Scratch Pad RAM bit
0 = Data Scratch Pad RAM is not implemented
bit 22
UDI: User-defined bit
0 = CorExtend User-Defined Instructions are not implemented
bit 21
SB: SimpleBE bit
1 = Only simple byte enables are allowed on the internal bus interface
bit 20
MDU: Multiply/Divide Unit bit
0 = Fast, high-performance MDU
bit 19
Unimplemented: Read as ‘0’
bit 18-17 MM: Merge Mode bits
10 = Merging is allowed
bit 16
BM: Burst Mode bit
0 = Burst order is sequential
bit 15
BE: Endian Mode bit
0 = Little-endian
bit 14-13 AT: Architecture Type bits
00 = MIPS32
bit 12-10 AR: Architecture Revision Level bits
001 = MIPS32 Release 2
bit 9-7
MT: MMU Type bits
001 = microAptiv MPU Microprocessor core uses a TLB-based MMU
bit 6-3
Unimplemented: Read as ‘0’
bit 2-0
K0: Kseg0 Coherency Algorithm bits
010 = Uncached
2015-2021 Microchip Technology Inc.
DS60001361J-page 57
PIC32MZ Graphics (DA) Family
REGISTER 3-2:
Bit
Range
31:24
23:16
15:8
7:0
CONFIG1: CONFIGURATION REGISTER 1; CP0 REGISTER 16, SELECT 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
r-1
R-0
R-1
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
R-1
R-1
R-1
R-1
—
R-0
MMU Size
R-1
R-1
R-0
IS
R-0
R-1
R-1
IS
R-0
IL
R-1
R-1
R-0
DS
Bit
24/16/8/0
R-1
R-1
IA
R-1
R-1
R-0
DL
R-1
DA
R-1
U-0
U-0
R-1
R-0
R-0
R-1
R-0
DA
—
—
PC
WR
CA
EP
FP
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Reserved: This bit is hardwired to a ‘1’ to indicate the presence of the Config2 register.
bit 30-25 MMU Size: Contains the number of TLB entries minus 1
011111 = 32 TLB entries
bit 24-22 IS: Instruction Cache Sets bits
011 = Contains 512 instruction cache sets per way
bit 21-19 IL: Instruction-Cache Line bits
011 = Contains instruction cache line size of 16 bytes
bit 18-16 IA
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
PIC32MZ DA microcontrollers provide 4 GB of unified
virtual memory address space. All memory regions,
including program, data memory, SFRs and
Configuration registers, reside in this address space
at their respective unique addresses. The program
and data memories can be optionally partitioned into
user and kernel memories. In addition, PIC32MZ DA
devices allow execution from data memory.
4.1
Memory Layout
PIC32MZ DA microcontrollers implement two address
schemes: virtual and physical. All hardware
resources, such as program memory, data memory
and peripherals, are located at their respective
physical addresses. Virtual addresses are exclusively
used by the CPU to fetch and execute instructions as
well as access peripherals. Physical addresses are
used by bus host peripherals, such as DMA and the
Flash controller, that access memory independently of
the CPU.
The main memory maps for the PIC32MZ DA devices
are illustrated in Figure 4-1. Figure 4-2 provides
memory map information for Boot Flash and boot
alias. Table 4-1 provides memory map information for
Program Flash, RAM, and DDR2 SDRAM. Table 4-2
provides memory map information for Special
Function Registers (SFRs).
Key features include:
• 32-bit native data width
• Separate User (KUSEG) and Kernel (KSEG0/
KSEG1/KSEG2/KSEG3) mode address space
• Separate Boot Flash memory for protected code
• Robust bus exception handling to intercept
runaway code
• Cacheable (KSEG0/KSEG2) and non-cacheable
(KSEG1/KSEG3) address regions
• Read-Write permission access to predefined
memory regions
2015-2021 Microchip Technology Inc.
DS60001361J-page 61
PIC32MZ Graphics (DA) Family
FIGURE 4-1:
PIC32MZ DA FAMILY MEMORY MAP
Virtual
Memory Map(1)
0xD4000000
0xD3FFFFFF
0xD0000000
0xC4000000
0xC3FFFFFF
0xC0000000
0xBFC74000
0xBFC73FFF
0xBFC00000
0xBF900000
0xBF8FFFFF
0xBF800000
Reserved
Reserved
External Memory via
SQI
Reserved
External Memory via
EBI
Boot Flash
(see Figure 4-2)
Program Flash
(see Table 4-1)
Boot Flash
(see Figure 4-2)
0x9FC74000
0x9FC73FFF
0x9FC00000
0x00000000
Note
1:
2:
3:
4:
DS60001361J-page 62
0x20000000
0x1FC74000
0x1FC73FFF
0x1FC00000
0x1F900000
0x1F8FFFFF
0x1F800000
0x1D000000
Reserved
Reserved
Boot Flash
(see Figure 4-2)
DDR2 SDRAM(4)
(see Table 4-1)
DDR2 SDRAM(4)
(see Table 4-1)
KSEG0
(cacheable)
Program Flash
(see Table 4-1)
0x08000000
Reserved
RAM(2)
(see Table 4-1)
Reserved
0x80000000
0x24000000
0x23FFFFFF
Program Flash
(see Table 4-1)
RAM(2)
(see Table 4-1)
Reserved
0x88000000
SFRs
(see Table 4-2)
0x30000000
Reserved
Reserved
0x9D000000
Reserved
0x34000000
0x33FFFFFF
DDR2 SDRAM(4)
(see Table 4-1)
Reserved
0xA0000000
Reserved
Reserved
Reserved
SFRs
(see Table 4-2)
External Memory via
SQI
External Memory via
EBI
Reserved
Reserved
0xA8000000
Reserved
External Memory via
EBI
Reserved
0xBD000000
KSEG3(3)
(not cacheable)
External Memory via
SQI
0xFFFFFFFF
KSEG2(3)
(cacheable)
0xE4000000
0xE3FFFFFF
0xE0000000
Reserved
KSEG1
(not cacheable)
0xFFFFFFFF
0xF4000000
0xF3FFFFFF
0xF0000000
Physical
Memory Map(1)
0x00000000
RAM(2)
(see Table 4-1)
Reserved
Memory areas are not shown to scale.
RAM memory is divided into two banks. Refer to Table 4-1 for additional information.
The MMU must be enabled and the TLB must be set up to access this segment.
This region is Reserved in devices without the DDR2 option.
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 4-1:
ADDRESS MAPPING TABLE
Memory
Program Flash
Size
Region End
Address (KSEG1)
Region End
Address (KSEG0)
Region End
Address (Physical)
2 MB
0xBD1FFFFF
0x9D1FFFFF
0x1D1FFFFF
1 MB
0xBD0FFFFF
0x9D0FFFFF
0x1D0FFFFF
0xAFFFFFFF
0x8FFFFFFF
0x0FFFFFFF
0xA9FFFFFF
0x89FFFFFF
0x09FFFFFF
(1)
EXT
DDR2 SDRAM
32 MB(5)
(2)
—
RAM
Note 1:
2:
3:
4:
5:
Reserved
Reserved
Reserved
(3)
640 KB
0xA009FFFF
0x8009FFFF
0x0009FFFF
256 KB(4)
0xA003FFFF
0x8003FFFF
0x0003FFFF
External DDR2 SDRAM can be up to 128 MB, EXTDDRSIZE bits (DEVCFG3) should be
set, and the region end address should be scaled accordingly.
Devices without the DDR2 option.
Devices with 640 KB RAM contain SRAM Bank 1 (256 KB) and SRAM Bank 2 (384 KB).
Devices with 256 KB RAM contain SRAM Bank 1 (128 KB) and SRAM Bank 2 (128 KB).
Refer to 4.2 “DDR2 SDRAM” for DDR2 SDRAM features, which are applicable to devices with internal
DDR2 SDRAM.
2015-2021 Microchip Technology Inc.
DS60001361J-page 63
PIC32MZ Graphics (DA) Family
FIGURE 4-2:
BOOT AND ALIAS
MEMORY MAP
Physical Memory Map(1)
0x1FC74000
Sequence/Configuration Space(3)
0x1FC70000
0x1FC6FF00
Boot Flash 2
0x1FC60000
Reserved
0x1FC5402C
(4)
Serial Number
0x1FC54020
TABLE 4-2:
SFR MEMORY MAP
Virtual Address
Peripheral
Base
System Bus(1)
0xBF8F0000
0x1FC50000
0x1FC4FF00
Boot Flash 1
0x1FC40000
Reserved
0x1FC34000
0xC000
GPU
0xB000
GLCD
0xA000
DDRPHY
0x9100
DDRC
0x8000
0xBF8E0000
Unused Configuration
0x1FC30000
0x1FC2FF00
Upper Boot Alias
0x1FC20000
Reserved
0x1FC14000
Configuration Space(2,3)
0x1FC10000
0x1FC0FF00
Lower Boot Alias
0x1FC00000
Note 1:
2:
3:
4:
5:
Memory areas are not shown to scale.
Memory locations 0x1FC0FF40
through 0x1FC0FFFC are used to
initialize Configuration registers (see
Section 41.0 “Special Features”).
Refer to Section 4.1.1 “Boot Flash
Sequence and Configuration
Spaces” for more information.
Memory location 0x1FC54020 contains
a 128-bit unique device serial number
(see Section 41.0 “Special
Features”).
This configuration space cannot be
used for executing code in the upper
boot alias.
0x5000
USB
0x3000
SQI1
0x2000
EBI
0x1000
Prefetch
0x0000
DSCTRL
0xBF8C0000
USBCR
0x0200
0x0000
0x4000
Ethernet
0xBF880000
CAN1 and CAN2
0x2000
0x0000
PORTA-PORTK
0xBF860000
0x0000
CTMU
0xC200
Comparator 1, 2
0xC000
ADC
0xBF840000
OC1-OC9
0xB000
0x4000
IC1-IC9
0x2000
Timer1-Timer9
0x0000
PMP
0xE000
UART1-UART6
0xBF820000
SPI1-SPI6
I2C1-I2C5
0x2000
0x1000
0x0000
DMA
Interrupt Controller
0xBF810000
0x1000
0x0000
HLVD
0x1800
PPS
0x1400
Oscillator
0x1200
CVREF
0x0E00
Deadman Timer
0xBF800000
0x0A00
Watchdog Timer
0x0800
Flash Controller
0x0600
Configuration
0x0000
Note 1:
DS60001361J-page 64
0x6000
Crypto
RTCC
Space(5)
0x0000
SDHC
RNG
Sequence/Configuration Space(3)
Offset
Start
Refer to 4.4 “System Bus Arbitration”
for important legal information.
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
4.1.1
BOOT FLASH SEQUENCE AND
CONFIGURATION SPACES
Sequence space is used to identify which Boot Flash is
aliased by aliased regions. If the value programmed
into the TSEQ bits of the BF1SEQ3 word is
equal to or greater than the value programmed into the
TSEQ bits of the BF2SEQ3 word, Boot Flash 1
is aliased by the lower boot alias region, and Boot
Flash 2 is aliased by the upper boot alias region. If the
TSEQ bits of the BF2SEQ3 word are greater
than the TSEQ bits of the BF1SEQ3 word, the
opposite is true (see Table 4-3 and Table 4-4 for
BFxSEQ3 word memory locations).
4.1.2
ALTERNATE SEQUENCE AND
CONFIGURATION WORDS
Every word in the configuration space and sequence
space has an associated alternate word (designated by
the letter A as the first letter in the name of the word).
During device start-up, primary words are read and if
uncorrectable ECC errors are found, the BCFGERR
(RCON) flag is set and alternate words are used.
If uncorrectable ECC errors are found in primary and
alternate words, the BCFGFAIL (RCON) flag is
set and the default configuration is used.
The CSEQ bits must contain the complement
value of the TSEQ bits; otherwise, the value of
the TSEQ bits are considered invalid, and an
alternate sequence is used, see Section 4.1.2
“Alternate Sequence and Configuration Words” for
more information.
Once Boot Flash memories are aliased, configuration
space located in the lower boot alias region is used as
the basis for the Configuration words, DEVSIGN0,
DEVCP0, and DEVCFGx (and the associated alternate
configuration registers). This means that the Boot
Flash region to be aliased by lower boot alias region
memory must contain configuration values in the
appropriate memory locations.
Note:
Do not use word program operation
(NVMOP = 0001) when programming data into the sequence and
configuration spaces.
2015-2021 Microchip Technology Inc.
DS60001361J-page 65
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
2015-2021 Microchip Technology Inc.
31:0
31:0
31:0
31:0
31:0
31:0
Note: See Table 41-2 for the bit descriptions.
31:0
31:0
31:0
31:0
31:0
31:0
31:0
CSEQ
31:16
FF70 ABF1SEQ3
15:0
TSEQ
—
—
—
—
—
—
—
—
—
—
—
31:16
FFF4 ABF1SEQ2
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
FF78 ABF1SEQ1
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
FF7C ABF1SEQ0
—
—
—
—
—
—
—
—
—
—
—
15:0
31:0
FFBC BF1DEVCFG4
31:0
FFC0 BF1DEVCFG3
FFC4 BF1DEVCFG2
31:0
FFC8 BF1DEVCFG1
31:0
FFCC BF1DEVCFG0
31:0
FFD0 BF1DEVCP3
31:0
Note: See Table 41-1 for the bit descriptions.
FFD4 BF1DEVCP2
31:0
FFD8 BF1DEVCP1
31:0
FFDC BF1DEVCP0
31:0
FFE0 BF1DEVSIGN3
31:0
FFE4 BF1DEVSIGN2
31:0
FFE8 BF1DEVSIGN1
31:0
FFEC BF1DEVSIGN0
31:0
CSEQ
31:16
FFF0 BF1SEQ3
15:0
TSEQ
—
—
—
—
—
—
—
—
—
—
—
31:16
FFF4 BF1SEQ2
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
FFF8 BF1SEQ1
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
FFFC BF1SEQ0
—
—
—
—
—
—
—
—
—
—
—
15:0
Legend:
x = unknown value on Reset; — = Read corresponding register bit detail for this information. Reset values are shown in hexadecimal.
20/4
19/3
18/2
17/1
16/0
ABF1DEVCFG4
ABF1DEVCFG3
ABF1DEVCFG2
ABF1DEVCFG1
ABF1DEVCFG0
ABF1DEVCP3
ABF1DEVCP2
ABF1DEVCP1
ABF1DEVCP0
ABF1DEVSIGN3
ABF1DEVSIGN2
ABF1DEVSIGN1
ABF1DEVSIGN0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
All Reset
Bit Range
Bits
Register
Name
Virtual Address
(BFC4_#)
FF3C
FF40
FF44
FF48
FF4C
FF50
FF54
FF58
FF5C
FF60
FF64
FF68
FF6C
BOOT FLASH 1 SEQUENCE AND CONFIGURATION WORDS SUMMARY
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
PIC32MZ Graphics (DA) Family
DS60001361J-page 66
TABLE 4-3:
BOOT FLASH 2 SEQUENCE AND CONFIGURATION WORDS SUMMARY
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
DS60001361J-page 67
31:0
31:0
31:0
31:0
31:0
31:0
Note: See Table 41-2 for the bit descriptions.
31:0
31:0
31:0
31:0
31:0
31:0
31:0
CSEQ
31:16
FF70 ABF2SEQ3
15:0
TSEQ
—
—
—
—
—
—
—
—
—
—
—
31:16
FFF4 ABF2SEQ2
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
FF78 ABF2SEQ1
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
FF7C ABF2SEQ0
—
—
—
—
—
—
—
—
—
—
—
15:0
31:0
FFBC BF2DEVCFG4
31:0
FFC0 BF2DEVCFG3
FFC4 BF2DEVCFG2
31:0
FFC8 BF2DEVCFG1
31:0
FFCC BF2DEVCFG0
31:0
FFD0 BF2DEVCP3
31:0
Note: See Table 41-1 for the bit descriptions.
FFD4 BF2DEVCP2
31:0
FFD8 BF2DEVCP1
31:0
FFDC BF2DEVCP0
31:0
FFE0 BF2DEVSIGN3
31:0
FFE4 BF2DEVSIGN2
31:0
FFE8 BF2DEVSIGN1
31:0
FFEC BF2DEVSIGN0
31:0
CSEQ
31:16
FFF0 BF2SEQ3
15:0
TSEQ
—
—
—
—
—
—
—
—
—
—
—
31:16
FFF4 BF2SEQ2
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
FFF8 BF2SEQ1
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
FFFC BF2SEQ0
—
—
—
—
—
—
—
—
—
—
—
15:0
Legend:
x = unknown value on Reset; — = Read corresponding register bit detail for this information. Reset values are shown in hexadecimal.
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
All Resets
ABF2DEVCFG4
ABF2DEVCFG3
ABF2DEVCFG2
ABF2DEVCFG1
ABF2DEVCFG0
ABF2DEVCP3
ABF2DEVCP2
ABF2DEVCP1
ABF2DEVCP0
ABF2DEVSIGN3
ABF2DEVSIGN2
ABF2DEVSIGN1
ABF2DEVSIGN0
Bit Range
FF3C
FF40
FF44
FF48
FF4C
FF50
FF54
FF58
FF5C
FF60
FF64
FF68
FF6C
31/15
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
PIC32MZ Graphics (DA) Family
Register
Name
Bits
Virtual Address
(BFC6_#)
2015-2021 Microchip Technology Inc.
TABLE 4-4:
PIC32MZ Graphics (DA) Family
REGISTER 4-1:
Bit
Range
31:24
23:16
15:8
7:0
BFxSEQ3/ABFxSEQ3: BOOT FLASH ‘x’ SEQUENCE WORD 0 REGISTER
(‘x’ = 1 AND 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
CSEQ
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
CSEQ
R/P
TSEQ
R/P
R/P
R/P
R/P
R/P
TSEQ
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 CSEQ: Boot Flash Complement Sequence Number bits
bit 15-0
Note:
TSEQ: Boot Flash True Sequence Number bits
The BFxSEQ0 through BFxSEQ2 and ABFxSEQ0 through ABFxSEQ2 registers are used for Quad Word
programming operation when programming the BFxSEQ3/ABFxSEQ3 registers, and do not contain any
valid information.
DS60001361J-page 68
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
4.2
DDR2 SDRAM
Stacked DDR2 SDRAM memory devices support
32 MB of DDR2 SDRAM. Memory in these devices is
organized as 4,194,304 x 4 banks x 16 bits. Refer to
Figure 4-1 and Table 4-1 for the DDR2 SDRAM
address ranges.
4.2.1
FEATURES
The DDR2 SDRAM includes the following features:
• Double Data Rate architecture: two data transfers
per clock cycle
• CAS Latency: 3 and 4
• Burst Length: 8
• Bi-directional, differential data strobes
(DDRUDQS, DDRLDQS and DDRUDQS,
DDRLDQS) are transmitted / received with data
• Edge-aligned with Read data and center-aligned
with Write data
• DLL aligns Data (DDRDQx) and Data Qualifier
Strobe (DDRxDQS, DDRxDQS) transitions with
clock
• Differential clock inputs (DDRCK and /DDRCK)
FIGURE 4-3:
DDRCK
DDRCK
DLL Clock
Buffer
Bank 3
Bank 2
Bank 1
Bank 0
DDRCS0
DDRCAS
Figure 4-3 provides a block diagram of the DDR2
SDRAM.
DDR2 SDRAM BLOCK DIAGRAM
DDRCKE
DDRRAS
• Data masks (DDRUDM, DDRLDM) for write data
• Commands entered on each positive DDRCK
edge, data and data mask are referenced to both
edges of DDRxDQS
• Posted CAS programmable additive latency supported to make command and data bus efficiency
• Read Latency = Additive Latency plus CAS
Latency (RL = AL + CL)
• Off-Chip-Driver impedance adjustment (OCD)
and On-Die-Termination (ODT) for better signal
quality
• Auto-precharge operation for read and write
bursts
• Auto Refresh and Self Refresh modes
• Precharged Power Down and Active Power Down
• Write Latency = Read Latency - 1 (WL = RL - 1)
Command
Decoder
Control
Signal
Generator
DDRWE
DDRODT
DDRDQ
DDRA
DDRA
DDRA
DDRA
DDRBA0
DDRBA1
Mode
Register
Address
Buffer
Memory
Array
DDRLDQS
ODT
Control
DDRLDQS
DDRUDQS
DDRUDQS
DDRLDM
DDRUDM
Refresh
Counter
2015-2021 Microchip Technology Inc.
Column
Counter
DS60001361J-page 69
PIC32MZ Graphics (DA) Family
4.3
Timing Parameters
4.4
Table 4-5 only applies to device variants with internal
32 MB DDR2 SDRAM. For device variants supporting
external DDR2 SDRAM memory, refer to the vendor
data sheet for timing parameters.
TABLE 4-5:
Parameter
TIMING PARAMETERS
Description
Value Units
tRFC
Auto-refresh Cycle Time
75
ns
tWR
Write Recovery Time
15
ns
tRP
Precharge-to-Active
Command Delay Time
20
ns
tRCD
Active to Read/Write
Command Delay Time
20
ns
tRRD
Row-to-Row (RAS to
RAS) Command Delay
Time
7.5
ns
tWTR
Write-to-Read Command
Delay Time
10
ns
tRTP
Read-to-Precharge
Command Delay Time
10
ns
tDLLK
DLL Lock Delay Time
200
Clock
cycles
tRAS
Active to Precharge
Minimum Command
Delay Time
40
ns
tRC
Row Cycle Time
65
ns
tFAW
Four Bank Activation
Window
35
ns
tMRD
Mode Register Set
Command Cycle Delay
2
Clock
cycles
tXP
Power Down Exit Delay
2
Clock
cycles
tCKE
Power Down Minimum
Delay
3
Clock
cycles
RL
CAS Latency
4
Clock
cycles
tRFI
Average Periodic
Refresh Interval
WL
Write Latency
3
Clock
cycles
BL
Burst Length (in cycles)
8
Clock
cycles
DS60001361J-page 70
7.8
Note:
System Bus Arbitration
The
System
Bus
interconnect
implements one or more instantiations of
the SonicsSX® interconnect from Sonics,
Inc. This document contains materials
that are (c) 2003-2015 Sonics, Inc., and
that constitute proprietary information of
Sonics, Inc. SonicsSX is a registered
trademark of Sonics, Inc. All such
materials and trademarks are used under
license from Sonics, Inc.
As shown in the PIC32MZ DA Family Block Diagram
(see Figure 1-1), there are multiple initiator modules (I1
through I14) in the system that can access various target modules (T1 through T23). Table 4-6 illustrates
which initiator can access which target. The System
Bus supports simultaneous access to targets by
initiators, so long as the initiators are accessing different targets. The System Bus will perform arbitration if
multiple initiators attempt to access the same target.
μs
2015-2021 Microchip Technology Inc.
2015-2021 Microchip Technology Inc.
TABLE 4-6:
INITIATORS TO TARGETS ACCESS ASSOCIATION
Target
Number
Initiator ID
1
2
3
4
Name
CPU
DMA
Read
DMA
Write
USB
Flash Memory:
Program Flash
Boot Flash
Prefetch Module
X
X
2
RAM Bank 1 Memory
X
X
3
RAM Bank 2 Memory
X
X
5
Peripheral Set 1:
System Control
Flash Control
DMT
CVREF
PPS Input
PPS Output
Interrupts
DMA
WDT
X
6
Peripheral Set 2:
SPI1-SPI6
I2C1-I2C5
UART1-UART6
PMP
X
X
X
7
Peripheral Set 3:
Timer1-Timer9
IC1-IC9
OC1-OC9
ADC
Comparator 1
Comparator 2
CTMU
X
X
X
8
Peripheral Set 4:
PORTA-PORTK
X
X
X
9
Peripheral Set 5:
CAN1
CAN2
Ethernet Controller
X
X
X
10
USB
X
X
X
11
External Memory via SQI1 and SQI1 Module
X
X
X
12
Crypto Engine
X
13
RNG Module
X
14
Graphics LCD Controller
X
15
External Memory via DDR2 and DDR2 Target 0
X
16
External Memory via DDR2 and DDR2 Targets 1 and 2
17
External Memory via DDR2 and DDR2 Targets 3 and 4
Note
1:
6
Ethernet Ethernet
Read
Write
7
8
9
CAN1
CAN2
SQI1
X
X
10
11
Flash
Crypto
Controller
12
13
14
GLCD
GPU
SDHC
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X(1)
X(1)
X
The GLCD and GPU are directly connected to the DDR2 SDRAM Controller to use DDR2 SDRAM for frame buffers. Arbitration control is done through the DDR2 SDRAM Controller arbitration engine.
Refer to Section 55. “DDR2 SDRAM Controller” (DS60001321) in the “PIC32 Family Reference Manual” for additional information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 71
1
5
INITIATORS TO TARGETS ACCESS ASSOCIATION (CONTINUED)
Target
Number
Initiator ID
1
2
3
4
Name
CPU
DMA
Read
DMA
Write
USB
X
X
X
18
2D Graphics Processing Unit
19
Secure Digital Host Controller
X
20
DDR2 PHY Control Register Interface
X
21
DDR2 Control Register Interface
X
22
Peripheral Set 6:
RTCC
DSCTRL
X
External Memory via EBI and EBI Module
X
23
Note
1:
5
6
Ethernet Ethernet
Read
Write
7
8
9
CAN1
CAN2
SQI1
X
X
X
10
11
Flash
Crypto
Controller
12
13
14
GLCD
GPU
SDHC
X
X
X
X
X
The GLCD and GPU are directly connected to the DDR2 SDRAM Controller to use DDR2 SDRAM for frame buffers. Arbitration control is done through the DDR2 SDRAM Controller arbitration engine.
Refer to Section 55. “DDR2 SDRAM Controller” (DS60001321) in the “PIC32 Family Reference Manual” for additional information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 72
TABLE 4-6:
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
The System Bus arbitration scheme implements a nonprogrammable, Least Recently Serviced (LRS).
The arbitration scheme for the available initiators is
shown in Table 4-7.
TABLE 4-7:
INITIATOR ID AND
ARBITRATION
ID
Name
Arbitration
1
CPU
LRS
2
DMA Read
LRS
3
DMA Write
LRS
4
USB
LRS
5
Ethernet Read
LRS
6
Ethernet Write
LRS
7
CAN1
LRS
8
CAN2
LRS
9
SQI1
LRS
10
Flash Controller
LRS
11
Crypto
LRS
12
GLCD(1)
LRS
13
GPU(1)
LRS
SDHC
LRS
14
Note 1:
The GLCD and GPU are directly
connected to DDR2 SDRAM Controller to
use DDR2 SDRAM for frame buffers.
Arbitration control is done through the
DDR2 SDRAM Controller arbitration
engine.
2015-2021 Microchip Technology Inc.
4.5
Permission Access and System
Bus Registers
The System Bus on PIC32MZ DA family of
microcontrollers provides access control capabilities
for the transaction initiators on the System Bus.
The System Bus divides the entire memory space into
17 regions and permits access to each target by initiators via permission groups. Four Permission Groups
(0 through 3) can be assigned to each initiator. Each
permission group is independent of the others and
can have exclusive or shared access to a region.
Using the CFGPG register (see Register 41-12 in
Section 41.0 “Special Features”), Boot firmware can
assign a permission group to each initiator, which can
make requests on the System Bus.
The available targets and their regions, as well as the
associated control registers to assign protection, are
described and listed in Table 4-8.
Register 4-2 through Register 4-13 are used for setting
and controlling access permission groups and regions.
To change these registers, they must be unlocked in
hardware. The register lock is controlled by the
PGLOCK Configuration bit (CFGCON). Setting
the PGLOCK bit prevents writes to the control
registers and clearing the PGLOCK bit allows writes.
To set or clear the PGLOCK bit, an unlock sequence
must be executed. Refer to Section 42. “Oscillators
with Enhanced PLL” (DS60001250) in the “PIC32
Family Reference Manual” for details.
DS60001361J-page 73
SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS
SBTxREGy Register (see Note 7)
Target
Protection
Number
0
1
2
3
4
Target Description
(see Note 5)
System Bus
Flash Memory(6):
Program Flash
Boot Flash Prefetch
RAM Bank 1 Memory
RAM Bank 2 Memory
External Memory via DDR2 and
DDR2 Target 0
2015-2021 Microchip Technology Inc.
External Memory via DDR2 and
DDR2 Targets 1 and 2
Name
Name
Write
Permission
(GROUP3,
GROUP2,
GROUP1,
GROUP0)
0
SBT0RD0
0,1,1,1
SBT0WR0
0,1,1,1
3
SBT0RD1
0,0,0,1
SBT0WR1
0,0,0,1
—
0
SBT1RD0
0,0,0,0
SBT1WR0
0,0,0,0
4 KB
1
2
SBT1RD2
R/W(1)
SBT1WR2
R/W(1)
R/W
R/W
1
2
SBT1RD3
0,0,0,0
SBT1WR3
0,0,0,0
R/W
R/W
1
2
SBT1RD4
0,0,0,0
SBT1WR4
0,0,0,0
R/W
R/W
R/W
1
2
SBT1RD5
0,0,0,0
SBT1WR5
0,0,0,0
R/W
R/W
R/W
R/W
1
2
SBT1RD6
0,0,0,0
SBT1WR6
0,0,0,0
SBT1REG7
R/W
R/W
R/W
R/W
0
1
SBT1RD7
0,0,0,0
SBT1WR7
0,0,0,0
SBT1REG8
R/W
R/W
R/W
R/W
0
1
SBT1RD8
0,0,0,0
SBT1WR8
0,0,0,0
SBT2REG0
R
0
R(4)
R(4)
—
0
SBT2RD0
R/W(1)
SBT2WR0
R/W(1)
SBT2REG1
R/W
R/W
R/W
R/W
—
3
SBT2RD1
R/W(1)
SBT2WR1
R/W(1)
SBT2RD2
R/W
(1)
SBT2WR2
R/W(1)
Name
Physical
Start
Address
Region Size
(SIZE)
(see Note 3)
Region
Size
Priority
(PRI)
Priority
Level
SBT0REG0
R
0x1F8F0000
R
64 KB
—
SBT0REG1
R
0x1F8F8000
R
32 KB
—
SBT1REG0
R
0x1D000000
R(4)
R(4)
SBT1REG2
R
0x1F8E0000
R
SBT1REG3
R/W
R/W
SBT1REG4
R/W
R/W
SBT1REG5
R/W
SBT1REG6
SBT2REG2
R/W
R/W
R/W
R/W
SBT3REG0
R(4)
R(4)
R(4)
R(4)
—
0
SBT3RD0
R/W(1)
SBT3WR0
R/W(1)
SBT3REG1
R/W
R/W
R/W
R/W
—
3
SBT3RD1
R/W(1)
SBT3WR1
R/W(1)
SBT3REG2
R/W
R/W
R/W
R/W
0
1
SBT3RD2
R/W(1)
SBT3WR2
R/W(1)
SBT4RD0
R/W(1)
SBT4WR0
R/W(1)
(1)
SBT4REG0
R
0x08000000
R
R(4)
0
—
1
0
SBT4REG1
R/W
R/W
R/W
R/W
—
3
SBT4RD1
R/W
SBT4WR1
R/W(1)
SBT4REG2
R/W
R/W
R/W
R/W
1
2
SBT4RD2
R/W(1)
SBT4WR2
R/W(1)
SBT4REG3
R/W
R/W
R/W
R/W
1
2
SBT4RD3
R/W(1)
SBT4WR3
R/W(1)
SBT4RD4
R/W
(1)
SBT4WR4
R/W(1)
(1)
R/W
R/W
R/W
R/W
1
2
SBT5REG0
R
0x08000000
R
R(4)
—
0
SBT5RD0
R/W
SBT5WR0
R/W(1)
SBT5REG1
R/W
R/W
R/W
R/W
—
3
SBT5RD1
R/W(1)
SBT5WR1
R/W(1)
SBT5REG2
R/W
R/W
R/W
R/W
1
2
SBT5RD2
R/W(1)
SBT5WR2
R/W(1)
SBT5RD3
R/W(1)
SBT5WR3
R/W(1)
SBT5RD4
(1)
SBT5WR4
R/W(1)
SBT5REG3
SBT5REG4
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
SBTxWRy Register
Read
Permission
(GROUP3,
GROUP2,
GROUP1,
GROUP0)
Region Base
(BASE)
(see Note 2)
SBT4REG4
5
SBTxRDy Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
2
2
R/W
R = Read;
R/W = Read/Write;
‘x’ in a register name = 0-13;
‘y’ in a register name = 0-8.
Reset values for these bits are ‘0’, ‘1’, ‘1’, ‘1’, respectively.
The BASE bits must be set to the corresponding Physical Address and right shifted by 10 bits. For Read-only bits, this value is set by hardware on Reset.
The SIZE bits must be set to the corresponding Region Size, based on the following formula: Region Size = 2(SIZE-1) x 1024 bytes. For read-only bits, this value is set by hardware on Reset.
Refer to the Device Memory Map (Figure 4-1) for specific device memory sizes and start addresses.
See Table 4-2 for information on specific target memory size and start addresses.
The SBTxREG1 SFRs are reserved, and therefore, are not listed in this table for this target.
The ‘x' in the SBTxREGy, SBTxRDy, and SBTxWRy registers represents the target protection number and not the actual target number (e.g., for SQI ‘x’ = 13 and not 11, whereas 11 is the actual
target number).
PIC32MZ Graphics (DA) Family
DS60001361J-page 74
TABLE 4-8:
2015-2021 Microchip Technology Inc.
TABLE 4-8:
SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS (CONTINUED)
SBTxREGy Register (see Note 7)
Target
Protection
Number
6
7
9
11
12
DS60001361J-page 75
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
SBT6RD0
R/W(1)
SBT6WR0
R/W(1)
1
SBT6RD2
R/W
(1)
SBT6WR2
R/W(1)
0
SBT7RD0
R/W(1)
SBT7WR0
R/W(1)
3
SBT7RD1
R/W(1)
SBT7WR1
R/W(1)
(1)
SBT7WR2
R/W(1)
Name
Region Size
(SIZE)
(see Note 3)
Region
Size
Priority
(PRI)
Priority
Level
External Memory via EBI and EBI
Module(6)
SBT6REG0
R
0x20000000
R
64 MB
—
0
SBT6REG2
R
0x1F8EC000
R
4 KB
0
System Controller
SBT7REG0
R
0x1F800000
R
—
—
Flash Controller
SBT7REG1
R/W
R/W
R/W
R/W
—
SBT7REG2
SPI1-SPI6
I2C1-I2C5
UART1-UART6
PMP
Timer1-Timer9
PORTA-PORTK
CAN1
R/W
R/W
SBT8REG0
R
SBT8REG1
R/W
SBT9REG0
R
SBT9REG1
R/W
R/W
0
1
SBT7RD2
R/W
0x1F820000
R
64 KB
—
0
SBT8RD0
R/W(1)
SBT8WR0
R/W(1)
R/W
R/W
R/W
—
3
SBT8RD1
R/W(1)
SBT8WR1
R/W(1)
0x1F840000
R
64 KB
—
0
SBT9RD0
R/W(1)
SBT9WR0
R/W(1)
(1)
SBT9WR1
R/W(1)
R/W
R/W
R/W
R/W
—
3
SBT9RD1
R/W
SBT10REG0
R
0x1F860000
R
64 KB
—
0
SBT10RD0
R/W(1)
SBT10WR0
R/W(1)
SBT10REG1
R/W
R/W
R/W
R/W
—
3
SBT10RD1
R/W(1)
SBT10WR1
R/W(1)
SBT11REG0
R
0x1F880000
R
64 KB
—
0
SBT11RD0
R/W(1)
SBT11WR0
R/W(1)
SBT11WR1
R/W(1)
SBT12WR0
R/W(1)
CAN2
Ethernet
SBT11REG1
GLCD
SBT12REG0
R/W
R/W
R/W
R/W
—
3
SBT11RD1
R/W(1)
SBT12RD0
R/W(1)
R
0x1F8EA000
R
4 KB
—
0
GPU
R
0x1F8EB000
R
4 KB
—
0
R/W(1)
R/W(1)
DDR2PHY
R
0x1F8E9000
R
4 KB
—
0
R/W(1)
R/W(1)
0
R/W(1)
R/W(1)
(1)
SBT13WR0
R/W(1)
SBT13WR1
R/W(1)
DDR2SFR
13
Name
Write
Permission
(GROUP3,
GROUP2,
GROUP1,
GROUP0)
Physical
Start
Address
IC1-IC9
OC1-OC9
ADC
Comparator 1
Comparator 2
10
Name
Read
Permission
(GROUP3,
GROUP2,
GROUP1,
GROUP0)
Region Base
(BASE)
(see Note 2)
DMT/WDT
CVREF
PPS Input
PPS Output
Interrupts
DMA
SBTxWRy Register
External Memory via SQI1 and
SQI1
R
0x1F8E8000
R
4 KB
—
SBT13REG0
R
0x30000000
R
64 MB
—
0
SBT13RD0
R/W
SBT13REG1
R
0x1F8E2000
R
4 KB
—
3
SBT13RD1
R/W(1)
R = Read;
R/W = Read/Write;
‘x’ in a register name = 0-13;
‘y’ in a register name = 0-8.
Reset values for these bits are ‘0’, ‘1’, ‘1’, ‘1’, respectively.
The BASE bits must be set to the corresponding Physical Address and right shifted by 10 bits. For Read-only bits, this value is set by hardware on Reset.
The SIZE bits must be set to the corresponding Region Size, based on the following formula: Region Size = 2(SIZE-1) x 1024 bytes. For read-only bits, this value is set by hardware on Reset.
Refer to the Device Memory Map (Figure 4-1) for specific device memory sizes and start addresses.
See Table 4-2 for information on specific target memory size and start addresses.
The SBTxREG1 SFRs are reserved, and therefore, are not listed in this table for this target.
The ‘x' in the SBTxREGy, SBTxRDy, and SBTxWRy registers represents the target protection number and not the actual target number (e.g., for SQI ‘x’ = 13 and not 11, whereas 11 is the actual
target number).
PIC32MZ Graphics (DA) Family
8
Target Description
(see Note 5)
SBTxRDy Register
SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS (CONTINUED)
SBTxREGy Register (see Note 7)
Target
Protection
Number
14
15
16
Target Description
(see Note 5)
DSCTRL
RTCC
USB
Region Base
(BASE)
(see Note 2)
Physical
Start
Address
SBT14REG0
R
SBT14REG1
R/W
Name
SBT15REG0
Name
Read
Permission
(GROUP3,
GROUP2,
GROUP1,
GROUP0)
Name
Write
Permission
(GROUP3,
GROUP2,
GROUP1,
GROUP0)
0
SBT14RD0
R/W(1)
SBT14WR0
R/W(1)
3
SBT14RD1
R/W(1)
SBT14WR1
R/W(1)
SBT15RD0
R/W(1)
SBT15WR0
R/W(1)
Region Size
(SIZE)
(see Note 3)
Region
Size
Priority
(PRI)
Priority
Level
0x1F8C0000
R
4 KB
—
R/W
R/W
R/W
—
0x1F8E0000
R
4 KB
—
SBTxWRy Register
0
(1)
R/W(1)
Crypto
R
0x1F8E5000
R
4 KB
—
0
R/W
RNG
R
0x1F8E6000
R
4 KB
—
0
R/W(1)
R/W(1)
SDHC
R
0x1F8EC000
R
4 KB
—
0
R/W(1)
R/W(1)
0
R/W
(1)
SBT16WR0
R/W(1)
(1)
External Memory via DDR2 and
DDR2 Targets 3 and 4
SBT16REG0
R
0x08000000
R
R(4)
—
SBT16RD0
SBT16REG1
R/W
R/W
R/W
R/W
—
3
SBT16RD1
R/W
SBT16WR1
R/W(1)
SBT16REG2
R/W
R/W
R/W
R/W
1
2
SBT16RD2
R/W(1)
SBT16WR2
R/W(1)
SBT16REG3
R/W
R/W
R/W
R/W
1
2
SBT16RD3
R/W(1)
SBT16WR3
R/W(1)
SBT16RD4
(1)
SBT16WR4
R/W(1)
SBT16REG4
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
R
SBTxRDy Register
R/W
R/W
R/W
R/W
1
2
R/W
R = Read;
R/W = Read/Write;
‘x’ in a register name = 0-13;
‘y’ in a register name = 0-8.
Reset values for these bits are ‘0’, ‘1’, ‘1’, ‘1’, respectively.
The BASE bits must be set to the corresponding Physical Address and right shifted by 10 bits. For Read-only bits, this value is set by hardware on Reset.
The SIZE bits must be set to the corresponding Region Size, based on the following formula: Region Size = 2(SIZE-1) x 1024 bytes. For read-only bits, this value is set by hardware on Reset.
Refer to the Device Memory Map (Figure 4-1) for specific device memory sizes and start addresses.
See Table 4-2 for information on specific target memory size and start addresses.
The SBTxREG1 SFRs are reserved, and therefore, are not listed in this table for this target.
The ‘x' in the SBTxREGy, SBTxRDy, and SBTxWRy registers represents the target protection number and not the actual target number (e.g., for SQI ‘x’ = 13 and not 11, whereas 11 is the actual
target number).
PIC32MZ Graphics (DA) Family
DS60001361J-page 76
TABLE 4-8:
2015-2021 Microchip Technology Inc.
SBFLAG0
90_
0510
SBFLAG1
91_
0510
SBFLAG2
92_
0510
SBFLAG3
Legend:
Bits
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Register
Name
8F_
0510
SYSTEM BUS VIOLATION FLAG REGISTER MAP
Bit Range
Virtual Address
(BFxx_#)
2015-2021 Microchip Technology Inc.
TABLE 4-9:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
T0PGV0
T3PGV
T6PGV
T2PGV
T5PGV
T4PGV
T1PGV
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
T0PGV1
T12PGV
T11PGV
T10PGV
T9PGV
T8PGV
T7PGV
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
T0PGV2
T15PGV
T14PGV
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T0PGV3
T13PGV 0000
—
0000
T16PGV 0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC32MZ Graphics (DA) Family
DS60001361J-page 77
8024
SBT0ELOG2
8028
SBT0ECON
8030
SBT0ECLRS
8038 SBT0ECLRM
8040
SBT0REG0
8050
SBT0RD0
8058
SBT0WR0
8060
SBT0REG1
8070
SBT0RD1
8078
SBT0WR1
2015-2021 Microchip Technology Inc.
Legend:
Note:
Bits
31/15
31:16 MULTI
30/14
29/13
28/12
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
All
Resets
Register
Name
SBT0ELOG1
Bit Range
Virtual Address
(BF8F_#)
8020
SYSTEM BUS TARGET PROTECTION GROUP 0 (T0PGV0 - T0PGV3) REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
—
—
—
xxxx
—
—
xxxx
31:16
—
—
GROUP
CLEAR 0000
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
PRI
—
31:16
GROUP1 GROUP0 xxxx
—
—
BASE
xxxx
SIZE
—
—
—
xxxx
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
GROUP3
GROUP2
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP1 GROUP0 xxxx
BASE
15:0
0000
CLEAR 0000
BASE
15:0
0000
0000
GROUP1 GROUP0 xxxx
—
—
xxxx
GROUP1 GROUP0 xxxx
PIC32MZ Graphics (DA) Family
DS60001361J-page 78
TABLE 4-10:
Virtual Address
(BF8F_#)
Register
Name
8420
SBT1ELOG1
8424
SBT1ELOG2
8428
SBT1ECON
8430
SBT1ECLRS
8450
SBT1RD0
8458
SBT1WR0
8480
SBT1REG2
8490
SBT1RD2
8498
SBT1WR2
84A0
SBT1REG3
DS60001361J-page 79
84B0
SBT1RD3
84B8
SBT1WR3
84C0
SBT1REG4
84D0
SBT1RD4
84D8
SBT1WR4
Legend:
Note:
30/14
29/13
28/12
MULTI
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP
0000
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Graphics (DA) Family
SBT1REG0
31:16
31/15
All
Resets
Bits
8438 SBT1ECLRM
8440
SYSTEM BUS TARGET PROTECTION GROUP 1 REGISTER MAP
Bit Range
2015-2021 Microchip Technology Inc.
TABLE 4-11:
Virtual Address
(BF8F_#)
Register
Name
84E0
SBT1REG5
SYSTEM BUS TARGET PROTECTION GROUP 1 REGISTER MAP (CONTINUED)
84F0
SBT1RD5
84F8
SBT1WR5
8500
SBT1REG6
8510
SBT1RD6
8518
SBT1WR6
8520
SBT1REG7
8530
SBT1RD7
8538
SBT1WR7
8540
SBT1REG8
8550
SBT1RD8
8558
SBT1WR8
2015-2021 Microchip Technology Inc.
Legend:
Note:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
PRI
—
31:16
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
xxxx
—
—
—
xxxx
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
All
Resets
Bit Range
Bits
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Graphics (DA) Family
DS60001361J-page 80
TABLE 4-11:
SBT2ELOG1
8824
SBT2ELOG2
8828
SBT2ECON
8830
SBT2ECLRS
8840
SBT2REG0
8850
SBT2RD0
8858
SBT2WR0
8860
SBT2REG1
8870
SBT2RD1
8878
SBT2WR1
8880
SBT2REG2
DS60001361J-page 81
8890
SBT2RD2
8898
SBT2WR2
Legend:
Note:
31/15
30/14
29/13
28/12
MULTI
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP
0000
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Graphics (DA) Family
8838 SBT2ECLRM
31:16
Bits
All
Resets
Register
Name
8820
SYSTEM BUS TARGET PROTECTION GROUP 2 REGISTER MAP
Bit Range
Virtual Address
(BF8F_#)
2015-2021 Microchip Technology Inc.
TABLE 4-12:
8C24 SBT3ELOG2
8C28
SBT3ECON
8C30 SBT3ECLRS
8C38 SBT3ECLRM
8C40
SBT3REG0
8C50
SBT3RD0
8C58
SBT3WR0
8C60
SBT3REG1
2015-2021 Microchip Technology Inc.
8C70
SBT3RD1
8C78
SBT3WR1
8C80
SBT3REG2
8C90
SBT3RD2
8C98
SBT3WR2
Legend:
Note:
31:16
Bits
31/15
30/14
29/13
28/12
MULTI
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
All
Resets
Bit Range
Register
Name
Virtual Address
(BF8F_#)
8C20 SBT3ELOG1
SYSTEM BUS TARGET PROTECTION GROUP 3 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP
0000
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Graphics (DA) Family
DS60001361J-page 82
TABLE 4-13:
SBT4ELOG1
9024
SBT4ELOG2
9028
SBT4ECON
9030
SBT4ECLRS
9040
SBT4REG0
9050
SBT4RD0
9058
SBT4WR0
9060
SBT4REG1
9070
SBT4RD1
9078
SBT4WR1
9080
SBT4REG2
DS60001361J-page 83
9090
SBT4RD2
9098
SBT4WR2
90A0
SBT4REG3
31/15
30/14
29/13
28/12
MULTI
—
—
—
15:0
27/11
26/10
25/9
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP
0000
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
BASE
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
PRI
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
BASE
BASE
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
SIZE
31:16
15:0
—
BASE
15:0
31:16
Legend:
Note:
24/8
xxxx
SIZE
—
—
—
xxxx
PIC32MZ Graphics (DA) Family
9038 SBT4ECLRM
31:16
Bits
All
Resets
Register
Name
9020
SYSTEM BUS TARGET PROTECTION GROUP 4 REGISTER MAP
Bit Range
Virtual Address
(BF8F_#)
2015-2021 Microchip Technology Inc.
TABLE 4-14:
90B8
SBT4WR3
90C0
SBT4REG4
90D0
SBT4RD4
90D8
SBT4WR4
Legend:
Note:
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
19/3
18/2
17/1
16/0
All
Resets
Register
Name
SBT4RD3
Bit Range
Virtual Address
(BF8F_#)
90B0
SYSTEM BUS TARGET PROTECTION GROUP 4 REGISTER MAP (CONTINUED)
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Graphics (DA) Family
DS60001361J-page 84
TABLE 4-14:
2015-2021 Microchip Technology Inc.
SBT5ELOG1
9424
SBT5ELOG2
9428
SBT5ECON
9430
SBT5ECLRS
9440
SBT5REG0
9450
SBT5RD0
9458
SBT5WR0
9460
SBT5REG1
9470
SBT5RD1
9478
SBT5WR1
9480
SBT5REG2
DS60001361J-page 85
9490
SBT5RD2
9498
SBT5WR2
Legend:
Note:
31/15
30/14
29/13
28/12
MULTI
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP
0000
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Graphics (DA) Family
9438 SBT5ECLRM
31:16
Bits
All
Resets
Register
Name
9420
SYSTEM BUS TARGET PROTECTION GROUP 5 REGISTER MAP
Bit Range
Virtual Address
(BF8F_#)
2015-2021 Microchip Technology Inc.
TABLE 4-15:
94B0
SBT5RD3
94B8
SBT5WR3
94C0
SBT5REG4
94D0
SBT5RD4
94D8
SBT5WR4
Legend:
Note:
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
PRI
—
31:16
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
xxxx
—
—
—
xxxx
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
All
Resets
Register
Name
SBT5REG3
Bit Range
Virtual Address
(BF8F_#)
94A0
SYSTEM BUS TARGET PROTECTION GROUP 5 REGISTER MAP (CONTINUED)
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Graphics (DA) Family
DS60001361J-page 86
TABLE 4-15:
2015-2021 Microchip Technology Inc.
SBT6ELOG1
9824
SBT6ELOG2
9828
SBT6ECON
9830
SBT6ECLRS
9840
SBT6REG0
9850
SBT6RD0
9858
SBT6WR0
9860
SBT6REG1
9870
SBT6RD1
9878
SBT6WR1
Legend:
Note:
31/15
30/14
29/13
28/12
MULTI
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP
0000
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
DS60001361J-page 87
PIC32MZ Graphics (DA) Family
9838 SBT6ECLRM
31:16
Bits
All
Resets
Register
Name
9820
SYSTEM BUS TARGET PROTECTION GROUP 6 REGISTER MAP
Bit Range
Virtual Address
(BF8F_#)
2015-2021 Microchip Technology Inc.
TABLE 4-16:
8424
SBT7ELOG2
8428
SBT7ECON
8430
SBT7ECLRS
8438 SBT7ECLRM
8440
SBT7REG0
8450
SBT7RD0
8458
SBT7WR0
8460
SBT7REG1
2015-2021 Microchip Technology Inc.
8470
SBT7RD1
8478
SBT7WR1
8480
SBT7REG2
8490
SBT7RD2
8498
SBT7WR2
Legend:
Note:
31:16
Bits
31/15
30/14
29/13
28/12
MULTI
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
All
Resets
Register
Name
SBT7ELOG1
Bit Range
Virtual Address
(BF90_#)
8420
SYSTEM BUS TARGET PROTECTION GROUP 7 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP
0000
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Graphics (DA) Family
DS60001361J-page 88
TABLE 4-17:
SBT8ELOG1
8824
SBT8ELOG2
8828
SBT8ECON
8830
SBT8ECLRS
8840
SBT8REG0
8850
SBT8RD0
8858
SBT8WR0
8860
SBT8REG1
8870
SBT8RD1
8878
SBT8WR1
Legend:
Note:
31/15
30/14
29/13
28/12
MULTI
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP
0000
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
DS60001361J-page 89
PIC32MZ Graphics (DA) Family
8838 SBT8ECLRM
31:16
Bits
All
Resets
Register
Name
8820
SYSTEM BUS TARGET PROTECTION GROUP 8 REGISTER MAP
Bit Range
Virtual Address
(BF90_#)
2015-2021 Microchip Technology Inc.
TABLE 4-18:
8C24 SBT9ELOG2
8C28
SBT9ECON
8C30 SBT9ECLRS
8C38 SBT9ECLRM
8C40
SBT9REG0
8C50
SBT9RD0
8C58
SBT9WR0
8C60
SBT9REG1
8C70
SBT9RD1
8C78
SBT9WR1
2015-2021 Microchip Technology Inc.
Legend:
Note:
31:16
Bits
31/15
30/14
29/13
28/12
MULTI
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
All
Resets
Bit Range
Register
Name
Virtual Address
(BF90_#)
8C20 SBT9ELOG1
SYSTEM BUS TARGET PROTECTION GROUP 9 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP
0000
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Graphics (DA) Family
DS60001361J-page 90
TABLE 4-19:
9020 SBT10ELOG1
9024 SBT10ELOG2
9028 SBT10ECON
9030 SBT10ECLRS
9040
SBT10REG0
9050
SBT10RD0
9058
SBT10WR0
9060
SBT10REG1
9070
SBT10RD1
9078
SBT10WR1
Legend:
Note:
31:16
31/15
30/14
29/13
28/12
MULTI
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
All
Resets
Bits
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP
0000
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
DS60001361J-page 91
PIC32MZ Graphics (DA) Family
9038 SBT10ECLRM
SYSTEM BUS TARGET PROTECTION GROUP 10 REGISTER MAP
Bit Range
Register
Name
Virtual Address
(BF90_#)
2015-2021 Microchip Technology Inc.
TABLE 4-20:
9424 SBT11ELOG2
9428
SBT11ECON
9430 SBT11ECLRS
9438 SBT11ECLRM
9440
SBT11REG0
9450
SBT11RD0
9458
SBT11WR0
9460
SBT11REG1
9470
SBT11RD1
9478
SBT11WR1
2015-2021 Microchip Technology Inc.
Legend:
Note:
31:16
Bits
31/15
30/14
29/13
28/12
MULTI
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
All
Resets
Bit Range
Register
Name
Virtual Address
(BF90_#)
9420 SBT11ELOG1
SYSTEM BUS TARGET PROTECTION GROUP 11 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP
0000
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Graphics (DA) Family
DS60001361J-page 92
TABLE 4-21:
9820 SBT12ELOG1
9824 SBT12ELOG2
9828 SBT12ECON
9830 SBT12ECLRS
9840
SBT12REG0
9850
SBT12RD0
9858
SBT12WR0
Legend:
Note:
31:16
31/15
30/14
29/13
28/12
MULTI
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
All
Resets
Bits
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP
0000
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
DS60001361J-page 93
PIC32MZ Graphics (DA) Family
9838 SBT12ECLRM
SYSTEM BUS TARGET PROTECTION GROUP 12 REGISTER MAP
Bit Range
Register
Name
Virtual Address
(BF90_#)
2015-2021 Microchip Technology Inc.
TABLE 4-22:
8424 SBT13ELOG2
8428 SBT13ECON
8430 SBT13ECLRS
8438 SBT13ECLRM
8440
SBT13REG0
8450
SBT13RD0
8458
SBT13WR0
8460
SBT13REG1
8470
SBT13RD1
8478
SBT13WR1
2015-2021 Microchip Technology Inc.
Legend:
Note:
31:16
Bits
31/15
30/14
29/13
28/12
MULTI
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
All
Resets
Bit Range
Register
Name
Virtual Address
(BF91_#)
8420 SBT13ELOG1
SYSTEM BUS TARGET PROTECTION GROUP 13 REGISTER MAP
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP
0000
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Graphics (DA) Family
DS60001361J-page 94
TABLE 4-23:
Virtual Address
(BF91_#)
8820 SBT14ELOG1
8824 SBT14ELOG2
8828 SBT14ECON
8830 SBT14ECLRS
8838 SBT14ECLRM
SBT14REG0
8850
SBT14RD0
8858
SBT14WR0
8860
SBT14REG1
8870
SBT14RD1
8878
SBT14WR1
Legend:
Note:
30/14
29/13
28/12
MULTI
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
All
Resets
Bit Range
31:16
31/15
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP
0000
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
DS60001361J-page 95
PIC32MZ Graphics (DA) Family
8840
SYSTEM BUS TARGET PROTECTION GROUP 14 REGISTER MAP
Bits
Register
Name
2015-2021 Microchip Technology Inc.
TABLE 4-24:
Virtual Address
(BF91_#)
SYSTEM BUS TARGET PROTECTION GROUP 15 REGISTER MAP
8C20 SBT15ELOG1
8C24 SBT15ELOG2
8C28 SBT15ECON
8C30 SBT15ECLRS
8C38 SBT15ECLRM
8C40 SBT15REG0
8C50
SBT15RD0
8C58
SBT15WR0
Legend:
Note:
31:16
31/15
30/14
29/13
28/12
MULTI
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
All
Resets
Bit Range
Register
Name
Bits
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP
0000
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
PRI
—
—
—
—
xxxx
—
—
—
xxxx
31:16
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Graphics (DA) Family
DS60001361J-page 96
TABLE 4-25:
2015-2021 Microchip Technology Inc.
Virtual Address
(BF92_#)
SYSTEM BUS TARGET PROTECTION GROUP 16 REGISTER MAP
C420 SBT16ELOG1
C424 SBT16ELOG2
C428 SBT16ECON
C430 SBT16ECLRS
C438 SBT16ECLRM
SBT16REG0
C450
SBT16RD0
C458
SBT16WR0
C460
SBT16REG1
C470
SBT16RD1
C478
SBT16WR1
C480
SBT16REG2
C490
SBT16RD2
C498
SBT16WR2
DS60001361J-page 97
C4A0 SBT16REG3
C4B0
SBT16RD3
C4B8
SBT16WR3
Legend:
Note:
31:16
30/14
29/13
28/12
MULTI
—
—
—
15:0
27/11
26/10
25/9
24/8
CODE
23/7
—
INITID
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
REGION
—
17/1
16/0
—
—
CMD
All
Resets
31/15
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GROUP
0000
31:16
—
—
—
—
—
—
—
ERRP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLEAR
0000
—
—
—
xxxx
—
—
—
xxxx
31:16
BASE
15:0
BASE
PRI
—
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PRI
—
31:16
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
BASE
15:0
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Graphics (DA) Family
C440
Bit Range
Bits
Register
Name
2015-2021 Microchip Technology Inc.
TABLE 4-26:
Virtual Address
(BF92_#)
SYSTEM BUS TARGET PROTECTION GROUP 16 REGISTER MAP (CONTINUED)
C4C0 SBT16REG4
C4D0
SBT16RD4
C4D8
SBT16WR4
Legend:
Note:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
PRI
—
31:16
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
xxxx
—
—
—
xxxx
BASE
15:0
BASE
xxxx
SIZE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For reset values listed as ‘xxxx’, please refer to Table 4-8 for the actual reset values.
All
Resets
Bit Range
Register
Name
Bits
—
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
—
—
—
—
xxxx
GROUP3 GROUP2 GROUP1 GROUP0 xxxx
PIC32MZ Graphics (DA) Family
DS60001361J-page 98
TABLE 4-26:
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 4-2:
Bit
Range
31:24
23:16
15:8
7:0
SBFLAG0: SYSTEM BUS STATUS FLAG REGISTER 0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
T0PGV0(1)
T3PGV
T6PGV
T2PGV
T5PGV
T4PGV
T1PGV
Legend:
R = Readable bit
-n = Value at POR
bit 31-7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Unimplemented: Read as ‘0’
T0PGV0: Target 0 (System Bus 0) Permission Group Violation Status bit(1)
1 = Target 0 (System Bus 0) is reporting a Permission Group (PG) violation
0 = Target 0 (System Bus 0) is not reporting a PG violation
T3PGV: Target 3 (RAM Bank 2) Permission Group Violation Status bit
1 = Target 3 is reporting a Permission Group (PG) violation
0 = Target 3 is not reporting a PG violation
T6PGV: Target 6 (EBI) Permission Group Violation Status bit
1 = Target 6 is reporting a Permission Group (PG) violation
0 = Target 6 is not reporting a PG violation
T2PGV: Target 2 (RAM Bank 1) Permission Group Violation Status bit
1 = Target 2 is reporting a Permission Group (PG) violation
0 = Target 2 is not reporting a PG violation
T5GV: Target 5 (DDR2 Target 1 and Target 2) Permission Group Violation Status bit
1 = Target 5 is reporting a Permission Group (PG) violation
0 = Target 5 is not reporting a PG violation
T4PGV: Target 4 (DDR2 Target 0) Permission Group Violation Status bit
1 = Target 4 is reporting a Permission Group (PG) violation
0 = Target 4 is not reporting a PG violation
T1PGV: Target 1 (Flash Memory) Permission Group Violation Status bit
1 = Target 1 is reporting a Permission Group (PG) violation
0 = Target 1 is not reporting a PG violation
Note 1:
System Bus 0 represents an internal sub-system element and should be treated as a general System Bus
violation.
Note:
All errors are cleared at the source (i.e., SBTxELOG1, SBTxELOG2, SBTxECLRS, or SBTxECLRM
registers).
2015-2021 Microchip Technology Inc.
DS60001361J-page 99
PIC32MZ Graphics (DA) Family
REGISTER 4-3:
Bit
Range
31:24
23:16
15:8
7:0
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
T0PGV1(1)
T12PGV(2)
T11PGV
T10PGV
T9PGV
T8PGV
T7PGV
Legend:
R = Readable bit
-n = Value at POR
bit 31-7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
Note:
SBFLAG1: SYSTEM BUS STATUS FLAG REGISTER 1
Bit
31/23/15/7
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Unimplemented: Read as ‘0’
T0PGV1: Target 1 (System Bus 1) Permission Group Violation Status bit(1)
1 = Target 0 (System Bus 1) is reporting a Permission Group (PG) violation
0 = Target 0 (System Bus 1) is not reporting a PG violation
T12PGV: Target Group 12 (GLCD, GPU, DDR2PHY, DDR2SFR) Permission Group Violation Status bit(2)
1 = Target group 12 is reporting a Permission Group (PG) violation
0 = Target group 12 is not reporting a PG violation
T11PGV: Target 11 (PB5) Permission Group Violation Status bit
1 = Target 11 is reporting a Permission Group (PG) violation
0 = Target 11 is not reporting a PG violation
T10PGV: Target 10 (PB4) Permission Group Violation Status bit
1 = Target 10 is reporting a Permission Group (PG) violation
0 = Target 10 is not reporting a PG violation
T9PGV: Target 9 (PB3) Permission Group Violation Status bit
1 = Target 9 is reporting a Permission Group (PG) violation
0 = Target 9 is not reporting a PG violation
T8PGV: Target 8 (PB2) Permission Group Violation Status bit
1 = Target 8 is reporting a Permission Group (PG) violation
0 = Target 8 is not reporting a PG violation
T7PGV: Target 7 (PB1) Permission Group Violation Status bit
1 = Target 7 is reporting a Permission Group (PG) violation
0 = Target 7 is not reporting a PG violation
System Bus 1 represents an internal sub-system element and should be treated as a general System Bus
violation.
This bit reports violations on Targets 14 (GLCD), 18 (GPU), 20 (DDR2PHY) and 21 (DDR2SFR).
All errors are cleared at the source (i.e., SBTxELOG1, SBTxELOG2, SBTxECLRS, or SBTxECLRM
registers).
DS60001361J-page 100
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 4-4:
Bit
Range
31:24
23:16
15:8
7:0
SBFLAG2: SYSTEM BUS STATUS FLAG REGISTER 2
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
T0PGV2(1)
T15PGV(2)
T14PGV
T13PGV
Legend:
R = Readable bit
-n = Value at POR
bit 31-4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
Note:
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Unimplemented: Read as ‘0’
T0PGV2: Target 0 (System Bus 2) Permission Group Violation Status bit(1)
1 = Target 0 (System Bus 2) is reporting a Permission Group (PG) violation
0 = Target 0 (System Bus 2) is not reporting a PG violation
T15PGV: Target Group 15 (USB, Crypto, RNG, SDHC) Permission Group Violation Status bit(2)
1 = Target group 15 is reporting a Permission Group (PG) violation
0 = Target group 15 is not reporting a PG violation
T14PGV: Target 14 (PB6) Permission Group Violation Status bit
1 = Target 14 is reporting a Permission Group (PG) violation
0 = Target 14 is not reporting a PG violation
T13PGV: Target 13 (SQI) Permission Group Violation Status bit
1 = Target 13 is reporting a Permission Group (PG) violation
0 = Target 13 is not reporting a PG violation
System Bus 2 represents an internal sub-system element and should be treated as a general System Bus violation.
This bit reports violations on Targets 10 (USB), 12 (Crypto), 13 (RNG) and 19 (SDHC).
All errors are cleared at the source (i.e., SBTxELOG1, SBTxELOG2, SBTxECLRS, or SBTxECLRM registers).
2015-2021 Microchip Technology Inc.
DS60001361J-page 101
PIC32MZ Graphics (DA) Family
REGISTER 4-5:
Bit
Range
31:24
23:16
15:8
7:0
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
T0PGV3(1)
T16PGV
Legend:
R = Readable bit
-n = Value at POR
bit 31-2
bit 1
bit 0
SBFLAG3: SYSTEM BUS STATUS FLAG REGISTER 3
Bit
31/23/15/7
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Unimplemented: Read as ‘0’
T0PGV3: Target 0 (System Bus 3) Permission Group Violation Status bit(1)
1 = Target 0 (System Bus 3) is reporting a Permission Group (PG) violation
0 = Target 0 (System Bus 3) is not reporting a PG violation
T16PGV: Target 16 (DDR2 Target 3 and Target 4) Permission Group Violation Status bit
1 = Target 16 is reporting a Permission Group (PG) violation
0 = Target 16 is not reporting a PG violation
Note 1:
System Bus 3 represents an internal sub-system element and should be treated as a general System Bus
violation.
Note:
All errors are cleared at the source (i.e., SBTxELOG1, SBTxELOG2, SBTxECLRS, or SBTxECLRM
registers).
DS60001361J-page 102
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 4-6:
Bit
Range
SBTxELOG1: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 1
(‘x’ = 0-13)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0, C
U-0
U-0
U-0
R/W-0, C
R/W-0, C
R/W-0, C
R/W-0, C
MULTI
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
31:24
23:16
15:8
CODE
INITID
7:0
REGION
U-0
—
CMD
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
U-0
MULTI: Multiple Permission Violations Status bit
This bit is cleared by writing a ‘1’.
1 = Multiple errors have been detected
0 = No multiple errors have been detected
bit 30-28 Unimplemented: Read as ‘0’
bit 27-24 CODE: Error Code bits
Indicates the type of error that was detected. These bits are cleared by writing a ‘1’.
1111 = Reserved
1101 = Reserved
•
•
•
0011 = Permission violation
0010 = Reserved
0001 = Reserved
0000 = No error
bit 23-16 Unimplemented: Read as ‘0’
Note:
Refer to Table 4-8 for the list of available targets and their descriptions.
2015-2021 Microchip Technology Inc.
DS60001361J-page 103
PIC32MZ Graphics (DA) Family
REGISTER 4-6:
bit 15-8
SBTxELOG1: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 1
(‘x’ = 0-13) (CONTINUED)
INITID: Initiator ID of Requester bits
11111111 = Reserved
•
•
•
00001111 = Reserved
00001110 = SDHC
00001101 = GPU
00001100 = GLCD
00001011 = Crypto Engine
00001010 = Flash Controller
00001001 = SQI1
00001000 = CAN2
00000111 = CAN1
00000110 = Ethernet Write
00000101 = Ethernet Read
00000100 = USB
00000011 = DMA Write
00000010 = DMA Read
00000001 = CPU
00000000 = Reserved
bit 7-4
REGION: Requested Region Number bits
1111 - 0000 = Target’s region that reported a permission group violation
bit 3
Unimplemented: Read as ‘0’
bit 2-0
CMD: Transaction Command of the Requester bits
111 = Reserved
110 = Reserved
101 = Write (a non-posted write)
100 = Reserved
011 = Read (a locked read caused by a Read-Modify-Write transaction)
010 = Read
001 = Write
000 = Idle
Note:
Refer to Table 4-8 for the list of available targets and their descriptions.
DS60001361J-page 104
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 4-7:
Bit
Range
31:24
23:16
15:8
7:0
SBTxELOG2: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 2 (‘x’ = 0-13)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R-0
R-0
—
—
—
—
—
—
GROUP
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-3
Unimplemented: Read as ‘0’
bit 1-0
GROUP: Requested Permissions Group bits
11 = Group 3
10 = Group 2
01 = Group 1
00 = Group 0
Note:
Refer to Table 4-8 for the list of available targets and their descriptions.
REGISTER 4-8:
Bit
Range
31:24
23:16
15:8
7:0
SBTxECON: SYSTEM BUS TARGET ‘x’ ERROR CONTROL REGISTER
(‘x’ = 0-13)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
ERRP
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-25 Unimplemented: Read as ‘0’
bit 24
ERRP: Error Control bit
1 = Report protection group violation errors
0 = Do not report protection group violation errors
bit 23-0
Unimplemented: Read as ‘0’
Note:
Refer to Table 4-8 for the list of available targets and their descriptions.
2015-2021 Microchip Technology Inc.
DS60001361J-page 105
PIC32MZ Graphics (DA) Family
REGISTER 4-9:
Bit
Range
31:24
23:16
15:8
7:0
SBTxECLRS: SYSTEM BUS TARGET ‘x’ SINGLE ERROR CLEAR REGISTER
(‘x’ = 0-13)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
CLEAR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-1
Unimplemented: Read as ‘0’
bit 0
CLEAR: Clear Single Error on Read bit
A single error as reported via SBTxELOG1 and SBTxELOG2 is cleared by a read of this register.
Note:
Refer to Table 4-8 for the list of available targets and their descriptions.
REGISTER 4-10:
Bit
Range
31:24
23:16
15:8
7:0
SBTxECLRM: SYSTEM BUS TARGET ‘x’ MULTIPLE ERROR CLEAR REGISTER
(‘x’ = 0-13)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
CLEAR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-1
Unimplemented: Read as ‘0’
bit 0
CLEAR: Clear Multiple Errors on Read bit
Multiple errors as reported via SBTxELOG1 and SBTxELOG2 is cleared by a read of this register.
Note:
Refer to Table 4-8 for the list of available targets and their descriptions.
DS60001361J-page 106
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 4-11:
Bit
Range
31:24
23:16
15:8
7:0
SBTxREGy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ REGISTER
(‘x’ = 0-13; ‘y’ = 0-8)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W0
R/W-0
R/W0
R/W-0
R/W0
R/W-0
R/W0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
U-0
BASE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BASE
R/W-0
R/W-0
BASE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SIZE
PRI
—
U-0
U-0
U-0
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-10 BASE: Region Base Address bits
bit 9
PRI: Region Priority Level bit
1 = Level 2
0 = Level 1
bit 8
Unimplemented: Read as ‘0’
bit 7-3
SIZE: Region Size bits
Permissions for a region are only active is the SIZE is non-zero.
11111 = Region size = 2(SIZE – 1) x 1024 (bytes)
•
•
•
00001 = Region size = 2(SIZE – 1) x 1024 (bytes)
00000 = Region is not present
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
2:
Refer to Table 4-8 for the list of available targets and their descriptions.
For some target regions, certain bits in this register are read-only with preset values. See Table 4-8 for
more information.
2015-2021 Microchip Technology Inc.
DS60001361J-page 107
PIC32MZ Graphics (DA) Family
REGISTER 4-12:
Bit
Range
31:24
23:16
15:8
7:0
SBTxRDy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ READ PERMISSIONS
REGISTER (‘x’ = 0-13; ‘y’ = 0-8)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-1
R/W-1
R/W-1
—
—
—
—
GROUP3
GROUP2
GROUP1
GROUP0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-4
Unimplemented: Read as ‘0’
bit 3
Group3: Group3 Read Permissions bits
1 = Privilege Group 3 has read permission
0 = Privilege Group 3 does not have read permission
bit 2
Group2: Group2 Read Permissions bits
1 = Privilege Group 2 has read permission
0 = Privilege Group 2 does not have read permission
bit 1
Group1: Group1 Read Permissions bits
1 = Privilege Group 1 has read permission
0 = Privilege Group 1 does not have read permission
bit 0
Group0: Group0 Read Permissions bits
1 = Privilege Group 0 has read permission
0 = Privilege Group 0 does not have read permission
Note 1:
2:
Refer to Table 4-8 for the list of available targets and their descriptions.
For some target regions, certain bits in this register are read-only with preset values. See Table 4-8 for
more information.
DS60001361J-page 108
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 4-13:
Bit
Range
31:24
23:16
15:8
7:0
SBTxWRy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ WRITE PERMISSIONS
REGISTER (‘x’ = 0-13; ‘y’ = 0-8)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-1
R/W-1
R/W-1
—
—
—
—
GROUP3
GROUP2
GROUP1
GROUP0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-4
Unimplemented: Read as ‘0’
bit 3
Group3: Group 3 Write Permissions bits
1 = Privilege Group 3 has write permission
0 = Privilege Group 3 does not have write permission
bit 2
Group2: Group 2 Write Permissions bits
1 = Privilege Group 2 has write permission
0 = Privilege Group 2 does not have write permission
bit 1
Group1: Group 1 Write Permissions bits
1 = Privilege Group 1 has write permission
0 = Privilege Group 1 does not have write permission
bit 0
Group0: Group 0 Write Permissions bits
1 = Privilege Group 0 has write permission
0 = Privilege Group 0 does not have write permission
Note 1:
2:
Refer to Table 4-8 for the list of available targets and their descriptions.
For some target regions, certain bits in this register are read-only with preset values. See Table 4-8 for
more information.
2015-2021 Microchip Technology Inc.
DS60001361J-page 109
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 110
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
5.0
Note:
FLASH PROGRAM MEMORY
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 52. “Flash
Program Memory with Support for Live
Update” (DS60001193), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
PIC32MZ DA devices contain an internal Flash
program memory for executing user code, which
includes the following features:
•
•
•
•
Two Flash banks for live update support
Dual boot support
Write protection for program and Boot Flash
ECC support
RTSP is performed by software executing from either
Flash or RAM memory. Information about RTSP
techniques is available in Section 52. “Flash
Program Memory with Support for Live Update”
(DS60001193) in the “PIC32 Family Reference
Manual”.
EJTAG is performed using the EJTAG port of the
device and an EJTAG capable programmer.
ICSP is performed using a serial data connection to the
device and allows much faster programming times than
RTSP.
The EJTAG and ICSP methods are described in the
“PIC32
Flash
Programming
Specification”
(DS60001145), which is available for download from
the Microchip website.
Note:
In PIC32MZ DA devices, the Flash page
size is 16 KB (4K IW) and the row size is
2 KB (512 IW).
There are three methods by which the user can
program this memory:
• Run-Time Self-Programming (RTSP)
• EJTAG Programming
• In-Circuit Serial Programming™ (ICSP™)
2015-2021 Microchip Technology Inc.
DS60001361J-page 111
Flash Control Registers
Virtual Address
(BF80_#)
TABLE 5-1:
0610
NVMKEY
0620
NVMADDR(1)
0630 NVMDATA0
0640 NVMDATA1
0650 NVMDATA2
0660 NVMDATA3
NVMSRC
ADDR
31/15
06A0 NVMCON2(1)
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
WR
WREN
WRERR
LVDERR
—
—
—
—
PFSWAP
BFSWAP
—
—
31:16
15:0
31:16
17/1
16/0
—
—
—
NVMOP
31:16
0000
0000
0000
0000
0000
NVMDATA0
15:0
31:16
0000
0000
NVMDATA1
15:0
31:16
0000
0000
NVMDATA2
15:0
31:16
0000
0000
NVMDATA3
15:0
31:16
0000
0000
NVMSRCADDR
15:0
—
—
—
—
—
—
—
0000
—
PWP
8000
PWP
—
—
—
—
—
—
—
15:0 LBWPULOCK
—
—
LBWP4
LBWP3
LBWP2
LBWP1
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
0000
0000
NVMADDR
15:0
31:16
18/2
NVMKEY
31:16 PWPULOCK
0680 NVMPWP(1)
15:0
0690 NVMBWP(1)
30/14
All Resets
Bit Range
Register
Name
Bits
0600 NVMCON(1)
0670
FLASH CONTROLLER REGISTER MAP
0000
—
—
—
—
—
—
—
—
—
UBWP4
UBWP3
UBWP2
UBWP1
—
—
—
—
—
—
—
00xx
SWAPLOCK
—
—
—
—
—
—
0000
LBWP0 UBWPULOCK
—
—
0000
UBWP0 9FDF
2015-2021 Microchip Technology Inc.
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more
information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 112
5.1
PIC32MZ Graphics (DA) Family
REGISTER 5-1:
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
R/W-0, HC
(1)
WR
R/W-0
7:0
NVMCON: PROGRAMMING CONTROL REGISTER
—
R/W-0
(1)
WREN
—
—
—
—
—
—
R-0, HS, HC
(1)
R-0, HS, HC
(1)
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
WRERR
R/W-0
PFSWAP(3) BFSWAP(3,4)
Legend:
LVDERR
HS = Hardware Set
NVMOP
HC = Cleared by Hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
WR: Write Control bit(1)
This bit cannot be cleared and can be set only when WREN = 1 and the unlock sequence has been
performed.
1 = Initiate a Flash operation
0 = Flash operation is complete or inactive
bit 14
WREN: Write Enable bit(1)
1 = Enable writes to the WR bit and the SWAP bit and disables writes to the NVMOP bits
0 = Disable writes to WR bit and the SWAP bit and enables writes to the NVMOP bits
bit 13
WRERR: Write Error bit(1)
This bit can be cleared only by setting the NVMOP bits = 0000 and initiating a Flash operation.
1 = Program or erase sequence did not complete successfully
0 = Program or erase sequence completed normally
bit 12
LVDERR: Low-Voltage Detect Error bit(1)
This bit can be cleared only by setting the NVMOP bits = 0000 and initiating a Flash operation.
1 = Low-voltage detected (possible data corruption, if WRERR is set)
0 = Voltage level is acceptable for programming
bit 11-8
Unimplemented: Read as ‘0’
bit 7
PFSWAP: Program Flash Bank Swap Control bit(3)
1 = Program Flash Bank 2 is mapped to the lower mapped region and program Flash Bank 1 is mapped to
the upper mapped region
0 = Program Flash Bank 1 is mapped to the lower mapped region and program Flash Bank 2 is mapped to
the upper mapped region
Note 1:
2:
These bits are only reset by a Power-on Reset (POR) and are not affected by other reset sources.
This operation results in a “no operation” (NOP) when the Dynamic Flash ECC Configuration bits = 00
(FECCCON (DVCFG0)), which enables ECC at all times. For all other FECCCON bit
settings, this command will execute, but will not write the ECC bits for the word and can cause DED errors
if dynamic Flash ECC is enabled (FECCCON = 01). Refer to Section 52. “Flash Program Memory
with Support for Live Update” (DS60001193) for information regarding ECC and Flash programming.
This bit can only be modified when the WREN bit = 0, the NVMKEY unlock sequence is satisfied, and the
SWAPLOCK bits (NVMCON2) are cleared to ‘0’.
The BFSWAP value is determined by the values the user programmed Sequence Numbers in each boot
panel.
3:
4:
2015-2021 Microchip Technology Inc.
DS60001361J-page 113
PIC32MZ Graphics (DA) Family
REGISTER 5-1:
NVMCON: PROGRAMMING CONTROL REGISTER (CONTINUED)
bit 6
BFSWAP: Boot Flash Bank Swap Control bit(3,4)
1 = Boot Flash Bank 2 is mapped to the lower boot region and Boot Flash Bank 1 is mapped to the upper
mapped region
0 = Boot Flash Bank 1 is mapped to the lower boot region and Boot Flash Bank 2 is mapped to the upper
mapped region
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
NVMOP: NVM Operation bits
These bits are only writable when WREN = 0.
1111 = Reserved
•
•
•
1000 = Reserved
0111 = Program erase operation: erase all of program Flash memory (all pages must be unprotected,
PWP = 0x000000)
0110 = Upper program Flash memory erase operation: erases only the upper mapped region of program
Flash (all pages in that region must be unprotected)
0101 = Lower program Flash memory erase operation: erases only the lower mapped region of program
Flash (all pages in that region must be unprotected)
0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected
0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected
0010 = Quad Word (128-bit) program operation: programs the 128-bit Flash word selected by NVMADDR,
if it is not write-protected
0001 = Word program operation: programs word selected by NVMADDR, if it is not write-protected(2)
0000 = No operation
Note 1:
2:
3:
4:
These bits are only reset by a Power-on Reset (POR) and are not affected by other reset sources.
This operation results in a “no operation” (NOP) when the Dynamic Flash ECC Configuration bits = 00
(FECCCON (DVCFG0)), which enables ECC at all times. For all other FECCCON bit
settings, this command will execute, but will not write the ECC bits for the word and can cause DED errors
if dynamic Flash ECC is enabled (FECCCON = 01). Refer to Section 52. “Flash Program Memory
with Support for Live Update” (DS60001193) for information regarding ECC and Flash programming.
This bit can only be modified when the WREN bit = 0, the NVMKEY unlock sequence is satisfied, and the
SWAPLOCK bits (NVMCON2) are cleared to ‘0’.
The BFSWAP value is determined by the values the user programmed Sequence Numbers in each boot
panel.
DS60001361J-page 114
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 5-2:
Bit
Range
31:24
23:16
15:8
7:0
NVMKEY: PROGRAMMING UNLOCK REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
W-0
W-0
W-0
Note:
W-0
31:24
23:16
15:8
7:0
W-0
W-0
W-0
Bit
24/16/8/0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY
W-0
W-0
W-0
W-0
W-0
NVMKEY
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
NVMKEY: Unlock Register bits
These bits are write-only, and read as ‘0’ on any read
This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.
NVMADDR: FLASH ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMADDR(1)
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
W-0
Bit
25/17/9/1
NVMKEY
REGISTER 5-3:
Bit
Range
W-0
Bit
26/18/10/2
NVMKEY
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
Bit
Bit
28/20/12/4 27/19/11/3
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
NVMADDR: Flash Address bits(1)
NVMOP
Selection
Flash Address Bits (NVMADDR)
Page Erase
Row Program
Word Program
Quad Word Program
Note 1:
Note:
Address identifies the page to erase (NVMADDR are ignored).
Address identifies the row to program (NVMADDR are ignored).
Address identifies the word to program (NVMADDR are ignored).
Address identifies the quad word (128-bit) to program (NVMADDR bits are
ignored).
For all other NVMOP bit settings, the Flash address is ignored.
The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other reset
sources.
2015-2021 Microchip Technology Inc.
DS60001361J-page 115
PIC32MZ Graphics (DA) Family
REGISTER 5-4:
Bit
Range
31:24
23:16
15:8
7:0
NVMDATAx: FLASH DATA REGISTER (x = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMDATA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0
NVMDATA: Flash Data bits
Word Program: Writes NVMDATA0 to the target Flash address defined in NVMADDR
Quad Word Program: Writes NVMDATA3:NVMDATA2:NVMDATA1:NVMDATA0 to the target Flash address
defined in NVMADDR. NVMDATA0 contains the Least Significant Instruction Word.
Note:
The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other reset
sources.
REGISTER 5-5:
Bit
Range
31:24
23:16
15:8
7:0
NVMSRCADDR: SOURCE DATA ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note:
x = Bit is unknown
NVMSRCADDR: Source Data Address bits
The system physical address of the data to be programmed into the Flash when the NVMOP bits
(NVMCON) are set to perform row programming.
The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other reset
sources.
DS60001361J-page 116
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 5-6:
Bit
Range
31:24
23:16
15:8
7:0
NVMPWP: PROGRAM FLASH WRITE-PROTECT REGISTER
Bit
31/23/15/7
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-1
U-0
U-0
U-0
U-0
U-0
U-0
PWPULOCK
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
PWP
R/W-0
R/W-0
R-0
R-0
R-0
PWP
R-0
R-0
R-0
R-0
R-0
PWP
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
PWPULOCK: Program Flash Memory Page Write-protect Unlock bit
1 = Register is not locked and can be modified
0 = Register is locked and cannot be modified
This bit is only clearable and cannot be set except by any reset.
bit 30-24 Unimplemented: Read as ‘0’
bit 23-0
Note:
PWP: Flash Program Write-protect (Page) Address bits
Physical memory below address 0x1Dxxxxxx is write protected, where ‘xxxxxx’ is specified by PWP.
When PWP has a value of ‘0’, write protection is disabled for the entire program Flash. If the specified
address falls within the page, the entire page and all pages below the current page will be protected.
The bits in this register are only writable when the NVMKEY unlock sequence is followed.
2015-2021 Microchip Technology Inc.
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PIC32MZ Graphics (DA) Family
REGISTER 5-7:
Bit
Range
31:24
23:16
15:8
7:0
NVMBWP: FLASH BOOT (PAGE) WRITE-PROTECT REGISTER
Bit
31/23/15/7
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LBWPULOCK
—
—
LBWP4(1)
LBWP3(1)
LBWP2(1)
LBWP1(1)
LBWP0(1)
R/W-1
r-1
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
UBWPULOCK
—
—
UBWP4
Legend:
(1)
(1)
UBWP3
(1)
UBWP2
(1)
UBWP1
UBWP0(1)
r = Reserved
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
LBWPULOCK: Lower Boot Alias Write-protect Unlock bit
1 = LBWPx bits are not locked and can be modified
0 = LBWPx bits are locked and cannot be modified
This bit is only clearable and cannot be set except by any reset.
bit 14-13 Unimplemented: Read as ‘0’
bit 12
LBWP4: Lower Boot Alias Page 4 Write-protect bit(1)
1 = Write protection for physical address 0x01FC10000 through 0x1FC13FFF enabled
0 = Write protection for physical address 0x01FC10000 through 0x1FC13FFF disabled
bit 11
LBWP3: Lower Boot Alias Page 3 Write-protect bit(1)
1 = Write protection for physical address 0x01FC0C000 through 0x1FC0FFFF enabled
0 = Write protection for physical address 0x01FC0C000 through 0x1FC0FFFF disabled
bit 10
LBWP2: Lower Boot Alias Page 2 Write-protect bit(1)
1 = Write protection for physical address 0x01FC08000 through 0x1FC0BFFF enabled
0 = Write protection for physical address 0x01FC08000 through 0x1FC0BFFF disabled
bit 9
LBWP1: Lower Boot Alias Page 1 Write-protect bit(1)
1 = Write protection for physical address 0x01FC04000 through 0x1FC07FFF enabled
0 = Write protection for physical address 0x01FC04000 through 0x1FC07FFF disabled
bit 8
LBWP0: Lower Boot Alias Page 0 Write-protect bit(1)
1 = Write protection for physical address 0x01FC00000 through 0x1FC03FFF enabled
0 = Write protection for physical address 0x01FC00000 through 0x1FC03FFF disabled
bit 7
UBWPULOCK: Upper Boot Alias Write-protect Unlock bit
1 = UBWPx bits are not locked and can be modified
0 = UBWPx bits are locked and cannot be modified
This bit is only user-clearable and cannot be set except by any reset.
bit 6
Reserved: This bit is reserved for use by development tools
bit 5
Unimplemented: Read as ‘0’
Note 1:
These bits are only available when the NVMKEY unlock sequence is performed and the associated Lock
bit (LBWPULOCK or UBWPULOCK) is set.
Note:
The bits in this register are only writable when the NVMKEY unlock sequence is followed.
DS60001361J-page 118
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 5-7:
NVMBWP: FLASH BOOT (PAGE) WRITE-PROTECT REGISTER
bit 4
UBWP4: Upper Boot Alias Page 4 Write-protect bit(1)
1 = Write protection for physical address 0x01FC30000 through 0x1FC33FFF enabled
0 = Write protection for physical address 0x01FC30000 through 0x1FC33FFF disabled
bit 3
UBWP3: Upper Boot Alias Page 3 Write-protect bit(1)
1 = Write protection for physical address 0x01FC2C000 through 0x1FC2FFFF enabled
0 = Write protection for physical address 0x01FC2C000 through 0x1FC2FFFF disabled
bit 2
UBWP2: Upper Boot Alias Page 2 Write-protect bit(1)
1 = Write protection for physical address 0x01FC28000 through 0x1FC2BFFF enabled
0 = Write protection for physical address 0x01FC28000 through 0x1FC2BFFF disabled
bit 1
UBWP1: Upper Boot Alias Page 1 Write-protect bit(1)
1 = Write protection for physical address 0x01FC24000 through 0x1FC27FFF enabled
0 = Write protection for physical address 0x01FC24000 through 0x1FC27FFF disabled
bit 0
UBWP0: Upper Boot Alias Page 0 Write-protect bit(1)
1 = Write protection for physical address 0x01FC20000 through 0x1FC23FFF enabled
0 = Write protection for physical address 0x01FC20000 through 0x1FC23FFF disabled
Note 1:
These bits are only available when the NVMKEY unlock sequence is performed and the associated Lock
bit (LBWPULOCK or UBWPULOCK) is set.
Note:
The bits in this register are only writable when the NVMKEY unlock sequence is followed.
2015-2021 Microchip Technology Inc.
DS60001361J-page 119
PIC32MZ Graphics (DA) Family
REGISTER 5-8:
Bit
Range
31:24
23:16
15:8
7:0
NVMCON2: PROGRAMMING CONTROL REGISTER 2
Bit
31/23/15/7
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
(1)
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
SWAPLOCK
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8
Unimplemented: Read as ‘0’
bit 7-6
SWAPLOCK: Program Flash Memory Page Write-protect Unlock bits(1)
11 = PFSWAP and BFSWP in the NVMCON register are Not Writable and SWAPLOCK is Not Writable
10 = PFSWAP and BFSWP in the NVMCON register are Not Writable and SWAPLOCK is Writable
01 = PFSWAP and BFSWP in the NVMCON register are Not Writable and SWAPLOCK is Writable
00 = PFSWAP and BFSWP in the NVMCON register are Writable and SWAPLOCK is Writable
bit 5-0
Unimplemented: Read as ‘0’
Note 1:
These bits can only be modified when the NVMKEY unlock sequence is satisfied and the
SWAPLOCK bits 11. If the SWAPLOCK bits == 11, only a Reset can clear these bits.
DS60001361J-page 120
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
6.0
RESETS
Note:
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 7. “Resets”
(DS60001118), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The Reset module combines all Reset sources and
controls the device System Reset signal, SYSRST. The
device Reset sources are as follows:
•
•
•
•
Power-on Reset (POR)
Brown-out Reset (BOR)
VBAT Power-on Reset (VBPOR)
High Voltage Detect Reset (HVD1V8R) on
VDDR1V8
Master Clear Reset pin (MCLR)
Software Reset (SWR)
Watchdog Timer Reset (WDTR)
Configuration Mismatch Reset (CMR)
Deadman Timer Reset (DMTR)
•
•
•
•
•
All types of device Reset will set a corresponding
Status bit in the RCON register (see Register 6-1) to
indicate the type of reset.
A simplified block diagram of the Reset module is
illustrated in Figure 6-1.
FIGURE 6-1:
SYSTEM RESET BLOCK DIAGRAM
MCLR
Glitch Filter
Sleep or Idle
MCLR
DMTR/WDTR
NMI
Time-out
WDT
Time-out
DMT
Time-out
Voltage Regulator Enabled
Power-up
Timer
VDDIO
POR(1)
VDDIO Rise
Detect
SYSRST
VDDCORE
POR
Brown-out
Reset
Configuration
Mismatch
Reset
BOR(1)
CMR
SWR
Software Reset
High-Voltage
Detect
HVD1V8R(1)
VDDR1V8
VBAT
Monitor
VBPOR(1)
VBAT
Note
1:
Refer to Table 44-5 for various RESET specifications.
2015-2021 Microchip Technology Inc.
DS60001361J-page 121
Reset Control Registers
Virtual Address
(BF80_#)
Register
Name(1)
TABLE 6-1:
1240
RCON
1250
1260
1270
RESETS REGISTER MAP
RSWRST
RNMICON
PWRCON
Legend:
Note 1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
HVD1V8R
—
15:0
—
—
—
—
—
DPSLP
—
—
—
—
—
—
CMR
—
EXTR
SWR
DMTO
WDTO
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
DMTO
WDTO
SWNMI
—
BCFGERR BCFGFAIL
15:0
23/7
22/6
21/5
20/4
19/3
All Resets
Bit Range
Bits
18/2
17/1
16/0
—
—
VBPOR
VBAT
C003
SLEEP
IDLE
BOR
POR
0003
—
—
—
—
0000
—
—
—
—
SWRST
0000
—
—
GNMI
HLVD
CF
WDTS
0000
NMICNT
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VREGS
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more
information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 122
6.1
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 6-1:
Bit
Range
31:24
23:16
15:8
7:0
RCON: RESET CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
—
U-0
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-0, HS
U-0
—
HVD1V8R
—
RW-0, HC
R/W-0, HC
U-0
U-0
BCFGERR
BCFGFAIL
—
U-0
U-0
U-0
U-0
—
U-0
R/W-1, HS
R/W-1, HS
—
—
—
—
—
—
VBPOR
VBAT
U-0
U-0
U-0
U-0
U-0
R/W-0, HS
R/W-0, HS
U-0
(1)
—
—
—
—
—
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
EXTR
SWR
DMTO
WDTO
SLEEP
IDLE
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Set
W = Writable bit
‘1’ = Bit is set
DPSLP
CMR
—
R/W-1, HS
(1)
R/W-1, HS
(1)
BOR
POR
HC = Hardware Cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Reserved: Read as ‘11’
bit 29
HVD1V8R: VDDR1V8 (DDR2) High Voltage Detect Flag bit
1 = A high voltage condition on the VDDR1V8 voltage has occurred
0 = A high voltage condition on the VDDR1V8 voltage has not occurred
bit
Unimplemented: Read as ‘0’
bit 27
BCFGERR: Primary Configuration Registers Error Flag bit
1 = An error occurred during a read of the primary configuration registers
0 = No error occurred during a read of the primary configuration registers
bit 26
BCFGFAIL: Primary/Secondary Configuration Registers Error Flag bit
1 = An error occurred during a read of the primary and alternate configuration registers
0 = No error occurred during a read of the primary and alternate configuration registers
bit 25-18 Unimplemented: Read as ‘0’
bit 17
VBPOR: VBPOR Mode Flag bit
1 = A VBAT domain POR has occurred
0 = A VBAT domain POR has not occurred
bit 16
VBAT: VBAT Mode Flag bit
1 = A POR exit from VBAT has occurred (a true POR must be established with the valid VBAT voltage on the
VBAT pin)
0 = A POR exit from VBAT has not occurred
bit 15-11 Unimplemented: Read as ‘0’
bit 10
DPSLP: Deep Sleep Mode Flag bit(1)
1 = Deep Sleep mode has occurred
0 = Deep Sleep mode has not occurred
bit 9
CMR: Configuration Mismatch Reset Flag bit
1 = A Configuration Mismatch Reset has occurred
0 = A Configuration Mismatch Reset has not occurred
bit 8
Unimplemented: Read as ‘0’
bit 7
EXTR: External Reset (MCLR) Pin Flag bit
1 = Master Clear (pin) Reset has occurred
0 = Master Clear (pin) Reset has not occurred
bit 6
SWR: Software Reset Flag bit
1 = Software Reset was executed
0 = Software Reset was not executed
bit 5
DMTO: Deadman Timer Time-out Flag bit
1 = A DMT time-out has occurred
0 = A DMT time-out has not occurred
Note 1:
User software must clear this bit to view the next detection.
2015-2021 Microchip Technology Inc.
DS60001361J-page 123
PIC32MZ Graphics (DA) Family
REGISTER 6-1:
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
RCON: RESET CONTROL REGISTER
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT Time-out has occurred
0 = WDT Time-out has not occurred
SLEEP: Wake From Sleep Flag bit
1 = Device was in Sleep mode
0 = Device was not in Sleep mode
IDLE: Wake From Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
BOR: Brown-out Reset Flag bit(1)
1 = Brown-out Reset has occurred
0 = Brown-out Reset has not occurred
POR: Power-on Reset Flag bit(1)
1 = Power-on Reset has occurred
0 = Power-on Reset has not occurred
User software must clear this bit to view the next detection.
DS60001361J-page 124
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 6-2:
Bit
Range
31:24
23:16
15:8
7:0
RSWRST: SOFTWARE RESET REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
—
—
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
W-0, HC
—
—
—
—
—
—
—
SWRST(1,2)
Legend:
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-1
Unimplemented: Read as ‘0’
bit 0
SWRST: Software Reset Trigger bit(1,2)
1 = Enable software Reset event
0 = No effect
Note 1:
The system unlock sequence must be performed before the SWRST bit can be written. Refer to the
Section 42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual”
for details.
Once this bit is set, any read of the RSWRST register will cause a reset to occur.
2:
2015-2021 Microchip Technology Inc.
DS60001361J-page 125
PIC32MZ Graphics (DA) Family
REGISTER 6-3:
Bit
Range
31:24
23:16
15:8
7:0
RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
DMTO
WDTO
R/W-0
U-0
U-0
U-0
R/W-0
HS,R/W-0
R/W-0
R/W-0
SWNMI
—
—
—
GNMI
HLVD
CF
WDTS
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NMICNT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NMICNT
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25
DMTO: Deadman Timer Time-out Flag bit
1 = DMT time-out has occurred and caused a NMI
0 = DMT time-out has not occurred
Setting this bit will cause a DMT NMI event, and NMICNT will begin counting.
bit 24
WDTO: Watchdog Timer Time-Out Flag bit
1 = WDT time-out has occurred and caused a NMI
0 = WDT time-out has not occurred
Setting this bit will cause a WDT NMI event, and MNICNT will begin counting.
bit 23
SWNMI: Software NMI Trigger.
1 = An NMI will be generated
0 = An NMI will not be generated
bit 22-20 Unimplemented: Read as ‘0’
bit 19
GNMI: General NMI bit
1 = A general NMI event has been detected or a user-initiated NMI event has occurred
0 = A general NMI event has not been detected
Setting GNMI to a ‘1’ causes a user-initiated NMI event. This bit is also set by writing 0x4E to the
NMIKEY (INTCON) bits.
bit 18
HLVD: High/Low-Voltage Detect bit
1 = HLVD has detected a low-voltage condition and caused an NMI
0 = HLVD has not detected a low-voltage condition
Note: When this bit is cleared inside NMI before exiting ISR the low voltage condition may still present. This
low voltage condition can be checked by monitoring HLVDCON inside or outside of ISR.
Note 1: If a Watchdog Timer NMI event (when not in Sleep mode) or a Deadman Timer NMI event is cleared
before this counter reaches ‘0’, no device Reset is asserted. This NMI reset counter is only applicable to
these two specific NMI events.
Note:
The system unlock sequence must be performed before the SWRST bit is written. Refer to Section 42.
“Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
DS60001361J-page 126
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 6-3:
bit 17
RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER
CF: Clock Fail Detect bit
1 = FSCM has detected clock failure and caused an NMI
0 = FSCM has not detected clock failure
Setting this bit will cause a a CF NMI event, but will not cause a clock switch to the BFRC.
bit 16
Note: On a clock fail event, if enabled by the FCKSM bits (DEVCFG1) = ‘0b11, this bit and
the OSCCON bit will be set. The user software must clear both the bits inside the CF NMI handler
before exiting the ISR. Software or hardware settings of the CF bit (OSCCON) will cause a CF NMI
event and an automatic clock switch to the Backup FRC (BFRC) provided the FCKSM = 0b11. Unlike
the CF bit (OSCCON), software or hardware settings of the CF bit (RNMICON) will cause a CF
NMI event but will not cause a clock switch to the BFRC. After a Clock Fail event, a successful user
software clock switch if implemented, hardware will automatically clear the CF bit (RNMICON) but not
the CF bit (OSCCON). The CF bit (OSCCON) must be cleared by software using the OSCCON
register unlock procedure.
WDTS: Watchdog Timer Time-out in Sleep Mode Flag bit
1 = WDT time-out has occurred during Sleep mode and caused a wake-up from sleep
0 = WDT time-out has not occurred during Sleep mode
Setting this bit will cause a WDT NMI.
bit 15-0
NMICNT: NMI Reset Counter Value bits
These bits specify the reload value used by the NMI reset counter.
1111111111111111-0000000000000001 = Number of SYSCLK cycles before a device Reset occurs(1)
0000000000000000 = No delay between NMI assertion and device Reset event
Note 1:
If a Watchdog Timer NMI event (when not in Sleep mode) or a Deadman Timer NMI event is cleared
before this counter reaches ‘0’, no device Reset is asserted. This NMI reset counter is only applicable to
these two specific NMI events.
Note:
The system unlock sequence must be performed before the SWRST bit is written. Refer to Section 42.
“Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
2015-2021 Microchip Technology Inc.
DS60001361J-page 127
PIC32MZ Graphics (DA) Family
REGISTER 6-4:
Bit
Range
31:24
23:16
15:8
7:0
PWRCON: POWER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
—
—
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
VREGS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-1
Unimplemented: Read as ‘0’
bit 0
VREGS: Voltage Regulator Stand-by Enable bit
1 = Voltage regulator will remain active during Sleep
0 = Voltage regulator will go to Stand-by mode during Sleep
DS60001361J-page 128
x = Bit is unknown
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
7.0
Note:
CPU EXCEPTIONS AND
INTERRUPT CONTROLLER
The CPU handles interrupt events as part of the exception handling mechanism, which is described in
Section 7.1 “CPU Exceptions”.
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Interrupt Controller” (DS60001108) and Section 50.
“CPU for Devices with MIPS32®
microAptiv™ and M-Class Cores”
(DS60001192), which are available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
PIC32MZ DA devices generate interrupt requests in
response to interrupt events from peripheral modules.
The Interrupt Controller module exists outside of the
CPU and prioritizes the interrupt events before
presenting them to the CPU.
• Up to 210 interrupt sources and vectors with
dedicated programmable offsets, eliminating the
need for redirection
• Single and multi-vector mode operations
• Five external interrupts with edge polarity control
• Interrupt proximity timer
• Seven user-selectable priority levels for each
vector
• Four user-selectable sub-priority levels within
each priority
• Seven shadow register sets that can be used for any
priority level, eliminating software context switch and
reducing interrupt latency
• Software can generate any interrupt
Figure 7-1 shows the block diagram for the Interrupt
Controller and CPU exceptions.
CPU EXCEPTIONS AND INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM
Interrupt Requests
FIGURE 7-1:
The Interrupt Controller module includes the following
features:
Vector Number and Offset
Interrupt Controller
Priority Level
CPU Core
(Exception Handling)
Shadow Set Number
SYSCLK
2015-2021 Microchip Technology Inc.
DS60001361J-page 129
CPU Exceptions
CPU coprocessor 0 contains the logic for identifying and managing exceptions.
Exceptions can be caused by a variety of sources, including boundary cases in
data, external events or program errors. Table 7-1 lists the exception types in
order of priority.
TABLE 7-1:
Exception Type
(In Order of
Priority)
MIPS32® microAptiv™ MICROPROCESSOR CORE EXCEPTION TYPES
Description
Branches to
Status
Bits Set
Debug Bits
EXCCODE
Set
XC32 Function Name
Highest Priority
Reset
Soft Reset
Assertion MCLR or a Power-on Reset (POR).
Assertion of a software Reset.
0xBFC0_0000
0xBFC0_0000
DSS
DINT
0xBFC0_0480
0xBFC0_0480
NMI
EJTAG debug single step.
EJTAG debug interrupt. Caused by the assertion of
the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
Assertion of NMI signal.
Machine Check
TLB write that conflicts with an existing entry.
EBASE+0x180
Interrupt
Assertion of unmasked hardware or software interSee Table 7-2.
rupt signal.
Deferred watch (unmasked by K|DM=>!(K|DM)
EBASE+0x180
transition).
EJTAG debug hardware instruction break matched.
0xBFC0_0480
A reference to an address that is in one of the
EBASE+0x180
Watch registers (fetch).
Fetch address alignment error. Fetch reference to
EBASE+0x180
protected address.
Fetch TLB miss or fetch TLB hit to page with V = 0. EBASE if Status.EXL = 0
EBASE+0x180 if
Status.EXL == 1
An instruction fetch matched a valid TLB entry that
EBASE+0x180
had the XI bit set.
Instruction fetch bus error.
EBASE+0x180
Deferred Watch
2015-2021 Microchip Technology Inc.
DIB
WATCH
AdEL
TLBL
TLBL ExecuteInhibit
IBE
0xBFC0_0000
BEV, ERL
BEV, SR,
ERL
—
—
—
—
—
—
DSS
DINT
—
—
BEV, NMI,
ERL
MCHECK,
EXL
IPL
—
—
—
0x18
_general_exception_handler
—
0x00
See Table 7-2.
WP, EXL
—
0x17
_general_exception_handler
—
EXL
DIB
—
—
0x17
—
_general_exception_handler
EXL
—
0x04
_general_exception_handler
—
—
—
—
0x02
0x02
—
_general_exception_handler
EXL
—
0x14
_general_exception_handler
EXL
—
0x06
_general_exception_handler
_on_reset
_on_reset
—
—
_nmi_handler
PIC32MZ Graphics (DA) Family
DS60001361J-page 130
7.1
2015-2021 Microchip Technology Inc.
TABLE 7-1:
Exception Type
(In Order of
Priority)
Instruction
Validity
Exceptions
Execute
Exception
WATCH
AdEL
AdES
TLBL
TLBS
DBE
DDBL
CBrk
Description
Branches to
Status
Bits Set
An instruction could not be completed because it
was not allowed to access the required resources
(Coprocessor Unusable) or was illegal (Reserved
Instruction). If both exceptions occur on the same
instruction, the Coprocessor Unusable Exception
takes priority over the Reserved Instruction
Exception.
An instruction-based exception occurred: Integer
overflow, trap, system call, breakpoint, floating
point, or DSP ASE state disabled exception.
Execution of a trap (when trap condition is true).
EJTAG Data Address Break (address only) or
EJTAG data value break on store (address +
value).
A reference to an address that is in one of the
Watch registers (data).
Load address alignment error. User mode load
reference to kernel address.
Store address alignment error. User mode store to
kernel address.
Load TLB miss or load TLB hit to page with V = 0.
Store TLB miss or store TLB hit to page with V = 0.
Load or store bus error.
EJTAG data hardware breakpoint matched in load
data compare.
EJTAG complex breakpoint.
EBASE+0x180
EXL
—
EBASE+0x180
EXL
—
EBASE+0x180
0xBFC0_0480
EXL
—
—
DDBL or
DDBS
0x0D
—
_general_exception_handler
—
EBASE+0x180
EXL
—
0x17
_general_exception_handler
EBASE+0x180
EXL
—
0x04
_general_exception_handler
EBASE+0x180
EXL
—
0x05
_general_exception_handler
EBASE+0x180
EBASE+0x180
EBASE+0x180
0xBFC0_0480
EXL
EXL
EXL
—
—
—
—
DDBL
0x02
0x03
0x07
—
_general_exception_handler
_general_exception_handler
_general_exception_handler
—
0xBFC0_0480
—
DIBIMPR,
DDBLIMPR,
and/or
DDBSIMPR
—
—
DS60001361J-page 131
Lowest Priority
Debug Bits
EXCCODE
Set
0x0A or
0x0B
XC32 Function Name
_general_exception_handler
0x08-0x0C _general_exception_handler
PIC32MZ Graphics (DA) Family
Tr
DDBL/DDBS
MIPS32® microAptiv™ MICROPROCESSOR CORE EXCEPTION TYPES (CONTINUED)
Interrupts
For details on the Variable Offset feature, refer to 8.5.2 “Variable Offset” in
Section 8. “Interrupt Controller” (DS60001108) of the “PIC32 Family
Reference Manual”.
The PIC32MZ DA family uses variable offsets for vector spacing. This allows
the interrupt vector spacing to be configured according to application needs. A
unique interrupt vector offset can be set for each vector using its associated
OFFx register.
TABLE 7-2:
Table 7-2 provides the Interrupt IRQ, vector and bit location information.
INTERRUPT IRQ, VECTOR AND BIT LOCATION
Interrupt Source(1)
IRQ
#
XC32 Vector Name
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
Highest Natural Order Priority
2015-2021 Microchip Technology Inc.
Core Timer Interrupt
_CORE_TIMER_VECTOR
0
OFF000
IFS0
IEC0
IPC0
IPC0
No
Core Software Interrupt 0
_CORE_SOFTWARE_0_VECTOR
1
OFF001
IFS0
IEC0
IPC0
IPC0
No
Core Software Interrupt 1
_CORE_SOFTWARE_1_VECTOR
2
OFF002
IFS0
IEC0
IPC0
IPC0
No
External Interrupt 0
_EXTERNAL_0_VECTOR
3
OFF003
IFS0
IEC0
IPC0
IPC0
No
Timer1
_TIMER_1_VECTOR
4
OFF004
IFS0
IEC0
IPC1
IPC1
No
Input Capture 1 Error
_INPUT_CAPTURE_1_ERROR_VECTOR
5
OFF005
IFS0
IEC0
IPC1
IPC1
Yes
Input Capture 1
_INPUT_CAPTURE_1_VECTOR
6
OFF006
IFS0
IEC0
IPC1
IPC1
Yes
Output Compare 1
_OUTPUT_COMPARE_1_VECTOR
7
OFF007
IFS0
IEC0
IPC1
IPC1
No
External Interrupt 1
_EXTERNAL_1_VECTOR
8
OFF008
IFS0
IEC0
IPC2
IPC2
No
Timer2
_TIMER_2_VECTOR
9
OFF009
IFS0
IEC0
IPC2
IPC2
No
Input Capture 2 Error
_INPUT_CAPTURE_2_ERROR_VECTOR
10
OFF010
IFS0 IEC0 IPC2
IPC2
Yes
Input Capture 2
_INPUT_CAPTURE_2_VECTOR
11
OFF011
IFS0 IEC0 IPC2
IPC2
Yes
Output Compare 2
_OUTPUT_COMPARE_2_VECTOR
12
OFF012
IFS0 IEC0 IPC3
IPC3
No
External Interrupt 2
_EXTERNAL_2_VECTOR
13
OFF013
IFS0 IEC0 IPC3
IPC3
No
Timer3
_TIMER_3_VECTOR
14
OFF014
IFS0 IEC0 IPC3
IPC3
No
Input Capture 3 Error
_INPUT_CAPTURE_3_ERROR_VECTOR
15
OFF015
IFS0 IEC0 IPC3
IPC3
Yes
Input Capture 3
_INPUT_CAPTURE_3_VECTOR
16
OFF016
IFS0 IEC0 IPC4
IPC4
Yes
Output Compare 3
_OUTPUT_COMPARE_3_VECTOR
17
OFF017
IFS0 IEC0 IPC4
IPC4
No
External Interrupt 3
_EXTERNAL_3_VECTOR
18
OFF018
IFS0 IEC0 IPC4
IPC4
No
Timer4
_TIMER_4_VECTOR
19
OFF019
IFS0 IEC0 IPC4
IPC4
No
Input Capture 4 Error
_INPUT_CAPTURE_4_ERROR_VECTOR
20
OFF020
IFS0 IEC0 IPC5
IPC5
Yes
Input Capture 4
_INPUT_CAPTURE_4_VECTOR
21
OFF021
IFS0 IEC0 IPC5
IPC5
Yes
Output Compare 4
_OUTPUT_COMPARE_4_VECTOR
22
OFF022
IFS0 IEC0 IPC5
IPC5
No
Note 1:
2:
Not all interrupt sources are available on all devices. See the Family Features tables (Table 1 through Table 2) for the list of available peripherals.
Upon Reset, the GLCD interrupt (both HSYNC and VSYNC) are persistent. However, through the IRQCON bit (GLCDINT), the type of interrupt can be
changed to non-persistent.
PIC32MZ Graphics (DA) Family
DS60001361J-page 132
7.2
2015-2021 Microchip Technology Inc.
TABLE 7-2:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
_EXTERNAL_4_VECTOR
23
OFF023
IFS0 IEC0 IPC5
IPC5
No
Timer5
_TIMER_5_VECTOR
24
OFF024
IFS0 IEC0 IPC6
IPC6
No
Input Capture 5 Error
_INPUT_CAPTURE_5_ERROR_VECTOR
25
OFF025
IFS0 IEC0 IPC6
IPC6
Yes
Input Capture 5
_INPUT_CAPTURE_5_VECTOR
26
OFF026
IFS0 IEC0 IPC6
IPC6
Yes
Output Compare 5
_OUTPUT_COMPARE_5_VECTOR
27
OFF027
IFS0 IEC0 IPC6
IPC6
No
Timer6
_TIMER_6_VECTOR
28
OFF028
IFS0 IEC0 IPC7
IPC7
No
Input Capture 6 Error
_INPUT_CAPTURE_6_ERROR_VECTOR
29
OFF029
IFS0 IEC0 IPC7
IPC7
Yes
Input Capture 6
_INPUT_CAPTURE_6_VECTOR
30
OFF030
IFS0 IEC0 IPC7
IPC7
Yes
Output Compare 6
_OUTPUT_COMPARE_6_VECTOR
31
OFF031
IFS0 IEC0 IPC7
IPC7
No
Timer7
_TIMER_7_VECTOR
32
OFF032
IFS1
IEC1
IPC8
IPC8
No
Input Capture 7 Error
_INPUT_CAPTURE_7_ERROR_VECTOR
33
OFF033
IFS1
IEC1
IPC8
IPC8
Yes
Input Capture 7
_INPUT_CAPTURE_7_VECTOR
34
OFF034
IFS1
IEC1
IPC8
IPC8
Yes
Output Compare 7
_OUTPUT_COMPARE_7_VECTOR
35
OFF035
IFS1
IEC1
IPC8
IPC8
No
Timer8
_TIMER_8_VECTOR
36
OFF036
IFS1
IEC1
IPC9
IPC9
No
Input Capture 8 Error
_INPUT_CAPTURE_8_ERROR_VECTOR
37
OFF037
IFS1
IEC1
IPC9
IPC9
Yes
Input Capture 8
_INPUT_CAPTURE_8_VECTOR
38
OFF038
IFS1
IEC1
IPC9
IPC9
Yes
Output Compare 8
_OUTPUT_COMPARE_8_VECTOR
39
OFF039
IFS1
IEC1
IPC9
IPC9
No
Timer9
_TIMER_9_VECTOR
40
OFF040
IFS1
IEC1
IPC10
IPC10
No
Input Capture 9 Error
_INPUT_CAPTURE_9_ERROR_VECTOR
41
OFF041
IFS1
IEC1
IPC10 IPC10
Yes
Input Capture 9
_INPUT_CAPTURE_9_VECTOR
42
OFF042
IFS1 IEC1 IPC10 IPC10
Output Compare 9
_OUTPUT_COMPARE_9_VECTOR
43
OFF043
IFS1 IEC1 IPC10 IPC10
No
ADC Global Interrupt
_ADC_VECTOR
44
OFF044
IFS1 IEC1 IPC11
IPC11
Yes
ADC FIFO Interrupt
_ADC_FIFO_VECTOR
45
OFF045
IFS1 IEC1 IPC11 IPC11
Yes
ADC Digital Comparator 1
_ADC_DC1_VECTOR
46
OFF046
IFS1 IEC1 IPC11 IPC11
Yes
ADC Digital Comparator 2
_ADC_DC2_VECTOR
47
OFF047
IFS1 IEC1 IPC11 IPC11
Yes
ADC Digital Comparator 3
_ADC_DC3_VECTOR
48
OFF048
IFS1 IEC1 IPC12
IPC12
Yes
ADC Digital Comparator 4
_ADC_DC4_VECTOR
49
OFF049
IFS1 IEC1 IPC12 IPC12
Yes
ADC Digital Comparator 5
_ADC_DC5_VECTOR
50
OFF050
IFS1 IEC1 IPC12 IPC12
Yes
ADC Digital Comparator 6
_ADC_DC6_VECTOR
51
OFF051
IFS1 IEC1 IPC12 IPC12
Yes
Note 1:
2:
Yes
Not all interrupt sources are available on all devices. See the Family Features tables (Table 1 through Table 2) for the list of available peripherals.
Upon Reset, the GLCD interrupt (both HSYNC and VSYNC) are persistent. However, through the IRQCON bit (GLCDINT), the type of interrupt can be
changed to non-persistent.
PIC32MZ Graphics (DA) Family
DS60001361J-page 133
External Interrupt 4
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
2015-2021 Microchip Technology Inc.
ADC Digital Filter 1
_ADC_DF1_VECTOR
52
OFF052
IFS1 IEC1 IPC13
IPC13
Yes
ADC Digital Filter 2
_ADC_DF2_VECTOR
53
OFF053
IFS1 IEC1 IPC13 IPC13
Yes
ADC Digital Filter 3
_ADC_DF3_VECTOR
54
OFF054
IFS1 IEC1 IPC13 IPC13
Yes
ADC Digital Filter 4
_ADC_DF4_VECTOR
55
OFF055
IFS1 IEC1 IPC13 IPC13
Yes
ADC Digital Filter 5
_ADC_DF5_VECTOR
56
OFF056
IFS1 IEC1 IPC14
IPC14
Yes
ADC Digital Filter 6
_ADC_DF6_VECTOR
57
OFF057
IFS1 IEC1 IPC14 IPC14
Yes
ADC Fault
_ADC_FAULT_VECTOR
58
OFF058
IFS1 IEC1 IPC14 IPC14
Yes
ADC Data 0
_ADC_DATA0_VECTOR
59
OFF059
IFS1 IEC1 IPC14 IPC14
Yes
ADC Data 1
_ADC_DATA1_VECTOR
60
OFF060
IFS1 IEC1 IPC15
IPC15
Yes
ADC Data 2
_ADC_DATA2_VECTOR
61
OFF061
IFS1 IEC1 IPC15 IPC15
Yes
ADC Data 3
_ADC_DATA3_VECTOR
62
OFF062
IFS1 IEC1 IPC15 IPC15
Yes
ADC Data 4
_ADC_DATA4_VECTOR
63
OFF063
IFS1 IEC1 IPC15 IPC15
Yes
ADC Data 5
_ADC_DATA5_VECTOR
64
OFF064
IFS2
IEC2
IPC16
IPC16
Yes
ADC Data 6
_ADC_DATA6_VECTOR
65
OFF065
IFS2
IEC2
IPC16 IPC16
Yes
ADC Data 7
_ADC_DATA7_VECTOR
66
OFF066
IFS2
IEC2
IPC16 IPC16
Yes
ADC Data 8
_ADC_DATA8_VECTOR
67
OFF067
IFS2
IEC2
IPC16 IPC16
Yes
ADC Data 9
_ADC_DATA9_VECTOR
68
OFF068
IFS2
IEC2
IPC17
IPC17
Yes
ADC Data 10
_ADC_DATA10_VECTOR
69
OFF069
IFS2
IEC2
IPC17 IPC17
Yes
ADC Data 11
_ADC_DATA11_VECTOR
70
OFF070
IFS2
IEC2
IPC17 IPC17
Yes
ADC Data 12
_ADC_DATA12_VECTOR
71
OFF071
IFS2
IEC2
IPC17 IPC17
Yes
ADC Data 13
_ADC_DATA13_VECTOR
72
OFF072
IFS2
IEC2
IPC18
IPC18
Yes
ADC Data 14
_ADC_DATA14_VECTOR
73
OFF073
IFS2
IEC2
IPC18 IPC18
Yes
ADC Data 15
_ADC_DATA15_VECTOR
74
OFF074
IFS2 IEC2 IPC18 IPC18
Yes
ADC Data 16
_ADC_DATA16_VECTOR
75
OFF075
IFS2 IEC2 IPC18 IPC18
Yes
ADC Data 17
_ADC_DATA17_VECTOR
76
OFF076
IFS2 IEC2 IPC19
IPC19
Yes
ADC Data 18
_ADC_DATA18_VECTOR
77
OFF077
IFS2 IEC2 IPC19 IPC19
Yes
ADC Data 19
_ADC_DATA19_VECTOR
78
OFF078
IFS2 IEC2 IPC19 IPC19
Yes
ADC Data 20
_ADC_DATA20_VECTOR
79
OFF079
IFS2 IEC2 IPC19 IPC19
Yes
ADC Data 21
_ADC_DATA21_VECTOR
80
OFF080
IFS2 IEC2 IPC20
Yes
Note 1:
2:
IPC20
Not all interrupt sources are available on all devices. See the Family Features tables (Table 1 through Table 2) for the list of available peripherals.
Upon Reset, the GLCD interrupt (both HSYNC and VSYNC) are persistent. However, through the IRQCON bit (GLCDINT), the type of interrupt can be
changed to non-persistent.
PIC32MZ Graphics (DA) Family
DS60001361J-page 134
TABLE 7-2:
2015-2021 Microchip Technology Inc.
TABLE 7-2:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
_ADC_DATA22_VECTOR
81
OFF081
IFS2 IEC2 IPC20 IPC20
Yes
ADC Data 23
_ADC_DATA23_VECTOR
82
OFF082
IFS2 IEC2 IPC20 IPC20
Yes
ADC Data 24
_ADC_DATA24_VECTOR
83
OFF083
IFS2 IEC2 IPC20 IPC20
Yes
ADC Data 25
_ADC_DATA25_VECTOR
84
OFF084
IFS2 IEC2 IPC21
IPC21
Yes
ADC Data 26
_ADC_DATA26_VECTOR
85
OFF085
IFS2 IEC2 IPC21 IPC21
Yes
ADC Data 27
_ADC_DATA27_VECTOR
86
OFF086
IFS2 IEC2 IPC21 IPC21
Yes
ADC Data 28
_ADC_DATA28_VECTOR
87
OFF087
IFS2 IEC2 IPC21 IPC21
Yes
ADC Data 29
_ADC_DATA29_VECTOR
88
OFF088
IFS2 IEC2 IPC22
IPC22
Yes
ADC Data 30
_ADC_DATA30_VECTOR
89
OFF089
IFS2 IEC2 IPC22 IPC22
Yes
ADC Data 31
_ADC_DATA31_VECTOR
90
OFF090
IFS2 IEC2 IPC22 IPC22
Yes
ADC Data 32
_ADC_DATA32_VECTOR
91
OFF091
IFS2 IEC2 IPC22 IPC22
Yes
ADC Data 33
_ADC_DATA33_VECTOR
92
OFF092
IFS2 IEC2 IPC23
IPC23
Yes
ADC Data 34
_ADC_DATA34_VECTOR
93
OFF093
IFS2 IEC2 IPC23 IPC23
Yes
ADC Data 35
_ADC_DATA35_VECTOR
94
OFF094
IFS2 IEC2 IPC23 IPC23
Yes
ADC Data 36
_ADC_DATA36_VECTOR
95
OFF095
IFS2 IEC2 IPC23 IPC23
Yes
ADC Data 37
_ADC_DATA37_VECTOR
96
OFF096
IFS3
IEC3
IPC24
IPC24
Yes
ADC Data 38
_ADC_DATA38_VECTOR
97
OFF097
IFS3
IEC3
IPC24 IPC24
Yes
ADC Data 39
_ADC_DATA39_VECTOR
98
OFF098
IFS3
IEC3
IPC24 IPC24
Yes
ADC Data 40
_ADC_DATA40_VECTOR
99
OFF099
IFS3
IEC3
IPC24 IPC24
Yes
ADC Data 41
_ADC_DATA41_VECTOR
100
OFF100
IFS3
IEC3
IPC25
IPC25
Yes
ADC Data 42
_ADC_DATA42_VECTOR
101
OFF101
IFS3
IEC3
IPC25 IPC25
Yes
ADC Data 43
_ADC_DATA43_VECTOR
102
OFF102
IFS3
IEC3
IPC25 IPC25
Yes
USB Suspend/Resume Event
_USB_SR_VECTOR
No
DS60001361J-page 135
103
OFF103
IFS3
IEC3
IPC25 IPC25
Core Performance Counter Interrupt _CORE_PERF_COUNT_VECTOR
104
OFF104
IFS3
IEC3
IPC26
IPC26
No
Core Fast Debug Channel Interrupt _CORE_FAST_DEBUG_CHAN_VECTOR
105
OFF105
IFS3
IEC3
IPC26 IPC26
Yes
System Bus Protection Violation
_SYSTEM_BUS_PROTECTION_VECTOR 106
OFF106
IFS3 IEC3 IPC26 IPC26
Yes
Crypto Engine Event
_CRYPTO_VECTOR
107
OFF107
IFS3 IEC3 IPC26 IPC26
Yes
108
—
109
OFF109
Reserved
SPI1 Fault
Note 1:
2:
—
_SPI1_FAULT_VECTOR
—
—
—
—
IFS3 IEC3 IPC27 IPC27
—
Yes
Not all interrupt sources are available on all devices. See the Family Features tables (Table 1 through Table 2) for the list of available peripherals.
Upon Reset, the GLCD interrupt (both HSYNC and VSYNC) are persistent. However, through the IRQCON bit (GLCDINT), the type of interrupt can be
changed to non-persistent.
PIC32MZ Graphics (DA) Family
ADC Data 22
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
2015-2021 Microchip Technology Inc.
SPI1 Receive Done
_SPI1_RX_VECTOR
110
OFF110
IFS3 IEC3 IPC27 IPC27
Yes
SPI1 Transfer Done
_SPI1_TX_VECTOR
111
OFF111
IFS3 IEC3 IPC27 IPC27
Yes
UART1 Fault
_UART1_FAULT_VECTOR
112
OFF112
IFS3 IEC3 IPC28
IPC28
Yes
UART1 Receive Done
_UART1_RX_VECTOR
113
OFF113
IFS3 IEC3 IPC28 IPC28
Yes
UART1 Transfer Done
_UART1_TX_VECTOR
114
OFF114
IFS3 IEC3 IPC28 IPC28
Yes
I2C1 Bus Collision Event
_I2C1_BUS_VECTOR
115
OFF115
IFS3 IEC3 IPC28 IPC28
Yes
I2C1 Client Event
_I2C1_SLAVE_VECTOR
116
OFF116
IFS3 IEC3 IPC29
IPC29
Yes
I2C1 Host Event
_I2C1_MASTER_VECTOR
117
OFF117
IFS3 IEC3 IPC29 IPC29
Yes
PORTA Input Change Interrupt
_CHANGE_NOTICE_A_VECTOR
118
OFF118
IFS3 IEC3 IPC29 IPC29
Yes
PORTB Input Change Interrupt
_CHANGE_NOTICE_B_VECTOR
119
OFF119
IFS3 IEC3 IPC29 IPC29
Yes
PORTC Input Change Interrupt
_CHANGE_NOTICE_C_VECTOR
120
OFF120
IFS3 IEC3 IPC30
IPC30
Yes
PORTD Input Change Interrupt
_CHANGE_NOTICE_D_VECTOR
121
OFF121
IFS3 IEC3 IPC30 IPC30
Yes
PORTE Input Change Interrupt
_CHANGE_NOTICE_E_VECTOR
122
OFF122
IFS3 IEC3 IPC30 IPC30
Yes
PORTF Input Change Interrupt
_CHANGE_NOTICE_F_VECTOR
123
OFF123
IFS3 IEC3 IPC30 IPC30
Yes
PORTG Input Change Interrupt
_CHANGE_NOTICE_G_VECTOR
124
OFF124
IFS3 IEC3 IPC31
IPC31
Yes
PORTH Input Change Interrupt
_CHANGE_NOTICE_H_VECTOR
125
OFF125
IFS3 IEC3 IPC31 IPC31
Yes
PORTJ Input Change Interrupt
_CHANGE_NOTICE_J_VECTOR
126
OFF126
IFS3 IEC3 IPC31 IPC31
Yes
PORTK Input Change Interrupt
_CHANGE_NOTICE_K_VECTOR
127
OFF127
IFS3 IEC3 IPC31 IPC31
Yes
PMP
_PMP_VECTOR
128
OFF128
IFS4
IEC4
IPC32
IPC32
Yes
PMP Error
_PMP_ERROR_VECTOR
129
OFF129
IFS4
IEC4
IPC32 IPC32
Yes
Comparator 1 Interrupt
_COMPARATOR_1_VECTOR
130
OFF130
IFS4
IEC4
IPC32 IPC32
No
Comparator 2 Interrupt
_COMPARATOR_2_VECTOR
131
OFF131
IFS4
IEC4
IPC32 IPC32
No
USB General Event
_USB_VECTOR
132
OFF132
IFS4
IEC4
IPC33
IPC33
Yes
USB DMA Event
_USB_DMA_VECTOR
133
OFF133
IFS4
IEC4
IPC33 IPC33
Yes
DMA Channel 0
_DMA0_VECTOR
134
OFF134
IFS4
IEC4
IPC33 IPC33
No
DMA Channel 1
_DMA1_VECTOR
135
OFF135
IFS4
IEC4
IPC33 IPC33
No
DMA Channel 2
_DMA2_VECTOR
136
OFF136
IFS4
IEC4
IPC34
IPC34
No
DMA Channel 3
_DMA3_VECTOR
137
OFF137
IFS4
IEC4
IPC34 IPC34
No
DMA Channel 4
_DMA4_VECTOR
138
OFF138
IFS4 IEC4 IPC34 IPC34
Note 1:
2:
No
Not all interrupt sources are available on all devices. See the Family Features tables (Table 1 through Table 2) for the list of available peripherals.
Upon Reset, the GLCD interrupt (both HSYNC and VSYNC) are persistent. However, through the IRQCON bit (GLCDINT), the type of interrupt can be
changed to non-persistent.
PIC32MZ Graphics (DA) Family
DS60001361J-page 136
TABLE 7-2:
2015-2021 Microchip Technology Inc.
TABLE 7-2:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
_DMA5_VECTOR
139
OFF139
IFS4 IEC4 IPC34 IPC34
No
DMA Channel 6
_DMA6_VECTOR
140
OFF140
IFS4 IEC4 IPC35
No
DMA Channel 7
_DMA7_VECTOR
141
OFF141
IFS4 IEC4 IPC35 IPC35
No
SPI2 Fault
_SPI2_FAULT_VECTOR
142
OFF142
IFS4 IEC4 IPC35 IPC35
Yes
SPI2 Receive Done
_SPI2_RX_VECTOR
143
OFF143
IFS4 IEC4 IPC35 IPC35
Yes
SPI2 Transfer Done
_SPI2_TX_VECTOR
144
OFF144
IFS4 IEC4 IPC36
IPC36
Yes
UART2 Fault
_UART2_FAULT_VECTOR
145
OFF145
IFS4 IEC4 IPC36 IPC36
Yes
UART2 Receive Done
_UART2_RX_VECTOR
146
OFF146
IFS4 IEC4 IPC36 IPC36
Yes
UART2 Transfer Done
_UART2_TX_VECTOR
147
OFF147
IFS4 IEC4 IPC36 IPC36
Yes
I2C2 Bus Collision Event
_I2C2_BUS_VECTOR
148
OFF148
IFS4 IEC4 IPC37
IPC37
Yes
I2C2 Client Event
_I2C2_SLAVE_VECTOR
149
OFF149
IFS4 IEC4 IPC37 IPC37
Yes
I2C2 Host Event
_I2C2_MASTER_VECTOR
150
OFF150
IFS4 IEC4 IPC37 IPC37
Yes
Control Area Network 1
_CAN1_VECTOR
151
OFF151
IFS4 IEC4 IPC37 IPC37
Yes
Control Area Network 2
_CAN2_VECTOR
152
OFF152
IFS4 IEC4 IPC38
IPC38
Yes
Ethernet Interrupt
_ETHERNET_VECTOR
153
OFF153
IFS4 IEC4 IPC38 IPC38
Yes
SPI3 Fault
_SPI3_FAULT_VECTOR
154
OFF154
IFS4 IEC4 IPC38 IPC38
Yes
SPI3 Receive Done
_SPI3_RX_VECTOR
155
OFF155
IFS4 IEC4 IPC38 IPC38
Yes
SPI3 Transfer Done
_SPI3_TX_VECTOR
156
OFF156
IFS4 IEC4 IPC39
IPC39
Yes
UART3 Fault
_UART3_FAULT_VECTOR
157
OFF157
IFS4 IEC4 IPC39 IPC39
Yes
UART3 Receive Done
_UART3_RX_VECTOR
158
OFF158
IFS4 IEC4 IPC39 IPC39
Yes
UART3 Transfer Done
_UART3_TX_VECTOR
159
OFF159
IFS4 IEC4 IPC39 IPC39
Yes
I2C3 Bus Collision Event
_I2C3_BUS_VECTOR
160
OFF160
IFS5
IEC5
IPC40
IPC40
Yes
I2C3 Client Event
_I2C3_SLAVE_VECTOR
161
OFF161
IFS5
IEC5
IPC40 IPC40
Yes
I2C3 Host Event
_I2C3_MASTER_VECTOR
162
OFF162
IFS5
IEC5
IPC40 IPC40
Yes
SPI4 Fault
_SPI4_FAULT_VECTOR
163
OFF163
IFS5
IEC5
IPC40 IPC40
Yes
SPI4 Receive Done
_SPI4_RX_VECTOR
164
OFF164
IFS5
IEC5
IPC41
IPC41
Yes
SPI4 Transfer Done
_SPI4_TX_VECTOR
165
OFF165
IFS5
IEC5
IPC41 IPC41
Yes
Real Time Clock
_RTCC_VECTOR
166
OFF166
IFS5
IEC5
IPC41 IPC41
No
Flash Control Event
_FLASH_CONTROL_VECTOR
167
OFF167
IFS5
IEC5
IPC41 IPC41
No
Note 1:
2:
IPC35
Not all interrupt sources are available on all devices. See the Family Features tables (Table 1 through Table 2) for the list of available peripherals.
Upon Reset, the GLCD interrupt (both HSYNC and VSYNC) are persistent. However, through the IRQCON bit (GLCDINT), the type of interrupt can be
changed to non-persistent.
PIC32MZ Graphics (DA) Family
DS60001361J-page 137
DMA Channel 5
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
2015-2021 Microchip Technology Inc.
Prefetch Module SEC Event
_PREFETCH_VECTOR
168
OFF168
IFS5
IEC5
IPC42
IPC42
Yes
SQI1 Event
_SQI1_VECTOR
169
OFF169
IFS5
IEC5
IPC42 IPC42
Yes
UART4 Fault
_UART4_FAULT_VECTOR
170
OFF170
IFS5 IEC5 IPC42 IPC42
Yes
UART4 Receive Done
_UART4_RX_VECTOR
171
OFF171
IFS5 IEC5 IPC42 IPC42
Yes
UART4 Transfer Done
_UART4_TX_VECTOR
172
OFF172
IFS5 IEC5 IPC43
IPC43
Yes
I2C4 Bus Collision Event
_I2C4_BUS_VECTOR
173
OFF173
IFS5 IEC5 IPC43 IPC43
Yes
I2C4 Client Event
_I2C4_SLAVE_VECTOR
174
OFF174
IFS5 IEC5 IPC43 IPC43
Yes
I2C4 Host Event
_I2C4_MASTER_VECTOR
175
OFF175
IFS5 IEC5 IPC43 IPC43
Yes
SPI5 Fault
_SPI5_FAULT_VECTOR
176
OFF176
IFS5 IEC5 IPC44
IPC44
Yes
SPI5 Receive Done
_SPI5_RX_VECTOR
177
OFF177
IFS5 IEC5 IPC44 IPC44
Yes
SPI5 Transfer Done
_SPI5_TX_VECTOR
178
OFF178
IFS5 IEC5 IPC44 IPC44
Yes
UART5 Fault
_UART5_FAULT_VECTOR
179
OFF179
IFS5 IEC5 IPC44 IPC44
Yes
UART5 Receive Done
_UART5_RX_VECTOR
180
OFF180
IFS5 IEC5 IPC45
IPC45
Yes
UART5 Transfer Done
_UART5_TX_VECTOR
181
OFF181
IFS5 IEC5 IPC45 IPC45
Yes
I2C5 Bus Collision Event
_I2C5_BUS_VECTOR
182
OFF182
IFS5 IEC5 IPC45 IPC45
Yes
I2C5 Client Event
_I2C5_SLAVE_VECTOR
183
OFF183
IFS5 IEC5 IPC45 IPC45
Yes
I2C5 Host Event
_I2C5_MASTER_VECTOR
184
OFF184
IFS5 IEC5 IPC46
IPC46
Yes
SPI6 Fault
_SPI6_FAULT_VECTOR
185
OFF185
IFS5 IEC5 IPC46 IPC46
Yes
SPI6 Receive Done
_SPI6_RX_VECTOR
186
OFF186
IFS5 IEC5 IPC46 IPC46
Yes
SPI6 Transfer Done
_SPI6_TX_VECTOR
187
OFF187
IFS5 IEC5 IPC46 IPC46
Yes
UART6 Fault
_UART6_FAULT_VECTOR
188
OFF188
IFS5 IEC5 IPC47
IPC47
Yes
UART6 Receive Done
_UART6_RX_VECTOR
189
OFF189
IFS5 IEC5 IPC47 IPC47
Yes
UART6 Transfer Done
_UART6_TX_VECTOR
190
OFF190
IFS5 IEC5 IPC47 IPC47
Yes
SDHC Interrupt
_SDHC_VECTOR
191
OFF191
IFS5 IEC5 IPC47 IPC47
Yes
GLCD Interrupt
_GLCD_VECTOR
192
OFF192
IFS6
IEC6
IPC48
GPU Interrupt
_GPU_VECTOR
193
OFF193
IFS6
IEC6
IPC48 IPC48
—
—
—
—
Reserved
—
—
IPC48
—
Yes/No(2)
Yes
—
CTMU Interrupt
_CTMU_VECTOR
195
OFF195
IFS6
IEC6
IPC48 IPC48
Yes
ADC End of Scan
_ADC_EOS_VECTOR
196
OFF196
IFS6
IEC6
IPC49
Yes
Note 1:
2:
IPC49
Not all interrupt sources are available on all devices. See the Family Features tables (Table 1 through Table 2) for the list of available peripherals.
Upon Reset, the GLCD interrupt (both HSYNC and VSYNC) are persistent. However, through the IRQCON bit (GLCDINT), the type of interrupt can be
changed to non-persistent.
PIC32MZ Graphics (DA) Family
DS60001361J-page 138
TABLE 7-2:
2015-2021 Microchip Technology Inc.
TABLE 7-2:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source(1)
XC32 Vector Name
IRQ
#
Vector #
Interrupt Bit Location
Flag
Enable
Priority
Sub-priority
Persistent
Interrupt
_ADC_ARDY_VECTOR
197
OFF197
IFS6
IEC6
IPC49 IPC49
Yes
ADC Update Ready
_ADC_URDY_VECTOR
198
OFF198
IFS6
IE6
IPC49 IPC49
Yes
ADC0 Early Interrupt
_ADC0_EARLY_VECTOR
199
OFF199
IFS6
IEC6
IPC49 IPC49
Yes
ADC1 Early Interrupt
_ADC1_EARLY_VECTOR
200
OFF200
IFS6
IEC6
IPC50
IPC50
Yes
ADC2 Early Interrupt
_ADC2_EARLY_VECTOR
201
OFF201
IFS6
IEC6
IPC50
IPC50
Yes
ADC3 Early Interrupt
_ADC3_EARLY_VECTOR
202
OFF202
IFS6 IEC6 IPC50 IPC50
Yes
ADC4 Early Interrupt
_ADC4_EARLY_VECTOR
203
OFF203
IFS6 IEC6 IPC50 IPC50
Yes
—
—
ADC Group Early Interrupt Request _ADC_EARLY_VECTOR
205
OFF205
IFS6 IEC6 IPC51
ADC7 Early Interrupt
_ADC7_EARLY_VECTOR
206
OFF206
IFS6 IEC6 IPC51 IPC51
Yes
ADC0 Warm Interrupt
_ADC0_WARM_VECTOR
207
OFF207
IFS6 IEC6 IPC51 IPC51
Yes
ADC1 Warm Interrupt
_ADC1_WARM_VECTOR
208
OFF208
IFS6 IEC6
IPC52
Yes
ADC2 Warm Interrupt
_ADC2_WARM_VECTOR
209
OFF209
IFS6 IEC6 IPC52
IPC52
Yes
ADC3 Warm Interrupt
_ADC3_WARM_VECTOR
210
OFF210
IFS6 IEC6 IPC52 IPC52
Yes
ADC4 Warm Interrupt
_ADC4_WARM_VECTOR
IFS6 IEC6 IPC52 IPC52
Yes
Reserved
—
—
—
—
IPC52
—
—
IPC51
Yes
211
OFF211
Reserved
—
—
—
—
—
—
—
Reserved
—
—
—
—
—
—
—
214
OFF214
IFS6 IEC6 IPC53 IPC53
Yes
215
OFF215
IFS6 IEC6 IPC53 IPC53
Yes
ADC7 Warm Interrupt
_ADC7_WARM_VECTOR
MPLL Fault Interrupt
_MPLL_FAULT_VECTOR
—
—
Lowest Natural Order Priority
Note 1:
2:
Not all interrupt sources are available on all devices. See the Family Features tables (Table 1 through Table 2) for the list of available peripherals.
Upon Reset, the GLCD interrupt (both HSYNC and VSYNC) are persistent. However, through the IRQCON bit (GLCDINT), the type of interrupt can be
changed to non-persistent.
DS60001361J-page 139
PIC32MZ Graphics (DA) Family
ADC Analog Circuit Ready
Interrupt Control Registers
0000 INTCON
0010
PRISS
0020
INTSTAT
0030 IPTMR
2015-2021 Microchip Technology Inc.
0040
IFS0
0050
IFS1
0060
IFS2
0070
IFS3
0080
IFS4
0090
IFS5
00A0
IFS6
00C0
IEC0
00D0
IEC1
00E0
IEC2
00F0
IEC3
0100
IEC4
0110
IEC5
0120
IEC6
INTERRUPT REGISTER MAP
Bits
31/15
30/14
29/13
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
28/12
27/11
26/10
25/9
24/8
NMIKEY
—
—
—
PRI7SS
MVEC
—
—
PRI3SS
—
—
—
—
—
—
—
—
—
TPC
PRI6SS
PRI2SS
—
—
—
23/7
22/6
21/5
—
—
—
—
—
—
PRI5SS
—
PRI1SS
—
—
SRIPL
20/4
19/3
—
—
INT4EP
INT3EP
—
—
—
18/2
17/1
—
—
INT2EP
INT1EP
PRI4SS
—
—
—
—
16/0
—
0000
INT0EP
0000
0000
SS0
—
0000
0000
SIRQ
0000
0000
IPTMR
OC6IF
IC6EIF
T3IF
ADCD3IF
INT2IF
ADCD2IF
T6IF
OC4IF
OC2IF
IC2IF
IC2EIF
T2IF
INT1IF
ADCD1IF ADCD0IF ADCFLTIF ADCDF6IF ADCDF5IF
OC1IF
ADCDF4IF
IC1IF
ADCDF3IF
IC1EIF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
ADCDF21IF ADCDF1IF ADCDC6IF ADCDC5IF ADCDC4IF ADCDC3IF 0000
15:0 ADCDC2IF ADCDC1IF ADCFIFOIF ADCIF
OC9IF
IC9IF
IC9EIF
T9IF
31:16 ADCD36IF ADCD35IF ADCD34IF ADCD33IF ADCD32IF ADCD31IF ADCD30IF ADCD29IF
OC8IF
ADCD28IF
IC8IF
ADCD27IF
IC8EIF
T8IF
OC7IF
IC7IF
IC7EIF
T7IF
0000
ADCD26IF ADCD25IF ADCD24IF ADCD23IF ADCD22IF ADCD21IF 0000
15:0 ADCD20IF ADCD19IF ADCD18IF ADCD17IF ADCD16IF ADCD15IF ADCD14IF ADCD13IF
31:16 CNKIF
CNJIF
CNHIF
CNGIF
CNFIF
CNEIF
CNDIF
CNCIF
ADCD12IF
CNBIF
ADCD11IF
CNAIF
ADCD10IF
I2C1MIF
ADCD42IF ADCD41IF ADCD40IF ADCD39IF ADCD38IF ADCD37IF 0000
I2C2SIF
I2C2BIF
U2TXIF
U2RXIF
U2EIF
SPI2TXIF 0000
—
CRPTIF(2)
SPI3TXIF SPI3RXIF
15:0 SPI1TXIF
31:16 U3TXIF
SPI1RXIF
U3RXIF
SPI1EIF
U3EIF
15:0 SPI2RXIF
31:16 SDHCIF
SPI2EIF
U6TXIF
DMA7IF
U6RXIF
DMA6IF
U6EIF
15:0 I2C4MIF
31:16
—
I2C4SIF
—
I2C4BIF
—
15:0 ADC0WIF
31:16 OC6IE
ADC7EIF ADCGRPIF
IC6IE
IC6EIE
15:0
IC3EIE
31:16 ADCD4IE
T3IE
ADCD3IE
INT2IE
ADCD2IE
OC5IF
IC5IF
IC5EIF
T5IF
IC4IF
SBIF
SPI3EIF
CFDCIF
ETHIF
CPCIF
CAN2IF
USBSRIF
CAN1IF
ADCD43IF
I2C2MIF
DMA5IF
SPI6TX
DMA4IF
SPI6RXIF
DMA3IF
SPI6IF
DMA2IF
I2C5MIF
DMA1IF
I2C5SIF
DMA0IF
I2C5BIF
USBDMAIF
U5TXIF
U4TXIF
—
U4RXIF
—
U4EIF
—
SQI1IF
—
PREIF
—
FCEIF
MPLLFLTIF
RTCCIF
ADC7WIF
SPI4TXIF
—
—
T6IE
ADC4EIF
OC5IE
ADC3EIF
IC5IE
ADC2EIF
IC5EIE
ADC1EIF
T5IE
ADC0EIF
INT4IE
IC4EIF
ADCD9IF
I2C1SIF
USBIF
U5RXIF
T4IF
ADCD8IF
I2C1BIF
CMP2IF
U5EIF
INT3IF
ADCD7IF
U1TXIF
CMP1IF
SPI5TXIF
OC3IF
ADCD6IF
U1RXIF
PMPEIF
SPI5RXIF
IC3IF
0000
0000
INT4IF
15:0
IC3EIF
31:16 ADCD4IF
IC6IF
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
TABLE 7-3:
ADCD5IF 0000
U1EIF 0000
PMPIF
SPI5EIF
0000
0000
SPI4RXIF SPI4EIF
I2C3MIF
I2C3SIF
I2C3BIF 0000
—
ADC4WIF ADC3WIF ADC2WIF ADC1WIF 0000
ADCURDYIF ADCARDYIF ADCEOSIF
OC4IE
IC4IE
IC4EIE
CTMUIF
T4IE
—
INT3IE
GPUIF
OC3IE
GLCDIF
IC3IE
0000
0000
OC2IE
IC2IE
IC2EIE
T2IE
INT1IE
ADCD1IE ADCD0IE ADCFLTIE ADCDF6IE ADCDF5IE
OC1IE
ADCDF4IE
IC1IE
ADCDF3IE
IC1EIE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
0000
ADCDF2IE ADCDF1IE ADCDC6IE ADCDC5IE ADCDC4IE ADCDC3IE 0000
15:0 ADCDC2IE ADCDC1IE ADCFIFOIE ADCIE
OC9IE
IC9IE
IC9EIE
T9IE
31:16 ADCD36IE ADCD35IE ADCD34IE ADCD33IE ADCD32IE ADCD31IE ADCD30IE ADCD29IE
OC8IE
ADCD28IE
IC8IE
ADCD27IE
IC8EIE
T8IE
OC7IE
IC7IE
IC7EIE
T7IE
0000
ADCD26IE ADCD25IE ADCD24IE ADCD23IE ADCD22IE ADCD21IE 0000
15:0 ADCD20IE ADCD19IE ADCD18IE ADCD17IE ADCD16IE ADCD15IE ADCD14IE ADCD13IE
31:16 CNKIE
CNJIE
CNHIE
CNGIE
CNFIE
CNEIE
CNDIE
CNCIE
ADCD12IE
CNBIE
ADCD11IE
CNAIE
ADCD10IE
I2C1MIE
ADCD42IE ADCD41IE ADCD40IE ADCD39IE ADCD38IE ADCD37IE 0000
I2C2SIE
I2C2BIE
U2TXIE
U2RXIE
U2EIE
SPI2TXIE 0000
—
CRPTIE(2)
SPI3TXIE SPI3RXIE
15:0 SPI1TXIE SPI1RXIE
31:16 U3TXIE
U3RXIE
SPI1EIE
U3EIE
15:0 SPI2RXIE
31:16 SDHCIE
SPI2EIE
U6TXIE
DMA7IE
U6RXIE
DMA6IE
U6EIE
15:0 I2C4MIE
31:16
—
I2C4SIE
—
I2C4BIE
—
U4TXIE
—
15:0 ADC0WIE ADC7EIE ADCGRPIE
—
SBIE
SPI3EIE
DMA5IE
DMA4IE
SPI6TXIE SPI6RXIE
U4RXIE
—
U4EIE
—
ADC4EIE ADC3EIE
CFDCIE
ETHIE
CPCIE
CAN2IE
USBSRIE
CAN1IE
ADCD43IE
I2C2MIE
DMA3IE
SPI6IE
DMA2IE
I2C5MIE
DMA1IE
I2C5SIE
DMA0IE
I2C5BIE
USBDMAIE
U5TXIE
SQI1IE
—
PREIE
—
FCEIE
MPLLFLTIE
RTCCIE
ADC7WIE
SPI4TXIE
—
ADC2EIE
ADC1EIE
ADC0EIE
ADCD9IE
I2C1SIE
USBIE
U5RXIE
ADCD8IE
I2C1BIE
CMP2IE
U5EIE
ADCD7IE
U1TXIE
ADCD6IE
U1RXIE
CMP1IE
PMPEIE
SPI5TXIE SPI5RXIE
ADCD5IE 0000
U1EIE 0000
PMPIE 0000
SPI5EIE 0000
SPI4RXIE SPI4EIE
I2C3MIE
I2C3SIE
I2C3BIE 0000
—
ADC4WIE ADC3WIE ADC2WIE ADC1WIE 0000
ADCURDYIE ADCARDYIE ADCEOSIE CTMUIE
—
GPUIE
GLCDIE
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET,
and INV Registers” for more information.
This bit is only available on devices with a Crypto module.
1:
2:
PIC32MZ Graphics (DA) Family
DS60001361J-page 140
7.3
IPC0
0150
0160
IPC1
IPC2
INTERRUPT REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
31:16
—
—
—
INT0IP
15:0
—
—
—
CS0IP
31:16
—
—
—
15:0
—
—
31:16
—
15:0
26/10
25/9
24/8
20/4
19/3
18/2
17/1
16/0
All Resets
Register
Name(1)
0140
Bit Range
Virtual Address
(BF81_#)
2015-2021 Microchip Technology Inc.
TABLE 7-3:
23/7
22/6
21/5
INT0IS
—
—
—
CS1IP
CS1IS
0000
CS0IS
—
—
—
CTIP
CTIS
0000
OC1IP
OC1IS
—
—
—
IC1IP
IC1IS
0000
—
IC1EIP
IC1EIS
—
—
—
T1IP
T1IS
0000
—
—
IC2IP
IC2IS
—
—
—
IC2EIP
IC2EIS
0000
—
—
—
T2IP
T2IS
—
—
—
INT1IP
INT1IS
0000
31:16
—
—
—
IC3EIP
IC3EIS
—
—
—
T3IP
T3IS
0000
15:0
—
—
—
INT2IP
INT2IS
—
—
—
OC2IP
OC2IS
0000
31:16
—
—
—
T4IP
T4IS
—
—
—
INT3IP
INT3IS
0000
15:0
—
—
—
OC3IP
OC3IS
—
—
—
IC3IP
IC3IS
0000
IPC3
0180
IPC4
0190
IPC5
31:16
15:0
—
—
—
—
—
—
INT4IP
IC4IP
INT4IS
IC4IS
—
—
—
—
—
—
OC4IP
IC4EIP
OC4IS
IC4EIS
0000
0000
01A0
IPC6
31:16
15:0
—
—
—
—
—
—
OC5IP
IC5EIP
OC5IS
IC5EIS
—
—
—
—
—
—
IC5IP
T5IP
IC5IS
T5IS
0000
0000
01B0
IPC7
31:16
15:0
—
—
—
—
—
—
OC6IP
IC6EIP
OC6IS
IC6EIS
—
—
—
—
—
—
IC6IP
T6IP
IC6IS
T6IS
0000
0000
01C0
IPC8
31:16
15:0
—
—
—
—
—
—
OC7IP
IC7EIP
OC7IS
IC7EIS
—
—
—
—
—
—
IC7IP
T7IP
IC7IS
T7IS
0000
0000
01D0
IPC9
31:16
15:0
—
—
—
—
—
—
OC8IP
IC8EIP
OC8IS
IC8EIS
—
—
—
—
—
—
IC8IP
T8IP
IC8IS
T8IS
0000
0000
01E0
IPC10
31:16
15:0
—
—
—
—
—
—
OC9IP
IC9EIP
OC9IS
IC9EIS
—
—
—
—
—
—
IC9IP
T9IP
IC9IS
T9IS
0000
0000
01F0
IPC11
31:16
15:0
—
—
—
—
—
—
ADCDC2IP
ADCFIFOIP
ADCDC2IS
ADCFIFOIS
—
—
—
—
—
—
ADCDC1IP
ADCIP
ADCDC1IS
ADCIS
0000
0000
0200
IPC12
31:16
15:0
—
—
—
—
—
—
ADCDC6IP
ADCDC4IP
ADCDC6S
ADCDC4IS
—
—
—
—
—
—
ADCDC5IP
ADCDC3IP
ADCDC5IS
ADCDC3IS
0000
0000
0210
IPC13
31:16
15:0
—
—
—
—
—
—
ADCDF4IP
ADCDF2IP
ADCDF4IS
ADCDF2IS
—
—
—
—
—
—
ADCDF3IP
ADCDF1IP
ADCDF3IS
ADCDF1IS
0000
0000
0220
IPC14
31:16
15:0
—
—
—
—
—
—
ADCD0IP
ADCDF6IP
ADCD0IS
ADCDF6IS
—
—
—
—
—
—
ADCFLTIP
ADCDF5IP
ADCFLTIS
ADCDF5IS
0000
0000
0230
IPC15
31:16
15:0
—
—
—
—
—
—
ADCD4IP
ADCD2IP
ADCD4IS
ADCD2IS
—
—
—
—
—
—
ADCD3IP
ADCD1IP
ADCD3IS
ADCD1IS
0000
0000
0240
IPC16
31:16
15:0
—
—
—
—
—
—
ADCD8IP
ADCD6IP
ADCD8IS
ADCD6IS
—
—
—
—
—
—
ADCD7IP
ADCD5IP
ADCD7IS
ADCD5IS
0000
0000
0250
IPC17
31:16
15:0
—
—
—
—
—
—
ADCD12IP
ADCD10IP
ADCD12IS
ADCD10IS
—
—
—
—
—
—
ADCD11IP
ADCD9IP
ADCD11IS
ADCD9IS
0000
0000
0260
IPC18
31:16
15:0
—
—
—
—
—
—
ADCD16IP
ADCD14IP
ADCD16IS
ADCD14IS
—
—
—
—
—
—
ADCD15IP
ADCD13IP
ADCD15IS
ADCD13IS
0000
0000
Legend:
Note
1:
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET,
and INV Registers” for more information.
This bit is only available on devices with a Crypto module.
PIC32MZ Graphics (DA) Family
DS60001361J-page 141
0170
0280
IPC20
0290
IPC21
02A0
02B0
IPC22
IPC23
Bits
31/15
30/14
29/13
28/12
27/11
31:16
—
—
—
ADCD20IP
15:0
—
—
—
ADCD18IP
31:16
—
—
—
15:0
—
—
31:16
—
15:0
26/10
25/9
24/8
20/4
19/3
18/2
17/1
16/0
All Resets
Register
Name(1)
IPC19
Bit Range
Virtual Address
(BF81_#)
0270
INTERRUPT REGISTER MAP (CONTINUED)
23/7
22/6
21/5
ADCD20IS
—
—
—
ADCD19IP
ADCD19IS
0000
ADCD18IS
—
—
—
ADCD17IP
ADCD17IS
0000
ADCD24IP
ADCD24IS
—
—
—
ADCD23IP
ADCD23IS
0000
—
ADCD22IP
ADCD22IS
—
—
—
ADCD21IP
ADCD21IS
0000
—
—
ADCD28IP
ADCD28IS
—
—
—
ADCD27IP
ADCD27IS
0000
—
—
—
ADCD26IP
ADCD26IS
—
—
—
ADCD25IP
ADCD25IS
0000
31:16
—
—
—
ADCD32IP
ADCD32IS
—
—
—
ADCD31IP
ADCD31IS
0000
15:0
—
—
—
ADCD30IP
ADCD30IS
—
—
—
ADCD29IP
ADCD29IS
0000
31:16
—
—
—
ADCD36IP
ADCD36IS
—
—
—
ADCD35IP
ADCD35IS
0000
15:0
—
—
—
ADCD34IP
ADCD34IS
—
—
—
ADCD33IP
ADCD33IS
0000
31:16
—
—
—
ADCD40IP
ADCD40IS
—
—
—
ADCD39IP
ADCD39IS
0000
2015-2021 Microchip Technology Inc.
02C0
IPC24
15:0
—
—
—
ADCD38IP
ADCD38IS
—
—
—
ADCD37IP
ADCD37IS
0000
02D0
31:16
IPC25
15:0
—
—
—
—
—
—
USBSRIP
ADCD42IP
USBSRIS
ADCD42IS
—
—
—
—
—
—
ADCD43IP
ADCD41IP
ADCD43IS
ADCD41IS
0000
0000
02E0
IPC26
31:16
15:0
—
—
—
—
—
—
CRPTIP(2)
CFDCIP
CRPTIS(2)
CFDCIS
—
—
—
—
—
—
SBIP
CPCIP
SBIS
CPCIS
0000
0000
02F0
IPC27
31:16
15:0
—
—
—
—
—
—
SPI1TXIP
SPI1EIP
SPI1TXIS
SPI1EIS
—
—
—
—
—
—
SPI1RXIS
—
—
0000
0000
0300
IPC28
31:16
15:0
—
—
—
—
—
—
I2C1BIP
U1RXIP
I2C1BIS
U1RXIS
—
—
—
—
—
—
U1TXIP
U1EIP
U1TXIS
U1EIS
0000
0000
0310
IPC29
31:16
15:0
—
—
—
—
—
—
CNBIP
I2C1MIP
CNBIS
I2C1MIS
—
—
—
—
—
—
CNAIP
I2C1SIP
CNAIS
I2C1SIS
0000
0000
0320
IPC30
31:16
15:0
—
—
—
—
—
—
CNFIP
CNDIP
CNFIS
CNDIS
—
—
—
—
—
—
CNEIP
CNCIP
CNEIS
CNCIS
0000
0000
0330
IPC31
31:16
15:0
—
—
—
—
—
—
CNKIP
CNHIP
CNKIS
CNHIS
—
—
—
—
—
—
CNJIP
CNGIP
CNJIS
CNGIS
0000
0000
0340
IPC32
31:16
15:0
—
—
—
—
—
—
CMP2IP
PMPEIP
CMP2IS
PMPEIS
—
—
—
—
—
—
CMP1IP
PMPIP
CMP1IS
PMPIS
0000
0000
0350
IPC33
31:16
15:0
—
—
—
—
—
—
DMA1IP
USBDMAIP
DMA1IS
USBDMAIS
—
—
—
—
—
—
DMA0IP
USBIP
DMA0IS
USBIS
0000
0000
0360
IPC34
31:16
15:0
—
—
—
—
—
—
DMA5IP
DMA3IP
DMA5IS
DMA3IS
—
—
—
—
—
—
DMA4IP
DMA2IP
DMA4IS
DMA2IS
0000
0000
0370
IPC35
31:16
15:0
—
—
—
—
—
—
SPI2RXIP
DMA7IP
SPI2RXIS
DMA7IS
—
—
—
—
—
—
SPI2EIP
DMA6IP
SPI2EIS
DMA6IS
0000
0000
0380
IPC36
31:16
15:0
—
—
—
—
—
—
U2TXIP
U2EIP
U2TXIS
U2EIS
—
—
—
—
—
—
U2RXIP
SPI2TXIP
U2RXIS
SPI2TXIS
0000
0000
0390
IPC37
31:16
15:0
—
—
—
—
—
—
CAN1IP
I2C2SIP
CAN1IS
I2C2SIS
—
—
—
—
—
—
I2C2MIP
I2C2BIP
I2C2MIS
I2C2BIS
0000
0000
Legend:
Note
1:
2:
—
SPI1RXIP
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET,
and INV Registers” for more information.
This bit is only available on devices with a Crypto module.
PIC32MZ Graphics (DA) Family
DS60001361J-page 142
TABLE 7-3:
IPC38
03B0
03C0
IPC39
IPC40
INTERRUPT REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
31:16
—
—
—
SPI3RXIP
15:0
—
—
—
ETHIP
31:16
—
—
—
15:0
—
—
31:16
—
15:0
26/10
25/9
24/8
20/4
19/3
18/2
17/1
16/0
All Resets
Register
Name(1)
03A0
Bit Range
Virtual Address
(BF81_#)
2015-2021 Microchip Technology Inc.
TABLE 7-3:
23/7
22/6
21/5
SPI3RXIS
—
—
—
SPI3EIP
SPI3EIS
0000
ETHIS
—
—
—
CAN2IP
CAN2IS
0000
U3TXIP
U3TXIS
—
—
—
U3RXIP
U3RXIS
0000
—
U3EIP
U3EIS
—
—
—
SPI3TXIP
SPI3TXIS
0000
—
—
SPI4EIP
SPI4EIS
—
—
—
I2C3MIP
I2C3MIS
0000
—
—
—
I2C3SIP
I2C3SIS
—
—
—
I2C3BIP
I2C3BIS
0000
31:16
—
—
—
FCEIP
FCEIS
—
—
—
RTCCIP
RTCCIS
0000
15:0
—
—
—
SPI4TXIP
SPI4TXIS
—
—
—
SPI4RXIP
SPI4RXIS
0000
31:16
—
—
—
U4RXIP
U4RXIS
—
—
—
U4EIP
U4EIS
0000
15:0
—
—
—
SQI1IP
SQI1IS
—
—
—
PREIP
PREIS
0000
IPC41
03E0
IPC42
03F0
IPC43
31:16
15:0
—
—
—
—
—
—
I2C4MIP
I2C4BIP
I2C4MIS
I2C4BIS
—
—
—
—
—
—
I2C4SIP
U4TXIP
I2C4SIS
U4TXIS
0000
0000
0400
IPC44
31:16
15:0
—
—
—
—
—
—
U5EIP
SPI5RXIP
U5EIS
SPI5RXIS
—
—
—
—
—
—
SPI5TXIP
SPI5EIP
SPI5TXIS
SPI5EIS
0000
0000
0410
IPC45
31:16
15:0
—
—
—
—
—
—
I2C5SIP
U5TXIP
I2C5SIS
U5TXIS
—
—
—
—
—
—
I2C5BIP
U5RXIP
I2C5BIS
U5RXIS
0000
0000
0420
IPC46
31:16
15:0
—
—
—
—
—
—
SPI6TXIP
SPI6EIP
SPI6TXIS
SPI6EIS
—
—
—
—
—
—
SPI6RXIP
I2C5MIP
SPI6RXIS
I2C5MIS
0000
0000
0430
IPC47
31:16
15:0
—
—
—
—
—
—
SDHCIP
U6RXIP
SDHC1IS
U6RXIS
—
—
—
—
—
—
U6TXIP
U6EIP
U6TXIS
U6EIS
0000
0000
0440
IPC48
31:16
15:0
—
—
—
—
—
—
CTMU1IP
GPUIP
CTMU1IS
GPU1IS
—
—
—
—
—
—
—
—
GLCDIS
0000
0000
0450
IPC49
31:16
15:0
—
—
—
—
—
—
ADC0EIP
ADCARDYIP
ADC0EIS
ADCARDYIS
—
—
—
—
—
—
ADCURDYIP
ADCEOSIP
ADCURDYIS
ADCEOSIS
0000
0000
0460
IPC50
31:16
15:0
—
—
—
—
—
—
ADC4EIP
ADC2EIP
ADC4EIS
ADC2EIS
—
—
—
—
—
—
ADC3EIP
ADC1EIP
ADC3EIS
ADC1EIS
0000
0000
0470
IPC51
31:16
15:0
—
—
—
—
—
—
ADC0WIP
ADCGRPIP
ADC0WIS
ADCGRPIS
—
—
—
—
—
—
ADC7EIS
—
—
0000
0000
0480
IPC52
31:16
15:0
—
—
—
—
—
—
ADC4WIP
ADC2WIP
ADC4WIS
ADC2WIS
—
—
—
—
—
—
ADC3WIS
ADC1WIS
0000
0000
0490
IPC53
31:16
15:0
—
—
—
—
—
—
—
MPLLFLTIS
—
—
—
—
—
—
—
—
—
ADC7WIP
—
—
ADC7WIS
—
—
0000
0000
0540 OFF000
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0544 OFF001
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0548 OFF002
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
Legend:
Note
1:
2:
MPLLFLTIP
—
—
—
—
—
GLCDIP
ADC7EIP
—
—
—
ADC3WIP
ADC1WIP
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET,
and INV Registers” for more information.
This bit is only available on devices with a Crypto module.
PIC32MZ Graphics (DA) Family
DS60001361J-page 143
03D0
0550 OFF004
0554 OFF005
0558 OFF006
055C OFF007
0560 OFF008
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/4
19/3
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
21/5
VOFF
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
VOFF
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
054C OFF003
INTERRUPT REGISTER MAP (CONTINUED)
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
2015-2021 Microchip Technology Inc.
31:16
0564 OFF009
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0568 OFF010
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
056C OFF011
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0570 OFF012
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0574 OFF013
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0578 OFF014
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
057C OFF015
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0580 OFF016
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0584 OFF017
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0588 OFF018
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
058C OFF019
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0590 OFF020
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0594 OFF021
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
Legend:
Note
1:
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET,
and INV Registers” for more information.
This bit is only available on devices with a Crypto module.
PIC32MZ Graphics (DA) Family
DS60001361J-page 144
TABLE 7-3:
0598 OFF022
059C OFF023
05A0 OFF024
05A4 OFF025
05A8 OFF026
31:16
INTERRUPT REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21/5
20/4
19/3
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
VOFF
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
2015-2021 Microchip Technology Inc.
TABLE 7-3:
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
05B0 OFF028
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
05B4 OFF029
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
05B8 OFF030
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
05BC OFF031
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
05C0 OFF032
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
05C4 OFF033
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
05C8 OFF034
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
05CC OFF035
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
05D0 OFF036
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
05D4 OFF037
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
05D8 OFF038
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
05DC OFF039
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
05E0 OFF040
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
Legend:
Note
1:
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET,
and INV Registers” for more information.
This bit is only available on devices with a Crypto module.
PIC32MZ Graphics (DA) Family
DS60001361J-page 145
05AC OFF027
05E8 OFF042
05EC OFF043
05F0 OFF044
05F4 OFF045
05F8 OFF046
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/4
19/3
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
21/5
VOFF
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
VOFF
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
05E4 OFF041
INTERRUPT REGISTER MAP (CONTINUED)
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
2015-2021 Microchip Technology Inc.
31:16
05FC OFF047
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0600 OFF048
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0604 OFF049
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0608 OFF059
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
060C OFF051
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0610 OFF052
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0614 OFF053
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0618 OFF054
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
061C OFF055
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0620 OFF056
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0624 OFF057
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0628 OFF058
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
062C OFF059
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
Legend:
Note
1:
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET,
and INV Registers” for more information.
This bit is only available on devices with a Crypto module.
PIC32MZ Graphics (DA) Family
DS60001361J-page 146
TABLE 7-3:
0630 OFF060
0634 OFF061
0638 OFF062
063C OFF063
0640 OFF064
31:16
INTERRUPT REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21/5
20/4
19/3
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
VOFF
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
2015-2021 Microchip Technology Inc.
TABLE 7-3:
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0648 OFF066
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
064C OFF067
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0650 OFF068
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0654 OFF069
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0658 OFF070
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
065C OFF071
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0660 OFF072
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0664 OFF073
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0668 OFF074
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
066C OFF075
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0670 OFF076
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0674 OFF077
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0678 OFF078
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
Legend:
Note
1:
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET,
and INV Registers” for more information.
This bit is only available on devices with a Crypto module.
PIC32MZ Graphics (DA) Family
DS60001361J-page 147
0644 OFF065
0680 OFF080
0684 OFF081
0688 OFF082
068C OFF083
0690 OFF084
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/4
19/3
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
21/5
VOFF
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
VOFF
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
067C OFF079
INTERRUPT REGISTER MAP (CONTINUED)
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
2015-2021 Microchip Technology Inc.
31:16
0694 OFF085
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0698 OFF086
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
069C OFF087
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06A0 OFF088
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06A4 OFF089
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06A8 OFF090
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06AC OFF091
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06B0 OFF092
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06B4 OFF093
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06B8 OFF094
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06BC OFF095
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06C0 OFF096
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06C4 OFF097
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
Legend:
Note
1:
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET,
and INV Registers” for more information.
This bit is only available on devices with a Crypto module.
PIC32MZ Graphics (DA) Family
DS60001361J-page 148
TABLE 7-3:
06C8 OFF098
06CC OFF099
06D0 OFF100
06D4 OFF101
06D8 OFF102
31:16
INTERRUPT REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21/5
20/4
19/3
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
VOFF
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
2015-2021 Microchip Technology Inc.
TABLE 7-3:
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06E0 OFF104
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06E4 OFF105
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06E8 OFF106
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06EC OFF107
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06F4 OFF109
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06F8 OFF110
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
06FC OFF111
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0700 OFF112
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0704 OFF113
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0708 OFF114
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
070C OFF115
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0710 OFF116
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0714 OFF117
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
Legend:
Note
1:
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET,
and INV Registers” for more information.
This bit is only available on devices with a Crypto module.
PIC32MZ Graphics (DA) Family
DS60001361J-page 149
06DC OFF103
071C OFF119
0720 OFF120
0724 OFF121
0728 OFF122
072C OFF123
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/4
19/3
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
21/5
VOFF
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
VOFF
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
0718 OFF118
INTERRUPT REGISTER MAP (CONTINUED)
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
2015-2021 Microchip Technology Inc.
31:16
0730 OFF124
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0734 OFF125
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0738 OFF126
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
073C OFF127
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0740 OFF128
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0744 OFF129
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0748 OFF130
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
074C OFF131
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0750 OFF132
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0754 OFF133
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0758 OFF134
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
075C OFF135
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0760 OFF136
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
Legend:
Note
1:
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET,
and INV Registers” for more information.
This bit is only available on devices with a Crypto module.
PIC32MZ Graphics (DA) Family
DS60001361J-page 150
TABLE 7-3:
0764 OFF137
0768 OFF138
076C OFF139
0770 OFF140
0774 OFF141
31:16
INTERRUPT REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21/5
20/4
19/3
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
VOFF
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
2015-2021 Microchip Technology Inc.
TABLE 7-3:
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
077C OFF143
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0780 OFF144
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0784 OFF145
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0788 OFF146
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
078C OFF147
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0790 OFF148
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0794 OFF149
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0798 OFF150
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
079C OFF151
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
07A0 OFF152
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
07A4 OFF153
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
07A8 OFF154
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
07AC OFF155
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
Legend:
Note
1:
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET,
and INV Registers” for more information.
This bit is only available on devices with a Crypto module.
PIC32MZ Graphics (DA) Family
DS60001361J-page 151
0778 OFF142
07B4 OFF157
07B8 OFF158
07BC OFF159
07C0 OFF160
07C4 OFF161
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/4
19/3
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
21/5
VOFF
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
VOFF
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
07B0 OFF156
INTERRUPT REGISTER MAP (CONTINUED)
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
2015-2021 Microchip Technology Inc.
31:16
07C8 OFF162
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
07CC OFF163
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
07D0 OFF164
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
07D4 OFF165
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
07D8 OFF166
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
07DC OFF167
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
07E0 OFF168
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
07E4 OFF169
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
07E8 OFF170
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
07EC OFF171
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
07F0 OFF172
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
07F4 OFF173
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
07F8 OFF174
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
Legend:
Note
1:
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET,
and INV Registers” for more information.
This bit is only available on devices with a Crypto module.
PIC32MZ Graphics (DA) Family
DS60001361J-page 152
TABLE 7-3:
07FC OFF175
0800 OFF176
0804 OFF177
0808 OFF178
080C OFF179
31:16
INTERRUPT REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21/5
20/4
19/3
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
VOFF
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
2015-2021 Microchip Technology Inc.
TABLE 7-3:
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0814 OFF181
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0818 OFF182
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
081C OFF183
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0820 OFF184
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0824 OFF185
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0828 OFF186
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
082C OFF187
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0830 OFF188
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0834 OFF189
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0838 OFF190
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
083C OFF191
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0840 OFF192
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0844 OFF193
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
Legend:
Note
1:
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET,
and INV Registers” for more information.
This bit is only available on devices with a Crypto module.
PIC32MZ Graphics (DA) Family
DS60001361J-page 153
0810 OFF180
0850 OFF196
0854 OFF197
0858 OFF198
085C OFF199
0860 OFF200
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/4
19/3
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
31:16
21/5
VOFF
15:0
31:16
22/6
VOFF
15:0
31:16
23/7
VOFF
15:0
31:16
24/8
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
VOFF
17/1
16/0
All Resets
Bit Range
Register
Name(1)
Virtual Address
(BF81_#)
084C OFF195
INTERRUPT REGISTER MAP (CONTINUED)
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
VOFF
0000
—
0000
2015-2021 Microchip Technology Inc.
31:16
0864 OFF201
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0868 OFF202
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
086C OFF203
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0874 OFF205
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0878 OFF206
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
087C OFF207
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0880 OFF208
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0884 OFF209
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0888 OFF210
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
08A4 OFF211
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
0898 OFF214
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
089C OFF215
31:16
15:0
—
—
—
—
—
—
—
—
VOFF
—
—
—
—
—
—
VOFF
—
0000
0000
Legend:
Note
1:
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET,
and INV Registers” for more information.
This bit is only available on devices with a Crypto module.
PIC32MZ Graphics (DA) Family
DS60001361J-page 154
TABLE 7-3:
PIC32MZ Graphics (DA) Family
REGISTER 7-1:
Bit
Range
31:24
23:16
15:8
7:0
INTCON: INTERRUPT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
U-0
NMIKEY
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
MVEC
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
TPC
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 NMIKEY: Non-Maskable Interrupt Key bits
When the correct key (0x4E) is written, a software NMI will be generated. The status is indicated by the
GNMI bit (RNMICON).
bit 23-13 Unimplemented: Read as ‘0’
bit 12
MVEC: Multi Vector Configuration bit
1 = Interrupt controller configured for multi-vectored mode
0 = Interrupt controller configured for single vectored mode
bit 11
Unimplemented: Read as ‘0’
bit 10-8 TPC: Interrupt Proximity Timer Control bits
111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer
110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer
101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer
100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer
011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer
010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer
001 = Interrupts of group priority 1 start the Interrupt Proximity timer
000 = Disables Interrupt Proximity timer
bit 7-5
Unimplemented: Read as ‘0’
bit 4
INT4EP: External Interrupt 4 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 3
INT3EP: External Interrupt 3 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 2
INT2EP: External Interrupt 2 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 1
INT1EP: External Interrupt 1 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 0
INT0EP: External Interrupt 0 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
2015-2021 Microchip Technology Inc.
DS60001361J-page 155
PIC32MZ Graphics (DA) Family
REGISTER 7-2:
Bit
Range
PRISS: PRIORITY SHADOW SELECT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
31:24
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
PRI7SS(1)
R/W-0
23:16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRI1SS(1)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRI4SS(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRI2SS(1)
PRI3SS
7:0
Bit
25/17/9/1
PRI6SS(1)
PRI5SS(1)
15:8
Bit
26/18/10/2
R/W-0
U-0
U-0
U-0
R/W-0
—
—
—
SS0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 PRI7SS: Interrupt with Priority Level 7 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 7 uses Shadow Set 0)
0111 = Interrupt with a priority level of 7 uses Shadow Set 7
0110 = Interrupt with a priority level of 7 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 7 uses Shadow Set 1
0000 = Interrupt with a priority level of 7 uses Shadow Set 0
bit 27-24 PRI6SS: Interrupt with Priority Level 6 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 6 uses Shadow Set 0)
0111 = Interrupt with a priority level of 6 uses Shadow Set 7
0110 = Interrupt with a priority level of 6 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 6 uses Shadow Set 1
0000 = Interrupt with a priority level of 6 uses Shadow Set 0
bit 23-20 PRI5SS: Interrupt with Priority Level 5 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 5 uses Shadow Set 0)
0111 = Interrupt with a priority level of 5 uses Shadow Set 7
0110 = Interrupt with a priority level of 5 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 5 uses Shadow Set 1
0000 = Interrupt with a priority level of 5 uses Shadow Set 0
bit 19-16 PRI4SS: Interrupt with Priority Level 4 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 4 uses Shadow Set 0)
0111 = Interrupt with a priority level of 4 uses Shadow Set 7
0110 = Interrupt with a priority level of 4 uses Shadow Set 6
•
•
•
0001 = Interrupt with a priority level of 4 uses Shadow Set 1
0000 = Interrupt with a priority level of 4 uses Shadow Set 0
Note 1:
These bits are ignored if the MVEC bit (INTCON) = 0.
DS60001361J-page 156
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 7-2:
PRISS: PRIORITY SHADOW SELECT REGISTER (CONTINUED)
bit 15-12 PRI3SS: Interrupt with Priority Level 3 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 3 uses Shadow Set 0)
0111 = Interrupt with a priority level of 3 uses Shadow Set 7
0110 = Interrupt with a priority level of 3 uses Shadow Set 6
•
•
•
bit 11-8
0001 = Interrupt with a priority level of 3 uses Shadow Set 1
0000 = Interrupt with a priority level of 3 uses Shadow Set 0
PRI2SS: Interrupt with Priority Level 2 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 2 uses Shadow Set 0)
0111 = Interrupt with a priority level of 2 uses Shadow Set 7
0110 = Interrupt with a priority level of 2 uses Shadow Set 6
•
•
•
bit 7-4
0001 = Interrupt with a priority level of 2 uses Shadow Set 1
0000 = Interrupt with a priority level of 2 uses Shadow Set 0
PRI1SS: Interrupt with Priority Level 1 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 1 uses Shadow Set 0)
0111 = Interrupt with a priority level of 1 uses Shadow Set 7
0110 = Interrupt with a priority level of 1 uses Shadow Set 6
•
•
•
bit 3-1
bit 0
0001 = Interrupt with a priority level of 1 uses Shadow Set 1
0000 = Interrupt with a priority level of 1 uses Shadow Set 0
Unimplemented: Read as ‘0’
SS0: Single Vector Shadow Register Set bit
1 = Single vector is presented with a shadow set
0 = Single vector is not presented with a shadow set
Note 1:
These bits are ignored if the MVEC bit (INTCON) = 0.
2015-2021 Microchip Technology Inc.
DS60001361J-page 157
PIC32MZ Graphics (DA) Family
REGISTER 7-3:
Bit
Range
31:24
23:16
15:8
7:0
INTSTAT: INTERRUPT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
SRIPL(1)
R-0
R-0
R-0
SIRQ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10-8 SRIPL: Requested Priority Level bits for Single Vector Mode bits(1)
111-000 = The priority level of the latest interrupt presented to the CPU
bit 7-0
SIRQ: Last Interrupt Request Serviced Status bits
11111111-00000000 = The last interrupt request number serviced by the CPU
Note 1:
This value should only be used when the interrupt controller is configured for Single Vector mode.
REGISTER 7-4:
Bit
Range
31:24
23:16
15:8
7:0
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR
R/W-0
IPTMR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IPTMR
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
IPTMR: INTERRUPT PROXIMITY TIMER REGISTER
Bit
31/23/15/7
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
IPTMR: Interrupt Proximity Timer Reload bits
Used by the Interrupt Proximity Timer as a reload value when the Interrupt Proximity timer is triggered by
an interrupt event.
DS60001361J-page 158
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 7-5:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
IFSx: INTERRUPT FLAG STATUS REGISTER
Bit
30/22/14/6
Note:
31:24
23:16
15:8
7:0
Note:
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS30
IFS29
IFS28
IFS27
IFS26
IFS25
IFS24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS23
IFS22
IFS21
IFS20
IFS19
IFS18
IFS17
IFS16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS15
IFS14
IFS13
IFS12
IFS11
IFS10
IFS9
IFS8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFS7
IFS6
IFS5
IFS4
IFS3
IFS2
IFS1
IFS0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
IFS31-IFS0: Interrupt Flag Status bits
1 = Interrupt request has occurred
0 = No interrupt request has occurred
This register represents a generic definition of the IFSx register. Refer to Table 7-2 for the exact bit
definitions.
Bit
31/23/15/7
IECx: INTERRUPT ENABLE CONTROL REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC31
IEC30
IEC29
IEC28
IEC27
IEC26
IEC25
IEC24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC23
IEC22
IEC21
IEC20
IEC19
IEC18
IEC17
IEC16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC15
IEC14
IEC13
IEC12
IEC11
IEC10
IEC9
IEC8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IEC7
IEC6
IEC5
IEC4
IEC3
IEC2
IEC1
IEC0
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
Bit
26/18/10/2
R/W-0
REGISTER 7-6:
Bit
Range
Bit
Bit
28/20/12/4 27/19/11/3
IFS31
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
Bit
29/21/13/5
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
IEC31-IEC0: Interrupt Enable bits
1 = Interrupt is enabled
0 = Interrupt is disabled
This register represents a generic definition of the IECx register. Refer to Table 7-2 for the exact bit
definitions.
2015-2021 Microchip Technology Inc.
DS60001361J-page 159
PIC32MZ Graphics (DA) Family
REGISTER 7-7:
Bit
Range
IPCx: INTERRUPT PRIORITY CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
31:24
23:16
15:8
7:0
Legend:
R = Readable bit
-n = Value at POR
Bit
Bit
28/20/12/4 27/19/11/3
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
IP3
R/W-0
R/W-0
IS3
R/W-0
IP2
R/W-0
R/W-0
R/W-0
IP0
R/W-0
IS2
R/W-0
IP1
R/W-0
R/W-0
R/W-0
R/W-0
IS1
R/W-0
R/W-0
R/W-0
IS0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-26 IP3: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 25-24 IS3: Interrupt Sub-priority bits
11 = Interrupt sub-priority is 3
10 = Interrupt sub-priority is 2
01 = Interrupt sub-priority is 1
00 = Interrupt subdirectory is 0
bit 23-21 Unimplemented: Read as ‘0’
bit 20-18 IP2: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 17-16 IS2: Interrupt Sub-priority bits
11 = Interrupt sub-priority is 3
10 = Interrupt sub-priority is 2
01 = Interrupt sub-priority is 1
00 = Interrupt sub-priority is 0
bit 15-13 Unimplemented: Read as ‘0’
Note:
This register represents a generic definition of the IPCx register. Refer to Table 7-2 for the exact bit
definitions.
DS60001361J-page 160
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 7-7:
IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED)
bit 12-10 IP1: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
bit 9-8
bit 7-5
bit 4-2
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
IS1: Interrupt Sub-priority bits
11 = Interrupt sub-priority is 3
10 = Interrupt sub-priority is 2
01 = Interrupt sub-priority is 1
00 = Interrupt sub-priority is 0
Unimplemented: Read as ‘0’
IP0: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
bit 1-0
Note:
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
IS0: Interrupt Sub-priority bits
11 = Interrupt sub-priority is 3
10 = Interrupt sub-priority is 2
01 = Interrupt sub-priority is 1
00 = Interrupt sub-priority is 0
This register represents a generic definition of the IPCx register. Refer to Table 7-2 for the exact bit
definitions.
2015-2021 Microchip Technology Inc.
DS60001361J-page 161
PIC32MZ Graphics (DA) Family
REGISTER 7-8:
Bit
Range
31:24
23:16
15:8
7:0
OFFx: INTERRUPT VECTOR ADDRESS OFFSET REGISTER (x = 0-190)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VOFF
R/W-0
R/W-0
R/W-0
U-0
VOFF
R/W-0
Legend:
R = Readable bit
-n = Value at POR
R/W-0
R/W-0
R/W-0
R/W-0
VOFF
W = Writable bit
‘1’ = Bit is set
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 17-1 VOFF: Interrupt Vector ‘x’ Address Offset bits
bit 0
Unimplemented: Read as ‘0’
DS60001361J-page 162
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
8.0
Note:
OSCILLATOR
CONFIGURATION
This data sheet summarizes the
features of the PIC32MZ DA family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 42. “Oscillators
with Enhanced PLL” (DS60001250) in
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
The PIC32MZ DA oscillator system has the following
modules and features:
• Five external and internal oscillator options as clock
sources
• On-Chip PLL with user-selectable input divider,
multiplier and output divider to boost operating frequency on select internal and external oscillator
sources
• On-Chip user-selectable divisor postscaler on select
oscillator sources
• Software-controllable switching between
various clock sources
• A Fail-Safe Clock Monitor (FSCM) that detects clock
failure and permits safe application recovery or shutdown with dedicated Back-up FRC (BFRC)
• Dedicated On-Chip PLL for DDR2 and USB modules
• Flexible reference clock output
• Multiple clock branches for peripherals for better
performance flexibility
A block diagram of the oscillator system is provided
in Figure 8-1. The clock distribution is shown in
Table 8-1.
2015-2021 Microchip Technology Inc.
DS60001361J-page 163
PIC32MZ Graphics (DA) Family
FIGURE 8-1:
PIC32MZ DA FAMILY OSCILLATOR DIAGRAM
(12 or 24 MHz only)
From POSC
USB Clock (USBCLK)
USB PLL
Reference Clock(5)
REFCLKIx
POSC
FRC
LPRC
SOSC
PBCLK1
SYSCLK
BFRC
System PLL
N
REFOxTRIM
REFOxCON
UPLLFSEL
FVco(6)
FIN(6)
PLL x M
PLLIDIV
PLLRANGE
(N)
PLLMULT
PLLICLK
(M)
PLLODIV
(N)
N
FPLL(6)
ROTRIM (M)
M
2 N + --------512
RODIV (N)
RP(1)
POSC (HS, EC)
RF(2)
Peripheral Bus Clock(5)
Peripherals,
CPU
Postscaler
PBCLKx
Enable
RS(1)
C2
SPLL
Primary Oscillator (POSC)
OSC1
XTAL
REFCLKOx
FREF(6)
To SPI, ADC,
SQI, GLCD,
and SDHC
‘x’ = 1-5
SPLL
ROSEL
C1(3)
OE
(3)
(4)
OSC2
PBxDIV
(N)
‘x’ = 1-7
POSCBOOST
POSCGAIN
To ADC and Flash
FRC
Oscillator
8 MHz typical
Postscaler
TUN
FRCDIV
(N)
N
FRCDIV
Backup FRC
Oscillator
8 MHz typical
Clock
Switch/
Slew
SYSCLK
Fsys(6)
BFRC
LPRC
LPRC
Oscillator
32.768 kHz
Secondary Oscillator (SOSC)
SOSCO
32.768 kHz
SOSC
SOSCEN
Clock Control Logic
SOSCI
MPLL(7)
N
MFIN
xM
MFVCO
N
N
MFMPLL(7)
To DDR2
MPLLIDIV MPLLMULT MPLLODIV1 MPLLODIV2 Controller
(N)
(N)
(N)
(M)
Notes:
1.
2.
3.
4.
5.
6.
7.
FSCM INT
Fail-Safe
Clock
Monitor
SOSCBOOST
SOSCGAIN
FSCM Event
NOSC
COSC
OSWEN
FCKSM
WDT, RTCC
Timer1, RTCC
A series resistor, RS, may be required for AT strip cut crystals, or to eliminate clipping. Alternately, to increase oscillator circuit gain,
add a parallel resistor, RP, with a value of 1 M.
The internal feedback resistor, RF, is typically in the range of 2 to 10 M
Refer to Section 42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for help in determining the best oscillator components.
PBCLK1 divided by 2 is available on the OSC2 pin in certain clock modes.
Shaded regions indicate multiple instantiations of a peripheral or feature.
Refer to Table 44-25 in Section 44.0 “Electrical Characteristics” for frequency limitations.
Memory Phase-Locked Loop (MPLL) is controlled through the CFGMPLL register (see 41.0 “Special Features” for details).
MFMPLL drives the DDR2 PHY and is the source clock (DDRCK, DDRCK) for DDR2 SDRAM.
DS60001361J-page 164
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 8-1:
SYSTEM AND PERIPHERAL CLOCK DISTRIBUTION
Peripheral
CPU
X
DMT
X
X(3)
X
X(3)
REFOCLK5
REFCLKO4
REFCLKO3
REFCLKO2
X
X(3)
GLCD
GPU
X(6)
X
X(3)
DDR2C
X
X(3)
SDHC
Flash
X(2)
X(2)
ADC
X
X
X(3)
Comparator
CTMU
X(3)
X
Crypto
X(3)
RNG
X(3)
USB
X
X(2)
X(3)
X(3)
X
USBCR(7)
X(3)
CAN
X(3)
X(3)
Ethernet
PMP
X(3)
I2 C
X(3)
UART
X(3)
RTCC
X
X(3)
X
EBI
X
X(3)
SQI
SPI
X
X
Timers
X
X(4)
X
X
Output Compare
X
Input Capture
X
X(3)
Ports
DMA
X
Interrupts
X
Prefetch
X
X(5)
OSC2 Pin
X
HLVD
Note 1:
2:
3:
4:
5:
6:
7:
8:
REFCLKO1
X
WDT
DSCTRL(8)
PBCLK7
PBCLK6
PBCLK5
PBCLK4
PBCLK3
PBCLK2
PBCLK1(1)
MPLL
USBCLK
SYSCLK
SOSC
LPRC
FRC
Clock Source
X
X
(3)
PBCLK1 is used by system modules and cannot be turned off.
SYSCLK/PBCLK5 is used to fetch data from/to the Flash Controller, while the FRC clock is used for programming.
Special Function Register (SFR) access only.
Timer1 only.
PBCLK1 divided by 2 is available on the OSC2 pin in certain clock modes.
REFCLKO5 is used for the Pixel Clock
.
USBCR is the Clock/Reset Control block for the USB.
DSCTRL is the Deep Sleep Control Block.
2015-2021 Microchip Technology Inc.
DS60001361J-page 165
PIC32MZ Graphics (DA) Family
8.1
Fail-Safe Clock Monitor (FSCM)
The PIC32MZ DA oscillator system includes a Fail-safe
Clock Monitor (FSCM). The FSCM monitors the
SYSCLK for continuous operation. If it detects that the
SYSCLK has failed, it switches the SYSCLK over to the
BFRC oscillator and triggers a NMI. The BFRC is an
untuned 8 MHz oscillator that will drive the SYSCLK
during FSCM event. When the NMI is executed, software can attempt to restart the main oscillator or shut
down the system.
In Sleep mode both the SYSCLK and the FSCM halt,
which prevents FSCM detection.
DS60001361J-page 166
2015-2021 Microchip Technology Inc.
Oscillator Control Registers
1200
OSCCON
1210
OSCTUN
1220
OSCILLATOR CONFIGURATION REGISTER MAP
SPLLCON
1280 REFO1CON
12A0 REFO2CON
12B0 REFO2TRIM
12C0 REFO3CON
12D0 REFO3TRIM
12E0 REFO4CON
12F0 REFO4TRIM
1300 REFO5CON
1310 REFO5TRIM
1340
PB1DIV
DS60001361J-page 167
1350
PB2DIV
1360
PB3DIV
1370
PB4DIV
31/15
30/14
31:16
—
—
15:0
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
—
—
—
—
—
PLLODIV
—
—
—
—
PLLIDIV
15:0
—
31:16
—
15:0
ON
29/13
28/12
27/11
—
—
—
—
COSC
26/10
25/9
24/8
23/7
22/6
21/5
FRCDIV
DRMEN
—
SLP2SPD
NOSC
CLKLOCK
—
—
—
—
—
—
—
—
—
—
—
31:16
—
15:0
ON
—
SIDL
OE
—
—
—
PLLICLK
RSLP
—
DIVSWEN
ACTIVE
—
—
—
—
—
SIDL
—
RSLP
—
DIVSWEN
ACTIVE
31:16
—
15:0
ON
—
—
—
—
—
—
—
—
SIDL
OE
31:16
—
—
—
RSLP
—
DIVSWEN
ACTIVE
—
ROTRIM
15:0
—
31:16
—
15:0
ON
—
—
—
—
—
—
—
—
—
SIDL
OE
RSLP
—
DIVSWEN
ACTIVE
—
ROTRIM
—
31:16
—
15:0
ON
—
—
—
CF
—
SOSCEN
—
—
—
—
—
—
—
—
—
—
—
—
TUN
SIDL
—
31:16
RSLP
—
DIVSWEN
ACTIVE
—
ROTRIM
0000
00xx
PLLMULT
01xx
—
—
—
—
PLLRANGE
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
0x0x
0000
ROSEL
0000
0000
ROSEL
0000
0000
ROSEL
0000
0000
ROSEL
0000
RODIV
—
0020
OSWEN xx0x
RODIV
31:16
15:0
—
SLPEN
16/0
RODIV
0000
ROSEL
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
1:
—
ROTRIM
—
17/1
RODIV
31:16
15:0
18/2
—
ROTRIM
—
19/3
RODIV
31:16
15:0
20/4
PBDIV
—
—
—
—
8801
PBDIV
—
—
—
—
8801
PBDIV
—
—
—
—
PBDIV
0000
0000
8801
0000
8801
PIC32MZ Graphics (DA) Family
1290 REFO1TRIM
Bit Range
Bits
All Resets(1)
Register
Name
TABLE 8-2:
Virtual Address
(BF80_#)
2015-2021 Microchip Technology Inc.
8.2
Register
Name
PB5DIV
1390
PB6DIV
13A0
13C0
13D0
PB7DIV
SLEWCON
CLKSTAT
Bit Range
Bits
31/15
30/14
29/13
28/12
31:16
—
—
—
15:0
ON
—
—
31:16
—
—
15:0
ON
31:16
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
—
—
—
—
—
—
—
—
—
—
PBDIVRDY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PBDIVRDY
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
—
—
PBDIVRDY
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
UPEN
DNEN
BUSY
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
SPLLRDY
—
—
POSCRDY
—
SLWDIV
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
1:
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
All Resets(1)
Virtual Address
(BF80_#)
1380
OSCILLATOR CONFIGURATION REGISTER MAP (CONTINUED)
PBDIV
—
—
—
—
8801
PBDIV
—
—
—
—
0000
8803
PBDIV
LPRCRDY SOSCRDY
0000
0000
8800
SYSDIV
0000
FRCRDY 0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 168
TABLE 8-2:
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 8-1:
Bit
Range
31:24
23:16
15:8
7:0
OSCCON: OSCILLATOR CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
Bit
26/18/10/2
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
FRCDIV
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
DRMEN
—
SLP2SPD
—
—
—
—
—
U-0
R-0
R-0
R-0
U-0
R/W-y
R/W-y
R/W-y
—
COSC
—
U-0
NOSC
R/W-0
U-0
U-0
R/W-0
R/W-0, HS
U-0
R/W-y
R/W-y
CLKLOCK
—
—
SLPEN
CF
—
SOSCEN
OSWEN(1)
Legend:
R = Readable bit
-n = Value at POR
y = Value set from Configuration bits on POR
HS = Hardware Set
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-24 FRCDIV: Internal Fast RC (FRC) Oscillator Clock Divider bits
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2
000 = FRC divided by 1 (default setting)
bit 23
DRMEN: Dream Mode Enable bit
1 = Dream mode is enabled
0 = Dream mode is disabled
bit 22
Unimplemented: Read as ‘0’
bit 21
SLP2SPD: Sleep Two-speed Start-up Control bit
1 = Use FRC as SYSCLK until the selected clock is ready
0 = Use the selected clock directly
bit 20-15 Unimplemented: Read as ‘0’
bit 14-12 COSC: Current Oscillator Selection bits
111 = System PLL (SPLL)
110 = Back-up Fast RC (BFRC) Oscillator
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Reserved
010 = Primary Oscillator (POSC) (HS or EC)
001 = System PLL (SPLL)
000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (FRCDIV)
bit 11
Unimplemented: Read as ‘0’
Note 1:
Note:
The reset value for this bit depends on the setting of the IESO bit (DEVCFG1). When IESO = 1, the
reset value is ‘1’. When IESO = 0, the reset value is ‘0’.
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL”
(DS60001250) in the “PIC32 Family Reference Manual” for details.
2015-2021 Microchip Technology Inc.
DS60001361J-page 169
PIC32MZ Graphics (DA) Family
REGISTER 8-1:
bit 10-8
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
Note:
OSCCON: OSCILLATOR CONTROL REGISTER
NOSC: New Oscillator Selection bits
111 = System PLL (SPLL)
110 = Reserved
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Reserved
010 = Primary Oscillator (POSC) (HS or EC)
001 = System PLL (SPLL)
000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV bits (FRCDIV)
On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1).
CLKLOCK: Clock Selection Lock Enable bit
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified
Unimplemented: Read as ‘0’
SLPEN: Sleep Mode Enable bit
1 = Device will enter Sleep mode when a WAIT instruction is executed
0 = Device will enter Idle mode when a WAIT instruction is executed
CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
Unimplemented: Read as ‘0’
SOSCEN: Secondary Oscillator (SOSC) Enable bit
1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator
OSWEN: Oscillator Switch Enable bit(1)
1 = Initiate an oscillator switch to selection specified by NOSC bits
0 = Oscillator switch is complete
The reset value for this bit depends on the setting of the IESO bit (DEVCFG1). When IESO = 1, the
reset value is ‘1’. When IESO = 0, the reset value is ‘0’.
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL”
(DS60001250) in the “PIC32 Family Reference Manual” for details.
DS60001361J-page 170
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 8-2:
Bit
Range
31:24
23:16
15:8
7:0
OSCTUN: FRC TUNING REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
TUN(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-6
Unimplemented: Read as ‘0’
bit 5-0
TUN: FRC Oscillator Tuning bits(1)
100000 = Center frequency -4%
100001 =
•
•
•
111111 =
000000 = Center frequency; Oscillator runs at nominal frequency (8 MHz)
000001 =
•
•
•
011110 =
011111 = Center frequency +4%
x = Bit is unknown
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither
characterized, nor tested.
Note:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced
PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
2015-2021 Microchip Technology Inc.
DS60001361J-page 171
PIC32MZ Graphics (DA) Family
REGISTER 8-3:
Bit
Range
31:24
23:16
15:8
7:0
SPLLCON: SYSTEM PLL CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
R/W-y
R/W-y
R/W-y
—
—
—
—
—
U-0
R/W-y
R/W-y
R/W-y
R/W-y
U-0
U-0
U-0
R/W-y
U-0
U-0
PLLICLK
—
—
R/W-y
R/W-y
U-0
R/W-y
R/W-y
R/W-y
U-0
U-0
R/W-y
—
—
—
U-0
PLLODIV
R/W-y
PLLMULT
—
PLLIDIV
R/W-y
R/W-y
PLLRANGE
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-24 PLLODIV: System PLL Output Clock Divider bits
111 = Reserved
110 = Reserved
101 = PLL Divide by 32
100 = PLL Divide by 16
011 = PLL Divide by 8
010 = PLL Divide by 4
001 = PLL Divide by 2
000 = Reserved
The default setting is specified by the FPLLODIV Configuration bits in the DEVCFG2 register. Refer
to Register 34-5 in Section 34.0 “Special Features” for information.
bit 23
Unimplemented: Read as ‘0’
bit 22-16 PLLMULT: System PLL Multiplier bits
1111111 = Multiply by 128
1111110 = Multiply by 127
1111101 = Multiply by 126
1111100 = Multiply by 125
•
•
•
0000000 = Multiply by 1
The default setting is specified by the FPLLMULT Configuration bits in the DEVCFG2 register. Refer
to Register 34-5 in Section 34.0 “Special Features” for information.
bit 15-11 Unimplemented: Read as ‘0’
Note 1:
2:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced
PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
Writes to this register are not allowed if the SPLL is selected as a clock source (COSC = 001).
DS60001361J-page 172
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 8-3:
bit 10-8
SPLLCON: SYSTEM PLL CONTROL REGISTER
PLLIDIV: System PLL Input Clock Divider bits
111 = Divide by 8
110 = Divide by 7
101 = Divide by 6
100 = Divide by 5
011 = Divide by 4
010 = Divide by 3
001 = Divide by 2
000 = Divide by 1
The default setting is specified by the FPLLIDIV Configuration bits in the DEVCFG2 register. Refer to
Register 34-5 in Section 34.0 “Special Features” for information. If the PLLICLK is set for FRC, this setting
is ignored by the PLL and the divider is set to Divide-by-1.
bit 7
PLLICLK: System PLL Input Clock Source bit
1 = FRC is selected as the input to the System PLL
0 = POSC is selected as the input to the System PLL
The POR default is specified by the FPLLICLK Configuration bit in the DEVCFG2 register. Refer to
Register 34-5 in Section 34.0 “Special Features” for information.
bit 6-3
Unimplemented: Read as ‘0’
bit 2-0
PLLRANGE: System PLL Frequency Range Selection bits
111 = Reserved
110 = Reserved
101 = 34-64 MHz
100 = 21-42 MHz
011 = 13-26 MHz
010 = 8-16 MHz
001 = 5-10 MHz
000 = Bypass
The default setting is specified by the FPLLRNG Configuration bits in the DEVCFG2 register. Refer to
Register 34-5 in Section 34.0 “Special Features” for information.
Note 1:
2:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced
PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
Writes to this register are not allowed if the SPLL is selected as a clock source (COSC = 001).
2015-2021 Microchip Technology Inc.
DS60001361J-page 173
PIC32MZ Graphics (DA) Family
REGISTER 8-4:
Bit
Range
31:24
23:16
15:8
7:0
REFOxCON: REFERENCE OSCILLATOR CONTROL REGISTER (‘x’ = 1-5)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RODIV
R/W-0
R/W-0
R/W-0
R/W-0
RODIV
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0, HC
R-0, HS, HC
ON(1)
—
SIDL
OE
RSLP(2)
—
DIVSWEN
ACTIVE(1)
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Cleared
W = Writable bit
‘1’ = Bit is set
ROSEL(3)
HS = Hardware Set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Unimplemented: Read as ‘0’
bit 30-16 RODIV Reference Clock Divider bits
This value specifies 1/2 period of the reference clock in the source clocks.
111111111111111 = REFO clock is Base clock frequency divided by 65,534 (32,767*2)
111111111111110 = REFO clock is Base clock frequency divided by 65,532 (32,766*2)
•
•
•
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-4
Note 1:
2:
3:
4:
000000000000011 = REFO clock is Base clock frequency divided by 6 (3*2)
000000000000010 = REFO clock is Base clock frequency divided by 4 (2*2)
000000000000001 = REFO clock is Base clock frequency divided by 2 (1*2)
000000000000000 = REFO is the same frequency as Base Clock (no divider)
ON: Output Enable bit(1)
1 = Reference Oscillator Module enabled
0 = Reference Oscillator Module disabled
Unimplemented: Read as ‘0’
SIDL: Peripheral Stop in Idle Mode bit
1 = Discontinue module operation when the device enters Idle mode
0 = Continue module operation in Idle mode
OE: Reference Clock Output Enable bit
1 = Reference clock is driven out on REFCLKOx pin
0 = Reference clock is not driven out on REFCLKOx pin
RSLP: Reference Oscillator Module Run in Sleep bit(2)
1 = Reference Oscillator Module output continues to run in Sleep
0 = Reference Oscillator Module output is disabled in Sleep
Unimplemented: Read as ‘0’
DIVSWEN: Divider Switch Enable bit
1 = Divider switch is in progress
0 = Divider switch is complete
ACTIVE: Reference Clock Request Status bit(1)
1 = Reference clock request is active
0 = Reference clock request is not active
Unimplemented: Read as ‘0’
Do not write to this register when the ON bit is not equal to the ACTIVE bit.
This bit is ignored when the ROSEL bits = 0000 or 0001.
The ROSEL bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result.
REFCLKI2 and REFCLKI5 do not exist and are therefore not selectable.
DS60001361J-page 174
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 8-4:
REFOxCON: REFERENCE OSCILLATOR CONTROL REGISTER (‘x’ = 1-5)
bit 3-0
ROSEL: Reference Clock Source Select bits(3)
1111 = Reserved
•
•
•
1001 = BFRC
1000 = REFCLKIx(4)
0111 = System PLL output
0110 = Reserved
0101 = Sosc
0100 = LPRC
0011 = FRC
0010 = Posc
0001 = PBCLK1
0000 = SYSCLK
Note 1:
2:
3:
4:
Do not write to this register when the ON bit is not equal to the ACTIVE bit.
This bit is ignored when the ROSEL bits = 0000 or 0001.
The ROSEL bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result.
REFCLKI2 and REFCLKI5 do not exist and are therefore not selectable.
2015-2021 Microchip Technology Inc.
DS60001361J-page 175
PIC32MZ Graphics (DA) Family
REGISTER 8-5:
Bit
Range
31:24
23:16
15:8
7:0
REFOxTRIM: REFERENCE OSCILLATOR TRIM REGISTER (‘x’ = 1-4)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
ROTRIM
R/W-0
R-0
U-0
U-0
U-0
U-0
U-0
ROTRIM
—
—
—
—
—
—
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-23 ROTRIM: Reference Oscillator Trim bits
111111111 = 511/512 divisor added to RODIV value
111111110 = 510/512 divisor added to RODIV value
•
•
•
100000000 = 256/512 divisor added to RODIV value
•
•
•
000000010 = 2/512 divisor added to RODIV value
000000001 = 1/512 divisor added to RODIV value
000000000 = 0 divisor added to RODIV value
bit 22-0
Note 1:
2:
3:
Unimplemented: Read as ‘0’
While the ON bit (REFOxCON) is ‘1’, writes to this register do not take effect until the DIVSWEN bit is
also set to ‘1’.
Do not write to this register when the ON bit (REFOxCON) is not equal to the ACTIVE bit
(REFOxCON).
Specified values in this register do not take effect if RODIV (REFOxCON) = 0.
DS60001361J-page 176
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 8-6:
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
(1)
U-0
U-0
U-0
R-1
U-0
U-0
U-0
—
—
—
PBDIVRDY
—
—
—
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ON
7:0
PBxDIV: PERIPHERAL BUS ‘x’ CLOCK DIVISOR CONTROL REGISTER (‘x’ = 1-7)
—
PBDIV
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Peripheral Bus ‘x’ Output Clock Enable bit(1)
1 = Output clock is enabled
0 = Output clock is disabled
bit 14-12 Unimplemented: Read as ‘0’
bit 11
PBDIVRDY: Peripheral Bus ‘x’ Clock Divisor Ready bit
1 = Clock divisor logic is not switching divisors and the PBxDIV bits may be written
0 = Clock divisor logic is currently switching values and the PBxDIV bits cannot be written
bit 10-7
Unimplemented: Read as ‘0’
bit 6-0
PBDIV: Peripheral Bus ‘x’ Clock Divisor Control bits
1111111 = PBCLKx is SYSCLK divided by 128
1111110 = PBCLKx is SYSCLK divided by 127
•
•
•
0000011 = PBCLKx is SYSCLK divided by 4
0000010 = PBCLKx is SYSCLK divided by 3
0000001 = PBCLKx is SYSCLK divided by 2 (default value for x < 7)
0000000 = PBCLKx is SYSCLK divided by 1 (default value for x 7)
Note 1: The clock for peripheral bus 1 cannot be turned off. Therefore, the ON bit in the PB1DIV register cannot
be written as a ‘0’.
2: For PB5DIV, when USB is enabled, PBCLK5 minimum frequency must be > 60 MHz.
Note:
Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL”
(DS60001250) in the “PIC32 Family Reference Manual” for details.
2015-2021 Microchip Technology Inc.
DS60001361J-page 177
PIC32MZ Graphics (DA) Family
REGISTER 8-7:
Bit
Range
31:24
23:16
15:8
7:0
SLEWCON: OSCILLATOR SLEW CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R-0, HS, HC
—
—
—
—
—
UPEN
DNEN
BUSY
SYSDIV(1)
R/W-0
R/W-0
R/W-0
SLWDIV
Legend:
HC = Hardware Cleared HS = Hardware Set
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-20 Unimplemented: Read as ‘0’
bit 19-16 SYSDIV: System Clock Divide Control bits(1)
1111 = SYSCLK is divided by 16
1110 = SYSCLK is divided by 15
•
•
•
0010 = SYSCLK is divided by 3
0001 = SYSCLK is divided by 2
0000 = SYSCLK is not divided
bit 15-11 Unimplemented: Read as ‘0’
bit 10-8
SLWDIV: Slew Divisor Steps Control bits
These bits control the maximum division steps used when slewing during a frequency change.
111 = Steps are divide by 128, 64, 32, 16, 8, 4, 2, and then no divisor
110 = Steps are divide by 64, 32, 16, 8, 4, 2, and then no divisor
101 = Steps are divide by 32, 16, 8, 4, 2, and then no divisor
100 = Steps are divide by 16, 8, 4, 2, and then no divisor
011 = Steps are divide by 8, 4, 2, and then no divisor
010 = Steps are divide by 4, 2, and then no divisor
001 = Steps are divide by 2, and then no divisor
000 = No divisor is used during slewing
The steps apply in reverse order (i.e., 2, 4, 8, etc.) during a downward frequency change.
bit 7-3
Unimplemented: Read as ‘0’
bit 2
UPEN: Upward Slew Enable bit
1 = Slewing enabled for switching to a higher frequency
0 = Slewing disabled for switching to a higher frequency
bit 1
DNEN: Downward Slew Enable bit
1 = Slewing enabled for switching to a lower frequency
0 = Slewing disabled for switching to a lower frequency
bit 0
BUSY: Clock Switching Slewing Active Status bit
1 = Clock frequency is being actively slewed to the new frequency
0 = Clock switch has reached its final value
Note 1:
The SYSDIV bit settings are ignored if both UPEN and DNEN = 0, and SYSCLK will be divided by 1.
DS60001361J-page 178
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
CLKSTAT: OSCILLATOR CLOCK STATUS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
Bit
30/22/14/6 29/21/13/5
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
U-0
R-0
R-0
U-0
R-0
U-0
R-0
SPLLRDY
—
—
POSCRDY
—
FRCRDY
LPRCRDY SOSCRDY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-8
Unimplemented: Read as ‘0’
bit 7
SPLLRDY: System PLL (SPLL) Ready Status bit
1 = SPLL is ready
0 = SPLL is not ready
bit 6
Unimplemented: Read as ‘0’
bit 5
LPRCRDY: Low-Power RC (LPRC) Oscillator Ready Status bit
1 = LPRC is stable and ready
0 = LPRC is disabled or not operating
bit 4
SOSCRDY: Secondary Oscillator (SOSC) Ready Status bit
1 = SOSC is stable and ready
0 = SOSC is disabled or not operating
bit 3
Unimplemented: Read as ‘0’
bit 2
POSCRDY: Primary Oscillator (POSC) Ready Status bit
1 = POSC is stable and ready
0 = POSC is disabled or not operating
bit 1
Unimplemented: Read as ‘0’
bit 0
FRCRDY: Fast RC (FRC) Oscillator Ready Status bit
1 = FRC is stable and ready
0 = FRC is disabled for not operating
2015-2021 Microchip Technology Inc.
x = Bit is unknown
DS60001361J-page 179
PIC32MZ Graphics (DA) Family
DS60001361J-page 180
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
9.0
PREFETCH MODULE
Note:
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 41. “Prefetch
Module for Devices with L1 CPU
Cache” (DS60001183), which is available
from the Documentation > Reference
Manual section of the Microchip PIC32
web site (www.microchip.com/pic32).
The Prefetch module is a performance enhancing
module that is included in PIC32MZ DA family devices.
When running at high-clock rates, Wait states must be
inserted into Program Flash Memory (PFM) read
transactions to meet the access time of the PFM. Wait
states can be hidden to the core by prefetching and
storing instructions in a temporary holding area that the
CPU can access quickly. Although the data path to the
CPU is 32 bits wide, the data path to the PFM is 128
bits wide. This wide data path provides the same
bandwidth to the CPU as a 32-bit path running at four
times the frequency.
FIGURE 9-1:
The Prefetch module holds a subset of PFM in
temporary holding spaces known as lines. Each line
contains a tag and data field. Normally, the lines hold a
copy of what is currently in memory to make
instructions or data available to the CPU without Flash
Wait states.
9.1
Features
The Prefetch module includes the following key
features:
•
•
•
•
•
•
•
4x16 byte fully-associative lines
One line for CPU instructions
One line for CPU data
Two lines for peripheral data
16-byte parallel memory fetch
Configurable predictive prefetch
Error detection and correction
A simplified block diagram of the Prefetch module is
shown in Figure 9-1.
PREFETCH MODULE BLOCK DIAGRAM
SYSCLK
CPU
Prefetch Buffer
Data
CPU
Tag
Bus Control
Line Control
Program Flash Memory (PFM)
2015-2021 Microchip Technology Inc.
DS60001361J-page 181
Prefetch Control Registers
Virtual Address
(BF8E_#)
Register
Name(1)
TABLE 9-1:
0000
PRECON
0010
PREFETCH REGISTER MAP
PRESTAT
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
—
—
—
—
PFMSECEN
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
PFMDED
PFMSEC
—
—
—
—
15:0
—
—
—
—
—
—
—
—
21/5
20/4
19/3
18/2
—
—
—
—
PREFEN
—
—
—
—
PFMSECCNT
17/1
16/0
—
—
PFMWS
—
—
All Resets
Bit Range
Bits
0000
0007
—
0000
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 182
9.2
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 9-1:
Bit Range
PRECON: PREFETCH MODULE CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
31:24
23:16
15:8
7:0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-0
U-0
U-0
—
—
—
—
—
PFMSECEN
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
U-0
R/W-1
R/W-1
—
—
PREFEN
—
R/W-1
(1)
PFMWS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27
Unimplemented: Write ‘0’; ignore read
bit 26
PFMSECEN: Flash SEC Interrupt Enable bit
1 = Generate an interrupt when the PFMSEC bit (PRESTAT) is set
0 = Do not generate an interrupt when the PFMSEC bit is set
bit 25-6
Unimplemented: Write ‘0’; ignore read
bit 5-4
PREFEN: Predictive Prefetch Enable bits
11 = Enable predictive prefetch for any address
10 = Enable predictive prefetch for CPU instructions and CPU data
01 = Enable predictive prefetch for CPU instructions only
00 = Disable predictive prefetch
bit 3
Unimplemented: Write ‘0’; ignore read
bit 2-0
PFMWS: PFM Access Time Defined in Terms of SYSCLK Wait States bits(1)
111 = Seven Wait states
•
•
•
010 = Two Wait states
001 = One Wait state
000 = Zero Wait states
Note 1:
For the Wait states to SYSCLK relationship, refer to Table 44-16 in Section44.0 “Electrical
Characteristics”.
2015-2021 Microchip Technology Inc.
DS60001361J-page 183
PIC32MZ Graphics (DA) Family
Register 9-1:
PRESTAT: Prefetch Module Status Register
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
31:24
23:16
15:8
7:0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
R/W-0, HS
R/W-0, HS
U-0
U-0
—
—
—
—
PFMDED
PFMSEC
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PFMSECCNT
Legend:
HS = Hardware Set
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 Unimplemented: Write ‘0’; ignore read
bit 27
PFMDED: Flash Double-bit Error Detected (DED) Status bit
This bit is set in hardware and can only be cleared (i.e., set to ‘0’) in software.
1 = A DED error has occurred
0 = A DED error has not occurred
bit 26
PFMSEC: Flash Single-bit Error Corrected (SEC) Status bit
1 = A SEC error occurred when PFMSECCNT was equal to zero
0 = A SEC error has not occurred
bit 25-8
Unimplemented: Write ‘0’; ignore read
bit 7-0
PFMSECCNT: Flash SEC Count bits
11111111 - 00000000 = SEC count
DS60001361J-page 184
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
10.0
Note:
DIRECT MEMORY ACCESS
(DMA) CONTROLLER
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 31. “Direct Memory
Access
(DMA)
Controller”
(DS60001117), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The Direct Memory Access (DMA) Controller is a bus
host module useful for data transfers between different
devices without CPU intervention. The source and destination of a DMA transfer can be any of the memory
mapped modules existent in the device such as SPI,
UART, PMP, etc., or memory itself.
Following are key features of the DMA Controller module:
• Eight identical channels, each featuring:
- Auto-increment source and destination
address registers
- Source and destination pointers
- Memory to memory and memory to
peripheral transfers
• Automatic word-size detection:
- Transfer granularity, down to byte level
- Bytes need not be word-aligned at source and
destination
FIGURE 10-1:
Interrupt Controller
Peripheral Bus
• Fixed priority channel arbitration
• Flexible DMA channel operating modes:
- Manual (software) or automatic (interrupt) DMA
requests
- One-Shot or Auto-Repeat Block Transfer modes
- Channel-to-channel chaining
• Flexible DMA requests:
- A DMA request can be selected from any of the
peripheral interrupt sources
- Each channel can select any (appropriate)
observable interrupt as its DMA request source
- A DMA transfer abort can be selected from any
of the peripheral interrupt sources
- Up to 2-byte Pattern (data) match transfer
termination
• Multiple DMA channel status interrupts:
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half full
- DMA transfer aborted due to an external event
- Invalid DMA address generated
• DMA debug support features:
- Most recent error address accessed by a DMA
channel
- Most recent DMA channel to transfer data
• CRC Generation module:
- CRC module can be assigned to any of the
available channels
- CRC module is highly configurable
DMA BLOCK DIAGRAM
System IRQ
Address Decoder
SE
Channel 0 Control
I0
Channel 1 Control
I1
DMA
SYSCLK
L
Y
Bus
Interface
System Bus + Bus Arbitration
I2
Global Control
(DMACON)
Channel n Control
In
SE
L
Channel Priority
Arbitration
2015-2021 Microchip Technology Inc.
DS60001361J-page 185
DMA Control Registers
Virtual Address
(BF81_#)
Register
Name(1)
TABLE 10-1:
1000
DMACON
1010
DMASTAT
DMA GLOBAL REGISTER MAP
1020 DMAADDR
31/15
30/14
29/13
31:16
—
—
—
15:0
ON
—
—
31:16
RDWR
—
—
—
15:0
—
—
—
—
All Resets
Bit Range
Bits
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
SUSPEND DMABUSY
31:16
DMACH
0000
0000
DMAADDR
15:0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
DMA CRC REGISTER MAP
1030 DCRCCON
1040 DCRCDATA
2015-2021 Microchip Technology Inc.
1050 DCRCXOR
31/15
30/14
31:16
—
—
15:0
—
—
31:16
15:0
31:16
15:0
29/13
28/12
BYTO
—
27/11
WBO
26/10
25/9
24/8
—
—
BITO
PLEN
23/7
—
CRCEN
DCRCDATA
DCRCXOR
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
—
—
CRCAPP CRCTYP
17/1
16/0
—
—
CRCCH
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF81_#)
TABLE 10-2:
0000
0000
0000
0000
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 186
10.1
Virtual Address
(BF81_#)
1060 DCH0CON
1070 DCH0ECON
1080
DCH0INT
1090 DCH0SSA
10A0 DCH0DSA
10C0 DCH0DSIZ
10D0 DCH0SPTR
10E0 DCH0DPTR
10F0 DCH0CSIZ
1100 DCH0CPTR
DCH0DAT
1120 DCH1CON
1130 DCH1ECON
1140
DCH1INT
DS60001361J-page 187
1150 DCH1SSA
1160 DCH1DSA
30/14
29/13
15:0 CHBUSY
—
CHPIGNEN
—
31:16
—
—
—
31:16
28/12
27/11
26/10
25/9
24/8
23/7
—
—
CHPATLEN
—
—
CHCHNS
CHEN
CHAED
—
—
—
—
CHPIGN
—
15:0
CHSIRQ
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
CHCHN
CHAEN
—
—
—
—
CHEDET
—
7700
CHPRI
0000
FF00
CHAIRQ
CFORCE CABORT
All Resets
Bit Range
31/15
00FF
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7700
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
0000
FF00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
0000
0000
xxxx
CHCPTR
15:0
—
—
0000
CHPDAT
31:16
CHPIGN
15:0 CHBUSY
—
CHPIGNEN
—
CHPATLEN
—
—
CHCHNS
31:16
—
—
—
—
—
—
—
—
15:0
CHSIRQ
0000
xxxx
CHCSIZ
15:0
31:16
—
CHDPTR
15:0
31:16
xxxx
—
CHSPTR
15:0
31:16
—
CHDSIZ
15:0
31:16
—
CHSSIZ
15:0
31:16
xxxx
xxxx
CHDSA
15:0
31:16
xxxx
CHSSA
15:0
0000
xxxx
CHAIRQ
CFORCE CABORT
00FF
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
31:16
15:0
31:16
15:0
CHSSA
CHDSA
xxxx
xxxx
xxxx
xxxx
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
10B0 DCH0SSIZ
1110
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP
Bits
Register
Name(1)
2015-2021 Microchip Technology Inc.
TABLE 10-3:
Virtual Address
(BF81_#)
1180 DCH1DSIZ
1190 DCH1SPTR
11A0 DCH1DPTR
11B0 DCH1CSIZ
11C0 DCH1CPTR
11D0 DCH1DAT
11E0 DCH2CON
11F0 DCH2ECON
DCH2INT
1210 DCH2SSA
1220 DCH2DSA
2015-2021 Microchip Technology Inc.
1230 DCH2SSIZ
1240 DCH2DSIZ
1250 DCH2SPTR
1260 DCH2DPTR
1270 DCH2CSIZ
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7700
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
0000
FF00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
0000
0000
xxxx
CHCPTR
15:0
—
—
0000
CHPDAT
31:16
CHPIGN
15:0 CHBUSY
—
CHPIGNEN
—
CHPATLEN
—
—
CHCHNS
31:16
—
—
—
—
—
—
—
—
15:0
CHSIRQ
0000
xxxx
CHCSIZ
15:0
31:16
21/5
CHDPTR
15:0
31:16
22/6
CHSPTR
15:0
31:16
23/7
CHDSIZ
15:0
31:16
24/8
CHSSIZ
—
All Resets
Bit Range
Register
Name(1)
Bits
1170 DCH1SSIZ
1200
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
0000
xxxx
CHAIRQ
CFORCE CABORT
00FF
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
xxxx
0000
CHDPTR
—
—
CHCSIZ
0000
xxxx
CHSPTR
15:0
31:16
—
CHDSIZ
15:0
31:16
xxxx
CHSSIZ
15:0
31:16
xxxx
CHDSA
15:0
31:16
xxxx
CHSSA
15:0
0000
0000
xxxx
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 188
TABLE 10-3:
Virtual Address
(BF81_#)
1280 DCH2CPTR
1290 DCH2DAT
12A0 DCH3CON
12B0 DCH3ECON
12C0
DCH3INT
12E0 DCH3DSA
12F0 DCH3SSIZ
1300 DCH3DSIZ
1310 DCH3SPTR
1320 DCH3DPTR
1330 DCH3CSIZ
1340 DCH3CPTR
1350 DCH3DAT
DS60001361J-page 189
1360 DCH4CON
1370 DCH4ECON
DCH4INT
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
7700
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
0000
FF00
—
—
CHPDAT
31:16
CHPIGN
15:0 CHBUSY
—
CHPIGNEN
—
CHPATLEN
—
—
CHCHNS
31:16
—
—
—
—
—
—
—
—
15:0
CHSIRQ
0000
0000
CHCPTR
—
All Resets
Bit Range
31:16
31/15
0000
xxxx
CHAIRQ
CFORCE CABORT
00FF
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7700
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
0000
FF00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
0000
0000
xxxx
CHCPTR
15:0
—
—
0000
CHPDAT
31:16
CHPIGN
15:0 CHBUSY
—
CHPIGNEN
—
CHPATLEN
—
—
CHCHNS
31:16
—
—
—
—
—
—
—
—
15:0
CHSIRQ
0000
xxxx
CHCSIZ
15:0
31:16
xxxx
—
CHDPTR
15:0
31:16
—
CHSPTR
15:0
31:16
—
CHDSIZ
15:0
31:16
xxxx
CHSSIZ
15:0
31:16
xxxx
CHDSA
15:0
31:16
xxxx
CHSSA
15:0
0000
xxxx
CHAIRQ
CFORCE CABORT
00FF
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
12D0 DCH3SSA
1380
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
Bits
Register
Name(1)
2015-2021 Microchip Technology Inc.
TABLE 10-3:
Virtual Address
(BF81_#)
13A0 DCH4DSA
13B0 DCH4SSIZ
13C0 DCH4DSIZ
13D0 DCH4SPTR
13E0 DCH4DPTR
13F0 DCH4CSIZ
1400 DCH4CPTR
1410 DCH4DAT
1420 DCH5CON
1430 DCH5ECON
DCH5INT
2015-2021 Microchip Technology Inc.
1450 DCH5SSA
1460 DCH5DSA
1470 DCH5SSIZ
1480 DCH5DSIZ
1490 DCH5SPTR
31/15
30/14
29/13
28/12
27/11
26/10
25/9
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
17/1
16/0
xxxx
xxxx
xxxx
—
—
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7700
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
0000
FF00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
0000
0000
xxxx
CHCPTR
15:0
—
—
0000
CHPDAT
31:16
CHPIGN
15:0 CHBUSY
—
CHPIGNEN
—
CHPATLEN
—
—
CHCHNS
31:16
—
—
—
—
—
—
—
—
15:0
CHSIRQ
0000
xxxx
CHCSIZ
15:0
31:16
18/2
CHDPTR
15:0
31:16
19/3
CHSPTR
15:0
31:16
20/4
CHDSIZ
15:0
31:16
21/5
CHSSIZ
15:0
31:16
22/6
CHDSA
15:0
31:16
23/7
CHSSA
15:0
31:16
24/8
All Resets
Bit Range
Register
Name(1)
Bits
1390 DCH4SSA
1440
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
0000
xxxx
CHAIRQ
CFORCE CABORT
00FF
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
31:16
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
15:0
xxxx
—
—
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
CHSSIZ
15:0
31:16
xxxx
CHDSA
15:0
31:16
xxxx
CHSSA
—
—
xxxx
CHDSIZ
—
—
—
—
—
—
—
—
—
CHSPTR
0000
xxxx
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 190
TABLE 10-3:
Virtual Address
(BF81_#)
14A0 DCH5DPTR
14B0 DCH5CSIZ
14C0 DCH5CPTR
14D0 DCH5DAT
14E0 DCH6CON
DCH6INT
1510 DCH6SSA
1520 DCH6DSA
1530 DCH6SSIZ
1540 DCH6DSIZ
1550 DCH6SPTR
1560 DCH6DPTR
1570 DCH6CSIZ
1580 DCH6CPTR
DS60001361J-page 191
1590 DCH6DAT
15A0 DCH7CON
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
15:0
31:16
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7700
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
0000
FF00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
CHCPTR
15:0
—
—
0000
CHPDAT
31:16
CHPIGN
15:0 CHBUSY
—
CHPIGNEN
—
CHPATLEN
—
—
CHCHNS
31:16
—
—
—
—
—
—
—
—
15:0
CHSIRQ
0000
0000
CHCSIZ
15:0
31:16
24/8
CHDPTR
—
All Resets
Bit Range
31:16
31/15
0000
xxxx
CHAIRQ
CFORCE CABORT
00FF
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7700
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
0000
0000
xxxx
CHCPTR
15:0
—
0000
CHPDAT
31:16
15:0 CHBUSY
—
CHPIGN
—
CHPIGNEN
—
CHPATLEN
—
—
CHCHNS
0000
xxxx
CHCSIZ
15:0
31:16
xxxx
—
CHDPTR
15:0
31:16
—
CHSPTR
15:0
31:16
—
CHDSIZ
15:0
31:16
xxxx
CHSSIZ
15:0
31:16
xxxx
CHDSA
15:0
31:16
xxxx
CHSSA
15:0
0000
xxxx
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
14F0 DCH6ECON
1500
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
Bits
Register
Name(1)
2015-2021 Microchip Technology Inc.
TABLE 10-3:
Virtual Address
(BF81_#)
DCH7INT
15D0 DCH7SSA
15E0 DCH7DSA
15F0 DCH7SSIZ
1600 DCH7DSIZ
1610 DCH7SPTR
1620 DCH7DPTR
1630 DCH7CSIZ
1640 DCH7CPTR
1650 DCH7DAT
31:16
31/15
30/14
29/13
—
—
—
15:0
28/12
27/11
26/10
25/9
24/8
—
—
—
—
—
CHSIRQ
23/7
22/6
21/5
20/4
PATEN
SIRQEN
19/3
18/2
17/1
16/0
AIRQEN
—
—
—
CHAIRQ
CFORCE CABORT
All Resets
Bit Range
Register
Name(1)
Bits
15B0 DCH7ECON
15C0
DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)
00FF
FF00
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE 0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF 0000
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
xxxx
0000
0000
xxxx
CHCPTR
—
—
CHPDAT
0000
xxxx
CHCSIZ
15:0
31:16
xxxx
—
CHDPTR
15:0
31:16
—
CHSPTR
15:0
31:16
—
CHDSIZ
15:0
31:16
xxxx
CHSSIZ
15:0
31:16
xxxx
CHDSA
15:0
31:16
xxxx
CHSSA
15:0
0000
0000
xxxx
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 192
TABLE 10-3:
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 10-1:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
DMACON: DMA CONTROLLER CONTROL REGISTER
Bit
Bit
30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
ON
—
—
SUSPEND
DMABUSY
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: DMA On bit
1 = DMA module is enabled
0 = DMA module is disabled
bit 14-13 Unimplemented: Read as ‘0’
bit 12
SUSPEND: DMA Suspend bit
1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus
0 = DMA operates normally
bit 11
DMABUSY: DMA Module Busy bit
1 = DMA module is active and is transferring data
0 = DMA module is disabled and not actively transferring data
bit 10-0
Unimplemented: Read as ‘0’
2015-2021 Microchip Technology Inc.
DS60001361J-page 193
PIC32MZ Graphics (DA) Family
REGISTER 10-2:
Bit
Range
31:24
23:16
15:8
7:0
DMASTAT: DMA STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
RDWR
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
—
—
—
—
—
DMACH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
RDWR: Read/Write Status bit
1 = Last DMA bus access when an error was detected was a read
0 = Last DMA bus access when an error was detected was a write
bit 30-3 Unimplemented: Read as ‘0’
bit 2-0
DMACH: DMA Channel bits
These bits contain the value of the most recent active DMA channel when an error was detected.
REGISTER 10-3:
Bit
Range
31:24
23:16
15:8
7:0
DMAADDR: DMA ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R-0
R-0
R-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DMAADDR
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DMAADDR
R-0
R-0
DMAADDR
R-0
R-0
R-0
R-0
R-0
DMAADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DMAADDR: DMA Module Address bits
These bits contain the address of the most recent DMA access when an error was detected.
DS60001361J-page 194
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 10-4:
Bit
Range
31:24
23:16
15:8
7:0
DCRCCON: DMA CRC CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
R/W-0
R/W-0
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
U-0
U-0
R/W-0
WBO(1)
—
—
BITO
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BYTO
PLEN(1)
R/W-0
R/W-0
R/W-0
U-0
U-0
CRCEN
CRCAPP(1)
CRCTYP
—
—
R/W-0
CRCCH
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 BYTO: CRC Byte Order Selection bits
11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order
per half-word)
10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per
half-word)
01 = Endian byte swap on word boundaries (i.e., reverse source byte order)
00 = No swapping (i.e., source byte order)
bit 27
WBO: CRC Write Byte Order Selection bit(1)
1 = Source data is written to the destination re-ordered as defined by BYTO
0 = Source data is written to the destination unaltered
bit 26-25 Unimplemented: Read as ‘0’
bit 24
BITO: CRC Bit Order Selection bit
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected)
0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected)
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected)
0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected)
bit 23-13 Unimplemented: Read as ‘0’
bit 12-8
PLEN: Polynomial Length bits(1)
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
These bits are unused.
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
Denotes the length of the polynomial – 1.
bit 7
CRCEN: CRC Enable bit
1 = CRC module is enabled and channel transfers are routed through the CRC module
0 = CRC module is disabled and channel transfers proceed normally
Note 1:
When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
2015-2021 Microchip Technology Inc.
DS60001361J-page 195
PIC32MZ Graphics (DA) Family
REGISTER 10-4:
DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED)
bit 6
CRCAPP: CRC Append Mode bit(1)
1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer
completes the DMA writes the calculated CRC value to the location given by CHxDSA
0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the
destination
bit 5
CRCTYP: CRC Type Selection bit
1 = The CRC module will calculate an IP header checksum
0 = The CRC module will calculate a LFSR CRC
bit 4-3
Unimplemented: Read as ‘0’
bit 2-0
CRCCH: CRC Channel Select bits
111 = CRC is assigned to Channel 7
110 = CRC is assigned to Channel 6
101 = CRC is assigned to Channel 5
100 = CRC is assigned to Channel 4
011 = CRC is assigned to Channel 3
010 = CRC is assigned to Channel 2
001 = CRC is assigned to Channel 1
000 = CRC is assigned to Channel 0
Note 1:
When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
DS60001361J-page 196
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 10-5:
Bit
Range
31:24
23:16
15:8
7:0
DCRCDATA: DMA CRC DATA REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA
R/W-0
R/W-0
DCRCDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DCRCDATA: CRC Data Register bits
Writing to this register will seed the CRC generator. Reading from this register will return the current value of
the CRC. Bits greater than PLEN will return ‘0’ on any read.
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written
to this register is converted and read back in 1’s complement form (i.e., current IP header checksum value).
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
Bits greater than PLEN will return ‘0’ on any read.
REGISTER 10-6:
Bit
Range
31:24
23:16
15:8
7:0
DCRCXOR: DMA CRCXOR ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR
R/W-0
R/W-0
DCRCXOR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DCRCXOR: CRC XOR Register bits
When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode):
This register is unused.
When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode):
1 = Enable the XOR input to the Shift register
0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in
the register
2015-2021 Microchip Technology Inc.
DS60001361J-page 197
PIC32MZ Graphics (DA) Family
REGISTER 10-7:
Bit
Range
31:24
23:16
15:8
7:0
DCHxCON: DMA CHANNEL x CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
CHPIGN
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
CHBUSY
—
CHIPGNEN
—
CHPATLEN
—
—
CHCHNS(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R-0
CHEN(2)
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 CHPIGN: Channel Register Data bits
Pattern Terminate mode:
Any byte matching these bits during a pattern match may be ignored during the pattern match determination when the CHPIGNEN bit is set. If a byte is read that is identical to this data byte, the pattern match
logic will treat it as a “don’t care” when the pattern matching logic is enabled and the CHPIGEN bit is set.
bit 23-16 Unimplemented: Read as ‘0’
bit 15
CHBUSY: Channel Busy bit
1 = Channel is active or has been enabled
0 = Channel is inactive or has been disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
CHPIGNEN: Enable Pattern Ignore Byte bit
1 = Treat any byte that matches the CHPIGN bits as a “don’t care” when pattern matching is enabled
0 = Disable this feature
bit 12
Unimplemented: Read as ‘0’
bit 11
CHPATLEN: Pattern Length bit
1 = 2 byte length
0 = 1 byte length
bit 10-9
Unimplemented: Read as ‘0’
bit 8
CHCHNS: Chain Channel Selection bit(1)
1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
bit 7
CHEN: Channel Enable bit(2)
1 = Channel is enabled
0 = Channel is disabled
bit 6
CHAED: Channel Allow Events If Disabled bit
1 = Channel start/abort events will be registered, even if the channel is disabled
0 = Channel start/abort events will be ignored if the channel is disabled
bit 5
CHCHN: Channel Chain Enable bit
1 = Allow channel to be chained
0 = Do not allow channel to be chained
Note 1:
2:
The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).
When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.
DS60001361J-page 198
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 10-7:
DCHxCON: DMA CHANNEL x CONTROL REGISTER (CONTINUED)
bit 4
CHAEN: Channel Automatic Enable bit
1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete
0 = Channel is disabled on block transfer complete
bit 3
Unimplemented: Read as ‘0’
bit 2
CHEDET: Channel Event Detected bit
1 = An event has been detected
0 = No events have been detected
bit 1-0
CHPRI: Channel Priority bits
11 = Channel has priority 3 (highest)
10 = Channel has priority 2
01 = Channel has priority 1
00 = Channel has priority 0
Note 1:
2:
The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).
When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.
2015-2021 Microchip Technology Inc.
DS60001361J-page 199
PIC32MZ Graphics (DA) Family
REGISTER 10-8:
Bit
Range
31:24
23:16
DCHxECON: DMA CHANNEL x EVENT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
(1)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CHAIRQ
15:8
R/W-1
CHSIRQ(1)
7:0
S-0
S-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
Legend:
R = Readable bit
-n = Value at POR
S = Settable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 CHAIRQ: Channel Transfer Abort IRQ bits(1)
11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag
•
•
•
bit 15-8
00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag
00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag
CHSIRQ: Channel Transfer Start IRQ bits(1)
11111111 = Interrupt 255 will initiate a DMA transfer
•
•
•
bit 2-0
00000001 = Interrupt 1 will initiate a DMA transfer
00000000 = Interrupt 0 will initiate a DMA transfer
CFORCE: DMA Forced Transfer bit
1 = A DMA transfer is forced to begin when this bit is written to a ‘1’
0 = This bit always reads ‘0’
CABORT: DMA Abort Transfer bit
1 = A DMA transfer is aborted when this bit is written to a ‘1’
0 = This bit always reads ‘0’
PATEN: Channel Pattern Match Abort Enable bit
1 = Abort transfer and clear CHEN on pattern match
0 = Pattern match is disabled
SIRQEN: Channel Start IRQ Enable bit
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer
AIRQEN: Channel Abort IRQ Enable bit
1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs
0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer
Unimplemented: Read as ‘0’
Note 1:
See Table 7-2: “Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources.
bit 7
bit 6
bit 5
bit 4
bit 3
DS60001361J-page 200
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 10-9:
Bit
Range
31:24
23:16
15:8
7:0
DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23
CHSDIE: Channel Source Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 22
CHSHIE: Channel Source Half Empty Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 21
CHDDIE: Channel Destination Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 20
CHDHIE: Channel Destination Half Full Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 19
CHBCIE: Channel Block Transfer Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 18
CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 17
CHTAIE: Channel Transfer Abort Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 16
CHERIE: Channel Address Error Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 15-8
Unimplemented: Read as ‘0’
bit 7
CHSDIF: Channel Source Done Interrupt Flag bit
1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
0 = No interrupt is pending
bit 6
CHSHIF: Channel Source Half Empty Interrupt Flag bit
1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
0 = No interrupt is pending
2015-2021 Microchip Technology Inc.
DS60001361J-page 201
PIC32MZ Graphics (DA) Family
REGISTER 10-9:
DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER (CONTINUED)
bit 5
CHDDIF: Channel Destination Done Interrupt Flag bit
1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
0 = No interrupt is pending
bit 4
CHDHIF: Channel Destination Half Full Interrupt Flag bit
1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
0 = No interrupt is pending
bit 3
CHBCIF: Channel Block Transfer Complete Interrupt Flag bit
1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a
pattern match event occurs
0 = No interrupt is pending
bit 2
CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit
1 = A cell transfer has been completed (CHCSIZ bytes have been transferred)
0 = No interrupt is pending
bit 1
CHTAIF: Channel Transfer Abort Interrupt Flag bit
1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
0 = No interrupt is pending
bit 0
CHERIF: Channel Address Error Interrupt Flag bit
1 = A channel address error has been detected
Either the source or the destination address is invalid.
0 = No interrupt is pending
DS60001361J-page 202
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 10-10: DCHxSSA: DMA CHANNEL x SOURCE START ADDRESS REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
R/W-0
R/W-0
31:24
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
R/W-0
R/W-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA
R/W-0
23:16
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA
R/W-0
15:8
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA
R/W-0
7:0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
CHSSA Channel Source Start Address bits
Channel source start address.
Note: This must be the physical address of the source.
REGISTER 10-11: DCHxDSA: DMA CHANNEL x DESTINATION START ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSA
R/W-0
R/W-0
CHDSA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSA
R/W-0
CHDSA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 CHDSA: Channel Destination Start Address bits
Channel destination start address.
Note: This must be the physical address of the destination.
2015-2021 Microchip Technology Inc.
DS60001361J-page 203
PIC32MZ Graphics (DA) Family
REGISTER 10-12: DCHxSSIZ: DMA CHANNEL x SOURCE SIZE REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSIZ
7:0
R/W-0
CHSSIZ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHSSIZ: Channel Source Size bits
1111111111111111 = 65,535 byte source size
•
•
•
0000000000000010 = 2 byte source size
0000000000000001 = 1 byte source size
0000000000000000 = 65,536 byte source size
REGISTER 10-13: DCHxDSIZ: DMA CHANNEL x DESTINATION SIZE REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSIZ
7:0
R/W-0
CHDSIZ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHDSIZ: Channel Destination Size bits
1111111111111111 = 65,535 byte destination size
•
•
•
0000000000000010 = 2 byte destination size
0000000000000001 = 1 byte destination size
0000000000000000 = 65,536 byte destination size
DS60001361J-page 204
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 10-14: DCHxSPTR: DMA CHANNEL x SOURCE POINTER REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHSPTR
7:0
R-0
R-0
CHSPTR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHSPTR: Channel Source Pointer bits
1111111111111111 = Points to byte 65,535 of the source
•
•
•
0000000000000001 = Points to byte 1 of the source
0000000000000000 = Points to byte 0 of the source
Note:
When in Pattern Detect mode, this register is reset on a pattern detect.
REGISTER 10-15: DCHxDPTR: DMA CHANNEL x DESTINATION POINTER REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHDPTR
7:0
R-0
R-0
CHDPTR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHDPTR: Channel Destination Pointer bits
1111111111111111 = Points to byte 65,535 of the destination
•
•
•
0000000000000001 = Points to byte 1 of the destination
0000000000000000 = Points to byte 0 of the destination
2015-2021 Microchip Technology Inc.
DS60001361J-page 205
PIC32MZ Graphics (DA) Family
REGISTER 10-16: DCHxCSIZ: DMA CHANNEL x CELL-SIZE REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHCSIZ
7:0
R/W-0
CHCSIZ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCSIZ: Channel Cell-Size bits
1111111111111111 = 65,535 bytes transferred on an event
•
•
•
0000000000000010 = 2 bytes transferred on an event
0000000000000001= 1 byte transferred on an event
0000000000000000 = 65,536 bytes transferred on an event
REGISTER 10-17: DCHxCPTR: DMA CHANNEL x CELL POINTER REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHCPTR
7:0
R-0
R-0
CHCPTR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCPTR: Channel Cell Progress Pointer bits
1111111111111111 = 65,535 bytes have been transferred since the last event
•
•
•
0000000000000001 = 1 byte has been transferred since the last event
0000000000000000 = 0 bytes have been transferred since the last event
Note:
When in Pattern Detect mode, this register is reset on a pattern detect.
DS60001361J-page 206
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 10-18: DCHxDAT: DMA CHANNEL x PATTERN DATA REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHPDAT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHPDAT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
CHPDAT: Channel Data Register bits
Pattern Terminate mode:
Data to be matched must be stored in this register to allow terminate on match.
All other modes:
Unused.
2015-2021 Microchip Technology Inc.
DS60001361J-page 207
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 208
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
11.0 HI-SPEED USB WITH ONTHE-GO (OTG)
Note:
This data sheet summarizes the
features of the PIC32MZ DA family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 51. “Hi-Speed
USB
with
On-The-Go
(OTG)”
(DS60001326) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
The Universal Serial Bus (USB) module contains
analog and digital components to provide a USB 2.0
embedded host, device, or OTG implementation with a
minimum of external components.
The module supports Hi-Speed, Full-Speed, or LowSpeed in any of the operating modes. This module in
Host mode is intended for use as an embedded host
and therefore does not implement a UHCI or OHCI
controller.
The USB module consists of the RAM controller,
packet
encode/decode,
UTM
synchronization,
endpoint control, a dedicated USB DMA controller, pullup and pull-down resistors, and the register interface.
A block diagram of the PIC32 USB OTG module is
illustrated in Figure 11-1.
The USB module includes the following features:
• USB Hi-Speed, Full-Speed, and Low-Speed
support for host and device
• USB OTG support with one or more Hi-Speed,
Full-Speed, or Low-Speed device
• Integrated signaling resistors
• Integrated analog comparators for VBUS
monitoring
• Integrated USB transceiver
• Transaction handshaking performed by hardware
• Integrated 8-channel DMA to access system RAM
and Flash
• Seven transmit endpoints and seven receive
endpoints, in addition to Endpoint 0
• Session Request Protocol (SRP) and Host
Negotiation Protocol (HNP) support
• Suspend and resume signaling support
• Dynamic FIFO sizing
• Integrated RAM for the FIFOs, eliminating the
need for system RAM for the FIFOs
• Link power management support
Note 1: The implementation and use of the USB
specifications, as well as other third party
specifications or technologies, may
require licensing; including, but not
limited to, USB Implementers Forum, Inc.
(also referred to as USB-IF). The user is
fully responsible for investigating and
satisfying any applicable licensing
obligations.
2: If the USB module is used, the Primary
Oscillator (POSC) is limited to either
12 MHz or 24 MHz.
2015-2019 Microchip Technology Inc.
DS60001361J-page 209
PIC32MZ DA FAMILY USB INTERFACE DIAGRAM
USBCLK
POSC
(12 MHz or 24 MHz only)
USB PLL
UPLLFSEL
Endpoint Control
EP0
Control
Host
EPO
Control
Function
EP1 - EP7
Control
Combine Endpoints
DMA
Requests
Transmit
Receive
Host
Transaction
Scheduler
Interrupt
Control
Interrupts
EP Reg
Decoder
Common
Regs
D+
UTM
Synchronization
Packet
Encode/Decode
D-
Data Sync
Packet Encode
HS Negotiation
Packet Decode
HNP/SRP
CRC Gen/Check
USBID
VUSB3V3
2015-2019 Microchip Technology Inc.
VBUS
USB 2.0
HS PHY
RAM Controller
RX
Buff
RX
Buff
TX
Buff
TX
Buff
Cycle Control
Timers
Link Power
Management
RAM
Cycle
Control
FIFO
Decoder
System Bus
Client mode
PIC32MZ Graphics (DA) Family
DS60001361J-page 210
FIGURE 11-1:
USB OTG Control Registers
TABLE 11-1:
USB REGISTER MAP 1
31:16
3000 USBCSR0
3004 USBCSR1
3008 USBCSR2
300C USBCSR3
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
—
—
—
—
—
—
EP7TXIF
EP6TXIF
EP5TXIF
EP4TXIF
—
—
ISOUPD(1)
SOFT
CONN(1)
—(2)
—(2)
31:16
—
—
—
—
—
15:0
—
—
—
—
—
31:16
VBUSIE
SOFIE
15:0
—
15:0
31:16 FORCEHST
—
HSMODE
SESSRQIE DISCONIE CONNIE
—
—
FIFOACC
—
FORCEFS FORCEHS
—
—
—
RESET
3010
31:16
USB
IE0CSR0(3)
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
USB
301C
IE0CSR3(3) 15:0
MPRXEN
MPTXEN
BIGEND
HBRXEN
—
—
—
—
ISO(1)
3010
31:16 AUTOSET
USB
IENCSR0(4)
MODE
—
15:0
31:16 AUTOCLR
USB
3014
IENCSR1(4)
AUTORQ(2)
15:0
DS60001361J-page 211
31:16
USB
301C
IENCSR3(1,3) 15:0
DMA
REQEN
EP7TXIE
EP6TXIE
EP5TXIE
EP4TXIE
EP3TXIE
EP2TXIE
EP1TXIE
EP0IE
00FF
—
EP7RXIF
EP6RXIF
EP5RXIF
EP4RXIF
EP3RXIF
EP2RXIF
EP1RXIF
—
0000
RESETIE
RESUMEIE
SUSPIE
VBUSIF
SESSREQIF
DISCONIF
CONNIF
SOFIF
RESETIF
EP3RXIE
EP2RXIE
—
—
EP7RXIE
EP6RXIE
EP5RXIE
EP4RXIE
NAK
—
—
—
—
—
—(1)
—(1)
DATA
TGGL(2)
—
FLSHFIFO
—
—
—
—
—
DMA
REQMD
SVCRPR(1)
SEND
STALL(1)
EP1RXIE
—
ENDPOINT
0000
DATAEND(1)
SENT
STALL(1)
RXSTALL(2)
NAK
TMOUT(2)
STATPKT(2)
REQPKT(2)
ERROR(2)
SETUP
PKT(2)
—
—
—
—
—
SPEED(2)
—
—
—
RXPKT
RDY
—
—
—
0000
—
—
—
0000
RXCNT
0000
—
—
—
—
—
—
—
xx00
—
—
—
—
—
—
—
0000
SENT
STALL(1)
SEND
STALL(1)
FIFONE
RXSTALL(2)
SETUPPKT(2)
TXPKT
RDY
—
—
—(1)
—(1)
INCOMP
TX(1)
DTWREN(2)
DATA
TGGL(2)
NAK
TMOUT(2)
PIDERR(2)
DMA
REQMD
—(1)
DATA
TWEN(2)
DATA
TGGL(2)
INCOM
PRX
CLRDT
FLUSH
UNDER
RUN(1)
ERROR(2)
CLRDT
RXSTALL(2)
REQPKT(2)
SPEED(2)
—
DATAERR(1) OVERRUN(1)
FLUSH
DERRNAKT(1)
ERROR(2)
FIFOFULL
TXFIFOSZ
RXINTERV
—
—
SPEED
0000
0000
RXPKT
RDY 0000
0000
PROTOCOL
TEP
0000
RXCNT
RXFIFOSZ
0000
0000
SENTSTALL(1) SENDSTALL(1)
RXMAXP
TXINTERV(2)
0000
—
—
—(1)
0000
TXPKT
RDY
TXMAXP
DISNYET(1)
00FE
0000
SETUP
END(1)
—
HBTXEN DYNFIFOS SOFTCONE UTMIDWID
—
SVC
SETEND(1)
2000
RESUMEIF SUSPIF 0600
RFRMNUM
MULT
—
—(2)
—(2)
TESTJ
FRC
DATTG
—(2)
—
NAKLIM(2)
DMA
REQEN
—(2)
0000
—
—(2)
—
—
EP0IF
—
—(2)
TESTK
—
EP1TXIF
—
—(2)
—
—
EP2TXIF
—
—
MULT
ISO(1)
31:16
USB
3018
IENCSR2(4) 15:0
—
EP3TXIF
SUSPEN
DISPING(2) DTWREN(2)
15:0
16/0
SUSP
MODE
RESUME
—
31:16
USB
3018
IE0CSR2(3) 15:0
17/1
FUNC(1)
PACKET
—(1)
18/2
0000
—
—
PROTOCOL
—
—
TEP
—
—
0000
0000
3020
USB
FIFO0
31:16
DATA
0000
15:0
DATA
0000
3024
USB
FIFO1
31:16
DATA
0000
15:0
DATA
0000
Legend:
Note
1:
2:
3:
4:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Device mode.
Host mode.
Definition for Endpoint 0 (ENDPOINT (USBCSR) = 0).
Definition for Endpoints 1-7 (ENDPOINT (USBCSR) = 1 through 7).
PIC32MZ Graphics (DA) Family
15:0
HSEN
19/3
All Resets
Register
Name
Bit Range
Bits
Virtual
Address
2015-2019 Microchip Technology Inc.
11.1
USB REGISTER MAP 1 (CONTINUED)
Virtual
Address
Register
Name
Bit Range
All Resets
Bits
3028
USB
FIFO2
31:16
DATA
0000
15:0
DATA
0000
302C
USB
FIFO3
31:16
DATA
0000
15:0
DATA
0000
3030
USB
FIFO4
31:16
DATA
0000
15:0
DATA
0000
3034
USB
FIFO5
31:16
DATA
0000
15:0
DATA
0000
3038
USB
FIFO6
31:16
DATA
0000
15:0
DATA
0000
303C
USB
FIFO7
31:16
DATA
0000
15:0
DATA
3060 USBOTG
31/15
30/14
29/13
28/12
27/11
31:16
—
—
—
RXDPB
15:0
—
—
—
—
26/10
25/9
24/8
23/7
RXFIFOSZ
—
—
TXEDMA
RXEDMA
22/6
21/5
—
—
BDEV
FSDEV
LSDEV
USB
FIFOA
31:16
—
—
—
RXFIFOAD
15:0
—
—
—
TXFIFOAD
306C
USB
HWVER
31:16
—
—
—
15:0
RC
3078
USB
INFO
31:16
31:16
—
—
—
—
VERMAJOR
—
—
—
15:0
RAMBITS
—
2015-2019 Microchip Technology Inc.
3080
—
15:0
—
—
—
NRSTX
3084
USB
E0RXA
31:16
—
15:0
—
3088
USB
E1TXA
31:16
—
15:0
—
308C
USB
E1RXA
31:16
—
15:0
—
3090
USB
E2TXA
31:16
—
15:0
—
3094
USB
E2RXA
31:16
—
15:0
—
3098
USB
E3TXA
31:16
—
15:0
—
—
—
—
—
—
—
RXHUBPRT
—
—
—
—
—
—
—
TXHUBPRT
—
—
—
—
—
—
—
RXHUBPRT
—
—
—
—
—
—
—
TXHUBPRT
—
—
—
—
—
—
—
RXHUBPRT
—
—
—
—
—
—
—
TXHUBPRT
—
—
—
16/0
TXDPB
TXFIFOSZ
VBUS
0000
HOSTMODE HOSTREQ SESSION 0088
0000
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Device mode.
Host mode.
Definition for Endpoint 0 (ENDPOINT (USBCSR) = 0).
Definition for Endpoints 1-7 (ENDPOINT (USBCSR) = 1 through 7).
—
0000
0800
WTCON
WTID
3C5C
RXENDPTS
TXENDPTS
8C77
NRST
TXHUBPRT
—
17/1
0000
FSEOF
31:16
18/2
VERMINOR
DMACHANS
USB
E0TXA
Legend:
Note
1:
2:
3:
4:
—
VPLEN
15:0
USB
307C
EOFRST
—
19/3
0000
—
3064
—
20/4
LSEOF
0072
HSEOF
7780
MULTTRAN
TXHUBADD
0000
—
TXFADDR
0000
MULTTRAN
RXHUBADD
—
—
—
—
—
0000
—
—
—
0000
MULTTRAN
TXHUBADD
0000
—
TXFADDR
0000
MULTTRAN
RXHUBADD
0000
—
RXFADDR
0000
MULTTRAN
TXHUBADD
0000
—
TXFADDR
0000
MULTTRAN
RXHUBADD
0000
—
RXFADDR
0000
MULTTRAN
TXHUBADD
0000
—
TXFADDR
0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 212
TABLE 11-1:
USB REGISTER MAP 1 (CONTINUED)
USB
E3RXA
31:16
—
15:0
—
30A0
US
BE4TXA
31:16
—
15:0
—
30A4
USB
E4RXA
31:16
—
15:0
—
30A8
USB
E5TXA
31:16
—
15:0
—
30AC
USB
E5RXA
31:16
—
15:0
—
30B0
USB
E6TXA
31:16
—
15:0
—
30B4
USB
E6RXA
31:16
—
15:0
—
30B8
USB
E7TXA
31:16
—
15:0
—
30BC
USB
E7RXA
31:16
—
15:0
—
3100
USB
E0CSR0
31:16
3108
USB
E0CSR2
31:16
USB
310C
E0CSR3
31:16
3110
USB
E1CSR0
31:16
3114
USB
E1CSR1
31:16
3118
USB
E1CSR2
31:16
311C
USB
E1CSR3
31:16
3120
USB
E2CSR0
31:16
3124
USB
E2CSR1
31:16
Legend:
Note
1:
2:
3:
4:
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
30/14
29/13
28/12
—
—
—
27/11
26/10
25/9
24/8
—
—
—
RXHUBPRT
—
TXHUBPRT
—
—
—
—
—
—
—
RXHUBPRT
—
—
—
—
—
—
—
TXHUBPRT
—
—
—
—
—
—
—
RXHUBPRT
—
—
—
—
—
—
—
TXHUBPRT
—
—
—
—
—
—
—
RXHUBPRT
—
—
—
—
—
—
—
TXHUBPRT
—
—
—
—
—
—
—
RXHUBPRT
—
—
—
—
—
—
—
23/7
22/6
20/4
19/3
18/2
17/1
16/0
MULTTRAN
RXHUBADD
0000
—
RXFADDR
0000
MULTTRAN
TXHUBADD
0000
—
TXFADDR
0000
MULTTRAN
RXHUBADD
0000
—
RXFADDR
0000
MULTTRAN
TXHUBADD
0000
—
TXFADDR
0000
MULTTRAN
RXHUBADD
0000
—
RXFADDR
0000
MULTTRAN
TXHUBADD
0000
—
TXFADDR
0000
MULTTRAN
RXHUBADD
0000
—
RXFADDR
0000
MULTTRAN
TXHUBADD
0000
—
TXFADDR
0000
MULTTRAN
RXHUBADD
0000
—
RXFADDR
0000
Indexed by the same bits in USBIE0CSR0
Indexed by the same bits in USBIE0CSR2
Indexed by the same bits in USBIE0CSR3
Indexed by the same bits in USBIE1CSR0
Indexed by the same bits in USBIE1CSR1
Indexed by the same bits in USBIE1CSR2
Indexed by the same bits in USBIE1CSR3
Indexed by the same bits in USBIE2CSR0
Indexed by the same bits in USBIE2CSR1
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Device mode.
Host mode.
Definition for Endpoint 0 (ENDPOINT (USBCSR) = 0).
Definition for Endpoints 1-7 (ENDPOINT (USBCSR) = 1 through 7).
21/5
All Resets
Bit Range
309C
31/15
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 213
Register
Name
Bits
Virtual
Address
2015-2019 Microchip Technology Inc.
TABLE 11-1:
USB REGISTER MAP 1 (CONTINUED)
Bit Range
3128
USB
E2CSR2
31:16
USB
312C
E2CSR3
31:16
3130
USB
E3CSR0
31:16
3134
USB
E3CSR1
31:16
3138
USB
E3CSR2
31:16
USB
313C
E3CSR3
31:16
3140
USB
E4CSR0
31:16
3144
USB
E4CSR1
31:16
3148
USB
E4CSR2
31:16
USB
314C
E4CSR3
31:16
3150
USB
E5CSR0
31:16
3154
USB
E5CSR1
31:16
3158
USB
E5CSR2
31:16
USB
315C
E5CSR3
31:16
3160
USB
E6CSR0
31:16
3164
USB
E6CSR1
31:16
3168
USB
E6CSR2
31:16
USB
316C
E6CSR3
31:16
Legend:
Note
1:
2:
3:
4:
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
Indexed by the same bits in USBIE2CSR2
Indexed by the same bits in USBIE2CSR3
Indexed by the same bits in USBIE3CSR0
Indexed by the same bits in USBIE3CSR1
Indexed by the same bits in USBIE3CSR2
Indexed by the same bits in USBIE3CSR3
Indexed by the same bits in USBIE4CSR0
Indexed by the same bits in USBIE4CSR1
Indexed by the same bits in USBIE4CSR2
Indexed by the same bits in USBIE4CSR3
Indexed by the same bits in USBIE5CSR0
Indexed by the same bits in USBIE5CSR1
Indexed by the same bits in USBIE5CSR2
Indexed by the same bits in USBIE5CSR3
Indexed by the same bits in USBIE6CSR0
Indexed by the same bits in USBIE6CSR1
Indexed by the same bits in USBIE6CSR2
Indexed by the same bits in USBIE6CSR3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Device mode.
Host mode.
Definition for Endpoint 0 (ENDPOINT (USBCSR) = 0).
Definition for Endpoints 1-7 (ENDPOINT (USBCSR) = 1 through 7).
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Register
Name
2015-2019 Microchip Technology Inc.
Virtual
Address
Bits
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 214
TABLE 11-1:
USB REGISTER MAP 1 (CONTINUED)
Bit Range
3170
USB
E7CSR0
31:16
3174
USB
E7CSR1
31:16
3178
USB
E7CSR2
31:16
USB
317C
E7CSR3
31:16
3200
USB
DMAINT
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
DMA8IF
DMA7IF
DMA6IF
DMA5IF
DMA4IF
DMA3IF
DMA2IF
3204
USB
DMA1C
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
3208
USB
DMA1A
31:16
DMAADDR
0000
15:0
DMAADDR
0000
320C
USB
DMA1N
31:16
DMACOUNT
0000
15:0
DMACOUNT
3214
USB
DMA2C
31:16
—
—
—
—
—
15:0
—
—
—
—
—
3218
USB
DMA2A
31:16
DMAADDR
0000
15:0
DMAADDR
0000
321C
USB
DMA2N
31:16
DMACOUNT
0000
15:0
DMACOUNT
3224
USB
DMA3C
31:16
—
—
—
—
—
15:0
—
—
—
—
—
3228
USB
DMA3A
31:16
DMAADDR
0000
15:0
DMAADDR
0000
322C
USB
DMA3N
31:16
DMACOUNT
0000
15:0
DMACOUNT
3234
USB
DMA4C
31:16
—
—
—
—
—
15:0
—
—
—
—
—
3238
USB
DMA4A
31:16
DMAADDR
0000
15:0
DMAADDR
0000
323C
USB
DMA4N
31:16
DMACOUNT
0000
15:0
DMACOUNT
3244
USB
DMA5C
31:16
—
—
—
—
—
15:0
—
—
—
—
—
Legend:
Note
1:
2:
3:
4:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
0000
Indexed by the same bits in USBIE7CSR0
15:0
0000
0000
Indexed by the same bits in USBIE7CSR1
15:0
0000
0000
Indexed by the same bits in USBIE7CSR2
15:0
0000
0000
Indexed by the same bits in USBIE7CSR3
15:0
DMABRSTM
—
—
DMABRSTM
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Device mode.
Host mode.
Definition for Endpoint 0 (ENDPOINT (USBCSR) = 0).
Definition for Endpoints 1-7 (ENDPOINT (USBCSR) = 1 through 7).
—
—
—
DMADIR
—
0000
DMAEN 0000
—
—
—
DMAIE
DMAMODE
DMADIR
—
0000
DMAEN 0000
—
—
—
DMAIE
DMAMODE
DMADIR
—
0000
DMAEN 0000
0000
—
—
—
DMAEP
—
—
DMAMODE
0000
—
DMAERR
DMAERR
—
DMAEP
—
—
—
DMAEP
—
—
DMAIE
0000
DMA1IF 0000
0000
—
DMAERR
—
DMABRSTM
DMAEP
DMAERR
—
DMABRSTM
—
—
—
DMABRSTM
—
DMAERR
0000
—
—
—
—
DMAIE
DMAMODE
DMADIR
—
0000
DMAEN 0000
0000
—
—
DMAEP
—
—
—
—
DMAIE
DMAMODE
DMADIR
—
0000
DMAEN 0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 215
Register
Name
All Resets
Bits
Virtual
Address
2015-2019 Microchip Technology Inc.
TABLE 11-1:
USB REGISTER MAP 1 (CONTINUED)
Register
Name
Bit Range
2015-2019 Microchip Technology Inc.
Virtual
Address
All Resets
Bits
3248
USB
DMA5A
31:16
DMAADDR
0000
15:0
DMAADDR
0000
324C
USB
DMA5N
31:16
DMACOUNT
0000
15:0
DMACOUNT
3254
USB
DMA6C
31:16
—
—
—
—
—
15:0
—
—
—
—
—
3258
USB
DMA6A
31:16
DMAADDR
0000
15:0
DMAADDR
0000
325C
USB
DMA6N
31:16
DMACOUNT
0000
15:0
DMACOUNT
3264
USB
DMA7C
31:16
—
—
—
—
—
15:0
—
—
—
—
—
3268
USB
DMA7A
31:16
DMAADDR
0000
15:0
DMAADDR
0000
326C
USB
DMA7N
31:16
DMACOUNT
0000
15:0
DMACOUNT
3274
USB
DMA8C
31:16
—
—
—
—
—
15:0
—
—
—
—
—
3278
USB
DMA8A
31:16
DMAADDR
0000
15:0
DMAADDR
0000
327C
USB
DMA8N
31:16
DMACOUNT
0000
15:0
DMACOUNT
3304
USB
E1RPC
31:16
3308
USB
E2RPC
31:16
330C
USB
E3RPC
31:16
3310
USB
E4RPC
31:16
3314
USB
E5RPC
31:16
3318
USB
E6RPC
31:16
331C
USB
E7RPC
31:16
Legend:
Note
1:
2:
3:
4:
31/15
—
30/14
—
29/13
—
28/12
—
27/11
—
26/10
—
25/9
—
DMABRSTM
—
23/7
—
22/6
—
15:0
—
—
—
—
—
DMAEP
—
18/2
17/1
16/0
—
—
—
DMAIE
DMAMODE
DMADIR
—
—
—
—
DMAIE
DMAMODE
DMADIR
—
—
—
—
—
—
—
—
15:0
—
—
—
—
DMAIE
DMAMODE
DMADIR
—
—
—
—
—
—
—
—
15:0
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Device mode.
Host mode.
Definition for Endpoint 0 (ENDPOINT (USBCSR) = 0).
Definition for Endpoints 1-7 (ENDPOINT (USBCSR) = 1 through 7).
—
—
—
—
—
—
—
—
—
RQPKTCNT
0000
0000
0000
0000
RQPKTCNT
—
0000
0000
RQPKTCNT
—
0000
0000
RQPKTCNT
—
0000
0000
RQPKTCNT
—
0000
DMAEN 0000
RQPKTCNT
—
0000
DMAEN 0000
RQPKTCNT
—
0000
DMAEN 0000
0000
—
DMAERR
—
—
DMAEP
—
19/3
0000
—
DMAERR
—
20/4
DMAEP
—
—
21/5
0000
—
DMAERR
—
DMABRSTM
—
—
—
DMABRSTM
—
24/8
0000
0000
0000
0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 216
TABLE 11-1:
USB REGISTER MAP 1 (CONTINUED)
Bit Range
3340
USB
DPBFD
31:16
3344
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
—
—
—
—
—
—
—
—
EP7TXD
EP6TXD
EP5TXD
EP4TXD
EP3TXD
15:0
—
—
—
—
—
—
—
—
EP7RXD
EP6RXD
EP5RXD
EP4RXD
EP3RXD
31:16
USB
TMCON1 15:0
31:16
USB
3348
TMCON2 15:0
3360
3364
31:16
USB
LPMR1
Legend:
Note
1:
2:
3:
4:
15:0
21/5
20/4
19/3
18/2
17/1
16/0
EP2TXD
EP1TXD
—
0000
EP2RXD
EP1RXD
—
0000
05E6
TUCH
4074
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LPM
ERRIE
LPM
RESIE
—
ENDPOINT
—
—
—
—
—
LPMACKIE LPMNYIE
LPMSTIE
LPMTOIE
—
—
—
RMTWAK
—
—
—
—
—
—
—
—
—
LPMFADDR
—
—
LPMNAK(1)
LPMEN
—(2)
—(2)
LPMRES LPMXMT
—(2)
LPMERR(1)
—(2)
0000
0000
LNKSTATE
—
—
—
THSBT
HIRD
—
—
0000
0000
0000
—
—
—
—
—
LPMRES
LPMNC
LPMACK
LPMNY
LPMST
0000
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Device mode.
Host mode.
Definition for Endpoint 0 (ENDPOINT (USBCSR) = 0).
Definition for Endpoints 1-7 (ENDPOINT (USBCSR) = 1 through 7).
TABLE 11-2:
USB REGISTER MAP 2
Register
Name
4000
USB
CRCON
Legend:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
USBIF
USBRF
USBWKUP
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
USB
IDOVEN
USB
IDVAL
PHYIDEN
VBUS
MONEN
ASVAL
MONEN
BSVAL
MONEN
SEND
MONEN
USBIE
USBRIE
USB
WKUPEN
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Virtual
Address
Bit Range
Bits
DS60001361J-page 217
PIC32MZ Graphics (DA) Family
USB
LMPR2
22/6
THHSRTN
15:0
31:16
23/7
All Resets
Register
Name
Bits
Virtual
Address
2015-2019 Microchip Technology Inc.
TABLE 11-1:
PIC32MZ Graphics (DA) Family
REGISTER 11-1:
Bit
Range
31:24
23:16
15:8
7:0
USBCSR0: USB CONTROL STATUS REGISTER 0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
EP7TXIF
EP6TXIF
EP5TXIF
EP4TXIF
EP3TXIF
EP2TXIF
EP1TXIF
EP0IF
R/W-0
R/W-0
R/W-1
R-0, HS
R-0
R/W-0
R-0, HC
R/W-0
ISOUPD
SOFTCONN
—
—
HSEN
HSMODE
RESET
RESUME
SUSPMODE
SUSPEN
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
—
—
FUNC
—
Legend:
HS = Hardware Set
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-17 EP7TXIF:EP1TXIF: Endpoint ‘n’ TX Interrupt Flag bit
1 = Endpoint has a transmit interrupt to be serviced
0 = No interrupt event
bit 16
EP0IF: Endpoint 0 Interrupt bit
1 = Endpoint 0 has an interrupt to be serviced
0 = No interrupt event
All EPxTX and EP0 bits are cleared when the byte is read. Therefore, these bits must be read independently
from the remaining bits in this register to avoid accidental clearing.
bit 15
ISOUPD: ISO Update bit (Device mode only; unimplemented in Host mode)
1 = USB module will wait for a SOF token from the time TXPKTRDY is set before sending the packet
0 = No change in behavior
This bit only affects endpoints performing isochronous transfers when in Device mode. This bit is
unimplemented in Host mode.
bit 14
SOFTCONN: Soft Connect/Disconnect Feature Selection bit
1 = The USB D+/D- lines are enabled and active
0 = The USB D+/D- lines are disabled and are tri-stated
bit 13
HSEN: Hi-Speed Enable bit
1 = The USB module will negotiate for Hi-Speed mode when the device is reset by the hub
0 = Module only operates in Full-Speed mode
bit 12
HSMODE: Hi-Speed Mode Status bit
1 = Hi-Speed mode successfully negotiated during USB reset
0 = Module is not in Hi-Speed mode
This bit is only available in Device mode.
In Device mode, this bit becomes valid when a USB reset completes. In Host mode, it becomes valid when
the RESET bit is cleared.
bit 11
RESET: Module Reset Status bit
1 = Reset signaling is present on the bus
0 = Normal module operation
In Device mode, this bit is read-only. In Host mode, this bit is read/write.
DS60001361J-page 218
2015-2019 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 11-1:
bit 10
USBCSR0: USB CONTROL STATUS REGISTER 0 (CONTINUED)
RESUME: Resume from Suspend control bit
1 = Generate Resume signaling when the device is in Suspend mode
0 = Stop Resume signaling
In Device mode, the software should clear this bit after 10 ms (a maximum of 15 ms) to end Resume signaling. In Host mode, the software should clear this bit after 20 ms.
bit 9
SUSPMODE: Suspend Mode status bit
1 = The USB module is in Suspend mode
0 = The USB module is in Normal operations
This bit is read-only in Device mode. In Host mode, it can be set by software, and is cleared by hardware.
bit 8
SUSPEN: Suspend Mode Enable bit
1 = Suspend mode is enabled
0 = Suspend mode is not enabled
bit 7
Unimplemented: Read as ‘0’
bit 6-0
FUNC: Device Function Address bits
These bits are only available in Device mode. This field is written with the address received through a
SET_ADDRESS command, which will then be used for decoding the function address in subsequent token
packets.
2015-2019 Microchip Technology Inc.
DS60001361J-page 219
PIC32MZ Graphics (DA) Family
REGISTER 11-2:
Bit
Range
31:24
23:16
15:8
7:0
USBCSR1: USB CONTROL STATUS REGISTER 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
EP7TXIE
EP6TXIE
EP5TXIE
EP4TXIE
EP3TXIE
EP2TXIE
EP1TXIE
EP0IE
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
U-0
EP7RXIF
EP6RXIF
EP5RXIF
EP4RXIF
EP3RXIF
EP2RXIF
EP1RXIF
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-17 EP7TXIE:EP1TXIE: Endpoint ‘n’ Transmit Interrupt Enable bits
1 = Endpoint Transmit interrupt events are enabled
0 = Endpoint Transmit interrupt events are not enabled
bit 16
EP0IE: Endpoint 0 Interrupt Enable bit
1 = Endpoint 0 interrupt events are enabled
0 = Endpoint 0 interrupt events are not enabled
bit 15-8 Unimplemented: Read as ‘0’
bit 7-1
bit 0
EP7RXIF:EP1RXIF: Endpoint ‘n’ RX Interrupt bit
1 = Endpoint has a receive event to be serviced
0 = No interrupt event
Unimplemented: Read as ‘0’
DS60001361J-page 220
2015-2019 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 11-3:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
R/W-0
VBUSIE
USBCSR2: USB CONTROL STATUS REGISTER 2
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
SESSRQIE DISCONIE
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
CONNIE
SOFIE
RESETIE
RESUMEIE
SUSPIE
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
R-0, HS
VBUSIF
SESSRQIF
DISCONIF
CONNIF
SOFIF
RESETIF
RESUMEIF
SUSPIF
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U-0
EP7RXIE
EP6RXIE
EP5RXIE
EP4RXIE
EP3RXIE
EP2RXIE
EP1RXIE
—
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Set
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
VBUSIE: VBUS Error Interrupt Enable bit
1 = VBUS error interrupt is enabled
0 = VBUS error interrupt is disabled
bit 30
SESSRQIE: Session Request Interrupt Enable bit
1 = Session request interrupt is enabled
0 = Session request interrupt is disabled
bit 29
DISCONIE: Device Disconnect Interrupt Enable bit
1 = Device disconnect interrupt is enabled
0 = Device disconnect interrupt is disabled
bit 28
CONNIE: Device Connection Interrupt Enable bit
1 = Device connection interrupt is enabled
0 = Device connection interrupt is disabled
bit 27
SOFIE: Start of Frame Interrupt Enable bit
1 = Start of Frame event interrupt is enabled
0 = Start of Frame event interrupt is disabled
bit 26
RESETIE: Reset/Babble Interrupt Enable bit
1 = Interrupt when reset (Device mode) or Babble (Host mode) is enabled
0 = Reset/Babble interrupt is disabled
bit 25
RESUMEIE: Resume Interrupt Enable bit
1 = Resume signaling interrupt is enabled
0 = Resume signaling interrupt is disabled
bit 24
SUSPIE: Suspend Interrupt Enable bit
1 = Suspend signaling interrupt is enabled
0 = Suspend signaling interrupt is disabled
bit 23
VBUSIF: VBUS Error Interrupt bit
1 = VBUS has dropped below the VBUS valid threshold during a session
0 = No interrupt
bit 22
SESSRQIF: Session Request Interrupt bit
1 = Session request signaling has been detected
0 = No session request detected
bit 21
DISCONIF: Device Disconnect Interrupt bit
1 = In Host mode, indicates when a device disconnect is detected. In Device mode, indicates when a
session ends.
0 = No device disconnect detected
bit 20
CONNIF: Device Connection Interrupt bit
1 = In Host mode, indicates when a device connection is detected
0 = No device connection detected
2015-2019 Microchip Technology Inc.
DS60001361J-page 221
PIC32MZ Graphics (DA) Family
REGISTER 11-3:
USBCSR2: USB CONTROL STATUS REGISTER 2 (CONTINUED)
bit 19
SOFIF: Start of Frame Interrupt bit
1 = A new frame has started
0 = No start of frame detected
bit 18
RESETIF: Reset/Babble Interrupt bit
1 = In Host mode, indicates babble is detected. In Device mode, indicates reset signaling is detected on
the bus.
0 = No reset/babble detected
bit 17
RESUMEIF: Resume Interrupt bit
1 = Resume signaling is detected on the bus while USB module is in Suspend mode
0 = No Resume signaling detected
bit 16
SUSPIF: Suspend Interrupt bit
1 = Suspend signaling is detected on the bus (Device mode)
0 = No suspend signaling detected
bit 15-8
Unimplemented: Read as ‘0’
bit 7-1
EP7RXIE:EP1RXIE: Endpoint ‘n’ Receive Interrupt Enable bit
1 = Receive interrupt is enabled for this endpoint
0 = Receive interrupt is not enabled
bit 0
Unimplemented: Read as ‘0’
DS60001361J-page 222
2015-2019 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 11-4:
Bit
Range
31:24
23:16
15:8
7:0
USBCSR3: USB CONTROL STATUS REGISTER 3
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0, HC
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FORCEHST
FIFOACC
FORCEFS
FORCEHS
PACKET
TESTK
TESTJ
NAK
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
U-0
U-0
U-0
U-0
U-0
ENDPOINT
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RFRMUM
R-0
R-0
R-0
RFRMNUM
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Cleared
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
FORCEHST: Test Mode Force Host Select bit
1 = Forces USB module into Host mode, regardless of whether it is connected to any peripheral
0 = Normal operation
bit 30
FIFOACC: Test Mode Endpoint 0 FIFO Transfer Force bit
1 = Transfers the packet in the Endpoint 0 TX FIFO to the Endpoint 0 RX FIFO
0 = No transfer
bit 29
FORCEFS: Test mode Force Full-Speed Mode Select bit
This bit is only active if FORCEHST = 1.
1 = Forces USB module into Full-Speed mode. Undefined behavior if FORCEHS = 1.
0 = If FORCEHS = 0, places USB module into Low-Speed mode.
bit 28
FORCEHS: Test mode Force Hi-Speed Mode Select bit
This bit is only active if FORCEHST = 1.
1 = Forces USB module into Hi-Speed mode. Undefined behavior if FORCEFS = 1.
0 = If FORCEFS = 0, places USB module into Low-Speed mode.
bit 27
PACKET: Test_Packet Test Mode Select bit
This bit is only active if module is in Hi-Speed mode.
1 = The USB module repetitively transmits on the bus a 53-byte test packet. Test packet must be loaded
into the Endpoint 0 FIFO before the test mode is entered.
0 = Normal operation
bit 26
TESTK: Test_K Test Mode Select bit
1 = Enters Test_K test mode. The USB module transmits a continuous K on the bus.
0 = Normal operation
This bit is only active if the USB module is in Hi-Speed mode.
bit 25
TESTJ: Test_J Test Mode Select bit
1 = Enters Test_J test mode. The USB module transmits a continuous J on the bus.
0 = Normal operation
This bit is only active if the USB module is in Hi-Speed mode.
bit 24
NAK: Test_SE0_NAK Test Mode Select bit
1 = Enter Test_SE0_NAK test mode. The USB module remains in Hi-Speed mode but responds to any valid
IN token with a NAK
0 = Normal operation
This mode is only active if module is in Hi-Speed mode.
bit 23-20 Unimplemented: Read as ‘0’
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REGISTER 11-4:
USBCSR3: USB CONTROL STATUS REGISTER 3 (CONTINUED)
bit 19-16 ENDPOINT: Endpoint Registers Select bits
1111 = Reserved
•
•
•
1000 = Reserved
0111 = Endpoint 7
•
•
•
0000 = Endpoint 0
These bits select which endpoint registers are accessed through addresses 3010-301F.
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0
RFRMNUM: Last Received Frame Number bits
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REGISTER 11-5:
Bit
Range
USBIE0CSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0
(ENDPOINT 0)
Bit
31/23/15/7
U-0
31:24
23:16
15:8
7:0
Bit
Bit
30/22/14/6 29/21/13/5
U-0
U-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-0
R/W-0, HC
R/W-0
R/W-0, HC
—
—
—
DISPING
DTWREN
DATATGGL
R-0
—
—
—
—
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/C-0, HS
SVCSETEND SVCRPR SENDSTALL SETUPEND
R/W-0, HS
R-0, HS
DATAEND
SENTSTALL
NAKTMOUT
STATPKT
REQPKT
ERROR
SETUPPKT
RXSTALL
U-0
U-0
U-0
U-0
U-0
U-0
FLSHFIFO
R-0
TXPKTRDY RXPKTRDY
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Cleared
W = Writable bit
‘1’ = Bit is set
HS = Hardware Set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 Unimplemented: Read as ‘0’
bit 27
DISPING: Disable Ping tokens control bit (Host mode)
1 = USB Module will not issue PING tokens in data and status phases of a Hi-Speed Control transfer
0 = Ping tokens are issued
bit 26
DTWREN: Data Toggle Write Enable bit (Host mode)
1 = Enable the current state of the Endpoint 0 data toggle to be written. Automatically cleared.
0 = Disable data toggle write
bit 25
DATATGGL: Data Toggle bit (Host mode)
When read, this bit indicates the current state of the Endpoint 0 data toggle.
If DTWREN = 1, this bit is writable with the desired setting.
If DTWREN = 0, this bit is read-only.
bit 24
FLSHFIFO: Flush FIFO Control bit
1 = Flush the next packet to be transmitted/read from the Endpoint 0 FIFO. The FIFO pointer is reset and
the TXPKTRDY/RXPKTRDY bit is cleared. Automatically cleared when the operation completes. Should
only be used when TXPKTRDY/RXPKTRDY = 1.
0 = No Flush operation
bit 23
SVCSETEND: Clear SETUPEND Control bit (Device mode)
1 = Clear the SETUPEND bit in this register. This bit is automatically cleared.
0 = Do not clear
NAKTMOUT: NAK Time-out Control bit (Host mode)
1 = Endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the
NAKLIM bits (USBICSR)
0 = Allow the endpoint to continue
bit 22
SVCRPR: Serviced RXPKTRDY Clear Control bit (Device mode)
1 = Clear the RXPKTRDY bit in this register. This bit is automatically cleared.
0 = Do not clear
STATPKT: Status Stage Transaction Control bit (Host mode)
1 = When set at the same time as the TXPKTRDY or REQPKT bit is set, performs a status stage transaction
0 = Do not perform a status stage transaction
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REGISTER 11-5:
bit 21
USBIE0CSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0
(ENDPOINT 0) (CONTINUED)
SENDSTALL: Send Stall Control bit (Device mode)
1 = Terminate the current transaction and transmit a STALL handshake. This bit is automatically cleared.
0 = Do not send STALL handshake.
REQPKT: IN transaction Request Control bit (Host mode)
1 = Request an IN transaction. This bit is cleared when the RXPKTRDY bit is set.
0 = Do not request an IN transaction
bit 20
SETUPEND: Early Control Transaction End Status bit (Device mode)
1 = A control transaction ended before the DATAEND bit has been set. An interrupt will be generated and
the FIFO flushed at this time.
0 = Normal operation
This bit is cleared by writing a ‘1’ to the SVCSETEND bit in this register.
ERROR: No Response Error Status bit (Host mode)
1 = Three attempts have been made to perform a transaction with no response from the peripheral. An interrupt is generated.
0 = Clear this flag. Software must write a ‘0’ to this bit to clear it.
bit 19
DATAEND: End of Data Control bit (Device mode)
The software sets this bit when:
• Setting TXPKTRDY for the last data packet
• Clearing RXPKTRDY after unloading the last data packet
• Setting TXPKTRDY for a zero length data packet
Hardware clears this bit.
SETUPPKT: Send a SETUP token Control bit (Host mode)
1 = When set at the same time as the TXPKTRDY bit is set, the module sends a SETUP token instead of an
OUT token for the transaction
0 = Normal OUT token operation
Setting this bit also clears the Data Toggle.
bit 18
SENTSTALL: STALL sent status bit (Device mode)
1 = STALL handshake has been transmitted
0 = Software clear of bit
RXSTALL: STALL handshake received Status bit (Host mode)
1 = STALL handshake was received
0 = Software clear of bit
bit 17
TXPKTRDY: TX Packet Ready Control bit
1 = Data packet has been loaded into the FIFO. It is cleared automatically.
0 = No data packet is ready for transmit
bit 16
RXPKTRDY: RX Packet Ready Status bit
1 = Data packet has been received. Interrupt is generated (when enabled) when this bit is set.
0 = No data packet has been received
This bit is cleared by setting the SVCRPR bit.
bit 15-0
Unimplemented: Read as ‘0’
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REGISTER 11-6:
Bit
Range
31:24
23:16
15:8
7:0
USBIE0CSR2: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 2
(ENDPOINT 0)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
U-0
U-0
U-0
—
—
—
SPEED
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
—
—
—
NAKLIM
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
—
Legend:
R = Readable bit
-n = Value at POR
RXCNT
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 NAKLIM: Endpoint 0 NAK Limit bits
The number of frames/microframes (Hi-Speed transfers) after which Endpoint 0 should time-out on receiving
a stream of NAK responses.
bit 23-22 SPEED: Operating Speed Control bits
11 = Low-Speed
10 = Full-Speed
01 = Hi-Speed
00 = Reserved
bit 21-7 Unimplemented: Read as ‘0’
bit 6-0
RXCNT: Receive Count bits
The number of received data bytes in the Endpoint 0 FIFO. The value returned changes as the contents of
the FIFO change and is only valid while the RXPKTRDY bit is set.
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REGISTER 11-7:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
USBIE0CSR3: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 3
(ENDPOINT 0)
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-x
R-1
R-0
R-x
R-x
R-0
R-x
R-x
MPRXEN
MPTXEN
BIGEND
HBRXEN
HBTXEN
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
DYNFIFOS SOFTCONE UTMIDWID
U-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
MPRXEN: Automatic Amalgamation Option bit
1 = Automatic amalgamation of bulk packets is done
0 = No automatic amalgamation
bit 30
MPTXEN: Automatic Splitting Option bit
1 = Automatic splitting of bulk packets is done
0 = No automatic splitting
bit 29
BIGEND: Byte Ordering Option bit
1 = Big Endian ordering
0 = Little Endian ordering
bit 28
HBRXEN: High-bandwidth RX ISO Option bit
1 = High-bandwidth RX ISO endpoint support is selected
0 = No High-bandwidth RX ISO support
bit 27
HBTXEN: High-bandwidth TX ISO Option bit
1 = High-bandwidth TX ISO endpoint support is selected
0 = No High-bandwidth TX ISO support
bit 26
DYNFIFOS: Dynamic FIFO Sizing Option bit
1 = Dynamic FIFO sizing is supported
0 = No Dynamic FIFO sizing
bit 25
SOFTCONE: Soft Connect/Disconnect Option bit
1 = Soft Connect/Disconnect is supported
0 = Soft Connect/Disconnect is not supported
bit 24
UTMIDWID: UTMI+ Data Width Option bit
Always ‘0’, indicating 8-bit UTMI+ data width
bit 23-0 Unimplemented: Read as ‘0’
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PIC32MZ Graphics (DA) Family
REGISTER 11-8:
Bit
Range
31:24
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AUTOSET
ISO
—
R/W-0, HS
R/W-0, HC
23:16 INCOMPTX
NAKTMOUT
15:8
7:0
bit 30
bit 29
bit 28
bit 27
bit 26
bit 25
bit 24
MODE
R/W-0
R/W-0
R/W-0
—
DMAREQEN FRCDATTG DMAREQMD
DATAWEN
R/W-0, HS
R/W-0
R/W-0
R/W-0, HS
R/W-0
R/W-0, HC
FLUSH
UNDERRUN
ERROR
FIFONE
TXPKTRDY
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MULT
R/W-0
—
DATATGGL
R/W-0
SENTSTALL SENDSTALL
RXSTALL SETUPPKT
CLRDT
R/W-0
TXMAXP
R/W-0
R/W-0
TXMAXP
Legend:
R = Readable bit
-n = Value at POR
bit 31
USBIENCSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0
(ENDPOINT 1-7)
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
AUTOSET: Auto Set Control bit
1 = TXPKTRDY will be automatically set when data of the maximum packet size (value in TXMAXP) is loaded
into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TXPKTRDY will have
to be set manually.
0 = TXPKTRDY must be set manually for all packet sizes
ISO: Isochronous TX Endpoint Enable bit (Device mode)
1 = Enables the endpoint for Isochronous transfers
0 = Disables the endpoint for Isochronous transfers and enables it for Bulk or Interrupt transfers.
This bit only has an effect in Device mode. In Host mode, it always returns zero.
MODE: Endpoint Direction Control bit
1 = Endpoint is TX
0 = Endpoint is RX
This bit only has any effect where the same endpoint FIFO is used for both TX and RX transactions.
DMAREQEN: Endpoint DMA Request Enable bit
1 = DMA requests are enabled for this endpoint
0 = DMA requests are disabled for this endpoint
FRCDATTG: Force Endpoint Data Toggle Control bit
1 = Forces the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of
whether an ACK was received.
0 = No forced behavior
DMAREQMD: Endpoint DMA Request Mode Control bit
1 = DMA Request Mode 1
0 = DMA Request Mode 0
This bit must not be cleared either before or in the same cycle as the DMAREQEN bit is cleared.
DATAWEN: Data Toggle Write Enable bit (Host mode)
1 = Enable the current state of the TX Endpoint data toggle (DATATGGL) to be written
0 = Disables writing the DATATGGL bit
DATATGGL: Data Toggle Control bit (Host mode)
When read, this bit indicates the current state of the TX Endpoint data toggle. If DATAWEN = 1, this bit may
be written with the required setting of the data toggle. If DATAWEN = 0, any value written to this bit is ignored.
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REGISTER 11-8:
bit 23
USBIENCSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0
(ENDPOINT 1-7) (CONTINUED)
INCOMPTX: Incomplete TX Status bit (Device mode)
1 = For high-bandwidth Isochronous endpoint, a large packet has been split into 2 or 3 packets for
transmission but insufficient IN tokens have been received to send all the parts
0 = Normal operation
In anything other than isochronous transfers, this bit will always return 0.
bit 22
bit 21
bit 20
NAKTMOUT: NAK Time-out status bit (Host mode)
1 = TX endpoint is halted following the receipt of NAK responses for longer than the NAKLIM setting
0 = Written by software to clear this bit
CLRDT: Clear Data Toggle Control bit
1 = Resets the endpoint data toggle to 0
0 = Do not clear the data toggle
SENTSTALL: STALL handshake transmission status bit (Device mode)
1 = STALL handshake is transmitted. The FIFO is flushed and the TXPKTRDY bit is cleared.
0 = Written by software to clear this bit
RXSTALL: STALL receipt bit (Host mode)
1 = STALL handshake is received. Any DMA request in progress is stopped, the FIFO is completely flushed
and the TXPKTRDY bit is cleared.
0 = Written by software to clear this bit
SENDSTALL: STALL handshake transmission control bit (Device mode)
1 = Issue a STALL handshake to an IN token
0 = Terminate stall condition
This bit has no effect when the endpoint is being used for Isochronous transfers.
SETUPPKT: Definition bit (Host mode)
1 = When set at the same time as the TXPKTRDY bit is set, send a SETUP token instead of an OUT token
for the transaction. This also clears the Data Toggle.
bit 19
bit 18
bit 17
bit 16
0 = Normal OUT token for the transaction
FLUSH: FIFO Flush control bit
1 = Flush the latest packet from the endpoint TX FIFO. The FIFO pointer is reset, the TXPKTRDY bit is
cleared and an interrupt is generated.
0 = Do not flush the FIFO
UNDERRUN: Underrun status bit (Device mode)
1 = An IN token has been received when the TXPKTRDY bit is not set.
0 = Written by software to clear this bit.
ERROR: Handshake failure status bit (Host mode)
1 = Three attempts have been made to send a packet and no handshake packet has been received
0 = Written by software to clear this bit.
FIFONE: FIFO Not Empty status bit
1 = There is at least 1 packet in the TX FIFO
0 = TX FIFO is empty
TXPKTRDY: TX Packet Ready Control bit
The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data
packet has been transmitted. This bit is also automatically cleared prior to loading a second packet into a double-buffered FIFO.
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REGISTER 11-8:
USBIENCSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0
(ENDPOINT 1-7) (CONTINUED)
bit 15-11 MULT: Multiplier Control bits
For Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints, multiplies TXMAXP by MULT+1
for the payload size.
For Bulk endpoints, MULT can be up to 32 and defines the number of “USB” packets of the specified payload
into which a single data packet placed in the FIFO should be split, prior to transfer. The data packet is required
to be an exact multiple of the payload specified by TXMAXP.
For Isochronous/Interrupts endpoints operating in Hi-Speed mode, MULT may be either 2 or 3 and specifies
the maximum number of such transactions that can take place in a single microframe.
bit 10-0 TXMAXP: Maximum TX Payload per transaction Control bits
This field sets the maximum payload (in bytes) transmitted in a single transaction. The value is subject to the
constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in
Full-Speed and Hi-Speed operations.
TXMAXP must be set to an even number of bytes for proper interrupt generation in DMA Mode 1.
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REGISTER 11-9:
USBIENCSR1: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 1
(ENDPOINT 1-7)
Bit
Bit
Range 31/23/15/7
R/W-0
31:24
15:8
7:0
Bit
29/21/13/5
R/W-0
R/W-0
ISO
AUTOCLR
AUTORQ
R/W-0, HC
23:16
Bit
30/22/14/6
R/W-0, HS
DMAREQEN
R/W-0
SENTSTALL SENDSTALL
CLRDT
RXSTALL
REQPKT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0, HC
R-0
R/W-0
—
—
DISNYET
PIDERR
DMAREQMD
R/W-0, HC
DATATWEN DATATGGL
R-0, HS
R/W-0, HS
DATAERR
OVERRUN
DERRNAKT
ERROR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLUSH
MULT
R/W-0
INCOMPRX
R-0, HS, HC
R/W-0, HS
FIFOFULL RXPKTRDY
R/W-0
R/W-0
RXMAXP
R/W-0
R/W-0
RXMAXP
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Cleared
W = Writable bit
‘1’ = Bit is set
HS = Hardware Set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
AUTOCLR: RXPKTRDY Automatic Clear Control bit
1 = RXPKTRDY will be automatically cleared when a packet of RXMAXP bytes has been unloaded from the
RX FIFO. When packets of less than the maximum packet size are unloaded, RXPKTRDY will have to be
cleared manually. When using a DMA to unload the RX FIFO, data is read from the RX FIFO in 4-byte
chunks regardless of the RXMAXP.
0 = No automatic clearing of RXPKTRDY
This bit should not be set for high-bandwidth Isochronous endpoints.
bit 30
ISO: Isochronous Endpoint Control bit (Device mode)
1 = Enable the RX endpoint for Isochronous transfers
0 = Enable the RX endpoint for Bulk/Interrupt transfers
AUTORQ: Automatic Packet Request Control bit (Host mode)
1 = REQPKT will be automatically set when RXPKTRDY bit is cleared.
0 = No automatic packet request
This bit is automatically cleared when a short packet is received.
bit 29
DMAREQEN: DMA Request Enable Control bit
1 = Enable DMA requests for the RX endpoint.
0 = Disable DMA requests for the RX endpoint.
bit 28
DISNYET: Disable NYET Handshakes Control/PID Error Status bit (Device mode)
1 = In Bulk/Interrupt transactions, disables the sending of NYET handshakes. All successfully received RX
packets are ACKed including at the point at which the FIFO becomes full.
0 = Normal operation.
In Bulk/Interrupt transactions, this bit only has any effect in Hi-Speed mode, in which mode it should be set for
all Interrupt endpoints.
PIDERR: PID Error Status bit (Host mode)
1 = In ISO transactions, this indicates a PID error in the received packet.
0 = No error
bit 27
DMAREQMD: DMA Request Mode Selection bit
1 = DMA Request Mode 1
0 = DMA Request Mode 0
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REGISTER 11-9:
USBIENCSR1: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 1
(ENDPOINT 1-7) (CONTINUED)
bit 26
DATATWEN: Data Toggle Write Enable Control bit (Host mode)
1 = DATATGGL can be written
0 = DATATGGL is not writable
bit 25
DATATGGL: Data Toggle bit (Host mode)
When read, this bit indicates the current state of the endpoint data toggle.
If DATATWEN = 1, this bit may be written with the required setting of the data toggle.
If DATATWEN = 0, any value written to this bit is ignored.
bit 24
INCOMPRX: Incomplete Packet Status bit
1 = The packet in the RX FIFO during a high-bandwidth Isochronous/Interrupt transfer is incomplete because
parts of the data were not received
0 = Written by then software to clear this bit
In anything other than Isochronous transfer, this bit will always return 0.
bit 23
CLRDT: Clear Data Toggle Control bit
1 = Reset the endpoint data toggle to 0
0 = Leave endpoint data toggle alone
bit 22
SENTSTALL: STALL Handshake Status bit (Device mode)
1 = STALL handshake is transmitted
0 = Written by the software to clear this bit
RXSTALL: STALL Handshake Receive Status bit (Host mode)
1 = A STALL handshake has been received. An interrupt is generated.
0 = Written by the software to clear this bit
bit 21
SENDSTALL: STALL Handshake Control bit (Device mode)
1 = Issue a STALL handshake
0 = Terminate stall condition
REQPKT: IN Transaction Request Control bit (Host mode)
1 = Request an IN transaction.
0 = No request
This bit is cleared when RXPKTRDY is set.
bit 20
FLUSH: Flush FIFO Control bit
1 = Flush the next packet to be read from the endpoint RX FIFO. The FIFO pointer is reset and the
RXPKTRDY bit is cleared. This should only be used when RXPKTRDY is set. If the FIFO is doublebuffered, FLUSH may need to be set twice to completely clear the FIFO.
0 = Normal FIFO operation
This bit is automatically cleared.
bit 19
DATAERR: Data Packet Error Status bit (Device mode)
1 = The data packet has a CRC or bit-stuff error.
0 = No data error
This bit is cleared when RXPKTRDY is cleared. This bit is only valid when the endpoint is operating in ISO
mode. In Bulk mode, it always returns zero.
DERRNAKT: Data Error/NAK Time-out Status bit (Host mode)
1 = The data packet has a CRC or bit-stuff error. In Bulk mode, the RX endpoint is halted following the receipt
of NAK responses for longer than the time set as the NAK limit.
0 = No data or NAK time-out error
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REGISTER 11-9:
bit 18
USBIENCSR1: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 1
(ENDPOINT 1-7) (CONTINUED)
OVERRUN: Data Overrun Status bit (Device mode)
1 = An OUT packet cannot be loaded into the RX FIFO.
0 = Written by software to clear this bit
This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero.
ERROR: No Data Packet Received Status bit (Host mode)
1 = Three attempts have been made to receive a packet and no data packet has been received. An interrupt
is generated.
0 = Written by the software to clear this bit.
This bit is only valid when the RX endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always
returns zero.
bit 17
FIFOFULL: FIFO Full Status bit
1 = No more packets can be loaded into the RX FIFO
0 = The RX FIFO has at least one free space
bit 16
RXPKTRDY: Data Packet Reception Status bit
1 = A data packet has been received. An interrupt is generated.
0 = Written by software to clear this bit when the packet has been unloaded from the RX FIFO.
bit 15-11 MULT: Multiplier Control bits
For Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints, multiplies RXMAXP by MULT+1
for the payload size.
For Bulk endpoints, MULT can be up to 32 and defines the number of “USB” packets of the specified payload
into which a single data packet placed in the FIFO should be split, prior to transfer. The data packet is required
to be an exact multiple of the payload specified by RXMAXP.
For Isochronous/Interrupts endpoints operating in Hi-Speed mode, MULT may be either 2 or 3 and specifies
the maximum number of such transactions that can take place in a single microframe.
bit 10-0
Note:
RXMAXP: Maximum RX Payload Per Transaction Control bits
This field sets the maximum payload (in bytes) transmitted in a single transaction. The value is subject to the
constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in
Full-Speed and Hi-Speed operations.
RXMAXP must be set to an even number of bytes for proper interrupt generation in DMA Mode 1.
Transfer size greater than RxMaxP is handled by DMA Mode 1 only.
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REGISTER 11-10: USBIENCSR2: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 2
(ENDPOINT 1-7)
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6
31:24
23:16
15:8
7:0
R/W-0
R/W-0
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
R-0
TXINTERV
R/W-0
R/W-0
R/W-0
SPEED
U-0
U-0
—
—
R-0
R-0
R/W-0
R/W-0
PROTOCOL
R-0
TEP
R-0
R-0
R-0
RXCNT
R-0
R-0
R-0
R-0
RXCNT
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Cleared
W = Writable bit
‘1’ = Bit is set
HS = Hardware Set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 TXINTERV: Endpoint TX Polling Interval/NAK Limit bits (Host mode)
For Interrupt and Isochronous transfers, this field defines the polling interval for the endpoint. For Bulk endpoints, this field sets the number of frames/microframes after which the endpoint should time out on receiving
a stream of NAK responses.
The following table describes the valid values and interpretation for these bits:
Transfer Type
Speed
Valid Values (m)
Low/Full
0x01 to 0xFF
Polling interval is ‘m’ frames.
High
0x01 to 0x10
Polling interval is 2(m-1) frames.
Isochronous
Full or High
0x01 to 0x10
Polling interval is 2(m-1) frames/microframes.
Bulk
Full or High
0x02 to 0x10
NAK limit is 2(m-1) frames/microframes. A
value of ‘0’ or ‘1’ disables the NAK time-out
function.
Interrupt
Interpretation
bit 23-22 SPEED: TX Endpoint Operating Speed Control bits (Host mode)
11 = Low-Speed
10 = Full-Speed
01 = Hi-Speed
00 = Reserved
bit 21-20 PROTOCOL: TX Endpoint Protocol Control bits
11 = Interrupt
10 = Bulk
01 = Isochronous
00 = Control
bit 19-16 TEP: TX Target Endpoint Number bits
This value is the endpoint number contained in the TX endpoint descriptor returned to the USB module during
device enumeration.
bit 15-14 Unimplemented: Read as ‘0’
bit 13-0 RXCNT: Receive Count bits
The number of received data bytes in the endpoint RX FIFO. The value returned changes as the contents of
the FIFO change and is only valid while RXPKTRDY is set.
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REGISTER 11-11: USBIENCSR3: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 3
(ENDPOINT 1-7)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
RXFIFOSZ
TXFIFOSZ
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXINTERV
R/W-0
R/W-0
R/W-0
SPEED
Legend:
R = Readable bit
-n = Value at POR
R/W-0
R/W-0
PROTOCOL
W = Writable bit
‘1’ = Bit is set
TEP
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 RXFIFOSZ: Receive FIFO Size bits
1111 = Reserved
1110 = Reserved
1101 = 8192 bytes
1100 = 4096 bytes
•
•
•
0011 = 8 bytes
0010 = Reserved
0001 = Reserved
0000 = Reserved or endpoint has not been configured
This register only has this interpretation when dynamic sizing is not selected. It is not valid where dynamic
FIFO sizing is used.
bit 27-24 TXFIFOSZ: Transmit FIFO Size bits
1111 = Reserved
1110 = Reserved
1101 = 8192 bytes
1100 = 4096 bytes
•
•
•
0011 = 8 bytes
0010 = Reserved
0001 = Reserved
0000 = Reserved or endpoint has not been configured
This register only has this interpretation when dynamic sizing is not selected. It is not valid where dynamic
FIFO sizing is used.
bit 23-16 Unimplemented: Read as ‘0’
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PIC32MZ Graphics (DA) Family
REGISTER 11-11: USBIENCSR3: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 3
(ENDPOINT 1-7) (CONTINUED)
bit 15-8
RXINTERV: Endpoint RX Polling Interval/NAK Limit bits
For Interrupt and Isochronous transfers, this field defines the polling interval for the endpoint. For Bulk endpoints, this field sets the number of frames/microframes after which the endpoint should time out on receiving
a stream of NAK responses.
The following table describes the valid values and meaning for this field:
Transfer Type
Speed
Valid Values (m)
Low/Full
0x01 to 0xFF
Polling interval is ‘m’ frames.
High
0x01 to 0x10
Polling interval is 2(m-1) frames.
Isochronous
Full or High
0x01 to 0x10
Polling interval is 2(m-1) frames/microframes.
Bulk
Full or High
0x02 to 0x10
NAK limit is 2(m-1) frames/microframes. A
value of ‘0’ or ‘1’ disables the NAK time-out
function.
Interrupt
bit 7-6
SPEED: RX Endpoint Operating Speed Control bits
11 = Low-Speed
10 = Full-Speed
01 = Hi-Speed
00 = Reserved
bit 5-4
PROTOCOL: RX Endpoint Protocol Control bits
11 = Interrupt
10 = Bulk
01 = Isochronous
00 = Control
bit 3-0
TEP: RX Target Endpoint Number bits
Interpretation
This value is the endpoint number contained in the TX endpoint descriptor returned to the USB module during
device enumeration.
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REGISTER 11-12: USBFIFOx: USB FIFO DATA REGISTER ‘x’ (‘x’ = 0-7)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATA
R/W-0
R/W-0
R/W-0
R/W-0
DATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATA
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
R/W-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DATA: USB Transmit/Receive FIFO Data bits
Writes to this register loads data into the TxFIFO for the corresponding endpoint. Reading from this register
unloads data from the RxFIFO for the corresponding endpoint.
Transfers may be 8-bit, 16-bit or 32-bit as required, and any combination of access is allowed provided the
data accessed is contiguous. However, all transfers associated with one packet must be of the same width
so that data is consistently byte-, word- or double-word aligned. The last transfer may contain fewer bytes
than the previous transfers in order to complete an odd-byte or odd-word transfer.
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PIC32MZ Graphics (DA) Family
REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
RXDPB
U-0
U-0
U-0
R/W-0
—
—
—
TXDPB
U-0
U-0
U-0
U-0
RXFIFOSZ
R/W-0
R/W-0
TXFIFOSZ
U-0
U-0
R/W-0
R/W-0
RXEDMA
—
—
—
—
—
—
TXEDMA
R-1
R-0
R-0
R-0
R-0
R-0
R/W-0, HC
BDEV
FSDEV
LSDEV
VBUS
HOSTMODE HOSTREQ
R/W-0
SESSION
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28
RXDPB: RX Endpoint Double-packet Buffering Control bit
1 = Double-packet buffer is supported. This doubles the size set in RXFIFOSZ.
0 = Double-packet buffer is not supported
bit 27-24 RXFIFOSZ: RX Endpoint FIFO Packet Size bits
The maximum packet size to allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth
packets prior to transmission)
1111 = Reserved
•
•
•
1010 = Reserved
1001 = 4096 bytes
1000 = 2048 bytes
0111 = 1024 bytes
0110 = 512 bytes
0101 = 256 bytes
0100 = 128 bytes
0011 = 64 bytes
0010 = 32 bytes
0001 = 16 bytes
0000 = 8 bytes
bit 23-21 Unimplemented: Read as ‘0’
bit 20
TXDPB: TX Endpoint Double-packet Buffering Control bit
1 = Double-packet buffer is supported. This doubles the size set in TXFIFOSZ.
0 = Double-packet buffer is not supported
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REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER (CONTINUED)
bit 19-16 TXFIFOSZ: TX Endpoint FIFO packet size bits
The maximum packet size to allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth
packets prior to transmission)
1111 = Reserved
•
•
•
1010 = Reserved
1001 = 4096 bytes
1000 = 2048 bytes
0111 = 1024 bytes
0110 = 512 bytes
0101 = 256 bytes
0100 = 128 bytes
0011 = 64 bytes
0010 = 32 bytes
0001 = 16 bytes
0000 = 8 bytes
bit 15-10 Unimplemented: Read as ‘0’
bit 9
TXEDMA: TX Endpoint DMA Assertion Control bit
1 = DMA_REQ signal for all IN endpoints will be deasserted when MAXP-8 bytes have been written to an
endpoint. This is Early mode.
0 = DMA_REQ signal for all IN endpoints will be deasserted when MAXP bytes have been written to an
endpoint. This is Late mode.
bit 8
RXEDMA: RX Endpoint DMA Assertion Control bit
1 = DMA_REQ signal for all OUT endpoints will be deasserted when MAXP-8 bytes have been written to
an endpoint. This is Early mode.
0 = DMA_REQ signal for all OUT endpoints will be deasserted when MAXP bytes have been written to an
endpoint. This is Late mode.
bit 7
BDEV: USB Device Type bit
1 = USB is operating as a ‘B’ device
0 = USB is operating as an ‘A’ device
bit 6
FSDEV: Full-Speed/Hi-Speed device detection bit (Host mode)
1 = A Full-Speed or Hi-Speed device has been detected being connected to the port
0 = No Full-Speed or Hi-Speed device detected
bit 5
LSDEV: Low-Speed Device Detection bit (Host mode)
1 = A Low-Speed device has been detected being connected to the port
0 = No Low-Speed device detected
bit 4-3
VBUS: VBUS Level Detection bits
11 = Above VBUS Valid
10 = Above AValid, below VBUS Valid
01 = Above Session End, below AValid
00 = Below Session End
bit 2
HOSTMODE: Host Mode bit
1 = USB module is acting as a Host
0 = USB module is not acting as a Host
bit 1
HOSTREQ: Host Request Control bit
‘B’ device only:
1 = USB module initiates the Host Negotiation when Suspend mode is entered. This bit is cleared when
Host Negotiation is completed.
0 = Host Negotiation is not taking place
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PIC32MZ Graphics (DA) Family
REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER (CONTINUED)
bit 0
SESSION: Active Session Control/Status bit
‘A’ device:
1 = Start a session
0 = End a session
‘B’ device:
1 = (Read) Session has started or is in progress, (Write) Initiate the Session Request Protocol
0 = When USB module is in Suspend mode, clearing this bit will cause a software disconnect
Clearing this bit when the USB module is not suspended will result in undefined behavior.
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REGISTER 11-14: USBFIFOA: USB FIFO ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXFIFOAD
R/W-0
R/W-0
RXFIFOAD
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXFIFOAD
R/W-0
R/W-0
R/W-0
TXFIFOAD
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-16 RXFIFOAD: Receive Endpoint FIFO Address bits
Start address of the endpoint FIFO in units of 8 bytes as follows:
1111111111111 = 0xFFF8
•
•
•
0000000000010 = 0x0010
0000000000001 = 0x0008
0000000000000 = 0x0000
bit 15-13 Unimplemented: Read as ‘0’
bit 12-0 TXFIFOAD: Transmit Endpoint FIFO Address bits
Start address of the endpoint FIFO in units of 8 bytes as follows:
1111111111111 = 0xFFF8
•
•
•
0000000000010 = 0x0010
0000000000001 = 0x0008
0000000000000 = 0x0000
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REGISTER 11-15: USBHWVER: USB HARDWARE VERSION REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-1
R-0
R-0
R-0
RC
R-0
VERMAJOR
R-0
R-0
R-0
VERMINOR
R-0
R-0
R-0
R-0
VERMINOR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
RC: Release Candidate bit
1 = USB module was created using a release candidate
0 = USB module was created using a full release
bit 14-10 VERMAJOR: USB Module Major Version number bits
This read-only number is the Major version number for the USB module.
bit 9-0
VERMINOR: USB Module Minor Version number bits
This read-only number is the Minor version number for the USB module.
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REGISTER 11-16: USBINFO: USB INFORMATION REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
VPLEN
R/W-0
R/W-1
R/W-0
R/W-1
R/W-1
WTCON
R-1
R-0
R-0
WTID
R-0
R-1
DMACHANS
R-0
R-1
R-1
RXENDPTS
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
R-1
R-0
R-0
RAMBITS
R-1
R-0
R-1
R-1
R-1
TXENDPTS
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 VPLEN: VBUS pulsing charge length bits
Sets the duration of the VBUS pulsing charge in units of 546.1 µs. (The default setting corresponds to 32.77
ms.)
bit 23-20 WTCON: Connect/Disconnect filter control bits
Sets the wait to be applied to allow for the connect/disconnect filter in units of 533.3 ns. The default setting
corresponds to 2.667 µs.
bit 19-6
WTID: ID delay valid control bits
Sets the delay to be applied from IDPULLUP being asserted to IDDIG being considered valid in units of
4.369ms. The default setting corresponds to 52.43ms.
bit 15-12 DMACHANS: DMA Channels bits
These read-only bits provide the number of DMA channels in the USB module. For the PIC32MZ DA family,
this number is 8.
bit 11-8 RAMBITS: RAM address bus width bits
These read-only bits provide the width of the RAM address bus. For the PIC32MZ DA family, this number is
12.
bit 7-4
RXENDPTS: Included RX Endpoints bits
This read-only register gives the number of RX endpoints in the design. For the PIC32MZ DA family, this
number is 7.
bit 3-0
TXENDPTS: Included TX Endpoints bits
These read-only bits provide the number of TX endpoints in the design. For the PIC32MZ DA family, this
number is 7.
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PIC32MZ Graphics (DA) Family
REGISTER 11-17: USBEOFRST: USB END-OF-FRAME/SOFT RESET CONTROL REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
NRSTX
NRST
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
R.W-0
R/W-1
R/W-0
R.W-1
R/W-1
R/W-1
R.W-0
R/W-0
R/W-0
LSEOF
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
FSEOF
R/W-1
R/W-0
Legend:
R = Readable bit
-n = Value at POR
R/W-0
R/W-0
R/W-0
HSEOF
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25
NRSTX: Reset of XCLK Domain bit
1 = Reset the XCLK domain, which is clock recovered from the received data by the PHY
0 = Normal operation
bit 24
NRST: Reset of CLK Domain bit
1 = Reset the CLK domain, which is clock recovered from the peripheral bus
0 = Normal operation
bit 23-16 LSEOF: Low-Speed EOF bits
These bits set the Low-Speed transaction in units of 1.067 µs (default setting is 121.6 µs) prior to the EOF
to stop new transactions from beginning.
bit 15-8 FSEOF: Full-Speed EOF bits
These bits set the Full-Speed transaction in units of 533.3 µs (default setting is 63.46 µs) prior to the EOF
to stop new transactions from beginning.
bit 7-0
HSEOF: Hi-Speed EOF bits
These bits set the Hi-Speed transaction in units of 133.3 µs (default setting is 17.07µs) prior to the EOF to
stop new transactions from beginning.
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REGISTER 11-18: USBExTXA: USB ENDPOINT ‘x’ TRANSMIT ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
R/W-0
TXHUBPRT
R/W-0
R/W-0
R/W-0
MULTTRAN
R/W-0
TXHUBADD
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
Legend:
R = Readable bit
-n = Value at POR
TXFADDR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Unimplemented: Read as ‘0’
bit 30-24 TXHUBPRT: TX Hub Port bits (Host mode)
When a Low-Speed or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, this
field records the port number of that USB 2.0 hub.
bit 23
MULTTRAN: TX Hub Multiple Translators bit (Host mode)
1 = The USB 2.0 hub has multiple transaction translators
0 = The USB 2.0 hub has a single transaction translator
bit 22-16 TXHUBADD: TX Hub Address bits (Host mode)
When a Low-Speed or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, these
bits record the address of the USB 2.0 hub.
bit 15-7
Unimplemented: Read as ‘0’
bit 6-0
TXFADDR: TX Functional Address bits (Host mode)
Specifies the address for the target function that is be accessed through the associated endpoint. It needs
to be defined for each TX endpoint that is used.
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2015-2019 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 11-19: USBExRXA: USB ENDPOINT ‘x’ RECEIVE ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
R/W-0
RXHUBPRT
R/W-0
R/W-0
R/W-0
MULTTRAN
R/W-0
RXHUBADD
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
Legend:
R = Readable bit
-n = Value at POR
RXFADDR
HC = Hardware Cleared
W = Writable bit
‘1’ = Bit is set
HS = Hardware Set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Unimplemented: Read as ‘0’
bit 30-24 RXHUBPRT: RX Hub Port bits (Host mode)
When a Low- Speed or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, this field
records the port number of that USB 2.0 hub.
bit 23
MULTTRAN: RX Hub Multiple Translators bit (Host mode)
1 = The USB 2.0 hub has multiple transaction translators
0 = The USB 2.0 hub has a single transaction translator
bit 22-16 TXHUBADD: RX Hub Address bits (Host mode)
When a Low-Speed or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, these
bits record the address of the USB 2.0 hub.
bit 15-7
Unimplemented: Read as ‘0’
bit 6-0
RXFADDR: RX Functional Address bits (Host mode)
Specifies the address for the target function that is be accessed through the associated endpoint. It needs to
be defined for each RX endpoint that is used.
2015-2019 Microchip Technology Inc.
DS60001361J-page 247
PIC32MZ Graphics (DA) Family
REGISTER 11-20: USBDMAINT: USB DMA INTERRUPT REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
DMA8IF
DMA7IF
DMA6IF
DMA5IF
DMA4IF
DMA3IF
DMA2IF
DMA1IF
Legend:
R = Readable bit
-n = Value at POR
bit 31-8
bit 7-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
DMAxIF: DMA Channel ‘x’ Interrupt bit
1 = The DMA channel has an interrupt event
0 = No interrupt event
All bits are cleared on a read of the register.
DS60001361J-page 248
2015-2019 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 11-21: USBDMAxC: USB DMA CHANNEL ‘x’ CONTROL REGISTER (‘x’ = 1-8)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
DMABRSTM
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DMAIE
DMAMODE
DMADIR
DMAEN
DMAEP
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
DMAERR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10-9 DMABRSTM: DMA Burst Mode Selection bit
11 = Burst Mode 3: INCR16, INCR8, INCR4 or unspecified length
10 = Burst Mode 2: INCR8, INCR4 or unspecified length
01 = Burst Mode 1: INCR4 or unspecified length
00 = Burst Mode 0: Bursts of unspecified length
bit 8
DMAERR: Bus Error bit
1 = A bus error has been observed on the input
0 = The software writes this to clear the error
bit 7-4
DMAEP: DMA Endpoint Assignment bits
These bits hold the endpoint that the DMA channel is assigned to. Valid values are 0-7.
bit 3
DMAIE: DMA Interrupt Enable bit
1 = Interrupt is enabled for this channel
0 = Interrupt is disabled for this channel
bit 2
DMAMODE: DMA Transfer Mode bit
1 = DMA Mode1 Transfers
0 = DMA Mode0 Transfers
bit 1
DMADIR: DMA Transfer Direction bit
1 = DMA Read (TX endpoint)
0 = DMA Write (RX endpoint)
bit 0
DMAEN: DMA Enable bit
1 = Enable the DMA transfer and start the transfer
0 = Disable the DMA transfer
2015-2019 Microchip Technology Inc.
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PIC32MZ Graphics (DA) Family
REGISTER 11-22: USBDMAxA: USB DMA CHANNEL ‘x’ MEMORY ADDRESS REGISTER (‘x’ = 1-8)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
DMAADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DMAADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DMAADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DMAADDR
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
Bit
28/20/12/4
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DMAADDR: DMA Memory Address bits
This register identifies the current memory address of the corresponding DMA channel. The initial memory
address written to this register during initialization must have a value such that its modulo 4 value is equal
to ‘0’. The lower two bits of this register are read only and cannot be set by software. As the DMA transfer
progresses, the memory address will increment as bytes are transferred.
REGISTER 11-23: USBDMAxN: USB DMA CHANNEL ‘x’ COUNT REGISTER (‘X’ = 1-8)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DMACOUNT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DMACOUNT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DMACOUNT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DMACOUNT
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
Bit
28/20/12/4
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DMACOUNT: DMA Transfer Count bits
This register identifies the current DMA count of the transfer. Software will set the initial count of the transfer
which identifies the entire transfer length. As the count progresses this count is decremented as bytes are
transferred.
DS60001361J-page 250
2015-2019 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 11-24: USBExRPC: USB ENDPOINT ‘x’ REQUEST PACKET COUNT REGISTER (HOST
MODE ONLY) (‘x’ = 1-7)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RQPKTCNT
R/W-0
R/W-0
RQPKTCNT
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 RQPKTCNT: Request Packet Count bits
Sets the number of packets of size MAXP that are to be transferred in a block transfer. This register is only
available in Host mode when AUTOREQ is set.
REGISTER 11-25: USBDPBFD: USB DOUBLE PACKET BUFFER DISABLE REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
EP7TXD
EP6TXD
EP5TXD
EP4TXD
EP3TXD
EP2TXD
EP1TXD
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
EP7RXD
EP6RXD
EP5RXD
EP4RXD
EP3RXD
EP2RXD
EP1RXD
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-17 EP7TXD:EP1TXD: TX Endpoint `x' Double Packet Buffer Disable bits
1 = TX double packet buffering is disabled for endpoint `x'
0 = TX double packet buffering is enabled for endpoint `x'
bit 16-8 Unimplemented: Read as ‘0’
bit 7-1
EP7RXD:EP1RXD: RX Endpoint `x' Double Packet Buffer Disable bits
1 = RX double packet buffering is disabled for endpoint `x'
0 = RX double packet buffering is enabled for endpoint `x'
bit 0
Unimplemented: Read as ‘0’
2015-2019 Microchip Technology Inc.
DS60001361J-page 251
PIC32MZ Graphics (DA) Family
REGISTER 11-26: USBTMCON1: USB TIMING CONTROL REGISTER 1
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
THHSRTN
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
THHSRTN
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
TUCH
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
TUCH
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 THHSRTN:: Hi-Speed Resume Signaling Delay bits
These bits set the delay from the end of Hi-Speed resume signaling (acting as a Host) to enable the UTM
normal operating mode.
bit 15-0 TUCH: Chirp Time-out bits
These bits set the chirp time-out. This number, when multiplied by 4, represents the number of USB module
clock cycles before the time-out occurs.
Note:
Use of this register will allow the Hi-Speed time-out to be set to values that are greater than the maximum
specified in the USB 2.0 specification, making the USB module non-compliant.
REGISTER 11-27: USBTMCON2: USB TIMING CONTROL REGISTER 2
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
THBST
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3-0 THBST: High Speed Time-out Adder bits
These bits represent the value to be added to the minimum high speed time-out period of 736 bit times. The
time-out period can be increased in increments of 64 Hi-Speed bit times (133 ns).
Note:
Use of this register will allow the Hi-Speed time-out to be set to values that are greater than the maximum
specified in the USB 2.0 specification, making the USB module non-compliant.
DS60001361J-page 252
2015-2019 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 11-28: USBLPMR1: USB LINK POWER MANAGEMENT CONTROL
REGISTER 1
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
—
—
U-0
U-0
U-0
R/W-0
—
—
—
LPMNAK
R-0
R-0
R-0
R-0
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
LPMERRIE LPMRESIE LPMACKIE
ENDPOINT
R-0
R-0
R-0
R-0
HIRD
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Cleared
W = Writable bit
‘1’ = Bit is set
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
LPMNYIE
LPMSTIE
LPMTOIE
R/W-0
LPMEN
R/W-0, HC
R/W-0, HC
LPMRES
LPMXMT
U-0
U-0
U-0
R-0
—
—
—
RMTWAK
R-0
R-0
R-0
R-0
LNKSTATE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29
LPMERRIE: LPM Error Interrupt Enable bit
1 = LPMERR interrupt is enabled
0 = LPMERR interrupt is disabled
bit 28
LPMRESIE: LPM Resume Interrupt Enable bit
1 = LPMRES interrupt is enabled
0 = LPMRES interrupt is disabled
bit 27
LPMACKIE: LPM Acknowledge Interrupt Enable bit
1 = Enable the LPMACK Interrupt
0 = Disable the LPMACK Interrupt
bit 26
LPMNYIE: LPM NYET Interrupt Enable bit
1 = Enable the LPMNYET Interrupt
0 = Disable the LPMNYET Interrupt
bit 25
LPMSTIE: LPM STALL Interrupt Enable bit
1 = Enable the LPMST Interrupt
0 = Disable the LPMST Interrupt
bit 24
LPMTOIE: LPM Time-out Interrupt Enable bit
1 = Enable the LPMTO Interrupt
0 = Disable the LPMTO Interrupt
bit 23-21 Unimplemented: Read as ‘0’
bit 20
LPMNAK: LPM-only Transaction Setting bit
1 = All endpoints will respond to all transactions other than a LPM transaction with a NAK
0 = Normal transaction operation
Setting this bit to ‘1’ will only take effect after the USB module as been LPM suspended.
bit 19-18 LPMEN: LPM Enable bits (Device mode)
11 = LPM Extended transactions are supported
10 = LPM and Extended transactions are not supported
01 = LPM mode is not supported but Extended transactions are supported
00 = LPM Extended transactions are supported
bit 17
LPMRES: LPM Resume bit
1 = Initiate resume (remote wake-up). Resume signaling is asserted for 50 µs.
0 = No resume operation
This bit is self-clearing.
2015-2019 Microchip Technology Inc.
DS60001361J-page 253
PIC32MZ Graphics (DA) Family
REGISTER 11-28: USBLPMR1: USB LINK POWER MANAGEMENT CONTROL
REGISTER 1 (CONTINUED)
bit 16
LPMXMT: LPM Transition to the L1 State bit
When in Device mode:
1 = USB module will transition to the L1 state upon the receipt of the next LPM transaction. LPMEN must
be set to ‘0b11. Both LPMXMT and LPMEN must be set in the same cycle.
0 = Maintain current state
When LPMXMT and LPMEN are set, the USB module can respond in the following ways:
• If no data is pending (all TX FIFOs are empty), the USB module will respond with an ACK. The bit will
self clear and a software interrupt will be generated.
• If data is pending (data resides in at least one TX FIFO), the USB module will respond with a NYET. In
this case, the bit will not self clear however a software interrupt will be generated.
When in Host mode:
1 = USB module will transmit an LPM transaction. This bit is self clearing, and will be immediately cleared
upon receipt of any Token or three time-outs have occurred.
0 = Maintain current state
bit 15-12 ENDPOINT: LPM Token Packet Endpoint bits
This is the endpoint in the token packet of the LPM transaction.
bit 11-9 Unimplemented: Read as ‘0’
bit 8
RMTWAK: Remote Wake-up Enable bit
This bit is applied on a temporary basis only and is only applied to the current suspend state.
1 = Remote wake-up is enabled
0 = Remote wake-up is disabled
bit 7-4
HIRD: Host Initiated Resume Duration bits
The minimum time the host will drive resume on the bus. The value in this register corresponds to an actual
resume time of:
bit 3-0
LNKSTATE: Link State bits
This value is provided by the host to the peripheral to indicate what state the peripheral must transition to
after the receipt and acceptance of a LPM transaction. The only valid value for this register is ‘1’ for Sleep
State (L1). All other values are reserved.
Resume Time = 50 µs + HIRD * 75 µs. The resulting range is 50 µs to 1200 µs.
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2015-2019 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 11-29: USBLPMR2: USB LINK POWER MANAGEMENT CONTROL REGISTER 2
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R-0
R-0, HS
—
—
—
LPMFADDR
Legend:
R = Readable bit
-n = Value at POR
LPMERRIF LPMRESIF
HS = Hardware Set
W = Writable bit
‘1’ = Bit is set
R-0, HS
R-0, HS
R-0, HS
R-0, HS
LPMNCIF
LPMACKIF
LPMNYIF
LPMSTIF
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14-8 LPMFADDR: LPM Payload Function Address bits
These bits contain the address of the LPM payload function.
bit 7-6
Unimplemented: Read as ‘0’
bit 5
LPMERRIF: LPM Error Interrupt Flag bit (Device mode)
1 = An LPM transaction was received that had a LINKSTATE field that is not supported. The response will
be a STALL.
0 = No error condition
bit 4
LPMRESIF: LPM Resume Interrupt Flag bit
1 = The USB module has resumed (for any reason)
0 = No Resume condition
bit 3
LPMNCIF: LPM NC Interrupt Flag bit
When in Device mode:
1 = The USB module received a LPM transaction and responded with a NYET due to data pending in the
RX FIFOs.
0 = No NC interrupt condition
When in Host mode:
1 = A LPM transaction is transmitted and has failed to complete. The transaction will have failed because
a timeout occurred or there were bit errors in the response for three attempts.
0 = No NC interrupt condition
bit 2
LPMACKIF: LPM ACK Interrupt Flag bit
When in Device mode:
1 = A LPM transaction was received and the USB Module responded with an ACK
0 = No ACK interrupt condition
When in Host mode:
1 = The LPM transaction is transmitted and the device responds with an ACK
0 = No ACK interrupt condition
bit 1
LPMNYIF: LPM NYET Interrupt Flag bit
When in Device mode:
1 = A LPM transaction is received and the USB Module responded with a NYET
0 = No NYET interrupt flag
When in Host mode:
1 = A LPM transaction is transmitted and the device responded with an NYET
0 = No NYET interrupt flag
2015-2019 Microchip Technology Inc.
DS60001361J-page 255
PIC32MZ Graphics (DA) Family
REGISTER 11-29: USBLPMR2: USB LINK POWER MANAGEMENT CONTROL REGISTER 2
bit 0
LPMSTIF: LPM STALL Interrupt Flag bit
When in Device mode:
1 = A LPM transaction was received and the USB Module responded with a STALL
0 = No Stall condition
When in Host mode:
1 = A LPM transaction was transmitted and the device responded with a STALL
0 = No Stall condition
DS60001361J-page 256
2015-2019 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 11-30: USBCRCON: USB CLOCK/RESET CONTROL REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
R-0, HS, HC
R-0, HS, HC
R/W-1, HS
—
—
—
—
—
USBIF
USBRF
USBWKUP
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
r-1
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
USB
IDOVEN
USB
IDVAL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PHYIDEN
VBUS
MONEN
ASVAL
MONEN
BSVAL
MONEN
SEND
MONEN
USBIE
USBRIE
USB
WKUPEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26
USBIF: USB General Interrupt Flag bit
1 = An event on the USB Bus has occurred
0 = No interrupt from USB module or interrupts have not been enabled
bit 25
USBRF: USB Resume Flag bit
1 = Resume from Suspend state. Device wake-up activity can be started.
0 = No Resume activity detected during Suspend, or not in Suspend state
bit 24
USBWKUP: USB Activity Status bit
1 = Connect, disconnect, or other activity on USB detected since last cleared
0 = No activity detected on USB
Note:
This bit should be cleared just prior to entering sleep, but it should be checked that no activity
has already occurred on USB before actually entering sleep.
bit 23-16 Unimplemented: Read as ‘0’
bit 15
Reserved: Read as ‘1’
bit 14-10 Unimplemented: Read as ‘0’
bit 9
USBIDOVEN: USB ID Override Enable bit
1 = Enable use of USBIDVAL bit
0 = Disable use of USBIDVAL and instead use the PHY value
bit 8
USBIDVAL: USB ID Value bit
1 = ID override value is 1
0 = ID override value is 0
bit 7
PHYIDEN: PHY ID Monitoring Enable bit
1 = Enable monitoring of the ID bit from the USB PHY
0 = Disable monitoring of the ID bit from the USB PHY
bit 6
VBUSMONEN: VBUS Monitoring for OTG Enable bit
1 = Enable monitoring for VBUS in VBUS Valid range (between 4.4V and 4.75V)
0 = Disable monitoring for VBUS in VBUS Valid range
bit 5
ASVALMONEN: A-Device VBUS Monitoring for OTG Enable bit
1 = Enable monitoring for VBUS in Session Valid range for A-device (between 0.8V and 2.0V)
0 = Disable monitoring for VBUS in Session Valid range for A-device
bit 4
BSVALMONEN: B-Device VBUS Monitoring for OTG Enable bit
1 = Enable monitoring for VBUS in Session Valid range for B-device (between 0.8V and 4.0V)
0 = Disable monitoring for VBUS in Session Valid range for B-device
2015-2019 Microchip Technology Inc.
DS60001361J-page 257
PIC32MZ Graphics (DA) Family
REGISTER 11-30: USBCRCON: USB CLOCK/RESET CONTROL REGISTER (CONTINUED)
bit 3
SENDMONEN: Session End VBUS Monitoring for OTG Enable bit
1 = Enable monitoring for VBUS in Session End range (between 0.2V and 0.8V)
0 = Disable monitoring for VBUS in Session End range
bit 2
USBIE: USB General Interrupt Enable bit
1 = Enables general interrupt from USB module
0 = Disables general interrupt from USB module
bit 1
USBRIE: USB Resume Interrupt Enable bit
1 = Enable remote resume from suspend Interrupt
0 = Disable interrupt to a Remote Devices USB resume signaling
bit 0
USBWKUPEN: USB Activity Detection Interrupt Enable bit
1 = Enable interrupt for detection of activity on USB bus in Sleep mode
0 = Disable interrupt for detection of activity on USB bus in Sleep mode
DS60001361J-page 258
2015-2019 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
12.0
I/O PORTS
Note:
Some of the key features of the I/O ports are as follows:
• Individual output pin open-drain enable/disable
• Individual input pin weak pull-up and pull-down
• Monitor selective inputs and generate interrupt
when change in pin state is detected
• Operation during Sleep and Idle modes
• Fast bit manipulation using CLR, SET, and INV
registers
Figure 12-1 illustrates a block diagram of a typical
multiplexed I/O port.
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS60001120), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
General purpose I/O pins are the simplest of
peripherals. They allow the PIC32MZ DA family device
to monitor and control other devices. To add flexibility
and functionality, some pins are multiplexed with
alternate function(s). These functions depend on which
peripheral features are on the device. In general, when
a peripheral is functioning, that pin may not be used as
a general purpose I/O pin.
FIGURE 12-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Peripheral Module
PIO Module
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
Port Control
RD ODC
PBCLK4
Data Bus
D
PBCLK4
Q
ODC
CK
EN Q
WR ODC
1
RD TRIS
0
0
I/O Cell
1
D
Q
1
TRIS
CK
EN Q
WR TRIS
0
Output Multiplexers
D
Q
I/O Pin
LAT
CK
EN Q
WR LAT
WR PORT
SRCON0x
RD LAT
SRCON1x
1
RD PORT
0
Sleep
Q
Q
D
CK
Q
Q
D
CK
PBCLK4
Synchronization
Peripheral Input
Legend:
Note:
R
Peripheral Input Buffer
R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure
for any specific port/peripheral combination may be different than it is shown here.
2015-2021 Microchip Technology Inc.
DS60001361J-page 259
PIC32MZ Graphics (DA) Family
12.1
Parallel I/O (PIO) Ports
All port pins have ten registers directly associated with
their operation as digital I/O. The data direction register
(TRISx) determines whether the pin is an input or an
output. If the data direction bit is a ‘1’, then the pin is an
input. All port pins are defined as inputs after a Reset.
Reads from the latch (LATx) read the latch. Writes to
the latch write the latch. Reads from the port (PORTx)
read the port pins, while writes to the port pins write the
latch.
12.1.1
OPEN-DRAIN CONFIGURATION
In addition to the PORTx, LATx, and TRISx registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of outputs higher than VDDIO (e.g., 5V) on any desired 5V-tolerant pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
Refer to the pin name tables (Table 5 and Table 7) for
the available pins and their functionality.
12.1.2
CONFIGURING ANALOG AND
DIGITAL PORT PINS
The ANSELx register controls the operation of the
analog port pins. The port pins that are to function as
analog inputs must have their corresponding ANSEL
and TRIS bits set. In order to use port pins for I/O
functionality with digital modules, such as Timers,
UARTs, etc., the corresponding ANSELx bit must be
cleared.
The ANSELx register has a default value of 0xFFFF;
therefore, all pins that share analog functions are
analog (not digital) by default.
12.1.4
INPUT CHANGE NOTIFICATION
The input change notification function of the I/O ports
allows the PIC32MZ DA devices to generate interrupt
requests to the processor in response to a change-ofstate on selected input pins. This feature can detect
input change-of-states even in Sleep mode, when the
clocks are disabled. Every I/O port pin can be selected
(enabled) for generating an interrupt request on a
change-of-state.
Five control registers are associated with the CN
functionality of each I/O port. The CNENx/CNNEx
registers contain the CN interrupt enable control bits
for each of the input pins. Setting any of these bits
enables a CN interrupt for the corresponding pins.
CNENx enables a mismatch CN interrupt condition
when the EDGEDETECT bit (CNCONx) is not
set. When the EDGEDETECT bit is set, CNNEx
controls the negative edge while CNENx controls the
positive.
The CNSTATx/CNFx registers indicate the status of
change notice based on the setting of the
EDGEDETECT bit. If the EDGEDETECT bit is set to
‘0’, the CNSTATx register indicates whether a change
occurred on the corresponding pin since the last read
of the PORTx bit. If the EDGEDETECT bit is set to ‘1’,
the CNFx register indicates whether a change has
occurred and through the CNNEx/CNENx registers
the edge type of the change that occurred is also
indicated.
Each I/O pin also has a weak pull-up and a weak
pull-down connected to it. The pull-ups act as a
current source or sink source connected to the pin,
and eliminate the need for external resistors when
push-button or keypad devices are connected. The
pull-ups and pull-downs are enabled separately using
the CNPUx and the CNPDx registers, which contain
the control bits for each of the pins. Setting any of
the control bits enables the weak pull-ups and/or
pull-downs for the corresponding pins.
Note:
Pull-ups and pull-downs on change
notification pins should always be
disabled when the port pin is configured as
a digital output.
If the TRIS bit is cleared (output) while the ANSELx bit
is set, the digital output level (VOH or VOL) is converted
by an analog peripheral, such as the ADC module or
Comparator module.
An additional control register (CNCONx) is shown in
Register 12-3.
When the PORT register is read, all pins configured as
analog input channels are read as cleared (a low level).
12.2
Pins configured as digital inputs do not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
12.1.3
I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be an NOP.
DS60001361J-page 260
CLR, SET, and INV Registers
Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
12.3
Slew Rate Registers
12.4.2
AVAILABLE PERIPHERALS
Each I/O pin can be configured for various types of
slew rate control on its associated port. This is controlled by the Slew Rate Control bits in the SRCON1x
and SRCON0x registers that are associated with each
I/O port.
The peripherals managed by the PPS are all digitalonly peripherals. These include general serial
communications (UART, SPI, and CAN), general purpose timer clock inputs, timer-related peripherals (input
capture and output compare), interrupt-on-change
inputs, and reference clocks (input and output).
12.4
In comparison, some digital-only peripheral modules
are never included in the PPS feature. This is because
the peripheral’s function requires special I/O circuitry
on a specific port and cannot be easily connected to
multiple pins. These modules include I2C among others. A similar requirement excludes all modules with
analog inputs, such as the Analog-to-Digital Converter
(ADC).
Peripheral Pin Select (PPS)
A major challenge in general purpose devices is providing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. The challenge is even greater on low pin-count devices. In an
application where more than one peripheral needs to
be assigned to a single pin, inconvenient workarounds
in application code or a complete redesign may be the
only option.
PPS configuration provides an alternative to these
choices by enabling peripheral set selection and their
placement on a wide range of I/O pins. By increasing
the pinout options available on a particular device,
users can better tailor the device to their entire
application, rather than trimming the application to fit
the device.
The PPS configuration feature operates over a fixed
subset of digital I/O pins. Users may independently
map the input and/or output of most digital peripherals
to these I/O pins. PPS is performed in software and
generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral
mapping once it has been established.
12.4.1
AVAILABLE PINS
The number of available pins is dependent on the
particular device and its pin count. Pins that support the
PPS feature include the designation “RPn” in their full
pin designation, where “RP” designates a remappable
peripheral and “n” is the remappable port number.
2015-2021 Microchip Technology Inc.
A key difference between remappable and non-remappable peripherals is that remappable peripherals are
not associated with a default I/O pin. The peripheral
must always be assigned to a specific I/O pin before it
can be used. In contrast, non-remappable peripherals
are always available on a default pin, assuming that the
peripheral is active and not conflicting with another
peripheral.
When a remappable peripheral is active on a given I/O
pin, it takes priority over all other digital I/O and digital
communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
is mapped. Remappable peripherals never take priority
over any analog functions associated with the pin.
12.4.3
CONTROLLING PPS
PPS features are controlled through two sets of SFRs:
one to map peripheral inputs, and one to map outputs.
Because they are separately controlled, a particular
peripheral’s input and output (if the peripheral has both)
can be placed on any selectable function pin without
constraint.
The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on
whether an input or output is being mapped.
DS60001361J-page 261
PIC32MZ Graphics (DA) Family
12.4.4
INPUT MAPPING
The inputs of the PPS options are mapped on the basis
of the peripheral. That is, a control register associated
with a peripheral dictates the pin it will be mapped to.
The [pin name]R registers, where [pin name] refers to the
peripheral pins listed in Table 12-1, are used to configure peripheral input mapping (see Register 12-1). Each
register contains sets of 4 bit fields. Programming these
bit fields with an appropriate value maps the RPn pin
with the corresponding value to that peripheral. For any
given device, the valid range of values for any bit field is
shown in Table 12-1.
For example, Figure 12-2 illustrates the remappable
pin selection for the U1RX input.
FIGURE 12-2:
REMAPPABLE INPUT
EXAMPLE FOR U1RX
U1RXR
0
RPD2
1
RPG8
2
RPF4
U1RX input
to peripheral
n
RPn
Note:
For input only, PPS functionality does not
have priority over TRISx settings. Therefore,
when configuring RPn pin for input, the
corresponding bit in the TRISx register must
also be configured for input (set to ‘1’).
DS60001361J-page 262
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 12-1:
INPUT PIN SELECTION
[pin name]R Value to
RPn Pin Selection
Peripheral Pin
[pin name]R SFR
[pin name]R bits
INT3
INT3R
INT3R
T2CK
T2CKR
T2CKR
0001 = RPG8
0010 = RPF4
0000 = RPD2
T6CK
T6CKR
T6CKR
IC3
IC3R
IC3R
IC7
IC7R
IC7R
U1RX
U1RXR
U1RXR
0110 = RPB10
U2CTS
U2CTSR
U2CTSR
0111 = RPC14
U5RX
U5RXR
U5RXR
U6CTS
U6CTSR
U6CTSR
SDI1
SDI1R
SDI1R
SDI3
SDI3R
SDI3R
SDI5
SDI5R
SDI5R
1101 = RPA14
SS6
SS6R
SS6R
1110 = RPD6
REFCLKI1
REFCLKI1R
REFCLKI1R
1111 = Reserved
INT4
INT4R
INT4R
T5CK
T5CKR
T5CKR
T7CK
T7CKR
T7CKR
IC4
IC4R
IC4R
IC8
IC8R
IC8R
U3RX
U3RXR
U3RXR
U4CTS
U4CTSR
U4CTSR
SDI2
SDI2R
SDI2R
SDI4
SDI4R
SDI4R
C1RX
C1RXR
C1RXR
REFCLKI4
REFCLKI4R
REFCLKI4R
0000 = RPD3
0001 = RPG7
0010 = RPF5
0011 = RPD11
0100 = RPF0
0101 = RPB1
0110 = RPE5
0111 = RPC13
1000 = RPB3
1001 = Reserved
1010 = RPC4
1011 = Reserved
1100 = RPG0
1101 = RPA15
1110 = RPD7
1111 = Reserved
2015-2021 Microchip Technology Inc.
0011 = Reserved
0100 = RPF1
0101 = RPB9
1000 = RPB5
1001 = Reserved
1010 = RPC1
1011 = RPD14
1100 = RPG1
DS60001361J-page 263
PIC32MZ Graphics (DA) Family
TABLE 12-1:
INPUT PIN SELECTION (CONTINUED)
[pin name]R Value to
RPn Pin Selection
Peripheral Pin
[pin name]R SFR
[pin name]R bits
INT2
INT2R
INT2R
0000 = RPD9
T3CK
T3CKR
T3CKR
0001 = Reserved
T8CK
T8CKR
T8CKR
0010 = RPB8
IC2
IC2R
IC2R
IC5
IC5R
IC5R
IC9
IC9R
IC9R
0110 = RPE3
U1CTS
U1CTSR
U1CTSR
0111 = RPB7
U2RX
U2RXR
U2RXR
U5CTS
U5CTSR
U5CTSR
SS1
SS1R
SS1R
SS3
SS3R
SS3R
SS4
SS4R
SS4R
1101 = RPE9
SS5
SS5R
SS5R
1110 = Reserved
C2RX
C2RXR
C2RXR
1111 = Reserved
INT1
INT1R
INT1R
T4CK
T4CKR
T4CKR
T9CK
T9CKR
T9CKR
IC1
IC1R
IC1R
IC6
IC6R
IC6R
U3CTS
U3CTSR
U3CTSR
U4RX
U4RXR
U4RXR
U6RX
U6RXR
U6RXR
SS2
SS2R
SS2R
SDI6
SDI6R
SDI6R
OCFA
OCFAR
OCFAR
REFCLKI3
REFCLKI3R
REFCLKI3R
0000 = Reserved
0001 = RPG9
0010 = Reserved
0011 = RPD0
0100 = Reserved
0101 = RPB6
0110 = RPD5
0111 = RPB2
1000 = RPF3
1001 = Reserved
1010 = Reserved
1011 = RPF2
1100 = RPC2
1101 = RPE8
1110 = Reserved
1111 = Reserved
DS60001361J-page 264
0011 = RPB15
0100 = RPD4
0101 = RPB0
1000 = Reserved
1001 = RPF12
1010 = RPD12
1011 = RPF8
1100 = RPC3
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
12.4.5
OUTPUT MAPPING
12.4.6.1
In contrast to inputs, the outputs of the PPS options
are mapped on the basis of the pin. In this case, a
control register associated with a particular pin
dictates the peripheral output to be mapped. The
RPnR registers (Register 12-2) are used to control
output mapping. Like the [pin name]R registers, each
register contains sets of 4 bit fields. The value of the
bit field corresponds to one of the peripherals, and
that peripheral’s output is mapped to the pin (see
Table 12-2 and Figure 12-3).
A null output is associated with the output register reset
value of ‘0’. This is done to ensure that remappable
outputs remain disconnected from all output pins by
default.
FIGURE 12-3:
EXAMPLE OF
MULTIPLEXING OF
REMAPPABLE OUTPUT
FOR RPF0
RPF0R
Default
U1TX Output
U2RTS Output
0
1
2
RPF0
Output Data
Control Register Lock
Under normal operation, writes to the RPnR and [pin
name]R registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK Configuration bit
(CFGCON). Setting the IOLOCK bit prevents
writes to the control registers and clearing the
IOLOCK bit allows writes.
To set or clear the IOLOCK bit, an unlock sequence
must be executed. Refer to Section 42. “Oscillators
with Enhanced PLL” (DS60001250) in the “PIC32
Family Reference Manual” for details.
12.4.6.2
Configuration Bit Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPnR and [pin name]R registers. The IOL1WAY
Configuration bit (DEVCFG3) blocks the IOLOCK
bit from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure
does not execute, and the PPS control registers cannot
be written to. The only way to clear the bit and reenable peripheral remapping is to perform a device
Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session.
14
REFCLKO1
12.4.6
15
CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC32MZ DA devices include two features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Configuration bit select lock
2015-2021 Microchip Technology Inc.
DS60001361J-page 265
PIC32MZ Graphics (DA) Family
TABLE 12-2:
OUTPUT PIN SELECTION
RPn Port Pin
RPnR SFR
RPnR bits
RPD2
RPD2R
RPD2R
RPG8
RPG8R
RPG8R
RPF4
RPF4R
RPF4R
RPF1
RPF1R
RPF1R
RPB9
RPB9R
RPB9R
RPB10
RPB10R
RPB10R
RPB5
RPB5R
RPB5R
RPC1
RPC1R
RPC1R
RPD14
RPD14R
RPD14R
RPG1
RPG1R
RPG1R
RPA14
RPA14R
RPA14R
RPD6
RPD6R
RPD6R
RPD3
RPD3R
RPD3R
RPG7
RPG7R
RPG7R
RPF5
RPF5R
RPF5R
RPD11
RPD11R
RPD11R
RPF0
RPF0R
RPF0R
RPB1
RPB1R
RPB1R
RPE5
RPE5R
RPE5R
RPB3
RPB3R
RPB3R
RPC4
RPC4R
RPC4R
RPG0
RPG0R
RPG0R
RPA15
RPA15R
RPA15R
RPD7
RPD7R
RPD7R
DS60001361J-page 266
RPnR Value to Peripheral
Selection
0000 = No Connect
0001 = U3TX
0010 = U4RTS
0011 = Reserved
0100 = Reserved
0101 = SDO1
0110 = SDO2
0111 = SDO3
1000 = Reserved
1001 = SDO5
1010 = SS6
1011 = OC3
1100 = OC6
1101 = REFCLKO4
1110 = C2OUT
1111 = C1TX
0000 = No Connect
0001 = U1TX
0010 = U2RTS
0011 = U5TX
0100 = U6RTS
0101 = SDO1
0110 = SDO2
0111 = SDO3
1000 = SDO4
1001 = SDO5
1010 = Reserved
1011 = OC4
1100 = OC7
1101 = Reserved
1110 = Reserved
1111 = REFCLKO1
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 12-2:
OUTPUT PIN SELECTION (CONTINUED)
RPn Port Pin
RPnR SFR
RPnR bits
RPD9
RPD9R
RPD9R
RPB8
RPB8R
RPB8R
RPB15
RPB15R
RPB15R
RPD4
RPD4R
RPD4R
RPB0
RPB0R
RPB0R
RPE3
RPE3R
RPE3R
RPB7
RPB7R
RPB7R
RPF12
RPF12R
RPF12R
RPD12
RPD12R
RPD12R
RPF8
RPF8R
RPF8R
RPC3
RPC3R
RPC3R
RPE9
RPE9R
RPE9R
RPG9
RPG9R
RPG9R
RPD0
RPD0R
RPD0R
RPB6
RPB6R
RPB6R
RPD5
RPD5R
RPD5R
RPB2
RPB2R
RPB2R
RPF3
RPF3R
RPF3R
RPC2
RPC2R
RPC2R
RPE8
RPE8R
RPE8R
RPF2
RPF2R
RPF2R
2015-2021 Microchip Technology Inc.
RPnR Value to Peripheral
Selection
0000 = No Connect
0001 = U3RTS
0010 = U4TX
0011 = Reserved
0100 = U6TX
0101 = SS1
0110 = Reserved
0111 = SS3
1000 = SS4
1001 = SS5
1010 = SDO6
1011 = OC5
1100 = OC8
1101 = Reserved
1110 = C1OUT
1111 = REFCLKO3
0000 = No Connect
0001 = U1RTS
0010 = U2TX
0011 = U5RTS
0100 = U6TX
0101 = Reserved
0110 = SS2
0111 = Reserved
1000 = SDO4
1001 = Reserved
1010 = SDO6
1011 = OC2
1100 = OC1
1101 = OC9
1110 = Reserved
1111 = C2TX
DS60001361J-page 267
I/O Ports Control Registers
Virtual Address
(BF86_#)
Register
Name(1)
TABLE 12-3:
0000
ANSELA
0020
0030
0040
TRISA
PORTA
LATA
ODCA
0050
CNPUA
0060
CNPDA
0070 CNCONA
0080
CNENA
Bit Range
Bits
31/15
30/14
29/13
28/12
27/11
31:16
—
—
—
—
—
15:0
—
—
—
—
—
31:16
—
—
—
—
—
—
—
15:0
2015-2021 Microchip Technology Inc.
00A0
CNNEA
00B0
CNFA
00C0 SRCON0A
00D0 SRCON1A
Legend:
Note 1:
25/9
24/8
23/7
22/6
—
—
—
—
ANSA10
ANSA9
—
—
—
—
—
—
TRISA10
TRISA9
17/1
16/0
—
—
—
0000
—
ANSA1
—
0622
—
—
—
—
0000
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
C6FF
21/5
20/4
19/3
18/2
—
—
—
—
—
ANSA5
—
—
—
—
—
—
—
TRISA7
TRISA6
TRISA5
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RA15
RA14
—
—
—
RA10
RA9
—
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATA15
LATA14
—
—
—
LATA10
LATA9
—
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
ODCA10
ODCA9
—
ODCA7
ODCA6
ODCA5
ODCA4
ODCA3
ODCA2
ODCA1
ODCA0
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0 CNPUA15 CNPUA14
—
—
—
31:16
15:0
31:16
ODCA15 ODCA14
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
—
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
CNIEA10
CNIEA9
—
CNIEA7
CNIEA6
CNIEA5
CNIEA4
CNIEA3
CNIEA2
CNIEA1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CN
STATA10
CN
STATA9
—
CN
STATA7
CN
STATA6
CN
STATA5
CN
STATA4
CN
STATA3
CN
STATA2
CN
STATA1
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
CN
CN
STATA15 STATA14
—
—
—
CNPDA10 CNPDA9
—
CNPUA7 CNPUA6 CNPUA5 CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000
—
CNIEA15 CNIEA14
—
—
—
15:0
—
CNPUA10 CNPUA9
—
31:16
—
—
15:0 CNPDA15 CNPDA14
31:16
0090 CNSTATA
TRISA15 TRISA14
26/10
All
Resets
0010
PORTA REGISTER MAP
—
—
—
—
—
—
—
—
—
0000
CNPDA7 CNPDA6 CNPDA5 CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000
CNIEA0 0000
—
0000
CN
0000
STATA0
—
—
—
15:0 CNNEA15 CNNEA14
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNFA15
CNFA14
—
—
—
CNFA10
CNFA9
—
CNFA7
CNFA76
CNFA5
CNFA4
CNFA3
CNFA2
CNFA1
CNFA0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
SR1A15
SR1A14
—
—
—
SR1A10
SR1A9
—
SR1A7
SR1A6
SR1A5
SR1A4
SR1A3
SR1A2
SR1A1
SR1A0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
SR0A15
SR0A14
—
—
—
SR0A10
SR0A9
—
SR0A7
SR0A6
SR0A5
SR0A4
SR0A3
SR0A2
SR0A1
SR0A0
0000
CNNEA10 CNNEA9
—
—
0000
CNNEA7 CNNEA6 CNNEA5 CNNEA4 CNNEA3 CNNEA2 CNNEA1 CNNEA0 0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 268
12.5
0100 ANSELB
0110
0120
PORTB REGISTER MAP
TRISB
PORTB
0130
LATB
0140
ODCB
CNPUB
0160
CNPDB
0180
CNENB
0190 CNSTATB
01A0 CNNEB
01B0
CNFB
01C0 SRCON0B
01D0 SRCON1B
DS60001361J-page 269
Legend:
Note 1:
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
30/14
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ANSB15
ANSB14
ANSB13
ANSB12
ANSB11
ANSB10
ANSB9
ANSB8
ANSB7
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
FFBF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
TRISB15
TRISB14
TRISB13
TRISB12
TRISB11
TRISB10
TRISB9
TRISB8
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
FFFF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATB15
LATB14
LATB13
LATB12
LATB11
LATB10
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCB15
ODCB14
ODCB13
ODCB12
ODCB11
ODCB10
ODCB9
ODCB8
ODCB7
ODCB6
ODCB5
ODCB4
ODCB3
ODCB2
ODCB1
ODCB0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0 CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0 CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5
31:16
0170 CNCONB
31/15
—
—
—
CNPUB4
—
CNPDB4
CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000
—
—
—
—
0000
CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
—
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNIEB15
CNIEB14
CNIEB13
CNIEB12
CNIEB11
CNIEB10
CNIEB9
CNIEB8
CNIEB7
CNIEB6
CNIEB5
CNIEB4
CNIEB3
CNIEB2
CNIEB1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CN
STATB15
CN
STATB14
CN
STATB13
CN
STATB12
CN
STATB11
CN
STATB10
CN
STATB9
CN
STATB8
CN
STATB7
CN
STATB6
CN
STATB5
CN
STATB4
CN
STATB3
CN
STATB2
CN
STATB1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0 CNNEB15 CNNEB14 CNNEB13 CNNEB12 CNNEB11 CNNEB10 CNNEB9 CNNEB8 CNNEB7 CNNEB6 CNNEB5
—
CNNEB4
CNIEB0 0000
—
0000
CN
0000
STATB0
—
0000
CNNEB3 CNNEB2 CNNEB1 CNNEB0 0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNFB15
CNFB14
CNFB13
CNFB12
CNFB11
CNFB10
CNFB9
CNFB8
CNFB7
CNFB76
CNFB5
CNFB4
CNFB3
CNFB2
CNFB1
CNFB0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
SR1B15
SR1B14
SR1B13
SR1B12
SR1B11
SR1B10
SR1B9
SR1B8
SR1B7
SR1B6
SR1B5
SR1B4
SR1B3
SR1B2
SR1B1
SR1B0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
SR0B15
SR0B14
SR0B13
SR0B12
SR0B11
SR0B10
SR0B9
SR0B8
SR0B7
SR0B6
SR0B5
SR0B4
SR0B3
SR0B2
SR0B1
SR0B0
0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
0150
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF86_#)
2015-2021 Microchip Technology Inc.
TABLE 12-4:
0230
PORTC
LATC
0240
ODCC
0250
CNPUC
0260
CNPDC
0270 CNCONC
0280
CNENC
0290 CNSTATC
02A0
02B0
CNNEC
CNFC
2015-2021 Microchip Technology Inc.
02C0 SRCON0C
02D0 SRCON1C
Legend:
Note 1:
17/1
16/0
All
Resets
0220
TRISC
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
0200 ANSELC
0210
PORTC REGISTER MAP
—
—
—
0000
ANSC2
ANSC1
—
001E
—
—
—
0000
TRISC3
TRISC2
TRISC1
—
901E
—
—
—
—
—
0000
—
RC4
RC3
RC2
RC1
—
xxxx
—
—
—
—
—
—
—
0000
—
—
—
LATC4
LATC3
LATC2
LATC1
—
xxxx
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
ODCC4
ODCC3
ODCC2
ODCC1
—
0000
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
CNPUC4
CNPUC3
CNPUC2
CNPUC1
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CNPDC13
CNPDC12
—
—
—
—
—
—
—
CNPDC4
CNPDC3
CNPDC2
CNPDC1
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
ANSC4
ANSC3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
TRISC15
—
—
TRISC12
—
—
—
—
—
—
—
TRISC4
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
RC15
RC14
RC13
RC12
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
15:0
LATC15
LATC14
LATC13
LATC12
—
—
—
—
31:16
—
—
—
—
—
—
—
15:0
ODCC15
ODCC14
ODCC13
ODCC12
—
—
31:16
—
—
—
—
—
15:0
CNPUC15
CNPUC14
CNPUC13
CNPUC12
31:16
—
—
—
15:0
CNPDC15
CNPDC14
31:16
—
15:0
ON
18/2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNIEC15
CNIEC14
CNIEC13
CNIEC12
—
—
—
—
—
—
—
CNIEC4
CNIEC3
CNIEC2
CNIEC1
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0 CNSTATC15 CNSTATC14 CNSTATC13 CNSTATC12
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNNEC15
CNNEC14
CNNEC13
CNNEC12
—
—
—
—
—
—
—
CNNEC4
CNNEC3
CNNEC2
CNNEC1
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNFC15
CNFC14
CNFC13
CNFC12
—
—
—
—
—
—
—
CNFC4
CNFC3
CNFC2
CNFC1
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
SR1C15
SR1C14
SR1C13
SR1C12
—
—
—
—
—
—
—
SR1C4
SR1C3
SR1C2
SR1C1
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
SR0C15
SR0C14
SR0C13
SR0C12
—
—
—
—
—
—
—
SR0C4
SR0C3
SR0C2
SR0C1
—
0000
CNSTATC4 CNSTATC3 CNSTATC2 CNSTATC1
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 270
TABLE 12-5:
0300 ANSELD
0310
TRISD
0320
PORTD
0330
LATD
ODCD
0350
CNPUD
0360
CNPDD
0370 CNCOND
CNEND
0390 CNSTATD
03A0
CNNED
03B0
CNFD
03C0 SRCON0D
03D0 SRCON1D
DS60001361J-page 271
Legend:
Note 1:
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
Bit Range
31/15
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ANSD15
ANSD14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
TRISD15
TRISD14
TRISD13
TRISD12
TRISD11
TRISD10
TRISD9
—
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0 FEFF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RD15
RD14
RD13
RD12
RD11
RD10
RD9
—
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATD15
LATD14
LATD13
LATD12
LATD11
LATD10
LATD9
—
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCD15
ODCD14
ODCD13
ODCD12
ODCD11
ODCD10
ODCD9
—
ODCD7
ODCD6
ODCD5
ODCD4
ODCD3
ODCD2
ODCD1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0 CNPUD15 CNPUD14 CNPUD13 CNPUD12 CNPUD11 CNPUD10 CNPUD9
—
31:16
—
—
—
—
—
—
—
—
15:0 CNPDD15 CNPDD14 CNPDD13 CNPDD12 CNPDD11 CNPDD10 CNPDD9
—
31:16
—
—
—
ODCD0 0000
—
0000
CNPUD7 CNPUD6 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 0000
—
—
—
—
—
—
—
—
0000
CNPDD7 CNPDD6 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
—
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNIED15
CNIED14
CNIED11
CNIED10
CNIED9
—
CNIED7
CNIED6
CNIED5
CNIED4
CNIED3
CNIED2
CNIED1
—
—
31:16
—
—
15:0
CNS
TATD15
CN
STATD14
31:16
—
—
CNIED13 CNIED12
—
—
CN
CN
CN
CN
STATD13 STATD12 STATD11 STATD10
—
—
—
—
—
—
—
—
—
—
—
—
—
CN
STATD9
—
CN
STATD7
CN
STATD6
CN
STATD5
CN
STATD4
CN
STATD3
CN
STATD2
CN
STATD1
—
—
—
—
—
—
—
—
—
CNIED0 0000
—
0000
CN
0000
STATD0
—
0000
15:0 CNNED15 CNNED14 CNNED13 CNNED12 CNNED11 CNNED10 CNNED9
—
CNNED7 CNNED6 CNNED5 CNNED4 CNNED3 CNNED2 CNNED1 CNNED0 0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNFD15
CNFD14
CNFD13
CNFD12
CNFD11
CNFD10
CNFD9
—
CNFD7
CNFD6
CNFD5
CNFD4
CNFD3
CNFD2
CNFD1
CNFD0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
SR1D15
SR1D14
SR1D13
SR1D12
SR1D11
SR1D10
SR1D9
—
SR1D7
SR1D6
SR1D5
SR1D4
SR1D3
SR1D2
SR1D1
SR1D0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
SR0D15
SR0D14
SR0D13
SR0D12
SR0D11
SR0D10
SR0D9
—
SR0D7
SR0D6
SR0D5
SR0D4
SR0D3
SR0D2
SR0D1
SR0D0
0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
0340
0380
PORTD REGISTER MAP
Bits
Register
Name(1)
Virtual Address
(BF86_#)
2015-2021 Microchip Technology Inc.
TABLE 12-6:
Virtual Address
(BF86_#)
Register
Name(1)
0400
ANSELE
0410
TRISE
0430
PORTE
LATE
0440
ODCE
0450
CNPUE
0460
CNPDE
0470 CNCONE
0480
CNENE
0490 CNSTATE
2015-2021 Microchip Technology Inc.
04A0
CNNEE
04B0
CNFE
04C0 SRCON0E
04D0 SRCON1E
Legend:
Note 1:
Bit Range
Bits
17/1
16/0
All
Resets
0420
PORTE REGISTER MAP
—
—
—
0000
—
ANSE1
—
03D2
—
—
—
—
0000
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
03FF
—
—
—
—
—
—
0000
RE6
RE5
RE4
RE3
RE2
RE1
RE0
xxxx
—
—
—
—
—
—
—
—
0000
LATE8
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
xxxx
—
—
—
—
—
—
—
—
—
—
0000
—
ODCE9
ODCE8
ODCE7
ODCE6
ODCE5
ODCE4
ODCE3
ODCE2
ODCE1
ODCE0
0000
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
CNPUE6
CNPUE5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIEE9
CNIEE8
CNIEE7
CNIEE6
CNIEE5
CNIEE4
CNIEE3
CNIEE2
CNIEE1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CN
STATE9
CN
STATE8
CN
STATE7
CN
STATE6
CN
STATE5
CN
STATE4
CN
STATE3
CN
STATE2
CN
STATE1
—
—
—
—
—
—
—
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
ANSE9
ANSE8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
TRISE9
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
31:16
—
—
—
—
15:0
—
—
—
31:16
—
—
15:0
—
31:16
23/7
22/6
21/5
20/4
19/3
18/2
—
—
ANSE7
ANSE6
—
—
—
—
ANSE4
—
—
—
—
—
TRISE8
TRISE7
TRISE6
TRISE5
—
—
—
—
—
RE9
RE8
RE7
—
—
—
—
—
—
—
LATE9
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
31:16
—
—
15:0
—
—
31:16
—
15:0
ON
31:16
15:0
31:16
CNPUE9 CNPUE8 CNPUE7
—
—
—
CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0 0000
—
—
CNPDE6
CNPDE5
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
0000
CNPDE9 CNPDE8 CNPDE7
—
—
—
—
—
0000
CNPDE4 CNPDE3 CNPDE2 CNPDE1 CNPDE0 0000
CNIEE0 0000
—
0000
CN
0000
STATE0
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
CNFE9
CNFE8
CNFE7
CNFE6
CNFE5
CNFE4
CNFE3
CNFE2
CNFE1
CNFE0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
SR1E9
SR1E8
SR1E7
SR1E6
SR1E5
SR1E4
SR1E3
SR1E2
SR1E1
SR1E0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
SR0E9
SR0E8
SR0E7
SR0E6
SR0E5
SR0E4
SR0E3
SR0E2
SR0E1
SR0E0
0000
CNNEE9 CNNEE8 CNNEE7
—
—
CNNEE6
CNNEE5
—
0000
CNNEE4 CNNEE3 CNNEE2 CNNEE1 CNNEE0 0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 272
TABLE 12-7:
TRISF
0520
PORTF
0530
LATF
0540
ODCF
CNPUF
0560
CNPDF
0570 CNCONF
0580
CNENF
0590 CNSTATF
05A0
CNNEF
05B0
CNFF
05C0 SRCON0F
05D0 SRCON1F
DS60001361J-page 273
Legend:
Note 1:
Bit Range
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
ANSF13
ANSF12
—
—
—
—
—
—
—
—
—
—
—
—
3000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
TRISF13
TRISF12
—
—
—
TRISF8
—
—
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0
313F
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
RF13
RF12
—
—
—
RF8
—
—
RF5
RF4
RF3
RF2
RF1
RF0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
LATF13
LATF12
—
—
—
LATF8
—
—
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
ODCF13
ODCF12
—
—
—
ODCF8
—
—
ODCF5
ODCF4
ODCF3
ODCF2
ODCF1
ODCF0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
CNPUF8
—
—
CNPUF5
CNPUF4
CNPUF3
CNPUF2
CNPUF1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
CNPDF8
—
—
CNPDF5
CNPDF4
CNPDF3
CNPDF2
CNPDF1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31/15
30/14
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
31:16
29/13
CNPUF13 CNPUF12
—
—
CNPDF13 CNPDF12
—
CNPUF0 0000
—
0000
CNPDF0 0000
15:0
ON
—
—
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
CNIEF13
CNIEF12
—
—
—
CNIEF8
—
—
CNIEF5
CNIEF4
CNIEF3
CNIEF2
CNIEF1
CNIEF0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
CN
STATF13
CN
STATF12
—
—
—
CN
STATF8
—
—
CN
STATF5
CN
STATF4
CN
STATF3
CN
STATF2
CN
STATF1
CN
STATF0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
CNNEF8
—
—
CNNEF5
CNNEF4
CNNEF3
CNNEF2
CNNEF1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
CNFF13
CNFF12
—
—
—
CNFF8
—
—
CNFF5
CNFF4
CNFF3
CNFF2
CNFF1
CNFF0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
SR1F13
SR1F12
—
—
—
SR1F8
—
—
SR1F5
SR1F4
SR1F3
SR1F2
SR1F1
SR1F0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
SR0F13
SR0F12
—
—
—
SR0F8
—
—
SR0F5
SR0F4
SR0F3
SR0F2
SR0F1
SR0F0
0000
CNNEF13 CNNEF12
CNNEF0 0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
0550
28/12
All
Resets
0500 ANSELF
0510
PORTF REGISTER MAP
Bits
Register
Name(1)
Virtual Address
(BF86_#)
2015-2021 Microchip Technology Inc.
TABLE 12-8:
0630
PORTG
LATG
0640
ODCG
0650
CNPUG
0660
CNPDG
0670 CNCONG
0680
CNENG
0690 CNSTATG
2015-2021 Microchip Technology Inc.
06A0
CNNEG
06B0
CNFG
06C0 SRCON0G
06D0 SRCON1G
Legend:
Note 1:
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All
Resets
0620
TRISG
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
0600 ANSELG
0610
PORTG REGISTER MAP
—
—
—
—
—
—
—
—
0000
ANSG7
ANSG6
—
—
—
—
—
—
83C0
—
—
—
—
—
—
—
—
0000
TRISG8
TRISG7
TRISG6
—
—
—
—
TRISG1
TRISG0
F3C3
—
—
—
—
—
—
—
—
—
—
0000
—
RG9
RG8
RG7
RG6
—
—
—
—
RG1
RG0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
0000
LATG12
—
—
LATG9
LATG8
LATG7
LATG6
—
—
—
—
LATG1
LATG0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
ODCG14
ODCG13
ODCG12
—
—
ODCG9
ODCG8
ODCG7
ODCG6
—
—
—
—
ODCG1
ODCG0
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0 CNPUG15 CNPUG14 CNPUG13 CNPUG12
—
—
CNPUG9
CNPUG8
CNPUG7
CNPUG6
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
CNPDG9
CNPDG8
CNPDG7
CNPDG6
—
—
—
—
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
—
—
—
—
—
—
—
15:0
ANSG15
—
—
—
—
—
ANSG9
ANSG8
31:16
—
—
—
—
—
—
—
—
15:0
TRISG15
—
—
TRISG9
31:16
—
—
—
—
—
—
15:0
RG15
RG14
RG13
RG12
—
31:16
—
—
—
—
15:0
LATG15
LATG14
LATG13
31:16
—
—
15:0
ODCG15
31:16
—
—
TRISG14 TRISG13 TRISG12
—
—
—
15:0 CNPDG15 CNPDG14 CNPDG13 CNPDG12
25/9
24/8
23/7
CNPUG1 CNPUG0 0000
—
—
0000
CNPDG1 CNPDG0 0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
—
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
CNIEG9
CNIEG8
CNIEG7
CNIEG6
—
—
—
—
CNIEG1
CNIEG0
0000
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
CN
STATG9
CN
STATG8
CN
STATG7
CN
STATG6
—
—
—
—
CN
STATG1
—
—
—
—
—
—
—
—
—
—
15:0 CNNEG15 CNNEG14 CNNEG13 CNNEG12
—
—
CNNEG9
CNNEG8
CNNEG7
CNNEG6
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNFG15
CNFG14
CNFG13
CNFG12
—
—
CNFG9
CNFG8
CNFG7
CNFG6
—
—
—
—
CNFG1
CNFG0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
SR1G15
SR1G14
SR1G13
SR1G12
—
—
SR1G9
SR1G9
SR1G7
SR1G6
—
—
—
—
SR1G1
SR1G0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
SR0G15
SR0G14
SR0G13
SR0G12
—
—
SR0G9
SR0G8
SR0G7
SR0G6
—
—
—
—
SR0G1
SR0G0
0000
31:16
—
15:0
CNIEG15
31:16
—
15:0
CN
STATG15
31:16
—
CNIEG14 CNIEG13 CNIEG12
—
—
—
CN
CN
CN
STATG14 STATG13 STATG12
—
—
—
—
CN
0000
STATG0
—
0000
CNNEG1 CNNEG0 0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 274
TABLE 12-9:
0710
TRISH
0720
PORTH
LATH
0740
ODCH
0750
CNPUH
0760
CNPDH
30/14
29/13
28/12
31:16
—
—
—
15:0
—
—
—
31:16
—
—
15:0
TRISH15
TRISH14
0780
CNENH
0790 CNSTATH
07A0
CNNEH
07B0
CNFH
07C0 SRCON0H
07D0 SRCON1H
DS60001361J-page 275
Legend:
Note 1:
26/10
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
ANSH11
—
—
—
—
—
—
—
ANSH7
—
—
—
—
—
—
—
—
—
—
—
TRISH13
TRISH12
TRISH11
TRISH10
TRISH9
TRISH8
TRISH7
TRISH6
TRISH5
19/3
18/2
17/1
16/0
—
—
—
—
—
0000
ANSH4
ANSH3
—
—
—
0898
—
—
—
—
—
0000
TRISH4
TRISH3
TRISH2
TRISH1
20/4
TRISH0 FFFF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RH15
RH14
RH13
RH12
RH11
RH10
RH9
RH8
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATH15
LATH14
LATH13
LATH12
LATH11
LATH10
LATH9
LATH8
LATH7
LATH6
LATH5
LATH4
LATH3
LATH2
LATH1
LATH0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCH15
ODCH14
ODCH13
ODCH12
ODCH11
ODCH10
ODCH9
ODCH8
ODCH7
ODCH6
ODCH5
ODCH4
ODCH3
ODCH2
ODCH1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0 CNPUH15 CNPUH14 CNPUH13 CNPUH12 CNPUH11 CNPUH10 CNPUH9
31:16
—
—
—
—
—
—
—
15:0 CNPDH15 CNPDH14 CNPDH13 CNPDH12 CNPDH11 CNPDH10 CNPDH9
31:16
0770 CNCONH
27/11
—
—
—
—
—
CNPUH8
CNPUH7
—
—
CNPDH8
CNPDH7
ODCH0 0000
—
0000
CNPUH6 CNPUH5 CNPUH4 CNPUH3 CNPUH2 CNPUH1 CNPUH0 0000
—
—
—
—
—
—
—
0000
CNPDH6 CNPDH5 CNPDH4 CNPDH3 CNPDH2 CNPDH1 CNPDH0 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
—
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNIEH15
CNIEH14
CNIEH13
CNIEH12
CNIEH11
CNIEH10
CNIEH9
CNIEH8
CNIEH7
CNIEH6
CNIEH5
CNIEH4
CNIEH3
CNIEH2
CNIEH1
31:16
—
CN
15:0
STATH15
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CN
STATH14
CN
STATH13
CN
STATH12
CN
STATH11
CN
STATH10
CN
STATH9
CN
STATH8
CN
STATH7
CN
STATH6
CN
STATH5
CN
STATH4
CN
STATH3
CN
STATH2
CN
STATH1
—
—
—
—
—
—
—
—
—
—
—
—
15:0 CNNEH15 CNNEH14 CNNEH13 CNNEH12 CNNEH11 CNNEH10 CNNEH9
—
—
CNNEH8
CNNEH7
CNIEH0 0000
—
0000
CN
0000
STATH0
—
0000
CNNEH6 CNNEH5 CNNEH4 CNNEH3 CNNEH2 CNNEH1 CNNEH0 0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CNFH15
CNFH14
CNFH13
CNFH12
CNFH11
CNFH10
CNFH9
CNFH8
CNFH7
CNFH6
CNFH5
CNFH4
CNFH3
CNFH2
CNFH1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
SR1H15
SR1H14
SR1H13
SR1H12
SR1H11
SR1H10
SR1H9
SR1H8
SR1H7
SR1H6
SR1H5
SR1H4
SR1H3
SR1H2
SR1H1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
SR0H15
SR0H14
SR0H13
SR0H12
SR0H11
SR0H10
SR0H9
SR0H8
SR0H7
SR0H6
SR0H5
SR0H4
SR0H3
SR0H2
SR0H1
—
0000
CNFH0 0000
—
0000
SR1H0 0000
—
0000
SR0H0 0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
0730
31/15
All
Resets
0700 ANSELH
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF86_#)
2015-2021 Microchip Technology Inc.
TABLE 12-10: PORTH REGISTER MAP
0800 ANSELJ
0810
TRISJ
0820
PORTJ
0830
LATJ
0840
ODCJ
0850
CNPUJ
0860
CNPDJ
0880
CNENJ
0890 CNSTATJ
08A0 CNNEJ
2015-2021 Microchip Technology Inc.
08B0
CNFJ
08C0 SRCON0J
08D0 SRCON1J
Legend:
Note 1:
17/1
16/0
—
—
—
—
0000
—
ANSJ2
—
—
0004
—
—
—
—
—
0000
TRISJ4
TRISJ3
TRISJ2
TRISJ1
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
TRISJ15
TRISJ14
TRISJ13
TRISJ12
TRISJ11
TRISJ10
TRISJ9
TRISJ8
TRISJ7
TRISJ6
TRISJ5
TRISJ0 FFFF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RJ15
RJ14
RJ13
RJ12
RJ11
RJ10
RJ9
RJ8
RJ7
RJ6
RJ5
RJ4
RJ3
RJ2
RJ1
RJ0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATJ15
LATJ14
LATJ13
LATJ12
LATJ11
LATJ10
LATJ9
LATJ8
LATJ7
LATJ6
LATJ5
LATJ4
LATJ3
LATJ2
LATJ1
LATJ0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCJ15
ODCJ14
ODCJ13
ODCJ12
ODCJ11
ODCJ10
ODCJ9
ODCJ18
ODCJ7
ODCJ6
ODCJ5
ODCJ4
ODCJ3
ODCJ2
ODCJ1
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0 CNPUJ15 CNPUJ14 CNPUJ13 CNPUJ12 CNPUJ11 CNPUJ10
31:16
—
—
—
—
—
—
15:0 CNPDJ15 CNPDJ14 CNPDJ13 CNPDJ12 CNPDJ11 CNPDJ10
31:16
0870 CNCONJ
18/2
All
Resets
Bit Range
Register
Name(1)
Virtual Address
(BF86_#)
Bits
15:0
—
ON
—
—
—
—
—
—
—
—
CNPUJ9
CNPUJ8
CNPUJ7
CNPUJ6
—
—
—
—
CNPDJ9
CNPDJ8
CNPDJ7
CNPDJ6
ODCJ0 0000
—
0000
CNPUJ5 CNPUJ4 CNPUJ3 CNPUJ2 CNPUJ1 CNPUJ0 0000
—
—
—
—
—
—
0000
CNPDJ5 CNPDJ4 CNPDJ3 CNPDJ2 CNPDJ1 CNPDJ0 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CNIEJ15
CNIEJ14
CNIEJ13
CNIEJ12
CNIEJ11
CNIEJ10
CNIEJ9
CNIEJ8
CNIEJ7
CNIEJ6
CNIEJ5
CNIEJ4
CNIEJ3
CNIEJ2
CNIEJ1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CN
STATJ15
CN
STATJ14
CN
STATJ13
CN
STATJ12
CN
STATJ11
CN
STATJ10
CN
STATJ9
CN
STATJ8
CN
STATJ7
CN
STATJ6
CN
STATJ5
CN
STATJ4
CN
STATJ3
CN
STATJ2
CN
STATJ1
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0 CNNEJ15 CNNEJ14 CNNEJ13 CNNEJ12 CNNEJ11 CNNEJ10
—
—
—
—
CNNEJ9
CNNEJ8
CNNEJ7
CNNEJ6
CNIEJ0 0000
—
0000
CN
0000
STATJ0
—
0000
CNNEJ5 CNNEJ4 CNNEJ3 CNNEJ2 CNNEJ1 CNNEJ0 0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CNFJ15
CNFJ14
CNFJ13
CNFJ12
CNFJ11
CNFJ10
CNFJ9
CNFJ8
CNFJ7
CNFJ6
CNFJ5
CNFJ4
CNFJ3
CNFJ2
CNFJ1
CNFJ0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
SR1J15
SR1J14
SR1J13
SR1J12
SR1J11
SR1J10
SR1J9
SR1J8
SR1J7
SR1J6
SR1J5
SR1J4
SR1J3
SR1J2
SR1J1
SR1J0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
SR0J15
SR0J14
SR0J13
SR0J12
SR0J11
SR0J10
SR0J9
SR0J8
SR0J7
SR0J6
SR0J5
SR0J4
SR0J3
SR0J2
SR0J1
SR0J0
0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 276
TABLE 12-11: PORTJ REGISTER MAP
0910
TRISK
0920
PORTK
LATK
0940
ODCK
0950
CNPUK
0960
CNPDK
0970 CNCONK
0980
CNENK
0990 CNSTATK
09A0 CNNEK
09B0
CNFK
09C0 SRCON0K
09D0 SRCON1K
DS60001361J-page 277
Legend:
Note 1:
16/0
—
—
—
0000
ANSK2
ANSK1
—
0006
—
—
—
0000
TRISK2
TRISK1
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
TRISK7
TRISK6
TRISK5
TRISK4
TRISK3
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
RK7
RK6
RK5
RK4
RK3
RK2
RK1
RK0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
LATK7
LATK6
LATK5
LATK4
LATK3
LATK2
LATK1
LATK0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
ODCK7
ODCK6
ODCK5
ODCK4
ODCK3
ODCK2
ODCK1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
CNPUK7
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
CNPDK7
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
TRISK0 00E9
ODCK0 0000
—
0000
CNPUK6 CNPUK5 CNPUK4 CNPUK3 CNPUK2 CNPUK1 CNPUK0 0000
—
—
—
—
—
—
—
0000
CNPDK6 CNPDK5 CNPDK4 CNPDK3 CNPDK2 CNPDK1 CNPDK0 0000
15:0
ON
—
—
—
EDGE
DETECT
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
CNIEK7
CNIEK6
CNIEK5
CNIEK4
CNIEK3
CNIEK2
CNIEK1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CN
STATK7
CN
STATK6
CN
STATK5
CN
STATK4
CN
STATK3
CN
STATK2
CN
STATK1
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
CNNEK7
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
CNFK7
CNFK6
CNFK5
CNFK4
CNFK3
CNFK2
CNFK1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
SR1K7
SR1K6
SR1K5
SR1K4
SR1K3
SR1K2
SR1K1
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
SR0K7
SR0K6
SR0K5
SR0K4
SR0K3
SR0K2
SR0K1
CNIEK0 0000
—
0000
CN
0000
STATK0
—
0000
CNNEK6 CNNEK5 CNNEK4 CNNEK3 CNNEK2 CNNEK1 CNNEK0 0000
—
0000
CNFK0 0000
—
0000
SR1K0 0000
—
0000
SR0K0 0000
x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
0930
17/1
All
Resets
0900 ANSELK
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF86_#)
2015-2021 Microchip Technology Inc.
TABLE 12-12: PORTK REGISTER MAP
1408
140C
1410
1418
141C
1420
1424
1428
142C
2015-2021 Microchip Technology Inc.
1430
1434
1438
143C
1440
Legend:
INT1R
INT2R
INT3R
INT4R
T2CKR
T3CKR
T4CKR
T5CKR
T6CKR
T7CKR
T8CKR
T9CKR
IC1R
IC2R
IC3R
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
1404
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
INT1R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
INT2R
—
0000
INT3R
—
0000
INT4R
—
0000
T2CKR
—
0000
T3CKR
—
0000
T4CKR
—
0000
T5CKR
—
0000
T6CKR
—
0000
T7CKR
—
0000
T8CKR
—
0000
T9CKR
—
0000
IC1R
—
0000
IC2R
—
IC3R
0000
0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 278
TABLE 12-13: PERIPHERAL PIN SELECT INPUT REGISTER MAP
1444
1448
144C
1450
1458
1460
1468
146C
1470
1474
1478
147C
DS60001361J-page 279
1480
1484
Legend:
IC4R
IC5R
IC6R
IC7R
IC8R
IC9R
OCFAR
U1RXR
U1CTSR
U2RXR
U2CTSR
U3RXR
U3CTSR
U4RXR
U4CTSR
All Resets
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
IC4R
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IC5R
—
0000
IC6R
—
0000
IC7R
—
0000
IC8R
—
0000
IC9R
—
0000
OCFAR
—
—
—
—
—
0000
U1RXR
—
0000
U1CTSR
—
—
—
—
—
0000
U2RXR
—
0000
U2CTSR
—
—
—
—
—
0000
U3RXR
—
0000
U3CTSR
—
—
—
—
—
0000
U4RXR
—
U4CTSR
0000
0000
PIC32MZ Graphics (DA) Family
1454
Bits
Register
Name
Virtual Address
(BF80_#)
2015-2021 Microchip Technology Inc.
TABLE 12-13: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
148C
1490
1494
149C
14A0
14A8
14AC
14B4
14B8
2015-2021 Microchip Technology Inc.
14C0
14C4
14CC
14D0
14D8
Legend:
U5RXR
U5CTSR
U6RXR
U6CTSR
SDI1R
SS1R
SDI2R
SS2R
SDI3R
SS3R
SDI4R
SS4R
SDI5R
SS5R
SDI6R
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
1488
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
U5RXR
—
—
—
0000
U5CTSR
—
—
—
—
—
0000
U6RXR
—
0000
U6CTSR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
SDI1R
—
0000
SS1R
—
0000
SDI2R
—
0000
SS2R
—
0000
SDI3R
—
0000
SS3R
—
0000
SDI4R
—
0000
SS4R
—
0000
SDI5R
—
0000
SS5R
—
SDI6R
0000
0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 280
TABLE 12-13: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
SS6R
C1RXR(1)
14E0
C2RXR(1)
14E4
14E8
14F4
REFCLKI3R
REFCLKI4R
Legend:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
0000
—
0000
—
0000
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SS6R
—
—
—
—
—
—
—
0000
C1RXR
—
0000
C2RXR
—
0000
REFCLKI1R
—
—
—
0000
REFCLKI3R
—
—
—
REFCLKI4R
0000
0000
DS60001361J-page 281
PIC32MZ Graphics (DA) Family
14F0
REFCLKI1R
All Resets
14DC
Bit Range
Register
Name
Bits
Virtual Address
(BF80_#)
2015-2021 Microchip Technology Inc.
TABLE 12-13: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
2015-2021 Microchip Technology Inc.
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
153C RPA15R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1540 RPB0R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1544 RPB1R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1548 RPB2R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
154C RPB3R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1554 RPB5R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1558 RPB6R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
155C RPB7R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1560 RPB8R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1564 RPB9R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1568 RPB10R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
157C RPB15R
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
1584 RPC1R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1588 RPC2R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
158C RPC3R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
15B4 RPC13R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
15B8 RPC14R
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15C0 RPD0R
15:0
—
—
—
—
—
—
—
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1538
RPA14R
23/7
22/6
21/5
20/4
19/3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
18/2
17/1
—
—
RPA14R
—
—
RPA15R
—
—
RPB0R
—
—
RPB1R
—
—
RPB2R
—
—
RPB3R
—
—
RPB5R
—
—
RPB6R
—
—
RPB7R
—
—
RPB8R
—
—
RPB9R
—
—
RPB10R
—
—
RPB15R
—
—
RPC1R
—
—
RPC2R
—
—
RPC3R
—
—
RPC13R
—
—
RPC14R
—
—
RPD0R
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 282
TABLE 12-14: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
RPD2R
22/6
21/5
20/4
19/3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
18/2
17/1
—
—
RPD2R
—
—
RPD3R
—
—
RPD4R
—
—
RPD5R
—
—
RPD6R
—
—
RPD7R
—
—
RPD9R
—
—
RPD11R
—
—
RPD12R
—
—
RPD14R
—
—
RPE3R
—
—
RPE5R
—
—
RPE8R
—
—
RPE9R
—
—
RPF0R
—
—
RPF1R
—
—
RPF2R
—
—
RPF3R
—
—
RPF4R
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 283
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
15CC RPD3R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
15D0 RPD4R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
15D4 RPD5R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
15D8 RPD6R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
15DC RPD7R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
15E4 RPD9R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
15EC RPD11R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
15F0 RPD12R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
15F8 RPD14R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
160C RPE3R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1614 RPE5R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1620 RPE8R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1624 RPE9R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1640 RPF0R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1644 RPF1R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1648 RPF2R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
164C RPF3R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1650 RPF4R
—
—
—
—
—
—
—
—
15:0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
15C8
23/7
All Resets
Bit Range
Bits
Register
Name
Virtual Address
(BF80_#)
2015-2021 Microchip Technology Inc.
TABLE 12-14: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1660 RPF8R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1670 RPF12R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
1680 RPG0R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
1684 RPG1R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
169C RPG7R
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
16A0 RPG8R
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
16A4 RPG9R
—
—
—
—
—
—
—
—
15:0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1654
RPF5R
23/7
22/6
21/5
20/4
19/3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
18/2
17/1
—
—
RPF5R
—
—
RPF8R
—
—
RPG12R
—
—
RPG1R
—
—
RPG1R
—
—
RPG7R
—
—
RPG8R
—
—
RPG9R
16/0
—
—
—
—
—
—
—
—
All Resets
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 284
TABLE 12-14: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 12-1:
Bit
Range
31:24
23:16
15:8
7:0
[pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
[pin name]R
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4
Unimplemented: Read as ‘0’
bit 3-0
[pin name]R: Peripheral Pin Select Input bits
Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Table for input
pin selection values.
Note:
Register values can only be changed if the IOLOCK Configuration bit (CFGCON) = 0.
REGISTER 12-2:
Bit
Range
31:24
23:16
15:8
7:0
RPnR: PERIPHERAL PIN SELECT OUTPUT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
RPnR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-4
Unimplemented: Read as ‘0’
bit 3-0
RPnR: Peripheral Pin Select Output bits
See Table for output pin selection values.
Note:
x = Bit is unknown
Register values can only be changed if the IOLOCK Configuration bit (CFGCON) = 0.
2015-2021 Microchip Technology Inc.
DS60001361J-page 285
PIC32MZ Graphics (DA) Family
REGISTER 12-3:
Bit
Range
31:24
23:16
15:8
7:0
CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (‘x’ = A – G)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
ON
—
—
—
EDGE
DETECT
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Change Notice (CN) Control ON bit
1 = CN is enabled
0 = CN is disabled
bit 14-12 Unimplemented: Read as ‘0’
bit 11
EDGEDETECT: Edge Detection Type Control bit
1 = Detects any edge on the pin (CNFx is used for the CN event)
0 = Detects any edge on the pin (CNSTATx is used for the CN event)
bit 10-0
Unimplemented: Read as ‘0’
DS60001361J-page 286
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
13.0
Note:
TIMER1
The following modes are supported by Timer1:
•
•
•
•
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS60001105), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
13.1
Additional Supported Features
• Selectable clock prescaler
• Timer operation during Sleep and Idle modes
• Fast bit manipulation using CLR, SET and INV
registers
• Asynchronous mode can be used with the SOSC
to function as a real-time clock
• ADC event trigger
PIC32MZ DA devices feature one synchronous/asynchronous 16-bit timer that can operate as a free-running
interval timer for various timing applications and counting
external events. This timer can also be used with the lowpower Secondary Oscillator (SOSC) for real-time clock
applications.
FIGURE 13-1:
Synchronous Internal Timer
Synchronous Internal Gated Timer
Synchronous External Timer
Asynchronous External Timer
TIMER1 BLOCK DIAGRAM
PR1
Equal
Trigger to ADC
16-bit Comparator
TSYNC
1
Reset
T1IF
Event Flag
Sync
TMR1
0
0
1
Q
TGATE
D
Q
TGATE
TCS
ON
SOSC
00
T1CK
01
LPRC
10
TECS
x1
Gate
Sync
PBCLK3
10
00
Prescaler
1, 8, 64, 256
2
TCKPS
2015-2021 Microchip Technology Inc.
DS60001361J-page 287
Timer1 Control Register
Virtual Address
(BF84_#)
TABLE 13-1:
TMR1
0020
PR1
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
TWDIS
TWIP
—
31:16
—
—
—
—
—
—
TECS
—
15:0
31:16
15:0
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
0000
TGATE
—
TCKPS
—
TSYNC
TCS
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
TMR1
—
—
—
—
—
—
—
All Resets
Register
Name(1)
Bit Range
Bits
0000 T1CON
0010
TIMER1 REGISTER MAP
—
—
PR1
0000
0000
FFFF
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 288
13.2
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 13-1:
Bit
Range
31:24
23:16
15:8
7:0
T1CON: TYPE A TIMER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
R/W-0
R-0
U-0
R/W-0
R/W-0
ON
—
SIDL
TWDIS
TWIP
—
R/W-0
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
TGATE
—
—
TSYNC
TCS
—
TCKPS
TECS
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Timer On bit
1 = Timer is enabled
0 = Timer is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation even in Idle mode
bit 12
TWDIS: Asynchronous Timer Write Disable bit
1 = Writes to TMR1 are ignored until pending write operation completes
0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
bit 11
TWIP: Asynchronous Timer Write in Progress bit
In Asynchronous Timer mode:
1 = Asynchronous write to TMR1 register in progress
0 = Asynchronous write to TMR1 register complete
In Synchronous Timer mode:
This bit is read as ‘0’.
bit 10
Unimplemented: Read as ‘0’
bit 9-8
TECS: Timer1 External Clock Selection bits
11 = Reserved
10 = External clock comes from the LPRC
01 = External clock comes from the T1CK pin
00 = External clock comes from the SOSC
bit 7
TGATE: Timer Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6
Unimplemented: Read as ‘0’
2015-2021 Microchip Technology Inc.
DS60001361J-page 289
PIC32MZ Graphics (DA) Family
REGISTER 13-1:
T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED)
bit 5-4
TCKPS: Timer Input Clock Prescale Select bits
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3
Unimplemented: Read as ‘0’
bit 2
TSYNC: Timer External Clock Input Synchronization Selection bit
When TCS = 1:
1 = External clock input is synchronized
0 = External clock input is not synchronized
When TCS = 0:
This bit is ignored.
bit 1
TCS: Timer Clock Source Select bit
1 = External clock is defined by the TECS bits
0 = Internal peripheral clock
bit 0
Unimplemented: Read as ‘0’
DS60001361J-page 290
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
14.0
Note:
TIMER2/3, TIMER4/5, TIMER6/7,
AND TIMER8/9
Four 32-bit synchronous timers are available by
combining Timer2 with Timer3, Timer4 with Timer5,
Timer6 with Timer7, and Timer8 with Timer9.
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS60001105), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The 32-bit timers can operate in one of three modes:
• Synchronous internal 32-bit timer
• Synchronous internal 32-bit gated timer
• Synchronous external 32-bit timer
14.1
Additional Features
• Selectable clock prescaler
• Timers operational during CPU idle
• Time base for Input Capture and Output Compare
modules (Timer2 through Timer7 only)
• ADC event trigger (Timer3 and Timer5 only)
• Fast bit manipulation using CLR, SET and INV
registers
This family of devices features eight synchronous
16-bit timers (default) that can operate as a freerunning interval timer for various timing applications
and counting external events.
The following modes are supported:
• Synchronous internal 16-bit timer
• Synchronous internal 16-bit gated timer
• Synchronous external 16-bit timer
FIGURE 14-1:
TIMER2 THROUGH TIMER9 BLOCK DIAGRAM (16-BIT)
Reset
Trigger to ADC (1)
Equal
Sync
TMRx
Comparator x 16
PRx
TxIF Event Flag
0
1
TGATE
Q
TGATE
D
Q
TCS
ON
TxCK
x1
Gate
Sync
PBCLK3
Note
1:
10
00
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
3
TCKPS
The ADC event trigger is available on Timer3 and Timer5 only.
2015-2021 Microchip Technology Inc.
DS60001361J-page 291
PIC32MZ Graphics (DA) Family
FIGURE 14-2:
TIMER2/3, TIMER4/5, TIMER6/7, AND TIMER8/9 BLOCK DIAGRAM (32-BIT)
Reset
TMRy(2)
MS Half Word
ADC Event Trigger(1)
TMRx(2)
LS Half Word
32-bit Comparator
Equal
PRy(2)
TyIF Event Flag(2)
Sync
PRx(2)
0
1
TGATE
Q
D
TGATE
Q
TCS
ON
TxCK(2)
x1
Gate
Sync
PBCLK3
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
10
00
3
TCKPS
Note
1:
2:
ADC event trigger is available only on the Timer2/3 and TImer4/5 pairs.
In this diagram, ‘x’ represents Timer2, 4, 6, or 8, and ‘y’ represents Timer3, 5, 7, or 9.
DS60001361J-page 292
2015-2021 Microchip Technology Inc.
Timer2-Timer9 Control Registers
TABLE 14-1:
Virtual Address
(BF84_#)
0210
TMR2
0220
PR2
PR3
—
15:0
ON
31:16
—
26/10
25/9
24/8
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
0A10 TMR6
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
15:0
20/4
—
—
TCKPS
19/3
18/2
17/1
16/0
—
—
—
—
0000
T32
—
TCS
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
TCS
—
0000
0000
0000
—
—
—
—
—
—
—
—
—
TCKPS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
T32
—
TCS
—
0000
0000
0000
PR3
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
TCKPS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
TCS
—
0000
0000
0000
PR4
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
TCKPS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
T32
—
TCS
—
0000
0000
0000
PR5
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
15:0
DS60001361J-page 293
—
—
—
—
—
—
—
—
TCKPS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
TCS
—
0000
0000
PR2
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
TGATE
0000
FFFF
TMR2
—
0000
FFFF
TMR5
—
0000
FFFF
TMR4
—
0000
FFFF
TMR3
15:0
0C00 T7CON
—
TGATE
—
31:16
PR6
—
—
21/5
PR2
15:0
0A00 T6CON
—
—
31:16
PR5
22/6
TMR2
15:0
TMR5
23/7
31:16
31:16
PR4
0A20
27/11
15:0
TMR4
0820
31:16
31:16
0800 T5CON
0810
28/12
0000
FFFF
TCKPS
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
TMR3
0620
29/13
15:0
0600 T4CON
0610
30/14
31:16
0400 T3CON
0420
31/15
All Resets
Bit Range
0200 T2CON
0410
TIMER2 THROUGH TIMER9 REGISTER MAP
Bits
Register
Name(1)
2015-2021 Microchip Technology Inc.
14.2
Virtual Address
(BF84_#)
0C20
0E10 TMR8
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
T32
—
TCS
—
0000
0000
TMR3
—
—
—
—
—
—
—
TMR9
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
15:0
31:16
15:0
TCKPS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
TCS
—
0000
0000
0000
PR4
31:16
—
—
—
—
—
—
—
—
PR5
0000
FFFF
TCKPS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TMR5
—
0000
FFFF
TMR4
—
0000
0000
PR3
15:0
1000 T9CON
—
31:16
31:16
PR8
PR9
30/14
15:0
0E00 T8CON
1020
31/15
15:0
31:16
PR7
0E20
31:16
All Resets
Register
Name(1)
Bit Range
Bits
0C10 TMR7
1010
TIMER2 THROUGH TIMER9 REGISTER MAP (CONTINUED)
0000
0000
FFFF
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 294
TABLE 14-1:
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 14-1:
Bit
Range
31:24
23:16
15:8
7:0
TxCON: TYPE B TIMER CONTROL REGISTER (‘x’ = 2-9)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ON(1)
—
SIDL(2)
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
T32(3)
—
TCS(1)
—
TGATE(1)
TCKPS(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-16
Unimplemented: Read as ‘0’
bit 15
ON: Timer On bit(1)
1 = Module is enabled
0 = Module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit(2)
1 = Discontinue operation when device enters Idle mode
0 = Continue operation even in Idle mode
x = Bit is unknown
bit 12-8
Unimplemented: Read as ‘0’
bit 7
TGATE: Timer Gated Time Accumulation Enable bit(1)
When TCS = 1:
This bit is ignored and is read as ‘0’.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6-4
TCKPS: Timer Input Clock Prescale Select bits(1)
111 = 1:256 prescale value
110 = 1:64 prescale value
101 = 1:32 prescale value
100 = 1:16 prescale value
011 = 1:8 prescale value
010 = 1:4 prescale value
001 = 1:2 prescale value
000 = 1:1 prescale value
bit 3
T32: 32-Bit Timer Mode Select bit(3)
1 = Odd numbered and even numbered timers form a 32-bit timer
0 = Odd numbered and even numbered timers form a separate 16-bit timer
Note 1:
While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, Timer5,
Timer7, and Timer9). All timer functions are set through the even numbered timers.
While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
This bit is available only on even numbered timers (Timer2, Timer4, Timer6, and Timer8).
2:
3:
2015-2021 Microchip Technology Inc.
DS60001361J-page 295
PIC32MZ Graphics (DA) Family
REGISTER 14-1:
TxCON: TYPE B TIMER CONTROL REGISTER (‘x’ = 2-9) (CONTINUED)
bit 2
Unimplemented: Read as ‘0’
bit 1
TCS: Timer Clock Source Select bit(1)
1 = External clock from TxCK pin
0 = Internal peripheral clock
bit 0
Unimplemented: Read as ‘0’
Note 1:
While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, Timer5,
Timer7, and Timer9). All timer functions are set through the even numbered timers.
While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
This bit is available only on even numbered timers (Timer2, Timer4, Timer6, and Timer8).
2:
3:
DS60001361J-page 296
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
15.0
INPUT CAPTURE
Note:
Capture events are caused by the following:
• Capture timer value on every edge (rising and falling),
specified edge first
• Prescaler capture event modes:
- Capture timer value on every 4th rising edge of
input at ICx pin
- Capture timer value on every 16th rising edge of
input at ICx pin
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 15. “Input
Capture” (DS60001122), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
Each input capture channel can select between one of
six 16-bit timers for the time base, or two of six 16-bit
timers together to form a 32-bit timer. The selected
timer can use either an internal or external clock.
Other operational features include:
The Input Capture module is useful in applications
requiring frequency (period) and pulse measurement.
• Device wake-up from capture pin during Sleep and
Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values; Interrupt
optionally generated after 1, 2, 3, or 4 buffer
locations are filled
• Input capture can also be used to provide additional
sources of external interrupts
The Input Capture module captures the 16-bit or 32-bit
value of the selected Time Base registers when an
event occurs at the ICx pin.
FIGURE 15-1:
INPUT CAPTURE BLOCK DIAGRAM
FEDGE
Specified/Every
Edge Mode
ICM
110
PBCLK3
Prescaler Mode
(16th Rising Edge)
101
Prescaler Mode
(4th Rising Edge)
100
Timerx(2)
Timery(2)
C32/ICTMR
CaptureEvent
ICx(1)
Rising Edge Mode
011
Falling Edge Mode
010
Edge Detection
Mode
001
To CPU
FIFO Control
ICxBUF(1)
FIFO
ICI
ICM
Set Flag ICxIF(1)
(In IFSx Register)
/N
Sleep/Idle
Wake-up Mode
001
111
Note
1:
An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
2:
See Table 15-1 for Timerx and Timery selections.
2015-2021 Microchip Technology Inc.
DS60001361J-page 297
PIC32MZ Graphics (DA) Family
The timer source for each Input Capture module
depends on the setting of the ICACLK bit in the
CFGCON register. The available configurations are
shown in Table 15-1.
TABLE 15-1:
TIMER SOURCE
CONFIGURATIONS
Input Capture
Module
Timerx
Timery
ICACLK (CFGCON) = 0
IC1
•
•
•
IC9
Timer2
•
•
•
Timer 2
Timer3
•
•
•
Timer 3
ICACLK (CFGCON) = 1
IC1
Timer4
Timer5
IC2
Timer4
Timer5
IC3
Timer4
Timer5
IC4
Timer2
Timer3
IC5
Timer2
Timer3
IC6
Timer2
Timer3
IC7
Timer6
Timer7
IC8
Timer6
Timer7
IC9
Timer6
Timer7
DS60001361J-page 298
2015-2021 Microchip Technology Inc.
Input Capture Control Registers
TABLE 15-2:
INPUT CAPTURE 1 THROUGH INPUT CAPTURE 9 REGISTER MAP
2000 IC1CON(1)
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
PIC32MZ Graphics (DA) Family
DS60001361J-page 299
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
2010 IC1BUF
IC1BUF
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2200 IC2CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
2210 IC2BUF
IC2BUF
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2400 IC3CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
2410 IC3BUF
IC3BUF
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2600 IC4CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
2610 IC4BUF
IC4BUF
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2800 IC5CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
2810 IC5BUF
IC5BUF
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2A00 IC6CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
2A10 IC6BUF
IC6BUF
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2C00 IC7CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
2C10 IC7BUF
IC7BUF
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2E00 IC8CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
2E10 IC8BUF
IC8BUF
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3000 IC9CON(1)
15:0
ON
—
SIDL
—
—
—
FEDGE
C32
ICTMR
ICI
ICOV
ICBNE
ICM
31:16
3010 IC9BUF
IC9BUF
15:0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more
information.
All Resets
Bit Range
Bits
Register
Name
Virtual Address
(BF84_#)
2015-2021 Microchip Technology Inc.
15.1
PIC32MZ Graphics (DA) Family
REGISTER 15-1:
Bit Range
31:24
23:16
15:8
7:0
ICXCON: INPUT CAPTURE X CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
bit 14
bit 13
bit 12-10
bit 9
bit 8
bit 7
bit 6-5
bit 4
bit 3
bit 2-0
Note 1:
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
ON
—
SIDL
—
—
—
FEDGE
C32
R/W-0
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
ICOV
ICBNE
ICTMR
ICI
Legend:
R = Readable bit
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = unknown)
bit 31-16
bit 15
Bit
25/17/9/1
ICM
U = Unimplemented bit
P = Programmable bit
r = Reserved bit
Unimplemented: Read as ‘0’
ON: Input Capture Module Enable bit
1 = Module enabled
0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Control bit
1 = Halt in CPU Idle mode
0 = Continue to operate in CPU Idle mode
Unimplemented: Read as ‘0’
FEDGE: First Capture Edge Select bit (only used in mode 6, ICM = 110)
1 = Capture rising edge first
0 = Capture falling edge first
C32: 32-bit Capture Select bit
1 = 32-bit timer resource capture
0 = 16-bit timer resource capture
ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON) is ‘1’)(1)
0 = Timery is the counter source for capture
1 = Timerx is the counter source for capture
ICI: Interrupt Control bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
ICBNE: Input Capture Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty; at least one more capture value can be read
0 = Input capture buffer is empty
ICM: Input Capture Mode Select bits
111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter
101 = Prescaled Capture Event mode – every sixteenth rising edge
100 = Prescaled Capture Event mode – every fourth rising edge
011 = Simple Capture Event mode – every rising edge
010 = Simple Capture Event mode – every falling edge
001 = Edge Detect mode – every edge (rising and falling)
000 = Input Capture module is disabled
Refer to Table 15-1 for Timerx and Timery selections.
DS60001361J-page 300
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
16.0
OUTPUT COMPARE
Note:
When a match occurs, the Output Compare module
generates an event based on the selected mode of
operation.
This data sheet summarizes the
features of the PIC32MZ Graphics (DA)
Family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 16.
“Output
Compare”
(DS60001111),
which
is
available
from
the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The following are some of the key features of the
Output Compare module:
• Multiple Output Compare modules in a device
• Programmable interrupt generation on compare
event
• Single and Dual Compare modes
• Single and continuous output pulse generation
• Pulse-Width Modulation (PWM) mode
• Hardware-based PWM Fault detection and
automatic output disable
• Programmable selection of 16-bit or 32-bit time
bases
• Can operate from either of two available 16-bit
time bases or a single 32-bit time base
• ADC event trigger
The Output Compare module is used to generate a
single pulse or a train of pulses in response to selected
time base events.
For all modes of operation, the Output Compare module compares the values stored in the OCxR and/or the
OCxRS registers to the value in the selected timer.
FIGURE 16-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit OCxIF(1)
OCxRS(1)
Trigger to ADC(4)
Output
Logic
OCxR(1)
3
OCM
Mode Select
Comparator
0
16
PBCLK3
Timerx(3)
OCTSEL
1
0
S
R
Output
Enable
Q
OCx(1)
Output Enable
Logic
OCFA or
OCFB(2)
1
16
Timery(3)
Timerx(3)
Rollover
Timery(3)
Rollover
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels,
1 through 9.
2: The OCFA pin controls the OC1, OC3, and OC7-OC9 channels. The OCFB pin controls the OC4-OC6 channels.
3: Refer to Table 16-1 for Timerx and Timery selections.
4: The ADC event trigger is only available on OC1,OC3, and OC 5.
2015-2021 Microchip Technology Inc.
DS60001361J-page 301
PIC32MZ Graphics (DA) Family
The timer source for each Output Compare module
depends on the setting of the OCACLK bit in the
CFGCON register. The available configurations are
shown in Table 16-1.
TABLE 16-1:
TIMER SOURCE
CONFIGURATIONS
Output
Compare
Module
Timerx
Timery
OCACLK (CFGCON) = 0
OC1
•
•
•
OC9
Timer2
•
•
•
Timer 2
Timer3
•
•
•
Timer 3
OCACLK (CFGCON) = 1
OC1
Timer4
Timer5
OC2
Timer4
Timer5
OC3
Timer4
Timer5
OC4
Timer2
Timer3
OC5
Timer2
Timer3
OC6
Timer2
Timer3
OC7
Timer6
Timer7
OC8
Timer6
Timer7
OC9
Timer6
Timer7
DS60001361J-page 302
2015-2021 Microchip Technology Inc.
Output Compare Control Registers
TABLE 16-2:
Virtual Address
(BF84_#)
4000 OC1CON
4010
4020
OC1R
OC1RS
4200 OC2CON
OC2R
OC2RS
4400 OC3CON
4410
4420
OC3R
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
15:0
ON
—
—
—
—
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
OC32
31:16
4610
OC4R
4620
OC4RS
4800 OC5CON
4810
OC5R
DS60001361J-page 303
OC5RS
21/5
20/4
19/3
18/2
—
—
—
OCFLT
OCTSEL
31:16
0000
xxxx
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM
31:16
xxxx
xxxx
xxxx
OC2RS
15:0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM
xxxx
xxxx
xxxx
OC3RS
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM
31:16
15:0
xxxx
xxxx
xxxx
OC4RS
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
OC5R
OC5RS
0000
0000
OC4R
15:0
0000
0000
OC3R
15:0
0000
0000
OC2R
15:0
0000
xxxx
—
15:0
—
xxxx
31:16
31:16
—
OCM
OC1RS
15:0
15:0
16/0
OC1R
15:0
31:16
17/1
All Resets
Bit Range
30/14
31:16
OC3RS
15:0
4600 OC4CON
4820
31/15
—
—
OCM
—
0000
0000
xxxx
xxxx
xxxx
xxxx
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
4210
4220
OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 9 REGISTER MAP
Bits
Register
Name(1)
2015-2021 Microchip Technology Inc.
16.1
Virtual Address
(BF84_#)
4A10
OC6R
OC6RS
4C00 OC7CON
4C10
OC7R
4C20 OC7RS
4E00 OC8CON
4E10
OC8R
4E20
OC8RS
5000 OC9CON
5010
5020
OC9R
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
15:0
ON
—
—
—
—
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
OC32
31:16
21/5
20/4
19/3
18/2
—
—
—
OCFLT
OCTSEL
31:16
—
0000
xxxx
xxxx
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM
31:16
xxxx
xxxx
xxxx
OC7RS
15:0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM
31:16
15:0
xxxx
xxxx
xxxx
OC8RS
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
OC9R
OC9RS
0000
0000
OC8R
15:0
0000
0000
OC7R
15:0
0000
xxxx
31:16
31:16
OC9RS
15:0
—
OCM
OC6RS
15:0
15:0
16/0
OC6R
15:0
31:16
17/1
All Resets
Bit Range
Register
Name(1)
Bits
4A00 OC6CON
4A20
OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 9 REGISTER MAP (CONTINUED)
—
—
OCM
—
0000
0000
xxxx
xxxx
xxxx
2015-2021 Microchip Technology Inc.
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 304
TABLE 16-2:
PIC32MZ Graphics (DA) Family
REGISTER 16-1:
Bit
Range
31:24
23:16
15:8
7:0
OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ON
—
SIDL
—
—
—
—
—
U-0
U-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
OC32
OCFLT(1)
OCTSEL(2)
OCM
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Output Compare Peripheral On bit
1 = Output Compare peripheral is enabled
0 = Output Compare peripheral is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters Idle mode
0 = Continue operation in Idle mode
bit 12-6
Unimplemented: Read as ‘0’
bit 5
OC32: 32-bit Compare Mode bit
1 = OCxR and/or OCxRS are used for comparisions to the 32-bit timer source
0 = OCxR and OCxRS are used for comparisons to the 16-bit timer source
bit 4
OCFLT: PWM Fault Condition Status bit(1)
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred
bit 3
OCTSEL: Output Compare Timer Select bit(2)
1 = Timery is the clock source for this Output Compare module
0 = Timerx is the clock source for this Output Compare module
bit 2-0
OCM: Output Compare Mode Select bits
111 = PWM mode on OCx; Fault pin enabled
110 = PWM mode on OCx; Fault pin disabled
101 = Initialize OCx pin low; generate continuous output pulses on OCx pin
100 = Initialize OCx pin low; generate single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initialize OCx pin high; compare event forces OCx pin low
001 = Initialize OCx pin low; compare event forces OCx pin high
000 = Output compare peripheral is disabled but continues to draw current
Note 1:
2:
This bit is only used when OCM = ‘111’. It is read as ‘0’ in all other modes.
Refer to Table 16-1 for Timerx and Timery selections.
2015-2021 Microchip Technology Inc.
DS60001361J-page 305
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 306
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
17.0
DEADMAN TIMER (DMT)
Note:
The primary function of the Deadman Timer (DMT) is
to reset the processor in the event of a software malfunction. The DMT is a free-running instruction fetch
timer, which is clocked whenever an instruction fetch
occurs until a count match occurs. Instructions are not
fetched when the processor is in Sleep mode.
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family
family of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 9. “Watchdog,
Deadman, and Power-up Timers”
(DS60001114), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The DMT consists of a 32-bit counter with a time-out
count match value as specified by the DMTCNT
bits in the DEVCFG1 Configuration register.
A Deadman Timer is typically used in mission critical
and safety critical applications, where any single failure of the software functionality and sequencing must
be detected.
Figure 17-1 shows a block diagram of the Deadman
Timer module.
FIGURE 17-1:
DEADMAN TIMER BLOCK DIAGRAM
“improper sequence” flag
ON
Instruction Fetched Strobe
Force DMT Event
System Reset
Counter Initialization Value
PBCLK7
Clock
“Proper Clear Sequence” Flag
ON
32-bit counter
ON
32
DMT event
to NMI(3)
DMT Count Reset Load
System Reset
(COUNTER) = DMT Max Count(1)
(COUNTER) DMT Window Interval(2)
Window Interval Open
Note
1:
2:
3:
DMT Max Count is controlled by the DMTCNT bits in the DEVCFG1 Configuration register.
DMT Window Interval is controlled by the DMTINTV bits in the DEVCFG1 Configuration register.
Refer to Section 6.0 “Resets” for more information.
2015-2021 Microchip Technology Inc.
DS60001361J-page 307
Deadman Timer Control Registers
Virtual Address
(BF80_#)
Register
Name
TABLE 17-1:
0A00
DMTCON
DEADMAN TIMER REGISTER MAP
0A10 DMTPRECLR
0A20
DMTCLR
0A30
DMTSTAT
0A40
DMTCNT
0A60
DMTPSCNT
0A70
DMTPSINTV
Legend:
All Resets
Bit Range
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
15:0
STEP1
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
BAD1
BAD2
DMTEVENT
—
—
—
—
31:16
15:0
31:16
15:0
31:16
15:0
STEP2
COUNTER
PSCNT
PSINTV
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
0000
WINOPN 0000
0000
0000
0000
0000
0000
0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 308
17.1
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 17-1:
Bit Range
DMTCON: DEADMAN TIMER CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
31:24
23:16
15:8
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
ON(1)
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
7:0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = unknown)
P = Programmable bit
bit 31-16
Unimplemented: Read as ‘0’
bit 15
ON: Deadman Timer Module Enable bit(1)
1 = Deadman Timer module is enabled
0 = Deadman Timer module is disabled
bit 13-0
Unimplemented: Read as ‘0’
Note 1:
r = Reserved bit
This bit only has control when FDMTEN (DEVCFG1) = 0. Once set, the DMTCON.ON bit cannot be
disabled by software.
REGISTER 17-2:
Bit Range
DMTPRECLR: DEADMAN TIMER PRECLEAR REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
STEP1
7:0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = unknown)
U = Unimplemented bit
P = Programmable bit
r = Reserved bit
bit 31-16
Unimplemented: Read as ‘0’
bit 15-8
STEP1: Preclear Enable bits
01000000 = Enables the Deadman Timer Preclear (Step 1)
All other write patterns = Set BAD1 flag.
These bits are cleared when a DMT reset event occurs. STEP1 is also cleared if the
STEP2 bits are loaded with the correct value in the correct sequence.
bit 7-0
Unimplemented: Read as ‘0’
2015-2021 Microchip Technology Inc.
DS60001361J-page 309
PIC32MZ Graphics (DA) Family
REGISTER 17-3:
Bit Range
31:24
23:16
15:8
7:0
DMTCLR: DEADMAN TIMER CLEAR REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STEP2
Legend:
R = Readable bit
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = unknown)
bit 31-8
bit 7-0
Bit
25/17/9/1
U = Unimplemented bit
P = Programmable bit
r = Reserved bit
Unimplemented: Read as ‘0’
STEP2: Clear Timer bits
00001000 = Clears STEP1, STEP2 and the Deadman Timer if, and only if, preceded by correct loading of STEP1 bits in the correct sequence. The write to these bits may be
verified by reading the DMTCNT bit and observing the counter being reset.
All other write patterns = Set BAD2 bit, the value of STEP1 will remain unchanged, and the new
value being written STEP2 will be captured. These bits are also cleared when a DMT reset event
occurs.
If the STEP2 bits are written without preceding with a correct loading of STEP1 bits, the
BAD1 bit is set.
DS60001361J-page 310
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 17-4:
Bit Range
31:24
23:16
15:8
7:0
DMTSTAT: DEADMAN TIMER STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
Bit
Bit
25/17/9/1 24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0, HC
R-0, HC
R-0, HC
R/W-0
R/W-0
R/W-0
R/W-0
R-0
BAD1
BAD2
DMTEVENT
WINOPN
Legend:
HC = Cleared by Hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = unknown)
P = Programmable bit r = Reserved bit
bit 31-8
bit 7
bit 6
bit 5
bit 4-1
bit 0
Unimplemented: Read as ‘0’
BAD1: Bad STEP1 Value Detect bit
1 = Incorrect STEP1 value or out of sequence write to STEP2 was detected
0 = Incorrect STEP1 value or out of sequence write to STEP2 was not detected
BAD2: Bad STEP2 Value Detect bit
1 = Incorrect STEP2 value was detected
0 = Incorrect STEP2 value was not detected
DMTEVENT: Deadman Timer Event bit
1 = Deadman timer event was detected (counter expired or bad STEP1 or STEP2 value was
entered prior to counter increment)
0 = Deadman timer event was not detected
Unimplemented: Read as ‘0’
WINOPN: Deadman Timer Clear Window bit
1 = Deadman timer clear window is open
0 = Deadman timer clear window is not open
2015-2021 Microchip Technology Inc.
DS60001361J-page 311
PIC32MZ Graphics (DA) Family
REGISTER 17-5:
Bit Range
DMTCNT: DEADMAN TIMER COUNT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
R-0
R-0
31:24
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
7:0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
U = Unimplemented bit
P = Programmable bit
r = Reserved bit
DMTPSCNT: POST STATUS CONFIGURE DMT COUNT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
R-0
R-0
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
R-0
R-0
R-0
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
PSCNT
R-0
R-0
R-0
R-0
R-0
PSCNT
R-0
R-0
R-0
R-0
R-0
PSCNT
R-0
R-0
R-0
R-0
R-0
PSCNT
Legend:
R = Readable bit
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = unknown)
bit 31-8
R-0
COUNTER: Read current contents of DMT counter
REGISTER 17-6:
15:8
R-0
COUNTER
Legend:
R = Readable bit
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = unknown)
23:16
R-0
COUNTER
7:0
31:24
R-0
COUNTER
15:8
Bit Range
Bit
24/16/8/0
COUNTER
23:16
bit 31-8
R-0
Bit
25/17/9/1
U = Unimplemented bit
P = Programmable bit
r = Reserved bit
PSCNT: DMT Instruction Count Value Configuration Status bits
This is always the value of the DMTCNT bits in the DEVCFG1 Configuration register.
DS60001361J-page 312
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 17-7:
Bit Range
31:24
23:16
15:8
7:0
DMTPSINTV: POST STATUS CONFIGURE DMT INTERVAL STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
R-0
R-0
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
R-0
R-0
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
PSINTV
R-0
R-0
R-0
R-0
R-0
PSINTV
R-0
R-0
R-0
R-0
R-0
PSINTV
R-0
R-0
R-0
R-0
R-0
PSINTV
Legend:
R = Readable bit
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = unknown)
bit 31-8
R-0
Bit
25/17/9/1
U = Unimplemented bit
P = Programmable bit
r = Reserved bit
PSINTV: DMT Window Interval Configuration Status bits
This is always the value of the DMTINTV bits in the DEVCFG1 Configuration register.
2015-2021 Microchip Technology Inc.
DS60001361J-page 313
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 314
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
18.0
WATCHDOG TIMER (WDT)
Note:
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family
family of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 9. “Watchdog,
Deadman, and Power-up Timers”
(DS60001114), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
FIGURE 18-1:
When enabled, the Watchdog Timer (WDT) operates
from the internal Low-Power Oscillator (LPRC) clock
source and can be used to detect system software malfunctions by resetting the device if the WDT is not
cleared periodically in software. Various WDT time-out
periods can be selected using the WDT postscaler. The
WDT can also be used to wake the device from Sleep
or Idle mode.
The following are some of the key features of the WDT
module:
• Configuration or software controlled
• User-configurable time-out period
• Can wake the device from Sleep or Idle
WATCHDOG TIMER BLOCK DIAGRAM
LPRC
WDTCLR = 1
ON
ON
Wake
ON
Reset Event
Clock
25-bit Counter
25
0
1
WDT Counter Reset
WDT Event
to NMI(1)
Power Save
Decoder
WDTPS (DEVCFG1)
Note 1:
Refer to Section 6.0 “Resets” for more information.
2015-2021 Microchip Technology Inc.
DS60001361J-page 315
Watchdog Timer Control Registers
Virtual Address
(BF80_#)
Register
Name
TABLE 18-1:
0800
WDTCON(1)
WATCHDOG TIMER REGISTER MAP
Legend:
Note 1:
31/15
30/14
29/13
ON
—
—
28/12
27/11
26/10
31:16
15:0
25/9
24/8
23/7
22/6
21/5
20/4
19/3
WDTCLRKEY
RUNDIV
—
—
18/2
17/1
16/0
All Resets
Bit Range
Bits
0000
SLPDIV
WDTWINEN xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 316
18.1
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 18-1:
Bit
Range
31:24
23:16
15:8
7:0
WDTCON: WATCHDOG TIMER CONTROL REGISTER
Bit
31/23/15/7
W-0
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4
W-0
W-0
W-0
Bit
Bit
27/19/11/3 26/18/10/2
W-0
Bit
25/17/9/1
Bit
24/16/8/0
W-0
W-0
W-0
W-0
W-0
W-0
R-y
R-y
R-y
U-0
R/W-0
WDTCLRKEY
W-0
W-0
W-0
R/W-0
(1)
U-0
U-0
—
—
U-0
U-0
U-0
—
—
W-0
W-0
WDTCLRKEY
ON
R-y
R-y
RUNDIV
U-0
U-0
U-0
SLPDIV
WDTWINEN
Legend:
y = Values set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 WDTCLRKEY: Watchdog Timer Clear Key bits
To clear the Watchdog Timer to prevent a time-out, software must write the value 0x5743 to these bits using
a single 16-bit write.
bit 15
ON: Watchdog Timer Enable bit(1)
1 = The Watchdog Timer module is enabled
0 = The Watchdog Timer module is disabled
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8
RUNDIV: Watchdog Timer Postscaler Value in Run Mode bits
In Run mode, these bits are set to the values of the WDTPS Configuration bits in DEVCFG1.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-1
SLPDIV: Watchdog Timer Postscaler Value in Sleep Mode bits
In Sleep mode, these bits are set to the values of the SWDTPS Configuration bits in DEVCFG4.
bit 0
WDTWINEN: Watchdog Timer Window Enable bit
1 = Enable windowed Watchdog Timer
0 = Disable windowed Watchdog Timer
Note 1:
This bit only has control when FWDTEN (DEVCFG1) = 0.
2015-2021 Microchip Technology Inc.
DS60001361J-page 317
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 318
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
19.0
Note:
DEEP SLEEP WATCHDOG
TIMER (DSWDT)
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family
family of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 9. “Watchdog,
Deadman, and Power-up Timers”
(DS60001114), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
FIGURE 19-1:
The Deep Sleep Watchdog Timer (DSWDT) is a dedicated Watchdog Timer for Deep Sleep mode operations of the device. The DSWDT is very useful in
Battery-powered applications and in Low-Power
modes of operations.
The primary function of the DSWDT is to automatically
exit Deep Sleep mode after a prescribed amount of
time has elapsed.
The DSWDT is controlled through the DEVCFG2
Configuration register at boot time (one-time
programmable per POR). When enabled through the
DSWDTEN bit in DEVCFG2, the DSWDT operates
either from the internal Low-Power RC (LPRC) clock
or from the Secondary Oscillator (SOSC). The clock
selection for the DSWDT is done through the
DSWDTOSC bit in the DEVCFG2 register.
DEEP SLEEP WATCHDOG TIMER BLOCK DIAGRAM
DSWDTPS (DEVCFG2)
Postscaler
Compare
DSWDT event
DSWDTEN (DEVCFG2)
LPRC
0
5-bit Prescaler
SOSC
31-bit Counter
1
DSWDTOSC (DEVCFG2)
Example: When DSWDTOSC = 1, DSWDTPS bits = 00000, and the SOSC is 32 kHz, the Watchdog delay is set to 1 ms.
2015-2021 Microchip Technology Inc.
DS60001361J-page 319
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 320
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
20.0
Note:
REAL-TIME CLOCK AND
CALENDAR (RTCC)
Key features of the RTCC module include:
•
•
•
•
•
This data sheet summarizes the
features of the PIC32MZ Graphics (DA)
Family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 29. “RealTime Clock and Calendar (RTCC)”
(DS60001125), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
•
•
•
•
•
•
•
•
The RTCC module is intended for applications in which
accurate time must be maintained for extended periods
of time with minimal or no CPU intervention. Lowpower optimization provides extended battery lifetime
while keeping track of time.
The RTCC module can operate in VBAT mode when
there is a power loss on the VDDIO pin. The RTCC will
continue to operate if the VBAT pin is powered on (it is
usually connected to the battery).
•
•
•
•
Time: hours, minutes and seconds
24-hour format (military time)
Visibility of one-half second period
Provides calendar: Weekday, date, month and year
Alarm intervals are configurable for half of a second,
one second, 10 seconds, one minute, 10 minutes,
one hour, one day, one week, one month, and one
year
Alarm repeat with decrementing counter
Alarm with indefinite repeat: Chime
Year range: 2000 to 2099
Leap year correction
BCD format for smaller firmware overhead
Optimized for long-term battery operation
Fractional second synchronization
User calibration of the clock crystal frequency with
auto-adjust
Calibration range: 0.66 seconds error per month
Calibrates up to 260 ppm of crystal error
Uses external crystal or internal oscillator
Alarm pulse, seconds clock, or internal clock output
on RTCC pin
Note:
FIGURE 20-1:
RTCC pin function is not available during
VBAT operation.
RTCC BLOCK DIAGRAM
RTCCLKSEL
Secondary Oscillator (SOSC)
Internal Oscillator (LPRC)
TRTC
RTCC Prescalers
0.5 seconds
YEAR, MTH, DAY
RTCVAL
RTCC Timer
Alarm
Event
WKDAY
HR, MIN, SEC
Comparator
MTH, DAY
Compare Registers
with Masks
ALRMVAL
WKDAY
HR, MIN, SEC
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
Seconds Pulse
TRTC
RTCC Pin
RTCOE
RTCOUTSEL
2015-2021 Microchip Technology Inc.
DS60001361J-page 321
RTCC Control Registers
Virtual Address
(BF8C_#)
Register
Name(1)
TABLE 20-1:
0000
RTCCON
RTCC REGISTER MAP
0010 RTCALRM
0020 RTCTIME
0030 RTCDATE
0040 ALRMTIME
0050 ALRMDATE
Legend:
Note 1:
31/15
30/14
31:16
—
15:0
ON
31:16
—
15:0 ALRMEN
29/13
28/12
27/11
—
—
—
—
—
SIDL
—
—
—
—
—
—
CHIME
PIV
ALRMSYNC
26/10
25/9
—
—
SEC10
SEC01
31:16
YEAR10
YEAR01
15:0
DAY10
DAY01
31:16
HR10
HR01
15:0
SEC10
SEC01
15:0
DAY10
—
—
—
20/4
19/3
18/2
17/1
16/0
—
—
—
—
DAY01
0000
—
—
—
—
AMASK
15:0
—
21/5
CAL
HR01
—
22/6
—
HR10
—
23/7
RTCCLKSEL RTCOUTSEL RTCCLKON
31:16
31:16
24/8
RTCWREN RTCSYNC HALFSEC RTCOE
—
—
—
—
ARPT
—
MIN01
—
—
—
MONTH10
—
—
—
—
MIN10
—
—
—
—
MONTH10
—
—
—
—
—
—
0000
xxxx
—
—
xx00
MONTH01
xxxx
WDAY01
xx00
MIN01
—
0000
0000
MIN10
—
All Resets
Bit Range
Bits
—
—
xxxx
—
xx00
MONTH01
00xx
WDAY01
xx0x
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more
information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 322
20.1
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 20-1:
Bit
Range
Bit
31/23/15/7
31:24
23:16
Bit
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CAL
CAL
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
ON(1)
—
SIDL
—
—
RTCCLKSEL
R/W-0
R-0
U-0
U-0
R/W-0
R-0
R-0
R/W-0
RTC
OUTSEL(2)
RTC
CLKON
—
—
RTC
WREN(3)
RTC
SYNC
HALFSEC(4)
RTCOE
15:8
7:0
RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER
RTC
OUTSEL(2)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25-16 CAL: Real-Time Clock Drift Calibration bits, which contain a signed 10-bit integer value
0111111111 = Maximum positive adjustment, adds 511 real-time clock pulses every one minute
•
•
•
0000000001 = Minimum positive adjustment, adds 1 real-time clock pulse every one minute
0000000000 = No adjustment
1111111111 = Minimum negative adjustment, subtracts 1 real-time clock pulse every one minute
•
•
•
1000000000 = Minimum negative adjustment, subtracts 512 real-time clock pulses every one minute
bit 15
ON: RTCC On bit(1)
1 = RTCC module is enabled
0 = RTCC module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Disables RTCC operation when CPU enters Idle mode
0 = Continue normal operation when CPU enters Idle mode
bit 12-11 Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
Note:
The ON bit is only writable when RTCWREN = 1.
Requires RTCOE = 1 (RTCCON) for the output to be active.
The RTCWREN bit can be set only when the write sequence is enabled.
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME).
This register is reset only on a Power-on Reset (POR).
2015-2021 Microchip Technology Inc.
DS60001361J-page 323
PIC32MZ Graphics (DA) Family
REGISTER 20-1:
RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER
bit 10-9
RTCCLKSEL: RTCC Clock Select bits
When a new value is written to these bits, the Seconds Value register should also be written to properly
reset the clock prescalers in the RTCC.
11 = Reserved
10 = Reserved
01 = RTCC uses the external 32.768 kHz Secondary Oscillator (SOSC)
00 = RTCC uses the internal 32 kHz oscillator (LPRC)
bit 8-7
RTCOUTSEL: RTCC Output Data Select bits(2)
11 = Reserved
10 = RTCC Clock is presented on the RTCC pin
01 = Seconds Clock is presented on the RTCC pin
00 = Alarm Pulse is presented on the RTCC pin when the alarm interrupt is triggered
bit 6
RTCCLKON: RTCC Clock Enable Status bit
1 = RTCC Clock is actively running
0 = RTCC Clock is not running
bit 5-4
Unimplemented: Read as ‘0’
bit 3
RTCWREN: Real-Time Clock Value Registers Write Enable bit(3)
1 = Real-Time Clock Value registers can be written to by the user
0 = Real-Time Clock Value registers are locked out from being written to by the user
bit 2
RTCSYNC: Real-Time Clock Value Registers Read Synchronization bit
1 = Real-time clock value registers can change while reading (due to a rollover ripple that results in an invalid
data read). If the register is read twice and results in the same data, the data can be assumed to be valid.
0 = Real-time clock value registers can be read without concern about a rollover ripple
bit 1
HALFSEC: Half-Second Status bit(4)
1 = Second half period of a second
0 = First half period of a second
bit 0
RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is not enabled
Note 1:
2:
3:
4:
The ON bit is only writable when RTCWREN = 1.
Requires RTCOE = 1 (RTCCON) for the output to be active.
The RTCWREN bit can be set only when the write sequence is enabled.
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME).
Note:
This register is reset only on a Power-on Reset (POR).
DS60001361J-page 324
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 20-2:
Bit
Range
31:24
23:16
15:8
7:0
RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
Bit
27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R-0
R/W-0
R/W-0
CHIME(2)
R/W-0
(2)
R/W-0
ALRMEN(1,2)
R/W-0
(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PIV
ALRMSYNC
R/W-0
AMASK
R/W-0
ARPT(2)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ALRMEN: Alarm Enable bit(1,2)
1 = Alarm is enabled
0 = Alarm is disabled
bit 14
CHIME: Chime Enable bit(2)
1 = Chime is enabled – ARPT is allowed to rollover from 0x00 to 0xFF
0 = Chime is disabled – ARPT stops once it reaches 0x00
bit 13
PIV: Alarm Pulse Initial Value bit(2)
When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse.
When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.
bit 12
ALRMSYNC: Alarm Sync bit
1 = ARPT and ALRMEN may change as a result of a half second rollover during a read.
The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple
bits may be changing.
0 = ARPT and ALRMEN can be read without concerns of rollover because the prescaler is more than
32 real-time clocks away from a half-second rollover
bit 11-8 AMASK: Alarm Mask Configuration bits(2)
0000 = Every half-second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29, once every four years)
1010 = Reserved
1011 = Reserved
11xx = Reserved
Note 1:
2:
Note:
Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT = 00 and
CHIME = 0.
This field should not be written when the RTCC ON bit = ‘1’ (RTCCON) and ALRMSYNC = 1.
This register is reset only on a Power-on Reset (POR).
2015-2021 Microchip Technology Inc.
DS60001361J-page 325
PIC32MZ Graphics (DA) Family
REGISTER 20-2:
RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER (CONTINUED)
ARPT: Alarm Repeat Counter Value bits(2)
11111111 = Alarm will trigger 256 times
bit 7-0
•
•
•
00000000 = Alarm will trigger one time
The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.
Note 1:
2:
Note:
Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT = 00 and
CHIME = 0.
This field should not be written when the RTCC ON bit = ‘1’ (RTCCON) and ALRMSYNC = 1.
This register is reset only on a Power-on Reset (POR).
DS60001361J-page 326
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 20-3:
Bit
Range
31:24
23:16
15:8
7:0
RTCTIME: REAL-TIME CLOCK TIME VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
HR10
R/W-x
R/W-x
HR01
R/W-x
R/W-x
R/W-x
R/W-x
MIN10
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MIN01
R/W-x
R/W-x
R/W-x
SEC10
R/W-x
R/W-x
SEC01
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 HR10: Binary-Coded Decimal Value of Hours bits, 10 digits; contains a value from 0 to 2
bit 27-24 HR01: Binary-Coded Decimal Value of Hours bits, 1 digit; contains a value from 0 to 9
bit 23-20 MIN10: Binary-Coded Decimal Value of Minutes bits, 10 digits; contains a value from 0 to 5
bit 19-16 MIN01: Binary-Coded Decimal Value of Minutes bits, 1 digit; contains a value from 0 to 9
bit 15-12 SEC10: Binary-Coded Decimal Value of Seconds bits, 10 digits; contains a value from 0 to 5
bit 11-8
SEC01: Binary-Coded Decimal Value of Seconds bits, 1 digit; contains a value from 0 to 9
bit 7-0
Unimplemented: Read as ‘0’
Note:
This register is only writable when RTCWREN = 1 (RTCCON).
2015-2021 Microchip Technology Inc.
DS60001361J-page 327
PIC32MZ Graphics (DA) Family
REGISTER 20-4:
Bit
Range
31:24
23:16
15:8
7:0
RTCDATE: REAL-TIME CLOCK DATE VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
YEAR10
R/W-x
R/W-x
R/W-x
YEAR01
R/W-x
R/W-x
MONTH10
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MONTH01
R/W-x
R/W-x
R/W-x
DAY10
R/W-x
R/W-x
DAY01
U-0
U-0
U-0
U-0
—
—
—
—
R/W-x
R/W-x
R/W-x
R/W-x
WDAY01
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 YEAR10: Binary-Coded Decimal Value of Years bits, 10 digits
bit 27-24 YEAR01: Binary-Coded Decimal Value of Years bits, 1 digit
bit 23-20 MONTH10: Binary-Coded Decimal Value of Months bits, 10 digits; contains a value from 0 to 1
bit 19-16 MONTH01: Binary-Coded Decimal Value of Months bits, 1 digit; contains a value from 0 to 9
bit 15-12 DAY10: Binary-Coded Decimal Value of Days bits, 10 digits; contains a value from 0 to 3
bit 11-8
DAY01: Binary-Coded Decimal Value of Days bits, 1 digit; contains a value from 0 to 9
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
WDAY01: Binary-Coded Decimal Value of Weekdays bits,1 digit; contains a value from 0 to 6
Note:
This register is only writable when RTCWREN = 1 (RTCCON).
DS60001361J-page 328
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 20-5:
Bit
Range
31:24
23:16
15:8
7:0
ALRMTIME: ALARM TIME VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
HR10
R/W-x
R/W-x
HR01
R/W-x
R/W-x
R/W-x
R/W-x
MIN10
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MIN01
R/W-x
R/W-x
R/W-x
SEC10
R/W-x
R/W-x
SEC01
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 HR10: Binary Coded Decimal value of hours bits, 10 digits; contains a value from 0 to 2
bit 27-24 HR01: Binary Coded Decimal value of hours bits, 1 digit; contains a value from 0 to 9
bit 23-20 MIN10: Binary Coded Decimal value of minutes bits, 10 digits; contains a value from 0 to 5
bit 19-16 MIN01: Binary Coded Decimal value of minutes bits, 1 digit; contains a value from 0 to 9
bit 15-12 SEC10: Binary Coded Decimal value of seconds bits, 10 digits; contains a value from 0 to 5
bit 11-8
SEC01: Binary Coded Decimal value of seconds bits, 1 digit; contains a value from 0 to 9
bit 7-0
Unimplemented: Read as ‘0’
2015-2021 Microchip Technology Inc.
DS60001361J-page 329
PIC32MZ Graphics (DA) Family
REGISTER 20-6:
Bit
Range
31:24
23:16
15:8
7:0
ALRMDATE: ALARM DATE VALUE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
Bit
27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MONTH10
R/W-x
R/W-x
R/W-x
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
R/W-x
R/W-x
R/W-x
MONTH01
R/W-x
R/W-x
R/W-x
DAY10
R/W-x
R/W-x
DAY01
U-0
U-0
U-0
U-0
—
—
—
—
R/W-x
R/W-x
R/W-x
R/W-x
WDAY01
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-20 MONTH10: Binary Coded Decimal value of months bits, 10 digits; contains a value from 0 to 1
bit 19-16 MONTH01: Binary Coded Decimal value of months bits, 1 digit; contains a value from 0 to 9
bit 15-12 DAY10: Binary Coded Decimal value of days bits, 10 digits; contains a value from 0 to 3
bit 11-8
DAY01: Binary Coded Decimal value of days bits, 1 digit; contains a value from 0 to 9
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
WDAY01: Binary Coded Decimal value of weekdays bits, 1 digit; contains a value from 0 to 6
DS60001361J-page 330
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
The SPI/I2S module is compatible with Motorola® SPI
and SIOP interfaces.
21.0 SERIAL PERIPHERAL
INTERFACE (SPI) AND
INTER-IC SOUND (I2S)
Note:
Some of the key features of the SPI module are:
•
•
•
•
•
Host and Client modes support
Four different clock formats
Enhanced Framed SPI protocol support
User-configurable 8-bit, 16-bit and 32-bit data width
Separate SPI FIFO buffers for receive and transmit
- FIFO buffers act as 4/8/16-level deep FIFOs
based on 32/16/8-bit data width
• Programmable interrupt event on every 8-bit,
16-bit and 32-bit data transfer
• Operation during Sleep and Idle modes
• Audio Codec Support:
- I2S protocol
- Left-justified
- Right-justified
- PCM
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 23. “Serial
Peripheral
Interface
(SPI)”
(DS60001106), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The SPI/I2S module is a synchronous serial interface
that is useful for communicating with external
peripherals and other microcontroller devices, as well
as digital audio devices. These peripheral devices may
be Serial EEPROMs, Shift registers, display drivers,
Analog-to-Digital Converters (ADC), etc.
SPI/I2S MODULE BLOCK DIAGRAM
FIGURE 21-1:
Internal
Data Bus
SPIxBUF
Read
Write
SPIxRXB FIFO
FIFOs Share Address SPIxBUF
SPIxTXB FIFO
Transmit
Receive
SPIxSR
SDIx
bit 0
SDOx
SSx/FSYNC
SPI Select
and Frame
Sync Control
Shift
Control
Clock
Control
MCLKSEL
Edge
Select
SCKx
Note: Access SPIxTXB and SPIxRXB FIFOs through the SPIxBUF register.
2015-2021 Microchip Technology Inc.
REFCLKO1
Baud Rate
Generator
PBCLK2
MSTEN
DS60001361J-page 331
SPI Control Registers
SPI1 THROUGH SPI6 REGISTER MAP
1000 SPI1CON
1010 SPI1STAT
1020 SPI1BUF
1030 SPI1BRG
1040 SPI1CON2
1200 SPI2CON
1210 SPI2STAT
1220 SPI2BUF
1230 SPI2BRG
1240 SPI2CON2
2015-2021 Microchip Technology Inc.
1400 SPI3CON
1410 SPI3STAT
1420 SPI3BUF
1430 SPI3BRG
1440 SPI3CON2
31/15
30/14
29/13
28/12
27/11
31:16 FRMEN FRMSYNC FRMPOL
MSSEN
FRMSYPW
15:0
ON
—
SIDL
DISSDO
MODE32
31:16
—
—
—
15:0
—
—
—
26/10
25/9
24/8
FRMCNT
MODE16
SMP
23/7
SPIBUSY
—
—
20/4
—
—
—
SSEN
CKP
MSTEN
DISSDI
—
—
—
SRMT
SPIROV
SPIRBE
SPITUR
31:16
21/5
MCLKSEL
CKE
RXBUFELM
FRMERR
22/6
19/3
18/2
17/1
—
—
SPIFE
STXISEL
16/0
ENHBUF 0000
SRXISEL
TXBUFELM
—
SPITBE
—
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
—
—
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
31:16 FRMEN FRMSYNC FRMPOL
MSSEN
FRMSYPW
DISSDO
MODE32
SPI
15:0
SGNEXT
—
15:0
ON
—
SIDL
31:16
—
—
—
15:0
—
—
—
—
—
—
—
—
SPIRBF 00A8
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRG
—
IGNROV
—
MODE16
—
SMP
AUDEN
—
—
—
—
—
—
—
SSEN
CKP
MSTEN
DISSDI
—
—
—
SRMT
SPIROV
SPIRBE
CKE
SPIBUSY
—
—
SPITUR
31:16
AUDMOD
SPIFE
STXISEL
SRXISEL
TXBUFELM
—
SPITBE
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
31:16 FRMEN FRMSYNC FRMPOL
MSSEN
FRMSYPW
DISSDO
MODE32
SPI
15:0
SGNEXT
—
15:0
ON
—
SIDL
31:16
—
—
—
15:0
—
—
—
IGNROV
—
—
SMP
—
SPIRBF 0008
FRMERR
SPIBUSY
—
—
31:16
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AUDEN
—
—
—
—
—
—
—
SSEN
CKP
MSTEN
DISSDI
—
—
—
SRMT
SPIROV
SPIRBE
CKE
SPITUR
AUDMOD
SPIFE
STXISEL
SPITBE
—
SRXISEL
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
SPI
15:0
SGNEXT
—
IGNROV
—
—
IGNTUR
—
AUDEN
0000
SPIRBF 0008
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
AUD
MONO
—
BRG
—
0000
0000
SPITBF
DATA
15:0
0000
ENHBUF 0000
TXBUFELM
—
0000
0000
MCLKSEL
RXBUFELM
0000
0000
AUD
MONO
IGNTUR
0C00
0000
SPITBF
BRG
FRMCNT
MODE16
—
0000
ENHBUF 0000
DATA
15:0
0000
0000
MCLKSEL
RXBUFELM
FRMERR
—
AUD
MONO
IGNTUR
FRMCNT
0000
0000
SPITBF
DATA
15:0
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF82_#)
TABLE 21-1:
—
—
—
—
0000
0000
AUDMOD
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and
INV Registers” for more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 332
21.1
SPI1 THROUGH SPI6 REGISTER MAP (CONTINUED)
1600 SPI4CON
1610 SPI4STAT
1620 SPI4BUF
1630 SPI4BRG
1640 SPI4CON2
1810 SPI5STAT
1820 SPI5BUF
1830 SPI5BRG
1840 SPI5CON2
1A00 SPI6CON
1A10 SPI6STAT
1A20 SPI6BUF
1A30 SPI6BRG
DS60001361J-page 333
1A40 SPI6CON2
30/14
29/13
28/12
27/11
31:16 FRMEN FRMSYNC FRMPOL
MSSEN
FRMSYPW
15:0
ON
—
SIDL
DISSDO
MODE32
31:16
—
—
—
15:0
—
—
—
26/10
25/9
24/8
FRMCNT
MODE16
SMP
23/7
SPIBUSY
—
—
20/4
—
—
—
SSEN
CKP
MSTEN
DISSDI
—
—
—
SRMT
SPIROV
SPIRBE
SPITUR
31:16
21/5
MCLKSEL
CKE
RXBUFELM
FRMERR
22/6
19/3
18/2
17/1
—
—
SPIFE
STXISEL
16/0
ENHBUF 0000
SRXISEL
TXBUFELM
—
SPITBE
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
31:16 FRMEN FRMSYNC FRMPOL
MSSEN
FRMSYPW
15:0
ON
—
SIDL
DISSDO
MODE32
31:16
—
—
—
15:0
—
—
—
SPI
15:0
SGNEXT
—
IGNROV
—
SPIRBF 0008
0000
—
—
IGNTUR
SMP
AUDEN
SPIBUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AUD
MONO
—
—
—
—
—
—
—
SSEN
CKP
MSTEN
DISSDI
—
—
—
SRMT
SPIROV
SPIRBE
SPITUR
31:16
—
MCLKSEL
CKE
RXBUFELM
FRMERR
0000
—
BRG
FRMCNT
MODE16
—
AUDMOD
SPIFE
STXISEL
SPITBE
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
SPI
SGNEXT
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
IGNROV
IGNTUR
AUDEN
—
—
31:16 FRMEN FRMSYNC FRMPOL
MSSEN
FRMSYPW
15:0
ON
—
SIDL
DISSDO
MODE32
31:16
—
—
—
15:0
—
—
—
SMP
0000
SPITBF
SPIRBF 0008
SPIBUSY
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
AUD
MONO
—
—
—
MCLKSEL
—
—
—
SSEN
CKP
MSTEN
DISSDI
—
—
—
SRMT
SPIROV
SPIRBE
RXBUFELM
FRMERR
—
BRG
CKE
SPITUR
AUDMOD
SPIFE
STXISEL
SPITBE
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
SPI
15:0
SGNEXT
—
IGNROV
—
—
IGNTUR
—
AUDEN
0000
0000
0000
SPITBF
SPIRBF 0008
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
AUD
MONO
—
BRG
—
0000
ENHBUF 0000
SRXISEL
TXBUFELM
—
0000
0000
DATA
15:0
0000
0000
—
FRMCNT
0000
0000
31:16
MODE16
—
0000
ENHBUF 0000
SRXISEL
TXBUFELM
—
0000
0000
DATA
15:0
0000
0000
SPITBF
DATA
15:0
All Resets
31/15
—
—
—
—
0000
0000
AUDMOD
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and
INV Registers” for more information.
PIC32MZ Graphics (DA) Family
1800 SPI5CON
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF82_#)
2015-2021 Microchip Technology Inc.
TABLE 21-1:
PIC32MZ Graphics (DA) Family
REGISTER 21-1:
Bit
Range
31:24
23:16
15:8
7:0
SPIxCON: SPI CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMEN
FRMSYNC
FRMPOL
MSSEN
FRMSYPW
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
FRMCNT
R/W-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
MCLKSEL(1)
—
—
—
—
—
SPIFE
ENHBUF(1)
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ON
—
SIDL
DISSDO(4)
MODE32
MODE16
SMP
CKE(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEN
CKP(3)
MSTEN
DISSDI(4)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
STXISEL
SRXISEL
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
FRMEN: Framed SPI Support bit
1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)
0 = Framed SPI support is disabled
bit 30
FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only)
1 = Frame sync pulse input (Client mode)
0 = Frame sync pulse output (Host mode)
bit 29
FRMPOL: Frame Sync / SPI Select Polarity bit (Framed SPI or Host Transmit modes only)
1 = Frame pulse or SSx pin is active-high
0 = Frame pulse or SSx is active-low
bit 28
MSSEN: Host Mode SPI Select Enable bit
1 = SPI select support enabled. The SS pin is automatically driven during transmission in
Host mode. Polarity is determined by the FRMPOL bit.
0 = SPI select support is disabled.
bit 27
FRMSYPW: Frame Sync Pulse Width bit
1 = Frame sync pulse is one character wide
0 = Frame sync pulse is one clock wide
bit 26-24 FRMCNT: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per
pulse. This bit is only valid in Framed mode.
111 = Reserved
110 = Reserved
101 = Generate a frame sync pulse on every 32 data characters
100 = Generate a frame sync pulse on every 16 data characters
011 = Generate a frame sync pulse on every 8 data characters
010 = Generate a frame sync pulse on every 4 data characters
001 = Generate a frame sync pulse on every 2 data characters
000 = Generate a frame sync pulse on every data character
bit 23
MCLKSEL: Host Clock Enable bit(1)
1 = REFCLKO1 is used by the Baud Rate Generator
0 = PBCLK2 is used by the Baud Rate Generator
bit 22-18 Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
This bit can only be written when the ON bit = 0. Refer to Section 44.0 “Electrical Characteristics” for
maximum clock frequency requirements.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual
value of the CKP bit.
This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see
Section 12.4 “Peripheral Pin Select (PPS)” for more information).
DS60001361J-page 334
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 21-1:
SPIxCON: SPI CONTROL REGISTER (CONTINUED)
bit 17
SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only)
1 = Frame synchronization pulse coincides with the first bit clock
0 = Frame synchronization pulse precedes the first bit clock
bit 16
ENHBUF: Enhanced Buffer Enable bit(1)
1 = Enhanced Buffer mode is enabled
0 = Enhanced Buffer mode is disabled
bit 15
ON: SPI/I2S Module On bit
1 = SPI/I2S module is enabled
0 = SPI/I2S module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters in Idle mode
0 = Continue operation in Idle mode
bit 12
DISSDO: Disable SDOx pin bit(4)
1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register
0 = SDOx pin is controlled by the module
bit 11-10 MODE: 32/16-Bit Communication Select bits
When AUDEN = 1:
MODE32
MODE16
Communication
1
1
24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
1
0
32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
0
1
16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame
0
0
16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame
When AUDEN = 0:
MODE32
MODE16
Communication
1
x
32-bit
0
1
16-bit
0
0
8-bit
SMP: SPI Data Input Sample Phase bit
Host mode (MSTEN = 1):
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Client mode (MSTEN = 0):
SMP value is ignored when SPI is used in Client mode. The module always uses SMP = 0.
CKE: SPI Clock Edge Select bit(2)
1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
SSEN: SPI Select Enable (Client mode) bit
1 = SSx pin used for Client mode
0 = SSx pin not used for Client mode, pin controlled by port function.
CKP: Clock Polarity Select bit(3)
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 9
bit 8
bit 7
bit 6
Note 1:
2:
3:
4:
This bit can only be written when the ON bit = 0. Refer to Section 44.0 “Electrical Characteristics” for
maximum clock frequency requirements.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual
value of the CKP bit.
This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see
Section 12.4 “Peripheral Pin Select (PPS)” for more information).
2015-2021 Microchip Technology Inc.
DS60001361J-page 335
PIC32MZ Graphics (DA) Family
REGISTER 21-1:
bit 5
SPIxCON: SPI CONTROL REGISTER (CONTINUED)
MSTEN: Host Mode Enable bit
1 = Host mode
0 = Client mode
DISSDI: Disable SDI bit(4)
1 = SDI pin is not used by the SPI module (pin is controlled by PORT function)
0 = SDI pin is controlled by the SPI module
STXISEL: SPI Transmit Buffer Empty Interrupt Mode bits
11 = Interrupt is generated when the buffer is not full (has one or more empty elements)
10 = Interrupt is generated when the buffer is empty by one-half or more
01 = Interrupt is generated when the buffer is completely empty
00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are
complete
SRXISEL: SPI Receive Buffer Full Interrupt Mode bits
11 = Interrupt is generated when the buffer is full
10 = Interrupt is generated when the buffer is full by one-half or more
01 = Interrupt is generated when the buffer is not empty
00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)
bit 4
bit 3-2
bit 1-0
Note 1:
2:
3:
4:
This bit can only be written when the ON bit = 0. Refer to Section 44.0 “Electrical Characteristics” for
maximum clock frequency requirements.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual
value of the CKP bit.
This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see
Section 12.4 “Peripheral Pin Select (PPS)” for more information).
DS60001361J-page 336
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 21-2:
Bit
Range
31:24
23:16
15:8
7:0
SPIxCON2: SPI CONTROL REGISTER 2
Bit
31/23/15/7
Bit
Bit
30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
Bit
Bit
26/18/10/2 25/17/9/1 24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SPISGNEXT
—
—
FRMERREN
SPIROVEN
R/W-0
U-0
U-0
U-0
R/W-0
U-0
AUDEN(1)
—
—
—
AUDMONO(1,2)
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
SPITUREN IGNROV
R/W-0
IGNTUR
R/W-0
AUDMOD(1,2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
SPISGNEXT: Sign Extend Read Data from the RX FIFO bit
1 = Data from RX FIFO is sign extended
0 = Data from RX FIFO is not sign extened
bit 14-13 Unimplemented: Read as ‘0’
bit 12
FRMERREN: Enable Interrupt Events via FRMERR bit
1 = Frame Error overflow generates error events
0 = Frame Error does not generate error events
bit 11
SPIROVEN: Enable Interrupt Events via SPIROV bit
1 = Receive overflow generates error events
0 = Receive overflow does not generate error events
bit 10
SPITUREN: Enable Interrupt Events via SPITUR bit
1 = Transmit Underrun Generates Error Events
0 = Transmit Underrun Does Not Generates Error Events
bit 9
IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions)
1 = A ROV is not a critical error; during ROV data in the fifo is not overwritten by receive data
0 = A ROV is a critical error which stop SPI operation
bit 8
IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions)
1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty
0 = A TUR is a critical error which stop SPI operation
bit 7
AUDEN: Enable Audio CODEC Support bit(1)
1 = Audio protocol enabled
0 = Audio protocol disabled
bit 6-5
Unimplemented: Read as ‘0’
bit 3
AUDMONO: Transmit Audio Data Format bit(1,2)
1 = Audio data is mono (Each data word is transmitted on both left and right channels)
0 = Audio data is stereo
bit 2
Unimplemented: Read as ‘0’
bit 1-0
AUDMOD: Audio Protocol Mode bit(1,2)
11 = PCM/DSP mode
10 = Right Justified mode
01 = Left Justified mode
00 = I2S mode
Note 1:
2:
This bit can only be written when the ON bit = 0.
This bit is only valid for AUDEN = 1.
2015-2021 Microchip Technology Inc.
DS60001361J-page 337
PIC32MZ Graphics (DA) Family
REGISTER 21-3:
Bit
Range
31:24
23:16
15:8
7:0
SPIxSTAT: SPI STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
R-0
—
—
—
U-0
U-0
U-0
R-0
R-0
—
—
—
U-0
U-0
U-0
R/C-0, HS
R-0
U-0
U-0
R-0
—
—
—
FRMERR
SPIBUSY
—
—
SPITUR
RXBUFELM
R-0
R-0
R-0
TXBUFELM
R-0
R/W-0
R-0
U-0
R-1
U-0
R-0
R-0
SRMT
SPIROV
SPIRBE
—
SPITBE
—
SPITBF
SPIRBF
Legend:
C = Clearable bit
HS = Hardware Set
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 RXBUFELM: Receive Buffer Element Count bits (valid only when ENHBUF = 1)
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFELM: Transmit Buffer Element Count bits (valid only when ENHBUF = 1)
bit 15-13 Unimplemented: Read as ‘0’
bit 12
FRMERR: SPI Frame Error status bit
1 = Frame error detected
0 = No Frame error detected
This bit is only valid when FRMEN = 1.
bit 11
SPIBUSY: SPI Activity Status bit
1 = SPI peripheral is currently busy with some transactions
0 = SPI peripheral is currently idle
bit 10-9
Unimplemented: Read as ‘0’
bit 8
SPITUR: Transmit Under Run bit
1 = Transmit buffer has encountered an underrun condition
0 = Transmit buffer has no underrun condition
This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling
the module.
bit 7
SRMT: Shift Register Empty bit (valid only when ENHBUF = 1)
1 = When SPI module shift register is empty
0 = When SPI module shift register is not empty
bit 6
SPIROV: Receive Overflow Flag bit
1 = A new data is completely received and discarded. The user software has not read the previous data in
the SPIxBUF register.
0 = No overflow has occurred
This bit is set in hardware; can only be cleared (= 0) in software.
bit 5
SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1)
1 = RX FIFO is empty (CRPTR = SWPTR)
0 = RX FIFO is not empty (CRPTR SWPTR)
bit 4
Unimplemented: Read as ‘0’
DS60001361J-page 338
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 21-3:
SPIxSTAT: SPI STATUS REGISTER
bit 3
SPITBE: SPI Transmit Buffer Empty Status bit
1 = Transmit buffer, SPIxTXB is empty
0 = Transmit buffer, SPIxTXB is not empty
Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR.
Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.
bit 2
Unimplemented: Read as ‘0’
bit 1
SPITBF: SPI Transmit Buffer Full Status bit
1 = Transmit not yet started, SPITXB is full
0 = Transmit buffer is not full
Standard Buffer Mode:
Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB.
Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR.
Enhanced Buffer Mode:
Set when CWPTR + 1 = SRPTR; cleared otherwise
bit 0
SPIRBF: SPI Receive Buffer Full Status bit
1 = Receive buffer, SPIxRXB is full
0 = Receive buffer, SPIxRXB is not full
Standard Buffer Mode:
Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer Mode:
Set when SWPTR + 1 = CRPTR; cleared otherwise
2015-2021 Microchip Technology Inc.
DS60001361J-page 339
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 340
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
22.0
Note:
SERIAL QUAD INTERFACE
(SQI)
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 46. “Serial Quad
Interface (SQI)” (DS60001244), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The SQI module is a synchronous serial interface that
provides access to serial Flash memories and other
serial devices. The SQI module supports Single Lane
(identical to SPI), Dual Lane, and Quad Lane modes.
The following are some of the key features of the SQI
module:
• Supports Single, Dual, and Quad Lane modes
• Supports Single Data Rate (SDR) and Double
Data Rate (DDR) modes
• Programmable command sequence
• eXecute-In-Place (XIP)
FIGURE 22-1:
• Data transfer:
- Programmed I/O mode (PIO)
- Buffer descriptor DMA
• Supports SPI Mode 0 and Mode 3
• Programmable Clock Polarity (CPOL) and Clock
Phase (CPHA) bits
• Supports up to two Chip Selects
• Supports up to four bytes of Flash address
• Programmable interrupt thresholds
• 32-byte transmit data buffer
• 32-byte receive data buffer
• 4-word controller buffer
Note:
Once the SQI module is configured,
external devices are memory mapped
into KSEG2 (see Figure 4-1 through
Figure 4-2 in Section 4.0 “Memory
Organization” for more information).
The MMU must be enabled and the TLB
must be set up to access this memory
(see Section 50. “CPU for Devices with
MIPS32® microAptiv™ and M-Class
Cores” (DS60001192) in the “PIC32
Family Reference Manual” for more
information).
SQI MODULE BLOCK DIAGRAM
PBCLK5(2)
REFCLKO2(1)
(TBC)
SQID0
Control
Buffer
SQID1
System Bus
Bus Client
Bus Host
Note
Control and
Status
Registers
(PIO)
DMA
SQID2
Transmit
Buffer
SQID3
SQI Host
Interface
Receive
Buffer
SQICLK
SQICS0
SQICS1
1:
When configuring the REFCLKO2 clock source, a value of ‘0’ for the ROTRIM bits must be selected.
REFCLKO2 must be turned on before SQI Special Function Registers (SFR) access.
2:
This clock source is only used for SQI Special Function Register (SFR) access.
2015-2021 Microchip Technology Inc.
DS60001361J-page 341
SQI Control Registers
Register
Name
Bit Range
SERIAL QUADRATURE INTERFACE (SQI) REGISTER MAP
Virtual Address
(BF8E_#)
TABLE 22-1:
2000
SQI1
XCON1
31:16
SQI1
XCON2
31:16
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
BURSTEN
—
HOLD
WP
31:16
—
—
—
—
—
—
—
2004
2008 SQI1CFG
200C SQI1CON
31/15
30/14
—
—
15:0
29/13
28/12
SDRCMD DDRDATA
—
—
—
—
31:16
—
—
15:0
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
201C
SQI1
INTEN
24/8
15:0
31:16
23/7
DDR
DUMMY
DDR
MODE
DDR
ADDR
DDRCMD
TYPEDATA
—
—
DEVSEL
—
22/6
—
—
—
19/3
18/2
ADDRBYTES
TYPEMODE
—
MODEBYTES
CSEN
20/4
DUMMYBYTES
TYPEDUMMY
—
21/5
—
TYPEADDR
—
17/1
16/0
READOPCODE
0000
TYPECMD
0000
—
—
—
RXBUFST
TXBUFST
RESET
MODECODE
SQIEN
—
—
—
SCHECK DDRMODE DASSERT
DATAEN
LSBF
CPOL
DEVSEL
CON
BUFRST
—
—
—
—
—
—
—
CLKDIV
—
—
—
—
—
—
TXCMDTHR
—
—
—
—
—
—
TXINTTHR
—
—
PKT
DMAEIE
COMPIE
—
—
0000
0000
CPHA
MODE
LANEMODE
0000
0000
CMDINIT
TXRXCOUNT
31:16
SQI1
2014
CMDTHR 15:0
2018
25/9
15:0
—
SQI1
INTTHR
26/10
READOPCODE
31:16
SQI1
CLKCON 15:0
2010
27/11
All Resets
Bits
0000
0000
—
—
—
—
—
CLKDIV
—
—
—
—
—
—
STABLE
EN
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
RXCMDTHR
—
—
—
—
0000
RXINTTHR
0000
0000
—
—
—
—
—
—
—
—
—
—
0000
BD
DONEIE
CON
THRIE
CON
EMPTYIE
CON
FULLIE
RX
THRIE
RX
FULLIE
RX
EMPTYIE
TX
THRIE
TX
FULLIE
TX
EMPTYIE
0000
—
—
—
—
—
—
—
—
—
—
0000
BD
DONEIF
CON
THRIF
CON
EMPTYIF
CON
FULLIF
RX
THRIF
RX
FULLIF
RX
EMPTYIF
TX
THRIF
TX
FULLIF
TX
EMPTYIF
0000
2015-2021 Microchip Technology Inc.
2020
SQI1
INTSTAT
2024
31:16
SQI1
TXDATA 15:0
TXDATA
0000
TXDATA
0000
2028
31:16
SQI1
RXDATA 15:0
RXDATA
0000
15:0
—
—
—
—
PKT
DMAEIF
COMPIF
RXDATA
0000
202C
SQI1
STAT1
31:16
—
—
—
—
—
—
—
—
—
—
TXBUFFREE
15:0
—
—
—
—
—
—
—
—
—
—
RXBUFCNT
2030
SQI1
STAT2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
SDID3
SDID2
SDID1
SDID0
—
RXUN
TXOV
00x0
2034
SQI1
BDCON
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
START
POLLEN
DMAEN
0000
CONAVAIL
0000
0000
CMDSTAT
0000
SQI1BD 31:16
2038
CURADD 15:0
BDCURRADDR
0000
BDCURRADDR
0000
SQI1BD 31:16
2040
BASEADD 15:0
BDADDR
0000
BDADDR
0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 342
22.1
Register
Name
Bit Range
SERIAL QUADRATURE INTERFACE (SQI) REGISTER MAP (CONTINUED)
Virtual Address
(BF8E_#)
2044
SQI1BD
STAT
31:16
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
—
—
—
—
—
—
—
—
—
—
15:0
21/5
20/4
19/3
18/2
17/1
DMA
START
BDSTATE
16/0
DMAACTV 0000
BDCON
—
—
—
—
—
—
0000
SQI1BD 31:16
2048
POLLCON 15:0
—
SQI1BD 31:16
204C
TXDSTAT 15:0
—
—
—
—
—
—
SQI1BD 31:16
2050
RXDSTAT 15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CON
THRISE
CON
EMPTYISE
CON
FULLISE
RX
THRISE
RX
FULLISE
RX
EMPTYISE
TX
THRISE
TX
FULLISE
TX
0000
EMPTYISE
2054 SQI1THR
—
All Resets
2015-2021 Microchip Technology Inc.
TABLE 22-1:
—
—
—
—
—
—
—
—
POLLCON
TXSTATE
—
—
—
—
—
0000
—
TXBUFCNT
—
RXSTATE
0000
TXCURBUFLEN
—
—
0000
—
0000
RXBUFCNT
0000
RXCURBUFLEN
0000
—
—
—
—
THRES
0000
0000
2058
SQI1INT
SIGEN
15:0
—
—
205C
31:16
SQI1
TAPCON 15:0
—
—
DDRCLKINDLY
SDRDATINDLY
DDRDATINDLY
0000
—
—
SDRCLKINDLY
DATAOUTDLY
CLKOUTDLY
0000
31:16
SQI1
2060
MEMSTAT 15:0
—
—
SQI1
XCON3
31:16
—
—
—
SQI1
XCON4
31:16
—
—
—
2064
2068
—
—
—
—
—
—
—
—
STATPOS
TYPESTAT
STATCMD
15:0
15:0
—
DMAEIS
PKT
BD
E
DONEISE DONEISE
INIT1
INIT1COUNT
SCHECK
INIT1TYPE
INIT1CMD2
INIT2
INIT2COUNT
SCHECK
INIT2CMD2
INIT2TYPE
STATBYTES
0000
0000
INIT1CMD3
0000
INIT1CMD1
0000
INIT2CMD3
0000
INIT2CMD1
0000
DS60001361J-page 343
PIC32MZ Graphics (DA) Family
0000
—
PIC32MZ Graphics (DA) Family
REGISTER 22-1:
Bit
Range
SQI1XCON1: SQI XIP CONTROL REGISTER 1
Bit
Bit
31/23/15/7 30/22/14/6
31:24
23:16
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
R/W-0
R/W-0
—
—
SDRCMD
DDRDATA
R/W-0
R/W-0
R/W-0
R/W-0
DUMMYBYTES
R/W-0
15:8
R/W-0
R/W-0
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
DDRDUMMY DDRMODE DDRADDR DDRCMD(1)
R/W-0
R/W-0
ADDRBYTES
R/W-0
R/W-0
R/W-0
R/W-0
TYPEDUMMY
R/W-0
R/W-0
READOPCODE
R/W-0
READOPCODE
7:0
R/W-0
R/W-0
R/W-0
TYPEDATA
R/W-0
R/W-0
TYPEMODE
R/W-0
TYPEADDR
R/W-0
R/W-0
TYPECMD
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29
SDRCMD: SQI Command in SDR Mode bit
1 = SQI command is in SDR mode and SQI data is in DDR mode
0 = SQI command is in DDR mode and SQI data is in DDR mode
bit 28
DDRDATA: SQI Data DDR Mode bit
1 = SQI data bytes are transferred in DDR mode
0 = SQI data bytes are transferred in SDR mode
bit 27
DDRDUMMY: SQI Dummy DDR Mode bit
1 = SQI dummy bytes are transferred in DDR mode
0 = SQI dummy bytes are transferred in SDR mode
bit 26
DDRMODE: SQI DDR Mode bit
1 = SQI mode bytes are transferred in DDR mode
0 = SQI mode bytes are transferred in SDR mode
bit 25
DDRADDR: SQI Address Mode bit
1 = SQI address bytes are transferred in DDR mode
0 = SQI address bytes are transferred in SDR mode
bit 24
DDRCMD: SQI DDR Command Mode bit(1)
1 = SQI command bytes are transferred in DDR mode
0 = SQI command bytes are transferred in SDR mode
bit 23-21 DUMMYBYTES: Transmit Dummy Bytes bits
111 = Transmit seven dummy bytes after the address bytes
•
•
•
011 = Transmit three dummy bytes after the address bytes
010 = Transmit two dummy bytes after the address bytes
001 = Transmit one dummy bytes after the address bytes
000 = Transmit zero dummy bytes after the address bytes
Note 1:
When DDRCMD is set to ‘0’, the SQI module will ignore the value in the SDRCMD bit.
DS60001361J-page 344
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 22-1:
SQI1XCON1: SQI XIP CONTROL REGISTER 1 (CONTINUED)
bit 20-18 ADDRBYTES: Address Cycle bits
111 = Reserved
•
•
•
101 = Reserved
100 = Four address bytes
011 = Three address bytes
010 = Two address bytes
001 = One address bytes
000 = Zero address bytes
bit 17-10 READOPCODE: Op code Value for Read Operation bits
These bits contain the 8-bit op code value for read operation.
bit 9-8
TYPEDATA: SQI Type Data Enable bits
The boot controller will receive the data in Single Lane, Dual Lane, or Quad Lane.
11 = Reserved
10 = Quad Lane mode data is enabled
01 = Dual Lane mode data is enabled
00 = Single Lane mode data is enabled
bit 7-6
TYPEDUMMY: SQI Type Dummy Enable bits
The boot controller will send the dummy in Single Lane, Dual Lane, or Quad Lane.
11 = Reserved
10 = Quad Lane mode dummy is enabled
01 = Dual Lane mode dummy is enabled
00 = Single Lane mode dummy is enabled
bit 5-4
TYPEMODE: SQI Type Mode Enable bits
The boot controller will send the mode in Single Lane, Dual Lane, or Quad Lane.
11 = Reserved
10 = Quad Lane mode is enabled
01 = Dual Lane mode is enabled
00 = Single Lane mode is enabled
bit 3-2
TYPEADDR: SQI Type Address Enable bits
The boot controller will send the address in Single Lane, Dual Lane, or Quad Lane.
11 = Reserved
10 = Quad Lane mode address is enabled
01 = Dual Lane mode address is enabled
00 = Single Lane mode address is enabled
bit 1-0
TYPECMD: SQI Type Command Enable bits
The boot controller will send the command in Single Lane, Dual Lane, or Quad Lane.
11 = Reserved
10 = Quad Lane mode command is enabled
01 = Dual Lane mode command is enabled
00 = Single Lane mode command is enabled
Note 1:
When DDRCMD is set to ‘0’, the SQI module will ignore the value in the SDRCMD bit.
2015-2021 Microchip Technology Inc.
DS60001361J-page 345
PIC32MZ Graphics (DA) Family
REGISTER 22-2:
Bit
Range
31:24
23:16
15:8
7:0
SQI1XCON2: SQI XIP CONTROL REGISTER 2
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
R/W-0
R/W-0
R/W-0
DEVSEL
R/W-0
R/W-0
R/W-0
MODEBYTES
R/W-0
R/W-0
MODECODE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-12 Unimplemented: Read as ‘0’
bit 11-10 DEVSEL: Device Select bits
11 = Reserved
10 = Reserved
01 = Device 1 is selected
00 = Device 0 is selected
bit 9-8
MODEBYTES: Mode Byte Cycle Enable bits
11 = Three cycles
10 = Two cycles
01 = One cycle
00 = Zero cycles
bit 7-0
MODECODE: Mode Code Value bits
These bits contain the 8-bit code value for the mode bits.
DS60001361J-page 346
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 22-3:
Bit
Range
31:24
23:16
15:8
7:0
SQI1CFG: SQI CONFIGURATION REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
R/W-0
U-0
R/W-0
R/W-0
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
CON
BUFRST
RX
BUFRST
TX
BUFRST
RESET
U-0
SQIEN
—
DATAEN
CSEN
U-0
r-0
r-0
R/W-0
r-0
R/W-0
R/W-0
—
—
—
BURSTEN(1)
—
HOLD
WP
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
LSBF
CPOL
CPHA
MODE
Legend:
HC = Hardware Cleared
r = Reserved
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25-24 CSEN: Chip Select Output Enable bits
11 = Chip Select 0 and Chip Select 1 are used
10 = Chip Select 1 is used (Chip Select 0 is not used)
01 = Chip Select 0 is used (Chip Select 1 is not used)
00 = Chip Select 0 and Chip Select 1 are not used
bit 23
SQIEN: SQI Enable bit
1 = SQI module is enabled
0 = SQI module is disabled
bit 22
Unimplemented: Read as ‘0’
bit 21-20 DATAEN: Data Output Enable bits
11 = Reserved
10 = SQID3-SQID0 outputs are enabled
01 = SQID1 and SQID0 data outputs are enabled
00 = SQID0 data output is enabled
bit 19
CONBUFRST: Control Buffer Reset bit
1 = A reset pulse is generated clearing the control buffer
0 = A reset pulse is not generated
bit 18
RXBUFRST: Receive Buffer Reset bit
1 = A reset pulse is generated clearing the receive buffer
0 = A reset pulse is not generated
bit 17
TXBUFRST: Transmit Buffer Reset bit
1 = A reset pulse is generated clearing the transmit buffer
0 = A reset pulse is not generated
bit 16
RESET: Software Reset Select bit
This bit is automatically cleared by the SQI module. All of the internal state machines and buffer pointers
are reset by this reset pulse.
1 = A reset pulse is generated
0 = A reset pulse is not generated
bit 15
Unimplemented: Read as ‘0’
bit 14-13 Reserved: Must be programmed as ‘0’
Note 1:
This bit must be programmed as ‘1’.
2015-2021 Microchip Technology Inc.
DS60001361J-page 347
PIC32MZ Graphics (DA) Family
REGISTER 22-3:
SQI1CFG: SQI CONFIGURATION REGISTER (CONTINUED)
bit 12
BURSTEN: Burst Configuration bit(1)
1 = Burst is enabled
0 = Burst is not enabled
bit 11
Reserved: Must be programmed as ‘0’
bit 10
HOLD: Hold bit
In Single Lane or Dual Lane mode, this bit is used to drive the SQID3 pin, which can be used for devices
with a HOLD input pin. The meaning of the values for this bit will depend on the device to which SQID3 is
connected.
bit 9
WP: Write Protect bit
In Single Lane or Dual Lane mode, this bit is used to drive the SQID2 pin, which can be used with devices
with a write-protect pin. The meaning of the values for this bit will depend on the device to which SQID2 is
connected.
bit 8-6
Unimplemented: Read as ‘0’
bit 5
LSBF: Data Format Select bit
1 = LSB is sent or received first
0 = MSB is sent or received first
bit 4
CPOL: Clock Polarity Select bit
1 = Active-low SQICLK (SQICLK high is the Idle state)
0 = Active-high SQICLK (SQICLK low is the Idle state)
bit 3
CPHA: Clock Phase Select bit
1 = SQICLK starts toggling at the start of the first data bit
0 = SQICLK starts toggling at the middle of the first data bit
bit 2-0
MODE: Mode Select bits
111 = Reserved
•
•
•
100 = Reserved
011 = XIP mode is selected (when this mode is entered, the module behaves as if executing in place (XIP),
but uses the register data to control timing)
010 = DMA mode is selected
001 = CPU mode is selected (the module is controlled by the CPU in PIO mode. This mode is entered when
leaving Boot or XIP mode)
000 = Reserved
Note 1:
This bit must be programmed as ‘1’.
DS60001361J-page 348
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 22-4:
Bit
Range
31:24
23:16
15:8
7:0
SQI1CON: SQI CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
U-0
U-0
U-0
U-0
U-0
U-0
r-0
R/W-0
—
—
—
—
—
—
—
SCHECK(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DDRMODE
DASSERT
R/W-0
R/W-0
DEVSEL
R/W-0
R/W-0
LANEMODE
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
CMDINIT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXRXCOUNT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXRXCOUNT
Legend:
r = Reserved
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25
Reserved: Must be programmed as ‘0’
bit 24
SCHECK: Flash Status Check bit(1)
1 = Check the status of the Flash
0 = Do not check the status of the Flash
bit 23
DDRMODE: Double Data Rate Mode bit
1 = Set the SQI transfers to DDR mode
0 = Set the SQI transfers to SDR mode
bit 22
DASSERT: Chip Select Assert bit
1 = Chip Select is deasserted after transmission or reception of the specified number of bytes
0 = Chip Select is not deasserted after transmission or reception of the specified number of bytes
bit 21-20 DEVSEL: SQI Device Select bits
11 = Reserved
10 = Reserved
01 = Select Device 1
00 = Select Device 0
bit 19-18 LANEMODE: SQI Lane Mode Select bits
11 = Reserved
10 = Quad Lane mode
01 = Dual Lane mode
00 = Single Lane mode
bit 17-16 CMDINIT: Command Initiation Mode Select bits
If it is Transmit, commands are initiated based on a write to the transmit register or the contents of TX
buffer. If CMDINIT is Receive, commands are initiated based on reads to the read register or RX buffer
availability.
11 = Reserved
10 = Receive
01 = Transmit
00 = Idle
bit 15-0
TXRXCOUNT: Transmit/Receive Count bits
These bits specify the total number of bytes to transmit or received (based on CMDINIT).
Note 1:
When this bit is set to ‘1’, the SQI module uses the SQI1MEMSTAT register to control the status check
command process.
2015-2021 Microchip Technology Inc.
DS60001361J-page 349
PIC32MZ Graphics (DA) Family
REGISTER 22-5:
Bit
Range
31:24
23:16
15:8
7:0
SQI1CLKCON: SQI CLOCK CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CLKDIV(1)
R/W-0
R/W-0
R/W-0
CLKDIV(1)
U-0
U-0
U-0
U-0
U-0
U-0
R-0
R/W-0
—
—
—
—
—
—
STABLE
EN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-19 Unimplemented: Read as ‘0’
bit 18-8
CLKDIV: SQI Clock TSQI Frequency Select bit(1)
10000000000 = Base clock TBC is divided by 2048
01000000000 = Base clock TBC is divided by 1024
00100000000 = Base clock TBC is divided by 512
00010000000 = Base clock TBC is divided by 256
00001000000 = Base clock TBC is divided by 128
00000100000 = Base clock TBC is divided by 64
00000010000 = Base clock TBC is divided by 32
00000001000 = Base clock TBC is divided by 16
00000000100 = Base clock TBC is divided by 8
00000000010 = Base clock TBC is divided by 4
00000000001 = Base clock TBC is divided by 2
00000000000 = Base clock TBC
bit 7-2
Unimplemented: Read as ‘0’
bit 1
STABLE: TSQI Clock Stable Select bit
This bit is set to ‘1’ when the SQI clock, TSQI, is stable after writing a ‘1’ to the EN bit.
1 = TSQI clock is stable
0 = TSQI clock is not stable
bit 0
EN: TSQI Clock Enable Select bit
When clock oscillation is stable, the SQI module will set the STABLE bit to ‘1’.
1 = Enable the SQI clock (TSQI) (when clock oscillation is stable, the SQI module sets the STABLE bit to ‘1’)
0 = Disable the SQI clock (TSQI) (the SQI module should stop its clock to enter a low power state); SFRs
can still be accessed, as they use PBCLK5
Note 1:
Refer to Table 44-41 in 44.0 “Electrical Characteristics” for the maximum clock frequency
specifications.
Setting these bits to ‘00000000’ specifies the highest frequency of the SQI clock.
DS60001361J-page 350
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 22-6:
Bit
Range
31:24
23:16
15:8
7:0
SQI1CMDTHR: SQI COMMAND THRESHOLD REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
U-0
U-0
R/W-0
R/W-0
—
—
TXCMDTHR
R/W-0
R/W-0
R/W-0
R/W-0
RXCMDTHR(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13-8
TXCMDTHR: Transmit Command Threshold bits
In transmit initiation mode, the SQI module performs a transmit operation when transmit command
threshold bytes are present in the TX buffer. These bits should usually be set to ‘1’ for normal Flash
commands, and set to a higher value for page programming. For 16-bit mode, the value should be a
multiple of 2.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RXCMDTHR: Receive Command Threshold bits(1)
In receive initiation mode, the SQI module attempts to perform receive operations to fetch the receive command threshold number of bytes in the receive buffer. If space for these bytes is not present in the buffer,
the SQI will not initiate a transfer. For 16-bit mode, the value should be a multiple of 2.
If software performs any reads, thereby reducing the buffer count, hardware would initiate a receive transfer
to make the buffer count equal to the value in these bits. If software would not like any more words latched
into the buffer, command initiation mode needs to be changed to Idle before any buffer reads by software.
In the case of Boot/XIP mode, the SQI module will use the System Bus burst size, instead of the receive
command threshold value.
Note 1:
These bits should only be programmed when a receive is not active (i.e., during Idle mode or a transmit).
2015-2021 Microchip Technology Inc.
DS60001361J-page 351
PIC32MZ Graphics (DA) Family
REGISTER 22-7:
Bit
Range
31:24
23:16
15:8
7:0
SQI1INTTHR: SQI INTERRUPT THRESHOLD REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
U-0
U-0
R/W-0
R/W-0
—
—
TXINTTHR
U-0
R/W-0
R/W-0
R/W-0
RXINTTHR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13-8
TXINTTHR: Transmit Interrupt Threshold bits
A transmit interrupt is set when the transmit buffer has more space than the set number of bytes. For 16-bit
mode, the value should be a multiple of 2.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RXINTTHR: Receive Interrupt Threshold bits
A receive interrupt is set when the receive buffer count is larger than or equal to the set number of bytes.
For 16-bit mode, the value should be multiple of 2.
DS60001361J-page 352
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 22-8:
Bit
Range
31:24
23:16
15:8
7:0
SQI1INTEN: SQI INTERRUPT ENABLE REGISTER
Bit
31/23/15/7
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
DMAEIE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CONEMPTYIE CONFULLIE RXTHRIE RXFULLIE RXEMPTYIE
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Set
W = Writable bit
‘1’ = Bit is set
PKTCOMPIE BDDONEIE CONTHRIE
R/W-0
TXTHRIE
R/W-0
R/W-0
TXFULLIE TXEMPTYIE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-12 Unimplemented: Read as ‘0’
bit 11
DMAEIE: DMA Bus Error Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 10
PKTCOMPIE: DMA Buffer Descriptor Packet Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 9
BDDONEIE: DMA Buffer Descriptor Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 8
CONTHRIE: Control Buffer Threshold Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 7
CONEMPTYIE: Control Buffer Empty Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 6
CONFULLIE: Control Buffer Full Interrupt Enable bit
This bit enables an interrupt when the receive buffer is full.
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 5
RXTHRIE: Receive Buffer Threshold Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 4
RXFULLIE: Receive Buffer Full Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 3
RXEMPTYIE: Receive Buffer Empty Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 2
TXTHRIE: Transmit Threshold Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 1
TXFULLIE: Transmit Buffer Full Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 0
TXEMPTYIE: Transmit Buffer Empty Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
2015-2021 Microchip Technology Inc.
DS60001361J-page 353
PIC32MZ Graphics (DA) Family
REGISTER 22-9:
Bit
Range
31:24
23:16
15:8
7:0
SQI1INTSTAT: SQI INTERRUPT STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
—
—
—
—
DMA
EIF
PKT
COMPIF
BD
DONEIF
CON
THRIF
R/W-1, HS
R/W-0, HS
R/W-1, HS
R/W-0, HS
R/W-1, HS
R/W-1, HS
R/W-0, HS
R/W-1, HS
CON
EMPTYIF
CON
FULLIF
RX
EMPTYIF
TXTHRIF
TXFULLIF
TX
EMPTYIF
RXTHRIF(1) RXFULLIF
Legend:
HS = Hardware Set
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-12 Unimplemented: Read as ‘0’
bit 11
DMAEIF: DMA Bus Error Interrupt Flag bit
1 = DMA bus error has occurred
0 = DMA bus error has not occurred
bit 10
PKTCOMPIF: DMA Buffer Descriptor Processor Packet Completion Interrupt Flag bit
1 = DMA BD packet is complete
0 = DMA BD packet is in progress
bit 9
BDDONEIF: DMA Buffer Descriptor Done Interrupt Flag bit
1 = DMA BD process is done
0 = DMA BD process is in progress
bit 8
CONTHRIF: Control Buffer Threshold Interrupt Flag bit
1 = The control buffer has more than THRES words of space available
0 = The control buffer has less than THRES words of space available
bit 7
CONEMPTYIF: Control Buffer Empty Interrupt Flag bit
1 = Control buffer is empty
0 = Control buffer is not empty
bit 6
CONFULLIF: Control Buffer Full Interrupt Flag bit
1 = Control buffer is full
0 = Control buffer is not full
bit 5
RXTHRIF: Receive Buffer Threshold Interrupt Flag bit(1)
1 = Receive buffer has more than RXINTTHR words of space available
0 = Receive buffer has less than RXINTTHR words of space available
bit 4
RXFULLIF: Receive Buffer Full Interrupt Flag bit
1 = Receive buffer is full
0 = Receive buffer is not full
bit 3
RXEMPTYIF: Receive Buffer Empty Interrupt Flag bit
1 = Receive buffer is empty
0 = Receive buffer is not empty
Note 1:
In the case of Boot/XIP mode, the POR value of the receive buffer threshold is zero. Therefore, this bit will
be set to a ‘1’, immediately after a POR until a read request on the System Bus bus is received.
Note:
The bits in the register are cleared by writing a '1' to the corresponding bit position.
DS60001361J-page 354
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 22-9:
SQI1INTSTAT: SQI INTERRUPT STATUS REGISTER (CONTINUED)
bit 2
TXTHRIF: Transmit Buffer Threshold Interrupt Flag bit
1 = Transmit buffer has more than TXINTTHR words of space available
0 = Transmit buffer has less than TXINTTHR words of space available
bit 1
TXFULLIF: Transmit Buffer Full Interrupt Flag bit
1 = The transmit buffer is full
0 = The transmit buffer is not full
bit 0
TXEMPTYIF: Transmit Buffer Empty Interrupt Flag bit
1 = The transmit buffer is empty
0 = The transmit buffer has content
Note 1:
In the case of Boot/XIP mode, the POR value of the receive buffer threshold is zero. Therefore, this bit will
be set to a ‘1’, immediately after a POR until a read request on the System Bus bus is received.
Note:
The bits in the register are cleared by writing a '1' to the corresponding bit position.
2015-2021 Microchip Technology Inc.
DS60001361J-page 355
PIC32MZ Graphics (DA) Family
REGISTER 22-10: SQI1TXDATA: SQI TRANSMIT DATA BUFFER REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXDATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXDATA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
TXDATA: Transmit Command Data bits
Data is loaded into this register before being transmitted. Just prior to the beginning of a data transfer, the
data in TXDATA is loaded into the shift register (SFDR).
Multiple writes to TXDATA can occur even while a transfer is already in progress. There can be a maximum
of eight commands that can be queued.
REGISTER 22-11: SQI1RXDATA: SQI RECEIVE DATA BUFFER REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R-0
R-0
R-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RXDATA
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RXDATA
R-0
R-0
RXDATA
R-0
R-0
R-0
R-0
R-0
RXDATA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
RXDATA: Receive Data Buffer bits
At the end of a data transfer, the data in the shift register is loaded into the RXDATA register. This register
works like a buffer. The depth of the receive buffer is eight words.
DS60001361J-page 356
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 22-12: SQI1STAT1: SQI STATUS REGISTER 1
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R-0
R-0
R-0
R-0
R-0
R-0
U-0
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R-0
R-0
R-0
R-0
R-0
R-0
—
—
Legend:
R = Readable bit
-n = Value at POR
bit 31-22
bit 21-16
bit 15-6
bit 5-0
TXBUFFREE
RXBUFCNT
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
TXBUFFREE: Transmit buffer Available Word Space bits
Unimplemented: Read as ‘0’
RXBUFCNT: Number of words of read data in the buffer
2015-2021 Microchip Technology Inc.
DS60001361J-page 357
PIC32MZ Graphics (DA) Family
REGISTER 22-13: SQI1STAT2: SQI STATUS REGISTER 2
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R-0
R-0
—
—
—
—
—
—
CMDSTAT
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
U-0
R-0
R-0
CONAVAIL
SQID3
SQID2
SQID1
SQID0
—
RXUN
TXOV
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
CONAVAIL
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-18 Unimplemented: Read as ‘0’
bit 17-16 CMDSTAT: Current Command Status bits
These bits indicate the current command status.
11 = Reserved
10 = Receive
01 = Transmit
00 = Idle
bit 15-11 Unimplemented: Read as ‘0’
bit 10-7 CONAVAIL: Control buffer Space Available bits
These bits indicate the available control word space.
1000 = 8 words are available
0111 = 7 words are available
•
•
•
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0001 = 1 word is available
0000 = No words are available
SQID3: SQID3 Status bit
1 = Data is present on SQID3
0 = Data is not present on SQID3
SQID2: SQID2 Status bit
1 = Data is present on SQID2
0 = Data is not present on SQID2
SQID1: SQID1 Status bit
1 = Data is present on SQID1
0 = Data is not present on SQID1
SQID0: SQID0 Status bit
1 = Data is present on SQID0
0 = Data is not present on SQID0
Unimplemented: Read as ‘0’
RXUN: Receive buffer Underflow Status bit
1 = Receive buffer Underflow has occurred
0 = Receive buffer underflow has not occurred
TXOV: Transmit buffer Overflow Status bit
1 = Transmit buffer overflow has occurred
0 = Transmit buffer overflow has not occurred
DS60001361J-page 358
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 22-14: SQI1BDCON: SQI BUFFER DESCRIPTOR CONTROL REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
START
POLLEN
DMAEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-3
Unimplemented: Read as ‘0’
bit 2
START: Buffer Descriptor Processor Start bit
1 = Start the buffer descriptor processor
0 = Disable the buffer descriptor processor
bit 1
POLLEN: Buffer Descriptor Poll Enable bit
1 = BDP poll is enabled
0 = BDP poll is not enabled
bit 0
DMAEN: DMA Enable bit
1 = DMA is enabled
0 = DMA is disabled
x = Bit is unknown
REGISTER 22-15: SQI1BDCURADD: SQI BUFFER DESCRIPTOR CURRENT ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
BDCURRADDR
R-0
R-0
BDCURRADDR
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
BDCURRADDR
R-0
R-0
BDCURRADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
BDCURRADDR: Current Buffer Descriptor Address bits
These bits contain the address of the current descriptor being processed by the Buffer Descriptor
Processor.
2015-2021 Microchip Technology Inc.
DS60001361J-page 359
PIC32MZ Graphics (DA) Family
REGISTER 22-16: SQI1BDBASEADD: SQI BUFFER DESCRIPTOR BASE ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BDADDR
R/W-0
BDADDR
R/W-0
R/W-0
BDADDR
R/W-0
R/W-0
BDADDR
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
R/W-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
BDADDR: DMA Base Address bits
These bits contain the physical address of the root buffer descriptor. This register should be updated only
when the DMA is idle.
REGISTER 22-17: SQI1BDSTAT: SQI BUFFER DESCRIPTOR STATUS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R-x
R-x
R-x
R-x
R-x
R-x
—
—
R-x
R-x
BDSTATE
R-x
R-x
R-x
DMASTART DMAACTV
R-x
R-x
R-x
R-x
R-x
R-x
BDCON
R-x
Legend:
R = Readable bit
-n = Value at POR
R-x
R-x
R-x
R-x
BDCON
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-22 Unimplemented: Read as ‘0’
bit 21-18 BDSTATE: DMA Buffer Descriptor Processor State Status bits
These bits return the current state of the buffer descriptor processor:
5 = Fetched buffer descriptor is disabled
4 = Descriptor is done
3 = Data phase
2 = Buffer descriptor is loading
1 = Descriptor fetch request is pending
0 = Idle
bit 17
DMASTART: DMA Buffer Descriptor Processor Start Status bit
1 = DMA has started
0 = DMA has not started
bit 16
DMAACTV: DMA Buffer Descriptor Processor Active Status bit
1 = Buffer Descriptor Processor is active
0 = Buffer Descriptor Processor is idle
bit 15-0 BDCON: DMA Buffer Descriptor Control Word bits
These bits contain the current buffer descriptor control word.
DS60001361J-page 360
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 22-18: SQI1BDPOLLCON: SQI BUFFER DESCRIPTOR POLL CONTROL REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POLLCON
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POLLCON
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
POLLCON: Buffer Descriptor Processor Poll Status bits
These bits indicate the number of cycles the BDP would wait before refetching the descriptor control word
if the previous descriptor fetched was disabled.
REGISTER 22-19: SQI1BDTXDSTAT: SQI BUFFER DESCRIPTOR DMA TRANSMIT STATUS
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R-x
R-x
R-x
R-x
U-0
R-x
R-x
R-x
R-x
U-0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
TXSTATE
—
R-x
TXBUFCNT
U-0
—
—
—
—
—
—
—
—
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
TXCURBUFLEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-25 TXSTATE: Current DMA Transmit State Status bits
These bits provide information on the current DMA receive states.
bit 24-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFCNT: DMA Buffer Byte Count Status bits
These bits provide information on the internal buffer space.
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
TXCURBUFLEN: Current DMA Transmit Buffer Length Status bits
These bits provide the length of the current DMA transmit buffer.
2015-2021 Microchip Technology Inc.
DS60001361J-page 361
PIC32MZ Graphics (DA) Family
REGISTER 22-20: SQI1BDRXDSTAT: SQI BUFFER DESCRIPTOR DMA RECEIVE STATUS
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
R-x
R-x
R-x
R-x
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R-x
R-x
R-x
R-x
R-x
RXSTATE
R-x
R-x
—
R-x
R-x
R-x
U-0
U-0
U-0
—
—
—
R-x
R-x
R-x
RXBUFCNT
RXCURBUFLEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-25 RXSTATE: Current DMA Receive State Status bits
These bits provide information on the current DMA receive states.
bit 24-21 Unimplemented: Read as ‘0’
bit 20-16 RXBUFCNT: DMA Buffer Byte Count Status bits
These bits provide information on the internal buffer space.
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
RXCURBUFLEN: Current DMA Receive Buffer Length Status bits
These bits provide the length of the current DMA receive buffer.
REGISTER 22-21: SQI1THR: SQI THRESHOLD CONTROL REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
THRES
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4
Unimplemented: Read as ‘0’
bit 3-0
THRES: SQI Control Threshold Value bits
The SQI control threshold interrupt is asserted when the amount of space indicated by THRES is
available in the SQI control buffer.
DS60001361J-page 362
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 22-22: SQI1INTSIGEN: SQI INTERRUPT SIGNAL ENABLE REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
DMAEISE
PKT
DONEISE
BD
DONEISE
CON
THRISE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CON
EMPTYISE
CON
FULLISE
RX
THRISE
RX
FULLISE
RX
EMPTYISE
TX
THRISE
TX
FULLISE
TX
EMPTYISE
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-12 Unimplemented: Read as ‘0’
bit 11
DMAEISE: DMA Bus Error Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 10
PKTDONEISE: Receive Error Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 9
BDDONEISE: Transmit Error Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 8
CONTHRISE: Control Buffer Threshold Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 7
CONEMPTYISE: Control Buffer Empty Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 6
CONFULLISE: Control Buffer Full Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 5
RXTHRISE: Receive Buffer Threshold Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 4
RXFULLISE: Receive Buffer Full Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 3
RXEMPTYISE: Receive Buffer Empty Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 2
TXTHRISE: Transmit Buffer Threshold Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 1
TXFULLISE: Transmit Buffer Full Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 0
TXEMPTYISE: Transmit Buffer Empty Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
2015-2021 Microchip Technology Inc.
DS60001361J-page 363
PIC32MZ Graphics (DA) Family
REGISTER 22-23: SQI1TAPCON: SQI TAP CONTROL REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
R/W-0
R/W-0
—
—
R/W-0
R/W-0
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DDRCLKINDLY
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDRDATINDLY
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
DDRDATINDLY
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDRCLKINDLY
R/W-0
DATAOUTDLY
R/W-0
R/W-0
R/W-0
CLKOUTDLY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-24 DDRCLKINDLY: SQI Clock Input Delay in DDR Mode bits
These bits are used to add fractional delays to SQI Clock Input while sampling the incoming data in DDR
mode.
111111 = 64 taps added on clock input
111110 = 63 taps added on clock input
•
•
•
000001 = 2 taps added on clock input
000000 = 1 tap added on clock input
bit 23-20 SDRDATINDLY: SQI Data Input Delay in SDR Mode bits
These bits are used to add fractional delays to SQI Data Output while writing the data to the Flash in SDR
mode.
1111 = 16 taps added on data input
1110 = 15 taps added on data input
•
•
•
0001 = 2 taps added on data input
0000 = 1 tap added on data input
bit 19-16 DDRDATINDLY: SQI Data Output Delay in DDR Mode bits
These bits are used to add fractional delays to SQI Data Output while writing the data to the Flash in DDR
mode.
1111 = 16 taps added on data input
1110 = 15 taps added on data input
•
•
•
0001 = 2 taps added on data input
0000 = 1 tap added on data input
bit 15-14 Unimplemented: Read as ‘0’
DS60001361J-page 364
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 22-23: SQI1TAPCON: SQI TAP CONTROL REGISTER (CONTINUED)
bit 13-8
SDRCLKINDLY: SQI Clock Input Delay in SDR Mode bits
These bits are used to add fractional delays to SQI Clock Input while sampling the incoming data in DDR
mode.
111111 = 64 taps added on clock input
111110 = 63 taps added on clock input
•
•
•
000001 = 2 taps added on clock input
000000 = 1 tap added on clock input
bit 7-4
DATAOUTDLY: SQI Data Output Delay bits
These bits are used to add fractional delays to SQI Data Output while writing the data to the Flash in all
modes of operation.
1111 = 16 taps added on data output
1110 = 15 taps added on data output
•
•
•
0001 = 2 taps added on data output
0000 = 1 tap added on data output
bit 3-0
CLKOUTDLY: SQI Clock Output Delay bits
These bits are used to add fractional delays to SQI Clock Output while writing the data to the Flash in all
modes of operation.
1111 = 16 taps added on clock output
1110 = 15 taps added on clock output
•
•
•
0001 = 2 taps added on clock output
0000 = 1 tap added on clock output
2015-2021 Microchip Technology Inc.
DS60001361J-page 365
PIC32MZ Graphics (DA) Family
REGISTER 22-24: SQI1MEMSTAT: SQI MEMORY STATUS CONTROL REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
STATPOS
R/W-0
R/W-0
R/W-0
R/W-0
STATTYPE
R/W-0
STATBYTES
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STATCMD
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STATCMD
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-21 Unimplemented: Read as ‘0’
bit 20
STATPOS: Status Bit Position in Flash bit
Indicates the BUSY bit position in the Flash Status register. This bit is added to support all Flash types
(with BUSY bit at 0 and at 7).
1 = BUSY bit position is bit 7 in status register
0 = BUSY bit position is bit 0 in status register
bit 19-18 STATTYPE: Status Command Lane Mode bits
11 = Reserved
10 = Status command and read are executed in Quad Lane mode
01 = Status command and read are executed in Dual Lane mode
00 = Status command and read are executed in Single Lane mode
bit 17-16 STATBYTES: Number of Status Bytes bits
11 = Reserved
10 = Status command is 2 bytes long
01 = Status command is 1 byte long
00 = Reserved
bit 15-0
STATCMD: Status Command bits
The status check command is written into these bits
DS60001361J-page 366
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 22-25: SQI1XCON3: SQI XIP CONTROL REGISTER 3
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
U-0
R/W-0
—
—
—
INIT1SCHECK
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
Bit
27/19/11/3 26/18/10/2
R/W-0
R/W-0
INIT1COUNT
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
INIT1TYPE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INIT1CMD3
R/W-0
R/W-0
INIT1CMD2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INIT1CMD1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28
INIT1SCHECK: Flash Initialization 1 Command Status Check bit
1 = Check the status after executing the INIT1 commands
0 = Do not check the status
bit 27-26 INIT1COUNT: Flash Initialization 1 Command Count bits
11 = INIT1CMD1, INIT1CMD2, and INIT1CMD3 are sent
10 = INIT1CMD1 and INIT1CMD2 are sent, but INIT1CMD3 is still pending
01 = INIT1CMD1 is sent, but INIT1CMD2 and INIT1CMD3 are still pending
00 = No commands are sent
bit 25-24 INIT1TYPE: Flash Initialization 1 Command Type bits
11 = Reserved
10 = INIT1 commands are sent in Quad Lane mode
01 = INIT1 commands are sent in Dual Lane mode
00 = INIT1 commands are sent in Single Lane mode
bit 24-16 INIT1CMD3: Flash Initialization Command 3 bits
Third command of the Flash initialization.
bit 15-8
INIT1CMD2: Flash Initialization Command 2 bits
Second command of the Flash initialization.
bit 7-0
INIT1CMD1: Flash Initialization Command 1 bits
First command of the Flash initialization.
Note:
Some Flash devices require write enable and sector unprotect commands before write/read operations and
this register is useful in working with those Flash types (XIP mode only)
2015-2021 Microchip Technology Inc.
DS60001361J-page 367
PIC32MZ Graphics (DA) Family
REGISTER 22-26: SQI1XCON4: SQI XIP CONTROL REGISTER 4
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
U-0
R/W-0
—
—
—
INIT2SCHECK
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
Bit
27/19/11/3 26/18/10/2
R/W-0
R/W-0
INIT2COUNT
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
INIT2TYPE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INIT2CMD3
R/W-0
R/W-0
INIT2CMD2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INIT2CMD1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28
INIT2SCHECK: Flash Initialization 2 Command Status Check bit
1 = Check the status after executing the INIT2 commands
0 = Do not check the status
bit 27-26 INIT2COUNT: Flash Initialization 2 Command Count bits
11 = INIT2CMD1, INIT2CMD2, and INIT2CMD3 are sent
10 = INIT2CMD1 and INIT2CMD2 are sent, but INIT2CMD3 is still pending
01 = INIT2CMD1 is sent, but INIT2CMD2 and INIT2CMD3 are still pending
00 = No commands are sent
bit 25-24 INIT2TYPE: Flash Initialization 2 Command Type bits
11 = Reserved
10 = INIT2 commands are sent in Quad Lane mode
01 = INIT2 commands are sent in Dual Lane mode
00 = INIT2 commands are sent in Single Lane mode
bit 24-16 INIT2CMD3: Flash Initialization Command 3 bits
Third command of the Flash initialization.
bit 15-8
INIT2CMD2: Flash Initialization Command 2 bits
Second command of the Flash initialization.
bit 7-0
INIT2CMD1: Flash Initialization Command 1 bits
First command of the Flash initialization.
Note:
Some Flash devices require write enable and sector unprotect commands before write/read operations and
this register is useful in working with those Flash types (XIP mode only)
DS60001361J-page 368
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
23.0
Note:
INTER-INTEGRATED CIRCUIT
(I2C)
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 24. “InterIntegrated Circuit (I2C)” (DS60001116),
which is available from the Documentation
> Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The I2C module provides complete hardware support
for both Client and Multi-Host modes of the I2C serial
communication standard.
Each I2C module offers the following key features:
• I2C interface supporting both host and client operation
• I2C Client mode supports 7-bit and 10-bit
addressing
• I2C Host mode supports 7-bit and 10-bit addressing
• I2C port allows bidirectional transfers between
host and clients
• Serial clock synchronization for the I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
• I2C supports multi-host operation; detects bus collision and arbitrates accordingly
• Provides support for address bit masking
• SMBus support
Figure 23-1 illustrates the I2C module block diagram.
Each I2C module has a 2-pin interface:
• SCLx pin is clock
• SDAx pin is data
2015-2021 Microchip Technology Inc.
DS60001361J-page 369
PIC32MZ Graphics (DA) Family
FIGURE 23-1:
I2C BLOCK DIAGRAM
Internal
Data Bus
I2CxRCV
SCLx
Read
Shift
Clock
I2CxRSR
LSB
SDAx
Address Match
Match Detect
Write
I2CxMSK
Write
Read
I2CxADD
Read
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
Control Logic
I2CxSTAT
Collision
Detect
Read
Write
I2CxCON
Acknowledge
Generation
Read
Clock
Stretching
Write
I2CxTRN
LSB
Read
Shift Clock
Reload
Control
BRG Down Counter
Write
I2CxBRG
Read
PBCLK2
DS60001361J-page 370
2015-2021 Microchip Technology Inc.
I2C Control Registers
TABLE 23-1:
0000 I2C1CON
0010 I2C1STAT
0020
I2C1ADD
0030 I2C1MSK
0050
I2C1TRN
0060
I2C1RCV
0200 I2C2CON
0210 I2C2STAT
I2C2ADD
0230 I2C2MSK
0240 I2C2BRG
0250
I2C2TRN
0260
I2C2RCV
30/14
31:16
—
—
15:0
ON
—
31:16
—
—
15:0 ACKSTAT TRSTAT
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
31:16
—
—
15:0
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
31:16
—
—
15:0
ON
—
31:16
—
—
15:0 ACKSTAT TRSTAT
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
31:16
—
—
15:0
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
—
SIDL
—
ACKTIM
—
—
—
—
—
—
SCLREL
—
—
—
—
—
—
—
—
STRICT
—
—
—
—
—
—
—
—
A10M
—
BCL
—
—
—
—
—
—
DISSLW
—
GCSTAT
—
—
SMEN
—
ADD10
—
—
GCEN
—
IWCOL
—
PCIE
STREN
—
I2COV
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2C1BRG
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCLREL
—
—
—
—
—
—
—
STRICT
—
—
—
—
—
—
—
A10M
—
BCL
—
—
—
—
—
DISSLW
—
GCSTAT
—
SMEN
—
ADD10
—
GCEN
—
IWCOL
—
PCIE
STREN
—
I2COV
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2C2BRG
—
—
—
—
—
—
—
20/4
SCIE
BOEN
ACKDT
ACKEN
—
—
D/A
P
—
—
ADD
—
—
ADD
—
—
—
SIDL
—
ACKTIM
—
—
—
—
—
—
21/5
—
—
—
18/2
17/1
16/0
SDAHT
RCEN
—
S
—
SBCDE
PEN
—
R/W
—
AHEN
RSEN
—
RBF
—
DHEN
SEN
—
TBF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDAHT
RCEN
—
S
—
SBCDE
PEN
—
R/W
—
AHEN
RSEN
—
RBF
—
DHEN
SEN
—
TBF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2C1TXDATA
—
—
I2C1RXDATA
SCIE
BOEN
ACKDT
ACKEN
—
—
D/A
P
—
—
ADD
—
—
MSK
—
—
—
19/3
—
—
I2C2TXDATA
—
—
I2C2RXDATA
All Resets
Bit Range
31/15
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
DS60001361J-page 371
31:16
—
—
—
—
—
—
—
—
—
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN 0000
15:0
ON
—
SIDL
SCLREL STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0410 I2C3STAT
15:0 ACKSTAT TRSTAT ACKTIM
—
—
BCL
GCSTAT ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0420 I2C3ADD
15:0
—
—
—
—
—
—
ADD
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and
INV Registers” for more information.
0400 I2C3CON
PIC32MZ Graphics (DA) Family
0040 I2C1BRG
0220
I2C1 THROUGH I2C5 REGISTER MAP
Bits
Register
Name(1)
Virtual Address
(BF82_#)
2015-2021 Microchip Technology Inc.
23.1
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
15:0
31:16
0440 I2C3BRG
15:0
31:16
0450 I2C3TRN
15:0
31:16
0460 I2C3RCV
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
0430 I2C3MSK
0600 I2C4CON
0610 I2C4STAT
0620
I2C4ADD
0630 I2C4MSK
0640 I2C4BRG
0650
I2C4TRN
0660
I2C4RCV
15:0
ON
—
31:16
—
—
15:0 ACKSTAT TRSTAT
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
31:16
—
—
15:0
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
—
—
I2C3BRG
—
—
—
—
—
—
—
—
—
ADD
—
—
—
—
—
—
—
—
—
—
—
—
—
SIDL
—
ACKTIM
—
—
—
—
—
SCLREL
—
—
—
—
—
—
—
STRICT
—
—
—
—
—
—
—
A10M
—
BCL
—
—
—
—
—
DISSLW
—
GCSTAT
—
SMEN
—
ADD10
—
GCEN
—
IWCOL
—
PCIE
STREN
—
I2COV
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2C4BRG
—
—
—
—
—
—
20/4
—
—
—
—
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDAHT
RCEN
—
S
—
SBCDE
PEN
—
R/W
—
AHEN
RSEN
—
RBF
—
DHEN
SEN
—
TBF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2C3TXDATA
—
—
I2C3RXDATA
SCIE
BOEN
ACKDT
ACKEN
—
—
D/A
P
—
—
ADD
—
—
ADD
—
—
—
19/3
—
—
I2C4TXDATA
—
—
I2C4RXDATA
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
—
—
—
—
—
—
—
—
—
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN 0000
15:0
ON
—
SIDL
SCLREL STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0810 I2C5STAT
15:0 ACKSTAT TRSTAT ACKTIM
—
—
BCL
GCSTAT ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0820 I2C5ADD
15:0
—
—
—
—
—
—
ADD
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0830 I2C5MSK
15:0
—
—
—
—
—
—
ADD
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0840 I2C5BRG
15:0
I2C5BRG
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0850 I2C5TRN
15:0
—
—
—
—
—
—
—
—
I2C4TXDATA
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0860 I2C5RCV
15:0
—
—
—
—
—
—
—
—
I2C4RXDATA
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and
INV Registers” for more information.
0800 I2C5CON
31:16
—
21/5
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF82_#)
I2C1 THROUGH I2C5 REGISTER MAP (CONTINUED)
PIC32MZ Graphics (DA) Family
DS60001361J-page 372
TABLE 23-1:
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 23-1:
Bit
Range
31:24
23:16
15:8
7:0
I2CXCON: I2C CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
R/W-0
U-0
R/W-0
R/W-1, HC
R/W-0
R/W-0
R/W-0
R/W-0
ON
—
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
R/W-0
R/W-0
R/W-0
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
Legend:
R = Readable bit
-n = Value at POR
HC = Cleared in Hardware
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-23 Unimplemented: Read as ‘0’
bit 22
PCIE: Stop Condition Interrupt Enable bit (I2C Client mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
bit 21
SCIE: Start Condition Interrupt Enable bit (I2C Client mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
bit 20
BOEN: Buffer Overwrite Enable bit (I2C Client mode only)
1 = I2CxRCV is updated and ACK is generated for a received address/data byte, ignoring the state of the
I2COV bit (I2CxSTAT)only if the RBF bit (I2CxSTAT) = 0
0 = I2CxRCV is only updated when the I2COV bit (I2CxSTAT) is clear
bit 19
SDAHT: SDA Hold Time Selection bit
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 18
SBCDE: Client Mode Bus Collision Detect Enable bit (I2C Client mode only)
1 = Enable client bus collision interrupts
0 = Client bus collision interrupts are disabled
bit 17
AHEN: Address Hold Enable bit (Client mode only)
1 = Following the 8th falling edge of SCL for a matching received address byte; SCLREL bit will be cleared
and the SCL will be held low.
0 = Address holding is disabled
bit 16
DHEN: Data Hold Enable bit (I2C Client mode only)
1 = Following the 8th falling edge of SCL for a received data byte; client hardware clears the SCLREL bit
and SCL is held low
0 = Data holding is disabled
bit 15
ON: I2C Enable bit
1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins
0 = Disables the I2C module; all I2C pins are controlled by PORT functions
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
2015-2021 Microchip Technology Inc.
DS60001361J-page 373
PIC32MZ Graphics (DA) Family
REGISTER 23-1:
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
I2CXCON: I2C CONTROL REGISTER (CONTINUED)
SCLREL: SCLx Release Control bit (when operating as I2C client)
1 = Release SCLx clock
0 = Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at
beginning of client transmission. Hardware clear at end of client reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of client
transmission.
STRICT: Strict I2C Reserved Address Rule Enable bit
1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate
addresses in reserved address space.
0 = Strict I2C Reserved Address Rule not enabled
A10M: 10-bit Client Address bit
1 = I2CxADD is a 10-bit client address
0 = I2CxADD is a 7-bit client address
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control disabled
0 = Slew rate control enabled
SMEN: SMBus Input Levels bit
1 = Enable I/O pin thresholds compliant with SMBus specification
0 = Disable SMBus input thresholds
GCEN: General Call Enable bit (when operating as I2C client)
1 = Enable interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0 = General call address disabled
STREN: SCLx Clock Stretch Enable bit (when operating as I2C client)
Used in conjunction with the SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
ACKDT: Acknowledge Data bit (when operating as I2C host, applicable during host receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1 = Send NACK during Acknowledge
0 = Send ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C host, applicable during host receive)
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Hardware clear at end of host Acknowledge sequence.
0 = Acknowledge sequence not in progress
RCEN: Receive Enable bit (when operating as I2C host)
1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of host receive data byte.
0 = Receive sequence not in progress
PEN: Stop Condition Enable bit (when operating as I2C host)
1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of host Stop sequence.
0 = Stop condition not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I2C host)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
host Repeated Start sequence.
0 = Repeated Start condition not in progress
SEN: Start Condition Enable bit (when operating as I2C host)
1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of host Start sequence.
0 = Start condition not in progress
DS60001361J-page 374
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 23-2:
Bit
Range
31:24
23:16
15:8
7:0
I2CXSTAT: I2C STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0, HS, HC
R-0, HS, HC
R/C-0, HS, HC
U-0
U-0
R/C-0, HS
R-0, HS, HC
R-0, HS, HC
ACKSTAT
TRSTAT
ACKTIM
—
—
BCL
GCSTAT
ADD10
R/C-0, HS, SC
R/C-0, HS, SC
R-0, HS, HC
R/C-0, HS, HC
R/C-0, HS, HC
R-0, HS, HC
R-0, HS, HC
R-0, HS, HC
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
Legend:
HS = Hardware Set
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
SC = Software Cleared
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
C = Clearable bit
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ACKSTAT: Acknowledge Status bit
(when operating as I2C host, applicable to host transmit operation)
1 = NACK received from client
0 = ACK received from client
Hardware set or clear at end of client Acknowledge.
bit 14
TRSTAT: Transmit Status bit (when operating as I2C host, applicable to host transmit operation)
1 = Host transmit is in progress (8 bits + ACK)
0 = Host transmit is not in progress
Hardware set at beginning of host transmission. Hardware clear at end of client Acknowledge.
bit 13
ACKTIM: Acknowledge Time Status bit (Valid in I2C Client mode only)
1 = I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCL clock
0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCL clock
bit 12-11 Unimplemented: Read as ‘0’
bit 10
BCL: Host Bus Collision Detect bit
1 = A bus collision has been detected during a host operation
0 = No collision
Hardware set at detection of bus collision.
bit 9
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware set when address matches general call address. Hardware clear at Stop detection.
bit 8
ADD10: 10-bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
bit 7
IWCOL: Write Collision Detect bit
1 = An attempt to write the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
bit 6
I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
2015-2021 Microchip Technology Inc.
DS60001361J-page 375
PIC32MZ Graphics (DA) Family
REGISTER 23-2:
I2CXSTAT: I2C STATUS REGISTER (CONTINUED)
bit 5
D_A: Data/Address bit (when operating as I2C client)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of client byte.
bit 4
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
bit 3
S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
bit 2
R_W: Read/Write Information bit (when operating as I2C client)
1 = Read – indicates data transfer is output from client
0 = Write – indicates data transfer is input to client
Hardware set or clear after reception of I 2C device address byte.
bit 1
RBF: Receive Buffer Full Status bit
1 = Receive complete, I2CxRCV is full
0 = Receive not complete, I2CxRCV is empty
Hardware set when I2CxRCV is written with received byte. Hardware clear when software
reads I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.
DS60001361J-page 376
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
24.0
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Note:
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 21. “Universal
Asynchronous Receiver Transmitter
(UART)” (DS60001107), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The UART module is one of the serial I/O modules
available in PIC32MZ DA family devices. The UART
is a full-duplex, asynchronous communication
channel that communicates with peripheral devices
and personal computers through protocols, such as
RS-232, RS-485, LIN, and IrDA®. The module also
supports the hardware flow control option, with
UxCTS and UxRTS pins, and also includes an IrDA
encoder and decoder.
The primary features of the UART module are:
• Full-duplex, 8-bit or 9-bit data transmission
• Even, Odd or No Parity options (for 8-bit data)
• One or two Stop bits
• Hardware auto-baud feature
• Hardware flow control option
• Fully integrated Baud Rate Generator (BRG) with
16-bit prescaler
• Baud rates ranging from 76 bps to 25 Mbps at
100 MHz (PBCLK2)
• 8-level deep First-In-First-Out (FIFO) transmit
data buffer
• 8-level deep FIFO receive data buffer
• Parity, framing and buffer overrun error detection
• Support for interrupt-only on address detect
(9th bit = 1)
• Separate transmit and receive interrupts
• Loopback mode for diagnostic support
• LIN Protocol support
• IrDA encoder and decoder with 16x baud clock
output for external IrDA encoder/decoder support
• Auto-baud support
• Ability to receive data during Sleep mode
Figure 24-1 illustrates a simplified block diagram of the
UART module.
FIGURE 24-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
PBCLK2
11
FRC
10
SYSCLK
01
PBCLK2
00
CLKSEL
(UxMOD)
2015-2021 Microchip Technology Inc.
IrDA®
Hardware Flow Control
UxRTS/BCLKx
UxCTS
UARTx Receiver
UxRX
UARTx Transmitter
UxTX
DS60001361J-page 377
UART Control Registers
Virtual Address
(BF82_#)
TABLE 24-1:
U1STA
(1)
—
—
ON
—
SIDL
31:16
26/10
25/9
24/8
23/7
—
—
—
—
—
SLPEN
ACTIVE
—
—
—
CLKSEL
IREN
RTSMD
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL
UEN
UTXISEL
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
—
—
—
—
—
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
U1BRG(1)
15:0
—
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
ON
—
SIDL
IREN
RTSMD
—
U2STA(1)
(1)
U2BRG
2400 U3MODE(1)
2015-2021 Microchip Technology Inc.
U3STA(1)
2420 U3TXREG
2430 U3RXREG
U3BRG(1)
—
—
UEN
UTXISEL
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
18/2
17/1
16/0
RUNOVF 0000
STSEL
—
—
ADDEN
—
PERR
FERR
OERR
URXDA 0110
—
—
—
—
—
—
—
—
—
—
Transmit Register
—
—
—
—
—
—
—
—
—
—
—
—
CLKSEL
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL
—
RUNOVF 0000
STSEL
ADDEN
—
—
—
PERR
FERR
OERR
—
—
—
—
—
—
—
—
—
—
—
—
URXDA 0110
—
—
—
—
—
—
—
ON
—
SIDL
IREN
RTSMD
—
—
—
UEN
—
—
—
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
ACTIVE
—
—
—
CLKSEL
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
URXISEL
—
—
RUNOVF 0000
STSEL
ADDEN
—
—
—
PERR
FERR
OERR
—
—
—
—
—
—
—
—
—
—
—
—
—
URXDA 0110
—
Baud Rate Generator Prescaler
—
—
—
0000
0000
Receive Register
—
0000
0000
RIDLE
Transmit Register
—
0000
0000
SLPEN
ADDR
UTXINV
0000
0000
—
MASK
UTXISEL
0000
0000
Receive Register
—
0000
0000
RIDLE
Transmit Register
—
0000
0000
ACTIVE
—
0000
0000
—
SLPEN
URXISEL
0000
0000
Receive Register
—
0000
0000
RIDLE
Baud Rate Generator Prescaler
31:16
15:0
19/3
ADDR
15:0
15:0
URXISEL
MASK
31:16
31:16
15:0
20/4
Baud Rate Generator Prescaler
31:16
15:0
21/5
ADDR
—
(1)
22/6
MASK
—
2230 U2RXREG
2440
—
15:0
27/11
—
2220 U2TXREG
2410
31:16
28/12
15:0
2200 U2MODE
2240
29/13
31:16
2030 U1RXREG
2210
30/14
15:0
2020 U1TXREG
2040
31/15
All Resets
Register
Name
Bit Range
Bits
2000 U1MODE(1)
2010
UART1 THROUGH UART6 REGISTER MAP
0000
0000
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 378
24.1
Virtual Address
(BF82_#)
U4STA(1)
2620 U4TXREG
2630 U4RXREG
2640
U4BRG(1)
2810
U5STA(1)
2820 U5TXREG
2830 U5RXREG
2840
U5BRG(1)
2A10
U6STA
29/13
—
—
—
ON
—
SIDL
31:16
15:0
28/12
27/11
26/10
25/9
24/8
23/7
—
—
—
—
—
SLPEN
ACTIVE
—
—
—
CLKSEL
IREN
RTSMD
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL
UEN
UTXISEL
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
ON
—
SIDL
IREN
RTSMD
—
—
—
UEN
UTXISEL
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
18/2
17/1
16/0
RUNOVF 0000
STSEL
—
—
ADDEN
—
PERR
FERR
OERR
URXDA 0110
—
—
—
—
—
—
—
—
—
—
Transmit Register
—
—
—
—
—
—
—
—
—
—
—
—
CLKSEL
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL
—
RUNOVF 0000
STSEL
ADDEN
—
—
—
PERR
FERR
OERR
—
—
—
—
—
—
—
—
—
—
—
—
URXDA 0110
—
—
—
—
—
—
—
ON
—
SIDL
IREN
RTSMD
—
31:16
—
—
UEN
—
—
—
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
ACTIVE
—
—
—
CLKSEL
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
2A40 U6BRG(1)
15:0
—
—
—
—
—
—
—
—
URXISEL
—
—
RUNOVF 0000
STSEL
ADDEN
—
—
—
DS60001361J-page 379
PERR
FERR
OERR
—
—
—
—
—
—
—
—
—
—
—
—
—
URXDA 0110
—
Baud Rate Generator Prescaler
—
—
—
0000
0000
Receive Register
—
0000
0000
RIDLE
Transmit Register
—
0000
0000
SLPEN
ADDR
UTXINV
0000
0000
—
MASK
UTXISEL
0000
0000
Receive Register
—
0000
0000
RIDLE
Transmit Register
—
0000
0000
ACTIVE
—
0000
0000
—
SLPEN
URXISEL
0000
0000
Receive Register
—
0000
0000
RIDLE
Baud Rate Generator Prescaler
15:0
2A30 U6RXREG
19/3
ADDR
31:16
2A20 U6TXREG
URXISEL
MASK
31:16
15:0
20/4
Baud Rate Generator Prescaler
31:16
15:0
21/5
ADDR
15:0
31:16
15:0
22/6
MASK
31:16
31:16
2A00 U6MODE(1)
15:0
(1)
30/14
0000
0000
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more information.
PIC32MZ Graphics (DA) Family
2800 U5MODE(1)
31:16
15:0
31/15
All Resets
Bit Range
2600 U4MODE(1)
2610
UART1 THROUGH UART6 REGISTER MAP (CONTINUED)
Bits
Register
Name
2015-2021 Microchip Technology Inc.
TABLE 24-1:
PIC32MZ Graphics (DA) Family
REGISTER 24-1:
Bit
Range
31:24
23:16
15:8
7:0
UxMODE: UARTx MODE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R-0, HS, HC
U-0
U-0
U-0
SLPEN
ACTIVE
—
—
—
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
ON
—
SIDL
IREN
RTSMD
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAKE
LPBACK
ABAUD
RXINV
BRGH
Legend:
CLKSEL
R/W-0
R/W-0
RUNOVF
R/W-0
UEN(1)
R/W-0
PDSEL
HS = Hardware set
HC = Hardware cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
R/W-0
STSEL
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23
SLPEN: Run During Sleep Enable bit
1 = UARTx BRG clock runs during Sleep mode
0 = UARTx BRG clock is turned off during Sleep mode
Note:
bit 22
SLPEN = 1 only applies if CLKSEL = FRC. All clocks, as well as the UART, are disabled in Deep
Sleep mode.
ACTIVE: UARTx Module Running Status bit
1 = UARTx module is active (UxMODE register should not be updated)
0 = UARTx module is not active (UxMODE register can be updated)
bit 21-19 Unimplemented: Read as ‘0’
bit 18-17 CLKSEL: UARTx Module Clock Selection bits
11 = BRG clock is PBCLK2
10 = BRG clock is FRC
01 = BRG clock is SYSCLK (turned off in Sleep mode)
00 = BRG clock is PBCLK2 (turned off in Sleep mode)
bit 16
RUNOVF: Run During Overflow Condition Mode bit
1 = When an Overflow Error (OERR) condition is detected, the shift register continues to run to remain
synchronized
0 = When an Overflow Error (OERR) condition is detected, the shift register stops accepting new data
(Legacy mode)
bit 15
ON: UARTx Enable bit
1 = UARTx module is enabled. UARTx pins are controlled by UARTx as defined by UEN and UTXEN
control bits
0 = UARTx module is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx,
and LATx registers; UARTx power consumption is minimal
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation in Idle mode
Note 1:
These bits are present for legacy compatibility, and are superseded by PPS functionality on these devices
(see Section 12.4 “Peripheral Pin Select (PPS)” for more information).
DS60001361J-page 380
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 24-1:
UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 12
IREN: IrDA® Encoder and Decoder Enable bit
1 = IrDA is enabled
0 = IrDA is disabled
bit 11
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
bit 9-8
UEN: UARTx Module Enable bits(1)
11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by
corresponding bits in the PORTx register
bit 7
WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit
1 = Wake-up enabled
0 = Wake-up disabled
bit 6
LPBACK: UARTx Loopback Mode Select bit
1 = Loopback mode is enabled
0 = Loopback mode is disabled
bit 5
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of Sync character (0x55);
cleared by hardware upon completion
0 = Baud rate measurement disabled or completed
bit 4
RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1 = High-Speed mode – 4x baud clock enabled
0 = Standard Speed mode – 16x baud clock enabled
bit 2-1
PDSEL: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0
STSEL: Stop Selection bit
1 = 2 Stop bits
0 = 1 Stop bit
Note 1:
These bits are present for legacy compatibility, and are superseded by PPS functionality on these devices
(see Section 12.4 “Peripheral Pin Select (PPS)” for more information).
2015-2021 Microchip Technology Inc.
DS60001361J-page 381
PIC32MZ Graphics (DA) Family
REGISTER 24-2:
Bit
Range
31:24
23:16
15:8
7:0
UxSTA: UARTx STATUS AND CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MASK
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR
R/W-0
R/W-0
UTXISEL
R/W-0
R/W-0
URXISEL
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-1
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
R/W-0
R-1
R-0
R-0
R/W-0
R-0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-25 MASK: UARTx Address Match Mask bits
These bits are used to mask the ADDR bits.
11111111 = Corresponding ADDRx bits are used to detect the address match
Note:
This setting allows the user to assign individual address as well as a group broadcast address
to a UART.
00000000 = Corresponding ADDRx bits are not used to detect the address match.
bit 23-16 ADDR: Automatic Address Mask bits
When the ADDEN bit is ‘1’, this value defines the address character to use for automatic address detection.
bit 15-14 UTXISEL: TX Interrupt Mode Selection bits
11 = Reserved, do not use
10 = Interrupt is generated and asserted while the transmit buffer is empty
01 = Interrupt is generated and asserted when all characters have been transmitted
00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space
bit 13
UTXINV: Transmit Polarity Inversion bit
If IrDA mode is disabled (i.e., IREN (UxMODE) is ‘0’):
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IrDA mode is enabled (i.e., IREN (UxMODE) is ‘1’):
1 = IrDA encoded UxTX Idle state is ‘1’
0 = IrDA encoded UxTX Idle state is ‘0’
bit 12
URXEN: Receiver Enable bit
1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)
0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module
Note:
bit 11
The event of disabling an enabled receiver will release the RX pin to the PORT function;
however, the receive buffers will not be reset. Disabling the receiver has no effect on the receive
status flags.
UTXBRK: Transmit Break bit
1 = Send Break on next transmission. Start bit followed by twelve ‘0’ bits, followed by Stop bit; cleared by
hardware upon completion
0 = Break transmission is disabled or completed
DS60001361J-page 382
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 24-2:
bit 10
UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
UTXEN: Transmit Enable bit
1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)
0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset
Note:
The event of disabling an enabled transmitter will release the TX pin to the PORT function and
reset the transmit buffers to empty. Any pending transmission is aborted and data characters in
the transmit buffers are lost. All transmit status flags are cleared and the TRMT bit is set
bit 9
UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register is Empty bit (read-only)
1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
bit 7-6
URXISEL: Receive Interrupt Mode Selection bit
11 = Reserved
10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full
01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full
00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character)
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect
0 = Address Detect mode is disabled
bit 4
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Data is being received
bit 3
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character
0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character
0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit.
This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit
resets the receiver buffer and RSR to empty state.
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed
bit 0
URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
2015-2021 Microchip Technology Inc.
DS60001361J-page 383
PIC32MZ Graphics (DA) Family
Figure 24-2 and Figure 24-3 illustrate typical receive
and transmit timing for the UART module.
FIGURE 24-2:
UART RECEPTION
Char 1
Char 2-4
Char 5-10
Char 11-13
Read to
UxRXREG
Start 1
Stop Start 2
Stop 4
Start 5
Stop 10 Start 11
Stop 13
UxRX
RIDLE
Cleared by
Software
OERR
Cleared by
Software
UxRXIF
URXISEL = 00
Cleared by
Software
UxRXIF
URXISEL = 01
UxRXIF
URXISEL = 10
FIGURE 24-3:
TRANSMISSION (8-BIT OR 9-BIT DATA)
8 into TxBUF
Write to
UxTXREG
TSR
Pull from Buffer
BCLK/16
(Shift Clock)
UxTX
Start
Bit 0
Bit 1
Stop
Start
Bit 1
UxTXIF
UTXISEL = 00
UxTXIF
UTXISEL = 01
UxTXIF
UTXISEL = 10
DS60001361J-page 384
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
25.0
PARALLEL HOST PORT (PMP)
Note:
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 13. “Parallel
Master Port (PMP)” (DS60001128),
which is available from the Documentation
> Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The PMP is a parallel 8-bit/16-bit input/output module
specifically designed to communicate with a wide
variety of parallel devices, such as communications
peripherals, LCDs, external memory devices and
microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP module is
highly configurable.
Key features of the PMP module include:
•
•
•
•
•
•
•
•
•
•
•
•
FIGURE 25-1:
8-bit,16-bit interface
Up to 16 programmable address lines
Up to two Chip Select lines
Programmable strobe options:
- Individual read and write strobes, or
- Read/write strobe with enable strobe
Address auto-increment/auto-decrement
Programmable address/data multiplexing
Programmable polarity on control signals
Parallel Client Port (PSP) support:
- Legacy addressable
- Address support
- 4-byte deep auto-incrementing buffer
Programmable Wait states
Operate during Sleep and Idle modes
Separate configurable read/write registers or dual
buffers for Host mode
Fast bit manipulation using CLR, SET, and INV
registers
PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
PBCLK2
Address Bus
Data Bus
PMP
Control Lines
PMA0
PMALL
PMA1
PMALH
Flash
EEPROM
SRAM
Up to 16-bit Address
PMA
PMA14
PMCS1
PMA15
PMCS2
PMRD
PMRD/PMWR
PMWR
PMENB
PMD
PMD
2015-2021 Microchip Technology Inc.
Microcontroller
LCD
FIFO
Buffer
8-bit/16-bit Data (with or without multiplexed addressing)
DS60001361J-page 385
Control Registers
Virtual Address
(BF82_#)
Register
Name(1)
TABLE 25-1:
E000
PMCON
E030
PMADDR
PMDOUT
E040
PMDIN
E050
E060
PMAEN
PMSTAT
E070 PMWADDR
31/15
30/14
31:16
—
—
—
15:0
ON
—
SIDL
31:16
—
—
—
15:0
BUSY
31:16
—
—
CS2
CS1
ADDR15
ADDR14
—
—
15:0
31:16
2015-2021 Microchip Technology Inc.
E090
PMRDIN
IRQM
—
28/12
27/11
—
—
ADRMUX
—
—
INCM
—
—
26/10
25/9
24/8
23/7
22/6
—
—
—
RDSTART
—
PMPTTL PTWREN PTRDEN
—
MODE16
—
—
31:16
—
—
WAITB
—
—
—
—
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
DUALBUF
—
0000
ALP
CS2P
CS1P
—
WRSP
RDSP
0000
—
—
—
—
—
—
0000
WAITE
0000
—
0000
WAITM
—
—
—
—
—
0000
ADDR
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
0000
0000
DATAIN
—
0000
0000
DATAOUT
15:0
31:16
—
CSF
MODE
15:0
0000
0000
PTEN
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
008F
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
WCS2
WCS1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
31:16
E080 PMRADDR
29/13
All Resets
Bit Range
Bits
E010 PMMODE
E020
PMP REGISTER MAP
15:0
31:16
15:0
WADDR15 WADDR14
0000
WADDR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
RCS2
RCS1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
RADDR15 RADDR14
—
—
0000
RADDR
—
—
—
—
—
—
—
RDATAIN
—
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 386
25.1
PIC32MZ Graphics (DA) Family
REGISTER 25-1:
Bit
Range
31:24
23:16
15:8
7:0
PMCON: PARALLEL PORT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0, HC
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
RDSTART
—
—
—
—
—
DUALBUF
—
R/W-0
(1)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SIDL
PMPTTL
PTWREN
PTRDEN
R/W-0
R/W-0
(2)
R/W-0
(2)
U-0
R/W-0
R/W-0
—
WRSP
RDSP
ON
CSF
Legend:
R = Readable bit
-n = Value at POR
ALP
ADRMUX
R/W-0
(2)
CS2P
W = Writable bit
‘1’ = Bit is set
R/W-0
(2)
CS1P
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23
RDSTART: Start Read on PMP Bus bit
This bit is cleared by hardware at the end of the read cycle.
1 = Start a read cycle on the PMP bus
0 = No effect
bit 22-18 Unimplemented: Read as ‘0’
bit 17
DUALBUF: PMP Dual Read/Write Buffer Enable bit
This bit is only valid in Host mode.
1 = PMP uses separate registers for reads and writes
Reads: PMRADDR and PMRDIN
Writes: PMRWADDR and PMDOUT
0 = PMP uses legacy registers for reads and writes
Reads/Writes: PMADDR and PMRDIN
bit 16
Unimplemented: Read as ‘0’
bit 15
ON: PMP Enable bit(1)
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-11 ADRMUX: Address/Data Multiplexing Selection bits
11 = All 16 bits of address are multiplexed on PMD
10 = All 16 bits of address are multiplexed on PMD
01 = Lower 8 bits of address are multiplexed on PMD pins, upper 8 bits are on PMA
00 = Address and data appear on separate pins
bit 10
PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffer
bit 9
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
2015-2021 Microchip Technology Inc.
DS60001361J-page 387
PIC32MZ Graphics (DA) Family
REGISTER 25-1:
bit 8
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port is enabled
0 = PMRD/PMWR port is disabled
CSF: Chip Select Function bits(2)
11 = Reserved
10 = PMCS1 and PMCS2 function as Chip Select
01 = PMCS1 functions as address bit 14; PMCS2 functions as Chip Select
00 = PMCS1 and PMCS2 function as address bits 14 and 15, respectively
ALP: Address Latch Polarity bit(2)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
CS2P: Chip Select 0 Polarity bit(2)
1 = Active-high (PMCS2)
0 = Active-low (PMCS2)
CS1P: Chip Select 0 Polarity bit(2)
1 = Active-high (PMCS1)
0 = Active-low (PMCS1)
Unimplemented: Read as ‘0’
WRSP: Write Strobe Polarity bit
For Client Modes and Host mode 2 (MODE = 00,01,10):
1 = Write strobe active-high (PMWR)
0 = Write strobe active-low (PMWR)
For Host mode 1 (MODE = 11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB)
RDSP: Read Strobe Polarity bit
For Client modes and Host mode 2 (MODE = 00,01,10):
1 = Read Strobe active-high (PMRD)
0 = Read Strobe active-low (PMRD)
For Host mode 1 (MODE = 11):
1 = Read/write strobe active-high (PMRD/PMWR)
0 = Read/write strobe active-low (PMRD/PMWR)
Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
DS60001361J-page 388
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 25-2:
Bit
Range
31:24
23:16
15:8
PMMODE: PARALLEL PORT MODE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUSY
R/W-0
7:0
IRQM
R/W-0
R/W-0
WAITB(1)
INCM
R/W-0
R/W-0
MODE16
MODE
R/W-0
R/W-0
WAITM(1)
R/W-0
WAITE(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
BUSY: Busy bit (Host mode only)
1 = Port is busy
0 = Port is not busy
bit 14-13 IRQM: Interrupt Request Mode bits
11 = Reserved, do not use
10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode),
or on a read or write operation when PMA =11 (Addressable Client mode only)
01 = Interrupt generated at the end of the read/write cycle
00 = No Interrupt generated
Note:
These bits only control the generation of the PMP interrupt. The PMP Error (PMPE) is always
generated.
bit 12-11 INCM: Increment Mode bits
11 = Client mode read and write buffers auto-increment (MODE = 00 only)
10 = Decrement ADDR by 1 every read/write cycle(2)
01 = Increment ADDR by 1 every read/write cycle(2)
00 = No increment or decrement of address
bit 10
MODE16: 8/16-bit Mode bit
1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer
0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer
bit 9-8
MODE: Parallel Port Mode Select bits
11 = Host mode 1 (PMCSx, PMRD/PMWR, PMENB, PMA, PMD and PMD(3))
10 = Host mode 2 (PMCSx, PMRD, PMWR, PMA, PMD and PMD(3))
01 = Enhanced Client mode, control signals (PMRD, PMWR, PMCS, PMD and PMA)
00 = Legacy PSP, control signals (PMRD, PMWR, PMCS and PMD)
Note 1: Whenever WAITM = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a
write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: Address bits, A15 and A14, are not subject to automatic increment/decrement if configured as Chip Select
CS2 and CS1.
3: These pins are active when MODE16 = 1 (16-bit mode).
2015-2021 Microchip Technology Inc.
DS60001361J-page 389
PIC32MZ Graphics (DA) Family
REGISTER 25-2:
PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED)
bit 7-6
WAITB: Data Setup to Read/Write Strobe Wait States bits(1)
11 = Data wait of 4 TPB; multiplexed address phase of 4 TPB
10 = Data wait of 3 TPB; multiplexed address phase of 3 TPB
01 = Data wait of 2 TPB; multiplexed address phase of 2 TPB
00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (default)
bit 5-2
WAITM: Data Read/Write Strobe Wait States bits(1)
1111 = Wait of 16 TPB
•
•
•
0001 = Wait of 2 TPB
0000 = Wait of 1 TPB (default)
bit 1-0
WAITE: Data Hold After Read/Write Strobe Wait States bits(1)
11 = Wait of 4 TPB
10 = Wait of 3 TPB
01 = Wait of 2 TPB
00 = Wait of 1 TPB (default)
For Read operations:
11 = Wait of 3 TPB
10 = Wait of 2 TPB
01 = Wait of 1 TPB
00 = Wait of 0 TPB (default)
Note 1: Whenever WAITM = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a
write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: Address bits, A15 and A14, are not subject to automatic increment/decrement if configured as Chip Select
CS2 and CS1.
3: These pins are active when MODE16 = 1 (16-bit mode).
DS60001361J-page 390
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 25-3:
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
(1)
R/W-0
(3)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CS2
ADDR15
7:0
PMADDR: PARALLEL PORT ADDRESS REGISTER
R/W-0
CS1
(2)
ADDR
ADDR14(4)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
CS2: Chip Select 2 bit(1)
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive
bit 15
ADDR: Target Address bit 15(2)
bit 14
CS1: Chip Select 1 bit(3)
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive
bit 14
ADDR: Target Address bit 14(4)
bit 13-0
ADDR: Address bits
Note 1:
2:
3:
4:
When the CSF bits (PMCON) = 10 or 01.
When the CSF bits (PMCON) = 00.
When the CSF bits (PMCON) = 10.
When the CSF bits (PMCON) = 00 or 01.
Note:
If the DUALBUF bit (PMCON) = 0, the bits in this register control both read and write target
addressing. If the DUALBUF bit = 1, the bits in this register are not used. In this instance, use the
PMRADDR register for Read operations and the PMWADDR register for Write operations.
2015-2021 Microchip Technology Inc.
DS60001361J-page 391
PIC32MZ Graphics (DA) Family
REGISTER 25-4:
Bit
Range
31:24
23:16
15:8
7:0
PMDOUT: PARALLEL PORT OUTPUT DATA REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATAOUT
R/W-0
R/W-0
DATAOUT
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 DATAOUT: Port Data Output bits
This register is used for Read operations in the Enhanced Parallel Client mode and Write operations for Dual
Buffer Host mode.
In Dual Buffer Host mode, the DUALBUF bit (PMPCON) = 1, a write to the MSB triggers the transaction
on the PMP port. When MODE16 = 1, MSB = DATAOUT. When MODE16 = 0,
MSB = DATAOUT.
Note:
In Host mode, a read will return the last value written to the register. In Client mode, a read will return indeterminate results.
DS60001361J-page 392
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 25-5:
Bit
Range
31:24
23:16
15:8
7:0
PMDIN: PARALLEL PORT INPUT DATA REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATAIN
R/W-0
R/W-0
DATAIN
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 DATAIN: Port Data Input bits
This register is used for both PMP mode and Enhanced Parallel Client mode.
In Parallel Host mode, a write to the MSB triggers the write transaction on the PMP port. Similarly, a read to
the MSB triggers the read transaction on the PMP port.
When MODE16 = 1, MSB = DATAIN. When MODE16 = 0, MSB = DATAIN.
Note:
This register is not used in Dual Buffer Host mode (i.e., DUALBUF bit (PMPCON) = 1).
2015-2021 Microchip Technology Inc.
DS60001361J-page 393
PIC32MZ Graphics (DA) Family
REGISTER 25-6:
Bit
Range
31:24
23:16
15:8
7:0
PMAEN: PARALLEL PORT PIN ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN(1)
R/W-0
R/W-0
PTEN
R/W-0
PTEN(2)
PTEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Write ‘0’; ignore read
bit 15-14 PTEN: PMCSx Address Port Enable bits
1 = PMA15 and PMA14 function as either PMA or PMCS2 and PMCS1(1)
0 = PMA15 and PMA14 function as port I/O
bit 13-2
PTEN: PMP Address Port Enable bits
1 = PMA function as PMP address lines
0 = PMA function as port I/O
bit 1-0
PTEN: PMALH/PMALL Address Port Enable bits
1 = PMA1 and PMA0 function as either PMA or PMALH and PMALL(2)
0 = PMA1 and PMA0 pads function as port I/O
Note 1:
2:
The use of these pins as PMA15/PMA14 or CS2/CS1 is selected by the CSF bits (PMCON).
The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode
selected by the ADRMUX bits in the PMCON register.
DS60001361J-page 394
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 25-7:
Bit
Range
31:24
23:16
15:8
7:0
PMSTAT: PARALLEL PORT STATUS REGISTER (CLIENT MODES ONLY)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R/W-0, HS, SC
U-0
U-0
R-0
R-0
R-0
R-0
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
R-1
R/W-0, HS, SC
U-0
U-0
R-1
R-1
R-1
R-1
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
Legend:
HS = Hardware Set
SC = Software Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
IBF: Input Buffer Full Status bit
1 = All writable input buffer registers are full
0 = Some or all of the writable input buffer registers are empty
bit 14
IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full input byte buffer has occurred (must be cleared in software)
0 = An overflow has not occurred
Note:
When this bit is set in Client mode, it will generate a PMP Error (PMPE) interrupt.
bit 13-12 Unimplemented: Read as ‘0’
bit 11-8
IBxF: Input Buffer ‘x’ Status Full bits
1 = Input Buffer contains data that has not been read (reading buffer will clear this bit)
0 = Input Buffer does not contain any unread data
bit 7
OBE: Output Buffer Empty Status bit
1 = All readable output buffer registers are empty
0 = Some or all of the readable output buffer registers are full
bit 6
OBUF: Output Buffer Underflow Status bit
1 = A read is occurred from an empty output byte buffer (must be cleared in software)
0 = No underflow is occurred
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
OBxE: Output Buffer ‘x’ Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains data that has not been transmitted
Note:
When this bit is set in Client mode, it will generate a PMP Error (PMPE) interrupt.
2015-2021 Microchip Technology Inc.
DS60001361J-page 395
PIC32MZ Graphics (DA) Family
REGISTER 25-8:
Bit
Range
31:24
23:16
15:8
PMWADDR: PARALLEL PORT WRITE ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(1)
R/W-0
(3)
WCS2
WCS1
(2)
WADDR15
7:0
R/W-0
WADDR
WADDR14(4)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
WCS2: Chip Select 2 bit(1)
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive
bit 15
WADDR: Target Address bit 15(2)
bit 14
WCS1: Chip Select 1 bit(3)
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive
bit 14
WADDR: Target Address bit 14(4)
bit 13-0
WADDR: Address bits
Note 1:
2:
3:
4:
When the CSF bits (PMCON) = 10 or 01.
When the CSF bits (PMCON) = 00.
When the CSF bits (PMCON) = 10.
When the CSF bits (PMCON) = 00 or 01.
Note:
This register is only used when the DUALBUF bit (PMCON) is set to ‘1’.
DS60001361J-page 396
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 25-9:
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(1)
R/W-0
(3)
RCS2
RADDR15
7:0
PMRADDR: PARALLEL PORT READ ADDRESS REGISTER
R/W-0
RCS1
(2)
RADDR
RADDR14(4)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
RCS2: Chip Select 2 bit(1)
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive (RADDR15 function is selected)
bit 15
RADDR: Target Address bit 15(2)
bit 14
RCS1: Chip Select 1 bit(3)
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive (RADDR14 function is selected)
bit 14
RADDR: Target Address bit 14(4)
bit 13-0
RADDR: Address bits
Note 1:
2:
3:
4:
When the CSF bits (PMCON) = 10 or 01.
When the CSF bits (PMCON) = 00.
When the CSF bits (PMCON) = 10.
When the CSF bits (PMCON) = 00 or 01.
Note:
This register is only used when the DUALBUF bit (PMCON) is set to ‘1’.
2015-2021 Microchip Technology Inc.
DS60001361J-page 397
PIC32MZ Graphics (DA) Family
REGISTER 25-10: PMRDIN: PARALLEL PORT READ INPUT DATA REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RDATAIN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RDATAIN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
Note:
RDATAIN: Port Read Input Data bits
This register is only used when the DUALBUF bit (PMCON) is set to ‘1’ and exclusively for reads. If the
DUALBUF bit is ‘0’, the PMDIN register (Register 25-5) is used for reads instead of PMRDIN.
DS60001361J-page 398
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
26.0
EXTERNAL BUS INTERFACE
(EBI)
Note:
With the EBI module, it is possible to connect
asynchronous SRAM and NOR Flash devices, as well
as non-memory devices such as camera sensors and
LCDs.
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 47. “External Bus
Interface (EBI)”, which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
Note 1: Once the EBI module is configured,
external devices will be memory mapped
and can be access from KSEG2 memory
space (see Figure 4-1 through Figure 4-2
in Section 4.0 “Memory Organization”
for more information). The MMU must be
enabled and the TLB must be set up to
access this memory (see Section 50.
“CPU for Devices with MIPS32®
microAptiv™ and M-Class Cores”
(DS60001192) in the “PIC32 Family
Reference
Manual”
for
more
information).
The External Bus Interface (EBI) module provides a
high-speed, convenient way to interface external
parallel memory devices to the PIC32MZ DA family
device.
FIGURE 26-1:
2: When using the EBI module, Graphics
LCD (GLCD) Controller functionality is
not available, as most of the I/O between
the EBI module and the GLCD is shared.
EBI SYSTEM BLOCK DIAGRAM
External Bus Interface
Bus Interface
Memory Interface
EBIA
EBID
SYSCLK
Control
Registers
Address Decoder
EBIBS
EBICS
System
Bus
Data
FIFO
Control Registers
EBIOE
EBIRP
Static Memory Controller
Address
FIFO
2015-2021 Microchip Technology Inc.
EBIWE
EBIRDY
DS60001361J-page 399
EBI Control Registers
Virtual Address
(BF8E_#)
Register
Name
TABLE 26-1:
1014
EBICS0
EBICS1
101C
EBICS2
1020
EBICS3
EBIMSK0
1058
EBIMSK1
105C
EBIMSK2
1060
1094
EBIMSK3
EBISMT0
1098
EBISMT1
109C
EBISMT2
2015-2021 Microchip Technology Inc.
10A0 EBIFTRPD
10A4 EBISMCON
Legend:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
—
—
—
—
—
—
—
—
31:16
15:0
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2000
CSADDR
—
—
—
—
—
—
—
—
31:16
15:0
22/6
CSADDR
31:16
15:0
23/7
—
—
—
—
—
—
—
—
31:16
—
0000
1000
CSADDR
—
All Resets
Bit Range
Bits
1018
1054
EBI REGISTER MAP
0000
2040
CSADDR
0000
1040
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
31:16
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
SMDWIDTH2
—
—
—
—
—
—
—
—
—
REGSEL
TWR
—
—
0020
—
—
—
—
—
—
041C
2D4B
TPRC
TBTA
041C
TRC
2D4B
TPRC
TBTA
041C
TRC
—
—
2D4B
—
—
—
—
—
TRPD
—
SMDWIDTH1
—
—
—
0000
0120
TBTA
TRC
TAS
0000
0120
MEMSIZE
TAS
0000
0020
MEMSIZE
TAS
—
—
TPRC
RDYMODE PAGESIZE PAGEMODE
—
—
MEMTYPE
RDYMODE PAGESIZE PAGEMODE
—
—
MEMSIZE
—
—
RDYMODE PAGESIZE PAGEMODE
—
—
MEMTYPE
TWR
—
—
MEMSIZE
MEMTYPE
TWR
—
—
REGSEL
TWP
31:16
—
MEMTYPE
REGSEL
TWP
15:0
15:0
—
TWP
15:0
31:16
REGSEL
0000
00C8
—
—
—
—
—
—
—
—
0000
SMDWIDTH0
—
—
—
—
—
—
SMRP
0201
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC32MZ Graphics (DA) Family
DS60001361J-page 400
26.1
PIC32MZ Graphics (DA) Family
REGISTER 26-1:
Bit
Range
31:24
23:16
15:8
7:0
EBICSx: EXTERNAL BUS INTERFACE CHIP SELECT REGISTER (‘x’ = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSADDR
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 CSADDR: Base Address for Device bits
Address in physical memory, which will select the external device.
bit 15-0
Unimplemented: Read as ‘0’
Note: Memory base address should be aligned on memory size boundary selected by EBIMSKx. For example,
2MB of memory can be assigned at base address 0x2000_0000 and 0x2020_0000, but not at 0x2010_0000.
2015-2021 Microchip Technology Inc.
DS60001361J-page 401
PIC32MZ Graphics (DA) Family
REGISTER 26-2:
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
7:0
EBIMSKx: EXTERNAL BUS INTERFACE ADDRESS MASK REGISTER (‘x’ = 0-3)
MEMTYPE
REGSEL
R/W-0
R/W-0
R/W-0
MEMSIZE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10-8
REGSEL: Timing Register Set for Chip Select ‘x’ bits
111 = Reserved
•
•
•
011 = Reserved
010 = Use EBISMT2
001 = Use EBISMT1
000 = Use EBISMT0
bit 7-5
MEMTYPE: Select Memory Type for Chip Select ‘x’ bits
111 = Reserved
•
•
•
011 = Reserved
010 = NOR-Flash
001 = SRAM
000 = Reserved
bit 4-0
MEMSIZE: Select Memory Size for Chip Select ‘x’ bits
11111 = Reserved
•
•
•
01010 = Reserved
01001 = 16 MB
01000 = 8 MB
00111 = 4 MB
00110 = 2 MB
00101 = 1 MB
00100 = 512 KB
00011 = 256 KB
00010 = 128 KB
00001 = 64 KB (smaller memories alias within this range)
00000 = Chip Select is not used
DS60001361J-page 402
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 26-3:
Bit
Range
31:24
23:16
15:8
7:0
EBISMTx: EXTERNAL BUS INTERFACE STATIC MEMORY TIMING REGISTER
(‘x’ = 0-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-1
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-0
R/W-0
R/W-0
—
RDYMODE
R/W-0
R/W-0
R/W-1
TPRC(1)
PAGEMODE
R/W-0
Bit
26/18/10/2
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
TAS(1)
Legend:
R = Readable bit
-n = Value at POR
R/W-0
R/W-0
R/W-0
TBTA(1)
R/W-0
R/W-0
TWP(1)
R/W-0
PAGESIZE
R/W-0
R/W-1
TWR(1)
R/W-1
R/W-1
R/W-0
R/W-0
TRC(1)
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26
RDYMODE: Data Ready Device Select bit
The device associated with register set ‘x’ is a data-ready device, and will use the EBIRDYx pin.
1 = EBIRDYx input is used
0 = EBIRDYx input is not used
bit 25-24 PAGESIZE: Page Size for Page Mode Device bits
11 = 32-word page
10 = 16-word page
01 = 8-word page
00 = 4-word page
bit 23
PAGEMODE: Memory Device Page Mode Support bit
1 = Device supports Page mode
0 = Device does not support Page mode
bit 22-19 TPRC: Page Mode Read Cycle Time bits(1)
Read cycle time is TPRC + 1 clock cycle.
bit 18-16 TBTA: Data Bus Turnaround Time bits(1)
Clock cycles (0-7) for static memory between read-to-write, write-to-read, and read-to-read when Chip
Select changes.
bit 15-10 TWP: Write Pulse Width bits(1)
Write pulse width is TWP + 1 clock cycle.
bit 9-8
TWR: Write Address/Data Hold Time bits(1)
Number of clock cycles to hold address or data on the bus.
bit 7-6
TAS: Write Address Setup Time bits(1)
Clock cycles for address setup time. A value of ‘0’ is only valid in the case of SSRAM.
bit 5-0
TRC: Read Cycle Time bits(1)
Read cycle time is TRC + 1 clock cycle.
Note 1:
Refer to Section 47. “External Bus Interface (EBI)” in the “PIC32 Family Reference Manual” for the EBI
timing diagrams and additional information.
2015-2021 Microchip Technology Inc.
DS60001361J-page 403
PIC32MZ Graphics (DA) Family
REGISTER 26-4:
Bit
Range
31:24
23:16
15:8
7:0
EBIFTRPD: EXTERNAL BUS INTERFACE FLASH TIMING REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
TRPD
R/W-0
R/W-0
R/W-0
R/W-0
TRPD
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-12 Unimplemented: Read as ‘0’
bit 11-0
TRPD: Flash Timing bits
These bits define the number of clock cycles to hold the external Flash memory in reset.
DS60001361J-page 404
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 26-5:
Bit
Range
Bit
31/23/15/7
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
23:16
7:0
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
U-0
31:24
15:8
EBISMCON: EXTERNAL BUS INTERFACE STATIC MEMORY CONTROL
REGISTER
SMDWIDTH2
SMDWIDTH1
SMDWIDTH0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-1
SMDWIDTH0
—
—
—
—
—
—
SMRP
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-13 SMDWIDTH2: Static Memory Width for Register EBISMT2 bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = 8 bits
011 = Reserved
010 = Reserved
001 = Reserved
000 = 16 bits
bit 12-10 SMDWIDTH1: Static Memory Width for Register EBISMT1 bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = 8 bits
011 = Reserved
010 = Reserved
001 = Reserved
000 = 16 bits
bit 9-7
SMDWIDTH0: Static Memory Width for Register EBISMT0 bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = 8 bits
011 = Reserved
010 = Reserved
001 = Reserved
000 = 16 bits
bit 6-1
Unimplemented: Read as ‘0’
bit 0
SMRP: Flash Reset/Power-down mode Select bit
After a Reset, the controller internally performs a power-down for Flash, and then sets this bit to ‘1’.
1 = Flash is taken out of Power-down mode
0 = Flash is forced into Power-down mode
2015-2021 Microchip Technology Inc.
DS60001361J-page 405
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 406
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
Note:
CRYPTO ENGINE
Bulk ciphers that are handled by the Crypto Engine
include:
This data sheet summarizes the
features of the PIC32MZ Graphics (DA)
Family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 49. “Crypto
Engine (CE) and Random Number
Generator
(RNG)”
(DS60001246),
which
is
available
from
the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The Crypto Engine is intended to accelerate applications that need cryptographic functions. By executing these functions in the hardware module, software
overhead is reduced, and actions such as encryption, decryption, and authentication can execute
much more quickly.
The Crypto Engine uses an internal descriptor-based
DMA for efficient programming of the security association data and packet pointers (allowing scatter/
gather data fetching). An intelligent state machine
schedules the crypto engines based on the protocol
selection and packet boundaries. The hardware
engines can perform the encryption and authentication in sequence or in parallel.
Key features of the Crypto Engine are:
• Bulk ciphers and hash engines
• Integrated DMA to off-load processing:
- Buffer descriptor-based
- Secure association per buffer descriptor
• Some functions can execute in parallel
FIGURE 27-1:
• AES:
- 128-bit, 192-bit, and 256-bit key sizes
- CBC, ECB, CTR, CFB, and OFB modes
• DES/TDES:
- CBC, ECB, CFB, and OFB modes
Authentication engines that are available through the
Crypto Engine include:
•
•
•
•
•
SHA-1
SHA-256
MD-5
AES-GCM
HMAC operation (for all authentication engines)
The rate of data that can be processed by the Crypto
Engine depends on a number of factors, including:
• Which engine is in use
• Whether the engines are used in parallel or in series
• The demands on source and destination memories
by other parts of the system (i.e., CPU, DMA, etc.)
• The speed of PBCLK5, which drives the Crypto
Engine
Table 27-1 provides typical performance for various
engines. Figure 27-1 illustrates the Crypto Engine
block diagram.
TABLE 27-1:
CRYPTO ENGINE
PERFORMANCE
Engine/
Algorithm
Performance
Factor
(Mbps/MHz)
Maximum Mbps
(PBCLK5 = 100 MHz)
DES
14.4
1440
TDES
6.6
660
AES-128
9.0
900
AES-192
7.9
790
AES-256
7.2
720
MD5
15.6
1560
SHA-1
13.2
1320
SHA-256
9.3
930
CRYPTO ENGINE BLOCK DIAGRAM
INB
FIFO
Packet
RD
DMA
Controller
Crypto
FSM
System
Bus
SFR
System
Bus
AES
Local Bus
27.0
TDES
SHA-1
SHA-256
OUTB
FIFO
Packet
WR
MD5
PBCLK5
2015-2021 Microchip Technology Inc.
DS60001361J-page 407
Crypto Engine Control Registers
5000 CEVER
5004 CECON
5008 CEBDADDR
500C CEBDPADDR
5010 CESTAT
5014 CEINTSRC
5018 CEINTEN
501C CEPOLLCON
5020 CEHDLEN
5024 CETRLLEN
Legend:
CRYPTO ENGINE REGISTER MAP
31/15
30/14
29/13
31:16
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
REVISION
20/4
19/3
18/2
17/1
16/0
VERSION
15:0
0000
ID
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
0000
—
—
SWAPOEN SWRST SWAPEN
—
—
—
—
—
—
—
31:16
0000
0000
0000
BASEADDR
15:0
31:16
ERRMODE
ERROP
ERRPHASE
15:0
—
0000
—
BDSTATE
START
ACTIVE 0000
BDCTRL
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
AREIF
PKTIF
CBDIF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
AREIE
PKTIE
CBDIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
0000
PENDIE 0000
0000
0000
HDRLEN
—
0000
PENDIF 0000
BDPPLCON
31:16
0000
BDPCHST BDPPLEN DMAEN 0000
BDPADDR
15:0
All Resets
Bit Range
Bits
Register
Name
Virtual Address
(BF8E_#)
TABLE 27-2:
—
—
—
—
TRLRLEN
0000
0000
0000
0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 408
27.1
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 27-1:
Bit
Range
31:24
23:16
15:8
7:0
CEVER: CRYPTO ENGINE REVISION, VERSION, AND ID REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R-0
R-0
R-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
REVISION
R-0
R-0
R-0
R-0
R-0
VERSION
R-0
R-0
R-0
R-0
ID
R-0
R-0
R-0
R-0
ID
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 REVISION: Crypto Engine Revision bits
bit 23-16 VERSION: Crypto Engine Version bits
bit 15-0
ID: Crypto Engine Identification bits
2015-2021 Microchip Technology Inc.
DS60001361J-page 409
PIC32MZ Graphics (DA) Family
REGISTER 27-2:
Bit
Range
31:24
23:16
15:8
7:0
CECON: CRYPTO ENGINE CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0, HC
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
SWAPOEN
SWRST
SWAPEN
—
—
BDPCHST
BDPPLEN
DMAEN
Legend:
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8
Unimplemented: Read as ‘0’
bit 7
SWAPOEN: Swap Output Data Enable bit
1 = Output data is byte swapped when written by dedicated DMA
0 = Output data is not byte swapped when written by dedicated DMA
bit 6
SWRST: Software Reset bit
1 = Initiate a software reset of the Crypto Engine
0 = Normal operation
bit 5
SWAPEN: I/O Swap Enable bit
1 = TFDMA inputs and RFDMA outputs are swapped
0 = TFDMA inputs and RFDMA outputs are not swapped
bit 4-3
Unimplemented: Read as ‘0’
bit 2
BDPCHST: Buffer Descriptor Processor (BDP) Fetch Enable bit
This bit should be enabled only after all DMA descriptor programming is completed.
1 = BDP descriptor fetch is enabled
0 = BDP descriptor fetch is disabled
bit 1
BDPPLEN: Buffer Descriptor Processor Poll Enable bit
This bit should be enabled only after all DMA descriptor programming is completed.
1 = Poll for descriptor until valid bit is set
0 = Do not poll
bit 0
DMAEN: DMA Enable bit
1 = Crypto Engine DMA is enabled
0 = Crypto Engine DMA is disabled
DS60001361J-page 410
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 27-3:
Bit
Range
31:24
23:16
15:8
7:0
CEBDADDR: CRYPTO ENGINE BUFFER DESCRIPTOR REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R-0
R-0
R-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
BDPADDR
R-0
R-0
R-0
R-0
R-0
BDPADDR
R-0
R-0
R-0
R-0
R-0
BDPADDR
R-0
R-0
R-0
R-0
R-0
BDPADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
BDPADDR: Current Buffer Descriptor Process Address Status bits
These bits contain the current descriptor address that is being processed by the Buffer Descriptor Processor
(BDP).
REGISTER 27-4:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
CEBDPADDR: CRYPTO ENGINE BUFFER DESCRIPTOR PROCESSOR
REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/w-0
R/w-0
R/w-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/w-0
R/w-0
R/w-0
R/w-0
R/w-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BASEADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BASEADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BASEADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BASEADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
BASEADDR: DMA Base Address Status bits
These bits contain the base address of the DMA controller. After a reset, a fetch starts from this address.
2015-2021 Microchip Technology Inc.
DS60001361J-page 411
PIC32MZ Graphics (DA) Family
REGISTER 27-5:
Bit
Range
31:24
CESTAT: CRYPTO ENGINE STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
R-0
R-0
R-0
R-0
ERRMODE
23:16
15:8
U-0
U-0
—
—
R-0
R-0
Bit
27/19/11/3
Bit
26/18/10/2
R-0
R-0
ERROP
R-0
R-0
R-0
R-0
R-0
Bit
24/16/8/0
R-0
R-0
ERRPHASE
R-0
R-0
R-0
START
ACTIVE
R-0
R-0
R-0
R-0
R-0
R-0
BDSTATE
R-0
Bit
25/17/9/1
BDCTRL
R-0
7:0
R-0
R-0
R-0
R-0
BDCTRL
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 ERRMOD: Internal Error Mode Status bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = CEK operation
010 = KEK operation
001 = Preboot authentication
000 = Normal operation
bit 28-26 ERROP: Internal Error Operation Status bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Authentication
011 = Reserved
010 = Decryption
001 = Encryption
000 = Reserved
bit 25-24 ERRPHASE: Internal Error Phase of DMA Status bits
11 = Destination data
10 = Source data
01 = Security Association (SA) access
00 = Buffer Descriptor (BD) access
bit 23-22 Unimplemented: Read as ‘0’
bit 21-18 BDSTATE: Buffer Descriptor Processor State Status bits
These bits contain a number, which indicates the current state of the BDP:
1111 = Reserved
•
•
•
bit 17
0111 = Reserved
0110 = SA fetch
0101 = Fetch BDP is disabled
0100 = Descriptor is done
0011 = Data phase
0010 = BDP is loading
0001 = Descriptor fetch request is pending
0000 = BDP is idle
START: DMA Start Status bit
1 = DMA start has occurred
0 = DMA start has not occurred
DS60001361J-page 412
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 27-5:
bit 16
bit 15-0
CESTAT: CRYPTO ENGINE STATUS REGISTER (CONTINUED)
ACTIVE: Buffer Descriptor Processor Status bit
1 = BDP is active
0 = BDP is idle
BDCTRL: Descriptor Control Word Status bits
These bits contain the current descriptor control word.
2015-2021 Microchip Technology Inc.
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PIC32MZ Graphics (DA) Family
REGISTER 27-6:
Bit
Range
31:24
23:16
15:8
7:0
CEINTSRC: CRYPTO ENGINE INTERRUPT SOURCE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
—
—
—
—
AREIF
PKTIF
CBDIF
PENDIF
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4
Unimplemented: Read as ‘0’
bit 3
AREIF: Access Response Error Interrupt bit
1 = Error occurred trying to access memory outside the Crypto Engine
0 = No error has occurred
bit 2
PKTIF: DMA Packet Completion Interrupt Status bit
1 = DMA packet was completed
0 = DMA packet was not completed
bit 1
CBDIF: BD Transmit Status bit
1 = Last BD transmit was processed
0 = Last BD transmit has not been processed
bit 0
PENDIF: Crypto Engine Interrupt Pending Status bit
1 = Crypto Engine interrupt is pending (this value is the result of an OR of all interrupts in the Crypto Engine)
0 = Crypto Engine interrupt is not pending
DS60001361J-page 414
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 27-7:
Bit
Range
31:24
23:16
15:8
7:0
CEINTEN: CRYPTO ENGINE INTERRUPT ENABLE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
AREIE
PKTIE
BDPIE
PENDIE(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4
Unimplemented: Read as ‘0’
bit 3
AREIE: Access Response Error Interrupt Enable bit
1 = Access response error interrupts are enabled
0 = Access response error interrupts are not enabled
bit 2
PKTIE: DMA Packet Completion Interrupt Enable bit
1 = DMA packet completion interrupts are enabled
0 = DMA packet completion interrupts are not enabled
bit 1
BDPIE: DMA Buffer Descriptor Processor Interrupt Enable bit
1 = BDP interrupts are enabled
0 = BDP interrupts are not enabled
bit 0
PENDIE: Host Interrupt Enable bit(1)
1 = Crypto Engine interrupts are enabled
0 = Crypto Engine interrupts are not enabled
Note 1:
The PENDIE bit is a Global enable bit and must be enabled together with the other interrupts desired.
2015-2021 Microchip Technology Inc.
DS60001361J-page 415
PIC32MZ Graphics (DA) Family
REGISTER 27-8:
Bit
Range
31:24
23:16
15:8
7:0
CEPOLLCON: CRYPTO ENGINE POLL CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BDPPLCON
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BDPPLCON
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
BDPPLCON: Buffer Descriptor Processor Poll Control bits
These bits determine the number of cycles that the DMA transmit BDP would wait before refetching the
descriptor control word if the previous descriptor fetched was disabled.
DS60001361J-page 416
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 27-9:
Bit
Range
31:24
23:16
15:8
7:0
CEHDLEN: CRYPTO ENGINE HEADER LENGTH REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HDRLEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-8
Unimplemented: Read as ‘0’
bit 7-0
HDRLEN: DMA Header Length bits
For every packet, skip this length of locations and start filling the data.
x = Bit is unknown
REGISTER 27-10: CETRLLEN: CRYPTO ENGINE TRAILER LENGTH REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRLRLEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8
Unimplemented: Read as ‘0’
bit 7-0
TRLRLEN: DMA Trailer Length bits
For every packet, skip this length of locations at the end of the current packet and start putting the next
packet.
2015-2021 Microchip Technology Inc.
DS60001361J-page 417
PIC32MZ Graphics (DA) Family
27.2
Crypto Engine Buffer Descriptors
Host software creates a linked list of buffer descriptors
and the hardware updates them. Table 27-3 provides a
list of the Crypto Engine buffer descriptors, followed by
format descriptions of each buffer descriptor (see
Figure 27-2 through Figure 27-10).
TABLE 27-3:
Name (see Note 1)
BD_CTRL
CRYPTO ENGINE BUFFER DESCRIPTORS
Bit
31/2315/7
Bit
30/22/14/6
31:24
DESC_EN
—
23:16
—
SA_FETCH_EN
15:8
7:0
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
LAST_BD
LIFM
CRY_MODE
—
—
—
23:16
BD_SAADDR
15:8
BD_SAADDR
BD_SRCADDR
23:16
BD_SRCADDR
15:8
BD_SRCADDR
BD_SRCADDR
BD_DSTADDR 31:24
BD_DSTADDR
23:16
BD_DSTADDR
15:8
BD_DSTADDR
BD_UPDPTR
7:0
BD_DSTADDR
31:24
BD_NXTADDR
23:16
BD_NXTADDR
15:8
BD_NXTADDR
7:0
BD_NXTADDR
31:24
BD_UPDADDR
23:16
BD_UPDADDR
15:8
BD_UPDADDR
7:0
BD_UPDADDR
BD_MSG_LEN 31:24
MSG_LENGTH
23:16
MSG_LENGTH
15:8
MSG_LENGTH
7:0
MSG_LENGTH
BD_ENC_OFF 31:24
ENCR_OFFSET
23:16
ENCR_OFFSET
15:8
ENCR_OFFSET
7:0
ENCR_OFFSET
Note
1:
—
BD_SAADR
BD_SCRADDR 31:24
BD_NXTPTR
—
PKT_INT_EN CBD_INT_EN
BD_BUFLEN
BD_SAADDR
7:0
Bit
24/16/8/0
BD_BUFLEN
BD_SA_ADDR 31:24
7:0
Bit
25/17/9/1
The buffer descriptor must be allocated in memory on a 64-bit boundary.
DS60001361J-page 418
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
FIGURE 27-2:
FORMAT OF BD_CTRL
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
31-24
23-16
DESC_EN
—
—
SA_FETCH_EN
Bit
29/21/
13/5
—
Bit
27/19/11/3
Bit
26/18/
10/2
Bit
25/17/9/1
Bit
24/16/8/0
CRY_MODE
—
LAST_BD
—
LIFM
—
PKT_INT_EN
—
CBD_INT_EN
Bit
28/20/12/4
15-8
BD_BUFLEN
7-0
BD_BUFLEN
bit 31
DESC_EN: Descriptor Enable
1 = The descriptor is owned by hardware. After processing the BD, hardware resets this bit to ‘0’.
0 = The descriptor is owned by software
bit 30
Unimplemented: Must be written as ‘0’
bit 29-27 CRY_MODE: Crypto Mode
111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = CEK operation
010 = KEK operation
001 = Preboot authentication
000 = Normal operation
bit 22
SA_FETCH_EN: Fetch Security Association From External Memory
1 = Fetch SA from the SA pointer. This bit needs to be set to ‘1’ for every new packet.
0 = Use current fetched SA or the internal SA
bit 21-20 Unimplemented: Must be written as ‘0’
bit 19
LAST_BD: Last Buffer Descriptors
1 = Last Buffer Descriptor in the chain
0 = More Buffer Descriptors in the chain
After the last BD, the CEBDADDR goes to the base address in CEBDPADDR.
bit 18
LIFM: Last In Frame
In case of Receive Packets (from H/W-> Host), this field is filled by the Hardware to indicate whether the
packet goes across multiple buffer descriptors. In case of transmit packets (from Host -> H/W), this field indicates whether this BD is the last in the frame.
bit 17
PKT_INT_EN: Packet Interrupt Enable
Generate an interrupt after processing the current buffer descriptor, if it is the end of the packet.
bit 16
CBD_INT_EN: CBD Interrupt Enable
Generate an interrupt after processing the current buffer descriptor.
bit 15-0
BD_BUFLEN: Buffer Descriptor Length
This field contains the length of the buffer and is updated with the actual length filled by the receiver.
2015-2021 Microchip Technology Inc.
DS60001361J-page 419
PIC32MZ Graphics (DA) Family
FIGURE 27-3:
Bit
Range
FORMAT OF BD_SADDR
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
31-24
BD_SAADDR
23-16
BD_SAADDR
15-8
BD_SAADDR
7-0
BD_SAADDR
bit 31-0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
BD_SAADDR
23-16
BD_SAADDR
15-8
BD_SAADDR
7-0
BD_SAADDR
Bit
24/16/8/0
Bit
25/17/9/1
Bit
24/16/8/0
BD_SAADDR: Security Association IP Session Address
The sessions’ SA pointer has the keys and IV values.
FIGURE 27-5:
Bit
Range
Bit
25/17/9/1
FORMAT OF BD_SADDR
31-24
bit 31-0
Bit
24/16/8/0
BD_SAADDR: Security Association IP Session Address
The sessions’ SA pointer has the keys and IV values.
FIGURE 27-4:
Bit
Range
Bit
25/17/9/1
FORMAT OF BD_SRCADDR
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
31-24
BD_SCRADDR
23-16
BD_SCRADDR
15-8
BD_SCRADDR
7-0
BD_SCRADDR
bit 31-0
BD_SCRADDR: Buffer Source Address
The source address of the buffer that needs to be passed through the PE-CRDMA for encryption or
authentication. This address must be on a 32-bit boundary.
DS60001361J-page 420
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
FIGURE 27-6:
Bit
Range
FORMAT OF BD_DSTADDR
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31-24
BD_DSTADDR
23-16
BD_DSTADDR
15-8
BD_DSTADDR
7-0
BD_DSTADDR
bit 31-0
BD_DSTADDR: Buffer Destination Address
The destination address of the buffer that needs to be passed through the PE-CRDMA for encryption
or authentication. This address must be on a 32-bit boundary.
FIGURE 27-7:
Bit
Range
FORMAT OF BD_NXTADDR
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
31-24
BD_NXTADDR
23-16
BD_NXTADDR
15-8
BD_NXTADDR
7-0
BD_NXTADDR
bit 31-0
Bit
24/16/8/0
BD_NXTADDR: Next BD Pointer Address Has Next Buffer Descriptor
The next buffer can be a next segment of the previous buffer or a new packet.
FIGURE 27-8:
Bit
Range
Bit
25/17/9/1
FORMAT OF BD_UPDPTR
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31-24
BD_UPDADDR
23-16
BD_UPDADDR
15-8
BD_UPDADDR
7-0
BD_UPDADDR
bit 31-0
BD_UPDADDR: UPD Address Location
The update address has the location where the CRDMA results are posted. The updated results are
the ICV values, key output values as needed.
2015-2021 Microchip Technology Inc.
DS60001361J-page 421
PIC32MZ Graphics (DA) Family
FIGURE 27-9:
Bit
Range
FORMAT OF BD_MSG_LEN
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
31-24
MSG_LENGTH
23-16
MSG_LENGTH
15-8
MSG_LENGTH
7-0
MSG_LENGTH
bit 31-0
Bit
24/16/8/0
MSG_LENGTH: Total Message Length
Total message length for the hash and HMAC algorithms in bytes. Total number of crypto bytes in
case of GCM algorithm (LEN-C).
FIGURE 27-10:
Bit
Range
Bit
25/17/9/1
FORMAT OF BD_ENC_OFF
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31-24
ENCR_OFFSET
23-16
ENCR_OFFSET
15-8
ENCR_OFFSET
7-0
ENCR_OFFSET
bit 31-0
ENCR_OFFSET: Encryption Offset
Encryption offset for the multi-task test cases (both encryption and authentication). The number of
AAD bytes in the case of GCM algorithm (LEN-A).
DS60001361J-page 422
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
27.3
Security Association Structure
Table 27-11 shows the Security Association Structure.
The Crypto Engine uses the Security Association to
determine the settings for processing a Buffer Descriptor Processor. The Security Association contains:
• Which algorithm to use
• Whether to use engines in parallel (for both
authentication and encryption/decryption)
• The size of the key
• Authentication key
• Encryption/decryption key
• Authentication Initialization Vector (IV)
• Encryption IV
FIGURE 27-11:
Bit
31/23/15/7
Name
SA_CTRL
CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
31:24
—
—
VERIFY
—
NO_RX
OR_EN
ICVONLY
IRFLAG
23:16
LNC
LOADIV
FB
FLAGS
—
—
—
ALGO
ENCTYPE
KEYSIZE
15:8
7:0
ALGO
KEYSIZE
MULTITASK
CRYPTOALGO
SA_AUTHKEY1 31:24
AUTHKEY
23:16
AUTHKEY
15:8
AUTHKEY
7:0
AUTHKEY
SA_AUTHKEY2 31:24
AUTHKEY
23:16
AUTHKEY
15:8
AUTHKEY
7:0
AUTHKEY
SA_AUTHKEY3 31:24
AUTHKEY
23:16
AUTHKEY
15:8
AUTHKEY
7:0
AUTHKEY
SA_AUTHKEY4 31:24
AUTHKEY
23:16
AUTHKEY
15:8
AUTHKEY
7:0
AUTHKEY
SA_AUTHKEY5 31:24
AUTHKEY
23:16
AUTHKEY
15:8
AUTHKEY
7:0
AUTHKEY
SA_AUTHKEY6 31:24
AUTHKEY
23:16
AUTHKEY
15:8
AUTHKEY
7:0
AUTHKEY
SA_AUTHKEY7 31:24
AUTHKEY
23:16
AUTHKEY
15:8
AUTHKEY
7:0
AUTHKEY
SA_AUTHKEY8 31:24
AUTHKEY
23:16
AUTHKEY
15:8
AUTHKEY
SA_ENCKEY1
SA_ENCKEY2
Bit
24/16/8/0
7:0
AUTHKEY
31:24
ENCKEY
23:16
ENCKEY
15:8
ENCKEY
7:0
ENCKEY
31:24
ENCKEY
2015-2021 Microchip Technology Inc.
DS60001361J-page 423
PIC32MZ Graphics (DA) Family
FIGURE 27-11:
Bit
31/23/15/7
Name
SA_ENCKEY3
SA_ENCKEY4
SA_ENCKEY5
SA_ENCKEY6
SA_ENCKEY7
SA_ENCKEY8
SA_AUTHIV1
SA_AUTHIV2
SA_AUTHIV3
SA_AUTHIV4
SA_AUTHIV5
SA_AUTHIV6
SA_AUTHIV7
SA_AUTHIV8
CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE (CONTINUED)
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
23:16
ENCKEY
15:8
ENCKEY
7:0
ENCKEY
31:24
ENCKEY
23:16
ENCKEY
15:8
ENCKEY
7:0
ENCKEY
31:24
ENCKEY
23:16
ENCKEY
15:8
ENCKEY
7:0
ENCKEY
31:24
ENCKEY
23:16
ENCKEY
15:8
ENCKEY
7:0
ENCKEY
31:24
ENCKEY
23:16
ENCKEY
15:8
ENCKEY
7:0
ENCKEY
31:24
ENCKEY
23:16
ENCKEY
15:8
ENCKEY
7:0
ENCKEY
31:24
ENCKEY
23:16
ENCKEY
15:8
ENCKEY
7:0
ENCKEY
31:24
AUTHIV
23:16
AUTHIV
15:8
AUTHIV
7:0
AUTHIV
31:24
AUTHIV
23:16
AUTHIV
15:8
AUTHIV
7:0
AUTHIV
31:24
AUTHIV
23:16
AUTHIV
15:8
AUTHIV
7:0
AUTHIV
31:24
AUTHIV
23:16
AUTHIV
15:8
AUTHIV
7:0
AUTHIV
31:24
AUTHIV
23:16
AUTHIV
15:8
AUTHIV
7:0
AUTHIV
31:24
AUTHIV
23:16
AUTHIV
15:8
AUTHIV
7:0
AUTHIV
31:24
AUTHIV
23:16
AUTHIV
15:8
AUTHIV
7:0
AUTHIV
31:24
AUTHIV
23:16
AUTHIV
15:8
AUTHIV
7:0
AUTHIV
DS60001361J-page 424
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
FIGURE 27-11:
Bit
31/23/15/7
Name
SA_ENCIV1
SA_ENCIV2
SA_ENCIV3
SA_ENCIV4
CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE (CONTINUED)
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
31:24
ENCIV
23:16
ENCIV
15:8
ENCIV
7:0
ENCIV
31:24
ENCIV
23:16
ENCIV
15:8
ENCIV
7:0
ENCIV
31:24
ENCIV
23:16
ENCIV
15:8
ENCIV
7:0
ENCIV
31:24
ENCIV
23:16
ENCIV
15:8
ENCIV
7:0
ENCIV
2015-2021 Microchip Technology Inc.
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
DS60001361J-page 425
PIC32MZ Graphics (DA) Family
Table 27-12 shows the Security Association control
word structure.
FIGURE 27-12:
Bit
Range
The Crypto Engine fetches different structures for different flows and ensures that hardware fetches minimum words from SA required for processing. The
structure is ready for hardware optimal data fetches.
FORMAT OF SA_CTRL
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31-24
—
—
VERIFY
—
NO_RX
OR_EN
ICVONLY
IRFLAG
23-16
LNC
LOADIV
FB
FLAGS
—
—
—
ALGO
ENC
KEY
SIZE
15-8
7-0
ALGO
KEY
SIZE
MULTITASK
CRYPTOALGO
bit 31-30 Reserved: Do not use
bit 29
VERIFY: NIST Procedure Verification Setting
1 = NIST procedures are to be used
0 = Do not use NIST procedures
bit 28
Reserved: Do not use
bit 27
NO_RX: Receive DMA Control Setting
1 = Only calculate ICV for authentication calculations
0 = Normal processing
bit 26
OR_EN: OR Register Bits Enable Setting
1 = OR the register bits with the internal value of the CSR register
0 = Normal processing
bit 25
ICVONLY: Incomplete Check Value Only Flag
This affects the SHA-1 algorithm only. It has no effect on the AES algorithm.
1 = Only three words of the HMAC result are available
0 = All results from the HMAC result are available
bit 24
IRFLAG: Immediate Result of Hash Setting
This bit is set when the immediate result for hashing is requested.
1 = Save the immediate result for hashing
0 = Do not save the immediate result
bit 23
LNC: Load New Keys Setting
1 = Load a new set of keys for encryption and authentication
0 = Do not load new keys
bit 22
LOADIV: Load IV Setting
1 = Load the IV from this Security Association
0 = Use the next IV
bit 21
FB: First Block Setting
This bit indicates that this is the first block of data to feed the IV value.
1 = Indicates this is the first block of data
0 = Indicates this is not the first block of data
bit 20
FLAGS: Incoming/Outgoing Flow Setting
1 = Security Association is associated with an outgoing flow
0 = Security Association is associated with an incoming flow
bit 19-17 Reserved: Do not use
DS60001361J-page 426
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
Figure 27-12: Format of SA_CTRL (Continued)
bit 16-10 ALGO: Type of Algorithm to Use
1xxxxxx = HMAC 1
x1xxxxx = SHA-256
xx1xxxx = SHA1
xxx1xxx = MD5
xxxx1xx = AES
xxxxx1x = TDES
xxxxxx1 = DES
bit 9
ENC: Type of Encryption Setting
1 = Encryption
0 = Decryption
bit 8-7
KEYSIZE: Size of Keys in SA_AUTHKEYx or SA_ENCKEYx
11 = Reserved; do not use
10 = 256 bits
01 = 192 bits
00 = 128 bits(1)
bit 6-4
MULTITASK: How to Combine Parallel Operations in the Crypto Engine
111 = Parallel pass (decrypt and authenticate incoming data in parallel)
101 = Pipe pass (encrypt the incoming data, and then perform authentication on the encrypted data)
011 = Reserved
010 = Reserved
001 = Reserved
000 = Encryption or authentication or decryption (no pass)
bit 3-0
CRYPTOALGO: Mode of operation for the Crypto Algorithm
1111 = Reserved
1110 = AES_GCM
(for AES processing)
1101 = RCTR
(for AES processing)
1100 = RCBC_MAC (for AES processing)
1011 = ROFB
(for AES processing)
1010 = RCFB
(for AES processing)
1001 = RCBC
(for AES processing)
1000 = REBC
(for AES processing)
0111 = TOFB
(for Triple-DES processing)
0110 = TCFB
(for Triple-DES processing)
0101 = TCBC
(for Triple-DES processing)
0100 = TECB
(for Triple-DES processing)
0011 = OFB
(for DES processing)
0010 = CFB
(for DES processing)
0001 = CBC
(for DES processing)
0000 = ECB
(for DES processing)
Note 1:
This setting does not alter the size of SA_AUTHKEYx or SA_ENCKEYx in the Security Association,
only the number of bits of SA_AUTHKEYx and SA_ENCKEYx that are used.
2015-2021 Microchip Technology Inc.
DS60001361J-page 427
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 428
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
28.0
Note:
RANDOM NUMBER
GENERATOR (RNG)
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 49. “Crypto
Engine (CE) and Random Number
Generator (RNG)” (DS60001246), which
is available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The Random Number Generator (RNG) core implements a thermal noise-based, True Random Number
Generator (TRNG) and a cryptographically secure
Pseudo-Random Number Generator (PRNG).
The TRNG uses multiple ring oscillators and the inherent thermal noise of integrated circuits to generate true
random numbers that can initialize the PRNG.
The PRNG is a flexible LFSR, which is capable of
manifesting a maximal length LFSR of up to 64-bits.
FIGURE 28-1:
RANDOM NUMBER
GENERATOR BLOCK
DIAGRAM
System Bus
SFR
PRNG
PBCLK5
TRNG
BIAS Corrector
Edge Comparator
The following are some of the key features of the
Random Number Generator:
• TRNG:
- Up to 25 Mbps of random bits
- Multi-Ring Oscillator based design
- Built-in Bias Corrector
• PRNG:
- LFSR-based
- Up to 64-bit polynomial length
- Programmable polynomial
- TRNG can be seed value
2015-2021 Microchip Technology Inc.
Ring
Oscillator
Ring
Oscillator
DS60001361J-page 429
RNG Control Registers
TABLE 28-1:
6008
600C
RNGCON
RNGPOLY1
RNGPOLY2
6010 RNGNUMGEN1
6014 RNGNUMGEN2
6018
601C
6020
Legend:
RNGSEED1
RNGSEED2
RNGCNT
31/15
30/14
29/13
28/12
27/11
26/10
25/9
31:16
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
ID
15:0
xxxx
VERSION
REVISION
31:16
—
—
—
—
—
—
15:0
—
—
—
LOAD
TRNGMODE
CONT
—
—
—
—
—
PRNGEN TRNGEN
31:16
—
—
xxxx
—
—
—
PLEN
31:16
FFFF
0000
FFFF
POLY
15:0
31:16
0000
FFFF
RNG
15:0
31:16
FFFF
FFFF
RNG
15:0
31:16
FFFF
0000
SEED
15:0
31:16
0000
0000
SEED
15:0
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
0064
POLY
15:0
All Resets
Register
Name
RNGVER
Bit Range
Virtual Address
(BF8E_#)
Bits
6000
6004
RANDOM NUMBER GENERATOR (RNG) REGISTER MAP
0000
—
—
—
—
RCNT
—
—
—
0000
0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 430
28.1
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 28-1:
Bit
Range
31:24
23:16
15:8
7:0
RNGVER: RANDOM NUMBER GENERATOR VERSION REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
ID
R-0
R-0
R-0
R-0
ID
R-0
R-0
R-0
R-0
VERSION
R-0
R-0
R-0
R-0
R-0
REVISION
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-6
ID: Block Identification bits
bit 15-8
VERSION: Block Version bits
bit 7-0
REVISION: Block Revision bits
2015-2021 Microchip Technology Inc.
x = Bit is unknown
DS60001361J-page 431
PIC32MZ Graphics (DA) Family
REGISTER 28-2:
Bit
Range
31:24
23:16
15:8
7:0
RNGCON: RANDOM NUMBER GENERATOR CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
LOAD
TRNGMODE(1)
CONT
PRNGEN
TRNGEN
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
PLEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12
LOAD: Device Select bit
This bit is self-clearing and is used to load the seed from the TRNG (i.e., the random value) as a seed to
the PRNG.
bit 11
TRNGMODE: True Random Number Generator Mode bit(1)
1 = Enhanced TRNG mode is selected
0 = Normal TRNG mode is selected
bit 10
CONT: PRNG Number Shift Enable bit
1 = The PRNG random number is shifted every cycle
0 = The PRNG random number is shifted when the previous value is removed
bit 9
PRNGEN: PRNG Operation Enable bit
1 = PRNG operation is enabled
0 = PRNG operation is not enabled
bit 8
TRNGEN: TRNG Operation Enable bit
1 = TRNG operation is enabled
0 = TRNG operation is not enabled
bit 7-0
PLEN: PRNG Polynomial Length bits
These bits contain the length of the polynomial used for the PRNG.
Note 1:
This bit is effective only when the TRNGEN bit is set to ‘1’.
DS60001361J-page 432
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 28-3:
Bit
Range
31:24
23:16
15:8
7:0
RNGPOLYx: RANDOM NUMBER GENERATOR POLYNOMIAL REGISTER ‘x’
(‘x’ = 1 OR 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POLY
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
POLY
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POLY
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POLY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
POLY: PRNG LFSR Polynomial MSb/LSb bits (RNGPOLY1 = LSb, RNGPOLY2 = MSb)
REGISTER 28-4:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
RNGNUMGENx: RANDOM NUMBER GENERATOR REGISTER ‘x’ (‘x’ = 1 OR 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RNG
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RNG
R/W-1
RNG
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RNG
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
RNG: Current PRNG MSb/LSb Value bits (RNGNUMGEN1 = LSb, RNGNUMGEN2 = MSb)
Note: RNGNUMGEN2 must be read before RNGNUMGEN1.
2015-2021 Microchip Technology Inc.
DS60001361J-page 433
PIC32MZ Graphics (DA) Family
REGISTER 28-5:
Bit
Range
31:24
23:16
15:8
7:0
RNGSEEDx: TRUE RANDOM NUMBER GENERATOR SEED REGISTER ‘x’
(‘x’ = 1 OR 2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R-0
R-0
R-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
SEED
R-0
R-0
R-0
R-0
R-0
SEED
R-0
R-0
R-0
R-0
R-0
SEED
R-0
R-0
R-0
R-0
R-0
SEED
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
SEED: TRNG MSb/LSb Value bits (RNGSEED1 = LSb, RNGSEED2 = MSb)
Note: RNGSEED2 must be read before RNGSEED1.
REGISTER 28-6:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
RNGCNT: TRUE RANDOM NUMBER GENERATOR COUNT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
RCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-7
Unimplemented: Read as ‘0’
bit 6-0
RCNT: Number of Valid TRNG MSB 32 bits
DS60001361J-page 434
x = Bit is unknown
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
29.0
Note:
12-BIT HIGH-SPEED
SUCCESSIVE APPROXIMATION
REGISTER (SAR) ANALOG-TODIGITAL CONVERTER (ADC)
This data sheet summarizes the features
of the PIC32MZ DA family of devices. It is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section
22.
“12-bit
High-Speed
Successive Approximation Register
(SAR) Analog-to-Digital
Converter
(ADC)” (DS60001344) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
The 12-bit High-Speed Successive Approximation
Register (SAR) Analog-to-Digital Converter (ADC)
includes the following features:
• 12-bit resolution
• Six ADC modules with dedicated Sample and
Hold (S&H) circuits
• Two dedicated ADC modules can be combined in
Turbo mode to provide double conversion rate
(clock sources for combined ADCs must be
synchronous)
• Up to 45 analog input sources, in addition to the
internal CTMU, VBAT, internal voltage reference
and internal temperature sensor
• Single-ended and/or differential inputs
• Can operate during Sleep mode
• Supports touch sense applications
• Six digital comparators
• Six digital filters supporting two modes:
- Oversampling mode
- Averaging mode
• 16-word FIFO on ADC0 through ADC4 for
increased throughput
• Early interrupt generation resulting in faster
processing of converted data
• Designed for motor control, power conversion,
and general purpose applications
• Operation during Sleep and Idle modes
A simplified block diagram of the ADC module is
illustrated in Figure 29-1.
The 12-bit HS SAR ADC has up to five dedicated
ADC modules (ADC0-ADC4) and one shared ADC
module (ADC7). The dedicated ADC modules use a
single input (or its alternate) and are intended for
high-speed and precise sampling of time-sensitive or
transient inputs. The the shared ADC module
incorporates a multiplexer on the input to facilitate a
larger group of inputs, with slower sampling, and
provides flexible automated scanning option through
the input scan logic.
For each ADC module, the analog inputs are
connected to the S&H capacitor. The clock, sampling
time, and output data resolution for each ADC
module can be set independently. The ADC module
performs the conversion of the input analog signal
based on the configurations set in the registers.
When conversion is complete, the final result is
stored in the result buffer for the specific analog
input and is passed to the digital filter and digital
comparator if configured to use data from this
particular sample. Input to ADCx mapping is
illustrated in Figure 29-2.
29.1
Activation Sequence
Step 1: Initialize the ADC calibration values by copying
them from the factory programmed DEVADCx Flash
locations starting at 0xBFC45000 into the ADCxCFG
registers starting at 0xBF887D00. Then, configure the
AICPMPEN bit (ADCCON1 and the IOANCPEN
bit (CFGCON) = 1 if and only if VDD is less than
2.5V. The default is ‘0’, which assumes VDD is greater
than or equal to 2.5V.
Step 2: The user writes all the essential ADC configuration SFRs including the ADC control clock and all
ADC core clocks setup:
• ADCCON1, keeping the ON bit = 0
• ADCCON2, especially paying attention to ADCDIV and SAMC
• ADCANCON, keeping all analog enables ANENx
bit = 0, WKUPCLKCNT bit = 0xA
• ADCCON3, keeping all DIGEN5x = 0, especially
paying attention to ADCSEL, CONCLKDIV
, and VREFSEL
• ADCxTIME, ADCDIVx, and SAMCx
• ADCTRGMODE, ADCIMCONx, ADCTRGSNS,
ADCCSSx, ADCGIRQENx, ADCTRGx, ADCBASE
• Comparators, filters, and so on
Step 3: The user sets the ANENx bit to ‘1’ for the ADC
SAR Cores needed (which internally in the ADC module enables the control clock to generate by division the
core clocks for the desired ADC SAR Cores, which in
turn enables the bias circuitry for these ADC SAR
Cores).
2015-2021 Microchip Technology Inc.
DS60001361J-page 435
PIC32MZ Graphics (DA) Family
Step 4: The user sets the ON bit to ‘1’, which enables
the ADC control clock. The following ADCx activation
sequence is to be followed at all times:
Standard non-interleaved dedicated Class_1 ADCx
throughput rate formula is shown in Equation 29-1.
Step 5: The user waits for the interrupt/polls the BGVRRDY bit (ADCCON2) and the WKRDYx bit
(ADCANCON) = 1, which signals that the
device analog environment (band gap and VREF) is
ready.
EQUATION 29-1:
Step 6: Set the DIGENx bit (ADCCON3) to
‘1’, which enables the digital circuitry to immediately
begin processing incoming triggers to perform data
conversions.
TABLE 29-1:
= 1 / ((SAMC+# bit resolution+1)(TAD))
Example:
SAMC = 3 TAD, 12-bit mode, TAD = 20 ns = 50 MHz:
Throughput rate:
= 1 / ((3+13)(20 ns))
= 1/(16 * 20 ns)
= 3.125 msps
PIC32MZXXDAXX INTERLEAVED ADC THROUGHPUT RATES
#No.of Interleaved
ADC Possible
Note:
THROUGHPUT RATE
ADC Throughput Rate = 1/((Sample time + Conversion time)(TAD))
ADC TAD(min) = 20ns (50Mhz max)
12-bit
(max.) msps
10-bit
(max.) msps
8-bit
(max.) msps
6-bit
(max.) msps
1
3.125 msps
3.571 msps
4.167 msps
5.0 msps
2
6.250 msps
7.143 msps
8.333 msps
10.00 msps
3
8.330 msps
10.00 msps
12.50 msps
12.50 msps
4
12.50 msps
12.50 msps
16.667 msps
16.667 msps
Interleaved ADCs in this context means connecting the same analog source signal to multiple dedicated
Class_1 ADCs (i.e., ADC0-ADC5), and using independent staggered trigger sources accordingly for each
interleaved ADC.
Note 1: Prior to enabling the ADC module, the
user application must copy the ADC
calibration data (DEVADC0-DEVADC4,
DEVADC7; see Register 41-8) from the
Configuration memory into the ADC
Configuration registers (ADC0CFGADC4CFG, ADC7CFG).
2: If VDDIO is greater than 2.5V, set the
AICPMPEN bit (ADCCON1) and
the IOANCPEN bit (CFGCON) to ‘0’.
If VDDIO is less than 2.5V, set both bits
to ‘1’.
DS60001361J-page 436
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
FIGURE 29-1:
AN0
AN45
N/C
N/C
ADC BLOCK DIAGRAM
00
01
10
11
SH0ALT
(ADCTRGMODE)
AN5
VREFL
AVSS
AVDD
VREF+
VREF-
00
ADCSEL
10 11
TCLK
CONCLKDIV
VREFSEL
1
0
VREFH
DIFF0
(ADCIMCON1)
VREFL
TAD0-TAD4
ADCDIV
(ADCxTIME)
TQ
ADC0
TAD7
AN4
AN49
N/C
N/C
01
ADCDIV
(ADCCON2)
00
01
10
11
SH4ALT
(ADCTRGMODE)
AN9
VREFL
1
0
ADC4
DIFF4
(ADCIMCON1)
AN5
CTMUT (AN40)
VBAT (AN41)
AN38
IVREF (AN42)
AN39
IVTEMP (AN43)
ADC7
AN10
VREFL
1
0
DIFFx
x = 5 to 43
(ADCIMCONy)
y = 1 to 3,
z = 1 to 31 (Odd numbers)
ADCDATA0
…...
FIFO
ADCDATA43
Digital Comparator
Data
Interrupt/Event
Triggers,
Turbo Channel,
Scan Control Logic
Trigger
Capacitive Voltage
Divider (CVD)
Status and Control
Registers
2015-2021 Microchip Technology Inc.
System Bus
Digital Filter
Interrupt/Event
Interrupt
DS60001361J-page 437
PIC32MZ Graphics (DA) Family
FIGURE 29-2:
S&H BLOCK DIAGRAM
ADC0
AN0
00
AN3
00
AN45
01
AN48
01
N/C
10
N/C
10
N/C
11
N/C
11
ADC3
SAR
SAR
SH3ALT
(ADCTRGMODE 7).
Note:
This register can only be modified when the CAN module is in Configuration mode (OPMOD
(CiCON) = 100).
2015-2021 Microchip Technology Inc.
DS60001361J-page 501
PIC32MZ Graphics (DA) Family
REGISTER 30-3:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
CiINT: CAN INTERRUPT REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
IVRIE
WAKIE
CERRIE
SERRIE
RBOVIE
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
MODIE
CTMRIE
RBIE
TBIE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
SERRIF
(1)
IVRIF
WAKIF
CERRIF
RBOVIF
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
MODIF
CTMRIF
RBIF
TBIF
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
IVRIE: Invalid Message Received Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 30
WAKIE: CAN Bus Activity Wake-up Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 29
CERRIE: CAN Bus Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 28
SERRIE: System Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 27
RBOVIE: Receive Buffer Overflow Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
x = Bit is unknown
bit 26-20 Unimplemented: Read as ‘0’
bit 19
MODIE: Mode Change Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 18
CTMRIE: CAN Timestamp Timer Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 17
RBIE: Receive Buffer Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 16
TBIE: Transmit Buffer Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 15
IVRIF: Invalid Message Received Interrupt Flag bit
1 = An invalid messages interrupt has occurred
0 = An invalid message interrupt has not occurred
Note 1:
This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit
(CiCON).
DS60001361J-page 502
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 30-3:
CiINT: CAN INTERRUPT REGISTER (CONTINUED)
bit 14
WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit
1 = A bus wake-up activity interrupt has occurred
0 = A bus wake-up activity interrupt has not occurred
bit 13
CERRIF: CAN Bus Error Interrupt Flag bit
1 = A CAN bus error has occurred
0 = A CAN bus error has not occurred
bit 12
SERRIF: System Error Interrupt Flag bit
1 = A system error occurred (typically an illegal address was presented to the System Bus)
0 = A system error has not occurred
bit 11
RBOVIF: Receive Buffer Overflow Interrupt Flag bit
1 = A receive buffer overflow has occurred
0 = A receive buffer overflow has not occurred
bit 10-4
Unimplemented: Read as ‘0’
bit 3
MODIF: CAN Mode Change Interrupt Flag bit
1 = A CAN module mode change has occurred (OPMOD has changed to reflect REQOP)
0 = A CAN module mode change has not occurred
bit 2
CTMRIF: CAN Timer Overflow Interrupt Flag bit
1 = A CAN timer (CANTMR) overflow has occurred
0 = A CAN timer (CANTMR) overflow has not occurred
bit 1
RBIF: Receive Buffer Interrupt Flag bit
1 = A receive buffer interrupt is pending
0 = A receive buffer interrupt is not pending
bit 0
TBIF: Transmit Buffer Interrupt Flag bit
1 = A transmit buffer interrupt is pending
0 = A transmit buffer interrupt is not pending
Note 1:
This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit
(CiCON).
2015-2021 Microchip Technology Inc.
DS60001361J-page 503
PIC32MZ Graphics (DA) Family
REGISTER 30-4:
Bit
Range
31:24
23:16
15:8
7:0
CiVEC: CAN INTERRUPT CODE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
—
—
—
U-0
R-1
R-0
FILHIT
R-0
ICODE(1)
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12-8
FILHIT: Filter Hit Number bit
11111 = Filter 31
11110 = Filter 30
•
•
•
00001 = Filter 1
00000 = Filter 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
ICODE: Interrupt Flag Code bits(1)
1001000-1111111 = Reserved
1001000 = Invalid message received (IVRIF)
1000111 = CAN module mode change (MODIF)
1000110 = CAN timestamp timer (CTMRIF)
1000101 = Bus bandwidth error (SERRIF)
1000100 = Address error interrupt (SERRIF)
1000011 = Receive FIFO overflow interrupt (RBOVIF)
1000010 = Wake-up interrupt (WAKIF)
1000001 = Error Interrupt (CERRIF)
1000000 = No interrupt
0100000-0111111 = Reserved
0011111 = FIFO31 Interrupt (CiFSTAT set)
0011110 = FIFO30 Interrupt (CiFSTAT set)
•
•
•
0000001 = FIFO1 Interrupt (CiFSTAT set)
0000000 = FIFO0 Interrupt (CiFSTAT set)
Note 1:
These bits are only updated for enabled interrupts.
DS60001361J-page 504
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 30-5:
Bit
Range
31:24
23:16
15:8
7:0
CiTREC: CAN TRANSMIT/RECEIVE ERROR COUNT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R-0
R-0
R-0
R-0
R-0
R-0
—
—
TXBO
TXBP
RXBP
TXWARN
RXWARN
EWARN
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
TERRCNT
R-0
RERRCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-22 Unimplemented: Read as ‘0’
bit 21
TXBO: Transmitter in Error State Bus OFF (TERRCNT 256)
bit 20
TXBP: Transmitter in Error State Bus Passive (TERRCNT 128)
bit 19
RXBP: Receiver in Error State Bus Passive (RERRCNT 128)
bit 18
TXWARN: Transmitter in Error State Warning (128 > TERRCNT 96)
bit 17
RXWARN: Receiver in Error State Warning (128 > RERRCNT 96)
bit 16
EWARN: Transmitter or Receiver is in Error State Warning
bit 15-8
TERRCNT: Transmit Error Counter
bit 7-0
RERRCNT: Receive Error Counter
REGISTER 30-6:
Bit
Range
31:24
23:16
15:8
7:0
CiFSTAT: CAN FIFO STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FIFOIP31
FIFOIP30
FIFOIP29
FIFOIP28
FIFOIP27
FIFOIP26
FIFOIP25
FIFOIP24
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FIFOIP23
FIFOIP22
FIFOIP21
FIFOIP20
FIFOIP19
FIFOIP18
FIFOIP17
FIFOIP16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FIFOIP15
FIFOIP14
FIFOIP13
FIFOIP12
FIFOIP11
FIFOIP10
FIFOIP9
FIFOIP8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FIFOIP7
FIFOIP6
FIFOIP5
FIFOIP4
FIFOIP3
FIFOIP2
FIFOIP1
FIFOIP0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 FIFOIP: FIFOn Interrupt Pending bits
1 = One or more enabled FIFO interrupts are pending
0 = No FIFO interrupts are pending
2015-2021 Microchip Technology Inc.
DS60001361J-page 505
PIC32MZ Graphics (DA) Family
REGISTER 30-7:
Bit
Range
31:24
23:16
15:8
7:0
CiRXOVF: CAN RECEIVE FIFO OVERFLOW STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
R-0
R-0
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
RXOVF31
RXOVF30
RXOVF29
RXOVF28
RXOVF27
R-0
R-0
R-0
R-0
R-0
RXOVF23
RXOVF22
RXOVF21
RXOVF20
RXOVF19
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RXOVF15
RXOVF14
RXOVF13
RXOVF12
RXOVF11
RXOVF10
RXOVF9
RXOVF8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RXOVF7
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0
RXOVF26 RXOVF25
R-0
R-0
RXOVF24
R-0
RXOVF18 RXOVF17
R-0
RXOVF16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
RXOVF: FIFOn Receive Overflow Interrupt Pending bit
1 = FIFO has overflowed
0 = FIFO has not overflowed
REGISTER 30-8:
Bit
Range
31:24
23:16
15:8
7:0
x = Bit is unknown
CiTMR: CAN TIMER REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CANTS
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CANTS
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CANTSPRE
R/W-0
R/W-0
CANTSPRE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0
CANTS: CAN Time Stamp Timer bits
This is a free-running timer that increments every CANTSPRE system clocks when the CANCAP bit
(CiCON) is set.
bit 15-0
CANTSPRE: CAN Time Stamp Timer Prescaler bits
1111 1111 1111 1111 = CAN time stamp timer (CANTS) increments every 65,535 system clocks
•
•
•
0000 0000 0000 0000 = CAN time stamp timer (CANTS) increments every system clock
Note 1:
2:
CiTMR will be frozen when CANCAP = 0.
The CiTMR prescaler count will be reset on any write to CiTMR (CANTSPRE will be unaffected).
DS60001361J-page 506
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 30-9:
Bit
Range
31:24
23:16
15:8
7:0
CiRXMN: CAN ACCEPTANCE FILTER MASK N REGISTER (N = 0, 1, 2 OR 3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
SID
R/W-0
R/W-0
R/W-0
U-0
SID
R/W-0
—
MIDE
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EID
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EID
R/W-0
EID
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-21
SID: Standard Identifier bits
1 = Include bit, SIDx, in filter comparison
0 = Bit SIDx is ‘don’t care’ in filter operation
x = Bit is unknown
bit 20
Unimplemented: Read as ‘0’
bit 19
MIDE: Identifier Receive Mode bit
1 = Match only message types (standard/extended address) that correspond to the EXID bit in filter
0 = Match either standard or extended address message if filters match (that is, if (Filter SID) = (Message
SID) or if (FILTER SID/EID) = (Message SID/EID))
bit 18
Unimplemented: Read as ‘0’
bit 17-0
EID: Extended Identifier bits
1 = Include bit, EIDx, in filter comparison
0 = Bit EIDx is ‘don’t care’ in filter operation
Note:
This register can only be modified when the CAN module is in Configuration mode (OPMOD
(CiCON) = 100).
2015-2021 Microchip Technology Inc.
DS60001361J-page 507
PIC32MZ Graphics (DA) Family
REGISTER 30-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN3
R/W-0
FLTEN2
R/W-0
FLTEN1
R/W-0
FLTEN0
MSEL3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL2
MSEL1
R/W-0
Bit
25/17/9/1
FSEL3
MSEL2
R/W-0
Bit
26/18/10/2
R/W-0
FSEL1
MSEL0
R/W-0
FSEL0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
FLTEN3: Filter 3 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29
MSEL3: Filter 3 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24
FSEL3: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN2: Filter 2 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21
MSEL2: Filter 2 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16
FSEL2: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
x = Bit is unknown
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001361J-page 508
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 30-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0 (CONTINUED)
bit 15
FLTEN1: Filter 1 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13
MSEL1: Filter 1 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL1: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN0: Filter 0 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL0: Filter 0 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL0: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2015-2021 Microchip Technology Inc.
DS60001361J-page 509
PIC32MZ Graphics (DA) Family
REGISTER 30-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN7
R/W-0
FLTEN6
R/W-0
FLTEN5
R/W-0
FLTEN4
MSEL7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL6
MSEL5
R/W-0
Bit
25/17/9/1
FSEL7
MSEL6
R/W-0
Bit
26/18/10/2
R/W-0
FSEL5
MSEL4
R/W-0
FSEL4
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
FLTEN7: Filter 7 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL7: Filter 7 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL7: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN6: Filter 6 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL6: Filter 6 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL6: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001361J-page 510
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 30-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1 (CONTINUED)
bit 15
FLTEN5: Filter 17 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL5: Filter 5 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL5: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN4: Filter 4 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL4: Filter 4 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL4: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2015-2021 Microchip Technology Inc.
DS60001361J-page 511
PIC32MZ Graphics (DA) Family
REGISTER 30-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN11
R/W-0
FLTEN10
R/W-0
FLTEN9
R/W-0
FLTEN8
MSEL11
R/W-0
FSEL11
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSEL10
R/W-0
FSEL10
R/W-0
MSEL9
R/W-0
R/W-0
R/W-0
FSEL9
R/W-0
MSEL8
R/W-0
FSEL8
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
FLTEN11: Filter 11 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29
MSEL11: Filter 11 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24
FSEL11: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN10: Filter 10 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21
MSEL10: Filter 10 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16
FSEL10: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
x = Bit is unknown
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001361J-page 512
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 30-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2 (CONTINUED)
bit 15
FLTEN9: Filter 9 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13
MSEL9: Filter 9 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL9: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN8: Filter 8 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL8: Filter 8 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL8: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2015-2021 Microchip Technology Inc.
DS60001361J-page 513
PIC32MZ Graphics (DA) Family
REGISTER 30-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN15
R/W-0
FLTEN14
R/W-0
FLTEN13
R/W-0
FLTEN12
MSEL15
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL14
R/W-0
MSEL13
R/W-0
Bit
25/17/9/1
FSEL15
MSEL14
R/W-0
Bit
26/18/10/2
R/W-0
FSEL13
R/W-0
MSEL12
R/W-0
FSEL12
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
FLTEN15: Filter 15 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29
MSEL15: Filter 15 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24
FSEL15: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN14: Filter 14 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21
MSEL14: Filter 14 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16
FSEL14: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
x = Bit is unknown
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001361J-page 514
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 30-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3 (CONTINUED)
bit 15
FLTEN13: Filter 13 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13
MSEL13: Filter 13 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL13: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN12: Filter 12 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL12: Filter 12 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL12: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2015-2021 Microchip Technology Inc.
DS60001361J-page 515
PIC32MZ Graphics (DA) Family
,4
REGISTER 30-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN19
R/W-0
FLTEN18
R/W-0
FLTEN17
R/W-0
FLTEN16
MSEL19
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL18
R/W-0
MSEL17
R/W-0
Bit
25/17/9/1
FSEL19
MSEL18
R/W-0
Bit
26/18/10/2
R/W-0
FSEL17
R/W-0
MSEL16
R/W-0
FSEL16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
FLTEN19: Filter 19 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29
MSEL19: Filter 19 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24
FSEL19: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN18: Filter 18 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21
MSEL18: Filter 18 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16
FSEL18: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
x = Bit is unknown
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001361J-page 516
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 30-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4 (CONTINUED)
bit 15
FLTEN17: Filter 13 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13
MSEL17: Filter 17 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL17: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN16: Filter 16 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL16: Filter 16 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL16: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2015-2021 Microchip Technology Inc.
DS60001361J-page 517
PIC32MZ Graphics (DA) Family
REGISTER 30-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5
Bit
Range
31:24
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN23
R/W-0
23:16
FLTEN22
R/W-0
15:8
FLTEN21
R/W-0
7:0
FLTEN20
MSEL23
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL22
R/W-0
MSEL21
R/W-0
Bit
25/17/9/1
FSEL23
MSEL22
R/W-0
Bit
26/18/10/2
R/W-0
FSEL21
R/W-0
MSEL20
R/W-0
FSEL20
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
FLTEN23: Filter 23 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29
MSEL23: Filter 23 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24
FSEL23: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
x = Bit is unknown
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN22: Filter 22 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21
MSEL22: Filter 22 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16
FSEL22: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001361J-page 518
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 30-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5 (CONTINUED)
bit 15
FLTEN21: Filter 21 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13
MSEL21: Filter 21 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL21: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN20: Filter 20 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL20: Filter 20 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL20: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2015-2021 Microchip Technology Inc.
DS60001361J-page 519
PIC32MZ Graphics (DA) Family
REGISTER 30-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN27
R/W-0
FLTEN26
R/W-0
FLTEN25
R/W-0
FLTEN24
MSEL27
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL26
R/W-0
MSEL25
R/W-0
Bit
25/17/9/1
FSEL27
MSEL26
R/W-0
Bit
26/18/10/2
R/W-0
FSEL25
R/W-0
MSEL24
R/W-0
FSEL24
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
FLTEN27: Filter 27 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL27: Filter 27 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL27: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN26: Filter 26 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL26: Filter 26 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL26: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001361J-page 520
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 30-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6 (CONTINUED)
bit 15
FLTEN25: Filter 25 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL25: Filter 25 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL25: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN24: Filter 24 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL24: Filter 24 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL24: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2015-2021 Microchip Technology Inc.
DS60001361J-page 521
PIC32MZ Graphics (DA) Family
REGISTER 30-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTEN31
R/W-0
FLTEN30
R/W-0
FLTEN29
R/W-0
FLTEN28
MSEL31
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FSEL30
R/W-0
MSEL29
R/W-0
Bit
25/17/9/1
FSEL31
MSEL30
R/W-0
Bit
26/18/10/2
R/W-0
FSEL29
R/W-0
MSEL28
R/W-0
FSEL28
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
x = Bit is unknown
FLTEN31: Filter 31 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL31: Filter 31 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL31: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23
FLTEN30: Filter 30Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL30: Filter 30Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL30: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
DS60001361J-page 522
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 30-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7 (CONTINUED)
bit 15
FLTEN29: Filter 29 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL29: Filter 29 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8
FSEL29: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7
FLTEN28: Filter 28 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5
MSEL28: Filter 28 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0
FSEL28: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note:
The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2015-2021 Microchip Technology Inc.
DS60001361J-page 523
PIC32MZ Graphics (DA) Family
REGISTER 30-18: CiRXFn: CAN ACCEPTANCE FILTER N REGISTER 7 (n = 0 THROUGH 31)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
U-0
R/W-x
R/W-x
SID
R/W-x
R/W-x
R/W-x
U-0
SID
R/W-0
—
EXID
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID
R/W-x
EID
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-21 SID: Standard Identifier bits
1 = Message address bit SIDx must be ‘1’ to match filter
0 = Message address bit SIDx must be ‘0’ to match filter
bit 20
Unimplemented: Read as ‘0’
bit 19
EXID: Extended Identifier Enable bits
1 = Match only messages with extended identifier addresses
0 = Match only messages with standard identifier addresses
bit 18
Unimplemented: Read as ‘0’
bit 17-0
EID: Extended Identifier bits
1 = Message address bit EIDx must be ‘1’ to match filter
0 = Message address bit EIDx must be ‘0’ to match filter
Note:
This register can only be modified when the filter is disabled (FLTENn = 0).
DS60001361J-page 524
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 30-19: CiFIFOBA: CAN MESSAGE BUFFER BASE ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0(1)
R-0(1)
CiFIFOBA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CiFIFOBA
R/W-0
CiFIFOBA
R/W-0
CiFIFOBA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0
CiFIFOBA: CAN FIFO Base Address bits
These bits define the base address of all message buffers. Individual message buffers are located based
on the size of the previous message buffers. This address is a physical address. Note that bits are
read-only and read ‘0’, forcing the messages to be 32-bit word-aligned in device RAM.
Note 1:
This bit is unimplemented and will always read ‘0’, which forces word-alignment of messages.
Note:
This register can only be modified when the CAN module is in Configuration mode (OPMOD
(CiCON) = 100).
2015-2021 Microchip Technology Inc.
DS60001361J-page 525
PIC32MZ Graphics (DA) Family
REGISTER 30-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER (n = 0 THROUGH 31)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
U-0
S/HC-0
S/HC-0
U-0
U-0
FSIZE(1)
R/W-0
DONLY
U-0
(1)
U-0
—
FRESET
UINC
—
—
—
—
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXEN
TXABAT(2)
TXLARB(3)
TXERR(3)
TXREQ
RTREN
TXPR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-21 Unimplemented: Read as ‘0’
bit 20-16 FSIZE: FIFO Size bits(1)
11111 = FIFO is 32 messages deep
•
•
•
00010 = FIFO is 3 messages deep
00001 = FIFO is 2 messages deep
00000 = FIFO is 1 message deep
bit 15
Unimplemented: Read as ‘0’
bit 14
FRESET: FIFO Reset bits
1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user should
poll if this bit is clear before taking any action
0 = No effect
bit 13
UINC: Increment Head/Tail bit
TXEN = 1: (FIFO configured as a Transmit FIFO)
When this bit is set the FIFO head will increment by a single message
TXEN = 0: (FIFO configured as a Receive FIFO)
When this bit is set the FIFO tail will increment by a single message
bit 12
DONLY: Store Message Data Only bit(1)
TXEN = 1: (FIFO configured as a Transmit FIFO)
This bit is not used and has no effect.
TXEN = 0: (FIFO configured as a Receive FIFO)
1 = Only data bytes will be stored in the FIFO
0 = Full message is stored, including identifier
bit 11-8
Unimplemented: Read as ‘0’
bit 7
TXEN: TX/RX Buffer Selection bit
1 = FIFO is a Transmit FIFO
0 = FIFO is a Receive FIFO
Note 1:
These bits can only be modified when the CAN module is in Configuration mode (OPMOD bits
(CiCON) = 100).
This bit is updated when a message completes (or aborts) or when the FIFO is reset.
This bit is reset on any read of this register or when the FIFO is reset.
2:
3:
DS60001361J-page 526
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 30-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER (n = 0 THROUGH 31)
bit 6
TXABAT: Message Aborted bit(2)
1 = Message was aborted
0 = Message completed successfully
bit 5
TXLARB: Message Lost Arbitration bit(3)
1 = Message lost arbitration while being sent
0 = Message did not loose arbitration while being sent
bit 4
TXERR: Error Detected During Transmission bit(3)
1 = A bus error occured while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 3
TXREQ: Message Send Request
TXEN = 1: (FIFO configured as a Transmit FIFO)
Setting this bit to ‘1’ requests sending a message.
The bit will automatically clear when all the messages queued in the FIFO are successfully sent
Clearing the bit to ‘0’ while set (‘1’) will request a message abort.
TXEN = 0: (FIFO configured as a Receive FIFO)
This bit has no effect.
bit 2
RTREN: Auto RTR Enable bit
1 = When a remote transmit is received, TXREQ will be set
0 = When a remote transmit is received, TXREQ will be unaffected
bit 1-0
TXPR: Message Transmit Priority bits
11 = Highest Message Priority
10 = High Intermediate Message Priority
01 = Low Intermediate Message Priority
00 = Lowest Message Priority
Note 1:
These bits can only be modified when the CAN module is in Configuration mode (OPMOD bits
(CiCON) = 100).
This bit is updated when a message completes (or aborts) or when the FIFO is reset.
This bit is reset on any read of this register or when the FIFO is reset.
2:
3:
2015-2021 Microchip Technology Inc.
DS60001361J-page 527
PIC32MZ Graphics (DA) Family
REGISTER 30-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER (n = 0 THROUGH 31)
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
31:24
23:16
15:8
7:0
U-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-0
R/W-0
R/W-0
TXEMPTYIE
—
—
—
—
—
TXNFULLIE
TXHALFIE
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
RXOVFLIE
RXFULLIE
RXHALFIE
RXNEMPTYIE
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
TXHALFIF
TXEMPTYIF(1)
R-0
R-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
TXNFULLIF
(1)
R-0
RXOVFLIF RXFULLIF(1) RXHALFIF(1) RXNEMPTYIF(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26
TXNFULLIE: Transmit FIFO Not Full Interrupt Enable bit
1 = Interrupt enabled for FIFO not full
0 = Interrupt disabled for FIFO not full
bit 25
TXHALFIE: Transmit FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 24
TXEMPTYIE: Transmit FIFO Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO empty
0 = Interrupt disabled for FIFO empty
bit 23-20 Unimplemented: Read as ‘0’
bit 19
RXOVFLIE: Overflow Interrupt Enable bit
1 = Interrupt enabled for overflow event
0 = Interrupt disabled for overflow event
bit 18
RXFULLIE: Full Interrupt Enable bit
1 = Interrupt enabled for FIFO full
0 = Interrupt disabled for FIFO full
bit 17
RXHALFIE: FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 16
RXNEMPTYIE: Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO not empty
0 = Interrupt disabled for FIFO not empty
bit 15-11 Unimplemented: Read as ‘0’
bit 10
TXNFULLIF: Transmit FIFO Not Full Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a Transmit Buffer)
1 = FIFO is not full
0 = FIFO is full
TXEN = 0: (FIFO configured as a Receive Buffer)
Unused, reads ‘0’
Note 1:
This bit is read-only and reflects the status of the FIFO.
DS60001361J-page 528
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 30-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER (n = 0 THROUGH 31)
bit 9
TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a Transmit Buffer)
1 = FIFO is half full
0 = FIFO is > half full
TXEN = 0: (FIFO configured as a Receive Buffer)
Unused, reads ‘0’
bit 8
TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a Transmit Buffer)
1 = FIFO is empty
0 = FIFO is not empty, at least 1 message queued to be transmitted
TXEN = 0: (FIFO configured as a Receive Buffer)
Unused, reads ‘0’
bit 7-4
Unimplemented: Read as ‘0’
bit 3
RXOVFLIF: Receive FIFO Overflow Interrupt Flag bit
TXEN = 1: (FIFO configured as a Transmit Buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a Receive Buffer)
1 = Overflow event has occurred
0 = No overflow event occured
bit 2
RXFULLIF: Receive FIFO Full Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a Transmit Buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a Receive Buffer)
1 = FIFO is full
0 = FIFO is not full
bit 1
RXHALFIF: Receive FIFO Half Full Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a Transmit Buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a Receive Buffer)
1 = FIFO is half full
0 = FIFO is < half full
bit 0
RXNEMPTYIF: Receive Buffer Not Empty Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a Transmit Buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a Receive Buffer)
1 = FIFO is not empty, has at least 1 message
0 = FIFO is empty
Note 1:
This bit is read-only and reflects the status of the FIFO.
2015-2021 Microchip Technology Inc.
DS60001361J-page 529
PIC32MZ Graphics (DA) Family
REGISTER 30-22: CiFIFOUAn: CAN FIFO USER ADDRESS REGISTER (n = 0 THROUGH 31)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R-x
R-x
R-x
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-0(1)
R-0(1)
CiFIFOUAn
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
CiFIFOUAn
R-x
R-x
CiFIFOUAn
R-x
R-x
R-x
R-x
R-x
CiFIFOUAn
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
Bit
28/20/12/4
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
CiFIFOUAn: CAN FIFO User Address bits
TXEN = 1: (FIFO configured as a Transmit Buffer)
A read of this register will return the address where the next message is to be written (FIFO head).
TXEN = 0: (FIFO configured as a Receive Buffer)
A read of this register will return the address where the next message is to be read (FIFO tail).
Note 1:
Note:
This bit will always read ‘0’, which forces byte-alignment of messages.
This register is not guaranteed to read correctly in Configuration mode, and should only be accessed when
the module is not in Configuration mode.
REGISTER 30-23: CiFIFOCIN: CAN MODULE MESSAGE INDEX REGISTER (n = 0 THROUGH 31)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R-0
R-0
R-0
R-0
R-0
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
CiFIFOCI
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-5 Unimplemented: Read as ‘0’
bit 4-0
CiFIFOCIn: CAN Side FIFO Message Index bits
TXEN = 1: (FIFO configured as a Transmit Buffer)
A read of this register will return an index to the message that the FIFO will next attempt to transmit.
TXEN = 0: (FIFO configured as a Receive Buffer)
A read of this register will return an index to the message that the FIFO will use to save the next message.
DS60001361J-page 530
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
31.0
ETHERNET CONTROLLER
Note:
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 35. “Ethernet
Controller” (DS60001155), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The Ethernet controller is a bus host module that interfaces with an off-chip Physical Layer (PHY) to implement a complete Ethernet node in a system.
Key features of the Ethernet Controller include:
•
•
•
•
Supports RMII and MII PHY interface
Supports MIIM PHY management interface
Supports both manual and automatic Flow Control
RAM descriptor-based DMA operation for both
receive and transmit path
Fully configurable interrupts
Configurable receive packet filtering
- CRC check
- 64-byte pattern match
- Broadcast, multicast and unicast packets
- Magic Packet™
- 64-bit hash table
- Runt packet
Supports packet payload checksum calculation
Supports various hardware statistics counters
Figure 31-1 illustrates a block diagram of the Ethernet
controller.
• Supports 10/100 Mbps data transfer rates
• Supports full-duplex and half-duplex operation
ETHERNET CONTROLLER BLOCK DIAGRAM
TX
FIFO
FIGURE 31-1:
•
•
•
•
TX DMA
TX BM
TX Bus
Host
TX Function
System Bus
TX Flow Control
RX DMA
RX
FIFO
MII/RMII
IF
RX Flow
Control
RX BM
External
PHY
MAC
RX Bus
Host
RX Filter
RX Function
Fast Peripheral Bus
Checksum
DMA
Control
Registers
Ethernet DMA
MIIM
IF
MAC Control
and
Configuration
Registers
Host IF
Ethernet Controller
2015-2021 Microchip Technology Inc.
PBCLK5
DS60001361J-page 531
PIC32MZ Graphics (DA) Family
Table 31-1 and Table 31-2 show two interfaces and the
associated pins that can be used with the Ethernet
Controller.
TABLE 31-1:
MII MODE DEFAULT
INTERFACE SIGNALS
(FMIIEN = 1, FETHIO = 1)
Pin Name
Description
EMDC
Management Clock
EMDIO
Management I/O
ETXCLK
Transmit Clock
ETXEN
Transmit Enable
ETXD0
Transmit Data
ETXD1
Transmit Data
ETXD2
Transmit Data
ETXD3
Transmit Data
ETXERR
Transmit Error
ERXCLK
Receive Clock
ERXDV
Receive Data Valid
ERXD0
Receive Data
ERXD1
Receive Data
ERXD2
Receive Data
ERXD3
Receive Data
ERXERR
Receive Error
ECRS
Carrier Sense
ECOL
Collision Indication
TABLE 31-2:
RMII MODE DEFAULT
INTERFACE SIGNALS
(FMIIEN = 0, FETHIO = 1)
Pin Name
Description
EMDC
Management Clock
EMDIO
Management I/O
ETXEN
Transmit Enable
ETXD0
Transmit Data
ETXD1
Transmit Data
EREFCLK
Reference Clock
ECRSDV
Carrier Sense – Receive Data Valid
ERXD0
Receive Data
ERXD1
Receive Data
ERXERR
Receive Error
Note:
Ethernet controller pins that are not used
by selected interface can be used by
other peripherals.
DS60001361J-page 532
2015-2021 Microchip Technology Inc.
Ethernet Control Registers
Register
Name(1)
TABLE 31-3:
Virtual Address
(BF88_#)
2000
ETHCON1
2010
ETHCON2
2020
2030
2050
2060
2070
2080
2090
ETHTXST
ETHRXST
ETHHT0
ETHHT1
ETHPMM0
ETHPMM1
ETHPMCS
ETHPMO
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
15:0
ON
—
SIDL
—
—
—
TXRTS
RXEN
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
31:16
20A0
ETHRXFC
20/4
19/3
18/2
17/1
16/0
AUTOFC
—
—
MANFC
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
0000
—
—
—
—
0000
BUFCDEC 0000
TXSTADDR
0000
TXSTADDR
31:16
RXSTADDR
15:0
31:16
0000
0000
HT
15:0
31:16
0000
0000
PMM
15:0
31:16
0000
0000
PMM
15:0
—
—
—
—
—
—
—
15:0
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CRC
ERREN
CRC
OKEN
RUNT
ERREN
UCEN
NOT
MEEN
MCEN
BCEN
0000
PMCS
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
0000
0000
15:0
HTEN
MPEN
—
NOTPM
31:16
—
—
—
—
—
—
—
—
RXFWM
15:0
—
—
—
—
—
—
—
—
RXEWM
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
TX
BUSEIE
RX
BUSEIE
—
—
—
EW
MARKIE
FW
MARKIE
RX
DONEIE
PK
TPENDIE
RX
ACTIE
—
TX
DONEIE
TX
ABORTIE
RX
BUFNAIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
TXBUSE
RXBUSE
—
—
—
EWMARK
FWMARK
RXDONE
PKTPEND
RXACT
—
TXDONE
TXABORT
RXBUFNA
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
BUSY
TXBUSY
RXBUSY
—
—
—
—
—
0000
31:16
ETH
2100
RXOVFLOW 15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
20B0 ETHRXWM
DS60001361J-page 533
20C0
ETHIEN
20D0
ETHIRQ
20E0
ETHSTAT
Legend:
Note
1:
2:
PMMODE
0000
0000
PMO
—
0000
0000
HT
15:0
0000
0000
RXSTADDR
31:16
31:16
21/5
RXBUFSZ
15:0
31:16
22/6
PTV
31:16
31:16
23/7
All Resets
Bits
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RUNTEN
0000
0000
—
—
0000
RXOVFLW 0000
BUFCNT
RXOVFLWCNT
0000
RX
0000
OVFLWIE
0000
0000
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and
INV Registers” for more information.
Reset values default to the factory programmed value.
PIC32MZ Graphics (DA) Family
2040
ETHERNET CONTROLLER REGISTER SUMMARY
Bit Range
2015-2021 Microchip Technology Inc.
31.1
Virtual Address
(BF88_#)
ETHERNET CONTROLLER REGISTER SUMMARY (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
2110
31:16
ETH
FRMTXOK 15:0
—
2120
31:16
ETH
SCOLFRM 15:0
—
2130
31:16
ETH
MCOLFRM 15:0
—
2140
31:16
ETH
FRMRXOK 15:0
—
31:16
—
2150
2160
ETH
FCSERR
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RXPAUSE
PASSALL
—
—
FRMTXOKCNT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
SOFT
RESET
SIM
RESET
—
—
RESET
RMCS
RESET
RFUN
RESET
TMCS
RESET
TFUN
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
BP
NOBKOFF
CRC
ENABLE
—
ALGNERRCNT
EMAC1
CFG1
2210
EMAC1
CFG2
15:0
—
EXCESS
DFR
NOBKOFF
—
—
LONGPRE
PUREPRE
AUTOPAD
VLANPAD
PAD
ENABLE
2220
EMAC1
IPGT
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
2230
EMAC1
IPGR
31:16
—
—
—
—
—
—
—
—
—
15:0
—
2240
EMAC1
CLRT
31:16
—
—
15:0
—
—
2250
EMAC1
MAXF
31:16
—
—
2015-2021 Microchip Technology Inc.
2260
EMAC1
SUPP
2270
EMAC1
TEST
2280
EMAC1
MCFG
2290
22A0
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
0000
DELAYCRC HUGEFRM LENGTHCK FULLDPLX 4082
—
—
—
—
—
—
—
—
—
—
—
NB2BIPKTGP2
—
0000
0012
0000
0C12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RETX
0000
370F
MACMAXF
—
0000
RXENABLE 800D
B2BIPKTGP
—
CWINDOW
—
LOOPBACK TXPAUSE
0000
05EE
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
RESET
RMII
—
—
SPEED
RMII
—
—
—
—
—
—
—
—
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
TESTBP
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
RESET
MGMT
—
—
—
—
—
—
—
—
—
EMAC1
MCMD
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCAN
READ
0000
EMAC1
MADR
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
Legend:
Note
—
0000
0000
2200
—
0000
0000
31:16
ETH
ALGNERR 15:0
NB2BIPKTGP1
0000
0000
FCSERRCNT
—
0000
0000
FRMRXOKCNT
—
0000
0000
MCOLFRMCNT
—
0000
0000
SCOLFRMCNT
—
All Resets
Bit Range
Register
Name(1)
Bits
1:
2:
PHYADDR
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TESTPAUSE SHRTQNTA 0000
CLKSEL
—
NOPRE
REGADDR
—
0000
SCANINC 0020
0100
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and
INV Registers” for more information.
Reset values default to the factory programmed value.
PIC32MZ Graphics (DA) Family
DS60001361J-page 534
TABLE 31-3:
Register
Name(1)
Bit Range
ETHERNET CONTROLLER REGISTER SUMMARY (CONTINUED)
Virtual Address
(BF88_#)
22B0
EMAC1
MWTD
31:16
22C0
EMAC1
MRDD
31:16
22D0
EMAC1
MIND
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
LINKFAIL
NOTVALID
SCAN
2300
EMAC1
SA0(2)
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2310
EMAC1
SA1(2)
31:16
—
—
—
2320
EMAC1
SA2(2)
31:16
—
—
—
Bits
Note
1:
2:
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
MWTD
—
—
—
—
—
—
—
15:0
—
0000
MRDD
15:0
—
—
—
—
—
—
—
—
—
—
STNADDR4
—
—
—
—
—
—
—
—
STNADDR2
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
—
—
—
STNADDR1
xxxx
xxxx
STNADDR3
—
0000
MIIMBUSY 0000
STNADDR5
—
0000
0000
STNADDR6
15:0
15:0
—
0000
xxxx
xxxx
xxxx
xxxx
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and
INV Registers” for more information.
Reset values default to the factory programmed value.
DS60001361J-page 535
PIC32MZ Graphics (DA) Family
Legend:
31/15
All Resets
2015-2021 Microchip Technology Inc.
TABLE 31-3:
PIC32MZ Graphics (DA) Family
REGISTER 31-1:
Bit Range
31:24
23:16
15:8
7:0
ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1
Bit
31/23/15/7
Bit
Bit
30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
ON
—
SIDL
—
—
—
TXRTS
RXEN(1)
R/W-0
U-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
AUTOFC
—
—
MANFC
—
—
—
BUFCDEC
PTV
R/W-0
PTV
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-16
x = Bit is unknown
PTV: PAUSE Timer Value bits
PAUSE Timer Value used for Flow Control.
This register should only be written when RXEN (ETHCON1) is not set.
These bits are only used for Flow Control operations.
bit 15
ON: Ethernet ON bit
1 = Ethernet module is enabled
0 = Ethernet module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Ethernet Stop in Idle Mode bit
1 = Ethernet module transfers are paused during Idle mode
0 = Ethernet module transfers continue during Idle mode
bit 12-10
Unimplemented: Read as ‘0’
bit 9
TXRTS: Transmit Request to Send bit
1 = Activate the TX logic and send the packet(s) defined in the TX EDT
0 = Stop transmit (when cleared by software) or transmit done (when cleared by hardware)
After the bit is written with a ‘1’, it will clear to a ‘0’ whenever the transmit logic has finished transmitting
the requested packets in the Ethernet Descriptor Table (EDT). If a ‘0’ is written by the CPU, the transmit
logic finishes the current packet’s transmission and then stops any further.
This bit only affects TX operations.
bit 8
RXEN: Receive Enable bit(1)
1 = Enable RX logic, packets are received and stored in the RX buffer as controlled by the filter
configuration
0 = Disable RX logic, no packets are received in the RX buffer
This bit only affects RX operations.
Note 1:
It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The
Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.
DS60001361J-page 536
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-1:
bit 7
ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1 (CONTINUED)
AUTOFC: Automatic Flow Control bit
1 = Automatic Flow Control is enabled
0 = Automatic Flow Control is disabled
Setting this bit will enable automatic Flow Control. If set, the full and empty watermarks are used to
automatically enable and disable the Flow Control, respectively. When the number of received buffers
BUFCNT (ETHSTAT) rises to the full watermark, Flow Control is automatically enabled. When
the BUFCNT falls to the empty watermark, Flow Control is automatically disabled.
This bit is only used for Flow Control operations and affects both TX and RX operations.
bit 6-5
Unimplemented: Read as ‘0’
bit 4
MANFC: Manual Flow Control bit
1 = Manual Flow Control is enabled
0 = Manual Flow Control is disabled
Setting this bit will enable manual Flow Control. If set, the Flow Control logic will send a PAUSE frame
using the PAUSE timer value in the PTV register. It will then resend a PAUSE frame every 128 *
PTV/2 TX clock cycles until the bit is cleared.
Note:
For 10 Mbps operation, TX clock runs at 2.5 MHz. For 100 Mbps operation, TX clock runs at
25 MHz.
When this bit is cleared, the Flow Control logic will automatically send a PAUSE frame with a 0x0000
PAUSE timer value to disable Flow Control.
This bit is only used for Flow Control operations and affects both TX and RX operations.
bit 3-1
Unimplemented: Read as ‘0’
bit 0
BUFCDEC: Descriptor Buffer Count Decrement bit
The BUFCDEC bit is a write-1 bit that reads as ‘0’. When written with a ‘1’, the Descriptor Buffer Counter,
BUFCNT, will decrement by one. If BUFCNT is incremented by the RX logic at the same time that this bit
is written, the BUFCNT value will remain unchanged. Writing a ‘0’ will have no effect.
This bit is only used for RX operations.
Note 1:
It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The
Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.
2015-2021 Microchip Technology Inc.
DS60001361J-page 537
PIC32MZ Graphics (DA) Family
REGISTER 31-2:
Bit Range
Bit
31/23/15/7
31:24
23:16
15:8
7:0
ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
—
RXBUFSZ
RXBUFSZ
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-11
Unimplemented: Read as ‘0’
bit 10-4
RXBUFSZ: RX Data Buffer Size for All RX Descriptors (in 16-byte increments) bits
1111111 = RX data Buffer size for descriptors is 2032 bytes
•
•
•
1100000 = RX data Buffer size for descriptors is 1536 bytes
•
•
•
0000011 = RX data Buffer size for descriptors is 48 bytes
0000010 = RX data Buffer size for descriptors is 32 bytes
0000001 = RX data Buffer size for descriptors is 16 bytes
0000000 = Reserved
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
2:
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0.
DS60001361J-page 538
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-3:
Bit
Range
31:24
23:16
15:8
7:0
ETHTXST: ETHERNET CONTROLLER TX PACKET DESCRIPTOR START
ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
—
—
TXSTADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXSTADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXSTADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXSTADDR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-2 TXSTADDR: Starting Address of First Transmit Descriptor bits
This register should not be written while any transmit, receive or DMA operations are in progress.
This address must be 4-byte aligned (bits 1-0 must be ‘00’).
bit 1-0 Unimplemented: Read as ‘0’
Note 1:
2:
This register is only used for TX operations.
This register will be updated by hardware with the last descriptor used by the last successfully transmitted
packet.
REGISTER 31-4:
Bit
Range
31:24
23:16
15:8
7:0
ETHRXST: ETHERNET CONTROLLER RX PACKET DESCRIPTOR START
ADDRESS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
—
—
RXSTADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXSTADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXSTADDR
R/W-0
R/W-0
R/W-0
R/W-0
RXSTADDR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-2 RXSTADDR: Starting Address of First Receive Descriptor bits
This register should not be written while any transmit, receive or DMA operations are in progress.
This address must be 4-byte aligned (bits 1-0 must be ‘00’).
bit 1-0 Unimplemented: Read as ‘0’
Note 1:
2:
This register is only used for RX operations.
This register will be updated by hardware with the last descriptor used by the last successfully transmitted
packet.
2015-2021 Microchip Technology Inc.
DS60001361J-page 539
PIC32MZ Graphics (DA) Family
REGISTER 31-5:
Bit
Range
ETHHT0: ETHERNET CONTROLLER HASH TABLE 0 REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
HT
23:16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HT
15:8
R/W-0
HT
7:0
R/W-0
HT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note 1:
2:
HT: Hash Table Bytes 0-3 bits
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0 or the HTEN bit
(ETHRXFC) = 0.
REGISTER 31-6:
Bit Range
31:24
23:16
15:8
7:0
x = Bit is unknown
ETHHT1: ETHERNET CONTROLLER HASH TABLE 1 REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HT
R/W-0
HT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
Note 1:
2:
x = Bit is unknown
HT: Hash Table Bytes 4-7 bits
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0 or the HTEN bit
(ETHRXFC) = 0.
DS60001361J-page 540
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-7:
Bit Range
31:24
ETHPMM0: ETHERNET CONTROLLER PATTERN MATCH MASK 0 REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMM
R/W-0
23:16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 31-24
bit 23-16
bit 15-8
bit 7-0
Note 1:
2:
R/W-0
R/W-0
W = Writable bit
‘1’ = Bit is set
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
ETHPMM1: ETHERNET CONTROLLER PATTERN MATCH MASK 1 REGISTER
Bit
24/16/8/0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMM
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMM
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMM
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMM
Legend:
R = Readable bit
-n = Value at POR
bit 31-24
bit 23-16
bit 15-8
bit 7-0
R/W-0
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0 or the PMMODE bit
(ETHRXFC) = 0.
Bit Range
7:0
R/W-0
PMM: Pattern Match Mask 3 bits
PMM: Pattern Match Mask 2 bits
PMM: Pattern Match Mask 1 bits
PMM: Pattern Match Mask 0 bits
REGISTER 31-8:
15:8
R/W-0
PMM
Legend:
R = Readable bit
-n = Value at POR
23:16
R/W-0
PMM
7:0
31:24
R/W-0
PMM
15:8
Note 1:
2:
R/W-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
PMM: Pattern Match Mask 7 bits
PMM: Pattern Match Mask 6 bits
PMM: Pattern Match Mask 5 bits
PMM: Pattern Match Mask 4 bits
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0 or the PMMODE bit
(ETHRXFC) = 0.
2015-2021 Microchip Technology Inc.
DS60001361J-page 541
PIC32MZ Graphics (DA) Family
REGISTER 31-9:
Bit Range
31:24
23:16
15:8
7:0
ETHPMCS: ETHERNET CONTROLLER PATTERN MATCH CHECKSUM
REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
Note 1:
2:
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMCS
R/W-0
PMCS
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-8
bit 7-0
Bit
24/16/8/0
Bit
31/23/15/7
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
PMCS: Pattern Match Checksum 1 bits
PMCS: Pattern Match Checksum 0 bits
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0 or the PMMODE bit
(ETHRXFC) = 0.
REGISTER 31-10: ETHPMO: ETHERNET CONTROLLER PATTERN MATCH OFFSET REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMO
R/W-0
Note 1:
2:
R/W-0
R/W-0
R/W-0
PMO
Legend:
R = Readable bit
-n = Value at POR
bit 31-16
bit 15-0
R/W-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
PMO: Pattern Match Offset 1 bits
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0 or the PMMODE bit
(ETHRXFC) = 0.
DS60001361J-page 542
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
Bit
25/17/9/1 24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HTEN
MPEN
—
NOTPM
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CRCERREN
CRCOKEN
RUNTERREN
RUNTEN
UCEN
NOTMEEN
MCEN
BCEN
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
PMMODE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
HTEN: Enable Hash Table Filtering bit
1 = Enable Hash Table Filtering
0 = Disable Hash Table Filtering
bit 14
MPEN: Magic Packet™ Enable bit
1 = Enable Magic Packet Filtering
0 = Disable Magic Packet Filtering
bit 13
Unimplemented: Read as ‘0’
bit 12
NOTPM: Pattern Match Inversion bit
1 = The Pattern Match Checksum must not match for a successful Pattern Match to occur
0 = The Pattern Match Checksum must match for a successful Pattern Match to occur
This bit determines whether Pattern Match Checksum must match in order for a successful Pattern Match
to occur.
bit 11-8 PMMODE: Pattern Match Mode bits
1001 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Packet = Magic Packet)(1,3)
1000 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Hash Table Filter match)(1,1)
0111 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Broadcast Address)(1)
0110 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Broadcast Address)(1)
0101 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Unicast Address)(1)
0100 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Unicast Address)(1)
0011 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Station Address)(1)
0010 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Station Address)(1)
0001 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches)(1)
0000 = Pattern Match is disabled; pattern match is always unsuccessful
Note 1:
2:
3:
XOR = True when either one or the other conditions are true, but not both.
This Hash Table Filter match is active regardless of the value of the HTEN bit.
This Magic Packet Filter match is active regardless of the value of the MPEN bit.
Note 1:
2:
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0.
2015-2021 Microchip Technology Inc.
DS60001361J-page 543
PIC32MZ Graphics (DA) Family
REGISTER 31-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION
REGISTER (CONTINUED)
bit 7
bit 6
bit 5
bit 4
CRCERREN: CRC Error Collection Enable bit
1 = The received packet CRC must be invalid for the packet to be accepted
0 = Disable CRC Error Collection filtering
This bit allows the user to collect all packets that have an invalid CRC.
CRCOKEN: CRC OK Enable bit
1 = The received packet CRC must be valid for the packet to be accepted
0 = Disable CRC filtering
This bit allows the user to reject all packets that have an invalid CRC.
RUNTERREN: Runt Error Collection Enable bit
1 = The received packet must be a runt packet for the packet to be accepted
0 = Disable Runt Error Collection filtering
This bit allows the user to collect all packets that are runt packets. For this filter, a runt packet is defined as
any packet with a size of less than 64 bytes (when CRCOKEN = 0) or any packet with a size of less than
64 bytes that has a valid CRC (when CRCOKEN = 1).
RUNTEN: Runt Enable bit
1 = The received packet must not be a runt packet for the packet to be accepted
0 = Disable Runt filtering
bit 3
This bit allows the user to reject all runt packets. For this filter, a runt packet is defined as any packet with a
size of less than 64 bytes.
UCEN: Unicast Enable bit
1 = Enable Unicast Filtering
0 = Disable Unicast Filtering
bit 2
This bit allows the user to accept all unicast packets whose Destination Address matches the Station
Address.
NOTMEEN: Not Me Unicast Enable bit
1 = Enable Not Me Unicast Filtering
0 = Disable Not Me Unicast Filtering
bit 1
This bit allows the user to accept all unicast packets whose Destination Address does not match the Station
Address.
MCEN: Multicast Enable bit
1 = Enable Multicast Filtering
0 = Disable Multicast Filtering
bit 0
This bit allows the user to accept all Multicast Address packets.
BCEN: Broadcast Enable bit
1 = Enable Broadcast Filtering
0 = Disable Broadcast Filtering
This bit allows the user to accept all Broadcast Address packets.
Note 1:
2:
3:
XOR = True when either one or the other conditions are true, but not both.
This Hash Table Filter match is active regardless of the value of the HTEN bit.
This Magic Packet Filter match is active regardless of the value of the MPEN bit.
Note 1:
2:
This register is only used for RX operations.
The bits in this register may only be changed while the RXEN bit (ETHCON1) = 0.
DS60001361J-page 544
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-12: ETHRXWM: ETHERNET CONTROLLER RECEIVE WATERMARKS REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
RXFWM
15:8
7:0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXEWM
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-24
Unimplemented: Read as ‘0’
bit 23-16
RXFWM: Receive Full Watermark bits
x = Bit is unknown
The software controlled RX Buffer Full Watermark Pointer is compared against the RX BUFCNT to
determine the full watermark condition for the FWMARK interrupt and for enabling Flow Control when
automatic Flow Control is enabled. The Full Watermark Pointer should always be greater than the Empty
Watermark Pointer.
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
RXEWM: Receive Empty Watermark bits
The software controlled RX Buffer Empty Watermark Pointer is compared against the RX BUFCNT to
determine the empty watermark condition for the EWMARK interrupt and for disabling Flow Control when
automatic Flow Control is enabled. The Empty Watermark Pointer should always be less than the Full
Watermark Pointer.
Note:
This register is only used for RX operations.
2015-2021 Microchip Technology Inc.
DS60001361J-page 545
PIC32MZ Graphics (DA) Family
REGISTER 31-13: ETHIEN: ETHERNET CONTROLLER INTERRUPT ENABLE REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
—
R/W-0
TXBUSEIE(1) RXBUSEIE(2)
R/W-0
R/W-0
RXDONEIE(2) PKTPENDIE(2) RXACTIE(2)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U-0
—
EWMARKIE(2) FWMARKIE(2)
R/W-0
R/W-0
TXDONEIE(1) TXABORTIE(1) RXBUFNAIE(2) RXOVFLWIE(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14
TXBUSEIE: Transmit BVCI Bus Error Interrupt Enable bit(1)
1 = Enable TXBUS Error Interrupt
0 = Disable TXBUS Error Interrupt
bit 13
RXBUSEIE: Receive BVCI Bus Error Interrupt Enable bit(2)
1 = Enable RXBUS Error Interrupt
0 = Disable RXBUS Error Interrupt
bit 12-10 Unimplemented: Read as ‘0’
bit 9
EWMARKIE: Empty Watermark Interrupt Enable bit(2)
1 = Enable EWMARK Interrupt
0 = Disable EWMARK Interrupt
bit 8
FWMARKIE: Full Watermark Interrupt Enable bit(2)
1 = Enable FWMARK Interrupt
0 = Disable FWMARK Interrupt
bit 7
RXDONEIE: Receiver Done Interrupt Enable bit(2)
1 = Enable RXDONE Interrupt
0 = Disable RXDONE Interrupt
bit 6
PKTPENDIE: Packet Pending Interrupt Enable bit(2)
1 = Enable PKTPEND Interrupt
0 = Disable PKTPEND Interrupt
bit 5
RXACTIE: RX Activity Interrupt Enable bit(2)
1 = Enable RXACT Interrupt
0 = Disable RXACT Interrupt
bit 4
Unimplemented: Read as ‘0’
bit 3
TXDONEIE: Transmitter Done Interrupt Enable bit(1)
1 = Enable TXDONE Interrupt
0 = Disable TXDONE Interrupt
bit 2
TXABORTIE: Transmitter Abort Interrupt Enable bit(1)
1 = Enable TXABORT Interrupt
0 = Disable TXABORT Interrupt
bit 1
RXBUFNAIE: Receive Buffer Not Available Interrupt Enable bit(2)
1 = Enable RXBUFNA Interrupt
0 = Disable RXBUFNA Interrupt
bit 0
RXOVFLWIE: Receive FIFO Overflow Interrupt Enable bit(2)
1 = Enable RXOVFLW Interrupt
0 = Disable RXOVFLW Interrupt
Note 1:
2:
This bit is only used for TX operations.
This bit is only used for RX operations.
DS60001361J-page 546
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
—
TXBUSE
RXBUSE
—
—
—
EWMARK
FWMARK
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
RXDONE
PKTPEND
RXACT
—
TXDONE
TXABORT
RXBUFNA RXOVFLW
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-15
Unimplemented: Read as ‘0’
bit 14
TXBUSE: Transmit BVCI Bus Error Interrupt bit(2)
1 = BVCI Bus Error has occurred
0 = BVCI Bus Error has not occurred
x = Bit is unknown
This bit is set when the TX DMA encounters a BVCI Bus error during a memory access. It is cleared by
either a Reset or CPU write of a ‘1’ to the CLR register.
bit 13
RXBUSE: Receive BVCI Bus Error Interrupt bit(2)
1 = BVCI Bus Error has occurred
0 = BVCI Bus Error has not occurred
This bit is set when the RX DMA encounters a BVCI Bus error during a memory access. It is cleared by
either a Reset or CPU write of a ‘1’ to the CLR register.
bit 12-10
Unimplemented: Read as ‘0’
bit 9
EWMARK: Empty Watermark Interrupt bit(2)
1 = Empty Watermark pointer reached
0 = No interrupt pending
This bit is set when the RX Descriptor Buffer Count is less than or equal to the value in the
RXEWM bit (ETHRXWM) value. It is cleared by BUFCNT bit (ETHSTAT)
being incremented by hardware. Writing a ‘0’ or a ‘1’ has no effect.
bit 8
FWMARK: Full Watermark Interrupt bit(2)
1 = Full Watermark pointer reached
0 = No interrupt pending
This bit is set when the RX Descriptor Buffer Count is greater than or equal to the value in the RXFWM
bit (ETHRXWM) field. It is cleared by writing the BUFCDEC (ETHCON1) bit to decrement
the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.
Note 1:
2:
Note:
This bit is only used for TX operations.
This bit is are only used for RX operations.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
2015-2021 Microchip Technology Inc.
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PIC32MZ Graphics (DA) Family
REGISTER 31-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER
bit 7
RXDONE: Receive Done Interrupt bit(2)
1 = RX packet was successfully received
0 = No interrupt pending
This bit is set whenever an RX packet is successfully received. It is cleared by either a Reset or CPU
write of a ‘1’ to the CLR register.
bit 6
PKTPEND: Packet Pending Interrupt bit(2)
1 = RX packet pending in memory
0 = RX packet is not pending in memory
This bit is set when the BUFCNT counter has a value other than ‘0’. It is cleared by either a Reset or by
writing the BUFCDEC bit to decrement the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.
bit 5
RXACT: Receive Activity Interrupt bit(2)
1 = RX packet data was successfully received
0 = No interrupt pending
This bit is set whenever RX packet data is stored in the RXBM FIFO. It is cleared by either a Reset or
CPU write of a ‘1’ to the CLR register.
bit 4
Unimplemented: Read as ‘0’
bit 3
TXDONE: Transmit Done Interrupt bit(2)
1 = TX packet was successfully sent
0 = No interrupt pending
This bit is set when the currently transmitted TX packet completes transmission, and the Transmit Status
Vector is loaded into the first descriptor used for the packet. It is cleared by either a Reset or CPU write
of a ‘1’ to the CLR register.
bit 2
TXABORT: Transmit Abort Condition Interrupt bit(2)
1 = TX abort condition occurred on the last TX packet
0 = No interrupt pending
This bit is set when the MAC aborts the transmission of a TX packet for one of the following reasons:
•
•
•
•
•
Jumbo TX packet abort
Underrun abort
Excessive defer abort
Late collision abort
Excessive collisions abort
This bit is cleared by either a Reset or CPU write of a ‘1’ to the CLR register.
bit 1
RXBUFNA: Receive Buffer Not Available Interrupt bit(2)
1 = RX Buffer Descriptor Not Available condition has occurred
0 = No interrupt pending
This bit is set by a RX Buffer Descriptor Overrun condition. It is cleared by either a Reset or a CPU write
of a ‘1’ to the CLR register.
bit 0
RXOVFLW: Receive FIFO Over Flow Error bit(2)
1 = RX FIFO Overflow Error condition has occurred
0 = No interrupt pending
RXOVFLW is set by the RXBM Logic for an RX FIFO Overflow condition. It is cleared by either a Reset
or CPU write of a ‘1’ to the CLR register.
Note 1:
2:
Note:
This bit is only used for TX operations.
This bit is are only used for RX operations.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
DS60001361J-page 548
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
BUFCNT(1)
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
ETHBUSY(5) TXBUSY(2,6) RXBUSY(3,6)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 BUFCNT: Packet Buffer Count bits(1)
Number of packet buffers received in memory. Once a packet has been successfully received, this register
is incremented by hardware based on the number of descriptors used by the packet. Software decrements
the counter (by writing to the BUFCDEC bit (ETHCON1) for each descriptor used) after a packet has
been read out of the buffer. The register does not roll over (0xFF to 0x00) when hardware tries to increment
the register and the register is already at 0xFF. Conversely, the register does not roll under (0x00 to 0xFF)
when software tries to decrement the register and the register is already at 0x0000. When software attempts
to decrement the counter at the same time that the hardware attempts to increment the counter, the counter
value will remain unchanged.
When this register value reaches 0xFF, the RX logic will halt (only if automatic Flow Control is enabled)
awaiting software to write the BUFCDEC bit in order to decrement the register below 0xFF.
If automatic Flow Control is disabled, the RXDMA will continue processing and the BUFCNT will saturate at
a value of 0xFF.
When this register is non-zero, the PKTPEND status bit will be set and an interrupt may be generated,
depending on the value of the ETHIEN bit register.
When the ETHRXST register is written, the BUFCNT counter is automatically cleared to 0x00.
Note:
BUFCNT will not be cleared when ON is set to ‘0’. This enables software to continue to utilize
and decrement this count.
bit 15-8
Unimplemented: Read as ‘0’
bit 7
ETHBUSY: Ethernet Module busy bit(4,5)
1 = Ethernet logic has been turned on (ON (ETHCON1) = 1) or is completing a transaction
0 = Ethernet logic is idle
This bit indicates that the module has been turned on or is completing a transaction after being turned off.
Note 1:
2:
3:
4:
5:
6:
This bit is only used for RX operations.
This bit is only affected by TX operations.
This bit is only affected by RX operations.
This bit is affected by TX and RX operations.
This bit will be set when the ON bit (ETHCON1) = 1.
This bit will be cleared when the ON bit (ETHCON1) = 0.
2015-2021 Microchip Technology Inc.
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PIC32MZ Graphics (DA) Family
REGISTER 31-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER (CONTINUED)
bit 6
TXBUSY: Transmit Busy bit(2,6)
1 = TX logic is receiving data
0 = TX logic is idle
This bit indicates that a packet is currently being transmitted. A change in this status bit is not necessarily
reflected by the TXDONE interrupt, as TX packets may be aborted or rejected by the MAC.
bit 5
RXBUSY: Receive Busy bit(3,6)
1 = RX logic is receiving data
0 = RX logic is idle
This bit indicates that a packet is currently being received. A change in this status bit is not necessarily
reflected by the RXDONE interrupt, as RX packets may be aborted or rejected by the RX filter.
bit 4-0
Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
5:
6:
This bit is only used for RX operations.
This bit is only affected by TX operations.
This bit is only affected by RX operations.
This bit is affected by TX and RX operations.
This bit will be set when the ON bit (ETHCON1) = 1.
This bit will be cleared when the ON bit (ETHCON1) = 0.
DS60001361J-page 550
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-16: ETHRXOVFLOW: ETHERNET CONTROLLER RECEIVE OVERFLOW STATISTICS
REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXOVFLWCNT
R/W-0
R/W-0
RXOVFLWCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15-0
RXOVFLWCNT: Dropped Receive Frames Count bits
Increment counter for frames accepted by the RX filter and subsequently dropped due to internal receive
error (RXFIFO overrun). This event also sets the RXOVFLW bit (ETHIRQ) interrupt flag.
Note 1:
2:
3:
This register is only used for RX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for
bytes 0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
2015-2021 Microchip Technology Inc.
DS60001361J-page 551
PIC32MZ Graphics (DA) Family
REGISTER 31-17: ETHFRMTXOK: ETHERNET CONTROLLER FRAMES TRANSMITTED OK
STATISTICS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMTXOKCNT
R/W-0
R/W-0
FRMTXOKCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15-0
FRMTXOKCNT: Frame Transmitted OK Count bits
Increment counter for frames successfully transmitted.
Note 1:
2:
This register is only used for TX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
3:
DS60001361J-page 552
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-18: ETHSCOLFRM: ETHERNET CONTROLLER SINGLE COLLISION FRAMES
STATISTICS REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SCOLFRMCNT
R/W-0
R/W-0
SCOLFRMCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15-0
SCOLFRMCNT: Single Collision Frame Count bits
Increment count for frames that were successfully transmitted on the second try.
Note 1:
2:
3:
This register is only used for TX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for
bytes 0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
2015-2021 Microchip Technology Inc.
DS60001361J-page 553
PIC32MZ Graphics (DA) Family
REGISTER 31-19: ETHMCOLFRM: ETHERNET CONTROLLER MULTIPLE COLLISION FRAMES
STATISTICS REGISTER
Bit
Range
31:24
23:16
15:8
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MCOLFRMCNT
R/W-0
7:0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
MCOLFRMCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
MCOLFRMCNT: Multiple Collision Frame Count bits
Increment count for frames that were successfully transmitted after there was more than one collision.
Note 1:
2:
This register is only used for TX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
3:
DS60001361J-page 554
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-20: ETHFRMRXOK: ETHERNET CONTROLLER FRAMES RECEIVED OK
STATISTICS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMRXOKCNT
R/W-0
R/W-0
FRMRXOKCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented: Read as ‘0’
bit 15-0
FRMRXOKCNT: Frames Received OK Count bits
Increment count for frames received successfully by the RX Filter. This count will not be incremented if
there is a Frame Check Sequence (FCS) or Alignment error.
Note 1:
2:
This register is only used for RX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for
bytes 0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
3:
2015-2021 Microchip Technology Inc.
DS60001361J-page 555
PIC32MZ Graphics (DA) Family
REGISTER 31-21: ETHFCSERR: ETHERNET CONTROLLER FRAME CHECK SEQUENCE ERROR
STATISTICS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FCSERRCNT
R/W-0
R/W-0
FCSERRCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
FCSERRCNT: FCS Error Count bits
Increment count for frames received with FCS error and the frame length in bits is an integral multiple of
8 bits.
Note 1:
2:
This register is only used for RX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should be only done for debug/test purposes.
3:
DS60001361J-page 556
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-22: ETHALGNERR: ETHERNET CONTROLLER ALIGNMENT ERRORS STATISTICS
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALGNERRCNT
R/W-0
R/W-0
ALGNERRCNT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
ALGNERRCNT: Alignment Error Count bits
Increment count for frames with alignment errors. Note that an alignment error is a frame that has an FCS
error and the frame length in bits is not an integral multiple of 8 bits (a.k.a., dribble nibble)
Note 1:
2:
This register is only used for RX operations.
This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are ‘0’.
It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should be only done for debug/test purposes.
3:
2015-2021 Microchip Technology Inc.
DS60001361J-page 557
PIC32MZ Graphics (DA) Family
REGISTER 31-23: EMAC1CFG1: ETHERNET CONTROLLER MAC CONFIGURATION 1 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
Bit
30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
SOFT
RESET
SIM
RESET
—
—
RESET
RMCS
RESET
RFUN
RESET
TMCS
RESET
TFUN
U-0
U-0
U-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-1
LOOPBACK
TX
PAUSE
RX
PAUSE
PASSALL
RX
ENABLE
—
Legend:
R = Readable bit
-n = Value at POR
—
—
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
SOFTRESET: Soft Reset bit
Setting this bit will put the MACMII in reset. Its default value is ‘1’.
bit 14
SIMRESET: Simulation Reset bit
Setting this bit will cause a reset to the random number generator within the Transmit Function.
bit 13-12 Unimplemented: Read as ‘0’
bit 11
RESETRMCS: Reset MCS/RX bit
Setting this bit will put the MAC Control Sub-layer/Receive domain logic in reset.
bit 10
RESETRFUN: Reset RX Function bit
Setting this bit will put the MAC Receive function logic in reset.
bit 9
RESETTMCS: Reset MCS/TX bit
Setting this bit will put the MAC Control Sub-layer/TX domain logic in reset.
bit 8
RESETTFUN: Reset TX Function bit
Setting this bit will put the MAC Transmit function logic in reset.
bit 7-5
Unimplemented: Read as ‘0’
bit 4
LOOPBACK: MAC Loopback mode bit
1 = MAC Transmit interface is loop backed to the MAC Receive interface
0 = MAC normal operation
bit 3
TXPAUSE: MAC TX Flow Control bit
1 = PAUSE Flow Control frames are allowed to be transmitted
0 = PAUSE Flow Control frames are blocked
bit 2
RXPAUSE: MAC RX Flow Control bit
1 = The MAC acts upon received PAUSE Flow Control frames
0 = Received PAUSE Flow Control frames are ignored
bit 1
PASSALL: MAC Pass all Receive Frames bit
1 = The MAC will accept all frames regardless of type (Normal vs. Control)
0 = The received Control frames are ignored
bit 0
RXENABLE: MAC Receive Enable bit
1 = Enable the MAC receiving of frames
0 = Disable the MAC receiving of frames
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
DS60001361J-page 558
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
25/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
—
EXCESS
DFR
BPNOBK
OFF
NOBK
OFF
—
—
LONGPRE
PUREPRE
R/W-1
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
AUTO
PAD(1,2)
VLAN
PAD(1,2)
PAD
ENABLE(1,3)
CRC
ENABLE
DELAYCRC HUGEFRM LENGTHCK FULLDPLX
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14
EXCESSDER: Excess Defer bit
1 = The MAC will defer to carrier indefinitely as per the Standard
0 = The MAC will abort when the excessive deferral limit is reached
bit 13
BPNOBKOFF: Backpressure/No Backoff bit
1 = The MAC after incidentally causing a collision during backpressure will immediately retransmit without
backoff reducing the chance of further collisions and ensuring transmit packets get sent
0 = The MAC will not remove the backoff
bit 12
NOBKOFF: No Backoff bit
1 = Following a collision, the MAC will immediately retransmit rather than using the Binary Exponential Backoff algorithm as specified in the Standard
0 = Following a collision, the MAC will use the Binary Exponential Backoff algorithm
bit 11-10 Unimplemented: Read as ‘0’
bit 9
LONGPRE: Long Preamble Enforcement bit
1 = The MAC only allows receive packets which contain preamble fields less than 12 bytes in length
0 = The MAC allows any length preamble as per the Standard
bit 8
PUREPRE: Pure Preamble Enforcement bit
1 = The MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with
errors in its preamble is discarded
0 = The MAC does not perform any preamble checking
bit 7
AUTOPAD: Automatic Detect Pad Enable bit(1,2)
1 = The MAC will automatically detect the type of frame, either tagged or untagged, by comparing the two
octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly
0 = The MAC does not perform automatic detection
Note 1:
2:
3:
Note:
Table 31-4 provides a description of the pad function based on the configuration of this register.
This bit is ignored if the PADENABLE bit is cleared.
This bit is used in conjunction with the AUTOPAD and VLANPAD bits.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware
2015-2021 Microchip Technology Inc.
DS60001361J-page 559
PIC32MZ Graphics (DA) Family
REGISTER 31-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER
bit 6
VLANPAD: VLAN Pad Enable bit(1,2)
1 = The MAC will pad all short frames to 64 bytes and append a valid CRC
0 = The MAC does not perform padding of short frames
bit 5
PADENABLE: Pad/CRC Enable bit(1,3)
1 = The MAC will pad all short frames
0 = The frames presented to the MAC have a valid length
bit 4
CRCENABLE: CRC Enable1 bit
1 = The MAC will append a CRC to every frame whether padding was required or not. Must be set if the
PADENABLE bit is set.
0 = The frames presented to the MAC have a valid CRC
bit 3
DELAYCRC: Delayed CRC bit
This bit determines the number of bytes, if any, of proprietary header information that exist on the front of the
IEEE 802.3 frames.
1 = Four bytes of header (ignored by the CRC function)
0 = No proprietary header
bit 2
HUGEFRM: Huge Frame enable bit
1 = Frames of any length are transmitted and received
0 = Huge frames are not allowed for receive or transmit
bit 1
LENGTHCK: Frame Length checking bit
1 = Both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field
represents a length then the check is performed. Mismatches are reported on the transmit/receive
statistics vector.
0 = Length/Type field check is not performed
bit 0
FULLDPLX: Full-Duplex Operation bit
1 = The MAC operates in Full-Duplex mode
0 = The MAC operates in Half-Duplex mode
Note 1:
2:
3:
Note:
Table 31-4 provides a description of the pad function based on the configuration of this register.
This bit is ignored if the PADENABLE bit is cleared.
This bit is used in conjunction with the AUTOPAD and VLANPAD bits.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware
TABLE 31-4:
PAD OPERATION
Type
AUTOPAD
VLANPAD
PADENABLE
Any
x
x
0
No pad, check CRC
Any
0
0
1
Pad to 60 Bytes, append CRC
Any
x
1
1
Pad to 64 Bytes, append CRC
Any
1
0
1
If untagged: Pad to 60 Bytes, append CRC
If VLAN tagged: Pad to 64 Bytes, append CRC
DS60001361J-page 560
Action
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-25: EMAC1IPGT: ETHERNET CONTROLLER MAC BACK-TO-BACK INTERPACKET
GAP REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
—
B2BIPKTGP
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-7
Unimplemented: Read as ‘0’
bit 6-0
B2BIPKTGP: Back-to-Back Interpacket Gap bits
This is a programmable field representing the nibble time offset of the minimum possible period between
the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value
should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the
desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6 µs (in 10 Mbps). In Half-Duplex mode, the recommended setting is 0x12 (18d), which also represents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6
µs (in 10 Mbps).
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
2015-2021 Microchip Technology Inc.
DS60001361J-page 561
PIC32MZ Graphics (DA) Family
REGISTER 31-26: EMAC1IPGR: ETHERNET CONTROLLER MAC NON-BACK-TO-BACK
INTERPACKET GAP REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-0
—
U-0
NB2BIPKTGP1
—
R/W-0
NB2BIPKTGP2
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-15
Unimplemented: Read as ‘0’
bit 14-8
NB2BIPKTGP1: Non-Back-to-Back Interpacket Gap Part 1 bits
This is a programmable field representing the optional carrierSense window referenced in section
4.2.3.2.1 “Deference” of the IEEE 80.23 Specification. If carrier is detected during the timing of IPGR1, the
MAC defers to carrier. If, however, carrier becomes after IPGR1, the MAC continues timing IPGR2 and
transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to
IPGR2. Its recommend value is 0xC (12d).
bit 7
Unimplemented: Read as ‘0’
bit 6-0
NB2BIPKTGP2: Non-Back-to-Back Interpacket Gap Part 2 bits
This is a programmable field representing the non-back-to-back Inter-Packet-Gap. Its recommended value
is 0x12 (18d), which represents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6 µs (in 10 Mbps).
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
DS60001361J-page 562
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-27: EMAC1CLRT: ETHERNET CONTROLLER MAC COLLISION WINDOW/RETRY
LIMIT REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-1
R/W-1
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U-0
U-0
U-0
U-0
CWINDOW
—
—
—
—
R/W-1
R/W-1
RETX
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13-8
CWINDOW: Collision Window bits
This is a programmable field representing the slot time or collision window during which collisions occur in
properly configured networks. Since the collision window starts at the beginning of transmission, the preamble and SFD is included. Its default of 0x37 (55d) corresponds to the count of frame bytes at the end of
the window.
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
RETX: Retransmission Maximum bits
This is a programmable field specifying the number of retransmission attempts following a collision before
aborting the packet due to excessive collisions. The Standard specifies the maximum number of attempts
(attemptLimit) to be 0xF (15d). Its default is ‘0xF’.
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
2015-2021 Microchip Technology Inc.
DS60001361J-page 563
PIC32MZ Graphics (DA) Family
REGISTER 31-28: EMAC1MAXF: ETHERNET CONTROLLER MAC MAXIMUM FRAME LENGTH
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
MACMAXF(1)
R/W-1
R/W-1
R/W-1
R/W-0
R/W-1
MACMAXF(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
MACMAXF: Maximum Frame Length bits(1)
These bits reset to 0x05EE, which represents a maximum receive frame of 1518 octets. An untagged
maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If
a shorter/longer maximum length restriction is desired, program this 16-bit field.
Note 1:
If a proprietary header is allowed, this bit should be adjusted accordingly. For example, if 4-byte headers
are prepended to frames, MACMAXF could be set to 1527 octets. This would allow the maximum VLAN
tagged frame plus the 4-byte header.
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
DS60001361J-page 564
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-29: EMAC1SUPP: ETHERNET CONTROLLER MAC PHY SUPPORT REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4
Bit
27/19/11/3
Bit
Bit
26/18/10/2 25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
U-0
U-0
R/W-0
—
—
—
—
RESETRMII(1)
—
—
SPEEDRMII(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-12
Unimplemented: Read as ‘0’
bit 11
RESETRMII: Reset RMII Logic bit(1)
1 = Reset the MAC RMII module
0 = Normal operation.
bit 10-9
Unimplemented: Read as ‘0’
bit 8
SPEEDRMII: RMII Speed bit(1)
This bit configures the Reduced MII logic for the current operating speed.
1 = RMII is running at 100 Mbps
0 = RMII is running at 10 Mbps
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
Note:
x = Bit is unknown
This bit is only used for the RMII module.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
2015-2021 Microchip Technology Inc.
DS60001361J-page 565
PIC32MZ Graphics (DA) Family
REGISTER 31-30: EMAC1TEST: ETHERNET CONTROLLER MAC TEST REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
TESTBP
TESTPAUSE(1) SHRTQNTA(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-3 Unimplemented: Read as ‘0’
bit 2
TESTBP: Test Backpressure bit
1 = The MAC will assert backpressure on the link. Backpressure causes preamble to be transmitted, raising
carrier sense. A transmit packet from the system will be sent during backpressure.
0 = Normal operation
bit 1
TESTPAUSE: Test PAUSE bit(1)
1 = The MAC Control sub-layer will inhibit transmissions, just as if a PAUSE Receive Control frame with a
non-zero pause time parameter was received
0 = Normal operation
bit 0
SHRTQNTA: Shortcut PAUSE Quanta bit(1)
1 = The MAC reduces the effective PAUSE Quanta from 64 byte-times to 1 byte-time
0 = Normal operation
Note 1:
Note:
This bit is only used for testing purposes.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
DS60001361J-page 566
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-31: EMAC1MCFG: ETHERNET CONTROLLER MAC MII MANAGEMENT
CONFIGURATION REGISTER
Bit
Range
Bit
31/23/15/7
31:24
23:16
15:8
Bit
Bit
30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
RESETMGMT
—
—
—
—
—
—
—
U-0
U-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
NOPRE
SCANINC
7:0
Legend:
R = Readable bit
-n = Value at POR
CLKSEL(1)
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
RESETMGMT: Test Reset MII Management bit
1 = Reset the MII Management module
0 = Normal Operation
bit 14-6 Unimplemented: Read as ‘0’
bit 5-2
CLKSEL: MII Management Clock Select 1 bits(1)
These bits are used by the clock divide logic in creating the MII Management Clock (MDC), which the IEEE
802.3 Specification defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz.
bit 1
NOPRE: Suppress Preamble bit
1 = The MII Management will perform read/write cycles without the 32-bit preamble field. Some PHYs
support suppressed preamble
0 = Normal read/write cycles are performed
bit 0
SCANINC: Scan Increment bit
1 = The MII Management module will perform read cycles across a range of PHYs. The read cycles will start
from address 1 through the value set in EMAC1MADR
0 = Continuous reads of the same PHY
Note 1:
Note:
Table 31-5 provides a description of the clock divider encoding.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
TABLE 31-5:
MIIM CLOCK SELECTION
MIIM Clock Select
EMAC1MCFG
TPBCLK5 divided by 4
TPBCLK5 divided by 6
TPBCLK5 divided by 8
TPBCLK5 divided by 10
TPBCLK5 divided by 14
TPBCLK5 divided by 20
TPBCLK5 divided by 28
TPBCLK5 divided by 40
TPBCLK5 divided by 48
TPBCLK5 divided by 50
Undefined
000x
0010
0011
0100
0101
0110
0111
1000
1001
1010
Any other combination
2015-2021 Microchip Technology Inc.
DS60001361J-page 567
PIC32MZ Graphics (DA) Family
REGISTER 31-32: EMAC1MCMD: ETHERNET CONTROLLER MAC MII MANAGEMENT COMMAND
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
Bit
Bit
26/18/10/2 25/17/9/1 24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
SCAN
READ
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-2
Unimplemented: Read as ‘0’
bit 1
SCAN: MII Management Scan Mode bit
1 = The MII Management module will perform read cycles continuously (for example, useful for monitoring
the Link Fail)
0 = Normal Operation
bit 0
READ: MII Management Read Command bit
1 = The MII Management module will perform a single read cycle. The read data is returned in the
EMAC1MRDD register
0 = The MII Management module will perform a write cycle. The write data is taken from the EMAC1MWTD
register
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
DS60001361J-page 568
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-33: EMAC1MADR: ETHERNET CONTROLLER MAC MII MANAGEMENT ADDRESS
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
—
—
—
PHYADDR
R/W-0
REGADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ’0’
bit 12-8
PHYADDR: MII Management PHY Address bits
This field represents the 5-bit PHY Address field of Management cycles. Up to 31 PHYs can be addressed
(0 is reserved).
bit 7-5
Unimplemented: Read as ’0’
bit 4-0
REGADDR: MII Management Register Address bits
This field represents the 5-bit Register Address field of Management cycles. Up to 32 registers can be
accessed.
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
2015-2021 Microchip Technology Inc.
DS60001361J-page 569
PIC32MZ Graphics (DA) Family
REGISTER 31-34: EMAC1MWTD: ETHERNET CONTROLLER MAC MII MANAGEMENT WRITE
DATA REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MWTD
R/W-0
R/W-0
MWTD
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ’0’
bit 15-0
MWTD: MII Management Write Data bits
When written, a MII Management write cycle is performed using the 16-bit data and the preconfigured PHY
and Register addresses from the EMAC1MADR register.
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
REGISTER 31-35: EMAC1MRDD: ETHERNET CONTROLLER MAC MII MANAGEMENT READ DATA
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MRDD
R/W-0
MRDD
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
Note:
MRDD: MII Management Read Data bits
Following a MII Management Read Cycle, the 16-bit data can be read from this location.
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
DS60001361J-page 570
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-36: EMAC1MIND: ETHERNET CONTROLLER MAC MII MANAGEMENT INDICATORS
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
LINKFAIL
NOTVALID
SCAN
MIIMBUSY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3
LINKFAIL: Link Fail bit
When ‘1’ is returned - indicates link fail has occurred. This bit reflects the value last read from the PHY status
register.
bit 2
NOTVALID: MII Management Read Data Not Valid bit
When ‘1’ is returned - indicates an MII management read cycle has not completed and the Read Data is not
yet valid.
bit 1
SCAN: MII Management Scanning bit
When ‘1’ is returned - indicates a scan operation (continuous MII Management Read cycles) is in progress.
bit 0
MIIMBUSY: MII Management Busy bit
When ‘1’ is returned - indicates MII Management module is currently performing an MII Management Read
or Write cycle.
Note:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
2015-2021 Microchip Technology Inc.
DS60001361J-page 571
PIC32MZ Graphics (DA) Family
REGISTER 31-37: EMAC1SA0: ETHERNET CONTROLLER MAC STATION ADDRESS 0 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
Bit
27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
STNADDR6
R/W-P
R/W-P
STNADDR5
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-8
STNADDR6: Station Address Octet 6 bits
These bits hold the sixth transmitted octet of the station address.
bit 7-0
STNADDR5: Station Address Octet 5 bits
These bits hold the fifth transmitted octet of the station address.
Note 1:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
This register is loaded at reset from the factory preprogrammed station address.
2:
DS60001361J-page 572
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 31-38: EMAC1SA1: ETHERNET CONTROLLER MAC STATION ADDRESS 1 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
STNADDR4
R/W-P
R/W-P
STNADDR3
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-8
STNADDR4: Station Address Octet 4 bits
These bits hold the fourth transmitted octet of the station address.
bit 7-0
STNADDR3: Station Address Octet 3 bits
These bits hold the third transmitted octet of the station address.
Note 1:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
This register is loaded at reset from the factory preprogrammed station address.
2:
2015-2021 Microchip Technology Inc.
DS60001361J-page 573
PIC32MZ Graphics (DA) Family
REGISTER 31-39: EMAC1SA2: ETHERNET CONTROLLER MAC STATION ADDRESS 2 REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
R/W-P
STNADDR2
R/W-P
R/W-P
STNADDR1
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Reserved: Maintain as ‘0’; ignore read
bit 15-8
STNADDR2: Station Address Octet 2 bits
These bits hold the second transmitted octet of the station address.
bit 7-0
STNADDR1: Station Address Octet 1 bits
These bits hold the most significant (first transmitted) octet of the station address.
Note 1:
Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
This register is loaded at reset from the factory preprogrammed station address.
2:
DS60001361J-page 574
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
32.0
COMPARATOR
Note:
The Analog Comparator module consists of two
comparators that can be configured in a variety of
ways.
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet,
refer
to
Section
19.
“Comparator” (DS60001110), which is
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
Key features of the Analog Comparator module are:
•
•
•
•
Differential inputs
Rail-to-rail operation
Selectable output polarity
Selectable inputs:
- Analog inputs multiplexed with I/O pins
- On-chip internal absolute voltage reference
- Comparator voltage reference (CVREF)
• Selectable interrupt generation
A block diagram of the comparator module is illustrated
in Figure 32-1.
FIGURE 32-1:
COMPARATOR BLOCK DIAGRAM
CCH (CM1CON)
C1INB
C1INC
COE (CM1CON)
C1IND
CMP1
CREF
(CM1CON)
C1OUT
CPOL
(CM1CON)
COUT (CM1CON)
and Trigger to ADC
C1INA
D
Q
CCH (CM2CON)
C2INB
C1OUT
(CMSTAT)
PBCLK3
C2INC
COE (CM2CON)
C2IND
CMP2
CREF
(CM2CON)
C2OUT
CPOL
(CM2CON)
COUT (CM2CON) and
Trigger to ADC
C2INA
CVREF(1)
IVREF (1.2V)
Note 1:
D
Q
C2OUT
(CMSTAT)
PBCLK3
Internally connected. See Section 33.0 “Comparator Voltage Reference (CVREF)” for more information.
2015-2021 Microchip Technology Inc.
DS60001361J-page 575
Comparator Control Registers
COMPARATOR REGISTER MAP
C000 CM1CON
C010 CM2CON
C060 CMSTAT
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
—
31:16
—
—
—
—
—
—
—
—
15:0
ON
COE
CPOL
—
—
—
—
COUT
31:16
—
—
—
—
—
—
—
—
15:0
ON
COE
CPOL
—
—
—
—
COUT
31:16
—
—
—
—
—
—
—
15:0
—
—
SIDL
—
—
—
—
20/4
19/3
18/2
17/1
16/0
—
—
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF84_#)
TABLE 32-1:
—
—
—
—
—
EVPOL
—
CREF
—
—
—
—
—
—
—
—
EVPOL
—
CREF
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
C2OUT
C1OUT
0000
CCH
—
—
CCH
0000
00C3
0000
00C3
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 576
32.1
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 32-1:
Bit
Range
31:24
23:16
15:8
7:0
CMxCON: COMPARATOR CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
R/W-0
R/W-0
ON
COE
R/W-1
R/W-1
EVPOL
Legend:
R = Readable bit
-n = Value at POR
bit 31-26
bit 25-24
bit 23-16
bit 15
bit 14
bit 13
bit 12-9
bit 8
bit 7-6
bit 5
bit 4
bit 3-2
bit 1-0
Note 1:
Bit
Bit
28/20/12/4 27/19/11/3
—
R/W-0
(1)
CPOL
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
R-0
COUT
—
—
—
—
U-0
R/W-0
U-0
U-0
R/W-1
—
CREF
—
—
W = Writable bit
‘1’ = Bit is set
R/W-1
CCH
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
ON: Comparator ON bit
1 = Module is enabled. Setting this bit does not affect the other bits in this register
0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this
register
COE: Comparator Output Enable bit
1 = Comparator output is driven on the output CxOUT pin
0 = Comparator output is not driven on the output CxOUT pin
CPOL: Comparator Output Inversion bit(1)
1 = Output is inverted
0 = Output is not inverted
Unimplemented: Read as ‘0’
COUT: Comparator Output bit
1 = Output of the Comparator is a ‘1’
0 = Output of the Comparator is a ‘0’
EVPOL: Interrupt Event Polarity Select bits
11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
10 = Comparator interrupt is generated on a high-to-low transition of the comparator output
01 = Comparator interrupt is generated on a low-to-high transition of the comparator output
00 = Comparator interrupt generation is disabled
Unimplemented: Read as ‘0’
CREF: Comparator Positive Input Configure bit
1 = Comparator non-inverting input is connected to the internal CVREF
0 = Comparator non-inverting input is connected to the CXINA pin
Unimplemented: Read as ‘0’
CCH: Comparator Negative Input Select bits for Comparator
11 = Comparator inverting input is connected to the IVREF
10 = Comparator inverting input is connected to the CxIND pin
01 = Comparator inverting input is connected to the CxINC pin
00 = Comparator inverting input is connected to the CxINB pin
Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an
interrupt being generated on the opposite edge from the one selected by EVPOL.
2015-2021 Microchip Technology Inc.
DS60001361J-page 577
PIC32MZ Graphics (DA) Family
REGISTER 32-2:
Bit
Range
31:24
23:16
15:8
7:0
CMSTAT: COMPARATOR STATUS REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
SIDL
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R-0
R-0
—
—
—
—
—
—
C2OUT
C1OUT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13
SIDL: Stop in IDLE Control bit
1 = All Comparator modules are disabled in IDLE mode
0 = All Comparator modules continue to operate in the IDLE mode
bit 12-2
Unimplemented: Read as ‘0’
bit 1
C2OUT: Comparator Output bit
1 = Output of Comparator 2 is a ‘1’
0 = Output of Comparator 2 is a ‘0’
bit 0
C1OUT: Comparator Output bit
1 = Output of Comparator 1 is a ‘1’
0 = Output of Comparator 1 is a ‘0’
DS60001361J-page 578
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
33.0
Note:
COMPARATOR VOLTAGE
REFERENCE (CVREF)
The resistor ladder is segmented to provide two ranges
of voltage reference values and has a power-down
function to conserve power when the reference is not
being used. The module’s supply reference can be provided from either device VDDIO/VSS or an external
voltage reference. The CVREF output is available for
the comparators and typically available for pin output.
This data sheet summarizes the
features of the PIC32MZ Graphics (DA)
Family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 20. “Comparator Voltage Reference (CVREF)”
(DS60001109), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The comparator voltage reference has the following
features:
• High and low range selection
• Sixteen output levels available for each range
• Internally connected to comparators to conserve
device pins
• Output can be connected to a pin
The CVREF module is a 16-tap, resistor ladder network
that provides a selectable reference voltage. Although
its primary purpose is to provide a reference for the
analog comparators, it also may be used independently
of them.
FIGURE 33-1:
VREF+
AVDD
A block diagram of the CVREF module is illustrated in
Figure 33-1.
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
CVRSRC
8R
CVRSS = 0
CVR
CVREF
R
CVREN
R
R
16-to-1 MUX
R
16 Steps
R
CVREFOUT
CVRCON
R
R
CVRR
VREFAVSS
2015-2021 Microchip Technology Inc.
8R
CVRSS = 1
CVRSS = 0
DS60001361J-page 579
Comparator Voltage Reference Control Registers
Virtual Address
(BF80_#)
TABLE 33-1:
COMPARATOR VOLTAGE REFERENCE REGISTER MAP
0E00 CVRCON
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
—
—
—
—
—
—
—
CVROE
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
CVRR
CVRSS
CVR
All Resets
Register
Name(1)
Bit Range
Bits
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
The register in this table has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
1:
PIC32MZ Graphics (DA) Family
DS60001361J-page 580
33.1
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 33-1:
Bit
Range
31:24
23:16
15:8
7:0
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
ON
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CVROE
CVRR
CVRSS
CVR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Comparator Voltage Reference On bit
1 = Module is enabled
Setting this bit does not affect other bits in the register.
0 = Module is disabled and does not consume current.
Clearing this bit does not affect the other bits in the register.
bit 14-7
Unimplemented: Read as ‘0’
bit 6
CVROE: CVREFOUT Enable bit
1 = Voltage level is output on CVREFOUT pin
0 = Voltage level is disconnected from CVREFOUT pin
bit 5
CVRR: CVREF Range Selection bit
1 = 0 to 0.67 CVRSRC, with CVRSRC/24 step size
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size
bit 4
CVRSS: CVREF Source Selection bit
1 = Comparator voltage reference source, CVRSRC = (VREF+) – (VREF-)
0 = Comparator voltage reference source, CVRSRC = AVDD – AVSS
bit 3-0
CVR: CVREF Value Selection 0 CVR 15 bits
When CVRR = 1:
CVREF = (CVR/24) (CVRSRC)
When CVRR = 0:
CVREF = 1/4 (CVRSRC) + (CVR/32) (CVRSRC)
2015-2021 Microchip Technology Inc.
DS60001361J-page 581
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 582
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
34.0
HIGH/LOW-VOLTAGE DETECT
(HLVD)
Note:
The High/Low-Voltage Detect (HLVD) module is a
programmable circuit that allows the user to specify
both the device voltage trip point and the direction of
change.
This data sheet summarizes the
features of the PIC32MZ Graphics (DA)
Family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 38.
“High/Low-Voltage Detect (HLVD)”
(DS60001408), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
FIGURE 34-1:
The HLVD module provides the following features:
• Hysteresis detection
• Low-to-high or high-to-low voltage change
detection
• Generation of Non-Maskable Interrupts (NMI)
• LVDIN pin to provide external voltage trip point
HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM
Externally Generated
Trip Point
VDDIO
VDDIO
HLVDIN
HLVDL
16-to-1 MUX
ON
VDIR
HLVD Event to
NMI
Band Gap
Reference
ON
2015-2021 Microchip Technology Inc.
DS60001361J-page 583
Control Registers
Virtual Address
(BF80_#)
TABLE 34-1:
HIGH/LOW-VOLTAGE DETECT REGISTER MAP
1800 HLVDCON
31/15
30/14
29/13
28/12
31:16
—
—
—
—
15:0
ON
—
—
—
27/11
26/10
25/9
—
—
—
VDIR
BGVST
—
24/8
23/7
22/6
21/5
20/4
19/3
—
—
—
—
—
—
—
—
—
HLEVT HLEVTOUTDIS
18/2
17/1
16/0
—
—
—
HLVDL
All Resets
Bit Range
Register
Name(1)
Bits
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
The register in this table has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
1:
PIC32MZ Graphics (DA) Family
DS60001361J-page 584
34.1
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
H
REGISTER 34-1:
Bit
Range
31:24
23:16
15:8
7:0
HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
Bit
31/23/15/7
Bit
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
U-0
U-0
U-0
R/W-0
HS,HC,R-0
r-1
HS,HC,R-0
ON
—
—
—
VDIR
BGVST
—
HLEVT
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
HLEVTOUTDIS(2)
—
—
—
R/W-0
(1)
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Set
W = Writable bit
‘1’ = Bit is set
HLVDL
HC = Hardware Cleared r = Reserved bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: HLVD Module Enable bit
1 = HLVD module is enabled
0 = HLVD module is disabled
bit 14-12 Unimplemented: Read as ‘0’
bit 11
VDIR: Voltage Change Direction Select bit
1 = Event occurs when voltage equals or exceeds the trip point (HLVDL)
0 = Event occurs when voltage equals or falls below the trip point (HLVDL)
bit 10
BGVST: Band Gap Reference Voltages Stable Status bit
1 = Indicates internal band gap voltage references is stable
0 = Indicates internal band gap voltage reference is not stable
This bit is readable when the HLVD module is disabled (ON = 0).
bit 9
Reserved: Read as ‘1’
bit 8
HLEVT: High/Low-Voltage Detection Event Status bit
1 = Indicates HLVD Event is active
0 = Indicates HLVD Event is not active
bit 7
HLEVTOUTDIS: High/Low-Voltage Detection Event Output Disable bit(2)
1 = Enables HLVD Event output
0 = Disable HLVD Event output
bit 6-4
Unimplemented: Read as ‘0’
Note 1:
2:
To avoid false HLVD events, all HLVD module setting changes should occur only when the module is
disabled (ON = 0). See Table 44-6 in 44.0 “Electrical Characteristics” for the actual trip points.
Once this bit is set to '1', it can only be cleared by disabling or enabling the HLVD module (or through the
HLVDMD bit).
2015-2021 Microchip Technology Inc.
DS60001361J-page 585
PIC32MZ Graphics (DA) Family
REGISTER 34-1:
HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
HLVDL: High/Low-Voltage Detection Limit Select bits(1)
1111 = Selects analog input on HLVDIN
1110 = Reserved; do not use
1101 = Reserved; do not use
1100 = Reserved; do not use
1011 = Selects trip point 11
1010 = Selects trip point 10
1001 = Selects trip point 9
1000 = Selects trip point 8
0111 = Selects trip point 7
0110 = Selects trip point 6
0101 = Selects trip point 5
0100 = Selects trip point 4
0011 = Reserved; do not use
0010 = Reserved; do not use
0001 = Reserved; do not use
0000 = Reserved; do not use
Note 1: To avoid false HLVD events, all HLVD module setting changes should occur only when the
module is disabled (ON = 0). See Table 44-6 in 44.0 “Electrical Characteristics” for the
actual trip points.
2: Once this bit is set to '1', it can only be cleared by disabling or enabling the HLVD module (or
through the HLVDMD bit).
bit 3-0
Note 1:
2:
To avoid false HLVD events, all HLVD module setting changes should occur only when the module is
disabled (ON = 0). See Table 44-6 in 44.0 “Electrical Characteristics” for the actual trip points.
Once this bit is set to '1', it can only be cleared by disabling or enabling the HLVD module (or through the
HLVDMD bit).
DS60001361J-page 586
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
35.0
Note:
CHARGE TIME
MEASUREMENT UNIT (CTMU)
The CTMU module includes the following key features:
• Up to 35 channels available for capacitive or time
measurement input (AN5 to AN39)
• On-chip precision current source
• 16-edge input trigger sources
• Selection of edge or level-sensitive inputs
• Polarity control for each edge source
• Control of edge sequence
• Control of response to edges
• High precision time measurement
• Time delay of external or internal signal asynchronous to system clock
• Integrated temperature sensing diode
• Control of current source during auto-sampling
• Four current source ranges
• Time measurement resolution of one nanosecond
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family
family of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 37. “Charge Time
Measurement
Unit
(CTMU)”
(DS60001167), which is available from the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The Charge Time Measurement Unit (CTMU) is a
flexible analog module that has a configurable current
source with a digital configuration circuit built around it.
The CTMU can be used for differential time
measurement between pulse sources and can be used
for generating an asynchronous pulse. By working with
other on-chip analog modules, the CTMU can be used
for high resolution time measurement, measure
capacitance, measure relative changes in capacitance
or generate output pulses with a specific time delay.
The CTMU is ideal for interfacing with capacitive-based
sensors.
FIGURE 35-1:
A block diagram of the CTMU is shown in Figure 35-1.
CTMU BLOCK DIAGRAM
CTMUCON
ITRIM
IRNG
Current Source
CTED1
Edge
Control
Logic
CTED2
Timer1
OC1-OC4
IC1-IC6
CMP1-CMP2
PBCLK3
EDG1STAT
EDG2STAT
TGEN
Current
Control
CTMUP
CTMUT
(To ADC)
Temperature
Sensor
CTMU
Control
Logic
ADC
Trigger
Pulse
Generator
CTPLS
CTMUI
(To ADC S&H capacitor)
C2INB
CDELAY
Comparator 2
External capacitor
for pulse generation
Current Control Selection
TGEN
EDG1STAT, EDG2STAT
CTMUT
0
EDG1STAT = EDG2STAT
CTMUI
0
EDG1STAT EDG2STAT
CTMUP
1
EDG1STAT EDG2STAT
No Connect
1
EDG1STAT = EDG2STAT
2015-2021 Microchip Technology Inc.
DS60001361J-page 587
CTMU Control Registers
CTMU REGISTER MAP
C200 CTMUCON
Legend:
Note 1:
31/15
30/14
29/13
28/12
CTMUSIDL
TGEN
31:16 EDG1MOD EDG1POL
15:0
ON
—
27/11
EDG1SEL
26/10
25/9
24/8
23/7
22/6
EDG2STAT EDG1STAT EDG2MOD EDG2POL
EDGEN EDGSEQEN IDISSEN
CTTRIG
21/5
20/4
19/3
EDG2SEL
ITRIM
18/2
All Resets
Bit Range
Bits
Register
Name(1)
Virtual Address
(BF84_#)
TABLE 35-1:
17/1
16/0
—
—
0000
IRNG
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
PIC32MZ Graphics (DA) Family
DS60001361J-page 588
35.1
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 35-1:
Bit
Range
31:24
23:16
15:8
7:0
CTMUCON: CTMU CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
EDG1MOD EDG1POL
R/W-0
R/W-0
R/W-0
Bit
26/18/10/2
R/W-0
EDG1SEL
R/W-0
R/W-0
EDG2MOD EDG2POL
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
EDG2STAT EDG1STAT
R/W-0
EDG2SEL
U-0
U-0
—
—
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ON
—
CTMUSIDL
TGEN(1)
EDGEN
EDGSEQEN
IDISSEN(2)
CTTRIG
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ITRIM
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
IRNG
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
EDG1MOD: Edge1 Edge Sampling Select bit
1 = Input is edge-sensitive
0 = Input is level-sensitive
bit 30
EDG1POL: Edge 1 Polarity Select bit
1 = Edge1 programmed for a positive edge response
0 = Edge1 programmed for a negative edge response
bit 29-26 EDG1SEL: Edge 1 Source Select bits
1111 = Reserved
1110 = C2OUT pin is selected
1101 = C1OUT pin is selected
1100 = IC6 Capture Event is selected
1011 = IC5 Capture Event is selected
1010 = IC4 Capture Event is selected
1001 = IC3 Capture Event is selected
1000 = IC2 Capture Event is selected
0111 = IC1 Capture Event is selected
0110 = OC4 Capture Event is selected
0101 = OC3 Capture Event is selected
0100 = OC2 Capture Event is selected
0011 = CTED1 pin is selected
0010 = CTED2 pin is selected
0001 = OC1 Compare Event is selected
0000 = Timer1 Event is selected
bit 25
EDG2STAT: Edge2 Status bit
Indicates the status of Edge2 and can be written to control edge source
1 = Edge2 has occurred
0 = Edge2 has not occurred
Note 1:
2:
3:
4:
When this bit is set for Pulse Delay Generation, the EDG2SEL bits must be set to ‘1110’ to select
the C2OUT pin.
The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
Refer to the CTMU Current Source Specifications (Table 44-20) in Section 44.0 “Electrical
Characteristics” for current values.
This bit setting is not available for the CTMU temperature diode.
2015-2021 Microchip Technology Inc.
DS60001361J-page 589
PIC32MZ Graphics (DA) Family
REGISTER 35-1:
bit 24
bit 23
bit 22
bit 21-18
bit 17-16
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
Note 1:
2:
3:
4:
CTMUCON: CTMU CONTROL REGISTER (CONTINUED)
EDG1STAT: Edge1 Status bit
Indicates the status of Edge1 and can be written to control edge source
1 = Edge1 has occurred
0 = Edge1 has not occurred
EDG2MOD: Edge2 Edge Sampling Select bit
1 = Input is edge-sensitive
0 = Input is level-sensitive
EDG2POL: Edge 2 Polarity Select bit
1 = Edge2 programmed for a positive edge response
0 = Edge2 programmed for a negative edge response
EDG2SEL: Edge 2 Source Select bits
1111 = Reserved
1110 = C2OUT pin is selected
1101 = C1OUT pin is selected
1100 = PBCLK3
1011 = IC5 Capture Event is selected
1010 = IC4 Capture Event is selected
1001 = IC3 Capture Event is selected
1000 = IC2 Capture Event is selected
0111 = IC1 Capture Event is selected
0110 = OC4 Capture Event is selected
0101 = OC3 Capture Event is selected
0100 = OC2 Capture Event is selected
0011 = CTED1 pin is selected
0010 = CTED2 pin is selected
0001 = OC1 Compare Event is selected
0000 = Timer1 Event is selected
Unimplemented: Read as ‘0’
ON: ON Enable bit
1 = Module is enabled
0 = Module is disabled
Unimplemented: Read as ‘0’
CTMUSIDL: Stop-in-Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
TGEN: Time Generation Enable bit(1)
1 = Enables edge delay generation
0 = Disables edge delay generation
EDGEN: Edge Enable bit
1 = Edges are not blocked
0 = Edges are blocked
EDGSEQEN: Edge Sequence Enable bit
1 = Edge1 must occur before Edge2 can occur
0 = No edge sequence is needed
When this bit is set for Pulse Delay Generation, the EDG2SEL bits must be set to ‘1110’ to select
the C2OUT pin.
The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
Refer to the CTMU Current Source Specifications (Table 44-20) in Section 44.0 “Electrical
Characteristics” for current values.
This bit setting is not available for the CTMU temperature diode.
DS60001361J-page 590
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 35-1:
CTMUCON: CTMU CONTROL REGISTER (CONTINUED)
IDISSEN: Analog Current Source Control bit(2)
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
CTTRIG: Trigger Control bit
1 = Trigger output is enabled
0 = Trigger output is disabled
ITRIM: Current Source Trim bits
011111 = Maximum positive change from nominal current
011110
bit 9
bit 8
bit 7-2
•
•
•
000001 = Minimum positive change from nominal current
000000 = Nominal current output specified by IRNG
111111 = Minimum negative change from nominal current
•
•
•
100010
100001 = Maximum negative change from nominal current
IRNG: Current Range Select bits(3)
11 = 100 times base current
10 = 10 times base current
01 = Base current level
00 = 1000 times base current(4)
bit 1-0
Note 1:
2:
3:
4:
When this bit is set for Pulse Delay Generation, the EDG2SEL bits must be set to ‘1110’ to select
the C2OUT pin.
The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
Refer to the CTMU Current Source Specifications (Table 44-20) in Section 44.0 “Electrical
Characteristics” for current values.
This bit setting is not available for the CTMU temperature diode.
2015-2021 Microchip Technology Inc.
DS60001361J-page 591
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 592
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
36.0
GRAPHICS LCD (GLCD)
CONTROLLER
Note 1: This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 54. “Graphics
LCD Controller” (DS60001379), which
is available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
The Graphics LCD (GLCD) Controller is designed to
directly interface with display panels with up to 24-bit
color depth.
The GLCD Controller transfers display data from a
memory device and formats it for a display device. The
memory may be internal RAM or DDR2.
The parallel interface at the pins will operate at standard 3.3V output, requires 28 pins for 24-bit color, and
is shared by general purpose I/O functions.
Key features of the GLCD Controller include:
• Supports a 50 MHz Pixel Clock (dependent on
DDR2 bandwidth)
• Up to 800x480 (WVGA) with Overlay and smaller
with three Overlay layers. High resolution is possible with smaller displays.
• Color depths: 8-bit, 16-bit, 18-bit, and 24-bit
Note:
16-bit color depth is supported through the
GLCDMODE bit (CFGCON2). When
set, functions shared with GD0, GD1, GD2,
GD8, GD9, GD16, GD17, GD18 are available for general purpose use.
• Up to three design timing layers, each including:
- Configurable Alpha blending
- Configurable Stride and Pitch
• Input formats: RGBA8888, ARGB8888, RGB888,
RGB565, RGBA5551, YUYV, RGB332, LUT8,
and Gray-scale
• Output formats: RGB888, RGB666, BT.656
• Dithering for 18-bit displays
• High-quality YUV conversion
• Global color palette look-up table (CLUT) supporting
256 colors
• Global gamma correction, brightness and contrast
support
• Programmable cursors supporting 16 colors
• Programmable polarity on HSYNC, VSYNC, DE,
and PCLK
• Integrated DMA to offload the CPU
• Programmable (level/edge) interrupt on HSYNC and
VSYNC
2015-2021 Microchip Technology Inc.
DS60001361J-page 593
TABLE 36-1:
RGB COLOR MAPPING
GLCD signal
on pin
GD23
GD22
GD21
GD20
GD19
GD18
GD17
GD16
GD15
GD14
GD13
GD12
GD11
GD10
GD9
GD8
GD7
GD6
GD5
GD4
GD3
GD2
GD1
GD0
24 bit color
B7
B6
B5
B4
B3
B2
B1
B0
G7
G6
G5
G4
G3
G2
G1
G0
R7
R6
R5
R4
R3
R2
R1
R0
16 bit color
B7
B6
B5
B4
B3
x
x
x
G7
G6
G5
G4
G3
G2
x
x
R7
R6
R5
R4
R3
x
x
x
Figure 36-1 shows a block diagram of the GLCD Controller interface.
PIC32MZ Graphics (DA) Family
DS60001361J-page 594
The following table provides the RGB color mapping in 16 bit and 24 bit modes
with GLCD output signals.
2015-2021 Microchip Technology Inc.
2015-2021 Microchip Technology Inc.
FIGURE 36-1:
R = GD; G = GD; B = GD.
PIC32MZ Graphics (DA) Family
DS60001361J-page 595
Note 1:
GRAPHICS LCD CONTROLLER BLOCK DIAGRAM
Graphics LCD Controller Control Registers
A000
A004
GLCD
CLKCON
GLCD
A008
BGCOLOR
Bit 31/15
31:16
LCDEN
Bit 30/14 Bit 29/13 Bit 28/12 Bit 27/11 Bit 26/10 Bit 25/9
Bit 24/8
Bit 23/7
Bit 22/6
Bit 21/5
CURSOR
EN
DITHER
VSYNC
CYC
PCLK
POL
—
—
VSYNC
POL
15:0
—
—
—
—
31:16
—
—
—
—
15:0
—
—
HSYNC
POL
DEPOL
—
—
—
—
—
YUV
FORMAT
OUTPUT
CLK
—
—
LPREFETCH
Bit 20/4
—
—
—
—
—
Bit 16/0
—
—
—
0000
Bit 19/3 Bit 118/2
PGRAMP FORCE
EN
BLANK
RGBSEQ
Bit 17/1
All Resets
GLCD
MODE
GRAPHICS LCD CONTROLLER REGISTER MAP
Bit Range
Register
Name
Virtual Address
(BF8E_#)
TABLE 36-2:
—
—
—
—
—
0000
—
—
—
—
—
0401
CLKDIV
0000
31:16
RED
GREEN
0000
15:0
BLUE
ALPHA
0000
31:16
—
—
—
—
RESX
0000
15:0
—
—
—
—
RESY
0000
31:16
—
—
—
—
FPORCHX
0000
15:0
—
—
—
—
FPORCHY
0000
31:16
—
—
—
—
BLANKINGX
0000
15:0
—
—
—
—
BLANKINGY
0000
GLCD
A01C
BPORCH
31:16
—
—
—
—
BPORCHX
0000
15:0
—
—
—
—
BPORCHY
0000
GLCD
CURSOR
31:16
—
—
—
—
CURSORX
0000
15:0
—
—
—
—
CURSORY
0000
DISA
BIFIL
FORCE
ALPHA
MUL
ALPHA
A00C GLCDRES
GLCD
A014
FPORCH
A018
A020
A030
A034
GLCD
BLANKING
2015-2021 Microchip Technology Inc.
GLCD
L0MODE
31:16 LAYEREN
GLCD
L0START
31:16
—
—
—
—
STARTX
0000
15:0
—
—
—
—
STARTY
0000
31:16
—
—
—
—
SIZEX
0000
15:0
—
—
—
—
SIZEY
0000
GLCD
A038
L0SIZE
15:0
—
DESTBLEND
—
—
—
SRCBLEND
ALPHA
—
GLCD
L0BADDR
31:16
BASEADDR
15:0
BASEADDR
GLCD
A040
L0STRIDE
31:16
A03C
A044
A050
GLCD
L0RES
GLCD
L1MODE
Legend:
Note 1:
—
—
—
—
—
—
—
15:0
—
—
—
—
—
0000
COLORMODE
0000
0000
0000
—
—
—
—
—
—
STRIDE
—
0000
0000
31:16
—
—
—
—
RESX
0000
15:0
—
—
—
—
RESY
0000
DISA
BIFIL
FORCE
ALPHA
MUL
ALPHA
31:16 LAYEREN
15:0
DESTBLEND
—
—
—
SRCBLEND
—
0000
ALPHA
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For the PIXELxy bits, x = 0-31 and y = 0-31 (i.e., GLCDCURDATA0 contains PIXEL00 through PIXEL07 with PIXEL00 in the most significant nibble).
COLORMODE
0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 596
36.1
GLCD
L1START
All Resets
Register
Name
A054
GRAPHICS LCD CONTROLLER REGISTER MAP (CONTINUED)
Bit Range
Virtual Address
(BF8E_#)
2015-2021 Microchip Technology Inc.
TABLE 36-2:
Bit 31/15
31:16
—
—
—
—
STARTX
0000
15:0
—
—
—
—
STARTY
0000
GLCD
A058
L1SIZE
31:16
—
—
—
—
SIZEX
0000
15:0
—
—
—
—
SIZEY
0000
GLCD
A05C
L1BADDR
31:16
BASEADDR
15:0
BASEADDR
GLCD
A060
L1STRIDE
31:16
GLCD
A064
L1RES
31:16
—
—
—
—
RESX
15:0
—
—
—
—
RESY
DISA
BIFIL
FORCE
ALPHA
MUL
ALPHA
GLCD
L2MODE
—
—
—
—
—
—
15:0
Bit 24/8
—
Bit 23/7
—
Bit 22/6
Bit 21/5
Bit 20/4
Bit 19/3 Bit 118/2
Bit 17/1
Bit 16/0
0000
0000
—
—
—
—
—
—
—
STRIDE
31:16 LAYEREN
15:0
—
DESTBLEND
—
—
0000
—
SRCBLEND
0000
0000
0000
ALPHA
—
0000
—
—
—
COLORMODE
0000
GLCD
A074
L2START
31:16
—
—
—
—
STARTX
0000
15:0
—
—
—
—
STARTY
0000
GLCD
A078
L2SIZE
31:16
—
—
—
—
SIZEX
0000
15:0
—
—
—
—
SIZEY
0000
GLCD
A07C
L2BADDR
31:16
BASEADDR
15:0
BASEADDR
GLCD
A080
L2STRIDE
31:16
—
—
—
—
—
—
—
15:0
—
—
0000
0000
—
—
—
—
—
—
—
STRIDE
0000
0000
31:16
—
—
—
—
RESX
15:0
—
—
—
—
RESY
31:16 IRQCON
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
LROW
—
VSYNC
HSYNC
DE
ACTIVE
0000
A400
31:16
GLCDCLUTx
through
('x' = 0-255)
15:0
A7FC
—
—
—
—
—
—
—
—
A084 GLCDL2RES
A0F8 GLCDINT
A0FC GLCDSTAT
DS60001361J-page 597
A800 GLCD
through CURDATAx
A9FC (‘x’ = 0-127)
31:16
AA00 GLCD
through CURLUTx
AA40 (‘x’ = 0-15)
31:16
Legend:
Note 1:
15:0
—
0000
HSYNCINT VSYNCINT 0001
0000
BLUE
0000
PIXELxy(1)
PIXELxy(1)
PIXELxy(1)
PIXELxy(1)
0000
(1)
(1)
(1)
(1)
0000
PIXELxy
—
0000
—
RED
GREEN
15:0
0000
—
—
PIXELxy
—
—
GREEN
—
—
PIXELxy
—
PIXELxy
RED
0000
BLUE
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
For the PIXELxy bits, x = 0-31 and y = 0-31 (i.e., GLCDCURDATA0 contains PIXEL00 through PIXEL07 with PIXEL00 in the most significant nibble).
PIC32MZ Graphics (DA) Family
A070
—
Bit 30/14 Bit 29/13 Bit 28/12 Bit 27/11 Bit 26/10 Bit 25/9
PIC32MZ Graphics (DA) Family
REGISTER 36-1:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
GLCDMODE: GRAPHICS LCD CONTROLLER MODE REGISTER
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
U-0
LCDEN
CURSOR
EN
R/W-0
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
—
VSYNC
POL
HSYNC
POL
DEPOL
—
DITHER
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
VSYNC
CYC
PCLKPOL
—
PGRAMP
EN
FORCE
BLANK
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
FORMAT
CLK
—
R/W-0
Bit
28/20/12/4
—
—
—
—
—
YUV
OUTPUT
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
RGBSEQ
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
LCDEN: LCD Controller Module Enable bit
1 = LCD Controller module is enabled
0 = LCD Controller module is not enabled
bit 30
CURSOREN: Programmable Cursor Enable bit
1 = Programmable cursor is enabled
0 = Programmable cursor is enabled
bit 29
Unimplemented: Read as ‘0’
bit 28
VSYNCPOL: Vertical Sync Polarity bit
1 = VSYNC polarity is negative
0 = VSYNC polarity is positive
bit 27
HSYNCPOL: Horizontal Sync Polarity bit
1 = HSYNC polarity is negative
0 = HSYNC polarity is positive
bit 26
DEPOL: DE Polarity bit
1 = DE polarity is negative
0 = DE polarity is positive
bit 25
Unimplemented: Read as ‘0’
bit 24
DITHER: Dithering Enable bit
1 = Dithering is enabled
0 = Dithering is not enabled
bit 23
VSYNCCYC: Vertical Sync for Single Cycle Per Line Enable bit
1 = VSYNC for a single cycle per line is enabled
0 = VSYNC for a single cycle per line is not enabled
bit 22
PCLKPOL: Pixel Clock Out Polarity bit
1 = Pixel clock out polarity is negative
0 = Pixel clock out polarity is positive
bit 21
Unimplemented: Read as ‘0’
bit 20
PGRAMPEN: Palette Gamma Ramp Enable bit
1 = Palette gamma ramp is enabled
0 = Palette gamma ramp is not enabled
DS60001361J-page 598
x = Bit is unknown
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 36-1:
bit 19
GLCDMODE: GRAPHICS LCD CONTROLLER MODE REGISTER (CONTINUED)
FORCEBLANK: Force Output to Blank bit
1 = Forces output to blank
0 = No effect
bit 18-10 Unimplemented: Read as ‘0’
bit 9
YUVOUTPUT: YUV Output Enable bit
1 = YUV is enabled
0 = RGB is enabled
bit 8
FORMATCLK: Formatting Clock Divide Enable bit
1 = Formatting clock is not divided
0 = Formatting clock is divided
bit 7-5
RGBSEQ: RGB Sequential Modes bit
111 = BT.656
110 = YUYV
101 = Reserved
100 = Reserved
011 = Reserved
010 = Reserved
001 = Reserved
000 = Parallel RGB (RGB888, RGB666, RGB332)
bit 4-0
Unimplemented: Read as ‘0’
2015-2021 Microchip Technology Inc.
DS60001361J-page 599
PIC32MZ Graphics (DA) Family
REGISTER 36-2:
Bit
Range
31:24
23:16
15:8
7:0
GLCDCLKCON: GRAPHICS LCD CONTROLLER CLOCK CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
U-0
U-0
—
—
Legend:
R = Readable bit
-n = Value at POR
LPREFETCH
R/W-0
R/W-0
CLKDIV
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13-8 LPREFETCH: Lines Prefetch bits
These bits represent the number of lines to be prefetched before starting the frame (through DMA). The
maximum value is 2LPREFETCH = 32.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
CLKDIV: Clock Divider bits
111111 = Reserved
111110 = Reserved
•
•
•
011111 = Divided by 31
011110 = Divided by 30
011101 = Divided by 29
•
•
•
000011 = Divided by 3
000010 = Divided by 2
000001 = Divided by 1
000000 = Divided by 0
Note:
DS60001361J-page 600
If the value of CLKDIV is even, PCLK = (REFCLKO5/CLKDIV) with a duty cycle of 50%.
If the value of CLKDIV is odd, PCLK = (REFCLKO5/CLKDIV) with a duty cycle of 60% to
40%.
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 36-3:
Bit
Range
31:24
23:16
15:8
7:0
GLCDBGCOLOR: GRAPHICS LCD CONTROLLER BACKGROUND COLOR
REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RED
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GREEN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BLUE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALPHA
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 RED: Color Red as Background bits
These bits specify that the color red is to be used as the background color.
bit 23-16 GREEN: Color Green as Background bits
These bits specify that the color green is to be used as the background color.
bit 15-8 BLUE: Color Blue as Background bits
These bits specify that the color blue is to be used as the background color.
bit 7-0
ALPHA: Color Alpha as Background bits
These bits specify that the color alpha is to be used as the background color.
Note:
If all of the bits in this register are set (RED, GREEN, BLUE and ALPHA), RGBA color is used as the
background.
REGISTER 36-4:
Bit
Range
31:24
23:16
15:8
7:0
GLCDRES: GRAPHICS LCD CONTROLLER RESOLUTION REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
RESX
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RESX
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
R/W-0
RESY
R/W-0
R/W-0
R/W-0
RESY
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-16 RESX: X Dimension Pixel Resolution bits
These bits specify the pixel resolution for the X dimension.
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0 RESY: Y Dimension Pixel Resolution bits
These bits specify the pixel resolution for the Y dimension.
2015-2021 Microchip Technology Inc.
DS60001361J-page 601
PIC32MZ Graphics (DA) Family
REGISTER 36-5:
Bit
Range
31:24
23:16
15:8
7:0
GLCDFPORCH: GRAPHICS LCD CONTROLLER FRONT PORCH REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FPORCHX
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FPORCHX
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FPORCHY
R/W-0
R/W-0
R/W-0
FPORCHY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-16 FPORCHX: X Dimension Front Porch Lines bits
These bits specify the front porch X dimension lines.
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0
FPORCHY: Y Dimension Front Porch Pixel Clocks bits
These bits specify the front porch Y dimension pixel clocks.
REGISTER 36-6:
Bit
Range
31:24
23:16
15:8
7:0
GLCDBLANKING: GRAPHICS LCD CONTROLLER BLANKING REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BLANKINGX
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BLANKINGX
R/W-0
BLANKINGY
R/W-0
R/W-0
R/W-0
BLANKINGY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-16 BLANKINGX: X Dimension Blanking Period bits
These bits specify the HSYNC pulse length for the X dimension blanking period.
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0
BLANKINGY: Y Dimension Blanking Period bits
These bits specify the VSYNC lines for the Y dimension blanking period.
DS60001361J-page 602
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 36-7:
Bit
Range
31:24
23:16
15:8
7:0
GLCDBPORCH: GRAPHICS LCD CONTROLLER BACK PORCH REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BPORCHX
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BPORCHX
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BPORCHY
R/W-0
R/W-0
R/W-0
BPORCHY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-16 BPORCHX: X Dimension Back Porch Lines bits
These bits specify the front porch X dimension lines.
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0
BPORCHY: Y Dimension Back Porch Pixel Clocks bits
These bits specify the front porch Y dimension pixel clocks.
REGISTER 36-8:
Bit
Range
31:24
23:16
15:8
7:0
GLCDCURSOR: GRAPHICS LCD CONTROLLER CURSOR REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CURSORX
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CURSORX
R/W-0
CURSORY
R/W-0
R/W-0
R/W-0
CURSORY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-16 CURSORX: Cursor X Dimension Position bits
These bits specify the X dimension position of the cursor
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0
CURSORY: Cursor Y Dimension Position bits
These bits specify the Y dimension position of the cursor
2015-2021 Microchip Technology Inc.
DS60001361J-page 603
PIC32MZ Graphics (DA) Family
REGISTER 36-9:
Bit
Range
31:24
23:16
15:8
7:0
GLCDLxMODE: GRAPHICS LCD CONTROLLER LAYER ‘x’ MODE REGISTER
(‘x’ = 0-2)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
LAYEREN
DISABIFIL
FORCE
ALPHA
MUL
ALPHA
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALPHA
DESTBLEND
SRCBLEND
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
COLORMODE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
LAYEREN: Layer Enable bit
1 = Layer is enabled
0 = Layer is not enabled
bit 30
DISABIFIL: Disable Bilinear Filtering bit
1 = Bilinear filtering is enabled
0 = Bilinear filtering is not enabled
bit 29
FORCEALPHA: Force Alpha with Global Alpha bit
1 = Force alpha with global alpha is enabled
0 = Force alpha with global alpha is not enabled
bit 28
MULALPHA: Premultiply Image Alpha bit
1 = Premultiply image alpha is enabled
0 = Premultiply image alpha is not enabled
bit 27-24 Unimplemented: Read as ‘0’
bit 23-16 ALPHA: Layer Alpha bits
These bits contain the Layer Alpha value ranging from 0 to 0xFF.
bit 15-12 DESTBLEND: Destinary Blending Function bits
1111 = Reserved
1110 = Reserved
1101 = Blend inverted destination
1100 = Reserved
1011 = Reserved
1010 = Blend alpha destination
1001 = Reserved
1000 = Reserved
0111 = Blend inverted source and inverted global
0110 = Blend inverted global
0101 = Blend inverted source
0100 = Blend alpha source and alpha global
0011 = Blend alpha global
0010 = Blend alpha source
0001 = Blend white
0000 = Blend black
DS60001361J-page 604
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 36-9:
bit 11-8
bit 7-4
bit 3-0
GLCDLxMODE: GRAPHICS LCD CONTROLLER LAYER ‘x’ MODE REGISTER
(‘x’ = 0-2) (CONTINUED)
SRCBLEND: Source Blending Function bits
1111 = Reserved
1110 = Reserved
1101 = Blend inverted destination
1100 = Reserved
1011 = Reserved
1010 = Blend alpha destination
1001 = Reserved
1000 = Reserved
0111 = Blend inverted source and inverted global
0110 = Blend inverted global
0101 = Blend inverted source
0100 = Blend alpha source and alpha global
0011 = Blend alpha global
0010 = Blend alpha source
0001 = Blend white
0000 = Blend black
Unimplemented: Read as ‘0’
COLORMODE: Color Mode bits
1111 = Reserved
1110 = Reserved
1101 = Reserved
1100 = Reserved
1011 = RGB888 color format
1010 = YUYV color format
1001 = L4 gray scale/palette format
1000 = L1 gray scale/palette format
0111 = L8 gray scale/palette format
0110 = 32-bit ARGB8888 color format
0101 = 16-bit RGB565 color format
0100 = 8-bit RGB332 color format
0011 = Reserved
0010 = 32-bit RGBA8888 color format
0001 = 16-bit RGBA5551 color format
0000 = 8-bit color palette look-up table (LUT8)
2015-2021 Microchip Technology Inc.
DS60001361J-page 605
PIC32MZ Graphics (DA) Family
REGISTER 36-10: GLCDLxSTART: GRAPHICS LCD CONTROLLER LAYER ‘x’ START REGISTER
(‘x’ = 0-2)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STARTX
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STARTX
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STARTY
R/W-0
R/W-0
R/W-0
STARTY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-16 STARTX: Layer Start X Dimension bits
These bits specify the pixel offset of the starting X dimension of the layer.
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0
STARTY: Layer Start Y Dimension bits
These bits specify the pixel offset of the starting Y dimension of the layer.
REGISTER 36-11: GLCDLxSIZE: GRAPHICS LCD CONTROLLER LAYER ‘x’ SIZE REGISTER
(‘x’ = 0-2)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
SIZEX
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SIZEX
R/W-0
SIZEY
R/W-0
R/W-0
R/W-0
SIZEY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-16 SIZEX: Layer Size X Dimension bits
These bits specify the pixel size of the layer in the X dimension.
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0
SIZEY: Layer size Y Dimension bits
These bits specify the pixel size of the layer in the Y dimension.
DS60001361J-page 606
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 36-12: GLCDLxBADDR: GRAPHICS LCD CONTROLLER LAYER ‘x’ BASE ADDRESS
REGISTER (‘x’ = 0-2)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BASEADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BASEADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BASEADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BASEADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
BASEADDR: Base Address of the Framebuffer bits
These bits specify the base address of the framebuffer.
REGISTER 36-13: GLCDLxSTRIDE: GRAPHICS LCD CONTROLLER LAYER ‘x’ STRIDE REGISTER
(‘x’ = 0-2)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STRIDE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STRIDE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0
STRIDE: Layer Stride bits
These bits specify the distance from line to line in bytes.
2015-2021 Microchip Technology Inc.
DS60001361J-page 607
PIC32MZ Graphics (DA) Family
REGISTER 36-14: GLCDLxRES: GRAPHICS LCD CONTROLLER LAYER ‘x’ RESOLUTION
REGISTER (‘x’ = 0-2)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
RESX
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RESX
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RESY
R/W-0
R/W-0
R/W-0
RESY
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-16 RESX: X Dimension Layer Pixel Resolution bits
These bits specify the layer pixel resolution in the X dimension.
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0 RESY: Y Dimension Layer Pixel Resolution bits
These bits specify the layer pixel resolution in the Y dimension.
DS60001361J-page 608
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 36-15: GLCDINT: GRAPHICS LCD CONTROLLER INTERRUPT REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
IRQCON
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
HSYNCINT VSYNCINT
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
IRQCON: IRQ Triggering Control bit
1 = Edge triggering is enabled
0 = Level triggering is enabled
bit 30-2
Unimplemented: Read as ‘0’
bit 1
HYSNNCINT: HSYNC Interrupt Enable bit
1 = HSYNC interrupt is enabled
0 = HSYNC interrupt is not enabled
bit 0
VSYNCINT: VSYNC Interrupt Enable bit
1 = VSYNC interrupt is enabled
0 = VSYNC interrupt is not enabled
2015-2021 Microchip Technology Inc.
x = Bit is unknown
DS60001361J-page 609
PIC32MZ Graphics (DA) Family
REGISTER 36-16: GLCDSTAT: GRAPHICS LCD CONTROLLER STATUS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R-0
U-0
R-0
R-0
R-0
R-0
—
—
LROW
—
VSYNC
HSYNC
DE
ACTIVE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-6
Unimplemented: Read as ‘0’
bit 5
LROW: Last Row bit
1 = Last row is currently being displayed
0 = Last row is not currently being displayed
bit 4
Unimplemented: Read as ‘0’
bit 3
VSYNC: VSYNC Signal Level bit
This bit returns the VSYNC signal level.
Note: This bit is set 0 after VSYNC Interrupt.
bit 2
HSYNC: HSYNC Signal Level bit
This bit returns the HSYNC signal level.
Note: This bit is set to 0 after HSYNC interrupt.
bit 1
DE: DE Signal Level bit
This bit returns the DE signal level.
bit 0
ACTIVE: Active bit
1 = LCD Controller is not in active vertical blanking
0 = LCD Controller is in active vertical blanking
DS60001361J-page 610
x = Bit is unknown
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 36-17: GLCDCLUTx: GRAPHICS LCD CONTROLLER GLOBAL COLOR LOOKUP TABLE
REGISTER x (‘x’=0-255)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RED
GREEN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BLUE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 RED: Global Color Lookup Table Red Component bits
bit 15-8
GREEN: Global Color Lookup Table Green Component bits
bit 7-0
BLUE: Global Color Lookup Table Blue Component bits
2015-2021 Microchip Technology Inc.
DS60001361J-page 611
PIC32MZ Graphics (DA) Family
REGISTER 36-18: GLCDCURDATAx: GRAPHICS LCD CONTROLLER CURSOR DATA ‘n’
REGISTER (‘n’ = 0-127)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PIXELxy(1)
R/W-0
R/W-0
R/W-0
PIXELxy(1)
R/W-0
R/W-0
PIXELxy(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PIXELxy(1)
R/W-0
R/W-0
PIXELxy(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PIXELxy(1)
R/W-0
PIXELxy(1)
R/W-0
R/W-0
R/W-0
R/W-0
PIXELxy(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 PIXELxy: Pixel ‘xy’ Color Lookup bits(1)
bit 27-24 PIXELxy: Pixel ‘xy’ Color Lookup bits(1)
bit 23-20 PIXELxy: Pixel ‘xy’ Color Lookup bits(1)
bit 19-16 PIXELxy: Pixel ‘xy’ Color Lookup bits(1)
bit 15-12 PIXELxy: Pixel ‘xy’ Color Lookup bits(1)
bit 11-8
PIXELxy: Pixel ‘xy’ Color Lookup bits(1)
bit 7-4
PIXELxy: Pixel ‘xy’ Color Lookup bits(1)
bit 3-0
PIXELxy: Pixel ‘xy’ Color Lookup bits(1)
Note 1:
For the PIXELxy bits, x = 0-31 and y = 0-31 (i.e., GLCDCURDATA0 contains PIXEL00 through PIXEL07
with PIXEL00 in the most significant nibble).
DS60001361J-page 612
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 36-19: GLCDCURLUTx: GRAPHICS LCD CONTROLLER CURSOR LUT REGISTER ‘x’
(‘x’ = 0-15)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RED
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GREEN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BLUE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 RED: Cursor Lookup Table Red Component bit
bit 15-8
GREEN: Cursor Lookup Table Green Component bit
bit 7-0
BLUE: Cursor Lookup Table Blue Component bit
Note:
The bits in this register contain the 8-bit RGB color value (0-255).
2015-2021 Microchip Technology Inc.
DS60001361J-page 613
PIC32MZ Graphics (DA) Family
DS60001361J-page 614
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
37.0
Note:
2-D GRAPHICS PROCESSING
UNIT (GPU)
The following are key features of the 2-D Graphics Processing Unit:
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the documents listed in the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The 2-D Graphics Processing Unit manipulates and
alters the contents of the frame buffer in system RAM
or DDR2 memory to accelerate the rendering of images
for eventual pixel display. Hardware acceleration is
brought to numerous 2-D applications, such as graphics user interfaces (menus, objects, and so on).
The 2-D GPU also provides accelerated on-the-fly
rendering of vertical and horizontal lines, rectangles,
copying of a rectangular area between different
locations in memory. Once initiated, the hardware will
perform the rendering through DMA, which makes the
CPU available for other tasks.
•
•
•
•
•
•
•
•
•
64-bit bus access to memory (higher throughput)
Global clock gating (low power)
Command buffers
Fixed Functions:
- Line draw
- Rectangle fill
- Rectangle clear
- Bit blit (stretch/shrink/filter)
- Programmable raster operation (ROP2), with
full alpha blending and transparency
Source data formats:
- RGBA8888, RGB565, RGB5551, 8-bit Index
Destination data formats:
- RGBA8888, RGB565, RGB5551
Dithering (18-bit)
Orientation in 90-degree steps
Clipping
Note 1: For RGB source formats, their related
swizzle formats, such as ARGB and
RGBA are supported.
2: The GPU is enabled and ready out of
POR. However, the GPU can be soft
Reset at run-time using the GPURESET
bit (CFGCON2). Make sure that the
GPUMD bit is set to '0' and wait 10 µs
before toggling the GPURESET bit to
achieve proper soft Reset.
A block diagram showing the interface for the 2-D
Graphics Processing Unit is provided in Figure 37-1.
Note:
For this peripheral, no hardware interface
is documented. Use the Nano-2D Library,
which is available in MPLAB Harmony, to
manage this module.
FIGURE 37-1:
2-D GRAPHICS PROCESSING UNIT BLOCK DIAGRAM
System Bus
64-bit System Bus
Graphics Processor
GPU Core
Host Interface
Memory Controller
Graphics
Pipeline
Front End
2015-2021 Microchip Technology Inc.
2-D Pipeline
2-D Drawing and Scaling Engine
Pixel
Engine
DS60001361J-page 613
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 614
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
38.0
DDR2 SDRAM CONTROLLER
Note:
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 55. “DDR SDRAM
Controller” (DS60001321‘), which is
available from the Documentation >
Reference Manual section of the Microchip PIC32 web site (www.microchip.com/
pic32).
FIGURE 38-1:
The DDR2 SDRAM Controller implements the controls
for an external memory bus interface using the Dual
Data Rate version 2 (DDR2) protocol and electrical
interface that adheres to the JEDEC Standard
JESD79-2F (Nov. 2009).
The component consists of a DDR2 SDRAM Controller
Core with configurable options and a DDR2 Physical
Interface.
A block diagram showing how these components
interface is provided in Figure 38-1.
DDR2 SDRAM CONTROLLER BLOCK DIAGRAM
DDR2 SDRAM Controller
MFMPLL
LDO or PMIC
SYSCLK
VDDR1V8
DDR2
Control
Registers
DDR2-PHY
Control
Registers
VTT
DDR2
Memory(1)
DDRVREF
DDRCKE
DDRCK
Target Manager
DDRCK
DDRCS0
Target 0
(CPU)
DDRRAS
System Bus
DDR2
Data
Controller
Target 1
Target 2
(DMA and other
initators)
Arbiter
and
FIFOs
DDRCAS
PHY
DDRWE
DDRA
DDRBA
DDRUDQS
DDRUDQS
DDRLDQS
Target 3
Target 4
(GLCD and GPU)
DDRLDQS
DDRDQ
DDRUDM
DDRLDM
DDRODT
Note
1:
DDR2 memory is internal in 169-pin LFBGA and 176-pin LQFP packages and is external in 288-pin LFBGA packages.
2015-2021 Microchip Technology Inc.
DS60001361J-page 615
Control Registers
DDR SDRAM CONTROLLER REGISTER SUMMARY
2015-2021 Microchip Technology Inc.
8000
DDR
TSEL
8004
DDR
MINLIM
8008
DDR
RQPER
800C
DDR
MINCMD
8010
DDR
MEMCON
8014
DDR
MEMCFG0
8018
DDR
MEMCFG1
801C
DDR
MEMCFG2
8020
DDR
MEMCFG3
8024
DDR
MEMCFG4
8028
DDR
REFCFG
802C
DDR
PWRCFG
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AP
CHRGEN
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
SLFREFDLY
31:16
15:0
RMWDLY
R2RCSDLY
DDR
DLYCFG1
31:16
8038
DDR
DLYCFG2
803C
DDR
DLYCFG3
8040
DDR
ODTCFG
8044
DDR
XFERCFG
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
—
—
BNKADDR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MAXREFS
19/3
—
—
TSEL
—
—
—
—
RQPER
—
—
MINCMD
—
—
—
—
18/2
17/1
16/0
—
—
—
—
MINLIMIT
—
—
—
—
—
—
—
—
—
—
—
INITDN
—
STINIT
CSADDR
—
—
—
—
—
—
RWADDRMSK
—
—
—
—
CLADDRHMSK
—
—
—
—
CLADDRLMSK
—
—
—
—
CSADDRMSK
—
—
—
—
—
—
BIGENDIAN
—
SLFREF
EXDLY8
NXTDAT
AVDLY4
RBENDDLY
W2PCHRGDLY
—
—
—
—
—
ODTWDLY
—
—
—
—
—
—
—
—
RWADDR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
REFDLY
—
PCHRG
PWRDN
—
—
BNKADDRMSK
SLFREFDLY
ASLF
REFEN
PWRDNDLY
R2WDLY>3:0>
R2RDLY
W2R
W2R
W2PCHRG
CSDLY4
DLY4>
DLY4
SLFREFEXDLY
PCHRG2RASDLY
R2PCHRGDLY
—
—
—
—
RAS2RASSBNKDLY
—
—
—
—
ODTRDLY
—
—
—
—
—
—
W2WCSDLY
W2RCSDLY
SLFREFMINDLY
—
—
MAXBURST
—
—
—
APWR
—
DNEN
W2WDLY
W2RDLY
PWRDNMINDLY
PWRDNEXDLY
—
—
—
—
—
—
RAS2CASDLY
—
—
—
—
—
ODTWLEN
—
—
NXTDATAVDLY
RAS2RASDLY
PCHRGALLDLY
FAWTDLY
RAS2PCHRGDLY
—
ODTRLEN
ODTCSEN
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
REFCNT
DDR
8030
DLYCFG0
8034
CLHADDR
20/4
All Resets
Bit Range
Bits
Register
Name
Virtual Address
(BF8E_#)
TABLE 38-1:
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
RDATENDLY
0000
NXTDATRQDLY
0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 616
38.1
8048
DDR
CMDISSUE
804C
DDR
ODTENCFG
8050
DDR
MEMWIDTH
8080
8088
808C
8090
8094
8098
DS60001361J-page 617
809C
80A0
80A4
DDR
CMD10
DDR
CMD11
DDR
CMD12
DDR
CMD13
DDR
CMD14
DDR
CMD15
DDR
CMD16
DDR
CMD17
DDR
CMD18
DDR
CMD19
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
31:16
15:0
31:16
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VALID
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
15:0
MDALCMD
CSCMD2
31:16
15:0
CSCMD2
CSCMD2
CSCMD2
CSCMD2
CSCMD2
CSCMD2
CSCMD2
WEN
CMD1
CASCMD1 RASCMD1
CLKEN
CMD2
WEN
CMD1
CLKEN
CMD2
WEN
CMD1
CLKEN
CMD2
WEN
CMD1
CLKEN
CMD2
WEN
CMD1
CLKEN
CMD2
WEN
CMD1
CSCMD2
CLKEN
CMD2
WEN
CMD1
CASCMD1 RASCMD1
CSCMD2
CLKEN
CMD2
WEN
CMD1
CASCMD1 RASCMD1
CASCMD2 RASCMD2
CASCMD2 RASCMD2
CASCMD1 RASCMD1
CASCMD2 RASCMD2
CASCMD1 RASCMD1
CASCMD2 RASCMD2
WEN
CMD2
CASCMD1 RASCMD1
CASCMD2 RASCMD2
CASCMD1 RASCMD1
CASCMD2 RASCMD2
CSCMD2
WEN
CMD2
CASCMD2 RASCMD2
CSCMD1
0000
0000
CLKEN
CMD1
CSCMD2
0000
0000
CLKEN
CMD1
CSCMD2
0000
0000
CLKEN
CMD1
CSCMD
0000
0000
CLKEN
CMD1
CSCMD2
0000
0000
CLKEN
CMD1
CSCMD2
0000
0000
CLKEN
CMD1
CSCMD1
0000
0000
CLKEN
CMD1
CSCMD1
WEN
CMD2
0000
0000
CSCMD2
CSCMD1
0000
0000
CLKEN
CMD1
CSCMD1
WEN
CMD2
—
CSCMD2
CSCMD1
WEN
CMD2
CASCMD1 RASCMD1
CASCMD2 RASCMD2
—
CLKEN
CMD1
CSCMD1
WEN
CMD2
MDALCMD
CASCMD2 RASCMD2
16/0
CSCMD2
CSCMD1
WEN
CMD2
MDALCMD
31:16
15:0
CLKEN
CMD2
—
CSCMD1
WEN
CMD2
MDALCMD
31:16
15:0
CASCMD1 RASCMD1
MDALCMD
31:16
15:0
WEN
CMD1
MDALCMD
31:16
15:0
CLKEN
CMD2
CASCMD2 RASCMD2
17/1
—
—
—
0000
NUMHOSTCMDS
0000
—
—
ODTWEN 0000
—
—
ODTREN 0000
—
—
—
0000
CSCMD1
WEN
CMD2
MDALCMD
31:16
15:0
CASCMD1 RASCMD1
MDALCMD
31:16
15:0
WEN
CMD1
MDALCMD
31:16
15:0
CLKEN
CMD2
MDALCMD
31:16
15:0
WEN
CMD2
—
—
—
HALF
RATE
18/2
All Resets
Bit Range
31/15
CSCMD2
0000
0000
CLKEN
CMD1
0000
PIC32MZ Graphics (DA) Family
8084
DDR SDRAM CONTROLLER REGISTER SUMMARY (CONTINUED)
Bits
Register
Name
Virtual Address
(BF8E_#)
2015-2021 Microchip Technology Inc.
TABLE 38-1:
80AC
80B0
80B4
80B8
80BC
DDR
CMD110
DDR
CMD111
DDR
CMD112
DDR
CMD113
DDR
CMD114
DDR
CMD115
2015-2021 Microchip Technology Inc.
80C0
DDR
CMD20
80C4
DDR
CMD21
80C8
DDR
CMD22
80CC
DDR
CMD23
80D0
DDR
CMD24
80D4
DDR
CMD25
80D8
DDR
CMD26
80DC
DDR
CMD27
80E0
DDR
CMD28
80E4
DDR
CMD29
31/15
30/14
29/13
31:16
27/11
26/10
25/9
24/8
CSCMD2
31:16
CLKEN
CMD2
WEN
CMD1
15:0
CSCMD2
31:16
WEN
CMD1
15:0
CSCMD2
31:16
WEN
CMD1
15:0
CSCMD2
31:16
WEN
CMD1
15:0
CSCMD2
31:16
CLKEN
CMD2
WEN
CMD1
15:0
CSCMD2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WAIT
—
WAIT
—
WAIT
—
WAIT
—
WAIT
—
WAIT
—
WAIT
—
WAIT
—
WAIT
—
WAIT
WEN
CMD1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CSCMD
CASCMD2 RASCMD2
CASCMD1 RASCMD1
—
—
—
CSCMD2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MDADDRHCMD
—
MDADDRHCMD
—
MDADDRHCMD
—
MDADDRHCMD
—
MDADDRHCMD
—
MDADDRHCMD
—
MDADDRHCMD
—
MDADDRHCMD
—
MDADDRHCMD
—
MDADDRHCMD
WAIT
WAIT
WAIT
WAIT
WAIT
WAIT
WAIT
WAIT
WAIT
0000
0000
CLKEN
CMD1
WAIT
0000
0000
CLKEN
CMD1
CSCMD1
0000
0000
CLKEN
CMD1
CSCMD1
WEN
CMD2
0000
0000
CLKEN
CMD1
CSCMD2
CASCMD2 RASCMD2
0000
0000
CLKEN
CMD1
CSCMD2
CASCMD2 RASCMD2
CASCMD1 RASCMD1
0000
CLKEN
CMD1
CSCMD1
WEN
CMD2
16/0
CSCMD2
CASCMD2 RASCMD2
CASCMD1 RASCMD1
—
—
BNKADDRCMD
—
—
—
BNKADDRCMD
—
—
—
BNKADDRCMD
—
—
—
BNKADDRCMD
—
—
—
BNKADDRCMD
—
—
—
BNKADDRCMD
—
—
—
BNKADDRCMD
—
—
—
BNKADDRCMD
—
—
—
BNKADDRCMD
—
—
—
BNKADDRCMD
17/1
CSCMD1
WEN
CMD2
—
18/2
CSCMD2
CASCMD2 RASCMD2
CASCMD1 RASCMD1
MDALCMD
CLKEN
CMD2
—
19/3
CSCMD1
WEN
CMD2
MDALCMD
20/4
CASCMD2 RASCMD2
CASCMD1 RASCMD1
MDALCMD
CLKEN
CMD2
21/5
CSCMD1
WEN
CMD2
MDALCMD
CLKEN
CMD2
22/6
CASCMD1 RASCMD1
MDALCMD
CLKEN
CMD2
23/7
WEN
CMD2
MDALCMD
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
28/12
All Resets
Bit Range
Bits
Register
Name
Virtual Address
(BF8E_#)
80A8
DDR SDRAM CONTROLLER REGISTER SUMMARY (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 618
TABLE 38-1:
DDR
CMD210
80EC
DDR
CMD211
80F0
DDR
CMD212
80F4
DDR
CMD213
80F8
DDR
CMD214
80FC
DDR
CMD215
9100
DDR
SCLSTART
DDR
910C
SCLLAT
DDR
9118
SCLCFG0
9120
9124
DDR
SCLCFG1
DDR
PHYPADCON
DDR
PHYDLLR
30/14
29/13
28/12
27/11
26/10
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
WAIT
—
WAIT
—
WAIT
—
WAIT
—
WAIT
—
WAIT
SCL
PHCAL
SCL
START
—
DS60001361J-page 619
DDR
ADLLBYP
DDR
916C
SCLCFG2
9188 DDR
PHYSCLADR
24/8
—
—
BNKADDRCMD
—
—
—
BNKADDRCMD
—
—
—
BNKADDRCMD
—
—
—
BNKADDRCMD
—
—
—
BNKADDRCMD
—
—
—
BNKADDRCMD
SCLEN
—
—
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
31:16
15:0
31:16
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ODTCSW
—
—
—
15:0
—
—
—
31:16
—
—
—
—
—
—
DBL
REFDLY
RCVREN
15:0
—
31:16
15:0
31:16
DDR
9128
PHYDLLCTRL 15:0
9140
31:16
DDR
PHYCLKDLY
15:0
915C
25/9
PREAMBDLY
HALF
WR
RATE
CMDDLY
—
DLYSTVAL
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
15:0
31:16
15:0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
SCLBANKADR
WCASLAT
—
—
—
—
DIS
RECALIB
RECALIBCNT
—
—
—
—
—
—
—
—
—
—
NOEXT
DLL
—
—
—
—
EOEN
CLKCYC
—
—
—
—
DDRCLKDLY
—
—
RCASLAT
—
—
—
—
20/4
19/3
—
MDADDRHCMD
—
MDADDRHCMD
—
MDADDRHCMD
—
MDADDRHCMD
—
MDADDRHCMD
—
MDADDRHCMD
—
—
—
—
—
—
—
—
—
—
—
—
—
DRVSTRPFET
ODTPUCAL
ODTPDCAL
ADDC
DRVSEL
18/2
17/1
16/0
WAIT
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
WAIT
WAIT
WAIT
WAIT
WAIT
—
—
—
—
SCL
UBPASS
SCL
LBPASS
0000
—
BURST8
—
0000
0000
0000
0000
0000
CAPCLKDLY
—
—
—
DDR2
—
—
—
—
DRVSTRNFET
DAT
ODTEN
DRVSEL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANL
DLLBYP
—
—
—
—
—
—
—
—
—
—
—
—
SCL
UBPASS
—
—
—
—
—
SCLROWADR
—
—
—
—
—
—
—
SCLCOLADR
0000
SCLSEN 0000
0000
ODTSEL 0000
RECALIBCNT
—
—
All Resets
Bit Range
31/15
0000
—
—
—
—
DDRDLLTRIM
—
—
SCL
—
LBPASS
—
—
—
—
—
—
—
—
—
CLKDLYDELTA
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
—
—
—
—
—
SCLLANSEL
0000
0000
0000
0000
0000
0000
PIC32MZ Graphics (DA) Family
80E8
911C
DDR SDRAM CONTROLLER REGISTER SUMMARY (CONTINUED)
Bits
Register
Name
Virtual Address
(BF8E_#)
2015-2021 Microchip Technology Inc.
TABLE 38-1:
PIC32MZ Graphics (DA) Family
REGISTER 38-1:
Bit
Range
31:24
23:16
15:8
7:0
DDRTSEL: DDR TARGET SELECT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
TSEL
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0 TSEL: Target Select bits
These bits select the target to program arbitration parameters. This field must be set before an arbitration
parameter is programmed for a target. The value in this field represents the target number (0-4) multiplied
by the field size of the arbitration parameter.
DS60001361J-page 620
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 38-2:
Bit
Range
31:24
23:16
15:8
7:0
DDRMINLIM: DDR MINIMUM BURST LIMIT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
MINLIMIT
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-5 Unimplemented: Read as ‘0’
bit 4-0 MINLIMIT: Minimum Burst Limit bits
These bits determine the minimum number of DDR bursts (two cycles per burst) that a target must have
uninterrupted access to without interference from another target.
Note:
The TSEL bits (DDRTSEL) must be programmed with the target number multiplied by the size of
the MINLIMIT field (5) before this register is used to program the minimum burst limit for that target.
2015-2021 Microchip Technology Inc.
DS60001361J-page 621
PIC32MZ Graphics (DA) Family
REGISTER 38-3:
Bit
Range
31:24
23:16
15:8
7:0
DDRRQPER: DDR REQUEST PERIOD REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RQPER
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0 RQPER: Request Period bits
These bits in conjunction with the MINCMD bits (DDRMINCMD), determine the percentage of
total bandwidth that is allocated to the target. If the number of DDR bursts specified by MINCMD are
not serviced for the target when it has been requesting access for (RQPER * 4) number of clocks, the
target's requests are treated with high priority until this condition becomes satisfied.
Note:
The TSEL bits (DDRTSEL) must be programmed with the target number multiplied by the size of
the MINLIMIT field (5) before this register is used to program the minimum burst limit for that target.
DS60001361J-page 622
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 38-4:
Bit
Range
31:24
23:16
15:8
7:0
DDRMINCMD: DDR MINIMUM COMMAND REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
MINCMD
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0 MINCMD: Minimum Command bits
These bits in conjunction with the RQPER bits (DDRRQPER) determine the percentage of total
bandwidth that is allocated to the target. If the number of DDR bursts specified by MINCMD are not
serviced for the target when it has been requesting access for (RQPER * 4) number of clocks, then
the target's requests are treated with high priority until this condition becomes satisfied.
Note:
The TSEL bits (DDRTSEL) must be programmed with the target number multiplied by the size of
the MINLIMIT field (5) before this register is used to program the minimum burst limit for that target.
2015-2021 Microchip Technology Inc.
DS60001361J-page 623
PIC32MZ Graphics (DA) Family
REGISTER 38-5:
Bit
Range
31:24
23:16
15:8
7:0
DDRMEMCON: DDR MEMORY CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
INITDN
STINIT
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-2 Unimplemented: Read as ‘0’
bit 1
INITDN: Memory Initialize Done bit
Set by software after memory initialization is completed to enable controller for regular operation.
bit 0
1 = All commands have been issued; the controller is enabled for regular operation
0 = Controller not enabled for regular operation
STINIT: Memory Initialize Start bit
Set by software after the memory initialization commands are loaded into the DDRCMD registers to start
memory initialization.
1 = Start memory initialization
0 = Do not start memory initialization
DS60001361J-page 624
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 38-6:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
DDRMEMCFG0: DDR MEMORY CONFIGURATION REGISTER 0
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
APCHRGEN
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
Legend:
R = Readable bit
-n = Value at POR
bit 31
bit 30
bit 29
bit 28-24
bit 23-21
bit 20-16
bit 15-13
bit 12-8
bit 7-5
bit 4-0
W = Writable bit
‘1’ = Bit is set
CLHADDR
R/W-0
R/W-0
R/W-0
CSADDR
R/W-0
R/W-0
R/W-0
BNKADDR
R/W-0
R/W-0
R/W-0
RWADDR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
APCHRGEN: Automatic Precharge Enable bit
When set, this bit issues an auto-precharge command to close the bank at the end of every user
command. If the command accesses more than one bank before completing, all banks accessed are autoprecharged.
1 = Issue an auto-precharged command
0 = Do not issue an auto-precharged command
Unimplemented: Read as ‘0’
CLHADDR: Column Address Shift bits
These bits specify how many bits the controller address must be right-shifted to put the high part of the column address to the immediate left of the low part of the column address. Used in conjunction with CLADDRHMSK (DDRMEMCFG2) and CLADDRLMASK (DDRMEMCFG3).
Unimplemented: Read as ‘0’
CSADDR: Chip Select Shift bits
These bits specify which bits of user address space are used to derive the Chip Select address for the
DDR memory. Used in conjunction with CSADDRMASK (DDRMEMCFG4).
Unimplemented: Read as ‘0’
BNKADDR: Bank Address Select Shift bits
These bits specify which bits of user address space are used to derive the bank address for the DDR
memory. Used in conjunction with BNKADDRMASK (DDRMEMCFG4).
Unimplemented: Read as ‘0’
RWADDR: Row Address Select Shift bits
These bits specify which bits of user address space are used to derive the row address for the DDR memory. Used in conjunction with RWADDRMSK (DDRMEMCFG1).
2015-2021 Microchip Technology Inc.
DS60001361J-page 625
PIC32MZ Graphics (DA) Family
REGISTER 38-7:
Bit
Range
31:24
23:16
15:8
7:0
DDRMEMCFG1: DDR MEMORY CONFIGURATION REGISTER 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
RWADDRMSK
R/W-0
R/W-0
R/W-0
RWADDRMSK
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12-0 RWADDRMSK: Row Address Mask bits
These bits, which are used in conjunction with the RWADDR bits (DDRMEMCFG0), specify
which bits of user address space are used to derive the row address for the DDR memory.
DS60001361J-page 626
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 38-8:
Bit
Range
31:24
23:16
15:8
7:0
DDRMEMCFG2: DDR MEMORY CONFIGURATION REGISTER 2
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
CLADDRHMSK
R/W-0
R/W-0
R/W-0
CLADDRHMSK
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12-0 CLADDRHMSK: Column Address High Mask bits
These bits, which are used in conjunction with the CLADDR bits (DDRMEMCFG0) and the
CLADDRLMASK bits (DDRMEMCFG3), specify which bits of user address space are used
to derive the column address for the DDR memory.
2015-2021 Microchip Technology Inc.
DS60001361J-page 627
PIC32MZ Graphics (DA) Family
REGISTER 38-9:
Bit
Range
31:24
23:16
15:8
7:0
DDRMEMCFG3: DDR MEMORY CONFIGURATION REGISTER 3
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
CLADDRLMSK
R/W-0
R/W-0
R/W-0
CLADDRLMSK
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12-0 CLADDRLMSK: Column Address Low Mask bits
These bits, which are used in conjunction with the CLADDR bits (DDRMEMCFG0) and the
CLADDRHMASK bits (DDRMEMCFG2), specify which bits of user address space are used
to derive the column address for the DDR memory.
DS60001361J-page 628
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 38-10: DDRMEMCFG4: DDR MEMORY CONFIGURATION REGISTER 4
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5
31:24
23:16
15:8
7:0
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
CSADDRMSK
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
CSADDRMSK
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
BNKADDRMSK
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-9 Unimplemented: Read as ‘0’
bit 8-6 CSADDRMSK: Chip Select Address Mask bits
These bits, which are used in conjunction with the CSADDR bits (DDRMEMCFG0), determine which bits of user address space are used to derive the Chip Select address for the DDR memory.
bit 5-3 Unimplemented: Read as ‘0’
bit 2-0 BNKADDRMSK: Bank Address Mask bits
These bits, which are used in conjunction with the BNKADDR bits (DDRMEMCFG0), determine which bits of user address space are used to derive the bank address for the DDR memory.
2015-2021 Microchip Technology Inc.
DS60001361J-page 629
PIC32MZ Graphics (DA) Family
REGISTER 38-11: DDRREFCFG: DDR REFRESH CONFIGURATION REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MAXREFS
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
REFDLY
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
REFCNT
R/W-0
Legend:
R = Readable bit
-n = Value at POR
R/W-0
R/W-0
R/W-0
R/W-0
REFCNT
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26-24 MAXREFS: Maximum Pending Refreshes bits
These bits specify the maximum number of refreshes that may be pending at any time. If there is any idle
time when one or more refreshes are pending, the pending refreshes are issued continuously until a new
request is received. If there is no idle time while MAXREFS refreshes are pending, subsequent
requests are stopped until at least one burst of pending refreshes can be issued.
bit 23-16 REFDLY: Minimum Refresh-to-Refresh Delay bits
These bits specify the minimum number of clocks required between refreshes.
bit 15-0 REFCNT: Refresh Count bits
These bits specify the number of clock cycles corresponding to the average periodic refresh interval.
DS60001361J-page 630
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 38-12: DDRPWRCFG: DDR POWER CONFIGURATION REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
Bit
29/21/13/5 28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
U-0
U-0
U-0
—
—
—
U-0
R/W-0
—
PCHRGPWRDN
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PWDNDLY
R/W-0
PWDNDLY
Legend:
R = Readable bit
-n = Value at POR
U-0
SLFREFDLY
SLFREFDLY
R/W-0
Bit
Bit
25/17/9/1 24/16/8/0
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
ASLFREFEN APWRDNEN
U-0
U-0
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-23 Unimplemented: Read as ‘0’
bit 22
PCHRGPWDN: Precharge Power Down Only bit
Allow automatic entry into Precharge Power Down mode but not into active Power Down mode. If any rows
are open they will be Precharged before DDR SDRAM is put into Precharge Power Down mode.
1 = Allow automatic entry into Precharge Power Down mode.
0 = Do not allow automatic entry into Precharge Power Down mode.
bit 21-12 SLFREFDLY: Self Refresh Delay bits
Specifies the minimum number of clock cycles of idle time the controller needs to wait before automatic
entry into Self Refresh mode. Value represents number of clocks multiplied by 1024.
111111111 = 2111452 clocks
….
000000001 = 1024 clocks
bit 11-4 PWDNDLY: Refresh Count bits
Specifies the minimum number of clock cycles of idle time the controller needs to wait before automatic entry
into Power Down mode (Active or Precharge). Value represents number of clocks multiplied by 4.
11111111 = 1020 clocks
….
00000001 = 4 clocks
bit 3
ASLFREFEN: Automatic Self Refresh Enable bit
1 = Allow automatic entry into Self Refresh mode.
0 = Do not allow automatic entry into Self Refresh mode.
bit 2
APWRDNEN: Automatic Power Down Enable bit
1 = Allow automatic entry into Power Down mode.
0 = Do not allow automatic entry into Power Down mode.
bit 1-0
Unimplemented: Read as ‘0’
2015-2021 Microchip Technology Inc.
DS60001361J-page 631
PIC32MZ Graphics (DA) Family
REGISTER 38-13: DDRDLYCFG0: DDR DELAY CONFIGURATION REGISTER 0
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RMWDLY
R/W-0
R/W-0
R/W-0
R2WDLY
R/W-0
R/W-0
W2WCSDLY
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
R/W-0
R/W-0
W2RCSDLY
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
W2WDLY
R/W-0
R/W-0
R2RCSDLY
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R2RDLY
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
W2RDLY
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 RMWDLY: Read-Modify-Write Delay bits
These bits specify the minimum number of clocks required between the read and write commands issued
for a read-modify-write operation.
bit 27-24 R2WDLY: Read-to-Write Delay bits
These bits specify the minimum number of clocks required between a read command and write command.
Commands may be to the same or different Chip Selects.
bit 23-20 W2WCSDLY: Write-to-Write Chip Select Delay bits
These bits specify the minimum number of clocks required between two write commands to different Chip
Selects.
bit 19-16 W2WDLY: Write-to-Write Delay bits
These bits specify the minimum number of clocks required between two write commands to the same Chip
Select.
bit 15-12 R2RCSDLY: Read-to-Read Chip Select Delay bits
These bits specify the minimum number of clocks required between two read commands to different Chip
Selects.
bit 11-8 R2RDLY: Read-to-Read Delay bits
These bits specify the minimum number of clocks required between two read commands to the same Chip
Select.
bit 7-4
W2RCSDLY: Write-to-Read Chip Select Delay bits
These bits specify the minimum number of clocks required between a write command and a read command to different Chip Selects.
bit 3-0
W2RDLY: Write-to-Read Delay bits
These bits specify the minimum number of clocks required between a write command and a read command to the same Chip Select.
DS60001361J-page 632
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 38-14: DDRDLYCFG1: DDR DELAY CONFIGURATION REGISTER 1
Bit
Range
31:24
23:16
15:8
7:0
Bit
Bit
31/23/15/7 30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
—
SLFREF
EXDLY
NXTDAT
AVDLY
W2RCS
DLY
R/W-0
R/W-0
R/W-0
R/W-0
W2PCHRGW2RDLY
DLY
R/W-0
PWRDNEXDLY
R/W-0
R/W-0
R/W-0
R/W-0
PWRDNEXDLY
R/W-0
R/W-0
PWRDNMINDLY
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SLFREFEXDLY
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
R/W-0
R/W-0
R/W-0
SLFREFMINDLY
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
bit 30
Unimplemented: Read as ‘0’
SLFREFEXDLY: Self Refresh Exit Delay bit 8
This bit specifies the minimum number of clocks required before normal operation after exiting Self Refresh
mode.
bit 29
NXTDATAVDLY: Next Data Available Delay bit 4
These bits specify the minimum number of clock cycles required between a Write command and the write
data transfer handshake signal “next data request”. Also, see the NXTDATAVDLY bits
(DDRXFERCFG).
bit 28
W2RCSDLY: Write-to-Read Chip Select Delay bit 4
This bit specify the minimum number of clocks required between a write command and a read command to
different Chip Selects. Also, see W2RCSDLY (DDRDLYCFG0).
bit 27
W2RDLY: Write-to-Read Delay bit 4
This bit specifies the minimum number of clocks required between a write command and a read command
to the same Chip Select. Also, see W2RDLY (DDRDLYCFG0).
bit 26
W2PCHRGDLY: Write to Precharge Delay bit 4
These bits specify the minimum number of clocks required from a Write command to a Precharge command to the same bank as the write. Also, see WPCHRGDLY (DDRDLYCFG2).
bit 25-20 PWRDNEXDLY: Power Down Exit Delay bits
These bits specify the minimum number of clocks required before normal operation after exiting Power Down
mode.
bit 19-16 PWRDNMINDLY: Power Down Minimum Delay bits
These bits specify the minimum number of clocks to stay in Power Down mode after entering it.
bit 15-8 SLFREFEXDLY: Self Refresh Exit Delay bits
These bits specify the minimum number of clocks required before normal operation after exiting Self Refresh
mode.
bit 7-0
SLFREFMINDLY: Self Refresh Minimum Delay bits
These bits specify the minimum number of clocks to stay in Self Refresh mode after entering it.
2015-2021 Microchip Technology Inc.
DS60001361J-page 633
PIC32MZ Graphics (DA) Family
REGISTER 38-15: DDRDLYCFG2: DDR DELAY CONFIGURATION REGISTER 2
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RBENDDLY
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R2PCHRGDLY
U-0
U-0
U-0
U-0
—
—
—
—
W = Writable bit
‘1’ = Bit is set
Bit
24/16/8/0
RAS2RASDLY
W2PCHRGDLY
Legend:
R = Readable bit
-n = Value at POR
Bit
25/17/9/1
PCHRG2RASDLY
RAS2CASDLY
R/W-0
Bit
26/18/10/2
R/W-0
R/W-0
R/W-0
R/W-0
PCHRGALLDLY
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 RBENDDLY: Read Burst End Delay bits
These bits specify the minimum number of clocks required from issue of a Read command to the read data
burst completion.
bit 27-24 PCHRG2RASDLY: Precharge-to-RAS Delay bits
These bits specify the minimum number of clocks required from a Precharge command to a RAS command
to the same bank.
bit 23-20 RAS2CASDLY: RAS-to-CAS Delay bits
These bits specify the minimum number of clocks required from a RAS command to a CAS command to
the same bank.
bit 19-16 RAS2RASDLY: Write-to-Read Delay bits
These bits specify the minimum number of clocks required from a RAS command to a RAS command to a
different bank on the same Chip Select.
bit 15-12 W2PCHRGDLY: Write-to-Precharge Delay bits 3-0
These bits specify the minimum number of clocks required from a Write command to a Precharge command
to the same bank as the write.
An overflow bit (DDRDLYCFG1) is provided for delays greater than 15 clock cycles.
bit 11-8 R2PCHRGDLY: Read-to-Precharge Delay bits
These bits specify the minimum number of clocks required from a read command to a Precharge command
to the same bank as the read.
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
PCHRGALLDLY: Precharge All Delay bits
These bits specify the minimum number of clocks required from a Precharge all banks command to an
Activate or Refresh command.
DS60001361J-page 634
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 38-16: DDRDLYCFG3: DDR DELAY CONFIGURATION REGISTER 3
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
U-0
U-0
—
—
U-0
U-0
U-0
—
—
—
Legend:
R = Readable bit
-n = Value at POR
FAWTDLY
R/W-0
RAS2RASSBNKDLY
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
R/W-0
RAS2PCHRGDLY
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-22 Unimplemented: Read as ‘0’
bit 21-16 FAWTDLY: Four Activate Window Time Delay bits
These bits specify the minimum number of clocks within which only four banks may be opened.
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 RAS2RASSBNKDLY: RAS-to-RAS Same Bank Delay bits
These bits specify the minimum number of clocks required between RAS commands to the same bank.
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RAS2PCHRGDLY: RAS-to-Precharge Delay bits
These bits specify the minimum number of clocks required from a RAS command to a Precharge command
to the same bank.
2015-2021 Microchip Technology Inc.
DS60001361J-page 635
PIC32MZ Graphics (DA) Family
REGISTER 38-17: DDRODTCFG: DDR ON-DIE TERMINATION CONFIGURATION REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
R/W-0
ODTWLEN
R/W-0
R/W-0
—
OTDWDLY
R/W-0
Legend:
R = Readable bit
-n = Value at POR
R/W-0
R/W-0
ODTRLEN
R/W-0
R/W-0
R/W-0
OTDRDLY
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OTDCSEN
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-23 Unimplemented: Read as ‘0’
bit 22-20 ODTWLEN: On-Die Termination Write Length bits
These bits specify the number of clocks ODT is turned on for writes.
bit 19
Unimplemented: Read as ‘0’
bit 18-16 ODTRLEN: On-Die Termination Read Length bits
These bits specify the number of clocks ODT is turned on for reads.
bit 15-12 ODTWDLY: On-Die Termination Write Delay bits
These bits specify the number of clocks after a Write command before turning on ODT to the DDR.
bit 11-8 ODTRDLY: On-Die Termination Read Delay bits
These bits specify the number of clocks after a Read command before turning on ODT to the DDR.
bit 7-0
ODTCSEN: On-Die Termination Chip Select Enable bits
These bits are used with the DDRODTENCFG register (Register 38-20) to program the ODT control for
each Chip Select. The value in this field represents the number of Chip Selects multiplied by the Chip
Select number to be programmed.
DS60001361J-page 636
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 38-18: DDRXFERCFG: DDR TRANSFER CONFIGURATION REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
bit 30-28
bit 27-24
bit 23-20
bit 19-16
bit 15-8
bit 7-4
bit 3-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-1
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
BIGENDIAN
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NXTDATAVDLY
Legend:
R = Readable bit
-n = Value at POR
bit 31
Bit
26/18/10/2
W = Writable bit
‘1’ = Bit is set
MAXBURST
R/W-0
R/W-0
R/W-0
R/W-0
RDATENDLY
U-0
NXTDATRQDLY
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
BIGENDIAN: Big Endian bit
1 = Data is big endian format
0 = Data is little endian format
Unimplemented: Read as ‘0’
MAXBURST: Maximum Command Burst Count bits
These bits specify the maximum number of commands that can be written to the DDR controller in Burst
mode.
Unimplemented: Read as ‘0’
RDATENDLY: PHY Read Data Enable Delay bits
These bits specify the minimum number of clocks Required between issuing a Read command to the PHY
and when the “read data enable” signal to the PHY is asserted.
Unimplemented: Read as ‘0’
NXTDATAVDLY: Next Data Available Delay bits
These bits specify the minimum number of clock cycles required between issuing a Read command and
the read data being received.
NXTDATRQDLY: Next Data Request Delay bits
These bits specify the minimum number of clock cycles required between issuing a Write command and
the write data transfer handshake signal “next data request”.
2015-2021 Microchip Technology Inc.
DS60001361J-page 637
PIC32MZ Graphics (DA) Family
REGISTER 38-19: DDRCMDISSUE: DDR COMMAND ISSUE REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0, HC
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
VALID
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Cleared
W = Writable bit
‘1’ = Bit is set
NUMHOSTCMDS
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-5 Unimplemented: Read as ‘0’
bit 4
VALID: Host Command Valid bit
When written with a '1', this bit indicates to the controller that the data in the Host command registers are
valid, and should be transmitted to the SDRAM. This bit is cleared by hardware when all data has been
transmitted.
bit 3-0 NUMHOSTCMDS: Number of Host Commands bits
The number of Host commands to be transmitted to the SDRAM.
DS60001361J-page 638
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 38-20: DDRODTENCFG: DDR ON-DIE TERMINATION ENABLE CONFIGURATION
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
ODTWEN
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
ODTREN
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-17 Unimplemented: Read as ‘0’
bit 16
ODTWEN: On-Die Termination Write Enable bit
1 = The Chip Select represented by the OTDCSEN bits (DDRODTCFG) has ODT enabled for
data reads
0 = The Chip Select represented by the OTDCSEN bits (DDRODTCFG) has ODT disabled for
data reads
bit 15-1 Unimplemented: Read as ‘0’
bit 0
ODTREN: On-Die Termination Read Enable bit
1 = The Chip Select represented by the OTDCSEN bits (DDRODTCFG) has ODT enabled for
data writes
0 = The Chip Select represented by the OTDCSEN bits (DDRODTCFG) has ODT disabled for
data writes
2015-2021 Microchip Technology Inc.
DS60001361J-page 639
PIC32MZ Graphics (DA) Family
REGISTER 38-21: DDRMEMWIDTH: DDR MEMORY WIDTH REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
—
—
—
—
HALFRATE
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3
HALFRATE: Half-rate Mode bit
The PIC32 always operates in Half-rate mode. This bit must be set during initialization.
1 = Half-rate mode
0 = Full-rate mode
bit 2-0 Unimplemented: Read as ‘0’
DS60001361J-page 640
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 38-22: DDRCMD1x: DDR HOST COMMAND 1 REGISTER ‘x’ (‘x’ = 0 THROUGH 15)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MDALCMD
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WENCMD2 CASCMD2 RASCMD2
R/W-0
R/W-0
R/W-0
CSCMD2
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
CSCMD2
R/W-0
R/W-0
R/W-0
CLKENCMD2 WENCMD1 CASCMD1
R/W-0
R/W-0
CSCMD1
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
R/W-0
R/W-0
RASCMD1
CSCMD1
R/W-0
R/W-0
CLKENCMD1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 MDALCMD: Mode Address Low Command bits
These bits specify the value to be driven on the SDRAM address bits 7 through 0 when issuing the command.
bit 23
WENCMD2: Write Enable Command 2 bit
This bit specifies the value to be driven on WE_N on the second and subsequent cycles of issuing the command
bit 22
CASCMD2: Column Address Strobe Command 2 bit
This bit specifies the value to be driven on CAS_N on the second and subsequent cycles of issuing the command
bit 21
RASCMD2: Row Address Strobe Command 2 bit
This bit specifies the value to be driven on RAS_N on the second and subsequent cycles of issuing the command
bit 20-13 CSCMD2: Chip Select Command 2 bits
These bits specify the value to be driven on the CS_N signals (maximum of 8) on the second and subsequent
cycles of issuing the command.
bit 12
CLKENCMD2: Clock Enable Command 2 bit
This bit specifies the value to be driven on CKE on the second and subsequent cycles of issuing the command.
bit 11
WENCMD1: Write Enable Command 1 bit
This bit specifies the value to be driven on the WE_N on the first cycle of issuing the command.
bit 10
CASCMD1: Column Address Strobe Command 1 bit
This bit specifies the value to be driven on the CAS_N on the first cycle of issuing the command.
bit 9
RASCMD1: Row Address Strobe Command 1 bit
This bit specifies the value to be driven on the RAS_N on the first cycle of issuing the command.
bit 8-1
CSCMD1: Chip Select Command 1 bit
These bits specify the value to be driven on the CS_N signals (maximum of 8) on the first cycle of issuing the
command.
bit 0
CLKENCMD1: Clock Enable Command 1 bit
This bit specifies the value to be driven on CKE on the first cycle of issuing the command.
2015-2021 Microchip Technology Inc.
DS60001361J-page 641
PIC32MZ Graphics (DA) Family
REGISTER 38-23: DDRCMD2x: DDR HOST COMMAND 2 REGISTER ‘x’ (‘x’ = 0 THROUGH 15)
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
Bit
30/22/14/6 29/21/13/5
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
WAIT
WAIT
R/W-0
Legend:
R = Readable bit
-n = Value at POR
R/W-0
R/W-0
R/W-0
BNKADDRCMD
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MDADDRHCMD
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-20 Unimplemented: Read as ‘0’
bit 19-11 WAIT: Wait Command bits
These bits specify the number of clock cycles to wait after issuing a command before issuing the next
command.
bit 10-8 BNKADDRCMD: Bank Address Command bit
These bits specify the value to be driven on the bank address bits when issuing the command.
bit 7-0
MDADDRHCMD: Mode Address High Command bits
These bits specify the value to be driven on the SDRAM address bits 15 through 8 when issuing the
command.
DS60001361J-page 642
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 38-24: DDRSCLSTART: DDL SELF CALIBRATION LOGIC START REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
Bit
27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
R/W-0
R/W-0
U-0
—
—
SCL
PHCAL
SCL
START
W-0
U-0
R/W-0
—
SCLEN
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R-0
R-0
—
—
—
—
—
—
SCLUB
PASS(1)
SCLLB
PASS(1)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Write as ‘0’
bit 29
SCLPHCAL: Start Phase Self-calibration Logic bit
1 = Phase calibration is enabled
0 = Phase calibration is disabled
bit 28
SCLSTART: Start Self Calibration Logic bit
1 = Start self calibration
0 = Do not start self calibration
bit 27
bit 26
bit 25-2
bit 1
bit 0
Note 1:
Note:
This bit is cleared by hardware when the SCL process is complete.
Unimplemented: Write as ‘0’
SCLEN: Self Calibration Logic Enable bit
1 = Enable dynamic self calibration logic
0 = Disable dynamic self calibration logic
Note:
Enabling dynamic self calibration may impact performance.
Unimplemented: Write as ‘0’
SCLUBPASS: Self Calibration Logic Upper Data Byte Status bit(1)
1 = Self calibration logic for upper data byte passed
0 = Self calibration logic for upper data byte failed
SCLLBPASS: Self Calibration Logic Lower Data Byte Status bit(1)
1 = Self calibration logic for lower data byte passed
0 = Self calibration logic for lower data byte failed
This bit is set by hardware when the SCL process has passed and is complete.
2015-2021 Microchip Technology Inc.
DS60001361J-page 643
PIC32MZ Graphics (DA) Family
REGISTER 38-25: DDRSCLLAT: DDL SELF CALIBRATION LOGIC LATENCY REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/
5
Bit
28/20/12/4
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
bit 3-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
R/W-0
—
—
—
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-1
R/W-1
R/W-0
U-0
U-0
R/W-1
R/W-0
DDRCLKDLY
Legend:
R = Readable bit
-n = Value at POR
bit 31-8
bit 7-4
Bit
Bit
27/19/11/ 26/18/10/
3
2
W = Writable bit
‘1’ = Bit is set
CAPCLKDLY
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
DDRCLKDLY: DDR Clock Delay bit
Recommended value is 4.
CAPCLKDLY: Capture Clock Delay bit
Recommended value is 3.
DS60001361J-page 644
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 38-26: DDRSCLCFG0: DDR SCL CONFIGURATION REGISTER 0
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-1
—
—
—
—
—
—
—
ODTCSW
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-1
R/W-0
R/W-1
R/W-1
U-0
U-0
R/W-0
R/W-1
—
—
DDR2
BURST8
RCASLAT
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-25 Unimplemented: Read as ‘0’
bit 24
ODTCSW: On-Die Termination Chip Select Write bit
1 = ODT is turned on to the DRAM on CS0 during writes performed by the SCL
0 = ODT is turned off to the DRAM on CS0 during writes performed by the SCL.
bit 23-8 Unimplemented: Read as ‘0’
bit 7-4
RCASLAT: Read CAS Latency bits
DRAM read CAS latency in clock cycles
bit 3-2
Unimplemented: Read as ‘0’
bit 1
DDR2: DDR2 bit
1 = DDR2 is connected
0 = DDR2 is not connected
bit 0
BURST8: PHY Burst 8 bit
1 = DRAM is in burst 8 mode while running SCL test
0 = DRAM is in burst 4 mode while running SCL test
2015-2021 Microchip Technology Inc.
DS60001361J-page 645
PIC32MZ Graphics (DA) Family
REGISTER 38-27: DDRSCLCFG1: DDR SCL CONFIGURATION REGISTER 1
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
—
—
—
DBLREFDLY
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-1
—
—
—
—
—
—
—
SCLCSEN
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
WCASLAT
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12
DBLREFDLY: Double Reference Delay bit
Determines whether the PHY will delay an SCL operation following an acknowledge by one or two time
intervals. The time interval is a function of the hardware design.
1 = SCL operation delay doubled
0 = SCL operation delay not doubled
bit 11-8 WCASLAT: Write CAS Latency bits
DRAM write CAS latency in clock cycles.
bit 7-1
Unimplemented: Read as ‘0’
bit 0
SCLCSEN: SCL Chip Select Enable bit
1 = Run SCL on Chip Select 0
0 = Do not run SCL on Chip Select 0
DS60001361J-page 646
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 38-28: DDRPHYPADCON: DDR PHY PAD CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
U-0
31:24
—
R/W-0
23:16
Bit
30/22/14/6
Bit
29/21/13/5
R/W-1
R/W-0
PREAMBDLY
R/W-1
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-1
U-0
U-0
U-0
RCVREN
—
—
—
—
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
U-0
U-0
R/W-0
DRVSTRPFET
U-0
15:8
7:0
DRVSTRNFET
R/W-1
R/W-0
—
HALFRATE
WR
CMDDLY
—
R/W-0
R/W-1
R/W-0
R/W-0
ODTPUCAL
Legend:
R = Readable bit
-n = Value at POR
ODTPDCAL
W = Writable bit
‘1’ = Bit is set
U-0
R/W-0
R/W-0
—
—
NOEXTDLL
EOEN
CLKCYC
R/W-0
R/W-0
R/W-0
R/W-1
ADDC
DRVDLY
DAT
DRVSEL
ODTEN
ODTSEL
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Unimplemented: Read as ‘0’
bit 30-29 PREAMBDLY: Preamble Delay bits
Controls the length of the preamble for writes.
11 = Reserved
10 = 1 cycle preamble
01 = 1.5 cycle preamble
00 = 2 cycle preamble
bit 28
RCVREN: Receiver Enable bit
1 = Pad receivers on bidirectional I/Os are turned on
0 = Pad receivers on bidirectional I/Os are turned off
bit 27-24 Unimplemented: Read as ‘0’
bit 23-20 DRVSTRPFET: PFET Drive Strength bits
Pad PFET driver output impedance adjustment control
1111 = Maximum drive strength
•
•
•
0000 = Minimum drive strength.
bit 19-16 DRVSTRNFET: NFET Drive Strength bits
Pad NFET driver output impedance adjustment control
1111 = Maximum drive strength
•
•
•
0000 = Minimum drive strength.
Unimplemented: Read as ‘0’
HALFRATE: Half Rate bit
1 = Controller clock is running at half rate with respect to PHY
0 = Controller clock is running at full rate with respect to PHY
bit 13
WRCMDDLY: Write Command Delay bit
This bit should be set to ‘1’ if Write Latency (WL) is an even number.
1 = Write command delay
0 = No Write command delay
bit 12-10 Unimplemented: Read as ‘0’
bit 15
bit 14
2015-2021 Microchip Technology Inc.
DS60001361J-page 647
PIC32MZ Graphics (DA) Family
REGISTER 38-28: DDRPHYPADCON: DDR PHY PAD CONTROL REGISTER (CONTINUED)
bit 9
bit 8
bit 7-6
NOEXTDLL: No External DLL bit
1 = Use internal digital DLL.
0 = Use external DLL.
EOENCLKCYC: Extra Output Enable bit
1 = Drive pad output enables for an extra clock cycle after a write burst
0 = Do not drive pad output enables for an extra clock cycle after a write burst
ODTPUCAL: On-Die Termination Pull-up Calibration bits
11 = Maximum ODT impedance
•
•
•
bit 5-4
00 = Minimum ODT impedance
ODTPFDCAL: On-Die Termination Pull-down Calibration bits
11 = Maximum ODT impedance
•
•
•
bit 3
bit 2
bit 1
bit 0
00 = Minimum ODT impedance
ADDCDRVSEL: Address and Control Pads Drive Strength Select bit
1 = Full drive strength
0 = 60% driver strength
DATDRVSEL: Data Pad Drive Strength Select bit
1 = Full Drive Strength
0 = 60% Drive Strength
ODTEN: On-Die Termination Enable bit
1 = ODT Enabled
0 = ODT Disabled
ODTSEL: On-Die Termination Select bit
1 = 150 ohm On-Die Termination
0 = 75 ohm On-Die Termination
DS60001361J-page 648
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 38-29: DDRPHYDLLR: DDR PHY DLL RECALIBRATE REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-1
—
DISRECALIB
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DLYSTVAL
R/W-0
R/W-0
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
RECALIBCNT
RECALIBCNT
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RECALIBCNT
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 DLYSTVAL: Delay Start Value bits
Start value of the digital DLL delay line. Recommended value is ‘0011’.
bit 27
Unimplemented: Read as ‘0’
bit 26
DISRECALIB: Disable Recalibration bit
1 = Do not recalibrate the digital DLL after the first time
0 = Recalibrate the digital DLL in accordance with the value of the RECALIBCNT bits
bit 25-8 RECALIBCNT: Recalibration Count bits
Determines the period of recalibration of the digital DLL in units of (256 * PHY clock cycles).
bit 7-0
Unimplemented: Read as ‘0’
2015-2021 Microchip Technology Inc.
DS60001361J-page 649
PIC32MZ Graphics (DA) Family
REGISTER 38-30: DDRPHYDLLCTRL: DDR PHY TRIM REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
r-x
r-x
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DDRDLLTRIM
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-10 Unimplemented: Read as ‘0’
bit 9-8
Reserved: Write as ‘0’
bit 7-0
DDRDLLTRIM: Trim Setting bits
These bits control the Trim settings for adjusting the output time of the bank address and control signals with
respect to data signals (DQ/DQS). The recommended value is 0x1.
REGISTER 38-31: DDRPHYCLKDLY: DDR CLOCK DELTA DELAY REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
Bit
31/23/15/7 30/22/14/6
bit 4
bit 3
Bit
28/20/12/4
Bit
Bit
Bit
27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R-0
R-0
U-0
R/W-0
R/W-0
R/W-0
—
—
Legend:
R = Readable bit
-n = Value at POR
bit 31-6
bit 5
Bit
29/21/13/5
SCLUBPASS(1) SCLLBPASS(1)
W = Writable bit
‘1’ = Bit is set
—
CLKDLYDELTA
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0
SCLUBPASS: Self Calibration Logic Upper Data Byte Status bit (1)
1 = Self calibration logic for upper data byte is passed
0 = Self calibration logic for upper data byte is failed
SCLLBPASS: Self Calibration Logic Lower Data Byte Status bit(1)
1 = Self calibration logic for lower data byte is passed
0 = Self calibration logic for lower data byte is failed
Unimplemented: Read as ‘0’
DS60001361J-page 650
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
bit 2-0
CLKDLYDELTA: DDR Clock Delay Delta bits
These bits indicate the SCL latency setting programmed per byte lane.
111 = 7 DDR clocks
110 = 6 DDR clocks
•
•
•
000 = 0 DDR clocks
These bits are automatically programmed by the SCL logic and can also be programmed by the user, and
are specifically useful for SCL retires.
Note 1:
These bits indicate the same status as the SCLLBPASS (DDRSCLSTART) and
SCLUBPASS (DDRSCLSTART) bits.
2015-2021 Microchip Technology Inc.
DS60001361J-page 651
PIC32MZ Graphics (DA) Family
REGISTER 38-32: DDRADLLBYP: DDR ANALOG DLL BYPASS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
ANLDLLBYP
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-25 Unimplemented: Read as ‘0’
bit 24
ANLDLLBYP: Bypass Analog DLL bit
1 = Bypass the Analog DLL and use the PHY Digital DLL
0 = Reserved; do not use
bit 23-0 Unimplemented: Read as ‘0’
DS60001361J-page 652
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 38-33: DDRSCLCFG2: DDR SCL CONFIGURATION REGISTER 2
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
SCLLANSEL
Legend:
R = Readable bit
-n = Value at POR
bit 31-2
bit 1-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
SCLLANSEL: Memory Lane Select bits
These bits can be used to run the SCL on a limited number of lanes rather than all lanes by default. Lanes
with the corresponding bit set are not checked by SCL.
11 = Reserved; do not use
10 = Use the upper byte lane
01 = Use the lower byte lane
00 = Use both lanes
2015-2021 Microchip Technology Inc.
DS60001361J-page 653
PIC32MZ Graphics (DA) Family
REGISTER 38-34: DDRPHYSCLADR: DDR PHY SCL ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SCLBANKADR
R/W-0
R/W-0
SCLCOLADR
R/W-0
R/W-0
R/W-0
SCLCOLADR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SCLROWADR
R/W-0
Legend:
R = Readable bit
-n = Value at POR
R/W-0
R/W-0
R/W-0
R/W-0
SCLROWADR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 SCLBANKADR: SCL Bank Address bits
These bits define the bank address to use when running SCL.
bit 28-16 SCLCOLADR: SCL Column Address bits
These bits define the column address to use when running SCL.
bit 15-0 SCLROWADR: SCL Row Address bits
These bits define the row address to use when running SCL.
DS60001361J-page 654
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
39.0
SECURE DIGITAL HOST
CONTROLLER (SDHC)
Note:
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 57. “Secure Digital
Host
Controller
(SDHC)”
(DS60001334), which is available from
the Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
The SDHC module uses a 32-bit System Bus host and
client interface to connect the Host system and standard card interface on the device side.
The core has a built-in DMA controller so that data can
be automatically transferred between system memory
and the SD/SDIO/eMMC card without intervention from
the CPU.
The SDHC module includes the following features:
•
•
•
•
•
•
•
•
- Physical Layer Simplified Specification,
version 2.00
- SDIO Simplified Specification, version 2.00
eMMC Standard: JESD84-A441
Default and high-speed modes of operation
1-bit or 4-bit data transfers
Built-in clock divider
PIO and ADMA modes of data transfer
3.3V operation
Interrupt support
Stop at block gap
A block diagram of the SDHC module is provided in
Figure 39-1.
Note 1: Transmit and receive buffer addresses in
ADMA mode should be word-aligned.
When multiple descriptors are used to
transfer a single block, all but the last
descriptor should have a transfer size in
multiples of four.
2: REFCLKO4 must be less or equal to
PBCLK5 when used as SDHC clock.
• SD Association specification compliance:
- SD Host Controller Simplified Specification,
version 2.00
FIGURE 39-1:
SECURE DIGITAL HOST CONTROLLER (SDHC) BLOCK DIAGRAM
System Bus
Client System Bus
SDHC
Control
Registers
SDWP
Host
State
Machine
SDCD
SDCMD
SDCK
Host System Bus
DMA Engine
TX/RX
Engine
FIFOs
REFCLKO4(1)
Clock Control
and Clock Tuning
PBCLK5(2)
SDDATA0
SDDATA1
SDDATA2
SDDATA3
Note
1:
2:
When configuring the REFCLKO4 clock source, a value of ‘0’ for the ROTRIM bits must be selected. REFCLKO4 must be
turned on before SDHC Special Function Registers (SFR) access.
This clock source is only used for SDHC Special Function Register (SFR) access.
2015-2021 Microchip Technology Inc.
DS60001361J-page 655
Control Registers
TABLE 39-1:
SDHC SFR SUMMARY
C004
SDHC 31:16
BLKCON 15:0
31/15
30/14
29/13
28/12
27/11
26/10
—
—
—
—
—
—
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
BCOUNT
All Resets
Bit Range
Register
Name
Virtual
Address
(BF8E_#)
Bits
0000
BSIZE
0000
C008
SDHC
ARG
31:16
ARG
15:0
ARG
C00C
SDHC
MODE
31:16
—
—
15:0
—
—
C010
SHDC 31:16
RESP0 15:0
RESP
0000
RESP
0000
C014
SHDC 31:16
RESP1 15:0
RESP
0000
RESP
0000
C018
SHDC 31:16
RESP2 15:0
RESP
0000
RESP
0000
C01C
SHDC 31:16
RESP3 15:0
RESP
0000
RESP
0000
C020
SHDC
DATA
31:16
DATA
0000
15:0
DATA
C024
SDHC
STAT1
31:16
—
—
—
—
—
15:0
—
—
—
—
BREN
C028
SDHC
CON1
31:16
—
—
—
—
—
15:0
—
—
—
—
—
C02C
SDHC
CON2
31:16
—
—
—
—
—
CIDX
—
15:0
—
—
—
—
BWEN
0000
0000
CTYPE
—
—
—
—
—
DPSEL
BSEL
CIDXCEN CCRCCEN
DTXDSEL
—
RESPTYPE
ACEN
BCEN
DMAEN
0000
0000
0000
CMDSLVL DATA3SLVL DATA2SLVL DATA1SLVL DATA0SLVL WPSLVL
CDSLVL
CARDST
CARDINS 0000
RDACTIVE WRACTIVE
—
—
—
—
—
DLACTIVE
CINHDAT
CINHCMD 0000
WKONREM WKONINS WKONINT
—
—
—
—
INTBG
RDWTCON
CONTREQ
SBGREQ 0000
SDBP
CDSSEL
CDTLVL
—
DMASEL
HSEN
DTXWIDTH
SWRALL
—
—
—
—
—
—
—
—
—
—
—
SWRDATA SWRCMD
SDCLKDIV
—
DTOC
SDCLKEN ICLKSTABLE
0000
0000
ICLKEN
0000
SDHC 31:16
INTSTAT 15:0
—
—
—
—
—
—
ADEIF
ACEIF
CLEIF
DEBEIF
DCRCEIF
DTOEIF
CIDXEIF
CEBEIF
CCRCEIF
CTOEIF
0000
EIF
—
—
—
—
—
—
CARDIF
CARDRIF
CARDIIF
BRRDYIF
BWRDYIF
DMAIF
BGIF
TXCIF
CCIF
0000
31:16
—
—
—
—
—
—
ADEIE
AACEIE
CLEIE
DEBEIE
DCRCEIE
DTOEIE
CIDXEIE
CDEBEIE
CCRCEIE
CTOEIE
0000
15:0
FTZIE
—
—
—
—
—
—
CARDIE
CARDRIE
CARDIIE
BRRDYIE
BWRDYIE
DMAIE
BGIE
TXCIE
CCE
0000
—
SDHC 31:16
INTSEN 15:0 FTZEISE
—
—
—
—
—
ADEISE
ACEISE
CLEISE
DEBEISE
DCRCEISE
DTOEISE
CIDXEISE
CEBEISE
CEBEISE
—
—
—
—
—
—
DMAISE
BGISE
TXCISE
CCISE
0000
C03C
SDHC
STAT2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
CNISSE
—
—
ACIDXE
ACEBE
ACCRCE
ACTOE
C040
SDHC
CAP
31:16 SLOTTYPE ASYNCINT
—
—
—
—
VOLT3V3
SRESUME
—
HISPEED
—
ADMA2
—
TOCLKU
—
—
—
C030
2015-2021 Microchip Technology Inc.
C034
C038
C048
C050
Legend:
SDHC
INTEN
15:0
CARDISE CARDRISE CARDIISE BRRDYISE BWRDYISE
BASECLK
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
FEAE
FEACE
FECLE
FEDEBE
FEDCRCE
15:0
—
—
—
—
—
—
—
—
FECNIACE
—
—
‘—’ = unimplemented; read as ‘0’.
ACNEXEC 0000
MBLEN
TOCLKFREQ
SDHC 31:16
MAXCAP 15:0
SDHCFE
CCRCEISE 0000
—
—
—
0000
—
—
—
FECEBE
FECCRCE
FECTOE
MC3V3
FEDTOE
FEIDXE
0000
0000
0000
FEACIDXE FEACEBE FEACCRCE
FEACTOE
0000
FEACNEE 0000
PIC32MZ Graphics (DA) Family
DS60001361J-page 656
39.1
SDHC SFR SUMMARY (CONTINUED)
C054
SDHC 31:16
AESTAT 15:0
C058
SDHC 31:16
AADDR 15:0
Legend:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ALMERR
AERRST
All Resets
Bit Range
Register
Name
Bits
Virtual
Address
(BF8E_#)
2015-2021 Microchip Technology Inc.
TABLE 39-1:
0000
0000
ADDR
0000
ADDR
0000
‘—’ = unimplemented; read as ‘0’.
PIC32MZ Graphics (DA) Family
DS60001361J-page 657
PIC32MZ Graphics (DA) Family
REGISTER 39-1:
Bit
Range
31:24
23:16
15:8
7:0
SDHCBLKCON: SDHC BLOCK CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
(2)
BCOUNT
R/W-0
BCOUNT(1)
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(2)
R/W-0
BSIZE
R/W-0
R/W-0
BSIZE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 BCOUNT: Blocks Count for Current Transfer bits(1)
These bits represent the number of blocks. The software sets this value between 1 and 65,535 blocks and
the SDHC decrements the count after each block transfer and stops when the count reaches zero.
0xFFFF = 65,535 blocks
0x0002 = 2 blocks
0x0001 = 1 block
0x0000 = Stop count Blocks Count for Current Transfer bits
bit 15-10 Unimplemented: Read as ‘0’
bit 9-0
BSIZE: Transfer Block Size bits(2)
These bits specify the block size of the data transfer for CMD17, CMD18, CMD24, CMD25, and CMD53.
0x200 = 512 bytes
0x1FF = 511 bytes
•
•
•
0x002 = 2 bytes
0x001 = 1 byte
0x000 = No data transfer
Note 1:
These bits are only used when the BCEN bit (SDHCMODE) is set to '1' and is valid only for multiple
block transfers. The BCOUNT bits need not be set if the BSIZE bit (SDHCMODE) is set to '0'.
These bits can only be accessed when no transactions are in progress. Read operations during transfers
will return an invalid value and write operations to these bits will be ignored.
2:
DS60001361J-page 658
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 39-2:
Bit
Range
31:24
23:16
15:8
7:0
SDHCARG: SDHC ARGUMENT REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ARG
R/W-0
ARG
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ARG
R/W-0
ARG
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
ARG: Command Argument bits
2015-2021 Microchip Technology Inc.
DS60001361J-page 659
PIC32MZ Graphics (DA) Family
REGISTER 39-3:
Bit
Range
31:24
23:16
15:8
7:0
SDHCMODE: SDHC MODE REGISTER
Bit
Bit
31/23/15/7 30/22/14/6
U-0
U-0
—
—
R/W-0
R/W-0
CTYPE
U-0
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R/W-0
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(1)
CIDX
R/W-0
R/W-0
R/W-0
U-0
DPSEL
CIDXCEN(2)
CCRCCEN(3)
—
U-0
U-0
U-0
U-0
U-0
RESPTYPE
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
BSEL
DTXDSEL
BCEN
DMAEN
ACEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-24 CIDX: Command Index bits(1)
These bits represent the command number (0-63).
bit 23-22 CTYPE: Command Type bits
11 = Abort
10 = Resume
01 = Suspend
00 = Normal
bit 21
DPSEL: Data Present Select bit
1 = Data is present
0 = Data is not present
bit 20
CIDXCEN: Command Index Check Enable bit(2)
1 = Command index check is enabled
0 = Command index check is disabled
bit 19
CCRCCEN: Command CRC Check Enable bit(3)
1 = Command CRC check is enabled
0 = Command CRC check is disabled
bit 18
Unimplemented: Read as ‘0’
bit 17-16 RESPTYPE: Response Type Select bits
11 = Response length 48; check busy after response
10 = Response length 48
01 = Response length 136
00 = No response
bit 15-6
Unimplemented: Read as ‘0’
bit 5
BSEL: Multiple/Single Block Select bit
1 = Multiple block, set when issuing multiple transfer commands using DAT lines
0 = Single block
Note 1:
Refer to bits 45-40 of the command format in the “SD Host Controller Simplified Specification” (version
2.00).
If these bits are set to '1', the SDHC will check the index field in the response to see if it has the same
value as the CIDX bits, if not, it will be reported as a command index error.
If these bits are set to '1', the SDHC will check the CRC field in the response and reports a command CRC
error upon a CRC error detection.
2:
3:
DS60001361J-page 660
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 39-3:
SDHCMODE: SDHC MODE REGISTER (CONTINUED)
bit 4
DTXDSEL: Data Transfer Direction Select bit
1 = Read (card to SDHC)
0 = Write (SDHC to card)
bit 3-2
ACEN: Auto CMD12 Enable bits
Auto CMD12 is used to stop multiple-block read/write operations.
11 = Reserved
10 = Reserved
01 = Auto CMD12 is enabled
00 = Auto CMD 12 is disabled
bit 1
BCEN: Block Count Enable Bit
1 = Block count is enabled
0 = Block count is disabled
bit 0
DMAEN: DMA Enable bit
1 = DMA (ADMA) is used to transfer data
0 = CPU is used to transfer data
Note 1:
Refer to bits 45-40 of the command format in the “SD Host Controller Simplified Specification” (version
2.00).
If these bits are set to '1', the SDHC will check the index field in the response to see if it has the same
value as the CIDX bits, if not, it will be reported as a command index error.
If these bits are set to '1', the SDHC will check the CRC field in the response and reports a command CRC
error upon a CRC error detection.
2:
3:
2015-2021 Microchip Technology Inc.
DS60001361J-page 661
PIC32MZ Graphics (DA) Family
REGISTER 39-4:
Bit
Range
SDHCRESPx: SDHC RESPONSE REGISTER ‘x’ (‘x’ = 0-3)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
31:24
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RESP
23:16
R-0
RESP
15:8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RESP
7:0
R-0
RESP
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
RESP: Response bits
These bits indicate the bit positions of Responses [31:0] defined in the “SD Host Controller Simplified
Specification (version 2.00). Refer to Table 39-2 for full bit definitions.
TABLE 39-2:
RESPONSE BIT DEFINITION FOR EACH RESPONSE TYPE
Response Type (see Note 1)
Response Meaning
Response Register
R1, R1b (normal response)
Card status
SDHCRESP0
R1b (Auto CMD12 response)
Card status for Auto CMD12
SDHCRESP3
R2 (CID, CSD register)
CID or CSD register
SDHCRESP0
SDHCRESP1
SDHCRESP2
SDHCRESP3
R3 (OCR register)
OCR register for memory
SDHCRESP0
R4 (OCR register)
OCR register for I/O, etc.
SDHCRESP0
R5, R5b
SDIO response
SDHCRESP0
New published RCA, etc.
SDHCRESP0
R6 (published RCA response)
Note 1:
For additional information, refer to the “SD Host Controller Simplified Specification” (version 2.00), the
“Physical Layer Simplified Specification” (version 2.00), and the “SDIO Simplified Specification” (version
2.00). These documents are available for download by visiting the SD Association web site at:
http://www.sdcard.org/downloads/pls/simplified_specs/archive/index.html
DS60001361J-page 662
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 39-5:
Bit
Range
31:24
23:16
15:8
7:0
SDHCDATA: SDHC DATA REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATA
R/W-0
DATA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATA
R/W-0
DATA
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
DATA: Buffer Data bits
These bits are used to access bits 31 through 0 of the internal data buffer.
2015-2021 Microchip Technology Inc.
DS60001361J-page 663
PIC32MZ Graphics (DA) Family
REGISTER 39-6:
Bit
Range
31:24
23:16
15:8
7:0
SDHCSTAT1: SDHC STATUS REGISTER 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
U-0
U-0
Bit
Bit
27/19/11/3 26/18/10/2
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R-x, HC
CMDSLVL
—
—
—
—
—
—
—
R-x, HC
R-x, HC
R-x, HC
R-x, HC
R-x, HC
R-x, HC
R-x, HC
R-x, HC
WPSLVL
CDSLVL
CARDST
CARDINS
U-0
R-0, HC
R-0, HC
R-0, HC
R-0, HC
DATA3SLVL DATA2SLVL DATA1SLVL DATA0SLVL
U-0
U-0
U-0
—
—
—
—
BREN
BWEN
U-0
U-0
U-0
U-0
U-0
R-0, HC
R-0, HC
R-0, HC
—
—
—
—
—
DLACTIVE
CINHDAT
CINHCMD
Legend:
RDACTIVE WRACTIVE
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-25 Unimplemented: Read as ‘0’
bit 24
CMDSLVL: Command Line Signal Level bit
1 = CMD line is high
0 = CMD line is low
bit 23
DATA3SLVL: DATA3 Signal Level bit
1 = DAT3 line is high
0 = DAT3 line is low
bit 22
DATA2SLVL: DATA2 Signal Level bit
1 = DAT2 line is high
0 = DAT2 line is low
bit 21
DATA1SLVL: DATA1 Signal Level bit
1 = DAT1 line is high
0 = DAT1 line is low
bit 20
DATA0SLVL: DATA0 Signal Level bit
1 = DAT0 line is high
0 = DAT0 line is low
bit 19
WPSLVL: Write-protect Signal Level bit
1 = Write-protect is disabled
0 = Write-protect is enabled
bit 18
CDSLVL: Card Detect Signal Level bit
1 = Card is present
0 = Card is not present
bit 17
CARDST: Card State Stable bit
1 = No card or inserted
0 = Reset or debouncing
bit 16
CARDINS: Card Inserted bit
1 = Card inserted
0 = Reset or debouncing or no card
bit 15-12 Unimplemented: Read as ‘0’
bit 11
Note:
BREN: Buffer Read Enable bit
1 = Buffer read is enabled
0 = Buffer read is disabled
This register is used to recover from errors and for debugging.
DS60001361J-page 664
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 39-6:
SDHCSTAT1: SDHC STATUS REGISTER 1 (CONTINUED)
bit 10
BWEN: Buffer Write Enable bit
1 = Buffer write is enabled
0 = Buffer write is disabled
bit 9
RDACTIVE: Read Transfer Active bit
1 = Data is being transferred
0 = No valid data
bit 8
WRACTIVE: Write Transfer Active bit
1 = Data is being transferred
0 = No valid data
bit 7-3
Unimplemented: Read as ‘0’
bit 2
DLACTIVE: DAT Line Active bit
1 = DAT line is active
0 = DAT line is inactive
bit 1
CINHDAT: Command Inhibit (DAT) bit
1 = A command that uses the DAT line cannot be issued
0 = A command that uses the DAT line can be issued
bit 0
CINHCMD: Command Inhibit (CMD) bit
1 = A command cannot be issued
0 = A command can only be issued using the CMD line
Note:
This register is used to recover from errors and for debugging.
2015-2021 Microchip Technology Inc.
DS60001361J-page 665
PIC32MZ Graphics (DA) Family
REGISTER 39-7:
Bit
Range
31:24
23:16
15:8
7:0
SDHCCON1: SDHC CONTROL REGISTER 1
Bit
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4
U-0
U-0
U-0
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
R/W-0
R/W-0
R/W-0
WKONINT
U-0
—
—
—
—
—
WKONREM
WKONINS
U-0
U-0
U-0
U-0
R/W-0
R/W-0
HC, R/W-0
R/W-0
—
—
—
—
INTBG
RDWTCON
CONTREQ
SBGREQ
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
SDBP
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
CDSSEL
CDTLVL
—
HSEN
DTXWIDTH
—
Legend:
DMASEL
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26
WKONREM: Wake-up Event Enable on SD Card Removal bit
1 = Wake-up event is enabled
0 = Wake-up event is disabled
bit 25
WKONINS: Wake-up Event Enable on SD Card Insertion bit
1 = Wake-up event is enabled
0 = Wake-up event is disabled
bit 24
WKONINT: Wake-up Event Enable on SD Card Interrupt bit
1 = Wake-up event is enabled
0 = Wake-up event is disabled
bit 23-20 Unimplemented: Read as ‘0’
bit 19
INTBG: Interrupt at Block Gap bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 18
RDWTCON: Read Wait Control bit
1 = Read wait control is enabled
0 = Read wait control is disabled
bit 17
CONTREQ: Continue Request bit
A write to this bit is ignored if STOPREQ is set to ‘1’.
1 = Restart
0 = No effect
bit 16
SBGREQ: Stop at Block Gap Request bit
1 = Stop
0 = Transfer
bit 15-9
Unimplemented: Read as ‘0’
bit 8
SDBP: SD Bus Power bit
1 = Bus power is on
0 = Bus power is off
bit 7
CDSSEL: Card Detect Signal Selection bit
1 = The card detect test level is select (for test purposes)
0 = SDCDx is selected (for normal use)
bit 6
CDTLVL: Card Detect Test Level bit
1 = Card is inserted
0 = Card is not inserted
DS60001361J-page 666
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 39-7:
SDHCCON1: SDHC CONTROL REGISTER 1 (CONTINUED)
bit 5
Unimplemented: Read as ‘0’
bit 4-3
DMASEL: DMA Select bits
11 = Reserved
10 = 32-bit address ADMA2 is selected
01 = Reserved
00 = Reserved
bit 2
HSEN: High-Speed Enable bit
1 = High-Speed mode is enabled
0 = Normal Speed mode is enabled
bit 1
DTXWIDTH: Data Transfer Width bit
1 = 4-bit mode
0 = 1-bit mode
bit 0
Unimplemented: Read as ‘0’
2015-2021 Microchip Technology Inc.
DS60001361J-page 667
PIC32MZ Graphics (DA) Family
REGISTER 39-8:
Bit
Range
31:24
23:16
15:8
SDHCCON2: SDHC CONTROL REGISTER 2
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
R/W-0, HC
R/W-0, HC
R/W-0, HC
—
—
—
—
—
SWRDATA
SWRCMD
SWRALL
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
DTOC
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDCLKEN
ICLK
STABLE
ICLKEN
SDCLKDIV
U-0
7:0
—
Legend:
R = Readable bit
-n = Value at POR
U-0
—
U-0
—
W = Writable bit
‘1’ = Bit is set
U-0
—
U-0
—
HC = Hardware Cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26
SWRDATA: Software Reset for DATA Line bit
1 = DMA and part of the data logic are reset
0 = Continue operation
bit 25
SWRCMD: Software Reset for CMD Line bit
1 = Clears Present State and Interrupt Status registers and CMD bits
0 = Continue operation
bit 24
SWRALL: Software Reset for All bit
1 = Issue reset command and reinitialize the SD card
0 = Divided Clock mode is selected
bit 23-20 Unimplemented: Read as ‘0’
bit 19-16 DTOC: Data Time-out Counter Value bits
1111 = Reserved
1110 = Time-out clock x 227
•
•
•
bit 15-8
bit 7-3
bit 2
bit 1
bit 0
0001 = Time-out clock x 214
0000 = Time-out clock x 213
SDCLKDIV: SDCLK Divider Select bits
When 8-bit Divided Clock mode is selected:
0x80 - Base clock divided by 256
0x40 - Base clock divided by 128
0x20 - Base clock divided by 64
0x10 - Base clock divided by 32
0x08 - Base clock divided by 16
0x04 - Base clock divided by 8
0x02 - Base clock divided by 4
0x01 - Base clock divided by 2
0x00 - Base clock
Unimplemented: Read as ‘0’
SDCLKEN: SD Clock Enable bit
1 = SD clock is enabled
0 = SD clock is disabled
ICLKSTABLE: Internal Clock Stable bit
1 = Internal clock is ready
0 = Internal clock is not ready
ICLKEN: Internal Clock Enable bit
1 = Oscillate
0 = Stop
DS60001361J-page 668
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 39-9:
Bit
Range
31:24
23:16
15:8
7:0
SDHCINTSTAT: SDHC INTERRUPT STATUS REGISTER
Bit
Bit
31/23/15/7 30/22/14/6
U-0
Bit
29/21/13/5
Bit
28/20/12/4
U-0
U-0
U-0
Bit
Bit
27/19/11/3 26/18/10/2
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0, HC
R/W-0, HC
—
—
—
—
—
—
ADEIF
ACEIF
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
CLEIF
DEBEIF
DCRCEIF
DTOEIF
CIDXEIF
CEBEIF
CCRCEIF
CTOEIF
R-0, HC
U-0
U-0
U-0
U-0
U-0
U-0
R-0, HC
EIF
—
—
—
—
—
—
CARDIF
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
CARDRIF
CARDIIF
BRRDYIF
BWRDYIF
DMAIF
BGIF
TXCIF
CEIF
Legend:
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25
ADEIF: ADMA Error Interrupt Flag bit
1 = ADMA error has occurred
0 = ADMA error has not occurred
bit 24
ACEIF: Auto CMD12 Error Interrupt Flag bit
1 = Auto CMD12 error has occurred
0 = Auto CMD12 error has not occurred
bit 23
CLEIF: Current-Limit Error Interrupt Flag bit
1 = Current-limit error has occurred
0 = Current-limit error has not occurred
bit 22
DEBEIF: Data End Bit Error Interrupt Flag bit
1 = Data End bit error has occurred
0 = Data End bit error has not occurred
bit 21
DCRCEIF: Data CRC Error Interrupt Flag bit
1 = Data CRC error has occurred
0 = Data CRC error has not occurred
bit 20
DTOEIF: Data Time-out Error Interrupt Flag bit
1 = Data time-out error has occurred
0 = Data time-out error has not occurred
bit 19
CIDXEIF: Command Index Error Interrupt Flag bit
1 = Command index error has occurred
0 = Command index error has not occurred
bit 18
CEBEIF: Command End Bit Error Interrupt Flag bit
1 = End bit error was generated
0 = End bit error was not generated
bit 17
CCRCEIF: Command CRC Error Interrupt Flag bit
1 = Command CRC error has occurred
0 = Command CRC error has not occurred
bit 16
CTOEIF: Command Time-out Error Interrupt Flag bit
1 = Command time-out error has occurred
0 = Command time-out error has not occurred
bit 15
EIF: Error Interrupt Flag bit
This bit is set if any or all bits, 0 through 9, in this register are set.
1 = Error was detected
0 = No error was detected
2015-2021 Microchip Technology Inc.
DS60001361J-page 669
PIC32MZ Graphics (DA) Family
REGISTER 39-9:
SDHCINTSTAT: SDHC INTERRUPT STATUS REGISTER (CONTINUED)
bit 14-9
Unimplemented: Read as ‘0’
bit 8
CARDIF: Card Interrupt Status bit
1 = Generate card interrupt
0 = Do not generate card interrupt
bit 7
CARDRIF: Card Removal Interrupt Flag bit
1 = Card has been removed
0 = Card state is stable or debouncing
bit 6
CARDIIF: Card Insertion Interrupt Flag bit
1 = Card has been inserted
0 = Card state is stable or debouncing
bit 5
BRRDYIF: Buffer Read Ready Interrupt Flag bit
1 = Ready to read buffer
0 = Not ready to read buffer
bit 4
BWRDYIF: Buffer Write Ready Interrupt Flag bit
1 = Ready to write buffer
0 = Not ready to write buffer
bit 3
DMAIF: DMA Interrupt Status bit
1 = DMA interrupt was generated
0 = DMA interrupt was not generated
bit 2
BGIF: Block Gap Interrupt Flag bit
1 = Transaction stopped at block gap
0 = No block gap event has occurred
bit 1
TXEIF: Transfer Complete Interrupt Flag bit
1 = Command execution has completed
0 = Command execution has not completed
bit 0
CEIF: Command Complete Interrupt Flag bit
1 = Command is complete
0 = Command is not complete
DS60001361J-page 670
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 39-10: SDHCINTEN: SDHC INTERRUPT FLAG ENABLE REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0, HC
R/W-0, HC
—
—
—
—
—
—
ADEFIE
ACEFIE
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
CLEFIE
DEBEFIE
DCRCEFIE
DTOEFIE
CIDXEFIE
R-0, HC
U-0
U-0
U-0
U-0
CDEBEFIE CCRCEFIE
U-0
CTOEFIE
U-0
R-0, HC
FTZIE
—
—
—
—
—
—
CARDIE
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
CARDRIE
CARDIIE
BRRDYIE
BWRDYIE
DMAIE
BGIE
TXEIE
CEIE
Legend:
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 21-26 Unimplemented: Read as ‘0’
bit 25
ADEFIE: ADMA Interrupt Flag Error Enable bit
1 = ADMA error interrupt flag is enabled
0 = ADMA error interrupt flag is masked
bit 24
ACEFIE: Auto CMD12 Interrupt Flag Error Enable bit
1 = Auto CMD12 error interrupt flag is enabled
0 = Auto CMD12 error interrupt flag is masked
bit 23
CLEFIE: Current-Limit Interrupt Flag Error Enable bit
1 = Current-limit error interrupt flag is enabled
0 = Current-limit error interrupt flag is masked
bit 22
DEBEFIE: Data End Bit Interrupt Flag Error Enable bit
1 = Data End bit error interrupt flag is enabled
0 = Data End error interrupt flag is masked
bit 21
DCRCEFIE: Data CRC Interrupt Flag Error Enable bit
1 = Data CRC error interrupt flag is enabled
0 = Data CRC error interrupt flag is masked
bit 20
DTOEFIE: Data Time-out Interrupt Flag Error Enable bit
1 = Data time-out error interrupt flag is enabled
0 = Data time-out error interrupt flag is masked
bit 19
CIDXEFIE: Command Index Interrupt Flag Error Enable bit
1 = Command index error interrupt flag is enabled
0 = Command index error interrupt flag is masked
bit 18
CDEBEFIE: Command End Bit Interrupt Flag Error Enable bit
1 = Command End bit error interrupt flag is enabled
0 = Command End bit error interrupt flag is masked
bit 17
CCRCEFIE: Command CRC Interrupt Flag Error Enable bit
1 = Command CRC error interrupt flag is enabled
0 = Command CRC error interrupt flag is masked
bit 16
CTOEFIE: Command Time-out Interrupt Flag Error Enable bit
1 = Command time-out error interrupt flag is enabled
0 = Command time-out error interrupt flag is masked
bit 15
FTZIE: Fixed to Zero Interrupt Flag Enable bit
This bit is set if any or all bits, 0 through 9, in this register are set.
1 = Error was detected
0 = No error was detected
2015-2021 Microchip Technology Inc.
DS60001361J-page 671
PIC32MZ Graphics (DA) Family
REGISTER 39-10: SDHCINTEN: SDHC INTERRUPT FLAG ENABLE REGISTER (CONTINUED)
bit 14-9
Unimplemented: Read as ‘0’
bit 8
CARDIE: Card Interrupt Flag Enable bit
1 = Card interrupt flag is enabled
0 = Card interrupt flag is masked
bit 7
CARDRIE: Card Removal Interrupt Flag Enable bit
1 = Card removal interrupt flag is enabled
0 = Card removal interrupt flag is masked
bit 6
CARDIIE: Card Insertion Interrupt Flag Enable bit
1 = Card insertion interrupt flag is enabled
0 = Card insertion interrupt flag is masked
bit 5
BRRDYIE: Buffer Read Ready Interrupt Flag Enable bit
1 = Buffer read ready interrupt flag is enabled
0 = Buffer read ready interrupt flag is masked
bit 4
BWRDYIE: Buffer Write Ready Interrupt Flag Enable bit
1 = Buffer write ready interrupt flag is enabled
0 = Buffer write ready interrupt flag is masked
bit 3
DMAIE: DMA Interrupt Flag Enable bit
1 = DMA interrupt flag is enabled
0 = DMA interrupt flag is masked
bit 2
BGIE: Block Gap Interrupt Flag Enable bit
1 = Block gap event interrupt flag is enabled
0 = Block gap event interrupt flag is masked
bit 1
TXEIE: Transfer Complete Interrupt Flag Enable bit
1 = Transfer complete interrupt flag is enabled
0 = Transfer complete interrupt flag is masked
bit 0
CEIE: Command Complete Interrupt Flag Enable bit
1 = Command complete interrupt flag is enabled
0 = Command complete interrupt flag is masked
DS60001361J-page 672
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 39-11: SDHCINTSEN: SDHC INTERRUPT SIGNAL ENABLE REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0, HC
R/W-0, HC
—
—
—
—
—
—
ADEISE
ACEISE
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
CLEISE
DEBEISE
DCRCEISE
DTOEISE
CIDXEISE
CEBEISE
CCRCEISE
CTOEISE
R-0, HC
U-0
U-0
U-0
U-0
U-0
U-0
R-0, HC
FTZEISE
—
—
—
—
—
—
CARDISE
R/W-1, HC
R/W-1, HC
R/W-1, HC
R/W-1, HC
R/W-1, HC
R/W-1, HC
R/W-1, HC
R/W-1, HC
DMAISE
BGISE
TXEISE
CEISE
CARDRISE
CARDIISE BRRDYISE BWRDYISE
Legend:
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25
ADEISE: ADMA Error Interrupt Signal Enable bit
1 = ADMA error signal is enabled
0 = ADMA error signal is masked
bit 24
ACEISE: Auto CMD12 Error Interrupt Signal Enable bit
1 = Auto CMD12 error signal is enabled
0 = Auto CMD12 error signal is masked
bit 23
CLEISE: Current-Limit Error Interrupt Signal Enable bit
1 = Current-limit error signal is enabled
0 = Current-limit error signal is masked
bit 22
DEBEISE: Data End Bit Error Interrupt Signal Enable bit
1 = Data end bit error signal is enabled
0 = Data end bit error signal is masked
bit 21
DCRCEISE: Data CRC Error Interrupt Signal Enable bit
1 = Data CRC error signal is enabled
0 = Data CRC error signal is masked
bit 20
DTOEISE: Data Time-out Error Interrupt Signal Enable bit
1 = Data time-out error signal is enabled
0 = Data time-out error signal is masked
bit 19
CIDXEISE: Command Index Error Interrupt Signal Enable bit
1 = Command index error signal is enabled
0 = Command index error signal is masked
bit 18
CEBEISE: Command End Bit Error Interrupt Signal Enable bit
1 = Command End bit error signal is enabled
0 = Command End bit error signal is masked
bit 17
CCRCEISE: Command CRC Error Interrupt Signal Enable bit
1 = Command CRC error signal is enabled
0 = Command CRC error signal is masked
bit 16
CTOEISE: Command Time-out Error Interrupt Signal Enable bit
1 = Command time-out error signal is enabled
0 = Command time-out error signal is masked
bit 15
FTZEISE: Fixed to Zero Error Interrupt Signal Enable bit
This bit is set if any or all bits, 0 through 9, in this register are set.
1 = Error was detected
0 = No error was detected
2015-2021 Microchip Technology Inc.
DS60001361J-page 673
PIC32MZ Graphics (DA) Family
REGISTER 39-11: SDHCINTSEN: SDHC INTERRUPT SIGNAL ENABLE REGISTER (CONTINUED)
bit 14-9
Unimplemented: Read as ‘0’
bit 8
CARDISE: Card Interrupt Signal Enable bit
1 = Card interrupt signal is enabled
0 = Card interrupt signal is masked
bit 7
CARDRISE: Card Removal Interrupt Signal Enable bit
1 = Card removal signal is enabled
0 = Card removal signal is masked
bit 6
CARDIISE: Card Insertion Interrupt Signal Enable bit
1 = Card insertion signal is enabled
0 = Card insertion signal is masked
bit 5
BRRDYISE: Buffer Read Ready Interrupt Signal Enable bit
1 = Buffer read ready signal is enabled
0 = Buffer read ready signal is masked
bit 4
BWRDYISE: Buffer Write Ready Interrupt Signal Enable bit
1 = Buffer write ready signal is enabled
0 = Buffer write ready signal is masked
bit 3
DMAISE: DMA Interrupt Signal Enable bit
1 = DMA interrupt signal is enabled
0 = DMA interrupt signal is masked
bit 2
BGISE: Block Gap Interrupt Signal Enable bit
1 = Block gap event signal is enabled
0 = Block gap event signal is masked
bit 1
TXEISE: Transfer Complete Interrupt Signal Enable bit
1 = Transfer complete signal is enabled
0 = Transfer complete signal is masked
bit 0
CEISE: Command Complete Interrupt Signal Enable bit
1 = Command complete signal is enabled
0 = Command complete signal is masked
DS60001361J-page 674
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 39-12: SDHCSTAT2: SDHC STATUS REGISTER 2
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
U-0
Bit
Bit
Bit
30/22/14/6 29/21/13/5 28/20/12/4
U-0
U-0
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0, HC
U-0
U-0
R-0, HC
R-0, HC
R-0, HC
R-0, HC
R-0, HC
CNISSE
—
—
ACIDXE
ACEBE
ACCRCE
ACTOE
ACNEXEC
Legend:
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
CNISSE: Command Not Issued by Auto CMD12 Error bit
1 = Command was not issued
0 = No error
bit 6-5
Unimplemented: Read as ‘0’
bit 4
ACIDXE: Auto CMD12 Index Error bit
1 = Index error was generated
0 = Index error was not generated
bit 3
ACEBE: Auto CMD12 End Bit Error bit
1 = End bit error was generated
0 = End bit error was not generated
bit 2
ACCRCE: Auto CMD12 CRC Error bit
1 = CRC error was generated
0 = CRC error was not generated
bit 1
ACTOE: Auto CMD12 Time-out Error bit
1 = Time-out error was generated
0 = Time-out error was not generated
bit 0
ACNEXEC: Auto CMD12 Not Executed bit
1 = Auto CMD12 was not executed
0 = Auto CMD12 was executed
2015-2021 Microchip Technology Inc.
DS60001361J-page 675
PIC32MZ Graphics (DA) Family
REGISTER 39-13: SDHCCAP: SDHC CAPABILITIES REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R-0
R-0
R-1
SLOTTYPE
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
R-1, HS
U-0
ASYNCINT
—
—
—
—
VOLT3V3
R1, HS
U-1
R-1, HS
U-0
R-1, HS
U-0
R-0, HS
R-0, HS
SRESUME
—
HISPEED
—
ADMA2
—
R-1, HS
R-1, HS
R-0, HS
R-0, HS
R-1, HS
R-0, HS
R-0, HS
R-0, HS
R-1
U-0
R-0
R-0
R-0
R-1
TOCLKU
—
MBLEN
BASECLK
R-1
R-1
TOCLKFREQ
Legend:
HS = Hardware settable
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 SLOTTYPE: Slot Type
11 = UHS-II Multiple Embedded Devices
10 = Shared Bus Slot (SD Mode)
01 = Embedded Slot for One Device
00 = Removable Card Slot
bit 29
ASYNCINT: Asynchronization Interrupt Support (SD Mode Only)
1 = Asynchronous Interrupt Supported
0 = Asynchronous Interrupt not Supported
bit 28-25 Unimplemented: Read as ‘0’
bit 24
VOLT3V3: 3.3V Voltage Support bit
1 = Voltage of 3.3V is supported
bit 23
SRESUME: Suspend/Resume Support bit
1 = Suspend/resume is supported
0 = Suspend/resume is not supported
bit 22
Unimplemented: Read as ‘1’
bit 21
HISPEED: High-speed Support bit
1 = High speed is supported
0 = High speed is not supported
bit 20
Unimplemented: Read as ‘0’
bit 19
ADMA2: ADMA2 Support bit
1 = ADMA2 is supported
0 = ADMA2 is not supported
bit 18
Unimplemented: Read as ‘0’
bit 17-16 MBLEN: Maximum Block Length bits
11 = Reserved
10 = 2048
01 = 1024
00 = 512
DS60001361J-page 676
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 39-13: SDHCCAP: SDHC CAPABILITIES REGISTER (CONTINUED)
bit 15-8
BASECLK: Base Clock Frequency for SDCLK bits
111111 = 63 MHz
111110 = 62 MHz
111101 = 61 MHz
•
•
•
000010 = 2 MHz
000001 = 1 MHz
000000 = Reserved
bit 7
TOCLKU: Time-out Clock Unit bit
1 = Time-out clock unit is in kHz
0 = Time-out clock unit is in MHz
bit 6
Unimplemented: Read as ‘0’
bit 5-0
TOCLKFREQ: Time-out Clock Frequency bits
The TOCLKU bit defines the unit, either kHz or MHz, of these bit values.
111111 = 63 kHz or 63 MHz
111110 = 62 kHz or 62 MHz
111101 = 61 kHz or 61 MHz
•
•
•
000010 = 2 kHz or 2 MHz
000001 = 1 kHz or 1 MHz
000000 = Reserved
2015-2021 Microchip Technology Inc.
DS60001361J-page 677
PIC32MZ Graphics (DA) Family
REGISTER 39-14: SDHCMAXCAP: SDHC MAXIMUM CURRENT CAPABILITIES REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-x, HS
R-x, HS
R-x, HS
R-x, HS
R-x, HS
R-x, HS
R-x, HS
R-x, HS
MC3V3
Legend:
HS = Hardware Set
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-8
Unimplemented: Read as ‘0’
bit 7-0
MC3V3: Maximum Current for 3.3V bits
11111111 = 1020 mA
11111110 = 1016 mA
11111101 = 1012 mA
x = Bit is unknown
•
•
•
00000011 = 12 mA
00000010 = 8 mA
00000001 = 4 mA
00000000 = Reserved
DS60001361J-page 678
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 39-15: SDHCFE: SDHC FORCE EVENT REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
U-0
U-0
U-0
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
W-0, HC
W-0, HC
FEACE
—
—
—
—
—
—
FEADE
W-0, HC
W-0, HC
W-0, HC
W-0, HC
W-0, HC
W-0, HC
W-0, HC
W-0, HC
FECLE
FEDEBE
FEDCRCE
FEDTOE
FEIDXE
FECEBE
FECCRCE
FECTOE
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
W-0
U-0
U-0
W-0
W-0
W-0
W-0
W-0
FECNIACE
—
—
FEACIDXE FEACEBE FEACCRCE FEACTOE FEACNEE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25
FEADE: Force Event for ADMA Error bit
1 = Interrupt was generated
0 = Interrupt was not generated
bit 24
FEACE: Force Event for Auto CMD 12 Error bit
1 = Interrupt was generated
0 = Interrupt was not generated
bit 23
FECLE: Force Event for Current-Limit Error bit
1 = Interrupt was generated
0 = Interrupt was not generated
bit 22
FEDEBE: Force Event for Data End Bit Error bit
1 = Interrupt was generated
0 = Interrupt was not generated
bit 21
FEDCRCE: Force Event for Data CRC Error bit
1 = Interrupt was generated
0 = Interrupt was not generated
bit 20
FEDTOE: Force Event for Data Time-out Error bit
1 = Interrupt was generated
0 = Interrupt was not generated
bit 19
FEIDXE: Force Event for Command Index Error bit
1 = Interrupt was generated
0 = Interrupt was not generated
bit 18
FECEBE: Force Event for Command End Bit Error bit
1 = Interrupt was generated
0 = Interrupt was not generated
bit 17
FECCRCE: Force Event for Command CRC Error bit
1 = Interrupt was generated
0 = Interrupt was not generated
bit 16
FECTOE: Force Event for Command Time-out Error bit
1 = Interrupt was generated
0 = Interrupt was not generated
bit 15-8
Unimplemented: Read as ‘0’
2015-2021 Microchip Technology Inc.
DS60001361J-page 679
PIC32MZ Graphics (DA) Family
REGISTER 39-15: SDHCFE: SDHC FORCE EVENT REGISTER (CONTINUED)
bit 7
FECNIACE: Force Event for Command Not Issued by Auto CMD12 Error bit
1 = Interrupt was generated
0 = Interrupt was not generated
bit 6-5
Unimplemented: Read as ‘0’
bit 4
FEACIDXE: Force Event for Auto CMD12 Index Error bit
1 = Interrupt was generated
0 = Interrupt was not generated
bit 3
FEACEBE: Force Event for Auto CMD12 End Bit Error bit
1 = Interrupt was generated
0 = Interrupt was not generated
bit 2
FEACCRCE: Force Event for Auto CMD12 CRC Error bit
bit 1
FEACTOE: Force Event for Auto CMD12 Time-out Error bit
1 = Interrupt was generated
0 = Interrupt was not generated
bit 0
FEACNEE: Force Event for Auto CMD12 Not Executed Error bit
1 = Interrupt was generated
0 = Interrupt was not generated
DS60001361J-page 680
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 39-16: SDHCADESTAT: SDHC ADMA ERROR STATUS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
R-0, HC
R-0, HC
R-0, HC
—
—
—
—
—
ADLMERR
Legend:
ADERRST
HC = Hardware Cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-3
Unimplemented: Read as ‘0’
bit 2
ADLMERR: ADMA Length Mismatch Error bit
1 = Length mismatch error has occurred
0 = Length mismatch error has not occurred
bit 1-0
ADERRST: ADMA Error State bits
11 = Data transfer error
10 = Reserved
01 = Fetch descriptor error
00 = Stop DMA error
x = Bit is unknown
REGISTER 39-17: SDHCAADDR: SDHC ADMA ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR
R/W-0
ADDR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-0
x = Bit is unknown
ADDR: ADMA Address Register bits
These bits contain the address of the executing command of the ADMA descriptor table.
2015-2021 Microchip Technology Inc.
DS60001361J-page 681
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 682
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
40.0
Note:
POWER-SAVING FEATURES
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. It is not intended to be a
comprehensive reference source. To complement the information in this data
sheet, refer to Section 10. “PowerSaving Features” (DS60001130), which
is available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
This section describes the power-saving features on
the PIC32MZ DA devices. These devices have multiple
power domains and offer various methods and modes
that allow the user to balance the power consumption
with device performance.
40.1
Power Saving with CPU Running
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency,
lowering the speed of PBCLK7, or selecting a lower
power clock source (i.e., LPRC or SOSC).
In addition, the Peripheral Bus Scaling mode is available
for each peripheral bus where peripherals are clocked at
reduced speed by selecting a higher divider for the
associated PBCLKx, or by disabling the clock
completely.
40.2
Power-Saving with CPU Halted
Peripherals and the CPU can be Halted or disabled to
further reduce power consumption.
40.2.1
SLEEP MODE
Sleep mode has the lowest power consumption of the
device power-saving operating modes. The CPU and
most peripherals are Halted and the associated clocks
are disabled. Select peripherals can continue to
operate in Sleep mode and can be used to wake the
device from Sleep. See the individual peripheral
module sections for descriptions of behavior in Sleep
mode.
• Some peripherals can continue to operate at limited
functionality in Sleep mode. These peripherals
include I/O pins that detect a change in the input
signal, WDT, ADC, UART and peripherals that use
an external clock input or the internal LPRC
oscillator (e.g., RTCC, Timer1 and Input Capture).
• I/O pins continue to sink or source current in the
same manner as they do when the device is not in
Sleep
The processor will exit, or ‘wake-up’, from Sleep on one
of the following events:
• On any interrupt from an enabled source that is
operating in Sleep. The interrupt priority must be
greater than the current CPU priority.
• On any form of device Reset
• On a WDT time-out
If the interrupt priority is lower than or equal to the
current priority, the CPU will remain Halted, but the
peripheral bus clocks will start running and the device
will enter into Idle mode.
40.2.2
IDLE MODE
In Idle mode, the CPU is Halted; however, all clocks are
still enabled. This allows peripherals to continue to
operate. Peripherals can be individually configured to
Halt when entering Idle by setting their respective SIDL
bit. Latency, when exiting Idle mode, is very low due to
the CPU oscillator source remaining active.
The device enters Idle mode when the SLPEN bit
(OSCCON) is clear and a WAIT instruction is
executed.
The processor will wake or exit from Idle mode on the
following events:
• On any interrupt event for which the interrupt source
is enabled. The priority of the interrupt event must
be greater than the current priority of the CPU. If the
priority of the interrupt event is lower than or equal
to current priority of the CPU, the CPU will remain
Halted and the device will remain in Idle mode.
• On any form of device Reset
• On a WDT time-out interrupt
Sleep mode includes the following characteristics:
• There can be a wake-up delay based on the
oscillator selection
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode
• The BOR circuit remains operative during Sleep
mode
• The WDT, if enabled, is not automatically cleared
prior to entering Sleep mode
2015-2021 Microchip Technology Inc.
DS60001361J-page 683
PIC32MZ Graphics (DA) Family
40.2.3
DEEP SLEEP MODE
Deep Sleep mode brings the device into its lowest
power consumption state without requiring the use of
external switches to remove power from the device.
• Deep Sleep
In this mode, the CPU, RAM and most peripherals
are powered down. Power is maintained to the
DSGPR0 register and one or more of the RTCC,
DSWDT and DSGPR1 through DSGPR32
registers.
Which of these peripherals is active depends on the
state of the following register bits when Deep Sleep
mode is entered:
• RTCDIS (DSCON)
This bit must be set to disable the RTCC in Deep
Sleep mode (see Register 40-1).
• DSWDTEN (DEVCFG2)
This Configuration bit must be set to enable the
DSWDT register in Deep Sleep mode (see
Register 41-5)
• DSGPREN (DSCON)
This bit must be set to enable the DSGPR1
through DSGPR32 registers in Deep Sleep mode
(see Register 40-1).
Note:
The Deep Sleep Control registers can
only be accessed after the system unlock
sequence has been performed. In addition, the Deep Sleep Control registers
must be written twice.
In addition to the conditionally enabled peripherals
described above, the MCLR filter and INT0 pin are
enabled in Deep Sleep mode.
DS60001361J-page 684
40.2.4
VBAT MODE
VBAT mode is similar to Deep Sleep mode, except that
the device is powered from the VBAT pin. VBAT mode
is controlled strictly by hardware, without any software
intervention. Device enters VBAT mode upon VDDCORE
Power-on Reset (refer to Table 44-4 for definitions of
VPORCORE and VBATSW). An external power source
must be connected to the VBAT pin before power is
removed from VDDIO/VDDCORE to enter VBAT mode.
VBAT is the lowest battery-powered mode that can
maintain an RTCC. Wake-up from VBAT mode can only
occur when VDDIO/VDDCORE is reapplied. The wake-up
will appear to be a POR to the rest of the device.
In VBAT mode, the Deep Sleep Watchdog Timer is disabled. The RTCC and DSGPR1 through DSGPR32
registers may be enabled or disabled depending on the
state of the RTCDIS bit (DSCON) and the
DSGPREN bit (DSCON), respectively. Deep
Sleep Persistent General Purpose Register 0
(DSGPR0) is always enabled in VBAT mode.
40.2.5
XLP POWER-SAVING MODES
Figure 40-1 shows a block diagram of the system
domain for XLP devices and the related power-saving
features. The various blocks are controlled by the
following Configuration bit settings and SFRs:
•
•
•
•
•
•
•
•
•
•
DSBOREN (DEVCFG2)
DSEN (DSCON)
DSGPREN (DSCON)
DSWDTEN (DEVCFG2)
DSWDTOSC (DEVCFG2)
RELEASE (DSCON)
RTCCLKSEL (RTCCON )
RTCDIS (DSCON)
SLPEN (OSCCON)
VREGS (PWRCON)
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
FIGURE 40-1:
XLP DEVICE BLOCK DIAGRAM
RTCDIS
VBAT
Low-Power
VREG
RTCCLKSEL
Timers
LPRC
SOSCI
RTCC
SOSC
VDDIO
DSWDT
SOSCO
VBPOR
VDDCORE
DSBOREN
DSBOR
POR
MCLR
Monitors
DSGPREN
DSGPR1-32
BOR
MCLR
DSWDTOSC
DSWDTEN
DSGPR0
Deep Sleep
Persistent General
Purpose Registers
Regulators
Main VREG
CPU
SRAM
Peripherals
Flash VREG
Idle/Sleep (SLPEN)
DSEN
VREGS
Program Flash
Memory
RELEASE
I/O Lock Logic
Peripheral I/O
2015-2021 Microchip Technology Inc.
DS60001361J-page 685
Deep Sleep (DSCTRL) Control Registers
Register
Name(2)
DSCON
0220
0240
0244
0248
024C
0250
0254
0258
2015-2021 Microchip Technology Inc.
025C
0260
0264
0268
DSWAKE
DSGPR0(1)
DSGPR1
DSGPR2
DSGPR3
DSGPR4
DSGPR5
DSGPR6
DSGPR7
DSGPR8
DSGPR9
DSGPR10
DSGPR11
Legend:
Note 1:
2:
Bit Range
Virtual Address
(BF8C_#)
Bits
0200
0210
POWER-SAVING MODES REGISTER SUMMARY
31/15
30/14
29/13
28/12
27/11
26/10
25/9
31:16
—
—
15:0
DSEN
—
—
—
—
—
—
—
31:16
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
DSGPREN RTCDIS
17/1
16/0
All Resets(1)
TABLE 40-1:
24/8
23/7
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
—
—
—
—
—
RTCCWDIS
—
—
—
—
—
—
DSBOR
—
—
—
—
—
—
—
—
—
0000
DSINT0
DSFLT
—
—
DSWDT
DSRTC
DSMCLR
—
—
0000
—
0000
RELEASE 0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
— = unimplemented, read as ‘0’.
The DSGPR0 register is persistent in all device modes of operation.
The Deep Sleep Control registers can only be accessed after the system unlock sequence has been performed. In addition, these registers must be written twice.
PIC32MZ Graphics (DA) Family
DS60001361J-page 686
40.3
Register
Name(2)
Bit Range
Bits
026C
DSGPR12
31:16
0270
0274
0278
0280
0284
0288
028C
0290
0294
0298
029C
DS60001361J-page 687
02A0
02A4
DSGPR14
DSGPR15
DSGPR16
DSGPR17
DSGPR18
DSGPR19
DSGPR20
DSGPR21
DSGPR22
DSGPR23
DSGPR24
DSGPR25
DSGPR26
Legend:
Note 1:
2:
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
— = unimplemented, read as ‘0’.
The DSGPR0 register is persistent in all device modes of operation.
The Deep Sleep Control registers can only be accessed after the system unlock sequence has been performed. In addition, these registers must be written twice.
PIC32MZ Graphics (DA) Family
027C
DSGPR13
31/15
All Resets(1)
POWER-SAVING MODES REGISTER SUMMARY
Virtual Address
(BF8C_#)
2015-2021 Microchip Technology Inc.
TABLE 40-1:
Virtual Address
(BF8C_#)
Register
Name(2)
Bit Range
Bits
02A8
DSGPR27
31:16
02AC DSGPR28
02B0
02B4
02B8
DSGPR29
DSGPR30
DSGPR31
02BC DSGPR32
Legend:
Note 1:
2:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets(1)
POWER-SAVING MODES REGISTER SUMMARY
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
31:16
Deep Sleep Persistent General Purpose bits
0000
15:0
Deep Sleep Persistent General Purpose bits
0000
— = unimplemented, read as ‘0’.
The DSGPR0 register is persistent in all device modes of operation.
The Deep Sleep Control registers can only be accessed after the system unlock sequence has been performed. In addition, these registers must be written twice.
PIC32MZ Graphics (DA) Family
DS60001361J-page 688
TABLE 40-1:
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 40-1:
Bit
Range
31:24
23:16
15:8
7:0
DSCON: DEEP SLEEP CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
HC, R/W-y
(1)
U-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
—
DSGPREN
RTCDIS
—
—
—
RTCCWDIS
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
DSBOR(2)
RELEASE
DSEN
Legend:
HC = Hardware Cleared
y = Value set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
DSEN: Deep Sleep Enable bit(1)
1 = Deep Sleep mode is entered on a WAIT instruction
0 = Sleep mode is entered on a WAIT instruction
bit 14
Unimplemented: Read as ‘0’
bit 13
DSGPREN: General Purpose Registers Enable bit
1 = General purpose register retention is enabled in Deep Sleep mode
0 = No general purpose register retention in Deep Sleep mode
bit 12
RTCDIS: RTCC Module Disable bit
1 = RTCC module is not enabled
0 = RTCC module is enabled
bit 11-9
Unimplemented: Read as ‘0’
bit 8
RTCCWDIS: RTCC Wake-up Disable bit
1 = Wake-up from RTCC is disabled
0 = Wake-up from RTCC is enabled
bit 7-2
Unimplemented: Read as ‘0’
bit 1
DSBOR: Deep Sleep BOR Event Status bit(2)
1 = DSBOREN was enabled and VDDIO dropped below the DSBOR threshold during Deep Sleep(2)
0 = DSBOREN was disabled, or VDDIO did not drop below the DSBOR threshold during Deep Sleep
bit 0
RELEASE: I/O Pin State Release bit
1 = Upon waking from Deep Sleep, the I/O pins maintain their previous states
0 = Release I/O pins and allow their respective TRIS and LAT bits to control their states
Note 1:
2:
To enter Deep Sleep mode, Sleep mode must be executed after setting the DSEN bit.
Unlike all other events, a Deep Sleep Brown-out Reset (BOR) event will not cause a wake-up from Deep
Sleep mode; this bit is present only as a status bit.
2015-2021 Microchip Technology Inc.
DS60001361J-page 689
PIC32MZ Graphics (DA) Family
REGISTER 40-2:
Bit
Range
31:24
23:16
15:8
7:0
DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0, HS
—
—
—
—
—
—
—
DSINT0
R/W-0, HS
U-0
U-0
R/W-0, HS
R/W-0, HS
R/W-0, HS
U-0
U-0
DSFLT
—
—
DSWDT
DSRTC
DSMCLR
—
—
Legend:
HS = Hardware Set
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-9
Unimplemented: Read as ‘0’
bit 8
DSINT0: Interrupt-on-Change bit
1 = Interrupt-on-change was asserted during Deep Sleep
0 = Interrupt-on-change was not asserted during Deep Sleep
bit 7
DSFLT: Deep Sleep Fault Detected bit
1 = A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been
corrupted
0 = No Fault was detected during Deep Sleep
bit 6-5
Unimplemented: Read as ‘0’
bit 4
DSWDT: Deep Sleep Watchdog Timer Time-out bit
1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep
0 = The Deep Sleep Watchdog Timer did not time-out during Deep Sleep
bit 3
DSRTC: Real-Time Clock and Calendar Alarm bit
1 = The Real-Time Clock and Calendar triggered an alarm during Deep Sleep
0 = The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep
bit 2
DSMCLR: MCLR Event bit
1 = The MCLR pin was active and was asserted during Deep Sleep
0 = The MCLR pin was not active, or was active, but not asserted during Deep Sleep
bit 1-0
Unimplemented: Read as ‘0’
Note:
All bits in this register are cleared when the DSEN bit (DSCON) is set.
DS60001361J-page 690
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 40-3:
Bit
Range
31:24
23:16
15:8
7:0
DSGPRX: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER ‘x’
(x = 0 THROUGH 32)
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Deep Sleep Persistent General Purpose bits
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Deep Sleep Persistent General Purpose bits
R/W-x
R/W-x
R/W-x
Deep Sleep Persistent General Purpose bits
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Deep Sleep Persistent General Purpose bits
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 Deep Sleep Persistent General Purpose bits
Note:
The contents of the DSGPR0 register are retained, even in Deep Sleep and VBAT modes. The DSPGR1
through DSPGR32 registers are disabled by default in Deep Sleep and VBAT modes, but can be enabled
with the DSGPREN bit (DSCON). All register bits are reset only if a VDDCORE Power-on Reset (POR)
event outside of Deep-Sleep mode.
2015-2021 Microchip Technology Inc.
DS60001361J-page 691
PIC32MZ Graphics (DA) Family
40.4
Peripheral Module Disable
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum
power consumption state. The control and status
registers associated with the peripheral are also
disabled, so writes to those registers do not have
effect and read values are invalid.
To disable a peripheral, the associated PMDx bit must
be set to ‘1’. To enable a peripheral, the associated
PMDx bit must be cleared (default). See Table 40-2 for
more information.
Note:
Disabling a peripheral module while it's
ON bit is set, may result in undefined
behavior. The ON bit for the associated
peripheral module must be cleared prior to
disable a module via the PMDx bits.
Note:
When a peripheral is disabled with the
PMD register, it resets the Interrupt Enable
Control (IECx) and Interrupt Priority Control
(IPCx) registers. When the peripheral is reenabled with the PMD register, the IECx
and IPCx registers must be configured
again.
DS60001361J-page 692
2015-2021 Microchip Technology Inc.
Register
Name
0040
PMD1
0050
0060
0070
0080
PERIPHERAL MODULE DISABLE REGISTER SUMMARY
PMD2
PMD3
PMD4
PMD5
PMD6
00A0
PMD7
Legend:
Note 1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
31:16
—
—
15:0
—
—
31:16
—
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
—
—
—
—
—
CVRMD
—
—
—
—
—
—
16/0
—
—
—
—
—
HLVDMD
—
—
—
—
—
CTMUMD
—
—
—
—
—
—
—
ADCMD
0000
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
OC9MD
OC8MD
OC7MD
OC6MD
OC5MD
OC4MD
OC3MD
CMP2MD CMP1MD 0000
OC2MD
OC1MD
15:0
—
—
—
—
—
—
—
IC9MD
IC8MD
IC7MD
IC6MD
IC5MD
IC4MD
IC3MD
IC2MD
IC1MD
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
—
—
—
—
—
—
—
T9MD
T8MD
T7MD
T6MD
T5MD
T4MD
T3MD
T2MD
T1MD
0000
31:16
—
—
CAN2MD
CAN1MD
—
—
—
USBMD
—
—
—
I2C5MD
I2C4MD
I2C3MD
I2C2MD
I2C1MD
0000
U6MD
U5MD
U4MD
U3MD
U2MD
U1MD
0000
—
GPUMD
EBIMD
PMPMD
0000
15:0
—
—
SPI6MD
SPI5MD
SPI4MD
SPI3MD
SPI2MD
SPI1MD
—
—
31:16
—
—
—
ETHMD
—
—
—
—
SQI1MD
—
15:0
—
—
—
REFO5MD REFO4MD REFO3MD REFO2MD REFO1MD
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
DDR2CMD
—
—
—
—
—
CRYPTMD
—
RNGMD
—
—
—
—
1000
15:0
—
—
—
—
—
—
—
—
—
—
—
DMAMD
—
—
—
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset values are dependent on the device variant.
SDHCMD GLCDMD
DS60001361J-page 693
PIC32MZ Graphics (DA) Family
0090
Bit Range
Bits
All Resets(1)
Virtual Address
(BF80_#)
2015-2021 Microchip Technology Inc.
TABLE 40-2:
PIC32MZ Graphics (DA) Family
TABLE 40-3:
PERIPHERAL MODULE DISABLE BITS AND LOCATIONS
Peripheral
ADC
PMDx Bit Name
Register Name and Bit Location
ADCMD
PMD1
CTMUMD
PMD1
Comparator Voltage Reference
CVRMD
PMD1
High/Low-Voltage Detect
HLVDMD
PMD1
Comparator 1
CMP1MD
PMD2
Comparator 2
CMP2MD
PMD2
Input Capture 1
IC1MD
PMD3
Input Capture 2
IC2MD
PMD3
Input Capture 3
IC3MD
PMD3
Input Capture 4
IC4MD
PMD3
Input Capture 5
IC5MD
PMD3
Input Capture 6
IC6MD
PMD3
Input Capture 7
IC7MD
PMD3
Input Capture 8
IC8MD
PMD3
CTMU
Input Capture 9
IC9MD
PMD3
Output Compare 1
OC1MD
PMD3
Output Compare 2
OC2MD
PMD3
Output Compare 3
OC3MD
PMD3
Output Compare 4
OC4MD
PMD3
Output Compare 5
OC5MD
PMD3
Output Compare 6
OC6MD
PMD3
Output Compare 7
OC7MD
PMD3
Output Compare 8
OC8MD
PMD3
Output Compare 9
OC9MD
PMD3
Timer1
T1MD
PMD4
Timer2
T2MD
PMD4
Timer3
T3MD
PMD4
Timer4
T4MD
PMD4
Timer5
T5MD
PMD4
Timer6
T6MD
PMD4
Timer7
T7MD
PMD4
Timer8
T8MD
PMD4
Timer9
T9MD
PMD4
UART1
U1MD
PMD5
UART2
U2MD
PMD5
UART3
U3MD
PMD5
UART4
U4MD
PMD5
UART5
U5MD
PMD5
UART6
SPI1
SPI2
Note 1:
2:
U6MD
PMD5
SPI1MD
PMD5
SPI2MD
PMD5
The USB module must not be busy after clearing the associated ON bit and prior to setting the USBMD
bit.
This peripheral is not available on all devices. Refer to the pin feature tables (Table 2 through Table 4) to
determine availability.
DS60001361J-page 694
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 40-3:
PERIPHERAL MODULE DISABLE BITS AND LOCATIONS (CONTINUED)
Peripheral
PMDx Bit Name
Register Name and Bit Location
SPI3
SPI3MD
PMD5
SPI4
SPI4MD
PMD5
SPI5
SPI5MD
PMD5
SPI6
SPI6MD
PMD5
I2C1
I2C1MD
PMD5
I2C2
I2C2MD
PMD5
I2C3
I2C3MD
PMD5
I2C4
I2C4MD
PMD5
I2C5
I2C5MD
PMD5
USB(1)
USBMD
PMD5
CAN1
CAN1MD
PMD5
CAN2MD
PMD5
REFO1MD
PMD6
CAN2
Reference Clock Output 1
Reference Clock Output 2
REFO2MD
PMD6
Reference Clock Output 3
REFO3MD
PMD6
Reference Clock Output 4
REFO4MD
PMD6
Reference Clock Output 5
REFO5MD
PMD6
PMP
PMPMD
PMD6
EBI
EBIMD
PMD6
2-D GPU
GPUMD
PMD6
GLCD
GLCDMD
PMD6
SDHC
SDHCMD
PMD6
SQI1
SQI1MD
PMD6
Ethernet
ETHMD
PMD6
DMA
DMAMD
PMD7
RNG
Crypto(2)
DDR2 SDRAM Controller(2)
Note 1:
2:
RNGMD
PMD7
CRYPTMD
PMD7
DDR2CMD
PMD7
The USB module must not be busy after clearing the associated ON bit and prior to setting the USBMD
bit.
This peripheral is not available on all devices. Refer to the pin feature tables (Table 2 through Table 4) to
determine availability.
2015-2021 Microchip Technology Inc.
DS60001361J-page 695
PIC32MZ Graphics (DA) Family
40.4.1
CONTROLLING CONFIGURATION
CHANGES
Because peripherals can be disabled during run time,
some restrictions on disabling peripherals are needed
to prevent accidental configuration changes. PIC32MZ
DA devices include two features to prevent alterations
to enabled or disabled peripherals:
• Control Register Lock Sequence
• Configuration Bit Select Lock
40.4.1.1
Control Register Lock
Under normal operation, writes to the PMDx registers
are not allowed. Attempted writes appear to execute
normally, but the contents of the registers remain
unchanged. To change these registers, they must be
unlocked in hardware. The register lock is controlled by
the PMDLOCK Configuration bit (CFGCON).
Setting the PMDLOCK bit prevents writes to the control
registers and clearing the PMDLOCK bit allows writes.
To set or clear the PMDLOCK bit, an unlock sequence
must be executed. Refer to Section 42. “Oscillators
with Enhanced PLL” (DS60001250) in the “PIC32
Family Reference Manual” for details.
40.4.1.2
Configuration Bit Select Lock
As an additional level of safety, the device can be configured to prevent more than one write session to the
PMDx registers. The PMDL1WAY Configuration bit
(DEVCFG3) blocks the PMDLOCK bit from being
cleared after it has been set once. If the PMDLOCK bit
remains set, the register unlock procedure does not
execute, and the PPS control registers cannot be written to. The only way to clear the bit and re-enable PMD
functionality is to perform a device Reset.
DS60001361J-page 696
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
41.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet,
refer
to
Section
32.
“Configuration”
(DS60001124)
and
Section
33.
“Programming
and
Diagnostics” (DS60001129), which are
available from the Documentation >
Reference Manual section of the
Microchip
PIC32
web
site
(www.microchip.com/pic32).
PIC32MZ DA devices include several features
intended to maximize application flexibility and reliability and minimize cost through elimination of external
components. These are:
•
•
•
•
Flexible device configuration
Joint Test Action Group (JTAG) interface
In-Circuit Serial Programming™ (ICSP™)
Internal temperature sensor
41.1
The following run-time programmable Configuration
registers provide additional configuration control:
• CFGCON: Configuration Control Register
• CFGEBIA: External Bus Interface Address Pin
Configuration Register
• CFGEBIC: External Bus Interface Control Pin
Configuration Register
• CFGPG: Permission Group Configuration
Register
• CFGCON2: Configuration Control Register 2
• CFGMPLL: Memory PLL Configuration Register
In addition, the DEVID register (see Register 41-15)
provides device and revision information and the
DEVSN0 and DEVSN3 registers contain a unique
serial number of the device (see Register 41-16).
Note:
Do not use word program operation
(NVMOP = 0001) when programming the device words that are described
in this chapter.
Configuration Bits
PIC32MZ DA devices contain two Boot Flash memories (Boot Flash 1 and Boot Flash 2), each with an
associated configuration space. These configuration
spaces can be programmed to contain various device
configurations. Configuration space that is aliased by
the Lower Boot Alias memory region is used to provide
values for the following Configuration registers. See
4.1.1 “Boot Flash Sequence and Configuration
Spaces” for more information.
• DEVSIGN0/ADEVSIGN0: Device Signature Word
0 Register
• DEVCP0/ADEVCP0: Device Code-Protect 0
Register
• DEVCFG0/ADEVCFG0: Device/Alternate Device
Configuration Word 0
• DEVCFG1/ADEVCFG1: Device Configuration
Word 1
• DEVCFG2/ADEVCFG2: Device Configuration
Word 2
• DEVCFG3/ADEVCFG3: Device Configuration
Word 3
• DEVCFG4/ADEVCFG4: Device Configuration
Word 4
• DEVADCx: Device ADC Calibration Word ‘x’ (‘x’ =
0-4, 7)
2015-2021 Microchip Technology Inc.
DS60001361J-page 697
Registers
DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
FFBC DEVCFG4
FFC0 DEVCFG3
FFC4 DEVCFG2
FFC8 DEVCFG1
FFCC DEVCFG0
31/15
30/14
29/13
31:16
—
—
—
15:0
—
—
—
31:16
—
—
FFD4 DEVCP2
FFD8 DEVCP1
FFDC DEVCP0
FFE0 DEVSIGN3
FFE4 DEVSIGN2
2015-2021 Microchip Technology Inc.
FFE8 DEVSIGN1
FFEC DEVSIGN0
Legend:
27/11
—
—
26/10
25/9
24/8
—
—
—
—
FETHIO
FMIIEN
SWDTPS
IOL1WAY PMDL1WAY PGL1WAY
15:0
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
xxxx
—
—
—
—
—
—
—
—
xxxx
—
—
—
—
EXTDDRSIZE
xxxx
USERID
31:16
—
15:0
—
UPLLFSEL
—
FDSEN
DSWDTEN DSWDTOSC
31:16 FDMTEN
xxxx
DSWDTPS
FPLLMULT
FPLLICLK
DMTCNT
DSBOREN VBATBOREN
FPLLRNG
FWDTWINSZ
FWDTEN
WINDIS
FCKSM
—
—
—
OSCIOFNC
POSCMOD
IESO
FSOSCEN
31:16
—
—
—
POSCAGC
—
POSCTYPE
—
—
POSCBOOST
FECCCON
EJTAGBEN
DBGPER
—
WDTSPGM
15:0
15:0 SMCLR
FFD0 DEVCP3
28/12
All Resets
Bit Range
Bits
Register
Name
Virtual Address
(BFC0_#)
TABLE 41-1:
FPLLODIV
xxxx
FPLLIDIV
xxxx
WDTPS
DMTINTV
xxxx
FNOSC
POSCGAIN
SOSCBOOST
ICESEL
JTAGEN
xxxx
SOSCGAIN
xxxx
—
FSLEEP
—
BOOTISA
TRCEN
DEBUG
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
CP
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC32MZ Graphics (DA) Family
DS60001361J-page 698
41.2
FF3C ADEVCFG4
FF40 ADEVCFG3
FF44 ADEVCFG2
FF48 ADEVCFG1
FF4C ADEVCFG0
FF54 ADEVCP2
FF58 ADEVCP1
FF5C ADEVCP0
FF60 ADEVSIGN3
FF64 ADEVSIGN2
FF68 ADEVSIGN1
FF6C ADEVSIGN0
30/14
29/13
31:16
—
—
—
15:0
—
—
—
31:16
—
—
28/12
27/11
—
—
26/10
25/9
24/8
—
—
—
—
FETHIO
FMIIEN
SWDTPS
IOL1WAY PMDL1WAY PGL1WAY
15:0
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
xxxx
—
—
—
—
—
—
—
—
xxxx
—
—
—
—
EXTDDRSIZE
xxxx
USERID
31:16
—
15:0
—
UPLLFSEL
—
FDSEN
DSWDTEN DSWDTOSC
31:16 FDMTEN
FPLLICLK
DMTCNT
15:0
FCKSM
31:16
—
EJTAGBEN
15:0 SMCLR
FWDTWINSZ FWDTEN
—
—
—
—
—
DBGPER
xxxx
DSWDTPS
FPLLMULT
All Resets
Bit Range
31/15
DSBOREN VBATBOREN
FPLLRNG
WINDIS
—
WDTSPGM
FSOSCEN
FPLLODIV
xxxx
FPLLIDIV
xxxx
WDTPS
DMTINTV
xxxx
OSCIOFNC
POSCMOD
IESO
FNOSC
POSCAGC
—
POSCTYPE
—
—
POSCBOOST
POSCGAIN
SOSCBOOST
SOSCGAIN
xxxx
—
FSLEEP
FECCCON
—
BOOTISA
TRCEN
ICESEL
JTAGEN
DEBUG
xxxx
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
CP
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS60001361J-page 699
PIC32MZ Graphics (DA) Family
FF50 ADEVCP3
Legend:
ADEVCFG: ALTERNATE DEVICE CONFIGURATION WORD SUMMARY
Bits
Register
Name
Virtual Address
(BFC0_#)
2015-2021 Microchip Technology Inc.
TABLE 41-2:
DEVID
SYSKEY
00C0 CFGEBIA
00D0 CFGEBIC
00E0
CFGPG
00F0 CFGCON2
0100 CFGMPLL
30/14
31:16
—
—
15:0
—
—
31:16
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
IOLOCK PMDLOCK PGLOCK
Virtual Address
(BFC5_#)
Register
Name
20/4
—
—
—
—
—
—
ECCCON
19/3
18/2
17/1
—
—
ICACLK
JTAGEN
TROEN
—
16/0
OCACLK 0000
TDOEN
DEVID
31:16
31:16
—
15:0
EBIA15EN
EBIA14EN EBIA13EN EBIA12EN EBIA11EN EBIA10EN EBIA9EN EBIA8EN
31:16
EBI
RDYINV3
EBI
RDYINV2
15:0
—
—
EBIWEEN EBIOEEN
31:16
—
—
GPUPG
GLCDPG
15:0
CAN2PG
CAN1PG
—
—
—
—
—
—
—
EBI
RDYINV1
—
—
—
15:0
MPLLRDY
—
—
EBI
RDYEN3
EBI
RDYEN2
—
—
31:16 GLCDPINEN GLCDMODE SDCDEN SDWPEN
31:16
xxxx
0000
SYSKEY
15:0
—
EBI
RDYEN1
0000
EBIA23EN EBIA22EN EBIA21EN EBIA20EN EBIA19EN EBIA18EN EBIA17EN EBIA16EN 0000
EBIA7EN
—
—
EBIA6EN
—
EBIA5EN
—
EBIA4EN
—
EBIBSEN1 EBIBSEN0 EBICSEN3 EBICSEN2 EBICSEN1 EBICSEN0
CRYPTPG
FCPG
USBPG
—
—
MPLLODIV2
EBIA2EN
EBIA1EN
EBIA0EN 0000
—
—
EBI
RDYLVL
EBIRPEN 0000
—
—
EBIDEN1
EBIDEN0 0000
SQI1PG
SDHCPG
ETHPG
DMAPG
—
CPUPG
SDRDFTHR
MPLLDIS
EBIA3EN
—
SDWRFTHR
—
MPLL
MPLL
VREGRDY VREGDIS
MPLLODIV1
MPLLMULT
—
—
INTVREFCON
0000
0000
0000
—
SDWPPOL
—
—
—
—
GPURESET 0000
—
MPLLIDIV
7F40
FFFF
DEVICE SERIAL NUMBER SUMMARY
Bits
DEVSN1
DEVSN2
DEVSN3
Legend:
Note 1:
000B
xxxx
DEVID
Bit Range
2015-2021 Microchip Technology Inc.
DEVSN0
402C
21/5
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset values are dependent on the specific device.
4020
4028
22/6
USBSSEN IOANCPEN
15:0
TABLE 41-4:
4024
23/7
VER
15:0
Legend:
Note
1:
24/8
All Resets(1)
31/15
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets(1)
0030
Bit Range
Register
Name
Virtual Address
(BF80_#)
Bits
0000 CFGCON
0020
DEVICE ID, REVISION, AND CONFIGURATION SUMMARY
31:16
Device Serial Number
xxxx
15:0
Device Serial Number
xxxx
31:16
Device Serial Number
xxxx
15:0
Device Serial Number
xxxx
31:16
Device Serial Number
xxxx
15:0
Device Serial Number
xxxx
31:16
Device Serial Number
xxxx
15:0
Device Serial Number
xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset values are dependent on the device variant.
PIC32MZ Graphics (DA) Family
DS60001361J-page 700
TABLE 41-3:
Register
Name
4000
DEVADC0
4004
4008
400C
4010
DEVADC1
DEVADC2
DEVADC3
DEVADC4
DEVADC7
Legend:
Note
1:
Bit Range
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
ADC Calibration Data
xxxx
15:0
ADC Calibration Data
xxxx
31:16
ADC Calibration Data
xxxx
15:0
ADC Calibration Data
xxxx
31:16
ADC Calibration Data
xxxx
15:0
ADC Calibration Data
xxxx
31:16
ADC Calibration Data
xxxx
15:0
ADC Calibration Data
xxxx
31:16
ADC Calibration Data
xxxx
15:0
ADC Calibration Data
xxxx
31:16
ADC Calibration Data
xxxx
15:0
ADC Calibration Data
xxxx
x = unknown value on Reset.
Reset values are dependent on the device variant.
DS60001361J-page 701
PIC32MZ Graphics (DA) Family
401C
DEVICE ADC CALIBRATION SUMMARY
All Resets(1)
Virtual Address
(BFC5_#)
2015-2021 Microchip Technology Inc.
TABLE 41-5:
PIC32MZ Graphics (DA) Family
REGISTER 41-1:
Bit
Range
31:24
23:16
15:8
7:0
DEVSIGN0/ADEVSIGN0: DEVICE SIGNATURE WORD 0 REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
r-0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
Reserved: Write as ‘0’
bit 30-0
Reserved: Write as ‘1’
Note:
31:24
23:16
15:8
7:0
x = Bit is unknown
The DEVSIGN1 through DEVSIGN3 and ADEVSIGN1 through ADEVSIGN3 registers are used for Quad
Word programming operation when programming the DEVSIGN0/ADESIGN0 registers, and do not contain
any valid information.
REGISTER 41-2:
Bit
Range
Bit
24/16/8/0
DEVCP0/ADEVCP0: DEVICE CODE-PROTECT 0 REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
r-1
r-1
R/P
r-1
r-1
r-1
r-1
—
—
—
CP
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
Legend:
r = Reserved bit
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Reserved: Write as ‘1’
bit 28
CP: Code-Protect bit
Prevents boot and program Flash memory from being read or modified by an external programming device.
1 = Protection is disabled
0 = Protection is enabled
bit 27-0
Reserved: Write as ‘1’
Note:
The DEVCP1 through DEVCP3 and ADEVCP1 through ADEVCP3 registers are used for Quad Word
programming operation when programming the DEVCP0/ADEVCP0 registers, and do not contain any valid
information.
DS60001361J-page 702
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 41-3:
Bit
Range
31:24
23:16
15:8
7:0
DEVCFG0/ADEVCFG0: DEVICE/ALTERNATE DEVICE
CONFIGURATION WORD 0
Bit
Bit
31/23/15/7 30/22/14/6
Bit
29/21/13/5
Bit
Bit
28/20/12/4 27/19/11/3
Bit
26/18/10/2
r-x
R/P
r-1
r-1
R/P
r-1
—
EJTAGBEN
—
—
POSCAGC
—
R/P
R/P
R/P
R/P
POSCFGAIN
R/P
R/P
SMCLR
R/P
POSCBOOST
R/P
POSCGAIN
R/P
DBGPER
r-1
R/P
R/P
—
BOOTISA
TRCEN
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R/P
R/P
SOSCBOOST
r-y
R/P
—
FSLEEP
R/P
ICESEL
R/P
JTAGEN
Bit
25/17/9/1
Bit
24/16/8/0
R/P
R/P
POSCAGCDLY
R/P
R/P
SOSCGAIN
R/P
R/P
FECCCON
R/P
R/P
DEBUG
P = Programmable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
bit 30
Reserved: The reset value of this bit is the same as DEVSIGN0.
EJTAGBEN: EJTAG Boot Enable bit
1 = Normal EJTAG functionality
0 = Reduced EJTAG functionality
bit 29-28 Reserved: Write as ‘1’
bit 27
POSCAGC: Primary Oscillator Automatic Gain Control bit
1 = Automatic gain control is enabled (default)
0 = Manual oscillator gain control
When the POSCAGC bit is enabled and POSC HS mode is selected, DEVCFG1 = ‘0b10 (i.e., POSCMOD), the Primary Oscillator will automatically do a linear search to find the lowest power/gain setting to
guarantee oscillation with the users crystal.
Note:
If the POSCMOD bits (DEVCFG1/ADEVCFG1_ = ‘0b00 (i.e., POSCMOD = EC
mode), the POSCAGC bit must be set to ‘0’. POSCMOD = EC mode with POSCAGC = 1 is not
permitted and will result in no oscillation.
bit 26
Reserved: Write as ‘1’
bit 25-24 POSCAGCDLY: Primary Crystal AGC Gain Search Step Settling Time Control bits
11 = Approximately (25 ms, default)
10 = Approximately (6.25 ms)
01 = Approximately (400 ms)
00 = Approximately (100 ms)
Note 1: When the POSCAGC bit (DEVCFG0) = 0 (i.e., manual oscillator gain control), these bits are
not used. They are only used when AGC is enabled.
2: For POSC HS mode (DEVCFG1 = ‘0b10), the default setting should meet the user crystal
requirements. Internally, there are a maximum of 16 and a minimum of one AGC linear gain
search steps the logic may utilize before locking. A lock will occur when the crystal is oscillating
and the amplitude of the crystal signal is between a max and min fixed internal threshold. The
POSCAGCDLY is the time for each of the possible AGC search steps settling time to allow the
crystal to startup and amplitude stabilize before determining if a lock is true or to continue to
search for the required gain. The POSCAGCDLY bits represent a balance between startup time and crystal power optimization. The lower the POSCAGCDLY delay time the faster the
crystal start-up time but potentially at a higher crystal power level. The higher the POSCAGCDLY
delay time the slower the crystal start-up time but with a better crystal power optimization level
(i.e., less power).
3: For resonators, due to their long start-up times it may be necessary to use a longer AGC gain
step settling time. Note that resonators are not validated on PIC32MZ DA devices.
2015-2021 Microchip Technology Inc.
DS60001361J-page 703
PIC32MZ Graphics (DA) Family
REGISTER 41-3:
DEVCFG0/ADEVCFG0: DEVICE/ALTERNATE DEVICE
CONFIGURATION WORD 0 (CONTINUED)
bit 23-22 POSCFGAIN: Primary Crystal Oscillator Fine Gain Control bits
11 = Gain is G3 (default)
10 = Gain is G2
01 = Gain is G1
00 = Gain is G0
Note 1: G3 > G2 > G1 > G0.
2: When the POSCAGC bit (DEVCFG0) = 1 (i.e., automatic gain control), or the
POSCMOD bits (DEVCFG1/ADEVCFG1) ‘0b10 (i.e., HS Crystal mode), the
POSCGAIN bits are not used.
3: These bits are used in conjunction with DEVCFG0/ADEVCFG0. In almost all cases, the
crystal fine gain default setting of ‘0b11 will work with the users course gain setting selection.
bit 21
POSCBOOST: Primary Oscillator Boost bit
1 = Uses internal XTAL feedback gain resistor (Default, in which case the user application should not use
any external XTAL feedback resistor in the crystal circuit)
0 = Disconnects the internal XTAL feedback resistor
bit 20-19 POSCGAIN: Primary Crystal Oscillator Coarse Gain Control bits
11 = Gain Level 3 (highest)
10 = Gain Level 2
01 = Gain Level 1
00 = Gain Level 0 (lowest)
Note 1: G3 > G2 > G1 > G0.
2: When the POSCAGC bit (DEVCFG0) = 1 (i.e., automatic gain control), or the
POSCMOD bits (DEVCFG1/ADEVCFG1) ‘0b10 (i.e., HS crystal mode), the POSCGAIN bits are not used.
bit 18
SOSCBOOST: Secondary Oscillator Kick Start Programmability bit
1 = Start up and operate with high-power SOSC internal buffer only. This option will consume more current
than allowed in the XLP specifications.
0 = Start up with internal SOSC high-power buffer, and then switch to low-power buffer when the SOSC is
stable.
bit 17-16 SOSCGAIN: Secondary Oscillator Gain Control bits
If SOSCGAIN = 0:
11 = Gain is G3 (default)
10 = Gain is G2
01 = Gain is G1
00 = Gain is G0
Note:
G3 > G2 > G1 > G0.
SMCLR: Soft Master Clear Enable bit
1 = MCLR pin generates a normal system Reset
0 = MCLR pin generates a POR
bit 14-12 DBGPER: Debug Mode CPU Access Permission bits
1xx = Allow CPU access to Permission Group 2 permission regions
x1x = Allow CPU access to Permission Group 1 permission regions
xx1 = Allow CPU access to Permission Group 0 permission regions
0xx = Deny CPU access to Permission Group 2 permission regions
x0x = Deny CPU access to Permission Group 1 permission regions
xx0 = Deny CPU access to Permission Group 0 permission regions
bit 15
Note:
bit 11
When the CPU is in Debug mode and the CPU1PG bits (CFGPG) are set to a denied
permission group as defined by DBGPER, the transaction request is assigned Group 3 permissions.
Reserved: This bit is controlled by debugger/emulator development tools and should not be modified by the
user.
DS60001361J-page 704
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 41-3:
bit 10
bit 9-8
DEVCFG0/ADEVCFG0: DEVICE/ALTERNATE DEVICE
CONFIGURATION WORD 0 (CONTINUED)
FSLEEP: Flash Sleep Mode bit
1 = Flash is powered down when the device is in Sleep mode
0 = Flash power down is controlled by the VREGS bit (PWRCON)
FECCCON: Dynamic Flash ECC Configuration bits
11 = ECC and dynamic ECC are disabled (ECCCON bits are writable)
10 = ECC and dynamic ECC are disabled (ECCCON bits are locked)
01 = Dynamic Flash ECC is enabled (ECCCON bits are locked)
00 = Flash ECC is enabled (ECCCON bits are locked; disables word Flash writes)
Note:
bit 7
bit 6
bit 5
bit 4-3
bit 2
Upon a device POR, the value of these bits are copied by hardware into CFGCON bits, (i.e.
ECCCON.
Reserved: Write as ‘1’
BOOTISA: Boot ISA Selection bit
1 = Boot code and Exception code is MIPS32
(ISAONEXC bit is set to ‘0’ and the ISA bits are set to ‘10’ in the CP0 Config3 register)
0 = Boot code and Exception code is microMIPS
(ISAONEXC bit is set to ‘1’ and the ISA bits are set to ‘11’ in the CP0 Config3 register)
TRCEN: Trace Enable bit
1 = Trace features in the CPU are enabled
0 = Trace features in the CPU are disabled
ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bits
11 = PGEC1/PGED1 pair is used
10 = PGEC2/PGED2 pair is used
01 = PGEC3/PGED3 pair is used
00 = Reserved
JTAGEN: JTAG Enable bit
1 = JTAG is enabled
0 = JTAG is disabled
Note 1: On Reset, this Configuration bit is copied into JTAGEN (CFGCON). If JTAGEN
(DEVCFG0) = 0, the JTAGEN bit cannot be set to ‘1’ by the user application at
run-time, as JTAG is always disabled. However, if JTAGEN (DEVCFG0) = 1, the
user application may enable/disable JTAG at run-time by simply writing JTAGEN
(CFGCON as required.
bit 1-0
2: This bit sets the value of the JTAGEN bit in the CFGCON register.
DEBUG: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)
11 = 4-wire JTAG Enabled - PGECx/PGEDx Disabled - ICD module Disabled
10 = 4-wire JTAG Enabled - PGECx/PGEDx Disabled - ICD module Enabled
01 = PGECx/PGEDx Enabled - 4-wire JTAG I/F Disabled - ICD module Disabled
00 = PGECx/PGEDx Enabled - 4-wire JTAG I/F Disabled - ICD module Enabled
Note:
When the FJTAGEN or JTAGEN bits are equal to ‘0’, this prevents 4-wire JTAG debugging, but
not PGECx/PGEDx debugging.
2015-2021 Microchip Technology Inc.
DS60001361J-page 705
PIC32MZ Graphics (DA) Family
REGISTER 41-4:
Bit
Range
31:24
DEVCFG1/ADEVCFG1: DEVICE CONFIGURATION WORD 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
R/P
R/P
R/P
R/P
R/P
R/P
FDMTEN
23:16
15:8
DMTCNT
R/P
R/P
R/P
FWDTEN
WINDIS
WDTSPGM
R/P
R/P
FCKSM
7:0
R/P
R/P
IESO
FSOSCEN
Legend:
R = Readable bit
-n = Value at POR
bit 31
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
WDTPS
r-1
r-1
r-1
R/P
—
—
OSCIOFNC
R/P
R/P
R/P
DMTINV
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
Bit
24/16/8/0
FWDTWINSZ
—
R/P
Bit
25/17/9/1
POSCMOD
R/P
R/P
FNOSC
P = Programmable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
FDMTEN: Deadman Timer enable bit
1 = Deadman Timer is enabled and cannot be disabled by software
0 = Deadman Timer is disabled and can be enabled by software
Note:
Once set, the DMTCON.ON bit cannot be disabled by software.
bit 30-26 DMTCNT: Deadman Timer Count Select bits
11111 = Reserved
•
•
•
11000 = Reserved
10111 = 231 (2147483648)
10110 = 230 (1073741824)
10101 = 229 (536870912)
10100 = 228 (268435456)
•
•
•
00001 = 29 (512)
00000 = 28 (256)
bit 25-24 FWDTWINSZ: Watchdog Timer Window Size bits
11 = Window size is 25%
10 = Window size is 37.5%
01 = Window size is 50%
00 = Window size is 75%
bit 23
FWDTEN: Watchdog Timer Enable bit
1 = Watchdog Timer is enabled and cannot be disabled by software
0 = Watchdog Timer is not enabled; it can be enabled in software
bit 22
WINDIS: Watchdog Timer Window Enable bit
1 = Watchdog Timer is in non-Window mode
0 = Watchdog Timer is in Window mode
bit 21
WDTSPGM: Watchdog Timer Stop During Flash Programming bit
1 = Watchdog Timer stops during Flash programming
0 = Watchdog Timer runs during Flash programming (for read/execute while programming Flash
applications)
DS60001361J-page 706
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 41-4:
DEVCFG1/ADEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED)
bit 20-16 WDTPS: Watchdog Timer Postscale Select bits
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
All other combinations not shown result in operation = 10100
bit 15-14 FCKSM: Clock Switching and Monitoring Selection Configuration bits
11 = Software Clock switching is enabled and clock monitoring is enabled
10 = Software Clock switching is disabled and clock monitoring is enabled
01 = Software Clock switching is enabled and clock monitoring is disabled
00 = Software Clock switching is disabled and clock monitoring is disabled
bit 13-11 Reserved: Write as ‘1’
bit 10
OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output is disabled
0 = CLKO output signal active on the OSCO pin; Primary Oscillator must be disabled or configured for the
External Clock mode (EC) for the CLKO to be active (POSCMOD = 11 or 00)
bit 9-8
POSCMOD: Primary Oscillator Configuration bits
11 = POSC is disabled
10 = HS Oscillator mode is selected
01 = Reserved
00 = EC mode is selected (this mode must not be selected if the POSCAGC bit (DEVCFG0/
ADEVCFG0) is equal to ‘1’)
bit 7
IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled)
0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled)
bit 6
FSOSCEN: Secondary Oscillator Enable bit
1 = Enable SOSC
0 = Disable SOSC
bit 5-3
DMTINV: Deadman Timer Count Window Interval bits
111 = Window/Interval value is 127/128 counter value
110 = Window/Interval value is 63/64 counter value
101 = Window/Interval value is 31/32 counter value
100 = Window/Interval value is 15/16 counter value
011 = Window/Interval value is 7/8 counter value
010 = Window/Interval value is 3/4 counter value
001 = Window/Interval value is 1/2 counter value
000 = Window/Interval value is zero
2015-2021 Microchip Technology Inc.
DS60001361J-page 707
PIC32MZ Graphics (DA) Family
REGISTER 41-4:
bit 2-0
DEVCFG1/ADEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED)
FNOSC: Oscillator Selection bits
111 = SPLL
110 = Reserved
101 = LPRC
100 = SOSC
011 = Reserved
010 = POSC (HS, EC)
001 = SPLL
000 = FRC divided by FRCDIV bits (FRCDIV)
DS60001361J-page 708
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 41-5:
Bit
Range
31:24
23:16
15:8
7:0
DEVCFG2/ADEVCFG2: DEVICE CONFIGURATION WORD 2
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
r-1
R/P
r-1
R/P
R/P
R/P
—
UPLLFSEL
—
FDSEN
DSWDTEN
DSWDTOSC
R/P
R/P
R/P
R/P
R/P
R/P
DSWDTPS
r-1
R/P
DSBOREN VBATBOREN
R/P
R/P
—
R/P
R/P
Bit
25/17/9/1
Bit
24/16/8/0
R/P
R/P
DSWDTPS
R/P
R/P
R/P
R/P
R/P
R/P
FPLLMULT
R/P
FPLLICLK
R/P
R/P
r-1
FPLLRNG
R/P
—
FPLLIDIV
Legend:
r = Reserved bit
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
Reserved: Write as ‘1’
bit 30
UPLLFSEL: USB PLL Input Frequency Select bit
1 = UPLL input clock is 24 MHz
0 = UPLL input clock is 12 MHz
bit 29
Reserved: Write as ‘1’
bit 28
FDSEN: Deep-Sleep Enable bit
1 = Deep Sleep mode is entered on a WAIT instruction
0 = Sleep mode is entered on a WAIT instruction
Note:
R/P
FPLLODIV
x = Bit is unknown
The user must clear this bit to '0' to prevent CPU going into Deep Sleep mode on a WAIT instruction.
bit 27
DSWDTEN: Deep Sleep Watchdog Timer Enable bit
1 = Enable the Deep Sleep Watchdog Timer (DSWDT) during Deep Sleep mode
0 = Disable the DSWDT during Deep Sleep mode
bit 26
DSWDTOSC: Deep Sleep Watchdog Timer Reference Clock Select bit
1 = Select the LPRC Oscillator as the DSWDT reference clock
0 = Select the Secondary Oscillator as the DSWDT reference clock
2015-2021 Microchip Technology Inc.
DS60001361J-page 709
PIC32MZ Graphics (DA) Family
REGISTER 41-5:
DEVCFG2/ADEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED)
bit 25-21 DSWDTPS: Deep Sleep Watchdog Timer Postscale Select bits
11111 = 1:236
11110 = 1:235
11101 = 1:234
11100 = 1:233
11011 = 1:232
11010 = 1:231
11001 = 1:230
11000 = 1:229
10111 = 1:228
10110 = 1:227
10101 = 1:226
10100 = 1:225
10011 = 1:224
10010 = 1:223
10001 = 1:222
10000 = 1:221
01111 = 1:220
01110 = 1:219
01101 = 1:218
01100 = 1:217
01011 = 1:216
01010 = 1:215
01001 = 1:214
01000 = 1:213
00111 = 1:212
00110 = 1:211
00101 = 1:210
00100 = 1:29
00011 = 1:28
00010 = 1:27
00001 = 1:26
00000 = 1:25
bit 20
DSBOREN: Deep Sleep BOR Enable bit
1 = Enable BOR during Deep Sleep mode
0 = Disable BOR during Deep Sleep mode
bit 19
VBATBOREN: VBAT BOR Enable bit
1 = Enable BOR during VBAT mode
0 = Disable BOR during VBAT mode
bit 18-16 FPLLODIV: Default System PLL Output Divisor bits
111 = PLL output divided by 32
110 = PLL output divided by 32
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 2
bit 15
Reserved: Write as ‘1’
DS60001361J-page 710
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 41-5:
DEVCFG2/ADEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED)
bit 14-8
FPLLMULT: System PLL Feedback Divider bits
1111111 = Multiply by 128
1111110 = Multiply by 127
1111101 = Multiply by 126
1111100 = Multiply by 125
•
•
•
0000000 = Multiply by 1
bit 7
FPLLICLK: System PLL Input Clock Select bit
1 = FRC is selected as input to the System PLL
0 = POSC is selected as input to the System PLL
bit 6-4
FPLLRNG: System PLL Divided Input Clock Frequency Range bits
111 = Reserved
110 = Reserved
101 = 34-64 MHz
100 = 21-42 MHz
011 = 13-26 MHz
010 = 8-16 MHz
001 = 5-10 MHz
000 = Bypass
bit 3
Reserved: Write as ‘1’
bit 2-0
FPLLIDIV: PLL Input Divider bits
111 = Divide by 8
110 = Divide by 7
101 = Divide by 6
100 = Divide by 5
011 = Divide by 4
010 = Divide by 3
001 = Divide by 2
000 = Divide by 1
2015-2021 Microchip Technology Inc.
DS60001361J-page 711
PIC32MZ Graphics (DA) Family
REGISTER 41-6:
Bit
Range
DEVCFG3/ADEVCFG3: DEVICE CONFIGURATION WORD 3
Bit
31/23/15/7
31:24
23:16
15:8
Bit
30/22/14/6
Bit
29/21/13/5
r-1
r-1
R/P
—
—
IOL1WAY
Bit
28/20/12/4
Bit
Bit
27/19/11/3 26/18/10/2
R/P
R/P
PMDL1WAY PGL1WAY
r-1
r-1
r-1
r-1
—
—
—
—
R/P
R/P
R/P
R/P
Bit
25/17/9/1
Bit
24/16/8/0
r-1
R/P
R/P
—
FETHIO
FMIIEN
R/P
R/P
R/P
EXTDDRSIZE
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
USERID
R/P
7:0
R/P
R/P
R/P
R/P
USERID
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
P = Programmable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Reserved: Write as ‘1’
bit 29
IOL1WAY: Peripheral Pin Select Configuration bit
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
bit 28
PMDL1WAY: Peripheral Module Disable Configuration bit
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
bit 27
PGL1WAY: Permission Group Lock One Way Configuration bit
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
bit 26
Reserved: Write as ‘1’
bit 25
FETHIO: Ethernet I/O Pin Selection Configuration bit
1 = Default Ethernet I/O pins
0 = Alternate Ethernet I/O pins
This bit is ignored for devices that do not have an alternate Ethernet pin selection.
FMIIEN: Ethernet MII Enable Configuration bit
1 = MII is enabled
0 = RMII is enabled
bit 23-20 Reserved: Write as ‘1’
bit 19-16 EXTDDRSIZE: External DDR2 SDRAM Size bits
This field is used to configure the DDR2 memory map. Refer to Table 4-1 for address mapping details.
1111 = 128 MB
1110 = 128 MB
bit 24
•
•
•
bit 15-0
0111 = 128 MB
0110 = 64 MB
0101 = 32 MB
0100 = 16 MB
0011 = 8 MB
0010 = 4 MB
0001 = 2 MB
0000 = 1 MB
USERID: This is a 16-bit value that is user-defined and is readable via ICSP™ and JTAG
DS60001361J-page 712
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 41-7:
Bit
Range
31:24
23:16
15:8
7:0
DEVCFG4/ADEVCFG4: DEVICE CONFIGURATION WORD 4
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
R/P
r-1
r-1
r-1
—
—
—
Bit
Bit
27/19/11/3 26/18/10/2
R/P
R/P
Bit
25/17/9/1
Bit
24/16/8/0
R/P
R/P
SWDTPS
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
P = Programmable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Reserved: Write as ‘1’
bit 29-24 SWDTPS: Sleep Mode Watchdog Timer Postscale Select bits
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
All other combinations not shown result in operation = 10100
bit 31-29 Reserved: Write as ‘1’
2015-2021 Microchip Technology Inc.
DS60001361J-page 713
PIC32MZ Graphics (DA) Family
REGISTER 41-8:
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R
R
R
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
ADCFG
R
R
R
R
R
ADCFG
R
R
R
R
R
ADCFG
R
R
R
R
R
ADCFG
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
DEVADCx: DEVICE ADC CALIBRATION WORD ‘x’ (‘x’ = 0-4, 7)
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
ADCFG: Calibration Data for the ADC Module bits
This data must be copied to the corresponding ADCxCFG register. Refer to Section 28.0 “Pipelined
Analog-to-Digital Converter (ADC)” for more information.
DS60001361J-page 714
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 41-9:
Bit
Range
31:24
23:16
15:8
7:0
CFGCON: CONFIGURATION CONTROL REGISTER
Bit
31/23/15/7
Bit
Bit
30/22/14/6 29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
ICACLK(1)
OCACLK(1)
U-0
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
—
—
—
—
USBSSEN(1)
R/W-0
U-0
R/W-1
R/W-0
U-0
R/W-1
IOANCPEN
—
JTAGEN(2)
TROEN
—
TDOEN
IOLOCK(1) PMDLOCK(1) PGLOCK(1)
R/W-1
R/W-1
ECCCON
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-18 Unimplemented: Read as ‘0’
bit 17
ICACLK: Input Capture Alternate Clock Selection bit(1)
1 = Input Capture modules use an alternative Timer pair as their timebase clock
0 = All Input Capture modules use Timer2/3 as their timebase clock
bit 16
OCACLK: Output Compare Alternate Clock Selection bit(1)
1 = Output Compare modules use an alternative Timer pair as their timebase clock
0 = All Output Compare modules use Timer2/3 as their timebase clock
bit 15-14 Unimplemented: Read as ‘0’
bit 13
IOLOCK: Peripheral Pin Select Lock bit(1)
1 = Peripheral Pin Select is locked. Writes to PPS registers is not allowed.
0 = Peripheral Pin Select is not locked. Writes to PPS registers is allowed.
bit 12
PMDLOCK: Peripheral Module Disable bit(1)
1 = Peripheral module is locked. Writes to PMD registers is not allowed.
0 = Peripheral module is not locked. Writes to PMD registers is allowed.
bit 11
PGLOCK: Permission Group Lock bit(1)
1 = Permission Group registers are locked. Writes to PG registers are not allowed.
0 = Permission Group registers are not locked. Writes to PG registers are allowed.
bit 10-9
Unimplemented: Read as ‘0’
bit 8
USBSSEN: USB Suspend Sleep Enable bit(1)
Enables features for USB PHY clock shutdown in Sleep mode.
1 = USB PHY clock is shut down when Sleep mode is active
0 = USB PHY clock continues to run when Sleep is active
Note 1:
To change this bit, the unlock sequence must be performed. Refer to Section 42. “Oscillators with
Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
The JTAGEN bit is only available at run-time when the JTAGEN (DEVCFG0) fuse bit is set at start-up.
2:
2015-2021 Microchip Technology Inc.
DS60001361J-page 715
PIC32MZ Graphics (DA) Family
REGISTER 41-9:
bit 7
CFGCON: CONFIGURATION CONTROL REGISTER (CONTINUED)
IOANCPEN: I/O Analog Charge Pump Enable bit
1 = Charge pumps are enabled
0 = Charge pumps are disabled
Note 1: For proper analog operation at VDD is less than 2.5V, the AICPMPEN bit (ADCCON1) must
be = 1 and the IOANCPEN bit must be set to ‘1’; however, the charge pumps will consume additional current. These bits should not be set if VDD is greater than 2.5V.
2: ADC throughput rate performance is reduced as defined in the table below if ADCCON1 = 1 and CFGCON = 1.
bit 6
Unimplemented: Read as ‘0’
bit 5-4
ECCCON: Flash ECC Configuration bits
11 = ECC and dynamic ECC are disabled (ECCCON bits are writable)
10 = ECC and dynamic ECC are disabled (ECCCON bits are locked)
01 = Dynamic Flash ECC is enabled (ECCCON bits are locked)
00 = Flash ECC is enabled (ECCCON bits are locked; disables word Flash writes)
bit 3
JTAGEN: JTAG Port Enable bit(2)
1 = Enable the JTAG port
0 = Disable the JTAG port
bit 2
TROEN: Trace Output Enable bit
1 = Enable trace outputs and start trace clock (trace probe must be present)
0 = Disable trace outputs and stop trace clock
bit 1
Unimplemented: Read as ‘0’
bit 0
TDOEN: TDO Enable for 2-Wire JTAG
1 = 2-wire JTAG protocol uses TDO
0 = 2-wire JTAG protocol does not use TDO
Note 1:
To change this bit, the unlock sequence must be performed. Refer to Section 42. “Oscillators with
Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.
The JTAGEN bit is only available at run-time when the JTAGEN (DEVCFG0) fuse bit is set at start-up.
2:
DS60001361J-page 716
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 41-10: CFGEBIA: EXTERNAL BUS INTERFACE ADDRESS PIN CONFIGURATION
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EBIA23EN
EBIA22EN
EBIA21EN
EBIA20EN
EBIA19EN
EBIA18EN
EBIA17EN
EBIA16EN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EBIA15EN
EBIA14EN
EBIA13EN
EBIA12EN
EBIA11EN
EBIA10EN
EBIA9EN
EBIA8EN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EBIA7EN
EBIA6EN
EBIA5EN
EBIA4EN
EBIA3EN
EBIA2EN
EBIA1EN
EBIA0EN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-0
Note:
EBIA23EN:EBIA0EN: EBI Address Pin Enable bits
1 = EBIAx pin is enabled for use by EBI
0 = EBIAx pin has is available for general use
When EBIMD = 1, the bits in this register are ignored and the pins are available for general use.
2015-2021 Microchip Technology Inc.
DS60001361J-page 717
PIC32MZ Graphics (DA) Family
REGISTER 41-11: CFGEBIC: EXTERNAL BUS INTERFACE CONTROL PIN CONFIGURATION
REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
Bit
Bit
28/20/12/4 27/19/11/3 26/18/10/2
R/W-0
R/W-0
R/W-0
U-0
R/W-0
EBI
RDYINV3
EBI
RDYINV2
EBI
RDYINV1
—
EBI
RDYEN3
U-0
U-0
U-0
U-0
U-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
U-0
EBI
RDYEN2
EBI
RDYEN1
—
U-0
R/W-0
R/W-0
EBIRPEN
—
—
—
—
—
—
EBIRDYLVL
U-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
—
—
EBIWEEN
EBIOEEN
—
—
EBIBSEN1
EBIBSEN0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
EBICSEN3
EBICSEN2
EBICSEN1
EBICSEN0
—
—
EBIDEN1
EBIDEN0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31
EBIRDYINV3: EBIRDY3 Inversion Control bit
1 = Invert EBIRDY3 pin before use
0 = Do not invert EBIRDY3 pin before use
bit 30
EBIRDYINV2: EBIRDY2 Inversion Control bit
1 = Invert EBIRDY2 pin before use
0 = Do not invert EBIRDY2 pin before use
bit 29
EBIRDYINV1: EBIRDY1 Inversion Control bit
1 = Invert EBIRDY1 pin before use
0 = Do not invert EBIRDY1 pin before use
bit 28
Unimplemented: Read as ‘0’
bit 27
EBIRDYEN3: EBIRDY3 Pin Enable bit
1 = EBIRDY3 pin is enabled for use by the EBI module
0 = EBIRDY3 pin is available for general use
bit 26
EBIRDYEN2: EBIRDY2 Pin Enable bit
1 = EBIRDY2 pin is enabled for use by the EBI module
0 = EBIRDY2 pin is available for general use
bit 25
EBIRDYEN1: EBIRDY1 Pin Enable bit
1 = EBIRDY1 pin is enabled for use by the EBI module
0 = EBIRDY1 pin is available for general use
x = Bit is unknown
bit 24-18 Unimplemented: Read as ‘0’
bit 17
EBIRDYLVL: EBIRDYx Pin Sensitivity Control bit
1 = Use level detect for EBIRDYx pins
0 = Use edge detect for EBIRDYx pins
bit 16
EBIRPEN: EBIRP Pin Sensitivity Control bit
1 = EBIRP pin is enabled for use by the EBI module
0 = EBIRP pin is available for general use
bit 15-14 Unimplemented: Read as ‘0’
bit 13
Note:
EBIWEEN: EBIWE Pin Enable bit
1 = EBIWE pin is enabled for use by the EBI module
0 = EBIWE pin is available for general use
When EBIMD = 1, the bits in this register are ignored and the pins are available for general use.
DS60001361J-page 718
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 41-11: CFGEBIC: EXTERNAL BUS INTERFACE CONTROL PIN CONFIGURATION
REGISTER (CONTINUED)
bit 12
EBIOEEN: EBIOE Pin Enable bit
1 = EBIOE pin is enabled for use by the EBI module
0 = EBIOE pin is available for general use
bit 11-10 Unimplemented: Read as ‘0’
bit 9
EBIBSEN1: EBIBS1 Pin Enable bit
1 = EBIBS1 pin is enabled for use by the EBI module
0 = EBIBS1 pin is available for general use
bit 8
EBIBSEN0: EBIBS0 Pin Enable bit
1 = EBIBS0 pin is enabled for use by the EBI module
0 = EBIBS0 pin is available for general use
bit 7
EBICSEN3: EBICS3 Pin Enable bit
1 = EBICS3 pin is enabled for use by the EBI module
0 = EBICS3 pin is available for general use
bit 6
EBICSEN2: EBICS2 Pin Enable bit
1 = EBICS2 pin is enabled for use by the EBI module
0 = EBICS2 pin is available for general use
bit 5
EBICSEN1: EBICS1 Pin Enable bit
1 = EBICS1 pin is enabled for use by the EBI module
0 = EBICS1 pin is available for general use
bit 4
EBICSEN0: EBICS0 Pin Enable bit
1 = EBICS0 pin is enabled for use by the EBI module
0 = EBICS0 pin is available for general use
bit 3-2
Unimplemented: Read as ‘0’
bit 1
EBIDEN1: EBI Data Upper Byte Pin Enable bit
1 = EBID pins are enabled for use by the EBI module
0 = EBID pins have reverted to general use
bit 0
EBIDEN01: EBI Data Upper Byte Pin Enable bit
1 = EBID pins are enabled for use by the EBI module
0 = EBID pins have reverted to general use
Note:
When EBIMD = 1, the bits in this register are ignored and the pins are available for general use.
2015-2021 Microchip Technology Inc.
DS60001361J-page 719
PIC32MZ Graphics (DA) Family
REGISTER 41-12: CFGPG: PERMISSION GROUP CONFIGURATION REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
R/W-0
R/W-0
FCPG
R/W-0
R/W-0
CAN2PG
U-0
U-0
—
—
Legend:
R = Readable bit
-n = Value at POR
GPUPG
R/W-0
R/W-0
SQI1PG
R/W-0
R/W-0
CAN1PG
R/W-0
R/W-0
DMAPG
W = Writable bit
‘1’ = Bit is set
GLCDPG
R/W-0
R/W-0
SDHCPG
U-0
U-0
—
—
U-0
U-0
—
—
CRYPTPG
R/W-0
R/W-0
ETHPG
R/W-0
R/W-0
USBPG
R/W-0
R/W-0
CPUPG
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 GPUPG: 2D Graphics Processing Unit Permission Group bits
11 = Initiator is assigned to Permission Group 3
10 = Initiator is assigned to Permission Group 2
01 = Initiator is assigned to Permission Group 1
00 = Initiator is assigned to Permission Group 0
bit 27-26 GLCDPG: Graphics LCD Controller Permission Group bits
Same definition as bits 29-28.
bit 25-24 CRYPTPG: Crypto Engine Permission Group bits
Same definition as bits 29-28.
bit 23-22 FCPG: Flash Control Permission Group bits
Same definition as bits 29-28.
bit 21-20 SQI1PG: SQI Module Permission Group bits
Same definition as bits 29-28.
bit 19-18 SDHCPG: Secure Digital Host Controller Permission Group bits
Same definition as bits 29-28.
bit 17-16 ETHPG: Ethernet Module Permission Group bits
Same definition as bits 29-28.
bit 15-14 CAN2PG: CAN2 Module Permission Group bits
Same definition as bits 29-28.
bit 13-12 CAN1PG: CAN1 Module Permission Group bits
Same definition as bits 29-28.
bit 11-10 Unimplemented: Read as ‘0’
bit 9-8
USBPG: USB Module Permission Group bits
Same definition as bits 29-28.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DMAPG: DMA Module Permission Group bits
Same definition as bits 29-28.
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
CPUPG: CPU Permission Group bits
Same definition as bits 29-28.
DS60001361J-page 720
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 41-13: CFGCON2: CONFIGURATION CONTROL REGISTER 2
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
R/W-0
R/W-0
Bit
Bit
Bit
Bit
29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
R/W-0
GLCDPINEN GLCDMODE(1) SDCDEN
R/W-0
R/W-0
R/W-0
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
U-0
U-0
R/W-0
SDWPEN
—
—
SDWRFTHR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDWRFTHR
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
SDRDFTHR
R/W-0
R/W-0
SDRDFTHR
Legend:
R = Readable bit
-n = Value at POR
R/W-0
W = Writable bit
‘1’ = Bit is set
r-1
R/W-0
U-0
R/W-0
—
SDWPPOL
—
GPURESET
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
GLCDPINEN: Graphics Display Pin Enable bit
1 = GLCD pins are used by the GLCD module
0 = GLCD pins are available for general purpose use
bit 30
GLCDMODE: Graphics Display Mode bit(1)
1 = GLCD pins are set to RGB565 mode. Other GDx pins are available for general purpose use.
0 = GLCD pins are set to RGB888 mode
bit 29
SDCDEN: SD Card Detect Pin Enable bit
1 = SDCD pin is enabled for use by SDHC
0 = SDCD pin is available for general purpose use
bit 28
SDWPEN: SD card Write Protect Enable bit
1 = SDWP pin is enabled for use by SDHC
0 = SDWP pin is available for general purpose use
bit 27-26 Unimplemented: Read as ‘0’
bit 25-16 SDWRFTHR: SDHC Write FIFO Threshold bits
SDHC FIFO threshold value in bytes (FIFO size is 512 bytes).
bit 15-14 Unimplemented: Read as ‘0’
bit 13-4 SDRDFTHR: SDHC Read FIFO Threshold bits
SDHC FIFO threshold value in bytes (FIFO size is 512 bytes).
bit 3
Reserved: Read as ‘1’
bit 2
SDWPPOL: SD card Write Protect Polarity bit
1 = SDWP pin is Active-High
0 = SDWP pin is Active-Low
bit 1
bit 0
Note:
This bit supports SD cards with different write-protect polarity types.
Unimplemented: Read as ‘0’
GPURESET: GPU Reset Bit
1 = Hold GPU in RESET
0 = Release RESET to the GPU module
Note:
Note 1:
This bit is only used if the GPU functionality is to be enabled or disabled at run-time. Writing to
this bit requires the GPUMD bit (PMD6) be set to '0' (GPU is enabled).
To use GLCD in RGB888 mode, the GLCDMODE bit should be set to ‘0’, which will turn-off the general
purpose I/O functionality on six additional pins. Refer to the specific package in “Device Pin Tables” for
information on GDx pin sharing.
2015-2021 Microchip Technology Inc.
DS60001361J-page 721
PIC32MZ Graphics (DA) Family
REGISTER 41-14: CFGMPLL: MEMORY PLL CONFIGURATION REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
MPLLRDY
MPLLDIS
bit 30
MPLLODIV1
R-0
R/W-1
U-0
U-0
U-0
U-0
U-0
U-0
MPLL
VREGRDY
MPLL
VREGDIS
—
—
—
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
MPLLMULT
INTVREFCON
Legend:
R = Readable bit
-n = Value at POR
bit 31
MPLLODIV2
R/W-1
MPLLIDIV
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
MPLLRDY: Memory PLL Status bit
1 = MPLL clock is stable and is ready for use
0 = MPLL clock is not ready. Initializing DDR2 SDRAM when the clock is not ready will result in undefined
behavior.
MPLLDIS: MPLL Disable bit
1 = MPLL is disabled
0 = MPLL is enabled
Note:
Clear this bit only after the MPLLVREGRDY bit is set to ‘1’.
bit 29-27 MPLLODIV2: MPLL Output Divider 2 bits
111 = MPLL second stage output is divided by 7
110 = MPLL second stage output is divided by 6
101 = MPLL second stage output is divided by 5
100 = MPLL second stage output is divided by 4
011 = MPLL second stage output is divided by 3
010 = MPLL second stage output is divided by 2
001 = MPLL second stage output is divided by 1
000 = Reserved
Note:
The Value in this field should be less than MPLLODIV1. Unless it is necessary, setting these bits
to '001' (MPLL second stage output is divided by 1) will produce less clock jitter.
bit 26-24 MPLLODIV1: MPLL Output Divider 1 bits
See bits 29-27 for available selections.
bit 23
MPLLVREGRDY: MPLL Voltage Regulator Ready bit
1 = MPLL voltage regulator is ready for use
0 = MPLL voltage regulator is not ready or is disabled
bit 22
MPLLVREGDIS: MPLL Voltage regulator Disable bit
1 = MPLL voltage regulator is disabled
0 = MPLL voltage regulator is enabled
bit 21-16 Unimplemented: Read as ‘0’
DS60001361J-page 722
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
REGISTER 41-14: CFGMPLL: MEMORY PLL CONFIGURATION REGISTER (CONTINUED)
bit 15-8
MPLLMULT: MPLL Multiplier bits
11111111 = Reserved
11111110 = Reserved
•
•
•
10100001 = Reserved
10100000 = Multiply by 160
10011111 = Multiply by 159
•
•
•
00010000 = Multiply by 16
00001111 = Reserved
•
•
•
bit 7-6
bit 5-0
00000000 = Reserved
INTVREFCON: Internal DDRVREF Control bits
11 = Enable the internal DDRVREF circuit
10 = Disable the internal DDRVREF circuit and drive the DDRVREF pin to VSS1V8
01 = Disable the internal DDRVREF circuit and drive the DDRVREF pin to VDDR1V8
00 = Use the external DDRVREF circuit
Note:
Set the INTVREFCON bits to the desired state before applying VDDR1V8.
MPLLIDIV: MPLL Input Divider bits
111111 = MPLL input clock is divider by 63
111110 = MPLL input clock is divider by 62
•
•
•
000001 = MPLL input clock is divider by 1
000000 = Reserved
2015-2021 Microchip Technology Inc.
DS60001361J-page 723
PIC32MZ Graphics (DA) Family
REGISTER 41-15: DEVID: DEVICE AND REVISION ID REGISTER
Bit
Range
31:24
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R
R
R
R
R
VER(1)
R
23:16
R
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R
R
R
DEVID(1)
R
R
R
R
R
R
R
R
R
R
R
R
DEVID(1)
R
15:8
R
R
R
R
DEVID(1)
R
7:0
R
R
R
R
DEVID(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 VER: Revision Identifier bits(1)
bit 27-0
DEVID: Device ID(1)
Note 1:
See the “PIC32 Flash Programming Specification” (DS60001145) for a list of Revision and Device ID values.
REGISTER 41-16: DEVSNx: DEVICE SERIAL NUMBER REGISTER ‘x’ (‘x’ = 0, 1,2,3)
Bit Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
SN
R
Note:
R
R
R
SN
R
R
R
R
SN
R
R
R
R
SN
Legend:
R = Readable bit
-n = Value at POR
bit 31-0
R
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
SN: Device Unique Serial Number bits
These registers contain a value, programmed during factory production test, that is unique to each unit and
are user read only. These values are persistent and not erased even when a new application code is programmed into the device. These values can be used if desired as an encryption key in combination with
the Microchip encryption library.
DS60001361J-page 724
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
41.3
High-Voltage Detect (HVD1V8) on
VDDR1V8
The High-Voltage Detect (HVD) module monitors the
DDR2 PHY voltage at the VDDR1V8 supply voltage
(1.8V). If a dangerously high voltage is detected, the
device is held in reset as long as the HVD condition
persists.
Recovery from an HVD event is indicated by the
HVD1V8R bit (RCON).
41.4
On-Chip Voltage Regulator
The core and digital logic for all PIC32MZ DA devices
is designed to operate at a nominal 1.2V. To simplify
system designs, devices in the PIC32MZ DA family
incorporate an on-chip regulator providing the required
core logic voltage from VDDCORE.
41.4.1
ON-CHIP REGULATOR AND POR
It takes a fixed delay for the on-chip regulator to generate
an output. During this time, designated as TPU, code
execution is disabled. TPU is applied every time the
device resumes operation after any power-down,
including Sleep mode.
41.4.2
ON-CHIP REGULATOR AND BOR
PIC32MZ DA devices also have a simple brown-out
capability. If the voltage supplied to the regulator is
inadequate to maintain a regulated level, the regulator
Reset circuitry will generate a Brown-out Reset (BOR).
This event is captured by the BOR Flag bit
(RCON). The brown-out voltage levels are specific
in Section 44.1 “DC Characteristics”.
41.5
On-chip Temperature Sensor
PIC32MZ DA devices include a temperature sensor
that provides accurate measurement of a device’s
junction temperature (see Section 44.2 “AC
Characteristics and Timing Parameters” for more
information).
The temperature sensor is connected to the ADC
module and can be measured using the shared S&H
circuit (see Section 29.0 “12-bit High-Speed
Successive Approximation Register (SAR) Analogto-Digital Converter (ADC)” for more information).
41.6
Programming and Diagnostics
PIC32MZ DA devices provide a complete range of programming and diagnostic features that can increase
the flexibility of any application using them. These
features allow system designers to include:
• Simplified field programmability using two-wire
In-Circuit Serial Programming™ (ICSP™)
interfaces
• Debugging using ICSP
• Programming and debugging capabilities using
the EJTAG extension of JTAG
• JTAG boundary scan testing for device and board
diagnostics
PIC32 devices incorporate two programming and diagnostic modules, and a trace controller, that provide a
range of functions to the application developer.
FIGURE 41-1:
BLOCK DIAGRAM OF
PROGRAMMING,
DEBUGGING AND TRACE
PORTS
PGEC1
PGED1
ICSP™
Controller
PGEC2
PGED2
ICESEL
TDI
TDO
TCK
JTAG
Controller
Core
TMS
JTAGEN
DEBUG
TRCLK
TRD0
TRD1
Instruction Trace
Controller
TRD2
TRD3
DEBUG
2015-2021 Microchip Technology Inc.
DS60001361J-page 725
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 726
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
42.0
INSTRUCTION SET
The PIC32MZ Graphics (DA) Family family instruction
set complies with the MIPS32® Release 2 instruction
set architecture. The PIC32MZ DA device family does
not support the following features:
• Core extend instructions
• Coprocessor 2 instructions
Note:
Refer to “MIPS32® Architecture for
Programmers Volume II: The MIPS32®
Instruction Set” at www.imgtec.com for
more information.
2015-2021 Microchip Technology Inc.
DS60001361J-page 727
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 728
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
43.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
43.1
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2015-2021 Microchip Technology Inc.
DS60001361J-page 729
PIC32MZ Graphics (DA) Family
43.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
43.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
43.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
43.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS60001361J-page 730
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
43.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
43.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2015-2021 Microchip Technology Inc.
43.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
43.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
43.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDIOMIN and VDDIOMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
DS60001361J-page 731
PIC32MZ Graphics (DA) Family
43.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
43.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS60001361J-page 732
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
44.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC32MZ DA electrical characteristics. Additional information will be provided
in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC32MZ DA devices are listed below. Exposure to these maximum rating conditions
for extended periods may affect device reliability. Functional operation of the device at these or any other conditions,
above the parameters indicated in the operation listings of this specification, is not implied.
ABSOLUTE MAXIMUM RATINGS
(see Note1)
Ambient temperature under bias.............................................................................................................. .-40°C to +85°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDDIO, VDDCORE, and VBAT with respect to VSS ...................................................................... -0.3V to +4.0V
Voltage on VDDR1V8 pin with respect to VSS1V8 ..................................................................................... -0.5V to +1.98V
Voltage on DDR2 pins with respect to VSS1V8 ....................................................................... -0.3V to (VDDR1V8 + 0.3V)
Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)...................................... -0.3V to (VDDIO + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDDIO 2.2V (Note 3)..................................... -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to VSS when VDDIO < 2.2V (Note 3)..................................... -0.3V to +3.6V
Voltage on D+ or D- pin with respect to VUSB3V3 .................................................................... -0.3V to (VUSB3V3 + 0.3V)
Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V
Maximum current out of VSS pin(s) .......................................................................................................................500 mA
Maximum current into VDDIO pin(s) (Note 2).........................................................................................................200 mA
Maximum current into VDDCORE pin(s) (Note 2).................................................................................................300 mA
Maximum current into VDDR1V8 pin(s) (Note 2)...................................................................................................270 mA
Maximum current out of VSS1V8 pin(s)..................................................................................................................270 mA
Maximum current sunk/sourced by DDR2 pin.........................................................................................................22 mA
Maximum current sunk/sourced by any 4x I/O pin (Note 4)....................................................................................15 mA
Maximum current sunk/sourced by any 8x I/O pin (Note 4)....................................................................................25 mA
Maximum current sunk/sourced by any 12x I/O pin (Note 4)..................................................................................33 mA
Maximum current sunk by all ports (Note 5) .........................................................................................................150 mA
Maximum current sourced by all ports (Note 2, Note 5).......................................................................................150 mA
ESD Qualification:
Human Body Model (HBM) per JESD22-A114........................................................................................................2000V
Machine Model (MM) per JESD22-A115....................................................................................................................200V
Changed Device Model (CDM) AEC Q100-011 (ANSI/ESD STM 5.3.1)...................................................................500V
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions,
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 44-2).
3: See the pin name tables (Table 5 through Table 7) for the 5V tolerant pins.
4: Characterized, but not tested. Refer to parameters DO10, DO20, and DO20a for the 4x, 8x, and 12x I/O
pin lists.
5: Excludes DDR2 pins.
2015-2021 Microchip Technology Inc.
DS60001361J-page 733
PIC32MZ Graphics (DA) Family
44.1
DC Characteristics
TABLE 44-1:
Characteristic
DC5
Note 1:
OPERATING MIPS VS. VOLTAGE
VDDIO Range
(in Volts)
(Note 1)
VDDCORE
Range
(in Volts)
(Note 1)
Temp. Range
(in °C)
Max. Frequency
PIC32MZ DA Devices
2.2V-3.6V
1.7V-1.9V
-40°C to +85°C
200 MHz
Comments
—
Overall functional device operation below operating voltages guaranteed (but not characterized) until
Reset is issued. All device Analog modules, when enabled, will function, but with degraded performance
below operating voltages. Refer to Table 44-5 for Reset values.
TABLE 44-2:
THERMAL OPERATING CONDITIONS
Rating
Symbol Min.
Industrial Temperature Devices
Operating Junction Temperature Range
Operating Ambient Temperature Range
Power Dissipation:
Internal Chip Power Dissipation (Device without DDR2):
PINT = VDDIO x (IDDIO – Ʃ IOH) + VDDCORE x IDDCORE
Internal Chip Power Dissipation (Device with DDR2):
PINT = VDDIO x (IDDIO – Ʃ IOH) + VDDCORE x IDDCORE + VDDR1V8 x IDDR1V8
I/O Pin Power Dissipation:
PI/O = Ʃ ({VDDIO – VOH} x IOH) + Ʃ (VOL x IOL)
Maximum Allowed Power Dissipation
TABLE 44-3:
TJ
TA
Typ.
Max.
Unit
—
—
+125
+85
°C
°C
-40
-40
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
THERMAL PACKAGING CHARACTERISTICS
Characteristics
Symbol
Typ.
Max.
Unit
Notes
Package Thermal Resistance, 169-pin LFBGA (11x11x1.4 mm)
JA
25
—
°C/W
1
Package Thermal Resistance, 169-pin LFBGA (11x11x1.56 mm)
JA
23.5
—
°C/W
1,2
Package Thermal Resistance, 176-pin LQFP (20x20x1.45 mm)
JA
20
—
°C/W
1
Package Thermal Resistance, 176-pin LQFP (20x20x1.45 mm)
JA
20
—
°C/W
1,2
Package Thermal Resistance, 288-pin LFBGA (15x15x1.4 mm)
JA
22
—
°C/W
1
Note 1:
2:
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
Devices with internal DDR2 SDRAM.
DS60001361J-page 734
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param.
No.
Symbol
Operating Voltage
DC10 VDDIO
DC11 VDDCORE
DC12 SVDDIO/
SVDDCORE
Characteristics
Min.
DC13
VBAT
I/O Supply Voltage (Note 1)
2.2
Core Supply Voltage (Note 1)
1.7
VDDIO/VDDCORE Rise Rate
to Ensure Internal
0.000011
Power-on Reset Signal (Note 2)
Battery Supply Voltage
2.2
DC14
VDDR1V8
DDR Memory Supply Voltage
DC15
DDRVREF
Note 1:
2:
Typ.
Max.
Units
Conditions
—
1.8
3.6
1.9
V
V
—
—
—
1.1
V/µs
—
3.6
V
—
1.8
1.9
V
—
1.7
300 ms to 3 µs @
3.3v
0.49 x
0.50 x
0.51 x
—
V
VDDR1V8 VDDR1V8 VDDR1V8
Overall functional device operation below operating voltages guaranteed (but not characterized) until
Reset is issued. All device Analog modules, when enabled, will function, but with degraded performance
below operating voltages. Refer to Table 44-5 for Reset values.
Voltage on VDDIO must always be greater than or equal to VDDCORE during power-up.
TABLE 44-5:
DDR Reference Voltage
ELECTRICAL CHARACTERISTICS: RESETS
DC CHARACTERISTICS (Note 1)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param.
No.
Min.
Typ.
Max.
Units
Conditions
—
—
1.75
V
—
RST10
RST11
Symbol
Characteristics
VPORIO
VDDIO POR Voltage
(Note 2)
VPORCORE VDDCORE POR Voltage
/VBATSW
(Note 2)
VDDCORE to VBAT Switch
Voltage (Note 3)
—
—
VSS+
0.3
V
Failure to meet this
specification when power
cycling the part may lead to
unexpected and abnormal
behavior.
RST12
VBORIO
BOR Event on VDDIO transition
high-to-low (Note 4)
1.92
—
2.2
V
—
RST13
VPORBAT
POR Event on VBAT (Note 4)
1.35
—
2.2
V
—
RST14
VHVD1V8
Note 1:
2:
3:
4:
High Voltage Detect on
2.16
—
2.24
V
—
VDDR1V8 pins
Parameters are for design guidance only and are not tested in manufacturing.
This is the limit to which VDDIO/VDDCORE must be lowered to ensure Power-on Reset (POR)
Device enters VBAT mode upon VDDCORE Power-on Reset (POR).
Overall functional device operation below operating voltages guaranteed (but not characterized) until Reset
is issued. All device analog modules when enabled will function, but with degraded performance below
operating voltages.
2015-2021 Microchip Technology Inc.
DS60001361J-page 735
PIC32MZ Graphics (DA) Family
TABLE 44-6:
LOW-VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param
Symbol
No.
LV10
LV11
Note 1:
VHLVD
VTHL
Characteristic
HLVD Voltage on
VDDIO Transition
Voltage on HLVDIN
Pin Transition
Min.
Typ.
Max.
Units
Conditions
HLVDL = 0100(1)
—
3.52
—
V
—
HLVDL = 0101
—
3.29
—
V
—
HLVDL = 0110
—
3.00
—
V
—
HLVDL = 0111
—
2.79
—
V
—
HLVDL = 1000
—
2.70
—
V
—
HLVDL = 1001
—
2.50
—
V
—
HLVDL = 1010
—
2.40
—
V
—
HLVDL = 1011
—
2.30
—
V
—
HLVDL = 1111
—
1.20
—
V
—
Trip points for values of LVD, from ‘0000’ to ‘0011’, are not implemented, and ‘1100,’ ‘1101’ to ‘1110’
are reserved.
DS60001361J-page 736
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-7:
DC CHARACTERISTICS: OPERATING CURRENT (IDD = IDDIO + IDDCORE)
DC CHARACTERISTICS(1,2)
Parameter
No.
Typical(3)
Maximum
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Units
Conditions
I/O Operating Current (IDDIO): Peripherals Enabled (PMDx=0, ON(PBxDIV)=1)
DC20
1.4
2.1
mA
8 MHz
DC21
3.5
4.1
mA
100 MHz(4)
DC22
5.6
6.5
mA
200 MHz
DC23
5.6
6.5
mA
200 MHz (L1 Cache and Prefetch modules disabled)(4)
I/O Operating Current (IDDCORE): Peripherals Enabled (PMDx=0, ON(PBxDIV)=1)
DC20a
20
34
mA
8 MHz
DC21a
97
118
mA
100 MHz(4)
DC22a
152
180
mA
200 MHz
DC23a
128
153
mA
200 MHz (L1 Cache and Prefetch modules disabled)(4)
I/O Operating Current (IDDIO): Peripherals Disabled (PMDx=1, ON(PBxDIV)=0)
DC24
1.4
2.1
mA
8 MHz
DC25
3.5
4.1
mA
100 MHz(4)
DC26
5.6
6.5
mA
200 MHz
DC27
5.6
6.5
mA
200 MHz (L1 Cache and Prefetch modules disabled)(4)
I/O Operating Current (IDDCORE): Peripherals Disabled (PMDx=1, ON(PBxDIV)=0)
DC24a
19
33
mA
8 MHz
DC25a
90
109
mA
100 MHz(4)
DC26a
146
177
mA
200 MHz
DC27a
121
147
mA
200 MHz (L1 Cache and Prefetch modules disabled)(4)
Note 1: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as Peripheral Bus Clock (PBCLK) frequency, number of peripheral modules enabled, internal code
execution pattern, I/O pin loading and switching rate, oscillator type, as well as temperature, can have an
impact on the current consumption.
2: The test conditions for IDD measurements are as follows:
• VDDR1V8 = 1.8V
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL is disabled (USBMD = 1), VUSB3V3 is connected to VSS
• CPU, Program Flash, and SRAM data memory are operational, Program Flash memory Wait states
are equal to two
• No peripheral modules are operating (ON bit = 0)
• L1 Cache and Prefetch modules are enabled, unless otherwise specified in conditions.
• No peripheral modules are operating, (ON bit = 0)
• WDT, DMT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDDIO
• CPU executing while(1) statement from Flash
• RTCC and JTAG are disabled
• I/O Analog Charge Pump is disabled (IOANCPEN bit (CFGCON) = 0)
• ADC Input Charge Pump is disabled (AICPMPEN bit (ADCCON1 = 0)
• All Peripheral Bus Clocks, except PBCLK7, are disabled (ON bit (PBxDIV) = 0, x = 2 through 6)
3: Data in “Typical” column is at 3.3V, +25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
4: This parameter is characterized, but not tested in manufacturing.
2015-2021 Microchip Technology Inc.
DS60001361J-page 737
PIC32MZ Graphics (DA) Family
TABLE 44-8:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical(2)
Maximum
Units
Conditions
Idle Current (IIDLE): Core Off, Clock on Base Current (1)
DC30
19
35
mA
8 MHz(3)
DC31
55
70
mA
100 MHz(3)
DC32
90
123
mA
200 MHz
Note 1:
2:
3:
The test conditions for IIDLE current measurements are as follows:
• VDDR1V8 = 1.8V
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL is disabled (USBMD = 1), VUSB3V3 is connected to VSS, PBCLKx divisor = 1:2 (‘x’ 7)
• CPU is in Idle mode (CPU core Halted)
• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared (except
USBMD)
• WDT, DMT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDDIO
• RTCC and JTAG are disabled
• I/O Analog Charge Pump is disabled (IOANCPEN bit (CFGCON) = 0)
• ADC Input Charge Pump is disabled (AICPMPEN bit (ADCCON1 = 0)
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
This parameter is characterized, but not tested in manufacturing.
DS60001361J-page 738
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-9:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC
CHARACTERISTICS(1,2)
Param.
No.
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Typical(2) Maximum Units
Conditions
Power-Down Current (IPD) (Note 1)
DC40k
9
14
mA
-40°C
DC40l
9.5
14
mA
+25°C
Sleep(1)
DC40m
15
25
mA
+85°C
Module Differential Current
DC44a
50
350
A
3.6V
Watchdog Timer Current: IWDT(3)
DC44b
3.5
5
mA
3.6V
ADC Current: IADC(3,4)
DC44c
50
350
µA
3.6V
Deadman Timer Current: IDMT
Note 1: The test conditions for IPD current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL is disabled (USBMD = 1), VUSB3V3 is connected to VSS
• CPU is in Sleep mode
• L1 Cache and Prefetch modules are disabled
• No peripheral modules are operating, (ON bit = 0), and the associated PMD bit is set. All clocks are
disabled ON bit (PBxDIV) = 0 (x 1,7)
• WDT, DMT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDDIO
• RTCC and JTAG are disabled
• Voltage regulator is in Stand-by mode (VREGS = 0; IOANCPEN = 0)
2: Data in the “Typical” column is at 3.3V, unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
4: Voltage regulator is operational (VREGS = 1).
2015-2021 Microchip Technology Inc.
DS60001361J-page 739
PIC32MZ Graphics (DA) Family
TABLE 44-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Param.
Symbol
No.
VIL
DI10
Characteristics
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min.
Typ.(1)
Max.
Units
Conditions
VSS
—
0.15 * VDDIO
V
—
Input Low Voltage
I/O Pins with PMP
I/O Pins
VSS
—
0.2 * VDDIO
V
DI18
SDAx, SCLx
VSS
—
0.3 * VDDIO
V
SMBus disabled
(Note 4)
DI19
SDAx, SCLx
VSS
—
0.8
V
SMBus enabled
(Note 4)
I/O Pins not 5V-tolerant(5)
0.65 * VDDIO
—
VDDIO
V
(Note 4)
I/O Pins 5V-tolerant with
PMP(5)
0.65 * VDDIO
—
5.5
V
(Note 4)
I/O Pins 5V-tolerant(5)
0.65 * VDDIO
—
5.5
V
DI28a
SDAx, SCLx on non-5V
tolerant pins(5)
0.65 * VDDIO
—
VDDIO
V
SMBus disabled
(Note 4)
DI29a
SDAx, SCLx on non-5V
tolerant pins(5)
2.1
—
VDDIO
V
SMBus enabled,
2.2V VPIN 5.5
(Note 4)
DI28b
SDAx, SCLx on 5V tolerant 0.65 * VDDIO
pins(5)
—
5.5
V
SMBus disabled
(Note 4)
DI29b
SDAx, SCLx on 5V tolerant
pins(5
2.1
—
5.5
V
SMBus enabled,
2.2V VPIN 5.5
(Note 4)
VIH
DI20
—
Input High Voltage
—
DI30
ICNPU
Change Notification
Pull-up Current
-400
-300
-50
A
VDDIO = 3.3V, VPIN =
VSS
DI31
ICNPD
Change Notification
Pull-down Current(4)
50
175
400
µA
VDDIO = 3.3V, VPIN =
VDDIO
IIL
Input Leakage Current
(Note 3)
DI50
I/O Ports
—
—
+1
A
VSS VPIN VDDIO,
Pin at high-impedance
DI51
Analog Input Pins
—
—
+1
A
VSS VPIN VDDIO,
Pin at high-impedance
DI55
MCLR(2)
—
—
+1
A
VSS VPIN VDDIO
DI56
OSC1
—
—
+1
A
VSS VPIN VDDIO,
HS mode
Note 1:
2:
3:
4:
5:
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
This parameter is characterized, but not tested in manufacturing.
See the pin name tables (Table 5 through Table 7) for the 5V-tolerant pins.
DS60001361J-page 740
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param. Sym.
Characteristic
Max. Units
Conditions(1)
Min.
Typ.
—
—
0.4
V
IOL 10 mA, VDDIO = 3.3V
—
—
0.4
V
IOL 15 mA, VDDIO = 3.3V
—
—
0.4
V
IOL 20 mA, VDDIO = 3.3V
Output Low Voltage
I/O Pins
4x Sink Driver Pins RA0-RA3, RA9, RA10, RA14, RA15
RB0, RB4, RB6, RB7, RB10, RB11, RB12,
RB14
RC12,RC15
RD6, RD7, RD11, RD14
RE8, RE9
RF2, RF3, RF8, RF12
RG15
RH0, RH1, RH4-RH14
RJ0-RJ2, RJ8, RJ9, RJ11
DO10
VOL
Output Low Voltage
I/O Pins:
8x Sink Driver Pins RA4, RA5
RB2, RB3, RB5, RB8, RB9, RB13, RB14,
RB15
RC1-RC4
RD0-RD3, RD9, RD10, RD12, RD13
RE0-RE7
RF0, RF1, RF4, RF5, RF13
RG0, RG1, RG6, RG7, RG8, RG9
RH2, RH3, RH7, RH15
RJ3-RJ7, RJ10, RJ12-RJ15
RK0-RK7
Output Low Voltage
I/O Pins:
12x Sink Driver Pins RA6, RA7
RD4, RD5
RG12-RG14
Note 1:
Parameters are characterized, but not tested.
2015-2021 Microchip Technology Inc.
DS60001361J-page 741
PIC32MZ Graphics (DA) Family
TABLE 44-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
Param. Sym.
Characteristic
-40°C TA +85°C for Industrial
Max. Units
Conditions(1)
Min.
Typ.
2.4
—
—
V
IOH -10 mA, VDDIO = 3.3V
2.4
—
—
V
IOH -15 mA, VDDIO = 3.3V
2.4
—
—
V
IOH -20 mA, VDDIO = 3.3V
Output High Voltage
I/O Pins
4x Sink Driver Pins RA0-RA3, RA9, RA10, RA14, RA15
RB0, RB4, RB6, RB7, RB10, RB11, RB12,
RB14
RC12, RC15
RD6, RD7, RD11, RD14
RE8, RE9
RF2, RF3, RF8, RF12
RG15
RH0, RH1, RH4-RH14
RJ0-RJ2, RJ8, RJ9, RJ11
DO20
VOH
Output High Voltage
I/O Pins:
8x Sink Driver Pins RA4, RA5
RB2, RB3, RB5, RB8, RB9, RB13, RB14,
RB15
RC1-RC4
RD0-RD3, RD9, RD10, RD12, RD13
RE0-RE7
RF0, RF1, RF4, RF5, RF13
RG0, RG1, RG6, RG7, RG8, RG9
RH2, RH3, RH7, RH15
RJ3-RJ7, RJ10, RJ12-RJ15
RK0-RK7
Output High Voltage
I/O Pins:
12x Source Driver Pins RA6, RA7
RD4, RD5
RG12-RG14
Note 1:
Parameters are characterized, but not tested.
DS60001361J-page 742
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
Param. Sym.
Characteristic
Output High Voltage
I/O Pins
4x Sink Driver Pins RA0-RA3, RA9, RA10, RA14, RA15
RB0, RB4, RB6, RB7, RB10, RB11, RB12,
RB14
RC12-RC15
RD6, RD7, RD11, RD14
RE8, RE9
RF2, RF3, RF8, RF12
RG15
RH0, RH1, RH4-RH14
RJ0-RJ2, RJ8, RJ9, RJ11
Output High Voltage
I/O Pins:
8x Sink Driver Pins -
-40°C TA +85°C for Industrial
Max. Units
Conditions(1)
Min.
Typ.
1.5
—
—
V
IOH -14 mA, VDDIO = 3.3V
2.0
—
—
V
IOH -12 mA, VDDIO = 3.3V
3.0
—
—
V
IOH -7 mA, VDDIO = 3.3V
1.5
—
—
V
IOH -22 mA, VDDIO = 3.3V
2.0
—
—
V
IOH -18 mA, VDDIO = 3.3V
3.0
—
—
V
IOH -10 mA, VDDIO = 3.3V
1.5
—
—
V
IOH -32 mA, VDDIO = 3.3V
2.0
—
—
V
IOH -25 mA, VDDIO = 3.3V
3.0
—
—
V
IOH -14 mA, VDDIO = 3.3V
DO20a VOH1 RA4, RA5
RB2, RB3, RB5, RB8, RB9, RB10, RB13,
RB14, RB15
RC1-RC4
RD0-RD3, RD9, RD10, RD12, RD13
RE0-RE7
RF0, RF1, RF4, RF5, RF13
RG0, RG1, RG6, RG7, RG8, RG9
RH2, RH3, RH7, RH15
RJ3-RJ7, RJ10, RJ12-RJ15
RK0-RK7
Output High Voltage
I/O Pins:
12x Source Driver Pins RA6, RA7
RD4, RD5
RG12-RG14
Note 1:
Parameters are characterized, but not tested.
2015-2021 Microchip Technology Inc.
DS60001361J-page 743
PIC32MZ Graphics (DA) Family
TABLE 44-12: DC CHARACTERISTICS: I/O PIN INPUT INJECTION CURRENT SPECIFICATIONS
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min.
Typ.(1)
Max.
Units
Conditions
This parameter applies
to all pins, with the
exception of RB10.
Maximum IICH current
for this exception is
0 mA.
DI60a
IICL
Input Low Injection
Current
0
—
-5(2,5)
mA
DI60b
IICH
Input High Injection
Current
0
—
+5(3,4,5)
mA
This parameter applies
to all pins, with the
exception of all 5V tolerant pins, SOSCI, and
RB10. Maximum IICH
current for these
exceptions is 0 mA.
DI60c IICT
Total Input Injection
-20(6)
—
+20(6)
mA Absolute instantaneous
Current (sum of all I/O
sum of all ± input
and control pins)
injection currents from
all I/O pins
( | IICL + | IICH | ) IICT
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: VIL source < (VSS - 0.3). Characterized but not tested.
3: VIH source > (VDDIO + 0.3) for non-5V tolerant pins only.
4: Digital 5V tolerant pins do not have an internal high side diode to VDDIO, and therefore, cannot tolerate any
“positive” input injection current.
5: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source >
(VDDIO + 0.3) or VIL source < (VSS - 0.3)).
6: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. If Note 2, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 3, IICH = ((IICH source - (VDDIO + 0.3)) /
RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3) VSOURCE (VDDIO +
0.3), injection current = 0.
DS60001361J-page 744
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-13: DDR2 SDRAM CONTROLLER I/O SPECIFICATIONS
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min.
Typ.
Max.
Units
Conditions
DDR1
VOH
Output High
Voltage
VDDR1V8 –
0.28
—
—
V
—
DDR2
VOL
Output Low
Voltage
—
—
0.28
V
—
DDR5
VIH
Input High Voltage
DDRVREF +
0.125
—
VDDR1V8 + 0.3
—
—
DDR6
VIL
Input Low Voltage
0.3
—
DDRVREF –
0.125
—
—
Note 1:
These parameters are characterized but not tested.
TABLE 44-14: SD HOST CONTROLLER I/O SPECIFICATIONS
DC CHARACTERISTICS
Param.
Symbol
No.
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Characteristic
Min.
Typ.
Max.
Units
Conditions
2.4
—
—
V
IOH 20 mA, VDDIO = 3.3V
IOL 20 mA, VDDIO = 3.3V
SD10
VOH
Output High Voltage
SD11
VOL
Output Low Voltage
—
—
0.4
V
SD12
VIH
Input High Voltage
0.65*VDDIO
—
VDDIO
V
—
SD13
VIL
Input Low Voltage
VSS
—
0.2*VDDIO
V
—
2015-2021 Microchip Technology Inc.
DS60001361J-page 745
PIC32MZ Graphics (DA) Family
TABLE 44-15: DC CHARACTERISTICS: PROGRAM MEMORY(3)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param.
Sym.
No.
D130a
EP
Characteristics
Cell Endurance
D130b
D131
VPR
D132
VPEW VDDCORE for Erase or Write
D134a
TRETD Characteristic Retention
VDDCORE for Read
Typ.(1)
Max.
Units
10,000
—
—
E/W
Without ECC
20,000
—
—
E/W
With ECC
Conditions
VDDCOREMIN
—
VDDCOREMAX
V
—
VDDCOREMIN
—
VDDCOREMAX
V
—
10
—
—
Year
Without ECC
20
—
—
Year
With ECC
D134b
D135
Min.
IDDP
Supply Current during
Programming
—
—
30
mA
—
Row Write Cycle Time (Notes 2, 4)
—
66813
—
FRC Cycles
—
773
—
FRC Cycles
—
D136
TRW
D137
TQWW Quad Word Write Cycle Time
(Note 4)
D138
TWW
Word Write Cycle Time (Note 4)
—
383
—
FRC Cycles
—
D139
TCE
Chip Erase Cycle Time (Note 4)
—
515373
—
FRC Cycles
—
D140
TPFE
All Program Flash (Upper and Lower
regions) Erase Cycle Time (Note 4)
—
256909
—
FRC Cycles
—
D141
TPBE
Program Flash (Upper or Lower
regions) Erase Cycle Time (Note 4)
—
128453
—
FRC Cycles
—
D142
TPGE
Page Erase Cycle Time (Note 4)
—
128453
—
FRC Cycles
—
Note 1:
2:
3:
4:
—
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
The minimum PBCLK5 for row programming is 4 MHz.
Refer to the “PIC32 Flash Programming Specification” (DS60001145) for operating conditions during
programming and erase cycles.
Translating this value to seconds depends on FRC accuracy (see Table 44-27) and FRC tuning values (see the
OSCTUN register: Register 8-2).
TABLE 44-16: DC CHARACTERISTICS: PROGRAM FLASH MEMORY WAIT STATES
DC CHARACTERISTICS
Required Flash Wait States(1)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
SYSCLK
Units
Conditions
MHz
—
MHz
—
With ECC:
0 Wait states
1 Wait state
2 Wait states
0 < SYSCLK 60
60 < SYSCLK 120
120 < SYSCLK 200
Without ECC:
0 Wait states
1 Wait state
2 Wait states
Note 1:
0 < SYSCLK 74
74 < SYSCLK 140
140 < SYSCLK 200
To use Wait states, the Prefetch module must be enabled (PREFEN 00) and the PFMWS
bits must be written with the desired Wait state value.
DS60001361J-page 746
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-17: DC CHARACTERISTICS: DDR2 SDRAM MEMORY
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param.
Nos.
(Note 1)
Symbol
Characteristics
Min.
Typ.
Max. Units
Conditions
DDRM12 IDD0
Operating Current, One Bank
Active Precharge
—
—
60
mA
Note 2
DDRM13 IDD1
Operating Current, One Back
Active-Read Precharge
—
—
70
mA
Note 2
DDRM14 IDD2
Precharge Power-Down Current
—
—
6
mA
Note 3
DDRM15 IDD3
Precharge Stand-by Current
—
—
40
mA
Note 2
DDRM16 IDD4
Precharge Quiet Stand-by Current
—
—
35
mA
Note 4
DDRM17 IDD5
Active Power-Down Current
—
—
12
mA
Note 3
DDRM18 IDD6
Active Stand-by Current
—
—
50
mA
Note 2
DDRM19 IDD7
Operating Burst Read Current
—
—
105
mA
Note 2
DDRM20 IDD8
Operating Burst Write Current
—
—
110
mA
Note 2
DDRM21 IDD9
Burst Refresh Current
—
—
70
mA
Note 2
DDRM22 IDD10
Self-Refresh Current
—
—
6
mA
Note 5
DDRM23 IDD11
Operating Bank Interleave Read
Current
—
—
135
mA
Note 6
Note 1:
2:
3:
4:
5:
6:
These parameters are characterized, but not tested in manufacturing. The specifications are only valid
after the memory is initialized.
DDRCKE is high, DDRCS0 is high between valid commands. Address, control, and data bus inputs are
switching.
DDRCKE is low. Other control and address inputs are stable. Data bus inputs are floating.
DDRCKE is high and DDRCS0 is high. Other control and address inputs are stable. Data bus inputs are
floating.
DDRCKE is low and DDRCK/DDRCK are low. Other control and address inputs are floating. Data bus
inputs are floating.
DDRCKE is high and DDRCS0 is high between valid commands. Address bus inputs are stable. Data bus
inputs are switching.
2015-2021 Microchip Technology Inc.
DS60001361J-page 747
PIC32MZ Graphics (DA) Family
TABLE 44-18: COMPARATOR SPECIFICATIONS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typ.
Max.
Units
Comments
D300
VIOFF
Input Offset Voltage
—
±10
—
mV
AVDD = VDDIO,
AVSS = VSS
D301
VICM
Input Common Mode Voltage
0.8
—
2.37
V
AVDD = VDDIO,
AVSS = VSS
(Note 2)
D302
CMRR
Common Mode Rejection Ratio
50
—
—
dB
Max VICM = (VDDIO - 1)V
(Note 2)
D303
TRESP
Small Signal Response Time
—
150
—
ns
VCM = VDD/2 in 100 mV
steps
(Notes 1,2)
D304
ON2OV
Comparator Enabled to Output
Valid
—
—
10
s
Comparator module is
configured before setting
the comparator ON bit
(Note 2)
D305
IVREF
Internal Voltage Reference
—
1.2
—
V
—
D306
VHYST
Input Hysteresis Voltage
48
120
192
mV
—
Note 1:
2:
These parameters are characterized but not tested.
The Comparator module is functional at VBORIOMIN < VDDIO < VDDIOMIN, but with degraded performance.
Unless otherwise stated, module functionality is guaranteed, but not characterized.
DS60001361J-page 748
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-19: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
DC CHARACTERISTICS
Param.
Symbol
No.
D312
D313
D314
D315
D316
Note
Characteristics
TSET
Internal 4-bit DAC
Comparator Reference
Settling time
DACREFH CVREF Input Voltage
Reference Range
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min.
Typ.
Max.
Units
—
—
10
µs
AVSS
VREF0
—
—
—
AVDD
VREF+
0.625 x
DACREFH
0.719 x
DACREFH
V
V
V
Comments
See Note 1
CVRSRC with CVRSS = 0
CVRSRC with CVRSS = 1
DVREF
CVREF Programmable
0 to 0.625 DACREFH with
Output Range
DACREFH/24 step size
0.25 x
—
V
0.25 x DACREFH to 0.719
DACREFH
DACREFH with DACREFH/32
step size
DACRES Resolution
—
—
DACREFH/24
CVRCON = 1
—
—
DACREFH/32
CVRCON = 0
DACACC Absolute Accuracy(2)
—
—
1/4
LSB DACREFH/24,
CVRCON = 1
—
—
1/2
LSB DACREFH/32,
CVRCON = 0
1: Settling time was measured while CVRR = 1 and CVR transitions from ‘0000’ to ‘1111’. This parameter is characterized, but is not tested in manufacturing.
2: These parameters are characterized but not tested.
2015-2021 Microchip Technology Inc.
DS60001361J-page 749
PIC32MZ Graphics (DA) Family
TABLE 44-20: CTMU CURRENT SOURCE SPECIFICATIONS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
DC CHARACTERISTICS
-40°C TA +85°C for Industrial
Operating temperature
Param
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
—
0.55
—
µA
CTMUCON = 01
CTMU CURRENT SOURCE
CTMUI1
Base Range(1)
IOUT1
(1)
CTMUI2
IOUT2
10x Range
—
5.5
—
µA
CTMUCON = 10
CTMUI3
IOUT3
100x Range(1)
—
55
—
µA
CTMUCON = 11
CTMUI4
IOUT4
CTMUFV1 VF
CTMUFV2 VFVR
Note 1:
2:
(1)
1000x Range
—
550
—
µA
CTMUCON = 00
Temperature Diode Forward
Voltage(1,2)
—
0.598
—
V
TA = +25ºC,
CTMUCON = 01
—
0.658
—
V
TA = +25ºC,
CTMUCON = 10
—
0.721
—
V
TA = +25ºC,
CTMUCON = 11
—
-1.92
—
mV/ºC CTMUCON = 01
—
-1.74
—
mV/ºC CTMUCON = 10
—
-1.56
—
mV/ºC CTMUCON = 11
Temperature Diode Rate of
Change(1,2)
Nominal value at center point of current trim range (CTMUCON = 000000).
Parameters are characterized but not tested in manufacturing. Measurements taken with the following
conditions:
• VREF+ = AVDD = 3.3V
• ADC module configured for conversion speed of 500 ksps
• All PMD bits are cleared (PMDx = 0)
• Executing a while(1) statement
• Device operating from the FRC with no PLL
TABLE 44-21: GLCD CONTROLLER DC SPECIFICATIONS
DC CHARACTERISTICS
Param.
Symbol
No.
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Characteristic
Min.
Typ.
Max.
Units
Conditions
2.4
—
—
V
IOH 20 mA, VDDIO = 3.3V
IOL 20 mA, VDDIO = 3.3V
GD10
VOH
Output High Voltage
GD11
VOL
Output Low Voltage
—
—
0.4
V
GD12
VIH
Input High Voltage
0.65*VDDIO
—
VDDIO
V
—
GD13
VIL
Input Low Voltage
VSS
—
0.2*VDDIO
V
—
DS60001361J-page 750
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
44.2
AC Characteristics and Timing
Parameters
The information contained in this section defines
PIC32MZ DA device AC characteristics and timing
parameters.
FIGURE 44-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2 (in EC mode)
VDDIO/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
VSS
TABLE 44-22: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Min.
Typ.(1)
Characteristics
Max.
Units
Conditions
DO56
CL
All I/O pins
—
—
50
pF
EC mode for OSC2
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C mode
DO59
CSQI
All SQI pins
—
—
10
pF
Note 1:
—
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2015-2021 Microchip Technology Inc.
DS60001361J-page 751
PIC32MZ Graphics (DA) Family
FIGURE 44-2:
EXTERNAL CLOCK TIMING
OS30
OS20
OS31
OSC1
OS31
OS30
TABLE 44-23: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
OS10
FOSC
OS13
Characteristics
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
Oscillator Crystal Frequency
OS15
Min.
Typ.(1)
Max.
Units
DC
—
64
MHz
EC (Note 2)
Conditions
4
—
32
MHz
HS (Note 2)
32
32.768
100
kHz
SOSC (Note 2)
—
—
—
—
See parameter
OS10 for FOSC
value
OS20
TOSC
TOSC = 1/FOSC
OS30
TOSL,
TOSH
External Clock In (OSC1)
High or Low Time
0.375 x TOSC
—
—
ns
EC (Note 2)
OS31
TOSR,
TOSF
External Clock In (OSC1)
Rise or Fall Time
—
—
7.5
ns
EC (Note 2)
OS40
TOST
Oscillator Start-up Timer Period
(Only applies to HS, HSPLL,
and SOSC Clock Oscillator
modes)
—
1024
—
OS41
TFSCM
Primary Clock Fail Safe
Time-out Period
—
2
—
ms
OS42
GM
External Oscillator
Transconductance (Primary
Oscillator Only)
—
400
—
µA/V
Note 1:
2:
TOSC (Note 2)
(Note 2)
VDDIO = 3.3V,
TA = +25°C
(Note 2)
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are characterized but are
not tested.
This parameter is characterized, but not tested in manufacturing.
DS60001361J-page 752
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-24: SYSTEM TIMING REQUIREMENTS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
OS51
OS55a
FSYS
Characteristics
System Frequency
FPB
Peripheral Bus Frequency
FREF
Reference Clock Frequency
OS55b
OS56
Min.
Typ.
Max.
Units
Conditions
DC
—
200
MHz
USB module disabled
30
—
200
MHz
USB module enabled
DC
—
100
MHz
For PBCLKx, ‘x’ < 7
DC
—
200
MHz
For PBCLK7
—
—
50
MHz
For REFCLKI1, REFCLKI3,
REFCLKI4, REFCLKO1,
REFCLKO3, and REFCLKO4 pins
TABLE 44-25: SPLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typ.
Max.
Units
Conditions
OS50
FIN
PLL Input Frequency Range
5
—
64
MHz
ECPLL, HSPLL, FRCPLL
modes
OS52
TLOCK
PLL Start-up Time (Lock Time)
—
—
100
µs
—
Stability(2)
OS53
DCLK
CLKO
(Period Jitter or Cumulative)
-0.25
—
+0.25
%
OS54
FVCO
PLL VCO Frequency Range
350
—
700
MHz
—
OS54a
FPLL
PLL Output Frequency Range
10
—
200
MHz
—
Note 1:
2:
Measured over 100 ms
period
These parameters are characterized, but not tested in manufacturing.
This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for
individual time-bases on communication clocks, use the following formula:
D CLK
EffectiveJitter = -------------------------------------------------------------PBCLK2
--------------------------------------------------------CommunicationClock
For example, if PBCLK2 = 100 MHz and SPI bit rate = 50 MHz, the effective jitter is as follows:
D CLK
D CLK
EffectiveJitter = -------------- = -------------1.41
100
--------50
2015-2021 Microchip Technology Inc.
DS60001361J-page 753
PIC32MZ Graphics (DA) Family
TABLE 44-26: MPLL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic(1)
MP10
MFIN
MPLL Input Frequency
MP11
MFVCO MPLL Vco Frequency Range
Min.
Typ.
Max.
Units
Conditions
8
—
64
MHz
—
400
—
1600
MHz
—
MP12
MFMPLL MPLL Output Frequency
8
—
200
MHz
—
MP13
MLOCK
MPLL Start-up Time (Lock Time)
—
—
1500 x 1/MFIN
µs
—
MP14
MPJ
MPLL Period Jitter
—
0.015
%
—
MP15
MCJ
MPLL Cycle Jitter
—
—
0.02
%
—
MP16
MLTJ
MPLL Long-term Jitter
—
—
0.5
%
—
Note 1:
These parameters are characterized, but not tested in manufacturing.
DS60001361J-page 754
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-27:
INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Param.
No.
Characteristics
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min.
Typ.
Max.
Units
Conditions
-5
—
+5
%
0°C TA +85°C
-8
—
+8
%
-40°C TA +85°C
Internal FRC Accuracy @ 8.00 MHz(1)
F20
Note 1:
FRC
Frequency calibrated at +25°C and 3.3V. The TUN bits can be used to compensate for temperature drift.
TABLE 44-28: INTERNAL LPRC ACCURACY
AC CHARACTERISTICS
Param.
No.
Characteristics
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min.
Typ.
Max.
Units
-8
-25
Conditions
—
+8
%
0°C TA +85°C
—
+25
%
-40°C TA +85°C
LPRC @ 31.25 kHz(1)
F21
Note 1:
LPRC
Change of LPRC frequency as VDDIO changes.
TABLE 44-29: INTERNAL BACKUP FRC (BFRC) ACCURACY
AC CHARACTERISTICS
Param.
No.
Characteristics
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min.
Typ.
Max.
Units
Conditions
-30
—
+30
%
—
Internal BFRC Accuracy @ 8 MHzl
F22
BFRC
2015-2021 Microchip Technology Inc.
DS60001361J-page 755
PIC32MZ Graphics (DA) Family
FIGURE 44-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
Note: Refer to Figure 44-1 for load conditions.
DO31
DO32
TABLE 44-30: I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Param.
No.
DO31
Characteristics(2)
Symbol
TIOR
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Port Output Rise Time
I/O Pins:
4x Source Driver Pins RA3, RA9, RA10, RA14, RA15
RB0-7, RB11, RB13
RC12-RC15
RD0, RD6-RD7, RD11, RD14
RE8, RE9
RF2, RF3, RF8
RG15
RH0, RH1, RH4-RH6, RH8-RH13
RJ0-RJ2, RJ8, RJ9, RJ11
Port Output Rise Time
I/O Pins:
8x Source Driver Pins RA0-RA2, RA4, RA5
RB8-RB10, RB12, RB14, RB15
RC1-RC4
RD1-RD5, RD9, RD10, RD12,
RD13, RD15
RE4-RE7
RF0, RF4, RF5, RF12, RF13
RG0, RG1, RG6-RG9
RH2, RH3, RH7, RH14, RH15
RJ3-RJ7, RJ10, RJ12-RJ15
RK0-RK7
Port Output Rise Time
I/O Pins:
12x Source Driver Pins RA6, RA7
RE0-RE3
RF1
RG12-RG14
Note 1:
2:
Min.
Typ.(1)
Max.
Units
—
—
9.5
ns
CLOAD = 50 pF
—
—
6
ns
CLOAD = 20 pF
—
—
8
ns
CLOAD = 50 pF
—
—
6
ns
CLOAD = 20 pF
—
—
3.5
ns
CLOAD = 50 pF
—
—
2
ns
CLOAD = 20 pF
Conditions
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
This parameter is characterized, but not tested in manufacturing.
DS60001361J-page 756
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-30: I/O TIMING REQUIREMENTS (CONTINUED)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
DO32
Symbol
TIOF
Characteristics(2)
Port Output Fall Time
I/O Pins:
4x Source Driver Pins RA3, RA9, RA10, RA14, RA15
RB0-7, RB11, RB13
RC12-RC15
RD0, RD6-RD7, RD11, RD14
RE8, RE9
RF2, RF3, RF8
RG15
RH0, RH1, RH4-RH6, RH8-RH13
RJ0-RJ2, RJ8, RJ9, RJ11
Port Output Fall Time
I/O Pins:
8x Source Driver Pins RA0-RA2, RA4, RA5
RB8-RB10, RB12, RB14, RB15
RC1-RC4
RD1-RD5, RD9, RD10, RD12,
RD13, RD15
RE4-RE7
RF0, RF4, RF5, RF12, RF13
RG0, RG1, RG6-RG9
RH2, RH3, RH7, RH14, RH15
RJ3-RJ7, RJ10, RJ12-RJ15
RK0-RK7
Port Output Fall Time
I/O Pins:
12x Source Driver Pins RA6, RA7
RE0-RE3
RF1
RG12-RG14
Min.
Typ.(1)
Max.
Units
—
—
9.5
ns
CLOAD = 50 pF
—
—
6
ns
CLOAD = 20 pF
—
—
8
ns
CLOAD = 50 pF
—
—
6
ns
CLOAD = 20 pF
—
—
3.5
ns
CLOAD = 50 pF
—
—
2
ns
CLOAD = 20 pF
—
—
ns
ns
DI35
TINP
INTx Pin High or Low Time
5
—
DI40
TRBP
CNx High or Low Time (input)
5
—
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
2: This parameter is characterized, but not tested in manufacturing.
2015-2021 Microchip Technology Inc.
Conditions
—
—
DS60001361J-page 757
PIC32MZ Graphics (DA) Family
FIGURE 44-4:
POWER-ON RESET TIMING CHARACTERISTICS
Internal Voltage Regulator Enabled
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDDCORE
VPORCORE
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
CPU Starts Fetching Code
SY00
(TPU)
(Note 1)
Internal Voltage Regulator Enabled
Clock Sources = (HS, HSPLL, and SOSC)
VDDCORE
VPORCORE
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
SY00
(TPU)
(Note 1)
Note 1:
2:
OS40
(TOST)
CPU Starts Fetching Code
The power-up period will be extended if the power-up sequence completes before the device exits from BOR
(VDDIO < VDDIOMIN).
Includes interval voltage regulator stabilization delay.
DS60001361J-page 758
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
FIGURE 44-5:
EXTERNAL RESET TIMING CHARACTERISTICS
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
MCLR
TMCLR
(SY20)
VBORIO
TBOR
(SY30)
(TSYSDLY)
SY02
Reset Sequence
CPU Starts Fetching Code
Clock Sources = (HS, HSPLL, and SOSC)
(TSYSDLY)
SY02
Reset Sequence
CPU Starts Fetching Code
TOST
(OS40)
TABLE 44-31: RESETS TIMING
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typ.(2)
Max.
Units
Conditions
SY00
TPU
Power-up Period
Internal Voltage Regulator Enabled
—
400
600
s
—
SY02
TSYSDLY System Delay Period:
Time Required to Reload Device
Configuration Fuses plus SYSCLK
Delay before First instruction is
Fetched.
—
s +
8 SYSCLK
cycles
—
—
—
SY20
TMCLR
MCLR Pulse Width (low)
2
—
—
s
—
SY30
TBOR
BOR Pulse Width (low)
—
1
—
s
—
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Characterized by design but not tested.
2015-2021 Microchip Technology Inc.
DS60001361J-page 759
PIC32MZ Graphics (DA) Family
FIGURE 44-6:
TIMER1-TIMER9 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRx
Note: Refer to Figure 44-1 for load conditions.
TABLE 44-32: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
TA10
TA11
TA15
Symbol
TTXH
TTXL
TTXP
Characteristics(2)
TxCK
High Time
TxCK
Low Time
Typ. Max.
Units
Conditions
Synchronous, [(12.5 ns or 1 TPBCLK3)
with prescaler
/N] + 20 ns
—
—
ns
Must also meet
parameter TA15
(Note 3)
Asynchronous,
with prescaler
—
—
ns
—
Synchronous, [(12.5 ns or 1 TPBCLK3)
with prescaler
/N] + 20 ns
—
—
ns
Must also meet
parameter TA15
(Note 3)
Asynchronous,
with prescaler
10
—
—
ns
—
[(Greater of 20 ns or
2 TPBCLK3)/N] + 30 ns
—
—
ns
VDDIO > 2.7V
(Note 3)
[(Greater of 20 ns or
2 TPBCLK3)/N] + 50 ns
—
—
ns
VDDIO < 2.7V
(Note 3)
20
—
—
ns
VDDIO > 2.7V
50
—
—
ns
VDDIO < 2.7V
32
—
50
kHz
—
—
—
1
TPBCLK3
—
TxCK
Synchronous,
Input Period with prescaler
Asynchronous,
with prescaler
OS60
FT1
TA20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
Note 1:
2:
3:
Min.
SOSC1/T1CK Oscillator
Input Frequency Range
(oscillator enabled by setting
TCS bit (T1CON))
10
Timer1 is a Type A.
This parameter is characterized, but not tested in manufacturing.
N = Prescale Value (1, 8, 64, 256).
DS60001361J-page 760
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-33: TIMER2-TIMER9 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Max.
Units
Conditions
TB10
TTXH
TxCK
Synchronous, with
High Time prescaler
[(12.5 ns or 1 TPBCLK3)
/N] + 25 ns
—
ns
Must also
meet
parameter
TB15
TB11
TTXL
TxCK
Synchronous, with
Low Time prescaler
[(12.5 ns or 1 TPBCLK3)
/N] + 25 ns
—
ns
Must also
meet
parameter
TB15
TB15
TTXP
TxCK
Input
Period
[(Greater of [(25 ns or
2 TPBCLK3)/N] + 30 ns
—
ns
VDDIO >
2.7V
[(Greater of [(25 ns or
2 TPBCLK3)/N] + 50 ns
—
ns
VDDIO <
2.7V
—
1
TPBCLK3
TB20
Synchronous, with
prescaler
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer Increment
Note 1:
N = prescale
value
(1, 2, 4, 8,
16, 32, 64,
256)
—
These parameters are characterized, but not tested in manufacturing.
FIGURE 44-7:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 44-1 for load conditions.
TABLE 44-34: INPUT CAPTURE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param.
Symbol
No.
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Characteristics(1)
Min.
Max.
Units
Conditions
IC10
TCCL
ICx Input Low Time
[(12.5 ns or 1 TPBCLK3)
/N] + 25 ns
—
ns
Must also
meet
parameter
IC15.
IC11
TCCH
ICx Input High Time
[(12.5 ns or 1 TPBCLK3)
/N] + 25 ns
—
ns
Must also
meet
parameter
IC15.
IC15
TCCP
ICx Input Period
[(25 ns or 2 TPBCLK3)
/N] + 50 ns
—
ns
Note 1:
These parameters are characterized, but not tested in manufacturing.
2015-2021 Microchip Technology Inc.
N = prescale
value (1, 4, 16)
—
DS60001361J-page 761
PIC32MZ Graphics (DA) Family
FIGURE 44-8:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM mode)
OC10
OC11
Note: Refer to Figure 44-1 for load conditions.
TABLE 44-35: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typ.(2)
Max.
Units
Conditions
OC10
TCCF
OCx Output Fall Time
—
—
—
ns
See parameter DO32
OC11
TCCR
OCx Output Rise Time
—
—
—
ns
See parameter DO31
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
FIGURE 44-9:
OCx/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCx
OCx is tri-stated
Note: Refer to Figure 44-1 for load conditions.
TABLE 44-36: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Symbol
Characteristics(1)
Min,
Typ.(2)
Max,
Units
Conditions
OC15
TFD
Fault Input to PWM I/O Change
—
—
50
ns
—
OC20
TFLT
Fault Input Pulse Width
50
—
—
ns
—
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
DS60001361J-page 762
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
FIGURE 44-10:
SPIx MODULE HOST MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
SP31
SDIx
MSb In
LSb
SP30
Bit 14 - - - -1
LSb In
SP40 SP41
Note: Refer to Figure 44-1 for load conditions.
2015-2021 Microchip Technology Inc.
DS60001361J-page 763
PIC32MZ Graphics (DA) Family
TABLE 44-37: SPIx HOST MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typ.(2) Max. Units
Conditions
—
—
—
—
ns
ns
TSCF
SCKx Output Low Time (Note 3) TSCK/2
SCKx Output High Time (Note 3) TSCK/2
SPI Clock Speed (Note 5)
—
—
—
—
—
SCKx Output Fall Time (Note 4)
—
—
—
—
—
—
—
25
50
25
50
25
—
MHz
MHz
MHz
MHz
MHz
ns
SP21
TSCR
SCKx Output Rise Time (Note 4)
—
—
—
ns
See parameter DO31
SP30
TDOF
—
—
—
ns
See parameter DO32
—
—
—
ns
See parameter DO31
—
—
7
ns
VDDIO > 2.7V
SP10
SP11
TSCL
TSCH
SP15
TSCK
SP20
SDOx Data Output Fall Time
(Note 4)
TDOR
SDOx Data Output Rise Time
(Note 4)
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
SP31
SP35
SP40
SP41
Note 1:
2:
3:
4:
5:
Note 5
Note 5
SPI1, SPI3, SPI4, SPI6
SPI2 on RPG7, RPG8
SPI2 on other I/O
SPI5 on RPC1, RPC4
SPI5 on other I/O
See parameter DO32
—
—
ns VDDIO < 2.7V
10
TDIV2SCH, Setup Time of SDIx Data Input to
—
—
ns
—
5
TDIV2SCL SCKx Edge
—
—
ns
—
TSCH2DIL, Hold Time of SDIx Data Input
5
TSCL2DIL to SCKx Edge
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The minimum clock period for SCKx is 20 ns. Therefore, the clock generated in Host mode must not
violate this specification.
Assumes 30 pF load on all SPIx pins.
To achieve maximum data rate, VDDIO must be greater than or equal to 3.0V and the SMP bit
(SPIxCON) must be set to ‘1’.
DS60001361J-page 764
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
FIGURE 44-11:
SPIx MODULE HOST MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11
SCKX
(CKP = 1)
SP10
SP21
SP20
SP20
SP21
SP35
Bit 14 - - - - - -1
MSb
SDOX
LSb
SP30,SP31
SDIX
MSb In
SP40
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 44-1 for load conditions.
2015-2021 Microchip Technology Inc.
DS60001361J-page 765
PIC32MZ Graphics (DA) Family
TABLE 44-38: SPIx MODULE HOST MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min. Typ.(2)
Max.
Units
Conditions
SP10
TSCL
SCKx Output Low Time (Note 3) TSCK/2
—
—
ns
Note 5
SP11
TSCH
SCKx Output High Time (Note 3) TSCK/2
—
—
ns
Note 5
SP15
TSCK
SPI Clock Speed (Note 5)
—
—
—
—
—
—
—
—
—
—
25
50
25
50
25
MHz
MHz
MHz
MHz
MHz
SP20
TSCF
SCKx Output Fall Time (Note 4)
—
—
—
ns
See parameter DO32
SP21
TSCR
SCKx Output Rise Time (Note 4)
—
—
—
ns
See parameter DO31
SP30
TDOF
SDOx Data Output Fall Time
(Note 4)
—
—
—
ns
See parameter DO32
SP31
TDOR
SDOx Data Output Rise Time
(Note 4)
—
—
—
ns
See parameter DO31
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
7
ns
SP36
TDOV2SC, SDOx Data Output Setup to
TDOV2SCL First SCKx Edge
SP40
TDIV2SCH, Setup Time of SDIx Data Input to
TDIV2SCL SCKx Edge
SP41
TSCH2DIL,
TSCL2DIL
Note 1:
2:
3:
4:
5:
Hold Time of SDIx Data Input
to SCKx Edge
—
10
SPI1, SPI3, SPI4, SPI6
SPI2 on RPG7, RPG8
SPI2 on other I/O
SPI5 on RPC1, RPC4
SPI5 on other I/O
VDDIO > 2.7V
VDDIO < 2.7V
7
—
—
ns
7
—
—
ns
10
—
VDDIO > 2.7V
VDDIO < 2.7V
7
—
—
ns
VDDIO > 2.7V
10
—
—
ns
VDDIO < 2.7V
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The minimum clock period for SCKx is 20 ns. Therefore, the clock generated in Host mode must not
violate this specification.
Assumes 30 pF load on all SPIx pins.
To achieve maximum data rate, VDDIO must be greater than or equal to 3.0V and the SMP bit (SPIxCON) must be set to ‘1’.
DS60001361J-page 766
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
FIGURE 44-12:
SPIx MODULE CLIENT MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
LSb
Bit 14 - - - - - -1
SP51
SP30,SP31
SDIX
MSb In
SP40
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 44-1 for load conditions.
TABLE 44-39: SPIx MODULE CLIENT MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for
Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
SP71
SP72
SP73
SP30
SP31
SP35
TSCL
TSCH
TSCF
TSCR
TDOF
TDOR
TSCH2DOV,
TSCL2DOV
SCKx Input Low Time (Note 3)
SCKx Input High Time (Note 3)
SCKx Input Fall Time
SCKx Input Rise Time
SDOx Data Output Fall Time (Note 4)
SDOx Data Output Rise Time (Note 4)
SDOx Data Output Valid after
SCKx Edge
SP40
TDIV2SCH,
TDIV2SCL
TSCH2DIL,
TSCL2DIL
TSSL2SCH,
TSSL2SCL
TSSH2DOZ
Setup Time of SDIx Data Input
to SCKx Edge
Hold Time of SDIx Data Input
to SCKx Edge
SSx to SCKx or SCKx Input
TSCK/2
TSCK/2
—
—
—
—
—
—
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7
10
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 5
Note 5
See parameter DO32
See parameter DO31
See parameter DO32
See parameter DO31
VDDIO > 2.7V
VDDIO < 2.7V
—
5
—
—
ns
—
88
—
—
ns
—
SP41
SP50
SP51
SP52
Note 1:
2:
3:
4:
5:
SSx to SDOx Output
2.5
—
12
ns
—
High-Impedance (Note 3)
TSCH2SSH SSx after SCKx Edge
10
—
—
ns
—
TSCL2SSH
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The minimum clock period for SCKx is 20 ns.
Assumes 10 pF load on all SPIx pins.
TSCK is 40 ns for SPI1, SPI3, SPI4, and SPI6 and it is 20 ns for SPI2 and SPI5.
2015-2021 Microchip Technology Inc.
DS60001361J-page 767
PIC32MZ Graphics (DA) Family
FIGURE 44-13:
SPIx MODULE CLIENT MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30,SP31
SDIx
SDI
MSb In
SP40
SP51
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 44-1 for load conditions.
TABLE 44-40: SPIx MODULE CLIENT MODE (CKE = 1) TIMING REQUIREMENTS
(‘x’ = 1, 3, 4, 6)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
TSCL
SCKx Input Low Time (Note 3)
TSCK/2
—
—
ns
Note 5
SP71
TSCH
SCKx Input High Time (Note 3)
TSCK/2
—
—
ns
Note 5
SP72
TSCF
SCKx Input Fall Time
—
—
10
ns
SP73
TSCR
SCKx Input Rise Time
—
—
10
ns
—
SP30
TDOF
SDOx Data Output Fall Time
(Note 4)
—
—
—
ns
See parameter DO32
SP31
TDOR
SDOx Data Output Rise Time
(Note 4)
—
—
—
ns
See parameter DO31
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
10
ns
VDDIO > 2.7V
—
—
15
ns
VDDIO < 2.7V
SP40
TDIV2SCH, Setup Time of SDIx Data Input
TDIV2SCL to SCKx Edge
0
—
—
ns
—
SP41
TSCH2DIL, Hold Time of SDIx Data Input
TSCL2DIL to SCKx Edge
7
—
—
ns
—
Note 1:
2:
3:
4:
5:
—
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The minimum clock period for SCKx is 20 ns.
Assumes 10 pF load on all SPIx pins.
TSCK is 40 ns for SPI1, SPI3, SPI4, and SPI6 and it is 20 ns for SPI2 and SPI5.
DS60001361J-page 768
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-40: SPIx MODULE CLIENT MODE (CKE = 1) TIMING REQUIREMENTS
(‘x’ = 1, 3, 4, 6) (CONTINUED)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature
Param.
No.
Symbol
Characteristics(1)
-40°C TA +85°C for Industrial
Min.
Typ.(2)
Max.
Units
Conditions
SP50
TSSL2SCH, SSx to SCKx or SCKx Input
TSSL2SCL
88
—
—
ns
—
SP51
TSSH2DOZ SSx to SDOX Output
High-Impedance
(Note 4)
2.5
—
12
ns
—
SP52
TSCH2SSH SSx after SCKx Edge
TSCL2SSH
10
—
—
ns
—
SP60
TSSL2DOV SDOx Data Output Valid after
SSx Edge
—
—
12.5
ns
—
Note 1:
2:
3:
4:
5:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The minimum clock period for SCKx is 20 ns.
Assumes 10 pF load on all SPIx pins.
TSCK is 40 ns for SPI1, SPI3, SPI4, and SPI6 and it is 20 ns for SPI2 and SPI5.
2015-2021 Microchip Technology Inc.
DS60001361J-page 769
PIC32MZ Graphics (DA) Family
FIGURE 44-14:
SQI SERIAL INPUT TIMING CHARACTERISTICS
T CPH
CE#
T CHH
T CEH
T CES
T CHS
SCK
T DS
SIO
TDH
T SCKF
T SCKR
MSB
FIGURE 44-15:
LSB
SQI SERIAL OUTPUT TIMING CHARACTERISTICS
CE#
T SCKH
TSCKL
SCK
T OH
TCLZ
T CHZ
MSB
SIO
LSB
TV
TABLE 44-41: SQI TIMING REQUIREMENTS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristic
SQ10
FCLK
Serial Clock Frequency
(1/TSQI)
SQ11
SQ12
SQ13
SQ14
SQ15
SQ16
SQ17
SQ18
SQ19
SQ20
SQ21
SQ22
SQ23
SQ24
SQ25
TSCKH
TSCKL
TSCKR
TSCKF
TCSS (TCES)
TCSH (TCEH)
TCHS
TCHH
TCPH
TCHZ
TCLZ
TDS
TDH
TOH
TOV (TV)
Serial Clock High Time
Serial Clock Low Time
Serial Clock Rise Time
Serial Clock Fall Time
CS Active Setup Time
CS Active Hold Time
CS Not Active Setup Time
CS Not Active Hold Time
CS High Time
CS High to High-Z Data Out
SCK Low to Low-Z Data Out
Data In Setup Time
Data In Hold Time
Data Out Hold
Data Out Valid
DS60001361J-page 770
Min.
Typ.
Max.
Units
Conditions
—
—
—
6
6
0.25
0.25
5
5
3
3
6
—
0
3
4
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
80
66
100
—
—
—
—
—
—
—
—
—
6
—
—
—
—
6
MHz DMA Read mode, SDR mode
MHz DMA Read mode, DDR mode
MHz PIO Write mode, SDR mode
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
FIGURE 44-16:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (HOST MODE)
SCLx
IM31
IM34
IM30
IM33
Start Condition
Stop Condition
SDAx
Note: Refer to Figure 44-1 for load conditions.
FIGURE 44-17:
I2Cx BUS DATA TIMING CHARACTERISTICS (HOST MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM33
IM25
SDAx
In
IM45
IM40
IM40
SDAx
Out
Note: Refer to Figure 44-1 for load conditions.
TABLE 44-42: I2Cx BUS DATA TIMING REQUIREMENTS (HOST MODE)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
IM10
IM11
IM20
Min.(1)
Max.
Units
Conditions
TLO:SCL Clock Low Time 100 kHz mode
TPBCLK2 * (BRG + 2)
—
s
—
400 kHz mode
TPBCLK2 * (BRG + 2)
—
s
—
1 MHz mode
(Note 2)
TPBCLK2 * (BRG + 2)
—
s
—
Clock High Time 100 kHz mode
TPBCLK2 * (BRG + 2)
—
s
—
400 kHz mode
TPBCLK2 * (BRG + 2)
—
s
—
1 MHz mode
(Note 2)
TPBCLK2 * (BRG + 2)
—
s
—
—
300
ns
20 + 0.1 CB
300
ns
—
100
ns
THI:SCL
TF:SCL
Characteristics
SDAx and SCLx 100 kHz mode
Fall Time
400 kHz mode
1 MHz mode
(Note 2)
Note 1:
2:
3:
CB is specified to be
from 10 to 400 pF
BRG is the value of the I2C Baud Rate Generator.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
The typical value for this parameter is 104 ns.
2015-2021 Microchip Technology Inc.
DS60001361J-page 771
PIC32MZ Graphics (DA) Family
TABLE 44-42: I2Cx BUS DATA TIMING REQUIREMENTS (HOST MODE) (CONTINUED)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
IM21
IM25
IM26
IM30
IM31
IM33
IM34
TR:SCL
Characteristics
Min.(1)
Max.
Units
SDAx and SCLx 100 kHz mode
Rise Time
400 kHz mode
—
1000
ns
20 + 0.1 CB
300
ns
1 MHz mode
(Note 2)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode
(Note 2)
100
—
ns
100 kHz mode
0
—
s
400 kHz mode
0
0.9
s
1 MHz mode
(Note 2)
0
0.3
s
100 kHz mode
TPBCLK2 * (BRG + 2)
—
s
400 kHz mode
TPBCLK2 * (BRG + 2)
—
s
1 MHz mode
(Note 2)
TPBCLK2 * (BRG + 2)
—
s
100 kHz mode
TPBCLK2 * (BRG + 2)
—
s
400 kHz mode
TPBCLK2 * (BRG + 2)
—
s
1 MHz mode
(Note 2)
TPBCLK2 * (BRG + 2)
—
s
100 kHz mode
TPBCLK2 * (BRG + 2)
—
s
400 kHz mode
TPBCLK2 * (BRG + 2)
—
s
1 MHz mode
(Note 2)
TPBCLK2 * (BRG + 2)
—
s
100 kHz mode
TPBCLK2 * (BRG + 2)
—
ns
400 kHz mode
TPBCLK2 * (BRG + 2)
—
ns
1 MHz mode
(Note 2)
TPBCLK2 * (BRG + 2)
—
ns
100 kHz mode
—
3500
ns
—
400 kHz mode
—
1000
ns
—
1 MHz mode
(Note 2)
—
350
ns
—
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode
(Note 2)
0.5
—
s
The amount of time
the bus must be free
before a new
transmission can start
TSU:DAT Data Input
Setup Time
THD:DAT Data Input
Hold Time
TSU:STA Start Condition
Setup Time
THD:STA Start Condition
Hold Time
TSU:STO Stop Condition
Setup Time
THD:STO Stop Condition
Hold Time
IM40
IM45
TAA:SCL Output Valid
from Clock
TBF:SDA Bus Free Time
Conditions
CB is specified to be
from 10 to 400 pF
—
—
Only relevant for
Repeated Start
condition
After this period, the
first clock pulse is
generated
—
—
IM50
CB
Bus Capacitive Loading
—
—
pF
See parameter DO58
IM51
TPGD
Pulse Gobbler Delay
52
312
ns
See Note 3
Note 1:
2:
3:
BRG is the value of the I2C Baud Rate Generator.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
The typical value for this parameter is 104 ns.
DS60001361J-page 772
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
FIGURE 44-18:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (CLIENT MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 44-1 for load conditions.
FIGURE 44-19:
I2Cx BUS DATA TIMING CHARACTERISTICS (CLIENT MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS33
IS25
SDAx
In
IS45
IS40
IS40
SDAx
Out
Note: Refer to Figure 44-1 for load conditions.
TABLE 44-43: I2Cx BUS DATA TIMING REQUIREMENTS (CLIENT MODE)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
IS10
IS11
Note 1:
Symbol
TLO:SCL
THI:SCL
Characteristics
Clock Low Time
Clock High Time
Min.
Max.
Units
Conditions
100 kHz mode
4.7
—
s
PBCLK must operate at a
minimum of 800 kHz
400 kHz mode
1.3
—
s
PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode
(Note 1)
0.5
—
s
100 kHz mode
4.0
—
s
PBCLK must operate at a
minimum of 800 kHz
400 kHz mode
0.6
—
s
PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode
(Note 1)
0.5
—
s
—
—
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2015-2021 Microchip Technology Inc.
DS60001361J-page 773
PIC32MZ Graphics (DA) Family
TABLE 44-43: I2Cx BUS DATA TIMING REQUIREMENTS (CLIENT MODE) (CONTINUED)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature
Param.
No.
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
Note 1:
Symbol
TF:SCL
TR:SCL
TSU:DAT
THD:DAT
TSU:STA
THD:STA
TSU:STO
THD:STO
TAA:SCL
TBF:SDA
CB
Characteristics
SDAx and SCLx
Fall Time
Min.
Max.
Units
—
300
ns
400 kHz mode 20 + 0.1 CB
300
ns
1 MHz mode
(Note 1)
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode 20 + 0.1 CB
300
ns
1 MHz mode
(Note 1)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode
(Note 1)
100
—
ns
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
1 MHz mode
(Note 1)
0
0.3
s
100 kHz mode
4700
—
ns
400 kHz mode
600
—
ns
1 MHz mode
(Note 1)
250
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode
(Note 1)
250
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode
(Note 1)
600
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode
(Note 1)
250
—
ns
Output Valid from 100 kHz mode
Clock
400 kHz mode
0
3500
ns
0
1000
ns
1 MHz mode
(Note 1)
0
350
ns
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode
(Note 1)
0.5
—
s
—
—
pF
SDAx and SCLx
Rise Time
Data Input
Setup Time
Data Input
Hold Time
Start Condition
Setup Time
Start Condition
Hold Time
Stop Condition
Setup Time
Stop Condition
Hold Time
Bus Free Time
100 kHz mode
-40°C TA +85°C for Industrial
Bus Capacitive Loading
Conditions
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
—
—
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
—
—
—
The amount of time the bus
must be free before a new
transmission can start
See parameter DO58
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS60001361J-page 774
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
FIGURE 44-20:
CiTx Pin
(output)
CANx MODULE I/O TIMING CHARACTERISTICS
New Value
Old Value
CA10 CA11
CiRx Pin
(input)
CA20
TABLE 44-44: CANx MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
—
—
—
ns
See parameter DO32
See parameter DO31
CA10
TioF
Port Output Fall Time
CA11
TioR
Port Output Rise Time
—
—
—
ns
CA20
Tcwf
Pulse Width to Trigger
CAN Wake-up Filter
700
—
—
ns
Note 1:
2:
Conditions
—
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2015-2021 Microchip Technology Inc.
DS60001361J-page 775
PIC32MZ Graphics (DA) Family
TABLE 44-45: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param.
Symbol
No.
Device Supply
AD01 AVDD
AD02 AVSS
Reference Inputs
AD05 VREFH
AD06 VREFL
AD07 VREF
AD08
IREF
Characteristics
Module VDDIO Supply
Module VSS Supply
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min.
Typ.
Max.
Greater of
VDDIO – 0.3
or 2.3
VSS
—
—
Lesser of
VDDIO +
0.3 or 3.6
VSS + 0.3
—
—
—
AVDD
VREFH – 1.8
AVDD
V
V
V
(Note 1)
(Note 1)
(Note 2)
102
—
µA
ADC is operating or is in
Stand-by.
VREFH
VREFL
V
V
—
—
VREFH
V
—
Reference Voltage High VREFL + 1.8
Reference Voltage Low
AVSS
Absolute Reference
1.8
Voltage (VREFH – VREFL)
Current Drain
—
Analog Input
AD12 VINH-VINL Full-Scale Input Span
VREFL
—
Absolute VINL Input
AVSS
—
AD13 VINL
Voltage
AD14 VINH
Absolute VINH Input
AVSS
—
Voltage
ADC Accuracy – Measurements with External VREF+/VREFAD20c Nr
Resolution
6
—
12
AD21c INL
Integral Nonlinearity
—
±3
—
AD22c DNL
Differential Nonlinearity
—
±1
—
AD23c GERR
Gain Error
—
±8
—
AD24c EOFF
Offset Error
—
±2
—
Units
Conditions
V
—
V
—
bits Selectable 6, 8, 10, 12
Resolution Ranges
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
LSb VINL = AVSS = 0V,
AVDD = 3.3V
— Guaranteed (Note 2)
AD25c
—
Monotonicity
—
—
—
Dynamic Performance
AD31b SINAD
Signal to Noise and
—
65
—
dB Single-ended (Notes 2,3)
Distortion
AD34b ENOB
Effective Number of bits
—
10.5
—
bits (Notes 2,3)
Note 1: These parameters are not characterized or tested in manufacturing.
2: These parameters are characterized, but not tested in manufacturing.
3: Characterized with a 1 kHz sine wave.
4: The ADC module is functional at VBORIOMIN < VDDIO < VDDIOMIN, but with degraded performance. Unless
otherwise stated, module functionality is guaranteed, but not characterized.
DS60001361J-page 776
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-46: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS
AC CHARACTERISTICS(2)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics
Min.
ADC Clock Period
20
—
Sample Rate for
ADC0-ADC4
(Class 1 Inputs)
—
—
—
—
Sample Rate for
ADC7
(Class 2 and Class
3 Inputs)
—
—
—
—
Typ.(1) Max.
Units
Conditions
6250
ns
—
—
—
—
—
3.125
3.57
4.16
5
Msps
Msps
Msps
Msps
12-bit resolution Source Impedance 200
10-bit resolution Source Impedance 200
8-bit resolution Source Impedance 200
6-bit resolution Source Impedance 200
—
—
—
—
2.94
3.33
3.84
4.55
Msps
Msps
Msps
Msps
12-bit resolution Source Impedance 200
10-bit resolution Source Impedance 200
8-bit resolution Source Impedance 200
6-bit resolution Source Impedance 200
TAD
Source Impedance 200, Max ADC clock
Source Impedance 500, Max ADC clock
Source Impedance 1 K, Max ADC clock
Source Impedance 5 K, Max ADC clock
Clock Parameters
AD50
TAD
Throughput Rate
AD51
FTP
Timing Parameters
AD60
TSAMP
Sample Time for
ADC0-ADC4
(Class 1 Inputs)
3
4
5
13
Sample Time for
ADC7
(Class 2 and Class
3 Inputs)
4
5
6
14
Sample Time for
See
ADC7
Table
(Class 2 and Class
44-47
3 Inputs)
AD62
AD65
Note 1:
2:
TCONV
TWAKE
—
—
—
—
TAD
Source Impedance 200, Max ADC clock
Source Impedance 500, Max ADC clock
Source Impedance 1 K, Max ADC clock
Source Impedance 5 K, Max ADC clock
—
—
TAD
CVDEN (ADCCON1) = 1
12-bit resolution
10-bit resolution
8-bit resolution
6-bit resolution
Conversion Time
(after sample time is
complete)
—
—
—
—
—
—
—
—
13
11
9
7
TAD
Wake-up time from
Low-Power Mode
—
500
—
TAD
—
20
—
µs
Lesser of 500 TAD or 20 µs.
These parameters are characterized, but not tested in manufacturing.
The ADC module is functional at VBORIOMIN < VDDIO < VDDIOMIN, but with degraded performance.
Unless otherwise stated, module functionality is guaranteed, but not characterized.
2015-2021 Microchip Technology Inc.
DS60001361J-page 777
PIC32MZ Graphics (DA) Family
TABLE 44-47: ADC SAMPLE TIMES WITH CVD ENABLED
AC CHARACTERISTICS(2)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Min.
AD60a TSAMP
Characteristics
Sample Time for
ADC7 (Class 2 and
Class 3 Inputs) with
the CVDEN bit
(ADCCON1) = 1
8
9
11
12
14
16
17
10
12
14
16
18
19
21
13
16
18
21
23
26
28
41
48
56
63
70
78
85
Note 1:
2:
Typ.(1) Max.
—
—
—
—
—
—
—
—
Units
Conditions
TAD
Source Impedance 200
CVDCPL (ADCCON2) = 001
CVDCPL (ADCCON2) = 010
CVDCPL (ADCCON2) = 011
CVDCPL (ADCCON2) = 100
CVDCPL (ADCCON2) = 101
CVDCPL (ADCCON2) = 110
CVDCPL (ADCCON2) = 111
TAD
Source Impedance 500
CVDCPL (ADCCON2) = 001
CVDCPL (ADCCON2) = 010
CVDCPL (ADCCON2) = 011
CVDCPL (ADCCON2) = 100
CVDCPL (ADCCON2) = 101
CVDCPL (ADCCON2) = 110
CVDCPL (ADCCON2) = 111
TAD
Source Impedance 1 K
CVDCPL (ADCCON2) = 001
CVDCPL (ADCCON2) = 010
CVDCPL (ADCCON2) = 011
CVDCPL (ADCCON2) = 100
CVDCPL (ADCCON2) = 101
CVDCPL (ADCCON2) = 110
CVDCPL (ADCCON2) = 111
TAD
Source Impedance 5 K
CVDCPL (ADCCON2) = 001
CVDCPL (ADCCON2) = 010
CVDCPL (ADCCON2) = 011
CVDCPL (ADCCON2) = 100
CVDCPL (ADCCON2) = 101
CVDCPL (ADCCON2) = 110
CVDCPL (ADCCON2) = 111
These parameters are characterized, but not tested in manufacturing.
The ADC module is functional at VBORIOMIN < VDDIO < VDDIOMIN, but with degraded performance. Unless
otherwise stated, module functionality is guaranteed, but not characterized.
DS60001361J-page 778
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-48: TEMPERATURE SENSOR SPECIFICATIONS
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min.
Typ.
Max.
Units
Conditions
TS10
VTS
Rate of Change
—
5
—
mV/ºC
—
TS11
TR
Resolution
-2
—
+2
ºC
—
TS12
IVTEMP
Voltage Range
0.5
—
1.5
V
TS13
TMIN
Minimum Temperature
—
-40
—
ºC
IVTEMP = 0.5V
TS14
TMAX
Maximum Temperature
—
160
—
ºC
IVTEMP = 1.5V
Note 1:
—
The temperature sensor is functional at VBORIOMIN < VDDIO < VDDIOMIN, but with degraded performance.
Unless otherwise stated, module functionality is tested, but not characterized.
2015-2021 Microchip Technology Inc.
DS60001361J-page 779
PIC32MZ Graphics (DA) Family
FIGURE 44-21:
PSP TIMING
PMCSx
PS5
PMRD
PS6
PMWR
PS4
PS7
PMD
PS1
PS3
PS2
TABLE 44-49: PSP REQUIREMENTS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Para
Symbol
m.No.
Characteristics(1)
Min.
Typ.
Max.
Units
Conditions
PS1
TdtV2wrH Data In Valid before PMWR or PMCSx
Inactive (setup time)
20
—
—
ns
—
PS2
TwrH2dtI PMWR or PMCSx Inactive to Data-in
Invalid (hold time)
40
—
—
ns
—
PS3
TrdL2dtV PMRD and PMCSx Active to Data-out
Valid
—
—
60
ns
—
PS4
TrdH2dtI
PMRD Activeor PMCSx Inactive to
Data-out Invalid
0
—
10
ns
—
PS5
Tcs
PMCSx Active Time
TPBCLK2 + 40
—
—
ns
—
PS6
TWR
PMWR Active Time
TPBCLK2 + 25
—
—
ns
—
PS7
TRD
PMRD Active Time
TPBCLK2 + 25
—
—
ns
—
Note 1:
These parameters are characterized, but not tested in manufacturing.
DS60001361J-page 780
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
FIGURE 44-22:
PMP READ TIMING DIAGRAM
TPBCLK2
TPBCLK2
TPBCLK2
TPBCLK2
TPBCLK2
TPBCLK2
TPBCLK2
TPBCLK2
PBCLK2
PM4
Address
PMA
PM6
PMD
Data
Data
Address
Address
PM2
PM7
PM3
PMRD
PM5
PMWR
PM1
PMALL/PMALH
PMCSx
TABLE 44-50: PMP READ TIMING REQUIREMENTS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typ.
Max.
Units
Conditions
PM1
TLAT
PMALL/PMALH Pulse Width
—
1 TPBCLK2
—
—
—
PM2
TADSU
Address Out Valid to PMALL/
PMALH Invalid (address setup
time)
—
2 TPBCLK2
—
—
—
PM3
TADHOLD PMALL/PMALH Invalid to
Address Out Invalid (address
hold time)
—
1 TPBCLK2
—
—
—
PM4
TAHOLD
PMRD Inactive to Address Out
Invalid
(address hold time)
5
—
—
ns
—
PM5
TRD
PMRD Pulse Width
—
1 TPBCLK2
—
—
—
PM6
TDSU
PMRD or PMENB Active to Data
In Valid (data setup time)
15
—
—
ns
—
PM7
TDHOLD
PMRD or PMENB Inactive to
Data In Invalid (data hold time)
5
—
—
ns
—
Note 1:
These parameters are characterized, but not tested in manufacturing.
2015-2021 Microchip Technology Inc.
DS60001361J-page 781
PIC32MZ Graphics (DA) Family
FIGURE 44-23:
PMP WRITE TIMING DIAGRAM
TPBCLK2
TPBCLK2
TPBCLK2
TPBCLK2
TPBCLK2
TPBCLK2
TPBCLK2
TPBCLK2
PBCLK2
Address
PMA
PM2 + PM3
Address
PMD
Data
PM12
PM13
PMRD
PM11
PMWR
PM1
PMALL/PMALH
PMCSx
TABLE 44-51: PMP WRITE TIMING REQUIREMENTS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typ.
Max.
Units
Conditions
PM11
TWR
PMWR Pulse Width
—
1 TPBCLK2
—
—
—
PM12
TDVSU
Data Out Valid before PMWR or
PMENB goes Inactive (data setup
time)
—
2 TPBCLK2
—
—
—
PM13
TDVHOLD PMWR or PMEMB Invalid to Data
Out Invalid (data hold time)
—
1 TPBCLK2
—
—
—
Note 1:
These parameters are characterized, but not tested in manufacturing.
DS60001361J-page 782
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-52: USB OTG ELECTRICAL SPECIFICATIONS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
USB313 VUSB3V3 USB Voltage
Min.
Typ.
Max.
Units
Conditions
3.0
—
3.6
V
Voltage on VUSB3V3
must be in this range for
proper USB operation
Low-Speed and Full-Speed Modes
USB315 VILUSB
Input Low Voltage for USB Buffer
—
—
0.8
V
—
USB316 VIHUSB
Input High Voltage for USB Buffer
2.0
—
—
V
—
USB318 VDIFS
Differential Input Sensitivity
0.2
—
—
V
The difference between
D+ and D- must exceed
this value while VCM is
met
USB319 VCM
Differential Common Mode Range
0.8
—
2.5
V
—
USB321 VOL
Voltage Output Low
0.0
—
0.3
V
1.425 k load
connected to VUSB3V3
USB322 VOH
Voltage Output High
2.8
—
3.6
V
14.25 k load
connected to ground
USB323 VHSDI
Differential input signal level
150
—
—
mV
USB324 VHSSQ
SQ detection threshold
100
—
150
mV
—
USB325 VHSCM
Common mode voltage range
-50
—
500
mV
—
USB326 VHSOH
Data signaling high
360
—
440
mV
—
USB327 VHSOL
Data signaling low
-10
—
10
mV
—
USB328 VCHIRPJ
Chirp J level
700
—
1100
mV
—
USB329 VCHIRPK Chirp K level
-900
—
-500
mV
—
—
45
—
—
Hi-Speed Mode
USB330 ZHSDRV
Note 1:
Driver output resistance
—
These parameters are characterized, but not tested in manufacturing.
2015-2021 Microchip Technology Inc.
DS60001361J-page 783
PIC32MZ Graphics (DA) Family
TABLE 44-53: ETHERNET MODULE SPECIFICATIONS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Characteristic
MIIM Timing Requirements
ET1
MDC Duty Cycle
ET2
MDC Period
ET3
MDIO Output Setup and Hold
ET4
MDIO Input Setup and Hold
MII Timing Requirements
ET5
TX Clock Frequency
ET6
TX Clock Duty Cycle
ET7
ETXDx, ETEN, ETXERR Output Delay
ET8
RX Clock Frequency
ET9
RX Clock Duty Cycle
ET10
ERXDx, ERXDV, ERXERR Setup and Hold
RMII Timing Requirements
ET11
Reference Clock Frequency
ET12
Reference Clock Duty Cycle
ET13
ETXDx, ETEN, Output Delay
ET14
ERXDx, ERXDV, ERXERR Setup and Hold
FIGURE 44-24:
Min.
Typ.
Max.
Units
Conditions
40
400
10
0
—
—
—
—
60
—
10
300
%
ns
ns
ns
—
—
See Figure 44-24
See Figure 44-25
—
35
0
—
35
10
25
—
—
25
—
—
—
65
25
—
65
30
MHz
%
ns
MHz
%
ns
—
—
See Figure 44-26
—
—
See Figure 44-27
—
35
2
2
50
—
—
—
—
65
16
16
MHz
%
ns
ns
—
—
—
—
MDIO SOURCED BY THE PIC32 DEVICE
VIHMIN
MDC
VILMAX
VIHMIN
MDIO
VILMAX
ET3 (Hold)
(Setup) ET3
FIGURE 44-25:
MDIO SOURCED BY THE PHY
VIHMIN
MDC
VILMAX
VIHMIN
MDIO
VILMAX
ET4
DS60001361J-page 784
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
FIGURE 44-26:
TRANSMIT SIGNAL TIMING RELATIONSHIPS AT THE MII
VIHMIN
VILMAX
TX Clock
VIHMIN
ETXD,
ETEN,
ETXERR
FIGURE 44-27:
VILMAX
ET7
RECEIVE SIGNAL TIMING RELATIONSHIPS AT THE MII
VIHMIN
RX Clock
VILMAX
VIHMIN
ERXD,
ERXDV,
ERXERR
VILMAX
(Setup) ET10
ET10 (Hold)
2015-2021 Microchip Technology Inc.
DS60001361J-page 785
PIC32MZ Graphics (DA) Family
FIGURE 44-28:
EBI PAGE READ TIMING
tEBI-RC
tEBI-PRC
tEBI-PRC
tEBI-PRC
SYSCLK
tEBICO
tEBICO
ADDRESS
EBIA
tEBICO
tEBICO
00
EBIA
tEBICO
01
tEBICO
10
tEBICO
11
tEBICO
tEBICO
tEBICO
tEBICO
EBICSx
00
EBIBSx
tEBICO
tEBICO
EBIOE
tEBIDH
tEBIDS
EBID
FIGURE 44-29:
tEBIDH
tEBIDS
READ DATA
tEBIDH
tEBIDS
READ DATA
tEBIDH
tEBIDS
READ DATA
READ DATA
EBI WRITE TIMING
tEBI-AS
tEBI-WP
tEBI-WR
SYSCLK
tEBICO
tEBICO
ADDRESS
EBIA
tEBICO
tEBICO
tEBICO
tEBICO
EBICSx
BYTE SELECTS
EBIBSx
EBIOE
tEBICO
tEBICO
EBIWE
tEBIDO
EBID
DS60001361J-page 786
tEBIDO
WRITE DATA
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-54: EBI TIMING REQUIREMENTS(1)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Min.
Typ.
Max.
Units
Conditions
5
—
—
ns
—
30
—
—
ns
—
EB10
TEBICLK Internal EBI Clock Period
(SYSCLK)
EB11
TEBIRC
EB12
TEBIPRC EBI Page Read Cycle Time
(TPRC)
30
—
—
ns
—
EB13
TEBIAS
15
—
—
ns
—
EB14
TEBIWP EBI Write Pulse Width
(TWP)
25
—
—
ns
—
EB15
TEBIWR EBI Write Recovery Time
(TWR)
15
—
—
ns
—
EB16
TEBICO
EBI Output Control Signal Delay
4
—
13
ns
See Note 2
EB17
TEBIDO
EBI Output Data Signal Delay
4
—
13
ns
See Note 2
EB18
TEBIDS
EBI Input Data Setup
10
—
—
ns
See Note 2
EB19
TEBIDH
EBI Input Data Hold
3
—
—
ns
See Note 2,3
Note 1:
2:
3:
EBI Read Cycle Time
(TRC)
EBI Write Address Setup (TAS)
EBI Timings Requirements data are from simulation.
Maximum pin capacitance = 10 pF.
Hold time from EBI Address change is 0 ns.
TABLE 44-55: GLCD CONTROLLER TIMING SPECIFICATIONS
AC CHARACTERISTICS
Param.
Symbol
No.
GD20
tGCLK
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Characteristic
Min.
Typ.
Max.
Units
Conditions
Pixel Clock Frequency on
GLCD pin
—
—
50
MHz
—
2015-2021 Microchip Technology Inc.
DS60001361J-page 787
PIC32MZ Graphics (DA) Family
TABLE 44-56: INTERNAL DDR2 SDRAM TIMING SPECIFICATIONS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic(1)
DDR10
tCK
Clock Frequency
—
DDR11
tDUTY
Duty Cycle
48
DDR12
tRCD
Active to Read/Write Command
Delay Time
20
DDR13
tRP
Precharge to Active Command
Period
DDR14
tRC
DDR15
DDR16
DDR17
Max.
Units
5
—
ns
—
50
52
%
—
—
—
ns
—
20
—
—
ns
—
Active to Ref/Active Command
Period
65
—
—
ns
—
tRAS
Active to Precharge Command
Period
40
70000
—
ns
Note 1
tRFC
Auto Refresh to Active/Auto Refresh
Command Period
75
—
—
ns
Note 2
—
—
7.8
µs
-40°C TJ
85°C
Note 2
—
—
3.9
µs
85°C TJ
95°C
Note 2
—
—
1.95
µs
95°C TJ
125°C
Note 2
tREFI
Average Periodic Refresh Interval
Min.
Typ.
Conditions
DDR18
tCKE
DDRCKE Minimum High and Low
Pulse Width
6
—
—
ntCK
—
DDR19
tRRD
Active to active command period for
1 KB page size
10
—
—
ns
Note 3
DDR20
tFAW
Four Activate Window for 1 KB
Page Size
35
—
—
ns
—
DDR21
tWR
Write Recovery Time
15
—
—
ns
—
DDR22
tWTR
Internal Write to Read Command
Delay
10
—
—
ns
Note 4
DDR23
tRTP
Internal Read To Precharge
Command Delay
10
—
—
ns
Note 1
DDR24
tXSRD
Exit Self Refresh to a Read
Command
200
—
—
ntCK
—
Note 1:
2:
3:
4:
5:
Note:
This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP
and tRAS(min) have been satisfied.
If refresh timing is violated, data corruption may occur and the data must be rewritten with valid data
before a valid READ can be executed.
A minimum of two clocks (2 * ntCK) is required regardless of operating frequency.
tWTR is at least two clocks (2 * ntCK) independent of operation frequency.
When DRAM is operated at 85°C < Tj ≤ 125°C the extended Self Refresh rate must be enabled by setting
bit A7 to “1” in extended mode register (2) EMR(2) before the Self Refresh mode can be entered.
For detailed information about the EMR(2) register please check the DDR2 SDRAM Specification
JESD79-2F.
DS60001361J-page 788
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE 44-56: INTERNAL DDR2 SDRAM TIMING SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
DDR25
tXP
Exit Precharge Power Down to Any
Command
2
—
—
ntCK
—
DDR26
tMRD
Mode Register Set Command Cycle
Time
2
—
—
ntCK
—
DDR27
RL
Read Latency
CL
—
—
ntCK
—
DDR28
CL
CAS Latency
3
—
4
ntCK
—
DDR29
WL
Write Latency
RL – 1
—
—
ntCK
—
8
—
—
ntCK
—
DDR30 BL
Note 1:
2:
3:
4:
5:
Note:
Burst Length
This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP
and tRAS(min) have been satisfied.
If refresh timing is violated, data corruption may occur and the data must be rewritten with valid data
before a valid READ can be executed.
A minimum of two clocks (2 * ntCK) is required regardless of operating frequency.
tWTR is at least two clocks (2 * ntCK) independent of operation frequency.
When DRAM is operated at 85°C < Tj ≤ 125°C the extended Self Refresh rate must be enabled by setting
bit A7 to “1” in extended mode register (2) EMR(2) before the Self Refresh mode can be entered.
For detailed information about the EMR(2) register please check the DDR2 SDRAM Specification
JESD79-2F.
TABLE 44-57: SD HOST CONTROLLER DEFAULT MODE TIMING SPECIFICATIONS
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min.
Typ.
Max.
Units
Conditions
SD20
tSDCK
Clock Frequency
—
—
25
MHz
—
SD21
tDUTY
Duty Cycle
—
50
—
%
—
SD22
tHIGH
Clock High Time
10
—
—
ns
—
SD23
tLOW
Clock Low Time
10
—
—
ns
—
SD24
tRISE
Clock Rise Time
—
10
—
ns
—
SD25
tFALL
Clock Fall Time
—
10
—
ns
—
SD26
tSETUP Input Setup Time
5
—
—
ns
—
SD27
tHOLD
5
—
—
ns
—
Input Hold Time
TABLE 44-58: SD HOST CONTROLLER HIGH-SPEED MODE TIMING SPECIFICATIONS
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min.
Typ.
Max.
Units
Conditions
SD30
tSDCK
Clock Frequency
—
—
50
MHz
—
SD31
tDUTY
Duty Cycle
—
50
—
%
—
2015-2021 Microchip Technology Inc.
DS60001361J-page 789
PIC32MZ Graphics (DA) Family
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min.
Typ.
Max.
Units
Conditions
7
—
—
ns
—
SD32
tHIGH
Clock High Time
SD33
tLOW
Clock Low Time
7
—
—
ns
—
SD34
tRISE
Clock Rise Time
—
3
—
ns
—
SD35
tFALL
Clock Fall Time
—
3
—
ns
—
SD36
tSETUP Input Setup Time
6
—
—
ns
—
SD37
tHOLD
2
—
—
ns
—
Input Hold Time
DS60001361J-page 790
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
FIGURE 44-30:
EJTAG TIMING CHARACTERISTICS
TTCKeye
TTCKhigh
TTCKlow
Trf
TCK
Trf
TMS
TDI
TTsetup TThold
Trf
Trf
TDO
TTRST*low
TTDOout
TTDOzstate
TRST*
Defined
Trf
Undefined
TABLE 44-59: EJTAG TIMING REQUIREMENTS
Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Description(1)
Min.
Max.
Units
Conditions
EJ1
TTCKCYC
TCK Cycle Time
25
—
ns
—
EJ2
TTCKHIGH
TCK High Time
10
—
ns
—
EJ3
TTCKLOW
TCK Low Time
10
—
ns
—
EJ4
TTSETUP
TAP Signals Setup Time Before
Rising TCK
5
—
ns
—
EJ5
TTHOLD
TAP Signals Hold Time After
Rising TCK
3
—
ns
—
EJ6
TTDOOUT
TDO Output Delay Time from
Falling TCK
—
5
ns
—
EJ7
TTDOZSTATE TDO 3-State Delay Time from
Falling TCK
—
5
ns
—
EJ8
TTRSTLOW
TRST Low Time
25
—
ns
—
EJ9
TRF
TAP Signals Rise/Fall Time, All
Input and Output
—
—
ns
—
Note 1:
These parameters are characterized, but not tested in manufacturing.
2015-2021 Microchip Technology Inc.
DS60001361J-page 791
PIC32MZ Graphics (DA) Family
DS60001361J-page 792
2015-2021 Microchip Technology Inc.
AC AND DC CHARACTERISTICS GRAPHS
Note:
The graphs provided are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested
or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FIGURE 45-1:
VOH – 4x DRIVER PINS
FIGURE 45-3:
VOH – 8x DRIVER PINS
VOH(V)
VOH(V)
Ͳ0.050
Ͳ0.090
Ͳ0.045
Ͳ0.080
Ͳ0.040
Ͳ0.070
Ͳ0.035
Ͳ0.060
Ͳ0.030
IOH(A)
IOH(A)
2015-2021 Microchip Technology Inc.
45.0
Ͳ0.025
Ͳ0.050
Ͳ0.040
Ͳ0.030
Ͳ0.015
Ͳ0.020
AbsoluteMaximum
Ͳ0.010
AbsoluteMaximum
Ͳ0.010
Ͳ0.005
0.000
0.000
0.00
0.50
FIGURE 45-2:
1.00
1.50
2.00
2.50
3.00
0.00
3.50
0.50
FIGURE 45-4:
VOL – 4x DRIVER PINS
1.00
2.00
2.50
3.00
3.50
VOL – 8x DRIVER PINS
VOL(V)
VOL(V)
0.050
0.090
0.045
0.080
0.040
0.070
0.035
0.060
0.030
IOL(A)
DS60001361J-page 793
IOL(A)
1.50
0.025
0 020
0.020
0.015
0.050
0.040
0.030
AbsoluteMaximum
AbsoluteMaximum
0.020
0.010
0.010
0.005
0.000
0.000
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
PIC32MZ Graphics (DA) Family
Ͳ0.020
0 020
VOH – 12x DRIVER PINS
FIGURE 45-7:
VOH(V)
TYPICAL TEMPERATURE SENSOR VOLTAGE
1.550
Ͳ0.140
1.350
Voltage (V)
Ͳ0.120
IOH(A)
Ͳ0.100
Ͳ0.080
Ͳ0.060
1.150
0.950
0 750
0.750
Ͳ0.040
0.550
AbsoluteMaximum
Ͳ0.020
0.350
0.000
0.00
0.50
FIGURE 45-6:
1.00
1.50
2.00
2.50
3.00
3.50
3.00
3.50
VOL – 12x DRIVER PINS
VOL(V)
0.140
0.120
IOL(A)
2015-2021 Microchip Technology Inc.
0.100
0.080
0.060
0.040
AbsoluteMaximum
0.020
0.000
0.00
0.50
1.00
1.50
2.00
2.50
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140
Temperature (Celsius)
PIC32MZ Graphics (DA) Family
DS60001361J-page 794
FIGURE 45-5:
PIC32MZ Graphics (DA) Family
46.0
PACKAGING INFORMATION
46.1
Package Marking Information
All devices are marked with Microchip logo and ordering code.
Additional marking is as shown below:
*
YYWWNNN
Where,
•
•
•
•
YY : Manufacturing year (last 2 digits of calender year)
WW : Manufacturing week (week of January 1 is week 01)
NNN: Alphanumeric traceability code
*
: Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb free. The Pb-free JEDEC designator,
package.
Note:
, can be found on this package or outer packaging of this
If the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus
limiting the number of available characters for customer-specific information.
2015-2021 Microchip Technology Inc.
DS60001361J-page 795
PIC32MZ Graphics (DA) Family
46.2
Package Details
The following sections give the technical details of the packages.
169-Ball Low Profile Fine Pitch Ball Grid Array (HF) - 11x11x1.4 mm Body [LFBGA]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
169X
0.15 C
D
0.10 C
A
NOTE 1
(A2)
B
E
2X
0.10 C
2X
0.10 C
NOTE 1
A1 CORNER
A1
(DATUM B)
(A3)
(DATUM A)
A
TOP VIEW
C
A1 CORNER
SEATING
PLANE
D1
NOTE 1
N
SIDE VIEW
e
E1
BOTTOM VIEW
166X Øb
0.10
0.05
C A B
C
Microchip Technology Drawing C04-365B Sheet 1 of 2
DS60001361J-page 796
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
169-Ball Low Profile Fine Pitch Ball Grid Array (HF) - 11x11x1.4 mm Body [LFBGA]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
N
Number of Terminals (Balls)
e
Pitch
A
Overall Height
Terminal (Ball) Height
A1
(A2)
Mold Cap Thickness
(A3)
Substrate Thickness
Overall Length
D
E
Overall Width
Overall Ball Pitch
D1
Overall Ball Pitch
E1
b
Ball Diameter
MIN
1.17
0.25
0.40
MILLIMETERS
NOM
169
0.80 BSC
1.285
0.325
0.70 REF
0.26 REF
11.00 BSC
11.00 BSC
9.60
9.60
0.45
MAX
1.40
0.40
0.50
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-365B Sheet 2 of 2
2015-2021 Microchip Technology Inc.
DS60001361J-page 797
PIC32MZ Graphics (DA) Family
DS60001361J-page 798
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
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2015-2021 Microchip Technology Inc.
DS60001361J-page 799
PIC32MZ Graphics (DA) Family
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DS60001361J-page 800
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
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2015-2021 Microchip Technology Inc.
DS60001361J-page 801
PIC32MZ Graphics (DA) Family
176-Lead Low Profile Quad Flat Pack (2J) - 20x20x1.4 mm Body [LQFP]
With 7x7 mm Exposed Pad
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
SEATING PLANE
C 176X
D1
D1
2
0.08 C
B
N
NOTE 1
12
SEE DETAIL B
E1
2
E2
E
E1
(DATUM B)
(DATUM A)
(L1)
4X
0.20 C
4X
Ĭ1
0.20 C
Ĭ
D2
TOP VIEW
SIDE VIEW
D3
e
2
X
X = A OR B
E3
e
DETAIL A
SEE DETAIL A
1 2
NOTE 1
N
176X b
0.07
C A B
BOTTOM VIEW
Microchip Technology Drawing C04-367A Sheet 1 of 2
DS60001361J-page 802
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
176-Lead Low Profile Quad Flat Pack (2J) - 20x20x1.4 mm Body [LQFP]
With 7x7 mm Exposed Pad
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Ĭ2
R1
R2
A A2
c
SEATING
PLANE
Ĭ3
C
A1
L
Units
Dimension Limits
N
Number of Leads
e
Pitch
Overall Height
A
Standoff
A1
Molded Package Height
A2
D
Overall Length
Molded Package Length
D1
Overall Lead Pitch
D2
D3
Exposed Pad Length
Overall Width
E
Molded Package Width
E1
Overall Lead Pitch
E2
E3
Exposed Pad Width
MILLIMETERS
NOM
MAX
176
0.40 BSC
1.60
0.05
0.15
1.35
1.40
1.45
22.00 BSC
20.00 BSC
17.20 BSC
6.90
7.10
7.00
22.00 BSC
20.00 BSC
17.20 BSC
6.90
7.00
7.10
MIN
Units
Dimension Limits
b
Lead Width
c
Lead Thickness
L
Lead Length
(L1)
Footprint
Bend Radius
R1
Bend Radius
R2
Foot Angle
Ĭ
Lead Angle
Ĭ1
Mold Draft Angle
Ĭ2
Mold Draft Angle
Ĭ3
MILLIMETERS
NOM
MAX
0.23
0.16
0.20
0.75
0.60
1.00 REF
0.08
0.08
0.20
0°
3.5°
7°
0°
11°
12°
13°
11°
12°
13°
MIN
0.13
0.09
0.45
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable Protrusion is 0.25mm per side.
D1 and E1 are maximum body size dimensions including mold mismatch.
3. Dimension b does not include dambar protrusion. Allowable dam bar protrusion shall not cause
the lead width to exceed the maximum b dimension by more than 0.08mm
Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion
and adjacent lead is 0.07mm for 0.40mm pitch packages.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-367A Sheet 2 of 2
2015-2021 Microchip Technology Inc.
DS60001361J-page 803
PIC32MZ Graphics (DA) Family
DS60001361J-page 804
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
2015-2021 Microchip Technology Inc.
DS60001361J-page 805
PIC32MZ Graphics (DA) Family
288 Ball Low Profile Fine Pitch Ball Grid Array (4J) - 15x15x1.4 mm Body [LFBGA]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Terminals (Balls)
N
e
Pitch
A
Overall Height
Terminal (Ball) Height
A1
(A2)
Mold Cap Height
(A3)
Substrate Thickness
Overall Length
D
Overall Ball Pitch
D1
Overall Width
E
Overall Ball Pitch
E1
b
Ball Diameter
MIN
0.30
0.40
MILLIMETERS
NOM
288
0.80 BSC
0.35
0.70 REF
0.26 REF
15.00 BSC
13.60 BSC
15.00 BSC
13.60 BSC
0.45
MAX
1.40
0.40
0.50
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-366B Sheet 2 of 2
DS60001361J-page 806
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
2015-2021 Microchip Technology Inc.
DS60001361J-page 807
PIC32MZ Graphics (DA) Family
NOTES:
DS60001361J-page 808
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
APPENDIX A:
REVISION HISTORY
Revision A (July 2015)
This is the initial released version of the document.
Revision B (November 2015)
In this revision, the document status has been updated
from Advance Information to Preliminary.
This revision includes the following major changes,
which are referenced by their respective chapter in
Table TABLE A-1:Major Section Updates.
In addition, minor updates to text and formatting were
incorporated throughout the document.
TABLE A-1:
MAJOR SECTION UPDATES
Section Name
Update Description
32-bit Graphics Applications
The pin names for 169-pin devices were updated (see Table 5).
MCUs (up to 2 MB Live Update The pin names for 288-pin devices were updated (see Table 7).
Flash, 640 KB SRAM, and 32
MB DDR2 SDRAM) with XLP
Technology
4.0 “Memory Organization”
The Boot Flash Sequence and Configuration Word Summary tables were updated
(see Table 4-3 and Table 4-4).
The BFxSEQ3/ABFxSEQ3: Boot Flash ‘x’ Sequence Word 0 Register was
updated (see Register 4-1).
6.0 “Resets”
The All Resets values were updated for the RCON register in the Resets Register
Map (see Table 6-1).
7.0 “CPU Exceptions and
Interrupt Controller”
The OFF199 register was added to the Interrupt Register Map (see Table 7-3).
8.0 “Oscillator Configuration” The All Resets values for the OSCON and PB6DIV registers were updated in the
Oscillator Register Map (see Table 8-2).
The PLLODIV bit values in the SPLLCON register were updated (see
Register 8-3).
10.0 “Direct Memory Access
(DMA) Controller”
The All Resets values were updated in the DMA Channel 0 through Channel 7
Register Map (see Table 10-3).
11.0 “Hi-Speed USB with OnThe-Go (OTG)”
The All Resets value for bits 15:0 of the USBOTG register was updated in the USB
Register Map 1 (see Table 11-1).
The value at POR was updated for bits 24 and 13 of the USBCRCON register (see
Register 11-30).
12.0 “I/O Ports”
The TRISC bits in the PORTC Register Map were updated (see Table 12-5).
The ANSH3 bit was added to the ANSELH register in the PORTH Register Map
(see Table 12-10).
The RPD15R register was removed from the Peripheral Pin Select Output Register
Map (see Table 12-14).
18.0 “Watchdog Timer (WDT)” The All Resets value for bits 15:0 of the WDTCON register in the Watchdog Timer
Register Map was updated (see Table 18-1).
21.0 “Serial Peripheral
Interface (SPI) and Inter-IC
Sound (I2S)”
The All Resets value for bits 15:0 of the SPI1STAT and SPI1CON2 registers in the
Watchdog Timer Register Map were updated (see Table 21-1).
22.0 “Serial Quad Interface
(SQI)”
The All Resets value for bits 15:0 of the SQI1XCON1 register in the Serial
Quadrature Interface (SQI) Register Map was updated (see Table 22-1).
2015-2021 Microchip Technology Inc.
DS60001361J-page 809
PIC32MZ Graphics (DA) Family
TABLE A-1:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
25.0 “Parallel Master Port
(PMP)”
The All Resets value for bits 15:0 of the PMSTAT register in the Parallel Master
Port Register Map was updated (see Table 25-1).
26.0 “External Bus Interface
(EBI)”
The All Resets values were updated in the EBI Register Map (see Table 26-2).
29.0 “12-bit High-Speed
Successive Approximation
Register (SAR) Analog-toDigital Converter (ADC)”
The All Resets values for the ADCCON1 and ADCxTIME registers were updated
and the Virtual Addresses for the ADCxCFG, ADCSYSCFGx, and ADCDATAx
registers were updated in the ADC Register Map (see Table 29-1).
34.0 “High/Low-Voltage Detect The chapter was renamed and the introduction was updated.
(HLVD)”
The HLVDCON register was updated (see Table 34-1 and Register 34-1).
High/Low-Voltage Detect (HLVD) Module Block Diagram was updated (see
Figure 34-1)
36.0 “Graphics LCD (GLCD)
Controller”
The Graphics LCD Controller Register Map was updated (see Table 36-1).
These registers were updated:
• Register 36-2: “GLCDCLKCON: Graphics LCD Controller Clock Control
Register”
• Register 36-4: “GLCDRES: Graphics LCD Controller Resolution Register”
• Register 36-5: “GLCDFPORCH: Graphics LCD Controller Front Porch
Register”
• Register 36-6: “GLCDBLANKING: Graphics LCD Controller Blanking
Register”
• Register 36-7: “GLCDBPORCH: Graphics LCD Controller Back Porch
Register”
• Register 36-8: “GLCDCURSOR: Graphics LCD Controller Cursor Register”
• Register 36-10: “GLCDLxstart: graphics lcd controller layer ‘x’ start
register (‘x’ = 0-2)”
• Register 36-11: “GLCDLxsize: graphics lcd controller layer ‘x’ size register
(‘x’ = 0-2)”
• Register 36-14: “GLCDLxres: graphics lcd controller layer ‘x’ resolution
register (‘x’ = 0-2)”
37.0 “2-D Graphics
Processing Unit (GPU)”
The introduction was updated.
39.0 “Secure Digital Host
Controller (SDHC)”
The SDHC block diagram was updated (see Figure 39-1).
The SDHC Register Map was updated (see Table 39-1).
The bit values for the CDSLVL bit in the SDHCSTAT1 register were updated (see
Register 39-6).
The SDHCCAP register was updated (see Register 39-13).
40.0 “Power-Saving Features” 40.2.3 “Deep Sleep Mode” was updated.
References to High-Voltage Detect were removed in the PMD Register Summary
(Table 40-2) and the PMD Bits and Locations (Table 40-3).
41.0 “Special Features”
DS60001361J-page 810
The CFGCON2 register was updated (see Table 41-3 and Register 41-12).
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE A-1:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
44.0 “Electrical
Characteristics”
Update Description
The following tables were updated:
•
•
•
•
•
•
•
•
•
•
Table 44-1: “Operating MIPS vs. Voltage”
Table 44-3: “Thermal Packaging Characteristics”
Table 44-4: “DC Temperature and Voltage Specifications”
Table 44-8: “DC Characteristics: Operating Current (Idd)”
Table 44-9: “DC Characteristics: Idle Current (Iidle)”
Table 44-10: “DC Characteristics: Power-Down Current (Ipd)”
Table 44-12: “DC Characteristics: I/O Pin Output Specifications”
Table 44-38: “SPIx Master Mode (CKE = 0) Timing Requirements”
Table 44-39: “SPIx Module Master Mode (CKE = 1) Timing Requirements”
Table 44-53: “USB OTG Electrical Specifications”
Revision C (October/November 2016)
All instances of VDD1V8 were changed to: VDDR1V8 and
VDD were changed to VDDIO throughout the data sheet.
All instances of V-Temp specifications were removed
throughout the data sheet.
This revision includes the following major changes,
which are referenced by their respective chapter in
Table TABLE A-2:Major Section Updates.
In addition, minor updates to text and formatting were
incorporated throughout the document.
TABLE A-2:
MAJOR SECTION UPDATES
Section Name
Update Description
32-bit Graphics Applications
The Operating Conditions were updated from 2.0V to 3.6V to 2.2V to 3.6V.
MCUs (up to 2 MB Live Update All Device Pin Tables were updated (see Table 5 through Table 7).
Flash, 640 KB SRAM, and 32
MB DDR2 SDRAM) with XLP
Technology
1.0 “Device Overview”
Note 1 was added to the Timer1 through Timer9 and RTCC Pinout I/O
Descriptions (see Table 1-7).
Note 2 and the pin numbers for the Power, Ground, and Voltage Reference Pinout
I/O Descriptions were updated (see Table 1-23).
2.0 “Guidelines for Getting
Started with 32-bit
Microcontrollers”
The Recommended Minimum Connection diagram was updated (see Figure 2-1).
3.0 “CPU”
The SB bit was updated in the Configuration Register; CP0 Register 16, Select 0
(see Register 3-1).
4.0 “Memory Organization”
4.3 “Timing Parameters” was updated.
6.0 “Resets”
Note 1 was added to the Resets Register Map (see Table 6-1).
2.9.1.3 “EMI/EMC/EFT (IEC 61000-4-4 and IEC 61000-4-2) Suppression
Considerations” was added.
8.0 “Oscillator Configuration” The DIVSPLLRDY bit was removed from the CLKSTAT register (see Table 8-2 and
Register 8-8).
Updated bit 5-0 center frequency values from -2% to -4% and +2% to +4% (see
Register 8-2).
2015-2021 Microchip Technology Inc.
DS60001361J-page 811
PIC32MZ Graphics (DA) Family
TABLE A-2:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
12.0 “I/O Ports”
Update Description
The CNCON registers in the Port Register Maps were updated (see Table 12-3
through Table 12-12).
The SIDL bit was removed from the CNCONx registers (see Register 12-3).
20.0 “Real-Time Clock and
Calendar (RTCC)”
A note regarding the RTCC pin was added in the key features.
22.0 “Serial Quad Interface
(SQI)”
Note 1 in the SQI Module Block Diagram was updated ( see Figure 22-1).
26.0 “External Bus Interface
(EBI)”
Note 2 was added on EBI module usage with the Graphics LCD (GLCD)
Controller.
Table 26-1: EBI Module Features was removed.
Note 1 was removed from the External Bus Interface Address Mask register (see
Register 26-2).
29.0 “12-bit High-Speed
Successive Approximation
Register (SAR) Analog-toDigital Converter (ADC)”
EQUATION 29-1: “ADC Throughput Rate” and notes were added.
Note 1 was added to the ADC Register Map (see Table 29-1).
A note was added to the SELRES bits in the ADCCON1 and the ADCxTIME
registers (see Register 29-1 and Register 29-27, respectively).
The AICPMPEN bit was added to the ADC Control Register 1 (see Table 29-1 and
Register 29-1).
The bit values and the note for the CHNLID bits in the ADCFLTRx register were
updated (see Register 29-16).
The bit values for the ADCID bits in the ADCFSTAT register were updated (see
Register 29-22).
The ADCCFG bit definition and the note were updated in the ADCxCFG register
(see Register 29-33).
34.0 “High/Low-Voltage Detect The SIDL bit was removed from the HLVDCON register (see Table 34-1 and
(HLVD)”
Register 34-1).
36.0 “Graphics LCD (GLCD)
Controller”
The bit positions of FORCEALPHA and DISABIFIL in the GLCDLxMODE register
were switched (see Table 36-1 and Register 36-9).
38.0 “DDR2 SDRAM
Controller”
The DDRPHYPADCON register was updated (see Table 38-1 and Register 38-28).
The values at POR were updated in the following registers:
•
•
•
•
39.0 “Secure Digital Host
Controller (SDHC)”
Register 38-18
Register 38-25
Register 38-26
Register 38-28
Note 1 in the Secure Digital Host Controller (SDHC) Block Diagram was updated
(see Figure 39-1).
40.0 “Power-Saving Features” The WAKEDIS bit was removed from the Deep Sleep Control register (see
Table 40-1 and Register 40-1).
41.0 “Special Features”
DEVSN2 and DEVSN3 were added to the Device Serial Number Summary (see
Table 41-4).
The Device ADC Calibration Summary was added (see Table 41-5).
Note 2 was added to the JTAGEN bit in the CFGCON register (see Register 41-9).
DS60001361J-page 812
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
TABLE A-2:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
44.0 “Electrical
Characteristics”
Update Description
The Operating Conditions were updated from 2.0V - 3.6V to 2.2V - 3.6V for VDDIO
and 1.7V - 1.9V for VDDCORE throughout the chapter.
The Absolute Maximum Ratings were updated.
Updated VDDIO values from 0.8*VDDIO to 0.65*VDDIO.(see Table 44-10, Table 4415, Table 44-22).
Updated thermal packaging characteristics (see Table 44-3).
Updated typical DC characteristics (see Table 44-7).
Updated SD Host Controller timing specs - min. standard operating conditions (see
Table 44-58 and Table 44-59).
All tables were updated.
46.0 “Packaging Information”
Updated packaging dimensions (see 46.1 “Package Marking Information”).
Added information for 6JX packaging (see 46.1 “Package Marking Information”
and 46.2 “Package Details”).
Product Identification System The package marking for V-Temp devices was changed to V.
2015-2021 Microchip Technology Inc.
DS60001361J-page 813
PIC32MZ Graphics (DA) Family
Revision D (March 2017)
This revision includes the following major changes,
which are referenced by their respective chapter in
Table TABLE A-3:Major Section Updates.
In addition, minor updates to text and formatting were
incorporated throughout the document.
TABLE A-3:
MAJOR SECTION UPDATES
Section Name
Update Description
32-bit Graphics Applications
Table 5, updated pin B4 to VDDCORE and B6 to VDDIO.
MCUs (up to 2 MB Live Update
Flash, 640 KB SRAM, and 32
MB DDR2 SDRAM) with XLP
Technology
4.0 “Memory Organization”
Figure 4-1, updated KSEG3 from “cacheable” to “not cacheable”
6.0 “Resets”
Updated Figure 6-1.
8.0 “Oscillator Configuration” Table 8-1, added SYSCLK to peripheral EBI.
26.0 “External Bus Interface
(EBI)”
Figure 26-1, changed PBCLK8 to SYSCLK
29.0 “12-bit High-Speed
Successive Approximation
Register (SAR) Analog-toDigital Converter (ADC)”
Register 29-1, bit 12, updated notes and added table.
38.0 “DDR2 SDRAM
Controller”
Table 38-1, swapped register names DRVSTRPFET and DRVSTRNFET.
Table 38-1, added offset address 9140.
Register 38-28, swapped register names and definitions DRVSTRPFET and
DRVSTRNFET.
Added Register 38-30,
40.0 “Power-Saving Features” Register 40-1, updated “command” to “instruction.” Updated 40.2.4 “VBAT Mode”
41.0 “Special Features”
Register 41-5, updated “command” to “instruction.”.
Register 41-9, bit 7, updated notes and added table.
44.0 “Electrical
Characteristics”
Updated 44.1 “DC Characteristics”
Updated Table 44-4 and Table 44-5.
Table 44-18, Added parameter D306.
Table 44-56, updated values for parameters DDR10, DDR19, DDR22, and
DDR23.
DS60001361J-page 814
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
Revision E (May 2017)
This revision includes the following major changes,
which are referenced by their respective chapter in
Table TABLE A-4:Major Section Updates.
In addition, minor updates to text and formatting were
incorporated throughout the document.
TABLE A-4:
MAJOR SECTION UPDATES
Section Name
Update Description
32-bit Graphics Applications
Updated the value of pin 168 from “CVREFOUT/AN5/RPB10/RB10” to “AN5/RPB10/
MCUs (up to 2 MB Live Update RB10” (see Table 6).
Flash, 640 KB SRAM, and 32
MB DDR2 SDRAM) with XLP
Technology
25.0 “Parallel Master Port
(PMP)”
The Virtual Address column heading was updated from BF80 to BF82 and the
virtual addresses were updated from 70xx to E0xx (see Table 25-1).
36.0 “Graphics LCD (GLCD)
Controller”
The resolutions in the key features list were updated.
39.0 “Secure Digital Host
Controller (SDHC)”
The eMMC Standard: JESD84-A441 was added to the features list.
44.0 “Electrical
Characteristics”
Table 44-7, Table 44-8, Table 44-9, Table 44-10, Table 44-11, Table 44-16,
Table 44-18 updated various DC Characteristics parameters.
Table 44-27, Table 44-28, Table 44-29 updated various AC Characteristics
parameters.
2015-2021 Microchip Technology Inc.
DS60001361J-page 815
PIC32MZ Graphics (DA) Family
Revision F (January 2018)
This revision includes the following major changes,
which are referenced by their respective chapter in
Table TABLE A-5:Major Section Updates.
In addition, minor updates to text and formatting were
incorporated throughout the document.
TABLE A-5:
MAJOR SECTION UPDATES
Section Name
1.0 “Device Overview”
Update Description
The PIC32MZ DA Family Block Diagram was updated (see Figure 1-1).
The 176-pin LQFP pin number for SDA3 in the I1C1 through I2C5 Pinout I/O
Descriptions was updated (see Table Table 1-10:I2C1 through I2C5 Pinout I/O
Descriptions).
The 169-pin LFBGA pin numbers for EBIOE and EBIWE in the EBI Pinout I/O
Descriptions were updated (see Table Table 1-13:EBI Pinout I/O Descriptions).
2.0 “Guidelines for
The following sections were added:
Getting Started with 32-bit • 2.7.1 “Crystal Oscillator Design Consideration”
Microcontrollers”
• 2.9 “Considerations When Interfacing to Remotely Powered Circuits”
4.0 “Memory
Organization”
The PIC32MZ DA Family Memory Map was updated (see Figure 4-1).
10.0 “Direct Memory
CRCTYP bit number references in the DMA CRC Control Register were updated (see
Access (DMA) Controller” Register 10-4 DCRCCON: DMA CRC Control Register, Register 10-5 DCRCDATA:
DMA CRC Data Register, and Register 10-6 DCRCXOR: DMA CRCXOR Enable
Register).
36.0 “Graphics LCD
(GLCD) Controller”
The key features for the module were updated.
37.0 “2-D Graphics
Processing Unit (GPU)”
The key features for the module were updated.
38.0 “DDR2 SDRAM
Controller”
The definition when SCLLBPASS is set to ‘0’ was updated and the SCLPHCAL bit was
added (see Register 38-24 DDRSCLSTART: DDL SELF CALIBRATION LOGIC START
REGISTER).
The GPURESET bit reference in Note 2 was updated.
The following registers were added:
•
•
•
•
41.0 “Special Features”
Register 38-31: “DDRPHYCLKDLY: DDR Clock Delta Delay Register”
Register 38-32: “DDRADLLBYP: DDR ANALOG DLL BYPASS Register”
Register 38-33: “DDRSCLCFG2: DDR SCL Configuration Register 2”
Register 38-34: “DDRPHYSCLADR: DDR PHY SCL Address Register”
The Device Configuration Word 0 registers, DEVCFG0/ADEVCFG0, was extensively
updated (see Register 41-3 DEVCFG0/ADEVCFG0: Device/Alternate Device
Configuration Word 0).
The bit value definitions for the FCKSM bits and the POSCMOD bits in the
Device Configuration Word 1 registers, DEVCFG1/ADEVCFG1, were updated (see
Register 41-4 DEVCFG1/ADEVCFG1: Device Configuration Word 1).
44.0 “Electrical
Characteristics”
DS60001361J-page 816
Parameter DO50 (COSCO) was removed from the Capacitive Loading Requirements on
Output Pins (see Table Table 44-22:Capacitive Loading Requirements on Output Pins).
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
Revision G (September 2018)
This revision includes the following major changes,
which are referenced by their respective chapter in the
following table.
TABLE A-6:
In addition, minor updates to text and formatting were
incorporated throughout the document.
MAJOR SECTION UPDATES
Section Name
Update Description
TABLE 2: “169-pin LFBGA PIC32MZ DA Features”, TABLE
3: “176-pin LQFP PIC32MZ DA Features”, and TABLE
4: “288-pin LFBGA PIC32MZ DA Features”
Updated three tables with package information
4.0 “Memory Organization”
The PIC32MZ DA Family Memory Map was
updated (see Figure 4-1).
Register 6-3: “RNMICON: Non-Maskable Interrupt (NMI)
Control Register”
Added attributes and new note.
TABLE 12-1: “Input Pin Selection”
Corrected peripheral pin name.
Register 17-3: “DMTCLR: Deadman Timer Clear Register”
and Register 17-4: “DMTSTAT: Deadman Timer Status
Register”
Corrected and added description of bits.
Register 28-4: “RNGNUMGENx: Random Number Generator Added Note to both registers.
Register ‘x’ (‘x’ = 1 or 2)” and Register 28-5: “RNGSEEDx:
True Random Number Generator Seed Register ‘x’ (‘x’ = 1 or
2)”
Register 34-1: “HLVDCON: High/Low-Voltage Detect Control Corrected Pin Description for HLVDL bits.
Register”
FIGURE 39-1: “Secure Digital Host Controller (SDHC) Block
Diagram”
Pin name corrected to SDDATA3.
FIGURE 40-1: “XLP Device Block Diagram”
Corrected text in figure.
Register 40-1: “DSCON: Deep Sleep Control Register”
Corrected Bit 1 DSBOR description
Table 44-2: “Thermal Operating Conditions”
Corrected the Formula for PINT and PI/O
TABLE 44-6: “Low-Voltage Detect Characteristics”
Removed bitfields 1100, 1101, and 1110 as they
are reserved.
“Communication Interfaces”
Corrected Lin support from LIN1.2 to LIN2.1
Table 1-6: “PORTA through PORTK Pinout I/O Descriptions” RB14 pin for LQFP176 corrected from 175 to 159
Table TABLE 4-3:Boot Flash 1 Sequence and Configuration
Words Summary
Table Note Updated
Table TABLE 4-4:Boot Flash 2 Sequence and Configuration
Words Summary
Table Note Updated
Table Register 8-4:REFOxCON: Reference Oscillator Control Bit 30-16 explained in detail
Register (‘x’ = 1-5)
Table Register 21-1:SPIx CON: SPI Control Register
Bit 29 Description Corrected
Table Register 26-1:EBICSx: External Bus Interface Chip
Select Register (‘x’ = 0-3)
Note added
Table Register 36-16:GLCDSTAT: Graphics LCD Controller
Status Register
Note Added for bit 3 and bit 2
Table Register 41-13:CFGCON2: Configuration Control
Register 2
Bit 0 definition corrected
Table Table 44-23:External Clock Timing Requirements
OS42 detail added
Table Table 44-53:Ethernet Module Specifications
Corrected parameter ET13 name from setup and
Hold to output Delay
46.1 “Package Marking Information”
Updated package marking information
2015-2021 Microchip Technology Inc.
DS60001361J-page 817
PIC32MZ Graphics (DA) Family
Revision H (May 2019)
This revision includes the following major changes,
which are referenced by their respective chapter in the
following table.
TABLE A-7:
In addition, minor updates to text and formatting were
incorporated throughout the document.
MAJOR SECTION UPDATES
Section Name
Update Description
Table TABLE 2:169-pin LFBGA PIC32MZ DA Features
Package information was added
Table Table 1-2:Oscillator Pinout I/O Descriptions
SOSCO description was added
Table Table 1-6:PORTA through PORTK Pinout I/O
Descriptions
Pin Number for 176-pin LQFP was corrected
Table Table 1-13:EBI Pinout I/O Descriptions
Pin Number for 176-pin LQFP was corrected
Table Table 4-5:Timing Parameters
Timing parameters was corrected
Register 8-6 PBxDIV: Peripheral Bus ‘x’ Clock Divisor
Control Register (‘x’ = 1-7)
Added Note 2
Register 11-9 USBIENCSR1: USB Indexed Endpoint
Control Status Register 1 (Endpoint 1-7)
Note added
Register 11-13 USBOTG: USB OTG Control/Status
Register
bit 4-3 was corrected
Register 11-25 USBDPBFD: USB Double Packet Buffer
Disable Register
Register bitfields were corrected
Register 23-1 I2CxCON: I2C Control Register
In bit16 and bit 18 the bit name SCKREL is corrected to
read SCLREL
Register 25-2 PMMODE: Parallel Port Mode Register
Note added for bitfield 14-13 IRQM
Register 25-7 PMSTAT: Parallel Port Status Register
(Slave modes only)
• Note added for bit 14 IBOV
• Note added for bit 6 OBUF
28.0 “Random Number Generator (RNG)”
LSFR was corrected to read LFSR
Register 29-3 ADCCON3: ADC Control Register 3
bitfield 15-13 bits definition was corrected
Register 29-16 ADCFLTRx: ADC Digital Filter ‘x’ Register Note added for bit 31 AFEN
(‘x’ = 1 through 6)
39.0 “Secure Digital Host Controller (SDHC)”
Added Note 2.
Register 41-5 DEVCFG2/ADEVCFG2: Device
Configuration Word 2
Note added for bit 28 FDSEN
44.0 “Electrical Characteristics”
• Maximum current rating added for VDDCORE and
VDDR1V8
• ESD Qualification added
Table Table 44-2:Thermal Operating Conditions
Formula added for DDR2 version
Table Table 44-5:Electrical Characteristics: RESETS
Parameter numbers RST10 and RST11 corrected and
Note added for RST11
Table Table 44-17:DC Characteristics: DDR2 SDRAM
Memory
Maximum current rating reduced for some parameters
Table Table 44-18:Comparator Specifications
CMRR and VICM values corrected
DS60001361J-page 818
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
Revision J (June 2021)
The I2C, SPI, and I2S standards use the terminology
"Master" and "Slave". The equivalent Microchip terminology used in this document is "Host" and "Client"
respectively.
This revision includes the following major changes,
which are referenced by their respective chapter in the
following table.
In addition, minor updates to text and formatting were
incorporated throughout the document.
Section Name or Type
Update Description
General
• Throughout the document, References to both “Master”
and “Slave” were revised to read “Host” and “Client” where
applicable
• Updated “Operating Conditions” to reflect correct temperature ranges
2.0 “Guidelines for Getting Started with 32-bit
Microcontrollers”
• Updated 2.9.2 “5V Tolerant Input Pins”, correcting VDD
to VDDIO, and updated VDDIO specifications in the text
8.0 “Oscillator Configuration”
• Removed erroneous information within parenthesis on
Note 6 for Table 8-1: “System and Peripheral clock Distribution”
• Updated Register 8-4: “REFOxCON: Reference Oscillator Control Register (‘x’ = 1-5)” to properly display x=15, and added a note number 4
17.0 “Deadman Timer (DMT)”
• Updated to note for Register 17-1: “DMTCON: Deadman
Timer Control Register”
21.0 “Serial Peripheral Interface (SPI) and Inter-IC • Updated FIGURE 21-1: “SPI/I2S Module Block DiaSound (I2S)”
gram” to read “SPI Select” instead of “Slave Select”
25.0 “Parallel HOST Port (PMP)””
• Added a new note to the IRQM bit of Register 252: “PMMODE: Parallel Port Mode Register”
• Added a new note to the IBOV bit of Register 257: “PMSTAT: Parallel Port Status Register (Client
modes only)”
35.0 “Charge Time Measurement Unit (CTMU)”
• Added AN5 to AN39 to the first bulleted item on page 585
36.0 “Graphics LCD (GLCD) Controller”
• Corrected typographical errors in bitfield 5-0 for Register
36-2: “GLCDCLKCON: Graphics LCD Controller Clock
Control Register”
38.0 “DDR2 SDRAM Controller”
• Added a note to bit 28 of Register 3824: “DDRSCLSTART: DDL SELF CALIBRATION LOGIC
START REGISTER”
• Corrected a typographical error is the DLYSTVAL bitfield
of Register 38-29: “DDRPHYDLLR: DDR PHY DLL
Recalibrate Register”
40.0 “Power-Saving Features”
• Updated FIGURE 40-1: “XLP Device Block Diagram” to
properly display VDDCORE
• A new note was added to 40.4 “Peripheral Module Disable”
2015-2021 Microchip Technology Inc.
DS60001361J-page 819
PIC32MZ Graphics (DA) Family
Section Name or Type
Update Description
41.0 “Special Features”
• Added a new note to the FDMTEN bitfield for Register 414: “DEVCFG1/ADEVCFG1: Device Configuration Word
1”
• Corrected typographical errors in 41.4 “On-Chip Voltage
Regulator”
44.0 “Electrical Characteristics”
• Updated Table 44-24: “System Timing Requirements”
with new conditions for the Reference Clock frequency
• Updated Table 44-26: “MPLL Clock Timing Requirements” with a new maximum value for the MP12 Parameter
• Updated the characteristics for Table 44-55: “GLCD Controller Timing Specifications”with the addition of GLCD
pin verbiage
• Updated TABLE 44-56: “Internal DDR2 SDRAM Timing
Specifications” with a correction to note 5
46.0 “Packaging Information”
• Updated the Descriptions for the 169-Ball Low Profile Ball
Grid Array
“Product Identification System”
• Updated the Package description for the 169 Lead LFBGA
DS60001361J-page 820
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
INDEX
A
AC Characteristics ............................................................ 751
ADC Specifications ................................................... 776
Analog-to-Digital Conversion Requirements............. 777
DDR2 SDRAM Timing Requirements ....................... 754
EBI Timing Requirements ................. 745, 750, 787, 789
EJTAG Timing Requirements ................................... 791
Ethernet .................................................................... 784
Internal BFRC Accuracy ........................................... 755
Internal FRC Accuracy.............................................. 755
Internal RC Accuracy ................................................ 755
OTG Electrical Specifications ................................... 783
Parallel Master Port Read Requirements ................. 781
Parallel Master Port Write ......................................... 782
Parallel Master Port Write Requirements.................. 782
Parallel Slave Port Requirements ............................. 780
PLL Clock Timing...................................................... 753
Assembler
MPASM Assembler................................................... 730
B
Block Diagrams
Comparator I/O Operating Modes............................. 575
Comparator Voltage Reference ................................ 579
CPU ............................................................................ 52
Crypto Engine ........................................... 407, 613, 615
CTMU Configurations
Time Measurement ........................................... 587
DMA .......................................................................... 185
Ethernet Controller.................................................... 531
Graphics LCD (GLCD) Controller ............................. 594
High/Low-Voltage Detect (HLVD) ............................. 583
Input Capture ............................................................ 297
Inter-Integrated Circuit (I2C) ..................................... 370
Interrupt Controller .................................................... 129
JTAG Programming, Debugging and Trace Ports .... 725
Output Compare Module........................................... 301
PIC32 CAN Module................................................... 493
PMP Pinout and Connections to External Devices ... 385
Prefetch Module........................................................ 181
Prefetch Module Block Diagram ............................... 181
Random Number Generator (RNG) .......................... 429
Reset System............................................................ 121
RTCC ........................................................................ 321
Serial Quad Interface (SQI) ...................................... 341
SPI Module ............................................................... 331
Timer1....................................................................... 287
Timer2/3/4/5 (16-Bit) ................................................. 291
Typical Multiplexed Port Structure ............................ 259
UART ........................................................................ 377
WDT and Power-up Timer ................................ 315, 319
Brown-out Reset (BOR)
and On-Chip Voltage Regulator................................ 725
C
C Compilers
MPLAB C18 .............................................................. 730
Charge Time Measurement Unit. See CTMU.
Comparator
Specifications............................................ 745, 748, 749
Comparator Module .......................................................... 575
Comparator Voltage Reference (CVref ............................. 579
Configuration Bit ............................................................... 697
2015-2021 Microchip Technology Inc.
Configuring Analog Port Pins............................................ 260
Controller Area Network (CAN) ........................................ 493
CP0 Register 16, Select 1) ................................................. 58
CP0 Register 16, Select 2) ................................................. 60
CP0 Register 16, Select 3) ................................................. 59
CPU
Architecture Overview ................................................ 53
Coprocessor 0 Registers ............................................ 54
Core Exception Types .............................................. 130
EJTAG Debug Support............................................... 56
Power Management ................................................... 56
CPU Module ................................................................. 39, 51
Crypto
Buffer Descriptors..................................................... 418
Format of SA_CTRL ................................................. 426
Security Association Structure.................................. 423
Crypto Engine ........................................................... 407, 615
Customer Change Notification Service............................. 827
Customer Notification Service .......................................... 827
Customer Support............................................................. 827
D
DC Characteristics............................................................ 734
I/O Pin Input Specifications .............................. 740, 744
I/O Pin Output Specifications.................................... 741
Idle Current (IIDLE) .................................................... 738
Power-Down Current (IPD)........................................ 739
Program Memory...................................................... 746
Temperature and Voltage Specifications.................. 735
Development Support ....................................................... 729
Direct Memory Access (DMA) Controller.......................... 185
E
Electrical Characteristics .................................................. 733
AC............................................................................. 751
High/Low-Voltage Detect.......................................... 736
Errata .................................................................................. 15
Ethernet Controller............................................................ 531
ETHPMM0 (Ethernet Controller Pattern Match Mask 0)... 541
ETHPMM1 (Ethernet Controller Pattern Match Mask 1)... 541
External Bus Interface (EBI) ............................................. 399
External Clock
Timer1 Timing Requirements ................................... 760
Timer2, 3, 4, 5 Timing Requirements ....................... 761
Timing Requirements ............................................... 752
F
Flash Program Memory ............................................ 111, 121
RTSP Operation ....................................................... 111
G
Graphics LCD (GLCD) Controller ..................................... 593
H
High-Voltage Detect (HVD)............................................... 123
Hi-Speed USB On-The-Go (OTG) .................................... 209
I
I/O Ports ........................................................................... 259
Parallel I/O (PIO) ...................................................... 260
Write/Read Timing.................................................... 260
Input Change Notification ................................................. 260
Instruction Set................................................................... 727
Inter-Integrated Circuit (I2C) ............................................. 369
DS60001361J-page 821
PIC32MZ Graphics (DA) Family
Internet Address................................................................ 827
Interrupt Controller
IRG, Vector and Bit Location .................................... 132
M
Memory Maps
Devices with 2048 KB Program Memory .................... 62
Memory Organization.......................................................... 61
Layout ......................................................................... 61
Microchip Internet Web Site .............................................. 827
MPLAB ASM30 Assembler, Linker, Librarian ................... 730
MPLAB Integrated Development Environment Software .. 729
MPLAB PM3 Device Programmer..................................... 731
MPLAB REAL ICE In-Circuit Emulator System................. 731
MPLINK Object Linker/MPLIB Object Librarian ................ 730
O
Oscillator Configuration..................................................... 163
Output Compare................................................................ 301
P
Packaging ......................................................................... 795
Details ....................................................................... 796
Marking ..................................................................... 795
Parallel Master Port (PMP) ............................................... 385
Pinout I/O Descriptions (table) . 18, 19, 20, 21, 24, 25, 26, 27,
28, 29, 30, 31, 32, 33, 34, 36, 38
Power-on Reset (POR)
and On-Chip Voltage Regulator ................................ 725
Power-Saving Features..................................................... 683
with CPU Running..................................................... 683
Prefetch Module ................................................................ 181
R
Random Number Generator (RNG) .................................. 429
Real-Time Clock and Calendar (RTCC)............................ 321
Register
GLCDLxBADDR (Graphics LCD Controller Layer ‘x’
Base Address) .................................................. 606
Register Map
Comparator ............................................................... 576
Comparator Voltage Reference ........................ 580, 584
Device ADC Calibration Summary ............................ 701
Device Configuration Word Summary............... 698, 699
Device Serial Number Summary............................... 700
DMA Channel 0-3 ..................................................... 187
DMA CRC ................................................................. 186
DMA Global............................................................... 186
EBI ............................................................................ 400
Flash Controller......................................... 112, 308, 316
I2C1 Through I2C5 ................................................... 371
Input Capture 1-9 ...................................................... 299
Interrupt..................................................................... 140
Oscillator Configuration............................................. 167
Output Compare1-9 .................................................. 303
Parallel Master Port .................................................. 386
Peripheral Pin Select Input ....................................... 278
Peripheral Pin Select Output..................................... 282
PORTA...................................................................... 268
PORTB...................................................................... 269
PORTH ..................................................................... 275
PORTK.............................................................. 276, 277
Prefetch..................................................................... 182
RTCC ........................................................................ 322
SPI1 through SPI6 .................................................... 332
System Bus ................................................................. 77
DS60001361J-page 822
System Bus Target 0 .................................................. 78
System Bus Target 1 ...................................... 95, 96, 97
System Bus Target 10 ................................................ 91
System Bus Target 11 ................................................ 92
System Bus Target 12 ................................................ 93
System Bus Target 13 ................................................ 94
System Bus Target 2 .................................................. 81
System Bus Target 3 .................................................. 82
System Bus Target 4 .................................................. 83
System Bus Target 5 .................................................. 85
System Bus Target 6 .................................................. 87
System Bus Target 7 .................................................. 88
System Bus Target 8 .................................................. 89
System Bus Target 9 .................................................. 90
System Control ......................................................... 122
Timer1-Timer9 .................................................. 288, 293
UART1-5................................................................... 378
USB .................................................................. 211, 217
Registers
[pin name]R (Peripheral Pin Select Input) ................ 285
AD1CON1 (A/D Control 1)........................................ 330
AD1CON1 (ADC Control 1) ...................................... 330
ADCANCON (ADC Analog Warm-up Control Register) .
489
ADCBASE (ADC Base) ............................................ 482
ADCCMP1CON (ADC Digital Comparator 1 Control
Register) ........................................................... 476
ADCCMPENx (ADC Digital Comparator ‘x’ Enable Register (‘x’ = 1 through 6))..................................... 469
ADCCMPx (ADC Digital Comparator ‘x’ Limit Value Register (‘x’ = 1 through 6))..................................... 470
ADCCMPxCON (ADC Digital Comparator ‘x’ Control
Register (‘x’ = 1 through 6)) .............................. 478
ADCCON1 (ADC Control Register 1) ....................... 446
ADCCON2 (ADC Control Register 2) ....................... 449
ADCCON3 (ADC Control Register 3) ....................... 452
ADCCSS1 (ADC Common Scan Select Register 1). 466
ADCCSS2 (ADC Common Scan Select Register 2). 467
ADCDATAx (ADC Output Data Register (‘x’ = 0 through
44)) ................................................................... 483
ADCDSTAT1 (ADC Data Ready Status Register 1). 468
ADCDSTAT2 (ADC Data Ready Status Register 2). 468
ADCEIEN1 (ADC Early Interrupt Enable Register 1) 486
ADCEIEN2 (ADC Early Interrupt Enable Register 2) 486
ADCEISTAT2 (ADC Early Interrupt Status Register 2) ..
488
ADCFLTRx (ADC Digital Filter ‘x’ Register (‘x’ = 1
through 6)) ........................................................ 471
ADCGIRQEN1 (ADC Interrupt Enable Register 1) ... 465
ADCIMCON1 (ADC Input Mode Control Register 1) 457
ADCIMCON2 (ADC Input Mode Control Register 2) 460
ADCIMCON3 (ADC Input Mode Control Register 3) 463
ADCIRQEN2 (ADC Interrupt Enable Register 2)...... 465
ADCSYSCFG1 (ADC System Configuration Register 1)
492
ADCSYSCFG2 (ADC System Configuration Register 2)
492
ADCTRG1 (ADC Trigger Source 1 Register) ........... 473
ADCTRG2 (ADC Trigger Source 2 Register) ........... 474
ADCTRG3 (ADC Trigger Source 3 Register) ........... 475
ADCTRGMODE (ADC Triggering Mode for Dedicated
ADC)................................................................. 455
ADCTRGSNS (ADC Trigger Level/Edge Sensitivity) 484
ADCxCFG (ADCx Configuration Register ‘x’ (‘x’ = 1
through 6)) ........................................................ 491
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
ADCxTIME (Dedicated ADCx Timing Register ‘x’ (‘x’ = 0
through 4)) ........................................................ 485
ALRMDATE (Alarm Date Value)............................... 330
ALRMDATECLR (ALRMDATE Clear)....................... 330
ALRMDATESET (ALRMDATE Set) .......................... 330
ALRMTIME (Alarm Time Value) ............................... 329
ALRMTIMECLR (ALRMTIME Clear)......................... 330
ALRMTIMEINV (ALRMTIME Invert) ......................... 330
ALRMTIMESET (ALRMTIME Set) ............................ 330
CFGCON (Configuration Control Register)............... 715
CFGCON2 (Configuration Control Register 2).......... 721
CFGMPLL (Memory PLL Configuration)................... 722
CHECON (Cache Control) ........................................ 184
CM1CON (Comparator 1 Control) ............................ 577
CMSTAT (Comparator Control Register).................. 578
CNCONx (Change Notice Control for PORTx) ......... 286
CONFIG (CP0 Register 16, Select 0) ......................... 57
CONFIG1 (CONFIG1 Register ................................... 58
CONFIG2
(CONFIG2 Register ............................................ 60
CONFIG2 (CONFIG2 Register ................................... 60
CONFIG3 (CONFIG3 Register ................................... 59
CTMUCON (CTMU Control) ..................................... 589
CVRCON (Comparator Voltage Reference Control). 581
DCHxCON (DMA Channel x Control) ....................... 198
DCHxCPTR (DMA Channel x Cell Pointer) .............. 206
DCHxCSIZ (DMA Channel x Cell-Size) .................... 206
DCHxDAT (DMA Channel x Pattern Data) ............... 207
DCHxDPTR (Channel x Destination Pointer)............ 205
DCHxDSA (DMA Channel x Destination
Start Address) ................................................... 203
DCHxDSIZ (DMA Channel x Destination Size)......... 204
DCHxECON (DMA Channel x Event Control)........... 200
DCHxINT (DMA Channel x Interrupt Control) ........... 201
DCHxSPTR (DMA Channel x Source Pointer) ......... 205
DCHxSSA (DMA Channel x Source Start Address) . 203
DCHxSSIZ (DMA Channel x Source Size) ............... 204
DCRCCON (DMA CRC Control)............................... 195
DCRCDATA (DMA CRC Data) ................................. 197
DCRCXOR (DMA CRCXOR Enable)........................ 197
Description ........................................................ 658, 675
DEVCFG0 (Device Configuration Word 0................. 703
DEVCFG1 (Device Configuration Word 1................. 706
DEVCFG2 (Device Configuration Word 2................. 709
DEVCFG3 (Device Configuration Word 3......... 712, 713
DEVID (Device and Revision ID) ................ 68, 702, 724
DMAADDR (DMA Address) ...................................... 194
DMAADDR (DMR Address) ...................................... 194
DMACON (DMA Controller Control) ......................... 193
DMASTAT (DMA Status) .......................................... 194
DMSTAT (Deadman Timer Status)........................... 311
DMTCLR (Deadman Timer Clear) ............................ 310
DMTCNT (Deadman Timer Count) ........................... 312
DMTCON (Deadman Timer Control) ........................ 309
DMTPRECLR (Deadman Timer Preclear) ................ 309
EBICSx (External Bus Interface Chip Select) .. 401, 404,
717, 718
EBIMSKx (External Bus Interface Address Mask) .... 402
EBISMCON (External Bus Interface Static Memory Control).................................................................... 405
EBISMTx (External Bus Interface Static Memory Timing)
403
EMAC1CFG1 (Ethernet Controller MAC Configuration 1)
558
EMAC1CFG2 (Ethernet Controller MAC Configuration 2)
2015-2021 Microchip Technology Inc.
559
EMAC1CLRT (Ethernet Controller MAC Collision Window/Retry Limit)................................................ 563
EMAC1IPGR (Ethernet Controller MAC Non-Back-toBack Interpacket Gap)...................................... 562
EMAC1IPGT (Ethernet Controller MAC Back-to-Back Interpacket Gap).................................................. 561
EMAC1MADR (Ethernet Controller MAC MII Management Address) .................................................. 569
EMAC1MAXF (Ethernet Controller MAC Maximum
Frame Length) .................................................. 564
EMAC1MCFG (Ethernet Controller MAC MII Management Configuration) .......................................... 567
EMAC1MCMD (Ethernet Controller MAC MII Management Command)............................................... 568
EMAC1MIND (Ethernet Controller MAC MII Management Indicators)................................................ 571
EMAC1MRDD (Ethernet Controller MAC MII Management Read Data) .............................................. 570
EMAC1MWTD (Ethernet Controller MAC MII Management Write Data) .............................................. 570
EMAC1SA0 (Ethernet Controller MAC Station Address
0) ...................................................................... 572
EMAC1SA1 (Ethernet Controller MAC Station Address
1) ...................................................................... 573
EMAC1SA2 (Ethernet Controller MAC Station Address
2) ...................................................................... 574
EMAC1SUPP (Ethernet Controller MAC PHY Support).
565
EMAC1TEST (Ethernet Controller MAC Test) ......... 566
ETHALGNERR (Ethernet Controller Alignment Errors
Statistics) .......................................................... 557
ETHCON1 (Ethernet Controller Control 1) ............... 536
ETHCON2 (Ethernet Controller Control 2) ............... 538
ETHFCSERR (Ethernet Controller Frame Check Sequence Error Statistics) .................................... 556
ETHFRMRXOK (Ethernet Controller Frames Received
OK Statistics).................................................... 555
ETHFRMTXOK (Ethernet Controller Frames Transmitted OK Statistics).............................................. 552
ETHHT0 (Ethernet Controller Hash Table 0)............ 540
ETHHT1 (Ethernet Controller Hash Table 1)............ 540
ETHIEN (Ethernet Controller Interrupt Enable) ........ 546
ETHIRQ (Ethernet Controller Interrupt Request)...... 547
ETHMCOLFRM (Ethernet Controller Multiple Collision
Frames Statistics)............................................. 554
ETHPM0 (Ethernet Controller Pattern Match Offset) 542
ETHPMCS (Ethernet Controller Pattern Match Checksum) ................................................................. 542
ETHRXFC (Ethernet Controller Receive Filter Configuration) .................................................................. 543
ETHRXOVFLOW (Ethernet Controller Receive Overflow
Statistics) .......................................................... 551
ETHRXST (Ethernet Controller RX Packet Descriptor
Start Address)................................................... 539
ETHRXWM (Ethernet Controller Receive Watermarks) .
545
ETHSCOLFRM (Ethernet Controller Single Collision
Frames Statistics)............................................. 553
ETHSTAT (Ethernet Controller Status) .................... 549
ETHTXST (Ethernet Controller TX Packet Descriptor
Start Address)................................................... 539
GLCDBGCOLOR (Graphics LCD Controller Background
Color)................................................................ 600
GLCDBLANKING (Graphics LCD Controller Blanking) ..
DS60001361J-page 823
PIC32MZ Graphics (DA) Family
601
GLCDBPORCH (Graphics LCD Controller Back Porch).
602
GLCDCLKCON (Graphics LCD Controller Clock Control)
599
GLCDCURSOR (Graphics LCD Controller Cursor) .. 602
GLCDFPORCH (Graphics LCD Controller Front Porch).
601
GLCDINT (Graphics LCD Controller Cursor Data) ... 611
GLCDINT (Graphics LCD Controller Cursor LUT) .... 612
GLCDINT (Graphics LCD Controller Interrupt) ......... 608
GLCDLxMODE (Graphics LCD Controller Layer ‘x’
Mode)................................................................ 603
GLCDLxRES (Graphics LCD Controller Layer ‘x’ Resolution .................................................................... 607
GLCDLxSIZE (Graphics LCD Controller Layer ‘x’ Size) .
605
GLCDLxSTART (Graphics LCD Controller Layer ‘x’
Start) ................................................................. 605
GLCDLxSTRIDE (Graphics LCD Controller Layer ‘x’
Stride) ....................................................... 606, 610
GLCDRES (Graphics LCD Controller Resolution) .... 600
GLCDSTAT (Graphics LCD Controller Status) ......... 609
GLDCMODE (Graphics LCD Controller Mode)......... 597
I2CxCON (I2C Control) ............................................. 373
I2CxSTAT (I2C Status) ............................................. 375
ICxCON (Input Capture x Control) ............................ 300
IFSx (Interrupt Flag Status)....................................... 159
INTCON (Interrupt Control) ....................................... 155
INTSTAT (Interrupt Status) ....................................... 158
IPCx (Interrupt Priority Control)................................. 160
IPTMR Interrupt Proximity Timer) ............................. 158
NVMADDR (Flash Address) ..................................... 115
NVMBWP (Flash Boot (Page) Write-protect) ............ 118
NVMCON (Programming Control Register) .............. 113
NVMCON2 (Programming Control Register 2) ......... 120
NVMDATA (Flash Data)............................................ 116
NVMKEY (Programming Unlock) .............................. 115
NVMPWP (Program Flash Write-Protect) ................. 117
NVMSRCADDR (Source Data Address)................... 116
OCxCON (Output Compare x Control) ..................... 305
OSCCON (Oscillator Control) ................................... 169
OSCTUN (FRC Tuning) ............................................ 171
PMADDR (Parallel Port Address) ............................. 391
PMAEN (Parallel Port Pin Enable) ............................ 394
PMCON (Parallel Port Control) ................................. 387
PMDIN (Parallel Port Input Data) ...................... 393, 398
PMDOUT (Parallel Port Output Data) ....................... 392
PMMODE (Parallel Port Mode) ................................. 389
PMRADDR (Parallel Port Read Address) ................. 397
PMSTAT (Parallel Port Status (Slave Modes Only) .. 395
PMWADDR (Parallel Port Write Address)................. 396
PRECON (Prefetch Module Control) ........................ 183
PRISS (Priority Shadow Select)................................ 156
PSCNT (Post Status Configure DMT Count Status) . 312
PSINTV (Post Status Configure DMT Interval Status) ....
313
REFOxCON (Reference Oscillator Control (’x’ = 1-4))....
174
REFOxTRIM (Reference Oscillator Trim (’x’ = 1-4)) . 176
RPnR (Peripheral Pin Select Output)........................ 285
RSWRST (Software Reset) ...................... 125, 126, 128
RTCCON (RTCC Control)......................................... 323
RTCDATE (RTC Date Value) ................................... 328
RTCTIME (RTC Time Value) .................................... 327
DS60001361J-page 824
SBFLAG (System Bus Status Flag).... 99, 100, 101, 102
SBTxECLRM (System Bus Target ’x’ Multiple Error Clear
106
SBTxECLRS (System Bus Target ’x’ Single Error Single)
106
SBTxECON (System Bus Target ’x’ Error Control)... 105
SBTxELOG1 (System Bus Target ’x’ Error Log 1).... 103
SBTxELOG2 (System Bus Target ’x’ Error Log 2).... 105
SBTxRDy (System Bus Target ’x’ Region ’y’ Read Permissions) .......................................................... 108
SBTxREGy (System Bus Target ’x’ Region ’y’) ........ 107
SBTxWRy (System Bus Target ’x’ Region ’y’ Write Permissions) .......................................................... 109
SPIxCON (SPI Control) ............................................ 334
SPIxCON2 (SPI Control 2) ....................................... 337
SPIxSTAT (SPI Status)............................................. 338
SPLLCON (System PLL Control).............................. 172
SQI1XCON1 (SQI XIP Control 1) ............................. 344
SQI1XCON2 (SQI XIP Control Register 2)............... 346
T1CON (Type A Timer Control) ................................ 289
TxCON (Type B Timer Control) ................................ 295
U1STAT (USB Status) ..... 620, 621, 622, 623, 624, 625,
626, 627, 628, 629, 630, 631, 632, 633, 634, 635,
636, 637, 638, 639, 640, 641, 642, 645, 646, 647,
649, 652, 653, 654
USBCRCON (USB Clock/Reset Control) ................. 257
USBCSR0 (USB Control Status 0) ........................... 218
USBCSR1 (USB Control Status 1) ........................... 220
USBCSR2 (USB Control Status 2) ........................... 221
USBCSR3 (USB Control Status 3) ........................... 223
USBDMAINT (USB DMA Interrupt) .......................... 248
USBDMAxA (USB DMA Channel ’x’ Memory Address) .
250
USBDMAxC (USB DMA Channel ’x’ Control)........... 249
USBDMAxN (USB DMA Channel ’x’ Count)............. 250
USBDPBFD (USB Double Packet Buffer Disable) ... 251
USBEOFRST (USB End-of-Frame/Soft Reset Control) .
245
USBExRPC (USB Endpoint ’x’ Request Packet Count
(Host Mode Only)) ............................................ 251
USBExRXA (USB Endpoint ’x’ Receive Address) .... 247
USBExTXA (USB Endpoint ’x’ Transmit Address).... 246
USBFIFOA (USB FIFO Address).............................. 242
USBHWVER (USB Hardware Version) .................... 243
USBIE0CSR0 (USB Indexed Endpoint Control Status 0
(Endpoint 0))..................................................... 225
USBIE0CSR2 (USB Indexed Endpoint Control Status 2
(Endpoint 0))..................................................... 227
USBIE0CSR3 (USB Indexed Endpoint Control Status 3
(Endpoint 0))..................................................... 228
USBIENCSR0 (USB Indexed Endpoint Control Status 0
(Endpoint 1-7)).................................................. 229
USBIENCSR1 (USB Indexed Endpoint Control Status 1
(Endpoint 1-7)).................................................. 232
USBIENCSR2 (USB Indexed Endpoint Control Status 2
(Endpoint 1-7)).................................................. 235
USBIENCSR3 (USB Indexed Endpoint Control Status 3
(Endpoint 1-7)).................................................. 236
USBINFO (USB Information) .................................... 244
USBLPMR1 (USB Link Power Management Control 1) .
253
USBLPMR2 (USB Link Power Management Control 2) .
255
USBTMCON1 (USB Timing Control 1) ..................... 252
USBTMCON2 (USB Timing Control 2) ..................... 252
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
WDTCON (Watchdog Timer Control) ............... 317, 689
Revision History ................................................................ 809
RTCALRM (RTC ALARM Control) .................................... 325
S
Serial Peripheral Interface (SPI) ....................................... 331
Serial Quad Interface (SQI) .............................................. 341
Software Simulator (MPLAB SIM)..................................... 731
Special Features ............................................................... 697
T
Timer1 Module .................................................................. 287
Timer2/3, Timer4/5, Timer6/7, and Timer8/9 Modules...... 291
Timing Diagrams
CAN I/O..................................................................... 775
EJTAG ...................................................................... 791
External Clock........................................................... 752
I/O Characteristics .................................................... 756
I2Cx Bus Data (Master Mode) .................................. 771
I2Cx Bus Data (Slave Mode) .................................... 773
I2Cx Bus Start/Stop Bits (Master Mode) ................... 771
I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 773
Input Capture (CAPx)................................................ 761
OCx/PWM ................................................................. 762
Output Compare (OCx)............................................. 762
Parallel Master Port Read......................................... 781
Parallel Master Port Write ......................................... 782
Parallel Slave Port .................................................... 780
SPIx Master Mode (CKE = 0) ................................... 763
SPIx Master Mode (CKE = 1) ................................... 765
2015-2021 Microchip Technology Inc.
SPIx Slave Mode (CKE = 0) ..................................... 767
SPIx Slave Mode (CKE = 1) ..................................... 768
Timer1, 2, 3, 4, 5 External Clock .............................. 760
UART Reception....................................................... 384
UART Transmission (8-bit or 9-bit Data) .................. 384
Timing Requirements
CLKO and I/O ........................................................... 756
Timing Specifications
CAN I/O Requirements............................................. 775
I2Cx Bus Data Requirements (Master Mode)........... 771
I2Cx Bus Data Requirements (Slave Mode)............. 773
Input Capture Requirements .................................... 761
Output Compare Requirements................................ 762
Simple OCx/PWM Mode Requirements ................... 762
SPIx Master Mode (CKE = 0) Requirements............ 764
SPIx Master Mode (CKE = 1) Requirements............ 766
SPIx Slave Mode (CKE = 1) Requirements.............. 768
SPIx Slave Mode Requirements (CKE = 0).............. 767
U
UART ................................................................................ 377
USB Interface Diagram..................................................... 210
V
Voltage Regulator (On-Chip) ............................................ 725
W
Watchdog Timer and Power-up Timer SFR Summary ..... 686
WWW Address ................................................................. 827
WWW, On-Line Support ..................................................... 15
DS60001361J-page 825
PIC32MZ Graphics (DA) Family
DS60001361J-page 826
2015-2021 Microchip Technology Inc.
PIC32MZ Graphics (DA) Family
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2015-2021 Microchip Technology Inc.
DS60001361J-page 827
PIC32MZ Graphics (DA) Family
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PIC32 MZ XX XX DA A XXX T - I / BG - XXX
Example:
PIC32MZ0512DAA176-I/2J:
Graphics MCU Family, PIC32,
MIPS32® microAptiv™ MPU core,
512 KB program memory,
176-pin, Industrial temperature,
LQFP package.
Microchip Brand
Architecture
Flash Memory Size
RAM Size
Family
Key Feature Set
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Flash Memory Family
Architecture
MZ
= MIPS32® microAptiv™ MPU Core
Flash Memory Size
10
20
= 1024 KB
= 2048 KB
RAM Size
25
64
= 256 KB
= 640 KB
Family
DA
= Graphics MCU Family
Key Feature
A
B
G
H
= PIC32 DA Family Features, no Crypto, no DDR memory
= PIC32 DA Family Features, with Crypto, no DDR memory
= PIC32 DA Family Features, no Crypto, with DDR memory
= PIC32 DA Family Features, with Crypto, with DDR memory
Pin Count
169
176
288
= 169-pin
= 176-pin
= 288-pin
Temperature Range
I
= -40°C to +85°C (Industrial)
Package
HF
6J
2J
4J
= 169-Lead (11x11x1.4 mm) LFBGA (Low Profile Fine Pitch Ball Grid Array)
= 169-Lead (11x11x1.56 mm) LFBGA (Low Profile Fine Pitch Ball Grid Array)
= 176-Lead (22x22x1.4 mm) LQFP (Low Profile Quad Flat Pack)
= 288-Lead (15x15x1.4 mm) LFBGA (Low Profile Fine Pitch Ball Grid Array)
Pattern
Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise)
ES
= Engineering Sample
2015-2021 Microchip Technology Inc.
DS60001361J-page 828
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specifications contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip
devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications
contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished
without violating Microchip's intellectual property rights.
•
Microchip is willing to work with any customer who is concerned about the integrity of its code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not
mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are
committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection
feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or
other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication is provided for the sole
purpose of designing with and using Microchip products. Information regarding device applications and the like is provided
only for your convenience and may be superseded by updates.
It is your responsibility to ensure that your application meets
with your specifications.
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS".
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION INCLUDING BUT NOT
LIMITED TO ANY IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
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Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
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INICnet, Intelligent Paralleling, Inter-Chip Connectivity,
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SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
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2015-2021 Microchip Technology Inc.
ISBN: 978-1-5224-8473-8
DS60001361J-page 829
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