PL123-09NSC

PL123-05N/-09N Low Skew Fanout Buffer FEATURES DESCRIPTION  The PL123-05N and PL123-09N are a low-cost fanout buffers for distributing high-speed clocks with low output to output skew and preserving low noise properties. The fanout buffers accept an input from DC to 134MHz and provide 5 or 9 outputs of the same frequency. A typical PL123-09N application for driving SDRAM in PC systems would use eight outputs to drive two DIMMs, or four SO-DIMMs, with the remaining output used for driving an external fee dback to a PLL. A typical PL123-05N application is to fanout a low noise CMOS clock oscillat or to 5 low noise CMOS clocks.          Output fanout buffer for DC to 134MHz Output Options: o 1:5 output fanout with PL123-05 o 1:9 output fanout with PL123-09 Low power consumption for portable applications Low input-output delay Output-Output skew less than 250ps Low Additive Phase Jitter of 60fs RMS 2.5V to 3.3V, ±10% operation 1.8V ±10% operation up to 67MHz Operating temperature range from -40°C to 85°C Available in 16-Pin SOP (PL123-09) and 8-Pin SOP (PL123-05). Both are GREEN/RoHS packages. These parts are not intended for 5V input-tolerant applications. BLOCK DIAGRAM AND PACKAGE PINOUT CLK1 REF CLK3 CLK4 REF 1 CLK1 2 CLK2 3 GND 4 CLK5 PL123-05N CLK2 8 CLK5 7 CLK4 6 VDD 5 CLK3 SOP-8L CLK1 1 16 CLK9 2 15 CLK8 CLK2 3 14 CLK7 CLK4 VDD 4 13 VDD CLK5 GND 5 12 GND CLK6 CLK3 6 11 CLK6 CLK4 7 10 CLK5 VDD 8 9 GND CLK3 REF CLK7 PL123-09N REF CLK1 CLK2 CLK8 CLK9 SOP-16L Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/15/12 Page 1 PL123-05N/-09N Low Skew Fanout Buffer PIN DESCRIPTIONS PL123-09N SOP-16L PL123-05N SOP-8L Type REF 1 1 I Input reference frequency. CLK1 2 2 O Buffered clock output CLK2 3 3 O Buffered clock output VDD 4, 8, 13 6 P VDD connection GND 5, 9, 12 4 P GND connection CLK3 6 5 O Buffered clock output CLK4 7 7 O Buffered clock output CLK5 10 8 O Buffered clock output CLK6 11 - O Buffered clock output CLK7 14 - O Buffered clock output CLK8 15 - O Buffered clock output CLK9 16 - O Buffered clock output Name Description LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a pe rformance optimized PCB design: Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations - Keep traces short! - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections ( looks like ringing ). - Design long traces (> 1 inch) as “striplines” or “microstrips” with defined impedance. - Match trace at one side to avoid reflections bounc ing back and forth. - Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1 F for designs using frequencies < 50MHz and 0.01F for designs using frequencies > 50MHz. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer To CMOS Input ( Typical buffer impedance 20 ohm) 50 ohm line Connect a 33 ohm series resistor at each of the output clocks to enhance the stability of the output signal Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/15/12 Page 2 PL123-05N/-09N Low Skew Fanout Buffer ABSOLUTE M AXIM UM CONDITIONS Supply Voltage to Ground Potential ...... –0.5V to 4.6V DC Input Voltage ............................ V SS – 0.5V to 4.6V Storage Temperature ..........................–65°C to 150°C Junction Temperature………………………….. 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015)…………..> 2000V OPERATING CONDITIONS Parameter Description Min. Max. Unit V DD Supply Voltage 1.62 3.63 V 0 70 C Industrial Operating Temperature (ambient te mperature) -40 85 C Load Capacitance, below 100 MHz, V DD > 2.25V ― 30 pF Load Capacitance, above 100 MHz , V DD > 2.25V ― 10 pF Load Capacitance, below 67MHz, 1.62V < V DD < 2.25V ― 15 pF Input Capacitance ― 7 pF Operating Frequency, Input=Output, V DD > 2.25V DC 134 MHz Operating Frequency, Input=Output, 1.62V < V DD < 2.25V DC 67 MHz Power-up time for all V DDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms TA CL C IN REF, CLK[1:9] t PU Commercial Operating Temperature (ambient temperature) Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/15/12 Page 3 PL123-05N/-09N Low Skew Fanout Buffer ELECTRICAL CHARACTERISTICS (Commercial and Industrial Temperature Devices) Parameter Description Test Conditions Min. Max. Unit VIL Input LOW Voltage [1] VDD > 2.25V – 0.8 V VIH Input HIGH Voltage VDD > 2.25V 2.0 – V IIL Input LOW Current VIN = 0V – 50 µA IIH Input HIGH Current VIN = VDD – 100 µA VOL Output LOW Voltage [2] IOL = 8 mA , VDD > 2.97V – 0.4 V VOH Output HIGH Voltage [2] IOH = –8 mA , VDD > 2.97V 2.4 – V IDD Supply Current 66.67MHz with unloaded outputs – 32 mA [1] SWITCHING CHARACTERISTICS (Commercial and Industrial Temperature Devices) [3 ] Parameter Description Duty Cycle [2] = t2 ÷ t1 t3 t4 Rise Time [2] Fall Time [2] Test Conditions Min. Typ. Max. Unit Measured at 1.4V, VDD=3.3V, Input=50% 40 50 60 % Measured at VDD/2 , Input = 50% 40 50 60 % 0.8V  2.0V , VDD=3.3V , 30pF Load – – 1.5 ns 10%  90% , VDD=2.5V , 15pF Load – – 2.5 ns 10%  90% , VDD=1.8V , 15pF Load – – 4.5 ns 2.0V  0.8V , VDD=3.3V , 30pF Load – – 1.5 ns 90%  10% , VDD=2.5V , 15pF Load – – 2.5 ns 90%  10% , VDD=1.8V , 15pF Load – – 4.5 ns t5 Output to Output Skew [2] All outputs equally loaded – – 250 ps t6 Propagation Delay, REF Rising Edge to CLKX Rising Edge [2] Measured at VDD/2 1 5 9.2 ns Notes: 1. REF input has a threshold voltage of V DD /2 2. Parameter is guaranteed by design and characterization. Not 100% tested in p roduction. 3. All parameters are specified with loaded outputs. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/15/12 Page 4 PL123-05N/-09N Low Skew Fanout Buffer NOISE CHARACTERISTICS (Commercial and Industrial Temperature Devices) Parameter Description Test Conditions Min. Additive Phase Jitter V DD=3.3V, Frequency=100MHz Offset=12KHz ~ 20MHz Typ. Max. Unit 60 fs 10000000 100000000 PL123-09N Additive Phase Jitter: VDD=3.3V, CLK=100MHz, Integration Range 12KHz to 20MHz: 0.059ps typical. REF Input PL123-09N Output 10000 100000 -60 -70 -80 Phase Noise (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 10 100 1000 1000000 Offset Frequency (Hz) When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive Phase Jitter is as follows: 2 Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter) 2 Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/15/12 Page 5 PL123-05N/-09N Low Skew Fanout Buffer SWITCHING WAVEFORMS Duty Cycle Timing t1 t2 1.4V All Outputs Rise/Fall Time 1.4V 2.0V 2.0V 0.8V OUTPUT 0.8V t3 3.3V V 0V t4 Output-Output Skew 1.4V OUTPUT 1.4V OUTPUT t5 Input-Output Propagation Delay VDD/2 INPUT VDD/2 OUTPUT t6 TEST CIRCUIT VDD 0.1 F OUTPUTS CL OAD VDD 0.1 F GND CLK GND Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/15/12 Page 6 PL123-05N/-09N Low Skew Fanout Buffer PACKAGE DRAWING (GREEN PACKAGE COM PLIANT) SOP-16L ( mm ) Symbol A A1 B C D E H L e Min. Max. 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 5.80 6.20 0.40 1.27 1.27 BSC E H D A A1 C L B e SOP-8L (mm) Symbol A A1 A2 B C D E H L e Min. Max. 1.35 1.75 0.10 0.25 1.25 1.50 0.33 0.53 0.19 0.27 4.80 5.00 3.80 4.00 5.80 6.20 0.40 0.89 1.27 BSC E H D A2 A A1 C e b L Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/15/12 Page 7 PL123-05N/-09N Low Skew Fanout Buffer ORDERING INFORMATION For part ordering, please contact our Sales Department: 2180 Fortune Drive, San Jose, CA 95131, USA Tel: (408) 944-0800 Fax: (408) 474-1000 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range PL123-0xN X X - X None=Tubes R=Tape & Reel Part Number Package Type S=SOP Temperature Range C=Commercial (0°C to 70°C) I=Industrial (-40°C to 85°C) Part/Order Number PL123-09NSC PL123-09NSC-R PL123-09NSI PL123-09NSI-R PL123-05NSC PL123-05NSC-R PL123-05NSI PL123-05NSI-R Marking Package Option Green (Lead-Free) Package P12309N 16-Pin SOP Tube SC 16-Pin SOP (Tape and Reel) LLLLL P12309N 16-Pin SOP Tube SI 16-Pin SOP (Tape and Reel) LLLLL P12305N 8-Pin SOP Tube SC 8-Pin SOP (Tape and Reel) LLLLL P12305N 8-Pin SOP Tube SI 8-Pin SOP (Tape and Reel) LLLLL *Note: LLLLL designates lot number Micrel Inc., reserves the right to make changes in its products or specifications, or both at any time without notice. The in formation furnished by Micrel is believed to be accurate and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: Micrel’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Micrel Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/15/12 Page 8