PL123E-05SC-R

(Preliminary) PL123E-05 Low Skew Zero Delay Buffer FEATURES DESCRIPTION     The PL123E-05 (-05H for High Drive) is a high performance, low skew, low jitter zero delay buffer d esigned to distribute high speed clocks. It has five low-skew outputs that are synchronized with the input. The sy nchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than 100ps, the device acts as a zero delay buffer. The input output propagation delay can be advanced or delayed by adjusting the load on the CLKOUT pin.   Frequency Range 10MHz to 220MHz Zero input - output delay. Low output-to-output skew. Optional Drive Strength: Standard (8mA) PL123E-05 High (12mA) PL123E-05H 2.5V or 3.3V, ±10% operation. Available in 8-pin SOP packaging. These parts are not intended for 5V input-tolerant applications. PIN CONFIGURATION REF 1 8 CLKOUT CLK2 2 7 CLK4 CLK1 3 6 VDD GND 4 5 CLK3 SOP-8L BLOCK DIAGRAM REF PLL CLKOUT CLK1 CLK2 CLK3 CLK4 Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 1 (Preliminary) PL123E-05 Low Skew Zero Delay Buffer PIN DESCRIPTION Name Package Type SOP-8L Type Description REF [1 ] 1 I Input reference frequency. CLK2 [2 ] 2 O Buffered clock output. CLK1 3 O Buffered clock output. GND 4 P Ground connection. CLK3 [2 ] 5 O Buffered clock output. VDD 6 P VDD connection. CLK4 [2 ] 7 O Buffered clock output. CLKOUT [2 ,3 ] 8 O Buffered clock output. Internal feed back on this pin. [2 ] Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output. INPUT / OUTPUT SKEW CONTROL The PL123E-05 will achieve Zero Delay from input to output when all the outputs are loaded equally. Adjus tments to the input/output delay can be made by adjusting the loading on the CLKOUT pin. Please contact Micrel for more information. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 2 (Preliminary) PL123E-05 Low Skew Zero Delay Buffer LAYOUT RECOMMENDATIONS The following guidelines are to assist y ou with a performance optimized PCB design: Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations - Keep traces short! - Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections ( looks like ringing ). - Design long traces as “striplines” or “microstrips” with defined impedance. - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1F for designs using frequencies < 50MHz and 0.01F for designs using frequencies > 50MHz. - Match trace at one side to avoid reflections bouncing back and forth. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer To CMOS Input ( Typical buffer impedance 20  50 line Connect a 33 series resistor at each of the output clocks to enhance the stability of the output signal Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 3 (Preliminary) PL123E-05 Low Skew Zero Delay Buffer Absolute Maximum Conditions Supply Voltage to Ground Potential ...... –0.5V to 4.6V DC Input Voltage............................. V SS – 0.5V to 4.6V Storage Temperature ......................... –65°C to 150°C Junction Temperature ....................................... 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015)………………> 2000V Operating Condition Description Parameter Min Max Unit Supply Voltage V DD 2.25 3.63 V Load Capacitance,