PL123S-05HSC-R

PL123S-05/-09 Spread-Compatible Low Skew Zero Delay Buffer FEATURES DESCRIPTION   The PL123S-05/-09 (-05H/-09H for High Drive) are high performance, low skew, low jitter zero delay buffers designed to distribute high speed clocks. They have one (PL123S-05) or two (PL123S-09) low-skew output banks, of 4 outputs each, that are synchronized with the input. The PL123S-09 allows control of the banks of outputs by using the S1 and S2 inputs as shown in the Selector Definition table on page 2.       Frequency Range 10MHz to 134 MHz Output Options: o 5 outputs PL123S-05 o 9 outputs PL123S-09 Zero input - output delay Optional Drive Strength: Standard (8mA) PL123S-05/-09 High (12mA) PL123S-05H/-09H 3.3V, ±10% operation Available in Commercial and Industrial temperature ranges Available in 16-Pin SOP or TSSOP (PL123S-09), and 8-Pin SOP (PL123S-05) packages Spread-compatible with spread-spectrum modulation clock inputs The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than 100ps, the device acts as a zero delay buffer. The input output propagation delay can be advanced or delayed by adjusting the load on the CLKOUT pin. These parts are not intended for 5V input-tolerant applications. BLOCK DIAGRAM Mux CLKOUT CLKA2 CLKA3 Bank A CLKA1 CLKA4 (PL123S-09 Only) CLKB2 CLKB3 CLKB4 Bank B S2 Selector Inputs 1 CLKA2 2 CLKA1 3 GND 4 8 CLKOUT 7 CLKA4 6 VDD 5 CLKA3 REF 1 16 CLKOUT CLKA1 2 15 CLKA4 CLKA2 3 14 CLKA3 13 VDD 12 GND PL123S-09 S1 CLKB1 REF PL123S-05 PLL REF VDD 4 GND 5 CLKB1 6 11 CLKB4 CLKB2 7 10 CLKB3 S2 8 9 S1 Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/14/11 Page 1 PL123S-05/-09 Spread-Compatible Low Skew Zero Delay Buffer PIN DESCRIPTIONS Name PL123S-09 PL123S-05 TSSOP-16L, SOP-16L SOP-8L REF [1 ] Type Description 1 1 I Input reference frequency [2 ] 2 3 O Buffered clock output, Bank A CLKA2 [2 ] 3 2 O Buffered clock output, Bank A VDD 4,13 6 P VDD connection GND 5,12 4 P GND connection CLKB1 [2 ] 6 - O Buffered clock output, Bank B CLKB2 [2 ] 7 - O Buffered clock output, Bank B S2 [3 ] 8 - I Selector input CLKA1 S1 [3 ] 9 - I Selector input [2 ] 10 - O Buffered clock output, Bank B CLKB4 [2 ] 11 - O Buffered clock output, Bank B CLKA3 [2 ] 14 5 O Buffered clock output, Bank A CLKA4 [2 ] 15 7 O CLKOUT [2 ] 16 8 O Buffered clock output, Bank A Buffered clock output. Internal feedback on this pin. CLKB3 Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2 SELECTOR DEFINITION FOR PL123S-09 S2 S1 CLOCK A1–A4 (Bank A) CLOCK B1–B4 (Bank B) CLKOUT Output Source PLL Shutdown 0 0 Three-state Three-state Driven PLL N 0 1 Driven Three-state Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N INPUT / OUTPUT SKEW CONTROL The PL123S-05/-09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjustments to the input/output delay can be made by adding additional loading to the CLKOUT pin. Please contact Micrel for more information. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/14/11 Page 2 PL123S-05/-09 Spread-Compatible Low Skew Zero Delay Buffer SPREAD COM PATIBLE Many products today utilize spread-spectrum modulation clocking to reduce electromagnetic interference (EMI) and pass FCC regulations. This product was designed to pass spread -spectrum input clock modulation frequencies to the output. When a buffer is not designed to pass spread spectrum, there will exist significant tracking ji tter between input and output clocks, which may result in problems with system timing and synchronization. LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a performance optimized PCB design: Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations - Keep traces short! - Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections ( looks like ringing ). - Design long traces as “striplines” or “microstrips” with defined impedance. - Match trace at one side to avoid reflections bounc ing back and forth. - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1F for designs using frequencies < 50MHz and 0.01F for designs using frequencies > 50MHz. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer To CMOS Input ( Typical buffer impedance 20  50 line Connect a 33 series resistor at each of the output clocks to enhance the stability of the output signal Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/14/11 Page 3 PL123S-05/-09 Spread-Compatible Low Skew Zero Delay Buffer ABSOLUTE M AXIM UM CONDITIONS Supply Voltage to Ground Potential ...... –0.5V to 4.6V DC Input Voltage ............................ V SS – 0.5V to 4.6V Storage Temperature ..........................–65°C to 150°C Junction Temperature………………………….. 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015)…………..> 2000V OPERATING CONDITIONS Parameter Description Min. Max. Unit V DD Supply Voltage 3.0 3.6 V 0 70 C Industrial Operating Temperature (ambient te mperature) -40 85 C Load Capacitance, below 100 MHz Load Capacitance, above 100 MHz Input Capacitance Power-up time for all V DDs to reach minimum specified voltage (power ramps must be monotonic) ― ― ― 30 10 7 pF pF pF 0.05 250 ms TA CL C IN t PU Commercial Operating Temperature (ambient temperature) ELECTRICAL CHARACTERISTICS Parameter Test Conditions Description Min. Max. Unit VIL Input LOW Voltage – 0.8 V VIH Input HIGH Voltage 2.5 – V IIL Input LOW Current VIN = 0V – 50 µA IIH Input HIGH Current – 100 µA VOL Output LOW Voltage[4] – 0.4 V VOH Output HIGH Voltage[4] 2.4 – V Supply Current (Unloaded Outputs) – 32 mA IDD VIN = VDD IOL = 8 mA IOL = 12 mA IOH = –8 mA IOL = –12 mA 66.67MHz with unloaded outputs Commercial Temp. 66.67MHz with unloaded outputs Industrial Temp. – 45 mA Notes: 4. Parameter is guaranteed by design and characterization. Not 100% tested in production . Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/14/11 Page 4 PL123S-05/-09 Spread-Compatible Low Skew Zero Delay Buffer SWITCHING CHARACTERISTICS Parameter Name t1 t3 t4 t5 t6A t6B [5 ] Test Conditions Min. Typ. Max. Unit 30-pF load 10 – 100 MHz 10-pF load 10 – 134 MHz Duty Cycle [4] = t2 ÷ t1 Measured at 1.4V, FOUT = 66.67MHz 40 50 60 % Duty Cycle Measured at 1.4V, FOUT