PL133-67OI-R

PL133-67 Low-Power DC to 150 MHz 1:6 Fanout Buffer IC Features General Description • 1:6 LVCMOS Output Fanout Buffer from DC to150 MHz • Low Additive Phase Jitter of 60 fs RMS • 8 mA Output Drive Strength • Low Power Consumption for Portable Applications • Low Input-Output Delay • Output-Output Skew 2000V Operating Ratings † Supply Voltage, VDD .................................................................................................................................. 1.71V to 3.63V † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Electrical Characteristics: Parameter Symbol Min. Typ. Max. Input Low Voltage VIL — — 0.3xVDD Input High Voltage VIH 0.7xVDD — Input Low Current IIL — — Input High Current IIH — — 100 µA VIN = VDD Supply Current IDD — — 32 mA 66.67 MHz with unloaded outputs — — 0.5 Output Low Voltage VOL — — 0.5 Output High Voltage OE Pin Pull-Up Resistance Load Capacitance VOH RPU CL Units Conditions V Note 1 — V Note 1 50 µA VIN = 0V IO = 8 mA, VDD = 3.3V V IO = 6 mA, VDD = 2.5V — — 0.5 IO = 4 mA, VDD = 1.8V VDD - 0.5 — — IO = –8 mA, VDD = 3.3V VDD - 0.5 — — VDD - 0.5 — — — 120 — V IO = –6 mA, VDD = 2.5V IO = –4 mA, VDD = 1.8V kΩ — — — 30 Load Capacitance, below 100 MHz, VDD > 2.25V — — 10 Load Capacitance between 100 MHz and 134 MHz, VDD > 2.25V — — 5 Load Capacitance, above 134 MHz, VDD > 2.25V — — 15 Load Capacitance, below 67 MHz, 1.71V < VDD < 2.25V pF Input Capacitance CIN — — 7 pF — Power-Up Time tPU 0.05 — 50 ms Power-up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) Note 1: REF input has a threshold voltage of VDD/2. DS20006671A-page 2  2022 Microchip Technology Inc. and its subsidiaries PL133-67 SWITCHING CHARACTERISTICS Note 2 Electrical Characteristics: Parameter Symbol Operating Frequency f Min. Typ. Max. Units Conditions DC — 150 MHz VDD = 3.3V, 2.5V DC — 67 MHz VDD = 1.8V Duty Cycle = t2 ÷ t1 — 40 50 60 % Measured at VDD/2, Input is 50% Rise Time t3 — — 1.5 ns Measured between 0.8V and 2.0V Fall Time t4 — — 1.5 ns Measured between 0.8V and 2.0V Output to Output Skew Note 1 t5 — — 250 ps All outputs equally loaded Propagation Delay, REF Rising Edge to CLKX Rising Edge Note 1 t6 1 5 9.2 ns Measured at VDD/2 Note 1: 2: Parameter is guaranteed by design and characterization. All parameters are specified with loaded outputs. NOISE CHARACTERISTICS Electrical Characteristics: Parameter Additive Phase Jitter Symbol Min. Typ. Max. — — 60 —  2022 Microchip Technology Inc. and its subsidiaries Units Conditions fs VDD = 3.3V, Frequency = 100 MHz Integration range 12 kHz - 20 MHz DS20006671A-page 3 PL133-67 TEMPERATURE SPECIFICATIONS (Note 1) Parameters Symbol Min. Typ. Max. Units Conditions TA –40 — +125 °C — Temperature Ranges Ambient Operating Temperature (T) Junction Temperature TJ — — +150 °C — Storage Temperature Range TS –65 — +150 °C — RθJA — 90 — °C/W — Package Thermal Resistance 16-Lead TSSOP Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above +150°C can impact the device reliability. DS20006671A-page 4  2022 Microchip Technology Inc. and its subsidiaries PL133-67 2.0 PIN DESCRIPTIONS FIGURE 2-1: Pin Configuration, 16-Lead TSSOP Package. The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number P8in Name Type Description 1 REF I Input reference frequency. 3 CLK0 O Buffered clock output. 6 CLK1 O Buffered clock output. 7 CLK2 O Buffered clock output. 10 CLK3 O Buffered clock output. 11 CLK4 O Buffered clock output. 14 CLK5 O Buffered clock output. 4, 13 VDD P VDD connection. 5, 9, 12 GND P GND connection. Output enable control input with 120 kΩ pull-up 8 OE I 2, 15, 16 DNC — Do not connect.  2022 Microchip Technology Inc. and its subsidiaries DS20006671A-page 5 PL133-67 3.0 Note: NOMINAL PERFORMANCE CHARACTERISTICS The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. U REF Input PL133-67 Output 10000 100000 -60 -70 -80 Phase Noise (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 10 100 1000 1000000 10000000 100000000 Offset Frequency (Hz) FIGURE 3-1: PL133-67 Additive Phase Jitter: VDD = 3.3V, CLK-100 MHz, Integration Range 12 kHz - 20 MHz, 0.059 ps Typical. When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the buffer will be a little bit more than the phase noise in the input signal. The noise added by the buffer to the input signal is quantified by the additive phase jitter defined by the following formula: EQUATION 3-1: AdditivePhaseJitter = DS20006671A-page 6 2  OutputPhaseJitter  –  InputPhaseJitter  2  2022 Microchip Technology Inc. and its subsidiaries PL133-67 4.0 SWITCHING WAVEFORMS t1 t2 VDD/2 VDD/2 FIGURE 4-1: Duty Cycle Timing. 2.0V 2.0V 0.8V OUTPUT 0.8V t3 FIGURE 4-2: 3.3V 0V t4 All Outputs rise/Fall Time. VDD/2 OUTPUT VDD/2 OUTPUT FIGURE 4-3: t5 Output to Output Skew. VDD/2 INPUT VDD/2 OUTPUT FIGURE 4-4: t6 Input-Output Propagation Delay.  2022 Microchip Technology Inc. and its subsidiaries DS20006671A-page 7 PL133-67 5.0 TEST CIRCUIT VDD 0.1 PF OUTPUTS CL OAD VDD 0.1 PF FIGURE 5-1: DS20006671A-page 8 GND CLK GND Test Circuit.  2022 Microchip Technology Inc. and its subsidiaries PL133-67 6.0 LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a performance optimized PCB design: 6.1 Signal Integrity and Termination Considerations - Keep traces short - Trace = Inductor. With a capacitive load this equals ringing - Long trace = Transmission Line. Without proper termination this will cause reflections ringing and waveforms degradations. - Use stripline or microstrip with defined impedance for long traces (> 1 inch) - Match traces on one side of the board to avoid reflections bouncing back and forth. 6.2 Decoupling and Power Supply Considerations - Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1 µF for designs using frequencies 50 MHz Place Series Resistor as close as possible to CMOS output CMOS Output Buffer To CMOS Input ( Typical buffer impedance 20 ohm) 50 ohm line Connect a 33 ohm series resistor at each of the output clocks to enhance the stability of the output signal FIGURE 6-1: Typical CMOS Termination.  2022 Microchip Technology Inc. and its subsidiaries DS20006671A-page 9 PL133-67 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 16-Lead TSSOP* XXXXXXX XX WWNNN Legend: XX...X Y YY WW NNN e3 * Example P133-67 OC 10114 Product code, customer-specific information, or frequency in MHz without printed decimal point Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. ●, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle mark). Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. Underbar (_) and/or Overbar (‾) symbol may not be to scale. DS20006671A-page 10  2022 Microchip Technology Inc. and its subsidiaries PL133-67 16-Lead TSSOP Package Outline and Recommended Land Pattern Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.  2022 Microchip Technology Inc. and its subsidiaries DS20006671A-page 11 PL133-67 NOTES: DS20006671A-page 12  2022 Microchip Technology Inc. and its subsidiaries PL133-67 APPENDIX A: REVISION HISTORY Revision A (April 2022) • Converted Micrel document PL133-67 to Microchip data sheet DS20006671A. • Minor text changes throughout.  2022 Microchip Technology Inc. and its subsidiaries DS20006671A-page 13 PL133-67 NOTES: DS20006671A-page 14  2022 Microchip Technology Inc. and its subsidiaries PL133-67 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. PART NO. X X X Device Package Temperature Range Media Type Device: PL133-67: Package: O = 16-Lead TSSOP Package Temperature Range: C I = = 0°C to +70°C (Commercial) –40°C to +85°C (Industrial) Media Type: (blank) = Low-Power DC to 150 MHz 1:6 Fanout Buffer IC 96/Tube  2022 Microchip Technology Inc. and its subsidiaries Examples: a) PL133-67OC Low-Power DC to 150 MHz 1:6 Fanout Buffer IC, TSSOP Package, 0°C to +70°C, 96/Tube b) PL133-67OI Low-Power DC to 150 MHz 1:6 Fanout Buffer IC, TSSOP Package, –40°C to +125°C, 96/Tube Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. DS20006671A-page 15 PL133-67 NOTES: DS20006671A-page 16  2022 Microchip Technology Inc. and its subsidiaries Note the following details of the code protection feature on Microchip products: • Microchip products meet the specifications contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions. • Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products. This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at https:// www.microchip.com/en-us/support/design-help/client-supportservices. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". 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