PL135-27
Low Power, 1.62V to 3.63V, 10MHz to
40MHz, 1:2 Oscillator Fanout Buffer
Revision 2.0
General Description
Features
The PL135-27 is an advanced oscillator fanout buffer
design for high performance, low-power, small form-factor
applications. The PL135-27 accepts a fundamental crystal
input of 10MHz to 40MHz and produces two LVCMOS
outputs of the same frequency. The PL135-27 is designed
to fit in a small 2mm × 1.3mm DFN package and offers the
best phase noise, jitter performance and lowest power
consumption of any comparable IC.
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Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
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Advanced oscillator design for wide frequency coverage
Two LVCMOS outputs
8mA output drive strength
Input/output frequency: 10MHz to 40MHz fundamental
crystal
Very low jitter and phase noise
Low current consumption
Single 1.62V to 3.63V power supply
Available in 2.0mm × 1.3mm DFN-6L, GREEN/RoHScompliant package
Block Diagram
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
September 8, 2014
Revision 2.0
tcghelp@micrel.com or (408) 955-1690
Micrel, Inc.
PL135-27
Ordering Information
Part Number
(1)
Ambient Temperature Range
PL135-27GC-R
0°C to +70°C
PL135-27GI-R
-40°C to +85°C
Marking
J27
LLL
Package
6-Pin 2.0mm × 1.3mm DFN
Note:
1. LLL designates lot number.
Pin Configuration
6-Lead DFN
Pin Description
Pin Number
DFN-6L
Pin Name
Type
1
XIN
I
Crystal input
2
CLK1
O
Clock output
3
GND
P
GND connection
4
CLK0
O
Clock output
5
VDD
P
VDD connection
6
XOUT
O
Crystal output
September 8, 2014
Pin Description
2
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PL135-27
Absolute Maximum Ratings(2)
Operating Ratings(3)
Supply Voltage (VDD) .................................... –0.5V to +4.6V
Output Voltage (VOUT) ............................ –0.5V to VDD+0.5V
Storage Temperature (TS) ......................... –65°C to +150°C
Supply Voltage (VDD) ................................ +1.62V to +3.63V
Ambient Temperature (TA) .......................... –40°C to +85°C
AC Electrical Characteristics
VDD = 1.8V ±10%, 2.5V ±10% or 3.3V ±10%; CL = 15pF; TA = -40°C to +85°C, unless otherwise noted
Symbol
Parameter
Condition
FX
Crystal Input Frequency
Fundamental crystal
tSETTLE
Settling Time
At Power-Up (VDD > 1.62V)
dF/dVDD
VDD Sensitivity
Frequency vs. VDD, ±10%
tR
Output Rise Time
10/90% VDD, VDD=3.3V
tF
Output Fall Time
90/10% VDD, VDD=3.3V
tSKEW
Output to Output Skew
D-C
Duty Cycle
Min.
Typ.
Max.
Units
40
MHz
2
ms
0.5
ppm
2
3
ns
2
3
ns
10
-0.5
45
500
ps
50
55
%
Typ.
Max.
Units
Notes:
2. Exceeding the absolute maximum ratings may damage the device.
3. The device is not guaranteed to function outside its operating ratings.
DC Electrical Characteristics
VDD = 1.8V ±10%, 2.5V ±10% or 3.3V ±10%; CL = 15pF; TA = -40°C to +85°C, unless otherwise noted
Symbol
IDD
Parameter
Supply Current, Dynamic
Condition
Min.
VDD = 3.3V, 25MHz, No Load
1.6
mA
VDD = 2.5V, 25MHz, No Load
1.2
mA
VDD = 1.8V, 25MHz, No Load
0.9
mA
VDD
Operating Voltage
1.62
VOL
Output Low Voltage
IOL = +4mA, 3.3V
VOH
Output High Voltage
IOH = -4mA, 3.3V
IOSD
Output Current
VOL = 0.4V, VOH = 2.4V
3.63
V
0.4
V
2.4
V
8
mA
Crystal Specifications
VDD = 1.8V ±10%, 2.5V ±10% or 3.3V ±10%; CL = 15pF; TA = -40°C to +85°C, unless otherwise noted
Symbol
Parameter
FXIN
Fundamental Crystal
Resonator Frequency
CL(xtal)
Crystal Loading Rating
12
PD
Operating Drive Level
0.1
C0
Shunt Capacitance
ESR
Effective Series Resistance
September 8, 2014
Condition
Min.
Typ.
10
Max.
Units
40
MHz
pF
2
mW
5.5
pF
C0 ≤ 5.5pF
40
Ω
C0 ≤ 2.5pF
60
Ω
3
Revision 2.0
tcghelp@micrel.com or (408) 955-1690
Micrel, Inc.
PL135-27
Layout Recommendations
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
Decoupling and Power Supply Considerations
• Keep traces short.
• Trace = Inductor. With a capacitive load this equals
ringing.
• Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like ringing).
• Design long traces as “striplines” or “microstrips” with
defined impedance.
• Match trace at one side to avoid reflections bouncing
back and forth.
• Place decoupling capacitors as close as possible to the
VDD pin(s) to limit noise from the power supply
• Multiple VDD pins should be decoupled separately for
best performance.
• Addition of a ferrite bead in series with VDD can help
prevent noise from other board sources
• Value of decoupling capacitor is frequency dependent.
Typical value to use is 0.1µF.
September 8, 2014
4
Revision 2.0
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Micrel, Inc.
PL135-27
Package Information(4)
6-Lead DFN
Note:
4. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high performance linear and power, LAN, and timing & communications
markets. The Company’s products include advanced mixed-signal, analog & power semiconductors; high-performance communication, clock
management, MEMs-based clock oscillators & crystal-less clock generators, Ethernet switches, and physical layer transceiver ICs. Company
customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and computer products.
Corporation headquarters and state-of-the-art wafer fabrication facilities are located in San Jose, CA, with regional sales and support offices and
advanced technology design centers situated throughout the Americas, Europe, and Asia. Additionally, the Company maintains an extensive network
of distributors and reps worldwide.
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this datasheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
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