PL138-58
2.5V-3.3V Low-Skew 1-4 PECL Fanout Buffer
FEATURES
DESCRIPTION
Four differential 2.5V/3.3V LVPECL output pairs.
Output Frequency: ≤ 266 MHz.
Selectable CLK0 or CLK1 inputs for redundant and
multiple frequency fanout applications
Translates single-ended LVCMOS or LVTTL input to
3.3V or 2.5V LVPECL differential outputs.
Output Skew: 25ps (typ).
Part-to-part skew: 85ps (typ).
Propagation delay: 0.7ns (typ).
Additive Jitter: 50 fs (typ).
Operating Supply Voltage: 2.375V ~ 3.63V.
Operating temperature range from -40C to 85C.
Package availability: 16-pin QFN and 20-pin TSSOP
The PL138-58 is a high performance low-cost 1: 4 outputs
Differential LVPECL fanout buffer, with very low-skew and
LVCMOS/LVTTL input interface for 3.3V and 2.5V operations.
BLOCK DIAGRAM
D
Q0B
CLKSEL
3
18
VCC
CLK0
4
17
Q1
DNC
5
16
Q1B
CLK1
6
15
Q2
DNC
7
14
Q2B
Q0
DNC
8
13
VCC
QB0
DNC
9
12
Q3
VCC
10
11
Q3B
Q1
20-Pin TSSOP Package
QB2
^: Denotes Pull Up Resistor
Resistor
16
15
14
13
Q3
CLKSEL
1
12
Q1
QB
CLK0
2
11
Q1B
CLK1
3
10
Q2
VEE
4
9
Q2B
PL138-58
5
6
7
8
VCC
: Denotes Pull Down
VCC
QB1
Q2
V
PL138-58
Q0B
CLKSELV
Q0
19
Q0
1
20
2
Q3
CLK1
0
1
CLK-EN
CLK-EN
CLK0
VEE
Q3B
LE
Q
Designed to fit in a small form-factor package, PL138
family offers very low-power consumption, and the
lowest additive jitter of any comparable device.
DNC
CLK-EN^
PL138-58’s two single-ended clock inputs are designed to
accept a standard LVCMOS or LVTTL signal levels and
produce a high quality set of 2.5V or 3.3V LVPECL outputs
with the lowest possible skew, guaranteed for part-to-part or
lot-to lot. The clock enable is internally synchronized to assure
no runt clock pulses on the output during asynchronous
assertion/deassertion of the clock enable pin.
16-Pin QFN Package
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/3/13 Page 1
PL138-58
2.5V-3.3V Low-Skew 1-4 PECL Fanout Buffer
PIN DESCRIPTIONS
Package Pin #
TSSOP-20
QFN-16
Name
Vcc
Type
Description
8, 13
10, 13, 18
P
Power Supply pin connection
QB0 ~ QB3
6, 9, 11, 14
11, 14, 16, 19
O
LVPECL Complementary output
Q0 ~ Q3
7, 10, 12, 15
12, 15, 17, 20
O
LVPECL True output
VEE
4
1
P
CLK-EN
16
2
I
CLK-SEL
1
3
I
CLK0
2
4
I
Power Supply pin connection
Synchronizing clock enable.
When HIGH, clock outputs follow clock input. When LOW, Q
outputs are forced low, QB outputs are forced high.
LVCMOS / LVTTL interface levels.
50k Internal Pull-Up Resistor.
Clock select input. When HIGH, selects CLK1 input. When
LOW, selects CLK0 input.
LVCMOS / LVTTL interface levels.
50k Internal Pull-Down Resistor.
LVCMOS, LVTTL Clock input.
DNC
5
5, 7, 8, 9
-
Do Not Connect.
CLK1
3
6
I
LVCMOS, LVTTL Clock input.
INPUT CLOCK CONTROL FUNCTION
Inputs
Outputs
CLK-EN
CLKSEL
Source
Q0:Q3
Q0B:Q3B
0
0
CLK0
Disabled Low
Disabled High
0
1
CLK1
Disabled Low
Disabled High
1
0
CLK0
Enabled
Enabled
1
1
CLK1
Enabled
Enabled
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/3/13 Page 2
PL138-58
2.5V-3.3V Low-Skew 1-4 PECL Fanout Buffer
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
PARAMETERS
SYMBOL
Supply Voltage
MIN.
V DD
MAX.
UNITS
4.6
V
Input Voltage, dc
VI
-0.5
V DD +0.5
V
Output Voltage, dc
VO
-0.5
V DD +0.5
V
Storage Temperature
TS
-65
150
C
Ambient Operating Temperature*
TA
-40
85
C
Junction Temperature
TJ
110
C
260
C
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product
reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this
specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
DC CHARACTERISTICS, VCC = 3.3V ±10%; VEE = 0V; T A= -40ºC TO +85ºC
PARAMETER
Output High Voltage*
Output Low Voltage*
Input High Voltage†
Input Low Voltage†
Input High Current
Input Low Current
SYMBOL
VOH
VOL
VIH
VIL
IIH
IIL
MIN
-40°C
TYP
2.215 2.320
1.470 1.610
0.7VCC
-0.3
MAX
MIN
2.420
1.745
VCC+0.3
0.3VCC
200
2.275
1.490
0.7VCC
-0.3
-150
25°C
TYP
2.350
1.585
MAX
2.420
1.680
VCC+0.3
0.3VCC
200
-150
MIN
80°C
TYP
MAX
2.275 2.35
2.420
1.490 1.585 1.680
0.7VCC
VCC+0.3
-0.3
0.3VCC
200
-150
UNITS
V
V
V
V
µA
µA
DC CHARACTERISTICS, VCC = 2.5V ±5%; VEE = 0V; T A= -40ºC TO +85ºC
PARAMETER
Output High Voltage*
Output Low Voltage*
Input High Voltage†
Input Low Voltage†
Input High Current
Input Low Current
SYMBOL
MIN
-40°C
TYP
MAX
MIN
25°C
TYP
MAX
VOH
1.415 1.520
1.620
1.475 1.550
1.620
VOL
0.670 0.810
0.945
0.690 0.785
0.880
VIH
0.7VCC
VCC+0.3 0.7VCC
VCC+0.3
0.3VCC
VIL
-0.3
0.3VCC
-0.3
IIH
150
150
IIL
-120
-120
.
Input and output parameters vary 1:1 with VCC VEE can vary +0.925V to -0.5V.
Input parameters vary with the ratio of VI : (VCC - VEE)
* Outputs terminated with 50 Ω to V CCO – 2V.
†
VIH/VIL apply to CLK0, CLK1, CLKEN, CLKSEL.
MIN
80°C
TYP
MAX
1.475 1.55
1.620
0.690 0.785 0.880
0.7VCC
VCC+0.3
-0.3
0.3VCC
150
-120
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/3/13 Page 3
UNITS
V
V
V
V
µA
µA
PL138-58
2.5V-3.3V Low-Skew 1-4 PECL Fanout Buffer
AC Electrical Characteristics
VCC =
-3.8V to -2.375V or, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
PARAMETER
SYMBOL
Output Frequency
fMAX
Propagation Delay*
tPD
MIN
-40°C
TYP
MAX
MIN
25°C
TYP
266
570
700
800
MAX
MIN
80°C
TYP
266
610
740
840
650
MAX
UNITS
266
MHz
810
940
ps
Output Skew ** †
tsk(o)
25
37
25
37
25
37
ps
Part-to-Part Skew *** †
tsk(pp)
85
225
85
225
85
225
ps
100
fs
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
tAPJ
100
100
Output Rise/Fall
20% to 80%
tR / tF
300
300
300
ps
Time
All parameters are measured at f ≤ 266MHz, unless otherwise noted.
* Measured from the differential input crossing point to the differential output crossing point.
** Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross
points.
*** Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs
on each device, the outputs are measured at the differential cross points.
†This parameter is defined in accordance with JEDEC Standard 65.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/3/13 Page 4
PL138-58
2.5V-3.3V Low-Skew 1-4 PECL Fanout Buffer
NOISE CHARACTERISTICS (Commercial and Industrial Temperature Devices)
Parameter
Description
Test Conditions
tAPJ
Additive Phase Jitter
Typ.
Max.
Unit
V DD=3.3V, Frequency=156.25MHz
Offset=12KHz ~ 20MHz
50
100
fs
V DD=3.3V, Frequency=25MHz
Offset=1KHz ~ 1MHz
50
100
fs
REF Input
Min.
PL138-58 Output
-60
Carrier = 156.25MHz
-70
-80
Phase Noise (dBc/Hz)
-90
-100
-110
-120
-130
-140
-150
-160
10
100
1000
10000
100000
1000000
10000000
100000000
Offset Frequency (Hz)
When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the
buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the
Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive
Phase Jitter is as follows:
2
Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter)
2
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/3/13 Page 5
PL138-58
2.5V-3.3V Low-Skew 1-4 PECL Fanout Buffer
PARAMETER MEASUREMENT INFORMATION
Output W aveform Test Circuit:
Differential Input Level:
+2.0V
VCC
OSCILLOSCOPE
VCC
50
Channel
50 Line
LVPECL
CLK-INxB
Cross Points
V PP
CLK-INx
50
Channel
50 Line
VEE
V CMR
VEE
-1.80V to -0.375V
Part-to-Part Skew:
Output Skew:
QBx
QBx
Part 1
Qx
Qx
QBy
QBy
Part 2
Qy
Qy
tsk(o)
tsk(pp)
Output Rise/Fall Time:
Qx
80%
Propagation Delay:
CLK-INxB
80%
CLK-INx
QBx
20%
20%
tR
QBy
tF
Qy
t PD
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/3/13 Page 6
PL138-58
2.5V-3.3V Low-Skew 1-4 PECL Fanout Buffer
TERMINATION FOR LVPECL OUTPUTS
The required termination for LVPECL is 50 to a V CC -2V DC voltage level. Below are two schematics to implement
this termination.
LVPECL Termination Schematic #1:
VCC
LVPECL Termination Schematic #2:
VCC
R1
VCC
R1
50 Line
Target
LVPECL
Input
PL138
Qx Buffer
50 Line
R2
R2
50 Line
Target
LVPECL
Input
PL138
Qx Buffer
50 Line
50
50
RT
VCC=3.3V, Ideal values: R1=127 , R2=82.5
Commercial values (E24): R1=130 , R2=82
VCC=2.5V, Ideal values: R1=250 , R2=62.5
Commercial values (E24): R1=240 , R2=62
Schematic #2 is an alternative simplified termination.
VCC=3.3V, Ideal value: RT=48.7
Commercial value: RT=50 (E24: 51 )
VCC=2.5V, Ideal value: RT=18.7
Commercial value: RT=18
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/3/13 Page 7
PL138-58
2.5V-3.3V Low-Skew 1-4 PECL Fanout Buffer
POWER CONSIDERATIONS
Driving LVPECL outputs requires an amount of power that can warm up the chip significantly.
The general requirement for the chip is that the junction temperature should not exceed +110°C.
The power consumption can be divided into two parts:
1) Core power dissipation
2) Output buffers power dissipation
CORE POWER DISSIPATION
The chip core power is equal to VCC×IEE. With a worst case VCC and IEE the power dissipation in the core is
3.63V×65mA=236mW.
OUTPUT BUFFER POWER DISSIPATION
The output buffers are not exposed to the full VCC-VEE voltage. On the differential output, one line is at logic 1
with a small voltage across the buffer and a large output current. The other line is at logic 0 with a larger voltage
across the buffer and a smaller output current. The power dissipation per ou tput buffer is 32mW. Only buffers that
are loaded will have power dissipation. With all 4 buffers loaded the worst case output buffer power dissipation will
be 128mW.
Total Chip Power Dissipation, worst case, is 236mW + 128mW = 364mW.
JUNCTION TEMPERATURE
How much the chip is warmed up from the power dissipation depends upon the thermal resistance from the chip to
the environment, also known as “junction to ambient”. The thermal resistance depends upon the type of package,
how the package is assembled to the PCB and if there is additional air flow for improved cooling. For the LQFP
package with use of the Thermal Relief pad, the thermal resistance is as follows:
TSSOP 20-pin Package
JEDEC Standard Multi Layer PCB
Air Flow Velocity in Linear Feet per Minute
0
200
500
θ JA = 73°C/W
θ JA = 67°C/W
θ JA = 64°C/W
The temperature of the chip (junction) will be higher than the environment (ambient) with an amount equal to θ JA ×
Power. For an ambient temperature of +70°C, all outputs loaded and no air flow, the junction temperature T J =
70°C+73×0.364 = 97°C.
QFN 16-pin Package
JEDEC Standard Multi Layer PCB
Air Flow Velocity in Linear Feet per Minute
0
200
500
θ JA = 60°C/W
θ JA = 53°C/W
θ JA = 46°C/W
The temperature of the chip (junction) will be higher than the environment (ambient) with an amount equal to θ JA ×
Power. For an ambient temperature of +85°C, all outputs loaded and no air flow, the junction temperature T J =
85°C+60×0.364 = 107°C.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/3/13 Page 8
PL138-58
2.5V-3.3V Low-Skew 1-4 PECL Fanout Buffer
PACKAGE DRAWING (GREEN PACKAGE COMPLIANT)
QFN 16L 3.0 X 3.5 mm
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/3/13 Page 9
PL138-58
2.5V-3.3V Low-Skew 1-4 PECL Fanout Buffer
TSSOP173 20L
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/3/13 Page 10
PL138-58
2.5V-3.3V Low-Skew 1-4 PECL Fanout Buffer
ORDERING INFORMATION (GREEN PACKAGE)
For part ordering, please contact our Sales Department:
2180 Fortune Drive, San Jose, CA 95131, USA
Tel: (408) 944-0800 Fax: (408) 474-1000
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
PL138-58 X X - R
Part Number
R=Tape and Reel
Package Type
Q=QFN
O=TSSOP
Part/Order Number
PL138-58QC
PL138-58QI
PL138-58OC
Temperature Range
C= Commercial (0°C to +70°C)
I= Industrial (-40°C to +85°C)
Marking
P138
58
LLLLL
P138
58I
LLLLL
P138-58
OC
LLLLL
Package Option
16-Pin QFN
16-Pin QFN
20-Pin TSSOP (Tube)
*Note: LLLLL designates lot number
Micrel Inc., reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Micrel is believed to be accurate
and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever
nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: Micrel’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the
President of Micrel Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/3/13 Page 11
