PL502-35OI-R

PL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise ICs FEATURES 1 XIN 2 XOUT 3 SEL3^ 4 SEL2^ 5 OE 6 VCON 7 GND 8 9 SEL[3:0] XOUT VDD CLKT GND GND VDD / GND* SEL0^ / VDD* SEL1^ 12 11 10 9 13 8 GND SEL3^ 14 7 CLKC SEL2^ 15 6 VDD OE 16 5 CLKT 2 3 4 GND VCON 1 GND PL502-3x QFN-16L OE XIN CLKC XOUT PL502-38 PLL (Phase Locked Loop) GND Internal pull-up On 3x3 package, PL502-35/-38 do not have SEL0 available: Pin 10 is VDD, pin 11 is GND. However, PL502 -37/-39 have SEL0 (pin 10), and pin11 is VDD. See pin assignment table for details. Part # Oscillator Amplifier w/ integrated varicaps SEL1^ OUTPUT ENABLE LOGICAL LEVELS BLOCK DIAGRAM VCON SEL0^ TSSOP-16L ^: *: DESCRIPTION The PL502-35 (LVPECL with inverted OE), PL502-37 (LVCMOS), PL502-38 (LVPECL), and PL502-39 (LVDS) are high performance and low phase noise VCXO IC chips. They provide phase noise performance as low as –125dBc at 10kHz offset (at 155MHz), by multiplying the input crystal frequency up to 32x. The wide pull range (±200 ppm) and very low jitter make them ideal for a wide range of applications, including SONET/SDH and FEC. They accept fundamental parallel resonant mode crystals from 12MHz to 25MHz. 1 6 1 5 1 4 1 3 1 2 1 1 1 0 GND        VDD PL 502-3x  Selectable 750kHz to 800MHz range Low phase noise output (@ 10kHz frequency offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for 155.52MHz, -115dBc/Hz for 622.08MHz) LVCMOS (PL502-37), LVPECL (PL502-35 and PL502-38) or LVDS (PL502-39) output 12MHz to 25MHz crystal input No external load capacitor or varicap required. Output Enable selector Wide pull range (±200 ppm) Selectable /16 to x32 frequency divider/multiplier 3.3V operation Available in 16-Pin TSSOP or 16-pin 3x3mm QFN GREEN/RoHS compliant packages XIN   PIN CONFIGURATION (Top View) CLKC CLKT PL502-35 PL502-37 PL502-39 OE 0 (Default) State Output enabled 1 Tri-state 0 Tri-state 1 (Default) Output enabled OE input: Logical states defined by LVPECL levels for PL502-38 Logical states defined by LVCMOS levels for PL502-37/-39 PLL by-pass PL502-3x Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/15/13 Page 1 PL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise ICs FREQUENCY SELECTION TABLE SEL3 SEL2 SEL1 SEL0 Selected Multiplier 0 0 1 1 Fin x 32 0 1 1 0 Fin / 8 0 1 1 1 Fin x 2 1 0 0 1 Fin / 2 1 0 1 0 Fin / 16 1 0 1 1 Fin x 4 1 1 0 0 Fin / 4 1 1 0 1 Fin x 8 1 1 1 0 Fin x 16 1 1 1 1 No multiplication Note: SEL0 is not available (always “1”) for PL502-35 and PL502-38 in 3x3mm package PIN DESCRIPTIONS PL502-35 and PL502-38 (see next page for PL502-37/-39) TSSOP Pin number 3x3mm QFN Pin number Type XIN 2 12 I Crystal input (See Crystal Specification on page 4) XOUT 3 13 I Crystal output (See Crystal Specification on page 4) OE 6 16 I Output enable pin (See OE logic state table on page 1) VCON 7 1 I Voltage Control input GND 8,9,10,14 2,3,4,8,11 P Ground connection CLKT 11 5 O LVPECL True output CLKC 13 7 O LVPECL Complementary output SEL0 16 Not available I SEL1 15 9 I SEL2 5 15 I SEL3 4 14 I VDD 1, 12 6,10 P Name Description Multiplier selector pins. These pins have an internal pull up that will default SEL to ‘1’ when not connected to GND. +3.3V power supply. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/15/13 Page 2 PL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise ICs PIN DESCRIPTIONS PL502-37/-39 (see previous page for PL502-35/-38) Name TSSOP Pin number 3x3mm QFN Pin number Type XIN 2 12 I Crystal input. See Crystal Specification on page 4. XOUT 3 13 I Crystal output. See Crystal Specification on page 4. OE 6 16 I Output enable pin (see OE logic state table on page 1). VCON 7 1 I Voltage Control input. GND 8,9,10,14 2,3,4,8 P Ground. CLKT 11 5 O LVDS True output for PL502-39 No Connect for PL502-37 CLKC 13 7 O LVDS Complementary output for PL502-39 LVCMOS out for PL502-37 SEL0 16 10 I SEL1 15 9 I SEL2 5 15 I SEL3 4 14 I VDD 1, 12 6,11 P Description Multiplier selector pins. These pins have an internal pull up that will default SELx to ‘1’ when not connected to GND. +3.3V power supply. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage SYMBOL MIN. V DD MAX. UNITS 4.6 V Input Voltage, dc VI -0.5 V DD +0.5 V Output Voltage, dc VO -0.5 V DD +0.5 V Storage Temperature TS -65 150 C Ambient Operating Temperature* TA -40 85 C Junction Temperature TJ 125 C Lead Temperature (soldering, 10s) 260 C ESD Protection, Human Body Model 2.5 kV Exposure of the device under conditions beyond the limits specified by Maximum R atings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the dev ice at these or any other conditions above the operational limits not ed in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade on ly. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/15/13 Page 3 PL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise ICs 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating SYMBOL CONDITIONS MIN. F XIN Parallel Fundamental Mode 12 C L (xtal) Crystal Pullability Recommended ESR At VCON = 1.65V TYP. MAX. UNITS 25 MHz 9.5 pF C 0 /C 1 (xtal) AT cut 250 - RE AT cut 30 Ω Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the cr ystal will be at nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additiona l load must be added externally. This however may reduce the pull range. 3. Voltage Control Crystal Oscillator PARAMETERS SYMBOL VCXO Stabilization Time * T VCXOSTB CONDITIONS MIN. TYP. From power valid VCXO Tuning Range F XIN = 12 – 25MHz; XTAL C 0 /C 1 < 250 0V  VCON  3.3V CLK output pullability VCON=1.65V, 1.65V MAX. UNITS 10 ms 500 ppm 200 VCXO Tuning Characteristic ppm 150 Pull range linearity ppm/V 10 VCON pin input impedance 0V  VCON  3.3V, -3dB VCON modulation BW % 2000 kΩ 10 kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS Supply Current, Dynamic (with Loaded Outputs) I DD F OUT