PL520-00DC

PL520-00 Low Phase Noise VCXO with multipliers (for 100 -200MHz Fund Xtal) FEATURES OUTSEL0^ VDD VDD VDD VDD SEL0^ SEL1^ OUTSEL1^ 24 23 22 21 20 19 18 Die ID: A1919-19A XOUT 27 SEL3^ 28 SEL2^ 29 OE CTRL 30 VCON 31 C502A 17 GNDBUF 16 CMOS 15 LVDSB 14 PECLB 13 12 VDDBUF VDDBUF 11 PECL 10 LVDS 5 6 X 7 OE_SEL^ 8 GNDBUF 4 GND 3 NC (0,0) 2 GND Y (1550,1475) 9 1 GND PL520-00 is a VCXO IC specifically designed to pull high frequency fundamental crystals. Its design was optimized to tolerate higher limits of interelectrodes capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input. 25 26 GND DESCRIPTION XIN GND      65 mil GND  100MHz to 200MHz Fundamental Mode Crystal. Output range: 100 – 200MHz (no multiplication), 200 – 400MHz (2x multiplier), 400 – 700MHz (4x multiplier), or 800MHz – 1GHz (LVDS output only for 8x multiplier). Available outputs: PECL, LVDS, or CMOS (High Drive (30mA) or Standard Drive (10mA) output). Selectable OE Logic (enable high or enable low). Integrated variable capacitors. Supports 3.3V-Power Supply. Available in die form. Thickness 10 mil. 62 mil   DIE CONFIGURATION Note: ^ deno tes internal pull up OUTPUT SELECTION AND ENABLE BLOCK DIAGRAM SEL OE VCON Oscillator XIN XOUT Amplifier w/ integrated varicaps PLL (Phase Locked Loop) Q Q OUTSEL1 (Pad #18) 0 0 1 1 OE_SELECT (Pad #9) 0 PLL by-pass PL520-00 DIE SPECIFICATIONS Name Size Reverse side Pad dimensions Thickness Value 65 x 62 m il GND 80 m icron x 80 micron 10 m il 1 (Default) OUTSEL0 (Pad #25) 0 1 0 1 OE_CTRL (Pad #30) 0 1 (Default) 0 (Default) 1 Selected Output High Drive CMOS Standard CMOS LVDS PECL (default) State Tri-state Output enabled Output enabled Tri-state Pad # 9, 18, 25: Bond to GND to set to “0”. No connection results to “default” setting through internal pull-up. Pad # 30: Logical states defined by PECL levels if OE_SELECT ( pad # 9) is “1” Logical states defined by CMOS levels if OE_SELECT is “0 Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/20/04 Page 1 PL520-00 Low Phase Noise VCXO with multipliers (for 100 -200MHz Fund Xtal) FREQUENCY SELECTION TABLE Pad #28 SEL3 0 Pad #29 SEL2 0 Pad #19 SEL1 1 Pad #20 SEL0 1 Fin x 8 (LVDS ouputs only) 1 1 0 1 1 1 1 0 Fin x 4 Fin x 2 1 1 1 1 No multiplication (no PLL) Selected Multiplier All pads have internal pull-ups (default value is 1). Bond to GND to set to 0. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. VDD VI VO TS TA TJ -0.5 -0.5 -65 -40 Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model MAX. UNITS 4.6 VDD +0.5 VDD +0.5 150 85 125 260 2 V V V C C C C kV Exposure of the devic e under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the dev ice at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade on ly. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Crystal Pullability Recommended ESR SYMBOL CONDITIONS MIN. F XIN Parallel Fundamental Mode 100 C L ( xtal) C0 C 0/C 1 ( xtal) RE Die at VCON = 1.65V AT cut AT cut TYP. MAX. UNITS 200 MHz 3.5 pF pF 4 250 30  Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/20/04 Page 2 PL520-00 Low Phase Noise VCXO with multipliers (for 100 -200MHz Fund Xtal) 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * SYMBOL T VC XOS TB VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW CONDITIONS From power valid F XIN = 100 – 200MHz; XTAL C 0/C 1 < 250 0V  VCON  3.3V VCON=1.65V, 1.65V VCON = 0 to 3.3V MIN. TYP. MAX. UNITS 10 ms 200* ppm 100* 4 – 18* 10* 65 60 0V  VCON  3.3V, -3dB ppm pF % ppm/V k kHz 25 Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. General Electrical Specifications PARAMETERS SYMBOL Supply Current (Loaded Outputs) Operating Voltage IDD VDD Output Clock Duty Cycle CONDITIONS MIN. TYP. PECL/LVDS/CMOS @ 50% V DD (CMOS) @ 1.25V (LVDS) @ VDD – 1.3V (PECL) 2.97 45 45 45 Short Circuit Current 50 50 50 50 MAX. UNITS 100/80/40 3.63 55 55 55 mA V % mA 5. Jitter Specifications PARAMETERS Period jitter RMS Period jitter peak-to-peak Accumulated jitter RMS Accumulated jitter peak-topeak Random Jitter Integrated jitter RMS at 155MHz Period jitter RMS Period jitter peak-to-peak Accumulated jitter RMS Accumulated jitter peak-topeak Random Jitter Integrated jitter RMS at 622MHz CONDITIONS At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 MIN. TYP. MAX. 2.5 18.5 2.5 20 24 27 2.5 0.3 0.4 At 622.08MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles 11 45 11 49 24 27 Integrated 12 kHz to 20 MHz 3 1.6 ps ps ps Integrated 12 kHz to 20 MHz At 622.08MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 UNITS ps ps ps ps 1.8 ps Measured on Wavecrest SIA 3000 Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/20/04 Page 3 PL520-00 Low Phase Noise VCXO with multipliers (for 100 -200MHz Fund Xtal) 6. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS 155.52MHz 622.08MHz -75 -75 -95 -95 -125 -110 -140 -125 -145 -120 dBc/Hz Phase Noise relative to carrier Note: Phase Noise measured at VCON = 0V 7. CMOS Electrical Characteristics PARAMETERS Output drive current (High Drive) Output drive current (Standard Drive) Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive) SYMBOL CONDITIONS MIN. TYP. MAX. UNITS I OH I OL I OH VOH = VDD -0.4V, V DD =3.3V VOL = 0.4V, V DD = 3.3V VOH = VDD -0.4V, V DD =3.3V 30 30 10 mA mA mA I OL VOL = 0.4V, V DD = 3.3V 10 mA 0.3V ~ 3.0V with 15 pF load 2.4 0.3V ~ 3.0V with 15 pF load 1.2 ns Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/20/04 Page 4 PL520-00 Low Phase Noise VCXO with multipliers (for 100 -200MHz Fund Xtal) 8. LVDS Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS 355 454 mV 50 1.6 Output Differential Voltage VOD 247 VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change V OD VOH VOL VOS -50 Power-off Leakage I OXD Output Short Circuit Current I OSD R L = 100  (see figure) 0.9 1.125 0 V OS Vout = VDD or GND VDD = 0V 1.4 1.1 1.2 3 1.375 25 mV V V V mV 1 10 uA -5.7 -8 mA 9. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100  C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50 VO D VO S VDIF F RL = 100  50 CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIF F 80% 0V 20% 20% tR tF Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/20/04 Page 5 PL520-00 Low Phase Noise VCXO with multipliers (for 100 -200MHz Fund Xtal) 10. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. VOH VOL R L = 50 to (VDD – 2V) (see figure) VDD – 1.025 Output High Voltage Output Low Voltage MAX. UNITS VDD – 1.620 V V 11. PECL Switching Characteristics PARAMETERS SYMBOL Clock Rise Time Clock Fall Time tr tf CONDITIONS MIN. TYP. MAX. UNITS 0.6 0.5 1.5 1.5 ns ns @20/80% - PECL @80/20% - PECL PECL Levels Test Circuit OUT PECL Output Skew VDD 50 OUT 2.0V 50% 50 OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/20/04 Page 6 PL520-00 Low Phase Noise VCXO with multipliers (for 100 -200MHz Fund Xtal) PAD ASSIGNMENT Pad # Name X (m) Y (m) Description 1 2 GND GND 248 361 109 109 Ground. Ground. 3 4 5 6 7 8 GND GND GND N/C GND GNDBUF 473 587 702 874 1042 1171 109 109 109 109 109 109 9 OE_SELECT 1400 125 10 LVDS 1400 259 Ground. Ground. Ground. No Connection. Ground. Ground, Buffer circuitry. Used to select between PECL or CMOS logic states for OE. See Output Selection and Enable table on page 1. Internal pull up. LVDS output. 11 12 13 14 15 16 17 PECL VDDBUF VDDBUF PECLB LVDSB CMOS GNDBUF 1400 1400 1400 1400 1400 1400 1389 476 616 716 871 1089 1227 1365 18 OUTSEL1 1232 1365 19 SEL1 1042 1365 20 SEL0 854 1365 21 22 23 24 VDD VDD VDD VDD 659 559 459 358 1365 1365 1365 1365 25 OUTSEL0 194 1365 26 27 XIN XOUT 109 109 1223 1017 28 SEL3 109 858 29 SEL2 109 646 30 OE_CTRL 109 397 31 VCON 109 181 PECL output. 3.3V power supply, Buffer circuitry. 3.3V power supply, Buffer circuitry. Complementary PECL output. Complementary LVDS output. CMOS output Ground, Buffer Circuitry. Used to select CMOS, PECL or LVDS output type. See Output Selection and Enable table on page 1. Internal pull up. Used to select multiplication factor. See Frequency Selection table on page 1. Internal pull up. Used to select multiplication factor. See Frequency Selection table on page 1. Internal pull up. 3.3V power supply. 3.3V power supply. 3.3V power supply. 3.3V power supply. Used to select CMOS, PECL or LVDS output type. See Output Selection and Enable table on page 1. Internal pull up. Crystal input. See crystal specification page 2. Crystal output. See crystal specification page 2. Used to select multiplication factor. See Frequency Selection table on page 1. Internal pull up. Used to select multiplication factor. See Frequency Selection table on page 1. Internal pull up. Used to enable/disable the output(s). See Output Selection and Enable table on page 1. Voltage Control input. 0V to 3.3V. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/20/04 Page 7 PL520-00 Low Phase Noise VCXO with multipliers (for 100 -200MHz Fund Xtal) ORDERING INFORM ATION For part ordering, please contact our Sales Department: 2180 Fortune Drive, San Jose, CA 95131, USA Tel: (408) 944-0800 Fax: (408) 474-1000 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL 520-00 DC PART NUMBER TEMPERATURE C=COMMERCIAL PACKAGE TYPE D=DIE Order Number Marking Package Option PL520-00DC P520-00DC Die – Waffle Pack Micrel Inc., reserves the right to make changes in its products or specifications, or both at any time without notice. The in formation furnished by Micrel is believed to be accurate and reliable. However, Micrel makes no guarantee or warranty concerning t he accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: Micrel’s products are not authorized for use as critical components in lif e support devices or systems without the express written approval of the President of Micrel Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/20/04 Page 8