PL602-03
Low Phase Noise CMOS XO (48MHz to 100MHz)
FEATURES
Low phase noise XO output for the 48MHz to
100MHz range (-130 dBc at 10kHz offset).
12 to 25MHz crystal input.
Integrated crystal load capacitor: no external
load capacitor required.
Selectable High Drive (30mA) or Sta ndard Drive
(10mA) output.
3.3V operation.
Available in 8-Pin TSSOP or SOIC.
CLK
1
VDD
2
OE^
3
XIN
4
PL602-03
PIN CONFIGURATION
8
GND
7
GND
6
N/C
5
XOUT
Note: ^ denotes internal pull up
OUTPUT RANGE
DESCRIPTION
The PL602-03 is a low cost, high performance and
low phase noise XO, providing less than -130dBc at
10kHz offset in the 48MHz to 100MHz operating
range. The very low jitter makes this chip ideal for
applications requiring clean reference frequency
sources. Input crystal can range from 12 to 25MHz
(fundamental resonant mode).
FREQUENCY
RANGE
48 - 100MHz
MULTIPLIER
X4
OUTPUT
BUFFER
CMOS
BLOCK DIAGRAM
VCO
Divider
Reference
Divider
XIN
XOUT
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLK
OE
XTAL
OSC
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 11/16/11 Page 1
PL602-03
Low Phase Noise CMOS XO (48MHz to 100MHz)
PIN DESCRIPTIONS
Name
Number
Type
Description
CLK
1
O
Output clock.
VDD
2
P
power supply.
OE
3
I
Output enable input. Disables (tri-state) output when low. Internal pull-up
enables output by default if pin is not connected to low.
XIN
4
I
Crystal input. See Crystal Specification on page 3.
XOUT
5
I
Crystal output. See Crystal Specification on page 3.
N/C
6
-
Not connected.
GND
7, 8
P
Ground.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
4.6
V
V
V
Supply Voltage
VDD
Input Voltage, dc
Output Voltage, dc
Storage Temperature
VI
VO
TS
-0.5
-0.5
-65
VDD +0.5
VDD +0.5
150
C
Ambient Operating Temperature*
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
TA
-40
85
260
2
C
C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for e xtended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the dev ice at these or any other co nditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDU STRIAL), but tested for COMMERCIAL grade only.
2. DC Specifications
PARAMETERS
Supply Current, Dynam ic, with
Loaded Outputs
Operating Voltage
SYMBOL
IDD
CONDITIONS
MIN.
F XIN = 12 - 25MHz
Output load of 10pF
VDD
2.97
TYP.
MAX.
UNITS
35
mA
3.63
V
Output drive current
(High Drive)
I OH
VOH = VDD -0.4V, V DD =3.3V
30
mA
I OL
VOL = 0.4V, V DD = 3.3V
30
mA
Output drive current
(Standard Drive)
I OH
VOH = VDD -0.4V, V DD =3.3V
10
mA
I OL
VOL = 0.4V, V DD = 3.3V
10
mA
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 11/16/11 Page 2
PL602-03
Low Phase Noise CMOS XO (48MHz to 100MHz)
3. AC Specifications
PARAMETERS
SYMBOL
CONDITIONS
Input Crystal Frequency
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
Output Clock Duty Cycle
MIN.
TYP.
12
0.3V ~ 3.0V with 15 pF load
2.4
0.3V ~ 3.0V with 15 pF load
1.2
Measured @ 50% V DD
45
50
MIN.
TYP.
MAX.
UNITS
25
MHz
ns
55
%
4. Jitter and Phase Noise Specification
PARAMETERS
CONDITIONS
MAX.
UNITS
RMS Period Jitter
(1 sigma – 1000 samples)
Phase Noise relative to carrier
at 80MHz, with capacitive decoupling
between VDD and GND.
80MHz @100Hz offset
20
ps
-106
dBc/Hz
Phase Noise relative to carrier
80MHz @1kHz offset
-124
dBc/Hz
Phase Noise relative to carrier
80MHz @10kHz offset
-130
dBc/Hz
Phase Noise relative to carrier
Phase Noise relative to carrier
80MHz @100kHz offset
80MHz @1MHz offset
-122
-121
dBc/Hz
dBc/Hz
5. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Capacitance Rating
Driving power
ESR
SYMBOL
MIN.
F XIN
12
TYP.
MAX.
UNITS
25
MHz
pF
mW
30
20
1
C L (xtal)
RS
PACKAGE INFORMATION
8 PIN ( dimensions in mm )
TSSOP
Min.
A
Narrow SOIC
Max
.
1.34
1.74
-
Max
.
1.20
A1
0.10
0.25
0.05
0.15
B
0.33
0.51
0.19
0.30
C
0.19
0.25
0.09
0.20
D
4.80
4.95
2.90
3.10
Symbol
Min.
E
3.80
4.00
4.30
4.50
H
5.80
6.20
6.20
6.60
L
0.38
1.27
0.45
0.75
e
1.27 BSC
0.65 BSC
E
H
D
A
A1
C
L
B
e
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 11/16/11 Page 3
PL602-03
Low Phase Noise CMOS XO (48MHz to 100MHz)
ORDERING INFORM ATION
For part ordering, please contact our Sales Department:
2180 Fortune Drive, San Jose, CA 95131, USA
Tel: (408) 944-0800 Fax: (408) 474-1000
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PL 602-03 (H ) X C
PART NUMBER
TEMPERATURE
C=COMMERCIAL
I=INDUSTRAL
Optional High Drive
PACKAGE TYPE
S=SOIC, O=TSSOP
Part/Order Number
(Commercial)
PL602-03OC
PL602-03OC-R
PL602-03HOC
PL602-03HOC-R
PL602-03SC
PL602-03SC-R
PL602-03HSC
PL602-03HSC-R
Marking*
P602-03
OC
LLLLL
P602-03
HOC
LLLLL
P602-03
SC
LLLLL
P602-03
HSC
LLLLL
Package Option
8-Pin SOP Tube
8-Pin SOP (Tape and Reel)
8-Pin SOP Tube
8-Pin SOP (Tape and Reel)
8-Pin SOP Tube
8-Pin SOP (Tape and Reel)
8-Pin SOP Tube
8-Pin SOP (Tape and Reel)
*Note: LLLLL designates lot number
Micrel Inc., reserves the right to make changes in its products or specifications, or both at any time without notice. The in formation furnished by Micrel
is believed to be accurate and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said information and shal l not be
responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPO RT POLICY: Micrel’s products are not authorized for use as critical components in life support devices or systems without the express
written approval of the President of Micrel Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 11/16/11 Page 4
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