PL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
FEATURES
1
XIN
2
XOUT
3
SEL3^
4
SEL2^
5
OE
6
GND
7
GND
8
1
6
1
5
1
4
1
3
1
2
1
1
1
0
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
9
GND
VDD / GND*
SEL0^ / VDD*
SEL1^
TSSOP-16L
12
11
10
9
DESCRIPTION
SEL3^
14
SEL2^
15
OE
16
PL602-3x
1
BLOCK DIAGRAM
2
3
4
GND
13
GND
XOUT
GND
The PL602-35 (LVPECL with inverted OE), PL602-37
(LVCMOS), PL602-38 (LVPECL), and PL602-39
(LVDS) are high performance and low phase noise XO
IC chips. They provide phase noise performance as
low as –127dBc at 10kHz offset (at 155MHz), by multiplying the input crystal frequency up to 32x. The very
low jitter makes them ideal for a wide range of applications, including SONET/SDH and FEC. They accept
fundamental parallel resonant mode crystals from
12MHz to 25MHz.
GND
VDD
PL602-3x
Selectable 750kHz to 800MHz range.
Low phase noise output
-127dBc/Hz for 155.52MHz @ 10kHz offset
-115dBc/Hz for 622.08MHz @ 10kHz offset
LVCMOS (PL602-37), LVPECL (PL602-35 and
PL602-38) or LVDS (PL602-39) output.
12MHz to 25MHz crystal input.
No external crystal load capacitors required.
Output Enable selector.
Selectable /16 to x32 frequency divider/multiplier.
3.3V operation.
Available in 16-Pin TSSOP or 16-pin 3x3mm QFN
GREEN/RoHS compliant packages.
XIN
PIN CONFIGURATION
(Top View)
8
GND
7
CLKC
6
VDD
5
CLKT
QFN-16L
SEL[3:0]
^:
*:
OE
XIN
XOUT
Oscillator
Amplifier
w/
integrated
load cap.
PLL
(Phase
Locked
Loop)
CLKC
CLKT
Internal pull -up
On QFN package, PL 602-35/-38 do not have SEL0 available: Pin 10
is VDD, pin 11 is GND. However, PL602-37/-39 have SEL0 (pin 10),
and pin11 is VDD. See pin assignment table for d etails.
Note: On QFN package there is a large center pad for thermal relief.
This pad needs to be connected to GND.
OUTPUT ENABLE LOGICAL LEVELS
Part #
PL602-38
PLL by-pass
PL602-3x
PL602-35
PL602-37
PL602-39
OE
0 (Default)
State
Output enabled
1
Tri-state
0
Tri-state
1 (Default)
Output enabled
OE input: Logical states defined by LVPECL levels for PL602-38
Logical states defined by LVCMOS levels for PL602-37/-39
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/07/2012 Page 1
PL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
FREQUENCY SELECTION TABLE
SEL3
SEL2
SEL1
SEL0
Selected Multiplier
0
0
1
1
Fin x 32
0
1
1
0
Fin / 8
0
1
1
1
Fin x 2
1
0
0
1
Fin / 2
1
0
1
0
Fin / 16
1
0
1
1
Fin x 4
1
1
0
0
Fin / 4
1
1
0
1
Fin x 8
1
1
1
0
Fin x 16
1
1
1
1
No multiplication
Note: SEL0 is not available (always “1”) for PL602-35 and PL602-38 in 3x3mm package
PIN DESCRIPTIONS PL602-35 and PL602-38 (see next page for PL602-37/-39)
TSSOP
Pin number
3x3mm QFN
Pin number
Type
XIN
2
12
I
Crystal input (See Crystal Specification on page 4)
XOUT
3
13
I
Crystal output (See Crystal Specification on page 4 )
OE
6
16
I
Output enable pin (See OE logic state table on page 1)
GND
7,8,9,10,14
1,2,3,4,8,11
P
Ground connection
CLKT
11
5
O
LVPECL True output
CLKC
13
7
O
LVPECL Complementary output
SEL0
16
Not available
I
SEL1
15
9
I
SEL2
5
15
I
SEL3
4
14
I
VDD
1, 12
6,10
P
Name
Description
Multiplier selector pins. These pins have an internal pullup that will default SEL to ‘1’ when not connected to
GND.
+3.3V power supply.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/07/2012 Page 2
PL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
PIN DESCRIPTIONS PL602-37/-39 (see previous page for PL602-35/-38)
Name
TSSOP
Pin number
3x3mm QFN
Pin number
Type
XIN
2
12
I
Crystal input. See Crystal Specification on page 4.
XOUT
3
13
I
Crystal output. See Crystal Specification on page 4.
OE
6
16
I
Output enable pin (see OE logic state table on page 1).
GND
7,8,9,10,14
1,2,3,4,8
P
Ground.
CLKT
11
5
O
LVDS True output for PL602-39.
No Connect for PL602-37
CLKC
13
7
O
LVDS Complementary output for PL602-39
LVCMOS out for PL602-37
SEL0
16
10
I
SEL1
15
9
I
SEL2
5
15
I
SEL3
4
14
I
VDD
1, 12
6,11
P
Description
Multiplier selector pins. These pins have an internal pull-up
that will default SELx to ‘1’ when not connected to GND.
+3.3V power supply.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/07/2012 Page 3
PL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
Supply Voltage
MIN.
V DD
MAX.
UNITS
4.6
V
Input Voltage, dc
VI
-0.5
V DD+0.5
V
Output Voltage, dc
VO
-0.5
V DD+0.5
V
Storage Temperature
TS
-65
150
C
Ambient Operating Temperature*
TA
-40
85
C
Junction Temperature
TJ
125
C
260
C
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
2.5
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product
reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this
specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
Crystal Resonator Frequency
F XIN
Parallel Fundamental Mode
12
Crystal Loading Rating
CL (x ta l)
Recommended ESR
RE
TYP.
MAX.
UNITS
25
MHz
20
AT cut
pF
30
Ω
MAX.
UNITS
3. General Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
Supply Current,
Dynamic (with
Loaded Outputs)
I DD
F OUT
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