PL607041
ClockWorks® PCIe Quad Outputs
Ultra-Low Jitter, HCSL Frequency
Synthesizer
General Description
Features
®
The PL607041 is a member of the ClockWorks family of
devices from Micrel and provides an extremely low-noise
Spread-Spectrum clock for PCI Express requirements.
The device operates from a 3.3V or 2.5V power supply
and synthesizes four HCSL output clocks at 25MHz,
100MHz, 125MHz, and 200MHz. The PL607041 accepts a
25MHz crystal.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
25MHz fundamental crystal or reference input
Generates four HCSL clock outputs at 25MHz, 100MHz,
125MHz, and 200MHz
Spread spectrum for EMI reduction
2.5V or 3.3V operating range
Typical phase jitter @ 100MHz (1.5MHz to 10MHz):
320fs
Compliant with PCI Express Gen1, Gen2, and Gen3
Industrial temperature range (–40°C to +85°C)
RoHS and PFOS compliant
Available in 24-pin 4mm × 4mm QFN package
Applications
Servers
Storage systems
Switches and routers
Gigabit Ethernet
Set-top boxes/DVRs
Block Diagram
ClockWorks is a registered trademark of Micrel, Inc.
Ripple Blocker is a trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
April 1, 2014
Revision 1.2
tcghelp@micrel.com or (408) 955-1690
Micrel, Inc.
PL607041
Ordering Information(1)
Marking
Shipping
Junction Temperature
Range
Package
PL607041UMG
PL607
041
Tube
–40° to +85°C
24-Pin QFN
PL607041UMG TR
PL607
041
Tape and Reel
–40° to +85°C
24-Pin QFN
Part Number
Note:
1. Devices are RoHS and PFOS compliant.
Pin Configuration
24-Pin QFN
(Top View)
Pin Description
Pin Number
Pin Name
Pin Type
Pin Level
17, 18
19, 20
/Q0, Q0
/Q1, Q1
O, (DIF)
HCSL
Differential Clock Outputs pins.
23, 24
1, 2
/Q2, Q2
/Q3, Q3
O, (DIF)
HCSL
Differential Clock Outputs pins.
9
VDDO2
PWR
Power Supply.
16
VDDO1
PWR
Power Supply.
7, 15
VDD
PWR
Core Power Supply.
5, 11, 13
VSS
PWR
Power Supply Ground.
6, 8
S0, S1
I
LVCMOS
Frequency Select for 25MHz, 100MHz, 125MHz, and
200MHz. Each pin has a 45kΩ pull-up.
14, 4
SS0, SS1
I
LVCMOS
Spread Spectrum Select pins. Each pin has a 60kΩ pullup.
22
XIN/FIN
I, (SE)
Crystal
Crystal or Reference Input, no load caps needed (see
Figure 5).
21
XOUT
O, (SE)
Crystal
Crystal Output, no load caps needed (see Figure 5).
12
OE
I, (SE)
LVCMOS
3, 10
TEST
I
April 1, 2014
Pin Function
Output Enable/Disable.
Factory test pins. Keep these pins floating.
2
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PL607041
EMI Reduction
The Spread Spectrum modulation causes the emission of
spectral components in the clock signal to be reduced. The
spectrum plot on the right shows measurement results with
the two spread settings versus no spread. This plot is
looking at the 11th harmonic in a 100MHz clock, at
1.1GHz. The scale is normalized to the strength of this
spur without spread. The plot shows about 21dB reduction
for -0.25% spread magnitude and 24dB for -0.50% spread
magnitude.
The plot also shows how the frequency spreading is
happening downwards.
April 1, 2014
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PL607041
Absolute Maximum Ratings(2)
Operating Ratings(3)
Supply Voltage (VDD, VDDO1/2) ....................................... +4.6V
Input Voltage (VIN) ............................... –0.50V to VDD + 0.5V
Lead Temperature (soldering, 20s) ............................ 260°C
Case Temperature ..................................................... 115°C
Storage Temperature (Ts)......................... –65°C to +150°C
Supply Voltage (VIN) ............................. +2.375V to +3.465V
Ambient Temperature (TA) .......................... –40°C to +85°C
(4)
Junction Thermal Resistance
QFN (JA) ........................................................... 50°C/W
QFN (JB)........................................................... 30°C/W
Electrical Characteristics(5)
VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%
VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V ±5%
TA = –40°C to +85°C
Symbol
Parameter
VDD,
VDDO1/2
Condition
Min.
Typ.
Max.
Units
2.5V operating voltage
2.375
2.5
2.625
V
VDD,
VDDO1/2
3.3V operating voltage
3.135
3.3
3.465
V
IDD
Supply current VDD + VDDO
150
185
mA
Min.
Typ.
Max.
Units
Outputs 50Ω to VSS
HCSL DC Electrical Characteristics(5)
VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%
VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V ±5%
TA = –40°C to +85°C. RL = 50Ω to VSS
Symbol
Parameter
Condition
VOH
Output High Voltage
660
700
850
mV
VOL
Output Low Voltage
–150
0
27
mV
VCROSS
Crossing Point Voltage
250
350
550
mV
Min.
Typ.
Max.
Units
LVCMOS (S0, S1) Electrical Characteristics(5)
VDD = 3.3V ±5%, or 2.5V ±5%, TA = –40°C to +85°C.
Symbol
Parameter
Condition
VIH
Input High Voltage
2.0
VDD +
0.3
V
VIL
Input Low Voltage
–0.3
0.8
V
IIH
Input High Current
VDD = VIN = 3.465V
150
µA
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
–150
µA
Notes:
2. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
3. The device is not guaranteed to function outside its operating ratings.
4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
5. The circuit is designed to meet the AC and DC specifications shown in the above table(s) after thermal equilibrium has been established.
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PL607041
Crystal Characteristics
Parameter
Condition
Min.
Mode of Oscillation
15pF load capacitance
Typ.
Max.
Units
Fundamental, Parallel Resonant
Frequency
25
MHz
Equivalent Series Resistance
(ESR)
50
Ω
Shunt Capacitor, C0
1
7
pF
Correlation Drive Level
10
100
µW
AC Electrical Characteristics(6, 7)
VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%
VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V ±5%
TA = –40°C to +85°C. RL = 50Ω to VSS
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
FOUT
Output Frequency
25
100
125
200
FREF
Crystal Input Frequency
25
MHz
FIN
Reference Input Frequency
25
MHz
FIN
FIN Signal Amplitude
Internally AC-coupled
0.9
TR/TF
HCSL Output Rise/Fall Time
20% - 80%
150
ODC
Output Duty Cycle
48
TSKEW
Output-to-Output Skew
TLOCK
PLL Lock Time
Tjit(Ø)
VDD
VPP
300
450
ps
50
52
%
45
ps
20
ms
Note 7
100MHz
Integration Range (1.5MHz – 10MHz)
(8)
RMS Phase Jitter
MHz
320
Cycle-to-Cycle Jitter
fs
30
ps,
peak
Notes:
6. All phase noise measurements were taken with an Agilent 5052B phase noise system.
7. Defined as skew between outputs at the same supply voltage and with equal load conditions; measured at the output differential crossing points.
8. Measured using 25MHz crystal as the input reference source. If using an external reference input, use a low phase noise source. With an external
reference, the phase noise will follow the input source phase noise up to about 1MHz.
Spread Spectrum Characteristics
Parameter
Modulation Rate
Condition
Min.
(9)
Modulation Magnitude
Typ.
Max.
31.6
(10)
Units
kHz
Setting is -0.25%
-0.073 to -0.265
0 to -0.250
+0.031 to -0.375
%
Setting is -0.50%
-0.136 to -0.383
0 to -0.500
+0.078 to -0.589
%
Notes:
9. The modulation rate is created from the crystal frequency, divided by 792.
10. The typical modulation makes the output frequency sweep between the target frequency (0%) and the down-spread value (-0.25% or -0.5%). There
is process variation on the modulation magnitude and the smallest and largest possible modulation magnitude sweep ranges are listed in the table.
April 1, 2014
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PL607041
Truth Tables
SS1
S1
S0
OUTPUT
0
0
25MHz
0
1
100MHz
1
0
125MHz
1
1
200MHz
(11)
SS0
(11)
Spread Type
Spread
0
0
Spread is OFF
No Spread
0
1
Down Spread
-0.25%
1
0
Spread is OFF
No Spread
1
1
Down Spread
-0.50%
Note:
11. SS0 is turning ON/OFF the spread spectrum modulation and SS1 is selecting the spread magnitude.
Phase Noise Plot
Phase Noise Plot: 100MHz, 1.5MHz – 10MHz 320fs
April 1, 2014
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PL607041
Figure 1. Duty Cycle Timing
Figure 2. All Outputs Rise/Fall Times
Figure 3. RMS Phase/Noise Jitter
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PL607041
Figure 4. HCSL Output Load and Test Circuit
Figure 5. HCSL Recommended Application Termination (Source Terminated)
Figure 6. Crystal Input Interface
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PL607041
Application Information
Crystal Layout
Keep the layers under the crystal as open as possible
and do not place switching signals or noisy supplies
under the crystal. Crystal load capacitance is built inside
the die so no external capacitance is needed. See the
Selecting a Quartz Crystal for the Clockworks Flex /
Family of Precision Synthesizers application note for
more details.
The impedance value of the Ferrite Bead (FB) needs to
be between 240Ω and 600Ω with a saturation current
≥150mA.
VDDO1 and VDDO2 pins connect directly to the VDD
Plane. All VDD pins on the PL607041 connect to VDD
after the power supply filter.
Contact
Micrel’s
TCG
applications
group
at:
tcghelp@micrel.com if you need help selecting a suitable
crystal for your application.
HCSL Outputs
HCSL outputs are to be terminated with 50Ω to VSS. For
best performance load all outputs. If you want to ACcouple or change the termination, contact Micrel’s
application group: tcghelp@micrel.com (see Figure 5).
Power Supply Decoupling
Place the smallest value decoupling capacitor (4.7nF
above) between the VDD and VSS pins, as close as
possible to those pins and at the same side of the PCB
as the IC. The shorter the physical path from VDD to
capacitor and back from capacitor to VSS, the more
effective the decoupling. Use one 4.7nF capacitor for
each VDD pin on the PL607041.
Power Supply Filtering Recommendations
Preferred filter, using Micrel’s MIC94300 or MIC94310 Ripple Blocker™:
Alternative, traditional filter, using a ferrite bead:
April 1, 2014
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Revision 1.2
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PL607041
Package Information(12)
24-Pin QFN
Note:
12. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
April 1, 2014
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Revision 1.2
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PL607041
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant
into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2014 Micrel, Incorporated.
April 1, 2014
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