PL620-20DC

PL620-20 Low Phase Noise XO (for HF Fund. and 3 rd O.T.) DIE CONFIGURATION FEATURES 65 mil 100MHz to 200MHz Fund. or 3 OT Crystal. Output range: 100 – 200MHz (no multiplication). Available outputs: PECL, or LVDS. OESEL/OECTRL for both PECL & LVDS. Supports 2.5V or 3.3V-Power Supply. Available in die form. Die thickness 10 mil. XIN N/C VDD VDD VDD VDD N/C Reserved Reserved 24 23 22 21 20 19 18 17 Die ID: A1212-12 27 N/C 28 N/C 29 OE CTRL 30 N/C 31 C502A 2 3 4 5 6 7 8 GND GND Reserved GNDBUF GNDBUF (0,0) 1 GND Y X Pad #9 OUTSEL Value 0 LVDS Size Reverse side Pad dimensions 62 x 65 m il GND 80 m icron x 80 micron 1 PECL (default) Thickness 10 m il Pad #9 OUTSEL 0 X+ X- Q Q Oscillator Amplifier 15 LVDSB 14 PECLB 13 12 VDDBUF VDDBUF 11 PECL 10 LVDS OUTSEL^ Selected Output Name OE N/C OUTPUT SELECTION AND ENABLE DIE SPECIFICATIONS BLOCK DIAGRAM GNDBUF 16 9 GND The PL620-20 is an XO IC specifically designed to work with high frequency fundamental and third overtone crystals. Its design was optimized to tolerate higher limits of interelectrode capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. It is ideal for XO applications requiring LVDS or PECL output levels at high frequencies. 25 GND DESCRIPTION (1550,1475) 26 XOUT 62 mil        rd 1 Pad #30 OE_CTRL 0 1 0 1 State Tri-state Output enabled (default) Output enabled (default) Tri-state Pad # 9: Bond to GND to set to “0”, bond to VDD to set to “1” Pad # 30: Logical states defined by PECL levels if OUTSEL is “1” Logical states defined by CMOS levels if OUTSEL is “0” PL620-20 Micrel Inc. • 2180 Fortune Drive • San J ose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/28/09 Page 1 PL620-20 Low Phase Noise XO (for HF Fund. and 3 rd O.T.) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage Input Voltage, dc Output Voltage, dc VDD VI VO Storage Temperature Ambient Operating Temperature* Junction Temperature TS TA TJ MIN. MAX. UNITS -0.5 -0.5 4.6 VDD +0.5 VDD +0.5 V V V 150 85 125 C C C 260 2 C kV -65 -40 Lead Temperature (soldering, 10s) ESD Protection, Human Body Model Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permane nt damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or an y other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaran teed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Recommended ESR SYMBOL CONDITIONS Fundamental or 3 r d overtone* Die only F XIN C L ( xtal) C0 MIN. TYP. 100 UNITS 200 MHz 3.0 3 30 25 30 F XIN