PL620-21DC

PL620-21 Low Phase Noise XO (for HF Fund. and 3 rd O.T.) DIE CONFIGURATION XIN VDD VDD VDD VDD DNC Reserved Reserved 24 23 22 21 20 19 18 XOUT 27 DNC 28 DNC 29 OE_CTRL 30 DNC 31 Die ID: A1919-19C C502A 3 4 5 6 GND Reserved X 7 8 GNDBUF 2 GNDBUF 1 GND (0,0) Y (1550,1475) 17 GNDBUF 16 DNC 15 LVDSB 14 PECLB 13 VDDBUF 12 VDDBUF 11 PECL 10 LVDS 9 GND PL620-21 is an XO IC specifically designed to work with high frequency fundamental and third overtone crystals. Its design was optimized to tolerate higher limits of interelectrodes capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. It offers a selectable OE logic and is ideal for XO applications requiring LVDS or PECL output levels at high frequencies. 25 26 GND DESCRIPTIONS OESEL 65 mil 100MHz to 200MHz Fundamental Mode Crystal. Output range: 100 – 200MHz (no multiplication). Selectable OE logic. Minimum bondwires required for VDD and GND. Available outputs: PECL or LVDS. Supports 3.3V-Power Supply. Available in die form. Thickness 10 mil. 62 mil         GND FEATURES OUTSEL^ DIE SPECIFICATIONS BLOCK DIAGRAM OE Value Size Reverse side 62 x 65 mil GND Pad dimensions 80 micron x 80 micron Thickness 10 mil Q X+ X- Name Q Oscillator Amplifier OUTPUT SELECTION AND ENABLE Pad #9 OUTSEL Selected Output 0 1 PL620-21 Pad #25 OESEL 0 1 (default) LVDS PECL (default) Pad #30 OE_CTRL 0 1 0 1 State Tri-state Output enabled (default) Output enabled (default) Tri-state Pad #9: Bond to GN D to se t to “0 ”, bond to VDD to se t to “1 ” Pad #30: Logical s ta tes de fined by PECL leve ls i f OUT SEL (pad #9) is “1 ” Logical s ta tes de fined by CM OS levels i f O UTSEL is “0 ” Micrel Inc. • 2180 Fortune Drive • San J ose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 05/10/07 Page 1 PL620-21 Low Phase Noise XO (for HF Fund. and 3 rd O.T.) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage MIN. MAX. UNITS 7 V VD D Input Voltage, dc VI V SS-0.5 VD D +0.5 V Output Voltage, dc VO V SS-0.5 VD D +0.5 V Storage Temperature TS -65 150 C Ambient Operating Temperature* TA -40 85 C Junction Temperature TJ 125 C 260 C 2 kV Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection Exposure of the device under conditions beyond the limits specified by Maximum Ratin gs for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the dev ice at these or any other conditions above the operational limits noted i n this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade on ly. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Recommended ESR SYMBOL F XIN C L ( xtal) C0 RE CONDITIONS Fundamental or overtone* Die only 3rd MIN. TYP. 100 MAX. UNITS 200 MHz 3.0 F XIN