PL620-80DC

PL620-80 Low Phase Noise XO (9.5-65MHz Output) DIE CONFIGURATION FEATURES XIN OUTSEL0^ VDD VDD VDD VDD N/C Reserved OUTSEL1^ 24 23 22 21 20 19 18 17 26 Die ID: A2020-20B XOUT 27 N/C 28 S2^ 29 OE CTRL 30 N/C 31 C502A 16 CMOS 15 LVDSB 14 PECLB 13 12 VDDBUF VDDBUF 11 PECL 10 LVDS 5 6 Reserved X 7 OE_SEL^ 8 GNDBUF 4 GNDBUF 3 GND (0,0) 2 GND Y GNDBUF 9 1 GND The PL620-80 is a XO IC specifically designed to work with fundamental or 3 rd OT crystals between 19MHz and 65MHz. The selectable divide by two feature extends the operation range from 9.5MHz to 65MHz. It requires very low current into the crystal resulting in better overall stability. The OE logic feature allows selection of enable high or enable low. Furthermore, it provides selectable CMOS, PECL or LVDS outputs. 25 GND DESCRIPTION (1550,1475) GND   19MHz to 65MHz crystal input. Output range: 9.5MHz – 65MHz Selectable OE Logic (enable high or enable low). Available outputs: PECL, LVDS, or CMOS (High Drive (30mA) or Standard Drive (10mA) output). Supports 2.5V or 3.3V Power Supply. Available in die form. 62 mil     65 mil OUTPUT SELECTION AND ENABLE DIE SPECIFICATIONS Name Value Size 62 x 65 m il Reverse side Pad dimensions Thickness GND 80 m icron x 80 micron 10 m il OUT_SEL1* (Pad 18) 0 0 1 OUT_SEL0* (Pad 25) 0 1 0 1 1 OE_SELECT (Pad 9) OE_CTRL (Pad 30) 0 1 (Default) 0 (Default) 1 0 BLOCK DIAGRAM 1 (Default) OE Q XIN XOUT Q Oscillator Amplifier Selected Output* High Drive CMOS Standard CMOS LVDS PECL (default) State Tri-state Output enabled Output enabled Tri-state Pads # 9, # 18 & # 25: Bond to GND to set to “0”, No connection results to “default” setting through internal pull-up. OE_CTRL: Logical states defined by PECL levels if OE_SELECT is “1” Logical states defined by CMOS levels if OE_SELECT is “0” OUTPUT FREQUENCY SELECTOR S2 PL620-80 S2 Output 0 1(Default)* Input/2 Input *Internally set to ‘Default’ through 60K Ω pull-up resistor Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/28/09 Page 1 PL620-80 Low Phase Noise XO (9.5-65MHz Output) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage Input Voltage, dc Output Voltage, dc VDD VI VO Storage Temperature Ambient Operating Temperature Junction Temperature TS TA TJ MIN. MAX. UNITS -0.5 -0.5 4.6 VDD +0.5 VDD +0.5 V V V 150 85 125 C C C 260 2 C kV -65 -40 Lead Temperature (soldering, 10s) ESD Protection, Human Body Model Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended pe riods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the dev ice at these or any other conditions above the operational limits noted in this specificati on is not implied. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Recommended ESR SYMBOL F XIN C L ( xtal) C0 RE CONDITIONS Fundamental Die MIN. TYP. 19 MAX. UNITS 65 5 MHz pF pF 30  8* AT cut Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any sp ecific limits. 3. General Electrical Specifications PARAMETERS SYMBOL Supply Current (Loaded Ou tputs) Operating Voltage IDD VDD Output Clock Duty Cycle Short Circuit Current CONDITIONS MIN. TYP. PECL/LVDS/CMOS @ 50% V DD (CMOS) @ 1.25V (LVDS) @ VDD – 1.3V (PECL) 2.25 45 45 45 50 50 50 50 MAX. UNITS 100/80/40 3.63 55 55 55 mA V % mA Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/28/09 Page 2 PL620-80 Low Phase Noise XO (9.5-65MHz Output) 4. Jitter Specifications PARAMETERS CONDITIONS MIN. TYP. MAX. 20 Period jitter RMS at 27MHz Period jitter peak-to-peak at 27MHz With capacitive decoupling between VDD and GND. Over 10,000 cycles 2.3 18.5 Accumulated jitter RMS at 27MHz With capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 2.3 Accumulated jitter peak-to-peak at 27MHz Random Jitter 24 25 2.3 UNITS ps ps ps Measured on Wavecrest SIA 3000 5. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS 27MHz -75 -100 -125 -140 -145 dBc/Hz Phase Noise relative to carrier Note: Phase Noise measured on Agilent E5500 6. CMOS Output Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Output drive current (High Drive) I OH I OL VOH = VDD -0.4V, V DD =3.3V VOL = 0.4V, V DD = 3.3V 30 30 mA mA Output drive current (Standard Drive) Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive) I OH I OL VOH = VDD -0.4V, V DD =3.3V VOL = 0.4V, V DD = 3.3V 10 10 mA mA 0.3V ~ 3.0V with 15 pF load 2.4 0.3V ~ 3.0V with 15 pF load 1.2 ns Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/28/09 Page 3 PL620-80 Low Phase Noise XO (9.5-65MHz Output) 7. LVDS Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS 355 454 mV 50 1.6 Output Differential Voltage VOD 247 VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change V OD VOH VOL VOS -50 Power-off Leakage I OXD Output Short Circuit Current I OSD R L = 100  (see figure) 0.9 1.125 0 V OS Vout = VDD or GND VDD = 0V 1.4 1.1 1.2 3 1.375 25 mV V V V mV 1 10 uA -5.7 -8 mA 8. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100  C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50 VO D VO S VDIF F RL = 100  50 CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIF F 80% 0V 20% 20% tR tF Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/28/09 Page 4 PL620-80 Low Phase Noise XO (9.5-65MHz Output) 9. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. VOH VOL R L = 50 to (VDD – 2V) (see figure) VDD – 1.025 Output High Voltage Output Low Voltage MAX. UNITS VDD – 1.620 V V 10. PECL Switching Characteristics PARAMETERS SYMBOL Clock Rise Time Clock Fall Time tr tf CONDITIONS MIN. @20/80% - PECL @80/20% - PECL PECL Levels Test Circuit OUT MAX. UNITS 0.6 0.5 1.5 1.5 ns ns PECL Output Skew VDD 50 TYP. OUT 2.0V 50% 50 OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/28/09 Page 5 PL620-80 Low Phase Noise XO (9.5-65MHz Output) PAD DESCRIPTIONS Pad # Name X (m) Y (m) Description 1 2 3 4 5 GND GND Optional GND GND GND 248 361 473 587 702 109 109 109 109 109 Ground. Ground. Optional Ground. Ground. Ground. 6 7 8 Reserved GNDBUF GNDBUF 874 1042 1171 109 109 109 9 OE_SEL 1400 125 10 11 12 13 14 LVDS PECL VDDBUF VDDBUF PECLB 1400 1400 1400 1400 1400 259 476 616 716 871 Reserved for future use. Ground, buffer circuitry. Ground, buffer circuitry. This is the selector input to choose the OE control logic. See the OE SELECTION AND ENABLE table on page 1. Internal pull up. LVDS output. PECL output. Power supply, buffer circuitry. Power supply, buffer circuitry. Complementary PECL output. 15 16 17 LVDSB CMOS GNDBUF 1400 1400 1389 1089 1227 1365 18 OUTSEL1 1232 1365 19 20 Reserved Not connected 1042 854 1365 1365 Complementary LVDS output. CMOS output. Ground, buffer circuitry. Selector input to choose the selected output type (PECL, LVDS, CMOS). See the OUTPUT SELECTION AND ENABLE table on page 1. Internal pull up. Reserved for future use. Not Connected. 21 22 23 VDD Optional VDD VDD 659 559 459 1365 1365 1365 Power supply. Optional Power supply. Power supply. 24 VDD 358 1365 25 OUTSEL0 194 1365 26 XIN 109 1223 Power supply. Selector input to choose the selected output type (PECL, LVDS, CMOS). See the OUTPUT SELECTION AND ENABLE table on page 1. Internal pull up. Crystal input. See Crystal Specifications on page 3. 27 28 XOUT Not connected 109 109 1017 858 29 S2 109 646 30 OE_CTRL 109 397 31 Not connected 109 181 Crystal output. See Crystal Specifications on page 3. Not Connected. Output Divide by Two selector pin, as presented on the OUTPUT FREQUENCY SELECTOR Table on page 1. Internal pull up. Used to enable/disable the output(s). See Output Selection and Enable table on page 1. Not connected. Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/28/09 Page 6 PL620-80 Low Phase Noise XO (9.5-65MHz Output) ORDERING INFORM ATION For part ordering, please contact our Sales Department: 2180 Fortune Drive, San Jose, CA 95131, USA Tel: (408) 944-0800 Fax: (408) 474-1000 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Oper ating temperature range PL 620-80 DC PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE D=DIE Order Number Marking Package Option PL620-80DC P620-80DC Die – Waffle Pack Micrel Inc., reserves the right to make changes in its products or specifications, or both at any time without notice. The in formation furnished by Micrel is believed to be acc urate and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: Micrel’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Micrel Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/28/09 Page 7