PL680-39OC

38-640MHz Low Phase Noise XO FEATURES XIN 2 15 SEL1^ XOUT 3 14 GNDBUF SEL2^ 4 13 QBAR OE_CTRL 5 12 VDDBUF DNC 6 11 Q GNDANA 7 10 GNDBUF LP 8 9 LM The PL680-3X is a monolithic low jitter and low phase noise high performance clock, capable of producing 0.4ps RMS phase jitter and LVCMOS, LVDS or LVPECL outputs, covering a wide frequency output range up to 640MHz. It allows high performance and high frequency output, using a low cost fundamental crystal of 19MHz to 40MHz. The frequency selector pads of PL680-3X enable output frequencies of (2, 4, 8, or 16) * F XIN . The PL680-3X is designed to address the demanding requirements of high performance applications such Fiber Channel, serial ATA, Ethernet, SAN, etc. 12 13 SEL2^ 14 OE_CTRL 15 DNC 16 11 10 9 PL680-3X 1 GNDANA DESCRIPTION XOUT SEL1^ 16-pin TSSOP 2 3 4 GNDBUF     SEL0^ SEL0^  16 LM  1 VDDANA  VDDANA LP  Less than 0.4ps RMS (12kHz - 20MHz) phase jitter for all frequencies. Less than 25ps peak to peak period jitter for all frequencies. Low phase noise output (@ 1MHz offset) o -144dBc/Hz for 106.25MHz o -144dBc/Hz for 156.25MHz o -144dBc/Hz for 212.5MHz o -140dBc/Hz for 312.5MHz, o -131dBc/Hz for 622.08MHz Fundamental Crystal Input Frequency: o 19MHz to 40MHz (3.3V) o 19MHz to 28.125MHz (2.5V) Output Frequency: o 38MHz to 640MHz (3.3V) o 38MHz to 450MHz (2.5V) Available in LVPECL, LVDS, or LVCMOS outputs. Output Enable selector. 2.5V ~ 3.3V operation. Available in 3x3 QFN or 16-pin TSSOP packages. XIN  PACKAGE PIN ASSIGNMENT 8 GNDBUF 7 QBAR 6 VDDBUF 5 Q 3x3 QFN Note1: QBAR is used for single ended CMOS output. Note2: ^ Denotes 60kΩ internal pull up resistor. SEL[0:2] BLOCK DIAGRAM VCO Divider XIN XOUT Xtal Osc Phase Detector Charge Pump + Loop Filter VCO (FXiNx16) Performance Tuner Output Divider (1,2,4,8) QBAR Q OE 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/14/07 Page 1 38-640MHz Low Phase Noise XO OUTPUT ENABLE LOGIC LEVELS Part # PL680-38 (LVPECL) PL680-37 & 39 (LVCMOS or LVDS) OE State 0 (Default) Output enabled 1 Tri-state 0 Tri-state 1 (Default) Output enabled PIN DESCRIPTIONS TSSOP-16L Pin number QFN-16L Pin number Type VDDANA 1 11 P VDD for analog Circuitry. XIN 2 12 I Crystal input pin. (See Crystal Specifications on page 4). XOUT 3 13 O Crystal output pin. (See Crystal Specifications on page 4). SEL2 4 14 I Output frequency Selector pin. OE_CTRL 5 15 I Output enable control pin. (See OUTPUT ENABLE LOGIC LEVELS above). DNC 6 16 - Do Not Connect GNDANA 7 1 P Ground for analog circuitry. LP 8 2 - LM 9 3 - GNDBUF 10 4 P GND connection for output buffer circuitry. Q 11 5 O LVPECL or LVDS output. VDDBUF 12 6 P VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. QBAR 13 7 O Complementary LVPECL, LVDS output; Or single ended LVCMOS output. GNDBUF 14 8 P GND connection for output buffer circuitry. SEL1 15 9 I Output frequency Selector pin. SEL0 16 10 I Output frequency Selector pin. Name Description Tuning inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between LP and adjacent LM pin. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/14/07 Page 2 38-640MHz Low Phase Noise XO FREQUENCY SELECTION TABLE SEL2 SEL1 SEL0 Selected Multiplier/Output Frequency 0 0 0 VCO Max* 0 0 1 VCO Min* 0 1 0 Reserved 0 1 1 Reserved 1 0 0 Fin x 2 1 0 1 Fin x 8 1 1 0 Fin x 16 1 1 1 Fin x 4 All SEL pads have a 60kΩ internal pull-up resistor (default value is ‘1’). Bond to GND to set to 0. * Special Test Modes to help selecting the inductor value for the target output frequency. PERFORMANCE TUNING & INDUCTOR VALUE SELECTION Please refer to PhaseLink’s ‘PhasorV Tuning Assistance’ software to automatically calculate the optimum inductor values. In addition, the chart below could be used as a reference for quick inductor value selection. Use the special test modes “VCO Max” and “VCO Min” to determine the optimum inductor value. “VCO Max” represents the high end of the VCO range and “VCO Min” represents the low end of the VCO range. The output frequency in the “VCO Max” and “VCO Min” test modes is VCO/16. This means that the output frequencies are around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency is closest to the middle between the “VCO Max” and “VCO Min” output frequencies. In this case the VCO will lock in the middle of its tuning range with maximum margin on either side. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/14/07 Page 3 38-640MHz Low Phase Noise XO ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage MIN. MAX. UNITS 4.6 V V DD Input Voltage, dc VI -0.5 V DD +0.5 V Output Voltage, dc VO -0.5 V DD +0.5 V Storage Temperature TS -65 150 C Ambient Operating Temperature* TA -40 85 C Junction Temperature TJ 125 C 260 C Lead Temperature (soldering, 10s) Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied.* Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS SYMBOL Crystal Resonator Frequency F XIN Crystal Loading Rating C L (xtal) Crystal Shunt Capacitance C 0 (xtal) Recommended ESR RE CONDITIONS MIN. TYP. MAX. Parallel Fundamental Mode, 3.3V 19 40 Parallel Fundamental Mode, 2.5V 19 28.125 18 AT cut UNITS MHz pF 5 pF 30 Ω Note: Crystal Loading rating: 18 pF is the loading the crystal sees from the XO chip. It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires less load to be at nominal frequency, then a capacitor can placed in series with the crystal. If the crystal requires more load to be at nominal frequency, capacitors can be placed from XIN and XOUT to ground. This however may reduce the oscillator gain. 3. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS Supply Current, Dynamic (Loaded Outputs) 65/45/30 I DD LVPECL/LVDS 38MHz