PL903101UMG-T5

PL903xxx Revision 1.0 General Description Features The PL903xxx series is a small form factor, high performance OTP-base device and a member of Micrel’s JitterBlocker, factory programmable jitter attenuators. The JitterBlocker product family cleans deterministic jitter by attenuating spurious components in the phase noise, thereby improving the phase jitter and the overall phase noise. The PL903xxx is capable of reducing multiple pico seconds of phase jitter in a clock to a level below 1psRMS, making that clock usable for many more applications. • • • • • The PL903xxx operates on a single 2.5V or 3.3V supply and is housed in a small QFN package for a broad range of applications. Input clock frequencies up to 200MHz can be filtered and frequency translation allows for output clock frequencies up to 840MHz. • • • • • Datasheets and support documentation are available on Micrel’s web site at: www.micrel.com. Block Diagram Lowest-power, smallest programmable jitter attenuator Input frequency up to 200MHz Output frequency up to 840MHz Jitter attenuation 20dB at 3MHz spur frequency Additive phase jitter or phase jitter floor: − 55fs for 1.875MHz to 20MHz − 251fs for 12kHz to 20MHz Single ended CMOS input One differential or two single ended outputs. Output logic types supported are LVPECL, LVDS, HCSL and LVCMOS (single ended or differential). Operating temperature range from –40°C to +85°C Available in 24-pin QFN RoHS-compliant package. Related devices: − PL902xxx: LVCMOS, period jitter cleaning. − PL904xxx: Differential input, two differential outputs, phase noise cleaning Applications • • • • • • • 1/10/40/100 Gigabit Ethernet (GbE) SONET/SDH PCI Express CPRI/OBSAI wireless base stations Fibre Channel SAS/SATA DIMM Ripple Blocker is a trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com October 2, 2014 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. PL903xxx Ordering Information Part Number Marking Shipping Ambient Temp. Range Package PL903xxxUMG PL903 XXX Tray –40° to +85°C QFN-24L PL903xxxUMG TR PL903 XXX Tape and Reel –40° to +85°C QFN-24L Pin Configuration 24-Pin QFN Pin Description Pin Number Pin Name Pin Type Pin Level Pin Function 22 23 Q /Q O Various Clock output. (1) Can be programmed to one of the following logic types: LVPECL, LVDS, HCSL, or LVCMOS. 3 REFIN I, (SE) Various Reference clock input. Can be programmed to either LVCMOS levels or smaller amplitude signals from other logic types. 12 OE I LVCMOS 1, 20 VDD PWR Core power supply. 17, 24 VDDO PWR Output buffer power supply. 2, 8, 13, 14 15, 21 VSS PWR Power supply ground. 4, 5, 7, 9, 11 16, 18 TEST 6, 10, 19 NC ePad Exposed Pad Output enable control input with pull-up (45kΩ). Used for production test Do not connect anything to these pins. Not internally connected. No need to connect anything to these pins. The center pad must be connected to the ground plane both for electrical ground and thermal relief. GND Note: 1. In case of LVCMOS, the output pair can provide two single-ended LVCMOS outputs. October 2, 2014 2 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. PL903xxx Functional Description PL903xxx series is a very flexible, advanced programmable jitter filter design for high performance, small form-factor applications. The PL903xxx accepts a reference clock input between 12MHz and 200MHz and is capable of producing one differential output up to 840MHz or two single ended outputs up to 250MHz. The most common configuration will be with the same input and output frequency but this flexible design also allows frequency translation from one frequency to another frequency, as long as both frequencies are within the specified ranges for input and output. Jitter Attenuation Typically the jitter attenuation settings will be optimized for one particular input and output frequency. Customization of attenuation properties is possible. Output Frequency The most common configuration is where the output frequency is the same as the input frequency. However, frequency translations are possible. The input frequency upper limit is 200MHz, but the output can go up to 840MHz. The lowest possible output phase jitter, or phase jitter floor, is 251fs for the 12kHz to 20MHz integration range and 55fs for the Gigabit Ethernet integration range of 1.875MHz to 20MHz. The PL903xxx excels at attenuating deterministic jitter that presents itself as spurs in the phase noise plot above 1MHz. Output Enable (OE) The Output Enable feature allows the user to enable and disable the clock output(s) by toggling the OE pin. The OE pin incorporates a 45kΩ pull-up resistor giving a default condition of logic “1” that enables the output(s). Clock Output The output pins Q and /Q make a differential output that can be programmed to several different logic types: LVPECL, LVDS, HCSL or LVCMOS. In the case of LVCMOS, there are three possible configurations: Reference (Noisy) Clock Input (REFIN) The input requires a single-ended CMOS signal. The frequency range for the input is 12MHz to 200MHz. 1. One single-ended output with the complementary pin disabled to a high impedance. 2. Two single-ended, in-phase outputs. 3. A differential output with opposite phases at the two output pins October 2, 2014 3 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. PL903xxx Absolute Maximum Ratings(2) Operating Ratings(3) Supply Voltage (VDD, VDDO) ......................................... +4.6V Input Voltage (VIN) ................................ −0.5V to VDD + 0.5V Lead Temperature (soldering, 20s) ............................ 260°C Case Temperature ..................................................... 115°C Storage Temperature (Ts)......................... –65°C to +150°C Supply Voltage (VDD, VDDO) .................. +2.375V to +3.465V Ambient Temperature (TA) .......................... –40°C to +85°C (4) Junction Thermal Resistance (θJA), Still-Air ...................................................... 50°C/W DC Electrical Characteristics(5) VDD = VDDO = 3.3V ±5% or 2.5V ±5%; TA = –40°C to +85°C. Symbol Parameter VDD Power supply voltage IDD Total supply current, VDD + VDDO Condition Min. Typ. 2.375 Max. Units 3.465 V LVPECL, 312.5MHz Outputs open 100 120 mA HCSL (PCIe), 100MHz Outputs terminated with 50Ω to VSS 80 100 mA 2 × LVCMOS, 125MHz Outputs open 70 90 mA Typ. Max. Units LVCMOS Inputs (OE, REFIN) DC Electrical Characteristics(5) VDD = VDDO = 3.3V ±5% or 2.5V ±5%; TA = –40°C to +85°C. Symbol Parameter Condition Min. VIH Input high voltage 70% VDD VDD + 0.3 V VIN Input low voltage VSS – 0.3 30% VDD V IIH Input high current VDD = VIN = 3.465V 150 µA IIL Input low current VDD = 3.465V, VIN = 0V –150 µA Notes: 2. Exceeding the absolute maximum ratings may damage the device. 3. The device is not guaranteed to function outside its operating ratings. 4. Package thermal resistance assumes the exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. 5. The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables after thermal equilibrium has been established. October 2, 2014 4 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. PL903xxx LVDS Output DC Electrical Characteristics(5) VDD = VDDO = 3.3V ±5% or 2.5V ±5%; TA = –40°C to +85°C, RL = 100Ω across Q and /Q. Symbol Parameter Condition Min. Typ. Max. Units VOD Differential output voltage Figure 6 275 350 475 mV ΔVOD VOD magnitude change 40 mV VOS Offset voltage 1.50 V ΔVOS VOS magnitude change 50 mV 1.15 1.25 HCSL Output DC Electrical Characteristics(5) VDD = VDDO = 3.3V ±5% or 2.5V ±5%; TA = –40°C to +85°C, RL = 50Ω to VSS Symbol Parameter Condition Min. Typ. Max. Units VOH Output high voltage Figure 1, Figure 5 660 700 850 mV VOL Output low voltage Figure 1, Figure 5 −150 0 27 mV VSWING Output voltage swing Figure 1, Figure 5 630 700 1000 mV Min. Typ. Max. Units LVPECL Output DC Electrical Characteristics(5) VDD = VDDO = 3.3V ±5% or 2.5V ±5%; TA = –40°C to +85°C, RL = 50Ω to VDD − 2V Symbol Parameter Condition VOH Output high voltage Figure 1, Figure 4 VDD – 1.145 VDD – 0.97 VDD – 0.845 V VOL Output low voltage Figure 1, Figure 4 VDD – 1.945 VDD – 1.77 VDD – 1.645 V VSWING Output voltage swing Figure 1, Figure 4 0.6 0.8 1.0 V Typ. Max. Units LVCMOS Output DC Electrical Characteristics(5) VDD = VDDO = 3.3V ±5% or 2.5V ±5%; TA = –40°C to +85°C, RL = 50Ω to VDD/2 Symbol Parameter Condition VOH Output high voltage Figure 1, Figure 7 VOL Output low voltage Figure 1, Figure 7 October 2, 2014 Min. 5 VDD – 0.7 V 0.6 V Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. PL903xxx LVPECL AC Electrical Characteristics(5, 6, 7, 11) VDD = VDDO = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C, unless otherwise noted. Symbol Parameter FOUT Output frequency TR/TF LVPECL output rise/fall time ODC Output duty cycle TLOCK PLL lock time Tjit(∅) RMS phase jitter @ 156.25MHz with clean input signal. Condition Min. Typ. 12 Max. Units 840 MHz 20% – 80% 80 175 350 ps < 350MHz 48 50 52 % ≥ 350MHz 45 50 55 % 20 ms Integration range (12kHz to 20MHz) 251 fs Integration range (1.875MHz to 20MHz) 55 fs Notes: 6. See Figures 4 through 7 for load test circuit examples. 7. All phase noise measurements were taken with an Agilent 5052B phase noise system. LVDS AC Electrical Characteristics(5, 6, 7, 8) VDD = VDDO = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C, unless otherwise noted. Symbol Parameter FOUT Output frequency TR/TF LVDS output rise/fall time ODC Output duty cycle TLOCK PLL lock time Tjit(∅) RMS phase jitter @ 156.25MHz Condition Min. Typ. 12 Max. Units 840 MHz 20% – 80% 100 160 400 ps < 350MHz 48 50 52 % ≥ 350MHz 45 50 55 % 20 ms Integration range (1.875MHz to 20MHz) 60 fs HCSL AC Electrical Characteristics(5, 6, 7, 9) VDD = VDDO = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C, unless otherwise noted. Symbol Parameter FOUT Output frequency TR/TF Output rise/fall time ODC Output duty cycle TLOCK PLL lock time Tjit(∅) RMS phase jitter @ 100MHz October 2, 2014 Condition Min. Typ. 12 Max. Units 840 MHz 20% – 80% 150 300 450 ps < 350MHz 48 50 52 % ≥ 350MHz 45 50 55 % 20 ms Integration range (12kHz to 20MHz) 6 250 fs Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. PL903xxx LVCMOS AC Electrical Characteristics(5, 6, 7, 10) VDD = VDD = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C, unless otherwise noted. Symbol Parameter FOUT Output frequency FREF Condition Min. Max. Units 12 250 MHz REFIN frequency 12 200 MHz VREF REFIN amplitude 40% VDD VDD + 0.6 VPP TR/TF Output rise/fall time 100 500 ps ODC Output duty cycle 55 % TLOCK PLL lock time 20 ms Tjit(∅) RMS phase jitter @ 125MHz 20% – 80% 45 Integration range: 1.875MHz to 20MHz Typ. 50 55 fs Notes: 8. Outputs terminated 100Ω between Q and /Q. All unused outputs must be terminated. 9. Output load is 50Ω to VSS. 10. Output load is 50Ω to VDD/2. 11. Output load is 50Ω to VDD – 2V October 2, 2014 7 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. PL903xxx Power Supply Filtering Recommendations Preferred filter, using Micrel’s MIC94300 or MIC94310 Ripple Blocker™: Alternative, traditional filter, using a ferrite bead: Output Traces Design the traces for the output signals according to the output logic requirements. If LVCMOS is unterminated, add a 30Ω resistor in series with the output, as close as possible to the output pin, and start a 50Ω trace on the other side of the resistor. Application Information Power Supply Decoupling Place the smallest value decoupling capacitor (4.7nF above) between the VDD and VSS pins, as close as possible to those pins and at the same side of the PCB as the IC. The shorter the physical path from VDD to capacitor and back from capacitor to VSS, the more effective the decoupling. Use one 4.7nF capacitor for each VDD pin on the PL903xxx. For differential traces, you can either use a differential design or two separate 50Ω traces. For EMI reasons, it is better to use a differential design. LVDS can be AC-coupled or DC-coupled to its termination. The impedance value of the ferrite bead (FB) needs to be between 240Ω and 600Ω with a saturation current ≥150mA. VDDO pins connect directly to the VDD plane. All VDD pins on the PL903xxx connect to VDD after the power supply filter. October 2, 2014 8 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. PL903xxx Figure 1. Duty Cycle Timing Figure 2. All Outputs Rise/Fall Time Figure 3. RMS Phase Noise Jitter Figure 4. LVPECL Output Load and Test Circuit October 2, 2014 9 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. PL903xxx Figure 5. HCSL Output Load and Test Circuit Figure 6. LVDS Output Load and Test Circuit Figure 7. LVCMOS Output Load and Test Circuit October 2, 2014 10 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. PL903xxx Jitter Attenuation Performance The jitter attenuating frequency response was measured at 156.25MHz. 10 Jitter Attenuation (dB) 0 -10 -20 -30 -40 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 Jitter / Modulation Frequency (Hz) The jitter attenuation works like a low-pass filter for frequency modulated signals or noise. The bandwidth for this low-pass filter is 900kHz with a 12dB/octave slope above 900kHz. At about 6MHz the noise floor of this measurement is reached but in reality, the attenuation continues with the 12dB/octave slope. October 2, 2014 11 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. PL903xxx Phase noise performance with a clean input clock. 156.25MHz with 55fsRMS of phase jitter for 1.875MHz to 20MHz integration range 156.25MHz with 251fsRMS of phase jitter for 12kHz to 20MHz integration range October 2, 2014 12 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. PL903xxx Example 156.25MHz input test clock with bad phase jitter caused by a 3MHz spur. 156.25MHz with 1.1psRMS of phase jitter for 1.875MHz to 20MHz integration range Output clock from PL903xxx. 156.25MHz with 104fsRMS of phase jitter for 1.875MHz to 20MHz integration range The 3MHz spur is attenuated by 20dB, resulting in a phase jitter reduction from 1.1ps to 0.10ps. October 2, 2014 13 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. PL903xxx Package Information(12) 24-Pin QFN Note: 12. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com. October 2, 2014 14 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. PL903xxx MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high performance linear and power, LAN, and timing & communications markets. The Company’s products include advanced mixed-signal, analog & power semiconductors; high-performance communication, clock management, MEMs-based clock oscillators & crystal-less clock generators, Ethernet switches, and physical layer transceiver ICs. Company customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and computer products. Corporation headquarters and state-of-the-art wafer fabrication facilities are located in San Jose, CA, with regional sales and support offices and advanced technology design centers situated throughout the Americas, Europe, and Asia. Additionally, the Company maintains an extensive network of distributors and reps worldwide. Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this datasheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2014 Micrel, Incorporated. October 2, 2014 15 Revision 1.0 tcghelp@micrel.com or (408) 955-1690 Micrel, Inc. October 2, 2014 PL903xxx 16 Revision 1.0 tcghelp@micrel.com or (408) 955-1690