PS10NG-G

Supertex inc. PS10 Quad Power Sequencing Controller Features General Description ►► Sequencing of four supplies, ICs, or subsystems ►► Independently programmable delays between open drain PWRGD flags (5.0 to 200ms) ►► ±10 to ±90V operation ►► Tracking in combination with Schottky diodes ►► Input supervisors including: • UV/OV lock out/enable • Power-on-Reset (POR) ►► Low power consumption, 0.4mA supply current ►► Available in a space saving 14-Lead SOIC package Many of today’s high performance FPGA’s, microprocessors, DSP and industrial/embedded subsystems require sequencing of the input power. Historically this has been accomplished by: i) discretely using comparators, references & RC circuits; ii) using expensive programmable controllers; or iii) with low voltage sequencers requiring resistor drop downs and several high voltage optocoupler or level shift components. The PS10 saves board space, improves accuracy, eliminates optocouplers or level shifts and reduces overall component count by combining four timers, programmable input UV/OV supervisors, a programmable POR, and four 90V open drain outputs. A high reliability, high voltage, junction isolated process allows the PS10 to be connected directly across the high voltage input rails. Applications ►► Power supply sequencing ►► -48V telecom and networking distributed systems ►► -24V cellular and fixed wireless systems ►► -24V PBX systems ►► +48V storage systems ►► FPGA, microprocessor tracking ►► Industrial/embedded system timing/sequencing ►► High voltage MEMs driver’s supply sequencing ►► High voltage display driver’s supply sequencing The power-on-reset interval (POR) may be programmed by a capacitor on CRAMP. To sequence additional systems, multiple PS10s may be daisy-chained together. If at any time the input supply falls outside the UV/OV detector range, the PWRGD outputs will immediately become IN-ACTIVE. The PS10 is available in a space saving 14-Lead SOIC package. Typical Application Circuit GND or +48V 14 487kΩ 6 PS10 5 7 Doc.#DSFP-PS10 C080613 PWRGD-C PWRGD-B OV VEE TB TC 11 RTB -48V or GND PWRGD-D UV 6.81kΩ 9.76kΩ /EN VIN TD 12 RTC PWRGD-A RAMP 13 RTD 10 10nF 1 2 3 4 DC/DC Converter /EN DC/DC Converter /EN DC/DC Converter /EN DC/DC Converter +12V COM +5V COM +3.3V COM +2.5V COM Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. Supertex inc. www.supertex.com PS10 Pin Configuration Ordering Information Part Number Package Option Packing PS10NG-G 14-Lead SOIC 53/Tube PS10NG-G-G M905 14-Lead SOIC 2500/Reel 14 1 -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value VEE referenced to VIN pin +0.3V to -100V VPWRGD referenced to VEE voltage -0.3V to +100V VUV and VOV referenced to VEE voltage (top view) -0.3V to 12V Operating ambient temperature -40°C to +85°C Operating junction temperature -40°C to +125°C Storage temperature range 14-Lead SOIC Product Marking Top Marking -65° to +150°C Power dissipation @ 25 C PS10NG 750mW O YWW Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. LLLLLLLL Bottom Marking CCCCCCCCC AAA *May be part of top marking PWRGD Logic Condition Package may or may not include the following marks: Si or PWRGD-A/B/C/D Inactive (not ready) 0 VEE Active (ready) 1 Hi Z Electrical Characteristics (-10V ≤ V IN Sym Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = “Green” Packaging 14-Lead SOIC Typical Thermal Resistance Package θja 14-Lead SOIC 75OC/W* ≤ -90V, TA = 25°C unless otherwise specified) Parameter Min Typ Max Units Conditions Supply (Referenced to VIN pin) VEE Supply voltage - -90 - -10 V --- IEE Supply current - - 400 450 µA VEE = -48V OV and UV Control (Referenced to VEE pin) VUVH UV high threshold # 1.16 1.22 1.28 V Low to high transition VUVL UV low threshold # 1.06 1.12 1.18 V High to low transition VUVHY UV hysteresis # - 100 - mV --- UV input current - - - 1.0 nA VUV = VEE + 1.9V VOVH OV high threshold # 1.16 1.22 1.28 V Low to high transition VOVL OV low threshold # 1.06 1.12 1.18 V VOVHY OV hysteresis # - 100 - mV --- OV input current - - - 1.0 nA VUV = VEE + 1.9V IUV IOV High to low transition # Specifications apply over 0OC ≤ TA ≤ 70OC Doc.#DSFP-PS10 C080613 2 Supertex inc. www.supertex.com PS10 Electrical Characteristics (cont.) (-10V ≤ V IN Sym ≤ -90V, TA = 25°C unless otherwise specified) Parameter Min Typ Max Units Conditions Power Good Timing (Test Conditions: CRAMP = 10nF, VUV = VEE + 1.9V, VOV = VEE + 0.5V) IRAMP Ramp pin output current - - 10 - µA --- tPWRGD-A Time from UV high to PWRGD-A - - 8.8 - ms VEE = -48V, CRAMP = 10nF, see typical application circuit tPWRGD-B Maximum time from PWRGD-A to PWRGD-B - 150 200* 250 ms RTB = 120kΩ tPWRGD-B Minimum time from PWRGD-A to PWRGD-B - 3.0 5.0* 8.0 ms RTD = 3.0kΩ tPWRGD-C Maximum time from PWRGD-B to PWRGD-C - 150 200* 250 ms RTB = 120kΩ tPWRGD-C Minimum time from PWRGD-B to PWRGD-C - 3.0 5.0* 8.0 ms RTD = 3.0kΩ tPWRGD-D Maximum time from PWRGD-C to PWRGD-D - 150 200* 250 ms RTB = 120kΩ tPWRGD-D Minimum time from PWRGD-C to PWRGD-D - 3.0 5.0* 8.0 ms RTD = 3.0kΩ * Variations will track. For example if tPWRGD-A is 250ms, then so will be tPWRGD-B/C/D. Contact factory for tighter tolerance version. Power Good Outputs (Test Conditions: VUV = VEE + 1.9V, VOV = VEE + 0.5V) VPWRGD-X(hi) Power good pin breakdown voltage - 90 - - V VPWRGD-X(lo) Power good pin output low voltage - - 0.4 0.5 V IPWRGD-X(lk) Maximum leakage current - -