QT1081-ISG

QT1081 lQ 8-KEY QTOUCH™ SENSOR IC SNS5K SNS6K SNS6 2 3 4 5 11 SNS2K 10 SNS2 9 SN1K 8 OUT_4 29 OUT_5 30 OUT_6 31 6 7 SNS0 SNS0K 1 OSC N/C OUT_7 32 SNS1 QT1081 32-QFN 14 SNS4 13 SNS3K 12 SNS3 OUT_2 27 OUT_3 28 VDD QTouch™ sensors employ a single reference capacitor tied to two pins of the chip for each sensing key; a signal trace leads from one of the pins to the sensing electrode which forms the key. The sensing electrode can be a simple solid shape such as a rectangle or circle. An LED can be placed near or inside the solid circle for illumination. 24 23 22 21 20 19 18 17 16 SNS5 15 SNS4K SS QTouch circuits are renowned for simplicity, reliability, ease of design, and cost effectiveness. OUT_0 25 OUT_1 26 /RST QTouch™ technology is a type of patented charge-transfer sensing method well known for its robust, stable, EMC-resistant characteristics. It is the only all-digital capacitive sensing technology in the market today. This technology has over a decade of applications experience spanning thousands of designs. SNS7K SNS7 The QT1081 is an improved, lower cost, simplified circuit version of the popular QT1080 sensor IC. The QT1081 is designed for low cost appliance, mobile, and consumer electronics applications. SYNC/LP VSS DETECT This datasheet is applicable to all revision 1 chips The key electrodes can be designed into a conventional printed circuit board (PCB) or flexible printed circuit board (FPCB) as a copper pattern, or as printed conductive ink. The QT1081 is also compatible with clear films to make simple button-style touch screens over LCD displays. AT A GLANCE Number of keys: 1 to 8 Technology: Patented spread-spectrum charge-transfer (one-per-key mode) Key outline sizes: 5mm x 5mm or larger (panel thickness dependent); widely different sizes and shapes possible Key spacings: 6mm or wider, center to center (panel thickness, human factors dependent) Electrode design: Single solid or ring shaped electrodes; wide variety of possible layouts Layers required: One layer substrate; electrodes and components can be on same side Substrates: FR-4, low cost CEM-1 or FR-2 PCB materials; polyamide FPCB; PET films, glass Electrode materials: Copper, silver, carbon, ITO, Orgacon† ink (virtually anything electrically conductive) Panel materials: Plastic, glass, composites, painted surfaces (low particle density metallic paints possible) Adjacent Metal: Compatible with grounded metal immediately next to keys Panel thickness: Up to 50mm glass, 20mm plastic (key size dependent) Key sensitivity: Settable via change in reference capacitor (Cs) value Outputs: Parallel discrete output, one-per-key, active-high Moisture tolerance: Good Power: 2.8V ~ 5.0V, 150µs to guarantee that the QT1081 will recognise that level. Low Power LP Mode: LP mode allows the device to be switched between full speed operation (20ms typical response time and normal power consumption), and Low Power operation (low average power consumption but an increased maximum response time) according to the needs of the application. There are three maximum response time settings for low power operation: 100ms, 180ms, and 340ms nominal; the response time setting is determined by option resistors SL_1 and SL_0; see Table 1.5. Slower response times result in a lower average power drain. Circuit of Figure 1.2: Binary coded not available. lQ 8 QT1081_1R0.04_0307 Operation in low power mode is governed by the state of the LP input and whether at least one key has a confirmed touch. Figure 2.5 LP Pin High at End of Touch etouch If the LP input is at a constant low level, then the QT1081 will remain in full speed operation (20ms typical response time and normal power consumption), as in Figure 2.2. LP pin Figure 2.2 Full Speed Operation bursts touch low power full speed low power LP pin Note that the LP input must remain at one level (high or low) for >150µs to guarantee that the QT1081 will recognise that level. bursts full speed operation If the LP input is at a constant high level, then the QT1081 will enter low power operation whenever it is not detecting a touch. It will switch automatically to full speed operation while there is a touch, and revert to low power operation at the end of the touch. This is shown in Figure 2.3. Figure 2.3 Low Power/Full Speed Operation etouch Optimization of LP Mode: For the lowest possible power consumption when up to four keys are required, all keys should be connected to QT1081 channels that are measured during acquire burst B (i.e. k2, k3, k6 and k7). If this is done the QT1081 automatically selects optimized LP operation, which gives a significantly lower power consumption than would be achieved if the burst A channels were used. Optimized LP operation is identical to the standard LP operation in all other ways; it is controlled as described above. 2.7 AKS™ Function Pins The QT1081 features an adjacent key suppression (AKS) function with two modes. Option resistors act to set this feature according to Tables 1.2 and 1.6. AKS can also be disabled, allowing any combination of keys to become active at the same time. When operating, the modes are: LP pin bursts low power full speed Global: AKS functions operates across all eight keys. This means that only one key can be active at any one time. low power While there is no touch, if the LP input is driven high then low, the QT1081 will enter low power operation, as described above, and remain in low power operation when LP is taken low. When there is a touch the QT1081 will switch automatically to full speed operation. At the end of the touch the choice of operation depends on the state of the LP input. This is shown in Figures 2.4 and 2.5 - the first with the LP pin being low at the end of the touch, and the second with the LP pin being high at the end of the touch. Figure 2.4 LP Pin Low at End of Touch etouch LP pin Groups: AKS functions among two groups of four keys: 0-1-4-5 and 2-3-6-7. This means that up to two keys can be active at any one time. In Group mode, keys in one group have no AKS interaction with keys in the other group. Note that in Fast Detect mode, AKS can only be off. 2.8 MOD_0, MOD_1 Inputs In full option mode, MOD_0 and MOD_1 resistors are used to set the ‘Max On-Duration’ recalibration timeouts. If a key becomes stuck on for a lengthy duration of time, this feature will cause an automatic recalibration event of that specific key once the specified on-time has been exceeded. Settings of 10s, 60s, and infinite are available. The Max On-Duration feature operates on a key-by-key basis; when one key is stuck on, its recalibration has no effect on other keys. bursts low power The logic combination on the MOD option pins sets the timeout delay (see Table 1.3). full speed Simplified mode MOD timing: In simplified mode, the max on-duration is fixed at 60 seconds. 2.9 Fast Detect Mode lQ 9 QT1081_1R0.04_0307 In many applications, it is desirable to sense touch at high speed. Examples include scrolling ‘slider’ strips or ‘Off’ buttons. It is possible to place the device into a ‘Fast Detect’ mode that usually requires under 10ms to respond. This is accomplished internally by setting the Detect Integrator to only two counts, i.e. only two successive detections are required to detect touch. In LP mode, ‘Fast’ detection will not speed up the initial delay (which could be up to 340ms nominal depending on the option setting). However, once a key is detected the device is forced back into normal speed mode. It will remain in this faster mode until requested to return to LP mode. When used in a ‘slider’ application, it is normally desirable to run the keys without AKS. In both normal and ‘Fast’ modes, the time required to process a key release is the same. It takes six sequential confirmations of nondetection to turn a key off. Fast Detect mode can be enabled as shown in Tables 1.2 and 1.6. 2.10 Simplified Mode connecting a resistor labelled SMR between pins SNS6K and SNS7 (see Figure 1.2). In this mode there is only one option possible - AKS enable or disable. When AKS is disabled, Fast Detect mode is enabled; when AKS is enabled, Fast Detect mode is off. AKS in this mode is Global only (i.e. operates across all functioning keys). The other option features are fixed as follows: OUT_n, DETECT Pins: Push-pull, active high, one-per-key outputs SYNC/LP Function: LP mode, ~180ms response time Max On-Duration: 60 seconds See Tables 1.6 and 1.7. 2.11 Unused Keys Unused keys should be disabled by removing the corresponding Cs, Rs, and Rsns components and connecting SNS pins as shown in the ‘Unused’ column of Table 1.1. Unused keys are ignored and do not factor into the AKS function (Section 2.7). A simplified operating mode which does not require the majority of option resistors is available. This mode is set by lQ 10 QT1081_1R0.04_0307 3 Design Notes In both cases the exact value depends on the precise circuit component values and timing. Vdd variations can shift the center frequency and spread slightly. 3.1 Oscillator Frequency The QT1081’s internal oscillator runs from an external resistor network connected to the OSC and SS pins, as shown in Figures 1.1 and 1.2, to achieve spread-spectrum operation. If spread-spectrum mode is not required, the OSC pin should be connected to Vdd with an 18KΩ one percent resistor. Under different Vdd voltage conditions the resistor network (or the solitary 18KΩ resistor) might require minor adjustment to obtain the specified burst center frequency. The network should be adjusted slightly so that the positive pulses on any key are approximately 2.67µs wide in the ‘solitary 18KΩ resistor’ mode, or 2.87µs wide at the beginning of a burst with the recommended spread-spectrum circuit (see next section). In practice, the pulse width has little effect on circuit performance if it varies in the range of 2µs to 3.3µs. The only effects seen will be proportional variations in Max On-Duration and non-LP mode response times. 3.2 Spread-Spectrum Circuit The QT1081 offers the ability to spectrally spread its frequency of operation to heavily reduce susceptibility to external noise sources and to limit RF emissions. The SS pin is used to modulate an external passive RC network that modulates the OSC pin. OSC is the main oscillator current input. The circuit is shown in both Figures 1.1 and 1.2. The resistors Rb1 and Rb2 should be changed depending on Vdd. As shown in Figures 1.1 and 1.2, two sets of values are recommended for these resistors depending on Vdd. The power curves in Section 4.6 also show the effect of these resistors. The circuit can be eliminated, if it is not desired, by using an 18KΩ resistor from OSC to Vdd to drive the oscillator, and connecting SS to Vss with a 100KΩ resistor. The spread-spectrum RC network will need to be adjusted according to the burst lengths. The sawtooth waveform observed on SS should reach a crest height as follows: Vdd >= 3.6V: 17 percent of Vdd Vdd < 3.6V: 20 percent of Vdd The Css capacitor connected to the SS pin (Figures 1.1 and 1.2) should be adjusted so that the waveform approximates the above amplitude, ±10 percent, during normal operation in the target circuit. Where the bursts are of differing lengths, the adjustment should be done for the longer burst. If this is done, the circuit will give a spectral modulation of 12-15 percent. Use of the spread-spectrum facility has the following effect on Idd: • Full speed operation: Idd changes within ±10 percent. • Idd increases by up to 15 percent. lQ 11 3.3 Cs Sample Capacitors - Sensitivity The Cs sample capacitors accumulate the charge from the key electrodes and determine sensitivity. Higher values of Cs make the corresponding sensing channel more sensitive. The values of Cs can differ for each channel, permitting differences in sensitivity from key to key or to balance unequal sensitivities. Unequal sensitivities can occur due to key size and placement differences and stray wiring capacitances. More stray capacitance on a sense trace will desensitize the corresponding key; increasing the Cs for that key will compensate for the loss of sensitivity. The Cs capacitors can be virtually any plastic film or low to medium-K ceramic capacitor. The normal Cs range is 1nF to 50nF depending on the sensitivity required; larger values of Cs require better quality to ensure reliable sensing. In certain circumstances the normal Cs range may be exceeded, hence the different values in Section 4.2. Acceptable capacitor types for most uses include PPS film, polypropylene film, and NP0 and X5R / X7R ceramics. Lower grades than X5R or X7R are not recommended. The required values of Cs can be noticeably affected by the presence and connection of the option resistors (see Section 2.2). Cs values should be adjusted for optimal sensitivity after the option resistors are connected. 3.4 Power Supply The power supply can range from 2.8 to 5.0 volts. If this fluctuates slowly with temperature, the device will track and compensate for these changes automatically with only minor changes in sensitivity. If the supply voltage drifts or shifts quickly, the drift compensation mechanism will not be able to keep up, causing sensitivity anomalies or false detections. The power supply should be locally regulated, using a three-terminal device, to between 2.8V and 5.0V. If the supply is shared with another electronic system, care should be taken to ensure that the supply is free of digital spikes, sags and surges which can cause adverse effects. It is not recommended to include a series inductor in the power supply to the QT1081. For proper operation a 0.1µF or greater bypass capacitor must be used between Vdd and Vss; the bypass capacitor should be routed with very short tracks to the device’s Vss and Vdd pins. 3.5 PCB Layout and Construction Refer to Quantum application note AN-KD02 for information related to layout and construction matters. QT1081_1R0.04_0307 4 Specifications 4.1 Absolute Maximum Specifications Operating temperature, Ta. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85oC Storage temp, Ts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50oC to +125oC Vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0V Max continuous pin current, any control or drive pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Short circuit duration to ground or Vdd, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite Voltage forced onto any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V (Vdd + 0.3) Volts 4.2 Recommended Operating Conditions Operating temperature, Ta. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40o to +85oC VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.8 to +5.0V Short-term supply ripple+noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5mV/s Long-term supply stability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100mV Cs range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1nF to 100nF Cx range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 50pF 4.3 AC Specifications Vdd = 5.0, Ta = recommended, Cx = 5pF, Cs = 1nF; circuit of Figure 1.1 Parameter Description Trc Fc Fm Recalibration time Burst center frequency Burst modulation, percent Tpc Sample pulse duration Tsu Tbd Tdf Tdn Tdl Tdr Start-up time from cold start Burst duration Response time - Fast mode Response time - Normal mode Response time - LP mode Release time - all modes Min Typ Max Units 150 132 15 ms kHz % 2 µs 300 2.5 6 20 180 20 ms ms ms ms ms ms Notes Total deviation Pulses appear 33 percent longer when viewed on an oscilloscope. Both bursts together 180ms LP setting End of touch 4.4 DC Specifications Vdd = 5.0, Ta = recommended, Cx = 5pF, Cs = 1nF; circuit of Figure 1.1 unless noted Parameter IDDN Description Min Average supply current, normal mode* IDDL Average supply current, LP mode* Average supply current, LP mode, keys on burst B only VDDS Average supply turn-on slope VIL Low input logic level VHL High input logic level VOL Low output voltage VOH High output voltage IIL Input leakage current Acquisition resolution AR *No spread spectrum circuit; Rosc = 18KΩ lQ Typ Max Units 5.6 3.6 2.3 1.6 8 mA 22 15 15 10 100 µA µA 0.7 3.5 0.5 Vdd-0.5 ±1 8 12 V/s V V V V µA bits Notes @ Vdd = 5.0 @ Vdd = 4.0 @ Vdd = 3.3 @ Vdd = 2.8 @ Vdd = 3.3V; 340ms LP mode @ Vdd = 2.8V; 340ms LP mode @ Vdd = 3.3V @ Vdd = 2.8V @ Vdd = 2.8V 7mA sink 2.5mA source QT1081_1R0.04_0307 4.5 Signal Processing Vdd = 5.0, Ta = recommended, Cx = 5pF, Cs = 1nF Description Detection threshold Detection hysteresis Anti-detection threshold Anti-detection recalibration delay Detect Integrator filter, normal mode Detect Integrator filter, ‘fast’ mode Max On-Duration Normal drift compensation rate Anti-drift compensation rate lQ Value Units Notes 10 2 6 2 counts counts counts secs Threshold for increase in Cx load 6 2 10, 60, ∞ 2,000 500 samples samples secs ms/level ms/level 13 Threshold for decrease of Cx load Time to recalibrate if Cx load has exceeded anti-detection threshold Must be consecutive or detection fails Must be consecutive or detection fails Option pin selected Towards increasing Cx load Towards decreasing Cx load QT1081_1R0.04_0307 4.6 Average Idd Curves All Idd curves are average values, under the following conditions: Cx = 5pF, Ta = 20oC, Rosc = 18KΩ; no spread-spectrum circuit. Refer to page 9 for more information about optimization of LP modes. Full speed operation QT1081, average Idd (full speed operation) 6.0 Idd (mA) 5.0 Vdd=5V 4.0 Vdd=4V 3.0 Vdd=3.3V 2.0 Vdd=2.8V 1.0 0.0 0 1 2 3 4 burst length (ms) 5 6 Low Power operation (optimized - only burst B in use) QT1081, average Idd (100ms optimized LP operation) QT1081, average Idd (180ms optimized LP operation) 400.0 800.0 600.0 300.0 Vdd=5V Vdd=4V 400.0 Vdd=3.3V Vdd=2.8V Idd (uA) Idd (uA) Vdd=5V Vdd=4V 200.0 Vdd=3.3V Vdd=2.8V 100.0 200.0 0.0 0.0 0 1 2 3 4 burst length (ms) 5 0 6 1 2 3 4 burst length (ms) 5 6 QT1081, average Idd (340ms optimized LP operation) 200.0 150.0 Idd (uA) Vdd=5V Vdd=4V 100.0 Vdd=3.3V Vdd=2.8V 50.0 0.0 0 1 2 3 4 burst length (ms) lQ 5 6 14 QT1081_1R0.04_0307 Low Power operation (non-optimized) QT1081, average Idd (100ms LP operation) QT1081, average Idd (180ms LP operation) 800.0 400.0 600.0 300.0 Vdd=5V Idd (uA) Idd (uA) Vdd=5V Vdd=4V 400.0 Vdd=3.3V Vdd=2.8V Vdd=4V 200.0 Vdd=3.3V Vdd=2.8V 100.0 200.0 0.0 0.0 0 1 2 3 4 burst length (ms) 5 0 6 1 2 3 4 burst length (ms) 5 6 QT1081, average Idd (340ms LP operation) 200.0 150.0 Idd (uA) Vdd=5V Vdd=4V 100.0 Vdd=3.3V Vdd=2.8V 50.0 0.0 0 1 2 3 4 burst length (ms) 5 6 4.7 LP Mode Typical Response Times QT1081 Response Time (180ms LP operation) 240 125 230 max. response time (ms) max. response time (ms) QT1081 Response Time (100ms LP operation) 130 120 115 110 105 100 95 220 210 200 190 180 170 160 90 2.5 3 3.5 4 4.5 5 2.5 5.5 3 3.5 4 4.5 5 5.5 Vdd Vdd QT1081 Response Time (340ms LP operation) max. response time (ms) 430 410 390 370 350 330 310 290 2.5 3 3.5 4 4.5 5 5.5 Vdd lQ 15 QT1081_1R0.04_0307 4.8 Mechanical - 32-QFN Package 0.4 Corner tie bar 3m m Exposed Centre Pad PIN 1 Depending upon the IC assembly supplier, the package may be slightly different from that depicted above. See the magnified areas for the main difference between the ICs. Dimensions In Millimeters Symbol Minimum Nominal Maximum A 0.70 0.95 A1 0.00 0.02 0.05 b 0.18 0.25 0.32 C 0.20 REF D 4.90 5.00 5.10 D2 3.05 3.65 E 4.90 5.00 5.10 E2 3.05 3.65 e 0.50 L 0.30 0.40 0.50 y 0.00 0.075 L1 0.00 0.10 Dimension L1 represents terminal pull-back from the package edge. Where terminal pull-back exists, only the upper half of the lead is visible on the package edge due to half etching of the leadframe. The corner tie bar is connected internally to the exposed central pad. Note that there is no functional requirement for the large pad on the underside of this package to be soldered. If the final application requires this area to be soldered for mechanical reasons, the pad to which it is soldered must be isolated and contained under the footprint only. lQ 16 QT1081_1R0.04_0307 4.9 Part Marking QRG Part No. QT1081 ©QRG 1 YYWWG run nr. Pin 1 Identification QRG Revision Code ‘YY’ = Year of manufacture ‘WW’ = Week of manufacture ‘G’ = Green/RoHS Compliant or ‘XX’ depending upon the IC assembly supplier 'run nr.' = 6 Digit Run Number (depending upon the IC assembly supplier, this line may not appear) 4.10 Moisture Sensitivity Level (MSL) lQ MSL Rating Peak Body Temperature Specifications MSL3 260OC IPC/JEDEC J-STD-020C 17 QT1081_1R0.04_0307 5 Datasheet Control 5.1 Changes Changes this issue (datasheet rev 04) Changes throughout to remove 48-SSOP package. Section 5: new. 5.2 Numbering Convention Part Number Datasheet Issue Number QT1081_MXN.nn_mmyy Chip Revision (Where M = Major chip revision, N = Minor chip revision, X = Prereleased Product [or R = Released Product]) Datasheet Release Date; (Where mm = Month, yy = Year) A minor chip revision (N) is defined as a revision change which does not affect product functionality or datasheet. The value of N is only stated for released parts (R). lQ 18 QT1081_1R0.04_0307 NOTES: lQ 19 QT1081_1R0.04_0307 lQ Copyright © 2006-2007 QRG Ltd. All rights reserved Patented and patents pending Corporate Headquarters 1 Mitchell Point Ensign Way, Hamble SO31 4RF Great Britain Tel: +44 (0)23 8056 5600 Fax: +44 (0)23 8045 3939 www.qprox.com North America 651 Holiday Drive Bldg. 5 / 300 Pittsburgh, PA 15220 USA Tel: 412-391-7367 Fax: 412-291-1015 The specifications set out in this document are subject to change without notice. All products sold and services supplied by QRG are subject to QRG’s Terms and Conditions of sale and services. QRG patents, trademarks and Terms and Conditions can be found online at http://www.qprox.com/about/legal.php. Numerous further patents are pending, one or more which may apply to this device or the applications thereof. QRG products are not suitable for medical (including lifesaving equipment), safety or mission critical applications or other similar purposes. Except as expressly set out in QRG's Terms and Conditions, no licenses to patents or other intellectual property of QRG (express or implied) are granted by QRG in connection with the sale of QRG products or provision of services. QRG will not be liable for customer product design and customers are entirely responsible for their products and applications which incorporate QRG's products. Development Team: John Dubery, Alan Bowens, Matthew Trend