RE46C311/2
Low-Input Leakage, Rail-to-Rail Input/Output Op Amps
Features
Description
•
•
•
•
•
•
•
The RE46C311/2 family of operational amplifiers (op
amps) from Microchip Technology Inc. operate with a
single-supply voltage as low as 1.8V, while drawing
less than 1 µA (maximum) of quiescent current per
amplifier. These devices are also designed to support
rail-to-rail input and output operation. This combination
of features supports battery-powered and portable
applications.
Low Quiescent Current: 600 nA/Amplifier (typical)
Rail-to-Rail Input/Output
Gain Bandwidth Product: 10 kHz (typical)
Wide Supply Voltage Range: 1.8V to 5.5V
Unity Gain Stable
Available in Single and Dual Configurations
Temperature Ranges: -10°C to +60°C
Applications
• Ionization Smoke Detectors
• Low Leakage High-Impedance Input Circuits
• Battery-Powered Circuits
Design Aids
• MAPS (Microchip Advanced Part Selector)
• Analog Demonstration and Evaluation Boards
• Application Notes
The RE46C311/2 family operational amplifiers are
offered in single (RE46C311), and dual (RE46C312)
configurations.
Package Types
RE46C311
PDIP, SOIC
Typical Application
VDD
Ionization
Chamber
The RE46C311/2 amplifiers have a gain-bandwidth
product of 10 kHz (typical) and are unity gain stable.
These specifications make these op amps appropriate
for low-frequency applications, such as ionization
smoke detectors and sensor conditioning.
-
RE46C31X
+
NC 1
8 NC
VIN– 2
7 VDD
VIN+ 3
6 VOUT
VSS 4
5 NC
RE46C312
PDIP, SOIC
VSS
2013 Microchip Technology Inc.
VOUTA 1
8 VDD
VINA– 2
7 VOUTB
VINA+ 3
6 VINB–
VSS 4
5 VINB+
DS25163A-page 1
RE46C311/2
1.0
ELECTRICAL
CHARACTERISTICS
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other conditions
above those indicated in the operational listings of this
specification is not implied. Exposure to maximum rating conditions for extended periods may affect device
reliability.
Absolute Maximum Ratings †
VDD – VSS ........................................................................6.0V
Current at Input Pins .....................................................±2 mA
All Inputs and Outputs .................... VSS – 0.3V to VDD + 0.3V
Difference Input voltage ...................................... |VDD – VSS|
Output Short Circuit Current ..................................continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature.................................... –65°C to +150°C
Junction Temperature.................................................. +150°C
ESD protection on all pins (HBM; MM) 4 kV; 400V
†† See Section 4.1, Rail-to-Rail Input.
DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C,
VCM = VDD/2, VOUT VDD/2, VL = VDD/2, and RL = 1 M to VL (refer to Figure 1-1 and Figure 1-2).
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Input Offset
Input Offset Voltage
Drift with Temperature
Power Supply Rejection
VOS
-3
—
+3
mV
VOS/TA
—
±2
—
µV/°C
PSRR
70
76
—
dB
VCM = VSS
-0.75
—
0.75
pA
Non Inverting Input only,
VIN = VDD or VSS
—
3.5
6
TA= -10°C to +60°C
Input Leakage Current and Impedance
Input Leakage Current
Input Leakage Current
IL1
TA = +60°C
IL2
-100
—
100
nA
Common Mode
Input Impedance
ZCM
—
1013||6
—
||pF
Inverting input only
Differential Input Impedance
ZDIFF
—
1013||6
—
||pF
Common-Mode Input Range
VCMR
VSS
—
VDD
V
Common-Mode
Rejection Ratio
CMRR
62
86
—
dB
VDD = 5V, VCM = 0V to 5.0V
AOL
85
115
—
dB
RL = 50 k to VL,
VOUT = 0.1V to VDD-0.1V
VOL, VOH
VSS + 10
—
VDD - 10
mV
RL = 50 k to VL,
0.5V input overdrive
Common Mode
Open-Loop Gain
DC Open-Loop Gain
(large signal)
Output
Maximum Output
Voltage Swing
Output Short Circuit Current
ISC
—
5
—
mA
VDD = 1.8V
—
27
—
mA
VDD = 5.5V
VDD
1.8
—
5.5
V
IQ
0.3
0.6
1.0
µA
Power Supply
Supply Voltage
Quiescent Current
per Amplifier
DS25163A-page 2
IO = 0
2013 Microchip Technology Inc.
RE46C311/2
AC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C,
VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, and CL = 60 pF (refer to Figure 1-1 and Figure 1-2).
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
AC Response
Gain Bandwidth Product
GBWP
—
10
—
kHz
Slew Rate
SR
—
3.0
—
V/ms
Phase Margin
PM
—
65
—
°
G = +1 V/V
Noise
Input Voltage Noise
Eni
—
5.0
—
µVP-P
Input Voltage Noise Density
eni
—
170
—
nV/Hz
f = 1 kHz
Input Current Noise Density
ini
—
0.6
—
fA/Hz
f = 1 kHz
f = 0.1 Hz to 10 Hz
TEMPERATURE CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND.
Parameters
Sym.
Min.
Typ.
Max. Units
Operating Temperature Range
TA
-10
—
+60
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 8L-PDIP
JA
—
89.3
—
°C/W
Thermal Resistance, 8L-SOIC
JA
—
149.5
—
°C/W
Conditions
Temperature Ranges
Thermal Package Resistances
1.1
Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-1 and Figure 1-2. The bypass
capacitors are laid out according to the rules discussed
in Section 4.5, Supply Bypass.
VDD
VDD/2
RN
0.1 µF 1 µF
VOUT
RE46C31X
CL
VDD
VIN
RN
0.1 µF
VIN
1 µF
RL
RF
VL
VOUT
RE46C31X
CL
VDD/2 RG
RG
RL
FIGURE 1-2:
AC and DC Test Circuit for
Most Inverting Gain Conditions.
RF
VL
FIGURE 1-1:
AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
2013 Microchip Technology Inc.
DS25163A-page 3
RE46C311/2
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 1 M to VL, and CL = 60 pF.
6
1500
VDD = V
Representative Part
Input, Output Voltages (V)
Input Offset Voltage (μV)
2000
1000
500
0
TA = +60°C
TA = +25°C
TA = -10°C
-500
-1000
-1500
FIGURE 2-1:
Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 1.8V.
Input
3
Output
2
1
-1
G = 2 V/V
VDD = 5V
Time (5 ms/div)
FIGURE 2-4:
The RE46C311/2 Family
Shows No Phase Reversal.
100
2000
VDD = 5.5V
Representative Part
PSRR, CMRR (dB)
Input Offset Voltage (μV)
4
0
-2000
-0.4-0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2
Common Mode Input Voltage (V)
1500
5
1000
500
0
TA = +60°C
TA = +25°C
TA = -10°C
-500
-1000
95
CMRR
(VDD =5.5V, VCM = -0.3V to +5.8V)
90
85
80
PSRR
75
-1500
70
-2000
-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Common Mode Input Voltage (V)
FIGURE 2-2:
Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 5.5V.
-10
0
10
20
30
40
50
Ambient Temperature (°C)
FIGURE 2-5:
Temperature.
CMRR, PSRR vs. Ambient
0
120
90
60
Open-Loop Gain (dB)
CMRR, PSRR (dB)
80
70
60
CMRR
PSRR-/+
50
40
30
1
FIGURE 2-3:
Frequency.
DS25163A-page 4
10
100
Frequency (Hz)
CMRR, PSRR vs.
-60
80
Open-Loop Phase
60
-90
40
-120
20
-150
0
-180
-201.0E-03 1.0E-02 1.0E-01
0.001 0.01 0.1
20
-30
100
1000
1.0E+00
1
1.0E+01
10
1.0E+02
100
1.0E+03
1k
Open-Loop Phase (°)
Open-Loop Gain
-210
1.0E+05
10k 100k
1.0E+04
Frequency (Hz)
FIGURE 2-6:
Frequency.
Open-Loop Gain, Phase vs.
2013 Microchip Technology Inc.
RE46C311/2
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 1 M to VL, and CL = 60 pF.
Output Voltage (5 mV/div)
130
120
110
100
90
RL = 50 k
VOUT = 0.1V to VDD – 0.1V
80
1.5
2.0
2.5 3.0 3.5 4.0 4.5 5.0
Power Supply Voltage (V)
5.5
Time (100 μs/div)
FIGURE 2-7:
DC Open-Loop Gain vs.
Power Supply Voltage.
20
100
18
90
80
GBWP (kHz)
70
PM
12
60
10
50
GBWP
8
40
6
30
4
2
FIGURE 2-10:
Pulse Response.
Phase Margin (°)
16
14
G = 1 V/V
RL = 50 kΩ
6.0
20
VDD = 5.5V
Gain = 100
10
Output Voltage (5 mV/div)
DC Open-Loop Gain (dB)
140
Small Signal Non-inverting
G = -1 V/V
RL = 50 kΩ
0
0
-0.500.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50
Common Mode Voltage (V)
Time (100 μs/div)
FIGURE 2-8:
Gain Bandwidth Product,
Phase Margin vs. Common Mode Input Voltage.
5.0
90
GBWP
10
70
PM
8
60
6
50
4
40
2
30
VDD = 5.5V
20
0
4.0
Small Signal Inverting Pulse
G = -1 V/V
RL = 50 kΩ
VDD = 5.0V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-10
4.5
80
Output Voltage (V)
12
Phase Margin (°)
Gain Bandwidth Product (KHz)
14
FIGURE 2-11:
Response.
10
20
30
40
50
Ambient Temperature (°C)
60
FIGURE 2-9:
Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature with
VDD = 5.5V.
2013 Microchip Technology Inc.
0.0
Time (1 ms/div)
FIGURE 2-12:
Pulse Response.
Large Signal Non-inverting
DS25163A-page 5
RE46C311/2
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 1 M to VL, and CL = 60 pF.
5.0
Output Voltage (V)
4.5
4.0
G = 1 V/V
RL = 50 kΩ
VDD = 5.0V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Time (1 ms/div)
FIGURE 2-13:
Response.
DS25163A-page 6
Large Signal Inverting Pulse
2013 Microchip Technology Inc.
RE46C311/2
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
RE46C311
RE46C312
PDIP, SOIC
PDIP, SOIC,
Symbol
3.1
6
1
VOUT, VOUTA
Analog Output (op amp A)
2
2
VIN–, VINA–
Inverting Input (op amp A)
3
3
VIN+, VINA+
Non-inverting Input (op amp A)
7
8
VDD
—
5
VINB+
Non-inverting Input (op amp B)
—
6
VINB–
Inverting Input (op amp B)
—
7
VOUTB
Analog Output (op amp B)
4
4
VSS
Negative Power Supply
1, 5, 8
—
NC
No Internal Connection
Analog Outputs
The output pins are low-impedance voltage sources.
3.2
Description
Analog Inputs
The non-inverting and inverting inputs are high-impedance CMOS inputs with low bias and leakage currents.
2013 Microchip Technology Inc.
Positive Power Supply
3.3
Power Supply Pins
The positive power supply pin (VDD) is 1.8V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
DS25163A-page 7
RE46C311/2
4.0
APPLICATIONS INFORMATION
The RE46C311/2 family of op amps is manufactured
using a state of the art CMOS process. These op amps
are unity gain stable and suitable for a wide range of
general purpose, low-power applications.
There are two transitions in input behavior as VCM is
changed. The first occurs when VCM is near
VSS + 0.4V, and the second occurs when VCM is near
VDD – 0.5V (see Figure 2-1 and Figure 2-2). For the
best distortion performance with non-inverting gains,
avoid these regions of operation.
4.1
4.2
Rail-to-Rail Input
4.1.1
PHASE REVERSAL
The RE46C311/2 op amps are designed to not exhibit
phase inversion when the input pins exceed the supply
voltages. Figure 2-4 shows an input voltage exceeding
both supplies with no phase inversion.
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS or one diode drop above VDD.
VDD Bond
Pad
There are two specifications that describe the output
swing capability of the RE46C311/2 family of op amps.
The first specification (Maximum Output Voltage
Swing) defines the absolute maximum swing that can
be achieved under the specified load condition. Thus,
the output voltage swings to within 10 mV of either
supply rail with a 50 k load to VDD/2. Figure 2-4
shows how the output voltage is limited when the input
goes beyond the linear region of operation.
The second specification that describes the output
swing capability of these amplifiers is the Linear Output
Voltage Range. This specification defines the maximum output swing that can be achieved while the
amplifier still operates in its linear region. To verify
linear operation in this range, the large signal DC
Open-Loop Gain (AOL) is measured at points inside the
supply rails. The measurement must meet the specified
AOL condition in the specification table.
4.3
VIN+
Bond
Pad
Input
Stage
Bond
VIN–
Pad
VSS Bond
Pad
FIGURE 4-1:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Absolute
Maximum Ratings †).
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below VSS or above VDD.
Applications that are high-impedance may need to limit
the usable voltage range.
4.1.3
NORMAL OPERATION
The input stage of the RE46C311/2 op amps uses two
differential input stages in parallel. One operates at a
low common mode input voltage (VCM), while the other
operates at a high VCM. With this topology, the device
operates with a VCM up to VDD and down to VSS. The
input offset voltage is measured at VCM = VSS and VDD
to ensure proper operation.
DS25163A-page 8
Rail-to-Rail Output
Output Loads and Battery Life
The RE46C311/2 op amp family has outstanding
quiescent current, which supports battery-powered
applications.
Heavy resistive loads at the output can cause
excessive battery drain. Driving a DC voltage of 2.5V
across a 100 k load resistor will cause the supply
current to increase by 25 µA, depleting the battery
43 times as fast as IQ (0.6 µA, typical) alone.
High frequency signals (fast edge rate) across
capacitive loads will also significantly increase supply
current. For instance, a 0.1 µF capacitor at the output
presents an AC impedance of 15.9 k (1/2fC) to a
100 Hz sine wave. It can be shown that the average
power drawn from the battery by a 5.0 Vp-p sine wave
(1.77 Vrms), under these conditions, is:
EQUATION 4-1:
PSupply = (VDD - VSS) (IQ + VL(p-p) f CL )
= (5V)(0.6 µA + 5.0Vp-p · 100Hz · 0.1µF)
= 3.0 µW + 50 µW
This will drain the battery 17 times as fast as IQ alone.
2013 Microchip Technology Inc.
RE46C311/2
4.4
Capacitive Loads
4.5
Supply Bypass
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity gain buffer (G = +1) is the most
sensitive to capacitive loads, although all gains show
the same general behavior.
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It can use a bulk
capacitor (i.e., 1 µF or larger) within 100 mm to provide
large, slow currents. This bulk capacitor is not required
for most applications and can be shared with nearby
analog parts.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-2) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
4.6
RISO
VOUT
RE46C31X
VIN
CL
FIGURE 4-2:
Output Resistor, RISO,
Stabilizes Large Capacitive Loads.
Figure 4-3 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
Recommended RISO (ȍ)
100,000
100k
Unused Op Amps
An unused op amp in a dual package (RE46C312)
should be configured as shown in Figure 4-4. These
circuits prevent the output from toggling and causing
crosstalk. Circuit A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
½ RE46C312 (A)
½ RE46C312 (B)
VDD
R1
VDD
VDD
R2
VREF
R2
V REF = VDD ------------------R1 + R 2
FIGURE 4-4:
Unused Op Amps.
10k
10,000
1k
1,000
10p
1.E+01
GN = +1
GN = +2
GN ≥ +5
100p
1n
10n
1.E+02
1.E+03
1.E+04
Normalized Load Capacitance; CL/GN (F)
FIGURE 4-3:
Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable.
2013 Microchip Technology Inc.
DS25163A-page 9
RE46C311/2
4.7
PCB Surface Leakage
In applications where low input bias current is critical,
printed circuit board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012. A 5V difference would
cause 5 pA of current to flow, which is greater than the
RE46C311/2 family’s leakage current at +25°C.
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
Figure 4-5 shows an example of this type of layout.
Guard Ring
VIN– VIN+
4.8
Application Circuits
4.8.1
INSTRUMENTATION AMPLIFIER
The RE46C311/2 op amp is well suited for conditioning
sensor signals in battery-powered applications.
Figure 4-6 shows a two op amp instrumentation
amplifier, using the RE46C312, that works well for
applications requiring rejection of Common mode noise
at higher gains. The reference voltage (VREF) is
supplied by a low impedance source. In single supply
applications, VREF is typically VDD/2.
.
RG
VREF R1
R2
R2
R1
VOUT
V2
V1
FIGURE 4-5:
for Inverting Gain.
1.
2.
Example Guard Ring Layout
Non-inverting Gain and Unity Gain Buffer:
a) Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b) Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
Common mode input voltage.
Inverting Gain and Transimpedance Gain
(convert current to voltage, such as photo
detectors) amplifiers:
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
DS25163A-page 10
½
RE46C312
½
RE46C312
R1 2R 1
VOUT = V1 – V 2 1 + ------ + --------- + VREF
R2 RG
FIGURE 4-6:
Two Op Amp
Instrumentation Amplifier.
2013 Microchip Technology Inc.
RE46C311/2
5.0
DESIGN AIDS
Microchip provides the basic design tools needed for
the RE46C311/2 family of op amps.
5.1
Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from
the
Microchip
website
at
www.microchip.com/ maps, the MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs.
Using this tool you can define a filter to sort features for
a parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for data sheets, purchase, and sampling of
Microchip parts.
5.3
Application Notes
The following Microchip Application Notes are
available
on
the
Microchip
web
site
at
www.microchip.com/appnotes and are recommended
as supplemental reference resources.
ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
AN990: “Analog Sensor Conditioning Circuits – An
Overview”, DS00990
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
5.2
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding user’s guides and technical information,
visit
the
Microchip
web
site
at
www.microchip.com/analogtools.
Three of our boards that are especially useful are:
• P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP
Evaluation Board
• P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP
Evaluation Board
• P/N MCP651EV-VOS: MCP651 Input Offset
Evaluation Board
2013 Microchip Technology Inc.
DS25163A-page 11
RE46C311/2
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
8-Lead SOIC (3.90 mm)
NNN
Legend: XX...X
Y
YY
WW
NN
e3
*
Note:
DS25163A-page 12
Example
RE46C311
V/P e^^3 256
1302
Example
RE46C311
e3 1302
SN ^^
256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2013 Microchip Technology Inc.
RE46C311/2
3
& '
!&" & 4 # *!( !!&
4 % &
&# &
&& 255***'
'5 4
N
NOTE 1
E1
1
3
2
D
E
A2
A
L
A1
c
e
eB
b1
b
6&!
'!
9'&!
7"')
% !
7,8.
7
7
7:
;
<
&
&
&
=
=
## 4
4!!
-
1 !&
&
=
=
"# &
"# >#&
.
-
-
## 4 >#&
.
#&
9
* 9 #>#&
:
* +
1,
-
!" #$% &" ' ()"&'"!&)
&#*& & & #
+% &, & !&
- '!
! #. #
&"#'
#% !
& "!
!
#% !
& "!
!!
&$# / !#
'!
#&
.0
1,21 !'!
& $ & "!
**&
"&&
!
* ,
