RFPIC12F675F-I/SS

rfPIC12F675 FLASH-Based Microcontroller with ASK/FSK Transmitter High Performance RISC CPU: Peripheral Features: • Memory - 1024 x 14 words of FLASH program memory - 128 x 8 bytes of EEPROM data memory - 64 x 8 bytes of SRAM data memory - 100,000 write FLASH endurance - 1,000,000 write EEPROM endurance - FLASH/data EEPROM retention: > 40 years • Programmable code protection • 6 I/O pins with individual direction control, weak pull-ups, and interrupt-on-pin change • High current sink/source for direct LED drive • Analog comparator: 16 internal reference levels • Analog-to-Digital Converter: 10 bits, 4 channels • Timer0: 8-bit timer/counter with 8-bit prescaler • Timer1: 16-bit timer/counter with 3-bit prescaler • Timer1 can use LP oscillator in INTOSC mode • 5 s wake-up from SLEEP typical with VDD = 3V • In-Circuit Serial ProgrammingTM (ICSPTM) Low Power Features: • Low power consumption: (typical with VDD = 3V) - 14 mA transmitting +6 dBm at 434 MHz - 4 mA transmitting -15 dBm at 434 MHz - 500 A, 4.0 MHz INTOSC - 0.6 A SLEEP with watchdog enabled - 0.1 A standby current • Wide operating voltage range from 2.0 – 5.5V • Industrial and Extended temperature range  2003-2013 Microchip Technology Inc. SSOP VDD GP5/T1CKI/OSC1/CLKIN GP4/T1G/OSC2/CLKOUT GP3/MCLR/VPP RFXTAL RFEN REFCLK PS VDDRF VSSRF •1 2 3 4 5 6 7 8 9 10 rfPIC12F675K/F/H • Only 35 instructions to learn - All single cycle instructions except branches • Operating speed: - Precision Internal 4 MHz oscillator, factory calibrated to ±1% - DC - 20 MHz Resonator/Crystal/Clock modes - DC - 20 MHz crystal oscillator/clock input - DC - 4 MHz external RC oscillator - DC - 4 MHz XT crystal oscillator - External Oscillator modes • Interrupt capability • 8-level deep hardware stack • Direct, Indirect and Relative Addressing modes Pin Diagram: 20 19 18 17 16 15 14 13 12 11 VSS GP0/CIN+/ICSPDAT GP1/CIN-/ICSPCLK GP2/T0CKI/INT/COUT FSKOUT DATAFSK DATAASK LF VSSRF ANT UHF ASK/FSK Transmitter: • Integrated crystal oscillator, VCO, loop filter and power amp for minimum external components • ASK data rate: 0 – 40 Kbps • FSK data rate: 0 – 40 Kbps by crystal pulling • Output power: +10 dBm to -12 dBm in 4 steps • Adjustable transmitter power consumption • Transmit frequency set by crystal multiplied by 32 • VCO phase locked to quartz crystal reference; allows narrow band receivers to be used to maximize range and interference immunity • Crystal frequency divide by 4 available (REFCLK) • Used in applications conforming to US FCC Part 15.231 and European EN 300 220 regulations Applications: • • • • • • • • • Automotive Remote Keyless Entry (RKE) systems Automotive alarm systems Community gate and garage door openers Burglar alarm systems Building access Low power telemetry Meter reading Tire pressure sensors Wireless sensors Device Frequency Modulation rfPIC12F675K 290-350 MHz ASK/FSK rfPIC12F675F 380-450 MHz ASK/FSK rfPIC12F675H 850-930 MHz ASK/FSK Preliminary DS70091B-page 1 rfPIC12F675 Table of Contents 1.0 Device Overview ............................................................................................................................................................................ 3 2.0 Memory Organization..................................................................................................................................................................... 5 3.0 GPIO Port ................................................................................................................................................................................... 17 4.0 Timer0 Module............................................................................................................................................................................ 25 5.0 Timer1 Module with Gate Control ............................................................................................................................................... 28 6.0 Comparator Module .................................................................................................................................................................... 33 7.0 Analog-to-Digital Converter (A/D) Module .................................................................................................................................. 39 8.0 Data EEPROM Memory.............................................................................................................................................................. 45 9.0 UHF ASK/FSK Transmitter ......................................................................................................................................................... 49 10.0 Special Features of the CPU ...................................................................................................................................................... 55 11.0 Instruction Set Summary ............................................................................................................................................................ 73 12.0 Development Support ................................................................................................................................................................. 81 13.0 Electrical Specifications .............................................................................................................................................................. 87 14.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 113 15.0 Packaging Information .............................................................................................................................................................. 123 Appendix A: Data Sheet Revision History.......................................................................................................................................... 125 Index ................................................................................................................................................................................................. 127 On-Line Support................................................................................................................................................................................ 131 Systems Information and Upgrade Hot Line ..................................................................................................................................... 131 Reader Response ............................................................................................................................................................................. 132 Product Identification System............................................................................................................................................................ 133 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS70091B-page 2 Preliminary  2003-2013 Microchip Technology Inc. rfPIC12F675 1.0 DEVICE OVERVIEW be considered a complementary document to this Data Sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. This document contains device specific information for the rfPIC12F675. Additional information may be found in the PICmicroTM Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The Reference Manual should FIGURE 1-1: The rfPIC12F675 comes in a 20-pin SSOP package. Figure 1-1 shows a block diagram of the rfPIC12F675 device. Table 1-1 shows the pinout description. rfPIC12F675 BLOCK DIAGRAM 13 FLASH Data Bus Program Counter Program Memory Program Bus GP0/AN0/CIN+ GP1/AN1/CIN-/VREF GP2/AN2/T0CKI/INT/COUT GP3/MCLR/VPP GP4/AN3/T1G/OSC2/CLKOUT GP5/T1CKI/OSC1/CLKIN RAM File Registers 64 x 8 8-Level Stack (13-bit) 1K x 14 8 14 RAM Addr(1) 9 Addr MUX Instruction Reg 7 Direct Addr 8 Indirect Addr FSR Reg Internal 4 MHz Oscillator 3 Timing Generation OSC1/CLKIN OSC2/CLKOUT MUX Power-up Timer ALU Oscillator Start-up Timer T1G RFXTAL W Reg Divide by 32 Charge Pump LF Voltage Controlled Oscillator T1CKI Timer0 Timer1 T0CKI PS DATAASK Analog to Digital Converter Analog Comparator and reference EEDATA 8 128 bytes DATA EEPROM EEADDR CIN- CIN+ COUT VREF Crystal Oscillator Phase/Freq Detector 8 Power-on Reset Watchdog Timer Brown-out Detect VDD, VSS REFCLK STATUS Reg 8 Instruction Decode & Control Clock Divider RFEN RF Power Amplifier RF Control Logic ANT VDDRF VSSRF VSSRF DATAFSK FSK Switch FSKOUT AN0 AN1 AN2 AN3 Note 1: Higher order bits are from STATUS register.  2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 3 rfPIC12F675 TABLE 1-1: rfPIC12F675 PINOUT BUFFER IN OUT WEAK PULL-UP VDD Direct — — GP5 TTL CMOS Prog T1CKI OSC1 CLKIN ST Xtal ST — — — — Bias — GP4 TTL CMOS Prog ST Analog — — — — Xtal CMOS — — Bias — TTL — ST HV Xtal TTL — — Xtal — PIN 1 2 3 T1G AN3 OSC2 CLKOUT GP3 4 DESCRIPTION Power Supply General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Timer1 clock XTAL connection External RC network or clock input General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Timer1 gate A/D Channel 3 input XTAL connection TOSC/4 reference clock General purpose input. Individually controlled interrupt-onchange. Master Clear Reset Programming voltage 5 RF Crystal 6 RF Enable Reference Clock/4 Output (on rfPIC12F675K/F) 7 REFCLK — CMOS — Reference Clock/8 Output (on rfPIC12F675H) 8 PS Analog — Bias Power Select 9 VDDRF Direct — — RF Power Supply 10 VSSRF Direct — — RF Ground Reference 11 ANT — OD — RF power amp output to antenna 12 VSSRF Direct — — RF Ground Reference 13 LF Analog Analog — Loop Filter TTL — — ASK modulation data 14 DATAASK 15 DATAFSK TTL — — FSK modulation data 16 FSKOUT — OD — FSK output to modulate reference crystal General purpose I/O. Individually controlled interrupt-on-change. GP2 ST CMOS Prog Individually enabled pull up. AN2 Analog — — A/D Channel 2 input 17 COUT — CMOS — Comparator output T0CKI ST — — External clock for Timer0 INT ST — — External interrupt General purpose I/O. Individually controlled interrupt-on-change. GP1 TTL CMOS Prog Individually enabled pull-up. AN1 Analog — — A/D Channel 1 input 18 CINAnalog — — Comparator input - negative VREF Analog — — External voltage reference ICSPCLK ST — — Serial programming clock General purpose I/O. Individually controlled interrupt-on-change. GP0 TTL CMOS Prog Individually enabled pull-up. AN0 Analog — — A/D Channel 0 input 19 CIN+ Analog — — Comparator input - positive ICSPDAT TTL CMOS — Serial Programming Data I/O 20 VSS Direct — — Ground reference Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, OD = Open Drain output MCLR VPP RFXTAL RFEN DS70091B-page 4 No — Bias — Preliminary  2003-2013 Microchip Technology Inc. rfPIC12F675 2.0 MEMORY ORGANIZATION 2.2 2.1 Program Memory Organization The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose registers and the Special Function registers. The Special Function registers are located in the first 32 locations of each bank. Register locations 20h-5Fh are General Purpose registers, implemented as static RAM and are mapped across both banks. All other RAM is unimplemented and returns ‘0’ when read. RP0 (STATUS) is the bank select bit. The rfPIC12F675 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h - 03FFh) for the rfPIC12F675 devices is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first 1K x 14 space. The RESET vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1). FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR THE rfPIC12F675 PC CALL, RETURN RETFIE, RETLW Data Memory Organization • RP0 = 0 Bank 0 is selected • RP0 = 1 Bank 1 is selected Note: 2.2.1 13 The IRP and RP1 bits STATUS are reserved and should always be maintained as ‘0’s. GENERAL PURPOSE REGISTER FILE The register file is organized as 64 x 8 in the rfPIC12F675 devices. Each register is accessed, either directly or indirectly, through the File Select Register FSR (see Section 2.4). Stack Level 1 Stack Level 2 Stack Level 8 RESET Vector 000h Interrupt Vector 0004 0005 On-chip Program Memory 03FFh 0400h 1FFFh  2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 5 rfPIC12F675 2.2.2 SPECIAL FUNCTION REGISTERS FIGURE 2-2: The Special Function registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM. DATA MEMORY MAP OF THE rfPIC12F675 File Address Indirect addr.(1) TMR0 PCL STATUS FSR GPIO The special registers can be classified into two sets: core and peripheral. The Special Function registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. PCLATH INTCON PIR1 TMR1L TMR1H T1CON CMCON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Registers File Address Indirect addr.(1) OPTION_REG PCL STATUS FSR TRISIO PCLATH INTCON PIE1 PCON OSCCAL WPU IOC VRCON EEDATA EEADR EECON1 EECON2(1) ADRESL ANSEL 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h accesses 20h-5Fh 64 Bytes 5Fh 60h DFh E0h 7Fh Bank 0 1: DS70091B-page 6 Preliminary FFh Bank 1 Unimplemented data memory locations, read as '0'. Not a physical register.  2003-2013 Microchip Technology Inc. rfPIC12F675 TABLE 2-1: Address SPECIAL FUNCTION REGISTERS SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOD Page Bank 0 00h INDF(1) Addressing this Location uses Contents of FSR to Address Data Memory 0000 0000 16,63 01h TMR0 Timer0 Module’s Register xxxx xxxx 25 02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 15 03h STATUS 04h FSR 05h GPIO IRP(2) RP1(2) RP0 TO PD Z DC C Indirect Data Memory Address Pointer — --xx xxxx 17 Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — ---0 0000 15 0Bh 0Ch 0Dh GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 16 — PCLATH GPIO5 9 xxxx xxxx 06h 0Ah — 0001 1xxx — — — INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 11 PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 13 — Write Buffer for Upper 5 bits of Program Counter — — 0Eh TMR1L Unimplemented Holding Register for the Least Significant Byte of the 16-bit Timer1 xxxx xxxx 28 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit Timer1 xxxx xxxx 28 10h T1CON -000 0000 30 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h — Unimplemented — — -0-0 0000 33 19h CMCON — — TMR1GE COUT T1CKPS1 — T1CKPS0 CINV T1OSCEN CIS T1SYNC CM2 TMR1CS CM1 TMR1ON CM0 1Ah — Unimplemented — — 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRESH xxxx xxxx 40 1Fh ADCON0 00-- 0000 41,63 Most Significant 8 bits of the Left Shifted A/D Result or 2 bits of the Right Shifted Result ADFM VCFG — — CHS1 CHS0 GO/DONE ADON Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: This is not a physical register. 2: These bits are reserved and should always be maintained as ‘0’.  2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 7 rfPIC12F675 TABLE 2-1: Address SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PS1 PS0 Value on POR, BOD Page 0000 0000 16,63 1111 1111 10,26 0000 0000 15 0001 1xxx 9 xxxx xxxx 16 --11 1111 17 Bank 1 80h INDF(1) 81h OPTION_REG 82h PCL 83h STATUS 84h FSR 85h TRISIO Addressing this Location uses Contents of FSR to Address Data Memory GPPU INTEDG T0CS T0SE PSA PS2 Program Counter's (PC) Least Significant Byte IRP (2) RP0 (2) RP1 TO PD Z DC C TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 Indirect Data Memory Address Pointer — — TRISIO5 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — ---0 0000 15 8Ah PCLATH 8Bh INTCON 8Ch PIE1 8Dh 8Eh — PCON — — — Write Buffer for Upper 5 bits of Program Counter GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 11 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 12 — — — — — — — POR BOD ---- --0x 14 — — CAL4 CAL3 CAL2 CAL1 CAL0 — — 1000 00-- 14 Unimplemented — 8Fh — 90h OSCCAL 91h — Unimplemented — — 92h — Unimplemented — — 93h — Unimplemented — — 94h — Unimplemented — — 95h WPU 96h IOC Unimplemented CAL5 — — WPU5 WPU4 — WPU2 WPU1 WPU0 --11 -111 18 — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 19 97h — Unimplemented — — 98h — Unimplemented — — 0-0- 0000 38 0000 0000 45 -000 0000 45 ---- x000 46 46 99h VRCON VREN — 9Ah EEDATA 9Bh EEADR — 9Ch EECON1 — 9Dh EECON2(1) EEPROM Control Register 2 ---- ---- 9Eh ADRESL Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result xxxx xxxx 40 9Fh ANSEL -000 1111 42,63 VRR — VR3 VR2 VR1 VR0 Data EEPROM Data Register — Data EEPROM Address Register — ADCS2 — ADCS1 — ADCS0 WRERR ANS3 WREN ANS2 WR ANS1 RD ANS0 Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: This is not a physical register. 2: These bits are reserved and should always be maintained as ‘0’. DS70091B-page 8 Preliminary  2003-2013 Microchip Technology Inc. rfPIC12F675 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the RESET status • the bank select bits for data memory (SRAM) It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any STATUS bits. For other instructions not affecting any STATUS bits, see the “Instruction Set Summary”. The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. Note 1: Bits IRP and RP1 (STATUS) are not used by the rfPIC12F675 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products. 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). REGISTER 2-1: STATUS — STATUS REGISTER (ADDRESS: 03h OR 83h) Reserved Reserved IRP RP1 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x RP0 TO PD Z DC C bit 7 bit 0 bit 7 IRP: This bit is reserved and should be maintained as ‘0’ bit 6 RP1: This bit is reserved and should be maintained as ‘0’ bit 5 RP0: Register Bank Select bit (used for direct addressing) 1 = Bank 1 (80h - FFh) 0 = Bank 0 (00h - 7Fh) bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)  For borrow, the polarity is reversed. 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared  2003-2013 Microchip Technology Inc. Preliminary x = Bit is unknown DS70091B-page 9 rfPIC12F675 2.2.2.2 OPTION Register Note: The OPTION register is a readable and writable register, which contains various control bits to configure: • • • • To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT by setting PSA bit to ‘1’ (OPTION). See Section 4.4. TMR0/WDT prescaler External GP2/INT interrupt TMR0 Weak pull-ups on GPIO REGISTER 2-2: OPTION_REG — OPTION REGISTER (ADDRESS: 81h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual port latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of GP2/INT pin 0 = Interrupt on falling edge of GP2/INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on GP2/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on GP2/T0CKI pin 0 = Increment on low-to-high transition on GP2/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the TIMER0 module bit 2-0 PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 Legend: DS70091B-page 10 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared Preliminary x = Bit is unknown  2003-2013 Microchip Technology Inc. rfPIC12F675 2.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, GPIO port change and external GP2/INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. INTCON — INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GIE PEIE T0IE INTE GPIE T0IF INTF GPIF bit 7 bit 0 bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4 INTE: GP2/INT External Interrupt Enable bit 1 = Enables the GP2/INT external interrupt 0 = Disables the GP2/INT external interrupt bit 3 GPIE: Port Change Interrupt Enable bit(1) 1 = Enables the GPIO port change interrupt 0 = Disables the GPIO port change interrupt bit 2 T0IF: TMR0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INTF: GP2/INT External Interrupt Flag bit 1 = The GP2/INT external interrupt occurred (must be cleared in software) 0 = The GP2/INT external interrupt did not occur bit 0 GPIF: Port Change Interrupt Flag bit 1 = When at least one of the GP5:GP0 pins changed state (must be cleared in software) 0 = None of the GP5:GP0 pins have changed state Note 1: IOC register must also be enabled to enable an interrupt-on-change. 2: T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on RESET and should be initialized before clearing T0IF bit. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared  2003-2013 Microchip Technology Inc. Preliminary x = Bit is unknown DS70091B-page 11 rfPIC12F675 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: Note: Bit PEIE (INTCON) must be set to enable any peripheral interrupt. PIE1 — PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch) R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 EEIE ADIE — — CMIE — — TMR1IE bit 7 bit 0 bit 7 EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit  1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt bit 5-4 Unimplemented: Read as ‘0’ bit 3 CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt bit 2-1 Unimplemented: Read as ‘0’ bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: DS70091B-page 12 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared Preliminary x = Bit is unknown  2003-2013 Microchip Technology Inc. rfPIC12F675 2.2.2.5 PIR1 Register The PIR1 register contains the interrupt flag bits, as shown in Register 2-5. REGISTER 2-5: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR1 — PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch) R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 EEIF ADIF — — CMIF — — TMR1IF bit 7 bit 0 bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started bit 6 ADIF: A/D Converter Interrupt Flag bit  1 = The A/D conversion is complete (must be cleared in software) 0 = The A/D conversion is not complete bit 5-4 Unimplemented: Read as ‘0’ bit 3 CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 2-1 Unimplemented: Read as ‘0’ bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared  2003-2013 Microchip Technology Inc. Preliminary x = Bit is unknown DS70091B-page 13 rfPIC12F675 2.2.2.6 PCON Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • Power-on Reset (POR) Brown-out Detect (BOD) Watchdog Timer Reset (WDT) External MCLR Reset The PCON Register bits are shown in Register 2-6. REGISTER 2-6: PCON — POWER CONTROL REGISTER (ADDRESS: 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-x — — — — — — POR BOD bit 7 bit 0 bit 7-2 Unimplemented: Read as '0' bit 1 POR: Power-on Reset STATUS bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOD: Brown-out Detect STATUS bit 1 = No Brown-out Detect occurred 0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs) Legend: 2.2.2.7 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown OSCCAL Register The Oscillator Calibration register (OSCCAL) is used to calibrate the internal 4 MHz oscillator. It contains 6 bits to adjust the frequency up or down to achieve 4 MHz. The OSCCAL register bits are shown in Register 2-7. REGISTER 2-7: OSCCAL — OSCILLATOR CALIBRATION REGISTER (ADDRESS: 90h) R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — bit 7 bit 0 bit 7-2 CAL5:CAL0: 6-bit Signed Oscillator Calibration bits 111111 = Maximum frequency 100000 = Center frequency 000000 = Minimum frequency bit 1-0 Unimplemented: Read as '0' Legend: DS70091B-page 14 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared Preliminary x = Bit is unknown  2003-2013 Microchip Technology Inc. rfPIC12F675 2.3 2.3.2 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC) is not directly readable or writable and comes from PCLATH. On any RESET, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH  PCH). The lower example in Figure 2-3 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH  PCH). FIGURE 2-3: LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL 12 8 7 0 PC 8 PCLATH 5 Instruction with PCL as Destination The rfPIC12F675 Family has an 8-level deep x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed, or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no STATUS bits to indicate stack overflow or stack underflow conditions. ALU result PCLATH PCH 12 11 10 PCL 8 STACK 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address. 0 7 PC GOTO, CALL 2 PCLATH 11 Opcode PCLATH 2.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note “Implementing a Table Read" (AN556).  2003-2013 Microchip Technology Inc. Preliminary DS70091B-page 15 rfPIC12F675 2.4 Indirect Addressing, INDF and FSR Registers A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-1. The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. EXAMPLE 2-1: Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although STATUS bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS), as shown in Figure 2-4. FIGURE 2-4: INDIRECT ADDRESSING movlw movwf clrf incf btfss goto NEXT 0x20 FSR INDF FSR FSR,4 NEXT CONTINUE DIRECT/INDIRECT ADDRESSING rfPIC12F675 Direct Addressing RP1(1) RP0 ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue 6 From Opcode Indirect Addressing IRP(1) 0 7 Bank Select Bank Select Location Select 00 01 10 FSR Register 0 Location Select 11 00h 180h Data Memory Not Used 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail see Figure 2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. DS70091B-page 16 Preliminary  2003-2013 Microchip Technology Inc. rfPIC12F675 3.0 GPIO PORT register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. There are as many as six general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. Note: 3.1 Note: Additional information on I/O ports may be found in the PIC Mid-Range Reference Manual (DS33023) EXAMPLE 3-1: bcf clrf movlw movwf bsf clrf movlw movwf GPIO and the TRISIO Registers GPIO is an 6-bit wide, bi-directional port. The corresponding data direction register is TRISIO. Setting a TRISIO bit (= 1) will make the corresponding GPIO pin an input (i.e., put the corresponding output driver in a Hi-impedance mode). Clearing a TRISIO bit (= 0) will make the corresponding GPIO pin an output (i.e., put the contents of the output latch on the selected pin). The exception is GP3, which is input only and its TRISIO bit will always read as ‘1’. Example 3-1 shows how to initialize GPIO. 3.2 INITIALIZING GPIO STATUS,RP0 GPIO 07h CMCON STATUS,RP0 ANSEL 0Ch TRISIO ;Bank 0 ;Init GPIO ;Set GP to ;digital IO ;Bank 1 ;Digital I/O ;Set GP as inputs ;and set GP ;as outputs Additional Pin Functions Every GPIO pin on the rfPIC12F675 has an interrupton-change option and every GPIO pin, except GP3, has a weak pull-up option. The next two sections describe these functions. Reading the GPIO register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. GP3 reads ‘0’ when MCLREN = 1. 3.2.1 WEAK PULL-UP Each of the GPIO pins, except GP3, has an individually configurable weak internal pull-up. Control bits WPUx enable or disable each pull-up. Refer to Register 3-3. Each weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the GPPU bit (OPTION). The TRISIO register controls the direction of the GP pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISIO REGISTER 3-1: The ANSEL (9Fh) and CMCON (19h) registers (9Fh) must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. GPIO — GPIO REGISTER (ADDRESS: 05h) U-0 — U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 bit 7 bit 0 bit 7-6: Unimplemented: Read as ’0’ bit 5-0: GPIO: General Purpose I/O pin. 1 = Port pin is >VIH 0 = Port pin is