RH1280-CQ172V

v3.1 Radiation-Hardened FPGAs Features • • • • • • • • Guaranteed Total Dose Radiation Capability Low Single Event Upset Susceptibility High Dose Rate Survivability Latch-Up Immunity Guaranteed QML Qualified Devices Commercial Devices Available for Prototyping and Pre-Production Requirements Gate Capacities of 2,000 and 8,000 Gate Array Gates More Design Flexibility than Custom ASICs • • • • • • • • • • Significantly Greater Densities than Discrete Logic Devices Replaces up to 200 TTL Packages Design Library with over 500 Macro Functions Single-Module Sequential Functions Wide-Input Combinatorial Functions Up to Two High-Speed, Low-Skew Clock Networks Two In-Circuit Diagnostic Probe Pins Support Speed Analysis to 50 MHz Non-Volatile, User Programmable Devices Fabricated in 0.8 µ Epitaxial Bulk CMOS Process Unique In-System Diagnostic and Verification Capability with Silicon Explorer Product Family Profile Device Capacity System Gates Gate Array Equivalent Gates PLD Equivalent Gates TTL Equivalent Packages 20-Pin PAL Equivalent Packages Logic Modules S-Modules C-Modules Flip-Flops (Maximum) Routing Resources Horizontal Tracks/Channel Vertical Tracks/Channel PLICE Antifuse Elements User I/Os (Maximum) Packages (by Pin Count) Ceramic Quad Flat Pack (CQFP) RH1020 3,000 2,000 6,000 50 20 547 0 547 273 22 13 186,000 69 84 RH1280 12,000 8,000 20,000 200 80 1,232 624 608 998 35 15 750,000 140 172 April 2005 © 2005 Actel Corporation i See the Actel website for the latest version of the datasheet. Radiation-Hardened FPGAs Ordering Information RH1280 – CQ 172 V Application V = QML Qualified Package Lead Count Package Type CQ = Ceramic Quad Flat Pack Part Number RH1280 = 8000 Gates RH1020 = 2000 Gates Figure 1-1 • Ordering Information Ceramic Device Resources CQFP 84-Pin RH1020 RH1280 69 – CQFP 172-Pin – 140 ii v3.1 Radiation-Hardened FPGAs Table of Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Radiation Survivability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 QML Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 RadHard Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 The RH1020 Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 QML Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Radiation Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Sequential Module Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 84-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 172-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 International Traffic in Arms Regulations (ITAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 v 3.1 iii Radiation-Hardened FPGAs Radiation-Hardened FPGAs General Description Actel Corporation, the leader in antifuse-based field programmable gate arrays (FPGAs), offers fully guaranteed RadHard versions of the A1280 and A1020 devices with gate densities of 8,000 and 2,000 gate array gates, respectively. The RH1020 and RH1280 devices are processed in 0.8 µ, two-level metal epitaxial bulk CMOS technology. The devices are based on the Actel patented channeled array architecture, and employ Actel’s PLICE antifuse technology. This architecture offers gate array flexibility, high performance, and fast design implementation through user programming. Actel devices also provide unique on-chip diagnostic probe capabilities, allowing convenient testing and debugging. On-chip clock drivers with hard-wired distribution networks provide efficient clock distribution with minimum skew. A security fuse may be programmed to disable all further programming, and to protect the design from being copied or reverse engineered. The RH1020 and RH1280 are available as fully qualified QML devices. Unlike traditional ASIC devices, the design does not have to be finalized six months prior to receiving the devices. Customers can make design modifications and program new devices within hours. These devices are fabricated, assembled, and tested at the Lockheed-Martin Space and Electronics facility in Manassas, Virginia on an optimized radiation-hardened CMOS process. line by expensive and destructive testing. QML also ensures continuous process improvement, a focus on enhanced quality and reliability, and shortened product introduction and cycle time. Actel Corporation has also achieved QML certification. All RH1020 and RH1280 devices will be shipped with a "QML" marking, signifying that the devices and processes have been reviewed and approved by DESC for QML status. Development Tool Support The RadHard family of FPGAs is fully supported by both Actel Libero® Integrated Design Environment (IDE) and Designer FPGA development software. Actel Libero IDE is a design management environment, seamlessly integrating design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. Libero IDE includes Synplify® for Actel from Synplicity®, ViewDraw® for Actel from Mentor Graphics®, ModelSim® HDL Simulator from Mentor Graphics, WaveFormer Lite™ from SynaptiCAD™, and Designer software from Actel. Refer to the Libero IDE flow diagram for more information (located on the Actel website). Actel Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes timing-driven place-and-route, and a world-class integrated static timing analyzer and constraints editor. With the Designer software, a user can select and lock package pins while only minimally impacting the results of place-and-route. Additionally, the back-annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Actel’s integrated verification and logic analysis tool. Another tool included in the Designer software is the ACTgen macro builder, which easily creates popular and commonly used logic functions for implementation in your schematic or HDL design. Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from companies such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. Radiation Survivability In addition to all electrical limits, all radiation characteristics are tested and guaranteed, reducing overall system-level risks. With total dose hardness of 300 krad (Si), latch-up immunity, and a tested single event upset (SEU) of less than 1x10–6 errors/bit-day, these are the only RadHard, high-density field programmable products available today. QML Qualification Lockheed Martin Space and Electronics in Manassas, Virginia has achieved full QML certification, assuring that quality management, procedures, processes, and controls are in place from wafer fabrication through final test. QML qualification means that quality is built into the production process rather than verified at the end of the v3.1 1-1 Radiation-Hardened FPGAs Applications The RH1020 and RH1280 devices are targeted for use in military and space applications subject to radiation effects. 1. Accumulated Total Dose Effects With the significant increase in Earth-orbiting satellite launches and the ever-decreasing time-tolaunch design cycles, the RH1020 and RH1280 devices offer the best combination of total dose radiation hardness and quick design implementation necessary for this increasingly competitive industry. In addition, the high total dose capability allows the use of these devices for deep space probes, which encounter other planetary bodies where the total dose radiation effects are more pronounced. 2. Single Event Effects (SEE) Many space applications are more concerned with the number of single event upsets and potential for latchup in space. The RH1020 and RH1280 devices are latch-up immune, guaranteeing that no latch-up failures will occur. Single event upsets can occur in these devices as with all semiconductor products, but the rate of upset is low, as shown in Table 1-2 on page 1-6. 3. High Dose Rate Survivability An additional radiation concern is high dose rate survivability. Solar flares and sudden nuclear events can cause immediate high levels of radiation. The RadHard devices are appropriate for use in these types of applications, including missile systems, ground-based communication systems, and orbiting satellites. where S0 = A0 × B0 S1 = A1 + B1 A0 B0 D00 D01 D10 D11 A1 B1 S0 Y S1 Figure 1-1 • C-Module Implementation The S-module, shown in Figure 1-2 on page 1-3, is designed to implement high-speed sequential functions within a single logic module. The S-module implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential element can be configured as either a D-flip-flop or a transparent latch. To increase flexibility, the S-module register can be bypassed so it implements purely combinatorial logic. Flip-flops can also be created using two C-modules. The single event upset (SEU) characteristics differ between an S-module flip-flop and a flip-flop created using two C-modules. For details see the Radiation Specifications table on Table 1-2 on page 1-6 and the Design Techniques for RadHard Field Programmable Gate Arrays application note. RadHard Architecture The RH1020 and RH1280 architecture is composed of fine-grained building blocks that produce fast and efficient logic designs. All the devices are composed of logic modules, routing resources, clock networks, and I/O modules, which are the building blocks for fast logic designs. The RH1020 Logic Module The RH1020 logic module is an 8-input, one-output logic circuit chosen for the wide range of functions it implements and for its efficient use of interconnect routing resources (Figure 1-3 on page 1-3). The logic module can implement the four basic logic functions (NAND, AND, OR, and NOR) in gates of two, three, or four inputs. Each function may have many versions, with different combinations of active-low inputs. The logic module can also implement a variety of D-latches, exclusivity functions, AND-ORs, and OR-ANDs. No dedicated hardwired latches or flip-flops are required in the array, since latches and flip-flops may be constructed from logic modules wherever needed in the application. Logic Modules RH1280 devices contain two types of logic modules, combinatorial (C-modules) and sequential (S-modules). RH1020 devices contain only C-modules. The C-module, shown in Figure 1-1, implements the following function: Y = !S1 × !S0 × D00 + !S1 × S0 × D01 + S1 × !S0 × D10 + S1 × S0 × D11 EQ 1-1 1 -2 v3.1 Radiation-Hardened FPGAs D00 D01 D10 D11 S1 Y S0 D CLR Q OUT D00 D01 D10 D11 S1 Y S0 D GATE Q OUT Up to 7-Input Function Plus D-Type Flip-Flop with Clear Up to 7-Input Function Plus Latch D00 D0 Y D1 S D GATE CLR Q OUT D01 D10 D11 S1 Y S0 OUT Up to 4-Input Function Plus Latch with Clear Figure 1-2 • S-Module Implementation Up to 8-Input Function (same as C-Module) EN Q D PAD G/CLK* From Array To Array Q D G/CLK* Note: *Can be configured as a Latch or D Flip-Flop (using C-Module). Figure 1-4 • I/O Module Figure 1-3 • RH1020 Logic Module I/O Modules I/O modules provide the interface between the device pins and the logic array. A variety of user functions, determined by a library macro selection, can be implemented in the I/O modules (refer to the Antifuse Macro Library Guide for more information). I/O modules contain a tristate buffer, and input and output latches which can be configured for input, output, or bidirectional pins (Figure 1-4). v3.1 1-3 Radiation-Hardened FPGAs RadHard devices contain flexible I/O structures in that each output pin has a dedicated output enable control. The I/O module can be used to latch input and/or output data, providing a fast set-up time. In addition, the Actel Designer software tools can build a D-flip-flop, using a C-module, to register input and/or output signals. Actel Designer development tools provide a design library of I/O macros that can implement all I/O configurations supported by the RadHard FPGAs. Antifuse Structures An antifuse is a "normally open" structure as opposed to the normally closed fuse structure used in PROMs or PALs. The use of antifuses to implement a programmable logic device results in highly testable structures, as well as efficient programming algorithms. The structure is highly testable because there are no pre-existing connections, enabling temporary connections to be made using pass transistors. These temporary connections can isolate individual antifuses to be programmed, as well as isolate individual circuit structures to be tested. This can be done both before and after programming. For example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. Routing Structure The RadHard device architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O modules. These routing tracks are metal interconnects that may either be of continuous length or broken into segments. Varying segment lengths allow over 90 percent of the circuit interconnects to be made with only two antifuse connections. Segments can be joined together at the ends, using antifuses to increase their length up to the full length of the track. All interconnects can be accomplished with a maximum of four antifuses. Segmented Horizontal Routing Tracks Logic Modules Horizontal Routing Horizontal channels are located between the rows of modules, and are composed of several routing tracks. The horizontal routing tracks within the channel are divided into one or more segments. The minimum horizontal segment length is the width of a module-pair, and the maximum horizontal segment length is the full length of the channel. Any segment that spans more than one-third the row length is considered a long horizontal segment. A typical channel is shown in Figure 1-5. Non-dedicated horizontal routing tracks are used to route signal nets. Dedicated routing tracks are used for the global clock networks and for power and ground tie-off tracks. Antifuses Vertical Routing Tracks Figure 1-5 • Routing Structure Related Documents Application Notes Design Techniques for RadHard Field Programmable Gate Arrays http://www.actel.com/documents/Des_Tech_RH_AN.pdf Analysis of SDI/DCLK Issue for RH1020 and RT1020 Vertical Routing Another set of routing tracks run vertically through the module. There are three types of vertical tracks, input, output, and long, that can be divided into one or more segments. Each segment in an input track is dedicated to the input of a particular module. Each segment in an output track is dedicated to the output of a particular module. Long segments are uncommitted and can be assigned during routing. Each output segment spans four channels (two above and two below), except near the top and bottom of the array where edge effects occur. Long vertical tracks contain either one or two segments. An example of vertical routing tracks and segments is shown in Figure 1-5. http://www.actel.com/documents/SDI_DCLK_AN.pdf Simultaneously Switching Noise and Signal Integrity http://www.actel.com/documents/SSN_AN.pdf User’s Guides Antifuse Macro Library Guide http://www.actel.com/documents/libguide_UG.pdf 1 -4 v3.1 Radiation-Hardened FPGAs QML Flow Test Inspection Wafer Lot Acceptance Serialization Die Adhesion Test Bond Pull Test Internal Visual Temperature Cycle Constant Acceleration Particle Impact Noise Detection (PIND) X-Ray Radiography Pre Burn-In Electrical Parameters (T0) Dynamic Burn-In Interim Electrical Parameters (T1) Percent Defective Allowable (PDA) Static Burn-In Final Electrical Parameters (T2) Percent Defective Allowable (PDA) Seal – Fine/Gross Leak External Visual (as required) Method LMFS Procedure MAN-STC-Q014 Required – 100% 2027 (Stud Pull) 2011 (Wirebond) 2010, Condition A 1010, Condition C, 50 Cycles 2001, Condition D or E, Y1 Orientation Only 2020, Condition A 2012 Per Device Specification 1015, 240 Hour Minimum, 125°C Per Device Specification LMFS Procedure MAN-STC-Q016 1015, 144 Hour Minimum, 125°C Minimum Per Device Specification LMFS Procedure MAN-STC-Q016 1014 2009 Absolute Maximum Ratings Table 1-1 • Free Air Temperature Range Symbol VCC VI VO IIO TSTG Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the recommended operating conditions. 3. VPP = VCC , except during device operation. 4. VSV = VCC , except during device operation. 5. VKS = GND , except during device operation. 6. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V or less than GND – 0.5V, the internal protection diode will be forward-biased and can draw excessive current. DC Supply Parameter Voltage2,3,4,5 Limits –0.5 to +7.0 –0.5 to VCC +0.5 –0.5 to VCC +0.5 Current6 2 Units V V V mA °C Input Voltage Output Voltage I/O Source/Sink ±20 –65 to +150 Storage Temperature v3.1 1-5 Radiation-Hardened FPGAs Recommended Operating Conditions Parameter Temperature Range1 Power Supply Tolerance Notes: 1. Case temperature (TC) is used. 2. All power supplies must be in the recommended operating range. 2 Military –55 to +125 ±10 Units °C %VCC Electrical Specifications Symbol VOH1 VOL1 VIH VIL Input Transition Time CIO, I/O Capacitance2 IIH, IIL IOZL, IOZH ICC Standby3 Notes: 1. Only one output tested at a time. VCC = min. 2. Not tested, for information only. 3. All outputs unloaded. All inputs = VCC or GND. VIN = VCC or GND VCC = 5.5 V VOUT = VCC or GND VCC = 5.5 V tR, tF2 Test Conditions (IOH = –4 mA) (IOL = 4 mA) Group A Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 — 4 1, 2, 3 1, 2, 3 1, 2, 3 –10 –10 2.2 –0.3 Limits Min. 3.7 0.4 VCC + 0.3 0.8 500 20 10 10 25 Max. Units V V V V ns pF µA µA mA Radiation Specifications Table 1-2 • Radiation Specifications1, 2 Symbol RTD SEL SEU1 SEU2 3 3 Characteristics Total Dose Single Event Latch-Up Single Event Upset for S-modules Single Event Upset for C-modules Single Event Fuse Rupture Neutron Fluence Conditions Min. Max. 300 k Units Rad (Si) Fails/Device-Day Upsets/Bit-Day Upsets/Bit-Day FIT (Fails/Device/1E9 Hrs) N/cm2 –55°C ≤ Tcase ≤ 125°C –55°C ≤ Tcase ≤ 125°C –55°C ≤ Tcase ≤ 125°C –55°C ≤ Tcase ≤ 125°C >1 E+12 0 1E-6 1E-7