RT3PE3000L-1CG484B

Advance v0.1 Radiation-Tolerant ProASIC3 Low-Power SpaceFlight Flash FPGAs with Flash*Freeze Technology Features and Benefits MIL-STD-883 Class B Qualified Packaging • Ceramic Column Grid Array with Six Sigma CopperWrapped Lead-Tin Columns • Land Grid Array • High-Performance, Low-Skew Global Network • Architecture Supports Ultra-High Utilization ® Advanced and Pro (Professional) I/Os • 700 Mbps DDR, LVDS-Capable I/Os • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 8 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input • Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS • Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II (RT3PE3000L only) • I/O Registers on Input, Output, and Enable Paths • Hot-Swappable and Cold-Sparing I/Os • Programmable Output Slew Rate and Drive Strength • Programmable Input Delay (RT3PE3000L only) • Schmitt Trigger Option on Single-Ended Inputs (RT3PE3000L) • Weak Pull-Up/-Down • IEEE 1149.1 (JTAG) Boundary Scan Test • Pin-Compatible Packages across the Radiation-Tolerant ProASIC®3 Family Low Power • Dramatic Reduction in Dynamic and Static Power • 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power • Low Power Consumption in Flash*Freeze Mode Enables Instantaneous Entry To / Exit From Low-Power Flash*Freeze Mode • Supports Single-Voltage System Operation • Low-Impedance Switches Radiation Tolerant • 15 krad Total Ionizing Dose (TID) • Wafer-Lot-Specific TID Reports High Capacity • 600 k to 3 M System Gates • Up to 504 kbits of True Dual-Port SRAM • Up to 620 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process • Live-at-Power-Up (LAPU) Level 0 Support • Single-Chip Solution • Retains Programmed Design when Powered Off Clock Conditioning Circuit (CCC) and PLL • Six CCC Blocks, All with Integrated PLL (RT ProASIC3) • Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback • Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V systems) and 350 MHz (1.5 V systems) High Performance • 350 MHz (1.5 V) and 250 MHz (1.2 V) System Performance • 3.3 V, 66 MHz, 66-Bit PCI (1.5 V); 66 MHz, 32-Bit PCI (1.2 V) SRAMs and FIFOs • Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available) • True Dual-Port SRAM (except ×18) • 24 SRAM and FIFO Blocks with Synchronous Operation: – 250 MHz: For 1.2 V Systems – 350 MHz: For 1.5 V Systems RT3PE3000L 3M 75,264 504 112 1k Yes 6 18 8 620 CG/LG484, CG/LG896 In-System Programming (ISP) and Security • Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant) • FlashLock® to Secure FPGA Contents High-Performance Routing Hierarchy • Segmented, Hierarchical Routing and Clock Structure RT ProASIC3 Devices System Gates VersaTiles (D-flip-flops) RAM kbits (1,024 bits) 4,608-Bit Blocks FlashROM Bits Secure (AES) ISP Integrated PLL in CCCs VersaNet Globals I/O Banks Maximum User I/Os Package Pins CCGA/LGA RT3PE600L 600 k 13,824 108 24 1k Yes 6 18 8 270 CG/LG484 Table I-1 • Radiation-Tolerant (RT) ProASIC3 Low-Power Space-Flight FPGAs September 2008 © 2008 Actel Corporation I Radiation-Tolerant ProASIC3 Low-Power Space-Flight Flash FPGAs I/Os Per Package1 Radiation-Tolerant ProASIC3 Low-Power Devices Package CG/LG484 CG/LG896 Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to ensure you are complying with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For RT3PE3000L devices, the usage of certain I/O standards is limited as follows: – SSTL3(I) and (II): up to 40 I/Os per north or south bank – LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank – SSTL2(I) and (II) / GTL+ 2.5 V / GTL 2.5 V: up to 72 I/Os per north or south bank 4. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of singleended user I/Os available is reduced by one. RT3PE600L Single-Ended I/Os 270 – 2 RT3PE3000L Single-Ended I/Os2 341 620 Differential I/O Pairs 168 300 Differential I/O Pairs 135 – RT ProASIC3 Ordering Information RT3PE3000L _ 1 FG 484 B Application (Screening Level) B = MIL-STD-883 Class B Package Lead Count Package Type CG = Ceramic Column Grid Array (1.0 mm pitch) LG = Land Grid Array (1.0 mm pitch) Speed Grade Blank = Standard 1 = 15% Faster than Standard Part Number RT ProASIC3 Space-Flight FPGAs RT3PE600L = 600,000 System Gates RT3PE3000L = 3,000,000 System Gates II A d v a n c e v 0 .1 Radiation-Tolerant ProASIC3 Low-Power Space-Flight Flash FPGAs Temperature Grade Offerings Package CG/LG484 CG/LG896 Note: B = MIL-STD-883 Class B screening RT3PE600L B – RT3PE3000L B B Speed Grade and Temperature Grade Matrix Temperature Grade B Note: B = MIL-STD-883 Class B screening Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx. Std. –1 ✓ ✓ Advance v0.1 III 1 – Radiation-Tolerant ProASIC3 Low-Power SpaceFlight FPGA Overview General Description The radiation-tolerant (RT) ProASIC3 family of Actel flash FPGAs dramatically reduces dynamic power consumption by 40% and static power by 50%. These power savings are coupled with performance, density, true single chip, 1.2 V to 1.5 V core and I/O operation, reprogrammability, and advanced features. The RT ProASIC3 FPGA is based on Actel's ProASIC3EL family of low-power FPGAs. Actel's proven Flash*Freeze technology enables RT ProASIC3 device users to shut off dynamic power instantaneously and switch the device to static mode without the need to switch off clocks or power supplies, and retaining internal states of the device. This greatly simplifies power management. In addition, optimized software tools using power-driven layout provide instant push-button power reduction. Nonvolatile flash technology gives RT ProASIC3 devices the advantage of being a secure, lowpower, single-chip solution that is live at power-up (LAPU). RT ProASIC3 devices offer dramatic dynamic power savings, giving FPGA users flexibility to combine low power with high performance. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. RT ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry (CCC) based on an integrated phase-locked loop (PLL). RT ProASIC3 devices support devices from 600 k system gates to 3 million system gates with up to 504 kbits of true dual-port SRAM and 620 user I/Os. Flash*Freeze Technology RT ProASIC3 devices offer Actel's proven Flash*Freeze technology, which allows instantaneous switching from an active state to a static state. When Flash*Freeze mode is activated, RT ProASIC3 devices enter a static state while retaining the contents of registers and SRAM. Power is conserved without the need for additional external components to turn off I/Os or clocks. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of RT ProASIC3 devices to support a 1.2 V core voltage allows for an even greater reduction in power consumption, which enables low total system power. When the RT ProASIC3 device enters Flash*Freeze mode, the device automatically shuts off the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is retained. The availability of low-power modes, combined with a reprogrammable, single-chip, single-voltage solution, make RT ProASIC3 devices suitable for low-power data transfer and manipulation in military-temperature applications where available power may be limited (e.g., in battery-powered equipment); or where heat dissipation may be limited (e.g., in enclosures with no forced cooling). Flash Advantages Low Power The RT ProASIC3 family of Actel flash-based FPGAs provides a low-power advantage, and when coupled with high performance, enables designers to make power-smart choices using a singlechip, reprogrammable, and live-at-power-up device. RT ProASIC3 devices offer 40% dynamic power and 50% static power savings by reducing the core operating voltage to 1.2 V. In addition, the power-driven layout (PDL) feature in Libero® Integrated Design Environment (IDE) offers up to 30% additional power reduction. With Flash*Freeze A dv a n c e v 0. 1 1-1 Radiation-Tolerant ProASIC3 Device Family Overview technology, an RT ProASIC3 device is able to retain device SRAM and logic while dynamic power is reduced to a minimum, without the need to stop clock or power supplies. Combining these features provides a low-power, feature-rich, and high-performance solution. Security Nonvolatile, flash-based RT ProASIC3 devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. RT ProASIC3 devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. RT ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in RT ProASIC3 devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. RT ProASIC3 devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. RT ProASIC3 devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed device cannot be read back, although secure design verification is possible. Security, built into the FPGA fabric, is an inherent component of the RT ProASIC3 family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The RT ProASIC3 family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. An RT ProASIC3 device provides the most impenetrable security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based RT ProASIC3 FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up Actel flash-based RT ProASIC3 devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based RT ProASIC3 devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based RT ProASIC3 devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, flash-based RT ProASIC3 devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The RT ProASIC3 family device architecture mitigates the need for ASIC migration at higher volumes. This makes the RT ProASIC3 family a cost-effective ASIC replacement. 1 -2 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 Device Family Overview Advanced Flash Technology The RT ProASIC3 family offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with 7 layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. Advanced Architecture The proprietary RT ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The RT ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1): • • • • • FPGA VersaTiles Dedicated FlashROM Dedicated SRAM/FIFO memory Extensive CCCs and PLLs I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the RT ProASIC3 core tile, as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable, allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generationarchitecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of RT ProASIC3 devices via an IEEE 1532 JTAG interface. CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Pro I/Os VersaTile RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps Figure 1-1 • RT ProASIC3 Device Architecture Overview A dv a n c e v 0. 1 1-3 Radiation-Tolerant ProASIC3 Device Family Overview Flash*Freeze Technology RT ProASIC3 devices offer Actel's proven Flash*Freeze technology, which enables designers to instantaneously shut off dynamic power consumption while retaining all SRAM and register information. Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the Flash*Freeze (FF) pin while all power supplies are kept at their original values. In addition, I/Os and global I/Os can still be driven and can be toggling without impact on power consumption; clocks can still be driven or can be toggling without impact on power consumption; all core registers and SRAM cells retain their states. I/Os are tristated during Flash*Freeze mode or can be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLLs. Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the power management of the device. The FF pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. It is also possible to use the FF pin as a regular I/O if Flash*Freeze mode usage is not planned, which is advantageous because of the inherent lowpower static and dynamic capabilities of the RT ProASIC3 device. Refer to Figure 1-2 for an illustration of entering/exiting Flash*Freeze mode. Flash*Freeze Mode Control Actel RT ProASIC3 FPGA Flash*Freeze Pin Figure 1-2 • RT ProASIC3 Flash*Freeze Mode VersaTiles The RT ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core tiles. The RT ProASIC3 VersaTile supports the following: • • • • All 3-input logic functions—LUT-3 equivalent Latch with clear or set D-flip-flop with clear or set Enable D-flip-flop with clear or set Refer to Figure 1-3 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 D-Flip-Flop with Clear or Set Data CLK CLR Y D-FF Enable D-Flip-Flop with Clear or Set Data CLK Enable CLR D-FF Y LUT-3 Y Figure 1-3 • VersaTile Configurations 1 -4 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 Device Family Overview User Nonvolatile FlashROM Actel RT ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: • • • • • • • • Internet protocol addressing (wireless or fixed) System calibration settings Device serialization and/or inventory control Subscription-based business models (for example, set-top boxes) Secure key storage for secure communications algorithms Asset management/tracking Date stamping Version management FlashROM is written using the standard RT ProASIC3 IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks, as in security keys stored in the FlashROM for a user design. FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Actel RT ProASIC3 development software solutions, Libero IDE and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO RT ProASIC3 devices have embedded SRAM blocks along their north and south sides. Each variableaspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC RT ProASIC3 space-flight FPGAs provide designers with flexible clock conditioning circuit (CCC) capabilities. Each member of the RT ProASIC3 family contains six CCCs, located at the four corners and the centers of the east and west sides. All six CCC blocks are equipped with a PLL. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. A dv a n c e v 0. 1 1-5 Radiation-Tolerant ProASIC3 Device Family Overview The CCC block has these key features: • • • • • • • • • • Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz 2 programmable delay types for clock skew minimization Clock frequency synthesis Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration. Output duty cycle = 50% ± 1.5% or better Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global network used Maximum acquisition time is 300 µs Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz / fOUT_CCC Additional CCC specifications: Global Clocking RT ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. I/Os with Advanced I/O Standards The RT ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). In addition, 1.2 V I/O operation is supported for RT ProASIC3 devices. RT ProASIC3 FPGAs support different I/O standards, including single-ended, differential, and voltage-referenced. The I/Os are organized into banks, with eight banks per device. The configuration of these banks determines the I/O standards supported. For RT ProASIC3, each I/O bank is subdivided into VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a given VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be able to use that reference voltage. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: • • Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II) Double-data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II). RT ProASIC3 banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads. Part Number and Revision Date Part Number 51700107-001-0 Revised September 2008 1 -6 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 Device Family Overview Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel’s products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. A dv a n c e v 0. 1 1-7 2 – Radiation-Tolerant ProASIC3 DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 • Symbol VCC VJTAG VPUMP VCCPLL VCCI and VI VMV3 Absolute Maximum Ratings Parameter DC core supply voltage JTAG DC voltage Programming voltage Analog power supply (PLL) DC I/O buffer supply voltage I/O input voltage Limits –0.3 to 1.65 –0.3 to 3.75 –0.3 to 3.75 –0.3 to 1.65 –0.3 to 3.75 –0.3 V to 3.6 V (when I/O hot insertion mode is enabled) –0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) TSTG 2 TJ 2 Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-7. 2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-3, and for recommended operating limits, refer to Table 2-2 on page 2-2. 3. VMV pins must be connected to the corresponding VCCI pins. Refer to the Pin Descriptions chapter for further information. Storage temperature Junction temperature –65 to +150 +150 °C °C Units V V V V V V A dv a n c e v 0. 1 2-1 Radiation-Tolerant ProASIC3 FPGAs Table 2-2 • Symbol TA TJ VCC VJTAG VPUMP 3 Recommended Operating Conditions2 Parameter Ambient temperature Junction temperature DC core supply voltage JTAG DC voltage Programming voltage Programming mode Operation3 Military –55 to 125 –55 to 125 1.14 to 1.575 1.4 to 3.45 3.15 to 3.45 0 to 3.6 1.14 to 1.575 1.14 to 1.26 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 3.0 to 3.6 2.375 to 2.625 3.0 to 3.6 Units °C °C V V V V V V V V V V V V VCCPLL VCCI and VMV 4 Analog power supply (PLL) 1.2 V DC supply voltage 1.5 V DC supply voltage 1.8 V DC supply voltage 2.5 V DC supply voltage 3.3 V DC supply voltage LVDS differential I/O LVPECL differential I/O DC core supply voltage Notes: 1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-17 on page 2-22. VMV and VCCI should be at the same voltage within a given I/O bank. 2. All parameters representing voltages are measured with respect to GND unless otherwise specified. 3. VPUMP can be left floating during normal operation (not programming mode). 4. VMV pins must be connected to the corresponding VCCI pins. See the Pin Descriptions chapter for further information. Tj (°C) 70 85 100 105 110 115 120 125 130 135 140 145 150 HTR Lifetime (yrs) 102.7 43.8 20.0 15.6 12.3 9.7 7.7 6.2 5.0 4.0 3.3 2.7 2.2 110 100 90 80 70 60 50 40 30 20 10 0 70 85 100 105 110 115 120 125 130 135 140 145 150 Temperature (ºC) Note: HTR time is the period during which you would not expect a verify failure due to flash cell leakage. Figure 2-1 • High-Temperature Data Retention (HTR) 2 -2 Years A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Table 2-3 • Overshoot and Undershoot Limits Average VCCI–GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle 10% 5% 3V 3.3 V 3.6 V Notes: 1. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 2. This table does not provide PCI overshoot/undershoot limits. 10% 5% 10% 5% 10% 5% Maximum Overshoot/ Undershoot (125°C) 0.72 V 0.82 V 0.72 V 0.81 V 0.69 V 0.79 V N/A N/A VCCI and VMV 2.7 V or less A dv a n c e v 0. 1 2-3 Radiation-Tolerant ProASIC3 FPGAs I/O Power-Up and Supply Voltage Thresholds for Power-On Reset Sophisticated power-up management circuitry is designed into every ProASIC®3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-2 on page 2-5 and Figure 2-3 on page 2-6. There are five regions to consider during power-up. RT ProASIC3 I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-2 on page 2-5 and Figure 2-3 on page 2-6). 2. VCCI > VCC – 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: • • During programming, I/Os become tristated and weakly pulled up to VCCI. JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. 2 -4 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic, at least until VCC and VCCPLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-2 and Figure 2-3 on page 2-6 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the PowerUp/-Down Behavior of Low-Power Flash Devices chapter of the handbook for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers Output buffers, after 200 ns delay from input buffer activation. VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 1: I/O Buffers are OFF Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH/VOL , etc. VCC = 1.425 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Activation trip point: Va = 0.85 V ± 0.25 V Deactivation trip point: Vd = 0.75 V ± 0.25 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V ± 0.3 V Deactivation trip point: Vd = 0.8 V ± 0.3 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V VCCI Figure 2-2 • Devices Operating at 1.5 V Core – I/O State as a Function of VCCI and VCC Voltage Levels A dv a n c e v 0. 1 2-5 Radiation-Tolerant ProASIC3 FPGAs VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 1: I/O Buffers are OFF Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH/VOL , etc. VCC = 1.14 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Activation trip point: Va = 0.85 V ± 0.2 V Deactivation trip point: Vd = 0.75 V ± 0.2 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V ± 0.15 V Deactivation trip point: Vd = 0.8 V ± 0.15 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.14 V,1.425 V, 1.7 V, 2.3 V, or 3.0 V VCCI Figure 2-3 • Device Operating at 1.2 V Core Voltage – I/O State as a Function of VCCI and VCC Voltage Levels 2 -6 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Thermal Characteristics Introduction The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction temperature to be higher than the ambient temperature. EQ 2-1 can be used to calculate junction temperature. TJ = Junction Temperature = ΔT + TA EQ 2-1 where: TA = Ambient Temperature ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P θja = Junction-to-ambient of the package. θja numbers are located in Table 2-4. P = Power dissipation Package Thermal Characteristics The device junction-to-case thermal resistivity is θjc and the junction-to-ambient air thermal resistivity is θja. The thermal characteristics for θja are shown for two air flow rates. The recommended maximum junction temperature is 125°C. EQ 2-2 shows a sample calculation of the recommended maximum power dissipation allowed for a 484-pin CCGA package with the junction at 125°C and with the case temperature maintained at 70°C. Max. junction temp. ( ° C) – Max. case temp. ( ° C) Maximum Power Allowed = ---------------------------------------------------------------------------------------------------------------------------θ jc ( ° C/W) EQ 2-2 Table 2-4 • Package Thermal Resistivities θja Package Type Ceramic Column Grid Array (CCGA) Device RT3PE600L RT3PE3000L RT3PE3000L Pin Count 484 484 896 θjc TBD TBD TBD Still Air 200 ft./min. 500 ft./min. Units TBD TBD TBD TBD TBD TBD TBD TBD TBD C/W C/W C/W A dv a n c e v 0. 1 2-7 Radiation-Tolerant ProASIC3 FPGAs Temperature and Voltage Derating Factors Table 2-5 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 125°C, VCC = 1.14 V) Junction Temperature Array Voltage VCC (V) 1.14 1.2 1.26 1.3 1.35 1.4 1.425 1.5 1.575 –55°C 0.86 0.83 0.79 0.77 0.75 0.72 0.70 0.67 0.64 –40°C 0.87 0.84 0.80 0.78 0.75 0.73 0.71 0.67 0.65 0°C 0.90 0.87 0.83 0.81 0.78 0.75 0.74 0.70 0.67 25°C 0.92 0.89 0.85 0.83 0.80 0.77 0.76 0.71 0.69 70°C 0.96 0.93 0.89 0.86 0.83 0.80 0.79 0.75 0.72 85°C 0.98 0.94 0.90 0.88 0.85 0.81 0.80 0.76 0.73 125°C 1.00 0.96 0.92 0.90 0.87 0.83 0.82 0.78 0.75 2 -8 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Calculating Power Dissipation Quiescent Supply Current Table 2-6 • Quiescent Supply Current (IDD) Characteristics When Using Flash*Freeze Mode in RT ProASIC3* Core Voltage Typical (25°C) 1.2 V 1.5 V RT3PE600L RT3PE3000L 2.75 Units mA mA * IDD includes VCC , VPUMP, VCCI, VJTAG , and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7). Table 2-7 • Quiescent Supply Current (IDD) Characteristics, RT ProASIC3 Sleep Mode (VCC = 0 V)* Core Voltage VCCI / VJTAG = 1.2 V (per bank) Typical (25°C) VCCI / VJTAG = 1.5 V (per bank) Typical (25°C) VCCI / VJTAG = 1.8 V (per bank) Typical (25°C) VCCI / VJTAG = 2.5 V (per bank) Typical (25°C) VCCI / VJTAG = 3.3 V (per bank) Typical (25°C) 1.2 V / 1.5 V 1.2 V / 1.5 V 1.2 V / 1.5 V 1.2 V / 1.5 V 1.2 V / 1.5 V RT3PE600L 1.7 1.8 1.9 2.2 2.5 RT3PE3000L 1.7 1.8 1.9 2.2 2.5 Units µA µA µA µA µA * IDD includes VCC , VPUMP, and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7). Table 2-8 • Quiescent Supply Current (IDD) Characteristics Shutdown Mode, (VCC and VCCI = 0 V)* Core Voltage Typical (25°C) 1.2 V / 1.5 V RT3PE600L 0 µA RT3PE3000L * IDD includes VCC , VPUMP, VCCI, VJTAG , and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7). A dv a n c e v 0. 1 2-9 Radiation-Tolerant ProASIC3 FPGAs Table 2-9 • Quiescent Supply Current (IDD), RT ProASIC3 Flash*Freeze Mode1 Core Voltage ICCA Current 2 RT3PE600L RT3PE3000L Units Typical (25°C) 1.2 V 1.5 V 2.75 mA mA ICCI or IJTAG Current 3, 4 VCCI / VJTAG = 1.2 V (per bank) Typical (25°C) VCCI / VJTAG = 1.5 V (per bank) Typical (25°C) VCCI / VJTAG = 1.8 V (per bank) Typical (25°C) VCCI / VJTAG = 2.5 V (per bank) Typical (25°C) VCCI / VJTAG = 3.3 V (per bank) Typical (25°C) Notes: 1.2 V / 1.5 V 1.2 V / 1.5 V 1.2 V / 1.5 V 1.2 V / 1.5 V 1.2 V / 1.5 V 1.7 1.8 1.9 2.2 2.5 1.7 1.8 1.9 2.2 2.5 µA µA µA µA µA 1. To calculate total device IDD, multiply the number of banks used by ICCI and add ICCA contribution. 2. Includes VCC , VCCPLL , and VPUMP currents. 3. Per VCCI or VJTAG bank. 4. Values do not include I/O static contribution (PDC6 and PDC7). 2 -1 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Power per I/O Pin Table 2-10 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings VCCI (V) Single-Ended 3.3 V LVTTL/LVCMOS 3.3 V LVTTL/LVCMOS – Schmitt trigger 2.5 V LVCMOS 2.5 V LVCMOS – Schmitt trigger 1.8 V LVCMOS 1.8 V LVCMOS – Schmitt trigger 1.5 V LVCMOS (JESD8-11) 1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.2 V LVCMOS 3 Static Power PDC6 (mW)1 Dynamic Power PAC9 (µW/MHz)2 3.3 3.3 2.5 2.5 1.8 1.8 1.5 1.5 1.2 trigger3 1.2 3.3 3.3 3.3 3.3 – – – – – – – – – – – – – – 16.34 24.49 4.71 6.13 1.66 1.78 1.01 0.97 0.60 0.53 17.76 19.10 17.76 19.10 1.2 V LVCMOS (JESD8-11) – Schmitt 3.3 V PCI 3.3 V PCI – Schmitt trigger 3.3 V PCI-X 3.3 V PCI-X – Schmitt trigger Voltage-Referenced 3.3 V GTL 2.5 V GTL 3.3 V GTL+ 2.5 V GTL+ HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) Differential LVDS LVPECL Notes: 3.3 2.5 3.3 2.5 1.5 1.5 2.5 2.5 3.3 3.3 2.90 2.13 2.81 2.57 0.17 0.17 1.38 1.38 3.21 3.21 7.07 3.62 2.97 2.55 0.85 0.85 3.30 3.30 8.08 8.08 2.5 3.3 2.26 5.71 0.95 1.62 1. PDC6 is the static power (where applicable) measured on VCCI. 2. PAC9 is the total dynamic power measured on VCCI. A dv a n c e v 0. 1 2 - 11 Radiation-Tolerant ProASIC3 FPGAs Table 2-11 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 CLOAD (pF) Single-Ended 3.3 V LVTTL/LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS 3.3 V PCI 3.3 V PCI-X Voltage-Referenced 3.3 V GTL 2.5 V GTL 3.3 V GTL+ 2.5 V GTL+ HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) Differential LVDS LVPECL Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC7 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI. – – 2.5 3.3 7.70 19.42 89.62 168.02 10 10 10 10 20 20 30 30 30 30 3.3 2.5 3.3 2.5 1.5 1.5 2.5 2.5 3.3 3.3 – – – – 7.08 13.88 16.69 25.91 26.02 42.21 24.08 13.52 24.10 13.54 26.22 27.22 105.56 116.60 114.87 131.76 4 VCCI (V) Static Power PDC7 (mW)2 Dynamic Power PAC10 (µW/MHz)3 5 5 5 5 5 10 10 3.3 2.5 1.8 1.5 1.2 3.3 3.3 – – – – – – – 148.00 83.23 54.58 37.05 17.94 204.61 204.61 2 -1 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-12 • Different Components Contributing to Dynamic Power Consumption in Devices Operating at 1.2 V VCC Device-Specific Dynamic Power (µW/MHz) Parameter PAC1 PAC2 PAC3 PAC4 PAC5 PAC6 PAC7 PAC8 PAC9 PAC10 PAC11 PAC12 PAC13 Definition Clock contribution of a Global Rib Clock contribution of a Global Spine Clock contribution of a VersaTile row Clock contribution of a VersaTile used as a sequential module First contribution of a VersaTile used as a sequential module Second contribution of a VersaTile used as a sequential module Contribution of a VersaTile used as a combinatorial module Average contribution of a routing net Contribution of an I/O input pin (standard-dependent) Contribution of an I/O output pin (standard-dependent) Average contribution of a RAM block during a read operation Average contribution of a RAM block during a write operation Dynamic contribution for PLL RT3PE3000L 12.61 2.66 0.56 0.07 0.05 0.19 0.11 0.45 See Table 2-10 on page 2-11. See Table 2-11 on page 2-12. 25.00 30.00 1.74 RT3PE600L A dv a n c e v 0. 1 2 - 13 Radiation-Tolerant ProASIC3 FPGAs Table 2-13 • Different Components Contributing to Dynamic Power Consumption in RT ProASIC3 Devices at 1.5 V VCC Device-Specific Dynamic Power (µW/MHz) Parameter PAC1 PAC2 PAC3 PAC4 PAC5 PAC6 PAC7 PAC8 PAC9 PAC10 PAC11 PAC12 PAC13 Definition Clock contribution of a Global Rib Clock contribution of a Global Spine Clock contribution of a VersaTile row Clock contribution of a VersaTile used as a sequential module First contribution of a VersaTile used as a sequential module Second contribution of a VersaTile used as a sequential module Contribution of a VersaTile used as a combinatorial module Average contribution of a routing net Contribution of an I/O input pin (standard-dependent) Contribution of an I/O output pin (standard-dependent) Average contribution of a RAM block during a read operation Average contribution of a RAM block during a write operation Dynamic contribution for PLL RT3PE3000L 19.7 4.16 0.88 0.12 0.07 0.29 0.29 0.70 See Table 2-10 on page 2-11. See Table 2-11 on page 2-12. 25.00 30.00 2.60 RT3PE600L Table 2-14 • Different Components Contributing to the Static Power Consumption in RT ProASIC3 Devices Device-Specific Dynamic Power (µW) Parameter PDC1 PDC2 PDC3 PDC4 PDC5 Definition Array static power in Active mode Array static power in Static (Idle) mode Array static power in Flash*Freeze mode Static PLL contribution at 1.2 V operating core voltage Static PLL contribution 1.5 V operating core voltage Bank quiescent power (VCCI-dependent) RT3PE3000L RT3PE600L See Table 2-9 on page 2-10. See Table 2-9 on page 2-10. See Table 2-6 on page 2-9. 1.42 mW 2.55 mW See Table 2-6 on page 2-9, Table 2-7 on page 2-9, Table 2-9 on page 2-10. See Table 2-10 on page 2-11. See Table 2-11 on page 2-12. PDC6 PDC7 I/O input pin static power (standard-dependent) I/O output pin static power (standard-dependent) * For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or SmartPower tool in Libero® Integrated Design Environment (IDE). 2 -1 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation methodology described below uses the following variables: • • • • • • • • The number of PLLs as well as the number and the frequency of each output clock generated The number of combinatorial and sequential cells used in the design The internal clock frequencies The number and the standard of I/O pins used in the design The number of RAM blocks used in the design Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-15 on page 2-17. Enable rates of output buffers—guidelines are provided for typical applications in Table 2-16 on page 2-17. Read rate and write rate to the memory—guidelines are provided for typical applications in Table 2-16 on page 2-17. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—PTOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption—PSTAT PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS* PDC5 + NINPUTS* PDC6 + NOUTPUTS* PDC7 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. NBANKS is the number of I/O banks powered in the design. Total Dynamic Power Consumption—PDYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution—PCLOCK PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK NSPINE is the number of global spines used in the user design—guidelines are provided in Table 2-15 on page 2-17. NROW is the number of VersaTile rows used in the design—guidelines are provided in Table 2-15 on page 2-17. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution—PS-CELL PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-15 on page 2-17. FCLK is the global clock signal frequency. A dv a n c e v 0. 1 2 - 15 Radiation-Tolerant ProASIC3 FPGAs Combinatorial Cells Contribution—PC-CELL PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. page 2-17. FCLK is the global clock signal frequency. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-15 on Routing Net Contribution—PNET PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. page 2-17. FCLK is the global clock signal frequency. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-15 on I/O Input Buffer Contribution—PINPUTS PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. FCLK is the global clock signal frequency. α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-15 on page 2-17. I/O Output Buffer Contribution—POUTPUTS POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-15 on page 2-17. β1 is the I/O buffer enable rate—guidelines are provided in Table 2-16 on page 2-17. FCLK is the global clock signal frequency. RAM Contribution—PMEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. β2 is the RAM enable rate for read operations. β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-16 on page 2-17. FWRITE-CLOCK is the memory write clock frequency. PLL Contribution—PPLL PPLL = PDC4 + PAC13 *FCLKOUT FCLKOUT is the output clock frequency.1 1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution. 2 -1 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: • • The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. The average toggle rate of an 8-bit counter is 25%: – – – – – – Bit 0 (LSB) = 100% Bit 1 Bit 2 … Bit 7 (MSB) = 0.78125% Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 = 50% = 25% Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-15 • Toggle Rate Guidelines Recommended for Power Calculation Component Definition Toggle rate of VersaTile outputs I/O buffer toggle rate Guideline 10% 10% α1 α2 Component Table 2-16 • Enable Rate Guidelines Recommended for Power Calculation Definition I/O output buffer enable rate RAM enable rate for read operations RAM enable rate for write operations Guideline 100% 12.5% 12.5% β1 β2 β3 A dv a n c e v 0. 1 2 - 17 Radiation-Tolerant ProASIC3 FPGAs User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Y tPD = 0.78 ns Combinational Cell Y tPD = 0.67 ns tDP = 1.54 ns Combinational Cell Y tPD = 1.21 ns I/O Module (Registered) tPY = 1.84 ns LVPECL D Q tPD = 0.70 ns Combinational Cell Y tICLKQ = 0.33 ns tISUD = 0.36 ns Input LVTTL Clock Register Cell tPY = 1.48 ns I/O Module (Non-Registered) LVDS, B-LVDS, M-LVDS tPY = 2.04 ns tCLKQ = 0.76 ns tSUD = 0.59 ns Input LVTTL Clock tPY = 1.48 ns D Q Combinational Cell Y tPD = 0.65 ns tCLKQ = 0.76 ns tSUD = 0.9 ns Input LVTTL Clock tPY = 1.48 ns Register Cell D Q D tPD = 0.65 ns tDP = 2.83 ns tDP = 2.08 ns I/O Module (Non-Registered) LVTTL Output Drive Strength = 8 mA High Slew Rate tDP = 2.37 ns I/O Module (Non-Registered) LVCMOS 1.5 V Output Drive Strength = 4 mA High Slew Rate I/O Module (Non-Registered) LVTTL Output Drive Strength = 12 mA High Slew Rate LVPECL Combinational Cell Y I/O Module (Registered) Q LVTTL 3.3 V Output Drive Strength = 12 mA tDP = 2.08 ns High Slew Rate tOCLKQ = 0.81 ns tOSUD = 0.43 ns Figure 2-4 • Timing Model Operating Conditions: –1 Speed, Military Temperature Range (TJ = 125°C), Worst-Case VCC = 1.14 V (example for RT3PE3000L and RT3PE600L) 2 -1 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics tPY tDIN PAD D Y Q DIN To Array CLK tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F)) I/O Interface VIH Vtrip Vtrip VCC 50% Y GND tPY (R) tPY (F) VCC 50% DIN GND tDOUT (R) Figure 2-5 • Input Buffer Timing Model and Delays (example) PAD VIL 50% 50% tDOUT (F) A dv a n c e v 0. 1 2 - 19 Radiation-Tolerant ProASIC3 FPGAs tDOUT DQ D From Array I/O Interface CLK tDP PAD Std Load tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) tDOUT VCC 50% VCC (F) 0V DOUT tDOUT (R) 50% D DOUT 50% 50% VOH 0V Vtrip PAD tDP (R) Figure 2-6 • Output Buffer Model and Delays (example) Vtrip VOL tDP (F) 2 -2 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics tEOUT D E Q tZL, tZH, tHZ, tLZ, tZLS, tZHS CLK EOUT D D Q DOUT CLK PAD I/O Interface tEOUT = MAX(tEOUT(r), tEOUT(f)) VCC D VCC E 50% tEOUT (R) 50% EOUT tZL PAD Vtrip VOL 50% tEOUT (F) VCC 50% tHZ 90% VCCI 50% tZH VCCI Vtrip 10% VCCI 50% tLZ VCC D VCC E 50% tEOUT (R) VCC EOUT PAD Vtrip VOL 50% tZLS 50% VOH 50% tZHS Vtrip 50% tEOUT (F) Figure 2-7 • Tristate Output Buffer Timing Model and Delays (example) A dv a n c e v 0. 1 2 - 21 Radiation-Tolerant ProASIC3 FPGAs Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-17 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Military Conditions—Software Default Settings I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI 3.3 V PCI-X 3.3 V GTL 2.5 V GTL 3.3 V GTL+ 2.5 V GTL+ HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) Notes: 1. Currents are measured at 125°C junction temperature. 2. Output drive strength is below JEDEC specification. 3. Output slew rate can be extracted using the IBIS Models. 25 mA 2 VIL Drive Slew Max, V Strength Rate Min, V 12 mA High 12 mA High 12 mA High 12 mA High 2 mA High –0.3 0.35 * VCCI –0.3 0.35 * VCCI –0.3 0.35 * VCCI –0.3 0.7 –0.3 0.8 VIH Min, V 2 1.7 0.65 * VCCI 0.65 * VCCI 0.65 * VCCI Max, V 3.6 2.7 1.9 1.575 1.26 VOL Max, V 0.4 0.7 0.45 0.25 * VCCI 0.25 * VCCI VOH Min, V 2.4 1.7 VCCI – 0.45 0.75 * VCCI 0.75 * VCCI IOL1 IOH1 mA mA 12 12 12 12 2 12 12 12 12 2 Per PCI Specification Per PCI-X Specification –0.3 High 25 mA2 High 35 mA High 33 mA High 8 mA High 15 mA2 High 15 mA High 18 mA High 14 mA High 21 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.5 VCCI – 0.9 21 21 –0.3 VREF – 0.2 VREF + 0.2 3.6 0.7 VCCI – 1.1 14 14 –0.3 VREF – 0.2 VREF + 0.2 2.7 0.35 VCCI – 0.43 18 18 –0.3 VREF – 0.2 VREF + 0.2 2.7 0.54 VCCI – 0.62 15 15 –0.3 VREF – 0.1 VREF + 0.1 1.575 0.4 VCCI – 0.4 15 15 –0.3 VREF – 0.1 VREF + 0.1 1.575 0.4 VCCI – 0.4 8 8 –0.3 VREF – 0.1 VREF + 0.1 2.7 0.6 – 40 40 –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 51 51 –0.3 VREF – 0.05 VREF + 0.05 2.7 0.4 – 25 25 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25 2 -2 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Table 2-18 • Summary of Maximum and Minimum DC Input Levels Military IIL DC I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI 3.3 V PCI-X 3.3 V GTL 2.5 V GTL 3.3 V GTL+ 2.5 V GTL+ HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) Note: Military temperature range: –55°C to 125°C µA 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 IIH µA 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 A dv a n c e v 0. 1 2 - 23 Radiation-Tolerant ProASIC3 FPGAs Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-19 • Summary of AC Memory Points* Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS* 3.3 V PCI 3.3 V PCI-X 3.3 V GTL 2.5 V GTL 3.3 V GTL+ 2.5 V GTL+ HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) LVDS LVPECL Input Reference Voltage (VREF_TYP) – – – – – – – 0.8 V 0.8 V 1.0 V 1.0 V 0.75 V 0.75 V 1.25 V 1.25 V 1.5 V 1.5 V – – Board Termination Voltage (VTT_REF) – – – – – – – 1.2 V 1.2 V 1.5 V 1.5 V 0.75 V 0.75 V 1.25 V 1.25 V 1.485 V 1.485 V – – Measuring Trip Point (Vtrip) 1.4 V 1.2 V 0.90 V 0.75 V 0.6V 0.285 * VCCI (RR) 0.615 * VCCI (FF)) 0.285 * VCCI (RR) 0.615 * VCCI (FF) VREF VREF VREF VREF VREF VREF VREF VREF VREF VREF Cross point Cross point * Applicable to RT3PE600L and RT3PE3000L devices operating at 1.2 V core regions only. Table 2-20 • I/O AC Parameter Definitions Parameter tDP tPY tDOUT tEOUT tDIN tHZ tZH tLZ tZL tZHS tZLS Parameter Definition Data to Pad delay through the Output Buffer Pad to Data delay through the Input Buffer Data to Output Buffer delay through the I/O interface Enable to Output Buffer Tristate Control delay through the I/O interface Input Buffer to Data delay through the I/O interface Enable to Pad delay through the Output Buffer—HIGH to Z Enable to Pad delay through the Output Buffer—Z to HIGH Enable to Pad delay through the Output Buffer—LOW to Z Enable to Pad delay through the Output Buffer—Z to LOW Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW 2 -2 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics 1.2 V Core Operating Voltage Table 2-21 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Military-Case Conditions: TJ = 125°C, Worst Case VCC = 1.14 V, Worst Case VCCI External Resistor (Ω) Capacitive Load (pF) Drive Strength (mA) Slew Rate tE OU T (ns) tDOUT (ns) tPYS (ns) tDIN (ns) tZLS (ns) tDP (ns) tZH (ns) tPY (ns) tZL (ns) tLZ (ns) tHZ (ns) tZHS (ns) – – Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI 3.3 V PCI-X 12 mA High 12 mA High 12 mA High 12 mA High 2mA Per PCI spec Per PCI-X spec High 5 5 5 5 5 – – – – – 0.68 2.08 0.05 1.48 2.03 0.44 2.12 1.56 2.76 3.04 4.00 3.44 ns 0.68 2.12 0.05 1.74 2.16 0.44 2.16 1.74 2.84 2.94 4.04 3.63 ns 0.68 2.36 0.05 1.69 2.38 0.44 2.40 1.94 3.14 3.57 4.28 3.82 ns 0.68 2.71 0.05 1.86 2.59 0.44 2.76 2.24 3.34 3.68 4.64 4.12 ns 0.68 4.40 0.05 2.23 3.20 0.44 4.21 3.71 4.35 4.11 6.02 5.52 ns High 10 25 0.68 2.36 0.05 2.31 3.12 0.44 2.41 1.68 2.76 3.04 4.29 3.56 ns High 10 25 0.68 2.36 0.05 2.31 3.12 0.44 2.41 1.68 2.76 3.04 4.29 3.56 ns 3.3 V GTL 2.5 V GTL 3.3 V GTL+ 2.5 V GTL+ HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) LVDS LVPECL Notes: 25 mA High 10 25 0.68 1.75 0.05 1.98 25 mA High 10 25 0.68 1.79 0.05 1.92 35 mA High 10 25 0.68 1.73 0.05 1.98 33 mA High 10 25 0.68 1.86 0.05 1.92 8 mA High 20 25 0.68 2.68 0.05 2.34 – – – – – – – – – – – – 0.44 1.72 1.75 0.44 1.82 1.79 0.44 1.76 1.73 0.44 1.89 1.77 0.44 2.73 2.65 0.44 2.59 2.29 0.44 1.82 1.56 0.44 1.86 1.49 0.44 1.98 1.55 0.44 1.77 1.41 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 3.60 3.63 ns 3.70 3.68 ns 3.65 3.61 ns 3.78 3.65 ns 4.61 4.53 ns 4.48 4.17 ns 1.82 1.56 ns 1.86 1.49 ns 1.98 1.55 ns 1.77 1.41 ns – – ns ns 15 mA High 20 50 0.68 2.55 0.05 2.34 15 mA High 30 25 0.68 1.79 0.05 1.77 18 mA High 30 50 0.68 1.83 0.05 1.77 14 mA High 30 25 0.68 1.94 0.05 1.69 21 mA High 30 50 0.68 1.74 0.05 1.69 24 mA High 24 mA High – – – – 0.68 1.57 0.05 2.04 0.68 1.54 0.05 1.84 1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-13 on page 2-44 for connectivity. This resistor is not required during normal operation. A dv a n c e v 0. 1 2 - 25 Units Radiation-Tolerant ProASIC3 FPGAs 1.5 V Core Voltage Table 2-22 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst Case VCCI External Resistor (Ω) Capacitive Load (pF) Drive Strength (mA) Slew Rate tE OU T (ns) tDOUT (ns) tPYS (ns) tDIN (ns) tZLS (ns) tDP (ns) tZH (ns) tPY (ns) tZL (ns) tLZ (ns) tHZ (ns) tZHS (ns) – – Standard 3.3 V LVTTL / 12 mA High 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X 12 mA High 12 mA High 12 mA High 5 5 5 5 – – – – 0.52 2.08 0.03 1.48 2.03 0.34 2.12 1.56 2.76 3.04 4.00 3.44 ns 0.52 2.12 0.03 1.74 2.16 0.34 2.16 1.74 2.84 2.94 4.04 3.63 ns 0.52 2.36 0.03 1.69 2.38 0.34 2.40 1.94 3.14 3.57 4.28 3.82 ns 0.52 2.71 0.03 1.86 2.59 0.34 2.76 2.24 3.34 3.68 4.64 4.12 ns Per PCI High 10 25 0.52 2.36 0.03 2.31 3.12 0.34 2.41 1.68 2.76 3.04 4.29 3.56 ns spec Per PCI-X spec High 10 25 0.52 2.36 0.03 2.31 3.12 0.34 2.41 1.68 2.76 3.04 4.29 3.56 ns 3.3 V GTL 2.5 V GTL 3.3 V GTL+ 2.5 V GTL+ HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) LVDS LVPECL Notes: 25 mA High 10 25 0.52 1.75 0.03 1.98 25 mA High 10 25 0.52 1.79 0.03 1.92 35 mA High 10 25 0.52 1.73 0.03 1.98 33 mA High 10 25 0.52 1.86 0.03 1.92 8 mA High 20 25 0.52 2.68 0.03 2.34 – – – – – – – – – – – – 0.34 1.72 1.75 0.34 1.82 1.79 0.34 1.76 1.73 0.34 1.89 1.77 0.34 2.73 2.65 0.34 2.59 2.29 0.34 1.82 1.56 0.34 1.86 1.49 0.34 1.98 1.55 0.34 1.77 1.41 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 3.60 3.63 ns 3.70 3.68 ns 3.65 3.61 ns 3.78 3.65 ns 4.61 4.53 ns 4.48 4.17 ns 1.82 1.56 ns 1.86 1.49 ns 1.98 1.55 ns 1.77 1.41 ns – – ns ns 15 mA High 20 50 0.52 2.55 0.03 2.34 15 mA High 30 25 0.52 1.79 0.03 1.77 18 mA High 30 50 0.52 1.83 0.03 1.77 14 mA High 30 25 0.52 1.94 0.03 1.69 21 mA High 30 50 0.52 1.74 0.03 1.69 24 mA High 24 mA High – – – – 0.52 1.57 0.03 2.04 0.52 1.54 0.03 1.84 1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-13 on page 2-44 for connectivity. This resistor is not required during normal operation. Detailed I/O DC Characteristics Table 2-23 • Input Capacitance Symbol CIN CINCLK Input capacitance Input capacitance on the clock pin Definition Conditions VIN = 0, f = 1.0 MHz VIN = 0, f = 1.0 MHz Min. Max. 8 8 Units pF pF 2 -2 6 A d v a n c e v 0. 1 Units Radiation-Tolerant ProASIC3 DC and Switching Characteristics Table 2-24 • I/O Output Buffer Maximum Resistances1 Standard 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA 2.5 V LVCMOS 4 mA 8 mA 12 mA 16 mA 24 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 1.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 1.2 V LVCMOS 3.3 V PCI/PCI-X 3.3 V GTL 2.5 V GTL 3.3 V GTL+ 2.5 V GTL+ HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHs pe c 2 mA Per PCI/PCI-X specification 25 mA 25 mA 35 mA 33 mA 8 mA 15 mA 15 mA 18 mA 14 mA 21 mA RPULL-DOWN (Ω)2 100 50 25 17 11 100 50 25 20 11 200 100 50 50 20 20 200 100 67 33 33 TBD 25 11 14 12 15 50 25 27 13 44 18 RPULL-UP (Ω)3 300 150 75 50 33 200 100 50 40 22 225 112 56 56 22 22 224 112 75 37 37 TBD 75 – – – – 50 25 31 15 69 32 A dv a n c e v 0. 1 2 - 27 Radiation-Tolerant ProASIC3 FPGAs Table 2-25 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(WEAK PULL-UP)1 (Ω) VCCI 3.3 V 2.5 V 1.8 V 1.5 V 1.2 V Notes: 1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN) 2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN) Min. 10 k 11 k 18 k 19 k TBD Max. 45 k 55 k 70 k 90 k TBD R(WEAK PULL-DOWN)2 (Ω) Min. 10 k 12 k 17 k 19 k TBD Max. 45 k 74 k 110 k 140 k TBD 2 -2 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Table 2-26 • I/O Short Currents IOSH/IOSL Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 4 mA 8 mA 12 mA 16 mA 24 mA 2.5 V LVCMOS 4 mA 8 mA 12 mA 16 mA 24 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 1.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 1.2 V LVCMOS 3.3 V PCI/PCIX 3.3 V GTL 2.5 V GTL 3.3 V GTL+ 2.5 V GTL+ HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) * TJ = 100°C 2mA Per PCI/PCI-X Specification 25 mA 25 mA 35 mA 33 mA 8 mA 15 mA 15 mA 18 mA 14 mA 21 mA 268 169 268 169 32 66 83 169 51 103 IOSL (mA)* 25 51 103 132 268 16 32 65 83 169 9 17 35 45 91 91 13 25 32 66 66 TBD Per PCI Curves 181 124 181 124 39 55 87 124 54 109 IOSH (mA)* 27 54 109 127 181 18 37 74 87 124 11 22 44 51 74 74 16 33 39 55 55 TBD A dv a n c e v 0. 1 2 - 29 Radiation-Tolerant ProASIC3 FPGAs Table 2-27 • Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (typical) for Schmitt Mode Input Buffers Applicable Input Buffer Configuration 3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 2.5 V LVCMOS (Schmitt trigger mode) 1.8 V LVCMOS (Schmitt trigger mode) 1.5 V LVCMOS (Schmitt trigger mode) 1.2 V LVCMOS (Schmitt trigger mode) Hysteresis Value (typical) 240 mV 140 mV 80 mV 60 mV 40 mV The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 110°C, the short current condition would have to be sustained for more than three months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-28 • Duration of Short Circuit Event before Failure Temperature –40°C 0°C 25°C 70°C 85°C 100°C 110°C 125°C Table 2-29 • I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer LVTTL/LVCMOS LVDS/B-LVDS/ M-LVDS/LVPECL Input Rise/Fall Time (min.) No requirement No requirement Input Rise/Fall Time (max.) 10 ns * 10 ns * Reliability 20 years (110°C) 10 years (100°C) Time before Failure > 20 years > 20 years > 20 years 5 years 2 years 6 months 3 months 1 month * The maximum input rise/fall time is related to the noise induced in the input buffer trace. If the noise is low, the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. 2 -3 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-30 • Minimum and Maximum DC Input and Output Levels 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. 3. Software default selection highlighted in gray. VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 –0.3 –0.3 –0.3 –0.3 –0.3 0.8 0.8 0.8 0.8 0.8 2 2 2 2 2 3.6 3.6 3.6 3.6 3.6 0.4 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 2.4 4 8 4 8 25 51 103 132 268 27 54 109 127 181 15 15 15 15 15 15 15 15 15 15 12 12 16 16 24 24 Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-8 • AC Loading Table 2-31 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 3.3 Measuring Point* (V) 1.4 CLOAD (pF) 5 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. A dv a n c e v 0. 1 2 - 31 Radiation-Tolerant ProASIC3 FPGAs Timing Characteristics 1.2 V DC Core Voltage Table 2-32 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Speed Grade Std. –1 Std. –1 Std. –1 Std. –1 Std. –1 tDOUT 0.80 0.68 0.80 0.68 0.80 0.68 0.80 0.68 0.80 0.68 tDP 6.03 5.13 4.93 4.19 4.15 3.53 3.92 3.34 3.81 3.24 tDIN 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 tPY 1.74 1.48 1.74 1.48 1.74 1.48 1.74 1.48 1.74 1.48 tPYS 2.39 2.03 2.39 2.03 2.39 2.03 2.39 2.03 2.39 2.03 tEOUT 0.52 0.44 0.52 0.44 0.52 0.44 0.52 0.44 0.52 0.44 tZL 6.14 5.22 5.02 4.27 4.22 3.59 3.99 3.40 3.88 3.30 tZH 4.84 4.12 4.14 3.52 3.61 3.07 3.49 2.97 3.51 2.98 tLZ 2.66 2.27 3.01 2.56 3.24 2.76 3.29 2.80 3.35 2.85 tHZ 2.42 2.06 3.03 2.58 3.43 2.92 3.54 3.01 3.92 3.34 tZLS 8.35 7.11 7.23 6.15 6.44 5.47 6.21 5.28 6.09 5.18 tZHS 7.06 6.00 6.35 5.40 5.82 4.95 5.71 4.85 5.72 4.87 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-33 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Speed Grade Std. –1 Std. –1 Std. –1 Std. –1 Std. –1 tDOUT 0.80 0.68 0.80 0.68 0.80 0.68 0.80 0.68 0.80 0.68 tDP 3.39 2.89 2.79 2.37 2.45 2.08 2.39 2.03 2.41 2.05 tDIN 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 tPY 1.74 1.48 1.74 1.48 1.74 1.48 1.74 1.48 1.74 1.48 tPYS 2.39 2.03 2.39 2.03 2.39 2.03 2.39 2.03 2.39 2.03 tEOUT 0.52 0.44 0.52 0.44 0.52 0.44 0.52 0.44 0.52 0.44 tZL 3.45 2.94 2.84 2.42 2.49 2.12 2.43 2.07 2.46 2.09 tZH 2.60 2.21 2.08 1.77 1.83 1.56 1.79 1.52 1.72 1.47 tLZ 2.66 2.27 3.02 2.57 3.24 2.76 3.30 2.80 3.35 2.85 tHZ 2.56 2.18 3.18 2.70 3.58 3.04 3.69 3.14 4.08 3.47 tZLS 5.67 4.82 5.05 4.30 4.71 4.00 4.65 3.95 4.67 3.97 tZHS 4.81 4.10 4.30 3.65 4.05 3.44 4.00 3.40 3.94 3.35 Units ns ns ns ns ns ns ns ns ns ns 2 -3 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics 1.5 V DC Core Voltage Table 2-34 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Speed Grade Std. –1 Std. –1 Std. –1 Std. –1 Std. –1 tDOUT 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 tDP 6.03 5.13 4.93 4.19 4.15 3.53 3.92 3.34 3.81 3.24 tDIN 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 tPY 1.74 1.48 1.74 1.48 1.74 1.48 1.74 1.48 1.74 1.48 tPYS 2.39 2.03 2.39 2.03 2.39 2.03 2.39 2.03 2.39 2.03 tEOUT 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 tZL 6.14 5.22 5.02 4.27 4.22 3.59 3.99 3.40 3.88 3.30 tZH 4.84 4.12 4.14 3.52 3.61 3.07 3.49 2.97 3.51 2.98 tLZ 2.66 2.27 3.01 2.56 3.24 2.76 3.29 2.80 3.35 2.85 tHZ 2.42 2.06 3.03 2.58 3.43 2.92 3.54 3.01 3.92 3.34 tZLS 8.35 7.11 7.23 6.15 6.44 5.47 6.21 5.28 6.09 5.18 tZHS 7.06 6.00 6.35 5.40 5.82 4.95 5.71 4.85 5.72 4.87 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-35 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Speed Grade Std. –1 Std. –1 Std. –1 Std. –1 Std. –1 tDOUT 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 tDP 3.39 2.89 2.79 2.37 2.45 2.08 2.39 2.03 2.41 2.05 tDIN 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 tPY 1.74 1.48 1.74 1.48 1.74 1.48 1.74 1.48 1.74 1.48 tPYS 2.39 2.03 2.39 2.03 2.39 2.03 2.39 2.03 2.39 2.03 tEOUT 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 tZL 3.45 2.94 2.84 2.42 2.49 2.12 2.43 2.07 2.46 2.09 tZH 2.60 2.21 2.08 1.77 1.83 1.56 1.79 1.52 1.72 1.47 tLZ 2.66 2.27 3.02 2.57 3.24 2.76 3.30 2.80 3.35 2.85 tHZ 2.56 2.18 3.18 2.70 3.58 3.04 3.69 3.14 4.08 3.47 tZLS 5.67 4.82 5.05 4.30 4.71 4.00 4.65 3.95 4.67 3.97 tZHS 4.81 4.10 4.30 3.65 4.05 3.44 4.00 3.40 3.94 3.35 Units ns ns ns ns ns ns ns ns ns ns A dv a n c e v 0. 1 2 - 33 Radiation-Tolerant ProASIC3 FPGAs 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table 2-36 • Minimum and Maximum DC Input and Output Levels 2.5 V LVCMOS Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. 3. Software default selection highlighted in gray. VIL VIH VOL VOH IOL IOH IOSL 1 IOSH Max., mA 18 37 74 87 124 1 IIL 2 IIH Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA –0.3 –0.3 –0.3 –0.3 –0.3 0.7 0.7 0.7 0.7 0.7 1.7 1.7 1.7 1.7 1.7 2.7 2.7 2.7 2.7 2.7 0.7 0.7 0.7 0.7 0.7 1.7 1.7 1.7 1.7 1.7 4 8 4 8 16 32 65 83 169 µA µA2 15 15 15 15 15 15 15 15 15 15 12 12 16 16 24 24 Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-9 • AC Loading Table 2-37 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 2.5 Measuring Point* (V) 1.2 CLOAD (pF) 5 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. 2 -3 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Timing Characteristics 1.2 V DC Core Voltage Table 2-38 • 2.5 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Drive Strength 4 mA Speed Grade Std. –1 8 mA Std. –1 12 mA Std. –1 16 mA Std. –1 24 mA Std. –1 tDOUT 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 tDP 6.86 5.84 5.61 4.77 4.72 4.02 4.45 3.79 4.33 3.69 tDIN 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 tPY 2.04 1.74 2.04 1.74 2.04 1.74 2.04 1.74 2.04 1.74 tPYS 2.54 2.16 2.54 2.16 2.54 2.16 2.54 2.16 2.54 2.16 tEOUT 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 tZL 6.99 5.95 5.72 4.86 4.81 4.09 4.53 3.86 4.41 3.76 tZH 5.83 4.96 4.94 4.20 4.30 3.66 4.16 3.54 4.18 3.55 tLZ 2.69 2.29 3.07 2.61 3.33 2.84 3.39 2.88 3.46 2.94 tHZ 2.17 1.85 2.90 2.47 3.36 2.86 3.49 2.97 3.96 3.37 tZLS 9.20 7.83 7.93 6.75 7.02 5.98 6.75 5.74 6.63 5.64 tZHS 8.04 6.84 7.15 6.08 6.51 5.54 6.37 5.42 6.39 5.43 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-39 • 2.5 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Drive Strength 4 mA Speed Grade Std. –1 8 mA Std. –1 12 mA Std. –1 16 mA Std. –1 24 mA Std. –1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. tDOUT 0.80 0.68 0.80 0.68 0.80 0.68 0.80 0.68 0.80 0.68 tDP 3.50 2.98 2.87 2.44 2.49 2.12 2.42 2.06 2.43 2.07 tDIN 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 tPY 2.04 1.74 2.04 1.74 2.04 1.74 2.04 1.74 2.04 1.74 tPYS 2.54 2.16 2.54 2.16 2.54 2.16 2.54 2.16 2.54 2.16 tEOUT 0.52 0.44 0.52 0.44 0.52 0.44 0.52 0.44 0.52 0.44 tZL 3.57 3.03 2.92 2.48 2.53 2.16 2.47 2.10 2.48 2.11 tZH 3.13 2.66 2.41 2.05 2.05 1.74 1.99 1.69 1.90 1.61 tLZ 2.69 2.29 3.07 2.61 3.33 2.84 3.39 2.88 3.46 2.94 tHZ 2.26 1.93 3.00 2.55 3.46 2.94 3.59 3.05 4.07 3.46 tZLS 5.78 4.92 5.13 4.37 4.75 4.04 4.68 3.98 4.69 3.99 tZHS 5.34 4.54 4.62 3.93 4.26 3.63 4.20 3.57 4.11 3.50 Units ns ns ns ns ns ns ns ns ns ns A dv a n c e v 0. 1 2 - 35 Radiation-Tolerant ProASIC3 FPGAs 1.5 V DC Core Voltage Table 2-40 • 2.5 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength 4 mA Speed Grade Std. –1 8 mA Std. –1 12 mA Std. –1 16 mA Std. –1 24 mA Std. –1 tDOUT 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 tDP 6.86 5.84 5.61 4.77 4.72 4.02 4.45 3.79 4.33 3.69 tDIN 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 tPY 2.04 1.74 2.04 1.74 2.04 1.74 2.04 1.74 2.04 1.74 tPYS 2.54 2.16 2.54 2.16 2.54 2.16 2.54 2.16 2.54 2.16 tEOUT 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 tZL 6.99 5.95 5.72 4.86 4.81 4.09 4.53 3.86 4.41 3.76 tZH 5.83 4.96 4.94 4.20 4.30 3.66 4.16 3.54 4.18 3.55 tLZ 2.69 2.29 3.07 2.61 3.33 2.84 3.39 2.88 3.46 2.94 tHZ 2.17 1.85 2.90 2.47 3.36 2.86 3.49 2.97 3.96 3.37 tZLS 9.20 7.83 7.93 6.75 7.02 5.98 6.75 5.74 6.63 5.64 tZHS 8.04 6.84 7.15 6.08 6.51 5.54 6.37 5.42 6.39 5.43 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-41 • 2.5 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength 4 mA Speed Grade Std. –1 8 mA Std. –1 12 mA Std. –1 16 mA Std. –1 24 mA Std. –1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. tDOUT 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 tDP 3.50 2.98 2.87 2.44 2.49 2.12 2.42 2.06 2.43 2.07 tDIN 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 tPY 2.04 1.74 2.04 1.74 2.04 1.74 2.04 1.74 2.04 1.74 tPYS 2.54 2.16 2.54 2.16 2.54 2.16 2.54 2.16 2.54 2.16 tEOUT 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 tZL 3.57 3.03 2.92 2.48 2.53 2.16 2.47 2.10 2.48 2.11 tZH 3.13 2.66 2.41 2.05 2.05 1.74 1.99 1.69 1.90 1.61 tLZ 2.69 2.29 3.07 2.61 3.33 2.84 3.39 2.88 3.46 2.94 tHZ 2.26 1.93 3.00 2.55 3.46 2.94 3.59 3.05 4.07 3.46 tZLS 5.78 4.92 5.13 4.37 4.75 4.04 4.68 3.98 4.69 3.99 tZHS 5.34 4.54 4.62 3.93 4.26 3.63 4.20 3.57 4.11 3.50 Units ns ns ns ns ns ns ns ns ns ns 2 -3 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics 1.8 V LVCMOS Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-42 • Minimum and Maximum DC Input and Output Levels 1.8 V LVCMOS Drive Strength Min., V 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. 3. Software default selection highlighted in gray. –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 VIL Max., V VIH Min., V VOL Max., V Max., V 1.9 1.9 1.9 1.9 1.9 1.9 0.45 0.45 0.45 0.45 0.45 0.45 VOH Min., V VCCI – 0.45 VCCI – 0.45 VCCI – 0.45 VCCI – 0.45 IOL IOH IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 µA2 µA2 2 4 6 8 2 4 6 8 9 17 35 45 91 91 11 22 44 51 74 74 15 15 15 15 15 15 15 15 15 15 15 15 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI VCCI – 0.45 12 12 VCCI – 0.45 16 16 Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-10 • AC Loading Table 2-43 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 1.8 Measuring Point* (V) 0.9 CLOAD (pF) 5 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. A dv a n c e v 0. 1 2 - 37 Radiation-Tolerant ProASIC3 FPGAs Timing Characteristics 1.2 V DC Core Voltage Table 2-44 • 1.8 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Drive Strength 2 mA Speed Grade Std. –1 4 mA Std. –1 6 mA Std. –1 8 mA Std. –1 12 mA Std. –1 16 mA Std. –1 tDOUT 0.80 0.68 0.80 0.68 0.80 0.68 0.80 0.68 0.80 0.68 0.80 0.68 tDP 9.15 7.79 7.54 6.41 6.39 5.44 6.01 5.11 5.89 5.01 5.89 5.01 tDIN 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 tPY 1.98 1.69 1.98 1.69 1.98 1.69 1.98 1.69 1.98 1.69 1.98 1.69 tPYS 2.80 2.38 2.80 2.38 2.80 2.38 2.80 2.38 2.80 2.38 2.80 2.38 tEOUT 0.52 0.44 0.52 0.44 0.52 0.44 0.52 0.44 0.52 0.44 0.52 0.44 tZL 9.32 7.93 7.68 6.53 6.51 5.54 6.12 5.20 6.00 5.11 6.00 5.11 tZH 7.69 6.54 6.48 5.51 5.65 4.80 5.48 4.66 5.49 4.67 5.49 4.67 tLZ 2.75 2.34 3.22 2.74 3.53 3.00 3.60 3.07 3.70 3.15 3.70 3.15 tHZ 1.57 1.33 2.74 2.33 3.32 2.83 3.49 2.97 4.07 3.46 4.07 3.46 tZLS 11.54 9.81 9.89 8.42 8.72 7.42 8.33 7.09 8.22 6.99 8.22 6.99 tZHS 9.90 8.42 8.69 7.39 7.86 6.69 7.70 6.55 7.71 6.56 7.71 6.56 Units ns ns ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-45 • 1.8 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Speed Grade Std. –1 Std. –1 Std. –1 Std. –1 Std. –1 Std. –1 tDOUT 0.80 0.68 0.80 0.68 0.80 0.68 0.80 0.68 0.80 0.68 0.80 0.68 tDP 4.14 3.52 3.35 2.85 2.87 2.44 2.78 2.37 2.77 2.36 2.77 2.36 tDIN 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 tPY 1.98 1.69 1.98 1.69 1.98 1.69 1.98 1.69 1.98 1.69 1.98 1.69 tPYS 2.80 2.38 2.80 2.38 2.80 2.38 2.80 2.38 2.80 2.38 2.80 2.38 tEOUT 0.52 0.44 0.52 0.44 0.52 0.44 0.52 0.44 0.52 0.44 0.52 0.44 tZL 4.21 3.58 3.42 2.91 2.93 2.49 2.83 2.41 2.82 2.40 2.82 2.40 tZH 4.05 3.45 3.01 2.56 2.49 2.12 2.40 2.04 2.28 1.94 2.28 1.94 tLZ 2.75 2.34 3.22 2.74 3.53 3.00 3.60 3.06 3.70 3.14 3.70 3.14 tHZ 1.62 1.38 2.84 2.41 3.43 2.92 3.59 3.05 4.19 3.57 4.19 3.57 tZLS 6.43 5.47 5.63 4.79 5.14 4.37 5.05 4.29 5.03 4.28 5.03 4.28 tZHS 6.27 5.33 5.22 4.44 4.71 4.00 4.61 3.92 4.49 3.82 4.49 3.82 Units ns ns ns ns ns ns ns ns ns ns ns ns 2 -3 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics 1.5 V DC Core Voltage Table 2-46 • 1.8 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength 2 mA Speed Grade Std. –1 4 mA Std. –1 6 mA Std. –1 8 mA Std. –1 12 mA Std. –1 16 mA Std. –1 tDOUT 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 tDP 9.15 7.79 7.54 6.41 6.39 5.44 6.01 5.11 5.89 5.01 5.89 5.01 tDIN 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 tPY 1.98 1.69 1.98 1.69 1.98 1.69 1.98 1.69 1.98 1.69 1.98 1.69 tPYS 2.80 2.38 2.80 2.38 2.80 2.38 2.80 2.38 2.80 2.38 2.80 2.38 tEOUT 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 tZL 9.32 7.93 7.68 6.53 6.51 5.54 6.12 5.20 6.00 5.11 6.00 5.11 tZH 7.69 6.54 6.48 5.51 5.65 4.80 5.48 4.66 5.49 4.67 5.49 4.67 tLZ 2.75 2.34 3.22 2.74 3.53 3.00 3.60 3.07 3.70 3.15 3.70 3.15 tHZ 1.57 1.33 2.74 2.33 3.32 2.83 3.49 2.97 4.07 3.46 4.07 3.46 tZLS 11.54 9.81 9.89 8.42 8.72 7.42 8.33 7.09 8.22 6.99 8.22 6.99 tZHS 9.90 8.42 8.69 7.39 7.86 6.69 7.70 6.55 7.71 6.56 7.71 6.56 Units ns ns ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-47 • 1.8 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength 2 mA Speed Grade Std. –1 4 mA Std. –1 6 mA Std. –1 8 mA Std. –1 12 mA Std. –1 16 mA Std. –1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. tDOUT 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 tDP 4.14 3.52 3.35 2.85 2.87 2.44 2.78 2.37 2.77 2.36 2.77 2.36 tDIN 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 tPY 1.98 1.69 1.98 1.69 1.98 1.69 1.98 1.69 1.98 1.69 1.98 1.69 tPYS 2.80 2.38 2.80 2.38 2.80 2.38 2.80 2.38 2.80 2.38 2.80 2.38 tEOUT 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 tZL 4.21 3.58 3.42 2.91 2.93 2.49 2.83 2.41 2.82 2.40 2.82 2.40 tZH 4.05 3.45 3.01 2.56 2.49 2.12 2.40 2.04 2.28 1.94 2.28 1.94 tLZ 2.75 2.34 3.22 2.74 3.53 3.00 3.60 3.06 3.70 3.14 3.70 3.14 tHZ 1.62 1.38 2.84 2.41 3.43 2.92 3.59 3.05 4.19 3.57 4.19 3.57 tZLS 6.43 5.47 5.63 4.79 5.14 4.37 5.05 4.29 5.03 4.28 5.03 4.28 tZHS 6.27 5.33 5.22 4.44 4.71 4.00 4.61 3.92 4.49 3.82 4.49 3.82 Units ns ns ns ns ns ns ns ns ns ns ns ns A dv a n c e v 0. 1 2 - 39 Radiation-Tolerant ProASIC3 FPGAs 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-48 • Minimum and Maximum DC Input and Output Levels 1.5 V LVCMOS Drive Strength Min., V 2 mA 4 mA 6 mA 8 mA 12 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. 3. Software default selection highlighted in gray. –0.3 –0.3 –0.3 –0.3 –0.3 VIL Max., V VIH Min., V Max., V VOL Max., V VOH Min., V IOL IOH IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 µA2 µA2 2 4 6 8 13 25 32 66 66 16 33 39 55 55 15 15 15 15 15 15 15 15 15 15 0.35 * VCCI 0.65 * VCCI 1.575 0.35 * VCCI 0.65 * VCCI 1.575 0.35 * VCCI 0.65 * VCCI 1.575 0.35 * VCCI 0.65 * VCCI 1.575 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 2 0.25 * VCCI 0.75 * VCCI 4 0.25 * VCCI 0.75 * VCCI 6 0.25 * VCCI 0.75 * VCCI 8 0.25 * VCCI 0.75 * VCCI 12 12 Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-11 • AC Loading Table 2-49 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 1.5 Measuring Point* (V) 0.75 CLOAD (pF) 5 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. 2 -4 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Timing Characteristics 1.2 V DC Core Voltage Table 2-50 • 1.5 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA Speed Grade Std. –1 4 mA Std. –1 6 mA Std. –1 8 mA Std. –1 12 mA Std. –1 tDOUT 0.80 0.68 0.80 0.68 0.80 0.68 0.80 0.68 0.80 0.68 tDP 9.52 8.10 8.14 6.92 7.64 6.50 7.54 6.41 7.54 6.41 tDIN 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 tPY 2.19 1.86 2.19 1.86 2.19 1.86 2.19 1.86 2.19 1.86 tPYS 3.05 2.59 3.05 2.59 3.05 2.59 3.05 2.59 3.05 2.59 tEOUT 0.52 0.44 0.52 0.44 0.52 0.44 0.52 0.44 0.52 0.44 tZL 9.69 8.25 8.29 7.05 7.78 6.62 7.68 6.53 7.68 6.53 tZH 7.89 6.71 6.89 5.86 6.70 5.70 6.71 5.71 6.71 5.71 tLZ 3.37 2.87 3.73 3.17 3.80 3.24 3.93 3.34 3.93 3.34 tHZ 2.65 2.26 3.32 2.83 3.51 2.99 4.18 3.55 4.18 3.55 tZLS 11.91 10.13 10.50 8.93 9.99 8.50 9.89 8.41 9.89 8.41 tZHS 10.10 8.59 9.10 7.74 8.92 7.59 8.92 7.59 8.92 7.59 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-51 • 1.5 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA Speed Grade Std. –1 4 mA Std. –1 6 mA Std. –1 8 mA Std. –1 12 mA Std. –1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. tDOUT 0.80 0.68 0.80 0.68 0.80 0.68 0.80 0.68 0.80 0.68 tDP 3.91 3.32 3.33 2.83 3.22 2.74 3.18 2.71 3.18 2.71 tDIN 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 tPY 2.19 1.86 2.19 1.86 2.19 1.86 2.19 1.86 2.19 1.86 tPYS 3.05 2.59 3.05 2.59 3.05 2.59 3.05 2.59 3.05 2.59 tEOUT 0.52 0.44 0.52 0.44 0.52 0.44 0.52 0.44 0.52 0.44 tZL 3.98 3.38 3.39 2.89 3.28 2.79 3.24 2.76 3.24 2.76 tZH 3.54 3.01 2.90 2.47 2.78 2.37 2.63 2.24 2.63 2.24 tLZ 3.36 2.86 3.71 3.16 3.80 3.23 3.92 3.34 3.92 3.34 tHZ 2.76 2.35 3.44 2.93 3.63 3.09 4.33 3.68 4.33 3.68 tZLS 6.19 5.27 5.61 4.77 5.49 4.67 5.46 4.64 5.46 4.64 tZHS 5.76 4.90 5.12 4.35 5.00 4.25 4.85 4.12 4.85 4.12 Units ns ns ns ns ns ns ns ns ns ns A dv a n c e v 0. 1 2 - 41 Radiation-Tolerant ProASIC3 FPGAs 1.5 V DC Core Voltage Table 2-52 • 1.5 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA Speed Grade Std. –1 4 mA Std. –1 6 mA Std. –1 8 mA Std. –1 12 mA Std. –1 tDOUT 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 tDP 9.52 8.10 8.14 6.92 7.64 6.50 7.54 6.41 7.54 6.41 tDIN 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 tPY 2.19 1.86 2.19 1.86 2.19 1.86 2.19 1.86 2.19 1.86 tPYS 3.05 2.59 3.05 2.59 3.05 2.59 3.05 2.59 3.05 2.59 tEOUT 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 tZL 9.69 8.25 8.29 7.05 7.78 6.62 7.68 6.53 7.68 6.53 tZH 7.89 6.71 6.89 5.86 6.70 5.70 6.71 5.71 6.71 5.71 tLZ 3.37 2.87 3.73 3.17 3.80 3.24 3.93 3.34 3.93 3.34 tHZ 2.65 2.26 3.32 2.83 3.51 2.99 4.18 3.55 4.18 3.55 tZLS 11.91 10.13 10.50 8.93 9.99 8.50 9.89 8.41 9.89 8.41 tZHS 10.10 8.59 9.10 7.74 8.92 7.59 8.92 7.59 8.92 7.59 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-53 • 1.5 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA Speed Grade Std. –1 4 mA Std. –1 6 mA Std. –1 8 mA Std. –1 12 mA Std. –1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. tDOUT 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 0.61 0.52 tDP 3.91 3.32 3.33 2.83 3.22 2.74 3.18 2.71 3.18 2.71 tDIN 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 tPY 2.19 1.86 2.19 1.86 2.19 1.86 2.19 1.86 2.19 1.86 tPYS 3.05 2.59 3.05 2.59 3.05 2.59 3.05 2.59 3.05 2.59 tEOUT 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 0.40 0.34 tZL 3.98 3.38 3.39 2.89 3.28 2.79 3.24 2.76 3.24 2.76 tZH 3.54 3.01 2.90 2.47 2.78 2.37 2.63 2.24 2.63 2.24 tLZ 3.36 2.86 3.71 3.16 3.80 3.23 3.92 3.34 3.92 3.34 tHZ 2.76 2.35 3.44 2.93 3.63 3.09 4.33 3.68 4.33 3.68 tZLS 6.19 5.27 5.61 4.77 5.49 4.67 5.46 4.64 5.46 4.64 tZHS 5.76 4.90 5.12 4.35 5.00 4.25 4.85 4.12 4.85 4.12 Units ns ns ns ns ns ns ns ns ns ns 2 -4 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics 1.2 V LVCMOS (JESD8-12A) Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-54 • Minimum and Maximum DC Input and Output Levels Applicable to I/Os Operating at 1.2 V Core Voltage 1.2 V LVCMOS Drive Strength Min., V 2 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. 3. Software default selection highlighted in gray. –0.3 VIL Max., V VIH Min., V Max., V 1.26 VOL Max., V VOH Min., V IOL IOH IOSH1 IOSL1 IIL2 IIH2 mA mA Max., mA Max., mA µA µA 2 TBD TBD 15 15 0.35 * VCCI 0.65 * VCCI 0.25 * VCCI 0.75 * VCCI 2 Test Point Datapath Figure 2-12 • AC Loading 5 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Table 2-55 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 1.2 Measuring Point* (V) 0.6 CLOAD (pF) 5 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics 1.2 V DC Core Voltage Table 2-56 • 1.2 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA Speed Grade Std. –1 tDOUT 0.80 0.68 tDP tDIN tPY 2.62 2.23 tPYS 3.76 3.20 tEOUT 0.52 0.44 tZL 12.07 10.27 tZH 9.47 8.05 tLZ tHZ tZLS 14.20 12.08 tZHS 11.60 9.87 Units ns ns 12.62 0.05 10.73 0.05 5.12 4.68 4.36 3.98 Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-57 • 1.2 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Speed Grade Std. –1 tDOUT 0.80 0.68 tDP 5.17 4.40 tDIN 0.05 0.05 tPY 2.62 2.23 tPYS 3.76 3.20 tEOUT 0.52 0.44 tZL 4.95 4.21 tZH 4.36 3.71 tLZ tHZ tZLS 7.08 6.02 tZHS 6.49 5.52 Units ns ns 5.11 4.83 4.35 4.11 A dv a n c e v 0. 1 2 - 43 Radiation-Tolerant ProASIC3 FPGAs 3.3 V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-58 • Minimum and Maximum DC Input and Output Levels 3.3 V PCI/PCI-X Drive Strength Per PCI specification Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the database; Actel loadings for enable path characterization are described in Figure 2-13. IOL IOH IOSL IOSH IIL IIH 1 1 Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA Max, mA µA2 µA2 VIL Per PCI curves 15 15 VIH VOL VOH R = 25 Test Point Datapath R to VCCI for tDP (F) R to GND for tDP (R) R=1k Test Point Enable Path R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 10 pF for tZH /tZHS /tZL /t ZLS 5 pF for tHZ /tLZ Figure 2-13 • AC Loading AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is described in Table 2-59. Table 2-59 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 3.3 Measuring Point* (V) 0.285 * VCCI for tDP(R) 0.615 * VCCI for tDP(F) * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. CLOAD (pF) 10 Timing Characteristics 1.2 V DC Core Voltage Table 2-60 • 3.3 V PCI/PCI-X Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Speed Grade Std. –1 tDOUT 0.80 0.68 tDP 2.78 2.36 tDIN 0.05 0.05 tPY 2.72 2.31 tPYS 3.67 3.12 tEOUT 0.52 0.44 tZL 2.83 2.41 tZH 1.98 1.68 tLZ 3.24 2.76 tHZ 3.58 3.04 tZLS 5.04 4.29 tZHS 4.19 3.56 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 1.5 V DC Core Voltage Table 2-61 • 3.3 V PCI/PCI-X Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V Speed Grade Std. –1 tDOUT 0.61 0.52 tDP 2.78 2.36 tDIN 0.04 0.03 tPY 2.72 2.31 tPYS 3.67 3.12 tEOUT 0.40 0.34 tZL 2.83 2.41 tZH 1.98 1.68 tLZ 3.24 2.76 tHZ 3.58 3.04 tZLS 5.04 4.29 tZHS 4.19 3.56 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -4 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Voltage-Referenced I/O Characteristics 3.3 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V. Table 2-62 • Minimum and Maximum DC Input and Output Levels 3.3 V GTL Drive Strength 25 mA3 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. 3. Output drive strength is below JEDEC specification. Min., V –0.3 VIL Max., V VIH Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 3.6 0.4 – 25 25 268 181 15 15 VREF – 0.05 VREF + 0.05 VTT GTL Test Point 10 pF Figure 2-14 • AC Loading Table 2-63 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.05 Input HIGH (V) VREF + 0.05 Measuring Point* (V) 0.8 VREF (typ.) (V) 0.8 VTT (typ.) (V) 1.2 CLOAD (pF) 10 25 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-64 • 3.3 V GTL Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V Speed Grade Std. –1 tDOUT 0.80 0.68 tDP 2.05 1.75 tDIN 0.05 0.05 tPY 2.33 1.98 tEOUT 0.52 0.44 tZL 2.02 1.72 tZH 2.05 1.75 tLZ tHZ tZLS 4.23 3.60 tZHS 4.27 3.63 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-65 • 3.3 V GTL Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V Speed Grade Std. –1 tDOUT 0.61 0.52 tDP 2.05 1.75 tDIN 0.04 0.03 tPY 2.33 1.98 tEOUT 0.40 0.34 tZL 2.02 1.72 tZH 2.05 1.75 tLZ tHZ tZLS 4.23 3.60 tZHS 4.27 3.63 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 45 Radiation-Tolerant ProASIC3 FPGAs 2.5 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Table 2-66 • Minimum and Maximum DC Input and Output Levels 2.5 GTL Drive Strength Min., V 25 mA3 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. 3. Output drive strength is below JEDEC specification. –0.3 VIL Max., V VIH Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 2.7 0.4 – 25 25 169 124 15 15 VREF – 0.05 VREF + 0.05 VTT GTL Test Point 10 pF Figure 2-15 • AC Loading Table 2-67 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.05 Input HIGH (V) VREF + 0.05 Measuring Point* (V) 0.8 VREF (typ.) (V) 0.8 VTT (typ.) (V) 1.2 CLOAD (pF) 10 25 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-68 • 2.5 V GTL Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V Speed Grade Std. –1 tDOUT 0.80 0.68 tDP 2.11 1.79 tDIN 0.05 0.05 tPY 2.26 1.92 tEOUT 0.52 0.44 tZL 2.14 1.82 tZH 2.11 1.79 tLZ tHZ tZLS 4.35 3.70 tZHS 4.32 3.68 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-69 • 2.5 V GTL Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V Speed Grade Std. –1 tDOUT 0.61 0.52 tDP 2.11 1.79 tDIN 0.04 0.03 tPY 2.26 1.92 tEOUT 0.40 0.34 tZL 2.14 1.82 tZH 2.11 1.79 tLZ tHZ tZLS 4.35 3.70 tZHS 4.32 3.68 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -4 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics 3.3 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V. Table 2-70 • Minimum and Maximum DC Input and Output Levels 3.3 V GTL+ Drive Strength 35 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. Min., V –0.3 VIL Max., V VIH Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 3.6 0.6 – 35 35 268 181 15 15 VREF – 0.1 VREF + 0.1 VTT GTL+ Test Point 10 pF Figure 2-16 • AC Loading Table 2-71 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.1 Input HIGH (V) VREF + 0.1 Measuring Point* (V) 1.0 VREF (typ.) (V) 1.0 VTT (typ.) (V) 1.5 CLOAD (pF) 10 25 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-72 • 3.3 V GTL+ Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V, VREF = 1.0 V Speed Grade Std. –1 tDOUT 0.80 0.68 tDP 2.03 1.73 tDIN 0.05 0.05 tPY 2.33 1.98 tEOUT 0.52 0.44 tZL 2.07 1.76 tZH 2.03 1.73 tLZ tHZ tZLS 4.29 3.65 tZHS 4.25 3.61 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-73 • 3.3 V GTL+ Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.0 V Speed Grade Std. –1 tDOUT 0.61 0.52 tDP 2.03 1.73 tDIN 0.04 0.03 tPY 2.33 1.98 tEOUT 0.40 0.34 tZL 2.07 1.76 tZH 2.03 1.73 tLZ tHZ tZLS 4.29 3.65 tZHS 4.25 3.61 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 47 Radiation-Tolerant ProASIC3 FPGAs 2.5 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Table 2-74 • Minimum and Maximum DC Input and Output Levels 2.5 V GTL+ Drive Strength 33 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. Min., V –0.3 VIL Max., V VIH Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 2.7 0.6 – 33 33 169 124 15 15 VREF – 0.1 VREF + 0.1 VTT GTL+ Test Point 10 pF 25 Figure 2-17 • AC Loading Table 2-75 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.1 Input HIGH (V) VREF + 0.1 Measuring Point* (V) 1.0 VREF (typ.) (V) 1.0 VTT (typ.) (V) 1.5 CLOAD (pF) 10 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-76 • 2.5 V GTL+ Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V, VREF = 1.0 V Speed Grade Std. –1 tDOUT 0.80 0.68 tDP 2.18 1.86 tDIN 0.05 0.05 tPY 2.26 1.92 tEOUT 0.52 0.44 tZL 2.22 1.89 tZH 2.08 1.77 tLZ tHZ tZLS 4.44 3.78 tZHS 4.29 3.65 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-77 • 2.5 V GTL+ Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.0 V Speed Grade Std. –1 tDOUT 0.61 0.52 tDP 2.18 1.86 tDIN 0.04 0.03 tPY 2.26 1.92 tEOUT 0.40 0.34 tZL 2.22 1.89 tZH 2.08 1.77 tLZ tHZ tZLS 4.44 3.78 tZHS 4.29 3.65 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -4 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). RT ProASIC3 devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-78 • Minimum and Maximum DC Input and Output Levels HSTL Class I Drive Strength 8 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. VIL Min., V Max., V –0.3 VIH Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V 1.575 0.4 Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 VCCI – 0.4 8 8 32 39 15 15 VREF – 0.1 VREF + 0.1 HSTL Class I Test Point VTT 50 20 pF Figure 2-18 • AC Loading Table 2-79 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.1 Input HIGH (V) VREF + 0.1 Measuring Point* (V) 0.75 VREF (typ.) (V) 0.75 VTT (typ.) (V) 0.75 CLOAD (pF) 20 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-80 • HSTL Class I Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V Speed Grade Std. –1 tDOUT 0.80 0.68 tDP 3.15 2.68 tDIN 0.05 0.05 tPY 2.75 2.34 tEOUT 0.52 0.44 tZL 3.21 2.73 tZH 3.11 2.65 tLZ tHZ tZLS 5.42 4.61 tZHS 5.33 4.53 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-81 • HSTL Class I Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V Speed Grade Std. –1 tDOUT 0.61 0.52 tDP 3.15 2.68 tDIN 0.04 0.03 tPY 2.75 2.34 tEOUT 0.40 0.34 tZL 3.21 2.73 tZH 3.11 2.65 tLZ tHZ tZLS 5.42 4.61 tZHS 5.33 4.53 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 49 Radiation-Tolerant ProASIC3 FPGAs HSTL Class II High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). RT ProASIC3 devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-82 • Minimum and Maximum DC Input and Output Levels HSTL Class II Drive Strength 15 mA3 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. 3. Output drive strength is below JEDEC specification. VIL Min., V Max., V –0.3 VIH Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 1.575 0.4 VCCI – 0.4 15 15 66 55 15 15 VREF – 0.1 VREF + 0.1 HSTL Class II Test Point VTT 25 20 pF Figure 2-19 • AC Loading Table 2-83 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.1 Input HIGH (V) VREF + 0.1 Measuring Point* (V) 0.75 VREF (typ.) (V) 0.75 VTT (typ.) (V) 0.75 CLOAD (pF) 20 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-84 • HSTL Class II Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V Speed Grade Std. –1 tDOUT 0.80 0.68 tDP 2.99 2.55 tDIN 0.05 0.05 tPY 2.75 2.34 tEOUT 0.52 0.44 tZL 3.05 2.59 tZH 2.69 2.29 tLZ tHZ tZLS 5.26 4.48 tZHS 4.90 4.17 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-85 • HSTL Class II Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V Speed Grade Std. –1 tDOUT 0.61 0.52 tDP 2.99 2.55 tDIN 0.04 0.03 tPY 2.75 2.34 tEOUT 0.40 0.34 tZL 3.05 2.59 tZH 2.69 2.29 tLZ tHZ tZLS 5.26 4.48 tZHS 4.90 4.17 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -5 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics SSTL2 Class I Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). RT ProASIC3 devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-86 • Minimum and Maximum DC Input and Output Levels SSTL2 Class I Drive Strength 15 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. VIL Min., V Max., V –0.3 VIH Min., V VOL VOH Min., V IOL IOH IOSL IOSH IIL IIH Max., V Max., V 2.7 0.54 mA mA Max., mA1 Max., mA1 µA2 µA2 83 87 15 15 VREF – 0.2 VREF + 0.2 VCCI – 0.62 15 15 SSTL2 Class I Test Point 25 VTT 50 30 pF Figure 2-20 • AC Loading Table 2-87 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.2 Input HIGH (V) VREF + 0.2 Measuring Point* (V) 1.25 VREF (typ.) (V) 1.25 VTT (typ.) (V) 1.25 CLOAD (pF) 30 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-88 • SSTL2 Class I Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V Speed Grade Std. –1 tDOUT 0.80 0.68 tDP 2.11 1.79 tDIN 0.05 0.05 tPY 2.08 1.77 tEOUT 0.52 0.44 tZL 2.14 1.82 tZH 1.83 1.56 tLZ tHZ tZLS 2.14 1.82 tZHS 1.83 1.56 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-89 • SSTL2 Class I Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V Speed Grade Std. –1 tDOUT 0.61 0.52 tDP 2.11 1.79 tDIN 0.04 0.03 tPY 2.08 1.77 tEOUT 0.40 0.34 tZL 2.14 1.82 tZH 1.83 1.56 tLZ tHZ tZLS 2.14 1.82 tZHS 1.83 1.56 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 51 Radiation-Tolerant ProASIC3 FPGAs SSTL2 Class II Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). RT ProASIC3 devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-90 • Minimum and Maximum DC Input and Output Levels SSTL2 Class II Drive Strength 18 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. VIL Min., V Max., V –0.3 VIH Min., V VOL Max., V Max., V 2.7 0.35 VOH Min., V IOL IOH IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 µA2 µA2 169 124 15 15 VREF – 0.2 VREF + 0.2 VCCI – 0.43 18 18 SSTL2 Class II Test Point 25 VTT 25 30 pF Figure 2-21 • AC Loading Table 2-91 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.2 Input HIGH (V) VREF + 0.2 Measuring Point* (V) 1.25 VREF (typ.) (V) 1.25 VTT (typ.) (V) 1.25 CLOAD (pF) 30 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-92 • SSTL2 Class II Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V Speed Grade Std. –1 tDOUT 0.80 0.68 tDP 2.15 1.83 tDIN 0.05 0.05 tPY 2.08 1.77 tEOUT 0.52 0.44 tZL 2.19 1.86 tZH 1.75 1.49 tLZ tHZ tZLS 2.19 1.86 tZHS 1.75 1.49 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-93 • SSTL2 Class II Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V Speed Grade Std. –1 tDOUT 0.61 0.52 tDP 2.15 1.83 tDIN 0.04 0.03 tPY 2.08 1.77 tEOUT 0.40 0.34 tZL 2.19 1.86 tZH 1.75 1.49 tLZ tHZ tZLS 2.19 1.86 tZHS 1.75 1.49 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -5 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). RT ProASIC3 devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-94 • Minimum and Maximum DC Input and Output Levels SSTL3 Class I Drive Strength 14 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. VIL Min., V Max., V –0.3 VIH Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 3.6 0.7 VCCI – 1.1 14 14 51 54 15 15 VREF – 0.2 VREF + 0.2 SSTL3 Class I Test Point 25 VTT 50 30 pF Figure 2-22 • AC Loading Table 2-95 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.2 Input HIGH (V) VREF + 0.2 Measuring Point* (V) 1.5 VREF (typ.) (V) 1.5 VTT (typ.) (V) 1.485 CLOAD (pF) 30 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-96 • SSTL3 Class I Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V Speed Grade Std. –1 tDOUT 0.80 0.68 tDP 2.28 1.94 tDIN 0.05 0.05 tPY 1.99 1.69 tEOUT 0.52 0.44 tZL 2.33 1.98 tZH 1.82 1.55 tLZ tHZ tZLS 2.33 1.98 tZHS 1.82 1.55 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-97 • SSTL3 Class I Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V Speed Grade Std. –1 tDOUT 0.61 0.52 tDP 2.28 1.94 tDIN 0.04 0.03 tPY 1.99 1.69 tEOUT 0.40 0.34 tZL 2.33 1.98 tZH 1.82 1.55 tLZ tHZ tZLS 2.33 1.98 tZHS 1.82 1.55 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 53 Radiation-Tolerant ProASIC3 FPGAs SSTL3 Class II Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). RT ProASIC3 devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-98 • Minimum and Maximum DC Input and Output Levels SSTL3 Class II Drive Strength 21 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. VIL Min., V Max., V –0.3 VIH Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 3.6 0.5 VCCI – 0.9 21 21 103 109 15 15 VREF – 0.2 VREF + 0.2 SSTL3 Class II Test Point 25 VTT 25 30 pF Figure 2-23 • AC Loading Table 2-99 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.2 Input HIGH (V) VREF + 0.2 Measuring Point* (V) 1.5 VREF (typ.) (V) 1.5 VTT (typ.) (V) 1.485 CLOAD (pF) 30 * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. Timing Characteristics Table 2-100 • SSTL3 Class II Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V Speed Grade Std. –1 tDOUT 0.80 0.68 tDP 2.04 1.74 tDIN 0.05 0.05 tPY 1.99 1.69 tEOUT 0.52 0.44 tZL 2.08 1.77 tZH 1.65 1.41 tLZ tHZ tZLS 2.08 1.77 tZHS 1.65 1.41 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-101 • SSTL3 Class II Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V Speed Grade Std. –1 tDOUT 0.61 0.52 tDP 2.04 1.74 tDIN 0.04 0.03 tPY 1.99 1.69 tEOUT 0.40 0.34 tZL 2.08 1.77 tZH 1.65 1.41 tLZ tHZ tZLS 2.08 1.77 tZHS 1.65 1.41 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -5 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with the LVPECL standards. LVDS Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit be carried through two signal lines, so two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-24. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different. Along with LVDS I/O, military ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (MLVDS) configuration (up to 40 nodes). Bourns Part Number: CAT16-LV4F12 OUTBUF_LVDS FPGA P 165 Ω Z0 = 50 Ω 140 Ω N 165 Ω Z0 = 50 Ω 100 Ω N P FPGA + – INBUF_LVDS Figure 2-24 • LVDS Circuit Diagram and Board-Level Implementation A dv a n c e v 0. 1 2 - 55 Radiation-Tolerant ProASIC3 FPGAs Table 2-102 • Minimum and Maximum DC Input and Output Levels DC Parameter VCCI VOL VOH IOL4 IOH4 VI IIH3 IIL3 VODIFF VOCM VICM VIDIFF Notes: 1. ± 5% 2. Differential input voltage = ±350 mV. 3. Currents are measured at 125°C junction temperature. 4. IOL/IOH is defined by VODIFF /(Resistor Network). Table 2-103 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 1.075 Input HIGH (V) 1.325 Measuring Point* (V) Cross point Description Supply Voltage Output Low Voltage Output High Voltage Output Lower Current Output High Current Input Voltage Input High Leakage Current Input Low Leakage Current Differential Output Voltage Output Common Mode Voltage Input Common Mode Voltage Input Differential Voltage 250 1.125 0.05 100 350 1.25 1.25 350 Min. 2.375 0.9 1.25 0.65 0.65 0 Typ. 2.5 1.075 1.425 0.91 0.91 Max. 2.625 1.25 1.6 1.16 1.16 2.925 10 10 450 1.375 2.35 Units V V V mA mA V µA µA mV V V mV * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. 2 -5 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Timing Characteristics 1.2 V DC Core Voltage Table 2-104 • LVDS Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Speed Grade Std. –1 tDOUT 0.80 0.68 tDP 1.81 1.57 tDIN 0.05 0.05 tPY 2.39 2.04 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 1.5 V DC Core Voltage Table 2-105 • LVDS Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V Speed Grade Std. –1 tDOUT 0.61 0.52 tDP 1.81 1.57 tDIN 0.04 0.03 tPY 2.39 2.04 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 57 Radiation-Tolerant ProASIC3 FPGAs B-LVDS/M-LVDS Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus since the driver can be located anywhere on the bus. These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-25. The input and output buffer delays are available in the LVDS section in Table 2-102 on page 2-56. Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 Ω and RT = 70 Ω, given Z0 = 50 Ω (2") and Zstub = 50 Ω (~1.5"). Receiver EN Transceiver EN Driver Receiver EN EN Transceiver EN D + R + - T + - - R + - T + BIBUF_LVDS - RS Zstub Z0 RT Z 0 RS Zstub Zstub Z0 Z0 RS RS Zstub Zstub Z0 Z0 RS RS Zstub Zstub Z0 Z0 RS RS Zstub ... Z0 Z0 RS RS Z0 Z0 RT Figure 2-25 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers 2 -5 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-26. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation because the output standard specifications are different. Bourns Part Number: CAT16-PC4F12 OUTBUF_LVPECL FPGA P 100 Ω Z0 = 50 Ω 187 W N 100 Ω Z0 = 50 Ω 100 Ω N P FPGA + – INBUF_LVPECL Figure 2-26 • LVPECL Circuit Diagram and Board-Level Implementation Table 2-106 • Minimum and Maximum DC Input and Output Levels DC Parameter VCCI VOL VOH VIL, VIH VODIFF VOCM VICM VIDIFF Description Supply Voltage Output LOW Voltage Output HIGH Voltage Input LOW, Input HIGH Voltages Differential Output Voltage Output Common-Mode Voltage Input Common-Mode Voltage Input Differential Voltage 0.96 1.8 0 0.625 1.762 1.01 300 Min. Max. 3.0 1.27 2.11 3.3 0.97 1.98 2.57 1.06 1.92 0 0.625 1.762 1.01 300 Min. Max. 3.3 1.43 2.28 3.6 0.97 1.98 2.57 1.30 2.13 0 0.625 1.762 1.01 300 Min. 3.6 1.57 2.41 3.9 0.97 1.98 2.57 Max. Units V V V V V V V mV Table 2-107 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 1.64 Input HIGH (V) 1.94 Measuring Point* (V) Cross point * Measuring point = Vtrip. See Table 2-19 on page 2-24 for a complete table of trip points. A dv a n c e v 0. 1 2 - 59 Radiation-Tolerant ProASIC3 FPGAs Timing Characteristics 1.2 V DC Core Voltage Table 2-108 • LVPECL Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Speed Grade Std. –1 tDOUT 0.80 0.68 tDP 1.81 1.54 tDIN 0.05 0.05 tPY 2.16 1.84 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 1.5 V DC Core Voltage Table 2-109 • LVPECL Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V Speed Grade Std. –1 tDOUT 0.61 0.52 tDP 1.81 1.54 tDIN 0.04 0.03 tPY 2.16 1.84 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -6 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset INBUF Preset L Pad Out D DOUT Data_out TRIBUF Data PRE D Q C DFN1E1P1 E B E Y Core Array F G PRE D Q DFN1E1P1 E INBUF INBUF Enable EOUT H I CLKBUF CLK A J K Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered PRE D Q DFN1E1P1 E CLKBUF INBUF INBUF Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive-Edge Triggered CLK Figure 2-27 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset A dv a n c e v 0. 1 D_Enable Enable 2 - 61 Radiation-Tolerant ProASIC3 FPGAs Table 2-110 • Parameter Definition and Measuring Nodes Parameter Name tOCLKQ tOSUD tOHD tOSUE tOHE tOPRE2Q tOREMPRE tORECPRE tOECLKQ tOESUD tOEHD tOESUE tOEHE tOEPRE2Q tOEREMPRE tOERECPRE tICLKQ tISUD tIHD tISUE tIHE tIPRE2Q tIREMPRE tIRECPRE Parameter Definition Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Measuring Nodes (from, to)* H, DOUT F, H F, H G, H G, H L, DOUT L, H L, H H, EOUT J, H J, H K, H K, H I, EOUT I, H I, H A, E C, A C, A B, A B, A D, E D, A D, A * See Figure 2-27 on page 2-61 for more information. 2 -6 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Pad Out DOUT Y D CC Q EE DFN1E1C1 E BB CLR LL HH AA JJ DD KK Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Data Core Array Data_out FF TRIBUF INBUF INBUF D Q DFN1E1C1 GG E CLR EOUT Enable CLKBUF CLK INBUF CLR D Q DFN1E1C1 E CLR INBUF INBUF CLKBUF Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive-Edge Triggered Enable Figure 2-28 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear A dv a n c e v 0. 1 D_Enable CLK 2 - 63 Radiation-Tolerant ProASIC3 FPGAs Table 2-111 • Parameter Definition and Measuring Nodes Parameter Name tOCLKQ tOSUD tOHD tOSUE tOHE tOCLR2Q tOREMCLR tORECCLR tOECLKQ tOESUD tOEHD tOESUE tOEHE tOECLR2Q tOEREMCLR tOERECCLR tICLKQ tISUD tIHD tISUE tIHE tICLR2Q tIREMCLR tIRECCLR Parameter Definition Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Measuring Nodes (from, to)* HH, DOUT FF, HH FF, HH GG, HH GG, HH LL, DOUT LL, HH LL, HH HH, EOUT JJ, HH JJ, HH KK, HH KK, HH II, EOUT II, HH II, HH AA, EE CC, AA CC, AA BB, AA BB, AA DD, EE DD, AA DD, AA * See Figure 2-28 on page 2-63 for more information. 2 -6 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Input Register tICKMPWH tICKMPWL 50% 50% tISUD Data 1 50% 0 tIHD 50% 50% 50% 50% 50% 50% CLK Enable 50% tIHE 50% tIWPRE tISUE tIRECPRE 50% tIWCLR tIRECCLR 50% tIREMPRE 50% tIREMCLR 50% Preset Clear tIPRE2Q Out_1 50% tICLKQ 50% 50% tICLR2Q 50% Figure 2-29 • Input Register Timing Diagram A dv a n c e v 0. 1 2 - 65 Radiation-Tolerant ProASIC3 FPGAs Timing Characteristics Table 2-112 • Input Data Register Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V Parameter tICLKQ tISUD tIHD tISUE tIHE tICLR2Q tIPRE2Q tIREMCLR tIRECCLR tIREMPRE tIRECPRE tIWCLR tIWPRE tICKMPWH tICKMPWL Description Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Asynchronous Clear Minimum Pulse Width for the Input Data Register Asynchronous Preset Minimum Pulse Width for the Input Data Register Clock Minimum Pulse Width HIGH for the Input Data Register Clock Minimum Pulse Width LOW for the Input Data Register –1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.33 0.39 0.36 0.43 0.00 0.00 0.51 0.60 0.00 0.00 0.63 0.74 0.63 0.74 0.00 0.00 0.31 0.36 0.00 0.00 0.31 0.36 0.19 0.22 0.19 0.22 0.31 0.36 0.28 0.32 Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-113 • Input Data Register Propagation Delays Military-Case Conditions: TJ = 125°C, VCC = 1.425 V Parameter tICLKQ tISUD tIHD tISUE tIHE tICLR2Q tIPRE2Q tIREMCLR tIRECCLR tIREMPRE tIRECPRE tIWCLR tIWPRE tICKMPWH tICKMPWL Description Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Asynchronous Clear Minimum Pulse Width for the Input Data Register Asynchronous Preset Minimum Pulse Width for the Input Data Register Clock Minimum Pulse Width HIGH for the Input Data Register Clock Minimum Pulse Width LOW for the Input Data Register –1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.25 0.30 0.28 0.33 0.00 0.00 0.39 0.46 0.00 0.00 0.48 0.56 0.48 0.56 0.00 0.00 0.24 0.28 0.00 0.00 0.24 0.28 0.19 0.22 0.19 0.22 0.31 0.36 0.28 0.32 Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -6 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Output Register tOCKMPWH tOCKMPWL 50% 50% tOSUD tOHD Data_out 1 50% 0 50% 50% 50% 50% 50% 50% CLK Enable 50% tOHE 50% tOWPRE tORECPRE 50% tORECCLR tOREMPRE 50% tOREMCLR 50% Preset tOSUE tOWCLR Clear tOPRE2Q DOUT 50% tOCLKQ 50% tOCLR2Q 50% 50% 50% Figure 2-30 • Output Register Timing Diagram A dv a n c e v 0. 1 2 - 67 Radiation-Tolerant ProASIC3 FPGAs Timing Characteristics Table 2-114 • Output Data Register Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V Parameter tOCLKQ tOSUD tOHD tOSUE tOHE tOCLR2Q tOPRE2Q tOREMCLR tORECCLR tOREMPRE tORECPRE tOWCLR tOWPRE tOCKMPWH tOCKMPWL Description Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Asynchronous Clear Minimum Pulse Width for the Output Data Register Asynchronous Preset Minimum Pulse Width for the Output Data Register Clock Minimum Pulse Width HIGH for the Output Data Register Clock Minimum Pulse Width LOW for the Output Data Register –1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.81 0.96 0.43 0.51 0.00 0.00 0.61 0.71 0.00 0.00 1.11 1.31 1.11 1.31 0.00 0.00 0.31 0.36 0.00 0.00 0.31 0.36 0.19 0.22 0.19 0.22 0.31 0.36 0.28 0.32 Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-115 • Output Data Register Propagation Delays Military-Case Conditions: TJ = 125°C, VCC = 1.425 V Parameter tOCLKQ tOSUD tOHD tOSUE tOHE tOCLR2Q tOPRE2Q tOREMCLR tORECCLR tOREMPRE tORECPRE tOWCLR tOWPRE tOCKMPWH tOCKMPWL Description Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Asynchronous Clear Minimum Pulse Width for the Output Data Register Asynchronous Preset Minimum Pulse Width for the Output Data Register Clock Minimum Pulse Width HIGH for the Output Data Register Clock Minimum Pulse Width LOW for the Output Data Register –1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.62 0.73 0.33 0.39 0.00 0.00 0.46 0.55 0.00 0.00 0.85 1.00 0.85 1.00 0.00 0.00 0.24 0.28 0.00 0.00 0.24 0.28 0.19 0.22 0.19 0.22 0.31 0.36 0.28 0.32 Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -6 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Output Enable Register tOECKMPWH tOECKMPWL 50% CLK 50% tOESUD tOEHD 50% 50% 50% 50% 50% D_Enable 1 50% 0 50% Enable 50% tOEWPRE 50% tOERECPRE 50% tOEREMPRE 50% Preset tOESUEtOEHE tOEWCLR 50% Clear tOEPRE2Q EOUT 50% tOECLKQ 50% tOECLR2Q 50% tOERECCLR 50% tOEREMCLR 50% Figure 2-31 • Output Enable Register Timing Diagram A dv a n c e v 0. 1 2 - 69 Radiation-Tolerant ProASIC3 FPGAs Timing Characteristics Table 2-116 • Output Enable Register Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V Parameter tOECLKQ tOESUD tOEHD tOESUE tOEHE tOECLR2Q tOEPRE2Q tOEREMCLR tOERECCLR tOEREMPRE tOERECPRE tOEWCLR tOEWPRE tOECKMPWH tOECKMPWL Description Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Asynchronous Clear Minimum Pulse Width for the Output Enable Register Asynchronous Preset Minimum Pulse Width for the Output Enable Register Clock Minimum Pulse Width HIGH for the Output Enable Register Clock Minimum Pulse Width LOW for the Output Enable Register –1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.62 0.72 0.43 0.51 0.00 0.00 0.60 0.71 0.00 0.00 0.92 1.08 0.92 1.08 0.00 0.00 0.31 0.36 0.00 0.00 0.31 0.36 0.19 0.22 0.19 0.22 0.31 0.36 0.28 0.32 Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-117 • Output Enable Register Propagation Delays Military-Case Conditions: TJ = 125°C, VCC = 1.425 V Parameter tOECLKQ tOESUD tOEHD tOESUE tOEHE tOECLR2Q tOEPRE2Q tOEREMCLR tOERECCLR tOEREMPRE tOERECPRE tOEWCLR tOEWPRE tOECKMPWH tOECKMPWL Description Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Asynchronous Clear Minimum Pulse Width for the Output Enable Register Asynchronous Preset Minimum Pulse Width for the Output Enable Register Clock Minimum Pulse Width HIGH for the Output Enable Register Clock Minimum Pulse Width LOW for the Output Enable Register –1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.47 0.55 0.33 0.39 0.00 0.00 0.46 0.54 0.00 0.00 0.70 0.83 0.70 0.83 0.00 0.00 0.24 0.28 0.00 0.00 0.24 0.28 0.19 0.22 0.19 0.22 0.31 0.36 0.28 0.32 Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -7 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics DDR Module Specifications Input DDR Module Input DDR INBUF Data A FF1 D Out_QF (to core) CLK CLKBUF B FF2 E Out_QR (to core) CLR INBUF C DDR_IN Figure 2-32 • Input DDR Timing Model Table 2-118 • Parameter Definitions Parameter Name tDDRICLKQ1 tDDRICLKQ2 tDDRISUD tDDRIHD tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR Parameter Definition Clock-to-Out Out_QR Clock-to-Out Out_QF Data Setup Time of DDR input Data Hold Time of DDR input Clear-to-Out Out_QR Clear-to-Out Out_QF Clear Removal Clear Recovery Measuring Nodes (from, to) B, D B, E A, B A, B C, D C, E C, B C, B A dv a n c e v 0. 1 2 - 71 Radiation-Tolerant ProASIC3 FPGAs CLK tDDRISUD Data 1 2 3 4 5 6 7 tDDRIHD 8 tDDRIRECCLR CLR tDDRIREMCLR tDDRICLKQ1 tDDRICLR2Q1 Out_QF tDDRICLR2Q2 Out_QR 3 2 4 tDDRICLKQ2 5 7 6 9 Figure 2-33 • Input DDR Timing Diagram Timing Characteristics Table 2-119 • Input DDR Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V Parameter tDDRICLKQ1 tDDRICLKQ2 tDDRISUD1 tDDRISUD2 tDDRIHD1 tDDRIHD2 tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR tDDRIWCLR tDDRICKMPWH tDDRICKMPWL FDDRIMAX Description Clock-to-Out Out_QR for Input DDR Clock-to-Out Out_QF for Input DDR Data Setup for Input DDR (fall) Data Setup for Input DDR (rise) Data Hold for Input DDR (fall) Data Hold for Input DDR (rise) Asynchronous Clear-to-Out Out_QR for Input DDR Asynchronous Clear-to-Out Out_QF for Input DDR Asynchronous Clear Removal Time for Input DDR Asynchronous Clear Recovery Time for Input DDR Asynchronous Clear Minimum Pulse Width for Input DDR Clock Minimum Pulse Width HIGH for Input DDR Clock Minimum Pulse Width LOW for Input DDR Maximum Frequency for Input DDR –1 0.38 0.54 0.39 0.34 0.00 0.00 0.64 0.79 0.00 0.31 0.19 0.31 0.28 TBD Std. 0.45 0.63 0.46 0.40 0.00 0.00 0.75 0.93 0.00 0.36 0.22 0.36 0.32 TBD Units ns ns ns ns ns ns ns ns ns ns ns ns ns MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -7 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Table 2-120 • Input DDR Propagation Delays Military-Case Conditions: TJ = 125°C, VCC = 1.425 V Parameter tDDRICLKQ1 tDDRICLKQ2 tDDRISUD1 tDDRISUD2 tDDRIHD1 tDDRIHD2 tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR tDDRIWCLR tDDRICKMPWH tDDRICKMPWL FDDRIMAX Description Clock-to-Out Out_QR for Input DDR Clock-to-Out Out_QF for Input DDR Data Setup for Input DDR (fall) Data Setup for Input DDR (rise) Data Hold for Input DDR (fall) Data Hold for Input DDR (rise) Asynchronous Clear-to-Out Out_QR for Input DDR Asynchronous Clear-to-Out Out_QF for Input DDR Asynchronous Clear Removal Time for Input DDR Asynchronous Clear Recovery Time for Input DDR Asynchronous Clear Minimum Pulse Width for Input DDR Clock Minimum Pulse Width HIGH for Input DDR Clock Minimum Pulse Width LOW for Input DDR Maximum Frequency for Input DDR –1 0.29 0.41 0.30 0.26 0.00 0.00 0.49 0.60 0.00 0.24 0.19 0.31 0.28 TBD Std. 0.34 0.48 0.35 0.31 0.00 0.00 0.58 0.71 0.00 0.28 0.22 0.36 0.32 TBD Units ns ns ns ns ns ns ns ns ns ns ns ns ns MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 73 Radiation-Tolerant ProASIC3 FPGAs Output DDR Module Output DDR Data_F (from core) A X FF1 B Out X 0 E X X FF2 1 X OUTBUF CLK CLKBUF C D Data_R (from core) CLR INBUF B C X X DDR_OUT Figure 2-34 • Output DDR Timing Model Table 2-121 • Parameter Definitions Parameter Name tDDROCLKQ tDDROCLR2Q tDDROREMCLR tDDRORECCLR tDDROSUD1 tDDROSUD2 tDDROHD1 tDDROHD2 Clock-to-Out Asynchronous Clear-to-Out Clear Removal Clear Recovery Data Setup Data_F Data Setup Data_R Data Hold Data_F Data Hold Data_R Parameter Definition Measuring Nodes (from, to) B, E C, E C, B C, B A, B D, B A, B D, B 2 -7 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics CLK tDDROSUD2 tDDROHD2 Data_F 1 2 tDDROREMCLR Data_R 6 7 tDDROHD1 8 9 10 tDDRORECCLR CLR tDDROREMCLR tDDROCLR2Q Out tDDROCLKQ 7 2 8 3 9 4 10 11 3 4 5 Figure 2-35 • Output DDR Timing Diagram Timing Characteristics Table 2-122 • Output DDR Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V Parameter tDDROCLKQ tDDRISUD1 tDDROSUD2 tDDROHD1 tDDROHD2 tDDROCLR2Q tDDROREMCLR tDDRORECCLR tDDROWCLR1 tDDROCKMPWH tDDROCKMPWL FDDOMAX Description Clock-to-Out of DDR for Output DDR Data_F Data Setup for Output DDR Data_R Data Setup for Output DDR Data_F Data Hold for Output DDR Data_R Data Hold for Output DDR Asynchronous Clear-to-Out for Output DDR Asynchronous Clear Removal Time for Output DDR Asynchronous Clear Recovery Time for Output DDR Asynchronous Clear Minimum Pulse Width for Output DDR Clock Minimum Pulse Width HIGH for the Output DDR Clock Minimum Pulse Width LOW for the Output DDR Maximum Frequency for the Output DDR –1 0.97 0.52 0.52 0.00 0.00 1.11 0.00 0.31 0.19 0.31 0.28 TBD Std. 1.14 0.62 0.62 0.00 0.00 1.30 0.00 0.36 0.22 0.36 0.32 TBD Units ns ns ns ns ns ns ns ns ns ns ns MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 75 Radiation-Tolerant ProASIC3 FPGAs Table 2-123 • Output DDR Propagation Delays Military-Case Conditions: TJ = 125°C, VCC = 1.425 V Parameter tDDROCLKQ tDDRISUD1 tDDROSUD2 tDDROHD1 tDDROHD2 tDDROCLR2Q tDDROREMCLR tDDRORECCLR tDDROWCLR1 tDDROCKMPWH tDDROCKMPWL FDDOMAX Description Clock-to-Out of DDR for Output DDR Data_F Data Setup for Output DDR Data_R Data Setup for Output DDR Data_F Data Hold for Output DDR Data_R Data Hold for Output DDR Asynchronous Clear-to-Out for Output DDR Asynchronous Clear Removal Time for Output DDR Asynchronous Clear Recovery Time for Output DDR Asynchronous Clear Minimum Pulse Width for Output DDR Clock Minimum Pulse Width HIGH for the Output DDR Clock Minimum Pulse Width LOW for the Output DDR Maximum Frequency for the Output DDR –1 0.74 0.40 0.40 0.00 0.00 0.85 0.00 0.24 0.19 0.31 0.28 TBD Std. 0.87 0.47 0.47 0.00 0.00 1.00 0.00 0.28 0.22 0.36 0.32 TBD Units ns ns ns ns ns ns ns ns ns ns ns MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -7 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The RT ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide. A INV Y A OR2 B A AND2 B Y Y A NOR2 B Y A NAND2 B A B C Y A B XOR2 Y XOR3 Y A A B C B C MAJ3 Y A 0 MUX2 B 1 Y NAND3 S Figure 2-36 • Sample of Combinatorial Cells A dv a n c e v 0. 1 2 - 77 Radiation-Tolerant ProASIC3 FPGAs tPD A NAND2 or Any Combinatorial Logic Y B tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for the particular combinatorial cell VCC 50% A, B, C 50% GND VCC 50% OUT GND VCC OUT 50% tPD (RF) Figure 2-37 • Timing Model and Waveforms 50% tPD (RR) tPD (FF) tPD (FR) GND 50% 2 -7 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-124 • Combinatorial Cell Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Equation Y = !A Y=A·B Y = !(A · B) Y=A+B Y = !(A + B) Y=A⊕B Y = MAJ(A , B, C) Y=A⊕B⊕C Y = A !S + B S Y=A·B·C Parameter tPD tPD tPD tPD tPD tPD tPD tPD tPD tPD –1 0.56 0.65 0.65 0.67 0.67 1.02 0.97 1.21 0.70 0.78 Std. 0.65 0.77 0.77 0.79 0.79 1.20 1.14 1.42 0.82 0.91 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-125 • Combinatorial Cell Propagation Delays Military-Case Conditions: TJ = 125°C, VCC = 1.425 V Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Equation Y = !A Y=A·B Y = !(A · B) Y=A+B Y = !(A + B) Y=A⊕B Y = MAJ(A , B, C) Y=A⊕B⊕C Y = A !S + B S Y=A·B·C Parameter tPD tPD tPD tPD tPD tPD tPD tPD tPD tPD –1 0.43 0.50 0.50 0.51 0.51 0.78 0.74 0.93 0.54 0.59 Std. 0.50 0.59 0.59 0.61 0.61 0.92 0.87 1.09 0.63 0.70 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 79 Radiation-Tolerant ProASIC3 FPGAs VersaTile Specifications as a Sequential Module The RT ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide. Data D DFN1 Q Out Data D En CLK Q DFN1E1 Out CLK PRE Data D Q DFN1C1 Out Data En CLK D Q Out DFI1E1P1 CLK CLR Figure 2-38 • Sample of Sequential Cells 2 -8 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics tCKMPWH tCKMPWL 50% 50% tSUD Data 50% tHD 0 50% 50% 50% 50% 50% 50% CLK EN 50% tHE tWPRE tSUE 50% tRECPRE 50% tRECCLR 50% tREMPRE 50% tREMCLR 50% PRE tWCLR CLR tPRE2Q Out tCLKQ 50% 50% 50% tCLR2Q 50% Figure 2-39 • Timing Model and Waveforms A dv a n c e v 0. 1 2 - 81 Radiation-Tolerant ProASIC3 FPGAs Timing Characteristics Table 2-126 • Register Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V Parameter tCLKQ tSUD tHD tSUE tHE tCLR2Q tPRE2Q tREMCLR tRECCLR tREMPRE tRECPRE tWCLR tWPRE tCKMPWH tCKMPWL Clock-to-Q of the Core Register Data Setup Time for the Core Register Data Hold Time for the Core Register Enable Setup Time for the Core Register Enable Hold Time for the Core Register Asynchronous Clear-to-Q of the Core Register Asynchronous Preset-to-Q of the Core Register Asynchronous Clear Removal Time for the Core Register Asynchronous Clear Recovery Time for the Core Register Asynchronous Preset Removal Time for the Core Register Asynchronous Preset Recovery Time for the Core Register Asynchronous Clear Minimum Pulse Width for the Core Register Asynchronous Preset Minimum Pulse Width for the Core Register Clock Minimum Pulse Width HIGH for the Core Register Clock Minimum Pulse Width LOW for the Core Register Description –1 0.76 0.59 0.00 0.63 0.00 0.55 0.55 0.00 0.31 0.00 0.31 0.30 0.30 0.56 0.56 Std. 0.90 0.70 0.00 0.74 0.00 0.65 0.65 0.00 0.36 0.00 0.36 0.34 0.34 0.64 0.64 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -8 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Table 2-127 • Register Delays Military-Case Conditions: TJ = 125°C, VCC = 1.425 V Parameter tCLKQ tSUD tHD tSUE tHE tCLR2Q tPRE2Q tREMCLR tRECCLR tREMPRE tRECPRE tWCLR tWPRE tCKMPWH tCKMPWL Clock-to-Q of the Core Register Data Setup Time for the Core Register Data Hold Time for the Core Register Enable Setup Time for the Core Register Enable Hold Time for the Core Register Asynchronous Clear-to-Q of the Core Register Asynchronous Preset-to-Q of the Core Register Asynchronous Clear Removal Time for the Core Register Asynchronous Clear Recovery Time for the Core Register Asynchronous Preset Removal Time for the Core Register Asynchronous Preset Recovery Time for the Core Register Asynchronous Clear Minimum Pulse Width for the Core Register Asynchronous Preset Minimum Pulse Width for the Core Register Clock Minimum Pulse Width HIGH for the Core Register Clock Minimum Pulse Width LOW for the Core Register Description –1 0.58 0.45 0.00 0.48 0.00 0.42 0.42 0.00 0.24 0.00 0.24 0.30 0.30 0.56 0.56 Std. 0.69 0.53 0.00 0.57 0.00 0.50 0.50 0.00 0.28 0.00 0.28 0.34 0.34 0.64 0.64 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 83 Radiation-Tolerant ProASIC3 FPGAs Global Resource Characteristics RT3PE600L Clock Tree Topology Clock delays are device-specific. Figure 2-40 is an example of a global tree used for clock routing. The global tree presented in Figure 2-40 is driven by a CCC located on the west side of the RT3PE600L device. It is used to drive all D-flip-flops in the device. Central Global Rib CCC VersaTile Rows Global Spine Figure 2-40 • Example of Global Tree Use in an RT3PE600L Device for Clock Routing 2 -8 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-87. Table 2-128 to Table 2-131 on page 2-86 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics 1.2 V DC Core Voltage Table 2-128 • RT3PE600L Global Resource Military-Case Conditions: TJ = 125°C, VCC = 1.14 V –1 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-129 • RT3PE3000L Global Resource Military-Case Conditions: TJ = 125°C, VCC = 1.14 V –1 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.30 0.35 Min. 1 Std. 2 Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock Min. 1 Max. Min.1 Max.2 Units ns ns ns ns ns MHz Std. Min.1 Max.2 Units 2.12 2.11 2.42 2.45 ns ns ns ns ns MHz 2.06 2.09 Max.2 1.80 1.79 A dv a n c e v 0. 1 2 - 85 Radiation-Tolerant ProASIC3 FPGAs 1.5 V DC Core Voltage Table 2-130 • RT3PE600L Global Resource Military-Case Conditions: TJ = 125°C, VCC = 1.425 V –1 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-131 • RT3PE3000L Global Resource Military-Case Conditions: TJ = 125°C, VCC = 1.425 V –1 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.27 0.32 Std. Min.1 Max.2 Min.1 Max.2 Units 1.61 1.60 1.85 1.87 1.89 1.88 2.17 2.20 ns ns ns ns ns MHz Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock Min. 1 Std. 2 Max. Min.1 Max.2 Units ns ns ns ns ns MHz 2 -8 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-132 • RT ProASIC3 CCC/PLL Specification For Devices Operating at 1.2 V DC Core Voltage Parameter Clock Conditioning Circuitry Input Frequency fIN_CCC Clock Conditioning Circuitry Output Frequency fOUT_CCC Delay Increments in Programmable Delay Blocks PLL3 1, 2 Min. 1.5 0.75 Typ. Max. 250 250 Units MHz MHz ps 270 32 100 1 Max Peak-to-Peak Period Jitter 1 Global Network Used External 3 Global FB Used Networks Used 0.75% 1.50% 3.75% 0.70% 1.20% 2.75% Number of Programmable Values in Each Programmable Delay Block Serial Clock (SCLK) for Dynamic MHz ns Input Cycle-to-Cycle Jitter (peak magnitude) CCC Output Peak-to-Peak Period Jitter FCCC_OUT 0.75 MHz to 24 MHz 24 MHz to 100 MHz 100 MHz to 250 MHz Acquisition Time LockControl = 0 LockControl = 1 Tracking Jitter LockControl = 0 LockControl = 1 Output Duty Cycle Delay Range in Block: Programmable Delay 1, 2 0.50% 1.00% 2.50% 300 6.0 µs ms 2 1 48.5 51.5 15.65 15.65 3.1 ns ns % ns ns ns 1 1, 2 1, 2 1.2 0.025 Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Delay Notes: 1. This delay is a function of voltage and temperature. See Table 2-5 on page 2-8 for deratings. 2. TJ = 25°C, VCC = 1.2 V 3. Maximum value obtained for a Std. speed grade device in worst-case military conditions. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter. A dv a n c e v 0. 1 2 - 87 Radiation-Tolerant ProASIC3 FPGAs Table 2-133 • RT ProASIC3 CCC/PLL Specification For Devices Operating at 1.5 V DC Core Voltage Parameter Clock Conditioning Circuitry Input Frequency fIN_CCC Clock Conditioning Circuitry Output Frequency fOUT_CCC Serial Clock (SCLK) for Dynamic PLL5 Delay Increments in Programmable Delay Blocks1, 2 Number of Programmable Programmable Delay Block Input Period Jitter CCC Output Peak-to-Peak Period Jitter FCCC_OUT Values in Each 200 32 1.5 Max Peak-to-Peak Period Jitter 1 Global Network Used 0.75 MHz to 24 MHz 24 MHz to 100 MHz 100 MHz to 250 MHz 250 MHz to 350 MHz Acquisition Time LockControl = 0 LockControl = 1 Tracking Jitter LockControl = 0 LockControl = 1 Output Duty Cycle Delay Range in Block: Programmable Delay 1 Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Delay Notes: 1. This delay is a function of voltage and temperature. See Table 2-5 on page 2-8 for deratings. 2. TJ = 25°C, VCC = 1.5 V 3. Maximum value obtained for a Std. speed grade device in worst-case military conditions. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter. 5. Maximum value obtained for a -1 speed grade device in worst-case military conditions. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 1, 2 1, 2 1, 2 Min. 1.5 0.75 Typ. Max. 350 350 110 Units MHz MHz MHz ps ns 3 Global Networks Used 0.70% 1.20% 2.00% 5.60% 0.50% 1.00% 1.75% 2.50% 300 6.0 µs ms 1.6 0.8 48.5 0.6 0.025 2.2 51.5 5.56 5.56 ns ns % ns ns ns 2 -8 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Output Signal Tperiod_max Tperiod_min Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min. Figure 2-41 • Peak-to-Peak Jitter Definition A dv a n c e v 0. 1 2 - 89 Radiation-Tolerant ProASIC3 FPGAs Embedded SRAM and FIFO Characteristics SRAM RAM4K9 ADDRA11 ADDRA10 ADDRA0 DINA8 DINA7 DOUTA8 DOUTA7 DOUTA0 RAM512X18 RADDR8 RADDR7 RADDR0 RD17 RD16 RD0 DINA0 RW1 RW0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DOUTB8 DOUTB7 DOUTB0 PIPE REN RCLK WADDR8 WADDR7 WADDR0 WD17 WD16 WD0 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB RESET WW1 WW0 WEN WCLK RESET Figure 2-42 • RAM Models 2 -9 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Timing Waveforms tCYC tCKH CLK tAS ADD A0 tBKS BLK_B tENS WEN_B tCKQ1 DO Dn D0 tDOH1 Figure 2-43 • RAM Read for Pass-Through Output tCKL tAH A1 A2 tBKH tENH D1 D2 tCYC tCKH CLK t ADD tBKS BLK_B tENS WEN_B tCKQ2 DO Dn D0 tDOH2 Figure 2-44 • RAM Read for Pipelined Output AS tCKL tAH A0 A1 A2 tBKH tENH D1 A dv a n c e v 0. 1 2 - 91 Radiation-Tolerant ProASIC3 FPGAs tCYC tCKH CLK tAS ADD tBKS tBKH BLK_B tENS WEN_B tDS DI DI0 tDH DI1 tENH A0 tAH A1 A2 tCKL DO Dn D2 Figure 2-45 • RAM Write, Output Retained (WMODE = 0) tCYC tCKH CLK tAS ADD tBKS BLK_B tENS WEN_B tDS DI DO (pass-through) DO (pipelined) DI0 tDH DI1 DI2 tBKH A0 tAH A1 A2 tCKL Dn DI0 DI1 Dn DI0 DI1 Figure 2-46 • RAM Write, Output as Write Data (WMODE = 1) 2 -9 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics CLK1 tAS ADD1 tDS DI1 tAH A0 tDH D1 tCCKH CLK2 WEN_B1 WEN_B2 ADD2 DI2 DO2 (pass-through) DO2 (pipelined) A0 D0 tCKQ1 Dn D0 tCKQ2 Dn D0 A1 D2 A3 D3 tAS tAH A0 A4 D4 Figure 2-47 • Write Access after Write onto Same Address A dv a n c e v 0. 1 2 - 93 Radiation-Tolerant ProASIC3 FPGAs CLK1 tAS tAH ADD1 DI1 CLK2 WEN_B1 WEN_B2 tAS tAH ADD2 DO2 (pass-through) DO2 (pipelined) Dn Dn A0 tCKQ1 D0 tCKQ2 D0 D1 A1 A4 A0 tDS tDH D0 tWRO A2 D2 A3 D3 Figure 2-48 • Read Access after Write onto Same Address 2 -9 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics CLK1 tAS ADD1 WEN_B1 tCKQ1 DO1 (pass-through) DO1 (pipelined) CLK2 tAS ADD2 A0 D1 tAH A1 D2 A3 D3 Dn D0 tCKQ2 Dn tCCKH D0 tCKQ1 D1 tAH A0 A1 A0 DI2 WEN_B2 Figure 2-49 • Write Access after Read onto Same Address tCYC tCKH CLK tCKL RESET_B tRSTBQ DO Dm Dn Figure 2-50 • RAM Reset A dv a n c e v 0. 1 2 - 95 Radiation-Tolerant ProASIC3 FPGAs Timing Characteristics Table 2-134 • RAM4K9 Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V Parameter tAS tAH tENS tENH tBKS tBKH tDS tDH tCKQ1 Address setup time Address hold time REN_B, WEN_B setup time REN_B, WEN_B hold time BLK_B setup time BLK_B hold time Input data (DI) setup time Input data (DI) hold time Clock HIGH to new data valid on DO (output retained, WMODE = 0) Clock HIGH to new data valid on DO (flow-through, WMODE = 1) tCKQ2 tWRO tCCKH tRSTBQ Clock HIGH to new data valid on DO (pipelined) Description –1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz 0.35 0.41 0.00 0.00 0.20 0.23 0.13 0.16 0.32 0.38 0.03 0.03 0.25 0.30 0.00 0.00 2.47 2.91 3.26 3.84 1.24 1.46 Address collision clk-to-clk delay for reliable read access after write on same TBD TBD address Address collision clk-to-clk delay for reliable write access after write/read on TBD TBD same address RESET_B LOW to data out LOW on DO (flow-through) RESET_B LOW to data out LOW on DO (pipelined) 1.28 1.50 1.28 1.50 0.40 0.47 2.08 2.44 0.66 0.76 6.08 6.99 164 143 tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B removal RESET_B recovery RESET_B minimum pulse width Clock cycle time Maximum frequency Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -9 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Table 2-135 • RAM4K9 Military-Case Conditions: TJ = 125°C, VCC = 1.425 V Parameter tAS tAH tENS tENH tBKS tBKH tDS tDH tCKQ1 Address setup time Address hold time REN_B, WEN_B setup time REN_B, WEN_B hold time BLK_B setup time BLK_B hold time Input data (DI) setup time Input data (DI) hold time Clock HIGH to new data valid on DO (output retained, WMODE = 0) Clock HIGH to new data valid on DO (flow-through, WMODE = 1) tCKQ2 tWRO tCCKH tRSTBQ Clock HIGH to new data valid on DO (pipelined) Description –1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz 0.26 0.31 0.00 0.00 0.15 0.18 0.10 0.12 0.25 0.29 0.02 0.02 0.19 0.23 0.00 0.00 1.89 2.22 2.50 2.93 0.95 1.11 Address collision clk-to-clk delay for reliable read access after write on same TBD TBD address Address collision clk-to-clk delay for reliable write access after write/read on TBD TBD same address RESET_B LOW to data out LOW on DO (flow-through) RESET_B LOW to data out LOW on DO (pipelined) 0.98 1.15 0.98 1.15 0.30 0.36 1.59 1.87 0.59 0.67 5.39 6.20 185 161 tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B removal RESET_B recovery RESET_B minimum pulse width Clock cycle time Maximum frequency Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 97 Radiation-Tolerant ProASIC3 FPGAs Table 2-136 • RAM512X18 Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V Parameter tAS tAH tENS tENH tDS tDH tCKQ1 tCKQ2 tWRO tCCKH tRSTBQ Address setup time Address hold time REN_B, WEN_B setup time REN_B, WEN_B hold time Input data (DI) setup time Input data (DI) hold time Clock HIGH to new data valid on DO (output retained, WMODE = 0) Clock HIGH to new data valid on DO (pipelined) Description –1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz 0.35 0.41 0.00 0.00 0.13 0.15 0.08 0.09 0.25 0.30 0.00 0.00 2.99 3.52 1.24 1.46 Address collision clk-to-clk delay for reliable read access after write on same TBD TBD address Address collision clk-to-clk delay for reliable write access after write/read on TBD TBD same address RESET_B LOW to data out LOW on DO (flow through) RESET_B LOW to data out LOW on DO (pipelined) 1.28 1.50 1.28 1.50 0.40 0.47 2.08 2.44 0.66 0.76 6.08 6.99 164 143 tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B removal RESET_B recovery RESET_B minimum pulse width Clock cycle time Maximum frequency Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -9 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Table 2-137 • RAM512X18 Military-Case Conditions: TJ = 125°C, VCC = 1.425 V Parameter tAS tAH tENS tENH tDS tDH tCKQ1 tCKQ2 tWRO tCCKH tRSTBQ Address setup time Address hold time REN_B, WEN_B setup time REN_B, WEN_B hold time Input data (DI) setup time Input data (DI) hold time Clock HIGH to new data valid on DO (output retained, WMODE = 0) Clock HIGH to new data valid on DO (pipelined) Description –1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz 0.26 0.31 0.00 0.00 0.10 0.11 0.06 0.07 0.19 0.23 0.00 0.00 2.29 2.69 0.95 1.12 Address collision clk-to-clk delay for reliable read access after write on same TBD TBD address Address collision clk-to-clk delay for reliable write access after write/read on TBD TBD same address RESET_B LOW to data out LOW on DO (flow through) RESET_B LOW to data out LOW on DO (pipelined) 0.98 1.15 0.98 1.15 0.30 0.36 1.59 1.87 0.59 0.67 5.39 6.20 185 161 tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B removal RESET_B recovery RESET_B minimum pulse width Clock cycle time Maximum frequency Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 - 99 Radiation-Tolerant ProASIC3 FPGAs FIFO FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP AEVAL11 AEVAL10 RD17 RD16 RD0 FULL AFULL EMPTY AEMPTY AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE RESET Figure 2-51 • FIFO Model 2 -1 0 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Timing Waveforms RCLK/ WCLK tMPWRSTB RESET_B tRSTFG EMPTY tRSTAF AEMPTY tRSTFG FULL tRSTAF AFULL WA/RA (Address Counter) Figure 2-52 • FIFO Reset tRSTCK MATCH (A0) tCYC RCLK tRCKEF EMPTY tCKAF AEMPTY WA/RA (Address Counter) NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY) Figure 2-53 • FIFO EMPTY Flag and AEMPTY Flag Assertion A dv a n c e v 0. 1 2 -101 Radiation-Tolerant ProASIC3 FPGAs tCYC WCLK tWCKFF FULL tCKAF AFULL WA/RA NO MATCH (Address Counter) NO MATCH Dist = AFF_TH MATCH (FULL) Figure 2-54 • FIFO FULL Flag and AFULL Flag Assertion WCLK WA/RA (Address Counter) MATCH (EMPTY) NO MATCH NO MATCH 2nd Rising Edge After 1st Write tRCKEF NO MATCH NO MATCH Dist = AEF_TH + 1 RCLK 1st Rising Edge After 1st Write EMPTY tCKAF AEMPTY Figure 2-55 • FIFO EMPTY Flag and AEMPTY Flag Deassertion RCLK WA/RA MATCH (FULL) NO MATCH (Address Counter) 1st Rising Edge After 1st WCLK Read FULL tCKAF AFULL NO MATCH 1st Rising Edge After 2nd Read tWCKF NO MATCH NO MATCH Dist = AFF_TH – 1 Figure 2-56 • FIFO FULL Flag and AFULL Flag Deassertion 2 -1 0 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-138 • FIFO Worst Military-Case Conditions: TJ = 125°C, VCC = 1.14 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ Description REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock HIGH to New Data Valid on DO (flow-through) Clock HIGH to New Data Valid on DO (pipelined) RCLK HIGH to Empty Flag Valid WCLK HIGH to Full Flag Valid Clock HIGH to Almost Empty/Full Flag Valid RESET_B LOW to Empty/Full Flag Valid RESET_B LOW to Almost Empty/Full Flag Valid RESET_B LOW to Data Out LOW on DO (flow-through) RESET_B LOW to Data Out LOW on DO (pipelined) tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency for FIFO –1 1.91 0.03 0.40 0.00 0.25 0.00 3.26 1.24 2.38 2.26 8.57 2.34 8.48 1.28 1.28 0.40 2.08 0.66 6.08 164 Std. 2.24 0.03 0.47 0.00 0.30 0.00 3.84 1.46 2.80 2.66 10.08 2.76 9.97 1.50 1.50 0.47 2.44 0.76 6.99 143 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 -103 Radiation-Tolerant ProASIC3 FPGAs Table 2-139 • FIFO Worst Military-Case Conditions: TJ = 125°C, VCC = 1.425 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ Description REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock HIGH to New Data Valid on DO (flow-through) Clock HIGH to New Data Valid on DO (pipelined) RCLK HIGH to Empty Flag Valid WCLK HIGH to Full Flag Valid Clock HIGH to Almost Empty/Full Flag Valid RESET_B LOW to Empty/Full Flag Valid RESET_B LOW to Almost Empty/Full Flag Valid RESET_B LOW to Data Out LOW on DO (flow-through) RESET_B LOW to Data Out LOW on DO (pipelined) tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency for FIFO –1 1.46 0.02 0.40 0.00 0.19 0.00 2.50 0.95 1.82 1.73 6.56 1.79 6.49 0.98 0.98 0.30 1.59 0.59 5.39 185 Std. 1.71 0.02 0.47 0.00 0.23 0.00 2.93 1.11 2.14 2.03 7.71 2.11 7.63 1.15 1.15 0.36 1.87 0.67 6.20 161 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -1 0 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Embedded FlashROM Characteristics tSU CLK tHOLD tSU tHOLD tSU tHOLD Address A0 tCKQ2 A1 tCKQ2 D0 tCKQ2 D1 Data D0 Figure 2-57 • Timing Diagram Timing Characteristics Table 2-140 • Embedded FlashROM Access Time Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V Parameter tSU tHOLD tCK2Q FMAX Description Address Setup Time Address Hold Time Clock to Out Maximum Clock Frequency –1 0.74 0.00 22.47 15 Std. 0.87 0.00 26.42 15 Units ns ns ns MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-141 • Embedded FlashROM Access Time Military-Case Conditions: TJ = 125°C, VCC = 1.425 V Parameter tSU tHOLD tCK2Q FMAX Description Address Setup Time Address Hold Time Clock to Out Maximum Clock Frequency –1 0.56 0.00 17.19 15 Std. 0.66 0.00 20.21 15 Units ns ns ns MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. A dv a n c e v 0. 1 2 -105 Radiation-Tolerant ProASIC3 FPGAs JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-18 for more details. Timing Characteristics Table 2-142 • JTAG 1532 Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V Parameter tDISU tDIHD tTMSSU tTMDHD tTCK2Q tRSTB2Q FTCKMAX tTRSTREM tTRSTREC tTRSTMPW Description Test Data Input Setup Time Test Data Input Hold Time Test Mode Select Setup Time Test Mode Select Hold Time Clock to Q (data out) Reset to Q (data out) TCK Maximum Frequency ResetB Removal Time ResetB Recovery Time ResetB Minimum Pulse –1 0.80 1.60 0.80 1.60 6.39 26.63 18.70 0.48 0.00 TBD Std. 0.94 1.88 0.94 1.88 7.52 31.33 15.90 0.56 0.00 TBD Units ns ns ns ns ns ns MHz ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-143 • JTAG 1532 Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V Parameter tDISU tDIHD tTMSSU tTMDHD tTCK2Q tRSTB2Q FTCKMAX tTRSTREM tTRSTREC tTRSTMPW Description Test Data Input Setup Time Test Data Input Hold Time Test Mode Select Setup Time Test Mode Select Hold Time Clock to Q (data out) Reset to Q (data out) TCK Maximum Frequency ResetB Removal Time ResetB Recovery Time ResetB Minimum Pulse –1 0.60 1.21 0.60 1.21 6.04 24.15 22.00 0.00 0.24 TBD Std. 0.71 1.42 0.71 1.42 7.10 28.41 19.00 0.00 0.28 TBD Units ns ns ns ns ns ns MHz ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 2 -1 0 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 DC and Switching Characteristics Part Number and Revision Date Part Number 51700107-002-0 Revised September 2008 Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status datasheet may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel’s products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. A dv a n c e v 0. 1 2 -107 Radiation-Tolerant ProASIC3 Packaging 3 – Package Pin Assignments 484-Pin CCGA A B C D E F G H J K L M N P R T U V W Y AA AB 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A dv a n c e v 0. 1 3-1 Package Pin Assignments 484-Pin CCGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 RT3PE600L GND GND VCCIB0 IO06NDB0V1 IO06PDB0V1 IO08NDB0V1 IO08PDB0V1 IO11PDB0V1 IO17PDB0V2 IO18NDB0V2 IO18PDB0V2 IO22PDB1V0 IO26PDB1V0 IO29NDB1V1 IO29PDB1V1 IO31NDB1V1 IO31PDB1V1 IO32NDB1V1 NC VCCIB1 GND GND GND VCCIB6 NC IO98PDB5V2 IO96NDB5V2 IO96PDB5V2 IO86NDB5V0 IO86PDB5V0 IO85PDB5V0 IO85NDB5V0 IO78PPB4V1 IO79NDB4V1 IO79PDB4V1 NC 484-Pin CCGA Pin Number AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 B1 B2 B3 B4 B5 B6 RT3PE600L NC IO71NDB4V0 IO71PDB4V0 NC NC NC VCCIB3 GND GND GND VCCIB5 IO97NDB5V2 IO97PDB5V2 IO93NDB5V1 IO93PDB5V1 IO87NDB5V0 IO87PDB5V0 NC NC IO75NDB4V1 IO75PDB4V1 IO72NDB4V0 IO72PDB4V0 IO73NDB4V0 IO73PDB4V0 NC NC VCCIB4 GND GND GND VCCIB7 NC IO03NDB0V0 IO03PDB0V0 IO07NDB0V1 484-Pin CCGA Pin Number B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 RT3PE600L IO07PDB0V1 IO11NDB0V1 IO17NDB0V2 IO14PDB0V2 IO19PDB0V2 IO22NDB1V0 IO26NDB1V0 NC NC IO30NDB1V1 IO30PDB1V1 IO32PDB1V1 NC NC VCCIB2 GND VCCIB7 NC NC NC GND IO04NDB0V0 IO04PDB0V0 VCC VCC IO14NDB0V2 IO19NDB0V2 NC NC VCC VCC NC NC GND NC NC 3 -2 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 484-Pin CCGA Pin Number C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 RT3PE600L NC VCCIB2 NC NC NC GND GAA0/IO00NDB0V 0 GAA1/IO00PDB0V 0 GAB0/IO01NDB0V 0 IO05PDB0V0 IO10PDB0V1 IO12PDB0V2 IO16NDB0V2 IO23NDB1V0 IO23PDB1V0 IO28NDB1V1 IO28PDB1V1 GBB1/IO34PDB1V1 GBA0/IO35NDB1V 1 GBA1/IO35PDB1V 1 GND NC NC NC NC NC GND GAB2/IO133PDB7 V1 GAA2/IO134PDB7 V1 GNDQ F10 F11 F12 F13 F14 F15 F16 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 484-Pin CCGA Pin Number E7 RT3PE600L GAB1/IO01PDB0V 0 IO05NDB0V0 IO10NDB0V1 IO12NDB0V2 IO16PDB0V2 IO20NDB1V0 IO24NDB1V0 IO24PDB1V0 GBC1/IO33PDB1V1 GBB0/IO34NDB1V 1 GNDQ GBA2/IO36PDB2V 0 IO42NDB2V0 GND NC NC NC IO131NDB7V1 IO131PDB7V1 IO133NDB7V1 IO134NDB7V1 VMV7 VCCPLA GAC0/IO02NDB0V 0 GAC1/IO02PDB0V 0 IO15NDB0V2 IO15PDB0V2 IO20PDB1V0 IO25NDB1V0 IO27PDB1V0 GBC0/IO33NDB1V 1 VCCPLB 484-Pin CCGA Pin Number F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 RT3PE600L VMV2 IO36NDB2V0 IO42PDB2V0 NC NC NC IO127NDB7V1 IO127PDB7V1 NC IO128PDB7V1 IO129PDB7V1 GAC2/IO132PDB7 V1 VCOMPLA GNDQ IO09NDB0V1 IO09PDB0V1 IO13PDB0V2 IO21PDB1V0 IO25PDB1V0 IO27NDB1V0 GNDQ VCOMPLB GBB2/IO37PDB2V0 IO39PDB2V0 IO39NDB2V0 IO43PDB2V0 IO43NDB2V0 NC NC NC VCC IO128NDB7V1 IO129NDB7V1 IO132NDB7V1 IO130PDB7V1 A dv a n c e v 0. 1 3-3 Package Pin Assignments 484-Pin CCGA Pin Number H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 RT3PE600L VMV0 VCCIB0 VCCIB0 IO13NDB0V2 IO21NDB1V0 VCCIB1 VCCIB1 VMV1 GBC2/IO38PDB2V0 IO37NDB2V0 IO41NDB2V0 IO41PDB2V0 VCC NC NC IO123NDB7V0 IO123PDB7V0 NC IO124PDB7V0 IO125PDB7V0 IO126PDB7V0 IO130NDB7V1 VCCIB7 GND VCC VCC VCC VCC GND VCCIB2 IO38NDB2V0 IO40NDB2V0 IO40PDB2V0 IO45PPB2V1 NC IO48PDB2V1 L7 L8 L9 L6 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 L1 L2 L3 L4 L5 484-Pin CCGA Pin Number J22 K1 K2 K3 K4 K5 K6 K7 RT3PE600L IO46PDB2V1 IO121NDB7V0 IO121PDB7V0 NC IO124NDB7V0 IO125NDB7V0 IO126NDB7V0 GFC1/IO120PPB7V 0 VCCIB7 VCC GND GND GND GND VCC VCCIB2 GCC1/IO50PPB2V1 IO44NDB2V1 IO44PDB2V1 IO49NPB2V1 IO45NPB2V1 IO48NDB2V1 IO46NDB2V1 NC IO122PDB7V0 IO122NDB7V0 GFB0/IO119NPB7V 0 GFA0/IO118NDB6 V1 GFB1/IO119PPB7V 0 VCOMPLF GFC0/IO120NPB7V 0 VCC M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M5 M6 M7 M8 484-Pin CCGA Pin Number L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 M3 M4 RT3PE600L GND GND GND GND VCC GCC0/IO50NPB2V1 GCB1/IO51PPB2V1 GCA0/IO52NPB3V 0 VCOMPLC GCB0/IO51NPB2V1 IO49PPB2V1 IO47NDB2V1 IO47PDB2V1 NC IO114NPB6V1 IO117NDB6V1 GFA2/IO117PDB6V 1 GFA1/IO118PDB6V 1 VCCPLF IO116NDB6V1 GFB2/IO116PDB6V 1 VCC GND GND GND GND VCC GCB2/IO54PPB3V0 GCA1/IO52PPB3V0 GCC2/IO55PPB3V0 VCCPLC GCA2/IO53PDB3V 0 3 -4 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 484-Pin CCGA Pin Number M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 RT3PE600L IO53NDB3V0 IO56PDB3V0 NC IO114PPB6V1 IO111NDB6V1 NC GFC2/IO115PPB6V 1 IO113PPB6V1 IO112PDB6V1 IO112NDB6V1 VCCIB6 VCC GND GND GND GND VCC VCCIB3 IO54NPB3V0 IO57NPB3V0 IO55NPB3V0 IO57PPB3V0 NC IO56NDB3V0 IO58PDB3V0 NC IO111PDB6V1 IO115NPB6V1 IO113NPB6V1 IO109PPB6V0 IO108PDB6V0 IO108NDB6V0 VCCIB6 GND VCC R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 484-Pin CCGA Pin Number P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 RT3PE600L VCC VCC VCC GND VCCIB3 GDB0/IO66NPB3V 1 IO60NDB3V1 IO60PDB3V1 IO61PDB3V1 NC IO59PDB3V0 IO58NDB3V0 NC IO110PDB6V0 VCC IO109NPB6V0 IO106NDB6V0 IO106PDB6V0 GEC0/IO104NPB6V 0 VMV5 VCCIB5 VCCIB5 IO84NDB5V0 IO84PDB5V0 VCCIB4 VCCIB4 VMV3 VCCPLD GDB1/IO66PPB3V1 GDC1/IO65PDB3V 1 IO61NDB3V1 VCC IO59NDB3V0 IO62PDB3V1 U5 U6 U7 U8 U9 U10 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 484-Pin CCGA Pin Number T1 T2 T3 T4 T5 T6 T7 T8 T9 RT3PE600L NC IO110NDB6V0 NC IO105PDB6V0 IO105NDB6V0 GEC1/IO104PPB6V 0 VCOMPLE GNDQ GEA2/IO101PPB5V 2 IO92NDB5V1 IO90NDB5V1 IO82NDB5V0 IO74NDB4V1 IO74PDB4V1 GNDQ VCOMPLD VJTAG GDC0/IO65NDB3V 1 GDA1/IO67PDB3V 1 NC IO64PDB3V1 IO62NDB3V1 NC IO107PDB6V0 IO107NDB6V0 GEB1/IO103PDB6V 0 GEB0/IO103NDB6 V0 VMV6 VCCPLE IO101NPB5V2 IO95PPB5V1 IO92PDB5V1 A dv a n c e v 0. 1 3-5 Package Pin Assignments 484-Pin CCGA Pin Number U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 RT3PE600L IO90PDB5V1 IO82PDB5V0 IO76NDB4V1 IO76PDB4V1 VMV4 TCK VPUMP TRST GDA0/IO67NDB3V 1 NC IO64NDB3V1 IO63PDB3V1 NC NC GND GEA1/IO102PDB6V 0 GEA0/IO102NDB6 V0 GNDQ GEC2/IO99PDB5V2 IO95NPB5V1 IO91NDB5V1 IO91PDB5V1 IO83NDB5V0 IO83PDB5V0 IO77NDB4V1 IO77PDB4V1 IO69NDB4V0 GDB2/IO69PDB4V 0 TDI GNDQ TDO GND NC W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 484-Pin CCGA Pin Number V22 W1 W2 W3 W4 W5 W6 RT3PE600L IO63NDB3V1 NC NC NC GND IO100NDB5V2 FF/GEB2/IO100PDB 5V2 IO99NDB5V2 IO88NDB5V0 IO88PDB5V0 IO89NDB5V0 IO80NDB4V1 IO81NDB4V1 IO81PDB4V1 IO70NDB4V0 GDC2/IO70PDB4V 0 IO68NDB4V0 GDA2/IO68PDB4V 0 TMS GND NC NC NC VCCIB6 NC NC IO98NDB5V2 GND IO94NDB5V1 IO94PDB5V1 VCC VCC IO89PDB5V0 IO80PDB4V1 484-Pin CCGA Pin Number Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 RT3PE600L IO78NPB4V1 NC VCC VCC NC NC GND NC NC NC VCCIB3 3 -6 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 484-Pin CCGA Pin Number RT3PE3000L Function A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 GND GND VCCIB0 IO10NDB0V1 IO10PDB0V1 IO16NDB0V1 IO16PDB0V1 IO18PDB0V2 IO24PDB0V2 IO28NDB0V3 IO28PDB0V3 IO46PDB1V0 IO54PDB1V1 IO56NDB1V1 IO56PDB1V1 IO64NDB1V2 IO64PDB1V2 IO72NDB1V3 IO74NDB1V4 VCCIB1 GND GND GND VCCIB6 IO228PDB5V4 IO224PDB5V3 IO218NDB5V3 IO218PDB5V3 IO212NDB5V2 IO212PDB5V2 IO198PDB5V0 IO198NDB5V0 IO188PPB4V4 IO180NDB4V3 IO180PDB4V3 IO170NDB4V2 484-Pin CCGA Pin Number RT3PE3000L Function AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 B1 B2 B3 B4 B5 B6 IO170PDB4V2 IO166NDB4V1 IO166PDB4V1 IO160NDB4V0 IO160PDB4V0 IO158NPB4V0 VCCIB3 GND GND GND VCCIB5 IO216NDB5V2 IO216PDB5V2 IO210NDB5V2 IO210PDB5V2 IO208NDB5V1 IO208PDB5V1 IO197NDB5V0 IO197PDB5V0 IO174NDB4V2 IO174PDB4V2 IO172NDB4V2 IO172PDB4V2 IO168NDB4V1 IO168PDB4V1 IO162NDB4V1 IO162PDB4V1 VCCIB4 GND GND GND VCCIB7 IO06PPB0V0 IO08NDB0V0 IO08PDB0V0 IO14NDB0V1 484-Pin CCGA Pin Number RT3PE3000L Function B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 IO14PDB0V1 IO18NDB0V2 IO24NDB0V2 IO34PDB0V4 IO40PDB0V4 IO46NDB1V0 IO54NDB1V1 IO62NDB1V2 IO62PDB1V2 IO68NDB1V3 IO68PDB1V3 IO72PDB1V3 IO74PDB1V4 IO76NPB1V4 VCCIB2 GND VCCIB7 IO303PDB7V3 IO305PDB7V3 IO06NPB0V0 GND IO12NDB0V1 IO12PDB0V1 VCC VCC IO34NDB0V4 IO40NDB0V4 IO48NDB1V0 IO48PDB1V0 VCC VCC IO70NDB1V3 IO70PDB1V3 GND IO76PPB1V4 IO88NDB2V0 A dv a n c e v 0. 1 3-7 Package Pin Assignments 484-Pin CCGA Pin Number RT3PE3000L Function C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 IO94PPB2V1 VCCIB2 IO293PDB7V2 IO303NDB7V3 IO305NDB7V3 GND GAA0/IO00NDB0V0 GAA1/IO00PDB0V0 GAB0/IO01NDB0V0 IO20PDB0V2 IO22PDB0V2 IO30PDB0V3 IO38NDB0V4 IO52NDB1V1 IO52PDB1V1 IO66NDB1V3 IO66PDB1V3 GBB1/IO80PDB1V4 GBA0/IO81NDB1V4 GBA1/IO81PDB1V4 GND IO88PDB2V0 IO90PDB2V1 IO94NPB2V1 IO293NDB7V2 IO299PPB7V3 GND GAB2/IO308PDB7V4 GAA2/IO309PDB7V4 GNDQ GAB1/IO01PDB0V0 IO20NDB0V2 IO22NDB0V2 IO30NDB0V3 IO38PDB0V4 IO44NDB1V0 484-Pin CCGA Pin Number RT3PE3000L Function E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 IO58NDB1V2 IO58PDB1V2 GBC1/IO79PDB1V4 GBB0/IO80NDB1V4 GNDQ GBA2/IO82PDB2V0 IO86NDB2V0 GND IO90NDB2V1 IO98PDB2V2 IO299NPB7V3 IO301NDB7V3 IO301PDB7V3 IO308NDB7V4 IO309NDB7V4 VMV7 VCCPLA GAC0/IO02NDB0V0 GAC1/IO02PDB0V0 IO32NDB0V3 IO32PDB0V3 IO44PDB1V0 IO50NDB1V1 IO60PDB1V2 GBC0/IO79NDB1V4 VCCPLB VMV2 IO82NDB2V0 IO86PDB2V0 IO96PDB2V1 IO96NDB2V1 IO98NDB2V2 IO289NDB7V1 IO289PDB7V1 IO291PPB7V2 IO295PDB7V2 484-Pin CCGA Pin Number RT3PE3000L Function G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 IO297PDB7V2 GAC2/IO307PDB7V4 VCOMPLA GNDQ IO26NDB0V3 IO26PDB0V3 IO36PDB0V4 IO42PDB1V0 IO50PDB1V1 IO60NDB1V2 GNDQ VCOMPLB GBB2/IO83PDB2V0 IO92PDB2V1 IO92NDB2V1 IO102PDB2V2 IO102NDB2V2 IO105NDB2V2 IO286PSB7V1 IO291NPB7V2 VCC IO295NDB7V2 IO297NDB7V2 IO307NDB7V4 IO287PDB7V1 VMV0 VCCIB0 VCCIB0 IO36NDB0V4 IO42NDB1V0 VCCIB1 VCCIB1 VMV1 GBC2/IO84PDB2V0 IO83NDB2V0 IO100NDB2V2 3 -8 A dv a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 484-Pin CCGA Pin Number RT3PE3000L Function H19 H20 H21 H22 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 IO100PDB2V2 VCC VMV2 IO105PDB2V2 IO285NDB7V1 IO285PDB7V1 VMV7 IO279PDB7V0 IO283PDB7V1 IO281PDB7V0 IO287NDB7V1 VCCIB7 GND VCC VCC VCC VCC GND VCCIB2 IO84NDB2V0 IO104NDB2V2 IO104PDB2V2 IO106PPB2V3 GNDQ IO109PDB2V3 IO107PDB2V3 IO277NDB7V0 IO277PDB7V0 GNDQ IO279NDB7V0 IO283NDB7V1 IO281NDB7V0 GFC1/IO275PPB7V0 VCCIB7 VCC GND 484-Pin CCGA Pin Number RT3PE3000L Function K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 GND GND GND VCC VCCIB2 GCC1/IO112PPB2V3 IO108NDB2V3 IO108PDB2V3 IO110NPB2V3 IO106NPB2V3 IO109NDB2V3 IO107NDB2V3 IO257PSB6V2 IO276PDB7V0 IO276NDB7V0 GFB0/IO274NPB7V0 GFA0/IO273NDB6V4 GFB1/IO274PPB7V0 VCOMPLF GFC0/IO275NPB7V0 VCC GND GND GND GND VCC GCC0/IO112NPB2V3 GCB1/IO113PPB2V3 GCA0/IO114NPB3V0 VCOMPLC GCB0/IO113NPB2V3 IO110PPB2V3 IO111NDB2V3 IO111PDB2V3 GNDQ IO255NPB6V2 484-Pin CCGA Pin Number RT3PE3000L Function M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 IO272NDB6V4 GFA2/IO272PDB6V4 GFA1/IO273PDB6V4 VCCPLF IO271NDB6V4 GFB2/IO271PDB6V4 VCC GND GND GND GND VCC GCB2/IO116PPB3V0 GCA1/IO114PPB3V0 GCC2/IO117PPB3V0 VCCPLC GCA2/IO115PDB3V0 IO115NDB3V0 IO126PDB3V1 IO124PSB3V1 IO255PPB6V2 IO253NDB6V2 VMV6 GFC2/IO270PPB6V4 IO261PPB6V3 IO263PDB6V3 IO263NDB6V3 VCCIB6 VCC GND GND GND GND VCC VCCIB3 IO116NPB3V0 A dv a n c e v 0. 1 3-9 Package Pin Assignments 484-Pin CCGA Pin Number RT3PE3000L Function N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 IO132NPB3V2 IO117NPB3V0 IO132PPB3V2 GNDQ IO126NDB3V1 IO128PDB3V1 IO247PDB6V1 IO253PDB6V2 IO270NPB6V4 IO261NPB6V3 IO249PPB6V1 IO259PDB6V3 IO259NDB6V3 VCCIB6 GND VCC VCC VCC VCC GND VCCIB3 GDB0/IO152NPB3V4 IO136NDB3V2 IO136PDB3V2 IO138PDB3V3 VMV3 IO130PDB3V2 IO128NDB3V1 IO247NDB6V1 IO245PDB6V1 VCC IO249NPB6V1 IO251NDB6V2 IO251PDB6V2 GEC0/IO236NPB6V0 VMV5 484-Pin CCGA Pin Number RT3PE3000L Function R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 VCCIB5 VCCIB5 IO196NDB5V0 IO196PDB5V0 VCCIB4 VCCIB4 VMV3 VCCPLD GDB1/IO152PPB3V4 GDC1/IO151PDB3V4 IO138NDB3V3 VCC IO130NDB3V2 IO134PDB3V2 IO243PPB6V1 IO245NDB6V1 IO243NPB6V1 IO241PDB6V0 IO241NDB6V0 GEC1/IO236PPB6V0 VCOMPLE GNDQ GEA2/IO233PPB5V4 IO206NDB5V1 IO202NDB5V1 IO194NDB5V0 IO186NDB4V4 IO186PDB4V4 GNDQ VCOMPLD VJTAG GDC0/IO151NDB3V4 GDA1/IO153PDB3V4 IO144PDB3V3 IO140PDB3V3 IO134NDB3V2 484-Pin CCGA Pin Number RT3PE3000L Function U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 IO240PPB6V0 IO238PDB6V0 IO238NDB6V0 GEB1/IO235PDB6V0 GEB0/IO235NDB6V0 VMV6 VCCPLE IO233NPB5V4 IO222PPB5V3 IO206PDB5V1 IO202PDB5V1 IO194PDB5V0 IO176NDB4V2 IO176PDB4V2 VMV4 TCK VPUMP TRST GDA0/IO153NDB3V4 IO144NDB3V3 IO140NDB3V3 IO142PDB3V3 IO239PDB6V0 IO240NPB6V0 GND GEA1/IO234PDB6V0 GEA0/IO234NDB6V0 GNDQ GEC2/IO231PDB5V4 IO222NPB5V3 IO204NDB5V1 IO204PDB5V1 IO195NDB5V0 IO195PDB5V0 IO178NDB4V3 IO178PDB4V3 3 -1 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 484-Pin CCGA Pin Number RT3PE3000L Function V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 IO155NDB4V0 GDB2/IO155PDB4V0 TDI GNDQ TDO GND IO146PDB3V4 IO142NDB3V3 IO239NDB6V0 IO237PDB6V0 IO230PSB5V4 GND IO232NDB5V4 FF/GEB2/IO232PDB5V 4 IO231NDB5V4 IO214NDB5V2 IO214PDB5V2 IO200NDB5V0 IO192NDB4V4 IO184NDB4V3 IO184PDB4V3 IO156NDB4V0 GDC2/IO156PDB4V0 IO154NDB4V0 GDA2/IO154PDB4V0 TMS GND IO150NDB3V4 IO146NDB3V4 IO148PPB3V4 VCCIB6 IO237NDB6V0 IO228NDB5V4 IO224NDB5V3 GND 484-Pin CCGA Pin Number RT3PE3000L Function Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 IO220NDB5V3 IO220PDB5V3 VCC VCC IO200PDB5V0 IO192PDB4V4 IO188NPB4V4 IO187PSB4V4 VCC VCC IO164NDB4V1 IO164PDB4V1 GND IO158PPB4V0 IO150PDB3V4 IO148NPB3V4 VCCIB3 A dv a n c e v 0. 1 3 - 11 Package Pin Assignments 896-Pin CCGA A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Note: This is the bottom view. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 3 -1 2 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 896-CCGA Pin Number RT3PE3000L Function A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 GND GND IO14NPB0V1 GND IO07NPB0V0 GND IO09NDB0V1 IO17NDB0V2 IO17PDB0V2 IO21NDB0V2 IO21PDB0V2 IO33NDB0V4 IO33PDB0V4 IO35NDB0V4 IO35PDB0V4 IO41NDB1V0 IO43NDB1V0 IO43PDB1V0 IO45NDB1V0 IO45PDB1V0 IO57NDB1V2 IO57PDB1V2 GND IO69PPB1V3 GND GBC1/IO79PPB1V4 GND GND IO256PDB6V2 IO248PDB6V1 IO248NDB6V1 IO246NDB6V1 GEA1/IO234PDB6V0 GEA0/IO234NDB6V0 IO243PPB6V1 IO245NDB6V1 896-CCGA Pin Number RT3PE3000L Function AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 GEB1/IO235PPB6V0 VCC IO226PPB5V4 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB4 VCCIB4 VCCIB4 VCCIB4 IO174PDB4V2 VCC IO142NPB3V3 IO144NDB3V3 IO144PDB3V3 IO146NDB3V4 IO146PDB3V4 IO147PDB3V4 IO139NDB3V3 IO139PDB3V3 IO133NDB3V2 IO256NDB6V2 IO244PDB6V1 IO244NDB6V1 IO241PDB6V0 IO241NDB6V0 IO243NPB6V1 VCCIB6 VCCPLE VCC IO222PDB5V3 IO218PPB5V3 IO206NDB5V1 IO206PDB5V1 IO198NDB5V0 896-CCGA Pin Number RT3PE3000L Function AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 IO198PDB5V0 IO192NDB4V4 IO192PDB4V4 IO178NDB4V3 IO178PDB4V3 IO174NDB4V2 IO162NPB4V1 VCC VCCPLD VCCIB3 IO150PDB3V4 IO148PDB3V4 IO147NDB3V4 IO145PDB3V3 IO143PDB3V3 IO137PDB3V2 IO254PDB6V2 IO254NDB6V2 IO240PDB6V0 GEC1/IO236PDB6V0 IO237PDB6V0 IO237NDB6V0 VCOMPLE GND IO226NPB5V4 IO222NDB5V3 IO216NPB5V2 IO210NPB5V2 IO204NDB5V1 IO204PDB5V1 IO194NDB5V0 IO188NDB4V4 IO188PDB4V4 IO182PPB4V3 IO170NPB4V2 IO164NDB4V1 A dv a n c e v 0. 1 3 - 13 Package Pin Assignments 896-CCGA Pin Number RT3PE3000L Function AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 IO164PDB4V1 IO162PPB4V1 GND VCOMPLD IO150NDB3V4 IO148NDB3V4 GDA1/IO153PDB3V4 IO145NDB3V3 IO143NDB3V3 IO137NDB3V2 GND IO242NPB6V1 IO240NDB6V0 GEC0/IO236NDB6V0 VCCIB6 GNDQ VCC VMV5 VCCIB5 IO224PPB5V3 IO218NPB5V3 IO216PPB5V2 IO210PPB5V2 IO202PPB5V1 IO194PDB5V0 IO190PDB4V4 IO182NPB4V3 IO176NDB4V2 IO176PDB4V2 IO170PPB4V2 IO166PDB4V1 VCCIB4 TCK VCC TRST VCCIB3 896-CCGA Pin Number RT3PE3000L Function AD27 AD28 AD29 AD30 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AF1 AF2 GDA0/IO153NDB3V4 GDC0/IO151NDB3V4 GDC1/IO151PDB3V4 GND IO242PPB6V1 VCC IO239PDB6V0 IO239NDB6V0 VMV6 GND GNDQ IO230NDB5V4 IO224NPB5V3 IO214NPB5V2 IO212NDB5V2 IO212PDB5V2 IO202NPB5V1 IO200NDB5V0 IO196PDB5V0 IO190NDB4V4 IO184PDB4V3 IO184NDB4V3 IO172PDB4V2 IO172NDB4V2 IO166NDB4V1 IO160PDB4V0 GNDQ VMV4 GND GDB0/IO152NDB3V4 GDB1/IO152PDB3V4 VMV3 VCC IO149PDB3V4 GND IO238PPB6V0 896-CCGA Pin Number RT3PE3000L Function AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 VCCIB6 IO220NPB5V3 VCC IO228NDB5V4 VCCIB5 IO230PDB5V4 IO229NDB5V4 IO229PDB5V4 IO214PPB5V2 IO208NDB5V1 IO208PDB5V1 IO200PDB5V0 IO196NDB5V0 IO186NDB4V4 IO186PDB4V4 IO180NDB4V3 IO180PDB4V3 IO168NDB4V1 IO168PDB4V1 IO160NDB4V0 IO158NPB4V0 VCCIB4 IO154NPB4V0 VCC TDO VCCIB3 GNDQ GND IO238NPB6V0 VCC IO232NPB5V4 GND IO220PPB5V3 IO228PDB5V4 IO231NDB5V4 GEC2/IO231PDB5V4 3 -1 4 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 896-CCGA Pin Number RT3PE3000L Function AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 IO225NPB5V3 IO223NPB5V3 IO221PDB5V3 IO221NDB5V3 IO205NPB5V1 IO199NDB5V0 IO199PDB5V0 IO187NDB4V4 IO187PDB4V4 IO181NDB4V3 IO171PPB4V2 IO165NPB4V1 IO161NPB4V0 IO159NDB4V0 IO159PDB4V0 IO158PPB4V0 GDB2/IO155PDB4V0 GDA2/IO154PPB4V0 GND VJTAG VCC IO149NDB3V4 GND IO233NPB5V4 VCC FF/GEB2/IO232PPB5V 4 VCCIB5 IO219NDB5V3 IO219PDB5V3 IO227NDB5V4 IO227PDB5V4 IO225PPB5V3 IO223PPB5V3 IO211NDB5V2 IO211PDB5V2 896-CCGA Pin Number RT3PE3000L Function AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 IO205PPB5V1 IO195NDB5V0 IO185NDB4V3 IO185PDB4V3 IO181PDB4V3 IO177NDB4V2 IO171NPB4V2 IO165PPB4V1 IO161PPB4V0 IO157NDB4V0 IO157PDB4V0 IO155NDB4V0 VCCIB4 TDI VCC VPUMP GND GND GND GEA2/IO233PPB5V4 VCC IO217NPB5V2 VCC IO215NPB5V2 IO213NDB5V2 IO213PDB5V2 IO209NDB5V1 IO209PDB5V1 IO203NDB5V1 IO203PDB5V1 IO197NDB5V0 IO195PDB5V0 IO183NDB4V3 IO183PDB4V3 IO179NPB4V3 IO177PDB4V2 896-CCGA Pin Number RT3PE3000L Function AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 IO173NDB4V2 IO173PDB4V2 IO163NDB4V1 IO163PDB4V1 IO167NPB4V1 VCC IO156NPB4V0 VCC TMS GND GND GND GND IO217PPB5V2 GND IO215PPB5V2 GND IO207NDB5V1 IO207PDB5V1 IO201NDB5V0 IO201PDB5V0 IO193NDB4V4 IO193PDB4V4 IO197PDB5V0 IO191NDB4V4 IO191PDB4V4 IO189NDB4V4 IO189PDB4V4 IO179PPB4V3 IO175NDB4V2 IO175PDB4V2 IO169NDB4V1 IO169PDB4V1 GND IO167PPB4V1 GND A dv a n c e v 0. 1 3 - 15 Package Pin Assignments 896-CCGA Pin Number RT3PE3000L Function AK27 AK28 AK29 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 C1 C2 C3 GDC2/IO156PPB4V0 GND GND GND GND GAA2/IO309PPB7V4 VCC IO14PPB0V1 VCC IO07PPB0V0 IO09PDB0V1 IO15PPB0V1 IO19NDB0V2 IO19PDB0V2 IO29NDB0V3 IO29PDB0V3 IO31PPB0V3 IO37NDB0V4 IO37PDB0V4 IO41PDB1V0 IO51NDB1V1 IO59PDB1V2 IO53PDB1V1 IO53NDB1V1 IO61NDB1V2 IO61PDB1V2 IO69NPB1V3 VCC GBC0/IO79NPB1V4 VCC IO64NPB1V2 GND GND GND IO309NPB7V4 VCC 896-CCGA Pin Number RT3PE3000L Function C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 D1 D2 D3 D4 D5 D6 D7 D8 D9 GAA0/IO00NPB0V0 VCCIB0 IO03PDB0V0 IO03NDB0V0 GAB1/IO01PDB0V0 IO05PDB0V0 IO15NPB0V1 IO25NDB0V3 IO25PDB0V3 IO31NPB0V3 IO27NDB0V3 IO39NDB0V4 IO39PDB0V4 IO55PPB1V1 IO51PDB1V1 IO59NDB1V2 IO63NDB1V2 IO63PDB1V2 IO67NDB1V3 IO67PDB1V3 IO75NDB1V4 IO75PDB1V4 VCCIB1 IO64PPB1V2 VCC GBA1/IO81PPB1V4 GND IO303PPB7V3 VCC IO305NPB7V3 GND GAA1/IO00PPB0V0 GAC1/IO02PDB0V0 IO06NPB0V0 GAB0/IO01NDB0V0 IO05NDB0V0 896-CCGA Pin Number RT3PE3000L Function D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 IO11NDB0V1 IO11PDB0V1 IO23NDB0V2 IO23PDB0V2 IO27PDB0V3 IO40PDB0V4 IO47NDB1V0 IO47PDB1V0 IO55NPB1V1 IO65NDB1V3 IO65PDB1V3 IO71NDB1V3 IO71PDB1V3 IO73NDB1V4 IO73PDB1V4 IO74NDB1V4 GBB0/IO80NPB1V4 GND GBA0/IO81NPB1V4 VCC GBA2/IO82PPB2V0 GND IO303NPB7V3 VCCIB7 IO305PPB7V3 VCC GAC0/IO02NDB0V0 VCCIB0 IO06PPB0V0 IO24NDB0V2 IO24PDB0V2 IO13NDB0V1 IO13PDB0V1 IO34NDB0V4 IO34PDB0V4 IO40NDB0V4 3 -1 6 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 896-CCGA Pin Number RT3PE3000L Function E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 IO49NDB1V1 IO49PDB1V1 IO50PDB1V1 IO58PDB1V2 IO60NDB1V2 IO77PDB1V4 IO68NDB1V3 IO68PDB1V3 VCCIB1 IO74PDB1V4 VCC GBB1/IO80PPB1V4 VCCIB2 IO82NPB2V0 GND IO296PPB7V2 VCC IO306PDB7V4 IO297PDB7V2 VMV7 GND GNDQ IO12NDB0V1 IO12PDB0V1 IO10PDB0V1 IO16PDB0V1 IO22NDB0V2 IO30NDB0V3 IO30PDB0V3 IO36PDB0V4 IO48NDB1V0 IO48PDB1V0 IO50NDB1V1 IO58NDB1V2 IO60PDB1V2 IO77NDB1V4 896-CCGA Pin Number RT3PE3000L Function F22 F23 F24 F25 F26 F27 F28 F29 F30 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 IO72NDB1V3 IO72PDB1V3 GNDQ GND VMV2 IO86PDB2V0 IO92PDB2V1 VCC IO100NPB2V2 GND IO296NPB7V2 IO306NDB7V4 IO297NDB7V2 VCCIB7 GNDQ VCC VMV0 VCCIB0 IO10NDB0V1 IO16NDB0V1 IO22PDB0V2 IO26PPB0V3 IO38NPB0V4 IO36NDB0V4 IO46NDB1V0 IO46PDB1V0 IO56NDB1V1 IO56PDB1V1 IO66NDB1V3 IO66PDB1V3 VCCIB1 VMV1 VCC GNDQ VCCIB2 IO86NDB2V0 896-CCGA Pin Number RT3PE3000L Function G28 G29 G30 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 J1 J2 J3 IO92NDB2V1 IO100PPB2V2 GND IO294PDB7V2 IO294NDB7V2 IO300NDB7V3 IO300PDB7V3 IO295PDB7V2 IO299PDB7V3 VCOMPLA GND IO08NDB0V0 IO08PDB0V0 IO18PDB0V2 IO26NPB0V3 IO28NDB0V3 IO28PDB0V3 IO38PPB0V4 IO42NDB1V0 IO52NDB1V1 IO52PDB1V1 IO62NDB1V2 IO62PDB1V2 IO70NDB1V3 IO70PDB1V3 GND VCOMPLB GBC2/IO84PDB2V0 IO84NDB2V0 IO96PDB2V1 IO96NDB2V1 IO89PDB2V0 IO89NDB2V0 IO290NDB7V2 IO290PDB7V2 IO302NDB7V3 A dv a n c e v 0. 1 3 - 17 Package Pin Assignments 896-CCGA Pin Number RT3PE3000L Function J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 K1 K2 K3 K4 K5 K6 K7 K8 K9 IO302PDB7V3 IO295NDB7V2 IO299NDB7V3 VCCIB7 VCCPLA VCC IO04NPB0V0 IO18NDB0V2 IO20NDB0V2 IO20PDB0V2 IO32NDB0V3 IO32PDB0V3 IO42PDB1V0 IO44NDB1V0 IO44PDB1V0 IO54NDB1V1 IO54PDB1V1 IO76NPB1V4 VCC VCCPLB VCCIB2 IO90PDB2V1 IO90NDB2V1 GBB2/IO83PDB2V0 IO83NDB2V0 IO91PDB2V1 IO91NDB2V1 IO288NDB7V1 IO288PDB7V1 IO304NDB7V3 IO304PDB7V3 GAB2/IO308PDB7V4 IO308NDB7V4 IO301PDB7V3 IO301NDB7V3 GAC2/IO307PPB7V4 896-CCGA Pin Number RT3PE3000L Function K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 VCC IO04PPB0V0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB1 IO76PPB1V4 VCC IO78PPB1V4 IO88NDB2V0 IO88PDB2V0 IO94PDB2V1 IO94NDB2V1 IO85PDB2V0 IO85NDB2V0 IO93PDB2V1 IO93NDB2V1 IO286NDB7V1 IO286PDB7V1 IO298NDB7V3 IO298PDB7V3 IO283PDB7V1 IO291NDB7V2 IO291PDB7V2 IO293PDB7V2 IO293NDB7V2 IO307NPB7V4 VCC VCC VCC VCC VCC 896-CCGA Pin Number RT3PE3000L Function L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 VCC VCC VCC VCC VCC IO78NPB1V4 IO104NPB2V2 IO98NDB2V2 IO98PDB2V2 IO87PDB2V0 IO87NDB2V0 IO97PDB2V1 IO101PDB2V2 IO103PDB2V2 IO119NDB3V0 IO282NDB7V1 IO282PDB7V1 IO292NDB7V2 IO292PDB7V2 IO283NDB7V1 IO285PDB7V1 IO287PDB7V1 IO289PDB7V1 IO289NDB7V1 VCCIB7 VCC GND GND GND GND GND GND GND GND VCC VCCIB2 3 -1 8 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 896-CCGA Pin Number RT3PE3000L Function M22 M23 M24 M25 M26 M27 M28 M29 M30 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 N27 NC IO104PPB2V2 IO102PDB2V2 IO102NDB2V2 IO95PDB2V1 IO97NDB2V1 IO101NDB2V2 IO103NDB2V2 IO119PDB3V0 IO276PDB7V0 IO278PDB7V0 IO280PDB7V0 IO284PDB7V1 IO279PDB7V0 IO285NDB7V1 IO287NDB7V1 IO281NDB7V0 IO281PDB7V0 VCCIB7 VCC GND GND GND GND GND GND GND GND VCC VCCIB2 IO106NDB2V3 IO106PDB2V3 IO108PDB2V3 IO108NDB2V3 IO95NDB2V1 IO99NDB2V2 896-CCGA Pin Number RT3PE3000L Function N28 N29 N30 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 R1 R2 R3 IO99PDB2V2 IO107PDB2V3 IO107NDB2V3 IO276NDB7V0 IO278NDB7V0 IO280NDB7V0 IO284NDB7V1 IO279NDB7V0 GFC1/IO275PDB7V0 GFC0/IO275NDB7V0 IO277PDB7V0 IO277NDB7V0 VCCIB7 VCC GND GND GND GND GND GND GND GND VCC VCCIB2 GCC1/IO112PDB2V3 IO110PDB2V3 IO110NDB2V3 IO109PPB2V3 IO111NPB2V3 IO105PDB2V2 IO105NDB2V2 GCC2/IO117PDB3V0 IO117NDB3V0 GFC2/IO270PDB6V4 GFB1/IO274PPB7V0 VCOMPLF 896-CCGA Pin Number RT3PE3000L Function R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 T1 T2 T3 T4 T5 T6 T7 T8 T9 GFA0/IO273NDB6V4 GFB0/IO274NPB7V0 IO271NDB6V4 GFB2/IO271PDB6V4 IO269PDB6V4 IO269NDB6V4 VCCIB7 VCC GND GND GND GND GND GND GND GND VCC VCCIB2 GCC0/IO112NDB2V3 GCB2/IO116PDB3V0 IO118PDB3V0 IO111PPB2V3 IO122PPB3V1 GCA0/IO114NPB3V0 VCOMPLC GCB1/IO113PPB2V3 IO115NPB3V0 IO270NDB6V4 VCCPLF GFA2/IO272PPB6V4 GFA1/IO273PDB6V4 IO272NPB6V4 IO267NDB6V4 IO267PDB6V4 IO265PDB6V3 IO263PDB6V3 A dv a n c e v 0. 1 3 - 19 Package Pin Assignments 896-CCGA Pin Number RT3PE3000L Function T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 VCCIB6 VCC GND GND GND GND GND GND GND GND VCC VCCIB3 IO109NPB2V3 IO116NDB3V0 IO118NDB3V0 IO122NPB3V1 GCA1/IO114PPB3V0 GCB0/IO113NPB2V3 GCA2/IO115PPB3V0 VCCPLC IO121PDB3V0 IO268PDB6V4 IO264NDB6V3 IO264PDB6V3 IO258PDB6V3 IO258NDB6V3 IO257PPB6V2 IO261PPB6V3 IO265NDB6V3 IO263NDB6V3 VCCIB6 VCC GND GND GND GND 896-CCGA Pin Number RT3PE3000L Function U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 GND GND GND GND VCC VCCIB3 IO120PDB3V0 IO128PDB3V1 IO124PDB3V1 IO124NDB3V1 IO126PDB3V1 IO129PDB3V1 IO127PDB3V1 IO125PDB3V1 IO121NDB3V0 IO268NDB6V4 IO262PDB6V3 IO260PDB6V3 IO252PDB6V2 IO257NPB6V2 IO261NPB6V3 IO255PDB6V2 IO259PDB6V3 IO259NDB6V3 VCCIB6 VCC GND GND GND GND GND GND GND GND VCC VCCIB3 896-CCGA Pin Number RT3PE3000L Function V22 V23 V24 V25 V26 V27 V28 V29 V30 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 IO120NDB3V0 IO128NDB3V1 IO132PDB3V2 IO130PPB3V2 IO126NDB3V1 IO129NDB3V1 IO127NDB3V1 IO125NDB3V1 IO123PDB3V1 IO266NDB6V4 IO262NDB6V3 IO260NDB6V3 IO252NDB6V2 IO251NDB6V2 IO251PDB6V2 IO255NDB6V2 IO249PPB6V1 IO253PDB6V2 VCCIB6 VCC GND GND GND GND GND GND GND GND VCC VCCIB3 IO134PDB3V2 IO138PDB3V3 IO132NDB3V2 IO136NPB3V2 IO130NPB3V2 IO141PDB3V3 3 -2 0 A d v a n c e v 0. 1 Radiation-Tolerant ProASIC3 Packaging 896-CCGA Pin Number RT3PE3000L Function W28 W29 W30 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 IO135PDB3V2 IO131PDB3V2 IO123NDB3V1 IO266PDB6V4 IO250PDB6V2 IO250NDB6V2 IO246PDB6V1 IO247NDB6V1 IO247PDB6V1 IO249NPB6V1 IO245PDB6V1 IO253NDB6V2 GEB0/IO235NPB6V0 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC IO142PPB3V3 IO134NDB3V2 IO138NDB3V3 IO140NDB3V3 IO140PDB3V3 IO136PPB3V2 IO141NDB3V3 IO135NDB3V2 IO131NDB3V2 IO133PDB3V2 A dv a n c e v 0. 1 3 - 21 Package Pin Assignments Part Number and Revision Date Part Number 51700107-003-0 Revised September 2008 Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel’s products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. 3 -2 2 A d v a n c e v 0. 1 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. w w w. a c t e l . c o m Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Actel Europe Ltd. River Court,Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 9AB United Kingdom Phone +44 (0) 1276 609 300 Fax +44 (0) 1276 607 540 Actel Japan EXOS Ebisu Buillding 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 http://jp.actel.com Actel Hong Kong Room 2107, China Resources Building 26 Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 www.actel.com.cn 51700107-005-0/9.08