RT54SX72S-CQ256M

v2 . 2 ™ RTSX-S RadTolerant FPGAs Designed for Space • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case Geosynchronous Orbit Up to 100 krad (Si) Total Ionizing Dose (TID) – Parametric Performance Supported with LotSpecific Test Data Single-Event Latch-Up (SEL) Immunity TM1019.5 Test Data Available QML Certified Devices ue Features • • • Very Low Power Consumption (Up to 68 mW at Standby) 3.3V and 5V Mixed Voltage Configurable I/O Support for 3.3V/5V PCI, LVTTL, TTL, and CMOS – 5V Input Tolerance and 5V Drive Strength – Slow Slew Rate Option – Configurable Weak Resistor Pull-Up/Down for Tristated Outputs at Power-Up – Hot-Swap Compliant with Cold-Sparing Support Secure Programming Technology Prevents Reverse Engineering and Design Theft 100% Circuit Resource Utilization with 100% Pin Locking Unique In-System Diagnostic and Verification Capability with Silicon Explorer II Low-Cost Prototyping Option Deterministic, User-Controllable Timing JTAG Boundary Scan Testing in Compliance with IEEE Standard 1149.1 – Dedicated JTAG Reset (TRST) Pin • • • • • • • • • • High Performance • • • 230 MHz System Performance 310 MHz Internal Performance 9.5 ns Input Clock to Output Pad Specifications • • • • 0.25 µm Metal-to-Metal Antifuse Process 48,000 to 108,000 Available System Gates Up to 2,012 SEU-Hardened Flip-Flops Up to 360 User-Programmable I/O Pins Table 1 • RTSX-S Product Profile Device Capacity Typical Gates System Gates Logic Modules Combinatorial Cells SEU-Hardened Register Cells (Dedicated Flip-Flops) Maximum Flip-Flops Maximum User I/Os Clocks Quadrant Clocks Speed Grades Package (by pin count) CQFP CCGA CCLG RT54SX32S 32,000 48,000 2,880 1,800 1,080 1,980 227 3 0 Std., –1 208, 256 256 RT54SX72S 72,000 108,000 6,036 4,024 2,012 4,024 360 3 4 Std., –1 208, 256 624 November 2004 © 2004 Actel Corporation i See Actel’s website for the latest version of the datasheet RTSX-S RadTolerant FPGAs Ordering Information RT54SX72S 1 CQ 256 B Application (Temperature Range) B = MIL-STD-883 Class B E = E-Flow (Actel Space Level Flow) M = Military Temperature Package Lead Count Package Type CQ = Ceramic Quad Flat Pack CG = Ceramic Column Grid Aray CC = Ceramic Chip Carrier Land Grid Speed Grade Blank = Standard Speed 1 = Approximately 15% Faster than Standard Part Number RT54SX32S = 32,000 RadTolerant Typical Gates RT54SX72S = 72,000 RadTolerant Typical Gates Ceramic Device Resources User I/Os (including clock buffers) Device RT54SX32S RT54SX72S Note: The 256-Pin CCLG available in Mil-Temp only. CQFP 208-Pin 173 170 CQFP 256-Pin 227 212 CCLG 256-Pin 202 – CCGA 624-Pin – 360 Temperature Grade and Application Offering Package CQ208 CQ256 CC256 CG624 Note: M = Military Temperature B = MIL-STD-883 Class B E = E-Flow RT54SX32S B, E B, E M – RT54SX72S B, E B, E – B, E ii v2.2 RTSX-S RadTolerant FPGAs Speed Grade and Temperature/Application Matrix Std. M B E ✓ ✓ ✓ –1 ✓ ✓ ✓ QML Certification Actel has achieved full QML certification, demonstrating that quality management procedures, processes, and controls are in place and comply with MIL-PRF-38535 (the performance specification used by the U.S. Department of Defense for monolithic integrated circuits). Actel MIL-STD-883 Class B Product Flow Step 1. 2. 3. 4. 5. Internal Visual Temperature Cycling Constant Acceleration Particle Impact Noise Detection Seal a. Fine b. Gross Visual Inspection Pre-Burn-In Electrical Parameters Dynamic Burn-In Interim (Post-Burn-In) Electrical Parameters Percent Defective Allowable Final Electrical Test a. Static Tests (1)25°C (Subgroup 1, Table I) (2)–55°C and +125°C (Subgroups 2, 3, Table I) b. Functional Tests (1)25°C (Subgroup 7, Table I) (2)–55°C and +125°C (Subgroups 8A and 8B, Table I) c. Switching Tests at 25°C (Subgroup 9, Table I) 12. External Visual Screen 883 Method 2010, Test Condition B 1010, Test Condition C 2001, Test Condition B or D, Y1, Orientation Only 2020, Condition A 1014 100% 100% 2009 In accordance with applicable Actel device specification 1015, Condition D, 160 hours at 125°C or 80 hours at 150°C In accordance with applicable Actel device specification 5% In accordance with applicable Actel device specification, which includes a, b, and c: 100% 5005 5005 100% 5005 5005 100% 5005 2009 100% 100% 100% 100% 100% All Lots 883 Class B Requirement 100% 100% 100% 100% 6. 7. 8. 9. 10. 11. v2.2 iii RTSX-S RadTolerant FPGAs Actel Extended Flow1 Step 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Internal Visual Serialization Temperature Cycling Constant Acceleration Particle Impact Noise Detection Radiographic Pre-Burn-In Test Dynamic Burn-In Interim (Post-Burn-In) Electrical Parameters Static Burn-In Interim (Post-Burn-In) Electrical Parameters Percent Defective Allowable (PDA) Calculation Final Electrical Test a. Static Tests (1)25°C (Subgroup 1, Table1) (2)–55°C and +125°C (Subgroups 2, 3, Table 1) b. Functional Tests (1)25°C (Subgroup 7, Table 15) (2)–55°C and +125°C (Subgroups 8A and B, Table 1) c. Switching Tests at 25°C (Subgroup 9, Table 1) 15. Seal a. Fine b. Gross External Visual 1010, Condition C 2001, Condition B or D, Y1 Orientation Only 2020, Condition A 2012 (one view only) In accordance with applicable Actel device specification 1015, Condition D, 240 hours at 125°C or 120 hours at 150°C minimum In accordance with applicable Actel device specification 1015, Condition C, 72 hours at 150°C or 144 hours at 125°C minimum In accordance with applicable Actel device specification 5%, 3% Functional Parameters at 25°C In accordance with Actel applicable device specification which includes a, b, and c: 5005 5005 100% 5005 5005 100% 5005 1014 100% Screen Destructive In-Line Bond Pull 3 Method 2011, Condition D 2010, Condition A Requirement Sample 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% All Lots 100% 100% 16. Notes: 2009 100% 1. Actel offers Extended Flow for users requiring additional screening beyond MIL-STD-833, Class B requirement. Actel offers this Extended Flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S. The exceptions to Method 5004 are shown in notes 2 and 4 below. 2. MIL-STD-883, Method 5004, requires a 100 percent radiation latch-up testing to Method 1020. Actel will NOT perform any radiation testing, and this requirement must be waived in its entirety. 3. Method 5004 requires a 100 percent, nondestructive bond-pull to Method 2003. Actel substitutes a destructive bond-pull to Method 2011 Condition D on a sample basis only. 4. Wafer lot acceptance complies to commercial standards only (requirement per Method 5007 is not performed). iv v2.2 RTSX-S RadTolerant FPGAs Table of Contents General Description Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Programmable Interconnect Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Low-Cost Prototyping Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 In-System Diagnostic and Debug Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Radiation Survivability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Detailed Specification General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Routing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 Package Pin Assignments 208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 256-Pin CCLG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 624-Pin CCGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 v 2.2 v RTSX-S RadTolerant FPGAs General Description RTSX-S RadTolerant FPGAs are enhanced versions of Actel’s SX-A family of devices, specifically designed for enhanced radiation performance. Featuring SEU-hardened D-type flip-flops that offer the benefits of Triple Module Redundancy (TMR) without the associated overhead, the RTSX-S family is a unique product offering for space applications. Manufactured using 0.25 µm technology at the Matsushita (MEC) facility in Japan, RTSX-S offers levels of radiation survivability far in excess of typical CMOS devices. found in traditional FPGAs. In a sea-of-modules architecture, the entire floor of the FPGA is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. The RTSX-S architecture adds several enhancements over the SX-A architecture to improve its performance in radiation environments, such as SEU-hardened flip-flops, wider clock lines, and stronger clock drivers. Device Architecture Actel's RTSX-S architecture, derived from the highly successful SX-A sea-of-modules architecture, has been designed to improve upset and total-dose performance in radiation environments. With three layers of metal interconnect in the RT54SX32S and four metal layers in RT54SX72S, the RTSX-S family provides efficient use of silicon by locating the routing interconnect resources between the top two metal layers. This completely eliminates the channels of routing and interconnect resources between logic modules as Programmable Interconnect Element Interconnection between logic modules is achieved using Actel’s patented metal-to-metal programmable antifuse interconnect elements. The antifuses are normally open circuit and form a permanent, low-impedance connection when programmed. The metal-to-metal antifuse is made up of a combination of amorphous silicon and dielectric material with barrier metals and has a programmed (“on” state) resistance of 25 Ω with capacitance of 1.0 fF for low signal impedance (Figure 1-1). Routing Tracks Amorphous Silicon/ Dielectric Antifuse Metal 4 Tungsten Plug Via Metal 3 Tungsten Plug Via Metal 2 Metal 1 Tungsten Plug Contact Silicon Substrate Figure 1-1 • RTSX-S Family Interconnect Elements v2.2 1-1 RTSX-S RadTolerant FPGAs These antifuse interconnects reside between the top two layers of metal and thereby enable the sea-of-modules architecture in an FPGA. The extremely small size of these interconnect elements gives the RTSX-S family abundant routing resources and provides excellent protection against design theft. Reverse engineering is virtually impossible because it is extremely difficult to distinguish between programmed and unprogrammed antifuses. Additionally, since RTSX-S is a nonvolatile, single-chip solution, there is no configuration bitstream to intercept. The RTSX-S interconnect (i.e., the antifuses and metal tracks) also has lower capacitance and resistance than that of any other device of similar capacity, leading to the fastest signal propagation in the industry for the radiation tolerance offered. integrate a three-input exclusive-OR function into a single C-cell. This facilitates the construction of nine-bit parity-tree functions. At the same time, the C-cell structure is extremely synthesis-friendly, simplifying the overall design and reducing synthesis time. The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines) control signals. The R-cell registers feature programmable clock polarity, selectable on a register-by-register basis. This provides additional flexibility during mapping of synthesized functions into the RTSX-S FPGA. The clock source for the R-cell can be chosen from the hardwired clock, the routed clocks, or the internal logic. While each SEU-hardened R-cell appears as a single Dtype flip-flop to the user, each is implemented employing triple redundancy to achieve a LET threshold of greater than 40 MeV-cm2/mg. Each TMR R-cell consists of three master-slave latch pairs, each with asynchronous, selfcorrecting feedback paths. The output of each latch on the master or slave side is voted with the outputs of the other two latches on that side. If one of the three latches is struck by an ion and starts to change state, the voting with the other two latches prevents the change from feeding back and permanently latching. Care was taken in the layout to ensure that a single ion strike could not affect more than one latch (see "R-Cell" section on page 2-23 for more details). Actel has arranged all C-cell and R-cell logic modules into horizontal banks called Clusters. There are two types of clusters: Type 1 contains two C-cells and one R-cell, while Type 2 contains one C-cell and two R-cells. To increase design efficiency and device performance, Actel has further organized these modules into SuperClusters. SuperCluster 1 is a two-wide grouping of Type 1 clusters. SuperCluster 2 is a two-wide group containing one Type 1 cluster and one Type 2 cluster. RTSX-S devices feature more SuperCluster 1 modules than SuperCluster 2 modules because designers typically require significantly more combinatorial logic than flipflops (Figure 1-2 on page 1-3). I/O Structure The RTSX-S family features a flexible I/O structure that supports 3.3V LVTTL, 5V TTL, 5V CMOS, and 3.3V and 5V PCI. All I/O standards are hot-swap compliant, coldsparing capable, and 5V tolerant (except for 3.3V PCI). In addition, each I/O on an RTSX-S device can be configured as an input, an output, a tristate output, or a bidirectional pin. Mixed I/O standards are allowed and can be set on a pin-by-pin basis. High or low slew rate can be set on individual output buffers (except for PCI, which defaults to high slew), as well as the power-up configuration (either pull-up or pull-down). Even without the inclusion of dedicated I/O registers, these I/Os, in combination with array registers, can achieve clock-to-output-pad timing as fast as 9.5 ns. In most FPGAs, I/O cells that have embedded latches and flip-flops require instantiation in HDL code; this is a design complication not encountered in RTSX-S FPGAs. Fast pin-to-pin timing ensures that the device will have little trouble interfacing with any other device in the system, which in turn, enables parallel design of system components and reduces overall design time. Logic Modules Actel’s RTSX-S family provides two types of logic modules to the designer (Figure 1-2 on page 1-3): the register cell (R-cell) and the combinatorial cell (C-cell). The C-cell implements a range of combinatorial functions with up to 5 inputs. Inclusion of the DB input and its associated inverter function dramatically increases the number of combinatorial functions that can be implemented in a single module from 800 options (as in previous architectures) to more than 4,000 in the RTSX-S architecture. An example of the improved flexibility enabled by the inversion capability is the ability to Routing R-cells and C-cells within Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within Clusters and SuperClusters. This routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance (Figure 1-3 on page 1-4 and Figure 1-4 on page 1-4). 1 -2 v2.2 RTSX-S RadTolerant FPGAs DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring R-cell in a given SuperCluster. DirectConnect uses a hardwired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns. FastConnect enables horizontal routing between any two logic modules within a given SuperCluster and vertical routing with the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering a maximum interconnect propagation delay of 0.4 ns. In addition to DirectConnect and FastConnect, the architecture makes use of two globally-oriented routing resources known as segmented routing and high-drive routing. Actel’s segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the 100-percent-automatic place-and-route software to minimize signal propagation delays. R-Cell Routed Data Input S1 S0 PRE Direct Connect Input HCLK CLKA, CLKB, Internal Logic D Q Y D2 D3 D0 D1 C-Cell Y Sa Sb CLR DB CKS CKP A0 B0 A1 B1 Cluster 1 Cluster 1 Cluster 2 Cluster 1 Type 1 SuperCluster Figure 1-2 • R-Cell, C-Cell, and Cluster Organization Type 2 SuperCluster v2.2 1-3 RTSX-S RadTolerant FPGAs DirectConnect • No antifuses for smallest routing delay FastConnect • One antifuse Routing Segments • Typically 2 antifuses • Max. 5 antifuses Type 1 SuperClusters Figure 1-3 • DirectConnect and FastConnect for SuperCluster 1s DirectConnect • No antifuses for smallest routing delay FastConnect • One antifuse Routing Segments • Typically 2 antifuses • Max. 5 antifuses Type 2 SuperClusters Figure 1-4 • DirectConnect and FastConnect for SuperCluster 2s 1 -4 v2.2 RTSX-S RadTolerant FPGAs Global Resources Actel’s high-drive routing structure provides three clock networks: hardwired clocks (HCLK), routed clocks (CLKA, CLKB), and quadrant clocks (QCLKA, QCLKB, QCLKC, QCLKD). Table 1-1 • RTSX-S Global Resources RT54SX32S Routed Clocks (CLKA, CLKB) Hardwired Clocks (HCLK) Quadrant Clocks (QCLKA, QCLKB, QCLKC, QCLKD) 2 1 0 RT54SX72S 2 1 4 The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select MUX in each R-cell. HCLK cannot be connected to combinational logic. This provides a fast propagation path for the clock signal, enabling the 9.5 ns clock-to-out (pad-to-pad) performance of the RTSX-S devices. The second type of clock, routed clocks, (CLKA, CLKB) are global clocks that can be sourced from either external pins or internal logic signals within the device. CLKA and CLKB may be connected to sequential cells (R-cells) or to combinational logic (C-cells). The last type of clock, quadrant clocks, are only found in the RT54SX72S. Similar to the routed clocks, the four quadrant clocks (QCLKA, QCLKB, QCLKC, QCLKD) can be sourced from external pins or from internal logic signals within the device. Each of these clocks can individually drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. Actel's Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes timing-driven place-and-route, and a world-class integrated static timing analyzer and constraints editor. With the Designer software, a user can select and lock package pins while only minimally impacting the results of place-and-route. Additionally, the back-annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Actel’s integrated verification and logic analysis tool. Another tool included in the Designer software is the ACTgen macro builder, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from companies such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. Programming Programming support is provided through Actel's Silicon Sculptor II, a single-site programmer driven via a PCbased GUI. Factory programming is available as well. Low-Cost Prototyping Solution Since the enhanced radiation characteristics of radiationtolerant devices are not required during the prototyping phase of the design, Actel has developed a prototyping solution for RTSX-S that utilizes commercial SX-A devices. The prototyping solution consists of two parts: • A well-documented design flow that allows the customer to target an RTSX-S design to the equivalent commercial SX-A device Either footprint-compatible packages or protoyping sockets to adapt commercial SX-A packages to the RTAX-S package footprints Design Environment The RTSX-S family of FPGAs is fully supported by both Actel's Libero™ Integrated Design Environment (IDE) and Designer FPGA Development software. Actel Libero IDE is a design management environment, seamlessly integrating design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. Libero IDE includes Synplify® for Actel from Synplicity®, ViewDraw for Actel from Mentor Graphics, ModelSim™ HDL Simulator from Mentor Graphics®, WaveFormer Lite™ from SynaptiCAD™, and Designer software from Actel. Refer to the Libero IDE flow (located on Actel’s website) diagram for more information. • This methodology provides the user with a cost-effective solution while maintaining the short time-to-market associated with Actel FPGAs. Please see the application note Prototyping for the RTSX-S Enhanced Aerospace FPGA for more details v2.2 1-5 RTSX-S RadTolerant FPGAs In-System Diagnostic and Debug Capabilities The RTXS-S family of FPGAs includes internal probe circuitry, allowing the designer to dynamically observe and analyze any signal inside the FPGA without disturbing normal device operation. Two individual signals can be brought out to two multipurpose pins (PRA and PRB) on the device. The probe circuitry is accessed and controlled via Silicon Explorer II, Actel's integrated verification and logic analysis tool, which attaches to the serial port of a PC and communicates with the FPGA via the JTAG port. Additional Channels 16 RTSX-S FPGA TDI TCK TMS Serial Connection Silicon Explorer II TDO PRA PRB Figure 1-5 • Probe Setup Radiation Survivability The RTSX-S RadTolerant devices have varying total-dose radiation survivability. The ability of these devices to survive radiation effects is both device and lot dependent. Total-dose results are summarized in two ways. The first summary is indicated by the maximum total-dose level achieved before the device fails to meet an individual performance specification but remains functional. For Actel FPGAs, the parameter that first exceeds the specification is ICC (standby supply current). The second summary is indicated by the maximum total dose achieved prior to the functional failure of the device. Actel provides total-dose radiation test data on each lot. Reports are available on Actel’s website or from Actel’s local sales representatives. Listings of available lots and devices can also be provided. For a radiation performance summary, see Radiation Data. This summary also shows single-event upset (SEU) and single-event latch-up (SEL) testing that has been performed on Actel FPGAs. All radiation performance information is provided for informational purposes only and is not guaranteed. Total dose effects are lot-dependent, and Actel does not guarantee that future devices will continue to exhibit similar radiation characteristics. In addition, actual performance can vary widely due to a variety of factors, including but not limited to, characteristics of the orbit, radiation environment, proximity to the satellite exterior, the amount of inherent shielding from other sources within the satellite, and actual bare die variations. For these reasons, it is the sole responsibility of the user to determine whether the device will meet the requirements of the specific design. Summary The RTSX-S family of RadTolerant FPGAs extends Actel’s highly successful offering of FPGAs for radiation environments with the industry’s first FPGA designed specifically for enhanced radiation performance. 1 -6 v2.2 RTSX-S RadTolerant FPGAs Related Documents Application Notes Simultaneous Switching Noise and Signal Integrity http://www.actel.com/documents/SSN_AN.pdf Implementation of Security in Actel Antifuse FPGAs http://www.actel.com/documents/Antifuse_Security_AN.pdf Using A54SX72A and RT54SX72S Quadrant Clocks http://www.actel.com/documents/QCLK_AN.pdf Actel eX, SX-A and RTSX-S I/Os http://www.actel.com/documents/AntifuseIO_AN.pdf IEEE Standard 1149.1 (JTAG) in the SX/RTSX/SX-A/eX/RT54SX-S Families http://www.actel.com/documents/SX_SXAJTAG_AN.pdf Prototyping for the RT54SX-S Enhanced Aerospace FPGA http://www.actel.com/documents/RTSXS_Proto_AN.pdf Actel CQFP to FBGA Adapter Socket Instructions http://www.actel.com/documents/CQ352-FPGA_Adapter_AN.pdf Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications http://www.actel.com/documents/HotSwapColdSparing_AN.pdf User’s Guides and Manuals Antifuse Macro Library Guide http://www.actel.com/documents/libguide.pdf ACTgen Macros User’s Guide http://www.actel.com/documents/genguide.pdf Libero IDE v5.2 User's Guide http://www.actel.com/documents/liberoUG.pdf Silicon Sculptor II User’s Guide http://www.actel.com/techdocs/manuals/default.asp White Papers Design Security in Nonvolatile Flash and Antifuse FPGAs http://www.actel.com/documents/DesignSecurity_WP.pdf Understanding Actel Antifuse Device Security http://www.actel.com/documents/AntifuseSecurityWP.pdf v2.2 1-7 RTSX-S RadTolerant FPGAs Detailed Specifications General Conditions Table 2-1 • Supply Voltages VCCA 2.5V 2.5V Note: *3.3V PCI is not 5V tolerant Table 2-2 • Characteristics for All I/O Configurations I/O Standard TTL, LVTTL 3.3V PCI 5V PCI Hot Swappable Yes No Yes Slew Rate Control Yes. Affects falling edge outputs only No. High slew rate only No. High slew rate only Power up Resistor Pull Pull-up or Pull-down Pull-up or Pull-down Pull-up or Pull-down VCCI 3.3V 5V Maximum Input Tolerance 5V* 5V Maximum Output Drive 3.3V 5V Table 2-3 • Time at which I/Os Become Active by Ramp Rate (At room temperature and nominal operating conditions) Ramp Rate Units RT54SX32S RT54SX72S 0.25V/ms ms 10 10 0.025V/ms ms 100 100 5V/ms ms 0.46 0.41 2.5V/ms ms 0.74 0.67 0.5V/ms ms 2.8 2.6 0.25V/ms ms 5.2 5.0 0.1V/ms ms 12.1 12.1 0.025V/ms ms 47.2 47.2 Power-Up and Power-Cycling The RTSX-S family does not require any specific initial power-up sequence. However, if the power-up/down happens periodically (power-cycling) with an improper power sequence profile and not enough delay between the cycles, an in-rush current appears on ICCI under specific conditions. Therefore, if an application requires periodic power-cycling of the device, the following power sequence profile is recommended: 1. Power-up VCCA to at least 0.7V before powering-up VCCI 2. If it is impossible to power-up VCCA before VCCI, ensure that a suitable period of time is allowed between VCCA and VCCI power-down and subsequent power-up The in-rush current phenomenon does not impact the long-term reliability of the device. Please see the application note Power Cycling of RTSX-S Devices for more details. v2.2 2-1 RTSX-S RadTolerant FPGAs Operating Conditions Absolute Maximum Conditions Stresses beyond those listed in Table 2-4 may cause permanent damage to the device. Exposure to absolute maximum rated conditions may affect device reliability. Devices should not be operated outside the recommendations in Table 2-5. Table 2-4 • Absolute Maximum Conditions Symbol VCCI VCCA VI VI TSTG Parameter DC Supply Voltage DC Supply Voltage Input Voltage Input Voltage for Bidirectional I/Os when using 3.3V PCI Storage Temperature Limits –0.3 to +6.0 –0.3 to +3.0 –0.5 to + 6.0 –0.5 to +VCCI + 0.5 –65 to +150 Units V V V V °C Table 2-5 • Recommended Operating Conditions Parameter Temperature Range (case temperature) 2.5V Power Supply Tolerance 3.3V Power Supply Tolerance 5V Power Supply Tolerance Military –55 to +125 2.25 to 2.75 3.0 to 3.6 4.5 to 5.5 Units °C V V V Power Dissipation A critical element of system reliability is the ability of electronic devices to safely dissipate the heat generated during operation. The thermal characteristics of a circuit depend on the device and package used, the operating temperature, the operating current, and the system's ability to dissipate heat. A complete power evaluation should be performed early in the design process to help identify potential heatrelated problems in the system and to prevent the system from exceeding the device’s maximum allowed junction temperature. The actual power dissipated by most applications is significantly lower than the power the package can dissipate. However, a thermal analysis should be performed for all projects. To perform a power evaluation, follow these steps: 1. Estimate the power consumption of the application. 2. Calculate the maximum power allowed for the device and package. 3. Compare the estimated power and maximum power values. Estimating Power Dissipation The total power dissipation for the RTSX-S family is the sum of the DC power dissipation and the AC power dissipation: PTotal = PDC + PAC EQ 2-1 DC Power Dissipation The power due to standby current is typically a small component of the overall power. The DC power dissipation is defined as: PDC = (ICC)*VCCA + (ICC)*VCCI EQ 2-2 2 -2 v2.2 RTSX-S RadTolerant FPGAs AC Power Dissipation The power dissipation of the RTSX-S family is usually dominated by the dynamic power dissipation. Dynamic power dissipation is a function of frequency, equivalent capacitance, and power supply voltage. The AC power dissipation is defined as follows: PAC = PC-Cells + PR-Cells + PCLKA + PCLKB + PHCLK + POutput Buffer + PInput Buffer EQ 2-3 or: PAC = VCCA2 * [(m * CEQCM * fm)C-Cells + (m * CEQSM * fm)R-Cells + (n * CEQI * fn)Input Buffer + (p * (CEQO + CL) * fp)Output Buffer + (0.5 * (q1 * CEQCR * fq1) + (r1 * fq1))CLKA + (0.5 * (q2 * CEQCR * fq2)+ (r2 * fq2))CLKB + (0.5 * (s1 * CEQHV * fs1) + (CEQHF * fs1))HCLK] EQ 2-4 Where: CEQCM = Equivalent capacitance of combinatorial modules (C-Cells) in pF CEQSM = Equivalent capacitance of sequential modules (R-Cells) in pF CEQI = Equivalent capacitance of input buffers in pF CEQO = Equivalent capacitance of output buffers in pF CEQCR = Equivalent capacitance of CLKA/B in pF CEQHV = Variable capacitance of HCLK in pF CEQHF = Fixed capacitance of HCLK in pF CL = Output lead capacitance in pF fm = Average logic module switching rate in MHz fn = Average input buffer switching rate in MHz fp = Average output buffer switching rate in MHz fq1 = Average CLKA rate in MHz fq2 = Average CLKB rate in MHz fs1 = Average HCLK rate in MHz m = Number of logic modules switching at fm n = Number of input buffers switching at fn p = Number of output buffers switching at fp q1 = Number of clock loads on CLKA q2 = Number of clock loads on CLKB r1 = Fixed capacitance due to CLKA r2 = Fixed capacitance due to CLKB s1 = Number of clock loads on HCLK x = Number of I/Os at logic low y = Number of I/Os at logic high Table 2-6 • Fixed Power Parameters Parameter CEQCM CEQSM CEQI CEQO CEQCR CEQHV CEQHF r1 r2 ICC RT54SX32S 3.00 3.00 1.40 7.40 3.50 4.30 300 100 100 25 RT54SX72S 3.00 3.00 1.30 7.40 3.50 4.30 690 245 245 25 Units pF pF pF pF pF pF pF pF pF mA Guidelines for Estimating Power The following guidelines are meant to represent worstcase scenarios; they can be generally used to predict the upper limits of power dissipation: Logic Modules (m) = 20% of modules Inputs Switching (n) = # inputs/4 Outputs Switching (p) = # output/4 CLKA Loads (q1) = 20% of R-cells CLKB Loads (q2) = 20% of R-cells Load Capacitance (CL) = 35 pF Average Logic Module Switching Rate (fm) = f/10 Average Input Switching Rate (fn) =f/5 Average Output Switching Rate (fp) = f/10 Average CLKA Rate (fq1) = f/2 Average CLKB Rate (fq2) = f/2 Average HCLK Rate (fs1) = f HCLK loads (s1) = 20% of R-cells To assist customers in estimating the power dissipations of their designs, Actel has published the eX, SX-A and RT54SX-S Power Calculator worksheet. v2.2 2-3 RTSX-S RadTolerant FPGAs Thermal Characteristics Introduction The temperature variable in Actel’s Designer software refers to the junction temperature, not the ambient, case, or board temperatures. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient, case, or board temperatures. EQ 2-5, EQ 26, and EQ 2-7 give the relationship between thermal resistance, temperature gradient and power. θ ja θ jc Tj – Ta = ---------------P EQ 2-5 Tj – Tc = ---------------P EQ 2-6 Tj – Tb θ jb = ---------------P EQ 2-7 Where: θja = Junction-to-air thermal resistance of the package. θja numbers are located in Table 2-7. θjc = Junction-to-case thermal resistance of the package. θjc numbers are located in Table 2-7. θjb = Junction-to-board thermal resistance of the package. θjb for a 624-pin CCGA is located in the notes for Table 2-7. Tj Ta Tb Tc P = Junction Temperature = Ambient Temperature = Board Temperature = Case Temperature = Power Package Thermal Characteristics The device thermal characteristics θjc and θja are given in Table 2-7. The thermal characteristics for θja are shown with two different air flow rates. Note that the absolute maximum junction temperature is 150°C. Table 2-7 • Package Thermal Characteristics θja Package Type Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) with heatsink Ceramic Quad Flat Pack (CQFP) with heatsink Ceramic Chip Carrier Land Grid (CCLG) Ceramic Column Grid Array (CCGA) Notes: 1. θjc for CQFP and CCLG packages refers to the thermal resistance between the junction and the bottom of the package. 2. θjc for the CCGA 624 refers to the thermal resistance between the junction and the top surface of the package. Thermal resistance from junction to board (θjb) for CG624 package is 3.4 °C/W. Pin Count 208 256 208 256 256 624 θjc 2.0 1 2.0 0.5 0.5 1 1 1 Still Air 22 20 21.0 19.0 12.1 8.9 θja 1.0m/s 19.8 16.5 17.3 15.7 10.0 8.5 θja 2.5m/s 18.0 15.0 15.7 14.2 9.1 8.0 Units °C/W °C/W °C/W °C/W °C/W °C/W 1.1 1 6.5 2 Maximum Allowed Power Dissipation Shown below are example calculations to estimate the maximum allowed power dissipation for a given device based on two different thermal environments while maintaining the device junction temperature at or below worst-case military operating conditions (125°C). Example 1: This example assumes that there is still air in the environment. The heat flow is shown by the arrows in Figure 2-1 on page 2-5. The maximum ambient air temperature is assumed to be 50°C. The device package used is the 624-pin CCGA. Max. Allowed Power = Max Junction Temp – Max. Ambient Temp = 125 ° C – 50 ° C = 8.43W ----------------------------------------------------------------------------------------------------------------------------------------θ ja 8.9 ° C/W 2 -4 v2.2 RTSX-S RadTolerant FPGAs Air Solder Columns PCB Figure 2-1 • Hear Flow When Air is Present Example 2: This example assumes that the primary heat conduction path will be through the bottom of the package (neglecting the heat conducted through the package pins) to the board for a package mounted with thermal paste. The heat flow is shown by the arrows in Figure 2-2. The maximum board temperature is assumed to be 70°C. The device package used is the 352-pin CQFP. The thermal resistance (θcb) of the thermal paste is assumed to be 0.58 °C/W. Tj – Tb Tj – Tb 125 ° C – 70 ° C Max. Allowed Power = ---------------- = -------------------- = ----------------------------------------------------- = 21.32W θ jb θ jc + θ cb 2.0 ° C/W + 0.58 ° C/W Thermal Adhesive PCB Figure 2-2 • Heat Flow in a Vacuum Timing Derating RTSX-S devices are manufactured in a CMOS process; therefore, device performance is dependent on temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. The derating factors shown in Table 2-8 should be applied to all timing data contained within this datasheet. Table 2-8 • Temperature and Voltage Derating Factors (Normalized to Worst-Case Military Conditions, TJ = 125°C, VCCA = 2.25V) Junction Temperature (Tj) VCCA 2.25 2.50 2.75 –55°C 0.71 0.67 0.62 –40°C 0.72 0.67 0.63 0°C 0.78 0.73 0.69 25°C 0.80 0.75 0.70 70°C 0.90 0.84 0.79 85°C 0.94 0.87 0.82 125°C 1.00 0.93 0.88 Note: The user can set the junction temperature in Actel’s Designer software to be any integer value in the range of –55°C to 175°C, and the core voltage to be any value between 2.25V and 2.75V. v2.2 2-5 RTSX-S RadTolerant FPGAs Timing Model Input Delays Internal Delays Combinatorial Cell Predicted Routing Delays Output Delays I/O Module t INYH = 0.7 ns t RD1 = 0.8 ns t RD2 = 1.0 ns I/O Module t PD = 1.2 ns t RD1 = 0.8 ns t RD4 = 1.5 ns t RD8 = 2.9 ns I/O Module t DHL = 3.8 ns t DHL = 3.8 ns Register Cell t SUD = 0.8 ns t HD = 0.0 ns Routed Clock D Q t RD1 = 0.8 ns t ENZL= 2.5 ns t RCKH = 5.3 ns (100% Load) t RCO= 1.0 ns Register Cell I/O Module t DHL = 3.8 ns I/O Module t INYH = 0.7 ns t SUD = 0.8 ns t HD = 0.0 ns Hardwired Clock D Q t RD1 = 0.8 ns t ENZL= 2.5 ns t HCKH = 3.9 ns t RCO= 1.0 ns Figure 2-3 • RTSX-S Timing Model Values shown for RT54SX32S, –1, 0 krad (Si), 5V TTL worst-case military conditions Hardwired Clock External Setup = (tINYH + tRD2 + tSUD) – tHCKH = 0.7 + 1.0 + 0.8 – 3.9 = –1.4 ns Clock-to-Out (Pad-to-Pad) = tHCKH + tRCO + tRD1 + tDHL = 3.9 + 1.0 + 0.8 + 3.8 = 9.5 ns Routed Clock External Setup = (tINYH + tRD2 + tSUD) – tRCKH = 0.7 + 1.0 + 0.8– 5.3= –2.8 ns Clock-to-Out (Pad-to-Pad) = tRCKH + tRCO + tRD1 + tDHL = 5.3+ 1.0 + 0.8 + 3.8 = 10.9 ns 2 -6 v2.2 RTSX-S RadTolerant FPGAs I/O Specifications Pin Descriptions Supply Pins GND Ground JTAG/Probe Pins PRA/PRB1 I/O, Probe A/B Low supply voltage. VCCI Supply Voltage Supply voltage for I/Os. See Table 2-1 on page 2-1. VCCA Supply Voltage Supply voltage for Array. See Table 2-1 on page 2-1. The probe pin is used to output data from any userdefined design node within the device. This independent diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of any signal path within the device. The probe pin can be used as a user-defined I/O when verification has been completed. The pin’s probe capabilities can be permanently disabled to protect programmed design confidentiality. TCK1, I/O Test Clock Global Pins CLKA/B Routed Clock A and B These pins are clock inputs for clock distribution networks. Input levels are compatible with standard TTL, LVTTL, 3.3V PCI, or 5V PCI specifications. The clock input is buffered prior to clocking the R-cells. When not used, this pin must be set Low or High on the board. When used, this pin should be held Low or High during powerup to avoid unwanted static power. For RT54SX72S, these pins can be configured as user I/Os. When used, this pin offers a built-in programmable pullup or pull-down resistor active during power-up only. QCLKA/B/C/D Quadrant Clock A, B, C, and D / I/O Test clock input for diagnostic probe and device programming. In flexible mode, TCK becomes active when the TMS pin is set Low (Table 2-32 on page 2-35). This pin functions as an I/O when the boundary scan state machine reaches the “logic reset” state. TDI1, I/O Test Data Input Serial input for boundary scan testing and diagnostic probe. In flexible mode, TDI is active when the TMS pin is set Low (Table 2-32 on page 2-35). This pin functions as an I/O when the boundary scan state machine reaches the “logic reset” state. TDO1, I/O Test Data Output These four pins are the quadrant clock inputs and are only found on the RT54SX72S. They are clock inputs for clock distribution networks. Input levels are compatible with standard TTL, LVTTL, 3.3V PCI or 5V PCI specifications. Each of these clock inputs can drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. The clock input is buffered prior to clocking the core cells. These pins can be configured as user I/Os. When not used, these pins must not be left floating. They must be set Low or High on the board. When used, this pin offers a built-in programmable pull-up or pull-down resistor, active during power-up only. HCLK Dedicated (Hardwired) Array Clock Serial output for boundary scan testing. In flexible mode, TDO is active when the TMS pin is set Low (Table 2-32 on page 2-35). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. When Silicon Explorer II is being used, TDO will act as an output when the "checksum" command is run. It will return to user I/O when "checksum" is complete. TMS1 Test Mode Select This pin is the clock input for sequential modules. Input levels are compatible with standard TTL, LVTTL, 3.3V PCI or 5V PCI specifications. This input is buffered prior to clocking the R-cells. It offers clock speeds independent of the number of R-cells being driven. When not used, this pin must not be left floating. It must be set to Low or High on the board. When used, this pin should be held Low or High during power-up to avoid unwanted static power. The TMS pin controls the use of the IEEE 1149.1 boundary scan pins (TCK, TDI, TDO, TRST). In flexible mode when the TMS pin is set Low, the TCK, TDI, and TDO pins are boundary scan pins (Table 2-32 on page 235). Once the boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the “logic reset” state. At this point, the boundary scan pins will be released and will function as regular I/O pins. The “logic reset” state is reached five TCK cycles after the TMS pin is set High. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications. 1. These pins should be terminated with a 70 Ω resistor to preserve probing capabilities. v2.2 2-7 RTSX-S RadTolerant FPGAs TRST Boundary Scan Reset Pin Hot Swapping RTSX-S I/Os can be configured to be hot swappable in compliance with the Compact PCI Specification. However, a 3.3V PCI device is not hot swappable. During power-up/down, all I/Os are tristated. VCCA and VCCI do not have to be stable during power-up/down. After the RTSX-S device is plugged into an electrically active system, the device will not degrade the reliability of or cause damage to the host system. The device’s output pins are driven to a high impedance state until normal chip operating conditions are reached. Table 2-3 on page 2-1 summarizes the VCCA voltage at which the I/Os behave according to the user’s design for an RTSX-S device at room temperature for various ramp-up rates. The data reported assumes a linear ramp-up profile to 2.5V. Refer to Actel’s application note, SX-A and RTSX-S Devices in Hot-Swap and Cold-Sparing Applications for more information on hot swapping. The TRST pin functions as an active-low input to asynchronously initialize or rest the boundary scan circuit. The TRST pin is equipped with an internal pull-up resistor. For flight applications, the TRST pin should be hardwired to GND. User I/O I/O Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output levels are compatible with standard TTL, LVTTL, 3.3V/5V PCI, or 5V CMOS specifications. Unused I/O pins are automatically tristated by the Designer software. See "User I/O" section on page 2-8 for more details. Special Functions NC No Connection This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. Customizing the I/O Each user I/O on an RTSX-S device can be configured as an input, an output, a tristate output, or a bidirectional pin. Mixed I/O standards are allowed and can be set on a pin-by-pin basis. High or low slew rates can be set on individual output buffers (except for PCI which defaults to high slew), as well as the power-up configuration (either pull-up or pull-down). The user selects the desired I/O by setting the I/O properties in PinEditor, Actel’s graphical pin-placement and I/O properties editor. See PinEditor online help for more information. User I/O The RTSX-S family features a flexible I/O structure that supports 3.3V LVTTL, 5V TTL, 5V CMOS, and 3.3V and 5V PCI. All I/O standards are hot-swap compliant, coldsparing capable, and 5V tolerant (except for 3.3V PCI). Each I/O module has an available power-up resistor of approximately 50 kΩ that can configure the I/O to a known state during power-up. Just slightly before VCCA reaches 2.5V, the resistors are disabled so the I/Os will behave normally. For more information about the power-up resistors, please see Actel’s application note SX-A and RTSX-S Devices in Hot-Swap and Cold Sparing Applications. RTSX-S inputs should be driven by high-speed push-pull devices with a low-resistance pull-up device. If the input voltage is greater than VCCI and a fast push-pull device is NOT used, the high-resistance pull-up of the driver and the internal circuitry of the RTSX-S I/O may create a voltage divider (when a user I/O is configured as an input, the associated output buffer is tristated). This voltage divider could pull the input voltage below specification for some devices connected to the driver. A logic ‘1’ may not be correctly presented in this case. For example, if an open drain driver is used with a pull-up resistor to 5V to provide the logic ‘1’ input, and VCCI is set to 3.3V on the RTSX-S device, the input signal may be pulled down by the RTSX-S input. Unused I/Os All unused user I/Os are automatically tristated by Actel’s Designer software. Although termination is not required, it is recommended that the user tie off all unused I/Os to GND externally. If the I/O clamp diode is disabled, then unused I/Os are 5V tolerant, otherwise unused I/Os are tolerant to VCCI. 2 -8 v2.2 RTSX-S RadTolerant FPGAs I/O Macros There are nine I/O macros available to the user for RTSX-S: • • • CLKBUF/CLKBUFI: Clock Buffer, noninverting and inverting CLKBIBUF/CLKBIBUFI: Bidirectional Clock Buffer, noninverting and inverting QCLKBUF/QCLKBUFI: Quadrant noninverting and inverting Clock Buffer, • • • • • • Table 2-9 • User I/O Features Function Input Buffer Threshold Selections Flexible Output Driver • • • • • Output Buffer • • 5V: CMOS, PCI, TTL 3.3V: PCI, LVTTL 5V: CMOS, PCI, TTL 3.3V: PCI, LVTTL Selectable on an individual I/O basis I/Os on an unpowered device does not sink the current (Power supplies are at 0V) Can be used for “cold sparing” Description QCLKBIBUF/QCLKBIBUFI: Quad Bidirectional Clock Buffer, noninverting and inverting HCLKBUF: Hardwired Clock Buffer INBUF: Input Buffer OUTBUF: Output Buffer TRIBUF: Tristate Buffer BIBUF: Bidirectional Buffer “Hot-Swap” Capability Individually selectable slew rate, high or low slew (The default is high slew rate). The slew rate selection only affects the falling edge of an output. There is no change on the rising edge of the output or any inputs. Power-Up Individually selectable pull-ups and pull-downs during power-up (default is to power-up in tristate mode) Enables deterministic power-up of a device VCCA and VCCI can be powered in any order v2.2 2-9 RTSX-S RadTolerant FPGAs I/O Module Timing Characteristics E D TRIBUFF PAD To AC test loads (shown below) VCC D Pad V OL t DLH 50% 50% VOH VMEAS VCC GND VMEAS VCC 50% GND 10% t ENLZ E VPad GND tENZH 50% 50% VOH VMEAS E Pad 50% VCC GND 90% t EN HZ VMEAS VOL tDHL t ENZ L Figure 2-4 • Output Timing Model and Waveforms VCCI Pad PAD INBUF Y Y GND VMEAS VMEAS 0V 50% tINYL VCC 50% tINYH Figure 2-5 • Input Timing Model and Waveforms Load 1 (Used to measure propagation delay) To the output under test 35 pF Load 2 (Used to measure enable delays) VCC GND Load 3 (Used to measure disable delays) VCC GND To the output under test R to VCC for tPZ L R to GND for t PZH To the output R = 1 kΩ under test 35 pF R to VCC for t PLZ R to GND for tPHZ R = 1 kΩ 5 pF Figure 2-6 • AC Test Loads 2 -1 0 v2.2 RTSX-S RadTolerant FPGAs 5V TTL and 3.3V LVTTL Table 2-10 • 5V TTL and 3.3V LVTTL Electrical Specifications Military Symbol VOH VCCI = Min, VI = VIH or VIL VCCI = Min, VI = VIH or VIL VOL VCCI = Min, VI = VIH or VIL VCCI = Min, VI = VIH or VIL VIL VIH IIL/ IIH IOZ tR , tF CIN CCLK VMEAS IV Curve Notes: 1. The IBIS model can be found at www.actel.com/techdocs/models/ibis.html. 2. If tR/tF exceeds the limit of 10 ns, Actel can guarantee reliability but not functionality. 3. Absolute maximum pin capacitance, which includes package and I/O input capacitance. 2 Parameter (IOH = -1mA) (IOH = -8mA) (IOL= 1mA) (IOL= 12mA) Min. 0.9 VCCI 2.4 Max. Units V V 0.1 VCCI 0.4 0.8 2.0 –20 –20 20 20 10 20 20 1.5 V V V V µA µA ns pF pF V Input Low Voltage Input High Voltage Input Leakage Current, VIN = VCCI or GND Tristate Output Leakage Current, VOUT = VCCI or GND Input Transition Time Input Pin CLK Pin Capacitance3 Capacitance3 Trip point for Input buffers and Measuring point for Output buffers Can be derived from the IBIS model on the web. v2.2 2-11 RTSX-S RadTolerant FPGAs Timing Characteristics Table 2-11 • RT54SX32S 5V TTL and 3.3V LVTTL I/O Module Worst-Case Military Conditions VCCA = 2.25V, TJ = 125°C, Radiation Level = 0 krad (Si) ‘–1’ Speed Parameter Description Min. Max. ‘Std.’ Speed Min. Max. Units 5V TTL Output Module Timing (VCCI = 4.5V) tINYH tINYL tDLH tDHL tDHLS tENZL tDENZLS tENZH tENLZ tENHZ dTLH dTHL dTHLS Input Data Pad-to-Y High Input Data Pad-to-Y Low Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low – low slew Enable-to-Pad, Z to Low Enable-to-Pad, Z to Low – low slew Enable-to-Pad, Z to High Enable-to-Pad, Low to Z Enable-to-Pad, High to Z Delta Delay vs. Load Low to High Delta Delay vs. Load High to Low Delta Delay vs. Load High to Low – low slew 0.7 1.1 3.1 3.8 9.8 2.5 9.0 3.1 4.4 3.8 0.036 0.029 0.049 0.9 1.3 3.6 4.4 11.5 3.0 10.6 3.6 5.3 4.4 0.046 0.038 0.064 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF 3.3V LVTTL Output Module Timing (VCCI = 3.0V) tINYH tINYL tDLH tDHL tDHLS tENZL tDENZLS tENZH tENLZ tENHZ dTLH dTHL dTHLS Input Data Pad-to-Y High Input Data Pad-to-Y Low Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low – low slew Enable-to-Pad, Z to L Enable-to-Pad, Z to Low – low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Delay vs. Load Low to High Delta Delay vs. Load High to Low Delta Delay vs. Load High to Low – low slew 0.8 1.1 4.1 3.7 13.2 2.9 12.7 4.1 3.7 3.7 0.064 0.031 0.069 0.9 1.3 4.8 4.4 15.6 3.4 14.9 4.8 4.4 4.4 0.081 0.040 0.088 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF Note: Output delays based on 35 pF loading. 2 -1 2 v2.2 RTSX-S RadTolerant FPGAs Table 2-12 • RT54SX72S 5V TTL and 3.3V LVTTL I/O Module Worst-Case Military Conditions VCCA = 2.25V, TJ = 125°C, Radiation Level = 0 krad (Si) ‘–1’ Speed Parameter Description Min. Max. ‘Std.’ Speed Min. Max. Units 5V TTL Output Module Timing (VCCI = 4.5V) tINYH tINYL tDLH tDHL tDHLS tENZL tDENZLS tENZH tENLZ tENHZ dTLH dTHL dTHLS Input Data Pad-to-Y High Input Data Pad-to-Y Low Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low – low slew Enable-to-Pad, Z to Low Enable-to-Pad, Z to Low – low slew Enable-to-Pad, Z to High Enable-to-Pad, Low to Z Enable-to-Pad, High to Z Delta Delay vs. Load Low to High Delta Delay vs. Load High to Low Delta Delay vs. Load High to Low – low slew 0.7 1.1 3.2 4.0 10.3 2.5 9.0 3.2 4.4 4.0 0.036 0.029 0.049 0.9 1.3 3.7 4.7 12.1 3.0 10.6 3.7 5.3 4.7 0.046 0.038 0.064 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF 3.3V LVTTL Output Module Timing (VCCI = 3.0V) tINYH tINYL tDLH tDHL tDHLS tENZL tDENZLS tENZH tENLZ tENHZ dTLH dTHL dTHLS Input Data Pad-to-Y High Input Data Pad-to-Y Low Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low – low slew Enable-to-Pad, Z to L Enable-to-Pad, Z to Low – low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta Delay vs. Load Low to High Delta Delay vs. Load High to Low Delta Delay vs. Load High to Low – low slew 1.0 2.2 4.0 3.6 12.7 2.9 12.7 4.0 3.9 3.6 0.064 0.031 0.069 1.2 2.5 4.6 4.2 14.9 3.4 14.9 4.6 4.4 4.2 0.081 0.04 0.088 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF Note: Output delays based on 35 pF loading. v2.2 2-13 RTSX-S RadTolerant FPGAs 5V CMOS Table 2-13 • 5V CMOS Electrical Specifications Military Symbol VOH VOL VIL VIH IOZ tR , tF CIN CCLK VMEAS IV Curve Notes: 1. Absolute maximum pin capacitance, which includes package and I/O input capacitance. 2. The IBIS model can be found at www.actel.com/techdocs/models/ibis.html. VCCI = MIN, VI = VCCI or GND VCCI = MIN, VI = VCCI or GND Input Low Voltage, VOUT = VVOL(max) Input High Voltage, VOUT = VVOH(min) Tristate Output Leakage Current, VOUT = VCCI or GND Input Transition Time Input Pin Capacitance CLK Pin Capacitance1 2.5 1 Parameter (IOH = –20µA) (IOL= ±20µA) Min. VCCI - 0.1 Max. Units V 0.1 0.3VCC 0.7VCC –20 20 10 20 20 V V V µA ns pF pF V Trip point for Input buffers and Measuring point for Output buffers Can be derived from the IBIS model on the web.2 Timing Characteristics Table 2-14 • RT54SX32S 5V CMOS I/O Module Worst-Case Military Conditions VCCA = 2.25V, VCCI = 4.5V, TJ = 125°C, Radiation Level = 0 krad (Si) ‘–1’ Speed Parameter Description Min. Max. ‘Std.’ Speed Min. Max. Units 5V CMOS Output Module Timing tINYH tINYL tDLH tDHL tDHLS tENZL tDENZLS tENZH tENLZ tENHZ dTLH dTHL dTHLS Input Data Pad-to-Y High Input Data Pad-to-Y Low Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low – low slew Enable-to-Pad, Z to Low Enable-to-Pad, Z to Low – low slew Enable-to-Pad, Z to High Enable-to-Pad, Low to Z Enable-to-Pad, High to Z Delta Delay vs. Load Low to High Delta Delay vs. Load High to Low Delta Delay vs. Load High to Low – low slew 0.7 1.1 3.4 3.6 8.7 2.3 8.8 3.6 4.5 3.4 0.036 0.029 0.049 0.9 1.3 4.0 4.2 10.3 2.8 10.4 4.2 5.3 4.0 0.046 0.038 0.064 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF Note: Output delays based on 35 pF loading. 2 -1 4 v2.2 RTSX-S RadTolerant FPGAs Table 2-15 • RT54SX72S 5V CMOS I/O Module Worst-Case Military Conditions VCCA = 2.25V, VCCI = 4.5V, TJ = 125°C, Radiation Level = 0 krad (Si) ‘–1’ Speed Parameter Description Min. Max. ‘Std.’ Speed Min. Max. Units 5V CMOS Output Module Timing tINYH tINYL tDLH tDHL tDHLS tENZL tDENZLS tENZH tENLZ tENHZ dTLH dTHL dTHLS Input Data Pad-to-Y High Input Data Pad-to-Y Low Data-to-Pad Low to High Data-to-Pad High to Low Data-to-Pad High to Low – low slew Enable-to-Pad, Z to Low Enable-to-Pad, Z to Low – low slew Enable-to-Pad, Z to High Enable-to-Pad, Low to Z Enable-to-Pad, High to Z Delta Delay vs. Load Low to High Delta Delay vs. Load High to Low Delta Delay vs. Load High to Low – low slew 0.7 0.0 3.6 3.8 9.2 2.3 8.8 3.8 4.5 3.6 0.036 0.029 0.049 0.9 0.0 4.2 4.5 10.8 2.8 10.4 4.5 5.3 4.2 0.046 0.038 0.064 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF Note: Output delays based on 35 pF loading. v2.2 2-15 RTSX-S RadTolerant FPGAs 5V PCI The RTSX-S family supports 5V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1. Table 2-16 • 5V PCI DC Specifications Symbol VCCA VCCI VIH VIL IIH IIL VOH VOL CIN CCLK VMEAS Notes: 1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up must have 6 mA; the latter include, FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted to motherboard-only devices, which could be up to 16 pF in order to accommodate PGA packaging. This mean that components for expansion boards need to use alternatives to ceramic PGA packaging (i.e., PBGA,PQFP, SGA, etc.). Supply Voltage for Array Supply Voltage for I/Os Input High Voltage1 Input Low Voltage 1 Parameter Condition Min. 2.25 4.5 2.0 –0.5 Max. 2.75 5.5 VCCI + 0.5 0.8 70 –70 Units V V V V µA µA V Input High Leakage Current Input Low Leakage Current Output High Voltage Output Low Voltage2 Input Pin Capacitance3 VIN = 2.75 VIN = 0.5 IOUT = –2 mA IOUT = 3 mA, 6 mA 2.4 0.55 10 5 1.5 12 V pF pF V CLK Pin Capacitance Trip Point for Input Buffers and Measuring Point for Output Buffers 200.0 IOL Max. Specification 150.0 100.0 IOL Min. Specification Current (mA) 50.0 0.0 0 –50.0 –100.0 –150.0 –200.0 IOH Voltage Out (V) 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 IOH Min. Specification IOL IOH Max. Specification Figure 2-7 • 5V PCI V/I Curve for RTSX-S Equation A IOH = 11.9 * (VOUT – 5.25) * (VOUT + 2.45) for VCCI > VOUT > 3.1V Equation B IOL = 78.5 * VOUT * (4.4 – VOUT) for 0V < VOUT < 0.71V 2 -1 6 v2.2 RTSX-S RadTolerant FPGAs Table 2-17 • 5V PCI AC Specifications Symbol IOH(AC) Switching Current High Parameter Condition 0 < VOUT < 1.4 1 Min. –44 (–44 + (VOUT – 1.4)/0.024) Max. Units mA mA 1.4 < VOUT < 2.4 1, 2 3.1 < VOUT < VCCI 1, 3 "Equation A" on page 2-16 –142 95 mA mA mA "Equation B" on page 2-16 206 –25 + (VIN + 1)/0.015 mA mA 5 5 V/ns V/ns (Test Point) IOL(AC) Switching Current Low VOUT = 3.1 3 VOUT = 2.2 1 1 2.2 > VOUT > 0.55 (VOUT/0.023) 0.71 > VOUT > 0 1, 3 (Test Point) ICL slewR slewF Notes: Low Clamp Current Output Rise Slew Rate Output Fall Slew Rate VOUT = 0.71 –5 < VIN ≤ –1 0.4V to 2.4V 2.4V to 0.4V load4 load4 1 1 1. Refer to the V/I curves in Figure 2-7 on page 2-16. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are system outputs. The “Switching Current High” specification is not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain outputs. 2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up. 3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B) are provided with the respective curves in Figure 2-7 on page 2-16. The equation defined maximum should be met by the design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load is optional; i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI Local Bus Specification (Figure 2-8). However, adherence to both the maximum and minimum parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to revision 2.1 of the specification, there may be components in the market that have faster edge rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs. pin output buffer 50 pF Figure 2-8 • 5V PCI Output Loading v2.2 2-17 RTSX-S RadTolerant FPGAs Timing Characteristics Table 2-18 • RT54SX32S 5V PCI I/O Module Worst-Case Military Conditions VCCA = 2.25V, VCCI = 4.5V, TJ= 125°C, Radiation Level = 0 krad (Si) ‘–1’ Speed Parameter 5V PCI Output Module Timing tINYH tINYL tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH dTHL Input Data Pad-to-Y High Input Data Pad-to-Y Low Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to Low Enable-to-Pad, Z to High Enable-to-Pad, Low to Z Enable-to-Pad, High to Z Delta Delay vs. Load Low to High Delta Delay vs. Load High to Low 0.7 1.1 3.4 4.1 2.8 3.4 4.9 4.1 0.036 0.029 0.9 1.3 4.0 4.8 3.3 4.0 5.8 4.8 0.046 0.038 ns ns ns ns ns ns ns ns ns/pF ns/pF Description Min. Max. ‘Std.’ Speed Min. Max. Units Note: Output delays based on 50 pF loading. Table 2-19 • RT54SX72S 5V PCI I/O Module Worst-Case Military Conditions VCCA = 2.25V, VCCI = 4.5V, TJ= 125°C, Radiation Level = 0 krad (Si) ‘–1’ Speed Parameter 5V PCI Output Module Timing tINYH tINYL tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH dTHL Input Data Pad-to-Y High Input Data Pad-to-Y Low Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to Low Enable-to-Pad, Z to High Enable-to-Pad, Low to Z Enable-to-Pad, High to Z Delta Delay vs. Load Low to High Delta Delay vs. Load High to Low 0.7 1.1 3.5 4.3 2.8 3.5 4.9 4.3 0.036 0.029 0.9 1.3 4.1 5.1 3.3 4.1 5.8 5.1 0.046 0.038 ns ns ns ns ns ns ns ns ns/pF ns/pF Description Min. Max. ‘Std.’ Speed Min. Max. Units Note: Output delays based on 50 pF loading. 2 -1 8 v2.2 RTSX-S RadTolerant FPGAs 3.3V PCI The RTSX-S family supports 3.3V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1. Table 2-20 • 3.3 V PCI DC Specifications Symbol VCCA VCCI VIH VIL IIPU IIL/IIH VOH VOL CIN CCLK VMEAS Parameter Supply Voltage for Array Supply Voltage for I/Os Input High Voltage Input Low Voltage Input Pull-up Voltage1 Input Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance3 5 CLK Pin Capacitance Trip point for Input buffers Output buffer measuring point - rising edge Output buffer measuring point - falling edge Notes: 1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this input VIN. 2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted to motherboard-only devices, which could be up to 16 pF, in order to accommodate PGA packaging. This means that components for expansion boards would need to use alternatives to ceramic PGA packaging. 2 Condition Min. 2.25 3.0 0.5VCCI –0.5 0.7VCCI Max. 2.75 3.6 VCCI + 0.5 0.3VCCI ±20 Units V V V V V µA V V pF pF V 0 < VIN < VCCI IOUT = –500 µA IOUT = 1500 µA 0.9VCCI 0.1VCCI 10 12 0.4 * VCCI 0.285 * VCCI 0.615 * VCCI 150.0 IOL Max. Specification 100.0 50.0 0.0 0 –50.0 –100.0 –150.0 Voltage Out (V) Figure 2-9 • 3.3V PCI V/I Curve for the RTSX-S Family IOL Current (mA) IOL Min. Specification 0.5 1 1.5 2 2.5 3 3.5 4 IOH Min. Specification IOH IOH Max. Specification Equation C IOH = (98.0/VCCI) * (VOUT – VCCI) * (VOUT + 0.4VCCI) for VCCI > VOUT > 0.7 VCCI Equation D IOL = (256/VCCI) * VOUT * (VCCI – VOUT) for 0V < VOUT < 0.18 VCCI v2.2 2-19 RTSX-S RadTolerant FPGAs Table 2-21 • 3.3V PCI AC Specifications Symbol IOH(AC) Parameter Switching Current High Condition 0 < VOUT ≤ 0.3VCCI 1 Min. –12VCCI (–17.1 + (VCCI – VOUT)) 1, 2 Max. Units mA mA 0.3VCCI ≤ VOUT < 0.9VCCI 1 0.7VCCI < VOUT < VCCI (Test Point) IOL(AC) Switching Current Low VOUT = 0.7VCC 2 VCCI > VOUT ≥ 0.6VCCI 1 1 "Equation C" on page 2-19 –32VCCI 16VCCI (26.7VOUT) "Equation D" on page 2-19 38VCCI –25 + (VIN + 1)/0.015 25 + (VIN – VCCI – 1)/0.015 1 1 4 4 mA mA mA V/ns V/ns mA mA mA 0.6VCCI > VOUT > 0.1VCCI 0.18VCCI > VOUT > 0 1, 2 (Test Point) ICL ICH slewR slewF Notes: Low Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate VOUT = 0.18VCC 2 –3 < VIN ≤ –1 VCCI + 4 > VIN ≥ VCCI + 1 0.2VCCI to 0.6VCCI load 3 0.6VCCI to 0.2VCCI load 3 1. Refer to the V/I curves in Figure 2-9 on page 2-19. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half-size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are system outputs. The “Switching Current High” specification is not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain outputs. 2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C and D) are provided with the respective curves in Figure 2-9 on page 2-19. The equation defined maximum should be met by the design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load is optional (Figure 2-10); i.e., the designer may elect to meet this parameter with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs. Pin Output Buffer 1 k/25 Ω 1/2 in. max. 10 pF Output Buffer Pin 1/2 in. max. VCC 1 k/25 Ω 10 pF Figure 2-10 • 3.3V PCI Output Loading 2 -2 0 v2.2 RTSX-S RadTolerant FPGAs Timing Characteristics Table 2-22 • RT54SX32S 3.3V PCI I/O Module Worst-Case Military Conditions VCCA = 2.25V, VCCI = 3.0V, TJ = 125°C, Radiation Level = 0 krad (Si) ‘–1’ Speed Parameter Description Min. Max. ‘Std.’ Speed Min. Max. Units 3.3V PCI Output Module Timing tINYH tINYL tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH dTHL Input Data Pad-to-Y High Input Data Pad-to-Y Low Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to Low Enable-to-Pad, Z to High Enable-to-Pad, Low to Z Enable-to-Pad, High to Z Delta Delay vs. Load Low to High Delta Delay vs. Load High to Low 0.8 0.9 3.0 3.0 2.1 3.0 2.7 3.0 0.067 0.031 0.9 1.1 3.5 3.5 2.5 3.5 3.9 3.5 0.085 0.040 ns ns ns ns ns ns ns ns ns/pF ns/pF Note: Delays based on 10 pF loading and 25 Ω resistance. Table 2-23 • RT54SX72S 3.3V PCI I/O Module Worst-Case Military Conditions VCCA = 2.25V, VCCI = 3.0V, TJ = 125°C, Radiation Level = 0 krad (Si) ‘–1’ Speed Parameter Description Min. Max. ‘Std.’ Speed Min. Max. Units 3.3V PCI Output Module Timing tINYH tINYL tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH dTHL Input Data Pad-to-Y High Input Data Pad-to-Y Low Data-to-Pad Low to High Data-to-Pad High to Low Enable-to-Pad, Z to Low Enable-to-Pad, Z to High Enable-to-Pad, Low to Z Enable-to-Pad, High to Z Delta Delay vs. Load Low to High Delta Delay vs. Load High to Low 0.7 0.9 2.8 2.8 2.1 2.8 2.7 2.8 0.067 0.031 0.8 1.1 3.3 3.3 2.5 3.3 3.9 3.3 0.085 0.040 ns ns ns ns ns ns ns ns ns/pF ns/pF Note: Delays based on 10 pF loading and 25 Ω resistance. v2.2 2-21 RTSX-S RadTolerant FPGAs Module Specifications C-Cell Introduction The C-cell is one of the two logic module types in the RTSXS architecture. It is the combinatorial logic resource in the device. The RTSX-S architecture uses the same C-cell configuration as found in the SX and SX-A families. The C-cell features the following (Figure 2-11): • Eight-input MUX (data: D0-D3, select: A0, A1, B0, B1). User signals can be routed to any one of these inputs. C-cell inputs (A0, A1, B0, B1) can be tied to one of the either the routed or quad clocks (CLKA/B or QCLKA/B/C/D). • • Inverter (DB input) can be used to drive a complement signal of any of the inputs to the C-cell. A hardwired connection (direct connect) to the associated R-cell with a signal propagation time of less than 0.1 ns. This layout of the C-cell enables the implementation of over 4,000 functions of up to five bits. For example, two C-cells can be used together to implement a four-input XOR function in a single cell delay. The C-cell configuration is handled automatically for the user with Actel's extensive macro library (please see Actel’s Antifuse Macro Library Guide for a complete listing of available RTSX-S macros). D0 D1 Y D2 D3 Sa Sb DB A0 B0 A1 B1 Figure 2-11 • C-Cell VC C S, A or B S A B Y Y GND Y 50% tPD GND tPD tPD 50% 50% VCC 50% t PD GND 50% VCC 50% Figure 2-12 • C-Cell Timing Model and Waveforms 2 -2 2 v2.2 RTSX-S RadTolerant FPGAs Timing Characteristics Table 2-24 • C-Cell Worst-Case Military Conditions VCCA = 2.25V, VCCI = 3.0V, TJ= 125°C, Radiation Level = 0 krad (Si) ‘–1’ Speed Parameter C-Cell Propagation Delays tPD Internal Array Module 1.2 1.4 ns Description Min. Max. ‘Std.’ Speed Min. Max. Units Note: For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. R-Cell Introduction The R-cell, the sequential logic resource of RTSX-S devices, is the second logic module type in the RTSX-S family architecture. The RTAX-S R-cell is an SEUenhanced version of the SX and SX-A R-cell (Figure 2-13). The main features of the R-cell include the following: • Direct connection to the adjacent C-cell through the hardwired connection DCIN. DCIN is driven by the DCOUT of an adjacent C-cell via the DirectConnect routing resource, providing a connection with less than 0.1 ns of routing delay. The R-cell can be used as a standalone flip-flop. It can be driven by any other C-cell or I/O modules through the regular routing structure (using DIN as a routable data input). This gives the option of using it as a 2:1 MUXed flip-flop as well. Independent active-low asynchronous clear (CLRB). Independent active-low asynchronous preset (PSETB). If both CLRB and PSETB are Low, CLRB has higher priority. • Clock can be driven by any of the following (CKP input selects clock polarity): – – – – • • The high-performance, hardwired, fast clock (HCLK) One of the two routed clocks (CLKA/B) One of the four quad clocks (QCLKA/B/C/D) in the case of the RT54SX72S User signals S0, S1, PSETB, and CLRB can be driven by CLKA/B, QCLKA/B/C/D (for the RT54SX72S) or user signals. Routed Data Input and S1 can be driven by user signals. • • • As with the C-cell, the configuration of the R-cell to perform various functions is handled automatically for the user through Actel's extensive macro library (please see Actel’s Macro Library Guide for a complete listing of available RTAX-S macros). S0 Routed Data Input S1 PSETB Direct Connect Input D Q Y HCLK CLKA, CLKB, Internal Logic CKS Figure 2-13 • R-Cell CLRB CKP v2.2 2-23 RTSX-S RadTolerant FPGAs SEU-Hardened D Flip-Flop In order to meet the stringent SEU requirements of a LET threshold greater than 40MeV-cm2/gm, the internal design of the R-cell was modified without changing the functionality of the cell. Figure 2-14 is a simplified representation of how the D flip-flop in the R-cell is implemented in the SX-A architecture. The flip-flop consists of a master and a slave latch gated by opposite edges of the clock. Each latch is constructed by feeding back the output to the input stage. The potential problem in a space environment is that either of the latches can change state when hit by a particle with enough energy. To achieve the SEU requirements, the D flip-flop in the RTSX-S R-cell is enhanced (Figure 2-15). Both the master and slave "latches" are each implemented with three latches. The asynchronous self-correcting feedback paths of each of the three latches is voted with the outputs of the other two latches. If one of the three latches is struck by an ion and starts to change state, the voting with the other two latches prevents the change from feeding back and permanently latching. Care was taken in the layout to ensure that a single ion strike could not affect more than one latch. Figure 2-16 shows a simplified schematic of the test circuitry that has been added to test the functionality of all the components of the flipflop. The inputs to each of the three latches are independently controllable so the voting circuitry in the asynchronous self-correcting feedback paths can be tested exhaustively. This testing is performed on an unprogrammed array during wafer sort, final test, and post-burn-in test. This test circuitry cannot be used to test the flip-flops once the device has been programmed. D CLK CLK Q Figure 2-14 • SX-A R-Cell Implementation of a D Flip-Flop D CLK CLK Q Voter Gate CLK CLK CLK CLK CLK CLK Figure 2-15 • RTSX-S R-Cell Implementation of D Flip-Flop Using Voter Gate Logic 2 -2 4 v2.2 RTSX-S RadTolerant FPGAs D Tst1 Q Voter Gate Tst2 Tst3 Test Circuitry CLK Figure 2-16 • R-Cell Implementation – Test Circuitry PRE D CLK CLR (Positive edge triggered) tHD Q D CLK Q CLR PRESET tSUD tHPWH tRPWH tRCO tHPWL tRPWL tCLR tWASYN tPRESET tHP Figure 2-17 • R-Cell Tiing Models and Waveforms v2.2 2-25 RTSX-S RadTolerant FPGAs Timing Characteristics Table 2-25 • R-Cell Worst-Case Military Conditions VCCA = 2.25V, VCCI = 3.0V, TJ = 125°C, Radiation Level = 0 krad (Si) ‘–1’ Speed Parameter R-Cell Propagation Delays tRCO tCLR tPRESET tSUD tHD tWASYN tRECASYN tHASYN Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Hold Time 1.0 0.8 1.1 0.8 0.0 2.8 0.7 0.7 1.2 1.0 1.3 1.0 0.0 3.3 0.8 0.8 ns ns ns ns ns ns ns ns Description Min. Max. ‘Std.’ Speed Min. Max. Units 2 -2 6 v2.2 RTSX-S RadTolerant FPGAs Routing Specifications Routing Resources The routing structure found in RTSX-S devices enables any logic module to be connected to any other logic module in the device while retaining high performance. There are multiple paths and routing resources that can be used to route one logic module to another, both within a SuperCluster and elsewhere on the chip. There are three primary types of routing within the RTSX-S architecture: DirectConnect, FastConnect, and Vertical and Horizontal Routing. Horizontal and Vertical Routing In addition to DirectConnect and FastConnect, the architecture makes use of two globally-oriented routing resources known as segmented routing and high-drive routing. Actel’s segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the 100-percent-automatic place-and-route software to minimize signal propagation delays. DirectConnect DirectConnects provide a high-speed connection between an R-cell and its adjacent C-cell (Figure 1-3 and Figure 1-4 on page 1-4). This connection can be made from the Y output of the C-cell to the DirectConnect input of the Rcell by configuring of the S0 line of the R-cell. This provides a connection that does not require an antifuse and has a delay of less than 0.1 ns. Critical Nets and Typical Nets Propagation delays are expressed only for typical nets, which are used for the initial design performance evaluation. Critical net delays can then be applied to the most time-critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to six percent of the nets in a design may be designated as critical, while 90 percent of the nets in a design are typical. FastConnect For high-speed routing of logic signals, FastConnects can be used to build a short distance connection using a single antifuse (Figure 1-3 and Figure 1-4 on page 1-4). FastConnects provide a maximum delay of 0.4 ns. The outputs of each logic module connect directly to the output tracks within a SuperCluster. Signals on the output tracks can then be routed through a single antifuse connection to drive the inputs of logic modules either within one SuperCluster or in the SuperCluster immediately below. Long Tracks Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes five antifuse connections. This increases capacitance and resistance results in longer net delays for macros connected to long tracks. Typically up to six percent of nets in a fully utilized device require long tracks. Long tracks can cause a delay from 4.0 ns to 8.4 ns. This additional delay is represented statistically in higher fanout routing delays in the "Timing Characteristics" on page 2-28. v2.2 2-27 RTSX-S RadTolerant FPGAs Timing Characteristics Table 2-26 • RT54SX32S Worst-Case Military Conditions VCCA = 2.25V, VCCI = 3.0V, TJ = 125°C, Radiation Level = 0 krad (Si) ‘–1’ Speed Parameter Description Min. Max. ‘Std.’ Speed Min. Max. Units Predicted Routing Delays tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 FO=1 Routing Delay, DirectConnect FO=1 Routing Delay, FastConnect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay 0.1 0.4 0.8 1.0 1.4 1.5 2.9 4.0 0.1 0.4 0.9 1.2 1.6 1.8 3.4 4.7 ns ns ns ns ns ns ns ns Note: Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Table 2-27 • RT54SX72S Worst-Case Military Conditions VCCA = 2.25V, VCCI = 3.0V, TJ = 125°C, Radiation Level = 0 krad (Si) ‘–1’ Speed Parameter Description Min. Max. ‘Std.’ Speed Min. Max. Units Predicted Routing Delays tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 FO=1 Routing Delay, DirectConnect FO=1 Routing Delay, FastConnect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay 0.1 0.4 0.9 1.2 1.8 1.9 3.7 5.1 0.1 0.4 1.0 1.4 2.0 2.3 4.3 6.0 ns ns ns ns ns ns ns ns Note: Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. 2 -2 8 v2.2 RTSX-S RadTolerant FPGAs Global Resources One of the most important aspects of any FPGA architecture is its global resource or clock structure. The RTSX-S family provides flexible and easy-to-use global resources without the limitations normally found in other FPGA architectures. The RTSX-S architecture contains three types of global resources, the HCLK (hardwired clock) and CLK (routed clock) and in the RT54SX72S, QCLK (quadrant clock). Each RTSX-S device is provided with one HCLK and two CLKs. The RT54SX72S has an additional four QCLKs. Routed Clocks The routed clocks (CLKA and CLKB) are low-skew networks that can drive the clock inputs of all R-cells in the device (logically equivalent to the HCLK). CLK has the added flexibility in that it can drive the S0 (Enable), S1, PSETB, and CLRB inputs of R-cells as well as any of the inputs of any C-cell in the device. This allows CLKs to be used not only as clocks but also for other global signals or high fanout nets. Both CLKs are available everywhere on the chip. If CLKA or CLKB pins are not used or sourced from signals, then these pins must be set as Low or High on the board. They must not be left floating (except in RTSX72S, where these clocks can be configured as regular I/Os). Hardwired Clock The hardwired (HCLK) is a low-skew network that can directly drive the clock inputs of all R-cells in the device with no antifuse in the path. The HCLK is available everywhere on the chip. Upon power-up of the RTSX-S device, four clock pulses must be detected on HCLK before the clock signal will be propagated to registers in the device. Quadrant Clocks The RT54SX72S device provides four quadrant clocks (QCLKA, QCLKB, QCLKC, QCLKD) to the user, which can be sourced from external pins or from internal logic signals within the device. Each of these clocks can individually drive up to one full quadrant of the chip, or they can be grouped together to drive multiple quadrants (Figure 2-18). If QCLKs are not used as quadrant clocks, they can behave as regular I/Os. See Actel’s application note Using A54SX72A and RT54SX72S Quadrant Clocks for more information. 4 QCLKBUFS Quadrant 2 4 5:1 5:1 Quadrant 3 QCLKINT (to array) 4 Quadrant 0 5:1 QCLKINT (to array) 5:1 Quadrant 1 QCLKINT (to array) Figure 2-18 • RTSX-S QCLK Structure QCLKINT (to array) v2.2 2-29 RTSX-S RadTolerant FPGAs Timing Characteristics Table 2-28 • RT54SX32S at VCCI = 3.0V Worst-Case Military Conditions VCCA = 2.25V, VCCI = 3.0V, TJ = 125°C, Radiation Level = 0 krad (Si) ‘–1’ Speed Parameter Description Min. Max. ‘Std.’ Speed Min. Max. Units Dedicated (Hardwired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Pad to R-Cell Input Low to High Pad to R-Cell Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 4.2 238 2.1 2.1 1.6 5.0 200 3.9 3.9 2.5 2.5 1.9 4.6 4.6 ns ns ns ns ns ns MHz Routed Array Clock Networks tRCKH tRCHKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW tRP fRMAX Pad to R-cell Input High to Low (Light Load)) Pad to R-cell Input Low to High (Light Load)) Pad to R-cell Input Low to High (50% Load) Pad to R-cell Input High to Low (50% Load) Pad to R-cell Input Low to High (100% Load) Pad to R-cell Input High to Low (100% Load) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) Minimum Period Maximum Frequency 4.2 238 2.1 2.1 2.8 2.8 2.8 5.0 200 4.2 3.9 5.0 4.3 5.6 4.9 2.5 2.5 3.3 3.3 3.3 4.9 4.6 5.9 5.1 6.5 5.7 ns ns ns ns ns ns ns ns ns ns ns ns MHz 2 -3 0 v2.2 RTSX-S RadTolerant FPGAs Table 2-29 • RT54SX32S at VCCI = 4.5V Worst-Case Military Conditions VCCA = 2.25V, VCCI = 4.5V, TJ = 125°C, Radiation Level = 0 krad (Si) ‘–1’ Speed Parameter Description Min. Max. ‘Std.’ Speed Min. Max. Units Dedicated (Hardwired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Pad to R-Cell Input Low to High Pad to R-Cell Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 4.2 238 2.1 2.1 1.6 5.0 200 3.9 3.9 2.5 2.5 1.9 4.6 4.6 ns ns ns ns ns ns MHz Routed Array Clock Networks tRCKH tRCHKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW tRP fRMAX Pad to R-cell Input High to Low (Light Load)) Pad to R-cell Input Low to High (Light Load)) Pad to R-cell Input Low to High (50% Load) Pad to R-cell Input High to Low (50% Load) Pad to R-cell Input Low to High (100% Load) Pad to R-cell Input High to Low (100% Load) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) Minimum Period Maximum Frequency 4.2 238 2.1 2.1 2.8 2.8 2.8 5.0 200 3.9 3.7 4.7 4.1 5.3 4.7 2.5 2.5 3.3 3.3 3.3 4.6 4.4 5.6 4.9 6.2 5.5 ns ns ns ns ns ns ns ns ns ns ns ns MHz v2.2 2-31 RTSX-S RadTolerant FPGAs Table 2-30 • RT54SX72S at VCCI = 3.0V Worst-Case Military Conditions VCCA = 2.25V, VCCI = 3.0V, TJ = 125°C, Radiation Level = 0 krad (Si) ‘–1’ Speed Parameter Description Min. Max. ‘Std.’ Speed Min. Max. Units Dedicated (Hardwired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW tRP fRMAX tQCKH tQCKL tQCKH tQCKL tQCKH tQCKL tQPWH tQPWL tQCKSW tQCKSW tQCKSW tQP fQMAX Pad to R-cell Input Low to High Pad to R-cell Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 5.4 185 2.7 2.7 2.7 6.4 156 3.2 3.5 3.2 3.2 3.1 3.8 4.1 ns ns ns ns ns ns MHz Routed Array Clock Networks Pad to R-cell Input Low to High (Light Load)) Pad to R-cell Input High to Low (Light Load) Pad to R-cell Input Low to High (50% Load) Pad to R-cell Input High to Low (50% Load) Pad to R-cell Input Low to High (100% Load) Pad to R-cell Input High to Low (100% Load) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) Minimum Period Maximum Frequency 5.4 185 2.7 2.7 5.1 4.9 4.9 6.4 156 5.7 6.5 5.7 6.5 5.7 6.5 3.2 3.2 6.0 5.8 5.8 6.7 7.7 6.7 7.7 6.7 7.7 ns ns ns ns ns ns ns ns ns ns ns ns MHz Quadrant Array Clock Networks Pad to R-cell Input Low to High (Light Load) Pad to R-cell Input High to Low (Light Load) Pad to R-cell Input Low to High (50% Load) Pad to R-cell Input High to Low (50% Load) Pad to R-cell Input Low to High (100% Load) Pad to R-cell Input High to Low (100% Load) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) Minimum Period Maximum Frequency 5.4 185 2.7 2.7 0.6 1.0 1.0 6.4 156 3.6 3.6 3.7 3.9 4.0 4.1 3.2 3.2 0.7 1.1 1.1 4.2 4.2 4.3 4.5 4.7 4.8 ns ns ns ns ns ns ns ns ns ns ns ns MHz 2 -3 2 v2.2 RTSX-S RadTolerant FPGAs Table 2-31 • RT54SX72S at VCCI = 4.5V Worst-Case Military Conditions VCCA = 2.25V, VCCI = 4.5V, TJ = 125°C, Radiation Level = 0 krad (Si) ‘–1’ Speed Parameter Description Min. Max. ‘Std.’ Speed Min. Max. Units Dedicated (Hardwired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW tQP fQMAX tQCKH tQCKL tQCKH tQCKL tQCKH tQCKL tQPWH tQPWL tQCKSW tQCKSW tQCKSW tQP fQMAX Pad to R-cell Input Low to High Pad to R-cell Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 5.6 179 2.8 2.8 3.2 6.6 152 4.1 4.1 3.3 3.3 3.7 4.8 4.8 ns ns ns ns ns ns MHz Routed Array Clock Networks Pad to R-cell Input Low to High (Light Load)) Pad to R-cell Input High to Low (Light Load) Pad to R-cell Input Low to High (50% Load) Pad to R-cell Input High to Low (50% Load) Pad to R-cell Input Low to High (100% Load) Pad to R-cell Input High to Low (100% Load) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) Minimum Period Maximum Frequency 5.6 179 2.8 2.8 7.0 6.8 6.8 6.6 152 6.8 8.2 6.8 8.2 6.8 8.2 3.3 3.3 8.2 8.0 8.0 8.0 9.7 8.0 9.7 8.0 9.7 ns ns ns ns ns ns ns ns ns ns ns ns MHz Quadrant Array Clock Networks Pad to R-cell Input Low to High (Light Load)) Pad to R-cell Input High to Low (Light Load) Pad to R-cell Input Low to High (50% Load) Pad to R-cell Input High to Low (50% Load) Pad to R-cell Input Low to High (100% Load) Pad to R-cell Input High to Low (100% Load) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) Minimum Period Maximum Frequency 5.6 179 2.8 2.8 0.7 1.3 1.4 6.6 152 3.9 4.2 4.2 4.5 4.5 5.0 3.3 3.3 0.8 1.5 1.6 4.6 4.9 4.9 5.3 5.3 5.9 ns ns ns ns ns ns ns ns ns ns ns ns MHz v2.2 2-33 RTSX-S RadTolerant FPGAs Global Resource Access Macros The user can configure which global resource is used in the design as well as how each global resource is driven through the use of the following macros: • • HCLKBUF – used to drive the hardwired clock (HCLK) in both devices from an external pin CLKBUF and CLKBUFI – noninverting and inverting inputs used to drive either routed clock (CLKA or CLKB) in both devices from external pins CLKINT and CLKINTI – noninverting and inverting inputs used to drive either routed clock (CLKA or CLKB) in both devices from internal logic QCLKBUF and QCLKBUFI – noninverting and inverting inputs used to drive quadrant routed clocks (QCLKA/B/C/D) in the RT54SX72S from external pins HCLKBUF • QCLKINT and QCLKINTI – noninverting and inverting inputs used to drive quadrant routed clocks (QCLKA/B/C/D) in the RT54SX72S from internal logic QCLKBIBUF and QCLUKBIBUFI – noninverting and inverting inputs used to drive quadrant routed clocks (QCLKA/B/C/D) in the RT54SX72S alternatively from either external pins or internal logic • • Figure 2-19, Figure 2-20, and Figure 2-21 illustrate the various global-resource access macros. • Constant Load Clock Network Figure 2-19 • Hardwired Clock Buffer Clock Network From Internal Logic CLKBUF CLKBUFI CLKINT CLKINTI Figure 2-20 • Routed Clock Buffers in RT54SX32S OE From Internal Logic Clock Network From Internal Logic CLKBUF CLKBUFI CLKINT CLKINTI CLKBIBUF CLKBIBUFI QCLKBUF QCLKBUFI QCLKINT QCLKINTI QCLKBIBUF QCLKBIBUFI Figure 2-21 • Routed And Quadrant Clock Buffers in RT54SX72S 2 -3 4 v2.2 RTSX-S RadTolerant FPGAs Other Architectural Features JTAG Interface All RTSX-S devices are IEEE 1149.1 compliant and offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. The BST function is controlled through special JTAG pins (TMS, TDI, TCK, TDO, and TRST). The functionality of the JTAG pins is defined by two available modes: dedicated and flexible (Table 2-32). Note that TRST and TMS cannot be employed as user I/Os in either mode. Table 2-32 • Boundary Scan Pin Functionality Program Fuse Blown (Dedicated Test Mode) TCK, TDI, TDO are dedicated BST pins Program Fuse Not Blown (Flexible Mode) TCK, TDI, TDO are flexible and may be used as user I/Os as user I/Os or BST pins in flexible mode. This functionality is controlled by the BST TAP controller. The TAP controller receives two control inputs: TMS and TCK. Upon power-up, the TAP controller enters the Test-LogicReset state. In this state, TDI, TCK, and TDO function as user I/Os. The TDI, TCK, and TDO are transformed from user I/Os into BST pins when a rising edge on TCK is detected while TMS is at logic Low. To return to the TestLogic-Reset state, in the absences of TRST assertion, TMS must be held High for at least five TCK cycles. An external, 10 kΩ pull-up resistor tied to VCCI should be placed on the TMS pin to pull it High by default. Table 2-33 describes the different configurations of the BST pins and their functionality in different modes. Table 2-33 • JTAG Pin Configurations and Functions Designer "Reserve JTAG" Selection Checked Unchecked Unchecked TAP Controller State Any Test-Logic-Reset Other No need for pull-up resistor for Use a pull-up resistor of 10 kΩ TMS on TMS Mode Dedicated (JTAG) Flexible (User I/O) Flexible (JTAG) Dedicated Mode In dedicated mode, all JTAG pins are reserved for BST; users cannot employ them as regular I/Os. An internal pull-up resistor (on the order of 17 kΩ to 22 kΩ2) is automatically enabled on both TMS and TDI pins, and the TMS pin will function as defined in the IEEE 1149.1 (JTAG) specification. To enter dedicated mode, users need to reserve the JTAG pins in Actel’s Designer software during device selection. To reserve the JTAG pins, users can check the "Reserve JTAG" box in the "Device Selection Wizard" in Actel’s Designer software (Figure 2-22). TRST Pin The TRST pin functions as a dedicated boundary scan reset pin. An internal pull-up resistor is permanently enabled on the TRST pin. Additionally, the TRST pin must be grounded for flight applications. This will prevent Single-Event Upsets (SEU) in the TAP controller from inadvertently placing the device into JTAG mode. Probing Capabilities RTSX-S devices also provide internal probing capability that is accessed with the JTAG pins. Silicon Explorer II Probe Interface Figure 2-22 • Device Selection Wizard Flexible Mode In flexible mode, TDI, TCK, and TDO may be employed as either user I/Os or as JTAG input pins. The internal resistors on the TMS and TDI pins are not present in flexible JTAG mode. To enter the flexible mode, users need to uncheck the "Reserve JTAG" box in the "Device Selection Wizard" in Designer software. TDI, TCK, and TDO pins may function Actel’s Silicon Explorer II is an integrated hardware and software solution that, in conjunction with Actel’s Designer software, allows users to examine any of the internal nets of the device while it is operating in a prototype or a production system. The user can probe two nodes at a time without changing the placement or routing of the design and without using any additional device resources. Highlighted nets in Designer’s ChipEditor can be accessed using Silicon Explorer II in order to observe their real time values. 2. On a given device, the value of the internal pull-up resistor varies within 1 kΩ between the TMS and TDI pins. v2.2 2-35 RTSX-S RadTolerant FPGAs Silicon Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle. In addition, Silicon Explorer II does not require relayout or additional MUXes to bring signals out to external pins, which is necessary when using programmable logic devices from other suppliers. By eliminating multiple place-and-route cycles, the integrity of the design is maintained throughout the debug process. Both members of the RTSX-S family have two external pads: PRA and PRB. These can be used to bring out two probe signals from the device. To disallow probing, the SFUS security fuse in the silicon signature has to be programmed. Table 2-34 shows the possible device configuration options and their effects on probing. During probing, the Silicon Explorer II Diagnostic Hardware is used to control the TDI, TCK, TMS, and TDO pins to select the desired nets for debugging. The user simply assigns the selected internal nets in the Silicon Explorer II software to the PRA/PRB output pins for observation. Probing functionality is activated when the Table 2-34 • Device Configuration Options for Probe Capability JTAG Mode Dedicated Flexible Dedicated Flexible – Notes: TRST Low Low High High – BST pins are in JTAG mode and the TRST pin is driven High. If the TRST pin is held Low, the TAP controller will remain in the Test-Logic-Reset state, so no probing can be performed. Silicon Explorer II automatically places the device into JTAG mode, but the user must drive the TRST pin High or allow the internal pull-up resistor to pull TRST High. Silicon Explorer II connects to the host PC using a standard serial port connector. Connections to the circuit board are achieved using a nine-pin D-Sub connector (Figure 1-5 on page 1-6). Once the design has been placed-and-routed and the RTSX-S device has been programmed, Silicon Explorer II can be connected and the Silicon Explorer software can be launched. Silicon Explorer II comes with an additional optional PChosted tool that emulates an 18-channel logic analyzer. Two channels are used to monitor two internal nodes, and 16 channels are available to probe external signals. The software included with the tool provides the user with an intuitive interface that allows for easy viewing and editing of signal waveforms. Security Fuse Programmed No No No No Yes PRA and PRB1 User I/O2 User I/O2 TDI, TCK, and TDO1 Probing Unavailable User I/O2 Probe Circuit I/O Probe Circuit I/O Probe Circuit Secured Probe Circuit Outputs Probe Circuit Outputs Probe Circuit Secured 1. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports during probing. Since these pins are active during probing, input signals will not pass through these pins and may cause contention. 2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by the Designer software. 2 -3 6 v2.2 RTSX-S RadTolerant FPGAs Security Fuses Actel antifuse FPGAs, with FuseLock technology, offer the highest level of design security available in a programmable logic device. Since antifuse FPGAs are live at power-up, there is no bitstream that can be intercepted, and no bitstream or programming data is ever downloaded to the device, thus making device cloning impossible. In addition, special security fuses are hidden throughout the fabric of the device and may be programmed by the user to thwart attempts to reverse engineer the device by attempting to exploit either the programming or probing interfaces. Both invasive and noninvasive attacks against an RTSX-S device that access or bypass these security fuses will destroy access to the rest of the device. Refer to the Understanding Actel Antifuse Device Security white paper for more information. Look for this symbol to ensure your valuable IP is secure(Figure 2-23). Programming Device programming is supported through the Silicon Sculptor II, a single-site, robust and compact deviceprogrammer for the PC. Two Silicon Sculptor IIs can be daisy-chained and controlled from a single PC host. With standalone software for the PC, Silicon Sculptor II is designed to allow concurrent programming of multiple units from the same PC when daisy-chained. Silicon Sculptor II programs devices independently to achieve the fastest programming times possible. Each fuse is verified by Silicon Sculptor II to ensure correct programming. Furthermore, at the end of programming, there are integrity tests that are run to ensure that programming was completed properly. Not only does it test programmed and nonprogrammed fuses, Silicon Sculptor II also provides a self-test to extensively test its own hardware. Programming an RTSX-S device using Silicon Sculptor II is similar to programming any other antifuse device. The procedure is as follows: 1. Load the .AFM file. 2. Select the device to be programmed. 3. Begin programming. ue ™ Figure 2-23 • FuseLock Logo To ensure maximum security in RTSX-S devices, it is recommended that the user program the device security fuse (SFUS). When programmed, the Silicon Explorer II testing probes are disabled to prevent internal probing, and the programming interface is also disabled. All JTAG public instructions are still accessible by the user. For more information, refer to Actel’s Implementation of Security in Actel Antifuse FPGAs application note. When the design is ready to go to production, Actel offers volume programming services either through distribution partners or via our In-House Programming Center. For more details on programming the RTSX-S devices, please refer to the Silicon Sculptor II User’s Guide. v2.2 2-37 RTSX-S RadTolerant FPGAs Package Pin Assignments 208-Pin CQFP 160 159 158 157 208 207 206 205 1 2 3 4 Pin 1 156 155 154 153 Ceramic Tie Bar 208-Pin CQFP 49 50 51 52 108 107 106 105 Figure 3-1 • 208-Pin CQFP (Top View) v2.2 101 102 103 104 53 54 55 56 3-1 RTSX-S RadTolerant FPGAs 208-Pin CQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 RT54SX32S Function GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC GND VCCA GND I/O TRST I/O I/O I/O I/O I/O I/O RT54SX72S Function GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O GND VCCA I/O I/O I/O I/O I/O I/O GND VCCA GND I/O TRST I/O I/O I/O I/O I/O I/O Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 208-Pin CQFP RT54SX32S Function I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O RT54SX72S Function I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Note: Pin 65 is a No Connect (NC) on Commercial A54SX32SPQ208. Note: Pin 65 is a No Connect (NC) on Commercial A54SX32SPQ208. 3 -2 v2.2 RTSX-S RadTolerant FPGAs 208-Pin CQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 RT54SX32S Function I/O I/O I/O PRB, I/O GND VCCA GND NC I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O RT54SX72S Function I/O QCLKA, I/O I/O PRB, I/O GND VCCA GND NC I/O HCLK VCCI QCLKB, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 208-Pin CQFP RT54SX32S Function I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RT54SX72S Function I/O I/O I/O I/O I/O VCCA VCCI GND VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Note: Pin 65 is a No Connect (NC) on Commercial A54SX32SPQ208. Note: Pin 65 is a No Connect (NC) on Commercial A54SX32SPQ208. v2.2 3-3 RTSX-S RadTolerant FPGAs 208-Pin CQFP Pin Number 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 RT54SX32S Function VCCA GND I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA RT54SX72S Function VCCA GND I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKD, I/O I/O CLKA, I/O Pin Number 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 208-Pin CQFP RT54SX32S Function CLKB NC GND VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O RT54SX72S Function CLKB, I/O NC GND VCCA GND PRA, I/O VCCI I/O I/O QCLKC, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O Note: Pin 65 is a No Connect (NC) on Commercial A54SX32SPQ208. Note: Pin 65 is a No Connect (NC) on Commercial A54SX32SPQ208. 3 -4 v2.2 RTSX-S RadTolerant FPGAs 256-Pin CQFP 196 195 194 193 256 255 254 253 1 2 3 4 Pin 1 192 191 190 189 Ceramic Tie Bar 256-Pin CQFP 61 62 63 64 132 131 130 129 Figure 3-2 • 256-Pin CQFP (Top View) v2.2 125 126 127 128 65 66 67 68 3-5 RTSX-S RadTolerant FPGAs 256-Pin CQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 RT54SX32S Function GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND VCCA GND I/O I/O TRST I/O I/O I/O RT54SX72S Function GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND VCCA GND I/O I/O TRST I/O VCCA GND Pin Number 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 256-Pin CQFP RT54SX32S Function I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RT54SX72S Function I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O 3 -6 v2.2 RTSX-S RadTolerant FPGAs 256-Pin CQFP Pin Number 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 RT54SX32S Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCI GND VCCA I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O RT54SX72S Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKA, I/O PRB, I/O GND VCCI GND VCCA I/O HCLK I/O QCLKB, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O Pin Number 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 256-Pin CQFP RT54SX32S Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O RT54SX72S Function I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI GND VCCA I/O I/O I/O I/O v2.2 3-7 RTSX-S RadTolerant FPGAs 256-Pin CQFP Pin Number 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 RT54SX32S Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND NC GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O RT54SX72S Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND NC GND VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O Pin Number 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 256-Pin CQFP RT54SX32S Function I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCI GND RT54SX72S Function I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKD, I/O CLKA, I/O CLKB, I/O VCCI GND 3 -8 v2.2 RTSX-S RadTolerant FPGAs 256-Pin CQFP Pin Number 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 RT54SX32S Function NC GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O RT54SX72S Function NC GND PRA, I/O I/O I/O VCCA I/O I/O QCLKC, I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O v2.2 3-9 RTSX-S RadTolerant FPGAs 256-Pin CCLG Top View A1 Index Corner 256 193 Extenral Wire-Bond Number 1 192 64 129 65 128 Bottom View T R P N M L K J H G F E D C B A 1 2 3 45 6 7 8 9 10 11 12 13 14 15 16 Figure 3-3 • 256-Pin CCLG 3 -1 0 v2.2 RTSX-S RadTolerant FPGAs 256-Pin CCLG* Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 Note: External WireBond Number 1 256 255 251 243 238 232 228 227 221 216 209 203 200 2 13 242 22 254 253 248 241 234 33 222 220 212 207 202 198 32 196 6 4 RT54SX32S Function GND TCK, I/O I/O I/O I/O I/O I/O I/O CLKB I/O I/O I/O I/O I/O GND GND I/O GND I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O GND I/O I/O TDI,I/O Note: Pin Number C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 256-Pin CCLG* External WireBond Number 65 252 249 245 239 230 226 218 210 201 197 211 178 195 12 8 10 7 250 244 237 229 217 208 206 199 205 173 190 188 16 15 9 11 RT54SX32S Function GND I/O I/O I/O I/O I/O CLKA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O *This table was sorted by the pin number. *This table was sorted by the pin number. v2.2 3-11 RTSX-S RadTolerant FPGAs 256-Pin CCLG* Pin Number E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 Note: External WireBond Number 5 240 233 231 223 219 213 167 183 189 187 186 17 18 20 14 19 28 3 23 44 55 157 97 177 185 184 181 24 25 27 26 21 66 RT54SX32S Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O VCCI VCCI VCCI VCCI I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI Note: Pin Number G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 256-Pin CCLG* External WireBond Number 43 54 67 77 87 169 180 176 179 175 29 31 160 35 37 108 86 96 107 118 128 165 170 168 166 174 30 38 40 41 39 139 127 140 RT54SX32S Function GND GND GND GND VCCI I/O GND I/O VCCA I/O I/O I/O VCCA TRST I/O VCCI GND GND GND GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND GND *This table was sorted by the pin number. *This table was sorted by the pin number. 3 -1 2 v2.2 RTSX-S RadTolerant FPGAs 256-Pin CCLG* Pin Number J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 Note: External WireBond Number 151 161 150 159 163 164 162 158 34 45 47 50 48 171 172 182 192 204 191 153 155 156 152 154 36 46 51 58 52 91 194 214 235 246 RT54SX32S Function GND GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O VCCI GND GND GND GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCI VCCI VCCI Note: Pin Number L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 256-Pin CCLG* External WireBond Number 103 149 146 148 145 147 42 53 61 60 72 81 89 95 101 105 114 111 141 142 137 144 49 57 63 79 70 76 83 99 109 117 112 124 RT54SX32S Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O *This table was sorted by the pin number. *This table was sorted by the pin number. v2.2 3-13 RTSX-S RadTolerant FPGAs 256-Pin CCLG* Pin Number N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 Note: External WireBond Number 121 133 135 136 59 138 56 74 64 82 90 94 104 113 119 123 143 131 132 134 62 215 68 73 78 85 92 98 100 106 115 120 126 130 RT54SX32S Function I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O HCLK I/O I/O I/O I/O I/O Note: Pin Number R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 256-Pin CCLG* External WireBond Number 225 193 236 69 71 75 80 84 88 93 224 102 110 116 122 125 129 247 RT54SX32S Function GND GND GND I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O TDO,I/O GND *This table was sorted by the pin number. *This table was sorted by the pin number. 3 -1 4 v2.2 RTSX-S RadTolerant FPGAs 256-Pin CCLG* Pin Number A1 A15 F7 C2 E5 C1 D4 D2 E3 D3 E4 D1 A16 F4 E2 E1 F1 F2 F5 F3 G5 B2 F8 G1 G2 G4 G3 F6 H1 J1 H2 B15 B8 K1 Note: External WireBond Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 RT54SX32S Function GND GND VCCI TDI,I/O I/O I/O I/O I/O I/O I/O I/O I/O GND TMS I/O I/O I/O I/O I/O I/O I/O GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA I/O Note: Pin Number H4 L1 H5 J2 J5 J3 J4 M1 G7 F9 K2 L2 K3 K5 N1 K4 L3 L5 M2 G8 F10 P3 N2 L4 P1 M4 M3 R1 N3 P5 C3 G6 G9 R3 256-Pin CCLG* External WireBond Number 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 RT54SX32S Function TRST I/O I/O I/O I/O I/O I/O I/O GND VCCI I/O I/O I/O I/O I/O VCCA I/O I/O I/O GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCI GND I/O *This table was sorted by the wire-bond number. *This table was sorted by the wire-bond number. v2.2 3-15 RTSX-S RadTolerant FPGAs 256-Pin CCLG* Pin Number T2 N5 T3 M5 R4 P4 T4 N6 G10 R5 N4 T5 M6 P6 N7 T6 R6 H7 G11 T7 M7 P7 L6 R7 T8 P8 M8 H8 F12 R8 N8 R9 M9 T10 Note: External WireBond Number 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 RT54SX32S Function I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCCI I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCA I/O I/O HCLK I/O I/O Note: Pin Number L11 P9 M10 R10 H9 H6 N9 T11 M12 N11 P10 M11 R11 T12 N10 H10 P11 R12 N13 T13 P12 N12 T14 R13 J7 H11 T15 R14 P14 P15 N14 P16 N15 N16 256-Pin CCLG* External WireBond Number 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 RT54SX32S Function I/O I/O I/O I/O GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCCI TDO,I/O I/O I/O I/O I/O I/O I/O I/O *This table was sorted by the wire-bond number. *This table was sorted by the wire-bond number. 3 -1 6 v2.2 RTSX-S RadTolerant FPGAs 256-Pin CCLG* Pin Number M15 P2 J6 J8 M13 M14 P13 M16 L15 L13 L16 L14 L12 J11 J9 K15 K12 K16 K13 K14 F11 J16 J12 H3 J10 J15 J13 J14 H12 H15 E12 H14 G12 H13 Note: External WireBond Number 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 RT54SX32S Function I/O GND VCCI GND I/O I/O VCCA I/O I/O I/O I/O I/O I/O VCCI GND I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O Note: Pin Number K6 K7 D14 H16 G16 G14 F13 C15 G15 G13 F16 K8 E13 F15 F14 E16 E15 D16 E14 D15 K11 K9 R16 L7 C16 B16 C13 B14 D12 A14 C12 B13 A13 K10 256-Pin CCLG* External WireBond Number 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 RT54SX32S Function VCCI GND I/O I/O I/O I/O I/O I/O VCCA GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O GND *This table was sorted by the wire-bond number. *This table was sorted by the wire-bond number. v2.2 3-17 RTSX-S RadTolerant FPGAs 256-Pin CCLG* Pin Number D13 D11 B12 D10 A12 C11 C14 B11 E11 L8 R2 A11 D9 C10 E10 B10 A10 B9 E9 T9 R15 C9 A9 A8 D8 C8 E8 A7 E7 B7 L9 T1 D7 A6 Note: External WireBond Number 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 RT54SX32S Function I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND CLKA CLKB I/O PRA, I/O I/O I/O I/O I/O I/O VCCI GND I/O I/O Note: Pin Number C7 E6 B6 B1 A5 D6 C6 L10 T16 B5 C5 D5 A4 C4 B4 B3 A3 A2 256-Pin CCLG* External WireBond Number 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 RT54SX32S Function I/O I/O I/O I/O I/O I/O I/O VCCI GND I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O *This table was sorted by the wire-bond number. *This table was sorted by the wire-bond number. 3 -1 8 v2.2 RTSX-S RadTolerant FPGAs 624-Pin CCGA 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE Figure 3-4 • 624-Pin CCGA (Bottom View) v2.2 3-19 RTSX-S RadTolerant FPGAs 624-Pin CCGA Pin Number A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 RT54SX72S Function NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND NC NC NC NC GND GND VCCI GND I/O I/O VCCI GND I/O I/O 624-Pin CCGA Pin Number B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 RT54SX72S Function I/O I/O CLKB, I/O I/O I/O I/O I/O I/O I/O I/O GND VCCI GND NC NC VCCI GND I/O I/O I/O I/O I/O I/O I/O QCLKC, I/O I/O PRA, I/O CLKA, I/O I/O I/O I/O I/O I/O I/O I/O 624-Pin CCGA Pin Number C22 C23 C24 C25 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 E1 E2 E3 E4 E5 E6 RT54SX72S Function I/O GND VCCI NC GND GND TDI GND I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKD, I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND GND GND I/O I/O I/O I/O TCK, I/O I/O 3 -2 0 v2.2 RTSX-S RadTolerant FPGAs 624-Pin CCGA Pin Number E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 RT54SX72S Function I/O I/O I/O I/O I/O VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O NC NC I/O NC NC NC NC I/O I/O NC GND 624-Pin CCGA Pin Number F17 F18 F19 F20 F21 F22 F23 F24 F25 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 H1 RT54SX72S Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O I/O VCCI NC NC NC NC NC NC NC NC NC NC GND VCCI I/O I/O I/O I/O I/O I/O I/O 624-Pin CCGA Pin Number H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 RT54SX72S Function I/O I/O I/O I/O I/O I/O VCCI NC NC NC NC NC NC NC NC NC VCCI I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O NC NC VCCI NC NC v2.2 3-21 RTSX-S RadTolerant FPGAs 624-Pin CCGA Pin Number J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 RT54SX72S Function NC NC NC NC NC VCCI NC NC I/O VCCA I/O I/O I/O I/O I/O GND I/O I/O I/O GND NC NC NC GND GND GND GND GND GND GND NC NC NC I/O I/O 624-Pin CCGA Pin Number K22 K23 K24 K25 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 M1 M2 M3 M4 M5 M6 RT54SX72S Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC GND GND GND GND GND GND GND NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O 624-Pin CCGA Pin Number M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 RT54SX72S Function NC NC NC GND GND GND GND GND GND GND NC NC NC I/O GND I/O I/O GND I/O I/O I/O I/O I/O VCCA I/O VCCA NC NC GND GND GND GND GND GND GND 3 -2 2 v2.2 RTSX-S RadTolerant FPGAs 624-Pin CCGA Pin Number N17 N18 N19 N20 N21 N22 N23 N24 N25 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 R1 RT54SX72S Function NC NC VCCA I/O VCCA I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O NC NC NC GND GND GND GND GND GND GND NC NC NC I/O GND I/O I/O I/O I/O I/O 624-Pin CCGA Pin Number R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 RT54SX72S Function I/O I/O TRST I/O GND NC NC NC GND GND GND GND GND GND GND NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC GND GND 624-Pin CCGA Pin Number T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 RT54SX72S Function GND GND GND GND GND NC NC NC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VCCI NC NC NC NC NC NC NC VCCI NC NC I/O I/O v2.2 3-23 RTSX-S RadTolerant FPGAs 624-Pin CCGA Pin Number U22 U23 U24 U25 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 W1 W2 W3 W4 W5 W6 RT54SX72S Function I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O GND VCCI NC NC NC NC NC NC NC NC NC VCCI I/O I/O I/O VCCA I/O I/O I/O I/O VCCI I/O I/O I/O I/O 624-Pin CCGA Pin Number W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 RT54SX72S Function VCCI NC NC NC NC NC NC NC NC NC NC I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC GND I/O NC GND I/O 624-Pin CCGA Pin Number Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AB1 RT54SX72S Function I/O I/O I/O I/O I/O I/O I/O GND I/O GND GND I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND NC 3 -2 4 v2.2 RTSX-S RadTolerant FPGAs 624-Pin CCGA Pin Number AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 RT54SX72S Function VCCI I/O GND I/O I/O I/O I/O I/O I/O I/O QCLKA, I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO, I/O VCCI I/O VCCI NC NC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O 624-Pin CCGA Pin Number AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 RT54SX72S Function PRB, I/O I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O GND I/O NC NC GND VCCI GND I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O 624-Pin CCGA Pin Number AD22 AD23 AD24 AD25 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 RT54SX72S Function GND VCCI GND NC NC NC NC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKB, I/O I/O I/O I/O I/O I/O I/O I/O GND NC NC NC v2.2 3-25 RTSX-S RadTolerant FPGAs Datasheet Information List of Changes The following table lists critical changes that were made to the current version of the document. Previous version Changes in current version (v2 . 2) v2.1 v2.0 Advanced v1.6 The "Ordering Information" was updated. In Table 2-13, the IOH = –20µA and IOL = ±20µA. Maximum user I/O in "RTSX-S Product Profile" was updated for the RT54SX72S. Table 2-4 was updated. The "Power Dissipation" section is new. The "Thermal Characteristics" section is new. Table 2-8 was updated. The "Timing Model" was updated. The "User I/O" section is new. Table 2-11 and Table 2-12 were updated. Table 2-14 and Table 2-15 were updated. Table 2-18 and Table 2-19 were updated. Table 2-22 and Table 2-23 were updated. The "Module Specifications"section is new. The "Routing Specifications" section is new. The "Global Resources" section is new. QCLK timing data added to Table 2-26 and Table 2-27 The "Other Architectural Features" section is new. Table 2-34 was updated. "208-Pin CQFP" pin table for RT54SX72S was updated. "256-Pin CQFP" pin table for RT54SX72S was updated. "624-Pin CCGA" pin table for RT54SX72S was updated. Page 1-ii 2-14 1-i 2-2 2-2 2-4 2-5 2-6 2-8 2-12, 2-13 2-14, 2-15 2-18, 2-18 2-21, 2-21 2-22 2-27 2-29 2-30, 2-31 2-35 2-36 3-1 3-5 3-19 v2.2 4-1 RTSX-S RadTolerant FPGAs Previous version Changes in current version (v2 . 2) Advanced v1.5 The “RTSX-S Product Profile” were updated. The “Clock Resources” section was updated. “I/O Modules” was updated. The “RTSX-S Timing Model” figure was updated. The “Input Buffer Delays” figure was updated. The “RTSX-S Timing Model” section on page 23 was updated. The Timing Characteristics were updated on the following pages. Advanced v1.4 The “RTSX-S Product Profile” table on page 1 was updated. The “Ordering Information” section on page 2 was updated. The “Product Plan” table on page 2 was updated. The “Ceramic Device Resources” table on page 2 was updated. The “SEU Hardened DFF Description” section on page 3 was updated. The “Power Cycling” section on page 12 is new. The “Actel MIL-STD-883 Class B Product Flow” table on page 20 was updated. The “Actel Extended Flow1” table on page 21 was updated. The “256-Pin CCLG*” table on page 45 is new. Advanced v1.3 Advanced v1.2.3 On the CQ208 package for the RT54SX72S, pin 13, the function is I/O and not VCCI. The “RTSX-S Product Profile” table on page 1 table has been updated. The “Ceramic Device Resources” section on page 2 The “Clock Resources” section on page 7 has been updated. Table 1 on page 9 is new. The “I/O Modules” section on page 10 and have been updated. Table 2 on page 10 has been updated. The “Hot Swapping” section on page 10 has been updated. Table 3 on page 11 is new. Table 4 on page 11 has been updated. The “Development Tool Support” section on page 13 has been updated. The “Design Considerations” section on page 14 has been updated. The “Pin Description” section on page 37 has been updated. The CG624 (Bottom View) on page 50 is new. Advanced v1.1.2 The “DC Specifications (3.3V PCI Operation)” section on page 18 was updated. Page page 1 page 7 page 10 page 23 page 24 page 23 25–27, 31–32 page 1 page 2 page 2 page 2 page 3 page 12 page 20 page 21 page 45 page 37 page 1 page 2 page 7 page 7 page 10 page 10 page 10 page 11 page 11 page 13 page 14 page 37 page 50 page 18 4 -2 v2.2 RTSX-S RadTolerant FPGAs Previous version Changes in current version (v2 . 2) Advanced v0.3 The “Programmable Interconnect Element” section on page 5 has been updated. The “I/O Modules” section on page 10 and Table 2 The “Boundary Scan Testing (BST)” section on page 12 has been updated. The “Dedicated Mode” section on page 12 has been updated. The “Flexible Mode” section on page 12 has been updated. Table 7 on page 13 was changed. The “TRST Pin” section on page 13 has been updated. The “Probing Capabilities” section on page 13 has been updated. Table 8 on page 13 is new. The “Development Tool Support” section on page 13 was changed. The “Recommended Operating Conditions” section on page 14 has been updated. The “3.3V LVTTL and 5V TTL Electrical Specifications” table on page 15 was changed. The “5V CMOS Electrical Specifications” table on page 15 is new. The “5V PCI Compliance for the RTSX-S Family” table on page 16 The “Actel MIL-STD-883 Class B Product Flow” table on page 20 has been updated. The “Actel Extended Flow1” table on page 21 has been updated. Page page 5 page 10 page 12 page 12 page 12 page 13 page 13 page 13 page 13 page 13 page 14 page 15 page 15 page 16 page 20 page 21 page 23 page 37 2 8 9-11 The “RTSX-S Timing Model” table on page 23 and the “Hard-Wired Clock” equation were updated. The “Pin Description” section on page 37 was updated. Advanced v0.2 The “Product Plan” table on page 2 has been updated. The “Clock Resources” table on page 7 has been updated. The “Performance” table on page 9, “I/O Modules” table on page 10, “Hot Swapping” table on page 10, “Boundary Scan Testing (BST)” table on page 12, “TRST Pin” table on page 13, “Development Tool Support” table on page 13, and “RTSX-S Probe Circuit Control Pins” table on page 13 have changed. The “Absolute Maximum Ratings*” table on page 14 and “Recommended Operating Conditions” table on page 14 have been updated. The “3.3V LVTTL and 5V TTL Electrical Specifications” table on page 15 and “5V CMOS Electrical Specifications” table on page 15 are new. The “RTSX-S Timing Model” on page 23 was updated. New slew rates were added to the “RT54SX32S Timing Characteristics” on page 30, page 31, and page 36. 11 12 22 29, 30, 35 v2.2 4-3 RTSX-S RadTolerant FPGAs Previous version Changes in current version (v2 . 2) Advanced v0.1.1 The TRSTB pin was incorrectly named and changed to TRST. In the “RTSX-S Product Profile” table on page 1, the User I/Os have changed. In the “Ceramic Device Resources” table on page 2, the User I/Os have changed. The Clock Networks section has changed to “Clock Resources” table on page 7. The “TRST Pin” table on page 13 has changed. The“Design Considerations” table on page 14 Design Considerations section has changed. In the “2.5V/3.3V/5V Operating Conditions” table on page 14 section, the “Absolute Maximum Ratings*” table on page 14 changed. The IIO row containing the I/O Source Sink Current was deleted. Equation 2 in the “Junction Temperature (TJ)” table on page 22 was corrected. Note that the “Package Characteristics and Mechanical Drawings” section has been eliminated from the data sheet. The mechanical drawings are now contained in a separate document, “Package Characteristics and Mechanical Drawings,” available on the Actel web site. Page All 1 2 8 10 11 12 15 4 -4 v2.2 RTSX-S RadTolerant FPGAs Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. Datasheet Supplement The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families. v2.2 4-5 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Actel Europe Ltd. Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 (0) 1276 401 450 Fax +44 (0) 1276 401 490 Actel Japan EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 Actel Hong Kong 39th Floor, One Pacific Place 88 Queensway, Admiralty Hong Kong Phone +852.227.35712 Fax +852.227.35999 5172151-11/11.04