RTAX250-SS624E

v5.3 RTAX-S/SL RadTolerant FPGAs Radiation Performance • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case Geosynchronous Orbit Expected SRAM Upset Rate of 117 MeVcm2/mg TM1019 Test Data Available Single Event Transient (SET) – No Anomalies up to 150 MHz Leading-Edge Performance • • • • High-Performance Embedded FIFOs 350+ MHz System Performance 500+ MHz Internal Performance 700 Mb/s LVDS Capable I/Os • Specifications • • • • • • Up to 4 Million Equivalent System Gates or 500 k Equivalent ASIC Gates Up to 20,160 SEU-Hardened Flip-Flops Up to 840 I/Os Up to 540 kbits Embedded SRAM Manufactured on Advanced 0.15 μm CMOS Antifuse Process Technology, 7 Layers of Metal Electrostatic Discharge (ESD) is 2,000 V (HBM MIL-STD-883, TM3015) • • • • Processing Flows • • • B-Flow – MIL-STD-883B E-Flow – Actel Extended Flow EV-Flow – Class V Equivalent Flow Processing Consistent with MIL-PRF 38535 Features • • • Single-Chip, Nonvolatile Solution 1.5 V Core Voltage for Low Power Flexible, Multi-Standard I/Os: – 1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation – Bank-Selectable I/Os – 8 Banks per Chip – Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3 V PCI – JTAG Boundary Scan Testing (as per IEEE 1149.1) – Differential I/O Standards: LVPECL and LVDS – Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 – Hot-Swap Compliant with Cold-Sparing Support (Except PCI) Embedded Memory with Variable Aspect Ratio and Organizations: – Independent, Width-Configurable Read and Write Ports – Programmable Embedded FIFO Control Logic – ROM Emulation Capability Deterministic, User-Controllable Timing Unique In-System Diagnostic and Debug Capability Prototyping Options • • Commercial Axcelerator Devices for Functional Verification RTAX-S PROTO Devices with Same Functional and Timing Characteristics as Flight Unit in a Non-Hermetic Package • RTAX-SL Low Power Option • Offers Approximately Half the Standby Current of the Standard RTAX-S Device at Worst-Case Conditions • • Table 1 • RTAX-S/SL Family Product Profile Device Capacity Equivalent System Gates ASIC Gates Modules Register (R-cells) Combinatorial (C-cells) Flip-Flops (maximum) Embedded RAM/FIFO (without EDAC) Core RAM Blocks Core RAM Bits (K = 1,024) Clocks (segmentable) Hardwired Routed I/Os I/O Banks User I/Os (maximum) I/O Registers Package CCGA/LGA CQFP RTAX250S/SL 250,000 30,000 1,408 2,816 2,816 12 54 k 4 4 8 198 744 – 208, 352 RTAX1000S/SL 1,000,000 125,000 6,048 12,096 12,096 36 162 k 4 4 8 418 1,548 624 352 RTAX2000S/SL 2,000,000 250,000 10,752 21,504 21,504 64 288 k 4 4 8 684 2,052 624, 1152 256, 352 RTAX4000S 4,000,000 500,000 20,160 40,320 40,320 120 540 k 4 4 8 840 2,520 1272 352 October 2008 © 2008 Actel Corporation i See the Actel website for the latest version of the datasheet. All RTAX4000S information is preliminary. RTAX-S/SL RadTolerant FPGAs Ordering Information RTAX2000S/SL _ 1 CGS 624 B Application B = MIL-STD 883 Class B E = E-Flow (Actel Space-Level Flow) EV = Class V Equivalent Flow Processing Consistent with MIL-PRF 38535 Package Lead Count Package Type CQ = Ceramic Quad Flat Pack CG = Ceramic Column Grid Array LG = Land Grid Array S = Six Sigma Column B = BAE Column Speed Grade Blank = Standard Speed 1 = Approximately 15% Faster than Standard Part Number S = Standard Family SL = Low-Power Option RTAX250S/SL = 250,000 Equivalent System Gates RTAX1000S/SL = 1,000,000 Equivalent System Gates RTAX2000S/SL = 2,000,000 Equivalent System Gates RTAX4000S = 4,000,000 Equivalent System Gates Note: PROTO refers to the RTAX-S/SL Prototype Units. All CCGA PROTO units will be offered with the Six Sigma Column. Temperature Grade Offerings Package CQ208 CQ256 CQ352 CG624*/LG624 CG1152/LG1152 CG1272/LG1272 RTAX250S/SL B, E, EV – B, E, EV – – – RTAX1000S/SL – – B, E, EV B, E, EV – – RTAX2000S/SL – B, E, EV B, E, EV B, E, EV B, E, EV – RTAX4000S – – B, E, EV – – B, E, EV Note: *Indicates that the CG624 package will be offered as CGS624 for the Six Sigma column and CGB624 for the BAE column. The other CCGA offerings (1152 and 1272) will be offered as Six Sigma columns. B = MIL-STD-883 Class B E = E-Flow (Actel Space-Level Flow) EV = Actel "V" Equivalent Flow (Class V processing consistent with MIL-PRF 38535) ii v5.3 RTAX-S/SL RadTolerant FPGAs Speed Grade and Temperature Grade Matrix Std B E EV ✓ ✓ ✓ –1 ✓ ✓ ✓ Contact your local Actel representative for device availability. Device Resources Device CQ208 CQ256 CQ352 CG624/LG624 CG1152/LG1152 CG1272/LG1272 User I/Os (Including Clock Buffers) RTAX250S/SL RTAX1000S/SL RTAX2000S/SL 115 – – – – 138 198 198 198 – 418 418 – – 684 – – – RTAX4000S – – 166 – – 840 Note: CQFP = Ceramic Quad Flat Pack and CCGA = Ceramic Column Grid Array, LGA = Land Grid Array v5.3 iii RTAX-S/SL RadTolerant FPGAs Actel MIL-STD-883 Class B Product Flow Table 2 • Actel MIL-STD-883 Class B Product Flow for RTAX-S/SL1, 2 Step 1 2 3 4 Internal Visual Serialization Temperature Cycling Constant Acceleration 1010, Condition C, 10 cycles minimum 2001, Y1 Orientation Only Condition B for CQ352, LG624, LG1152 Condition D for CQ208 TBD for LG1272 2020, Condition A 1014 In accordance specification with applicable Actel device Screen 2010, Condition B Method Requirement 100% 100% 100% 100% 5 6 7 8 9 10 11 Particle Impact Noise Detection Seal (Fine & Gross Leak Test) Pre-Burn-In Electrical Parameters Dynamic Burn-In Interim (Post-Burn-In) Electrical Parameters Percent Defective Allowable (PDA) Calculation Final Electrical Test 2 100% 100% 100% 100% 100% All Lots device 100% 1015, Condition D, 160 hours at 125°C or 80 hours at 150°C minimum In accordance specification 5% In accordance with applicable Actel specification, which includes a, b, and c: 5005, Table 1, Subgroup 1 5005, Table 1, Subgroup 2, 3 with applicable Actel device a. Static Tests (1) 25°C (2) –55°C and +125°C b. Functional Tests (1) 25°C (2) –55°C and +125°C c. Switching Tests at 25°C 12 Notes: External Visual 5005, Table 1, Subgroup 7 5005, Table 1, Subgroup 8a, 8b 5005, Table 1, Subgroup 9 2009 100% 1. For CCGA devices, all Assembly, Screening, and TCI testing are performed at LGA level. Only QA electrical and mechanical visual are performed after solder column attachment. 2. RTAX-S and RTAX-SL devices have the same silicon and are distinguished by screening the ICCA current limits at 125°C final electrical test. iv v5.3 RTAX-S/SL RadTolerant FPGAs Actel Extended Flow Table 3 • Actel Extended Flow for RTAX-S/SL 1, 2, 3, 4 Step 1 2 3 4 5 Destructive Bond Pull Internal Visual Serialization Temperature Cycling Constant Acceleration 1010, Condition C, 10 cycles minimum 2001, Y1 Orientation Only Condition B for CQ352, LG624, LG1152 Condition D for CQ208 TBD for LG1272 2020, Condition A 2012, One View (Y1 Orientation) Only In accordance specification with applicable Actel device 100% 100% 100% Screen 5 Method 2011, Condition D 2010, Condition A Requirement Extended Sample 100% 100% 100% 6 7 8 9 Particle Impact Noise Detection Radiographic (X-Ray) Pre-Burn-In Electrical Parameters Dynamic Burn-In 1015, Condition D, 240 hours at 125°C or 120 hours at 150°C minimum Electrical In accordance specification with applicable Actel device 10 11 12 13 14 Interim (Post-Dynamic-Burn-In) Parameters Static Burn-In 100% 100% 100% All Lots 100% 1015, Condition C, 72 hours at 150°C or 144 hours at 125°C minimum In accordance specification with applicable Actel device Interim (Post-Static-Burn-In) Electrical Parameters Percent Defective Allowable (PDA) Calculation Final Electrical Test 4 5% Overall, 3% Functional Parameters at 25°C In accordance with applicable Actel specification, which includes a, b, and c: 5005, Table 1, Subgroup 1 5005, Table 1, Subgroup 2, 3 device a. Static Tests (1) 25°C (2) –55°C and +125°C b. Functional Tests (1) 25°C (2) –55°C and +125°C c. Switching Tests at 25°C 15 16 Notes: Seal (Fine & Gross Leak Test) External Visual 5005, Table 1, Subgroup 7 5005, Table 1, Subgroup 8a, 8b 5005, Table 1, Subgroup 9 1014 2009 100% 100% 1. Actel offers Extended Flow for users requiring additional screening beyond MIL-STD-833, Class B requirement. Actel is offering this Extended Flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S. 2. The Quality Conformance Inspection (QCI) for Extended Flow devices still comply to MIL-STD-833, Class B requirement. 3. For CCGA devices, all Assembly/Screening/TCI testing are performed at LGA level. Only QA electrical and mechanical visual are performed after solder column attachment. 4. RTAX-S and RTAX-SL devices have the same silicon and are distinguished by screening the ICCA current limits at 125°C final electrical test. 5. Requirement for 100% nondestructive bond pull per Method 2003 is substituted by an extensive destructive bond pull to Method 2011 Condition D on an extended sample basis. v5.3 v RTAX-S/SL RadTolerant FPGAs Actel "EV" Flow (Class V Flow Equivalent Processing) Table 4 • Actel "EV" Flow (Class V Equivalent Flow Processing) for RTAX-S/SL1, 2, 3 Step 1 2 3 4 5 Destructive Bond Pull Internal Visual Serialization Temperature Cycling Constant Acceleration 1010, Condition C, 50 cycles minimum 2001, Y1 Orientation Only Condition B for CQ352, LG624, LG1152 Condition D for CQ208 TBD for LG1272 2020, Condition A 2012, One View (Y1 Orientation) Only In accordance specification with applicable Actel device Screen 4 Method 2011, Condition D 2010, Condition A Requirement Extended Sample 100% 100% 100% 100% 6 7 8 9 Particle Impact Noise Detection Radiographic (X-Ray) Pre-Burn-In Electrical Parameters Dynamic Burn-In 100% 100% 100% 100% 1015, Condition D, 240 hours at 125°C or 120 hours at 150°C minimum with applicable Actel device 10 11 12 13 14 Interim (Post-Dynamic-Burn-In) Electrical Parameters In accordance specification Static Burn-In Interim (Post-Static-Burn-In) Electrical Parameters Percent Defective Allowable (PDA) Calculation Final Electrical Test 3 100% 100% 100% All Lots 100% 1015, Condition C, 72 hours at 150°C or 144 hours at 125°C minimum In accordance specification with applicable Actel device 5% Overall, 3% Functional Parameters at 25°C In accordance with applicable Actel specification, which includes a, b, and c: 5005, Table 1, Subgroup 1 5005, Table 1, Subgroup 2, 3 device a. Static Tests (1) 25°C (2) –55°C and +125°C b. Functional Tests (1) 25°C (2) –55°C and +125°C c. Switching Tests at 25°C 15 16 17 Notes: Seal (Fine & Gross Leak Test) External Visual Wafer Lot Specific Life Test (Group C) 5005, Table 1, Subgroup 7 5005, Table 1, Subgroup 8a, 8b 5005, Table 1, Subgroup 9 1014 2009 MIL-PRF-38535, Appendix B, sec. B.4.2.c 100% 100% All Wafer Lots 1. Actel offers "EV" flow for users requiring full compliance to MIL-PRF-38535 class V requirement. The "EV" process flow is expanded from the existing E-flow requirement (it still meets the full SMD requirement for current E-flow devices) with the intention to be in full compliance to MIL-PRF-38535 Table IA and Appendix B requirement, but without the official class V certification from DSCC. 2. For CCGA devices, all Assembly/Screening/TCI testing are performed at LGA level. Only QA electrical and mechanical visual are performed after solder column attachment. 3. RTAX-S and RTAX-SL devices have the same silicon and are distinguished by screening the ICCA current limits at 125°C final electrical test. 4. Requirement for 100% nondestructive bond pull per Method 2003 is substituted by an extensive destructive bond pull to Method 2011 Condition D on an extended sample basis. vi v5.3 RTAX-S/SL RadTolerant FPGAs Table of Contents General Description Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Programmable Interconnect Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Low-Cost Prototyping Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 In-System Diagnostic and Debug Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Detailed Specifications Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44 Routing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52 Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84 Package Pin Assignments 208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 352-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 624-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 1152-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 1272-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 International Traffic in Arms Regulations (ITAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 v 5.3 vii RTAX-S/SL RadTolerant FPGAs General Description RTAX-S/SL offers high performance at densities of up to two million equivalent system gates for space-based applications. Based upon the Actel commercial Axcelerator® family, RTAX-S/SL has several system-level features such as embedded SRAM (with built-in FIFO control logic), segmentable clocks, chip-wide highway routing, and carry logic. Featuring SEU-hardened flip-flops that offer the benefits of user-implemented Triple Module Redundancy (TMR) without the associated overhead, the RTAX-S/SL family is the second generation Actel product offering for space applications. The RTAX-S/SL devices are manufactured using a 0.15 µm technology at a UMC facility in Taiwan. These devices offer levels of radiation survivability far in excess of typical CMOS devices. the entire floor of the RTAX-S/SL device is covered with a grid of logic modules, with virtually no chip area lost to interconnect elements or routing. Programmable Interconnect Element The RTAX-S/SL family uses a patented metal-to-metal antifuse programmable interconnect element that resides between the upper two layers of metal (Figure 1-2 on page 1-2). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on traditional FPGAs) and enables the efficient sea-of-modules architecture. The antifuses are normally open circuit and, when programmed, form a permanent, passive, lowimpedance connection, leading to the fastest signal propagation in the industry. In addition, the extremely small size of these interconnect elements gives the RTAX-S family abundant routing resources. Device Architecture Actel RTAX-S/SL architecture, derived from the highlysuccessful A54SX-A sea-of-modules architecture, has been designed for high performance and total logic module utilization (Figure 1-1). Unlike traditional FPGAs, Routing Switch Matrix Logic Block Sea-of-Modules Architecture Traditional FPGA Architecture Logic Modules Figure 1-1 • Sea-of-Modules Comparison v5.3 1-1 RTAX-S/SL RadTolerant FPGAs Figure 1-2 • RTAX-S/SL Family Interconnect Elements The very nature of Actel's nonvolatile antifuse technology provides excellent protection against design pirating and cloning (FuseLock® technology). Cloning is impossible (even if the security fuse is left unprogrammed) as no bitstream or programming file is ever downloaded or stored in the device. Reverse engineering is virtually impossible due to the difficulty of trying to distinguish between programmed and unprogrammed antifuses and also due to the programming methodology of antifuse devices (see "Security" on page 2-83). Actel's RTAX-S/SL family provides two types of logic modules: the register cell (R-cell) and the combinatorial cell (C-cell). The RTAX-S/SL C-cell can implement more than 4,000 combinatorial functions of up to five inputs (Figure 1-3 on page 1-3). The C-cell contains carry logic for even more efficient implementation of arithmetic functions. With its small size, the C-cell structure is extremely synthesis-friendly, simplifying the overall design as well as reducing design time. While each SEU-hardened R-cell appears as a single D-Type flip-flop to the user, each is implemented in silicon using triple redundancy to achieve a LET threshold of greater than 60 MeV-mg/cm2. Each TMR R-cell consist of three master-slave latch pairs, each with asynchronous self-correcting feedback paths. The output of each latch on the master or slave side votes with the outputs of the other two latches on that side. If one of the three latches is struck by an ion and starts to change state, the voting with the other two latches prevents that change from feeding back and permanently latching. Care was also taken in the layout to ensure that a single ion strike could not affect more than one latch (see "R-Cell" on page 2-48 for more details). The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and active-low enable control signals (Figure 1-3 on page 1-3). The R-cell registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional flexibility (e.g., easy mapping of dual-data-rate functions into the FPGA) while conserving valuable clock resources. The clock source for the R-cell can be chosen from the hardwired clocks, routed clocks, or internal logic. Two C-cells, a single R-cell, and two Transmit (TX) and two Receive (RX) routing buffers form a Cluster, while two Clusters comprise a SuperCluster (Figure 1-4 on page 1-3). Each SuperCluster also contains an independent Buffer (B) module, which supports buffer insertion on high-fanout nets by the place-and-route tool, minimizing system delays while improving logic utilization. The logic modules within the SuperCluster are arranged so that two combinatorial modules are side-by-side, giving a C–C–R – C–C–R pattern to the SuperCluster. This C–C–R pattern enables efficient implementation (minimum delay) of two-bit carry logic for improved arithmetic performance (Figure 1-5 on page 1-3). The RTAX-S/SL architecture is fully fracturable, meaning that if one or more of the logic modules in a SuperCluster are used by a particular signal path, the other logic modules are still available for use by other paths. 1 -2 v5.3 RTAX-S/SL RadTolerant FPGAs FCI A[0:1] B[0:1] D[0:3] DB CFN C-cell Y D E CLK PRE CLR Q (Positive Edge Triggered) FCO C-Cell Figure 1-3 • RTAX-S/SL C-Cell and R-Cell R-Cell TX TX RX B TX RX TX C C R RX RX C C R Figure 1-4 • RTAX-S/SL SuperCluster FCI DCOUT C-Cell Y C-Cell Y Carry Logic FCO Figure 1-5 • RTAX-S/SL Two-Bit Carry Logic v5.3 1-3 RTAX-S/SL RadTolerant FPGAs At the chip level, SuperClusters are organized into core tiles, which are arrayed to build up the full chip. For example, the RTAX1000S/SL is composed of a 3×3 array of nine core tiles. Surrounding the array of core tiles are blocks of I/O Clusters and the I/O bank ring (Table 1-1). Table 1-1 • Number of Core Tiles per Device Device RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S Each core tile consists of an array of 336 SuperClusters and four SRAM blocks (176 SuperClusters and three SRAM blocks for the RTAX250S/SL). The SRAM blocks are arranged in a column on the west side of the tile (Figure 1-6). Number of Core Tiles 4 smaller tiles 9 regular tiles 16 regular tiles 30 regular tiles SuperCluster C C R TX RX TX RX B TX RX TX RX C C R RAMC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC 4k RAM/ FIFO 4k RAM/ FIFO RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC HD RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC Chip Layout 4k RAM/ FIFO 4k RAM/ FIFO SC SC CoreSCTile I/O Structure Figure 1-6 • RTAX-S/SL Device Architecture (RTAX1000S/SL shown) 1 -4 v5.3 RTAX-S/SL RadTolerant FPGAs Embedded Memory As mentioned earlier, each core tile has either three (in a smaller tile) or four (in the regular tile) embedded SRAM blocks along the west side, and each variable-aspectratio SRAM block is 4,608 bits in size. Available memory configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or 4kx1 bits. The individual blocks have separate read and write ports that can be configured with different bit widths on each port. For example, data can be written in by eight and read out by one. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using core logic modules. The FIFO width and depth are programmable. The FIFO also features programmable ALMOST-EMPTY (AEMPTY) and ALMOST-FULL (AFULL) flags in addition to the normal EMPTY and FULL flags. In addition to the flag logic, the embedded FIFO control unit also contains the counters necessary for the generation of the read and write address pointers as well as control circuitry to prevent metastability and erroneous operation. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. The FIFO control unit was not implemented with SEUhardened registers. Designs requiring high SEU tolerance should implement the FIFO control unit from hardened core logic. SRAM structures are inherently susceptible to upsets caused by high-energy particles encountered in space. High-energy particles can cause an SRAM cell to change state, resulting in the loss or corruption of a valuable data bit. Actel has enhanced the SEU tolerance of the embedded SRAM within RTAX-S/SL by employing the use of two upset-mitigation techniques: • Actel has developed Error Detection and Correction (EDAC) IP for use with RTAX-S/SL. EDAC can be accomplished by the use of SmartGen-generated Error Correcting Codes (ECC) IP, which employs the use of shortened Hamming Codes A background memory-refresher, or scrubber circuitry, which has been embedded into the EDAC IP. The embedded scrubber circuitry periodically refreshes memory in the background to ensure that no data corruption occurs while the memory is not in use. I/O Logic The RTAX-S/SL family of FPGAs features a flexible I/O structure, supporting a range of mixed voltages with its bank-selectable I/Os: 1.5 V, 1.8 V, 2.5 V, and 3.3 V. In all, RTAX-S/SL FPGAs support at least 14 different I/O standards (single-ended, differential, voltagereferenced). The I/Os are organized into banks, with eight banks per device (two per side). The configuration of these banks determines the I/O standards supported (see "User I/Os" on page 2-12 for more information). All I/O standards are available in each bank. Each I/O module has an input register (InReg), an output register (OutReg), and an enable register (EnReg) (Figure 1-7 on page 1-6). An I/O Cluster includes two I/O modules, four RX modules, two TX modules, and a buffer (B) module. By design, all user flip-flops in the RTAX-S FPGAs are immune to SEUs including the following three registers located in every I/O cell buffer: InReg, OutReg, and EnReg. Routing The RTAX-S/SL hierarchical routing structure ties the logic modules, the embedded memory blocks, and the I/O modules together (Figure 1-8 on page 1-6). At the lowest level, in and between SuperClusters, there are three local routing structures: FastConnect, DirectConnect, and CarryConnect routing. DirectConnects provide the highest performance routing inside the SuperClusters by connecting a C-cell to the adjacent R-cell. DirectConnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. FastConnects provide high-performance, horizontal routing inside the SuperCluster and vertical routing to the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering a maximum routing delay of 0.4 ns. CarryConnects are used for routing carry logic between adjacent SuperClusters. They connect the carry-logic FCO output of one C-cell pair to the carry-logic FCI input of the C-cell pair of the SuperCluster below. CarryConnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. The next level contains the core tile routing. Over the SuperClusters within a core tile, both vertical and horizontal tracks run across rows or columns, respectively. At the chip level, vertical and horizontal tracks extend across the full length of the device, both north-to-south and east-to-west. These tracks are composed of highway routing that extend the entire length of the device (segmented at core tile boundaries) as well as segmented routing of varying lengths. • The use of EDAC IP combined with the embedded memory scrubber circuitry, gives the RTAX-S/SL an SEU radiation performance level of better than 10-10 errors/ bit-day. See the application note Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs. v5.3 1-5 RTAX-S/SL RadTolerant FPGAs I/O Module InReg OutReg EnReg I O B A N K 4k RAM/ FIFO I/O Module 4k RAM/ FIFO TX RX RX B TX RX RX I/O Module I/O Cluster 4k RAM/ FIFO CoreTile 4k RAM/ FIFO Figure 1-7 • I/O Cluster Arrangement Figure 1-8 • RTAX-S/SL Routing Structures 1 -6 v5.3 RTAX-S/SL RadTolerant FPGAs Global Resources Each family member has three types of global signals available to the designer: HCLK, CLK, and GCLR/GPSET. There are four hardwired clocks (HCLK) per device that can directly drive the clock input of each R-cell. Each of the four routed clocks (CLK) can drive the clock, clear, preset, or enable pin of an R-cell or any input of a C-cell (Figure 1-3 on page 1-3). Global clear (GCLR) and global preset (GPSET) drive the clear and preset inputs of each R-cell as well as each I/O Register on a chip-wide basis at power-up. functions for implementation into your schematic or HDL design. Actel Designer software is compatible with the most popular FPGA design entry and verification tools from EDA vendors, such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. Programming Programming support is provided through Actel Silicon Sculptor 3, a single-site programmer driven via a PC-based GUI. Factory programming is available for highvolume production needs. Design Environment The RTAX-S/SL family of FPGAs is fully supported by both Actel Libero® Integrated Design Environment (IDE) and Designer FPGA Development software. Actel Libero IDE is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment (see the Libero IDE Flow diagram located on the Actel website). Libero IDE includes Synplify® AE from Synplicity®, ViewDraw® AE from Mentor Graphics®, ModelSim® HDL Simulator from Mentor Graphics, WaveFormer Lite™ AE from SynaptiCAD®, and Designer software from Actel. Actel's Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes the following: • Timer – a world-class integrated static timing analyzer and constraints editor which support timing-driven place-and-route NetlistViewer – a design netlist schematic viewer ChipPlanner – a graphical floorplanner viewer and editor SmartPower – allows the designer to quickly estimate the power consumption of a design PinEditor – a graphical application for editing pin assignments and I/O attributes I/O Attribute Editor – displays all assigned and unassigned I/O macros and their attributes in a spreadsheet format Low-Cost Prototyping Solutions Since the enhanced radiation characteristics of radiationtolerant devices are not required during the prototyping phase of the design, Actel has developed two prototyping options for RTAX-S/SL. For early design development and functional verification, Actel offers the commercial Axcelerator devices while for final flight design verification in hardware, Actel offers the RTAX-S PROTO device that has the same form, fit, and function as the flight silicon. Prototyping with Axcelerator Units The prototyping solution using the commercial Axcelerator devices consists of two parts: • A well-documented design flow that allows the customer to target an RTAX-S/SL design to the equivalent commercial Axcelerator device A set of Actel Extender circuit boards that map the commercial device package to the appropriate RTAX-S package footprint • • • • • • This methodology provides the user with a cost-effective solution while maintaining the short time-to-market associated with Actel FPGAs. Prototyping with RTAX-S PROTO Units The RTAX-S PROTO units offer a prototyping solution that can be used for final timing verification of the flight design. The RTAX-S PROTO prototype units have the same timing attributes as the RTAX-S/SL flight units. Prototype units are offered in non-hermetic ceramic packages. The prototype units include "PROTO" in their part number, and “PROTO” is marked on devices to indicate that they are not intended for space flight. They also are not intended for applications, which require the quality of space-flight units, such as qualification of space-flight hardware. RT-PROTO units offer no guarantee of hermeticity, and no MIL-STD-883B processing. At a minimum, users should plan on using class B level devices for all qualification activities. With the Designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. Additionally, the Actel backannotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, the Actel integrated verification and logic analysis tool. Another tool included in the Designer software is the SmartGen core generator, which easily creates popular and commonly used logic v5.3 1-7 RTAX-S/SL RadTolerant FPGAs The RT-PROTO units are electrically tested in a manner to guarantee their performance over the full military temperature range. The RT-PROTO units will also be offered in -1 or standard speed grades, so as to enable customers to validate the timing attributes of their space designs using actual flight silicon. Please see the application note Prototyping for RTAX-S and RTAX-SL Devices for more details. serial port of a PC and communicates with the FPGA via the JTAG port (See "Silicon Explorer II Probe Interface" on page 2-84). In addition, Actel offers a Configurable Logic Analyzer Module (CLAM), which allows a real-time verification and debug capability to be embedded into IP programmed into Actel FPGAs. CLAM allows signals from the inside of the IP core to be routed to the exterior of the chip for verification purposes. In-System Diagnostic and Debug Capabilities The RTAX-S/SL family of FPGAs includes internal probe circuitry, allowing the designer to dynamically observe and analyze any signal inside the FPGA without disturbing normal device operation. Up to four individual signals can be brought out to dedicated probe pins (PRA/B/C/D) on the device. The probe circuitry is accessed and controlled via Silicon Explorer II (Figure 1-9), the Actel integrated verification and logic analysis tool that attaches to the Summary The Actel RTAX-S/SL family of FPGAs extends the successful RTSX-SU family of radiation-tolerant FPGAs, adding embedded RAM, FIFOs, and high-speed I/Os. With the support of a suite of robust software tools, design engineers can incorporate high gate counts and fixed pins into an RTAX-S/SL design yet still achieve high performance and efficient device utilization in an SEUhardened device. 16-Pin Connection TDI* TCK* RTAX-S/SL FPGAs S erial Connection Silicon Explorer II TDO* PRA* PRB* TMS* 22-Pin Connection CH3/PRC* CH4/PRD* Additional 14 Channels (Logic Analyzer) Note: *Refer to the "Pin Descriptions" on page 2-11 for more information. Figure 1-9 • Probe Setup 1 -8 v5.3 RTAX-S/SL RadTolerant FPGAs Related Documents Application Notes Simultaneous Switching Noise and Signal Integrity http://www.actel.com/documents/SSN_AN.pdf Differences Between RTAX-S/SL and Axcelerator http://www.actel.com/documents/RTAXS_AX_Features_AN.pdf Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs http://www.actel.com/documents/EDAC_AN.pdf Prototyping for RTAX-S and RTAX-SL Devices http://www.actel.com/documents/PrototypingRTAXS_AN.pdf Implementation of Security in Actel Antifuse FPGAs http://www.actel.com/documents/Antifuse_Security_AN.pdf Actel CQFP to FBGA Adapter Socket Instructions http://www.actel.com/documents/CCGA_FBGA_AN.pdf Actel CCGA to FBGA Adapter Socket Instructions http://www.actel.com/documents/CQ352-FPGA_Adapter_AN.pdf IEEE Standard 1149.1 (JTAG) in the Axcelerator Family http://www.actel.com/documents/AX_JTAG_AN.pdf User’s Guides and Manuals Antifuse Macro Library Guide http://www.actel.com/documents/libguide_UG.pdf SmartGen, FlashROM, Analog System Builder, and Flash Memory System Builder User’s Guide http://www.actel.com/documents/smarttime_ug.pdf Silicon Sculptor User’s Guide http://www.actel.com/documents/SiliSculptII_Sculpt3_ug.pdf Silicon Explorer II User’s Guide http://www.actel.com/documents/Silexpl_UG.pdf White Papers Design Security in Nonvolatile Flash and Antifuse FPGAs http://www.actel.com/documents/DesignSecurity_WP.pdf Understanding Actel Antifuse Device Security http://www.actel.com/documents/AntifuseSecurityWP.pdf RTAX-S/SL Testing and Reliability Update http://www.actel.com/documents/RTAXS_Rel_Test_WP.pdf Miscellaneous Libero IDE flow diagram http://www.actel.com/products/software/libero/#flow v5.3 1-9 RTAX-S/SL RadTolerant FPGAs Detailed Specifications Table 2-1 • I/O Features Comparison I/O Assignment LVTTL 3.3 V PCI LVCMOS2.5 V LVCMOS1.8 V LVCMOS1.5 V (JESD8-11) Voltage-Referenced Input Buffer Differential, LVDS/LVPECL, Input Differential, LVDS/LVPECL, Output Notes: 1. Can be implemented with an external resistor. 2. The OE input of the output buffer is automatically deasserted by Designer. 3. The OE input of the output buffer is automatically asserted by Designer. Clamp Diode No Yes No No No No No No Hot Insertion / Cold Sparing Yes No Yes Yes Yes Yes Yes Yes 5V Tolerance No Yes 1 Input Buffer Output Buffer Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled Disabled Disabled2 Enabled3 No No No No No No 5 V Tolerance 3.3 V PCI is the only I/O standard that directly allows 5 V tolerance. This standard provides an internal clamp diode between the input pad, and the VCCI pad so that the voltage at the input pin is clamped as shown in EQ 2-1: Vinput = VCCI + Vdiode = 3.3 V + 0.8 V = 4.1 V EQ 2-1 An external series resistor (~100 Ω) is required between the input pin and the 5 V signal source to limit the current (Figure 2-1). Non-Actel Part 5V Actel FPGA 3.3 V PCI clamp diode . 3.3 V Rext PCI clamp diode Figure 2-1 • Use of an External Resistor for 5 V Tolerance v5.3 2-1 RTAX-S/SL RadTolerant FPGAs Operating Conditions Absolute Maximum Conditions Stresses beyond those listed in Table 2-2 may cause permanent damage to the device. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the recommended operating conditions in Table 2-3. Table 2-2 • Absolute Maximum Ratings Symbol VCCA VCCA VCCI VREF VI VO TSTG VCCDA2 Notes: 1. The AC transient VCCA limit is for radiation-induced transients less than 10 µs duration and not intended for repetitive use. Core voltage spikes from a single event transient will not negatively affect the reliability of the device if, for this non-repetitive event, the transient does not exceed 1.8 V at any time and the total time that the transient exceeds 1.575 V does not exceed 10 µs in duration. 2. VCCDA must be greater than or equal to the highest VCCI voltage Table 2-3 • RTAX-S/SL Recommended Operating Conditions Parameter Range Ambient Temperature (TA)1 1.5 V Core Supply Voltage 1.5 V I/O Supply Voltage 1.8 V I/O Supply Voltage 2.5 V I/O Supply Voltage 3.3 V I/O Supply Voltage 2.5 V VCCDA I/O Supply Voltage (no differential I/O used) 3.3 V VCCDA I/O Supply Voltage (differential or voltage-referenced I/O 3.3 V VPUMP Supply Voltage Notes: 1. Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades. 2. Please see "VCCDA Supply Voltage" on page 2-11 more detail. 3. Tj (max) = 125ºC. used)2 Military –55 to +125 1.425 to 1.575 1.425 to 1.575 1.71 to 1.89 2.375 to 2.625 3.0 to 3.6 2.375 to 2.625 3.0 to 3.6 3.0 to 3.6 Units °C V V V V V V V V Parameter AC Core Supply Voltage DC Core Supply Voltage DC I/O Supply Voltage DC I/O Reference Voltage Input Voltage Output Voltage Storage Temperature Supply Voltage for Differential I/Os 1 Limits –0.3 to 1.8 –0.3 to 1.7 –0.3 to 3.75 –0.3 to 3.75 –0.5 to 3.75 –0.5 to 3.75 –60 to +150 –0.3 to 3.75 Units V V V V V V °C V Overshoot/Undershoot Limits For AC signals, the input signal may undershoot during transitions to –1.0 V for no longer than 10% of the period or 11 ns (whichever is smaller). Current during the transition must not exceed 95 mA. For AC signals, the input signal may overshoot during transitions to VCCI + 1.0 V for no longer than 10% of the period or 11 ns (whichever is smaller). Current during the transition must not exceed 95 mA. Note: The above specification does not apply to the PCI standard. The RTAX-S/SL PCI I/Os are compliant to the PCI standard including the PCI overshoot/undershoot specifications. 2 -2 v5.3 RTAX-S/SL RadTolerant FPGAs Power-Up/Down Sequence VCCA, VCCI, and VCCDA can be powered up or powered down in any sequence. During power-up, all RTAX-S/SL I/Os are tristated until reaching the state defined by the design. Calculating Power Dissipation Table 2-4 • RTAX-S Standby Current Device RTAX4000S Temperature Typical 25ºC 125ºC RTAX2000S Typical 25ºC 125ºC RTAX1000S Typical 25ºC 125ºC RTAX250S Typical 25ºC 125ºC Notes: 1. 2. 3. 4. For calculating the leakage values, use a pull-down/pull-up resistor value of 60 Ω. Above values are maximum. Values in the ICCDA column refer to the current consumed by all the I/Os. Values in the ICCDIFFA column refer to the current flowing per pair through differential amplifiers when using differential pairs or voltage references pins. ICCA (mA) TBD TBD 50 500 30 450 20 250 ICCI (mA) TBD TBD 10 35 10 35 5 20 ICCDA (mA) TBD TBD 7 10 7 10 5 10 ICCDIFFA (mA) TBA TBA 3.13 2.96 3.13 2.96 3.13 2.96 IIL/IIH TBD TBD 1 μA 5 μA 1 μA 5 μA 1 μA 5 μA Table 2-5 • RTAX-SL Standby Current Device RTAX2000SL Temperature Typical 25ºC 125ºC RTAX1000SL Typical 25ºC 125ºC RTAX250SL Typical 25ºC 125ºC Notes: 1. 2. 3. 4. For calculating the leakage values, use a pull-down/pull-up resistor value of 60 Ω. Above values are maximum. Values in the ICCDA column refer to the current consumed by all the I/Os. Values in the ICCDIFFA column refer to the current flowing per pair through differential amplifiers when using differential pairs or voltage references pins. ICCA (mA) 50 150 30 90 20 60 ICCI (mA) 10 35 10 35 5 20 ICCDA (mA) 7 10 7 10 5 10 ICCDIFFA (mA) 3.13 2.96 3.13 2.96 3.13 2.96 IIL/IIH 1 μA 5 μA 1 μA 5 μA 1 μA 5 μA v5.3 2-3 RTAX-S/SL RadTolerant FPGAs Table 2-6 • Default Cload / VCCI Cload (pF) Single-Ended without VREF LVCMOS – 15 (JESD8-11) LVCMOS –18 LVCMOS – 25 LVTTL 8 mA Low Slew LVTTL 12 mA Low Slew LVTTL 16 mA Low Slew LVTTL 24 mA Low Slew LVTTL 8 mA High Slew LVTTL 12 mA High Slew LVTTL 16 mA High Slew LVTTL 24 mA High Slew PCI PCI-X Single-Ended with VREF SSTL2-I SSTL2-II SSTL3-I SSTL3-II HSTL-I GTLP – 33 Differential LVPECL – 33 LVDS – 25 Note: *PI/O = P10 + Cload * Table 2-7 • VCCI2 N/A N/A 30 30 30 30 20 10 35 35 35 35 35 35 35 35 35 35 35 10 10 VCCI (V) 1.5 1.8 2.5 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 2.5 2.5 3.3 3.3 1.5 3.3 3.3 2.5 Pload (µW/MHz) 78.75 113.4 218.75 381.15 381.15 381.15 381.15 381.15 381.15 381.15 381.15 108.9 108.9 – – – – – – – – P10 (µW/MHz) 49 73.4 155 118.2 138.1 150.3 168.7 129.8 165.4 224.6 267 218 162.4 171.2 147.8 327.2 288.4 40.9 67.6 260.1 145.3 PI/O (µW/MHZ)* 127.7 186.8 373.8 499.4 519.2 531.5 549.8 511 546.5 605.7 648.1 326.9 271.3 171.2 147.8 327.2 288.4 40.9 67.6 260.1 145.3 Different Components Contributing to the Total Power Consumption in RTAX-S/SL Devices Device-Specific Value (in µW/MHz) Symbol P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Power Component Core tile HCLK power component R-cell power component HCLK signal power dissipation Core tile RCLK power component R-cell power component RCLK signal power dissipation Power dissipation due to the switching activity on the R-cell Power dissipation due to the switching activity on the C-cell Power component associated with the input voltage Power component associated with the output voltage RTAX250S/ RTAX1000S/ RTAX2000S/ SL SL SL 85.8 0.6 7.7 1.8 0.9 8.6 1.6 1.4 10.0 227.5 0.6 23.2 227.5 0.9 25.7 1.6 1.4 10.0 378.0 0.6 31.0 378.0 0.9 34.3 1.6 1.4 10.0 RTAX4000S 700 0.6 50 700 0.9 55 1.6 1.4 10 See Table 2-4 and Table 2-5 on page 2-3 for per pin contribution. 2 -4 v5.3 RTAX-S/SL RadTolerant FPGAs Table 2-7 • Different Components Contributing to the Total Power Consumption in RTAX-S/SL Devices (Continued) Device-Specific Value (in µW/MHz) Symbol P11 P12 Power Component Power component associated with the read operation in the RAM block Power component associated with the write operation in the RAM block RTAX250S/ RTAX1000S/ RTAX2000S/ SL SL SL 25.0 30.0 25.0 30.0 25.0 30.0 RTAX4000S 25.0 30.0 Ptotal = Pdc + Pac Pdc Pac Nbanks = ICCA * VCCA + ICCI * VCCI * Nbanks + ICCDA * VCCDA + ICCDIFFA * VCCDA * Nb_da_pairs = PHCLK + PCLK + PR-cells + PC-cells + Pinputs + Poutputs + Pmemory = number of banks Nb_da_pairs = number of differential pairs or voltage referenced pins used PHCLK= (P1 + P2 * s + P3 * sqrt[s]) * Fs s Fs = number of R-cells clocked by this clock = clock frequency PCLK = (P4 + P5 * s + P6 * sqrt[s]) * Fs s Fs = number of R-cells clocked by this clock = clock frequency PR-cells = P7 * ms * Fs ms Fs = number of R-cells switching at each Fs cycle = clock frequency PC-cells = P8 * mc * Fs mc Fs = number of C-cells switching at each Fs cycle = clock frequency Pinputs = P9 * pi * Fpi pi Fpi = number of inputs = average input frequency Poutputs = (P10 + Cload * VCCI2) * po * Fpo Cload VCCI po Fpo = output load (technology dependent) = output voltage (technology dependent) = number of outputs = average output frequency Pmemory = P11 * Nblock * FRCLK + P12 * Nblock * FWCLK Nblock FRCLK FWCLK = number of RAM/FIFO blocks (1 block = 4k) = read-clock frequency of the memory = write-clock frequency of the memory v5.3 2-5 RTAX-S/SL RadTolerant FPGAs Power Estimation Example This example employs an RTAX1000S/SL shift-register design with 1,080 R-cells, one C-cell, one reset input, and one output. This design also uses a single clock (HCLK) at 100 MHz and is operated under room temperature. ms = 1,080 (in a shift register 100% of R-cells are toggling at each clock cycle) = 100 MHz = 1,080 => PHCLK = (P1 + P2 * s + P3 * sqrt[s]) * Fs = 163.8 mW and Fs = 100 MHz => PR-cells = P7 * ms * Fs = 172.8 mW mc = 1 (1 C-cell in this design) and Fs = 100 MHz => PC-cells = P8 * mc * Fs = 0.14 mW Fpi ~ 0 MHz and pi= 1 (1 reset input => this is why Fpi = 0) => Pinputs = P9 * pi * Fpi = 0 mW Fpo = 50 MHz Cload = 35 pF VCCI= 3.3 V and po = 1 => Poutputs = (P10 + Cload * VCCI2) * po * Fpo = 23.6 mW No RAM/FIFO in this shift-register => Pmemory = 0 mW Pac = PHCLK + PCLK + PR-cells + PC-cells + Pinputs + Poutputs + Pmemory = 360.4 mW Pdc = ICCA * VCCA + ICCI * VCCI * Nbanks + ICCDA * VCCDA + ICCDIFFA * VCCDA * Nb_da_pairs = 101.1 mW Ptotal = Pdc + Pac = 360.4 mW + 101.1 mW = 461.5 mW Fs s 2 -6 v5.3 RTAX-S/SL RadTolerant FPGAs Thermal Characteristics The temperature variable in Actel Designer software refers to the junction temperature, not the ambient, case or board temperature. This is an important distinction because dynamic and static power consumption causes the chip's junction temperature to be higher than the ambient, case or board temperature. EQ 2-2, EQ 2-3, and EQ 2-4 show the relationship between thermal resistance, temperature, and power. Tj – Ta θ ja = --------------P EQ 2-2 Where: θja θjc θjb Tj Ta Tc Tb P = Thermal resistance from junction to air = Thermal resistance from junction to case = Thermal resistance from junction to board = Junction Temperature = Ambient Temperature = Case Temperature = Board Temperature = Power θ jc θ jb Tj – Tc = --------------P EQ 2-3 Tj – Tb = --------------P EQ 2-4 Table 2-8 • Package Thermal Characteristics Product RTAX250S/SL Package Type CQ208 CQ352 RTAX1000S/SL CQ352 CG624 RTAX2000S/SL CQ256 CQ352 CG624 CG1152 RTAX4000S CQ352 CG1272 Notes: 1. 2. 3. 4. θja 19.9 16.8 13.3 10.8 15.8 12.3 9.7 9.0 12.3 8.0 θjc 0.8 0.7 0.4 5.6 0.25 0.2 4.3 2.0 0.2 2.0 θjb N/A N/A N/A 4.5 N/A N/A 3.5 2.6 N/A 2.2 Units C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W θja are estimated at still air. θjc for CQFP refers to the thermal resistance between the junction and the bottom surface of the package. θjc for CG packages refers to the thermal resistance between the junction and the top surface of the package. The θjb values in the table are simulated under conduction heat transfer only. v5.3 2-7 RTAX-S/SL RadTolerant FPGAs Calculation for Power Sample Case 1: Convection = 0 A sample calculation of the power dissipation allowed for an RTAX1000S/SL-CG624 in still air is shown below. Assume that the maximum junction temperature is maintained at 110°C and the ambient temperature is 50°C. The maximum power allowed can be estimated using the equation below. Tj = 110°C Ta = 50°C 110°C – 50°C θ ja = 10.8°C/W = ---------------------------------P P = 5.55 W Air Solder Columns PCB Figure 2-2 • Heat Flow when Air is Present Sample Case 2: Convection = 0 A sample calculation of the power dissipation when there is no air in the environment is shown below. An RTAX1000S/ SL-CQ352 is attached to the board with a thermal adhesive between the package body. The thermal resistance of the paste is 0.58°C/W. Since air is not present in the environment, most of the heat will be flowing through the bottom of the package, through the thermal paste, and to the board. Neglecting the heat flowing through the package leads, the maximum power allowed can be estimated as shown in the equations below. Tj = 110°C θcb = Thermal resistance of the thermal paste from case to board (i.e., = 0.58°C/W) Tb = 70°C θ jb (Total) = θ jc + θ cb 110°C – 70°C θ jc + θ cb = ---------------------------------P 110°C – 70°C 0.4°C/W + 0.58°C/W = ---------------------------------P 110°C – 70°C θ jb (Total) = ---------------------------------P P = 40.8 W Thermal Adhesive PCB Figure 2-3 • Heat Flow in a Vacuum The thermal resistances, shown in Table 2-8 on page 2-7, are based on the simulations done with test conditions and test boards configurations specified in JEDEC specification JESD51. 2 -8 v5.3 RTAX-S/SL RadTolerant FPGAs Timing Characteristics RTAX-S/SL devices are manufactured in a CMOS process, therefore, device performance varies according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. The derating factors shown in Table 2-9 should be applied to all timing data contained within this datasheet. Table 2-9 • Temperature and Voltage Timing Derating Factors (Normalized to Worst-Case Military, TJ = 125°C, VCCA = 1.4 V) Junction Temperature VCCA 1.4V 1.425V 1.5V 1.575V 1.6V Notes: 1. The user can set the junction temperature in Designer software to be any integer value in the range of –55°C to 125°C. 2. The user can set the core voltage in Designer software to be any value between 1.4V and 1.6V. –55°C 0.74 0.72 0.69 0.66 0.65 –40°C 0.75 0.74 0.71 0.68 0.67 0°C 0.80 0.79 0.75 0.72 0.71 25°C 0.84 0.82 0.78 0.75 0.74 70°C 0.89 0.88 0.84 0.80 0.79 85°C 0.92 0.91 0.86 0.83 0.82 125°C 1.00 0.98 0.94 0.90 0.89 All timing numbers listed in this datasheet represent sample timing characteristics of RTAX-S/SL devices. Actual timing delay values are design-specific and can be derived from the Timer tool in Actel’s Designer software after place-androute. v5.3 2-9 RTAX-S/SL RadTolerant FPGAs Timing Model I/O Module (Nonregistered) Carry Chain Combinatorial Cell FCO tPDC = 0.70 ns I/O Module (Registered) + tDP = 1.83 ns tRD2 = 0.84 ns Buffer Module tBFPD = 0.17 ns LVTTL tDP = 1.85 ns tICLKQ = 0.91 ns tSUD = 0.31 ns Combinatorial Cell Y tPD = 0.95 ns tBFPD = 0.17 ns tRD1 = 0.66 ns tRD2 = 0.84 ns tRD3 = 1.07 ns Buffer Module tCCY = 0.76 ns I/O I/O Module (Nonregistered) tPY = 3.51 ns LVTTL Output Drive Strength = 4 (24mA) High Slew Rate Combinatorial Cell tPY = 2.45 ns I/O LVPECL LVPECL Routed or Hardwired tHCKH = 3.65 ns FMAX (external) = 350 MHz FMAX (internal) = 700 MHz I/O Module (Non- registered) Register Cell Combinatorial Cell tRD1 = 0.66 ns Y tPD = 0.95 ns Register Cell tRCO = 0.96 ns tSUD = 0.21 ns DQ Buffer Module I/O Module tOCLKQ = 0.91 ns tSUD = 0.31 ns D tBPFD = 0.21ns Q tPY = 1.26 ns GTL + 3.3V D Q LVDS + tRCKH = 3.71 ns tRCKL = 3.54 ns tDP = 2.00 ns tRCO = 0.96 ns tSUD = 0.21 ns Routed Clock LVTTL tDP = 1.85 ns tRCKL = 3.54 ns FMAX (external) = 350 MHz FMAX (internal) = 700 MHz tHCKL = 3.48 ns LVTTL tDP = 1.85 ns tRCKL = 3.55 ns Hardwired or Routed Clock Note: Timing data is for the RTAX2000S/SL, –1 speed. Figure 2-4 • Timing Model Hardwired Clock External Setup = = = = = = (tDP + tRD2 + tSUD) – tHCKH (1.85 + 0.84 + 0.31) – 3.65 –0.61 tHCKH + tRCO + tRD1 + tPY 3.65 + 0.90 + 0.66 + 3.51 8.72 ns Routed Clock External Setup = = = = = = (tDP + tRD2 + tSUD) – tRCKH (1.85 + 0.84 + 0.31) – 3.54 –0.71 ns tRCKH + tRCO + tRD1 + tPY 3.71 + 0.90 + 0.66 + 3.51 8.78 ns Clock-to-Out (Pad-to-Pad) Clock-to-Out (Pad-to-Pad) 2 -1 0 v5.3 RTAX-S/SL RadTolerant FPGAs I/O Specifications Pin Descriptions Supply Pins GND Ground User-Defined Supply Pins VREF Supply Voltage Low supply voltage. VCCA Supply Voltage Reference voltage for I/O banks. VREF pins are configured by the user from regular I/O pins; VREF are not in fixed locations. There can be one or more VREF pins in an I/O bank. Supply voltage for array (1.5 V). VCCIBx Supply Voltage Global Pins HCLKA/B/C/D Dedicated (Hardwired) Clocks A, B, C, and D Supply voltage for I/Os. Bx is the I/O Bank ID – 0 to 7. See "User I/Os" on page 2-12 for more information. VCCDA Supply Voltage Supply voltage for the I/O differential amplifier and JTAG and probe interfaces. VCCDA is either 3.3 V or 2.5 V and must use 3.3 V when voltage-referenced and/or differential is used. Additionally, VCCDA must be greater than or equal to any VCCI voltages (i.e. VCCDA ≥ VCCIBx). VPUMP Supply Voltage (External Pump) These pins are the clock input for sequential modules. Input levels are compatible with all supported I/O standards (there is a P/N pin pair for support of differential I/O standards). This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. When the HCLK pins are unused, it is recommended that they are tied to the ground. CLKE/F/G/H Global Clocks E, F, G, and H In low-power mode, VPUMP will be used to access an external charge pump (if the user desires to bypass the internal charge pump to further reduce power). The device starts using the external charge pump when the voltage level on VPUMP reaches 3.3 V.1 In normal device operation, when using the internal charge pump, VPUMP should be tied to GND. These pins are clock inputs for clock distribution networks. Input levels are compatible with all supported I/O standards (there is a P/N pin pair for support of differential I/O standards). The clock input is buffered prior to clocking the R-cells. When the CLK pins are unused, Actel recommends that they are tied to a known state. 1. When VPUMP = 3.3V, it shuts off the internal charge pump. v5.3 2-11 RTAX-S/SL RadTolerant FPGAs JTAG/Probe Pins PRA/B/C/D2 Probes A, B, C, and D Special Functions NC No Connection The probe pins are used to output data from any userdefined design node within the device (controlled with Silicon Explorer II). These independent diagnostic pins can be used to allow real-time diagnostic output of any signal path within the device. The pins’ probe capabilities can be permanently disabled to protect programmed design confidentiality. TCK2 Test Clock This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. User I/Os3 Introduction The RTAX-S/SL family features a flexible I/O structure, supporting a range of mixed voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V) with its bank-selectable I/Os. Table 2-10 on page 2-13 contains the I/O standards supported by the RTAX-S/SL family. Unused I/Os are configured as follows: • • • Output buffer is disabled (with tristated value of Hi-Z) Input buffer is disabled (with tristated value of Hi-Z) No pull-up/pull-down is programmed Test clock input for JTAG boundary-scan testing and diagnostic probe (Silicon Explorer II). TDI2 Test Data Input Serial input for JTAG boundary-scan testing and diagnostic probe. TDI is equipped with an internal pullup resistor with approximately 10 kΩ resistance. TDO2 Test Data Output Serial output for JTAG boundary-scan testing. TMS Test Mode Select The TMS pin controls the use of the IEEE 1149.1 boundary-scan pins (TCK, TDI, TDO, TRST). TMS is equipped with an internal pull-up resistor with approximately 10 kΩ resistance. TRST Boundary Scan Reset Pin In Actel Designer Software, unused RTAX-S/SL I/Os are configured as tristate with no pull-up resistors. Each I/O provides programmable slew rates, drive strengths, and weak pull-up and weak pull-down circuits. All I/O standards are 3.3 V tolerant, and I/O standards, except 3.3 V PCI, are capable of hot insertion and cold sparing. 3.3 V PCI is also 5 V tolerant with the aid of an external resistor (see "5 V Tolerance" on page 2-1). Each I/O includes three registers: an input (InReg), an output (OutReg), and an enable register (EnReg). I/Os are organized into banks, and there are eight banks per device – two per side (Figure 2-7 on page 2-20). Each I/O bank has a common VCCI, the supply voltage for its I/Os. For voltage-referenced I/Os, each bank also has a common reference-voltage bus, VREF. While VREF must have a common voltage for an entire I/O bank, its location is user-selectable. In other words, any user I/O in the bank can be selected to be a VREF. The TRST pin functions as an active-low input to asynchronously initialize or reset the boundary scan circuit. The TRST pin is equipped with a programmable pull-up resistor with approximately 10 kΩ resistance (i.e. with or without the pull-up resistor). This pin must be hardwired to ground for flight. 2. Actel recommends that you use a series termination resistor on every probe connector (TDI, TCK, TDO, PRA, PRB, PRC, and PRD). The series termination is used to prevent data transmission corruption (i.e., due to reflection from the FPGA to the probe connector) during probing and reading back the checksum. With an internal setup we have seen 70-ohm termination resistor improved the signal transmission. Since the series termination depends on the setup, Actel recommends users to calculate the termination resistor for their own setup. Below is a guideline on how to calculate the resistor value. The resistor value should be chosen so that the sum of it and the probe signal’s driver impedance equals the effective trace impedance. Z0 = Rs + Zd Z0 = trace impedance (silicon explorer’s breakout cable’s resistance + PCB trace impedance), Rs = series termination, Zd = probe signal’s driver impedance. The termination resistor should be placed as close as possible to the driver. Among the probe signals, TDI, TCK, and TMS are driven by Silicon Explorer. A54SX16 is used in Silicon Explorer and hence the driver impedances needs to be calculated from RTAX-S IBIS Models (Mixed Voltage Operation). PRA, PRB, PRC, PRD, and TDO are driven by the FPGA and driver impedance can also be calculated from the IBIS Model. Silicon explorer’s breakout cable’s resistance is usually close to 1 ohm. 3. Do not use an external resistor to pull the I/O above VCCI for a higher logic “1” voltage level. The desired higher logic “1” voltage level will be degraded due to a small I/O current, which exists when the I/O is pulled up above VCCI. 2 -1 2 v5.3 RTAX-S/SL RadTolerant FPGAs The location of the VREF pin should be selected according to the following rules: • Any pin that is assigned as a VREF can control a maximum of eight user I/O pad locations in each direction (16 total maximum) within the same I/O bank. I/O package locations listed as no-connects are counted as part of the 16 maximum. In many cases, this leads to fewer than eight user I/O package pins in each direction being controlled by a VREF pin. Dedicated I/O pins (GND, VCCI...) are not counted as part of the 16. The user I/O pad immediately adjacent on either side of the VREF pin may only be used as an input. The exception is when there is a VCCI/GND pair separating the VREF pin and the user I/O pad location. Input/Output Supply Voltage (VCCI) 3.3 2.5 1.8 1.5 3.3 3.3 2.5 1.5 3.3 2.5 2.5 3.3 V* The differential amplifier supply voltage VCCDA should be connected to 3.3 V. When neither voltage-referenced nor differential I/Os are used, VCCDA may be connected to 2.5 V when VCCI