SG1525A/SG2525A/SG3525A
SG1527A/SG2527A/SG3527A
Regulating Pulse Width Modulator
Description
Features
The SG1525A/1527A series of pulse width modulator integrated
circuits are designed to offer improved performance and lower
external parts count when used to implement all types of switching
power supplies. The on-chip +5.1 V reference is trimmed to ±1%
initial accuracy and the input common-mode range of the error
amplifier includes the reference voltage, eliminating external
potentiometers and divider resistors. A Sync input to the oscillator
allows multiple units to be slaved together, or a single unit to be
synchronized to an external system clock. A single resistor between
the CT pin and the Discharge pin provides a wide range of deadtime
adjustment. These devices also feature built-in soft-start circuitry
with only a timing capacitor required externally. A Shutdown pin
controls both the soft-start circuitry and the output stages, providing
instantaneous turn-off with soft-start recycle for slow turn-on. These
functions are also controlled by an undervoltage lockout which
keeps the outputs off and the soft-start capacitor discharged for
input voltages less than that required for normal operation. Another
unique feature of these PWM circuits is a latch following the
comparator. Once a PWM pulse has been terminated for any
reason, the outputs remain off for the duration of the period. The
latch is reset with each clock pulse. The output stages are totempole designs capable of sourcing or sinking in excess of 200mA.
The SG1525A output stage features NOR logic, giving a LOW
output for an OFF state. The SG1527A utilizes OR logic, which
results in a HIGH output level when OFF.
8V to 35V Operation
5.1V Reference Trimmed to 1%
100Hz to 500kHz Oscillator Range
Separate Oscillator Sync Terminal
Adjustable Deadtime Control
Internal Soft-start
Input Undervoltage Lockout
Latching P.W.M. to Prevent Multiple Pulses
Dual Source/Sink Output Drivers
High Reliability Features
Following are the high reliability features of SG1525A
and SG1527A:
Available to MIL-STD-883, ¶ 1.2.1
MIL-M38510/12602BEA - JAN1525AJ
MIL-M38510/12604BEA - JAN1527AJ
MSC-AMS level “S” Processing Available
Block Diagram
VREF
VC
U.V.
LOCKOUT
REFERENCE
REGULATOR
+VIN
TO
INTERNAL CIRCUITRY
GROUND
OUTPUT A
OSC OUTPUT
SYNC
Q
RT
OSCILLATOR
CT
Q
DISCHARGE
F/F
+
COMPENSATION
R
P.W.M.
VIN
OUTPUT B
S
LATCH
SG1525A OUTPUT STAGE
VC
INV. INPUT
OUTPUT A
+
N.I. INPUT
ERROR
AMP
50µA
SOFT-SART
VREF
5k
SHUTDOWN
OUTPUT B
5k
SG1527A OUTPUT STAGE
Figure 1 · Block Diagram
September 2014 Rev. 1.4a
www.microsemi.com
© 2014 Microsemi Corporation
1
Regulating Pulse Width Modulator
Connection Diagrams and Ordering Information
Ambient
Temperature
Type
Package
Part Number
Packaging
Type
Connection Diagram
SG1525AJ-883B
SG1525AJ-JAN
SG1525AJ-DESC
SG1525AJ
-55°C to
125°C
J
16-PIN
ceramic DIP
SG1527AJ-883B
SG1527AJ-JAN
SG1527AJ-DESC
SG1527AJ
-25°C to 85°C
SG2525AJ
SG2527AJ
-0°C to 70°C
SG3525AJ
SG3527AJ
-25°C to 85°C
SG2525AN
SG2527AN
N
-0°C to 70°C
16-PIN
plastic DIP
SG3525AN
SG3527AN
-0°C to 70°C
VREF
15
+VIN
Output B
SYNC
3
14
OSC. Output
4
13
CT
5
12
Ground
VC
RT
6
11
Output A
Discharge
7
10
Shutdown
Soft-start
8
9
Compensation
PDIP
SG3525ADW
DW
16
2
N Package: RoHS Compliant / Pb-free
Transition DC: 0503
N Package: RoHS / Pb-free 100%
Matte Tin Lead Finish
SG2527ADW
16-pin wide
body
plastic
SOIC
1
N.I. Input
CERDIP
SG2525ADW
-25°C to 85°C
INV. Input
SOIC
INV. Input
N.I. Input
SYNC
OSC. Output
CT
1
16
VREF
2
15
3
14
4
13
+VIN
Output B
VC
5
12
RT
Discharge
Soft-start
6
11
7
10
8
9
Ground
Output A
Shutdown
Compensation
SG3527ADW
DW Package: RoHS Compliant / Pbfree Transition DC: 0516
DW Package: RoHS / Pb-free 100%
Matte Tin Lead Finish
SG1525AL-883B
-55°C to
125°C
L
20-pin
ceramic
leadless
chip carrier
(LCC)
SG1525AL
SG1527AL-883B
SG1527AL
CLCC
1. N.C.
2. INV. Input
3. N.I. Input
4. SYNC
5. OSC. Output
6. N.C.
7. C T
8. R T
9. Discharge
10. Soft-start
3
2
1
20 19
4
18
5
17
6
16
7
15
8
14
9
10 11 12 13
11. N.C.
12. Comp
13. Shutdown
14. Output A
15. Ground
16. N.C.
17. VC
18. Output B
19. +VIN
20. VREF
Notes:
1. Contact factory for JAN and DESC product availability.
2. All packages are viewed from the top.
3. Hermetic Packages J & L use Sn63Pb37 hot solder dip lead finish, contact factory for availability of RoHS compliant
versions.
2
Absolute Maximum Ratings1
Absolute Maximum Ratings1
Value
Units
40
40
V
V
-0.3 to 5.5
-0.3 to VIN
V
V
Output Current, Source or Sink
Reference Load Current
500
50
mA
mA
Oscillator Charging Current
Operating Junction Temperature
5
mA
150
150
°C
°C
-65 to 150
300
°C
°C
260 (+0, -5)
°C
Value
Units
30
80
°C/W
°C/W
Parameter
Supply Voltage (+VIN)
Collector Supply Voltage (V C)
Logic Inputs
Analog Inputs
Hermetic (J, L Packages)
Plastic (N, DW Packages)
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
RoHS Peak Package Solder Reflow Temp. (40 s max. exp.)
Note: Values beyond which damage may occur
Thermal Data
Parameter
J Package
Thermal Resistance-Junction to Case, θJC
Thermal Resistance-Junction to Ambient, θJA
N Package
Thermal Resistance-Junction to Case, θJC
40
°C/W
Thermal Resistance-Junction to Ambient, θJA
DW Package
65
°C/W
Thermal Resistance-Junction to Case, θJC
Thermal Resistance-Junction to Ambient, θJA
40
95
°C/W
°C/W
35
°C/W
L Package
Thermal Resistance-Junction to Case, θJC
Thermal Resistance-Junction to Ambient, θJA
120
°C/W
Notes:
1. Junction Temperature Calculation: TJ = TA + (PD × θJA).
2. The above numbers for θJC are maximums for the limiting thermal resistance of the package in a standard mounting
configuration. The θJA numbers are meant to be guidelines for the thermal performance of the device/pc-board system. All of
the above assume no ambient airflow.
3
Regulating Pulse Width Modulator
Recommended Operating Conditions1
Value
Units
Input Voltage (+VIN)
Collector Voltage (VC)
8 to 35
4.5 to 35
V
V
Sink/Source Load Current (steady state)
Sink/Source Load Current (peak)
0 to 100
0 to 400
mA
mA
0 to 20
0.1 to 350
mA
kHz
2 to 150
0 to 500
kΩ
Ω
5
0.001 to 0.1
kΩ
µF
-55 to 125
°C
-25 to 85
0 to 70
°C
°C
Parameter
Reference Load Current
Oscillator Frequency Range
Oscillator Timing Resistor (RT)
Deadtime Resistor Range (RD)
Maximum Shutdown Source Impedance
Oscillator Timing Capacitor (CT)
Operating Ambient Temperature Range
SG1525A/SG1527A
1
SG2525A/SG2527A
SG3525A/SG3527A
Note: Range over which the device is functional.
Electrical Characteristics
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for
SG1525A/SG1527A with -55°C ≤ TA ≤ 125°C, SG2525A/SG2527A with -25°C ≤ TA ≤ 85°C,
SG3525A/SG3527A with 0°C ≤ TA ≤ 70°C, and +VIN = 20V. Low duty cycle pulse testing techniques are
used that maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Test Conditions
Reference Section
Output Voltage
SG1525A/2525A
SG1527A/2527A
Min
Typ
Max
SG3525A
SG3527A
Min
Typ
Max
5.05
5.00
Units
1
TJ = 25C
Line Regulation
Load Regulation
VIN = 8V to 35V
IL = 0 to 20mA
Temperature Stability
1
Total Output Voltage
1
Range
Short Circuit Current
Output Noise Voltage
1
1
Over Operating
Temperature Range
Over Line, Load and
Temperature
VREF = 0V, TJ = 25C
10Hz ≤ f ≤ 10kHz,
TJ = 25°C
TJ = 125C
5.10
5.15
10
20
20
5.00
5.10
5.20
V
30
50
10
20
30
50
mV
mV
50
20
50
mV
5.25
V
5.20
80
40
100
200
4.95
80
40
100
200
mA
Vrms
Long Term Stability
20
50
20
50
mV/khr
Notes:
1. These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
2. FOSC = 40 kHz (RT = 3.6k Ω, CT = 0.01µF, RD = 0Ω.).
3. Applies to SG1525A/2525A/3525A only, due to polarity of output pulses.
4
Electrical Characteristics (continued)
Electrical Characteristics (continued)
Parameter
Test Conditions
Oscillator Section
SG1525A/2525A
SG1527A/2527A
Units
Min
Typ
Max
Min
Typ
Max
37.6
40
±0.3
42.4
±1
37.6
40
±1
42.4
±2
kHz
%
±3
±6
150
±3
±6
150
%
Hz
2
Initial Accuracy
Voltage Stability
TJ = 25C
VIN = 8V to 35V
1
MIN ≤ TJ ≤ MAX
RT = 150kΩ, CT = 0.1μF
1
RT = 2 kΩ, CT = 1nF
IRT = 2mA
350
1.7
2.0
TJ = 25C
3.0
0.3
3.5
0.5
1.2
2.0
1.0
2.8
2.5
0.5
1
Temperature Stability
1
Minimum Frequency
Maximum Frequency
Current Mirror
Clock Amplitude
Clock Width
Sync Threshold
Sync Input Current
Sync Voltage = 3.5V
Error Amplifier Section (VCM = 5.1V)
Input Offset Voltage
Input Bias Current
Input Offset Current
DC Open Loop Gain
Output Low Level
Output High Level
Common Mode Rejection
Minimum Duty Cycle
Maximum Duty Cycle
2
2.2
350
1.7
2.0
2.2
kHz
mA
1.0
3.0
0.3
3.5
0.5
1.0
V
µs
1.2
2.0
1.0
2.8
2.5
V
mA
5
2
10
mV
10
1
10
µA
1
µA
0.5
dB
V
1
RL ≥ 10MΩ, TJ = 25C
60
75
0.2
60
0.5
75
0.2
3.8
60
5.6
75
3.8
60
5.6
75
V
dB
50
60
50
60
dB
45
49
45
49
0.6
0.9
3.3
0.6
3.6
0.9
3.3
3.6
V
V
0.05
2.0
0.05
2.0
µA
50
80
50
80
µA
VSHUTDOWN = 2V
0.4
0.6
0.4
0.6
V
VSHUTDOWN = 2.5V
0.4
1.0
0.4
1.0
mA
VCM = 1.5V to 5.2 V
Supply Voltage Rejection
VIN = 8V to 35V
2
PWM Comparator Section
Input Threshold
SG3525A/SG3527A
VCOMP = 0.6V
VCOMP = 3.6V
Zero Duty Cycle
Maximum Duty Cycle
0
Input Bias Current
0
%
%
Soft-Start Section
Soft Start Current
Soft Start Voltage
Shutdown Input Current
VSHUTDOWN = 0V
25
25
5
Regulating Pulse Width Modulator
Parameter
Test Conditions
SG1525A/2525A
SG1527A/2527A
Min
Typ
18
17
19
18
Max
SG3525A/SG3527A
Min
Typ
18
17
19
18
Units
Max
Output Drivers Section (each transistor, VC = 20V)
Output High Level
ISOURCE = 20mA
ISOURCE = 100mA
Output Low Level
ISINK = 20mA
ISINK = 100mA
Undervoltage Lockout
3
Collector Leakage
VCOMP and VSS = High
VC = 35V
Rise Time
Fall Time
1
Shutdown Delay
Total Standby Current
Standby Current
0.2
1.0
0.4
2.2
7
8
200
CL = 1nF, TJ = 25°C
CL = 1nF, TJ = 25°C
100
50
VSD = 3V, CS = 0,
TJ = 25°C
VIN = 35V
6
V
V
0.2
1.0
0.4
2.2
V
V
7
8
200
V
µA
600
300
100
50
600
300
ns
ns
0.2
0.5
0.2
0.5
µs
14
20
14
20
mA
6
Notes:
1. These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
2. FOSC = 40 kHz (RT = 3.6k Ω, CT = 0.01µF, RD = 0Ω).
3. Applies to SG1525A/2525A/3525A only, due to polarity of output pulses.
6
Oscillator Section
Oscillator Section
VREF
16
Q1
RT
6
CT
5
Q5
Q8
Q6
Q9
7.4k
Q3
Q10
RAMP
TO PWM
14k
2k
Q11
Q14
2k
SYNC
3
DISCHARGE
7
25k
BLANKING
TO OUTPUT
400µA
5 pF
23k
Q4
Q2
1k
Q7
250
3k
1k
Q13
Q12
GND 12
4
CLOCK
Figure 2 · Oscillator Schematic
500
200
CT
CT
10
5
6
7
5
RD
5µF
CT =
0.1µ
F
CT =
.0
CT =
5nF
CT =
.01µ
F
CT =
.02µ
F
300
200
100
RT
CT
2
CHARGE TIME - µs
Figure 3 · Oscillator Charge Time versus RT And CT
200
100
50
20
10
5
2
1
0.5
0.2
5000
2000
500
1000
200
100
50
20
5
10
1
0
2
0
400
CT =
1n
DEADTIME RESISTOR (RD) - Ω
=5
nF
=.
01
µF
CT
=.
02
µF
CT
=.
05
µ
F
CT
=0
.1 µ
F
nF
nF
=2
=1
CT
20
CT
TIMING RESISTOR (RT) - kΩ
RD = 0
50
F
CT =
2nF
100
DISCHARGE TIME - ms
Figure 4 · Oscillator Discharge Time versus RD And CT
7
Regulating Pulse Width Modulator
Error Amplifier Section
15
80
+VIN
=0
1n
F
40
RZ = 20k
-
20
1
10
+
2
RZ
To PWM
COMPARATOR
CP
=
10M
100k
10k
100
COMP
10
9
1k
RZ
30 Ω
5.8 V
1
100 µA
200 µA
0
0
1M
2
CP
=
N.I.
INPUT
1
60
CP
INV.
INPUT
Q4
Q2
Q1
VOLTAGE GAIN - DB
Q3
FREQUENCY - Hz
Figure 5 · Error Amplifier
Figure 6 · Error Amplifier Open-Loop Frequency
Response
Output Section
+VIN
13 +VC
4
Q5
VIN = 20 V
TA = 25°C
Q7
Q4
Q9
3
Q10
5k
11
14
+VREF
Q8
OUTPUT
2
Q11
2k
Q6
Q2
Q1
Q3
Q6 OMITTED
in SG1527A
SOURCE SAT. VC - VOH
1
SINK SAT. VOL
5k
10k
10k
Figure 7 · Output Circuit (½ circuit shown)
8
1A
.50
.30
.20
.10
.05
.03
PWM
.02
F/F
.01
0
CLOCK
Figure 8 · Output Saturation Characteristics
Application Information
Application Information
Q1
+VSUPPLY
+VSUPPLY
TO OUTPUT FILTER
R1
R1
13
R2
C1
+VC
13
A
+VC
T1
R2
C2
SG1525A
11
A
Q1
11
SG1525A
B
14
B
Q2
14
R3
GND
GND
12
12
RETURN
RETURN
For single-ended supplies, the driver outputs are
grounded. The VC terminal is switched to ground by
the totem-pole source transistors on alternate
oscillator cycles.
In conventional push-pull bipolar designs, forward base
drive is controlled by R1 - R3 .Rapid turn-off times for the
power devices are achieved with speed-up capacitors
C1 and C2.
+VSUPPLY
R1
+VSUPPLY
R1
13
13
Q1
+VC
A
T1
T1
11
+VC
A
SG1525A
SG1525A
Q2
B
11
GND
R1
T2
Q2
B
14
GND
C1
Q1
14
R2
C2
12
12
RETURN
RETURN
The low source impedance of the output drivers
provides rapid charging of power FET input
capacitance while minimizing external components.
Low power transformers can be driven directly by the
SG1525A. Automatic reset occurs during deadtime, when
both ends of the primary winding are switched to ground.
9
Regulating Pulse Width Modulator
Shutdown Options
1.
Use an external transistor or open-collector comparator to pull down on the Comp terminal. This sets the
PWM latch turning off both outputs. If the shutdown signal is momentary, pulse-by-pulse protection can be
accomplished as the PWM latch resets with each clock pulse.
2.
The same results can be accomplished by pulling down on the Soft-Start terminal with the difference that on
this pin, shutdown does not affect the amplifier compensation network but must discharge any Soft-Start
capacitor.
3.
Apply a positive-going signal to the Shutdown terminal. This provides most rapid shutdown of the outputs
but will not immediately set the PWM latch if there is a Soft-Start capacitor. This capacitor discharges but
with a current of approximately twice the charging current.
4.
The shutdown terminal can be used to set the PWM latch on a pulse-by-pulse basis if there is no external
capacitance on Soft-Start terminal. Slow turn-on may still be accomplished by applying an external
capacitor, blocking diode, and charging resistor to the comp terminal. (See SG1524 Application Note).
VREF
REFERENCE
REGULATOR
16
+VIN
15
0.1µF
CLOCK
0.1µF
FLIP/
FLOP
4
VC
13
SYNC
3 kΩ
0.1µF
3
OUT A
RT
PWM
ADJ
O
S
C
I
L
L
A
T
O
R
10 kΩ
6
3.6 kΩ
DEADTIME
RAMP
0.009µF
7
1k, 1W
(2)
100 Ω
1.5
kΩ
11
A
B
5
14
OUT B
CT
0.1µF
0.001µF
COMP
PWM
9
2 = I(+)
0.01µF
8
1
1
1
3
1
SHUTDOWN
_
3
2
5µF
2
5k
E/A
2
5k
+
2
+
10
VREF
2k
2
2k
3
D.U.T
Figure 9 · SG1525A/1527A Lab Test Fixture
10
+
1
3
V/I METER
SOFTSTART
50 µA
3 = I(-)
_
GND
12
10 kΩ
1 = VOS
Package Outline Dimensions
Package Outline Dimensions
Controlling dimensions are in metric, inches equivalents are shown for general information.
Dim
D
16
9
H
E
e
L
B
A2
A
c
INCHES
MIN
MAX
A
2.06
2.65
0.081
0.104
A1
0.10
0.30
0.004
0.012
A2
2.03
2.55
0.080
0.100
B
0.33
0.51
0.013
0.020
c
0.23
0.32
0.009
0.013
D
10.08
10.50
0.397
0.413
E
7.40
7.60
0.291
0.299
e
8
1
MILLIMETERS
MIN
MAX
1.27 BSC
H
10.00
10.65
0.05 BSC
0.394
0.419
L
0.40
1.27
0.016
0.050
θ
0°
8°
*LC
-
0.10
0°
-
8°
0.004
*Lead co planarity
SEATING PLANE
A1
Note:
Dimensions do not include protrusions; these shall
not exceed 0.155mm (.006”) on any side. Lead
dimension shall not include solder coverage.
Dimensions are in mm, inches are for reference only.
Figure 10 · DW 16-Pin SOWB Package Dimensions
Dim
D
MIN
MAX
A
-
A1
0.38
A2
E1
1
b1
E
A
c
A1
L
e
SEATING PLANE
b
θ
INCHES
MIN
MAX
5.33
-
0.210
-
0.015
3.30 Typ.
-
0.130 Typ.
b
0.36
0.56
0.014
0.022
b1
1.14
1.78
0.045
0.070
c
0.20
0.36
0.008
0.014
D
18.67
19.69
0.735
0.775
e
A2
MILLIMETERS
2.54 BSC
0.100 BSC
E
7.62
8.26
0.300
0.325
E1
6.10
7.11
0.240
0.280
L
2.92
0.381
0.115
0.150
θ
-
15°
-
15°
Note:
Figure 11 ·do not include protrusions; these shall
Dimensions
not exceed 0.155mm (.006”) on any side. Lead
dimension shall not include solder coverage.
Dimensions are in mm, inches are for reference only.
Figure 11 · N 16-Pin Plastic Dual Inline Package Dimensions
11
Regulating Pulse Width Modulator
Package Outline Dimensions (continued)
Controlling dimensions are in inches, metric equivalents are shown for general information.
Dim
D
9
16
E
8
1
b2
Q A
Seating Plane
L c
H
θ
b
e
INCHES
MIN
MAX
A
-
5.08
-
0.200
b
0.38
0.51
0.015
0.020
b2
1.04
1.65
0.045
0.065
c
0.20
0.38
0.008
0.015
D
19.30
19.94
0.760
0.785
E
5.59
7.11
0.220
0.280
e
eA
MILLIMETERS
MIN
MAX
2.54 BSC
0.100 BSC
eA
7.37
7.87
0.290
0.310
H
0.63
1.78
0.025
0.070
L
3.18
5.08
0.125
0.200
α
-
15°
-
15°
Q
0.51
1.02
0.020
0.040
Note:
Dimensions do not include protrusions; these shall
not exceed 0.155mm (.006”) on any side. Lead
dimension shall not include solder coverage.
Figure 12 · J 16-Pin Ceramic Dual Inline Package Dimensions
E3
D
Dim
E
A
A1
L2
L
3
8.64
9.14
0.340
0.360
E3
-
8.128
-
0.320
e
1.270 BSC
0.050 BSC
B1
0.635 TYP
0.025 TYP
L
1.02
1.52
0.040
0.060
A
1.626
2.286
0.064
0.090
1.016 TYP
1.372
1.68
0.054
0.066
A2
-
1.168
-
0.046
L2
1.91
2.41
0.075
0.203R
0.95
0.008R
Note:
1
13
h
18
B1
e
All exposed metalized area shall be gold plated
60 micro-inch minimum thickness over nickel
plated unless otherwise specified in purchase
order.
B3
Figure 13 · L 20-Pin Ceramic LCC Package Outline Dimensions
12
0.040 TYP
A1
B3
A2
INCHES
MIN
MAX
D/E
h
8
MILLIMETERS
MIN
MAX
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SG1525A/SG1527A.1/09.14