SM802XXX
Flexible Ultra-Low Jitter Clock Synthesizer
Features
General Description
• 115 fs at 156.25 MHz (1.875 MHz to 20 MHz)
• 265 fs at 156.25 MHz (12 kHz to 20 MHz)
• On-Chip Power Supply Regulation for Excellent
Board-Level Power Supply Noise Immunity
• Generates up to 8 Combinations of Differential or
16 Single-Ended Clock Outputs
- LVPECL, LVDS, HCSL, LVCMOS (SE or Diff)
• Selectable Input:
- Crystal: 11.4 MHz to 27 MHz
- Reference Input: 11.4 MHz to 80 MHz
• No External Crystal Oscillator Capacitors
Required
• 2.5V or 3.3V Operating Power Supply
• Available in Industrial Temperature Range
• Available in Green, RoHS, and PFOS Compliant
QFN Packages:
- 44-pin, 7 mm × 7 mm
- 32-pin, 5 mm × 5 mm
- 24-pin, 4 mm × 4 mm
- 16-pin, 3 mm × 3.5 mm
The SM802xxx series is a member of the ClockWorks®
family of devices from Microchip and provide an
extremely low-noise timing solution for applications
such as (1-100) Gigabit Ethernet, SONET, wireless
base station, satellite communication, Fibre Channel,
SAS/SATA, and PCIe. It is based upon a unique PLL
architecture that provides less than 250 fs phase jitter.
The devices operate from a 2.5V or 3.3V power supply
and synthesize up to 8 different combinations
(LVPECL, LVDS, HCSL) of differential or 16
single-ended output clocks. The devices accept an
external reference clock or crystal input.
The SM802xxx series is fully programmable and a web
tool is available to configure a part for samples at the
ClockWorks Configurator tool.
Applications
•
•
•
•
•
•
•
1/10/40/100 Gigabit Ethernet (GbE)
SONET/SDH
PCI Express
CPRI/OBSAI – Wireless Base Station
Fibre Channel
SAS/SATA
DIMM
2019 Microchip Technology Inc.
DS20006176A-page 1
SM802XXX
Package Types
SM802XXX
Option 2: 32-Pin 5 mm x 5 mm QFN
(Top View)
VDDO2
VDDO2
QE
/QE
VSSO2
VSSO1
VDDO1
VDDO1
QD
/QD
TEST
VDDO2
QE
/QE
VSSO2
VSSO1
VDDO1
QD
/QD
SM802XXX
Option 1: 44-Pin 7 mm x 7 mm QFN
(Top View)
32 31 30 29 28 27 26 25
VDDO2
VSSO2
/QG
QG
PLL_BYPASS
XTAL_SEL
TEST
VDD
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
TEST
19
/QD
QD
20
QD
/QD
21
VSSO1
VSSO1
22
SM802XXX
Option 4: 24-Pin 4 mm x 4 mm QFN
(Top View)
/QE
/QE
23
15 16
QE
QE
SM802XXX
Option 3: 24-Pin 4 mm x 4 mm QFN
(Top View)
24
10 11 12 13 14
TEST
VDDO1
QB
/QB
TEST
VSSO1
VSS
VSS
VDD
FSEL
OE1
REF_IN
XIN
XOUT
TEST
OE2
QC
/QC
VDDO1
TEST
QB
/QB
TEST
QA
/QA
VSSO1
VSS
VDDO2
44 43 42 41 40 39 38 37 36 35 34
33
1
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
24
10
23
11
12 13 14 15 16 17 18 19 20 21 22
VDD
VDD
FSEL
OE1
VDDO2
REF_IN
XIN
XOUT
TEST
VSS
OE2
/QF
QF
VSSO2
/QG
QG
VSSO2
/QH
QH
PLL_BYPASS
XTAL_SEL
TEST
24
23
22
21
20
19
VDDO1
16
/QB
PLL_BYPASS
3
16
TEST
4
15
TEST
XTAL_SEL
4
15
VSS
PLL_BYPASS
5
14
VSS
TEST
5
14
VSS
XTAL_SEL
6
13
VSS
FSEL
6
13
VSS
8
9
10
11
12
TEST
TEST
7
XOUT
QG
XIN
3
VDD
/QG
REF_IN
17
8
9
10
11
12
QD
/QD
TEST
VDDO1/2
QD
/QD
TEST
SM802XXX
Option 6: 16-Pin 3 mm x 3.5 mm QFN
(Top View)
VDDO1/2
SM802XXX
Option 5: 16-Pin 3 mm x 3.5 mm QFN
(Top View)
7
OE2
17
2
TEST
2
VSSO2
XOUT
TEST
VSSO2
VDDO1
XIN
18
QB
18
REF_IN
1
1
OE1
VDD
VDDO2
16
15
14
13
16
15
14
13
TEST
QF
11
TEST
VSS
3
10
VSS
VSS
3
10
VSS
TEST
4
9
VSS
TEST
4
9
VSS
DS20006176A-page 2
5
6
7
8
5
6
7
8
TEST
2
XIN
VSS
QF
XOUT
12
2
VDD
1
TEST
/QF
FSEL
VSS
11
REF_IN
12
VDD
1
/QF
2019 Microchip Technology Inc.
SM802XXX
Block Diagram
VDDO 1
VDDO 2
VDD
VSS
VDD Power Rail Regulation
QA
1
QB
Div 1
÷
QC
0
QD
REFIN
0
PLL 1
XO
QE
1
1
QF
Div 2
÷
XTAL_SEL
INTERNAL
PULL-UPS
VSSO 1
VSSO 2
PLL_BYPASS
OE1
OE2
FSEL
2019 Microchip Technology Inc.
QH
INTERNAL
PULL-DOWN
INTERNAL PULL-UP
QG
0
DS20006176A-page 3
SM802XXX
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Supply Voltage (VDD, VDDO1/2).................................................................................................................................+4.6V
Input Voltage (VIN).............................................................................................................................–0.5V to VDD + 0.5V
Operating Ratings ††
Supply Voltage (VDD, VDDO1/2).......................................................................................................... +2.375V to +3.465V
† Notice: Exceeding the absolute maximum ratings may damage the device.
†† Notice: The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
DC ELECTRICAL CHARACTERISTICS (Note 1)
Electrical Characteristics: VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%; VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V
±5%; TA = –40°C to +85°C.
Parameter
3.3V Operating Voltage
2.5V Operating Voltage
Total Supply Current,
VDD + VDDO
Note 1:
Symbol
Min.
Typ.
Max.
VDD,
VDDO1/2
3.135
3.3
3.465
2.375
2.5
2.625
—
275
345
8 LVPECL, 312.5 MHz (44-pin QFN)
Outputs open
—
150
185
4 HCSL (PCIe), 100 MHz (32-pin or
24-pin QFN)
Outputs 50Ω to VSS
—
70
90
IDD
Units
V
mA
Conditions
VDDO1 = VDDO2
2 LVCMOS, 125 MHz
(16-pin QFN)
Outputs open
The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
LVCMOS INPUTS (OE1, OE2, PLL_BYPASS, XTAL_SEL, FSEL) DC ELECTRICAL
CHARACTERISTICS (Note 1)
Electrical Characteristics: VDD = 3.3V ±5% or 2.5V ±5%; TA = –40°C to +85°C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Input High Voltage
VIH
2
—
VDD +
0.3
V
Input Low Voltage
VIL
–0.3
—
0.8
V
—
Input High Current
IIH
—
—
150
µA
VDD = VIN = 3.465V
Input Low Current
IIL
–150
—
—
µA
VDD = 3.465V, VIN = 0V
Note 1:
Conditions
—
The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
DS20006176A-page 4
2019 Microchip Technology Inc.
SM802XXX
LVDS OUTPUT DC ELECTRICAL CHARACTERISTICS (Note 1)
Electrical Characteristics: VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%; VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V
±5%; TA = –40°C to +85°C. RL = 100Ω across Q1 and /Q1.
Parameter
Symbol
Min.
Typ.
Max.
Units
Differential Output Voltage
VOD
275
350
475
mV
Figure 5-8
∆VOD
—
—
40
mV
—
VOS
1.15
1.25
1.50
V
—
∆VOS
—
—
50
mV
—
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
Note 1:
Conditions
The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
HCSL OUTPUT DC ELECTRICAL CHARACTERISTICS (Note 1)
Electrical Characteristics: VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%; VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V
±5%; TA = –40°C to +85°C. RL = 50Ω to VSS.
Parameter
Symbol
Min.
Typ.
Max.
Units
Conditions
Output High Voltage
VOH
660
700
850
mV
Output Low Voltage
VOL
–150
0
27
mV
—
VSWING
250
350
550
mV
—
Output Voltage Swing
Note 1:
—
The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
LVPECL OUTPUT DC ELECTRICAL CHARACTERISTICS (Note 1)
Electrical Characteristics: VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%; VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V
±5%; TA = –40°C to +85°C. RL = 50Ω to VDDO –2V.
Parameter
Symbol
Min.
Typ.
Max.
Units
Conditions
Output High Voltage
VOH
VDDO – VDDO – VDDO –
1.145
0.97
0.845
V
—
Output Low Voltage
VOL
VDDO – VDDO – VDDO –
1.945
1.77
1.645
V
—
V
—
Output Voltage Swing
Note 1:
VSWING
0.6
0.8
1.0
The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
LVCMOS OUTPUT DC ELECTRICAL CHARACTERISTICS (Note 1)
Electrical Characteristics: VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%; VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V
±5%; TA = –40°C to +85°C. RL = 50Ω to VDDO/2.
Parameter
Symbol
Min.
Typ.
Max.
Units
Output High Voltage
VOH
VDDO –
0.7
—
—
V
Figure 5-9
Output Low Voltage
VOL
—
—
0.6
V
Figure 5-9
Note 1:
Conditions
The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
2019 Microchip Technology Inc.
DS20006176A-page 5
SM802XXX
REF_IN DC ELECTRICAL CHARACTERISTICS (Note 1)
Electrical Characteristics: VDD = 3.3V ±5% or 2.5V ±5%; TA = –40°C to +85°C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Input High Voltage
VIH
1.1
—
VDD +
0.3
V
Input Low Voltage
VIL
–0.3
—
0.6
V
—
Input Current
IIN
–5
—
5
µA
XTAL_SEL = VIL, VIN = 0V to VDD
—
20
—
µA
XTAL_SEL = VIH, VIN = VDD
Note 1:
Conditions
—
The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
CRYSTAL CHARACTERISTICS
Electrical Characteristics: VDD = 3.3V ±5% or 2.5V ±5%; TA = –40°C to +85°C.
Parameter
Min.
Typ.
Max.
Mode of Oscillation
Fundamental, parallel
resonant
Frequency
11.4
—
27
Units
Conditions
—
10 pF load capacitance
MHz
—
Equivalent Series Resistance (ESR)
—
—
30
Ω
—
Shunt Capacitance, C0
—
2
5
pF
—
Correlation Drive Level
—
10
100
µW
—
LVPECL AC ELECTRICAL CHARACTERISTICS (Note 1, Note 2, Note 3, Note 4)
Electrical Characteristics: VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C,
unless otherwise noted.
Parameter
Output Frequency
LVPECL Output Rise/Fall
Time
Output Duty Cycle
Symbol
Min.
Typ.
Max.
Units
FOUT
11
—
840
MHz
tr/tf
80
175
350
ps
ODC
Conditions
—
20% - 80%
48
50
52
%
< 350 MHz
45
50
55
%
≥ 350 MHz
—
45
ps
Note 5
Output-to-Output Skew
TSKEW
—
PLL Lock Time
TLOCK
—
—
20
ms
—
RMS Phase Jitter @
156.25 MHz
Tjit(Ø)
—
265
—
fs
Integration Range (12 kHz to
20 MHz)
—
115
—
fs
Integration Range (1.875 MHz to
20 MHz)
Note 1:
2:
3:
4:
5:
The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
See Figure 5-6 through Figure 5-9 for load test circuit examples.
All phase noise measurements were taken with an Agilent 5052B phase noise system.
Output load is 50Ω to VDD – 2V.
Defined as skew between outputs at the same supply voltage and with equal load conditions; Measured at
the output differential crossing points.
DS20006176A-page 6
2019 Microchip Technology Inc.
SM802XXX
LVDS AC ELECTRICAL CHARACTERISTICS (Note 1, Note 2, Note 3, Note 4)
Electrical Characteristics: VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C,
unless otherwise noted.
Parameter
Output Frequency
LVDS Output Rise/Fall
Time
Output Duty Cycle
Symbol
Min.
Typ.
Max.
Units
FOUT
11.4
—
840
MHz
tr/tf
100
160
400
ps
ODC
Conditions
—
20% - 80%
48
50
52
%
< 350 MHz
45
50
55
%
≥ 350 MHz
Output-to-Output Skew
TSKEW
—
—
45
ps
Note 5
PLL Lock Time
TLOCK
—
—
20
ms
—
RMS Phase Jitter @
156.25 MHz
Tjit(Ø)
—
110
—
fs
Integration Range (1.875 MHz to
20 MHz)
Note 1:
2:
3:
4:
5:
The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
See Figure 5-6 through Figure 5-9 for load test circuit examples.
All phase noise measurements were taken with an Agilent 5052B phase noise system.
Outputs terminated 100Ω between Q and /Q. All unused outputs must be terminated.
Defined as skew between outputs at the same supply voltage and with equal load conditions; Measured at
the output differential crossing points.
HCSL AC ELECTRICAL CHARACTERISTICS (Note 1, Note 2, Note 3, Note 4)
Electrical Characteristics: VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C,
unless otherwise noted.
Parameter
Output Frequency
Output Rise/Fall Time
Output Duty Cycle
Symbol
Min.
Typ.
Max.
Units
Conditions
FOUT
11.4
—
840
MHz
tr/tf
150
300
450
ps
20% - 80%
ODC
48
50
52
%
< 350 MHz
—
45
50
55
%
≥ 350 MHz
Output-to-Output Skew
TSKEW
—
—
50
ps
Note 5
PLL Lock Time
TLOCK
—
—
20
ms
—
RMS Phase Jitter @
100 MHz
Tjit(Ø)
—
265
—
fs
Integration Range (12 kHz to
20 MHz)
—
115
—
fs
Integration Range (1.875 MHz to
20 MHz)
Note 1:
2:
3:
4:
5:
The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
See Figure 5-6 through Figure 5-9 for load test circuit examples.
All phase noise measurements were taken with an Agilent 5052B phase noise system.
Output load is 50Ω to VDD / 2.
Defined as skew between outputs at the same supply voltage and with equal load conditions; Measured at
the output differential crossing points.
2019 Microchip Technology Inc.
DS20006176A-page 7
SM802XXX
LVCMOS AC ELECTRICAL CHARACTERISTICS (Note 1, Note 2, Note 3, Note 4)
Electrical Characteristics: VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C,
unless otherwise noted.
Parameter
Symbol
Min.
Typ.
Max.
Units
Output Frequency
FOUT
11.4
—
250
MHz
REF_IN Frequency
FREF
11
—
80
MHz
tr/tf
100
—
500
ps
Output Rise/Fall Time
Output Duty Cycle
Conditions
—
—
20% - 80%
ODC
45
50
55
%
—
Output-to-Output Skew
TSKEW
—
—
60
ps
Note 5
PLL Lock Time
TLOCK
—
—
20
ms
—
RMS Phase Jitter @
125 MHz
Tjit(Ø)
—
115
—
fs
Integration Range (1.875 MHz to
20 MHz)
Note 1:
2:
3:
4:
5:
The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
See Figure 5-6 through Figure 5-9 for load test circuit examples.
All phase noise measurements were taken with an Agilent 5052B phase noise system.
Output load is 50Ω to VDD / 2.
Defined as skew between outputs at the same supply voltage and with equal load conditions; Measured at
the output differential crossing points.
DS20006176A-page 8
2019 Microchip Technology Inc.
SM802XXX
TEMPERATURE SPECIFICATIONS
Parameters
Sym.
Min.
Typ.
Max.
Units
TA
–40
—
+85
°C
Conditions
Temperature Ranges
Ambient Temperature Range
—
Lead Temperature
—
—
—
+260
°C
Soldering, 20s
Case Temperature
—
—
—
+115
°C
—
Storage Temperature Range
TS
–65
—
+150
°C
—
Junction Thermal Resistance, 7 x 7
QFN-44Ld
JA
—
24
—
°C/W
—
Junction Thermal Resistance, 5 x 5
QFN-32Ld
JA
—
34
—
°C/W
—
Junction Thermal Resistance, 4 x 4
QFN-24Ld
θJA
—
50
—
°C/W
—
Junction Thermal Resistance, 3 x 3.5
QFN-16Ld
θJA
—
60
—
°C/W
—
Package Thermal Resistances (Note 1)
Note 1:
Package thermal resistance assumes the exposed pad is soldered (or equivalent) to the device’s most
negative potential on the PCB.
2019 Microchip Technology Inc.
DS20006176A-page 9
SM802XXX
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Pin Numbers by Package Option
#1
#2
#3
#4
#5
#6
44-pin 32-pin 24-pin 24-pin 16-pin 16-pin
Pin
Name
18
13
10
9
—
6
XIN
19
14
11
10
—
7
XOUT
17
12
9
8
7
—
REF_IN
14
10
9
10
6
5
—
6
5
6
4
3
6
—
—
—
FSEL
—
XTAL
SEL
—
PLL
BYPASS
25
—
—
—
—
—
/QA
26
—
—
—
—
—
QA
28
21
16
—
—
—
/QB
29
22
17
—
—
—
QB
32
—
—
—
—
—
/QC
33
—
—
—
—
—
QC
Pin
Level
I,O (SE)
—
Pin Function
Crystal connections.
I, (SE)
LVCMOS Reference clock input.
I, (SE)
Frequency Select, divides
output frequencies by 2.
LVCMOS
0 = FREQ,
1 = FREQ/2, 45 kΩ pull-up
I, (SE)
XTAL Select, selects between
XTAL and REF_IN
LVCMOS
0 = REF_IN,
1 = XTAL, 45 kΩ pull-up
I, (SE)
Bypasses the PLL and switches
the XTAL or REF_IN frequency
to all outputs
LVCMOS
0 = PLL mode,
1 = Bypass mode, 45 kΩ
pull-down
O
Various
O
Various
O
Various
O
Various
O
Various
O
Various
O
Various
O
Various
VDDO1
PWR
—
Power Supply for the outputs on
Bank 1.
VDDO2
PWR
—
Power Supply for the outputs on
Bank 2.
VSSO1
PWR
—
Power Supply Ground for the
outputs on Bank 1.
35
25
20
19
14
14
/QD
36
26
21
20
15
15
QD
41
30
23
22
—
—
/QE
42
31
24
23
—
—
QE
1
—
—
—
1
1
/QF
2
—
—
—
2
2
QF
4
3
3
—
—
—
/QG
5
4
4
—
—
—
QG
7
—
—
—
—
—
/QH
8
—
—
—
—
—
QH
31
23
18
17
16
16
37
27
—
—
—
—
38
—
—
—
—
—
16
1
1
24
16
16
43
32
—
—
—
—
44
—
—
—
—
—
24
19
22
21
—
—
39
28
—
—
—
—
DS20006176A-page 10
Pin Type
Clock Outputs from Bank 1
Each output can be
programmed to its own logic
type: LVPECL, LVDS, HCSL, or
LVCMOS (Note 1)
Clock Outputs from Bank 2
Each output can be
programmed to its own logic
type: LVPECL, LVDS, HCSL, or
LVCMOS (Note 1)
2019 Microchip Technology Inc.
SM802XXX
TABLE 2-1:
PIN FUNCTION TABLE (CONTINUED)
Pin Numbers by Package Option
#1
#2
#3
#4
#5
#6
44-pin 32-pin 24-pin 24-pin 16-pin 16-pin
3
2
2
2
—
—
6
29
—
—
—
—
40
—
—
—
—
—
11
7
7
5
4
4
20
15
12
11
8
8
27
20
15
16
11
11
30
24
19
18
13
13
34
—
—
—
—
—
12
8
8
1
5
5
13
9
—
—
—
—
21
17
13
13
3
3
23
18
14
14
9
9
—
—
—
15
10
10
—
—
—
—
12
12
—
—
—
—
—
—
15
11
22
16
Note 1:
—
—
7
12
—
—
—
—
Pin
Name
Pin Type
Pin
Level
VSSO2
PWR
—
Power Supply Ground for the
outputs on Bank 2.
TEST
—
—
Used for production test.
Do not connect anything to
these pins.
VDD
PWR
—
Core power supply.
VSS
PWR
—
Core power supply ground.
EPAD
—
—
The exposed pad must be
connected to the VSS ground
plane.
OE1
OE2
Pin Function
I, (SE)
Output Enable 1, OUT1–8
disables to tri-state,
LVCMOS
0 = Disabled,
1 = Enabled, 45 kΩ pull-up
I, (SE)
Output Enable 2, OUT9–16
disables to tri-state,
LVCMOS
0 = Disabled,
1 = Enabled, 45 kΩ pull-up
In the case of LVCMOS, an output pair can provide two single-ended LVCMOS outputs.
TABLE 2-2:
TRUTH TABLE
Control Pin
Internal Resistor
(Note 1)
OE1
0 Level (Low)
1 Level (High)
Pull-Up
Outputs QA~QD disabled to Hi Z
(Tri-State)
Outputs QA~QD enabled
OE2
Pull-Up
Outputs QE~QH disabled to Hi Z
(Tri-State)
Outputs QE~QH enabled
XTAL_SEL
Pull-Up
External reference clock input is
selected
Crystal is selected
FSEL; (Note 2)
Pull-Up
Output = Target Frequency x2 or /2
Output = Target Frequency
PLL_BYPASS
Pull-Down
PLL frequency is connected to outputs
PLL is bypassed, Crystal or Ref-in
is connected to outputs
Note 1:
2:
The internal resistor sets the default logic level on the control pin when the pin is left open. Pull up will set
default logic 1 and pull down will set default logic 0. When the pin is not available on a specific configuration, the level will be the default logic level.
The FSEL pin behavior can be programmed between two types:
- At FSEL=0 (low), the output frequency changes to multiply by 2.
- At FSEL=0 (low), the output frequency changes to divide by 2.
The FSEL function affects all outputs the same way, all outputs change when the FSEL pin level changes.
2019 Microchip Technology Inc.
DS20006176A-page 11
SM802XXX
3.0
PHASE NOISE PLOTS
FIGURE 3-1:
100 MHz HCSL, 254 fsRMS for 12 kHz to 20 MHz Integration Range.
FIGURE 3-2:
125 MHz LVCMOS, 114 fsRMS for 1.875 MHz to 20 MHz Integration Range.
DS20006176A-page 12
2019 Microchip Technology Inc.
SM802XXX
FIGURE 3-3:
156.25 MHz LVPECL, 245fsRMS for 12 kHz to 20 MHz Integration Range.
FIGURE 3-4:
644.53125 MHz LVDS, 293fsRMS for 12 kHz to 20 MHz Integration Range.
2019 Microchip Technology Inc.
DS20006176A-page 13
SM802XXX
4.0
APPLICATION INFORMATION
4.1
Input Reference
When operating with a crystal input reference, do not
apply a switching signal to REF_IN.
4.2
Crystal Layout
Keep the layers under the crystal as open as possible
and do not place switching signals or noisy supplies
under the crystal. Crystal load capacitance is built
inside the die, so no external capacitance is needed.
See the Microchip application note ANTC207 for
further details.
4.3
Power Supply Decoupling
Place the smallest value decoupling capacitor (4.7 nF
above) between the VDD and VSS pins, as close as
possible to those pins and at the same side of the PCB
as the IC. The shorter the physical path from VDD to
capacitor and back from capacitor to VSS, the more
effective the decoupling. Use one 4.7 nF capacitor for
each VDD pin on the SM802xxx.
The impedance value of the ferrite bead (FB) needs to
be between 80Ω and 240Ω with a saturation current
≥150 mA.
The VDDO1 and VDDO2 pins connect directly to the VDD
plane. All VDD pins on the SM802xxx connect to VDD
after the power supply filter.
4.4
Output Traces
Design the traces for the output signals according to
the output logic requirements. If LVCMOS is
unterminated, add a 30Ω resistor in series with the
output, as close as possible to the output pin, and start
a 50Ω trace on the other side of the resistor.
For differential traces, you can either use a differential
design or two separate 50Ω traces. For EMI reasons, it
is better to use a differential design.
LVDS can be AC-coupled or DC-coupled to its
termination.
DS20006176A-page 14
2019 Microchip Technology Inc.
SM802XXX
5.0
POWER SUPPLY FILTERING RECOMMENDATIONS
RIPPLE
BLOCKER
VDD PLANE
1μF
FIGURE 5-1:
VDD
1μF 0.01μF
4.7nF
Preferred Filter, Using the MIC94300 or MIC94310 Ripple Blocker.
FB
0.5
VDD PLANE
VDD
10μF
FIGURE 5-2:
0.047μF
0.01μF
4.7nF
Alternative, Traditional Filter, Using a Ferrite Bead.
ODC=
2V
T1
×100%
T2
T2
VDD, VDDA, VDDO
Q
T1
VOH
Z0 = 50
Q0
/Q
VSWING
50
VOL
GND
nQ0
FIGURE 5-3:
OSCILLOSCOPE
Duty Cycle Timing.
–1.3V or –0.5V
FIGURE 5-6:
Test Circuit.
LVPECL Output Load and
80%
VDDO
20%
OSCILLOSCOPE
TR
FIGURE 5-4:
TF
Q
All Outputs Rise/Fall Time.
Z0 = 50
/Q
RMS PHASE NOISE/JITTER
50
NOISE POWER
VSS
PHASE NOISE PLOT
PHASE NOISE MASK
f1
OFFSET FREQUENCY
FIGURE 5-7:
Circuit.
HCSL Output Load and Test
f2
RMS JITTER = ¥AREA UNDER THE MASKED PHASE NOISE PLOT
FIGURE 5-5:
RMS Phase/Noise/Jitter.
2019 Microchip Technology Inc.
DS20006176A-page 15
SM802XXX
VDD = VDDA = 3.3V
VDDO = 2.5V or 3.3V
Q0
100
Z0 = 50
/Q0
GND
FIGURE 5-8:
Circuit.
LVDS Output Load and Test
+VDDO/2
VDDO
OSCILLOSCOPE
Q
Z0 = 50
50
VSS
–VDDO/2
FIGURE 5-9:
Test Circuit.
LVCMOS Output Load and
XTAL_IN
10pF PARALLEL CRYSTAL
XTAL_OUT
FIGURE 5-10:
DS20006176A-page 16
Crystal Input Interface.
2019 Microchip Technology Inc.
SM802XXX
6.0
PACKAGING INFORMATION
44-Lead QFN Package Outline and Recommended Land Pattern
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
2019 Microchip Technology Inc.
DS20006176A-page 17
SM802XXX
32-Lead QFN Package Outline and Recommended Land Pattern
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
DS20006176A-page 18
2019 Microchip Technology Inc.
SM802XXX
24-Lead QFN Package Outline and Recommended Land Pattern
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
2019 Microchip Technology Inc.
DS20006176A-page 19
SM802XXX
16-Lead QFN Package Outline and Recommended Land Pattern
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
DS20006176A-page 20
2019 Microchip Technology Inc.
SM802XXX
APPENDIX A:
REVISION HISTORY
Revision A (March 2019)
• Converted Micrel document SM802xxx to Microchip data sheet DS20006176A.
• Minor text changes throughout.
• Updated the Crystal and Reference Input frequency ranges in the Features section and in
Crystal Characteristics table.
• Updated ESR value in Crystal Characteristics
table.
• Updated the 12 kHz to 20 MHz Phase Jitter to
265 fs in the Features and in LVPECL AC Electrical Characteristics (Note 1, Note 2, Note 3,
Note 4).
• Updated Output Frequency minimum and typical
Phase Jitter in LVDS AC Electrical Characteristics
(Note 1, Note 2, Note 3, Note 4), HCSL AC Electrical Characteristics (Note 1, Note 2, Note 3,
Note 4), and LVCMOS AC Electrical Characteristics (Note 1, Note 2, Note 3, Note 4).
• Corrected the impedance values for using a ferrite
bead in Power Supply Decoupling section.
2019 Microchip Technology Inc.
DS20006176A-page 21
SM802XXX
NOTES:
DS20006176A-page 22
2019 Microchip Technology Inc.
SM802XXX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Examples:
PART NO.
X
X
X
X
a) SM802xxxUMG:
Device
Package
Type
Voltage
Option
Temperature
Flexible Ultra-Low Jitter Clock
Synthesizer, 2.5V/3.3V Voltage
Option, QFN Package, –40°C to
Special
Processing
+85°C Temperature Range, Tray
Device:
SM802xxx:
Voltage Option:
U
Package Type:
M
= 44-, 32-, 24-, or 16-QFN; see the Package
Options Table (Note 1).
Temperature:
G
=
–40°C to +85°C (NiPdAu Lead Free)
Special
Processing:
Blank
TR
=
=
Tray
Tape and Reel
=
Flexible Ultra-Low Jitter Clock Synthesizer
b) SM802xxxUMG-TR: Flexible Ultra-Low Jitter Clock
Synthesizer, 2.5V/3.3V Voltage
Option, QFN Package, –40°C to
+85°C Temperature Range, Tape &
Reel
2.5V/3.3V
Package Options Table (Note 1)
Package
Option
QFN
Package
# of
Outputs
XTAL
REF_IN
XTAL_SEL
FSEL
OE1
OE2
PLL
BYPASS
#1
44-Pin 7x7
8 Diff.
Yes
Yes
Yes
Yes
Yes
Yes
#2
32-Pin 5x5
4 Diff.
Yes
Yes
Yes
Yes
Yes
Yes
#3
24-Pin 4x4
4 Diff.
Yes
Yes
Yes
No
No
Yes
#4
24-Pin 4x4
2 Diff.
Yes
Yes
Yes
Yes
Yes
Yes
#5
16-Pin 3x3.5
2 Diff.
No
Yes
No
Yes
No
No
16-Pin 3x3.5
2 Diff.
Yes
No
No
No
No
No
#6
Note 1:
Use the web tool at http://clockworks.microchip.com/micrel/ to determine the desired configuration.
2019 Microchip Technology Inc.
DS20006176A-page 23
SM802XXX
NOTES:
DS20006176A-page 24
2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-4300-1
== ISO/TS 16949 ==
2019 Microchip Technology Inc.
DS20006176A-page 25
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DS20006176A-page 26
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2019 Microchip Technology Inc.
08/15/18