Not recommended for new designs.
Please use SST25VF020B
2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
SST serial flash family features a four-wire, SPI-compatible interface that allows
for a low pin-count package occupying less board space and ultimately lowering
total system costs. SST25LF020A SPI serial flash memory is manufactured with
SST proprietary, high performance CMOS SuperFlash Technology. The split-gate
cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.
Features
• Single 3.0-3.6V Read and Write Operations
• End-of-Write Detection
– Software Status
• Serial Interface Architecture
• Hold Pin (HOLD#)
– SPI Compatible: Mode 0 and Mode 3
– Suspends a serial sequence to the memory
without deselecting the device
• 33 MHz Max Clock Frequency
• Superior Reliability
• Write Protection (WP#)
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
– Enables/Disables the Lock-Down function of the status
register
• Low Power Consumption:
• Software Write Protection
– Active Read Current: 7 mA (typical)
– Standby Current: 8 µA (typical)
– Write protection through Block-Protection bits in status
register
• Flexible Erase Capability
• Temperature Range
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
– Extended: -20°C to +85°C
• Fast Erase and Byte-Program:
• Packages Available
– Chip-Erase Time: 70 ms (typical)
– Sector- or Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over Byte-Program operations
©2011 Silicon Storage Technology, Inc.
– 8-lead SOIC 150 mil body width
for SST25LF020A
– 8-contact WSON (5mm x 6mm)
• All non-Pb (lead-free) devices are RoHS compliant
www.microchip.com
DS25080A
11/11
2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
Product Description
SST’s serial flash family features a four-wire, SPI-compatible interface that allows for a low pincount package occupying less board space and ultimately lowering total system costs.
SST25LF020A SPI serial flash memories are manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared with alternate approaches.
The SST25LF020A devices significantly improve performance, while lowering power consumption.
The total energy consumed is a function of the applied voltage, current, and time of application.
Since for any given voltage range, the SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed during any Erase or Program operation is
less than alternative flash memory technologies. The SST25LF020A devices operate with a single
3.0-3.6V power supply.
The SST25LF020A devices are offered in an 8-lead SOIC 150 mil body width (SA) package, and in
an 8-contact WSON package. See Figure 2 for the pin assignments.
©2011 Silicon Storage Technology, Inc.
DS25080A
2
11/11
2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
Block Diagram
SuperFlash
Memory
X - Decoder
Address
Buffers
and
Latches
Y - Decoder
I/O Buffers
and
Data Latches
Control Logic
Serial Interface
1242 B1.0
CE#
SCK
SI
SO
WP#
HOLD#
Figure 1: Functional Block Diagram
©2011 Silicon Storage Technology, Inc.
DS25080A
3
11/11
2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
Pin Description
CE#
1
8
VDD
SO
2
7
HOLD#
WP#
3
6
SCK
VSS
4
5
SI
Top View
CE#
1
SO
2
8
VDD
7
HOLD#
Top View
WP#
3
6
SCK
VSS
4
5
SI
1242 08-wson P2.0
1242 08-soic P1.0
8-contact WSON
8-lead SOIC
Figure 2: Pin Assignments
Table 1: Pin Description
Symbol Pin Name
Functions
SCK
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
SI
Serial Data
Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data
Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
WP#
Write Protect
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD#
Hold
To temporarily stop serial communication with SPI flash memory without resetting the
device.
VDD
Power Supply
To provide power supply (3.0-3.6V).
VSS
Ground
T1.0 25080
©2011 Silicon Storage Technology, Inc.
DS25080A
4
11/11
2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
Memory Organization
The SST25LF020A SuperFlash memory array is organized in 4 KByte sectors with 32 KByte overlay
blocks.
Device Operation
The SST25LF020A is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25LF020A supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK
signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the
SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
CE#
SCK
SI
MODE 3
MODE 3
MODE 0
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1Bit 0
MSB
SO
HIGH IMPEDANCE
DON T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1242 F02.0
Figure 3: SPI Protocol
©2011 Silicon Storage Technology, Inc.
DS25080A
5
11/11
2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
Hold Operation
HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without resetting
the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD#
mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The
HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode
when the SCK next reaches the active low state. See Figure 4 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be VIL or
VIH.
If CE# is driven active high during a Hold condition, it resets the internal logic of the device. As long as
HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the
device, HOLD# must be driven active high, and CE# must be driven active low. See Figure 19 for Hold
timing.
SCK
HOLD#
Active
Hold
Active
Hold
Active
1242 F03.0
Figure 4: Hold Condition Waveform
Write Protection
SST25LF020A provides software Write protection. The Write Protect pin (WP#) enables or disables
the lock-down function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 4 for BlockProtection description.
©2011 Silicon Storage Technology, Inc.
DS25080A
6
11/11
2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined
by the value of the BPL bit (see Table 2). When WP# is high, the lock-down function of the BPL bit is
disabled.
Table 2: Conditions to execute Write-Status-Register (WRSR) Instruction
WP#
BPL
L
1
Execute WRSR Instruction
Not Allowed
L
0
Allowed
H
X
Allowed
T2.0 25080
Status Register
The software status register provides status on whether the flash memory array is available for any
Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 3 describes the function of each bit in the
software status register.
Table 3: Software Status Register
Default at
Power-up
Read/Write
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
WEL
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
0
R
2
BP0
Indicate current level of block write protection (See
Table 4)
1
R/W
3
BP1
Indicate current level of block write protection (See
Table 4)
1
R/W
4:5
RES
Reserved for future use
0
N/A
6
AAI
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
0
R
7
BPL
1 = BP1, BP0 are read-only bits
0 = BP1, BP0 are read/writable
0
R/W
Bit
Name
Function
0
BUSY
1
T3.0 25080
Busy
The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for
the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is
ready for the next valid operation.
©2011 Silicon Storage Technology, Inc.
DS25080A
7
11/11
2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the
Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset),
it indicates the device is not Write enabled and does not accept any memory Write (Program/Erase)
commands. The Write-Enable-Latch bit is automatically reset under the following conditions:
•
•
•
•
•
•
•
Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instruction completion
Auto Address Increment (AAI) programming reached its highest memory address
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
Block Protection (BP1, BP0)
The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table 4, to be
software protected against any memory Write (Program or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the BlockProtect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are both 0. After
power-up, BP1 and BP0 are set to 1.
Block Protection Lock-Down (BPL)
WP# pin driven low (VIL), enables the Block-Protection-Lock-Down (BPL) bit. When BPL is set to 1, it
prevents any further alteration of the BPL, BP1, and BP0 bits. When the WP# pin is driven high (VIH),
the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
Table 4: Software Status Register Block Protection1
Status Register Bit
Protected Memory Area
Protection Level
BP1
BP0
2 Mbit
0
0
0
None
1 (1/4 Memory Array)
0
1
030000H-03FFFFH
2 (1/2 Memory Array)
1
0
020000H-03FFFFH
3 (Full Memory Array)
1
1
000000H-03FFFFH
T4.0 25080
1. Default at power-up for BP1 and BP0 is ‘11’.
Auto Address Increment (AAI)
The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI
programming mode or Byte-Program mode. The default at power up is Byte-Program mode.
©2011 Silicon Storage Technology, Inc.
DS25080A
8
11/11
2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
Instructions
Instructions are used to Read, Write (Erase and Program), and configure the SST25LF020A. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or
Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list
of the instructions is provided in Table 5. All instructions are synchronized off a high to low transition of
CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must
be driven low before an instruction is entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read-ID and Read-Status-Register instructions). Any low to high
transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction
in progress and return the device to the standby mode. Instruction commands (Op Code), addresses,
and data are all input from the most significant bit (MSB) first.
Table 5: Device Operation Instructions1
Bus Cycle4
Max
Freq
MHz
SIN
SOUT
SIN
SOUT
SIN
SOUT
SIN
20
03H
Hi-Z
A23A16
Hi-Z
A15A8
Hi-Z
High-Speed-Read
0BH
Hi-Z
A23A16
Hi-Z
A15A8
Sector-Erase5,6
20H
Hi-Z
A23A16
Hi-Z
Block-Erase5,7
52H
Hi-Z
A23A16
Hi-Z
Chip-Erase6
60H
Hi-Z
-
-
-
-
-
-
-
-
Byte-Program6
02H
Hi-Z
A23A16
Hi-Z
A15A8
Hi-Z
A7-A0
Hi-Z
DIN
Hi-Z
Auto Address Increment
(AAI) Single-Byte
Program6,8
AFH
Hi-Z
A23A16
Hi-Z
A15A8
Hi-Z
A7-A0
Hi-Z
DIN
Hi-Z
05H
Hi-Z
X
DOUT
-
Note
-
Note
-
Note9
Cycle Type/
Operation2,3
Read
Read-Status-Register
(RDSR)
33
1
2
3
4
5
6
SOUT SIN
SOUT
A7-A0
Hi-Z
X
DOUT
Hi-Z
A7-A0
Hi-Z
X
X
A15A8
Hi-Z
A7-A0
Hi-Z
-
-
A15A8
Hi-Z
A7-A0
Hi-Z
-
-
9
SIN SOUT
X
DOUT
9
Enable-Write-StatusRegister
(EWSR)10
50H
Hi-Z
-
-
-
-
-
-
-
-
Write-Status-Register
(WRSR)10
01H
Hi-Z
Data
Hi-Z
-
-
-.
-
-
-
Write-Enable (WREN)
06H
Hi-Z
-
-
-
-
-
-
-
-
Write-Disable (WRDI)
04H
Hi-Z
-
-
-
-
-
-
-
-
Read-ID
90H
or
ABH
Hi-Z
00H
Hi-Z
00H
Hi-Z
ID
Addr
Hi-Z
X
DOUT
12
11
T5.0 25080
1. AMS = Most Significant Address
AMS = A17 for SST25LF020A
Address bits above the most significant bit of each density can be VIL or VIH
2. Operation: SIN = Serial In, SOUT = Serial Out
3. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary)
4. One bus cycle is eight clock periods.
5. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH
6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable
(WREN) instruction must be executed.
©2011 Silicon Storage Technology, Inc.
DS25080A
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11/11
2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
7. Block addresses for: use AMS-A15, remaining addresses can be VIL or VIH
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
followed by the data to be programmed.
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in
conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR
instruction to make both instructions effective.
11. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer
and Device ID output stream is continuous until terminated by a low to high transition on CE#
12. Device ID = 43H for SST25LF020A
Read (20 MHz)
The Read instruction supports up to 20 MHz, it outputs the data starting from the specified address
location. The data output stream is continuous through all addresses until terminated by a low to high
transition on CE#. The internal address pointer will automatically increment until the highest memory
address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 2 Mbit density, once the
data from address location 3FFFFH had been read, the next output will be from address location
00000H.
The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23A0]. CE# must remain active low for the duration of the Read cycle. See Figure 5 for the Read
sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
03
SI
ADD.
ADD.
MSB
MSB
SO
15 16
23 24
31 32
39 40
47
48
55 56
63 64
70
MODE 0
HIGH IMPEDANCE
ADD.
N
DOUT
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSB
1242 F04.0
Figure 5: Read Sequence
©2011 Silicon Storage Technology, Inc.
DS25080A
10
11/11
2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
High-Speed-Read (33 MHz)
The High-Speed-Read instruction supporting up to 33 MHz is initiated by executing an 8-bit command,
0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration
of the High-Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence.
Following a dummy byte (8 clocks input dummy cycle), the High-Speed-Read instruction outputs the
data starting from the specified address location. The data output stream is continuous through all
addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is
reached, the address pointer will automatically increment to the beginning (wrap-around) of the
address space, i.e. for 2 Mbit density, once the data from address location 03FFFFH has been read,
the next output will be from address location 000000H.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
MODE 0
ADD.
MSB
0B
SI
MSB
ADD.
ADD.
X
N+1
DOUT
N
DOUT
HIGH IMPEDANCE
SO
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSB
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH)
1242 F05.0
Figure 6: High-Speed-Read Sequence
Byte-Program
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected
byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction
applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain
active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by
executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is
input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBP for the completion of
the internal self-timed Byte-Program operation. See Figure 7 for the Byte-Program sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39
MODE 0
02
SI
ADD.
ADD.
MSB
MSB
SO
ADD.
DIN
MSB
LSB
HIGH IMPEDANCE
1242 F06.0
Figure 7: Byte-Program Sequence
©2011 Silicon Storage Technology, Inc.
DS25080A
11
11/11
2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
Auto Address Increment (AAI) Program
The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the
next sequential address location. This feature decreases total programming time when the entire memory array is to be programmed. An AAI program instruction pointing to a protected memory area will be
ignored. The selected address range must be in the erased state (FFH) when initiating an AAI program
instruction.
Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI program
instruction is initiated by executing an 8-bit command, AFH, followed by address bits [A23-A0]. Following the addresses, the data is input sequentially from MSB (bit 7) to LSB (bit 0). CE# must be driven
high before the AAI program instruction is executed. The user must poll the BUSY bit in the software
status register or wait TBP for the completion of each internal self-timed Byte-Program cycle. Once the
device completes programming byte, the next sequential address may be program, enter the 8-bit
command, AFH, followed by the data to be programmed. When the last desired byte had been programmed, execute the Write-Disable (WRDI) instruction, 04H, to terminate AAI. After execution of the
WRDI command, the user must poll the Status register to ensure the device completes programming.
See Figure 8 for AAI programming sequence.
There is no wrap mode during AAI programming; once the highest unprotected memory address is
reached, the device will exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0).
TBP
TBP
CE#
MODE 3
SCK
SI
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32 33 34 35 36 37 38 39
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 1
MODE 0
AF
A[23:16] A[15:8]
Data Byte 1
A[7:0]
Data Byte 2
AF
TBP
CE#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
SI
AF
Last Data Byte
05
04
Write Disable (WRDI)
Instruction to terminate
AAI Operation
Read Status Register (RDSR)
Instruction to verify end of
AAI Operation
DOUT
SO
1242 F07.0
Figure 8: Auto Address Increment (AAI) Program Sequence
©2011 Silicon Storage Technology, Inc.
DS25080A
12
11/11
2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area will be ignored. Prior to any Write operation, the WriteEnable (WREN) instruction must be executed. CE# must remain active low for the duration of the any
command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23-A0]. Address bits [AMS-A12] (AMS = Most Significant address) are used to
determine the sector address (SAX), remaining address bits can be VIL or VIH. CE# must be driven high
before the instruction is executed. The user may poll the Busy bit in the software status register or wait
TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 9 for the Sector-Erase
sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31
MODE 0
ADD.
ADD.
20
SI
MSB
ADD.
MSB
SO
HIGH IMPEDANCE
1242 F08.0
Figure 9: Sector-Erase Sequence
Block-Erase
The Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be ignored. Prior to any Write operation, the WriteEnable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The Block-Erase instruction is initiated by executing an 8-bit command, 52H, followed
by address bits [A23-A0]. Address bits [AMS-A15] (AMS = Most significant address) are used to determine block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the
instruction is executed. The user may poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Erase cycle. See Figure 10 for the Block-Erase sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE 0
52
SI
MSB
ADD.
ADD.
ADD.
MSB
SO
HIGH IMPEDANCE
1242 F09.0
Figure 10:Block-Erase Sequence
©2011 Silicon Storage Technology, Inc.
DS25080A
13
11/11
2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored
if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence.
The Chip-Erase instruction is initiated by executing an 8-bit command, 60H. CE# must be driven high
before the instruction is executed. The user may poll the Busy bit in the software status register or wait TCE
for the completion of the internal self-timed Chip-Erase cycle. See Figure 11 for the Chip-Erase
sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
60
SI
MSB
SO
HIGH IMPEDANCE
1242 F10.0
Figure 11:Chip-Erase Sequence
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register
may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in
progress, the Busy bit may be checked before sending any new commands to assure that the new
commands are properly received by the device. CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing
clock cycles until it is terminated by a low to high transition of the CE#. See Figure 12 for the RDSR
instruction sequence.
CE#
MODE 3
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MODE 0
05
SI
MSB
SO
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
Status
Register Out
1242 F11.0
Figure 12:Read-Status-Register (RDSR) Sequence
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2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-Enable-Latch bit to 1 allowing Write operations to
occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE#
must be driven high before the WREN instruction is executed.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
06
SI
MSB
SO
HIGH IMPEDANCE
1242 F12.0
Figure 13:Write Enable (WREN) Sequence
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-Enable-Latch bit and AAI bit to 0 disabling any
new Write operations from occurring. CE# must be driven high before the WRDI instruction is executed.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
04
SI
MSB
SO
HIGH IMPEDANCE
1242 F13.0
Figure 14:Write Disable (WRDI) Sequence
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR)
instruction and opens the status register for alteration. The Enable-Write-Status-Register instruction
does not have any effect and will be wasted, if it is not followed immediately by the Write-Status-Register (WRSR) instruction. CE# must be driven low before the EWSR instruction is entered and must be
driven high before the EWSR instruction is executed.
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2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
Write-Status-Register (WRSR)
The Write-Status-Register instruction works in conjunction with the Enable-Write-Status-Register
(EWSR) instruction to write new values to the BP1, BP0, and BPL bits of the status register. The WriteStatus-Register instruction must be executed immediately after the execution of the Enable-Write-Status-Register instruction (very next instruction bus cycle). This two-step instruction sequence of the
EWSR instruction followed by the WRSR instruction works like SDP (software data protection) command structure which prevents any accidental alteration of the status register values. The Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to “1”. When the WP# is
low, the BPL bit can only be set from “0” to “1” to lock-down the status register, but cannot be reset
from “1” to “0”. When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0,
and BP1 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP# pin is
driven high (VIH) prior to the low-to-high transition of the CE# pin at the end of the WRSR instruction,
the BP0, BP1, and BPL bit in the status register can all be altered by the WRSR instruction. In this
case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as
altering the BP0 and BP1 bit at the same time. See Table 2 for a summary description of WP# and BPL
functions. CE# must be driven low before the command sequence of the WRSR instruction is entered
and driven high before the WRSR instruction is executed. See Figure 15 for EWSR and WRSR instruction sequences.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 3
MODE 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MODE 0
01
50
SI
MSB
MSB
STATUS
REGISTER IN
7 6 5 4 3 2 1 0
MSB
HIGH IMPEDANCE
SO
1242 F14.0
Figure 15:Enable-Write-Status-Register (EWSR) and Write-Status-Register (WRSR)
Sequence
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DS25080A
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2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
Read-ID
The Read-ID instruction identifies the devices as SST25LF020A and manufacturer as SST. The device
information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A23A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H and the
device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer’s and
device ID output data toggles between address 00000H and 00001H until terminated by a low to high
transition on CE#.
Table 6: Product Identification
Manufacturer’s ID
Address
Data
00000H
BFH
00001H
43H
Device ID
SST25LF020A
T6.0 25080
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
90 or AB
SI
00
00
MSB
SO
23 24
15 16
31 32
39 40
47 48
55 56
63
MODE 0
ADD1
MSB
HIGH IMPEDANCE
BF
Device ID
BF
Device ID
HIGH
IMPEDANCE
MSB
Note: The manufacturer s and device ID output stream is continuous until terminated by a low to high transition on CE#.
1. 00H will output the manfacturer s ID first and 01H will output device ID first before toggling between the two.
1242 F15.0
Figure 16:Read-ID Sequence
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DS25080A
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2 Mbit SPI Serial Flash
SST25LF020A
A Microchip Technology Company
Not Recommended for New Designs
Electrical Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these conditions or conditions greater than those defined in the operational sections
of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (