SST25PF040C
4-Mbit, 3.3V, SPI Serial Flash
Features
• Single Voltage Read and Write Operations
- 2.3V-3.6V
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
• High-Speed Clock Frequency
- 40 MHz
• Dual Input/Output Support
- Fast-Read Dual-Output Instruction (3BH)
- Fast-Read Dual I/O Instruction (BBH)
• Superior Reliability
- Endurance: 100,000 Cycles
- Greater than 20 years Data Retention
• Ultra-Low Power Consumption:
- Active Read current: 5 mA (typical)
- Standby current: 5 µA (typical)
- Power-down Mode Standby current: 3 µA
(typical)
• Flexible Erase Capability
- Uniform 4-Kbyte sectors
- Uniform 64-Kbyte overlay blocks
• Page Program Mode
- 256 bytes per Page
• Fast Erase and Page Program:
- Chip Erase Time: 250 ms (typical)
- Sector Erase Time: 40 ms (typical)
- Block Erase Time: 80 ms (typical)
- Page Program Time: 4 ms/ 256 bytes
(typical)
• End-of-Write Detection
- Software polling the BUSY bit in STATUS
Register
• Hold Pin (HOLD#)
- Suspend a serial sequence without
deselecting the device
• Write Protection (WP#)
- Enables/Disables the Lock-Down function of
the STATUS register
• Software Write Protection
- Write protection through Block-Protection bits
in STATUS register
2015-2022 Microchip Technology Inc. and its subsidiaries
• Temperature Range
- Industrial: -40°C to +85°C
- Industrial Plus: -40°C to +105°C
- Extended: -40°C to +125°C
• Automotive AEC-Q100 Qualified
• All devices are RoHS compliant
Packages
• 8-contact USON (2 mm x 3 mm)
• 8-lead SOIC (150 mils)
• 8-contact WDFN (5 mm x 6 mm)
Product Description
SST25PF040C is a member of the Serial Flash 25
Series family and feature a four-wire, SPI-compatible
interface that allows for a low pin-count package which
occupies less board space and ultimately lowers total
system costs. SPI serial flash memory is manufactured
with
proprietary,
high-performance
CMOS
SuperFlash® technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
This Serial Flash significantly improve performance
and reliability, while lowering power consumption. The
device writes (Program or Erase) with a single power
supply of 2.3V-3.6V. The total energy consumed is a
function of the applied voltage, current, and time of
application. Since for any given voltage range, the
SuperFlash technology uses less current to program
and has a shorter erase time, the total energy consumed during any Erase or Program operation is less
than alternative flash memory technologies.
See Figure 2-1 for the pin assignments.
DS20005397F-page 1
SST25PF040C
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS20005397F-page 2
2015-2022 Microchip Technology Inc. and its subsidiaries
SST25PF040C
1.0
FUNCTIONAL BLOCKS
FIGURE 1-1:
FUNCTIONAL BLOCK DIAGRAM
X - Decoder
Address
Buffers
and
Latches
SuperFlash
Memory
Y - Decoder
Control Logic
I/O Buffers
and
Data Latches
Serial Interface
CE#
SCK
2015-2022 Microchip Technology Inc. and its subsidiaries
SI/ SO/ WP#
SIO0 SIO1
HOLD#
DS20005397F-page 3
SST25PF040C
2.0
PIN ASSIGNMENTS
FIGURE 2-1:
PIN ASSIGNMENTS
8-Lead SOIC
8-Contact USON 2x3 mm
CE# 1
CE#
1
8
VDD
SO/SIO1
2
7
HOLD#
WP#
3
6
SCK
WP# 3
VSS
4
5
SI/SIO0
VSS 4
8 VDD
SO/SIO1 2
7 HOLD#
Top View
6 SCK
5 SI/SIO0
8-Contact WDFN 5x6 mm
CE#
1
SO/SIO1
2
8
VDD
7
HOLD#
Top View
TABLE 2-1:
WP#
3
6
SCK
VSS
4
5
SI/SIO0
PIN DESCRIPTION
Symbol
Pin Name
Functions
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence. The device is deselected and
placed in Standby mode when CE# is high.
SO
Serial Data Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
SIO[0:1]
To transfer commands, addresses, or data serially into the device, or data out of
Serial Data Input/
the device. Inputs are latched on the rising edge of the serial clock. Data is
Output for Dual I/O
shifted out on the falling edge of the serial clock. These pins are used in Dual
Mode
I/O mode
WP#
Write-Protect
VSS
Ground
VDD
Power Supply
To provide power supply voltage: 2.3V-3.6V
HOLD#
Hold
To temporarily stop serial communication with SPI Flash memory while device
is selected.
SCK
Serial Clock
To provide the input/output timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
DS20005397F-page 4
The Write-Protect (WP#) pin is used to enable/disable BPL bit in the STATUS
register.
2015-2022 Microchip Technology Inc. and its subsidiaries
SST25PF040C
3.0
MEMORY ORGANIZATION
The SST25PF040C SuperFlash memory arrays are
organized in 128 uniform 4-Kbyte sectors, with eight
64-Kbyte overlay erasable blocks.
MEMORY MAP
Number of Sectors
Top of Memory Block
127
07FFFFH
07F000H
7
...
Number of 64-Kbyte
Blocks
...
FIGURE 3-1:
070FFFH
070000H
...
...
01FFFFH
01F000H
...
1
31
...
...
112
01FFFFH
010000H
00FFFFH
00F000H
16
...
0
...
15
001FFFH
001000H
000FFFH
000000H
1
0
Bottom of Memory Block
4.0
DEVICE OPERATION
SST25PF040C is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI
bus consist of four control lines: Chip Enable (CE#) is
used to select the device, and data is accessed through
the Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK).
FIGURE 4-1:
The SST25PF040C supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 4-1, is the
state of the SCK signal when the bus host is in Standby mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode
3. For both modes, the Serial Data In (SI) is sampled at
the rising edge of the SCK clock signal and the Serial
Data Output (SO) is driven after the falling edge of the
SCK clock signal.
SPI PROTOCOL
CE#
SCK
SI
MODE 3
MODE 3
MODE 0
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSb
SO
High-Impediance
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSb
2015-2022 Microchip Technology Inc. and its subsidiaries
DS20005397F-page 5
SST25PF040C
4.0.1
HOLD
In the hold mode, serial sequences underway with the
SPI Flash memory are paused without resetting the
clocking sequence. To activate the HOLD# mode, CE#
must be in active low state. The HOLD# mode begins
when the SCK active low state coincides with the falling
edge of the HOLD# signal. The Hold mode ends when
the rising edge of the HOLD# signal coincides with the
SCK active low state. HOLD# must not rise or fall when
SCK logic level is high. See Figure 4-2 for Hold Condition waveform.
FIGURE 4-2:
Once the device enters Hold mode, SO will be in highimpedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, the
device returns to standby mode. The device can then
be re-initiated with the command sequences listed in
Table 5-1. As long as HOLD# signal is low, the memory
remains in the Hold condition. To resume communication with the device, HOLD# must be driven active high,
and CE# must be driven active low. See Figure 4-2 for
Hold timing.
HOLD CONDITION WAVEFORM
SCK
HOLD#
Active
4.1
Hold
Active
Write Protection
SST25PF040C provides software Write protection. The
Write-Protect pin (WP#) enables or disables the lockdown function of the STATUS register. The Block Protection bits (BP0, BP1, BP2, TB, and BPL) in the STATUS register provide Write protection to the memory
array and the STATUS register. See Table 4-3 for the
Block-Protection description.
TABLE 4-1:
4.1.1
WRITE-PROTECT PIN (WP#)
The Write-Protect (WP#) pin enables the lock-down
function of the BPL bit (bit 7) in the STAUS register.
When WP# is driven low, the execution of the Write
STATUS Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 4-1). When WP# is
high, the lock-down function of the BPL bit is disabled.
CONDITIONS TO EXECUTE WRITE STATUS REGISTER (WRSR) INSTRUCTION
WP#
BPL
L
1
Not Allowed
L
0
Allowed
H
X
Allowed
DS20005397F-page 6
Execute WRSR Instruction
2015-2022 Microchip Technology Inc. and its subsidiaries
SST25PF040C
4.2
STATUS Register
The software STATUS register provides status on
whether the flash memory array is available for any
read or write operation, whether the device is Write
enabled, and the state of the Memory Write protection.
TABLE 4-2:
Bit
SOFTWARE STATUS REGISTER
Name
Function
Default at
Power-up
Read/Write
0
BUSY
Write operation status
1 = Internal write operation is in progress
0 = No internal write operation is in progress
0
R
1
WEL
Write Enable Latch status
1 = Device is memory write-enabled
0 = Device is not memory write-enabled
0
R
2
BP0
Indicate current level of block write protection (See Table 4-3)
0 or 1
R/W
3
BP1(1)
Indicate current level of block write protection (See Table 4-3)
0 or 1
R/W
4
BP2(1)
Indicate current level of block write protection (See Table 4-3)
0 or 1
R/W
5
TB(1)
1 = 1/8, 1/4, or 1/2 Bottom Memory Blocks are protected (See Table 4-3)
0 = 1/8, 1/4, or 1/2 Top Memory Blocks are protected
0 or 1
R/W
6
RES
Reserved for future use
0
N/A
7
BPL(1)
1 = BP0, BP1, BP2, TB, and BPL are read-only bits
0 = BP0, BP1, BP2, TB, and BPL are read/writable
0 or 1
R/W
Note 1:
4.2.1
BP0, BP1, BP2, TB, and BPL bits are non-volatile memory bits.
BUSY (BIT 0)
The BUSY bit determines whether there is an internal
Erase or Program operation in progress. A ‘1’ for the
BUSY bit indicates the device is busy with an operation
in progress. A ‘0’ indicates the device is ready for the
next valid operation.
4.2.2
WRITE ENABLE LATCH (WEL–BIT 1)
The Write-Enable Latch bit indicates the status of the
internal Write-Enable Latch memory. If the WEL bit is
set to ‘1’, it indicates the device is Write enabled. If the
bit is set to ‘0’ (reset), it indicates the device is not Write
enabled and does not accept any Write (Program/
Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions:
•
•
•
•
•
•
•
During an internal erase or program operation, the
STATUS register may be read only to determine the
completion of an operation in progress. Table 4-2
describes the function of each bit in the software STATUS register.
4.2.3
BLOCK PROTECTION (BP0, BP1,
BP2, AND TB–BITS 2, 3, 4, AND 5)
The Block Protection (BP0, BP1, BP2, and TB) bits
define the size of the memory area to be software protected against any memory Write (Program or Erase)
operation, see Table 4-3. The Write STATUS Register
(WRSR) instruction is used to program the BP0, BP1,
BP2, and TB bits as long as WP# is high or the Block
Protect Lock (BPL) bit is ‘0’. Chip Erase can only be
executed if Block Protection bits are all ‘0’. BP0, BP1,
and BP2 select the protected area and TB allocates the
protected area to the higher-order address area (Top
Blocks) or lower-order address area (Bottom Blocks).
Power-Up
Write Disable (WRDI) instruction completion
Page Program instruction completion
Sector Erase instruction completion
64-Kbyte Block Erase instruction completion
Chip Erase instruction completion
Write STATUS Register instruction completion
2015-2022 Microchip Technology Inc. and its subsidiaries
DS20005397F-page 7
SST25PF040C
4.2.4
BLOCK PROTECTION LOCK-DOWN
(BPL–BIT 7)
BP1, BP2, TB, and BPL bits. When the WP# pin is
driven high (VIH), the BPL bit has no effect and its value
is ‘Don’t Care’.
When the WP# pin is driven low (VIL), it enables the
Block Protection Lock-Down (BPL) bit. When BPL is
set to ‘1’, it prevents any further alteration of the BP0,
TABLE 4-3:
SOFTWARE STATUS REGISTER BLOCK PROTECTION
Protection Level
STATUS Register Bit
TB
BP2
BP1
BP0
Protected Memory Address
0 (Full Memory Array unprotected)
X
0
0
0
None
T1 (1/8 Top Memory Block protected)
0
0
0
1
070000H-07FFFFH
T2 (1/4 Top Memory Block protected)
0
0
1
0
060000H-07FFFFH
T3 (1/2 Top Memory Block protected)
0
0
1
1
040000H-07FFFFH
B1 (1/8 Bottom Memory Block protected)
1
0
0
1
000000H-00FFFFH
B2 (1/4 Bottom Memory Block protected)
1
0
1
0
000000H-01FFFFH
B3 (1/2 Bottom Memory Block protected)
1
0
1
1
000000H-03FFFFH
4 (Full Memory Block protected)
X
1
X
X
000000H-07FFFFH
DS20005397F-page 8
2015-2022 Microchip Technology Inc. and its subsidiaries
SST25PF040C
5.0
INSTRUCTIONS
Instructions are used to read, write (erase and program), and configure the SST25PF040C devices. The
instruction bus cycles are 8 bits each for commands
(Op Code), data, and addresses. The Write Enable
(WREN) instruction must be executed prior to Sector
Erase, Block Erase, Page Program, Write STATUS
Register, or Chip Erase instructions. The complete
instructions are provided in Table 5-1. All instructions
are synchronized off a high-to-low transition of CE#.
Inputs will be accepted on the rising edge of SCK start-
TABLE 5-1:
Instruction
Read
DEVICE OPERATION INSTRUCTIONS
Description
Read Memory
Note 1:
2:
3:
4:
5:
6:
7:
8:
ing with the most significant bit. CE# must be driven low
before an instruction is entered and must be driven
high after the last bit of the instruction has been shifted
in (except for Read, Read-ID, and Read STATUS Register instructions). Any low-to-high transition on CE#,
before receiving the last bit of an instruction bus cycle,
will terminate the instruction in progress and return the
device to standby mode. Instruction commands (Op
Code), addresses, and data are all input from the most
significant bit (MSb) first.
Op Code Cycle(1)
0000 0011b (03H)
Address Dummy
Data
Maximum
Cycle(s)(2) Cycle(s) Cycle(s) Frequency
3
0
1 to
25 MHz
One bus cycle is eight clock periods.
Address bits above the most significant bit of each density can be VIL or VIH.
One bus cycle is four clock periods in Dual Operation.
4-Kbyte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either
at VIL or VIH.
64-Kbyte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either
at VIL or VIH.
The Read STATUS Register is continuous with ongoing clock cycles until terminated by a low-to-high transition on CE#.
Device ID is read after three dummy address bytes. The Device ID output stream is continuous until terminated by a low-to-high transition on CE#.
The instructions Release from Deep Power down and Read-ID are similar instructions (ABH). Executing
Read-ID requires the ABH instruction, followed by 24 dummy address bits to retrieve the Device ID.
Release from Deep Power-Down only requires the instruction ABH.
2015-2022 Microchip Technology Inc. and its subsidiaries
DS20005397F-page 9
SST25PF040C
TABLE 5-1:
DEVICE OPERATION INSTRUCTIONS (CONTINUED)
Instruction
Description
Op Code Cycle(1)
Address Dummy
Data
Maximum
Cycle(s)(2) Cycle(s) Cycle(s) Frequency
High-Speed Read
Read Memory at Higher
Speed
0000 1011b (0BH)
3
1
1 to
Fast-Read
Dual-Output
Read Memory with Dual
Output
0011 1011b (3BH)
3
1 (3)
1 to (3)
Fast-Read
Dual I/O
Read Memory with Dual
Address Input and Data Output
1011 1011b (BBH)
3(3)
1(3)
1 to (3)
4-Kbyte
Sector-Erase(4)
Erase 4 -Kbyte of memory
array
0010 0000b (20H)
1101 0111b (D7H)
3
0
0
64-Kbyte
Block-Erase(5)
Erase 64-Kbyte block
of memory array
1101 1000b (D8H)
3
0
0
Chip-Erase
Erase Full Memory Array
0110 0000b (60H)
or
1100 0111b (C7H)
0
0
0
Page Program
To program up to 256 Bytes
0000 0010b (02H)
3
0
1 to 256
RDSR(6)
Read STATUS Register
0000 0101b (05H)
0
0
1 to
WRSR
Write STATUS Register
0000 0001b (01H)
0
0
1
WREN
Write Enable
0000 0110b (06H)
0
0
0
WRDI
Write Disable
0000 0100b (04H)
0
0
0
RDID(7, 8)
Read-ID
1010 1011b (ABH)
3
0
1 to
JEDEC-ID
JEDEC ID Read
1001 1111b (9FH)
0
0
4 to
DPD
Deep Power-Down Mode
1011 1001b (B9H)
0
0
0
RDPD(8)
Release from Deep PowerDown or Read ID
1010 1011b (ABH)
0
0
0
Note 1:
2:
3:
4:
5:
6:
7:
8:
40 MHz
One bus cycle is eight clock periods.
Address bits above the most significant bit of each density can be VIL or VIH.
One bus cycle is four clock periods in Dual Operation.
4-Kbyte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either
at VIL or VIH.
64-Kbyte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either
at VIL or VIH.
The Read STATUS Register is continuous with ongoing clock cycles until terminated by a low-to-high transition on CE#.
Device ID is read after three dummy address bytes. The Device ID output stream is continuous until terminated by a low-to-high transition on CE#.
The instructions Release from Deep Power down and Read-ID are similar instructions (ABH). Executing
Read-ID requires the ABH instruction, followed by 24 dummy address bits to retrieve the Device ID.
Release from Deep Power-Down only requires the instruction ABH.
DS20005397F-page 10
2015-2022 Microchip Technology Inc. and its subsidiaries
SST25PF040C
5.1
Read (25 MHz)
The Read instruction, 03H, supports up to 25 MHz
Read. The device outputs a data stream starting from
the specified address location. The data stream is continuous through all addresses until terminated by a lowto-high transition on CE#. The internal address pointer
automatically increments until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer automatically incre-
FIGURE 5-1:
ments to the beginning (wrap-around) of the address
space. For example, for 4 Mbit density, once the data
from the address location 7FFFFH is read, the next output is from address location 000000H. The READ
instruction is initiated by executing an 8-bit command,
03H, followed by address bits A23-A0. CE# must remain
active low for the duration of the Read cycle. See Figure 5-1 for the Read sequence.
READ SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31 32
39 40
47
48
55 56
63 64
70
MODE 0
03
SI
ADD.
ADD.
ADD.
MSb
MSb
N
DOUT
High-Impedance
SO
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSb
5.2
High-Speed Read (40 MHz)
The High-Speed Read instruction supporting up to
40 MHz Read is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a
dummy byte. CE# must remain active low for the duration of the High-Speed Read cycle. See Figure 5-2 for
the High-Speed Read sequence.
through all addresses until terminated by a low-to-high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address
space. For example, for 4-Mbit density, once the data
from address location 7FFFFH is read, the next output
will be from address location 000000H.
Following a dummy cycle, the High-Speed Read
instruction outputs the data starting from the specified
address location. The data output stream is continuous
FIGURE 5-2:
HIGH-SPEED READ SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
MODE 0
0B
SI
ADD.
ADD.
ADD.
X
MSb
SO
N
DOUT
High-Impedance
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSb
2015-2022 Microchip Technology Inc. and its subsidiaries
DS20005397F-page 11
SST25PF040C
5.3
Fast-Read Dual Output (40 MHz)
The Fast-Read Dual-Output (3BH) instruction outputs
data up to 40 MHz from the SIO0 and SIO1 pins. To initiate the instruction, execute an 8-bit command (3BH)
followed by address bits A23-A0 and a dummy byte on
SI/SIO0. Following a dummy cycle, the Fast-Read
Dual-Output instruction outputs the data starting from
the specified address location on the SIO1 and SIO0
lines. SIO1 outputs, per clock sequence, odd data bits
D7, D5, D3, and D1; and SIO0 outputs even data bits
D6, D4, D2, and D0. CE# must remain active-low for
FIGURE 5-3:
the duration of the Fast-Read Dual-Output instruction
cycle. See Figure 5-3 for the Fast-Read Dual-Output
sequence.
The data output stream is continuous through all
addresses until terminated by a low-to-high transition
on CE#. The internal address pointer will automatically
increment until the highest memory address is
reached. Once the highest memory address is
reached, the address pointer automatically increments
to the beginning (wraparound) of the address space.
For 4-Mbit density, once the data from address location
7FFFFH has been read the next output will be from
address location 000000H.
FAST-READ DUAL OUTPUT SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
MODE 0
24-Bit Address
SIO
3B
ADD.
ADD.
Dummy Cycle
ADD.
X
IO, Switches from Input to Output
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
DOUT
SIO
High-Impedance
7 5 3 1
MSb
DOUT
DOUT
7 5 3 1
7 5 3 1
7 5 3 1
MSb
N
DS20005397F-page 12
DOUT
N+1
MSb
N+2
MSb
N+3
2015-2022 Microchip Technology Inc. and its subsidiaries
SST25PF040C
5.4
Fast-Read Dual I/O (40 MHz)
Following a dummy cycle, the Fast-Read Dual I/O
instruction outputs the data starting from the specified
address location on the SIO1 and SIO0 lines. SIO1 outputs, per clock sequence, odd data bits D7, D5, D3,
and D1; and SIO0 outputs even data bits D6, D4, D2,
and D0 per clock edge. CE# must remain active low for
the duration of the Fast-Read Dual I/O instruction
cycle. The data output stream is continuous through all
addresses until terminated by a low-to-high transition
on CE#.
The Fast-Read Dual I/O (BBH) instruction reduces the
total number of input clock cycles, which results in
faster data access. The device is first selected by driving Chip Enable CE# low. Fast-Read Dual I/O is initiated by executing an 8-bit command (BBH) on SI/SIO0,
thereafter, the device accepts address bits A23-A0 and
a dummy byte on SI/SIO0 and SO/SIO1. It offers the
capability to input address bits A23-A0 at a rate of two
bits per clock. Odd address bits A23 through A1 are
input on SIO1 and even address bits A22 through A0
are input on SIO0, alternately For example, the most
significant bit is input first followed by A23/22, A21/A20,
and so on. Each bit is latched at the same rising edge
of the Serial Clock (SCK). The input data during the
dummy clocks is “don’t care”. However, the SIO0 and
SIO1 pin must be in high-impedance prior to the falling
edge of the first data output clock.
FIGURE 5-4:
The internal address pointer will automatically increment until the highest memory address is reached.
Once the highest memory address is reached, the
address pointer automatically increments to the beginning (wraparound) of the address space. For example,
once the data from address location 7FFFFH is read,
the next output is from address location 000000H. See
Figure 5-4 for the Fast-Read Dual I/O sequence.
FAST-READ DUAL I/O SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
MODE 0
Dummy
Cycle
SIO0
BB
6 4 2 0 6 4 2 0 6 4 2 0
X
IO, Switches from Input to Output
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
DOUT
SIO1
7 5 3 1
7 5 3 1
A23-16
2015-2022 Microchip Technology Inc. and its subsidiaries
A15-8
7 5 3 1
A7-0
X
DOUT
DOUT
7 5 3 1
7 5 3 1
7 5 3 1
7 5 3 1 7
MSb
MSb
MSb
MSb
N
N+1
N+2
DOUT
N+3
DS20005397F-page 13
SST25PF040C
5.5
Page Program
The Page Program instruction programs up to
256 bytes of data in the memory. The data for the
selected page address must be in the erased state
(FFH) before initiating the Page-Program operation. A
Page Program applied to a protected memory area will
be ignored. Prior to the program operation, execute the
WREN instruction.
When executing Page Program, the memory range for
the SST25PF040C is divided into 256-byte page
boundaries. The device handles the shifting of more
than 256 bytes of data by maintaining the last
256 bytes as the correct data to be programmed. If the
target address for the Page Program instruction is not
the beginning of the page boundary (A[7:0] are not all
zero), and the number of bytes of data input exceeds or
overlaps the end of the address of the page boundary,
the excess data inputs wrap around and will be programmed at the start of that target page.
To execute a Page Program operation, the host drives
CE# low, then sends the Page Program command
cycle (02H), three address cycles, followed by the data
to be programmed, and then drives CE# high. The programmed data must be between 1 to 256 bytes and in
whole byte increments; sending less than a full byte will
cause the partial byte to be ignored. Poll the BUSY bit
in the STATUS register, or wait TPP, for the completion
of the internal, self-timed, Page Program operation.
See Figure 5-5 for the Page Program sequence and
Figure 6-8 for the Page Program flow chart.
FIGURE 5-5:
PAGE PROGRAM SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31 32
39
MODE 0
SI
ADD.
02
MSb
ADD.
ADD.
SO
Data Byte 0
LSb MSb
LSb MSb
LSb
High-Impedance
2079
2078
2077
2076
2075
2074
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CE#(cont’)
SCK(cont’)
SI(cont’)
Data Byte 1
MSb
SO(cont’)
DS20005397F-page 14
Data Byte 255
Data Byte 2
LSb MSb
LSb
MSb
LSb
High-Impedance
2015-2022 Microchip Technology Inc. and its subsidiaries
SST25PF040C
5.6
Sector Erase
The Sector-Erase instruction clears all bits in the
selected 4-Kbyte sector to FFH. A Sector Erase
instruction applied to a protected memory area will be
ignored. Prior to any write operation, the Write Enable
(WREN) instruction must be executed. CE# must remain
active low for the duration of any command sequence.
The Sector Erase instruction is initiated by executing
an 8-bit command, 20H or D7H, followed by address
FIGURE 5-6:
bits [A23-A0]. Address bits [AMS-A12] (AMS = Most Significant address) are used to determine the sector
address (SAX), remaining address bits can be VIL or VIH.
CE# must be driven high before the instruction is executed. Poll the BUSY bit in the Software STATUS register, or wait TSE, for the completion of the internal selftimed Sector Erase cycle. See Figure 5-6 for the Sector
Erase sequence and Figure 6-9 for the flow chart.
SECTOR ERASE SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
ADD.
20 or D7
SI
MSb
23 24
31
ADD.
ADD.
MSb
SO
5.7
15 16
MODE 0
High-Impedance
64-KByte Block Erase
The 64-Kbyte Block Erase instruction clears all bits in
the selected 64-Kbyte block to FFH. Applying this
instruction to a protected memory area results in the
instruction being ignored. Prior to any write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of any command sequence.
[A23-A0]. Address bits [AMS-A16] (AMS = Most Significant Address) determine the block address (BAX),
remaining address bits can be VIL or VIH. CE# must be
driven high before executing the instruction. Poll the BUSY
bit in the software STATUS register or wait TBE for the
completion of the internal self-timed Block-Erase cycle.
See Figure 5-7 for the 64-Kbyte Block Erase
sequences and Figure 6-9 for the flow chart.
Initiate the 64-Kbyte Block Erase instruction by executing an 8-bit command, D8H, followed by address bits
FIGURE 5-7:
64-KBYTE BLOCK ERASE SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE 0
D8
SI
MSb
SO
2015-2022 Microchip Technology Inc. and its subsidiaries
ADDR
ADDR
ADDR
MSb
High-Impedance
DS20005397F-page 15
SST25PF040C
5.8
Chip Erase
The Chip Erase instruction clears all bits in the device
to FFH. A Chip Erase instruction is ignored if any of the
memory area is protected. Prior to any write operation, the
Write Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of the Chip
Erase instruction sequence. Initiate the Chip Erase
FIGURE 5-8:
instruction by executing an 8-bit command, 60H or
C7H. CE# must be driven high before the instruction is executed. Poll the BUSY bit in the software STATUS register, or wait TSCE, for the completion of the internal selftimed Chip Erase cycle. See Figure 5-8 for the Chip
Erase sequence and Figure 6-10 for the flow chart.
CHIP ERASE SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
60 or C7
SI
MSb
SO
5.9
High-Impedance
Read STATUS Register (RDSR)
The Read STATUS Register (RDSR) instruction, 05H,
allows reading of the STATUS register. The STATUS
register may be read at any time even during a Write
(Program/Erase) operation. When a write operation is
in progress, the BUSY bit may be checked before
sending any new commands to assure that the new
commands are properly received by the device. CE#
FIGURE 5-9:
must be driven low before the RDSR instruction is
entered and remain low until the status data is read.
Read STATUS Register is continuous with ongoing
clock cycles until it is terminated by a low-to-high transition of the CE#. See Figure 5-9 for the RDSR instruction sequence.
READ STATUS REGISTER (RDSR) SEQUENCE
CE#
MODE 3
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MODE 0
05
SI
MSb
SO
High-Impedance
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSb
DS20005397F-page 16
STATUS
Register Out
2015-2022 Microchip Technology Inc. and its subsidiaries
SST25PF040C
5.10
Write Enable (WREN)
The Write Enable (WREN) instruction, 06H, sets the
Write Enable Latch bit in the STATUS Register to ‘1’
allowing write operations to occur. The WREN instruction
must be executed prior to any Write (Program/Erase)
operation. The WREN instruction may also be used to
allow execution of the Write STATUS Register (WRSR)
FIGURE 5-10:
instruction; however, the Write Enable Latch bit in the
STATUS Register will be cleared upon the rising edge
CE# of the WRSR instruction. CE# must be driven low
before entering the WREN instruction, and CE# must be
driven high before executing the WREN instruction. See
Figure 5-10 for the WREN instruction sequence.
WRITE ENABLE (WREN) SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
06
SI
MSb
SO
5.11
High-Impedance
Write Disable (WRDI)
The Write Disable (WRDI) instruction, 04H, resets the
Write Enable Latch bit to ‘0’, thus preventing any new
Write operations. CE# must be driven low before enter-
FIGURE 5-11:
ing the WRDI instruction, and CE# must be driven high
before executing the WRDI instruction. See Figure 5-11
for the WRDI instruction sequence.
WRITE DISABLE (WRDI) SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
04
SI
MSb
SO
2015-2022 Microchip Technology Inc. and its subsidiaries
High-Impedance
DS20005397F-page 17
SST25PF040C
5.12
Write STATUS Register (WRSR)
The Write STATUS Register instruction writes new values to the BP0, BP1, BP2, TB, and BPL bits of the status register. CE# must be driven low before the
command sequence of the WRSR instruction is entered
and driven high before the WRSR instruction is executed. Poll the BUSY bit in the Software STATUS register, or wait TWRSR, for the completion of the internal,
self-timed Write STATUS Register cycle. See Figure 512 for WREN and WRSR instruction sequences and Figure 6-11 for the WRSR flow chart.
Executing the Write STATUS Register instruction will
be ignored when WP# is low and BPL bit is set to ‘1’.
When the WP# is low, the BPL bit can only be set from
FIGURE 5-12:
‘0’ to ‘1’ to lock-down the status register, but cannot be
reset from ‘1’ to ‘0’. When WP# is high, the lock-down
function of the BPL bit is disabled and the BPL, BP0,
BP1, BP2, and TB bits in the STATUS register can all
be changed. As long as BPL bit is set to ‘0’ or WP# pin
is driven high (VIH) prior to the low-to-high transition of
the CE# pin at the end of the WRSR instruction, the bits
in the status register can all be altered by the WRSR
instruction. In this case, a single WRSR instruction can
set the BPL bit to ‘1’ to lock down the status register as
well as altering the BP0, BP1, BP2, and TB bits at the
same time. See Table 4-1 for a summary description of
WP# and BPL functions.
WRITE-ENABLE (WREN) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
01
06
MSb
DS20005397F-page 18
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MODE 0
SI
SO
MODE 3
MSb
STATUS
Register In
7 6 5 4 3 2 1 0
MSb
High-Impedance
2015-2022 Microchip Technology Inc. and its subsidiaries
SST25PF040C
5.13
Power-Down
The Deep Power-Down (DPD) instruction puts the
device in the lowest power consumption mode – the
Deep Power-Down mode. This instruction is ignored if
the device is busy with an internal write operation.
While the device is in DPD mode, all instructions are
ignored except for the Release Deep Power-Down
instruction or Read ID.
of TDPD before the standby current ISB is reduced to the
deep power-down current IDPD. See Figure 5-13 for the
DPD instruction sequence.
Exit the power-down state using the Release from
Deep Power-Down or Read ID instruction. CE# must
be driven low before sending the Release from Deep
Power-Down command cycle (ABH), and then driving
CE# high. The device will return to Standby mode and
be ready for the next instruction after TSBR. See Figure
5-14. for the Release from Deep Power-Down
sequence.
To initiate deep power-down, input the Deep PowerDown instruction (B9H) while driving CE# low. CE#
must be driven high before executing the DPD instruction. After driving CE# high, the device requires a delay
FIGURE 5-13:
DEEP POWER-DOWN SEQUENCE
CE#
TDPD
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
B9
SI
MSb
SO
FIGURE 5-14:
High-Impedance
RELEASE FROM DEEP POWER-DOWN SEQUENCE
CE#
TSBR
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
AB
SI
MSb
SO
2015-2022 Microchip Technology Inc. and its subsidiaries
High-Impedance
DS20005397F-page 19
SST25PF040C
5.14
Read-ID
The Read-ID instruction identifies the device as
SST25PF040C. Use the Read-ID instruction to identify
SST25PF040C when using multiple manufacturers in
the same socket. See Table 5-2.
command, ABH, followed by 24 dummy address bits.
Following the Read-ID instruction, and 24 address
dummy bits, the device ID continues to output with continuous clock input until terminated by a low-to-high
transition on CE#.
The device ID information is read by executing an 8-bit
TABLE 5-2:
PRODUCT IDENTIFICATION
Device ID
SST25PF040C ID
FIGURE 5-15:
Address
Data
XXXXXXH
6EH
READ-ID SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31 32
39 40
47 48
55 56
63
MODE 0
XX
AB
SI
XX
MSb
XX
MSb
High-Impedance
SO
High-Impedance
Device ID Device ID Device ID Device ID
MSb
Note: The Device ID output stream is continuous until terminated by a low-to-high transition on CE#.
5.15
JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device ID
information of SST25PF040C. The device information
can be read by executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, 32-bit device ID
information is output from the device. The Device ID
information is assigned by the manufacturer and contains the Device ID 1 in the first byte, the type of mem-
FIGURE 5-16:
ory in the second byte, the memory capacity of the
device in the third byte, and a reserved code in the
fourth byte. The 4-byte code outputs repeatedly with
continuous clock input until a low-to-high transition on
CE#. See Figure 5-16 for the instruction sequence. The
JEDEC Read ID instruction is terminated by a low-tohigh transition on CE# at any time during data output.
JEDEC READ-ID SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
MODE 0
SI
SO
9F
High-Impedance
06
62
MSb
TABLE 5-3:
13
00
MSb
JEDEC READ-ID DATA-OUT
Device ID
Product
Device ID 1
(Byte 1)
Memory Type (Byte 2)
Memory Capacity (Byte 3)
Reserved Code
(Byte 4)
SST25PF040C
62H
06H
13H
00H
DS20005397F-page 20
2015-2022 Microchip Technology Inc. and its subsidiaries
SST25PF040C
6.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (†)
Temperature under bias .......................................................................................................................... -55°C to +125°C
Storage temperature ............................................................................................................................... -55°C to +150°C
DC voltage on any pin to ground potential ...........................................................................................-0.5V to VDD+0.5V
Transient voltage (