SST25VF016B-50-4I-S2AF

SST25VF016B 16 Mbit SPI Serial Flash Features Product Description • Single Voltage Read and Write Operations - 2.7-3.6V • Serial Interface Architecture - SPI Compatible: Mode 0 and Mode 3 • High Speed Clock Frequency - Up to 50 MHz • Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention • Low Power Consumption: - Active Read Current: 10 mA (typical) - Standby Current: 5 µA (typical) • Flexible Erase Capability - Uniform 4 KByte sectors - Uniform 32 KByte overlay blocks - Uniform 64 KByte overlay blocks • Fast Erase and Byte-Program: - Chip-Erase Time: 35 ms (typical) - Sector-/Block-Erase Time: 18 ms (typical) - Byte-Program Time: 7 µs (typical) • Auto Address Increment (AAI) Programming - Decrease total chip programming time over Byte-Program operations • End-of-Write Detection - Software polling the BUSY bit in Status Register - Busy Status readout on SO pin in AAI Mode • Hold Pin (HOLD#) - Suspends a serial sequence to the memory without deselecting the device • Write Protection (WP#) - Enables/Disables the Lock-Down function of the status register • Software Write Protection - Write protection through Block-Protection bits in status register • Temperature Range - Commercial: 0°C to +70°C - Industrial: -40°C to +85°C • Packages Available - 8-lead SOIC (200 mils) - 8-contact WSON (6mm x 5mm) • All devices are RoHS compliant The 25 series Serial Flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. The SST25VF016B devices are enhanced with improved operating frequency and even lower power consumption than the original SST25VFxxxA devices. SST25VF016B SPI serial flash memories are manufactured with proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.  2015 Microchip Technology Inc. SST25VF016B devices significantly improve performance and reliability, while lowering power consumption. The devices write (Program or Erase) with a single power supply of 2.7-3.6V for SST25VF016B. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST25VF016B device is offered in both 8-lead SOIC (200 mils) and 8-contact WSON (6mm x 5mm) packages. See Figure 2-1 for pin assignments. DS20005044C-page 1 SST25VF016B TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via Email at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS20005044C-page 2  2015 Microchip Technology Inc. SST25VF016B 1.0 BLOCK DIAGRAM FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM SuperFlash Memory X - Decoder Address Buffers and Latches Y - Decoder I/O Buffers and Data Latches Control Logic Serial Interface CE# SCK SI SO WP# HOLD# 1271 B1.0  2015 Microchip Technology Inc. DS20005044C-page 3 SST25VF016B 2.0 PIN DESCRIPTION FIGURE 2-1: PIN ASSIGNMENTS CE# 1 SO 2 8 VDD 7 HOLD# CE# 1 SO 2 8 VDD 7 HOLD# Top View Top View WP# 3 6 SCK WP# 3 6 SCK VSS 4 5 SI VSS 4 5 SI 1271 08-wson QA P2.0 1271 08-soic S2A P1.0 8-Lead SOIC TABLE 2-1: 8-Contact WSON PIN DESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. SI Serial Data Input To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. SO Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. Outputs Flash busy status during AAI Programming when reconfigured as RY/BY# pin. See “Hardware End-of-Write Detection” on page 11 for details. CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device. VDD Power Supply To provide power supply voltage: 2.7-3.6V for SST25VF016B VSS Ground DS20005044C-page 4  2015 Microchip Technology Inc. SST25VF016B 3.0 MEMORY ORGANIZATION used to select the device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25VF016B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32 KByte overlay blocks and 64 KByte overlay erasable blocks. 4.0 The SST25VF016B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 4-1, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal. DEVICE OPERATION The SST25VF016B is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consist of four control lines; Chip Enable (CE#) is FIGURE 4-1: SPI PROTOCOL CE# SCK MODE 3 MODE 3 MODE 0 MODE 0 SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB HIGH IMPEDANCE DON'T CARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SO MSB 4.1 Hold Operation The HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD# mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state. If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the FIGURE 4-2: 1271 SPIprot.0 HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode when the SCK next reaches the active low state. See Figure 4-2 for Hold Condition waveform. Once the device enters Hold mode, SO will be in highimpedance state while SI and SCK can be VIL or VIH. If CE# is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD# must be driven active high, and CE# must be driven active low. See Figure 5-3 for Hold timing. HOLD CONDITION WAVEFORM SCK HOLD# Active Hold Active Hold Active 1271 HoldCond.0 4.2 Write Protection SST25VF016B provides software Write protection. The Write Protect pin (WP#) enables or disables the lockdown function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL) in the status  2015 Microchip Technology Inc. register provide Write protection to the memory array and the status register. See Table 4-3 for the Block-Protection description. DS20005044C-page 5 SST25VF016B 4.2.1 WRITE PROTECT PIN (WP#) Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 4-1). When WP# is high, the lock-down function of the BPL bit is disabled. The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP# is driven low, the execution of the Write- TABLE 4-1: 4.3 CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION WP# BPL Execute WRSR Instruction L 1 Not Allowed L 0 Allowed H X Allowed Status Register The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the Memory Write protection. TABLE 4-2: During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4-2 describes the function of each bit in the software status register. SOFTWARE STATUS REGISTER Default at Power-up Read/Write 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 0 R WEL 1 = Device is memory Write enabled 0 = Device is not memory Write enabled 0 R 2 BP0 Indicate current level of block write protection (See Table 4-3) 1 R/W 3 BP1 Indicate current level of block write protection (See Table 4-3) 1 R/W 4 BP2 Indicate current level of block write protection (See Table 4-3) 1 R/W 5 BP3 Indicate current level of block write protection (See Table 4-3) 0 R/W 6 AAI Auto Address Increment Programming status 1 = AAI programming mode 0 = Byte-Program mode 0 R 7 BPL 1 = BP3, BP2, BP1, BP0 are read-only bits 0 = BP3, BP2, BP1, BP0 are read/writable 0 R/W Bit Name Function 0 BUSY 1 4.3.1 BUSY The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. 4.3.2 WRITE ENABLE LATCH (WEL) The Write-Enable-Latch (WEL) bit indicates the status of the internal memory Write Enable Latch. If the WriteEnable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions: DS20005044C-page 6 • • • • • • • • Power-up Write-Disable (WRDI) instruction completion Byte-Program instruction completion Auto Address Increment (AAI) programming is completed or reached its highest unprotected memory address Sector-Erase instruction completion Block-Erase instruction completion Chip-Erase instruction completion Write-Status-Register instructions 4.3.3 AUTO ADDRESS INCREMENT (AAI) The Auto Address Increment Programming-Status bit provides status on whether the device is in Auto Address Increment (AAI) programming mode or ByteProgram mode. The default at power up is Byte-Program mode.  2015 Microchip Technology Inc. SST25VF016B 4.3.4 BLOCK PROTECTION (BP3,BP2, BP1, BP0) 4.3.5 The Block-Protection (BP3, BP2, BP1, BP0) bits define the size of the memory area, as defined in Table 4-3, to be software protected against any memory Write (Program or Erase) operation. The Write-Status-Register (WRSR) instruction is used to program the BP3, BP2, BP1 and BP0 bits as long as WP# is high or the BlockProtect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are all 0. After powerup, BP3, BP2, BP1 and BP0 are set to 1. TABLE 4-3: BLOCK PROTECTION LOCK-DOWN (BPL) WP# pin driven low (VIL), enables the Block-ProtectionLock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP3, BP2, BP1, and BP0 bits. When the WP# pin is driven high (VIH), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. SOFTWARE STATUS REGISTER BLOCK PROTECTION FOR SST25VF016B1 Status Register Bit2 Protection Level None Protected Memory Address BP3 BP2 BP1 BP0 16 Mbit X 0 0 0 None Upper 1/32 X 0 0 1 1F0000H-1FFFFFH Upper 1/16 X 0 1 0 1E0000H-1FFFFFH Upper 1/8 X 0 1 1 1C0000H-1FFFFFH Upper 1/4 X 1 0 0 180000H-1FFFFFH Upper 1/2 X 1 0 1 100000H-1FFFFFH All Blocks X 1 1 0 000000H-1FFFFFH All Blocks X 1 1 1 000000H-1FFFFFH 1. X = Don’t Care (RESERVED) default is “0 2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected)  2015 Microchip Technology Inc. DS20005044C-page 7 SST25VF016B 4.4 Instructions Instructions are used to read, write (Erase and Program), and configure the SST25VF016B. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list of instructions is provided in Table 4-4. All instructions are synchronized off a high to low transition TABLE 4-4: of CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID, and Read-StatusRegister instructions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. DEVICE OPERATION INSTRUCTIONS Instruction Description Op Code Cycle1 Address Cycle(s)2 Dummy Cycle(s) Data Cycle(s) Maximum Frequency Read Read Memory at 25 MHz 0000 0011b (03H) 3 0 1 to  25 MHz High-Speed Read Read Memory at 50 MHz 0000 1011b (0BH) 3 1 1 to  50 MHz 4 KByte Sector- Erase 4 KByte of Erase3 memory array 0010 0000b (20H) 3 0 0 50 MHz 32 KByte Block- Erase 32 KByte block Erase4 of memory array 0101 0010b (52H) 3 0 0 50 MHz 64 KByte Block- Erase 64 KByte block Erase5 of memory array 1101 1000b (D8H) 3 0 0 50 MHz Chip-Erase Erase Full Memory Array 0110 0000b (60H) or 1100 0111b (C7H) 0 0 0 50 MHz Byte-Program To Program One Data Byte 0000 0010b (02H) 3 0 1 50 MHz AAI-Word-Program6 Auto Address Increment Programming 1010 1101b (ADH) 3 0 2 to  50 MHz RDSR7 Read-Status-Register 0000 0101b (05H) 0 0 1 to  50 MHz EWSR Enable-Write-Status-Register 0101b 0000b (50H) 0 0 0 50 MHz WRSR Write-Status-Register 0000 0001b (01H) 0 0 1 50 MHz WREN Write-Enable 0000 0110b (06H) 0 0 0 50 MHz WRDI Write-Disable 0000 0100b (04H) 0 0 0 50 MHz RDID8 Read-ID 1001 0000b (90H) or 1010 1011b (ABH) 3 0 1 to  50 MHz JEDEC-ID JEDEC ID read 1001 1111b (9FH) 0 0 3 to  50 MHz EBSY Enable SO to output RY/BY# status during AAI programming 0111 0000b (70H) 0 0 0 50 MHz DBSY Disable SO as RY/BY# status during AAI programming 1000 0000b (80H) 0 0 0 50 MHz 1. 2. 3. 4. 5. 6. One bus cycle is eight clock periods. Address bits above the most significant bit of each density can be VIL or VIH. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be programmed into the initial address [A23-A1] with A0=1. 7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. 8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#. DS20005044C-page 8  2015 Microchip Technology Inc. SST25VF016B 4.4.1 READ (25 MHZ) cally increment to the beginning (wrap-around) of the address space. Once the data from address location 1FFFFFH has been read, the next output will be from address location 000000H. The Read instruction, 03H, supports up to 25 MHz Read. The device outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automati- FIGURE 4-3: The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23-A0]. CE# must remain active low for the duration of the Read cycle. See Figure 4-3 for the Read sequence. READ SEQUENCE CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 23 24 15 16 31 32 39 40 47 48 55 56 63 64 70 MODE 0 ADD. 03 SI ADD. ADD. MSB MSB N DOUT HIGH IMPEDANCE SO N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT MSB 1271 ReadSeq.0 4.4.2 HIGH-SPEED-READ (50 MHZ) through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space. Once the data from address location 1FFFFFH has been read, the next output will be from address location 000000H. The High-Speed-Read instruction supporting up to 50 MHz Read is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration of the High-Speed-Read cycle. See Figure 4-4 for the HighSpeed-Read sequence. Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the specified address location. The data output stream is continuous FIGURE 4-4: HIGH-SPEED-READ SEQUENCE CE# MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80 SCK MODE 0 0B SI ADD. MSB MSB SO ADD. ADD. HIGH IMPEDANCE Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH)  2015 Microchip Technology Inc. X N DOUT MSB N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT 1271 HSRdSeq.0 DS20005044C-page 9 SST25VF016B 4.4.3 BYTE-PROGRAM The Byte-Program instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23A0]. Following the address, the data is input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBP for the completion of the internal self-timed ByteProgram operation. See Figure 4-5 for the Byte-Program sequence. The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Byte-Program instruction. FIGURE 4-5: BYTE-PROGRAM SEQUENCE CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 ADD. 02 SI MSB SO 15 16 23 24 31 32 39 MODE 0 ADD. MSB ADD. DIN MSB LSB HIGH IMPEDANCE 1271 ByteProg.0 4.4.4 AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when multiple bytes or entire memory array is to be programmed. An AAI Word program instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when initiating an AAI Word Program operation. While within AAI Word Programming sequence, only the following instructions are valid: for software end-of-write detection—AAI Word (ADH), WRDI (04H), and RDSR (05H); for hardware end-of-write detection—AAI Word (ADH) and WRDI (04H). There are three options to determine the completion of each AAI Word program cycle: hardware detection by reading the Serial Output, software detection by polling the BUSY bit in the software status register, or wait TBP. Refer to“End-of-Write Detection” for details. Prior to any write operation, the Write-Enable (WREN) instruction must be executed. Initiate the AAI Word Program instruction by executing an 8-bit command, ADH, followed by address bits [A23-A0]. Following the addresses, two bytes of data are input sequentially, each one from MSB (Bit 7) to LSB (Bit 0). The first byte of data (D0) is programmed into the initial address [A23A1] with A0=0, the second byte of Data (D1) is programmed into the initial address [A23-A1] with A0=1. CE# must be driven high before executing the AAI Word Program instruction. Check the BUSY status before entering the next valid command. Once the DS20005044C-page 10 device indicates it is no longer busy, data for the next two sequential addresses may be programmed, followed by the next two, and so on. When programming the last desired word, or the highest unprotected memory address, check the busy status using either the hardware or software (RDSR instruction) method to check for program completion. Once programming is complete, use the applicable method to terminate AAI. If the device is in Software End-of-Write Detection mode, execute the Write-Disable (WRDI) instruction, 04H. If the device is in AAI Hardware End-of-Write Detection mode, execute the Write-Disable (WRDI) instruction, 04H, followed by the 8-bit DBSY command, 80H. There is no wrap mode during AAI programming once the highest unprotected memory address is reached. See Figures 4-8 and 4-9 for the AAI Word programming sequence. 4.4.5 END-OF-WRITE DETECTION There are three methods to determine completion of a program cycle during AAI Word programming: hardware detection by reading the Serial Output, software detection by polling the BUSY bit in the Software Status Register, or wait TBP. The Hardware End-of-Write detection method is described in the section below.  2015 Microchip Technology Inc. SST25VF016B 4.4.6 HARDWARE END-OF-WRITE DETECTION on the SO pin. A ‘0’ indicates the device is busy and a ‘1’ indicates the device is ready for the next instruction. De-asserting CE# will return the SO pin to tri-state. While in AAI and Hardware End-of-Write detection mode, the only valid instructions are AAI Word (ADH) and WRDI (04H). The Hardware End-of-Write detection method eliminates the overhead of polling the Busy bit in the Software Status Register during an AAI Word program operation. The 8-bit command, 70H, configures the Serial Output (SO) pin to indicate Flash Busy status during AAI Word programming. (see Figure 4-6) The 8bit command, 70H, must be executed prior to initiating an AAI Word-Program instruction. Once an internal programming operation begins, asserting CE# will immediately drive the status of the internal flash status FIGURE 4-6: To exit AAI Hardware End-of-Write detection, first execute WRDI instruction, 04H, to reset the Write-EnableLatch bit (WEL=0) and AAI bit. Then execute the 8-bit DBSY command, 80H, to disable RY/BY# status during the AAI command. See Figures 4-7 and 4-8. ENABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING CE# MODE 3 SCK 0 1 2 3 4 5 6 7 MODE 0 70 SI MSB HIGH IMPEDANCE SO 1271 EnableSO.0 FIGURE 4-7: DISABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING CE# MODE 3 SCK 0 1 2 3 4 5 6 7 MODE 0 80 SI MSB SO HIGH IMPEDANCE 1271 DisableSO.0  2015 Microchip Technology Inc. DS20005044C-page 11 SST25VF016B FIGURE 4-8: AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH HARDWARE END-OF-WRITE DETECTION CE# MODE 3 0 0 7 0 7 7 8 15 16 23 24 31 32 39 40 47 0 7 8 15 16 23 SCK MODE 0 SI AD WREN EBSY A A A D0 D1 AD D2 D3 Load AAI command, Address, 2 bytes data SO Check for Flash Busy Status to load next valid1 command CE# cont. 0 7 8 15 16 23 0 7 0 7 0 7 8 15 SCK cont. Dn-1 AD SI cont. WRDI Dn Last 2 Data Bytes RDSR DBSY WRDI followed by DBSY to exit AAI Mode DOUT SO cont. 1 Check for Flash Busy Status to load next valid command Note: 1. Valid commands during AAI programming: AAI command or WRDI command 2. User must configure the SO pin to output Flash Busy status during AAI programming 1271 AAI.HW.3 FIGURE 4-9: AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH SOFTWARE END-OF-WRITE DETECTION Wait TBP or poll Software Status register to load next valid1 command CE# MODE 3 0 7 8 15 16 23 24 31 32 39 40 47 0 7 8 15 16 23 0 7 8 15 16 23 0 7 0 7 8 15 SCK MODE 0 SI AD A A A D0 D1 Load AAI command, Address, 2 bytes data AD D2 D3 AD Dn-1 Dn Last 2 Data Bytes SO Note: WRDI RDSR WRDI to exit AAI Mode DOUT 1. Valid commands during AAI programming: AAI command, RDSR command, or WRDI command DS20005044C-page 12 1271 AAI.SW.1  2015 Microchip Technology Inc. SST25VF016B 4.4.7 4-KBYTE SECTOR-ERASE bits [A23-A0]. Address bits [AMS-A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 4-10 for the Sector-Erase sequence. The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address FIGURE 4-10: SECTOR-ERASE SEQUENCE CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 23 24 15 16 31 MODE 0 ADD. ADD. 20 SI MSB ADD. MSB HIGH IMPEDANCE SO 1271 SecErase.0 4.4.8 32-KBYTE AND 64-KBYTE BLOCKERASE nificant Address) are used to determine block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. The 64-Kbyte Block-Erase instruction is initiated by executing an 8-bit command D8H, followed by address bits [A23-A0]. Address bits [AMS-A15] are used to determine block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed 32KByte Block-Erase or 64-KByte Block-Erase cycles. See Figures 4-11 and 4-12 for the 32-KByte BlockErase and 64-KByte Block-Erase sequences. The 32-KByte Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. The 64-KByte Block-Erase instruction clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The 32-Kbyte Block-Erase instruction is initiated by executing an 8-bit command, 52H, followed by address bits [A23-A0]. Address bits [AMS-A15] (AMS = Most Sig- FIGURE 4-11: 32-KBYTE BLOCK-ERASE SEQUENCE CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 52 SI MSB SO 15 16 23 24 31 MODE 0 ADDR ADDR ADDR MSB HIGH IMPEDANCE 1271 32KBklEr.0  2015 Microchip Technology Inc. DS20005044C-page 13 SST25VF016B FIGURE 4-12: 64-KBYTE BLOCK-ERASE SEQUENCE CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 MODE 0 ADDR D8 SI MSB ADDR ADDR MSB HIGH IMPEDANCE SO 1271 63KBlkEr.0 4.4.9 CHIP-ERASE The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence. The Chip-Erase FIGURE 4-13: instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TCE for the completion of the internal self-timed Chip-Erase cycle. See Figure 4-13 for the Chip-Erase sequence. CHIP-ERASE SEQUENCE CE# MODE 3 SCK 0 1 2 3 4 5 6 7 MODE 0 60 or C7 SI MSB SO HIGH IMPEDANCE 1271 ChEr.0 DS20005044C-page 14  2015 Microchip Technology Inc. SST25VF016B 4.4.10 READ-STATUS-REGISTER (RDSR) properly received by the device. CE# must be driven low before the RDSR instruction is entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 4-14 for the RDSR instruction sequence. The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register may be read at any time even during a Write (Program/ Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the new commands are FIGURE 4-14: READ-STATUS-REGISTER (RDSR) SEQUENCE CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 MODE 0 SI 05 MSB HIGH IMPEDANCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SO MSB Status Register Out 1271 RDSRseq.0 4.4.11 WRITE-ENABLE (WREN) execution of the Write-Status-Register (WRSR) instruction; however, the Write-Enable-Latch bit in the Status Register will be cleared upon the rising edge CE# of the WRSR instruction. CE# must be driven high before the WREN instruction is executed. The Write-Enable (WREN) instruction sets the WriteEnable-Latch bit in the Status Register to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. The WREN instruction may also be used to allow FIGURE 4-15: WRITE ENABLE (WREN) SEQUENCE CE# MODE 3 SCK 0 1 2 3 4 5 6 7 MODE 0 06 SI MSB SO HIGH IMPEDANCE 1271 WREN.0  2015 Microchip Technology Inc. DS20005044C-page 15 SST25VF016B 4.4.12 WRITE-DISABLE (WRDI) terminate any programming operation in progress. Any program operation in progress may continue up to TBP after executing the WRDI instruction. CE# must be driven high before the WRDI instruction is executed. The Write-Disable (WRDI) instruction resets the WriteEnable-Latch bit and AAI bit to 0 disabling any new Write operations from occurring. The WRDI instruction will not FIGURE 4-16: WRITE DISABLE (WRDI) SEQUENCE CE# MODE 3 SCK 0 1 2 3 4 5 6 7 MODE 0 04 SI MSB SO HIGH IMPEDANCE 1271 WRDI.0 4.4.13 ENABLE-WRITE-STATUSREGISTER (EWSR) The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR) instruction and opens the status register for alteration. The WriteStatus-Register instruction must be executed immediately after the execution of the Enable-Write-StatusRegister instruction. This two-step instruction sequence of the EWSR instruction followed by the WRSR instruction works like SDP (software data protection) command structure which prevents any accidental alteration of the status register values. CE# must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. 4.4.14 WRITE-STATUS-REGISTER (WRSR) The Write-Status-Register instruction writes new values to the BP3, BP2, BP1, BP0, and BPL bits of the status register. CE# must be driven low before the FIGURE 4-17: command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 4-17 for EWSR or WREN and WRSR instruction sequences. Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to “1”. When the WP# is low, the BPL bit can only be set from “0” to “1” to lock-down the status register, but cannot be reset from “1” to “0”. When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, and BP1 and BP2 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP# pin is driven high (VIH) prior to the low-to-high transition of the CE# pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the BP0, BP1, and BP2 bits at the same time. See Table 4-1 for a summary description of WP# and BPL functions. ENABLE-WRITE-STATUS-REGISTER (EWSR) OR WRITE-ENABLE (WREN) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE CE# MODE 3 SCK 0 1 2 3 4 5 6 7 MODE 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MODE 0 50 or 06 SI MSB SO MODE 3 01 MSB STATUS REGISTER IN 7 6 5 4 3 2 1 0 MSB HIGH IMPEDANCE 1271 EWSR.0 DS20005044C-page 16  2015 Microchip Technology Inc. SST25VF016B 4.4.15 JEDEC READ-ID type as SPI Serial Flash. Byte 3, 41H, identifies the device as SST25VF016B. The instruction sequence is shown in Figure 4-18. The JEDEC Read ID instruction is terminated by a low to high transition on CE# at any time during data output. If no other command is issued after executing the JEDEC Read-ID instruction, issue a 00H (NOP) command before going into Standby Mode (CE#=VIH). The JEDEC Read-ID instruction identifies the device as SST25VF016B and the manufacturer as Microchip. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte 1, BFH, identifies the manufacturer as Microchip. Byte 2, 25H, identifies the memory FIGURE 4-18: JEDEC READ-ID SEQUENCE CE# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 MODE 0 SCK 9F SI SO HIGH IMPEDANCE BF 25 MSB 41 MSB 1271 JEDECID.1 TABLE 4-5: JEDEC READ-ID DATA Device ID Manufacturer’s ID Memory Type Memory Capacity Byte1 Byte 2 Byte 3 BFH 25H 41H  2015 Microchip Technology Inc. DS20005044C-page 17 SST25VF016B 4.4.16 READ-ID (RDID) Read-ID instruction, the manufacturer’s ID is located in address 00000H and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer’s and device ID output data toggles between address 00000H and 00001H until terminated by a low to high transition on CE#. The Read-ID instruction (RDID) identifies the devices as SST25VF016B and manufacturer as Microchip. This command is backward compatible to all SST25xFxxxA devices and should be used as default device identification when multiple versions of SPI Serial Flash devices are used in a design. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A23-A0]. Following the FIGURE 4-19: Refer to Tables 4-5 and 4-6 for device identification data. READ-ID SEQUENCE CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 23 24 15 16 31 32 39 40 47 48 55 56 63 MODE 0 90 or AB SI 00 00 MSB ADD1 MSB HIGH IMPEDANCE SO BF Device ID BF Device ID HIGH IMPEDANCE MSB Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#. Device ID = 41H for SST25VF016B 1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two. 1271 RdID.0 TABLE 4-6: PRODUCT IDENTIFICATION Manufacturer’s ID Address Data 00000H BFH 00001H 41H Device ID SST25VF016B DS20005044C-page 18  2015 Microchip Technology Inc. SST25VF016B 5.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V Transient Voltage (