SST25VF040B
4-Mbit SPI Serial Flash
Features
Packages
• Single Voltage Read and Write Operations:
- 2.7V-3.6V
• Serial Interface Architecture:
- SPI Compatible: Mode 0 and Mode 3
• High-Speed Clock Frequency:
- Up to 50 MHz
• Superior Reliability:
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
• Low-Power Consumption:
- Active Read Current: 10 mA (typical)
- Standby Current: 5 µA (typical)
• Flexible Erase Capability:
- Uniform 4-Kbyte sectors
- Uniform 32-Kbyte overlay blocks
- Uniform 64-Kbyte overlay blocks
• Fast Erase and Byte Program:
- Chip Erase Time: 35 ms (typical)
- Sector/Block Erase Time: 18 ms (typical)
- Byte Program Time: 7 µs (typical)
• Auto Address Increment (AAI) Programming:
- Decrease total chip programming time over
Byte Program operations
• End of Write Detection:
- Software polling the BUSY bit in STATUS
Register
- Busy Status readout on SO pin in AAI Mode
• Hold Pin (HOLD#):
- Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#):
- Enables/Disables the Lock-Down function of
the STATUS register
• Software Write Protection:
- Write protection through Block Protection bits
in STATUS register
• Temperature Range:
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
• All devices are RoHS compliant
• 8-lead SOIC (208 mils), 8-lead SOIC (150 mils)
and 8-contact WSON (6 mm x 5 mm)
2005-2020 Microchip Technology Inc.
Description
The 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ultimately lowers total system costs. The SST25VF040B
devices are enhanced with improved operating frequency and even lower power consumption.
SST25VF040B SPI serial Flash memories are manufactured with proprietary, high-performance CMOS
SuperFlash® technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
SST25VF040B devices significantly improve performance and reliability, while lowering power consumption. The devices write (Program or Erase) with a single
power supply of 2.7V-3.6V for SST25VF040B. The total
energy consumed is a function of the applied voltage,
current, and time of application. Since for any given
voltage range, the SuperFlash technology uses less
current to program and has a shorter erase time, the
total energy consumed during any erase or program
operation is less than alternative Flash memory technologies.
See Figure 2-1 for pin assignments.
DS20005051E-page 1
SST25VF040B
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last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
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DS20005051E-page 2
SST25VF040B
1.0
BLOCK DIAGRAM
FIGURE 1-1:
FUNCTIONAL BLOCK DIAGRAM
SuperFlash
Memory
X - Decoder
Address
Buffers
and
Latches
Y --Decoder
Decoder
I/O Buffers
and
Data Latches
Control Logic
Serial Interface
CE#
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SCK
SI
SO
WP#
HOLD#
DS20005051E-page 3
SST25VF040B
2.0
PIN DESCRIPTION
FIGURE 2-1:
PIN ASSIGNMENTS
Pin Assignment for 8-Lead SOIC
CE#
SO
TABLE 2-1:
1
2
WP#
3
VSS
4
8
Top View
7
VDD
HOLD#
6
SCK
5
SI
Pin Assignment for 8-Contact WSON
CE#
1
8
VDD
7
HOLD#
SO
2
WP#
3
6
SCK
VSS
4
5
SI
Top View
PIN DESCRIPTION
Symbol Pin Name
Functions
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
SO
Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY#
pin. See Section 5.5 “End of Write Detection” for details.
WP#
Write-Protect
VSS
Ground
VDD
Power Supply
To provide power supply voltage:2.7V-3.6V for SST25VF040B.
HOLD#
Hold
To temporarily stop serial communication with SPI Flash memory without resetting the
device.
SCK
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
The Write-Protect (WP#) pin is used to enable/disable BPL bit in the STATUS register.
2005-2020 Microchip Technology Inc.
DS20005051E-page 4
SST25VF040B
3.0
MEMORY ORGANIZATION
The SST25VF040B supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 4-1, is the
state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The
SCK signal is low for Mode 0 and SCK signal is high for
Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the
Serial Data Output (SO) is driven after the falling edge
of the SCK clock signal.
The SST25VF040B SuperFlash memory array is organized in uniform 4-Kbyte erasable sectors with
32-Kbyte overlay blocks and 64-Kbyte overlay erasable blocks.
4.0
DEVICE OPERATION
The SST25VF040B is accessed through the SPI
(Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable
(CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial
Data Output (SO), and Serial Clock (SCK).
FIGURE 4-1:
SPI PROTOCOL
CE#
SCK
MODE 3
MODE 3
MODE 0
MODE 0
SI
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSb
High-Impedance
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSb
4.1
Hold Operation
The HOLD# pin is used to pause a serial sequence
underway with the SPI Flash memory without resetting
the clocking sequence. To activate the HOLD# mode,
CE# must be in active-low state. The HOLD# mode
begins when the SCK active-low state coincides with
the falling edge of the HOLD# signal. The HOLD mode
ends when the HOLD# signal’s rising edge coincides
with the SCK active-low state.
Once the device enters Hold mode, SO will be in
high-impedance state while SI and SCK can be VIL or
VIH.
If CE# is driven active-high during a Hold condition, it
resets the internal logic of the device. As long as
HOLD# signal is low, the memory remains in the Hold
condition. To resume communication with the device,
HOLD# must be driven active-high, and CE# must be
driven active-low. See Figure 8-3 for Hold timing.
If the falling edge of the HOLD# signal does not coincide with the SCK active-low state, then the device
enters Hold mode when the SCK next reaches the
active-low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK activelow state, then the device exits in Hold mode when the
SCK next reaches the active-low state. See Figure 4-2
for Hold Condition waveform.
FIGURE 4-2:
HOLD CONDITION WAVEFORM
SCK
HOLD#
Active
2005-2020 Microchip Technology Inc.
Hold
Active
Hold
Active
DS20005051E-page 5
SST25VF040B
4.2
Write Protection
4.2.1
The Write-Protect (WP#) pin enables the lock-down
function of the BPL bit (bit 7) in the STATUS register.
When WP# is driven low, the execution of the Write
STATUS Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 4-1). When WP# is
high, the lock-down function of the BPL bit is disabled.
SST25VF040B provides software write protection. The
Write-Protect pin (WP#) enables or disables the lockdown function of the STATUS register. The Block Protection bits (BP3, BP2, BP1, BP0, and BPL) in the STATUS register provide Write protection to the memory
array and the STATUS register. See Table 4-3 for the
Block Protection description.
TABLE 4-1:
4.3
WRITE PROTECTION PIN (WP#)
CONDITIONS TO EXECUTE WRITE STATUS REGISTER (WRSR) INSTRUCTIONS
WP#
BPL
L
1
Not Allowed
L
0
Allowed
H
X
Allowed
STATUS Register
The software STATUS register provides status on
whether the Flash memory array is available for any
read or write operation, whether the device is write
enabled and the state of the Memory Write-protected.
TABLE 4-2:
Execute WRSR Instructions
During an internal erase or program operation, the
STATUS register may be read only to determine the
completion of an operation in progress. Table 4-2
describes the function of each bit in the software STATUS register.
SOFTWARE STATUS REGISTER
Default at
Power-up
Read/Write
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
0
R
Indicate current level of block write protection (See Table 4-3)
1
R/W
Bit
Name
Function
0
BUSY
1
WEL
2
BP0
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
3
BP1
Indicate current level of block write protection (See Table 4-3)
4
BP2
Indicate current level of block write protection (See Table 4-3)
5
BP3
Indicate current level of block write protection (See Table 4-3)
6
AAI
7
BPL
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte Program mode
4.3.1
1 = BP3, BP2, BP1, BP0 are read-only bits
0 = BP3, BP2, BP1, BP0 are read/writable
BUSY
The BUSY bit determines whether there is an internal
Erase or Program operation in progress. A ‘1’ for the
BUSY bit indicates the device is busy with an operation
in progress. A ‘0’ indicates the device is ready for the
next valid operation.
4.3.2
WRITE ENABLE LATCH (WEL)
The Write Enable Latch bit indicates the status of the
internal memory Write Enable Latch. If the Write
Enable Latch bit is set to ‘1’, it indicates the device is
Write enabled. If the bit is set to ‘0’ (reset), it indicates
the device is not write enabled and does not accept any
2005-2020 Microchip Technology Inc.
1
1
R/W
R/W
0
R/W
0
R
0
R/W
memory write (program/erase) commands. The Write
Enable Latch bit is automatically reset under the following conditions:
•
•
•
•
•
•
•
•
Power-up
Write Disable (WRDI) instruction completion
Byte Program instruction completion
Auto Address Increment (AAI) programming is
completed or reached its highest unprotected
memory address
Sector Erase instruction completion
Block Erase instruction completion
Chip Erase instruction completion
Write STATUS register instructions
DS20005051E-page 6
SST25VF040B
4.3.3
AUTO ADDRESS INCREMENT (AAI)
The Auto Address Increment Programming Status bit
provides status on whether the device is in AAI programming mode or Byte-Program mode. The default at
power up is Byte-Program mode.
4.3.4
BLOCK PROTECTION (BP3,BP2,
BP1, BP0)
4.3.5
BLOCK PROTECTION LOCK-DOWN
(BPL)
WP# pin driven low (VIL), enables the Block Protection
Lock Down (BPL) bit. When BPL is set to ‘1’, it prevents
any further alteration of the BPL, BP3, BP2, BP1, and
BP0 bits. When the WP# pin is driven high (VIH), the
BPL bit has no effect and its value is “don’t care”. After
power-up, the BPL bit is reset to ‘0’.
The Block Protection (BP3, BP2, BP1, BP0) bits define
the size of the memory area, as defined in Table 4-3, to
be software protected against any memory write (program or erase) operation. The Write STATUS Register
(WRSR) instruction is used to program the BP3, BP2,
BP1 and BP0 bits as long as WP# is high or the Block
Protect Lock (BPL) bit is ‘0’. Chip Erase can only be
executed if Block Protection bits are all ‘0’. After powerup, BP3, BP2, BP1 and BP0 are set to ‘1’.
TABLE 4-3:
SOFTWARE STATUS REGISTER BLOCK PROTECTION FOR SST25VF040B(1)
Protection Level
STATUS Register Bit
BP3
None
X
Upper 1/16
X
Upper 1/8
X
Upper 1/4
X
Upper 1/2
X
All Blocks
X
All Blocks
X
All Blocks
X
Note 1:
2:
BP2
0
0
0
0
1
1
1
1
BP1
0
0
1
1
0
0
1
1
Protected Memory Address
BP0
0
1
0
1
0
1
0
1
4 Mbits
None
70000H-7FFFFH
60000H-7FFFFH
40000H-7FFFFH
00000H-7FFFFH
00000H-7FFFFH
00000H-7FFFFH
00000H-7FFFFH
X = “Don’t care” (RESERVED) default is ‘0’.
Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected)
2005-2020 Microchip Technology Inc.
DS20005051E-page 7
SST25VF040B
5.0
INSTRUCTIONS
Instructions are used to read, write (Erase and Program), and configure the SST25VF040B. The instruction bus cycles are 8 bits each for commands (Op
Code), data, and addresses. Prior to executing any
Byte Program, Auto Address Increment (AAI) programming, Sector Erase, Block Erase, Write STATUS Register, or Chip Erase instructions, the Write Enable
(WREN) instruction must be executed first. The complete list of instructions is provided in Table 5-1. All
instructions are synchronized off a high-to-low transition of CE#. Inputs will be accepted on the rising edge
of SCK starting with the most significant bit. CE# must
be driven low before an instruction is entered and must
be driven high after the last bit of the instruction has
been shifted in (except for Read, Read ID, and Read
STATUS Register instructions). Any low-to-high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress
and return the device to standby mode. Instruction
commands (Op Code), addresses, and data are all
input from the most significant bit (MSb) first.
TABLE 5-1:
DEVICE OPERATION INSTRUCTION
Instruction
Description
Op Code Cycle(1)
Address
Cycle(s)(2)
Dummy
Cycle(s)
Data
Cycle(s)
Read
Read Memory
0000 0011b (03H)
3
0
1 to ∞
High-Speed Read
Read Memory at higher speed
0000 1011b (0BH)
3
1
1 to ∞
Erase 4-Kbyte of memory array 0010 0000b (20H)
3
0
0
Erase 32-Kbyte block of
memory array
0101 0010b (52H)
3
0
0
Erase 64-Kbyte block of
memory array
1101 1000b (D8H)
3
0
0
Chip-Erase
Erase Full Memory Array
0110 0000b (60H) or
1100 0111b (C7H)
0
0
0
Byte Program
To Program One Data Byte
0000 0010b (02H)
3
0
1
Auto Address Increment
Programming
1010 1101b (ADH)
3
0
2 to ∞
Read STATUS Register
0000 0101b (05H)
0
0
1 to ∞
0
0
0
4-Kbyte Sector Erase
(3)
32-Kbyte Block Erase(4)
64-Kbyte Block Erase(5)
AAI Word Program(6)
RDSR(7)
EWSR
Enable Write STATUS Register 0101b 0000b (50H)
Write STATUS Register
0000 0001b (01H)
0
0
1
Write Enable
0000 0110b (06H)
0
0
0
WRDI
Write Disable
0000 0100b (04H)
0
0
0
Read ID
1001 0000b (90H) or
1010 1011b (ABH)
3
0
1 to ∞
JEDEC-ID
JEDEC ID read
1001 1111b (9FH)
0
0
3 to ∞
EBSY
Enable SO to output RY/BY#
0111 0000b (70H)
status during AAI programming
0
0
0
DBSY
Disable SO as RY/BY# status
during AAI programming
0
0
0
WRSR
WREN
RDID(8)
2005-2020 Microchip Technology Inc.
1000 0000b (80H)
DS20005051E-page 8
SST25VF040B
TABLE 5-1:
DEVICE OPERATION INSTRUCTION
Instruction
Note 1:
2:
3:
4:
5:
6:
7:
8:
5.1
Address
Cycle(s)(2)
Op Code Cycle(1)
Description
Dummy
Cycle(s)
Data
Cycle(s)
One bus cycle is eight clock periods.
Address bits above the most significant bit of each density can be VIL or VIH.
4-Kbyte Sector Erase addresses: use AMS-A12, remaining addresses are “don’t care” but must be set
either at VIL or VIH.
32-Kbyte Block Erase addresses: use AMS-A15, remaining addresses are “don’t care” but must be set
either at VIL or VIH.
64-Kbyte Block Erase addresses: use AMS-A16, remaining addresses are “don’t care” but must be set
either at VIL or VIH.
To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed
by 2 bytes of data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with
A0 = 0, Data Byte 1 will be programmed into the initial address [A23-A1] with A0 = 1.
The Read STATUS Register is continuous with ongoing clock cycles until terminated by a low-to-high transition on CE#.
Manufacturer’s ID is read with A0 = 0, and Device ID is read with A0 = 1. All other address bits are 00H.
The Manufacturer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
Read (25 MHz)
The Read instruction is initiated by executing an 8-bit
command, 03H, followed by address bits [A23-A0]. CE#
must remain active-low for the duration of the Read
cycle. See Figure 5-1 for the Read sequence.
The Read instruction, 03H, supports up to 25 MHz
Read. The device outputs the data starting from the
specified address location. The data output stream is
continuous through all addresses until terminated by a
low-to-high transition on CE#. The internal address
pointer will automatically increment until the highest
memory address is reached. Once the highest memory
address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the
address space. Once the data from address location
1FFFFFH has been read, the next output will be from
address location 00000H.
FIGURE 5-1:
READ SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
03
SI
ADD.
ADD.
MSE
MSE
SO
15 16
23 24
31 32
39 40
47
48
55 56
63 64
70
MODE 0
HLJK,PSHGDQFH
ADD.
N
DOUT
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSE
5.2
High-Speed Read (50 MHz)
The High-Speed Read instruction, supporting up to
50 MHz Read, is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a
dummy byte. CE# must remain active-low for the duration of the High-Speed Read cycle. See Figure 5-2 for
the High-Speed Read sequence.
2005-2020 Microchip Technology Inc.
Following a dummy cycle, the High-Speed Read
instruction outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low-to-high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically incre-
DS20005051E-page 9
SST25VF040B
ment to the beginning (wrap-around) of the address
space. Once the data from address location 7FFFFH
has been read, the next output will be from address
location 00000H.
FIGURE 5-2:
HIGH-SPEED READ SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
MODE 0
ADD.
MSE
0B
SI
MSb
ADD.
ADD.
X
N
DOUT
High-Impedance
SO
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSb
Note:
5.3
X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH)
Byte Program
tion. The Byte Program instruction is initiated by executing an 8-bit command, 02H, followed by address bits
[A23-A0]. Following the address, the data is input in
order from MSb (bit 7) to LSb (bit 0). CE# must be
driven high before the instruction is executed. The user
may poll the BUSY bit in the software STATUS register
or wait TBP for the completion of the internal self-timed
Byte Program operation. See Figure 5-3 for the Byte
Program sequence.
The Byte Program instruction programs the bits in the
selected byte to the desired data. The selected byte
must be in the erased state (FFH) when initiating a Program operation. A Byte Program instruction applied to
a protected memory area will be ignored.
Prior to any write operation, the Write Enable (WREN)
instruction must be executed. CE# must remain
active-low for the duration of the Byte Program instruc-
FIGURE 5-3:
BYTE PROGRAM SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
ADD.
02
SI
SO
23 24
31 32
39
ADD.
DIN
MSE LSE
HLJKIPSHGDQFH
Auto Address Increment (AAI)
Word Program
The AAI program instruction allows multiple bytes of
data to be programmed without re-issuing the next
sequential address location. This feature decreases
total programming time when multiple bytes or entire
memory array is to be programmed. An AAI Word program instruction pointing to a protected memory area
will be ignored. The selected address range must be in
the erased state (FFH) when initiating an AAI Word
Program operation. While within AAI Word programming sequence, only the following instructions are
valid: for software end of write detection—AAI Word
2005-2020 Microchip Technology Inc.
ADD.
MSE
MSE
5.4
15 16
MODE 0
(ADH), WRDI (04H), and RDSR (05H); for hardware end
of write detection—AAI Word (ADH) and WRDI (04H).
There are three options to determine the completion of
each AAI Word program cycle: hardware detection by
reading the Serial Output, software detection by polling
the BUSY bit in the software STATUS register, or wait
TBP. Refer to Section 5.5 “End of Write Detection”
for details.
Prior to any write operation, the Write Enable (WREN)
instruction must be executed. Initiate the AAI Word
Program instruction by executing an 8-bit command,
ADH, followed by address bits [A23-A0]. Following the
addresses, two bytes of data are input sequentially,
DS20005051E-page 10
SST25VF040B
each one from MSb (Bit 7) to LSb (Bit 0). The first byte
of data (D0) is programmed into the initial address [A23A1] with A0 = 0, the second byte of Data (D1) is programmed into the initial address [A23-A1] with A0 = 1.
CE# must be driven high before executing the AAI
Word Program instruction. Check the Busy status
before entering the next valid command. Once the
device indicates it is no longer busy, data for the next
two sequential addresses may be programmed, followed by the next two, and so on.
When programming the last desired word, or the highest unprotected memory address, check the busy status using either the hardware or software (RDSR
instruction) method to check for program completion.
Once programming is complete, use the applicable
method to terminate AAI. If the device is in Software
End of Write Detection mode, execute the Write Disable (WRDI) instruction, 04H. If the device is in AAI
Hardware End of Write Detection mode, execute the
Write Disable (WRDI) instruction, 04H, followed by the
8-bit DBSY command, 80H. There is no wrap mode
during AAI programming once the highest unprotected
memory address is reached. See Figure 5-6 and
Figure 5-7 for the AAI Word programming sequence.
FIGURE 5-4:
CE#
MODE 3
SCK
End of Write Detection
There are three methods to determine completion of a
program cycle during AAI Word programming: hardware detection by reading the Serial Output, software
detection by polling the BUSY bit in the software STATUS register, or wait TBP. The Hardware End of Write
detection method is described in the section below.
5.6
0 1 2 3 4 5 6 7
MODE 0
70
SI
MSE
SO
HLJKIPSHGDQFH
FIGURE 5-5:
DISABLE SO AS
HARDWARE RY/BY#
DURING AAI
PROGRAMMING
CE#
MODE 3
5.5
ENABLE SO AS
HARDWARE RY/BY#
DURING AAI
PROGRAMMING
SCK
0 1 2 3 4 5 6 7
MODE 0
80
SI
MSE
SO
HLJKIPSHGDQFH
Hardware End of Write Detection
The Hardware End of Write detection method eliminates the overhead of polling the BUSY bit in the software STATUS register during an AAI Word program
operation. The 8-bit command, 70H, configures the
Serial Output (SO) pin to indicate Flash Busy status
during AAI Word programming. (see Figure 5-4) The
8-bit command, 70H, must be executed prior to initiating an AAI Word Program instruction. Once an internal
programming operation begins, asserting CE# will
immediately drive the status of the internal Flash status
on the SO pin. A ‘0’ indicates the device is busy and a
‘1’ indicates the device is ready for the next instruction.
De-asserting CE# will return the SO pin to tri-state.
While in AAI and Hardware End of Write detection
mode, the only valid instructions are AAI Word (ADH)
and WRDI (04H).
To exit AAI Hardware End of Write detection, first execute WRDI instruction, 04H, to reset the Write Enable
Latch bit (WEL = 0) and AAI bit. Then execute the 8-bit
DBSY command, 80H, to disable RY/BY# status during
the AAI command. See Figure 5-5 and Figure 5-6.
2005-2020 Microchip Technology Inc.
DS20005051E-page 11
SST25VF040B
FIGURE 5-6:
AUTO ADDRESS INCREMENT (AAI) WORD PROGRAM SEQUENCE WITH
HARDWARE END OF WRITE DETECTION
CE#
MODE 3
0
0
7
0
7
7 8
15 16 23 24
31 32 39 40 47
0
7 8
15 16 23
SCK MODE 0
SI
AD
WREN
EBSY
A
A
A
D0
D1
AD
D2
D3
Load AAI command, Address, 2 bytes data
SO
Check for Flash Busy Status to load next valid(1) command
CE# cont.
0
7 8
15 16 23
0
7
0
7
0
7 8
15
SCK cont.
Dn-1
AD
SI cont.
WRDI
Dn
Last 2
Data Bytes
DBSY
RDSR
WRDI followed by DBSY
to exit AAI Mode
DOUT
SO cont.
Check for Flash Busy Status to load next valid(1) command
Note 1: Valid commands during AAI programming: AAI command or WRDI command.
2: User must configure the SO pin to output Flash Busy status during AAI programming
FIGURE 5-7:
AUTO ADDRESS INCREMENT (AAI) WORD PROGRAM SEQUENCE WITH
SOFTWARE END OF WRITE DETECTION
Wait TBP or poll software STATUS
register to load next valid(1) command
CE#
MODE 3
0
7 8
15 16 23 24
31 32 39 40
47
0
7 8
15 16 23
0
7 8
15 16 23
0
7
0
7 8
15
SCK MODE 0
SI
AD
A
A
A
D0
D1
AD
Load AAI command, Address, 2 bytes data
D2
D3
AD
Dn-1
Dn
Last 2
Data Bytes
SO
WRDI
RDSR
WRDI to exit
AAI Mode
DOUT
Note 1: Valid commands during AAI programming: RDSR command or WRDI command.
5.7
4-KByte Sector Erase
The Sector Erase instruction clears all bits in the
selected 4-Kbyte sector to FFH. A Sector Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write Enable
(WREN) instruction must be executed. CE# must remain
active-low for the duration of any command sequence.
2005-2020 Microchip Technology Inc.
The Sector Erase instruction is initiated by executing
an 8-bit command, 20H, followed by address bits [A23A0]. Address bits [AMS-A12] (AMS = Most Significant
address) are used to determine the sector address
(SAX), remaining address bits can be VIL or VIH. CE#
must be driven high before the instruction is executed.
The user may poll the BUSY bit in the software STA-
DS20005051E-page 12
SST25VF040B
TUS register or wait TSE for the completion of the internal self-timed Sector Erase cycle. See Figure 5-8 for
the Sector Erase sequence.
FIGURE 5-8:
SECTOR ERASE
SEQUENCE
FIGURE 5-10:
64-KBYTE BLOCK ERASE
SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE 0
CE#
MODE 3
SCK
23 24
31
20
MSE
ADD.
ADD.
5.9
ADD.
MSE
SO
HLJKIPSHGDQFH
32-Kbyte and 64-Kbyte Block
Erase
The 32-Kbyte Block Erase instruction clears all bits in
the selected 32 Kbyte block to FFH. A Block Erase
instruction applied to a protected memory area will be
ignored. The 64-Kbyte Block-Erase instruction clears
all bits in the selected 64 Kbyte block to FFH. A Block
Erase instruction applied to a protected memory area
will be ignored. Prior to any Write operation, the Write
Enable (WREN) instruction must be executed. CE# must
remain active-low for the duration of any command
sequence. The 32-Kbyte Block Erase instruction is initiated by executing an 8-bit command, 52H, followed by
address bits [A23-A0]. Address bits [AMS-A15]
(AMS = Most Significant Address) are used to determine block address (BAX), remaining address bits can
be VIL or VIH. CE# must be driven high before the
instruction is executed. The 64-Kbyte Block Erase
instruction is initiated by executing an 8-bit command
D8H, followed by address bits [A23-A0]. Address bits
[AMS-A15] are used to determine block address (BAX),
remaining address bits can be VIL or VIH. CE# must be
driven high before the instruction is executed. The user
may poll the BUSY bit in the software STATUS register
or wait TBE for the completion of the internal self-timed
32-Kbyte Block Erase or 64-Kbyte Block Erase cycles.
See Figure 5-9 and Figure 5-10 for the 32-Kbyte Block
Erase and 64-Kbyte Block Erase sequences.
FIGURE 5-9:
32-KBYTE BLOCK ERASE
SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
52
SI
MSB
SO
15 16
23 24
MODE 0
ADDR
ADDR
31
ADDR
ADDR
MSB
MSB
SO
SI
5.8
15 16
ADDR
D8
SI
0 1 2 3 4 5 6 7 8
MODE 0
HLJKIPSHGDQFH
Chip Erase
The Chip Erase instruction clears all bits in the device
to FFH. A Chip Erase instruction will be ignored if any
of the memory area is protected. Prior to any Write
operation, the Write Enable (WREN) instruction must be
executed. CE# must remain active-low for the duration
of the Chip Erase instruction sequence. The Chip
Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven high before the
instruction is executed. The user may poll the BUSY bit
in the software STATUS register or wait TCE for the
completion of the internal self-timed Chip Erase cycle.
See Figure 5-11 for the Chip Erase sequence.
FIGURE 5-11:
CHIP ERASE SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
60 or C7
SI
MSE
SO
5.10
HLJKIPSHGDQFH
Read STATUS Register (RDSR)
The Read STATUS Register (RDSR) instruction allows
reading of the STATUS register. The STATUS register
may be read at any time even during a write (program/
erase) operation. When a write operation is in progress, the BUSY bit may be checked before sending any
new commands to assure that the new commands are
properly received by the device. CE# must be driven
low before the RDSR instruction is entered and remain
low until the status data is read. Read STATUS register
is continuous with ongoing clock cycles until it is terminated by a low-to-high transition of the CE#. See
Figure 5-12 for the RDSR instruction sequence.
ADDR
MSB
HLJKIPSHGDQFH
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DS20005051E-page 13
SST25VF040B
FIGURE 5-12:
READ STATUS REGISTER (RDSR) SEQUENCE
CE#
MODE 3
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MODE 0
05
SI
MSE
High-Impedance
SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
67$786
Register Out
MSb
5.11
Write Enable (WREN) Sequence
FIGURE 5-14:
The Write Enable (WREN) instruction sets the Write
Enable Latch bit in the STATUS register to ‘1’ allowing
write operations to occur. The WREN instruction must be
executed prior to any write (program/erase) operation.
The WREN instruction may also be used to allow execution of the Write STATUS Register (WRSR) instruction;
however, the Write Enable Latch bit in the STATUS register will be cleared upon the rising edge CE# of the
WRSR instruction. CE# must be driven high before the
WREN instruction is executed.
FIGURE 5-13:
WRITE ENABLE (WREN)
SEQUENCE
CE#
MODE 3
SCK
SCK
0 1 2 3 4 5 6 7
MODE 0
06
SI
MSE
SO
5.12
HLJKIPSHGDQFH
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write
Enable-Latch bit and AAI bit to ‘0’ disabling any new
Write operations from occurring. The WRDI instruction
will not terminate any programming operation in progress. Any program operation in progress may continue
up to TBP after executing the WRDI instruction. CE#
must be driven high before the WRDI instruction is executed.
0 1 2 3 4 5 6 7
MODE 0
04
SI
MSE
SO
5.13
CE#
MODE 3
WRITE DISABLE (WRDI)
SEQUENCE
HLJKIPSHGDQFH
Enable Write STATUS Register
(EWSR)
The Enable Write STATUS Register (EWSR) instruction
arms the Write STATUS Register (WRSR) instruction
and opens the STATUS register for alteration. The
Write STATUS Register instruction must be executed
immediately after the execution of the Enable Write
STATUS Register instruction. This two-step instruction
sequence of the EWSR instruction followed by the WRSR
instruction works like SDP (software data protection)
command structure which prevents any accidental
alteration of the STATUS register values. CE# must be
driven low before the EWSR instruction is entered and
must be driven high before the EWSR instruction is executed.
5.14
Write STATUS Register (WRSR)
The Write STATUS Register instruction writes new values to the BP3, BP2, BP1, BP0, and BPL bits of the
STATUS register. CE# must be driven low before the
command sequence of the WRSR instruction is entered
and driven high before the WRSR instruction is executed. See Figure 5-15 for EWSR or WREN and WRSR
instruction sequences.
Executing the Write STATUS Register instruction will
be ignored when WP# is low and BPL bit is set to ‘1’.
When the WP# is low, the BPL bit can only be set from
‘0’ to ‘1’ to lock-down the STATUS register, but cannot
be reset from ‘1’ to ‘0’. When WP# is high, the lock-
2005-2020 Microchip Technology Inc.
DS20005051E-page 14
SST25VF040B
WRSR instruction. In this case, a single WRSR instruction
can set the BPL bit to ‘1’ to lock down the STATUS register as well as altering the BP0, BP1, and BP2 bits at
the same time. See Table 4-1 for a summary description of WP# and BPL functions.
down function of the BPL bit is disabled and the BPL,
BP0, and BP1 and BP2 bits in the STATUS register can
all be changed. As long as BPL bit is set to ‘0’ or WP#
pin is driven high (VIH) prior to the low-to-high transition
of the CE# pin at the end of the WRSR instruction, the
bits in the STATUS register can all be altered by the
FIGURE 5-15:
ENABLE WRITE STATUS REGISTER (EWSR) OR WRITE ENABLE (WREN) AND
WRITE STATUS REGISTER (WRSR) SEQUENCE
CE#
0 1 2 3 4 5 6 7
MODE 3
SCK
MODE 3
MODE 0
STATUS
REGISTER IN
7 6 5 4 3 2 1 0
01
50 or 06
SI
MSE
MSE
MSE
High-Impedance
SO
5.15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MODE 0
JEDEC Read ID
out on the SO pin. Byte 1, BFH, identifies the manufacturer as Microchip. Byte 2, 25H, identifies the memory
type as SPI Serial Flash. Byte 3, 8EH, identifies the
device as SST25VF040B. The instruction sequence is
shown in Figure 5-16. The JEDEC Read ID instruction
is terminated by a low-to-high transition on CE# at any
time during data output.
The JEDEC Read ID instruction identifies the device as
SST25VF040B and the manufacturer as Microchip.
The device information can be read from executing the
8-bit command, 9FH. Following the JEDEC Read ID
instruction, the 8-bit manufacturer’s ID, BFH, is output
from the device. After that, a 16-bit device ID is shifted
FIGURE 5-16:
JEDEC READ ID SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
MODE 0
SI
SO
9F
High-Impedance
25
BF
MSE
TABLE 5-2:
JEDEC READ ID DATA
Manufacturer’s ID
5.16
8E
MSE
Device ID
Memory Type
Memory Capacity
Byte1
Byte 2
Byte 3
BFH
25H
8EH
Read ID (RDID)
The Read ID (RDID) instruction identifies the devices
as SST25VF040B and manufacturer as Microchip.
This command is backward compatible and should be
2005-2020 Microchip Technology Inc.
used as default device identification when multiple versions of SPI Serial Flash devices are used in a design.
The device information can be read from executing an
8-bit command, 90H or ABH, followed by address bits
DS20005051E-page 15
SST25VF040B
Refer to Table 5-2 and Table 5-3 for device identification data.
[A23-A0]. Following the Read ID instruction, the manufacturer’s ID is located in address 00000H and the
device ID is located in address 00001H. Once the
device is in Read ID mode, the manufacturer’s and
device ID output data toggles between address
00000H and 00001H until terminated by a low-to-high
transition on CE#.
FIGURE 5-17:
READ ID SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31 32
39 40
47 48
55 56
63
MODE 0
90 or AB
SI
00
00
MSE
ADD 1
MSE
HLJKIPSHGDQFH
SO
BF
Device ID
BF
Device ID
HLJK
IPSHGDQFH
MSE
Note 1: The manufacturer’s and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
Device ID = 8EH for SST25VF040B.
TABLE 5-3:
PRODUCT IDENTIFICATION
Manufacturer’s ID
Address
Data
00000H
BFH
00001H
8DH
Device ID
SST25VF040B
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DS20005051E-page 16
SST25VF040B
6.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (†)
Temperature under bias ..........................................................................................................................-55°C to +125°C
Storage temperature ...............................................................................................................................-65°C to +150°C
DC voltage on any pin to ground potential ...........................................................................................-0.5V to VDD+0.5V
Transient voltage (
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