Obsolete Device
Please contact Microchip Sales for replacement information.
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 are members of
the Serial Flash 25 Series family and feature a four-wire, SPI-compatible interface
that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. SPI serial flash memory is manufactured with
SST proprietary, high performance CMOS SuperFlash technology. The split-gate
cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.
Features
• Single Voltage Read and Write Operations
– 1.65-1.95V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
– 40MHz
• Superior Reliability
– Endurance: 100,000 Cycles
– Greater than 100 years Data Retention
• Ultra-Low Power Consumption:
– Active Read Current: 2 mA (typical @ 20MHz)
– Standby Current: 2 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
(2 Mbit and 4 Mbit only)
• Fast Erase and Byte-Program:
– Chip-Erase Time: 125 ms (typical)
– Sector-/Block-Erase Time: 62ms (typical)
– Byte-Program Time: 50 µS (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over Byte-Program operations
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin
• Reset Pin (RST#) or Programmable Hold Pin
(HOLD#) option
– Hardware Reset pin as default
– Hold pin option to suspend a serial sequence without
deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the status
register
• Software Write Protection
– Write protection through Block-Protection bits in status
register
• Temperature Range
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC (150 mils)
– 8-contact WSON (5mm x 6mm)
• All devices are RoHS compliant
©2014 Silicon Storage Technology, Inc.
www.microchip.com
DS20005016C
11/14
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Product Description
The SST25WF512, SST25WF010, SST25WF020, and SST25WF040 are members of the Serial Flash
25 Series family and feature a four-wire, SPI-compatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. SST25WF512/010/
020/040 SPI serial flash memories are manufactured with SST proprietary, high-performance CMOS
SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.
The SST25WF512/010/020/040 devices significantly improve performance and reliability, while lowering power consumption. The devices write (Program or Erase) with a single power supply of 1.651.95V for SST25WF512/010/020/040. The total energy consumed is a function of the applied voltage,
current, and time of application. Since for any given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time, the total energy consumed during any Erase or
Program operation is less than alternative flash memory technologies.
The SST25WF512/010/020/040 devices are offered in both 8-lead SOIC and an 8-contact WSON
packages. See Figure 2 for the pin assignment.
©2014 Silicon Storage Technology, Inc.
DS20005016C
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11/14
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Block Diagram
X - Decoder
Address
Buffers
and
Latches
SuperFlash
Memory
Y - Decoder
I/O Buffers
and
Data Latches
Control Logic
Serial Interface
CE#
SCK
SI
SO
WP#
RST#/HOLD#
1328 F01.0
Note: In AAI mode, the SO pin functions as an RY/BY# pin when configured as a ready/
busy status pin. See “End-of-Write Detection” on page 16. for more information.
Figure 1: Functional Block Diagram
©2014 Silicon Storage Technology, Inc.
DS20005016C
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11/14
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Pin Description
Top View
CE#
1
8
VDD
SO
2
7
RST#/HOLD#
WP#
3
6
SCK
VSS
4
5
SI
CE#
1
SO
2
8
VDD
7
RST#/HOLD#
Top View
WP#
3
6
SCK
VSS
4
5
SI
1328 08-wson P2.0
1328.25WF 08-soic-P0.0
8-Contact WSON
8-Lead SOIC
Figure 2: Pin Assignment for 8-Lead SOIC and 8-Contact WSON
Table 1: Pin Description
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the
clock input, while output data is shifted out on the falling edge of the clock
input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY#
pin. See “End-of-Write Detection” on page 16. for more information.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain
low for the duration of any command sequence.
WP#
Write Protect
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status
register.
Reset
RST#/
HOLD#
To reset the operation of the device and the internal logic. The device powers
on with RST# pin functionality as default.
Hold
To temporarily stop serial communication with SPI Flash memory while
device is selected. This is selected by an instruction sequence which is
detailed in “Reset/Hold Mode” on page 6.
VDD
Power Supply
To provide power supply voltage: 1.65-1.95V for SST25WF512/010/020/040
VSS
Ground
T1.0 20005016
©2014 Silicon Storage Technology, Inc.
DS20005016C
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11/14
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Memory Organization
The SST25WF512/010/020/040 SuperFlash memory arrays are organized in uniform 4 KByte with 16
KByte, 32 KByte, and 64 KByte (2 Mbit and 4 Mbit Only) overlay erasable blocks.
Device Operation
The SST25WF512/010/020/040 are accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the
device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK).
The SST25WF512/010/020/040 support both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations.
The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the
bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising
edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the
SCK clock signal.
CE#
SCK
SI
MODE 3
MODE 3
MODE 0
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
SO
HIGH IMPEDANCE
DON T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1328 F03.0
Figure 3: SPI Protocol
©2014 Silicon Storage Technology, Inc.
DS20005016C
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Reset/Hold Mode
The RST#/HOLD# pin provides either a hardware reset or a hold pin. From power-on, the RST#/
HOLD# pin defaults as a hardware reset pin (RST#). The Hold mode for this pin is a user selected
option where an Enable-Hold instruction enables the Hold mode. Once selected as a hold pin
(HOLD#), the RST#/HOLD# pin will be configured as a HOLD# pin, and goes back to RST# pin only
after a power-off and power-on sequence.
Reset
If the RST#/HOLD# pin is used as a reset pin, RST# pin provides a hardware method for resetting the
device. Driving the RST# pin high puts the device in normal operating mode. The RST# pin must be
driven low for a minimum of TRST time to reset the device. The SO pin is in high impedance state while
the device is in reset. A successful reset will reset the status register to its power-up state. See Table 4
for default power-up modes. A device reset during an active Program or Erase operation aborts the
operation and data of the targeted address range may be corrupted or lost due to the aborted erase or
program operation. The device exits AAI Programming Mode in progress and places the SO pin in high
impedance state.
CE#
TRECR
TRECP
TRECE
SCK
TRST
RST#
TRHZ
SO
SI
1328 Fx4.0
Figure 4: Reset Timing Diagram
Table 2: Reset Timing Parameters
Symbol
Parameter
Min
100
Max
Units
TRST
Reset Pulse Width
TRHZ
Reset to High-Z Output
107
ns
ns
TRECR
Reset Recovery from Read
100
ns
TRECP
Reset Recovery from Program
10
µs
TRECE
Reset Recovery from Erase
1
ms
T2.20005016
©2014 Silicon Storage Technology, Inc.
DS20005016C
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Hold
The Hold operation enables the hold pin functionality of the RST#/HOLD# pin. Once set to hold pin
mode, the RST#/HOLD# pin continues functioning as a hold pin until the device is powered off and
then powered on. After a power-off and power-on, the pin functionality returns to a reset pin (RST#)
mode. See “Enable-Hold (EHLD)” on page 22 for detailed timing of the Hold instruction.
In the hold mode, serial sequences underway with the SPI Flash memory are paused without resetting
the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD#
mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The
Hold mode ends when the rising edge of the HOLD# signal coincides with the SCK active low state. If
the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active low state, then the device exits Hold mode when
the SCK next reaches the active low state. See Figure 5 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, the device returns to standby mode. The device
can then be re-initiated with the command sequences listed in Tables 9 and 10. As long as HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device,
HOLD# must be driven active high, and CE# must be driven active low. See Figure 5 for Hold timing.
SCK
HOLD#
Active
Hold
Active
Hold
Active
1328 Fx5.0
Figure 5: Hold Condition Waveform
Write Protection
SST25WF512/010/020/040 provide software Write protection. The Write Protect pin (WP#) enables or
disables the lock-down function of the status register. The Block-Protection bits (BP2, BP1, BP0, and
BPL) in the status register provide Write protection to the memory array and the status register. See
Table 5 for the Block-Protection description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 3). When WP# is high, the lock-down function of the BPL bit is disabled.
Table 3: Conditions to execute Write-Status-Register (WRSR) Instruction
WP#
BPL
L
1
Execute WRSR Instruction
Not Allowed
L
0
Allowed
H
X
Allowed
T3.0 20005016
©2014 Silicon Storage Technology, Inc.
DS20005016C
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Status Register
The software status register provides status on whether the flash memory array is available for any
Read or Write operation, whether the device is Write enabled, and the state of the Memory Write protection. During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the
software status register.
Table 4: Software Status Register
Bit Name Function
Default at
Power-up
Read/Write
0
BUSY
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
1
WEL
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
0
R
2
BP0
Indicate current level of block write protection (See Tables 5 through 8)
1
R/W
3
BP1
Indicate current level of block write protection (See Tables 5 through 8)
1
R/W
4
BP2
Indicate current level of block write protection (See Tables 5 through 8)
1
R/W
5
RES
Reserved for future use
0
N/A
6
AAI
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
0
R
7
BPL
1 = BP1 and BP0 are read-only bits
0 = BP1 and BP0 are read/writable
0
R/W
T4.1 20005016
Busy
The Busy bit determines whether there is an internal Erase or Program operation in progress. A ‘1’ for
the Busy bit indicates the device is busy with an operation in progress. A ‘0’ indicates the device is
ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal Write-Enable-Latch memory. If the WEL
bit is set to ‘1’, it indicates the device is Write enabled. If the bit is set to ‘0’ (reset), it indicates the
device is not Write enabled and does not accept any Write (Program/Erase) commands. The WriteEnable-Latch bit is automatically reset under the following conditions:
•
•
•
•
•
•
•
•
•
Device Reset
Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instruction completion
Auto Address Increment (AAI) programming is completed or reached its highest unprotected memory address
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
Write-Status-Register instructions
©2014 Silicon Storage Technology, Inc.
DS20005016C
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11/14
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Auto Address Increment (AAI)
The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI
programming mode or Byte-Program mode. The default at power up is Byte-Program mode.
Block-Protection (BP2, BP1, BP0)
The Block-Protection (BP1, BP0) bits define the size of the memory area to be software protected
against any memory Write (Program or Erase) operation, see Tables 5-7. The Write-Status-Register
(WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is ‘0’. Chip-Erase can only be executed if Block-Protection bits are all ‘0’. After
power-up, BP2, BP1, and BP0 are set to defaults. See Table 4 for defaults at power-up.
Block Protection Lock-Down (BPL)
When the WP# pin is driven low (VIL), it enables the Block-Protection-Lock-Down (BPL) bit. When BPL is
set to ‘1’, it prevents any further alteration of the BPL, BP1, and BP0 bits. When the WP# pin is driven high
(VIH), the BPL bit has no effect and its value is ‘Don’t Care’. After power-up, the BPL bit is reset to ‘0’.
Table 5: Software Status Register Block Protection for SST25WF512
Status Register Bit
Protection Level
None
Protected Memory Address
BP11
BP0
512 Kbit
0
0
None
1 (Upper Quarter Memory)
0
1
00C000H-00FFFFH
2 (Upper Half Memory)
1
0
008000H-00FFFFH
3 (Full Memory)
1
1
000000H-00FFFFH
T5.1 20005016
1. Default at power-up for BP1 and BP0 is ‘11’.
Table 6: Software Status Register Block Protection for SST25WF010
Status Register Bit
Protected Memory Address
BP11
BP0
None
0
0
None
1 (Upper Quarter Memory)
0
1
018000H-01FFFFH
2 (Upper Half Memory)
1
0
010000H-01FFFFH
3 (Full Memory)
1
1
000000H-01FFFFH
Protection Level
1 Mbit
T6.0 20005016
1. Default at power-up for BP1 and BP0 is ‘11’.
Table 7: Software Status Register Block Protection for SST25WF020
Status Register Bit
Protected Memory Address
BP11
BP0
2 Mbit
None
0
0
None
1 (Upper Quarter Memory)
0
1
030000H-03FFFFH
2 (Upper Half Memory)
1
0
020000H-03FFFFH
3 (Full Memory)
1
1
000000H-03FFFFH
Protection Level
T7.0 20005016
1. Default at power-up for BP1 and BP0 is ‘11’.
©2014 Silicon Storage Technology, Inc.
DS20005016C
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Table 8: Software Status Register Block Protection for SST25WF040
Status Register Bit
Protection Level
None
Protected Blocks
None
Protected Memory Address
BP21
BP1
BP0
4 Mbit
0
0
0
None
1 (Upper Eighth Memory)
Blocks 14 through 15
0
0
1
70000H-7FFFFH
2 (Upper Quarter Memory)
Blocks 12 through 15
0
1
0
60000H-7FFFFH
3 (Upper Half Memory)
Blocks 8 through 15
0
1
1
40000H-7FFFFH
4 (Full Memory)
Blocks 0 through 15
1
0
0
00000H-7FFFFH
5 (Full Memory)
Blocks 0 through 15
1
0
1
00000H-7FFFFH
6 (Full Memory)
Blocks 0 through 15
1
1
0
00000H-7FFFFH
7 (Full Memory)
Blocks 0 through 15
1
1
1
00000H-7FFFFH
T8.0 20005016
1. Default at power-up for BP2, BP1, and BP0 is ‘11’.
©2014 Silicon Storage Technology, Inc.
DS20005016C
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Instructions
Instructions are used to read, write (Erase and Program), and configure the SST25WF512/010/020/
040. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The
Write-Enable (WREN) instruction must be executed prior to Byte-Program, Auto Address Increment
(AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instructions. The
complete instructions are provided in Tables 9 and 10. All instructions are synchronized off a high-tolow transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must be driven low before an instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instructions). Any low-to-high transition on CE#, before receiving the last bit of an instruction bus cycle, will
terminate the instruction in progress and return the device to standby mode. Instruction commands
(Op Code), addresses, and data are all input from the most significant bit (MSB) first.
Table 9: Device Operation Instructions for SST25WF512 and SST25WF010
Address Dummy
Data
Maximum
Cycle(s)2 Cycle(s) Cycle(s) Frequency
3
0
1 to
20 MHz
3
1
1 to
Instruction
Read
High-Speed Read
Description
Read Memory
Read Memory at Higher
Speed
Op Code Cycle1
0000 0011b (03H)
0000 1011b (0BH)
4 KByte SectorErase3
Erase 4 KByte of
memory array
0010 0000b (20H)
3
0
0
32 KByte BlockErase4
Erase 32 KByte block
0101 0010b (52H)
of memory array
Erase Full Memory Array 0110 0000b (60H)
or
1100 0111b (C7H)
To Program One Data Byte 0000 0010b (02H)
3
0
0
0
0
0
Chip-Erase
Byte-Program
AAI-Word-Program5
RDSR6
EWSR7
WRSR
WREN7
WRDI
RDID8
EBSY
DBSY
JEDEC-ID
EHLD
3
0
1
Auto Address Increment
Programming
1010 1101b (ADH)
3
0
2 to
Read-Status-Register
Enable-Write-StatusRegister
Write-Status-Register
0000 0101b (05H)
0110 0000b (50H)
0
0
0
0
1 to
0
0000 0001b (01H)
0
0
1
0000 0110b (06H)
0000 0100b (04H)
1001 0000b (90H)
or
1010 1011b (ABH)
Enable SO to output RY/ 0111 0000b (70H)
BY# status during AAI
programming
Disable SO to output RY/ 1000 0000b (80H)
BY# status during AAI
programming
JEDEC ID read
1001 1111b (9FH)
Enable HOLD# pin func- 1010 1010b (AAH)
tionality of the RST#/
HOLD# pin
0
0
3
0
0
0
0
0
1 to
0
0
0
0
0
0
0
0
0
0
3 to
0
Write-Enable
Write-Disable
Read-ID
40 MHz
T9.0 20005016
©2014 Silicon Storage Technology, Inc.
DS20005016C
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
1.
2.
3.
4.
5.
One bus cycle is eight clock periods.
Address bits above the most significant bit of each density can be VIL or VIH.
4 KByte Sector-Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
32 KByte Block-Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.
To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of
data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be
programmed into the
initial address [A23-A1] with A0 = 1.
6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
7. Either EWSR or WREN followed by WRSR will write to the Status register. The EWSR-WRSR sequence provides backward compatibility to the SST25VF/LF series. The WREN-WRSR sequence is recommended for new designs.
8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
Table 10: Device Operation Instructions for SST25WF020 AND SST25WF040
Address Dummy
Data
Maximum
Cycle(s)2 Cycle(s) Cycle(s) Frequency
Instruction
Description
Op Code Cycle1
Read
Read Memory
0000 0011b (03H)
3
0
1 to
High-Speed Read Read Memory at Higher
Speed
0000 1011b (0BH)
3
1
1 to
4 KByte SectorErase3
Erase 4 KByte of memory
array
0010 0000b (20H)
3
0
0
32 KByte BlockErase4
Erase 32 KByte block
of memory array
0101 0010b (52H)
3
0
0
64 KByte BlockErase5
Erase 64 KByte block
of memory array
1101 1000b (D8H)
3
0
0
Chip-Erase
Erase Full Memory Array
0110 0000b (60H)
or
1100 0111b (C7H)
0
0
0
Byte-Program
To Program One Data Byte 0000 0010b (02H)
3
0
1
AAI-Word-Program6
Auto Address Increment
Programming
1010 1101b (ADH)
3
0
2 to
RDSR7
Read-Status-Register
0000 0101b (05H)
0
0
1 to
EWSR8
Enable-Write-Status-Regis- 0110 0000b (50H)
ter
0
0
0
WRSR
Write-Status-Register
0000 0001b (01H)
0
0
1
WREN8
Write-Enable
0000 0110b (06H)
0
0
0
WRDI
Write-Disable
0000 0100b (04H)
0
0
0
RDID9
Read-ID
1001 0000b (90H)
or
1010 1011b (ABH)
3
0
1 to
EBSY
Enable SO to output RY/
0111 0000b (70H)
BY# status during AAI programming
0
0
0
DBSY
Disable SO to output RY/
1000 0000b (80H)
BY# status during AAI programming
0
0
0
JEDEC-ID
JEDEC ID read
1001 1111b (9FH)
0
0
3 to
EHLD
Enable HOLD# pin function- 1010 1010b (AAH)
ality of the RST#/HOLD# pin
0
0
0
20 MHz
40 MHz
T10.0 20005016
©2014 Silicon Storage Technology, Inc.
DS20005016C
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
1.
2.
3.
4.
5.
6.
One bus cycle is eight clock periods.
Address bits above the most significant bit of each density can be VIL or VIH.
4 KByte Sector-Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
32 KByte Block-Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.
64 KByte Block-Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.
To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of
data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be
programmed into the
initial address [A23-A1] with A0 = 1.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
8. Either EWSR or WREN followed by WRSR will write to the Status register. The EWSR-WRSR sequence provides backward compatibility to the SST25VF/LF series. The WREN-WRSR sequence is recommended for new designs.
9. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
Read (20 MHz)
The Read instruction, 03H, supports up to 20 MHz Read. The device outputs a data stream starting
from the specified address location. The data stream is continuous through all addresses until terminated by a low-to-high transition on CE#. The internal address pointer automatically increments until
the highest memory address is reached. Once the highest memory address is reached, the address
pointer automatically increments to the beginning (wrap-around) of the address space. For example,
for 2 Mbit density, once the data from the address location 3FFFFH is read, the next output is from
address location 000000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits A23-A0. CE# must remain active low for the duration of the Read cycle. See Figure 6 for the Read sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
ADD.
ADD.
03
SI
MSB
MSB
SO
15 16
23 24
31 32
39 40
47
48
55 56
63 64
70
MODE 0
HIGH IMPEDANCE
ADD.
N
DOUT
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSB
1328 Fx6.0
Figure 6: Read Sequence
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SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
High-Speed-Read (40 MHz)
The High-Speed-Read instruction supporting up to 40 MHz Read is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the
duration of the High-Speed-Read cycle. See Figure 7 for the High-Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a
low-to-high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer
will automatically increment to the beginning (wrap-around) of the address space. For example, for 2
Mbit density, once the data from address location 3FFFFH is read, the next output will be from address
location 000000H.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
80
71 72
MODE 0
0B
SI
ADD.
ADD.
ADD.
X
MSB
SO
N
DOUT
HIGH IMPEDANCE
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSB
1328 F07.0
Figure 7: High-Speed-Read Sequence
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EOL Data Sheet
Byte-Program
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected
byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction
applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain
active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by
executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is
input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBP for the completion of
the internal self-timed Byte-Program operation. See Figure 8 for the Byte-Program sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5
6 7 8
15 16
23 24
31 32
39
MODE 0
SI
02
ADD.
ADD.
MSB
ADD.
DIN
MSB LSB
HIGH IMPEDANCE
SO
1328 F08.0
Figure 8: Byte-Program Sequence
Auto Address Increment (AAI) Word-Program
The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the
next sequential address location. This feature decreases total programming time when multiple bytes
or the entire memory array is to be programmed. An AAI Word program instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH)
when initiating an AAI Word Program operation. While within AAI Word Programming sequence, the
only valid instructions are AAI Word (ADH), RDSR (05H), or WRDI (04H). Users have three options to
determine the completion of each AAI Word program cycle: hardware detection by reading the Serial
Output, software detection by polling the BUSY bit in the software status register or wait TBP. Refer to
End-Of-Write Detection section for details.
Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI Word
Program instruction is initiated by executing an 8-bit command, ADH, followed by address bits [A23-A0].
Following the addresses, two bytes of data are input sequentially, each one from MSB (Bit 7) to LSB
(Bit 0). The first byte of data (D0) will be programmed into the initial address [A23-A1] with A0 = 0, the
second byte of Data (D1) will be programmed into the initial address [A23-A1] with A0 = 1. CE# must be
driven high before the AAI Word Program instruction is executed. The user must check the BUSY status before entering the next valid command. Once the device indicates it is no longer busy, data for the
next two sequential addresses may be programmed and so on. When the last desired byte had been
entered, check the busy status using the hardware method or the RDSR instruction and execute the
Write-Disable (WRDI) instruction, 04H, to terminate AAI. Check the busy status after WRDI to determine if the device is ready for any command. See Figures 11 and 12 for AAI Word programming
sequence.
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SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
There is no wrap mode during AAI programming; once the highest unprotected memory address is
reached, the device will exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0) and the AAI
bit (AAI = 0).
End-of-Write Detection
There are three methods to determine completion of a program cycle during AAI Word programming:
hardware detection by reading the Serial Output, software detection by polling the BUSY bit in the Software Status Register or wait TBP.
Hardware End-of-Write Detection
The Hardware End-of-Write detection method eliminates the overhead of polling the Busy bit in the
Software Status Register during an AAI Word program operation. The 8-bit command, 70H, configures
the Serial Output (SO) pin to indicate Flash Busy status during AAI Word programming, as shown in
Figure 9. The 8-bit command, 70H, must be executed prior to executing an AAI Word-Program instruction. Once an internal programming operation begins, asserting CE# will immediately drive the status
of the internal flash status on the SO pin. A ‘0’ indicates the device is busy and a ‘1’ indicates the
device is ready for the next instruction. De-asserting CE# will return the SO pin to tri-state.
The 8-bit command, 80H, disables the Serial Output (SO) pin to output busy status during AAI-Wordprogram operation, and re-configures SO as an output pin. In this state, the SO pin will function as a
normal Serial Output pin. At this time, the RDSR command can poll the status of the Software Status
Register. This is shown in Figure 10.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
70
SI
MSB
SO
HIGH IMPEDANCE
1328 F09.0
Figure 9: Enable SO as Hardware RY/BY# during AAI Programming
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
80
SI
MSB
SO
HIGH IMPEDANCE
1328 F10.0
Figure 10:Disable SO as Hardware RY/BY# during AAI Programming
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SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
CE#
8
0
8 0
16
8
32
24
48
40
0
16
8
24 0
16
8
24
8 0
0
8
16
SCK
SI
WREN
AD
A
A
A
D0
D2
AD
D1
D3
AD
Dn-1
Dn
WRDI
Last 2
Data Bytes
Load AAI command, Address, 2 bytes data
RDSR
WRDI to exit
AAI Mode
DOUT
SO
Check for Flash Busy Status to load next valid command
Output Status
Register Data
1328 F11.1
Note: Valid Commands during AAI programming: AAI command or WRDI command.
User must configure the SO pin to output Flash Busy status during AAI programming.
Figure 11:Auto Address Increment (AAI) Word Program Sequence with Hardware End-ofWrite Detection
Check for Flash Busy Status to load next valid command
CE#
8
0
8 0
16
8
24
32
48
40
24 0
16
8
0
16
8
24
0
8
0
8
16
SCK
SI
WREN
AD
A
A
A
D0
D1
Load AAI command, Address, 2 bytes data
AD
D2
D3
AD
Dn-1
Dn
WRDI
Last 2
Data Bytes
WRDI to exit
AAI Mode
RDSR
SO
DOUT
Output Status
Register Data
1328 F12.1
Note: Valid Commands during AAI programming: AAI command, Read Status Register command, or WRDI command.
Figure 12:Auto Address Increment (AAI) Word Program Sequence with Software End-ofWrite Detection
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SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area will be ignored. Prior to any Write operation, the WriteEnable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23-A0]. Address bits [AMS-A12] (AMS = Most Significant address) are used to
determine the sector address (SAX), remaining address bits can be VIL or VIH. CE# must be driven high
before the instruction is executed. The user may poll the Busy bit in the software status register or wait
TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 13 for the SectorErase sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31
MODE 0
ADD.
ADD.
20
SI
MSB
ADD.
MSB
SO
HIGH IMPEDANCE
1326 F13.0
Figure 13:Sector-Erase Sequence
32-KByte Block-Erase
The Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area is ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must remain active low for the duration of any command
sequence. The Block-Erase instruction is initiated by executing an 8-bit command, 52H, followed by
address bits [A23-A0]. Address bits [AMS-A15] (AMS = Most Significant Address) are used to determine
block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. Poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Erase. See Figure 14 for the Block-Erase sequences.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE 0
ADDR
52
SI
MSB
ADDR
ADDR
MSB
SO
HIGH IMPEDANCE
1328 F14.0
Figure 14:32-KByte Block-Erase Sequence
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SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
64-KByte Block-Erase for SST25WF020 and SST25WF040
The Block-Erase instruction clears all bits in the selected 64 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area is ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must remain active low for the duration of any command
sequence. The Block-Erase instruction is initiated by executing an 8-bit command, D8H, followed by
address bits [A23-A0]. Address bits [AMS-A16] (AMS = Most Significant Address) are used to determine
block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. Poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Erase. See Figure 15 for the Block-Erase sequences.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE 0
ADDR
ADDR
D8
SI
MSB
ADDR
MSB
SO
HIGH IMPEDANCE
1328 F15.0
Figure 15:64-KByte Block-Erase Sequence
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction is ignored if
any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must
be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence. The
Chip-Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven high
before the instruction is executed. The user may poll the Busy bit in the software status register or wait TCE
for the completion of the internal self-timed Chip-Erase cycle. See Figure 16 for the Chip-Erase
sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
60 or C7
SI
MSB
SO
HIGH IMPEDANCE
1328 F16.0
Figure 16:Chip-Erase Sequence
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction, 05H, allows reading of the status register. The status
register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the
new commands are properly received by the device. CE# must be driven low before the RDSR instruction is entered and remain low until the status data is read. Read-Status-Register is continuous with
ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 17 for the
RDSR instruction sequence.
CE#
MODE 3
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MODE 0
05
SI
MSB
SO
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
Status
Register Out
1327 F17.0
Figure 17:Read-Status-Register (RDSR) Sequence
Write-Enable (WREN)
The Write-Enable (WREN) instruction, 06H, sets the Write-Enable-Latch bit in the Status Register to 1
allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. The WREN instruction may also be used to allow execution of the Write-Status-Register (WRSR) instruction; however, the Write-Enable-Latch bit in the Status Register will be
cleared upon the rising edge CE# of the WRSR instruction. CE# must be driven high before the WREN
instruction is executed. See Figure 18 for the WREN instruction sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
06
SI
MSB
SO
HIGH IMPEDANCE
1328 F18.0
Figure 18:Write Enable (WREN) Sequence
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction, 04H, resets the Write-Enable-Latch bit and AAI to 0 disabling
any new Write operations from occurring. The WRDI instruction will not terminate any programming
operation in progress. Any program operation in progress may continue up to TBP after executing the
WRDI instruction. CE# must be driven high before the WRDI instruction is executed. See Figure 19 for
the WRDI instruction sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
04
SI
MSB
SO
HIGH IMPEDANCE
1328 Fx19.0
Figure 19:Write Disable (WRDI) Sequence
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR)
instruction and opens the status register for alteration. The Write-Status-Register instruction must be
executed immediately after the execution of the Enable-Write-Status-Register instruction. This twostep instruction sequence of the EWSR instruction followed by the WRSR instruction works like SDP
(software data protection) command structure which prevents any accidental alteration of the status
register values. CE# must be driven low before the EWSR instruction is entered and must be driven
high before the EWSR instruction is executed. See Figure 20 for EWSR instruction followed by WRSR
instruction.
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to the BP1, BP0, and BPL bits of the status
register. CE# must be driven low before the command sequence of the WRSR instruction is entered
and driven high before the WRSR instruction is executed. See Figure 20 for EWSR or WREN and
WRSR instruction sequences.
Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to
‘1’. When the WP# is low, the BPL bit can only be set from ‘0’ to ‘1’ to lock-down the status register, but
cannot be reset from ‘1’ to ‘0’. When WP# is high, the lock-down function of the BPL bit is disabled and
the BPL, BP0, and BP1 bits in the status register can all be changed. As long as BPL bit is set to ‘0’ or
WP# pin is driven high (VIH) prior to the low-to-high transition of the CE# pin at the end of the WRSR
instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to ‘1’ to lock down the status register as well as altering the
BP0, and BP1 bits at the same time. See Table 3 for a summary description of WP# and BPL func-
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SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
tions.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 3
MODE 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MODE 0
01
50 or 06
SI
MSB
MSB
STATUS
REGISTER IN
7 6 5 4 3 2 1 0
MSB
HIGH IMPEDANCE
SO
1328 F20.0
Figure 20:Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register (WRSR) Sequence
Enable-Hold (EHLD)
The 8-bit command, AAH, Enable-Hold instruction enables the HOLD functionality of the RST#/
HOLD# pin. CE# must remain active low for the duration of the Enable-Hold instruction sequence. CE#
must be driven high before the instruction is executed. See Figure 21 for the Enable-Hold instruction
sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
AA
SI
MSB
SO
HIGH IMPEDANCE
1328 F21.0
Figure 21:Enable-Hold Sequence
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SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Read-ID
The Read-ID instruction identifies the manufacturer as SST and the device as SST25WF512/010/020/
040. Use the Read-ID instruction to identify SST device when using multiple manufacturers in the
same socket. See Table 11.
The device information is read by executing an 8-bit command, 90H or ABH, followed by address bits
[A23-A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 000000H and
the device ID is located in address 000001H. Once the device is in Read-ID mode, the manufacturer’s
and device ID output data toggles between address 000000H and 000001H until terminated by a low
to high transition on CE#.
Table 11: Product Identification
Address
Data
Manufacturer’s ID
000000H
BFH
Device ID
SST25WF512
000001H
01H
SST25WF010
000001H
02H
SST25WF020
000001H
03H
SST25WF040
000001H
04H
T11.20005016
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
90 or AB
SI
00
00
MSB
SO
23 24
15 16
31 32
39 40
47 48
55 56
63
MODE 0
ADD
MSB
HIGH IMPEDANCE
BF
Device ID
BF
Device ID
HIGH
IMPEDANCE
MSB
1328 F22.0
Note: The manufacturer’s and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
00H will output the manufacturer’s ID first and 01H will out device ID first before toggling between the two.
Figure 22:Read-ID Sequence
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SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device as SST25WF512/010/020/040 and the manufacturer as SST. The device information can be read from executing the 8-bit command, 9FH. Following
the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that,
a 16-bit device ID is shifted out on the SO pin. The Device ID is assigned by the manufacturer and contains the type of memory in the first byte and the memory capacity of the device in the second byte.
See Figure 23 for the instruction sequence. The JEDEC Read ID instruction is terminated by a low to
high transition on CE# at any time during data output.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
MODE 0
SI
SO
9F
HIGH IMPEDANCE
25
BF
MSB
Byte 3
MSB
1328 F23.0
Note: See Table 12 for Device ID Byte 3 value.
Figure 23:JEDEC Read-ID Sequence
Table 12: JEDEC Read-ID Data-Out for SST25WF512
Device ID
Product
Manufacturer’s ID (Byte 1)
Memory Type (Byte 2)
Memory Capacity (Byte 3)
SST25WF512
SST25WF010
BFH
25H
01H
BFH
25H
02H
SST25WF020
BFH
25H
03H
SST25WF040
BFH
25H
04H
T12.0 20005016
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SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Electrical Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (