SST26VF016B
2.5V/3.0V 16-Mbit Serial Quad I/O™ (SQI™) Flash Memory
Features
• Single Voltage Read and Write Operations:
- 2.7V-3.6V or 2.3V-3.6V
• Serial Interface Architecture:
- Nibble-wide multiplexed I/O’s with SPI-like serial
command structure
- Mode 0 and Mode 3
- x1/x2/x4 Serial Peripheral Interface (SPI) Protocol
• High-Speed Clock Frequency:
- 2.7V-3.6V: 104 MHz maximum
- 2.3V-3.6V: 80 MHz maximum
• Burst Modes:
- Continuous linear burst
- 8/16/32/64-byte linear burst with wrap-around
• Superior Reliability:
- Endurance: 100,000 Cycles (minimum)
- Greater than 100 years data retention
• Low-Power Consumption:
- Active Read current: 15 mA (typical @ 104 MHz)
- Standby current: 15 µA (typical)
• Fast Erase Time:
- Sector/Block Erase: 18 ms (typical), 25 ms
(maximum)
- Chip Erase: 35 ms (typical), 50 ms
(maximum)
• Page Program:
- 256 bytes per page in x1 or x4 mode
• End-of-Write Detection:
- Software polling the BUSY bit in STATUS register
• Flexible Erase Capability:
- Uniform 4-Kbyte sectors
- Four 8-Kbyte top and bottom parameter overlay
blocks
- One 32-Kbyte top and bottom overlay blocks
- Uniform 64-Kbyte overlay blocks
• Write Suspend:
- Suspend Program or Erase operation to access
another block/sector
• Software Reset (RST) mode
• Software Write Protection:
- Individual Block Write Protection with permanent
lock-down capability
- 64-Kbyte blocks, two 32-Kbyte blocks and
eight 8-Kbyte parameter blocks
2014-2022 Microchip Technology Inc. and its subsidiaries
•
•
•
•
- Read Protection on top and bottom 8-Kbyte
parameter blocks
Security ID:
- One-Time-Programmable (OTP) 2-Kbyte,
Secure ID
- 64-bit unique, factory pre-programmed
identifier
- User-programmable area
Temperature Range:
- Industrial:
-40°C to +85°C
- Industrial Plus: -40°C to +105°C
- Extended:
-40°C to +125°C
Automotive AEC-Q100 Qualified
All devices are RoHS compliant
Packages
• 8-Lead SOIC (3.90 mm)
• 8-Lead SOIJ (5.28 mm)
• 8-Contact WDFN (6 mm x 5 mm)
Product Description
The Serial Quad I/O™ (SQI™) family of Flash memory
devices features a six-wire, 4-bit I/O interface that
allows for low-power, high-performance operation in a
low pin-count package. SST26VF016B also supports
full command-set compatibility to traditional Serial
Peripheral Interface (SPI) protocol. System designs
using SQI Flash devices occupy less board space and
ultimately lower system costs.
All members of the 26 Series SQI family are
manufactured with proprietary, high-performance
CMOS SuperFlash® technology. The split-gate cell
design and thick-oxide tunneling injector attain better
reliability and manufacturability compared with
alternate approaches.
SST26VF016B significantly improves performance and
reliability, while lowering power consumption. These
devices write (Program or Erase) with a single power
supply of 2.3V-3.6V. The total energy consumed is a
function of the applied voltage, current and time of
application. Since for any given voltage range, the
SuperFlash technology uses less current to program
and has a shorter erase time, the total energy consumed during any Erase or Program operation is less
than alternative Flash memory technologies.
See Figure 2-1 for pin assignments.
DS20005262G-page 1
SST26VF016B
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS20005262G-page 2
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
1.0
BLOCK DIAGRAM
FIGURE 1-1:
FUNCTIONAL BLOCK DIAGRAM
OTP
X - Decoder
Address
Buffers
and
Latches
SuperFlash
Memory
Y - Decoder
Page Buffer,
I/O Buffers
and
Data Latches
Control Logic
Serial Interface
WP# HOLD# SCK
2014-2022 Microchip Technology Inc. and its subsidiaries
CE#
SIO [3:0]
DS20005262G-page 3
SST26VF016B
2.0
PIN DESCRIPTION
FIGURE 2-1:
PIN DESCRIPTIONS
PIN ASSIGNMENT FOR 8-LEAD SOIC
CE#
1
SO/SIO1
8
2
7
PIN ASSIGNMENT FOR 8-LEAD SOIJ
Vඌඌ
HOLD/SIO3
Top View
CE#
1
SO/SIO1
2
8
Vඌඌ
7
HOLD/SIO3
Top View
WP#/SIO2
3
6
SCK
Vඛඛ
4
5
SI/SIO0
WP#/SIO2
3
6
SCK
Vඛඛ
4
5
SI/SIO0
PIN ASSIGNMENT FOR 8-CONTACT WDFN
CE# 1
8 Vඌඌ
SO/SIO1 2
7 HOLD/SIO3
Top View
WP#/SIO2 3
Vඛඛ 4
TABLE 2-1:
Symbol
6 SCK
5 SI/SIO0
PIN DESCRIPTION
Pin Name
Functions
The device is enabled by a high-to-low transition on CE#. CE# must remain low for
the duration of any command sequence; or in the case of Write operations, for the
command/data input sequence.
CE#
Chip Enable
SO
Serial Data Output Transfer data serially out of the device. Data is shifted out on the falling edge of the
for SPI mode
serial clock. SO is the default state after a Power-on Reset.
SIO[3:0]
Serial Data
Input/Output
Transfer commands, addresses or data serially into the device or data out of the
device. Inputs are latched on the rising edge of the serial clock. Data are shifted out
on the falling edge of the serial clock. The Enable Quad I/O (EQIO) command
instruction configures these pins for Quad I/O mode.
WP#
Write-Protect
The WP# is used in conjunction with the WPEN and IOC bits in the Configuration
register to prohibit write operations to the Block Protection register. This pin only
works in SPI, single-bit and dual-bit Read mode.
VSS
Ground
SI
Serial Data Input
for SPI mode
Transfer commands, addresses or data serially into the device. Inputs are latched on
the rising edge of the serial clock. SI is the default state after a Power-on Reset.
SCK
Serial Clock
Provide the timing of the serial interface.
Commands, addresses or input data are latched on the rising edge of the clock input,
while output data are shifted out on the falling edge of the clock input.
HOLD#
Hold
Temporarily stops serial communication with the SPI Flash memory while the device
is selected. This pin only works in SPI, single-bit and dual-bit Read mode and must
be tied high when not in use.
VDD
Power Supply
Provide power supply voltage.
DS20005262G-page 4
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
3.0
MEMORY ORGANIZATION
The SST26VF016B SQI memory array is organized in
uniform, 4-Kbyte erasable sectors with the following
erasable blocks: eight 8-Kbyte parameter, two
32-Kbyte overlay and thirty 64-Kbyte overlay blocks
(see Figure 3-1).
FIGURE 3-1:
MEMORY MAP
Top of Memory Block
8-Kbyte
8-Kbyte
8-Kbyte
8-Kbyte
32-Kbyte
...
64-Kbyte
2 Sectors for 8-Kbyte blocks
8 Sectors for 32-Kbyte blocks
16 Sectors for 64-Kbyte blocks
64-Kbyte
...
4-Kbyte
4-Kbyte
4-Kbyte
4-Kbyte
64-Kbyte
32-Kbyte
8-Kbyte
8-Kbyte
8-Kbyte
8-Kbyte
Bottom of Memory Block
2014-2022 Microchip Technology Inc. and its subsidiaries
DS20005262G-page 5
SST26VF016B
4.0
DEVICE OPERATION
The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data I/O
(SIO[3:0]) is sampled at the rising edge of the SCK
clock signal for input and driven after the falling edge of
the SCK clock signal for output. The traditional SPI protocol uses separate input (SI) and output (SO) data signals as shown in Figure 4-1. The SQI protocol uses
four multiplexed signals, SIO[3:0], for both data in and
data out, as shown in Figure 4-2. This means the SQI
protocol quadruples the traditional bus transfer speed
at the same clock frequency, without the need for more
pins on the package.
SST26VF016B supports both Serial Peripheral Interface (SPI) bus protocol and a 4-bit multiplexed SQI bus
protocol. To provide backward compatibility to traditional SPI Serial Flash devices, the device’s initial state
after a Power-on Reset is SPI mode which supports
multi-I/O (x1/x2/x4) Read/Write commands. A command instruction configures the device to SQI mode.
The dataflow in the SQI mode is similar to the SPI
mode, except it uses four multiplexed I/O signals for
command, address and data sequence.
SQI Flash Memory supports both Mode 0 (0,0) and
Mode 3 (1,1) bus operations. The difference between
the two modes is the state of the SCK signal when the
bus host is in standby mode and no data are being
transferred.
FIGURE 4-1:
SPI PROTOCOL (TRADITIONAL 25 SERIES SPI DEVICE)
CE#
SCK
MODE 3
MODE 3
MODE 0
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SI
MSb
SO
High-Impedance
Don't Care
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSb
FIGURE 4-2:
SQI SERIAL QUAD I/O PROTOCOL
CE#
MODE 3
MODE 3
CLK
MODE 0
SIO[3:0]
MODE 0
C1 C0
A5
A4
A3
A2
A1
A0
H0
L0
H1
L1
H2
L2
H3
L3
MSb
4.1
Device Protection
SST26VF016B offers a flexible memory protection
scheme that allows the protection state of each individual block to be controlled separately. In addition, the
Write Protection Lock-Down register prevents any
change of the lock status during device operation. To
avoid inadvertent writes during power-up, the device is
write-protected by default after a Power-on Reset
cycle. A Global Block Protection Unlock command
offers a single command cycle that unlocks the entire
memory array for faster manufacturing throughput.
DS20005262G-page 6
For extra protection, there is an additional nonvolatile
register that can permanently write-protect the Block
Protection register bits for each individual block.
Each of the corresponding lock-down bits are
One-Time-Programmable (OTP) — once written, they
cannot be erased. Data that had been previously programmed into these blocks cannot be altered by programming or erase and are not reversible.
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
4.1.1
INDIVIDUAL BLOCK PROTECTION
SST26VF016B has a Block Protection register which
provides a software mechanism to write-lock the individual memory blocks and write-lock and/or read-lock
the individual parameter blocks. The Block Protection
register is 48-bit wide: two bits each for the eight
8-Kbyte parameter blocks (write-lock and read-lock),
and one bit each for the remaining 32-Kbyte and
64-Kbyte overlay blocks (write-lock). See Table 5-6 for
address range protected per register bit.
Each bit in the Block Protection register (BPR) can be
written to a ‘1’ (protected) or ‘0’ (unprotected). For the
parameter blocks, the Most Significant bit is for
read-lock and the Least Significant bit is for write-lock.
Read-locking the parameter blocks provides additional
security for sensitive data after retrieval (e.g., after initial boot). If a block is read-locked, all reads to the block
return data 00H.
The Write Block Protection Register command is a
two-cycle command which requires that Write Enable
(WREN) is executed prior to the Write Block Protection
Register command. The Global Block Protection
Unlock command clears all write protection bits in the
Block Protection register.
4.1.2
WRITE PROTECTION LOCK-DOWN
(VOLATILE)
To prevent changes to the Block Protection register,
use the Lock-Down Block Protection Register (LBPR)
command to enable Write Protection Lock-Down. Once
Write Protection Lock-Down is enabled, the Block
Protection register cannot be changed. To avoid
inadvertent lock-down, the WREN command must be
executed prior to the LBPR command.
To reset Write Protection Lock-Down, performing a power
cycle on the device is required. The Write Protection
Lock-Down status may be read from the STATUS register.
4.1.3
WRITE-LOCK LOCK-DOWN
(NONVOLATILE)
The nonvolatile Write-Lock Lock-Down register is an
alternate register that permanently prevents changes
to the block-protect bits. The nonvolatile Write-Lock
Lock-Down register (nVWLDR) is 40-bit wide per
device: one bit each for the eight 8-Kbyte parameter
blocks and one bit each for the remaining 32-Kbyte and
64-Kbyte overlay blocks. See Table 5-6 for address
range protected per register bit.
Subsequent writes to the nVWLDR can only alter
available locations that have not been previously
written to a ‘1’. This method provides write protection
for the corresponding memory-array block by
protecting it from future program or erase operations.
Writing a ‘0’ in any location in the nVWLDR has no
effect on either the nVWLDR or the corresponding
Write-Lock bit in the BPR.
Note that if the Block Protection register had been
previously locked down (see Section 4.1.2 “Write
Protection Lock-Down (Volatile)”), the device must
be power cycled before using the nVWLDR. If the Block
Protection register is locked down and the Write
nVWLDR command is accessed, the command will be
ignored.
4.2
Hardware Write Protection
The hardware Write Protection pin (WP#) is used in
conjunction with the WPEN and IOC bits in the
Configuration register to prohibit write operations to the
Block Protection and Configuration registers. The WP#
pin function only works in SPI single-bit and dual-bit read
mode when the IOC bit in the Configuration register is
set to ‘0’.
The WP# pin function is disabled when the WPEN bit
in the Configuration register is ‘0’. This allows
installation of SST26VF016B in a system with a
grounded WP# pin while still enabling Write to the
Block Protection register. The Lock-Down function of
the Block Protection register supersedes the WP# pin.
See Table 4-1 for Write Protection Lock-Down states.
The factory default setting at power-up of the WPEN bit
is ‘0’, disabling the Write-Protect function of the WP#
after power-up. WPEN is a nonvolatile bit; once the bit
is set to ‘1’, the Write-Protect function of the WP# pin
continues to be enabled after power-up. The WP# pin
only protects the Block Protection register and Configuration register from changes. Therefore, if the WP#
pin is set to low before or after a Program or Erase
command or while an internal Write is in progress, it will
have no effect on the Write command.
The IOC bit takes priority over the WPEN bit in the
Configuration register. When the IOC bit is ‘1’, the
function of the WP# pin is disabled and the WPEN bit
serves no function. When the IOC bit is ‘0’ and WPEN
is ‘1’, setting the WP# pin active-low prohibits Write
operations to the Block Protection Register.
Writing ‘1’ to any or all of the nVWLDR bits disables the
change mechanism for the corresponding Write-Lock
bit in the BPR and permanently sets this bit to a ‘1’
(protected) state. After this change, both bits will be set
to ‘1’, regardless of the data entered in subsequent
writes to either the nVWLDR or the BPR.
2014-2022 Microchip Technology Inc. and its subsidiaries
DS20005262G-page 7
SST26VF016B
TABLE 4-1:
WRITE PROTECTION LOCK-DOWN STATES
Execute WBPR Instruction
WP#
IOC
WPEN
WPLD
L
0
1
1
Not Allowed
Protected
Not Allowed
Writable
0
1
0
Not Allowed
Protected
Allowed
Writable
1
Not Allowed
Writable
L
0
L
L
0
H
(1)
(2)
0
0
H
X
0
X
X
1
X
Note 1:
2:
4.3
0
X
0(2)
1
1
0
0
1
0
Allowed
Writable
Not Allowed
Writable
Allowed
Writable
Default at power-up register settings.
Factory default setting is ‘0’. This is a nonvolatile bit; default at power-up is the value set prior to
power-down.
Security ID
SST26VF016B offers a 2-Kbyte Security ID (Sec ID)
feature. The Security ID space is divided into two parts:
one factory-programmed, 64-bit segment and one
user-programmable segment.
The factory-programmed segment is programmed
during part manufacture with a unique number and
cannot be changed. The user-programmable segment
is left unprogrammed for the customer to program as
desired.
Use the Program Security ID (PSID) command to program the Security ID using the address shown in
Table 5-5. The Security ID can be locked using the
Lockout Security ID (LSID) command. This prevents
any future write operations to the Security ID.
The factory-programmed portion of the Security ID
cannot be programmed by the user; neither the
factory-programmed nor user-programmable areas
can be erased.
4.4
Configuration Register
Hold Operation
The HOLD# pin pauses active serial sequences without resetting the clocking sequence. This pin is active
after every power up and only operates during SPI
single-bit and dual-bit modes.
FIGURE 4-3:
SST26VF016B ships with the IOC bit set to ‘0’ and the
HOLD# pin function enabled. The HOLD# pin is always
disabled in SQI mode and only works in SPI single-bit
and dual-bit read mode.
To activate the Hold mode, CE# must be in active-low
state. The Hold mode begins when the SCK active-low
state coincides with the falling edge of the HOLD#
signal. The Hold mode ends when the HOLD# signal’s
rising edge coincides with the SCK active-low state.
If the falling edge of the HOLD# signal does not coincide with the SCK active-low state, then the device
enters Hold mode when the SCK next reaches the
active-low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK
active-low state, then the device exits Hold mode when
the SCK next reaches the active-low state (see
Figure 4-3).
Once the device enters Hold mode, SO will be in high
impedance state while SI and SCK can be VIL or VIH.
If CE# is driven active-high during a Hold condition, it
resets the internal logic of the device. As long as
HOLD# signal is low, the memory remains in the Hold
condition. To resume communication with the device,
HOLD# must be driven active-high, and CE# must be
driven active-low.
HOLD CONDITION WAVEFORM
SCK
HOLD#
Active
DS20005262G-page 8
Hold
Active
Hold
Active
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
4.5
STATUS Register
The STATUS register is a read-only register that provides the following status information: whether the
Flash memory array is available for any Read or Write
operation, if the device is write-enabled, whether an
erase or program operation is suspended and if the
Block Protection register and/or Security ID are locked
down. During an internal Erase or Program operation,
the STATUS register may be read to determine the
completion of an operation in progress. Table 4-2
describes the function of each bit in the STATUS register.
TABLE 4-2:
STATUS REGISTER
Bit
Name
0
BUSY
1
WEL
2
WSE
3
WSP
4
WPLD
5
SEC(1)
6
RES
7
BUSY
Note 1:
Function
Write operation status
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
Write Enable Latch status
1 = Device is write-enabled
0 = Device is not write-enabled
Write Suspend Erase status
1 = Erase suspended
0 = Erase is not suspended
Write Suspend Program status
1 = Program suspended
0 = Program is not suspended
Write Protection Lock-Down status
1 = Write Protection Lock-Down enabled
0 = Write Protection Lock-Down disabled
Security ID status
1 = Security ID space locked
0 = Security ID space not locked
Reserved for future use
Write operation status
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
Default at
Power-up
Read/Write
(R/W)
0
R
0
R
0
R
0
R
0
R
0(1)
R
0
R
0
R
The Security ID status will always be ‘1’ at power-up after a successful execution of the Lockout Security
ID instruction, otherwise default at power-up is ‘0’.
2014-2022 Microchip Technology Inc. and its subsidiaries
DS20005262G-page 9
SST26VF016B
4.5.1
WRITE-ENABLE LATCH (WEL)
The Write Enable Latch (WEL) bit indicates the status
of the internal memory’s Write Enable Latch. If the WEL
bit is set to ‘1’, the device is write enabled. If the bit is
set to ‘0’ (reset), the device is not write enabled and
does not accept any memory Program or Erase, Protection Register Write or Lock-Down commands. The
Write Enable Latch bit is automatically reset under the
following conditions:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Power-up
Reset
Write Disable (WRDI) instruction
Page Program instruction completion
Sector Erase instruction completion
Block Erase instruction completion
Chip Erase instruction completion
Write Block Protection register instruction
Lock-Down Block Protection register instruction
Program Security ID instruction completion
Lockout Security ID instruction completion
Write Suspend instruction
SPI Quad Page program instruction completion
Write STATUS Register
4.5.2
WRITE SUSPEND ERASE STATUS
(WSE)
The Write Suspend Erase status (WSE) indicates when
an erase operation has been suspended. The WSE bit
is ‘1’ after the host issues a suspend command during
an erase operation. Once the suspended erase
resumes, the WSE bit is reset to ‘0’.
TABLE 4-3:
Name
0
RES
Reserved
1
IOC
2
RES
I/O Configuration for SPI Mode
1 = WP# and HOLD# pins disabled
0 = WP# and HOLD# pins enabled
3
BPNV
The Write Suspend Program status (WSP) bit indicates
when a program operation has been suspended. The
WSP is ‘1’ after the host issues a suspend command
during the Program operation. Once the suspended
Program resumes, the WSP bit is reset to ‘0’.
4.5.4
WRITE PROTECTION LOCK-DOWN
STATUS (WPLD)
The Write Protection Lock-Down status (WPLD) bit
indicates when the Block Protection register is locked
down to prevent changes to the protection settings.
The WPLD is ‘1’ after the host issues a Lock-Down
Block Protection command. After a power cycle, the
WPLD bit is reset to ‘0’.
4.5.5
SECURITY ID STATUS (SEC)
The Security ID Status (SEC) bit indicates when the
Security ID space is locked to prevent a write command. The SEC is ‘1’ after the host issues a Lockout
SID command. Once the host issues a Lockout SID
command, the SEC bit can never be reset to ‘0.’
4.5.6
BUSY
The Busy bit determines whether there is an internal
erase or program operation in progress. If the BUSY bit
is ‘1’, the device is busy with an internal erase or program operation. If the bit is ‘0’, no erase or program
operation is in progress.
4.6
Configuration Register
The Configuration register is a Read/Write register that
stores a variety of configuration information. See
Table 4-3 for the function of each bit in the register.
Function
Reserved
Block Protection Volatility State
1 = No memory block has been permanently locked
0 = Any block has been permanently locked
4
RES
5
RES
Reserved
RES
Reserved
6
WRITE SUSPEND PROGRAM
STATUS (WSP)
CONFIGURATION REGISTER
Bit
Note 1:
2:
4.5.3
Reserved
Default at
Power-up
Read/Write (R/W)
0
R
0(1)
R/W
0
R
1
R
0
0
0
R
R
R
Default at Power-up is ‘0’.
Factory default setting. This is a nonvolatile bit; default at power-up will be the setting prior to power-down.
DS20005262G-page 10
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
TABLE 4-3:
Bit
7
Note 1:
2:
4.6.1
CONFIGURATION REGISTER (CONTINUED)
Name
WPEN
Function
Write-Protection Pin (WP#) Enable
1 = WP# enabled
0 = WP# disabled
Read/Write (R/W)
0(2)
R/W
Default at Power-up is ‘0’.
Factory default setting. This is a nonvolatile bit; default at power-up will be the setting prior to power-down.
I/O CONFIGURATION (IOC)
The I/O Configuration (IOC) bit re-configures the I/O
pins. The IOC bit is set by writing a ‘1’ to Bit 1 of the
Configuration register. When IOC bit is ‘0’, the WP# pin
and HOLD# pin are enabled (SPI or Dual Configuration
setup). When IOC bit is set to ‘1’, the SIO2 pin and
SIO3 pin are enabled (SPI Quad I/O Configuration
setup). The IOC bit must be set to ‘1’ before issuing the
following SPI commands: SQOR (6BH), SQIOR (EBH),
RBSPI (ECH) and SPI Quad page program (32H).
Without setting the IOC bit to ‘1’, those SPI commands
are not valid. The I/O configuration bit does not apply
when in SQI mode. The default at power-up is ‘0’.
4.6.2
Default at
Power-up
BLOCK PROTECTION VOLATILITY
STATE (BPNV)
The Block Protection Volatility State bit indicates
whether any block has been permanently locked with
the Nonvolatile Write Lock Lock-Down register
(nVWLDR). When no bits in the nVWLDR have been
set, the BPNV is ‘1’; this is the default state from the
factory. When one or more bits in the nVWLDR are set
to ‘1’, the BPNV bit will be ‘0’ from that point forward,
even after power-up.
2014-2022 Microchip Technology Inc. and its subsidiaries
4.6.3
WRITE-PROTECT ENABLE (WPEN)
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that enables the WP# pin.
The Write-Protect (WP#) pin and the Write-Protect
Enable (WPEN) bit control the programmable
hardware write-protect feature. Setting the WP# pin to
low and the WPEN bit to ‘1’ enable hardware write
protection. To disable hardware write protection, set
either the WP# pin to high or the WPEN bit to ‘0’. There
is latency associated with writing to the WPEN bit. Poll
the BUSY bit in the STATUS register or wait TWPEN for
the completion of the internal, self-timed write
operation. When the chip is hardware write-protected,
only write operations to Block Protection and
Configuration registers are disabled. See Section 4.2
“Hardware Write Protection” and Table 4-1 for more
information about the functionality of the WPEN bit.
DS20005262G-page 11
SST26VF016B
5.0
INSTRUCTIONS
Instructions are used to read, write (erase and program) and configure the SST26VF016B. The complete
list of the instructions is provided in Table 5-1.
TABLE 5-1:
DEVICE OPERATION INSTRUCTIONS FOR SST26VF016B
Instruction
Description
Mode
Address
Dummy
Data
Command
(2,3) Cycle(s)(3) Cycle(s)(3)
Cycle(s)
Cycle(1)
SPI SQI
Max
Freq(4)
Configuration
No Operation
00H
X
X
0
0
0
Reset Enable
66H
X
X
0
0
0
Reset Memory
99H
X
X
0
0
0
Enable Quad I/O
38H
X
0
0
0
RSTQIO
Reset Quad I/O
FFH
X
0
0
0
RDSR
Read STATUS Register
05H
0
0
1 to ∞
X
0
1
1 to ∞
WRSR
Write STATUS Register
01H
X
0
0
2
RDCR
Read Configuration
Register
35H
0
0
1 to ∞
0
1
1 to ∞
Read Memory
03H
3
0
1 to ∞
NOP
RSTEN
(5)
RST
EQIO
(6)
X
X
X
X
X
104 MHz/
80 MHz
Read
READ
3
3
1 to ∞
X
3
1
1 to ∞
6BH
X
3
1
1 to ∞
EBH
X
3
3
1 to ∞
High-Speed Read Memory at
Read
Higher Speed
0BH
SQOR(7)
SPI Quad Output Read
SPI Quad I/O Read
SQIOR(8)
SDOR
(9)
SDIOR(10)
SB
RBSQI
RBSPI(8)
X
X
SPI Dual Output Read
3BH
X
3
1
1 to ∞
SPI Dual I/O Read
BBH
X
3
1
1 to ∞
X
X
0
0
1
X
3
3
n to ∞
3
3
n to ∞
Set Burst Length
C0H
SQI Read Burst with Wrap
0CH
SPI Read Burst with Wrap
ECH
X
40 MHz
104 MHz/
80 MHz
80 MHz
104 MHz/
80 MHz
Note 1:
2:
3:
Command cycle is two-clock periods in SQI mode and eight-clock periods in SPI mode.
Address bits above the Most Significant bit of each density can be VIL or VIH.
Address, Dummy/Mode bits and Data cycles are two-clock periods in SQI and eight-clock periods in SPI
mode.
4: The maximum frequency for all instructions is up to 104 MHz from 2.7V to 3.6V and up to 80 MHz from
2.3V to 3.6V unless otherwise noted. For extended temperature (+125°C), the maximum frequency is up
to 80 MHz.
5: RST command only executed if RSTEN command is executed first. Any intervening command will disable
Reset.
6: Device accepts eight-clock command in SPI mode or two-clock command in SQI mode.
7: Data cycles are two-clock periods. IOC bit must be set to ‘1’ before issuing the command.
8: Address, Dummy/Mode bits and data cycles are two-clock periods. IOC bit must be set to ‘1’ before issuing the command.
9: Data cycles are four-clock periods.
10: Address, Dummy/Mode bits and Data cycles are four-clock periods.
11: Sector Addresses: Use AMS-A12, remaining address are “don’t care”, but must be set to VIL or VIH.
12: Blocks are 64-Kbyte, 32-Kbyte or 8-Kbyte, depending on location. Block Erase Address: AMS-A16 for
64-Kbyte; AMS-A15 for 32-Kbyte; AMS-A13 for 8-Kbyte. Remaining addresses are “don’t care”, but must be
set to VIL or VIH.
DS20005262G-page 12
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
TABLE 5-1:
DEVICE OPERATION INSTRUCTIONS FOR SST26VF016B (CONTINUED)
Instruction
Description
Mode
Address
Dummy
Data
Command
(2,3) Cycle(s)(3) Cycle(s)(3)
Cycle(1)
SPI SQI Cycle(s)
Max
Freq(4)
Identification
JEDEC-ID
JEDEC-ID Read
9FH
X
0
0
3 to ∞
Quad J-ID
Quad I/O J-ID Read
AFH
SFDP
Serial Flash Discoverable
Parameters
0
1
3 to ∞
5AH
X
3
1
1 to ∞
WREN
Write Enable
06H
X
X
0
0
0
SE(11)
Write Disable
04H
Erase 4 Kbytes of Memory
Array
X
X
0
0
0
20H
X
X
3
0
0
Erase 64, 32 or 8 Kbytes of
Memory Array
D8H
X
X
3
0
0
CE
Erase Full Array
C7H
X
X
0
0
0
Page Program
02H
X
X
3
0
1 to 256
SPI Quad
PP(7)
SQI Quad Page Program
32H
X
3
0
1 to 256
WRSU
Suspends Program/Erase
B0H
X
X
0
0
0
Resumes Program/Erase
30H
X
X
0
0
0
X
104 MHz/
80 MHz
Write
WRDI
BE(12)
PP
WRRE
104 MHz/
80 MHz
104 MHz/
80 MHz
Note 1:
2:
3:
Command cycle is two-clock periods in SQI mode and eight-clock periods in SPI mode.
Address bits above the Most Significant bit of each density can be VIL or VIH.
Address, Dummy/Mode bits and Data cycles are two-clock periods in SQI and eight-clock periods in SPI
mode.
4: The maximum frequency for all instructions is up to 104 MHz from 2.7V to 3.6V and up to 80 MHz from
2.3V to 3.6V unless otherwise noted. For extended temperature (+125°C), the maximum frequency is up
to 80 MHz.
5: RST command only executed if RSTEN command is executed first. Any intervening command will disable
Reset.
6: Device accepts eight-clock command in SPI mode or two-clock command in SQI mode.
7: Data cycles are two-clock periods. IOC bit must be set to ‘1’ before issuing the command.
8: Address, Dummy/Mode bits and data cycles are two-clock periods. IOC bit must be set to ‘1’ before issuing the command.
9: Data cycles are four-clock periods.
10: Address, Dummy/Mode bits and Data cycles are four-clock periods.
11: Sector Addresses: Use AMS-A12, remaining address are “don’t care”, but must be set to VIL or VIH.
12: Blocks are 64-Kbyte, 32-Kbyte or 8-Kbyte, depending on location. Block Erase Address: AMS-A16 for
64-Kbyte; AMS-A15 for 32-Kbyte; AMS-A13 for 8-Kbyte. Remaining addresses are “don’t care”, but must be
set to VIL or VIH.
2014-2022 Microchip Technology Inc. and its subsidiaries
DS20005262G-page 13
SST26VF016B
TABLE 5-1:
DEVICE OPERATION INSTRUCTIONS FOR SST26VF016B (CONTINUED)
Instruction
Description
Mode
Address
Dummy
Data
Command
(2,3) Cycle(s)(3) Cycle(s)(3)
Cycle(1)
SPI SQI Cycle(s)
Max
Freq(4)
Protection
0
0
1 to 6
X
0
1
1 to 6
X
X
0
0
1 to 6
8DH
X
X
0
0
0
Nonvolatile Write
Lock-Down Register
E8H
X
X
0
0
1 to 6
ULBPR
Global Block Protection
Unlock
98H
X
X
0
0
0
RSID
Read Security ID
88H
2
1
1 to 2048
X
2
3
1 to 2048
PSID
Program User
Security ID area
A5H
X
X
2
0
1 to 256
LSID
Lockout Security ID
Programming
85H
X
X
0
0
0
Deep Power-Down Mode
B9H
X
X
0
0
0
Release from Deep
Power-Down and Read ID
ABH
X
X
3
0
1 to ∞
RBPR
Read Block Protection
Register
72H
WBPR
Write Block Protection
Register
42H
LBPR
Lock Down Block
Protection Register
nVWLDR
X
X
104 MHz/
80 MHz
Power Saving
DPD
RDPD
104 MHz/
80 MHz
Note 1:
2:
3:
Command cycle is two-clock periods in SQI mode and eight-clock periods in SPI mode.
Address bits above the Most Significant bit of each density can be VIL or VIH.
Address, Dummy/Mode bits and Data cycles are two-clock periods in SQI and eight-clock periods in SPI
mode.
4: The maximum frequency for all instructions is up to 104 MHz from 2.7V to 3.6V and up to 80 MHz from
2.3V to 3.6V unless otherwise noted. For extended temperature (+125°C), the maximum frequency is up
to 80 MHz.
5: RST command only executed if RSTEN command is executed first. Any intervening command will disable
Reset.
6: Device accepts eight-clock command in SPI mode or two-clock command in SQI mode.
7: Data cycles are two-clock periods. IOC bit must be set to ‘1’ before issuing the command.
8: Address, Dummy/Mode bits and data cycles are two-clock periods. IOC bit must be set to ‘1’ before issuing the command.
9: Data cycles are four-clock periods.
10: Address, Dummy/Mode bits and Data cycles are four-clock periods.
11: Sector Addresses: Use AMS-A12, remaining address are “don’t care”, but must be set to VIL or VIH.
12: Blocks are 64-Kbyte, 32-Kbyte or 8-Kbyte, depending on location. Block Erase Address: AMS-A16 for
64-Kbyte; AMS-A15 for 32-Kbyte; AMS-A13 for 8-Kbyte. Remaining addresses are “don’t care”, but must be
set to VIL or VIH.
DS20005262G-page 14
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
5.1
No Operation (NOP)
The Reset operation requires the Reset Enable command followed by the Reset command. Any command
other than the Reset command after the Reset Enable
command will disable the Reset Enable.
The No Operation command only cancels a Reset
Enable command. NOP has no impact on any other
command.
5.2
Once the Reset Enable and Reset commands are successfully executed, the device returns to normal operation Read mode and then does the following: resets the
protocol to SPI mode, resets the burst length to
8 bytes, clears all the bits, except for bit 4 (WPLD) and
bit 5 (SEC) in the STATUS register to their default
states, and clears bit 1 (IOC) in the Configuration register to its default state. A device Reset during an active
program or erase operation aborts the operation, which
can cause the data of the targeted address range to be
corrupted or lost. Depending on the prior operation, the
Reset timing may vary. Recovery from a write operation
requires more latency time than recovery from other
operations. See Table 8-2 for Rest timing parameters.
Reset Enable (RSTEN) and Reset
(RST)
The Reset operation is used as a system (software)
reset that puts the device in normal operating Ready
mode. This operation consists of two commands:
Reset Enable (RSTEN) followed by Reset (RST).
To reset SST26VF016B, the host drives CE# low,
sends the Reset Enable command (66H) and drives
CE# high. Next, the host drives CE# low again, sends
the Reset command (99H) and drives CE# high (see
Figure 5-1).
FIGURE 5-1:
RESET SEQUENCE
Tඋඐ
CE#
MODE 3
MODE 3
MODE 3
MODE 0
MODE 0
MODE 0
CLK
SIO[3:0]
Note:
5.3
C1 C0
C3 C2
C[1:0] = 66H; C[3:2] = 99H
Read (40 MHz)
The internal Address Pointer will automatically increment until the highest memory address is reached.
Once the highest memory address is reached, the
Address Pointer will automatically return to the beginning (wrap-around) of the address space.
The READ instruction, 03H, is supported in SPI bus protocol only with clock frequencies up to 40 MHz. This
command is not supported in SQI bus protocol. The
device outputs the data starting from the specified
address location, then continuously streams the data
output through all addresses until terminated by a
low-to-high transition on CE#.
FIGURE 5-2:
Initiate the READ instruction by executing an 8-bit command, 03H, followed by address bits A[23:0]. CE# must
remain active-low for the duration of the Read cycle.
See Figure 5-2 for Read Sequence.
READ SEQUENCE (SPI)
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
03
SI
MSb
SO
15 16
23 24
31 32
39 40
47 48
55 56
63 64
70
MODE 0
ADD.
MSb
High-Impedance
ADD.
ADD.
N
DOUT
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSb
2014-2022 Microchip Technology Inc. and its subsidiaries
DS20005262G-page 15
SST26VF016B
5.4
Enable Quad I/O (EQIO)
The Enable Quad I/O (EQIO) instruction, 38H, enables
the Flash device for SQI bus operation. Upon completion of the instruction, all instructions thereafter are
expected to be 4-bit multiplexed input/output (SQI
mode) until a power cycle or a “Reset Quad I/O instruction” is executed (see Figure 5-3).
FIGURE 5-3:
ENABLE QUAD I/O SEQUENCE
CE#
MODE 3
SCK
0
2
1
3
4
5
6
7
MODE 0
SIO0
38
SIO[3:1]
Note:
5.5
SIO[3:1] must be driven VIH.
Reset Quad I/O (RSTQIO)
To execute a Reset Quad I/O operation, the host drives
CE# low, sends the Reset Quad I/O command cycle
(FFH), then drives CE# high. Execute the instruction in
either SPI (8 clocks) or SQI (2 clocks) command
cycles. For SPI, SIO[3:1] are “don’t care” for this command, but should be driven to VIH or VIL (see Figure 5-4
and Figure 5-5).
The Reset Quad I/O instruction, FFH, resets the device
to 1-bit SPI protocol operation or exits the Set Mode
configuration during a read sequence. This command
allows the Flash device to return to the default I/O state
(SPI) without a power cycle and executes in either 1-bit
or 4-bit mode. If the device is in the Set Mode configuration, while in SQI High-Speed Read mode, the
RSTQIO command will only return the device to a state
where it can accept new command instruction. An additional RSTQIO is required to reset the device to SPI
mode.
FIGURE 5-4:
RESET QUAD I/O SEQUENCE (SPI)
CE#
MODE 3
SCK
0
1
2
3
4
5
6
7
MODE 0
SIO0
FF
SIO[3:1]
Note:
SIO[3:1] must be driven VIH.
DS20005262G-page 16
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
FIGURE 5-5:
RESET QUAD I/O SEQUENCE (SQI)
CE#
MODE 3
SCK
High-Speed Read
The High-Speed Read instruction, 0BH, is supported in
both SPI bus protocol and SQI protocol. This
instruction supports frequencies of up to 80 MHz or
104 MHz with additional dummy input cycles prior to
first data byte output. On power-up, the device is set to
use SPI.
FIGURE 5-6:
1
F
F
MODE 0
SIO[3:0]
5.6
0
Initiate High-Speed Read by executing an 8-bit command, 0BH, followed by address bits A[23-0] and a
dummy byte. CE# must remain active-low for the duration of the High-Speed Read cycle. See Figure 5-6 for
the High-Speed Read sequence for SPI bus protocol.
HIGH-SPEED READ SEQUENCE (SPI) (C[1:0] = 0BH)
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
SCK MODE 0
SI/SIO0
SO/SIO1
0B
ADD.
ADD.
High-Impedance
In SQI protocol, the host drives CE# low then sends
one High-Speed Read command cycle, 0BH, followed
by three address cycles, a Set Mode Configuration
cycle and two dummy cycles. Each cycle is two nibbles
(clocks) long, most significant nibble first.
After the dummy cycles, the device outputs data on the
falling edge of the SCK signal starting from the specified address location. The device continually streams
data output through all addresses until terminated by a
low-to-high transition on CE#. The internal Address
Pointer automatically increments until the highest
memory address is reached, at which point the
Address Pointer returns to address location 000000H.
During this operation, blocks that are Read-locked will
output data 00H.
The Set Mode Configuration bit M[7:0] indicates if the
next instruction cycle is another SQI High-Speed Read
command. When M[7:0] = AXH, the device expects the
next continuous instruction to be another Read command, 0BH, and does not require the op-code to be
entered again.
2014-2022 Microchip Technology Inc. and its subsidiaries
ADD.
X
N
DOUT
MSb
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
The host may initiate the next Read cycle by driving
CE# low, then sending the four-bit input for address
A[23:0], followed by the Set Mode configuration bits
M[7:0] and two dummy cycles. After the two dummy
cycles, the device outputs the data starting from the
specified address location. There are no restrictions on
address location access.
When M[7:0] is any value other than AXH, the device
expects the next instruction initiated to be a command
instruction. To reset/exit the Set Mode configuration,
execute the Reset Quad I/O command, FFH. While in
the Set Mode configuration, the RSTQIO command will
only return the device to a state where it can accept
new command instruction. An additional RSTQIO is
required to reset the device to SPI mode. See
Figure 5-10 for the SPI Quad I/O Mode Read sequence
when M[7:0] = AXH.
DS20005262G-page 17
SST26VF016B
FIGURE 5-7:
HIGH-SPEED READ SEQUENCE (SQI)
CE#
0
1
MODE 0 MSN
LSN
C0
C1
MODE 3
2
3
4
5
6
7
8
9
A5
A4
A3
A2
A1
A0
M1
M0
10
11
12
13
14
15
20
21
SCK
SIO[3:0]
Command
Note:
5.7
X
X
Mode
Address
X
X
Dummy
H0
L0
Data Byte 0
H8
L8
Data Byte 7
MSN= Most Significant Nibble, LSN = Least Significant Nibble
Hx = High Data Nibble, Lx = Low Data Nibble C[1:0] = 0BH
SPI Quad Output Read
Following the dummy byte, the device outputs data
from SIO[3:0] starting from the specified address location. The device continually streams data output
through all addresses until terminated by a low-to-high
transition on CE#. The internal Address Pointer automatically increments until the highest memory address
is reached, at which point the Address Pointer returns
to the beginning of the address space.
The SPI Quad Output Read instruction supports frequencies of up to 80 MHz or 104 MHz with additional
dummy input cycles prior to first data byte output.
SST26VF016B requires the IOC bit in the Configuration register to be set to ‘1’ prior to executing the command. Initiate SPI Quad Output Read by executing an
8-bit command, 6BH, followed by address bits A[23-0]
and a dummy byte. CE# must remain active-low for the
duration of the SPI Quad Mode Read. See Figure 5-8
for the SPI Quad Output Read sequence.
FIGURE 5-8:
SPI QUAD OUTPUT READ
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40 41
MODE 0
6BH
SIO0
OP Code
A[23:16]
A[15:8]
A[7:0]
Address
X
b4 b0
b4 b0
Dummy
Data
Byte 0
Data
Byte N
SIO1
b5 b1
b5 b1
SIO2
b6 b2
b6 b2
SIO3
b7 b3
b7 b3
Note:
MSN= Most Significant Nibble, LSN = Least Significant Nibble
DS20005262G-page 18
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
5.8
SPI Quad I/O Read
The SPI Quad I/O Read (SQIOR) instruction supports
frequencies of up to 80 MHz or 104 MHz with additional
dummy input cycles prior to first data byte output.
SST26VF016B requires the IOC bit in the Configuration register to be set to ‘1’ prior to executing the command. Initiate SQIOR by executing an 8-bit command,
EBH. The device then switches to 4-bit I/O mode for
address bits A[23-0], followed by the Set Mode configuration bits M[7:0] and two dummy bytes. CE# must
remain active-low for the duration of the SPI Quad I/O
Read. See Figure 5-9 for the SPI Quad I/O Read
sequence.
The Set Mode Configuration bit M[7:0] indicates if the
next instruction cycle is another SPI Quad I/O Read
command. When M[7:0] = AXH, the device expects the
next continuous instruction to be another Read command (EBH) and does not require the op-code to be
entered again. The host may set the next SQIOR cycle
by driving CE# low, then sending the four-bit wide input
for address A[23:0], followed by the Set Mode configuration bits M[7:0] and two dummy cycles. After the two
dummy cycles, the device outputs the data starting
from the specified address location. There are no
restrictions on address location access.
Following the dummy bytes, the device outputs data
from the specified address location. The device continually streams data output through all addresses until
terminated by a low-to-high transition on CE#. The
internal Address Pointer automatically increments until
the highest memory address is reached, at which point
the Address Pointer returns to the beginning of the
address space.
When M[7:0] is any value other than AXH, the device
expects the next instruction initiated to be a command
instruction. To reset/exit the Set Mode configuration,
execute the Reset Quad I/O command (FFH). See
Figure 5-10 for the SPI Quad I/O Mode Read sequence
when M[7:0] = AXH.
FIGURE 5-9:
SPI QUAD I/O READ SEQUENCE
CE#
MODE 3
SCK
SIO0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
MODE 0
EBH
A20 A16 A12 A8 A4 A0 M4 M0 X X X X b4 b0 b4 b0
SIO1
A21 A17 A13 A9 A5 A1 M5 M1 X X X X b5 b1 b5 b1
SIO2
A22 A18 A14 A10 A6 A2 M6 M2 X X X X b6 b2 b6 b2
MSN LSN
A23 A19 A15 A11 A7 A3 M7 M3 X X X X b7 b3 b7 b3
SIO3
Address
Note:
Set
Mode
Dummy
Data Data
Byte 0 Byte 1
MSN= Most Significant Nibble, LSN = Least Significant Nibble
2014-2022 Microchip Technology Inc. and its subsidiaries
DS20005262G-page 19
SST26VF016B
FIGURE 5-10:
BACK-TO-BACK SPI QUAD I/O READ SEQUENCES WHEN M[7:0] = AXH
CE#
0 1 2 3 4 5 6 7 8 9 10 11 12 13
SCK
SIO0
b4 b0 b4 b0
A20 A16 A12 A8 A4 A0 M4 M0 X X X X b4 b0
SIO1
b5 b1 b5 b1
A21 A17 A13 A9 A5 A1 M5 M1 X X X X b5 b1
SIO2
b6 b2 b6 b2
A22 A18 A14 A10 A6 A2 M6 M2 X X X X b6 b2
MSN LSN
b7 b3 b7 b3
SIO3
A23 A19 A15 A11 A7 A3 M7 M3 X X X X b7 b3
Data Data
Byte Byte
N+1
N
Note:
5.9
Set
Mode
Address
Dummy
Data
Byte 0
MSN= Most Significant Nibble, LSN = Least Significant Nibble
Set Burst
After power-up or Reset, the burst length is set to eight
bytes (00H). See Table 5-2 for burst length data and
Figures 5-11 and 5-12 for the sequences.
The Set Burst command specifies the number of bytes
to be output during a Read Burst command before the
device wraps around. It supports both SPI and SQI protocols. To set the burst length, the host drives CE# low,
sends the Set Burst command cycle (C0H) and one
data cycle, then drives CE# high.
TABLE 5-2:
BURST LENGTH DATA
Burst Length
High Nibble (H0)
Low Nibble (L0)
8 Bytes
0h
0h
16 Bytes
0h
1h
32 Bytes
0h
2h
64 Bytes
0h
3h
FIGURE 5-11:
SET BURST LENGTH SEQUENCE (SQI)
CE#
MODE 3
SCK
SIO[3:0]
0
1
2
3
MODE 0
C1 C0 H0 L0
MSN LSN
Note:
MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = C0H
DS20005262G-page 20
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
FIGURE 5-12:
SET BURST LENGTH SEQUENCE (SPI)
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MODE 0
SIO0
C0
DIN
SIO[3:1]
Note:
5.10
SIO[3:1] must be driven VIH.
SQI Read Burst with Wrap (RBSQI)
SQI Read Burst with wrap is similar to High-Speed
Read in SQI mode, except data will output continuously
within the burst length until a low-to-high transition on
CE#. To execute a SQI Read Burst operation, drive
CE# low, then send the Read Burst command cycle
(0CH), followed by three address cycles and then three
dummy cycles. Each cycle is two nibbles (clocks) long,
most significant nibble first.
After the dummy cycles, the device outputs data on the
falling edge of the SCK signal starting from the specified address location. The data output stream is continuous through all addresses until terminated by a
low-to-high transition on CE#.
During RBSQI, the internal Address Pointer automatically increments until the last byte of the burst is
reached, then it wraps around to the first byte of the
burst. All bursts are aligned to addresses within the
burst length (see Table 5-3). For example, if the burst
length is eight bytes and the start address is 06h, the
burst sequence would be: 06h, 07h, 00h, 01h, 02h,
03h, 04h, 05h, 06h, etc. The pattern repeats until the
command is terminated by a low-to-high transition on
CE#.
During this operation, blocks that are read-locked will
output data 00H.
TABLE 5-3:
5.11
SPI Read Burst with Wrap (RBSPI)
SPI Read Burst with Wrap (RBSPI) is similar to SPI
Quad I/O Read except the data will output continuously
within the burst length until a low-to-high transition on
CE#. To execute a SPI Read Burst with Wrap operation, drive CE# low, then send the Read Burst command cycle (ECH), followed by three address cycles
and then three dummy cycles.
After the dummy cycle, the device outputs data on the
falling edge of the SCK signal starting from the specified address location. The data output stream is continuous through all addresses until terminated by a
low-to-high transition on CE#.
During RBSPI, the internal Address Pointer automatically increments until the last byte of the burst is
reached, then it wraps around to the first byte of the
burst. All bursts are aligned to addresses within the
burst length (see Table 5-3). For example, if the burst
length is eight bytes and the start address is 06h, the
burst sequence would be: 06h, 07h, 00h, 01h, 02h,
03h, 04h, 05h, 06h, etc. The pattern repeats until the
command is terminated by a low-to-high transition on
CE#.
During this operation, blocks that are read-locked will
output data 00H.
BURST ADDRESS RANGES
Burst Length
Burst Address Ranges
8 Bytes
00-07H, 08-0FH, 10-17H, 18-1FH...
16 Bytes
00-0FH, 10-1FH, 20-2FH, 30-3FH...
32 Bytes
00-1FH, 20-3FH, 40-5FH, 60-7FH...
64 Bytes
00-3FH, 40-7FH, 80-BFH, C0-FFH
2014-2022 Microchip Technology Inc. and its subsidiaries
DS20005262G-page 21
SST26VF016B
5.12
SPI Dual Output Read
Following the dummy byte, SST26VF016B outputs
data from SIO[1:0] starting from the specified address
location. The device continually streams data output
through all addresses until terminated by a low-to-high
transition on CE#. The internal Address Pointer automatically increments until the highest memory address
is reached, at which point the Address Pointer returns
to the beginning of the address space.
The SPI Dual Output Read instruction supports frequencies of up to 80 MHz or 104 MHz with additional
dummy input cycles prior to first data byte output. Initiate SPI Dual Output Read by executing an 8-bit command (3BH), followed by address bits A[23-0] and a
dummy byte. CE# must remain active-low for the duration of the SPI Dual Output Read operation. See
Figure 5-13 for the SPI Quad Output Read sequence.
FIGURE 5-13:
FAST READ, DUAL OUTPUT SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
3BH
SIO0
A[23:16]
A[15:8]
SIO1
OP Code
Note:
5.13
39 40 41
31 32
MODE 0
Address
A[7:0]
b6 b5 b3 b1
b6 b5 b3 b1
MSb
b7 b4 b2 b0
b7 b4 b2 b0
X
Dummy
Data
Byte 0
Data
Byte N
MSb = Most Significant bit
SPI Dual I/O Read
The SPI Dual I/O Read (SDIOR) instruction supports up
to 80 MHz frequency. Initiate SDIOR by executing an
8-bit command (BBH). The device then switches to
2-bit I/O mode for address bits A[23-0], followed by the
Set Mode configuration bits M[7:0]. CE# must remain
active-low for the duration of the SPI Dual I/O Read.
See Figure 5-14 for the SPI Dual I/O Read sequence.
When M[7:0] is any value other than AXH, the device
expects the next instruction initiated to be a command
instruction. To reset/exit the Set Mode configuration,
execute the Reset Quad I/O command (FFH). See
Figure 5-15 for the SPI Dual I/O Read sequence when
M[7:0] = AXH.
Following the Set Mode configuration bits, the
SST26VF016B outputs data from the specified address
location. The device continually streams data output
through all addresses until terminated by a low-to-high
transition on CE#. The internal Address Pointer automatically increments until the highest memory address
is reached, at which point the Address Pointer returns
to the beginning of the address space.
The Set Mode Configuration bit M[7:0] indicates if the
next instruction cycle is another SPI Dual I/O Read
command. When M[7:0] = AXH, the device expects the
next continuous instruction to be another SDIOR command (BBH) and does not require the op-code to be
entered again. The host may set the next SDIOR cycle
by driving CE# low, then sending the two-bit wide input
for address A[23:0], followed by the Set Mode configuration bits M[7:0]. After the Set Mode Configuration bits,
the device outputs the data starting from the specified
address location. There are no restrictions on address
location access.
DS20005262G-page 22
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
FIGURE 5-14:
SPI DUAL I/O READ SEQUENCE
CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
MODE 0
SCK
SIO0
6 4 2 0 6 4 2 0 6 4 2 0 6 4
BBH
SIO1
7 5 3 1 7 5 3 1 7 5 3 1 7 5
A[23:16]
A[7:0]
A[15:8]
M[7:0]
CE#(cont’)
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK(cont’)
I/O Switches from Input to Output
SIO0(cont’)
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
MSb
SIO1(cont’)
Byte 0
Note:
MSb
MSb
MSb
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte 2
Byte 1
Byte 3
MSb= Most Significant bit, LSb = Least Significant bit
FIGURE 5-15:
BACK-TO-BACK SPI DUAL I/O READ SEQUENCES WHEN M[7:0] = AXH
CE#
MODE 3
0 1 2
3 4 5 6 7 8 9 10 11 12 13 14 15
MODE 0
SCK
I/O Switch
SIO0 6 4
MSb
SIO1 7 5
6 4 2 0 6 4 2 0 6 4 2 0 6 4
6 4 2 0
MSb
7 5 3 1 7 5 3 1 7 5 3 1 7 5
7 5 3 1
A[23:16]
A[15:8]
A[7:0]
M[7:0]
CE#(cont’)
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK(cont’)
I/O Switches from Input to Output
SIO0(cont’)
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
MSb
SIO1(cont’)
Byte 0
Note:
MSb
MSb
MSb
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte 1
Byte 2
Byte 3
MSb = Most Significant bit, LSb = Least Significant bit
2014-2022 Microchip Technology Inc. and its subsidiaries
DS20005262G-page 23
SST26VF016B
5.14
JEDEC ID Read (SPI Protocol)
Immediately
following
the
command
cycle,
SST26VF016B output data on the falling edge of the
SCK signal. The data output stream is continuous until
terminated by a low-to-high transition on CE#. The
device outputs three bytes of data: manufacturer,
device type and device ID (see Table 5-4). See
Figure 5-16 for instruction sequence.
Using traditional SPI protocol, the JEDEC ID Read
instruction identifies the device as SST26VF016B and
the manufacturer as Microchip®. To execute a JECEC
ID operation, the host drives CE# low, then sends the
JEDEC ID command cycle (9FH).
TABLE 5-4:
DEVICE ID DATA OUTPUT
Product
Manufacturer ID (Byte 1)
SST26VF016B
BFH
FIGURE 5-16:
Device ID
Device Type (Byte 2)
Device ID (Byte 3)
26H
41H
JEDEC ID SEQUENCE (SPI)
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
MODE 0
SI
9F
High-Impedance
SO
26
BF
MSb
5.15
Read Quad J-ID Read (SQI
Protocol)
Immediately following the command cycle and one
dummy cycle, SST26VF016B outputs data on the falling edge of the SCK signal. The data output stream is
continuous until terminated by a low-to-high transition
of CE#. The device outputs three bytes of data: manufacturer, device type and device ID (see Table 5-4).
See Figure 5-17 for instruction sequence.
The Read Quad J-ID Read instruction identifies the
device as SST26VF016B and manufacturer as Microchip. To execute a Quad J-ID operation, the host drives
CE# low and then sends the Quad J-ID command cycle
(AFH). Each cycle is two nibbles (clocks) long, most
significant nibble first.
FIGURE 5-17:
Device ID
MSb
QUAD J-ID READ SEQUENCE
CE#
0
1
2
C0
C1
X
MODE 3
3
4
5
MSN
LSN
H0
L0
6
7
8
9
H2
L2
10
11
12
13
N
SCK
MODE 0
SIO[3:0]
X
Dummy
Note:
BFH
H1
L1
26H
Device ID
H0
L0
BFH
H1
L1
26H
HN
LN
N
MSN = Most significant Nibble; LSN= Least Significant Nibble, C{1:0] = AFH
DS20005262G-page 24
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
5.16
Serial Flash Discoverable
Parameters (SFDP)
Initiate SFDP by executing an 8-bit command (5AH),
followed by address bits A[23-0] and a dummy byte.
CE# must remain active-low for the duration of the
SFDP cycle. For the SFDP sequence, see Figure 5-18.
The Serial Flash Discoverable Parameters (SFDP) contain information describing the characteristics of the
device. This allows device-independent, JEDEC
ID-independent and forward/backward compatible software support for all future Serial Flash device families.
See Table 11-1 for address and data values.
FIGURE 5-18:
SERIAL FLASH DISCOVERABLE PARAMETERS SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
MODE 0
5A
SI
ADD.
X
Sector Erase
N+2
DOUT
N+3
DOUT
N+4
DOUT
Address bits [AMS-A12] (AMS = Most Significant
Address) determine the sector address (SAX); the
remaining address bits can be VIL or VIH. To identify the
completion of the internal, self-timed, Write operation,
poll the BUSY bit in the STATUS register or wait TSE.
See Figures 5-19 and 5-20 for the Sector Erase
sequence.
The Sector Erase instruction clears all bits in the
selected 4 Kbyte sector to ‘1,’ but it does not change a
protected memory area. Prior to any write operation,
the Write Enable (WREN) instruction must be executed.
To execute a Sector Erase operation, the host drives
CE# low, then sends the Sector Erase command cycle
(20H) and three address cycles and then drives CE#
high.
FIGURE 5-19:
N+1
DOUT
N
DOUT
MSb
High-Impedance
SO
5.17
ADD.
ADD.
4-KBYTE SECTOR ERASE SEQUENCE (SQI)
CE#
MODE 3
SCK
SIO[3:0]
0
1
2
4
6
MODE 0
C1 C0 A5 A4 A3 A2 A1 A0
MSN LSN
Note:
MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = 20H
2014-2022 Microchip Technology Inc. and its subsidiaries
DS20005262G-page 25
SST26VF016B
FIGURE 5-20:
4-KBYTE SECTOR ERASE SEQUENCE (SPI)
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
MSb
31
ADD.
MSb
High-Impedance
SO
Block Erase
To execute a Block Erase operation, the host drives
CE# low then sends the Block Erase command cycle
(D8H), three address cycles, then drives CE# high.
Address bits AMS-A13 determine the block address
(BAX); the remaining address bits can be VIL or VIH.
For 32-Kbyte blocks, A14-A13 can be VIL or VIH; for
64-Kbyte blocks, A15-A13 can be VIL or VIH. Poll the
BUSY bit in the STATUS register or wait TBE, for the
completion of the internal, self-timed, Block Erase
operation. See Figures 5-21 and 5-22 for the Block
Erase sequence.
The Block Erase instruction clears all bits in the
selected block to ‘1’. Block sizes can be 8-Kbyte,
32-Kbyte or 64-Kbyte depending on address (see
Figure 3-1 for details. A Block Erase instruction applied
to a protected memory area will be ignored. Prior to any
write operation, execute the WREN instruction. Keep
CE# active-low for the duration of any command
sequence.
FIGURE 5-21:
ADD.
ADD.
20
SI
5.18
23 24
15 16
MODE 0
BLOCK ERASE SEQUENCE (SQI)
CE#
MODE 3
SCK
0
1
2
4
6
MODE 0
SIO[3:0]
C1 C0 A5 A4 A3 A2 A1 A0
MSN LSN
Note:
MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = D8H
FIGURE 5-22:
BLOCK ERASE SEQUENCE (SPI)
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
D8
SI
MSb
SO
DS20005262G-page 26
15 16
23 24
31
MODE 0
ADDR
ADDR
ADDR
MSb
High-Impedance
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
5.19
Chip Erase
The Chip Erase instruction clears all bits in the device
to ‘1.’ The Chip Erase instruction is ignored if any of the
memory area is protected. Prior to any write operation,
execute the WREN instruction.
To execute a Chip Erase operation, the host drives CE#
low, sends the Chip Erase command cycle (C7H), then
drives CE# high. Poll the BUSY bit in the STATUS register or wait TSCE for the completion of the internal,
self-timed, Write operation. See Figures 5-23 and 5-24
for the Chip Erase sequence.
FIGURE 5-23:
CHIP ERASE SEQUENCE (SQI)
CE#
MODE 3
SCK
1
MODE 0
SIO[3:0]
Note:
0
C1 C0
C[1:0] = C7H
FIGURE 5-24:
CHIP ERASE SEQUENCE (SPI)
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
C7
SI
MSb
SO
2014-2022 Microchip Technology Inc. and its subsidiaries
High-Impedance
DS20005262G-page 27
SST26VF016B
5.20
Page Program
Poll the BUSY bit in the STATUS register or wait TPP for
the completion of the internal, self-timed, Write operation. See Figures 5-25 and 5-26 for the Page Program
sequence.
The Page Program instruction programs up to
256 bytes of data in the memory and supports both SPI
and SQI protocols. The data for the selected page
address must be in the erased state (FFH) before initiating the Page Program operation. A Page Program
applied to a protected memory area will be ignored.
Prior to the program operation, execute the WREN
instruction.
When executing Page Program, the memory range for
the SST26VF016B is divided into 256-byte page
boundaries. The device handles shifting of more than
256 bytes of data by maintaining the last 256 bytes of
data as the correct data to be programmed. If the target
address for the Page Program instruction is not the
beginning of the page boundary (A[7:0] are not all zero)
and the number of bytes of data input exceeds or overlaps the end of the address of the page boundary, the
excess data inputs wrap around and will be programmed at the start of that target page.
To execute a Page Program operation, the host drives
CE# low, then sends the Page Program command
cycle (02H), three address cycles followed by the data
to be programmed, then drives CE# high. The programmed data must be between 1 to 256 bytes and in
whole byte increments; sending less than a full byte will
cause the partial byte to be ignored.
FIGURE 5-25:
PAGE PROGRAM SEQUENCE (SQI)
CE#
MODE 3
SCK
0
2
4
6
8
10
12
MODE 0
SIO[3:0]
C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2
HN LN
MSN LSN
Data Byte 0 Data Byte 1 Data Byte 2
Note:
Data Byte 255
MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = 02H
FIGURE 5-26:
PAGE PROGRAM SEQUENCE (SPI)
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31 32
39
MODE 0
SI
ADD.
02
MSb
ADD.
ADD.
LSb MSb
SO
Data Byte 0
LSb MSb
LSb
High-Impedance
2079
2078
2077
2076
2075
2074
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CE#(cont’)
SCK(cont’)
SI(cont’)
Data Byte 1
MSb
SO(cont’)
DS20005262G-page 28
Data Byte 255
Data Byte 2
LSb MSb
LSb
MSb
LSb
High-Impedance
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
5.21
SPI Quad Page Program
The SPI Quad Page Program instruction programs up
to 256 bytes of data in the memory. The data for the
selected page address must be in the erased state
(FFH) before initiating the SPI Quad Page Program
operation. A SPI Quad Page Program applied to a protected memory area will be ignored. SST26VF016B
requires the ICO bit in the Configuration register to be
set to ‘1’ prior to executing the command. Prior to the
program operation, execute the WREN instruction.
To execute a SPI Quad Page Program operation, the
host drives CE# low, then sends the SPI Quad Page
Program command cycle (32H), three address cycles
followed by the data to be programmed, then drives
CE# high. The programmed data must be between 1 to
256 bytes and in whole byte increments.
FIGURE 5-27:
The command cycle is eight clocks long, the address
and data cycles are each two clocks long, Most Significant bit first. Poll the BUSY bit in the STATUS register
or wait TPP for the completion of the internal, self-timed,
Write operation (see Figure 5-27).
When executing SPI Quad Page Program, the memory
range for the SST26VF016B is divided into 256 byte
page boundaries. The device handles shifting of more
than 256 bytes of data by maintaining the last
256 bytes of data as the correct data to be programmed. If the target address for the SPI Quad Page
Program instruction is not the beginning of the page
boundary (A[7:0] are not all zero) and the of bytes of
data input exceeds or overlaps the end of the address
of the page boundary, the excess data inputs wrap
around and will be programmed at the start of that target page.
SPI QUAD PAGE PROGRAM SEQUENCE
CE#
MODE 3
SCK
SIO0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
MODE 0
32H
A20A16A12 A8 A4 A0 b4 b0 b4 b0
b4 b0
SIO1
A21 A17A13 A9 A5 A1 b5 b1 b5 b1
b5 b1
SIO2
A22 A18A14A10 A6 A2 b6 b2 b6 b2
b6 b2
SIO3
A23 A19 A15 A11 A7 A3 b7 b3 b7 b3
b7 b3
Data Data
Byte 0 Byte 1
Data
Byte
255
MSN LSN
Address
5.22
Write Suspend and Write Resume
Write Suspend allows the interruption of Sector Erase,
Block Erase, SPI Quad Page Program or Page Program operations in order to erase, program or read
data in another portion of memory. The original operation can be continued with the Write Resume command. This operation is supported in both SQI and SPI
protocols.
Only one write operation can be suspended at a time;
if an operation is already suspended, the device will
ignore the Write Suspend command. Write Suspend
during Chip Erase is ignored; Chip Erase is not a valid
command while a write is suspended. The Write
Resume command is ignored until any write operation
(Program or Erase) initiated during the Write Suspend
is complete. The device requires a minimum of 500 µs
between each Write Suspend command.
2014-2022 Microchip Technology Inc. and its subsidiaries
5.23
Write Suspend During Sector
Erase or Block Erase
Issuing a Write Suspend instruction during Sector
Erase or Block Erase allows the host to program or
read any sector that was not being erased. The device
will ignore any programming commands pointing to the
suspended sector(s). Any attempt to read from the suspended sector(s) will output unknown data because the
Sector or Block Erase will be incomplete.
To execute a Write Suspend operation, the host drives
CE# low, sends the Write Suspend command cycle
(B0H), then drives CE# high. The STATUS register indicates that the erase has been suspended by changing
the WSE bit from ‘0’ to ‘1,’ but the device will not accept
another command until it is ready. To determine when
the device will accept a new command, poll the BUSY
bit in the STATUS register or wait TWS.
DS20005262G-page 29
SST26VF016B
5.24
Write Suspend During Page
Programming or SPI Quad Page
Programming
Issuing a Write Suspend instruction during Page Programming allows the host to erase or read any sector
that is not being programmed. Erase commands pointing to the suspended sector(s) will be ignored. Any
attempt to read from the suspended page will output
unknown data because the program will be incomplete.
To execute a Write Suspend operation, the host drives
CE# low, sends the Write Suspend command cycle
(B0H), then drives CE# high. The STATUS register indicates that the programming has been suspended by
changing the WSP bit from ‘0’ to ‘1,’ but the device will
not accept another command until it is ready. To determine when the device will accept a new command, poll
the BUSY bit in the STATUS register or wait TWS.
5.25
Write Resume
Write Resume restarts a write command that was suspended and changes the suspend status bit in the STATUS register (WSE or WSP) back to ‘0’.
To execute a Write Resume operation, the host drives
CE# low, sends the Write Resume command cycle
(30H), then drives CE# high. To determine if the internal, self-timed Write operation completed, poll the
BUSY bit in the STATUS register or wait the specified
time TSE, TBE or TPP for Sector Erase, Block Erase or
Page Programming, respectively. The total write time
before suspend and after resume will not exceed the
uninterrupted write times TSE, TBE or TPP.
5.26
Read Security ID
The Read Security ID operation is supported in both
SPI and SQI modes. To execute a Read Security ID
(SID) operation in SPI mode, the host drives CE# low,
sends the Read Security ID command cycle (88H), two
address cycles and then one dummy cycle. To execute
a Read Security ID operation in SQI mode, the host
drives CE# low and then sends the Read Security ID
command, two address cycles and three dummy
cycles.
TABLE 5-5:
After the dummy cycles, the device outputs data on the
falling edge of the SCK signal, starting from the specified address location. The data output stream is continuous through all SID addresses until terminated by a
low-to-high transition on CE#. See Table 5-5 for the
Security ID address range.
5.27
Program Security ID
The Program Security ID instruction programs one to
2040 bytes of data in the user-programmable, Security
ID space. This Security ID space is One-Time-Programmable (OTP). The device ignores a Program
Security ID instruction pointing to an invalid or protected address (see Table 5-5). Prior to the program
operation, execute WREN.
To execute a Program SID operation, the host drives
CE# low, sends the Program Security ID command
cycle (A5H), two address cycles, the data to be programmed, then drives CE# high. The programmed data
must be between 1 to 256 bytes and in whole byte
increments.
The device handles shifting of more than 256 bytes of
data by maintaining the last 256 bytes of data as the
correct data to be programmed. If the target address for
the Program Security ID instruction is not the beginning
of the page boundary and the number of data input
exceeds or overlaps the end of the address of the page
boundary, the excess data inputs wrap around and will
be programmed at the start of that target page.
The Program Security ID operation is supported in both
SPI and SQI mode. To determine the completion of the
internal, self-timed Program SID operation, poll the
BUSY bit in the software STATUS register or wait TPSID
for the completion of the internal self-timed Program
Security ID operation.
PROGRAM SECURITY ID
Program Security ID
Address Range
Unique ID Pre-Programmed at factory
0000–0007H
User Programmable
0008H–07FFH
DS20005262G-page 30
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
5.28
Lockout Security ID
To read the STATUS or Configuration registers, the
host drives CE# low, then sends the Read Status Register command cycle (05H) or the Read Configuration
Register command (35H). A dummy cycle is required in
SQI mode. Immediately after the command cycle, the
device outputs data on the falling edge of the SCK signal. The data output stream continues until terminated
by a low-to-high transition on CE#. See Figures 5-28
and 5-29 for the instruction sequence.
The Lockout Security ID instruction prevents any future
changes to the Security ID and is supported in both SPI
and SQI modes. Prior to the operation, execute WREN.
To execute a Lockout SID, the host drives CE# low,
sends the Lockout Security ID command cycle (85H),
then drives CE# high. Poll the BUSY bit in the software
STATUS register or wait TPSID, for the completion of the
Lockout Security ID operation.
5.29
Read Status Register (RDSR) and
Read Configuration Register (RDCR)
The Read Status Register (RDSR) and Read Configuration Register (RDCR) commands output the contents of
the STATUS and Configuration registers. These commands function in both SPI and SQI modes. The STATUS register may be read at any time, even during a
write operation. When a write is in progress, poll the
BUSY bit before sending any new commands to assure
that the new commands are properly received by the
device.
FIGURE 5-28:
READ STATUS REGISTER AND READ CONFIGURATION REGISTER SEQUENCE
(SQI)
CE#
MODE 3
0
2
4
6
8
SCK MODE 0
MSN LSN
SIO[3:0]
C1 C0 X
X H0 L0 H0 L0
Dummy
Note:
H0 L0
Status Byte Status Byte
Status Byte
MSN = Most Significant Nibble; LSN = Least Significant Nibble, C[1:0] = 05H or 35H
FIGURE 5-29:
READ STATUS REGISTER AND READ CONFIGURATION REGISTER SEQUENCE
(SPI)
CE#
MODE 3
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MODE 0
05 or 35H
SI
MSb
SO
High-Impedance
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSb
2014-2022 Microchip Technology Inc. and its subsidiaries
Status or Configuration
Register Out
DS20005262G-page 31
SST26VF016B
5.30
Write Status Register (WRSR)
The Write Status Register (WRSR) command writes new
values to the Configuration register. To execute a Write
Status Register operation, the host drives CE# low,
then sends the Write Status Register command cycle
(01H), two cycles of data and then drives CE# high.
Values in the second data cycle will be accepted by the
device (see Figures 5-30 and 5-31).
FIGURE 5-30:
WRITE STATUS REGISTER SEQUENCE (SQI)
CE#
MODE 3
SCK
0
1
2
3
4
5
MODE 0
MSN LSN
SIO[3:0]
C1 C0 H0 L0 H0 L0
Command Status
Byte
Note:
Configuration
Byte
MSN = Most Significant Nibble; LSN = Least Significant Nibble, XX = Don’t Care, C[1:0] = 01H
FIGURE 5-31:
WRITE STATUS REGISTER SEQUENCE (SPI)
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
MODE 0
01
06
SI
MSb
MSb
Status
Configuration
Register
Register
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSb
MSb
High-Impedance
SO
Note:
MODE 3
XX = Don’t Care
DS20005262G-page 32
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
5.31
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write
Enable Latch bit in the STATUS register to ‘1,’ allowing
write operations to occur. The WREN instruction must be
executed prior to any of the following operations: Sector Erase, Block Erase, Chip Erase, Page Program,
Program Security ID, Lockout Security ID, Write Block
Protection Register, Lock-Down Block Protection Register, Nonvolatile Write Lock Lock-Down Register, SPI
Quad Page program and Write Status Register. To execute a Write Enable, the host drives CE# low, then
sends the Write Enable command cycle (06H) and
drives CE# high. See Figures 5-32 and 5-33 for the
WREN instruction sequence.
FIGURE 5-32:
WRITE ENABLE SEQUENCE (SQI)
CE#
MODE 3
SCK
1
0
6
MODE 0
SIO[3:0]
FIGURE 5-33:
0
WRITE ENABLE SEQUENCE (SPI)
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
06
SI
MSb
SO
2014-2022 Microchip Technology Inc. and its subsidiaries
High-Impedance
DS20005262G-page 33
SST26VF016B
5.32
Write Disable (WRDI)
The Write Disable (WRDI) instruction sets the Write
Enable Latch bit in the STATUS register to ‘0,’ preventing write operations. The WRDI instruction is ignored
during any internal write operations. Any write operation started before executing WRDI will complete. Drive
CE# high before executing WRDI.
To execute a Write Disable, the host drives CE# low,
sends the Write Disable command cycle (04H), then
drives CE# high (see Figures 5-34 and 5-35).
FIGURE 5-34:
WRITE DISABLE (WRDI) SEQUENCE (SQI)
CE#
MODE 3
SCK
1
0
4
MODE 0
SIO[3:0]
FIGURE 5-35:
0
WRITE DISABLE (WRDI) SEQUENCE (SPI)
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
04
SI
MSb
SO
DS20005262G-page 34
High-Impedance
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
5.33
Read Block Protection Register
(RBPR)
The Read Block Protection Register instruction outputs
the Block Protection register data which determines the
protection status. To execute a Read Block Protection
Register operation, the host drives CE# low and then
sends the Read Block Protection Register command
cycle (72H). A dummy cycle is required in SQI mode.
After the command cycle, the device outputs data on
the falling edge of the SCK signal starting with the Most
Significant bit(s); see Table 5-6 for definitions of each
bit in the Block Protection register. The RBPR command
does not wrap around. After all data have been output,
the device will output 0H until terminated by a
low-to-high transition on CE# (see Figures 5-36 and
5-37).
FIGURE 5-36:
READ BLOCK PROTECTION REGISTER SEQUENCE (SQI)
CE#
MODE 3
0
2
4
6
8
10
12
SCK
SIO[3:0]
C1 C0 X
X H0 L0 H1 L1 H2 L2 H3 L3 H4 L4
MSN LSN
BPR [m:m-7]
Note:
HN LN
BPR [7:0]
MSN = Most Significant Nibble, LSN = Least Significant Nibble
Block Protection Register (BPR), m = 47 for SST26VF016B, C[1:0] = 72H
FIGURE 5-37:
READ BLOCK PROTECTION REGISTER SEQUENCE (SPI)
CE#
MODE 3
SCK
SIO0
0 1 2 3 4 5 6 7 8
15 16
23 24
32 33
MODE 0
72H
OP Code
SIO
2014-2022 Microchip Technology Inc. and its subsidiaries
Data Byte 0
Data Byte 1 Data Byte 2
Data Byte N
DS20005262G-page 35
SST26VF016B
5.34
Write Block Protection Register
(WBPR)
The Write Block Protection Register (WBPR) command
changes the Block Protection register data to indicate
the protection status. Execute WREN before executing
WBPR.
To execute a Write Block Protection Register operation,
the host drives CE# low, sends the Write Block Protection Register command cycle (42H), sends 18 cycles of
data and finally drives CE# high. Data input must be
Most Significant bit(s) first. See Table 5-6 for definitions
of each bit in the Block Protection register (see
Figures 5-38 and 5-39).
FIGURE 5-38:
WRITE BLOCK PROTECTION REGISTER SEQUENCE (SQI)
CE#
MODE 3
SCK
0
2
4
6
8
10
12
MODE 0
SIO[3:0]
C1 C0 H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5
HN LN
MSN LSN
BPR [m:m-7]
Note:
BPR [7:0]
MSN = Most Significant Nibble, LSN = Least Significant Nibble
Block Protection Register (BPR) m = 47, C[1:0] = 42H
FIGURE 5-39:
WRITE BLOCK PROTECTION REGISTER SEQUENCE (SPI)
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
MODE 0
OP Code
SI
42H
Data Byte0
Data Byte1 Data Byte2
Data ByteN
SO
Note:
C[1:0 ]= 42H
DS20005262G-page 36
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
5.35
Lock-Down Block Protection
Register (LBPR)
The Lock-Down Block Protection Register instruction
prevents changes to the Block Protection register
during device operation. Lock-Down resets after power
cycling; this allows the Block Protection register to be
changed. Execute WREN before initiating the
Lock-Down Block Protection Register instruction.
To execute a Lock-Down Block Protection Register, the
host drives CE# low, then sends the Lock-Down Block
Protection Register command cycle (8DH), then drives
CE# high.
FIGURE 5-40:
LOCK-DOWN BLOCK PROTECTION REGISTER (SQI)
CE#
MODE 3
SCK
0
MODE 0
SIO[3:0]
Note:
FIGURE 5-41:
1
C1 C0
C[1:0] = 8DH
LOCK-DOWN BLOCK PROTECTION REGISTER (SPI)
CE#
MODE 3
SCK
0
1
2
3
4
5
6
7
MODE 0
SIO0
8D
SIO[3:1]
2014-2022 Microchip Technology Inc. and its subsidiaries
DS20005262G-page 37
SST26VF016B
5.36
Nonvolatile Write Lock Lock-Down
Register (nVWLDR)
The Nonvolatile Write Lock Lock-Down Register
(nVWLDR) instruction controls the ability to change the
Write Lock bits in the Block Protection register. Execute
WREN before initiating the nVWLDR instruction.
To execute nVWLDR, the host drives CE# low, then
sends the nVWLDR command cycle (E8H), followed by
18 cycles of data, and then drives CE# high.
After CE# goes high, the nonvolatile bits are programmed and the programming time-out must complete before any additional commands, other than
Read Status Register, can be entered. Poll the BUSY
bit in the STATUS register, or wait TPP, for the completion of the internal, self-timed, Write operation. Data
inputs must be Most Significant bit(s) first.
FIGURE 5-42:
WRITE LOCK LOCK-DOWN REGISTER SEQUENCE (SQI)
CE#
MODE 3
SCK
0
2
4
6
8
10
12
MODE 0
SIO[3:0]
E
8 H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5
HN LN
MSN LSN
nVWLDR[m:m-7]
Note:
BPR [7:0]
MSN= Most Significant Nibble; LSN = Least Significant Nibble
Write Lock Lock-Down Register (nVWLDR) m = 47
FIGURE 5-43:
WRITE LOCK LOCK-DOWN REGISTER SEQUENCE (SPI)
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
MODE 0
OP Code
SI
E8H
Data Byte0
Data Byte1 Data Byte2
Data ByteN
SO
DS20005262G-page 38
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
5.37
Global Block Protection Unlock
(ULBPR)
The Global Block Protection Unlock (ULBPR) instruction clears all write protection bits in the Block Protection register, except for those bits that have been
locked down with the nVWLDR command. Execute
WREN before initiating the ULBPR instruction.
To execute a ULBPR instruction, the host drives CE#
low, then sends the ULBPR command cycle (98H) and
then drives CE# high.
FIGURE 5-44:
GLOBAL BLOCK PROTECTION UNLOCK (SQI)
CE#
MODE 3
SCK
1
MODE 0
SIO[3:0]
Note:
0
C1 C0
C[1:0] = 98H
FIGURE 5-45:
GLOBAL BLOCK PROTECTION UNLOCK (SPI)
CE#
MODE 3
SCK
0
1
2
3
4
5
6
7
MODE 0
SIO0
98
SIO[3:1]
2014-2022 Microchip Technology Inc. and its subsidiaries
DS20005262G-page 39
SST26VF016B
BLOCK PROTECTION REGISTER FOR SST26VF016B(1)
TABLE 5-6:
BPR Bits
Address Range
Protected Block Size
46
1FE000H-1FFFFFH
8 Kbytes
44
1FC000H-1FDFFFH
8 Kbytes
43
42
1FA000H-1FBFFFH
8 Kbytes
41
40
1F8000H-1F9FFFH
8 Kbytes
Read Lock
Write Lock/nVWLDR(2)
47
45
Note 1:
2:
39
38
006000H-007FFFH
8 Kbytes
37
36
004000H-005FFFH
8 Kbytes
35
34
002000H-003FFFH
8 Kbytes
33
32
000000H-001FFFH
8 Kbytes
31
1F0000H-1F7FFFH
32 Kbytes
30
008000H-00FFFFH
32 Kbytes
29
1E0000H-1EFFFFH
64 Kbytes
28
1D0000H-1DFFFFH
64 Kbytes
27
1C0000H-1CFFFFH
64 Kbytes
26
1B0000H-1BFFFFH
64 Kbytes
25
1A0000H-1AFFFFH
64 Kbytes
24
190000H-19FFFFH
64 Kbytes
23
180000H-18FFFFH
64 Kbytes
22
170000H-17FFFFH
64 Kbytes
21
160000H-16FFFFH
64 Kbytes
20
150000H-15FFFFH
64 Kbytes
19
140000H-14FFFFH
64 Kbytes
18
130000H-13FFFFH
64 Kbytes
17
120000H-12FFFFH
64 Kbytes
16
110000H-11FFFFH
64 Kbytes
15
100000H-10FFFFH
64 Kbytes
14
0F0000H-0FFFFFH
64 Kbytes
13
0E0000H-0EFFFFH
64 Kbytes
12
0D0000H-0DFFFFH
64 Kbytes
11
0C0000H-0CFFFFH
64 Kbytes
10
0B0000H-0BFFFFH
64 Kbytes
9
0A0000H-0AFFFFH
64 Kbytes
8
090000H-09FFFFH
64 Kbytes
7
080000H-08FFFFH
64 Kbytes
6
070000H-07FFFFH
64 Kbytes
5
060000H-06FFFFH
64 Kbytes
4
050000H-05FFFFH
64 Kbytes
3
040000H-04FFFFH
64 Kbytes
2
030000H-03FFFFH
64 Kbytes
1
020000H-02FFFFH
64 Kbytes
0
010000H-01FFFFH
64 Kbytes
The default state after a Power-on Reset is write-protected BPR[47:0] = 5555 FFFF FFFF.
nVWLDR bits are One-Time-Programmable. Once a WLLDR bit is set, the protection state of that particular block is permanently write-locked.
DS20005262G-page 40
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
5.38
Deep Power-Down
Enter Deep Power-Down mode by initiating the Deep
Power-Down (DPD) instruction (B9H) while driving CE#
low. CE# must be driven high before executing the DPD
instruction. After CE# is driven high, it requires a delay
of TDPD before the standby current ISB is reduced to
deep power-down current IDPD. See Table 5-7 for Deep
Power-Down timing. If the device is busy performing an
internal erase or program operation, initiating a Deep
Power-Down instruction will not place the device in
Deep Power-Down mode. See Figures 5-47 and for
the DPD instruction sequence.
The Deep Power-Down (DPD) instruction puts the
device in the lowest power consumption mode – the
Deep Power-Down mode. The Deep Power-Down
instruction is ignored during an internal write operation.
While the device is in Deep Power-Down mode, all
instructions will be ignored except for the Release
Deep Power-Down instruction.
TABLE 5-7:
DEEP POWER-DOWN
Symbol
Parameter
TDPD
TSBR
CE# High to Deep Power-Down
CE# High to Standby Mode
Min.
Max.
Units
—
—
3
10
µs
µs
DEEP POWER-DOWN (DPD) SEQUENCE (SQI)
FIGURE 5-46:
CE#
TDPD
MODE 3
SCK
1
0
MODE 0
SIO[3:0]
B
9
MSN
LSN
Standby Mode Deep Power-Down Mode
Note:
MSN= Most Significant Nibble; LSN = Least Significant Nibble
DEEP POWER-DOWN (DPD) SEQUENCE (SPI)
FIGURE 5-47:
CE#
TDPD
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
B9
SI
MSb
SO
High-Impedance
Standby Mode Deep Power-Down Mode
2014-2022 Microchip Technology Inc. and its subsidiaries
DS20005262G-page 41
SST26VF016B
5.39
Release from Deep Power-Down
and Read ID
To execute RDPD and read the Device ID, the host
drives CE# low, then sends the Deep Power-Down
command cycle (ABH), three dummy clock cycles and
then drives CE# high. The device outputs the Device ID
on the falling edge of the SCK signal following the
dummy cycles. The data output stream is continuous
until terminated by a low-to-high transition on CE and
will return to Standby mode and be ready for the next
instruction after TSBR. See Figures 5-48 and 5-49 for
the command sequence.
Release from Deep Power-Down (RDPD) and Read ID
instruction exits Deep Power-Down mode. To exit Deep
Power-Down mode, execute the RDPD. During this
command, the host drives CE# low, then sends the
Deep Power-Down command cycle (ABH) and then
drives CE# high. The device will return to Standby
mode and be ready for the next instruction after TSBR.
RELEASE FROM DEEP POWER-DOWN (RDPD) AND READ ID SEQUENCE (SQI)
FIGURE 5-48:
TSBR
CE#
MODE 3
1
0
SCK MODE 0
Op Code
SIO[3:0]
C1
C0
MSN
LSN
X
X
X
X
X
X
D1 D0
Device ID
Deep Power-Down Mode Standby Mode
Note:
C[1:0] = ABH
FIGURE 5-49:
RELEASE FROM DEEP POWER-DOWN (RDPD) AND READ ID SEQUENCE (SPI)
TSBR
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23 24
32 33
40
SCK MODE 0
Op Code
SIO[3:0]
AB
XX
XX
XX
Device ID
Deep Power-Down Mode Standby Mode
DS20005262G-page 42
2014-2022 Microchip Technology Inc. and its subsidiaries
SST26VF016B
6.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (†)
Temperature under bias ..........................................................................................................................-55°C to +125°C
Storage temperature ............................................................................................................................... -65°C to +150°C
DC voltage on any pin to ground potential ...........................................................................................-0.5V to VDD+0.5V
Transient voltage (
工商网监
湘ICP备2023018690号
