SST38VF6402-90-5C-B3KE

64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 The SST38VF6401/6402/6403/6404 are 4M x16 CMOS Advanced Multi-Purpose Flash Plus (Advanced MPF+) devices manufactured with proprietary, high-performance CMOS Super- Flash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST38VF6401/6402/6403/6404 write (Program or Erase) with a 2.7-3.6V power supply. This device conforms to JEDEC standard pin assignments for x16 memories. Features • Organized as 4M x16 • Single Voltage Read and Write Operations – 2.7-3.6V • Superior Reliability – Endurance: 100,000 Cycles minimum – Greater than 100 years Data Retention3 • Low Power Consumption (typical values at 5 MHz) – Active Current: 4 mA (typical) – Standby Current: 3 µA (typical) – Auto Low Power Mode: 3 µA (typical) • 128-bit Unique ID • Security-ID Feature – 256 Word, user One-Time-Programmable • Protection and Security Features – Hardware Boot Block Protection/WP# Input Pin, Uniform (32 KWord) and Non-Uniform (8 KWord) options available – User-controlled individual block (32 KWord) protection, using software only methods – Password protection • Hardware Reset Pin (RST#) • Fast Read and Page Read Access Times: – 90 ns Read access time – 25 ns Page Read access times - 4-Word Page Read buffer • Fast Erase Times: – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 40 ms (typical) • Erase-Suspend/-Resume Capabilities • Fast Word and Write-Buffer Programming Times: – Word-Program Time: 7 µs (typical) – Write Buffer Programming Time: 1.75 µs / Word (typical) - 16-Word Write Buffer • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bits – Data# Polling – RY/BY# Output • CMOS I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts and command sets • CFI Compliant • Packages Available – 48-lead TSOP – 48-ball TFBGA • All devices are RoHS compliant • Latched Address and Data ©2015-2018 Microchip Technology Inc DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Product Description The SST38VF6401, SST38VF6402, SST38VF6403, and SST38VF6404 devices are 4M x16 CMOS Advanced Multi-Purpose Flash Plus (Advanced MPF+) manufactured with proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST38VF6401/ 6402/6403/6404 write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pin assignments for x16 memories. Featuring high performance Word-Program, the SST38VF6401/6402/6403/6404 provide a typical WordProgram time of 7 µsec. For faster word-programming performance, the Write-Buffer Programming feature, has a typical word-program time of 1.75 µsec. These devices use Toggle Bit or Data# Polling to indicate Program operation completion. In addition to single-word Read, Advanced MPF+ devices provide a Page-Read feature that enables a faster word read time of 25 ns, for words on the same page. To protect against inadvertent write, the SST38VF6401/6402/6403/6404 have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are available with 100,000 cycles minimum endurance. Data retention is rated at greater than 100 years. The SST38VF6401/6402/6403/6404 are suited for applications that require the convenient and economical updating of program, configuration, or data memory. For all system applications, Advanced MPF+ significantly improve performance and reliability, while lowering power consumption. These devices inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. For any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time; therefore, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST38VF6401/6402/6403/6404 also offer flexible data protection features. Applications that require memory protection from program and erase operations can use the Boot Block, Individual Block Protection, and Advanced Protection features. For applications that require a permanent solution, the Irreversible Block Locking feature provides permanent protection for memory blocks. To meet high-density, surface mount requirements, the SST38VF6401/6402/6403/6404 devices are offered in 48-lead TSOP and 48-ball TFBGA packages. See Figures 2 and 3 for pin assignments and Table 1 for pin descriptions. ©2015-2018 Microchip Technology Inc 2 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Functional Block Diagram SuperFlash Memory X-Decoder Memory Address Address Buffer & Latches Y-Decoder CE# OE# WE# WP# RESET# I/O Buffers and Data Latches Control Logic DQ15 - DQ0 RY/BY# 1309 B1.1 Figure 1: Functional Block Diagram ©2015-2018 Microchip Technology Inc 3 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Pin Assignments A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RST# A21 WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Standard Pinout Top View Die Up A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1309 48-tsop P1.0 Figure 2: Pin Assignments for 48-lead TSOP 6 5 4 3 2 1 A13 A12 A14 A15 A16 NC DQ15 VSS A10 A11 DQ7 DQ14 DQ13 DQ6 WE# RST# A21 A19 DQ5 DQ12 VDD DQ4 RY/BY# WP# A18 A20 DQ2 DQ10 DQ11 DQ3 A9 A8 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A3 A4 A2 A1 A0 CE# OE# VSS A B C D E F G H 1309 48-tfbga P1.0 TOP VIEW (balls facing down) Figure 3: Pin assignments for 48-ball TFBGA ©2015-2018 Microchip Technology Inc 4 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Table 1: Pin Description Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. During Block-Erase AMS-A15 address lines will select the block. DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded. RY/BY# Ready/Busy To indicate when the device is actively programming or erasing. RST# Reset To reset and return the device to Read mode. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. VDD Power Supply To provide power supply voltage: 2.7-3.6V VSS Ground NC No Connection Unconnected pins. 1. AMS = Most significant address AMS = A21 for SST38VF6401/6402/6403/6404 ©2015-2018 Microchip Technology Inc 5 T1.0 20005015 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Memory Maps Table 2: SST38VF6401and SST38VF6402 Memory Maps SST38VF6401 Block1,2 Sectors3 Address A21-A124 6 B0 S0-S7 0000000XXX B1 S8-S15 0000001XXX B2 S16-S23 0000010XXX B3 S24-S31 0000011XXX B4 S32-S39 0000100XXX B5 S40-S47 0000101XXX B6 S48-S55 0000110XXX B7 S56-S63 0000111XXX B8 - B119 follow the same pattern B120 S960-S967 1111000XXX B121 S968-S975 1111001XXX B122 S976-S983 1111010XXX B123 S984-S991 1111011XXX B124 S992-S999 1111100XXX B125 S1000-S1007 1111101XXX B126 S1008-S1015 1111110XXX B127 S1016-S1023 1111111XXX VPB5 YES YES YES YES YES YES YES YES NVPB5 YES YES YES YES YES YES YES YES WP#6 YES NO NO NO NO NO NO NO YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES NO NO NO NO NO NO NO NO VPB5 YES YES YES YES YES YES YES YES NVPB5 YES YES YES YES YES YES YES YES WP#7 NO NO NO NO NO NO NO NO YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES NO NO NO NO NO NO NO YES SST38VF6402 Block1,2 Sectors3 Address A21-A124 B0 S0-S7 0000000XXX B1 S8-S15 0000001XXX B2 S16-S23 0000010XXX B3 S24-S31 0000011XXX B4 S32-S39 0000100XXX B5 S40-S47 0000101XXX B6 S48-S55 0000110XXX B7 S56-S63 0000111XXX B8 - B119 follow the same pattern B120 S960-S967 1111000XXX B121 S968-S975 1111001XXX B122 S976-S983 1111010XXX B123 S984-S991 1111011XXX B124 S992-S999 1111100XXX B125 S1000-S1007 1111101XXX B126 S1008-S1015 1111110XXX B1277 S1016-S1023 1111111XXX T2.0 20005015 1. 2. 3. 4. 5. 6. 7. ©2015-2018 Microchip Technology Inc Each block, B0-B127 is 32KWord. Each block consists of eight sectors. Each sector, S0-S1023 is 4KWord. X = 0 or 1. Block Address (BA) = A21 - A15; Sector Address (SA) = A21 - A12 Each block has an associated VPB and NVPB. Block B0 is the boot block. Block B127 is the boot block. 6 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Table 3: SST38VF6403and SST38VF6404 Memory Maps (1 of 2) SST38VF6403 Block1,2 Sectors3 Address A21-A124 VPB5 NVPB5 WP#6 B05,6 S0 0000000000 YES YES YES S1 0000000001 YES YES YES S2 0000000010 YES YES NO S3 0000000011 YES YES NO S4 0000000100 YES YES NO S5 0000000101 YES YES NO S6 0000000110 YES YES NO S7 0000000111 YES YES NO B1 S8-S15 0000001XXX YES YES NO B2 S16-S23 0000010XXX YES YES NO B3 S24-S31 0000011XXX YES YES NO B4 S32-S39 0000100XXX YES YES NO B5 S40-S47 0000101XXX YES YES NO B6 S48-S55 0000110XXX YES YES NO B7 S56-S63 0000111XXX YES YES NO B8 - B119 follow the same pattern B120 S960-S967 1111000XXX YES YES NO B121 S968-S975 1111001XXX YES YES NO B122 S976-S983 1111010XXX YES YES NO B123 S984-S991 1111011XXX YES YES NO B124 S992-S999 1111100XXX YES YES NO B125 S1000-S1007 1111101XXX YES YES NO B126 S1008-S1015 1111110XXX YES YES NO B127 S1016-S1023 1111111XXX YES YES NO Block1,2 Sectors3 Address A21-A124 VPB5 NVPB5 WP#7 B0 S0-S7 0000000XXX YES YES NO B1 S8-S15 0000001XXX YES YES NO NO SST38VF6404 B2 S16-S23 0000010XXX YES YES B3 S24-S31 0000011XXX YES YES NO B4 S32-S39 0000100XXX YES YES NO B5 S40-S47 0000101XXX YES YES NO B6 S48-S55 0000110XXX YES YES NO B7 S56-S63 0000111XXX YES YES NO B8 - B119 follow the same pattern B120 S960-S967 1111000XXX YES YES NO B121 S968-S975 1111001XXX YES YES NO B122 S976-S983 1111010XXX YES YES NO B123 S984-S991 1111011XXX YES YES NO B124 S992-S999 1111100XXX YES YES NO ©2015-2018 Microchip Technology Inc 7 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Table 3: SST38VF6403and SST38VF6404 Memory Maps (Continued) (2 of 2) B125 S1000-S1007 1111101XXX YES YES NO B126 S1008-S1015 1111110XXX YES YES NO Block1,2 B1275, 7 Sectors3 S1016 Address A21-A124 1111111000 VPB5 YES NVPB5 YES WP#7 NO S1017 1111111001 YES YES NO S1018 1111111010 YES YES NO S1019 1111111011 YES YES NO S1020 1111111100 YES YES NO S1021 1111111101 YES YES NO S1022 1111111110 YES YES YES S1023 1111111111 YES YES YES T3.0 20005015 1. 2. 3. 4. 5. Each block, B0-B127 is 32KWord. Each block consists of eight sectors. Each sector, S0-S1023 is 4KWord. X = 0 or 1. Block Address (BA) = A21 - A15; Sector Address (SA) = A21 - A12 Each block has an associated VPB and NVPB, except for some blocks in SST38VF6403 and SST38VF6404. In SST38VF6403, Block B0 does not have a single VPB or NVPB for all 32 KWords. Instead, each sector (4 KWord) in Block B0 has its own VPB and NVPB. In SST38VF6404, Block B127 does not have a single VPB or NVPB for all 32 KWords. Instead, each sector (4 KWord) in Block B127 has its own VPB and NVPB. 6. The 8KWord boot block consists of S0 and S1 in Block B0. 7. The 8KWord boot block consists of S1022 and S1023 in Block B127. ©2015-2018 Microchip Technology Inc 8 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Device Operation The memory operations functions of these devices are initiated using commands written to the device using standard microprocessor Write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST38VF6401/6402/6403/6404 also have the Auto Low Power mode which puts the device in a near-standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 4 mA to typically 3 µA. The Auto Low Power mode reduces the typical IDD active read current to the range of 2 mA/MHz of Read cycle time. The device requires no access time to exit the Auto Low Power mode after any address transition or control signal transition used to initiate another Read cycle. The device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high. Read The Read operation of the SST38VF6401/6402/6403/6404 is controlled by CE# and OE#, both of which have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to Figure 5, the Read cycle timing diagram, for further details. Page Read The Page Read operation utilizes an asynchronous method that enables the system to read data from the SST38VF6401/6402/6403/6404 at a faster rate. This operation allows users to read a four-word page of data at an average speed of 41.25 ns per word. In Page Read, the initial word read from the page requires TACC to be valid, while the remaining three words in the page require only TPACC. All four words in the page have the same address bits, A21-A2, which are used to select the page. Address bits A1 and A0 are toggled, in any order, to read the words within the page. The Page Read operation of the SST38VF6401/6402/6403/6404 is controlled by CE# and OE#. Both CE# and OE# must be low for the system to obtain data from the output pins. CE# controls device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to Figure 6, the Page Read cycle timing diagram, for further details. Word-Program Operation The SST38VF6401/6402/6403/6404 can be programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 10 µs. See Figures 7 and 8 for WE# and CE# controlled Program operation timing diagrams and Figure 24 for flowcharts. ©2015-2018 Microchip Technology Inc 9 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 During the Program operation, the only valid reads are Data# Polling, Toggle Bits, and RY/BY#. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. During the command sequence, WP# should be statically held high or low. When programming more than a few words, Microchip recommends Write-Buffer Programming. Write-Buffer Programming The SST38VF6401/6402/6403/6404 offer Write-Buffer Programming, a feature that enables faster effective word programming. To use this feature, write up to 16 words with the Write-to-Buffer command, then use the Program Buffer-to-Flash command to program the Write-Buffer to memory. The Write-to-Buffer command consists of between 5 and 20 write cycles. The total number of write cycles in the Write-to-Buffer command sequence is equal to the number of words to be written to the buffer plus four. The first three cycles in the command sequence tell the device that a Write-to-Buffer operation will begin. The fourth cycle tells the device the number of words to be written into the buffer and the block address of these words. Specifically, the write cycle consists of a block address and a data value called the Word Count (WC), which is the number of words to be written to the buffer minus one. If the WC is greater than 15, the maximum buffer size minus 1, then the operation aborts. For the fifth cycle, and all subsequent cycles of the Write-to-Buffer command, the command sequence consists of the addresses and data of the words to be written into the buffer. All of these cycles must have the same A21 - A4 address, otherwise the operation aborts. The number of Write cycles required is equal to the number of words to be written into the Write-Buffer, which is equal to WC plus one. The correct number of Write cycles must be issued or the operation will abort. Each Write cycle decrements the Write-Buffer counter, even if two or more of the Write cycles have identical address values. Only the final data loaded for each buffer location is held in the Write-Buffer. Once the Write-to-Buffer command sequence is completed, the Program Buffer-to-Flash command should be issued to program the Write-Buffer contents to the specified block in memory. The block address (i.e. A21 - A15) in this command must match the block address in the 4th write cycle of the Write-to-Buffer command or the operation aborts. See Table 11 for details on Write-to-Buffer and Program-Buffer-to-Flash commands. While issuing these command sequences, the Write-Buffer Programming Abort detection bit (DQ1) indicates if the operation has aborted. There are several cases in which the device can abort: • • • • • ©2015-2018 Microchip Technology Inc In the fourth write cycle of the Write-to-Buffer command, if the WC is greater than 15, the operation aborts. In the fifth and all subsequent cycles of the Write-to-Buffer command, if the address values, A21 A4, are not identical, the operation aborts. If the number of write cycles between the fifth to the last cycle of the Write-to-Buffer command is greater than WC +1, the operation aborts. After completing the Write-to-Buffer command sequence, issuing any command other than the Program Buffer-to-Flash command, aborts the operation. Loading a block address, i.e. A21-A15, in the Program Buffer-to-Flash command that does not match the block address used in the Write-to-Buffer command aborts the operation. 10 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 If the Write-to-Buffer or Program Buffer-to-Flash operation aborts, then DQ1 = 1 and the device enters Write-Buffer-Abort mode. To execute another operation, a Write-to-Buffer Abort-Reset command must be issued to clear DQ1 and return the device to standard read mode. After the Write-to-Buffer and Program Buffer-to-Flash commands are successfully issued, the programming operation can be monitored using Data# Polling, Toggle Bits, and RY/BY#. Sector/Block-Erase Operations The Sector-Erase and Block-Erase operations allow the system to erase the device on a sector-bysector, or block-by-block, basis. The SST38VF6401/6402/6403/6404 offer both Sector-Erase and BlockErase modes. The Sector-Erase architecture is based on a sector size of 4 KWords. The Sector-Erase command can erase any 4 KWord sector (S0 - S1023). The Block-Erase architecture is based on block size of 32 KWords. In SST38VF6401 and SST38VF6402 devices, the Block-Erase command can erase any 32KWord Block (B0-B127). For the non-uniform boot block devices, SST38VF6403 and SST38VF6404, the Block-Erase command can erase any 32 KWord block except the block that contains the boot area. In the boot area, Block-Erase behaves like Sector-Erase, and only erases a 4KWord sector. For the SST38VF6403 device, a BlockErase executed on the Boot Block (B0), will result in the device erasing a 4KWord sector in B0 located at A21-A12. For the SST38VF6404 device, a Block-Erase executed on the Boot Block (B127), will result in the device erasing a 4KWord sector in B127 located at A21-A12. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (50H or 30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. The RY/BY# pin can also be used to monitor the erase operation. For more information, see Figures 14 and 15 for timing waveforms and Figure 29 for the flowchart. Any commands, other than Erase-Suspend, issued during the Sector- or Block-Erase operation are ignored. Any attempt to Sector- or Block-Erase memory inside a block protected by Volatile Block Protection, Non-Volatile Block Protection, or WP# (low) will be ignored. During the command sequence, WP# should be statically held high or low. Erase-Suspend/Erase-Resume Commands The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read or programmed into any sector or block that is not engaged in an Erase operation. The operation is executed with a one-byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode within 20 µs (max) after the Erase-Suspend command had been issued. Valid data can be read, using a Read or Page Read operation, from any sector or block that is not being erased. Reading at an address location within Erase-Suspended sectors or blocks will output DQ2 toggling and DQ6 at ‘1’. While in Erase-Suspend, a Word-Program or Write-Buffer Programming operation is allowed anywhere except the sector or block selected for Erase-Suspend. ©2015-2018 Microchip Technology Inc 11 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 To resume a suspended Sector-Erase or Block-Erase operation, the system must issue the EraseResume command. The operation is executed by issuing one byte command sequence with EraseResume command (30H) at any address in the last Byte sequence. When an erase operation is suspended, or re-suspended, after resume the cumulative time needed for the erase operation to complete is greater than the erase time of a non-suspended erase operation. If the hold time from Erase-Resume to the next Erase- Suspend operation is less than 200µs, the accumulative erase time can become very long Therefore, after issuing an Erase-Resume command, the system must wait at least 200µs before issuing another Erase-Suspend command. The EraseResume command will be ignored until any program operations initiated during Erase-Suspend are complete. Bypass mode can be entered while in Erase-Suspend, but only Bypass Word-Program is available for those sectors or blocks that are not suspended. Bypass Sector-Erase, Bypass Block-Erase, and Bypass Chip-Erase, Erase-Suspend, and Erase-Resume are not available. In order to resume an Erase operation, the Bypass mode must be exited before issuing Erase-Resume. For more information about Bypass mode, see “Bypass Mode” on page 17. Chip-Erase Operation The SST38VF6401/6402/6403/6404 devices provide a Chip-Erase operation, which erases the entire memory array to the ‘1’ state. This operation is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid reads are Toggle Bit, Data# Polling, or RY/BY#. See Table 11 for the command sequence, Figure 13 for timing diagram, and Figure 29 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. If WP# is low, or any VPBs or NVPBs are in the protect state, any attempt to execute a Chip-Erase operation is ignored. During the command sequence, WP# should be statically held high or low. Write Operation Status Detection To optimize the system Write cycle time, the SST38VF6401/6402/6403/6404 provide two software means to detect the completion of a Write (Program or Erase) cycle The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system. Therefore, Data# Polling or Toggle Bit maybe be read concurrent with the completion of the write cycle. If this occurs, the system may possibly get an incorrect result from the status detection process. For example, valid data may appear to conflict with either DQ7 or DQ6. To prevent false results, upon detection of failures, the software routine should loop to read the accessed location an additional two times. If both reads are valid, then the device has completed the Write cycle, otherwise the failure is valid. For the Write-Buffer Programming feature, DQ1 informs the user if either the Write-to-Buffer or Program Buffer-to-Flash operation aborts. If either operation aborts, then DQ1 = 1. DQ1 must be cleared to '0' by issuing the Write-to-Buffer Abort Reset command. The SST38VF6401/6402/6403/6404 also provide a RY/BY# signal. This signal indicates the status of a Program or Erase operation. ©2015-2018 Microchip Technology Inc 12 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 If a Program or Erase operation is attempted on a protected sector or block, the operation will abort. After the device initiates an abort, the corresponding Write Operation Status Detection Bits will stay active for approximately 200ns (program or erase) before the device returns to read mode. For the status of these bits during a Write operation, see Table 4. Data# Polling (DQ7) When the SST38VF6401/6402/6403/6404 are in an internal Program operation, any attempt to read DQ7 will produce the complement of true data. For a Program Buffer-to-Flash operation, DQ7 is the complement of the last word loaded in the Write-Buffer using the Write-to-Buffer command. Once the Program operation is completed, DQ7 will produce valid data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid. Valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During an internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 11 for Data# Polling timing diagram and Figure 26 for a flowchart. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating ‘1’s and ‘0’s, i.e., toggling between ‘1’ and ‘0’. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling, and the device is then ready for the next operation. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector or Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector or block is being actively erased or erase-suspended. Table 4 shows detailed bit status information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of Write operation. See Figure 12 for Toggle Bit timing diagram and Figure 26 for a flowchart. DQ1 If an operation aborts during a Write-to-Buffer or Program Buffer-to-Flash operation, DQ1 is set to ‘1’. To reset DQ1 to ‘0’, issue the Write-to-Buffer Abort Reset command to exit the abort state. A power-off/ power-on cycle or a Hardware Reset (RST# = 0) will also clear DQ1. ©2015-2018 Microchip Technology Inc 13 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 RY/BY# The RY/BY# pin can be used to determine the status of a Program or Erase operation. The RY/BY# pin is valid after the rising edge of the final WE# pulse in the command sequence. If RY/BY# = 0, then the device is actively programming or erasing. If RY/BY# = 1, the device is in Read mode. The RY/BY# pin is an open drain output pin. This means several RY/BY# can be tied together with a pull-up resistor to VDD.. Table 4: Write Operation Status Status DQ71 DQ6 DQ21 DQ1 RY/BY#2 Normal Operation Standard Program DQ7# Toggle No Toggle 0 0 Standard Erase 0 Toggle Toggle N/A 0 Erase-Suspend Mode Read from Erase-Suspended Sector/Block 1 No toggle Toggle N/A 1 Read from Non- EraseSuspended Sector/Block Data Data Data Data 1 Program DQ7# Toggle N/A N/A 0 Busy DQ7#3 DQ7#3 Toggle N/A 0 0 Toggle N/A 1 Program Buffer-to-Flash Abort 0 T4.0 20005015 1. DQ7 and DQ2 require a valid address when reading status information. 2. RY/BY# is an open drain pin. RY/BY# is high in Read mode, and Read in Erase-Suspend mode. 3. During a Program Buffer-to-Flash operation, the datum on the DQ7 pin is the complement of DQ7 of the last word loaded in the Write-Buffer using the Write-to-Buffer command. Data Protection The SST38VF6401/6402/6403/6404 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. ©2015-2018 Microchip Technology Inc 14 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Hardware Block Protection The SST38VF6402 and SST38VF6404 devices support top hardware block protection, which protects the top boot block of the device. For SST38VF6402, the boot block consists of the top 32 KWord block, and for SST38VF6404 the boot block consists of the top two 4 KWord sectors (8 KWord total). The SST38VF6401 and SST38VF6403 devices support bottom hardware block protection, which protects the bottom boot block of the device. For SST38VF6401, the boot block consists of the bottom 32 KWord block, and for SST38VF6403 the Boot Block consists of the bottom two 4 KWord sectors (8 KWord total). The boot block addresses are described in Table 5. Table 5: Boot Block Address Ranges Product Size Address Range 32 KW 000000H-007FFFH 32 KW 3F8000H-3FFFFFH 8 KW 000000H-001FFFH 8 KW 3FE000H-3FFFFFH Bottom Boot Uniform SST38VF6401 Top Boot Uniform SST38VF6402 Bottom Boot Non-Uniform SST38VF6403 Top Boot Non-Uniform SST38VF6404 T5.0 20005015 Program and Erase operations are prevented on the Boot Block when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor. When WP# is high, the Boot Block is unprotected, which allows Program and Erase operations on that area. Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place. See Figure 20 for more information. The interrupted Erase or Program operation must be re-initiated after the device resumes normal operation mode to ensure data integrity. Software Data Protection (SDP) The SST38VF6401/6402/6403/6404 devices implement the JEDEC approved Software Data Protection (SDP) scheme for all data alteration operations, such as Program and Erase. These devices are shipped with the Software Data Protection permanently enabled. See Table 11 for the specific software command codes. All Program operations require the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations. SDP for Erase operations is similar to Program, but a six-byte load sequence is required for Erase operations. During SDP command sequence, invalid commands will abort the device to read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. ©2015-2018 Microchip Technology Inc 15 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 The SST38VF6401/6402/6403/6404 devices provide Bypass Mode, which allows for reduced Program and Erase command sequence lengths. In this mode, the SDP portion of Program and Erase command sequences are omitted. See “Bypass Mode” on page 17. for further details. Common Flash Memory Interface (CFI) The SST38VF6401/6402/6403/6404 contain Common Flash Memory Interface (CFI) information that describes the characteristics of the device. In order to enter the CFI Query mode, the system can either write a one-byte sequence using a standard CFI Query Entry command, or a three-bye sequence using the SST CFI Query Entry command. A comparison of these two commands is shown in Table 11. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 13 through 16. The system must write the CFI Exit command to return to Read mode. Note that the CFI Exit command is ignored during an internal Program or Erase operation. See Table 11 for software command codes, Figures 17 and 18 for timing waveform, and Figures 27 and 28 for flowcharts. Product Identification The Product Identification mode identifies the devices as the SST38VF6401, SST38VF6402, SST38VF6403, or SST38VF6404, and the manufacturer as SST. See Table 6 for specific address and data information. Product Identification mode is accessed through software operations. The software Product Identification operations identify the part, and can be useful when using multiple manufacturers in the same socket. For details, see Table 11 for software operation, Figure 16 for the software ID Entry and Read timing diagram, and Figure 27 for the software ID Entry command sequence flowchart. Table 6: Product Identification Address Data 0000H BFH SST38VF6401 0001H 536B SST38VF6402 0001H 536A SST38VF6403 0001H 536D SST38VF6404 0001H 536C Manufacturer’s ID Device ID T6.0 20005015 While in Product Identification mode, the Read Block Protection Status command determines if a block is protected. The status returned indicates if the block has been protected, but does not differentiate between Volatile Block Protection and Non-Volatile Block Protection. See Table 11 for further details. The Read-Irreversible Block-Lock Status command indicates if the Irreversible Block Command has been issued. If DQ0 = 0, then the Irreversible Lock command has been previously issued. In order to return to the standard Read mode, the software Product Identification mode must be exited. The exit is accomplished by issuing the software ID Exit command sequence, which returns the device to the Read mode. See Table 11 for software command codes, Figure 18 for timing waveform, and Figures 27 and 28 for flowcharts. ©2015-2018 Microchip Technology Inc 16 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Security ID The SST38VF6401/6402/6403/6404 devices offer a Security ID feature. The Secure ID space is divided into two segments — one factory programmed 128 bit segment and one user programmable 256 word segment. See Table 7 for address information. The first segment is programmed and locked and contains a 128 bit Unique ID which uniquely identifies the device. The user segment is left un-programmed for the customer to program as desired. Table 7: Address Range for Sec ID Unique ID User Size Address 128 bits 000H – 007H 256 W 100H – 1FFH T7.1 20005015 The user segment of the Security ID can be programmed in several ways. For smaller datasets, use the Security ID Word-Program command for word-programming. To program larger sets of data more quickly, use the SEC ID Entry command to enter the Secure ID space. Once in the Secure ID space, use the Write-Buffer Programming or Bypass Mode feature. Note that the Word-Programming command can also be used while in this mode. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling to detect end of Write. Once the programming is complete, lock the Sec ID by issuing the User Sec ID Program LockOut command or by programming bit ‘0’ in the PSR with the PSR Program command. Locking the Sec ID disables any corruption of this space. Note that regardless of whether or not the Sec ID is locked, the Sec ID segments can not be erased. The Secure ID space can be queried by executing a three-byte command sequence with Enter Sec ID command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 11 for software commands and Figures 27 and 28 for flow charts. Bypass Mode Bypass mode shortens the time needed to issue program and erase commands by reducing these commands to two write cycles each. After using the Bypass Entry command to enter the Bypass mode, only the Bypass Word-Program, Bypass Sector Erase, Bypass Block Erase, Bypass Chip Erase, Erase-Suspend, and Erase-Resume commands are available. The Bypass Exit command exits Bypass mode. See Table 11 for further details. Entering Bypass Mode while already in Erase-Suspend limits the available commands. See “EraseSuspend/Erase-Resume Commands” on page 11. for more information. ©2015-2018 Microchip Technology Inc 17 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Protection Settings Register (PSR) The Protection Settings Register (PSR) is a user-programmable register that allows for further customization of the SST38VF6401/6402/6403/6404 protection features. The 16-bit PSR provides four One Time Programmable (OTP) bits for users, each of which can be programmed individually. However, once an OTP bit is programmed to ‘0’, the value cannot be changed back to a ‘1’. The other 12 bits of the PSR are reserved. See Table 8 for the definition of all 16-bits of the PSR. Table 8: PSR Bit Definitions Bit DQ15-DQ5 Default from Factory Definition FFFh Reserved DQ4 1 VPB power-up / hardware reset state 0 = all protected 1 = all unprotected DQ3 1 Reserved DQ2 1 Password mode 0 = Password only mode 1 = Pass-Through mode DQ1 1 Pass-Through mode 0 = Pass-Through only mode 1 = Pass-Through mode DQ0 1 SEC ID Lock Out Bit 0 = locked 1 = unlocked T8.0 20005015 Note that DQ4, DQ2, DQ1, DQ0 do not have to be programmed at the same time. In addition, DQ2 and DQ1 cannot both be programmed to ‘0’. The valid combinations of states of DQ2 and DQ1 are shown in Table 9. Table 9: Valid DQ2 and DQ1 Combinations Combination Definition DQ2, DQ1 = 11 Pass-Through mode (factory default) DQ2, DQ1 = 10 Pass-Through only mode DQ2, DQ1 = 01 Password only mode DQ2, DQ1 = 00 Not Allowed T9.0 20005015 The PSR can be accessed by issuing the PSR Entry command. Users can then use the PSR Program and PSR Read commands. The PSR Exit command must be issued to leave this mode. See Table 11 for further details. ©2015-2018 Microchip Technology Inc 18 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Individual Block Protection The SST38VF6401/6402/6403/6404 provide two methods for Individual Block protection: Volatile Block Protection and Non-Volatile Block Protection. Data in protected blocks cannot be altered. Volatile Block Protection The Volatile Block Protection feature provides a faster method than Non-Volatile Protection to protect and unprotect 32 KWord blocks. Each block has it’s own Volatile Protection Bit (VPB). In the SST38VF6401/2, the 32 KWord boot block also has a VPB. In the SST38VF6403/4 devices, each of the two 4 KWord sectors in the 8 KWord boot area has it's own VPB. After using the Volatile Block Protection Mode Entry command to enter the Volatile Block Protection mode, individual VPBs can be set or reset with VPB Set/Clear, or be read with VPB Status Read. If the VPB is ‘0’, then the block is protected from Program and Erase. If the VPB is ‘1’, then the block is unprotected. The Volatile Block Protection Exit command must be issued to exit Volatile Block Protection mode. See Table 11 for further details on the commands and Figure 31 for a flow chart. If the device experiences a hardware reset or a power cycle, all the VPBs return to their default state as determined by user-programmable bit DQ4 in the PSR. If DQ4 is ‘0’, then all VPBs default to ‘0’ (protected). If DQ4 is ‘1’, then all VPBs default to ‘1’ (unprotected). Non-Volatile Block Protection The Non-Volatile Block Protection feature provides protection to individual blocks using Non-Volatile Protection Bits (NVPBs). Each block has it’s own Non-Volatile Protection Bit. In the SST38VF6401/2, the 32 KWord boot block also has a it's own NVPB. In the SST38VF6403/4, each 4 KWord sector in the 8KWord boot area has it's own NVPB. All NVPBs come from the factory set to ‘1’, the unprotected state. Use the Non-Volatile Block Protection Mode Entry command to enter the Non-Volatile Block Protection mode. Once in this mode, the NVPB Program command can be used to protect individual blocks by setting individual NVPBs to ‘0’. The time needed to program an NVPB is two times TBP, which is a maximum of 20µs. The NVPB Status Read command can be used to check the protection state of an individual NVPB. To change an NVPB to ‘1’, the unprotected state, the NVPB must be erased using NVPBs Erase command. This command erases all NVPBs to ‘1’. NVPB Program should be used to set the NVPBs of any blocks that are to be protected before exiting the Non-Volatile Block Protection mode. See Table 11 and Figure 32 for further details. Upon a power cycle or hardware reset, the NVPBs retain their states. Memory areas that are protected using Non-Volatile Block Protection remain protected. The NVPB Program and NVPBs Erase commands are permanently disabled once the Irreversible Block Lock command is issued. See “Irreversible Block Locking” on page 22 for further information. ©2015-2018 Microchip Technology Inc 19 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Advanced Protection The SST38VF6401/6402/6403/6404 provide Advanced Protection features that allow users to implement conditional access to the NVPBs. Specifically, Advanced Protection uses the Global Lock Bit to protect the NVPBs. If the Global Lock bit is ‘0’ then all the NVPBs states are frozen and cannot be modified in any mode. If the Global Lock bit is ‘1’, then all the NVPBs can be modified in Non-Volatile Block Protection mode. After using the Global Lock of NVPBs Entry command to enter the Global Lock of NVPBs mode, the Global Lock Bit can be activated by issuing a Set Global Lock Bit command, which sets the Global Lock Bit to ‘0’. The Global Lock bit cannot be set to ‘1’ with this command. The status of the bit can be read with the Global Lock Bit Status command. Use the Global Lock of NVPBs Exit command to exit Global Lock of NVPBs mode. See Table 11 and Figure 33 for further details. The steps used to change the Global Lock Bit from '0' to'1,' to allow access to the NVPBs, depend on whether the device has been set to use Pass-Through or Password mode. When using Advanced Protection, select either Pass-Through only mode or Password only mode by programming the DQ2 and DQ1 bits in the PSR. Although the factory default is Pass-Through mode (DQ2 = 1, DQ1 = 1), the user should explicitly chose either Pass-Through only mode (DQ2 = 1, DQ1 = 0), or Password only mode (DQ2 = 0, DQ1 = 1). Keeping the SST38VF6401/6402/6403/6404 in the factory default Pass-Through mode leaves the device open to unauthorized changes of DQ2 and DQ1 in the PSR. See “Protection Settings Register (PSR)” on page 18. for more information about the PSR. Pass-Through Mode (DQ2, DQ1 = 1,0) The Pass-Through Mode allows the Global Lock Bit state to be cleared to ‘1’ by a power-down powerup sequence or a hardware reset (RST# pin = 0). No password is required in Pass-Through mode. To set the Global Lock Bit to ‘0’, use the Set Global Lock Bit command while in the Global Lock of NVPBs mode. Select the Pass-Through only mode by programming PSR bit DQ2 = 1 and DQ1 = 0. Password Mode (DQ2, DQ1 = 0,1) In the Password Mode, the Global Lock Bit is set to ‘0’ by the Set Global Lock Bit command, a powerdown power-up sequence, or a hardware reset (RST# pin = 0). Select the Password only mode by programming PSR bit DQ2 = 0 and DQ1 = 1. Note that when the PSR Program command is issued in Password mode, the Global Lock bit is automatically set to ‘0’. In contrast to the Pass-Through Mode, in the Password mode, the only way to clear the Global Lock Bit to ‘1’ is to submit the correct 64-bit password using the Submit Password command in Password Commands Mode. The words of the password can be submitted in any order as long as each 16 bit section of the password is matched with its correct address. After the entire 64 bit password is submitted, the device takes approximately 2 µs to verify the password. A subsequent Submit Password command cannot be issued until this verification time has elapsed. The 64-bit password must be chosen by the user before programming the DQ2 and DQ1 OTP bits of the PSR to choose Password Mode. The default 64 bit password on the device from the factory is FFFFFFFFFFFFFFFFh. Enter the Password Commands mode by issuing the Password Commands Entry command. Then, use the Password Program command to program the desired password. Use caution when programming the password because there is no method to reset the password to FFFFFFFFFFFFFFFFh. Once a password bit has been set to ‘0’, it cannot be changed back to ‘1’. See Table 11 for further details about Password-related commands. ©2015-2018 Microchip Technology Inc 20 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 The password can be read using the Password Read command to verify the desired password has been programmed. Microchip recommends testing the password before permanently choosing Password Mode. To test the password, do the following: 1. Enter the Global Lock of NVPBs mode. 2. Set the Global Lock Bit to ‘0’, and verify the value. 3. Exit the Global Lock of NVPBs mode. 4. Enter the Password Commands mode. 5. Submit the 64-bit password with the Submit Password command. 6. Wait 2 µs for the device to verify the password. 7. Exit the Password Commands mode. 8. Re-enter the Global Lock of NVPBs mode 9. Read the Global Lock Bit with the Global Lock Bit Status Read command. The Global Lock bit should now be ‘1’. After verifying the password, program the DQ2 and DQ1 OTP bits of the PSR to explicitly choose Password mode. Once the Password mode has been selected, the Password Read and Password Program commands are permanently disabled. There is no longer any method for reading or modifying the password. In addition, Microchip is unable to read or modify the password. If a Password Read command is issued while in Password mode, the data presented for each word of the password is FFFFh. If the Password Mode is not explicitly chosen in the PSR, then the password can still be read and modified. Therefore, Microchip strongly recommends that users explicitly choose Password Mode in the PSR. ©2015-2018 Microchip Technology Inc 21 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Irreversible Block Locking The SST38VF6401/6402/6403/6404 provides Irreversible Block Locking, a feature that allows users to customize the size of Read-Only Memory (ROM) on the device and provides more flexibility than OneTime Programmable (OTP) memory. Applying Irreversible Block Locking turns user-selected memory areas into ROM by permanently disabling Program and Erase operations to these chosen areas. Any area that becomes ROM cannot be changed back to Flash. Any memory blocks in the main memory, including boot blocks, can be irreversibly locked. In non-uniform boot block devices (SST38VF6403 and SST38VF6404) each 4 KW sector in the boot area can be irreversibly locked. If desired, all blocks in the main memory can be irreversibly locked. To use Irreversible Block Locking do the following: 1. Global Lock Bit should be ‘1’. The Irreversible Block Lock command is disabled when Global Lock Bit is ‘0’. 2. Enter the Non-Volatile Block Protection mode. 3. Use the NVPB Program command to protect only the blocks that are to be changed into ROM. 4. Exit the Non-Volatile Block Protection mode. 5. Issue the Irreversible Block Lock command (see Table 11 for details). The Irreversible Block Lock command can only be used once. Issuing the command after the first time has no effect on the device. Important: Once the Irreversible Block Lock command is used, the state of the NVPBs can no longer be changed or overridden. Therefore, the following features no longer have any effect on the device: • • • • • Global Lock of NVPBs feature Password feature NVPB Program command NVPB Erase command DQ2 and DQ1 of PSR In addition, WP# has no effect on any memory in the boot block area that has been irreversibly locked. To verify whether the Irreversible Block Lock command has already been issued, enter the Product ID mode and read address 5FEH. If DQ0 = 0, then Irreversible Block Lock has already been executed. When using this feature to determine if a specific block is ROM, use the NVPB Status Read. ©2015-2018 Microchip Technology Inc 22 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Operations Table 10: Operation Modes Selection Mode CE# OE# WE# RST# Read Program VIL VIL VIH H X VIL VIH VIL H VIL/VIH1 1 Erase VIL Standby Write Inhibit WP# VIL/VIH DQ Address DOUT AIN DIN AIN X2 Sector or block address, XXH for Chip-Erase VIH VIL H VIH X X VIH X High Z X X VIL X X X High Z/ DOUT X Product Identification X X VIH H X High Z/ DOUT X Reset X X X L X High Z X VIL VIH VIL H X See Table 11 See Table 11 Software Mode 1. WP# can be VIL when programming or erasing outside of the bootblock. WP# must be VIH when programming or erasing inside the bootblock area. 2. X can be VIL or VIH, but no other value. ©2015-2018 Microchip Technology Inc 23 T10.0 20005015 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Table 11: Software Command Sequence (1 of 3) Command Sequence Read3 Page Read3 1st Bus Cycle Addr1 Data2 WA Data WA0 Data0 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle Addr1 Data2 Addr1 Data2 Addr1 Data2 WA1 Data1 WA2 Data WA3 Data3 5th Bus Cycle 6th Bus Cycle 7th Bus Cycle Addr1 Data2 Addr1 Data2 Addr1 Data2 WAX Data WAX Data 50H 2 Word-Program 555H AAH 2AAH 55H 555H A0H WA Data 2AAH 55H BA 25H BA WC WAX Data Write-Buffer Programming Write-to-Buffer4 555H AAH Program Bufferto- Flash BAX 29H Write-to-Buffer Abort-Reset 555H AAH 2AAH 55H 555H F0H Bypass Mode Entry 555H AAH 2AAH 55H 555H 20H Bypass Word-Program XXXH A0H WA Data Bypass Sector Erase XXXH 80H SA 50H Bypass Block Erase XXXH 80H BA 30H Bypass Chip Erase XXXH 80H 555H 10H Bypass Mode Exit XXXH 90H XXXH 00H Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SAX Block-Erase6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAx 30H Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Erase Suspend XXXH B0H Erase Resume XXXH 30H 2AAH 55H 555H 88H XXH 00H Bypass Mode5 Erase Related Security ID SEC ID Entry7 555H AAH SEC ID Read3,8 WAX Data SEC ID Exit 555H AAH 2AAH 55H 555H 90H Software ID Exit /CFI Exit/SEC ID Exit9 555H AAH 2AAH 55H 555H F0H Software ID Exit /CFI Exit/SEC ID Exit9 XXH F0H User Security ID Word-Program10 555H AAH 2AAH 55H 555H A5H WAX Data User Security ID Program LockOut 555H AAH 2AAH 55H 555H 85H XXH 0000H ©2015-2018 Microchip Technology Inc 24 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Table 11: Software Command Sequence (Continued) (2 of 3) Command Sequence 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle Data2 Addr1 Data2 Addr1 Data2 555H AAH 2AAH 55H 555H 90H Manufacturer ID3,12 X00 BFH Device ID3,12 X01 2AAH 55H 555H F0H 555H E0H 555H C0H Addr1 4th Bus Cycle Addr1 Data2 5th Bus Cycle Addr1 Data2 6th Bus Cycle Addr1 Data2 7th Bus Cycle Addr1 Product Identification Software ID Entry11 Data BAX0213 Read Block Protection Status3 Data14 Read Irrevers- 5FEH ible Block Lock Status3 Data15 9FFH Data16 Software ID Exit 555H /CFI Exit/SEC ID Exit 9 AAH XXH F0H Read Global Lock Bit Status3 Software ID Exit /CFI Exit/SEC ID Exit9 Volatile Block Protection Volatile Block 555H Protection Mode Entry AAH 2AAH 55H Volatile Protection Bit (VPB) Set/Clear XXH A0H BAX17 Data VPB Status Read3 BAX Data18 Volatile Block Protection Mode Exit XXH 90H XXH 00H 18 Non-Volatile Block Protection Non-Volatile Block Protection Mode Entry 555H AAH 2AAH 55H Non-Volatile Protect Bit (NVPB) Program XXH A0H BAX17 00H Non-Volatile Protect Bits (NVPB) Erase19 XXH 80H 00H 30H NVPB Status Read3 BAX17 Data18 Non-Volatile Block Protection Mode Exit XXH 90H XXH 00H ©2015-2018 Microchip Technology Inc 25 DS20005015D Data2 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Table 11: Software Command Sequence (Continued) (3 of 3) Command Sequence 1st Bus Cycle Addr1 2nd Bus Cycle 3rd Bus Cycle Data2 Addr1 Data2 Addr1 Data2 555H 50H 555H 60H 00H PWD0 555H 40H 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle 7th Bus Cycle Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 01H PWD1 02H PWD2 03H PWD3 00H 29H XXH 00H Global Lock of NVPBs Global Lock of NVPBs Entry 555H AAH 2AAH 55H Set Global Lock Bit XXH A0H XXH 00H Global Lock Bit Status Read3 XXXH Data16 Global Lock of NVPBs Exit XXH 90H XXH 00H Password Commands Password Commands Mode Entry 555H AAH 2AAH 55H Password Program20 XXH A0H PWAX PWDx Password Read3 PWAX PWDX Submit Password21 00H 25H 00H 03H Password Commands Mode Exit XXH 90H XXH 00H Program and Settings Register (PSR) PSR Entry 555H AAH 2AAH 55H PSR Program 22 XXH A0H XXXH Data PSR Read3 XXH Data PSR Exit XXH 90H XXH 00H CFI Query Entry23 55H 98H SST CFI Query Entry23 555H AAH 2AAH 55H 555H 98H Software ID Exit 555H /CFI Exit/SEC ID Exit9 AAH 2AAH 55H 555H F0H Software ID Exit/CFI Exit/ SEC ID Exit9 F0H 2AAH 55H 555H 87H CFI XXH Irreversible Block Lock Irreversible Block Lock24 555H AAH T11.0 20005015 1. Address format A10-A0 (Hex). Addresses A11- A21 can be VIL or VIH, but no other value, for the SST38VF6401/6402/ 6403/6404 command sequence. 2. DQ15-DQ8 can be VIL or VIH, but no other value, for command sequence 3. All read commands are in Bold Italics. ©2015-2018 Microchip Technology Inc 26 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 4. Total number of cycles in this command sequence depends on the number of words to be written to the buffer. Additional words are written by repeating Write Cycle 5. Address (WAX) values for Write Cycle 6 and later must have the same A21-A4 values as WAX in Write Cycle 5. WC = Word Count. The value of WC is the number of words to be written into the buffer, minus 1. Maximum WC value is 15 (i.e. F Hex) 5. Erase-Suspend and Erase-Resume commands are also available in Bypass Mode. 6. For SST38VF6404, Sector-Erase or Block-Erase can be used to erase sectors S1016 - S1023. Use address SAx. Block Erase cannot be used to erase all 32kW of Block B127. For SST38VF6403, Sector-Erase or Block-Erase can be used to erase sectors S0 - S7. Use address SAx. Block Erase cannot be used to erase all 32kW of Block B0. 7. Once in SEC ID mode, the Word-Program, Write-Buffer Programming, and Bypass Word-Program features can be used to program the SEC ID area. 8. Unique ID is read with A3 = 0 (Address range = 000000H to 000007H), User portion of SEC ID is read with A8 = 1 (Address range = 000100H to 0001FFH). Lock-out Status is read with A7-A0 = FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. Lock status can also be checked by reading Bit ‘0’ in the PSR. 9. Both Software ID Exit operations are equivalent 10. If bits are not locked, then the user-programmable portion of the Sec ID can be programmed over the previously unprogrammed bits (Data =1) using the Sec ID mode again (bits programmed ‘0’ cannot be reversed to ‘1’). Valid WordAddresses for the user-programmable portion of the Sec ID are from 000100H-0001FFH. 11. The device does not remain in Software Product ID Mode if powered down. 12. With AMS-A1 =0; Manufacturer ID = 00BFH, is read with A0 = 0, SST38VF6401 Device ID = 536B, is read with A0 = 1, SST38VF6402 Device ID = 536A, is read with A0 = 1, SST38VF6403 Device ID = 536D, is ready with A0 = 1, SST38VF6404 Device ID = 536C, is read with A0 = 1. 13. BAX02: AMS-A15 = Block Address; A14-A8 = xxxxxx; A7-A0 = 02 14. Data = 00H unprotected block; Data = 01H protected block. 15. DQ0 = 0 means the Irreversible Block Lock command has been previously used. DQ0 = 1 means the Irreversible Block Lock command has not yet been used. 16. DQ0 = 0 means that the Global Lock Bit is locked. DQ0 = 1 means that the Global Lock Bit is unlocked. 17. For Non-Uniform Boot Block devices (i.e. 8 KWord size), in the boot area, use SAX = Sector Address (sector size = 4 KWord). 18. DQ0 = 0 means protected; DQ0 = 1 means unprotected 19. Erases all NVPBs to ‘1’ (unprotected) 20. Entire two-bus cycle sequence must be entered for each portion of the password. 21. Entire password sequence required for validation. The word order doesn’t matter as long as the Address and Data pair match. 22. Reserved register bits (DQ15-DQ5 and DQ3) must be ‘1’ during program. 23. CFI Query Entry and SST CFI Query Entry are equivalent. Both allow access to the same CFI tables. 24. Global Lock Bit must be ‘1’ before executing this command. Note: Table 11 uses the following abbreviations: X = Don’t care (VIL or VIH, but no other value. SAX = Sector Address; uses AMS-A12 address lines BAX= Block Address; uses AMS-A15 address lines WA = Word Address WC = Word Count PWAX = Password Address; PWAX = PWA0, PWA1, PWA2 or PWA3; A1 and A0 are used to select each 16-bit portion of the password PWDX = Password Data; PWDX = PSWD0, PWD1, PWD2, or PWD3 AMS = Most significant Address ©2015-2018 Microchip Technology Inc 27 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Table 12: Protection Priority for Main Array NVPB1 VPB1 Protection State of Block protect X protected X protect protected unprotect unprotect unprotected T12.0 20005015 1. X = protect or unprotect Table 13: CFI Query Identification String1 for SST38VF6401/6402/6403/6404 Address Data 10H 0051H 11H 0052H 12H 0059H 13H 0002H 14H 0000H 15H 0040H 16H 0000H 17H 0000H 18H 0000H 19H 0000H 1AH 0000H Description Query Unique ASCII string “QRY” Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM Extended Table (00H = none exits) 1. Refer to CFI publication 100 for more details. ©2015-2018 Microchip Technology Inc 28 T13.0 20005015 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Table 14: System Interface Information for SST38VF6401/6402/6403/6404 Address Data 1BH 0027H Description VDD Min (Program/Erase) 1CH 0036H VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1DH 0000H VPP min. (00H = no VPP pin) 1EH 0000H VPP max. (00H = no VPP pin) 1FH 0003H Typical time out for Word-Program 2N µs (23 = 8 µs) 20H 0003H Typical time out for min. size buffer program 2N µs (00H = not supported) 21H 0004H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) 22H 0005H Typical time out for Chip-Erase 2N ms (25 = 32 ms) 23H 0001H Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs) 24H 0003H Maximum time out for buffer program 2N times typical 25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) 26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts T14.0 20005015 Table 15: Device Geometry Information for SST38VF6401/6402/6403/6404 Address Data Description 27H 0017H Device size = 2N Bytes (17H = 23; 223 = 8 MByte) 28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface 29H 0000H 2AH 0005H Maximum number of bytes in multi-byte write = 2N (00H = not supported) 2BH 0000H 2CH 0002H Number of Erase Sector/Block sizes supported by device 2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size) 2EH 0003H y = 2047 + 1 = 2048 sectors (03FFH = 1023) 2FH 0000H 30H 0001H z = 32 x 256 Bytes = 8 KBytes/sector (0100H = 32) 31H 007FH Block Information (y + 1 = Number of blocks; z x 256B = block size) 32H 0000H y =127 + 1 = 128 blocks (007FH = 127) 33H 0000H 34H 0001H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256) T15.1 20005015 ©2015-2018 Microchip Technology Inc 29 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Table 16: Primary Vendor-Specific Extended Information for SST38VF6401/6402/6403/ 6404 Address Data 40H 0050H 41H 0052H Description Query-unique ASCII string “PRI” 42H 0049H 43H FFFFH Reserved 44H FFFFH Reserved 45H 0000H Reserved 46H 0002H Erase Suspend 0 = Not supported, 1 = Only read during Erase Suspend, 2 = Read and Program during Erase Suspend. 47H 0001H Individual Block Protection 0 = Not supported, 1 = Supported 48H 0000H Reserved 49H 0008H Protection 0008H = Advanced 4AH 0000H Simultaneous Operation 00 = Not supported 4BH 0000H Burst Mode 00 = Not supported 4CH 0001H Page Mode 00 = Not supported, 01 = 4 Word page. 4DH 0000H Acceleration Supply Minimum 00 = Not supported 4EH 0000H Acceleration Supply Maximum 00 = Not supported 4FH 00XXH Top / Bottom Boot Block 02H = 8 KWord Bottom Boot 03H = 8 KWord Top Boot 04H = Uniform (32 KWord) Bottom Boot 05H = Uniform (32 KWord) Top Boot 50H 0000H Program Suspend 00H = Not Supported, 01H = Supported T16.1 20005015 ©2015-2018 Microchip Technology Inc 30 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage ( 100 µs VDD min VDD 0V VIH RESET# TRHR > 50ns CE# 1309 F37.0 Figure 4: Power-Up Diagram ©2015-2018 Microchip Technology Inc 32 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 DC Characteristics Table 20: DC Operating Characteristics VDD = 2.7-3.6V1 Limits Symbol Parameter IDD Min Max Units Test Conditions Address input=VILT/VIHT2, VDD=VDD Max Power Supply Current Read3 18 Intra-Page Read @5 MHz 2.5 mA CE#=VIL, OE#=WE#=VIH Intra-Page Read @40 MHz 20 mA CE#=VIL, OE#=WE#=VIH Program and Erase 35 mA CE#=WE#=VIL, OE#=VIH Program-Write-Buffer-toFlash 50 mA CE#=WE#=VIL, OE#=VIH mA CE#=VIL, OE#=WE#=VIH at f= 5 MHz ISB Standby VDD Current 30 µA CE#=VIHC, VDD=VDD Max IALP Auto Low Power 20 µA CE#=VILC, VDD=VDD Max All inputs=VSS or VDD, WE#=VIHC ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILIW Input Leakage Current on WP# pin and RST# 10 µA WP#=GND to VDD or RST#=GND to VDD ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max VIH Input High Voltage 0.7VDD V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max VOL Output Low Voltage V IOL=100 µA, VDD=VDD Min VOH Output High Voltage V IOH=-100 µA, VDD=VDD Min 0.2 VDD-0.2 T20.0 20005015 1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C (room temperature), and VDD = 3V. Not 100% tested. 2. See Figure 27 3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V. Table 21: Capacitance (TA = 25°C, f=1 Mhz, other pins open) Parameter Description CI/O1 CIN1 Test Condition Maximum I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF T21.0 20005015 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 22: Reliability Characteristics Symbol Parameter Minimum Specification Units Test Method NEND1,2 Endurance 100,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Years JEDEC Standard A103 ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78 T22.0 20005015 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as 100,000 cycles minimum per block. ©2015-2018 Microchip Technology Inc 33 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 AC Characteristics Table 23: Read Cycle Timing Parameters VDD = 2.7-3.6V Symbol Parameter Min Max Units TRC Read Cycle Time TCE Chip Enable Access Time TAA Address Access Time 90 ns TPACC Page Access Time 25 ns TOE Output Enable Access Time TCLZ1 CE# Low to Active Output 0 TOLZ1 OE# Low to Active Output 0 TCHZ1 CE# High to High-Z Output TOHZ1 OE# High to High-Z Output TOH1 Output Hold from Address Change TRP1 RST# Pulse Width 500 ns TRHR1 RST# High before Read 50 ns TRYE1,2 RST# Pin Low to Read Mode 20 µs TRY1 RST# Pin Low to Read Mode – not during Program or Erase algorithms. 500 ns TRPD TRB1 1 90 ns 90 ns 25 ns ns ns 20 ns 20 ns 0 RST# Input Low to Standby mode 20 RY / BY# Output high to CE# / OE# pin Low 0 ns µs ns T23.0 20005015 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase, and Program operations. This parameter does not apply to Chip-Erase operations. ©2015-2018 Microchip Technology Inc 34 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Table 24: Program/Erase Cycle Timing Parameters Symbol Parameter TBP Word-Program Time Min Max Units 10 TWBP1 µs Program Buffer-to-Flash Time TAS Address Setup Time 0 40 µs ns TAH Address Hold Time 30 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH2 WE# Pulse Width High 30 ns TCPH2 CE# Pulse Width High 30 ns TDS Data Setup Time 30 ns TDH2 Data Hold Time 0 TIDA2 Software ID, Volatile Protect, Non-Volatile Protect, Global Lock Bit, Password mode, Lock Bit, Bypass Entry, and Exit Times 150 ns TSE Sector-Erase 25 ms TBE Block-Erase 25 ms TSCE Chip-Erase 50 ms TBUSY CE# High or WE# High to RY / BY# Low ns 90 ns T24.0 20005015 1. Effective programming time is 2.5 µs per word if 16-words are programmed during this operation. 2. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2015-2018 Microchip Technology Inc 35 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 TAA TRC ADDRESS AMS-0 TCE CE# TOE OE# WE# DQ15-0 TOHZ TOLZ VIH TCLZ HIGH-Z TCHZ TOH DATA VALID HIGH-Z DATA VALID TRB RY/BY# 1309 F03.1 Note: AMS = Most significant address Figure 5: Read Cycle Timing Diagram Same Page ADDRESS AMS-2 Ax A1 - A0 Ax TPACC TAA DQ15-0 Ax Ax TPACC TPACC DATA VALID DATA VALID DATA VALID DATA VALID CE# OE# RY/BY# 1309 F24.3 Note: AMS = Most significant address AMS = A21 for SST38VF6401/6402/6403/6404 Figure 6: Page Read Timing Diagram ©2015-2018 Microchip Technology Inc 36 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 555 TAH 2AA 555 ADDR TWP TDH WE# TAS TDS TWPH OE# TCH CE# TCS DQ15-0 XXAA XX55 XXA0 SW0 SW1 SW2 DATA WORD (ADDR/DATA) RY/BY# TBUSY 1309 F04.1 Note: AMS = Most significant address AMS = A21 for SST38VF6401/6402/6403/6404 WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. X can be VIL or VIH, but no other value. Figure 7: WE# Controlled Program Cycle Timing Diagram ©2015-2018 Microchip Technology Inc 37 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 555 TAH 2AA 555 ADDR TCP TDH CE# TAS TDS TCPH OE# TCH WE# TCS DQ15-0 XXAA XX55 XXA0 SW0 SW1 SW2 DATA WORD (ADDR/DATA) RY/BY# TBUSY 1309 F05.1 Note: AMS = Most significant address AMS = A21 for SST38VF6401/6402/6403/6404 WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. Figure 8: CE# Controlled Program Cycle Timing Diagram ©2015-2018 Microchip Technology Inc 38 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 FILL WRITE BUFFER WITH DATA ADDRESS AMS-0 555 2AA BA BA WAX WAX CE# OE# TWP WE# DQ15-0 XXAA XX55 XX25 WC SW0 SW1 SW2 SW3 DATA SW4 DATAn SWn RY/BY# 1309 F34.2 Note: BA= Block Address WAx = Word Address WC = Word Count DATAn = nth Data Figure 9: WE# Controlled Write-Buffer Cycle Timing Diagram TWBP BA ADDRESS AMS-0 CE# OE# TWP WE# TAS DQ15-0 TDH 29H TBusy RY/BY# 1309 F35.1 Note: BA= Block Address Figure 10:WE# Controlled Program-Write-Buffer-to-Flash Cycle Timing Diagram ©2015-2018 Microchip Technology Inc 39 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 ADDRESS AMS-0 TCE CE# TOEH TOES OE# TOE WE# DQ7 DATA DATA# DATA# DATA 1309 F06.1 Note: AMS = Most significant address AMS = A21 for SST38VF6401/6402/6403/6404 Figure 11: Data# Polling Timing Diagram ADDRESS AMS-0 TCE CE# TOES TOEH OE# TOE WE# DQ6 and DQ2 TWO READ CYCLES WITH SAME OUTPUTS 1309 F07.0 Note: AMS = Most significant address AMS = A21 for SST38VF6401/6402/6403/6404 Figure 12:Toggle Bits Timing Diagram ©2015-2018 Microchip Technology Inc 40 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 TSCE SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 555 2AA 555 555 2AA 555 CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 SW0 SW1 SW2 SW3 SW4 SW5 TBUSY RY/BY# 1309 F08.1 Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 24) AMS = Most significant address AMS = A21 for SST38VF6401/6402/6403/6404 WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. Figure 13:WE# Controlled Chip-Erase Timing Diagram ©2015-2018 Microchip Technology Inc 41 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 TBE SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS AMS-0 555 2AA 555 555 2AA BAX CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 SW0 SW1 SW2 SW3 SW4 XX30 SW5 TBusy RY/BY# 1309 F09.1 Note: This device also supports CE# controlled Block-Erase operation The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 24) BAX = Block Address AMS = Most significant address AMS = A21 for SST38VF6401/6402/6403/6404 WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. Figure 14:WE# Controlled Block-Erase Timing Diagram ©2015-2018 Microchip Technology Inc 42 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 TSE SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS AMS-0 555 2AA 555 555 2AA SAX CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50 SW0 SW1 SW2 SW3 SW4 SW5 TBUSY RY/BY# 1309 F10.1 Note: This device also supports CE# controlled Sector-Erase operation The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 24) SAX = Sector Address AMS = Most significant address AMS = A21 for SST38VF6401/6402/6403/6404 WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. X can be VIL or VIH, but no other value. Figure 15:WE# Controlled Sector-Erase Timing Diagram ©2015-2018 Microchip Technology Inc 43 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Three-Byte Sequence for Software ID Entry ADDRESS AMS-0 555 2AA 555 0000 0001 CE# OE# TIDA TWP WE# TAA TWPH DQ15-0 XXAA SW0 XX55 XX90 SW1 00BF Device ID SW2 1309 F11.0 Note: Device ID = 536B for SST38VF6401, 536A for SST38VF6402, 536D for SST38VF6403, 536C for SST38VF6404 AMS = Most significant address AMS = A21 for SST38VF6401/6402/6403/6404 WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. Figure 16:Software ID Entry and Read ADDRESS AMS-0 55H CE# OE# TWP TIDA WE# TAA DQ15-0 98H 1309 F12.2 Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. AMS = Most significant address AMS = A21 for SST38VF6401/6402/6403/6404 Figure 17:CFI Query Entry and Read ©2015-2018 Microchip Technology Inc 44 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS AMS-0 555 DQ15-0 2AA XXAA 555 XX55 XXF0 TIDA CE# OE# TWP WE# TWHP SW0 SW1 SW2 1309 F13.0 Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. AMS = Most significant address AMS = A21 for SST38VF6401/6402/6403/6404 Figure 18:Software ID Exit/CFI Exit THREE-BYTE SEQUENCE FOR SEC ID ENTRY ADDRESS AMS-0 555 2AA 555 CE# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX88 SW0 SW1 SW2 1309 F14.1 Note: AMS = Most significant address AMS = A21 for SST38VF6401/6402/6403/6404 WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. X can be VIL or VIH, but no other value. Figure 19:Sec ID Entry ©2015-2018 Microchip Technology Inc 45 DS20005015D 64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 TRY TRP RST# TRHR CE#/OE# RY/BY# 1309 F15.2 Figure 20:RST# Timing Diagram (When no internal operation is in progress) TRP RST# TRYE CE#/OE# TRB RY/BY# 1309 F16.2 Figure 21:RST# Timing Diagram (During Program or Erase operation) VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1309 F17.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10%  90%) are