SST39VF020-70-4C-NHE-T

1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet The SST39LF010, SST39LF020, SST39LF040 and SST39VF010, SST39VF020, SST39VF040 are 128K x8, 256K x8 and 5124K x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF010/020/040 devices write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF010/020/040 devices write with a 2.7-3.6V power supply. The devices conform to JEDEC standard pinouts for x8 memories. Features • Organized as 128K x8 / 256K x8 / 512K x8 • Single Voltage Read and Write Operations – 3.0-3.6V for SST39LF010/020/040 – 2.7-3.6V for SST39VF010/020/040 • Fast Erase and Byte-Program: – Sector-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 2 seconds (typical) for SST39LF/VF010 4 seconds (typical) for SST39LF/VF020 8 seconds (typical) for SST39LF/VF040 • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption (typical values at 14 MHz) – Active Current: 5 mA (typical) – Standby Current: 1 µA (typical) • Sector-Erase Capability – Uniform 4 KByte sectors • Fast Read Access Time: – 55 ns for SST39LF010/020/040 – 70 ns for SST39VF010/020/040 • Latched Address and Data • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts and command sets • Packages Available – 32-lead PLCC – 32-lead TSOP (8mm x 14mm) • All devices are RoHS compliant ©2012 Silicon Storage Technology, Inc. www.microchip.com DS25023B 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Product Description The SST39LF010, SST39LF020, SST39LF040 and SST39VF010, SST39VF020, SST39VF040 are 128K x8, 256K x8 and 5124K x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF010/020/040 devices write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF010/020/040 devices write with a 2.7-3.6V power supply. The devices conform to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39LF010/020/040 and SST39VF010/020/040 devices provide a maximum Byte-Program time of 20 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, they are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39LF010/020/040 and SST39VF010/020/040 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improves performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet surface mount requirements, the SST39LF010/020/040 and SST39VF010/020/040 devices are offered in 32-lead PLCC and 32-lead TSOP packages. See Figures 2 and 3 for pin assignments. ©2012 Silicon Storage Technology, Inc. DS25023B 2 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Block Diagram X-Decoder Memory Address SuperFlash Memory Address Buffers & Latches Y-Decoder CE# OE# Control Logic I/O Buffers and Data Latches WE# DQ7 - DQ0 1150 B1.1 Figure 1: Functional Block Diagram ©2012 Silicon Storage Technology, Inc. DS25023B 3 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet A17 A17 NC WE# WE# WE# VDD VDD VDD A18 NC 4 3 2 1 32 31 30 29 NC A16 A16 A16 A15 A15 A15 A12 SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 A12 A12 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040 Pin Assignments SST39LF/VF010 SST39LF/VF020 SST39LF/VF040 A7 A7 A7 5 A14 A14 A14 A6 A6 A6 6 28 A13 A13 A13 A5 A5 A5 7 27 A8 A8 A8 A4 A4 A4 8 26 A9 A9 A9 A3 A3 A3 9 25 A11 A11 A11 A2 A2 A2 10 24 OE# OE# OE# A1 A1 A1 11 23 A10 A10 A10 A0 A0 A0 12 22 CE# CE# CE# DQ0 DQ0 DQ0 13 21 14 15 16 17 18 19 20 DQ7 DQ7 DQ7 32-lead PLCC Top View DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 1150 32-plcc NH P4.4 Figure 2: Pin Assignments for 32-lead PLCC ©2012 Silicon Storage Technology, Inc. DS25023B 4 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 A17 WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View Die Up OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 1150 32-tsop WH P1.1 Figure 3: Pin Assignments for 32-lead TSOP (8mm x 14mm) Table 1: Pin Description Symbol AMS1-A0 DQ7-DQ0 CE# OE# WE# VDD VSS NC Pin Name Address Inputs Functions To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. During Block-Erase AMS-A16 address lines will select the block. Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. Chip Enable To activate the device when CE# is low. Output Enable To gate the data output buffers. Write Enable To control the Write operations. Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF010/020/040 2.7-3.6V for SST39VF010/020/040 Ground No Connection Unconnected pins. T1.1 25023 1. AMS = Most significant address AMS = A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040 ©2012 Silicon Storage Technology, Inc. DS25023B 5 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the SST39LF010/020/040 and SST39VF010/020/040 devices are controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4). Byte-Program Operation The SST39LF010/020/040 and SST39VF010/020/040 are programmed on a byte-by-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 15 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any commands written during the Sector-Erase operation will be ignored. Chip-Erase Operation The SST39LF010/020/040 and SST39VF010/020/040 devices provide a Chip-Erase operation, which allows the user to erase the entire memory array to the ‘1’s state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the ©2012 Silicon Storage Technology, Inc. DS25023B 6 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 18 for the flowchart. Any commands written during the Chip-Erase operation will be ignored. Write Operation Status Detection The SST39LF010/020/040 and SST39VF010/020/040 devices provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-ofWrite detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. ©2012 Silicon Storage Technology, Inc. DS25023B 7 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Data# Polling (DQ7) When the SST39LF010/020/040 and SST39VF010/020/040 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a “0”. Once the internal Erase operation is completed, DQ7 will produce a “1”. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating ‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 16 for a flowchart. Data Protection The SST39LF010/020/040 and SST39VF010/020/040 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. ©2012 Silicon Storage Technology, Inc. DS25023B 8 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Software Data Protection (SDP) The SST39LF010/020/040 and SST39VF010/020/040 provide the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC. Product Identification The Product Identification mode identifies the devices as the SST39LF/VF010, SST39LF/VF020, and SST39LF/VF040 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 11 for the Software ID Entry and Read timing diagram, and Figure 17 for the Software ID entry command sequence flowchart. Table 2: Product Identification Address Data 0000H BFH SST39LF/VF010 0001H D5H SST39LF/VF020 0001H D6H SST39LF/VF040 0001H D7H Manufacturer’s ID Device ID T2.1 25023 Product Identification Mode Exit/Reset In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 12 for timing waveform, and Figure 17 for a flowchart. ©2012 Silicon Storage Technology, Inc. DS25023B 9 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Operations Table 3: Operation Modes Selection Mode CE# OE# WE# DQ Address Read VIL VIL VIH DOUT AIN Program VIL VIH VIL DIN AIN VIL X1 Sector address, XXH for Chip-Erase Erase VIL Standby VIH X X High Z X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit VIH Product Identification Software Mode See Table 4 T3.4 25023 1. X can be VIL or VIH, but no other value. Table 4: Software Command Sequence Command Sequence 1st Bus Write Cycle 2nd Bus Write Cycle Addr1 Addr1 Data 3rd Bus Write Cycle Data Addr1 4th Bus Write Cycle Data Addr1 BA2 Data 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data Addr1 Data Byte-Program 5555H AAH 2AAAH 55H 5555H A0H Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX3 30H Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Software ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H 55H 5555H F0H Software ID Exit6 Software ID Exit6 XXH Data F0H 5555H AAH 2AAAH T4.2 25023 1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence. AMS = Most significant address AMS = A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040 2. BA = Program Byte address 3. SAX for Sector-Erase; uses AMS-A12 address lines 4. The device does not remain in Software Product ID mode if powered down. 5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0, SST39LF/VF010 Device ID = D5H, is read with A0 = 1, SST39LF/VF020 Device ID = D6H, is read with A0 = 1, SST39LF/VF040 Device ID = D7H, is read with A0 = 1. 6. Both Software ID Exit operations are equivalent ©2012 Silicon Storage Technology, Inc. DS25023B 10 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (