SST39VF1682-70-4I-B3KE

16 Mbit (x8) Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 A Microchip Technology Company Data Sheet The SST39VF1681 / SST39VF1682 are 2M x8 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary, high performance CMOS SuperFlash® technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF1681 / SST39VF1682 write (Program or Erase) with a 2.7-3.6V power supply. These devices conforms to JEDEC standard pinouts for x8 memories. Features • Organized as 2M x8 • Security-ID Feature – SST: 128 bits; User: 128 bits • Single Voltage Read and Write Operations • Fast Read Access Time: – 2.7-3.6V – 70 ns • Superior Reliability • Latched Address and Data – Endurance: 100,000 Cycles (Typical) – Greater than 100 years Data Retention • Low Power Consumption (typical values at 5 MHz) – Active Current: 9 mA (typical) – Standby Current: 3 µA (typical) – Auto Low Power Mode: 3 µA (typical) • Hardware Block-Protection/WP# Input Pin – Top Block-Protection (top 64 KByte) for SST39VF1682 – Bottom Block-Protection (bottom 64 KByte) for SST39VF1681 • Sector-Erase Capability – Uniform 4 KByte sectors • Block-Erase Capability – Uniform 64 KByte blocks • Chip-Erase Capability • Erase-Suspend/Erase-Resume Capabilities • Hardware Reset Pin (RST#) ©2011 Silicon Storage Technology, Inc. • Fast Erase and Byte-Program: – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 40 ms (typical) – Byte-Program Time: 7 µs (typical) • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bits – Data# Polling • CMOS I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts and Command sets • Packages Available – 48-ball TFBGA (6mm x 8mm) – 48-lead TSOP (12mm x 20mm) • All devices are RoHS compliant www.microchip.com DS25040A 05/11 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 A Microchip Technology Company Data Sheet Product Description The SST39VF168x devices are 2M x8 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST’s proprietary, high performance CMOS SuperFlash® technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF168x write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39VF168x devices provide a typical Byte-Program time of 7 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39VF168x devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39VF168x are offered in both 48-ball TFBGA and 48-lead TSOP packages. See Figures 2 and 3 for pin assignments. ©2011 Silicon Storage Technology, Inc. DS25040A 2 05/11 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 A Microchip Technology Company Data Sheet Block Diagram SuperFlash Memory X-Decoder Memory Address Address Buffer Latches Y-Decoder CE# OE# WE# WP# RESET# I/O Buffers and Data Latches Control Logic DQ7 - DQ0 1243 B1.0 Figure 1: SST39VF1681 / SST39VF1682 Block Diagram Pin Description 6 5 4 3 2 A14 A13 A15 A16 A17 NC A0 VSS A10 A9 A11 A12 DQ7 NC NC DQ6 WE# RST# NC A20 DQ5 NC VDD DQ4 NC WP# A19 NC DQ2 NC NC DQ3 A8 A18 A7 A6 NC DQ1 A4 A5 A3 A2 A1 CE# OE# VSS A B C D E DQ0 NC 1 F G 1243 48-tfbga B3K P1.0 TOP VIEW (balls facing down) H Figure 2: Pin Assignments for 48-lead TFBGA ©2011 Silicon Storage Technology, Inc. DS25040A 3 05/11 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 A Microchip Technology Company Data Sheet A16 A15 A14 A13 A12 A11 A10 A9 A20 NC WE# RST# NC WP# NC A19 A18 A8 A7 A6 A5 A4 A3 A2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Standard Pinout Top View Die Up A17 NC VSS A0 DQ7 NC DQ6 NC DQ5 NC DQ4 VDD NC DQ3 NC DQ2 NC DQ1 NC DQ0 OE# VSS CE# A1 1243 48-tsop P2.0 Figure 3: Pin Assignments for 48-lead TSOP Table 1: Pin Description Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. During Block-Erase AMS-A16 address lines will select the block. DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded. RST# Reset To reset and return the device to Read mode. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. VDD Power Supply To provide power supply voltage: 2.7-3.6V VSS Ground NC No Connection Unconnected pins. T1.1 25040 1. AMS = Most significant address AMS = A20 for SST39VF1681/1682 ©2011 Silicon Storage Technology, Inc. DS25040A 4 05/11 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 A Microchip Technology Company Data Sheet Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST39VF168x also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 9 mA to typically 3 µA. The Auto Low Power mode reduces the typical IDD active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high. Read The Read operation of the SST39VF168x is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4). Byte-Program Operation The SST39VF168x are programmed on a byte-by-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 10 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 20 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. During the command sequence, WP# should be statically held high or low. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. The SST39VF168x offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 4 KByte. The Block-Erase mode is based on uniform block size of 64 KByte. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The BlockErase operation is initiated by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 10 and 11 for ©2011 Silicon Storage Technology, Inc. DS25040A 5 05/11 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 A Microchip Technology Company Data Sheet timing waveforms and Figure 24 for the flowchart. Any commands issued during the Sector- or BlockErase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP# should be statically held high or low. Erase-Suspend/Erase-Resume Commands The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing one byte command sequence with EraseSuspend command (B0H). The device automatically enters read mode typically within 20 µs after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/ blocks will output DQ2 toggling and DQ6 at “1”. While in Erase-Suspend mode, a Byte-Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase Resume command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at any address in the last Byte sequence. Chip-Erase Operation The SST39VF168x provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase command (10H) at address AAAH in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 6 for the command sequence, Figure 10 for timing diagram, and Figure 24 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to ChipErase will be ignored. During the command sequence, WP# should be statically held high or low. Write Operation Status Detection The SST39VF168x provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling (DQ7) When the SST39VF168x are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will pro- ©2011 Silicon Storage Technology, Inc. DS25040A 6 05/11 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 A Microchip Technology Company Data Sheet duce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 21 for a flowchart. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to “1” if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 2 shows detailed status bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of Write operation. See Figure 8 for Toggle Bit timing diagram and Figure 21 for a flowchart. Table 2: Write Operation Status Status Normal Operation Erase-Suspend Mode DQ7 DQ6 DQ2 DQ7# Toggle No Toggle Standard Erase 0 Toggle Toggle Read from Erase Suspended Sector/Block 1 1 Toggle Standard Program Read from Non- Erase Suspended Sector/Block Data Data Data Program DQ7# Toggle N/A T2.0 25040 Note: DQ7 and DQ2 require a valid address when reading status information. Data Protection The SST39VF168x provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. ©2011 Silicon Storage Technology, Inc. DS25040A 7 05/11 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 A Microchip Technology Company Data Sheet Hardware Block Protection The SST39VF1682 supports top hardware block protection, which protects the top 64 KByte block of the device. The SST39VF1681 supports bottom hardware block protection, which protects the bottom 64 KByte block of the device. The Boot Block address ranges are described in Table 3. Program and Erase operations are prevented on the 64 KByte when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block. Table 3: Boot Block Address Ranges Product Address Range Bottom Boot Block SST39VF1681 000000H-00FFFFH Top Boot Block SST39VF1682 1F0000H-1FFFFFH T3.1 25040 Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 16). The Erase or Program operation that has been interrupted needs to be re-initiated after the device resumes normal operation mode to ensure data integrity. Software Data Protection (SDP) The SST39VF168x provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the threebyte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. Common Flash Memory Interface (CFI) The SST39VF168x also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as product ID entry command with 98H (CFI Query command) to address AAAH in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 7 through 9. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. ©2011 Silicon Storage Technology, Inc. DS25040A 8 05/11 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 A Microchip Technology Company Data Sheet Product Identification The Product Identification mode identifies the devices as the SST39VF1681 and SST39VF1682, and manufacturer as SST. Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 6 for software operation, Figure 12 for the software ID Entry and Read timing diagram, and Figure 22 for the software ID Entry command sequence flowchart. Table 4: Product Identification Address Data 0000H BFH SST39VF1681 0001H C8H SST39VF1682 0001H C9H Manufacturer’s ID Device ID T4.1 25040 Product Identification Mode Exit/CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table 6 for software command codes, Figure 14 for timing waveform, and Figures 22 and 23 for flowcharts. Security ID The SST39VF168x devices offer a 256-bit Security ID space which is divided into two 128-bit segments. The first segment is programmed and locked at SST with a random 128-bit number. The user segment is left un-programmed for the customer to program as desired. To program the user segment of the Security ID, the user must use the Security ID Byte-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. The Security ID space can be queried by executing a three-byte command sequence with Enter-SecID command (88H) at address AAAH in the last byte sequence. Execute the Exit-Sec-ID command to exit this mode. Refer to Table 6 for more details. ©2011 Silicon Storage Technology, Inc. DS25040A 9 05/11 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 A Microchip Technology Company Data Sheet Operations Table 5: Operation Modes Selection Mode CE# OE# WE# DQ Address Read VIL VIL VIH DOUT AIN Program VIL VIH VIL DIN AIN VIL X1 Sector or block address, XXH for Chip-Erase Erase VIL Standby VIH X X High Z X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit VIH Product Identification Software Mode See Table 6 T5.0 25040 1. X can be VIL or VIH, but no other value. Table 6: Software Command Sequence Command Sequence 1st Bus Write Cycle 2nd Bus Write Cycle 3rd Bus Write Cycle Addr1 Addr1 Addr1 Data Data 4th Bus Write Cycle Data Addr1 Data Data AAH Byte-Program AAAH AAH 555H 55H AAAH A0H BA2 Sector-Erase AAAH AAH 555H 55H AAAH 80H AAAH 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data Addr1 Data 555H 55H SAX3 50H 3 Block-Erase AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H BAX 30H Chip-Erase AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H Erase-Suspend XXXXH B0H Erase-Resume XXXXH 30H ID4 AAAH AAH 555H 55H AAAH 88H User Security ID Byte-Program AAAH AAH 555H 55H AAAH A5H BA5 Data User Security ID Program Lock-Out AAAH AAH 555H 55H AAAH 85H XXH5 00H Software ID Entry6,7 AAAH AAH 555H 55H AAAH 90H CFI Query Entry Query Sec AAAH AAH 555H 55H AAAH 98H Software ID Exit8,9 AAAH /CFI Exit/Sec ID Exit AAH 555H 55H AAAH F0H Software ID Exit8,9 /CFI Exit/Sec ID Exit F0H XXH T6.1 25040 1. Address format A11-A0 (Hex). Addresses A20-A12 can be VIL or VIH, but no other value, for Command sequence for SST39VF1681/1682. 2. BA = Program Byte Address 3. SAX for Sector-Erase; uses AMS-A12 address lines BAX, for Block-Erase; uses AMS-A16 address lines AMS = Most significant address AMS = A20 for SST39VF1681/1682 ©2011 Silicon Storage Technology, Inc. DS25040A 10 05/11 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 A Microchip Technology Company Data Sheet 4. With AMS-A5 = 0; Sec ID is read with A4-A0, SST ID is read with A4 = 0 (Address range = 00000H to 0000FH), User ID is read with A4 = 1 (Address range = 00010H to 0001FH). Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. 5. Valid Byte Addresses for Sec ID are from 000000H-00000FH and 000020H-00002FH. 6. The device does not remain in Software Product ID Mode if powered down. 7. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0, SST39VF1681 Device ID = C8H, is read with A0 = 1, SST39VF1682 Device ID = C9H, is read with A0 = 1, AMS = Most significant address AMS = A20 for SST39VF1681/1682 8. Both Software ID Exit operations are equivalent 9. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID mode again (the programmed “0” bits cannot be reversed to “1”). Table 7: CFI Query Identification String1 Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Data 51H 52H 59H 01H 07H 00H 00H 00H 00H 00H 00H Data Query Unique ASCII string “QRY” Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) T7.1 25040 1. Refer to CFI publication 100 for more details. Table 8: System Interface Information Address Data Data 1BH 27H VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1CH 36H VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1DH 00H VPP min. (00H = no VPP pin) 1EH 00H VPP max. (00H = no VPP pin) 1FH 03H Typical time out for Byte-Program 2N µs (23 = 8 µs) 20H 00H Typical time out for min. size buffer program 2N µs (00H = not supported) 21H 04H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) 22H 05H Typical time out for Chip-Erase 2N ms (25 = 32 ms) 23H 01H Maximum time out for Byte-Program 2N times typical (21 x 23 = 16 µs) 24H 00H Maximum time out for buffer program 2N times typical 25H 01H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) 26H 01H Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms) T8.1 25040 ©2011 Silicon Storage Technology, Inc. DS25040A 11 05/11 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 A Microchip Technology Company Data Sheet Table 9: Device Geometry Information Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 15H 00H 00H 00H 00H 02H FFH 01H 10H 00H 1FH 00H 00H 01H Data Device size = 2N Bytes (15H = 21; 221 = 2 MByte) Flash Device Interface description; 00H = x8-only asynchronous interface Maximum number of byte in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 511 + 1 = 512 sectors (01FF = 511 z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16) Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 31 + 1 = 32 blocks (1F = 31) z = 256 x 256 Bytes = 64 KByte/block (0100H = 256) T9.1 25040 ©2011 Silicon Storage Technology, Inc. DS25040A 12 05/11 16 Mbit Multi-Purpose Flash Plus SST39VF1681 / SST39VF1682 A Microchip Technology Company Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (