8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
The SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C are 512K
x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary,
high performance CMOS SuperFlash® technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF801C / SST39VF802C /
SST39LF801C / SST39LF802C write (Program or Erase) with a 2.7-3.6V power
supply. These devices conforms to JEDEC standard pinouts for x16 memories.
Features
• Organized as 512K x16
• Security-ID Feature
– SST: 128 bits; User: 128 words
• Single Voltage Read and Write Operations
• Fast Read Access Time:
– 2.7-3.6V for SST39VF801C/802C
– 3.0-3.6V for SST39LF801C/802C
– 70 ns for SST39VF801C/802C
– 55 ns for SST39LF801C/802C
• Superior Reliability
• Fast Erase and Word-Program:
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• Automatic Write Timing
– Internal VPP Generation
• Hardware Block-Protection/WP# Input Pin
• End-of-Write Detection
– Top Block-Protection (top 8 KWord)
– Bottom Block-Protection (bottom 8 KWord)
– Toggle Bits
– Data# Polling
– Ready/Busy# Pin
• Sector-Erase Capability
– Uniform 2 KWord sectors
• CMOS I/O Compatibility
• Block-Erase Capability
– Flexible block architecture; one 8-, two 4-, one 16-, and
fifteen 32-KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Latched Address and Data
©2011 Silicon Storage Technology, Inc.
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm)
• All devices are RoHS compliant
www.microchip.com
DS25041A
05/11
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
Product Description
The SST39VF801C/802C and SST39LF801C/802C devices are 512K x16 CMOS Multi-Purpose Flash
Plus (MPF+) manufactured with SST proprietary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability
compared with alternate approaches. The SST39VF801C/802C and SST39LF801C/802C write (Program
or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16
memories.
Featuring high performance Word-Program, the SST39VF801C/802C and SST39LF801C/802C
devices provide a typical Word-Program time of 7 µsec. These devices use Toggle Bit, Data# Polling,
or the RY/BY# pin to indicate the completion of Program operation. To protect against inadvertent
write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical
endurance of 100,000 cycles. Data retention is rated at greater than 100 years.
The SST39VF801C/802C and SST39LF801C/802C devices are suited for applications that require
convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They
inherently use less energy during Erase and Program than alternative flash technologies. The total
energy consumed is a function of the applied voltage, current, and time of application. Since for any
given voltage range, the SuperFlash technology uses less current to program and has a shorter erase
time, the total energy consumed during any Erase or Program operation is less than alternative flash
technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the SST39VF801C/802C and SST39LF801C/802C
are offered in 48-lead TSOP, 48-ball TFBGA, and 48-ball WFBGA packages. See Figures 2, 3, and 4
for pin assignments.
©2011 Silicon Storage Technology, Inc.
DS25041A
2
05/11
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
Block Diagrams
X-Decoder
Memory Address
SuperFlash
Memory
Address Buffer Latches
Y-Decoder
CE#
OE#
WE#
WP#
RESET#
RY/BY#
I/O Buffers and Data Latches
Control Logic
DQ15 - DQ0
1434 B1.0
Figure 1: Functional Block Diagram
©2011 Silicon Storage Technology, Inc.
DS25041A
3
05/11
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
Pin Assignment
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RST#
NC
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Standard Pinout
Top View
Die Up
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
1434 48-tsop EK P1.0
Figure 2: Pin Assignments for 48-Lead TSOP
TOP VIEW (balls facing down)
6
5
4
3
2
1
A13 A12 A14
A15 A16 NC DQ15 VSS
A9
A8
A10
A11 DQ7 DQ14 DQ13 DQ6
WE# RST#
NC
NC DQ5 DQ12 VDD DQ4
RY/BY# WP# A18
NC DQ2 DQ10 DQ11 DQ3
A7
A17
A6
A5
DQ0 DQ8 DQ9 DQ1
A3
A4
A2
A1
A0 CE# OE# VSS
A
B
C
D
E
F
G
H
1434 48-tfbga B3K P2.0
Figure 3: Pin Assignments for 48-Ball TFBGA
©2011 Silicon Storage Technology, Inc.
DS25041A
4
05/11
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
TOP VIEW (balls facing down)
6
5
4
3
2
1
A2
A4
A6
A17
A1
A3
A7
WP#
A0
A5
A18
NC
NC
WE# RST# A9
A11
RY/BY# A10
A13
A14
A8
A12
A15
CE# DQ8 DQ10
VSS OE# DQ9
DQ4 DQ11 A16
NC
NC
DQ5 DQ6 DQ7
DQ0 DQ1 DQ2 DQ3 VDD DQ12 DQ13 DQ14 DQ15 VSS
A B C D E F G H J K L
1434 48-wfbga MAQ P3.0
Figure 4: Pin Assignments for 48-Ball WFBGA
Table 1: Pin Description
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses.
During Sector-Erase AMS-A11 address lines will select the sector.
During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0
Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP#
Write Protect
To protect the top/bottom boot block from Erase/Program operation when
grounded.
RST#
Reset
To reset and return the device to Read mode.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
VDD
Power Supply
To provide power supply voltage: 2.7-3.6V
VSS
Ground
NC
No Connection
Unconnected pins.
RY/BY#
Ready/Busy#
To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
T1.2 25041
1. AMS = Most significant address
AMS = A18
©2011 Silicon Storage Technology, Inc.
DS25041A
5
05/11
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
Table 2: Top / Bottom Boot Block Address
Bottom Boot Block Address
SST39VF801C/SST39LF801C
Top Boot Block Address
SST39VF802C/SST39LF802C
#
Size
(KWord)
Address Range
#
Size
(KWord)
Address Range
18
8
7E000H-7FFFFH
18
32
78000H-7FFFFH
17
4
7D000H-7DFFFH
17
32
70000H-77FFFH
16
4
7C000H-7CFFFH
16
32
68000H-6FFFFH
15
16
78000H-7BFFFH
15
32
60000H-67FFFH
14
32
70000H-77FFFH
14
32
58000H-5FFFFH
13
32
68000H-6FFFFH
13
32
50000H-57FFFH
12
32
60000H-67FFFH
12
32
48000H-4FFFFH
11
32
58000H-5FFFFH
11
32
40000H-47FFFH
10
32
50000H-57FFFH
10
32
38000H-3FFFFH
9
32
48000H-4FFFFH
9
32
30000H-37FFFH
8
32
40000H-47FFFH
8
32
28000H-2FFFFH
7
32
38000H-3FFFFH
7
32
20000H-27FFFH
6
32
30000H-37FFFH
6
32
18000H-1FFFFH
5
32
28000H-2FFFFH
5
32
10000H-17FFFH
4
32
20000H-27FFFH
4
32
08000H-0FFFFH
3
32
18000H-1FFFFH
3
16
04000H-07FFFH
2
32
10000H-17FFFH
2
4
03000H-03FFFH
1
32
08000H-0FFFFH
1
4
02000H-02FFFH
0
32
00000H-07FFFH
0
8
00000H-01FFFH
T2.25041
©2011 Silicon Storage Technology, Inc.
DS25041A
6
05/11
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
The SST39VF801C/802C and SST39LF801C/802C also have the Auto Low Power mode which puts
the device in a near standby mode after data has been accessed with a valid Read operation. This
reduces the IDD active read current from typically 5 mA to typically 3 µA. The Auto Low Power mode
reduces the typical IDD active read current to the range of 2 mA/MHz of Read cycle time. The device
exits the Auto Low Power mode with any address transition or control signal transition used to initiate
another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power
mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF801C/802C and SST39LF801C/802C is controlled by CE# and OE#,
both have to be low for the system to obtain data from the outputs. CE# is used for device selection.
When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either
CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6).
Word-Program Operation
The SST39VF801C/802C and SST39LF801C/802C are programmed on a word-by-word basis. Before
programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The
second step is to load word address and word data. During the Word-Program operation, the
addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs
first. The Program operation, once initiated, will be completed within 10 µs. See Figures 7 and 8 for
WE# and CE# controlled Program operation timing diagrams and Figure 22 for flowcharts. During the
Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. During the command sequence, WP# should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The SST39VF801C/802C and SST39LF801C/802C offer both Sector-Erase and
Block-Erase mode.
The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based
on non-uniform block sizes—fifteen 32 KWord, one 16 KWord, two 4 KWord, and one 8 KWord blocks.
See Figure 2 for top and bottom boot device block addresses. The Sector-Erase operation is initiated
by executing a six-byte command sequence with Sector-Erase command (50H) and sector address
(SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command
sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector
or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or
50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the
©2011 Silicon Storage Technology, Inc.
DS25041A
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05/11
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle
Bit methods. See Figures 12 and 13 for timing waveforms and Figure 26 for the flowchart. Any commands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt
to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP#
should be statically held high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing
data to be read from any memory location, or program data into any sector/block that is not suspended
for an Erase operation. The operation is executed by issuing one byte command sequence with EraseSuspend command (B0H). The device automatically enters read mode typically within 20 µs after the
Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address location within erase-suspended sectors/
blocks will output DQ2 toggling and DQ6 at ‘1’. While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue
Erase Resume command. The operation is executed by issuing one byte command sequence with
Erase Resume command (30H) at any address in the last Byte sequence.
Chip-Erase Operation
The SST39VF801C/802C and SST39LF801C/802C provide a Chip-Erase operation, which allows the
user to erase the entire memory array to the ‘1’ state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase
command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising
edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is
Toggle Bit or Data# Polling. See Table 7 for the command sequence, Figure 11 for timing diagram, and
Figure 26 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When
WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should
be statically held high or low.
Write Operation Status Detection
The SST39VF801C/802C and SST39LF801C/802C provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software
detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
©2011 Silicon Storage Technology, Inc.
DS25041A
8
05/11
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
Ready/Busy# (RY/BY#)
The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that
indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain output, it allows several devices to be tied in parallel to VDD via an external pull-up resistor. After the rising
edge of the final WE# pulse in the command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress.
When RY/BY# is high (Ready), the devices may be read or left in standby mode.
Data# Polling (DQ7)
When the SST39VF801C/802C and SST39LF801C/802C are in the internal Program operation, any
attempt to read DQ7 will produce the complement of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on
the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal
Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#)
pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for Data# Polling timing diagram and Figure 23 for
a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce
alternating ‘1’s and ‘0’s, i.e., toggling between 1 and 0. When the internal Program or Erase operation
is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ6 will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle.
An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check
whether a particular sector is being actively erased or erase-suspended. Table 3 shows detailed status
bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of
Write operation. See Figure 10 for Toggle Bit timing diagram and Figure 23 for a flowchart.
Table 3: Write Operation Status
Status
Normal Operation
Erase-Suspend
Mode
DQ7
DQ6
DQ2
RY/BY#
DQ7#
Toggle
No Toggle
0
Standard Erase
0
Toggle
Toggle
0
Read from Erase-Suspended Sector/Block
1
1
Toggle
1
Read from Non-EraseSuspended Sector/Block
Data
Data
Data
1
Program
DQ7#
Toggle
N/A
0
Standard Program
T3.0 25041
Note: DQ7 and DQ2 require a valid address when reading status information.
©2011 Silicon Storage Technology, Inc.
DS25041A
9
05/11
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
Data Protection
The SST39VF801C/802C and SST39LF801C/802C provide both hardware and software features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Hardware Block Protection
The SST39VF802C/SST39LF802C support top hardware block protection, which protects the top 8
KWord block of the device. The SST39VF801C/SST39LF801C support bottom hardware block protection, which protects the bottom 8KWord block of the device. The Boot Block address ranges are
described in Table 4. Program and Erase operations are prevented on the 8 KWord when WP# is low.
If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected,
enabling Program and Erase operations on that block.
Table 4: Boot Block Address Ranges
Product
Address Range
Bottom Boot Block
SST39VF801C/SST39LF801C
00000H - 01FFFH
Top Boot Block
SST39VF802C/SST39LF802C
7E000H - 7FFFFH
T4.0 25041
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the device to read array data. When the RST#
pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When
no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST#
is driven high before a valid Read can take place (see Figure 18).
The Erase or Program operation that has been interrupted needs to be re-initiated after the device
resumes normal operation mode to ensure data integrity.
Software Data Protection (SDP)
The SST39VF801C/802C and SST39LF801C/802C provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the
Program operation, providing optimal protection from inadvertent Write operations, e.g., during the
system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence.
These devices are shipped with the Software Data Protection permanently enabled. See Table 7 for
©2011 Silicon Storage Technology, Inc.
DS25041A
10
05/11
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
the specific software command codes. During SDP command sequence, invalid commands will abort
the device to read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value,
during any SDP command sequence.
Common Flash Memory Interface (CFI)
The SST39VF801C/802C and SST39LF801C/802C also contain the CFI information to describe the
characteristics of the device. In order to enter the CFI Query mode, the system writes a three-byte
sequence, same as product ID entry command with 98H (CFI Query command) to address 555H in
the last byte sequence. Additionally, the system can use the one-byte sequence with 55H on the
Address and 89H on the Data Bus to enter the CFI Query mode. Once the device enters the CFI
Query mode, the system can read CFI data at the addresses given in Tables 8 through 10. The system
must write the CFI Exit command to return to Read mode from the CFI Query mode.
Product Identification
The Product Identification mode identifies the devices as the SST39VF801C / SST39VF802C /
SST39LF801C / SST39LF802C, and manufacturer as SST. This mode may be accessed software
operations. Users may use the Software Product Identification operation to identify the part (i.e., using
the device ID) when using multiple manufacturers in the same socket. For details, see Table 7 for software operation, Figure 14 for the Software ID Entry and Read timing diagram and Figure 24 for the
Software ID Entry command sequence flowchart.
Table 5: Product Identification
Address
Data
0000H
BFH
SST39VF801C/SST39LF801C
0001H
233BH
SST39VF802C/SST39LF802C
0001H
233AH
Manufacturer’s ID
Device ID
T5.2 25041
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited.
Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to
the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program
or Erase operation. See Table 7 for software command codes, Figure 16 for timing waveform, and Figure 25 for flowcharts.
©2011 Silicon Storage Technology, Inc.
DS25041A
11
05/11
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
Security ID
The SST39VF801C/802C and SST39LF801C/802C devices offer a 136 Word Security ID space. The
Secure ID space is divided into two segments—one factory programmed segment and one user programmed segment. The first segment is programmed and locked at SST with a random 128-bit number. The user segment, with a 128 word space, is left un-programmed for the customer to program as
desired.
To program the user segment of the Security ID, the user must use the Security ID Word-Program
command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once
this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables
any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.
The Secure ID space can be queried by executing a three-byte command sequence with Enter Sec ID
command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 7 for more details.
©2011 Silicon Storage Technology, Inc.
DS25041A
12
05/11
8 Mbit (x16) Multi-Purpose Flash Plus
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
A Microchip Technology Company
Data Sheet
Operations
Table 6: Operation Modes Selection
Mode
CE#
OE#
WE#
Read
Program
VIL
VIL
VIL
VIH
Address
VIH
DOUT
AIN
VIL
DIN
AIN
VIL
X1
Sector or block address, XXH for ChipErase
Erase
VIL
Standby
VIH
X
X
High Z
X
X
VIL
X
High Z/ DOUT
X
X
X
VIH
High Z/ DOUT
X
VIL
VIL
VIH
Write Inhibit
VIH
DQ
Product Identification
Software Mode
See Table 7
T6.0 25041
1. X can be VIL or VIH, but no other value.
Table 7: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
Addr1
Addr1
Data2 Addr1 Data2 Addr1
Data2
Data
AAH
Data2
3rd Bus
Write Cycle
4th Bus
Write Cycle
Word-Program
555H
AAH
2AAH
55H
555H
A0H
WA3
Sector-Erase
555H
AAH
2AAH
55H
555H
80H
555H
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1
Data2 Addr1 Data2
2AAH
55H
SAX4
50H
4
Block-Erase
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
BAX
30H
Chip-Erase
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
555H
10H
Erase-Suspend
XXXH
B0H
Erase-Resume
XXXH
30H
ID5
555H
AAH
2AAH
55H
555H
88H
User Security ID
Word-Program
555H
AAH
2AAH
55H
555H
A5H
WA6
Data
User Security ID
Program LockOut
555H
AAH
2AAH
55H
555H
85H
XXH6
0000
H
Software ID
Entry7,8
555H
AAH
2AAH
55H
555H
90H
CFI Query Entry
555H
AAH
2AAH
55H
555H
98H
2AAH
55H
555H
F0H
Query Sec
55H
98H
Software ID Exit9,10
/CFI Exit/Sec ID
Exit
555H
AAH
Software ID Exit9,10
/CFI Exit/Sec ID
Exit
XXH
F0H
CFI Query Entry
T7.6 25041
1.
2.
3.
4.
Address format A10-A0 (Hex). Addresses A11-A18 can be VIL or VIH, but no other value, for Command sequence.
DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence
WA = Program Word address
SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses AMS-A15 address lines
AMS = Most significant address; AMS = A18
©2011 Silicon Storage Technology, Inc.
DS25041A
13
05/11
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
5. With AMS-A4 = 0; Sec ID is read with A3-A0,
SST ID is read with A3 = 0 (Address range = 000000H to 000007H),
User ID is read with A3 = 1 (Address range = 000008H to 000087H).
Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H-000087H.
7. The device does not remain in Software Product ID Mode if powered down.
8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,
SST39VF801C/SST39LF801C Device ID = 233BH, is read with A0 = 1, SST39VF802C/SST39LF802C Device ID =
233AH, is read with A0 = 1,
AMS = Most significant address; AMS = A18
9. Both Software ID Exit operations are equivalent
10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1)
using the Sec ID mode again (the programmed ‘0’ bits cannot be reversed to ‘1’). Valid Word-Addresses for Sec ID are
from 000000H-000007H and 000008H-000087H.
Table 8: CFI Query Identification String1
Address
Data
10H
0051H
11H
0052H
12H
0059H
13H
0002H
14H
0000H
15H
0000H
16H
0000H
17H
0000H
18H
0000H
19H
0000H
1AH
0000H
Data
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T8.1 25041
1. Refer to CFI publication 100 for more details.
Table 9: System Interface Information
Address
Data
1BH
0027H
Data
1CH
0036H
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
0000H
VPP min. (00H = no VPP pin)
VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1EH
0000H
VPP max. (00H = no VPP pin)
1FH
0003H
Typical time out for Word-Program 2N µs (23 = 8 µs)
20H
0000H
Typical time out for min. size buffer program 2N µs (00H = not supported)
21H
0004H
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
22H
0005H
Typical time out for Chip-Erase 2N ms (25 = 32 ms)
23H
0001H
Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs)
24H
0000H
Maximum time out for buffer program 2N times typical
25H
0001H
Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
26H
0001H
Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)
T9.3 25041
©2011 Silicon Storage Technology, Inc.
DS25041A
14
05/11
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
Table 10:Device Geometry Information
Address
Data
27H
0014H
Device size = 2N Bytes (14H = 20; 220 = 1 MByte)
28H
0001H
Flash Device Interface description; 0001H = x16-only asynchronous interface
29H
0000H
2AH
0000H
2BH
0000H
2CH
0005H
Number of Erase Sector/Block sizes supported by device
2DH
0000H
Erase Block Region 1 Information (Refer to the CFI specification or CFI publication
100)
2EH
0000H
2FH
0040H
30H
0000H
31H
0001H
32H
0000H
33H
0020H
34H
0000H
35H
0000H
36H
0000H
37H
0080H
38H
0000H
39H
000FH
3AH
0000H
3BH
0000H
3CH
0001H
Data
Maximum number of byte in multi-byte write = 2N (00H = not supported)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
T10.0 25041
©2011 Silicon Storage Technology, Inc.
DS25041A
15
05/11
8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
Electrical Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (
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