SST39WF400B-70-4I-MAQE

4 Mbit (x16) Multi-Purpose Flash SST39WF400B A Microchip Technology Company Data Sheet The SST39WF400B is a 256K x16 CMOS Multi-Purpose Flash (MPF) manufactured with proprietary, high-performance CMOS SuperFlash technology. The splitgate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared to alternate approaches. The SST39WF400B writes (Program or Erase) with a 1.65-1.95V power supply. This device conforms to JEDEC standard pin assignments for x16 memories. Features • Organized as 256K x16 • Fast Erase and Word-Program – Sector-Erase Time: 36 ms (typical) – Block-Erase Time: 36 ms (typical) – Chip-Erase Time: 140 ms (typical) – Word-Program Time: 28 µs (typical) • Single Voltage Read and Write Operations – 1.65-1.95V • Superior Reliability • Automatic Write Timing – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention – Internal VPP Generation • Low Power Consumption (typical values at 5 MHz) – Active Current: 5 mA (typical) – Standby Current: 5 µA (typical) • Sector-Erase Capability – Uniform 2 KWord sectors • Block-Erase Capability – Uniform 32 KWord blocks • Fast Read Access Time – 70 ns • Latched Address and Data ©2011 Silicon Storage Technology, Inc. • End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts and command sets • Packages Available – 48-ball TFBGA (6mm x 8mm) – 48-ball WFBGA (4mm x 6mm) Micro-Package – 48-ball XFLGA (4mm x 6mm) Micro-Package • All devices are RoHS compliant www.microchip.com DS25034A 09/11 4 Mbit (x16) Multi-Purpose Flash SST39WF400B A Microchip Technology Company Data Sheet Product Description The SST39WF400B is a 256K x16 CMOS Multi-Purpose Flash (MPF) manufactured with SST proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared to alternate approaches. The SST39WF400B writes (Program or Erase) with a 1.65-1.95V power supply. This device conforms to JEDEC standard pin assignments for x16 memories. The SST39WF400B features high-performance Word-Programming which provides a typical WordProgram time of 28 µsec. It uses Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. On-chip hardware and software data protection schemes protect against inadvertent writes. Designed, manufactured, and tested for a wide spectrum of applications, the SST39WF400B is offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39WF400B is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, this MPF significantly improves performance and reliability, while lowering power consumption. It inherently uses less energy during Erase and Program than alternative flash technologies. When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. For any given voltage range, SuperFlash technology uses less current to program and has a shorter erase time; therefore, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. SuperFlash technology provides fixed Erase and Program times independent of the number of Erase/ Program cycles that have occurred. Consequently, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet surface mount requirements, the SST39WF400B is offered in 48-ball TFBGA, 48-ball WFBGA, and a 48-ball XFLGA packages. See Figures 2 and 3 for pin assignments and Table 1 for pin descriptions. ©2011 Silicon Storage Technology, Inc. DS25034A 2 09/11 4 Mbit (x16) Multi-Purpose Flash SST39WF400B A Microchip Technology Company Data Sheet Block Diagram X-Decoder Memory Address SuperFlash Memory Address Buffer Latches Y-Decoder CE# OE# Control Logic I/O Buffers and Data Latches WE# DQ15 - DQ0 1370 B1.0 Figure 1: Functional Block Diagram ©2011 Silicon Storage Technology, Inc. DS25034A 3 09/11 4 Mbit (x16) Multi-Purpose Flash SST39WF400B A Microchip Technology Company Data Sheet Pin Assignments TOP VIEW (balls facing down) SST39WF400B 6 A2 A4 A6 A17 A1 A3 A7 NC A0 A5 NC NC NC WE# NC A9 A11 NC A10 A13 A14 A8 A12 A15 5 4 3 CE# DQ8 DQ10 VSS OE# DQ9 DQ4 DQ11 A16 2 NC NC DQ5 DQ6 DQ7 1 DQ0 DQ1 DQ2 DQ3 A B C D E VDD DQ12 DQ13 DQ14 DQ15 VSS F G H J K L 1370 48-wfbga M2Q P02.0 Figure 2: Pin Assignments for 48-Ball WFBGA and 48-Ball XFLGA TOP VIEW (balls facing down) SST39WF400B 6 A13 A12 A14 A15 A16 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 WE# NC NC NC DQ5 DQ12 VDD DQ4 NC NC NC NC DQ2 DQ10 DQ11 DQ3 A7 A17 A6 A5 5 NC DQ15 VSS 4 3 2 DQ0 DQ8 DQ9 DQ1 1 A3 A4 A2 A1 A0 CE# OE# VSS A B C D E F G H 1370 48-tfbga P01.0 Figure 3: Pin Assignments for 48-ball TFBGA ©2011 Silicon Storage Technology, Inc. DS25034A 4 09/11 4 Mbit (x16) Multi-Purpose Flash SST39WF400B A Microchip Technology Company Data Sheet Table 1: Pin Description Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A11 address lines will select the sector. During Block-Erase AMS-A15 address lines will select the block. DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Program cycles. Data is internally latched during a Program cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Program operations. VDD Power Supply To provide power supply voltage: VSS Ground NC No Connection 1.65-1.95V for SST39WF400B Unconnected pins. T1.0 25034 1. AMS = Most significant address AMS = A17 for SST39WF400B ©2011 Silicon Storage Technology, Inc. DS25034A 5 09/11 4 Mbit (x16) Multi-Purpose Flash SST39WF400B A Microchip Technology Company Data Sheet Device Operation Commands, which are used to initiate the memory operation functions of the device, are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the SST39WF400B is controlled by CE# and OE#; both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. See Figure 5. Word-Program Operation The SST39WF400B is programmed on a word-by-word basis. The sector where the word exists must be fully erased before programming. Programming is accomplished in three steps: 1. Load the three-byte sequence for Software Data Protection. 2. Load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. 3. Initiate the internal Program operation after the rising edge of the fourth WE# or CE#, whichever occurs first. Once initiated, the Program operation will be completed within 40 µs. See Figures 6 and 7 for WE# and CE# controlled Program operation timing diagrams and Figure 18 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. ©2011 Silicon Storage Technology, Inc. DS25034A 6 09/11 4 Mbit (x16) Multi-Purpose Flash SST39WF400B A Microchip Technology Company Data Sheet Sector-/Block-Erase Operation The SST39WF400B offers both Sector-Erase and Block-Erase modes which allow the system to erase the device on a sector-by-sector, or block-by-block, basis. The sector architecture is based on an uniform sector size of 2 KWord. Initiate the Sector-Erase operation by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase mode is based on an uniform block size of 32 KWord. Initiate the Block-Erase operation by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 11 and 12 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored. Chip-Erase Operation The SST39WF400B provides a Chip-Erase operation, which allows the user to erase the entire memory array to the ‘1’ state. This is useful when the entire device must be quickly erased. Initiate the Chip-Erase operation by executing a six-byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for the timing diagram, and Figure 21 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. ©2011 Silicon Storage Technology, Inc. DS25034A 7 09/11 4 Mbit (x16) Multi-Purpose Flash SST39WF400B A Microchip Technology Company Data Sheet Write Operation Status Detection To optimize the system write cycle time, the SST39WF400B provides two software means to detect the completion of a Program or Erase write cycle. The software detection includes two status bits—Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The completion of the nonvolatile Write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may occur simultaneously with the completion of the Write cycle. If this occurs, the system may get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. To prevent spurious rejection in the event of an erroneous result, the software routine must include a loop to read the accessed location an additional two (2) times. If both Reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling (DQ7) When the SST39WF400B is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is complete, DQ7 will produce true data. Although DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid. Valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During an internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is complete, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 19 for a flowchart. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating ‘1’s and ‘0’s, i.e., toggling between ‘1’ and ‘0’. When the Program or Erase operation is complete, the DQ6 bit will stop toggling and the device is ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for Toggle Bit timing diagram and Figure 19 for a flowchart. Data Protection The SST39WF400B provides both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.0V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. ©2011 Silicon Storage Technology, Inc. DS25034A 8 09/11 4 Mbit (x16) Multi-Purpose Flash SST39WF400B A Microchip Technology Company Data Sheet Software Data Protection (SDP) The SST39WF400B provides the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the threebyte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. This group of devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. Common Flash Memory Interface (CFI) The SST39WF400B contains the CFI information that describes the characteristics of the device, and supports both the original SST CFI Query mode implementation for compatibility with existing SST devices, as well as the general CFI Query mode. To enter the SST CFI Query mode, the system must write the three-byte sequence, same as the Product ID Entry command, with 98H (CFI Query command) to address 5555H in the last byte sequence. To enter the general CFI Query mode, the system must write a one-byte sequence using the Entry command with 98H to address 55H. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5 through 7. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. Product Identification The Product Identification mode identifies the device as the SST39WF400B and the manufacturer as SST. This mode is accessed by software operations. Use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 13 for the Software ID Entry and Read timing diagram, and Figure 20 for the Software ID Entry command sequence flowchart. Table 2: Product Identification Table Manufacturer’s ID Address Data 0000H 00BFH 0001H 272EH Device ID SST39WF400B T2.0 25034 ©2011 Silicon Storage Technology, Inc. DS25034A 9 09/11 4 Mbit (x16) Multi-Purpose Flash SST39WF400B A Microchip Technology Company Data Sheet Product Identification Mode Exit/CFI Mode Exit To return to the standard Read mode, exit the Software Product Identification mode by issuing the Software ID Exit command sequence. The Software ID Exit command can reset the SST39WF400B to the Read mode after an inadvertent transient condition that causes the device to behave abnormally. The Software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 15 for timing waveform, and Figure 20 for a flowchart. ©2011 Silicon Storage Technology, Inc. DS25034A 10 09/11 4 Mbit (x16) Multi-Purpose Flash SST39WF400B A Microchip Technology Company Data Sheet Operations Table 3: Operation Modes Selection Mode CE# OE# WE# DQ Address Read VIL VIL VIH DOUT AIN Program VIL VIH VIL DIN AIN VIH VIL X1 Sector or Block address, XXH for Chip-Erase Erase VIL Standby VIH X X High Z X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit Product Identification Software Mode See Table 4 T3.0 25034 1. X can be VIL or VIH, but no other value. Table 4: Software Command Sequence Command Sequence 1st Bus Write Cycle 2nd Bus Write Cycle 3rd Bus Write Cycle 4th Bus Write Cycle 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Addr1 Addr1 Data2 Addr1 Addr1 Data2 Addr1 Data2 Data AAH 2AAAH 55H SAX4 30H 50H 10H Data2 Data2 Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3 Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H Data2 Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX4 Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H Software ID Entry5,6 5555H AAH 2AAAH 55H 5555H 90H SST CFI Query Entry5 5555H AAH 2AAAH 55H 5555H 98H General CFI Query Mode 55H 98H Software ID Exit7/ CFI Exit XXH F0H Software ID Exit7/ CFI Exit 5555H AAH 2AAAH 55H 5555H F0H T4.0 25034 1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence. AMS = Most significant address AMS = A17 for SST39WF400B 2. DQ15-DQ8 can be VIL or VIH, but no other value, for the Command sequence 3. WA = Program word address 4. SAX for Sector-Erase; uses AMS-A11 address lines BAX for Block-Erase; uses AMS-A15 address lines 5. The device does not remain in Software Product ID mode if powered down. 6. With AMS-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0, SST39WF400B Device ID = 272EH, is read with A0 = 1. 7. Both Software ID Exit operations are equivalent ©2011 Silicon Storage Technology, Inc. DS25034A 11 09/11 4 Mbit (x16) Multi-Purpose Flash SST39WF400B A Microchip Technology Company Data Sheet Table 5: CFI Query Identification String1 for SST39WF400B Address Data 10H 0051H 11H 0052H 12H 0059H 13H 0001H 14H 0007H 15H 0000H 16H 0000H 17H 0000H 18H 0000H 19H 0000H 1AH 0000H Data Query Unique ASCII string “QRY” Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) T5.0 25034 1. Refer to CFI publication 100 for more details. Table 6: System Interface Information for SST39WF400B Address Data 1BH 0016H VDD Min (Program/Erase) Data 1CH 0020H VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1DH 0000H VPP min (00H = no VPP pin) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1EH 0000H VPP max (00H = no VPP pin) 1FH 0005H Typical time out for Word-Program 2N µs (25 = 32 µs) 20H 0000H Typical time out for min size buffer program 2N µs (00H = not supported) 21H 0005H Typical time out for individual Sector/Block-Erase 2N ms (25 = 32 ms) 22H 0007H Typical time out for Chip-Erase 2N ms (27 = 128 ms) 23H 0001H Maximum time out for Word-Program 2N times typical (21 x 25 = 64 µs) 24H 0000H Maximum time out for buffer program 2N times typical 25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 25 = 64 ms) 26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 27 = 256 ms) T6.0 25034 ©2011 Silicon Storage Technology, Inc. DS25034A 12 09/11 4 Mbit (x16) Multi-Purpose Flash SST39WF400B A Microchip Technology Company Data Sheet Table 7: Device Geometry Information for SST39WF400B Address Data 27H 0013H Device size = 2N Byte (0013H = 19; 219 = 512 KByte) Data 28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface 29H 0000H 2AH 0000H 2BH 0000H Maximum number of byte in multi-byte write = 2N (0000H = not supported) 2CH 0002H Number of Erase Sector/Block sizes supported by device 2DH 007FH Sector Information (y + 1 = Number of sectors; z x 256B = sector size) 2EH 0000H y +1 = 127 + 1 = 128 sectors (007FH = 127) 2FH 0010H 30H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16) 31H 0007H Block Information (y + 1 = Number of blocks; z x 256B = block size) y + 1 = 7 + 1 = 8 blocks (0007H = 7) 32H 0000H 33H 0000H 34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256) T7.1 25034 ©2011 Silicon Storage Technology, Inc. DS25034A 13 09/11 4 Mbit (x16) Multi-Purpose Flash SST39WF400B A Microchip Technology Company Data Sheet Electrical Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (